1 // 2 // Copyright 1998-2009 Sun Microsystems, Inc. All Rights Reserved. 3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 // 5 // This code is free software; you can redistribute it and/or modify it 6 // under the terms of the GNU General Public License version 2 only, as 7 // published by the Free Software Foundation. 8 // 9 // This code is distributed in the hope that it will be useful, but WITHOUT 10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 // version 2 for more details (a copy is included in the LICENSE file that 13 // accompanied this code). 14 // 15 // You should have received a copy of the GNU General Public License version 16 // 2 along with this work; if not, write to the Free Software Foundation, 17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 // 19 // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 20 // CA 95054 USA or visit www.sun.com if you need additional information or 21 // have any questions. 22 // 23 // 24 25 // SPARC Architecture Description File 26 27 //----------REGISTER DEFINITION BLOCK------------------------------------------ 28 // This information is used by the matcher and the register allocator to 29 // describe individual registers and classes of registers within the target 30 // archtecture. 31 register %{ 32 //----------Architecture Description Register Definitions---------------------- 33 // General Registers 34 // "reg_def" name ( register save type, C convention save type, 35 // ideal register type, encoding, vm name ); 36 // Register Save Types: 37 // 38 // NS = No-Save: The register allocator assumes that these registers 39 // can be used without saving upon entry to the method, & 40 // that they do not need to be saved at call sites. 41 // 42 // SOC = Save-On-Call: The register allocator assumes that these registers 43 // can be used without saving upon entry to the method, 44 // but that they must be saved at call sites. 45 // 46 // SOE = Save-On-Entry: The register allocator assumes that these registers 47 // must be saved before using them upon entry to the 48 // method, but they do not need to be saved at call 49 // sites. 50 // 51 // AS = Always-Save: The register allocator assumes that these registers 52 // must be saved before using them upon entry to the 53 // method, & that they must be saved at call sites. 54 // 55 // Ideal Register Type is used to determine how to save & restore a 56 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get 57 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI. 58 // 59 // The encoding number is the actual bit-pattern placed into the opcodes. 60 61 62 // ---------------------------- 63 // Integer/Long Registers 64 // ---------------------------- 65 66 // Need to expose the hi/lo aspect of 64-bit registers 67 // This register set is used for both the 64-bit build and 68 // the 32-bit build with 1-register longs. 69 70 // Global Registers 0-7 71 reg_def R_G0H( NS, NS, Op_RegI,128, G0->as_VMReg()->next()); 72 reg_def R_G0 ( NS, NS, Op_RegI, 0, G0->as_VMReg()); 73 reg_def R_G1H(SOC, SOC, Op_RegI,129, G1->as_VMReg()->next()); 74 reg_def R_G1 (SOC, SOC, Op_RegI, 1, G1->as_VMReg()); 75 reg_def R_G2H( NS, NS, Op_RegI,130, G2->as_VMReg()->next()); 76 reg_def R_G2 ( NS, NS, Op_RegI, 2, G2->as_VMReg()); 77 reg_def R_G3H(SOC, SOC, Op_RegI,131, G3->as_VMReg()->next()); 78 reg_def R_G3 (SOC, SOC, Op_RegI, 3, G3->as_VMReg()); 79 reg_def R_G4H(SOC, SOC, Op_RegI,132, G4->as_VMReg()->next()); 80 reg_def R_G4 (SOC, SOC, Op_RegI, 4, G4->as_VMReg()); 81 reg_def R_G5H(SOC, SOC, Op_RegI,133, G5->as_VMReg()->next()); 82 reg_def R_G5 (SOC, SOC, Op_RegI, 5, G5->as_VMReg()); 83 reg_def R_G6H( NS, NS, Op_RegI,134, G6->as_VMReg()->next()); 84 reg_def R_G6 ( NS, NS, Op_RegI, 6, G6->as_VMReg()); 85 reg_def R_G7H( NS, NS, Op_RegI,135, G7->as_VMReg()->next()); 86 reg_def R_G7 ( NS, NS, Op_RegI, 7, G7->as_VMReg()); 87 88 // Output Registers 0-7 89 reg_def R_O0H(SOC, SOC, Op_RegI,136, O0->as_VMReg()->next()); 90 reg_def R_O0 (SOC, SOC, Op_RegI, 8, O0->as_VMReg()); 91 reg_def R_O1H(SOC, SOC, Op_RegI,137, O1->as_VMReg()->next()); 92 reg_def R_O1 (SOC, SOC, Op_RegI, 9, O1->as_VMReg()); 93 reg_def R_O2H(SOC, SOC, Op_RegI,138, O2->as_VMReg()->next()); 94 reg_def R_O2 (SOC, SOC, Op_RegI, 10, O2->as_VMReg()); 95 reg_def R_O3H(SOC, SOC, Op_RegI,139, O3->as_VMReg()->next()); 96 reg_def R_O3 (SOC, SOC, Op_RegI, 11, O3->as_VMReg()); 97 reg_def R_O4H(SOC, SOC, Op_RegI,140, O4->as_VMReg()->next()); 98 reg_def R_O4 (SOC, SOC, Op_RegI, 12, O4->as_VMReg()); 99 reg_def R_O5H(SOC, SOC, Op_RegI,141, O5->as_VMReg()->next()); 100 reg_def R_O5 (SOC, SOC, Op_RegI, 13, O5->as_VMReg()); 101 reg_def R_SPH( NS, NS, Op_RegI,142, SP->as_VMReg()->next()); 102 reg_def R_SP ( NS, NS, Op_RegI, 14, SP->as_VMReg()); 103 reg_def R_O7H(SOC, SOC, Op_RegI,143, O7->as_VMReg()->next()); 104 reg_def R_O7 (SOC, SOC, Op_RegI, 15, O7->as_VMReg()); 105 106 // Local Registers 0-7 107 reg_def R_L0H( NS, NS, Op_RegI,144, L0->as_VMReg()->next()); 108 reg_def R_L0 ( NS, NS, Op_RegI, 16, L0->as_VMReg()); 109 reg_def R_L1H( NS, NS, Op_RegI,145, L1->as_VMReg()->next()); 110 reg_def R_L1 ( NS, NS, Op_RegI, 17, L1->as_VMReg()); 111 reg_def R_L2H( NS, NS, Op_RegI,146, L2->as_VMReg()->next()); 112 reg_def R_L2 ( NS, NS, Op_RegI, 18, L2->as_VMReg()); 113 reg_def R_L3H( NS, NS, Op_RegI,147, L3->as_VMReg()->next()); 114 reg_def R_L3 ( NS, NS, Op_RegI, 19, L3->as_VMReg()); 115 reg_def R_L4H( NS, NS, Op_RegI,148, L4->as_VMReg()->next()); 116 reg_def R_L4 ( NS, NS, Op_RegI, 20, L4->as_VMReg()); 117 reg_def R_L5H( NS, NS, Op_RegI,149, L5->as_VMReg()->next()); 118 reg_def R_L5 ( NS, NS, Op_RegI, 21, L5->as_VMReg()); 119 reg_def R_L6H( NS, NS, Op_RegI,150, L6->as_VMReg()->next()); 120 reg_def R_L6 ( NS, NS, Op_RegI, 22, L6->as_VMReg()); 121 reg_def R_L7H( NS, NS, Op_RegI,151, L7->as_VMReg()->next()); 122 reg_def R_L7 ( NS, NS, Op_RegI, 23, L7->as_VMReg()); 123 124 // Input Registers 0-7 125 reg_def R_I0H( NS, NS, Op_RegI,152, I0->as_VMReg()->next()); 126 reg_def R_I0 ( NS, NS, Op_RegI, 24, I0->as_VMReg()); 127 reg_def R_I1H( NS, NS, Op_RegI,153, I1->as_VMReg()->next()); 128 reg_def R_I1 ( NS, NS, Op_RegI, 25, I1->as_VMReg()); 129 reg_def R_I2H( NS, NS, Op_RegI,154, I2->as_VMReg()->next()); 130 reg_def R_I2 ( NS, NS, Op_RegI, 26, I2->as_VMReg()); 131 reg_def R_I3H( NS, NS, Op_RegI,155, I3->as_VMReg()->next()); 132 reg_def R_I3 ( NS, NS, Op_RegI, 27, I3->as_VMReg()); 133 reg_def R_I4H( NS, NS, Op_RegI,156, I4->as_VMReg()->next()); 134 reg_def R_I4 ( NS, NS, Op_RegI, 28, I4->as_VMReg()); 135 reg_def R_I5H( NS, NS, Op_RegI,157, I5->as_VMReg()->next()); 136 reg_def R_I5 ( NS, NS, Op_RegI, 29, I5->as_VMReg()); 137 reg_def R_FPH( NS, NS, Op_RegI,158, FP->as_VMReg()->next()); 138 reg_def R_FP ( NS, NS, Op_RegI, 30, FP->as_VMReg()); 139 reg_def R_I7H( NS, NS, Op_RegI,159, I7->as_VMReg()->next()); 140 reg_def R_I7 ( NS, NS, Op_RegI, 31, I7->as_VMReg()); 141 142 // ---------------------------- 143 // Float/Double Registers 144 // ---------------------------- 145 146 // Float Registers 147 reg_def R_F0 ( SOC, SOC, Op_RegF, 0, F0->as_VMReg()); 148 reg_def R_F1 ( SOC, SOC, Op_RegF, 1, F1->as_VMReg()); 149 reg_def R_F2 ( SOC, SOC, Op_RegF, 2, F2->as_VMReg()); 150 reg_def R_F3 ( SOC, SOC, Op_RegF, 3, F3->as_VMReg()); 151 reg_def R_F4 ( SOC, SOC, Op_RegF, 4, F4->as_VMReg()); 152 reg_def R_F5 ( SOC, SOC, Op_RegF, 5, F5->as_VMReg()); 153 reg_def R_F6 ( SOC, SOC, Op_RegF, 6, F6->as_VMReg()); 154 reg_def R_F7 ( SOC, SOC, Op_RegF, 7, F7->as_VMReg()); 155 reg_def R_F8 ( SOC, SOC, Op_RegF, 8, F8->as_VMReg()); 156 reg_def R_F9 ( SOC, SOC, Op_RegF, 9, F9->as_VMReg()); 157 reg_def R_F10( SOC, SOC, Op_RegF, 10, F10->as_VMReg()); 158 reg_def R_F11( SOC, SOC, Op_RegF, 11, F11->as_VMReg()); 159 reg_def R_F12( SOC, SOC, Op_RegF, 12, F12->as_VMReg()); 160 reg_def R_F13( SOC, SOC, Op_RegF, 13, F13->as_VMReg()); 161 reg_def R_F14( SOC, SOC, Op_RegF, 14, F14->as_VMReg()); 162 reg_def R_F15( SOC, SOC, Op_RegF, 15, F15->as_VMReg()); 163 reg_def R_F16( SOC, SOC, Op_RegF, 16, F16->as_VMReg()); 164 reg_def R_F17( SOC, SOC, Op_RegF, 17, F17->as_VMReg()); 165 reg_def R_F18( SOC, SOC, Op_RegF, 18, F18->as_VMReg()); 166 reg_def R_F19( SOC, SOC, Op_RegF, 19, F19->as_VMReg()); 167 reg_def R_F20( SOC, SOC, Op_RegF, 20, F20->as_VMReg()); 168 reg_def R_F21( SOC, SOC, Op_RegF, 21, F21->as_VMReg()); 169 reg_def R_F22( SOC, SOC, Op_RegF, 22, F22->as_VMReg()); 170 reg_def R_F23( SOC, SOC, Op_RegF, 23, F23->as_VMReg()); 171 reg_def R_F24( SOC, SOC, Op_RegF, 24, F24->as_VMReg()); 172 reg_def R_F25( SOC, SOC, Op_RegF, 25, F25->as_VMReg()); 173 reg_def R_F26( SOC, SOC, Op_RegF, 26, F26->as_VMReg()); 174 reg_def R_F27( SOC, SOC, Op_RegF, 27, F27->as_VMReg()); 175 reg_def R_F28( SOC, SOC, Op_RegF, 28, F28->as_VMReg()); 176 reg_def R_F29( SOC, SOC, Op_RegF, 29, F29->as_VMReg()); 177 reg_def R_F30( SOC, SOC, Op_RegF, 30, F30->as_VMReg()); 178 reg_def R_F31( SOC, SOC, Op_RegF, 31, F31->as_VMReg()); 179 180 // Double Registers 181 // The rules of ADL require that double registers be defined in pairs. 182 // Each pair must be two 32-bit values, but not necessarily a pair of 183 // single float registers. In each pair, ADLC-assigned register numbers 184 // must be adjacent, with the lower number even. Finally, when the 185 // CPU stores such a register pair to memory, the word associated with 186 // the lower ADLC-assigned number must be stored to the lower address. 187 188 // These definitions specify the actual bit encodings of the sparc 189 // double fp register numbers. FloatRegisterImpl in register_sparc.hpp 190 // wants 0-63, so we have to convert every time we want to use fp regs 191 // with the macroassembler, using reg_to_DoubleFloatRegister_object(). 192 // 255 is a flag meaning "don't go here". 193 // I believe we can't handle callee-save doubles D32 and up until 194 // the place in the sparc stack crawler that asserts on the 255 is 195 // fixed up. 196 reg_def R_D32x(SOC, SOC, Op_RegD,255, F32->as_VMReg()); 197 reg_def R_D32 (SOC, SOC, Op_RegD, 1, F32->as_VMReg()->next()); 198 reg_def R_D34x(SOC, SOC, Op_RegD,255, F34->as_VMReg()); 199 reg_def R_D34 (SOC, SOC, Op_RegD, 3, F34->as_VMReg()->next()); 200 reg_def R_D36x(SOC, SOC, Op_RegD,255, F36->as_VMReg()); 201 reg_def R_D36 (SOC, SOC, Op_RegD, 5, F36->as_VMReg()->next()); 202 reg_def R_D38x(SOC, SOC, Op_RegD,255, F38->as_VMReg()); 203 reg_def R_D38 (SOC, SOC, Op_RegD, 7, F38->as_VMReg()->next()); 204 reg_def R_D40x(SOC, SOC, Op_RegD,255, F40->as_VMReg()); 205 reg_def R_D40 (SOC, SOC, Op_RegD, 9, F40->as_VMReg()->next()); 206 reg_def R_D42x(SOC, SOC, Op_RegD,255, F42->as_VMReg()); 207 reg_def R_D42 (SOC, SOC, Op_RegD, 11, F42->as_VMReg()->next()); 208 reg_def R_D44x(SOC, SOC, Op_RegD,255, F44->as_VMReg()); 209 reg_def R_D44 (SOC, SOC, Op_RegD, 13, F44->as_VMReg()->next()); 210 reg_def R_D46x(SOC, SOC, Op_RegD,255, F46->as_VMReg()); 211 reg_def R_D46 (SOC, SOC, Op_RegD, 15, F46->as_VMReg()->next()); 212 reg_def R_D48x(SOC, SOC, Op_RegD,255, F48->as_VMReg()); 213 reg_def R_D48 (SOC, SOC, Op_RegD, 17, F48->as_VMReg()->next()); 214 reg_def R_D50x(SOC, SOC, Op_RegD,255, F50->as_VMReg()); 215 reg_def R_D50 (SOC, SOC, Op_RegD, 19, F50->as_VMReg()->next()); 216 reg_def R_D52x(SOC, SOC, Op_RegD,255, F52->as_VMReg()); 217 reg_def R_D52 (SOC, SOC, Op_RegD, 21, F52->as_VMReg()->next()); 218 reg_def R_D54x(SOC, SOC, Op_RegD,255, F54->as_VMReg()); 219 reg_def R_D54 (SOC, SOC, Op_RegD, 23, F54->as_VMReg()->next()); 220 reg_def R_D56x(SOC, SOC, Op_RegD,255, F56->as_VMReg()); 221 reg_def R_D56 (SOC, SOC, Op_RegD, 25, F56->as_VMReg()->next()); 222 reg_def R_D58x(SOC, SOC, Op_RegD,255, F58->as_VMReg()); 223 reg_def R_D58 (SOC, SOC, Op_RegD, 27, F58->as_VMReg()->next()); 224 reg_def R_D60x(SOC, SOC, Op_RegD,255, F60->as_VMReg()); 225 reg_def R_D60 (SOC, SOC, Op_RegD, 29, F60->as_VMReg()->next()); 226 reg_def R_D62x(SOC, SOC, Op_RegD,255, F62->as_VMReg()); 227 reg_def R_D62 (SOC, SOC, Op_RegD, 31, F62->as_VMReg()->next()); 228 229 230 // ---------------------------- 231 // Special Registers 232 // Condition Codes Flag Registers 233 // I tried to break out ICC and XCC but it's not very pretty. 234 // Every Sparc instruction which defs/kills one also kills the other. 235 // Hence every compare instruction which defs one kind of flags ends 236 // up needing a kill of the other. 237 reg_def CCR (SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad()); 238 239 reg_def FCC0(SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad()); 240 reg_def FCC1(SOC, SOC, Op_RegFlags, 1, VMRegImpl::Bad()); 241 reg_def FCC2(SOC, SOC, Op_RegFlags, 2, VMRegImpl::Bad()); 242 reg_def FCC3(SOC, SOC, Op_RegFlags, 3, VMRegImpl::Bad()); 243 244 // ---------------------------- 245 // Specify the enum values for the registers. These enums are only used by the 246 // OptoReg "class". We can convert these enum values at will to VMReg when needed 247 // for visibility to the rest of the vm. The order of this enum influences the 248 // register allocator so having the freedom to set this order and not be stuck 249 // with the order that is natural for the rest of the vm is worth it. 250 alloc_class chunk0( 251 R_L0,R_L0H, R_L1,R_L1H, R_L2,R_L2H, R_L3,R_L3H, R_L4,R_L4H, R_L5,R_L5H, R_L6,R_L6H, R_L7,R_L7H, 252 R_G0,R_G0H, R_G1,R_G1H, R_G2,R_G2H, R_G3,R_G3H, R_G4,R_G4H, R_G5,R_G5H, R_G6,R_G6H, R_G7,R_G7H, 253 R_O7,R_O7H, R_SP,R_SPH, R_O0,R_O0H, R_O1,R_O1H, R_O2,R_O2H, R_O3,R_O3H, R_O4,R_O4H, R_O5,R_O5H, 254 R_I0,R_I0H, R_I1,R_I1H, R_I2,R_I2H, R_I3,R_I3H, R_I4,R_I4H, R_I5,R_I5H, R_FP,R_FPH, R_I7,R_I7H); 255 256 // Note that a register is not allocatable unless it is also mentioned 257 // in a widely-used reg_class below. Thus, R_G7 and R_G0 are outside i_reg. 258 259 alloc_class chunk1( 260 // The first registers listed here are those most likely to be used 261 // as temporaries. We move F0..F7 away from the front of the list, 262 // to reduce the likelihood of interferences with parameters and 263 // return values. Likewise, we avoid using F0/F1 for parameters, 264 // since they are used for return values. 265 // This FPU fine-tuning is worth about 1% on the SPEC geomean. 266 R_F8 ,R_F9 ,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15, 267 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23, 268 R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,R_F30,R_F31, 269 R_F0 ,R_F1 ,R_F2 ,R_F3 ,R_F4 ,R_F5 ,R_F6 ,R_F7 , // used for arguments and return values 270 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x, 271 R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x, 272 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x, 273 R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x); 274 275 alloc_class chunk2(CCR, FCC0, FCC1, FCC2, FCC3); 276 277 //----------Architecture Description Register Classes-------------------------- 278 // Several register classes are automatically defined based upon information in 279 // this architecture description. 280 // 1) reg_class inline_cache_reg ( as defined in frame section ) 281 // 2) reg_class interpreter_method_oop_reg ( as defined in frame section ) 282 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ ) 283 // 284 285 // G0 is not included in integer class since it has special meaning. 286 reg_class g0_reg(R_G0); 287 288 // ---------------------------- 289 // Integer Register Classes 290 // ---------------------------- 291 // Exclusions from i_reg: 292 // R_G0: hardwired zero 293 // R_G2: reserved by HotSpot to the TLS register (invariant within Java) 294 // R_G6: reserved by Solaris ABI to tools 295 // R_G7: reserved by Solaris ABI to libthread 296 // R_O7: Used as a temp in many encodings 297 reg_class int_reg(R_G1,R_G3,R_G4,R_G5,R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); 298 299 // Class for all integer registers, except the G registers. This is used for 300 // encodings which use G registers as temps. The regular inputs to such 301 // instructions use a "notemp_" prefix, as a hack to ensure that the allocator 302 // will not put an input into a temp register. 303 reg_class notemp_int_reg(R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); 304 305 reg_class g1_regI(R_G1); 306 reg_class g3_regI(R_G3); 307 reg_class g4_regI(R_G4); 308 reg_class o0_regI(R_O0); 309 reg_class o7_regI(R_O7); 310 311 // ---------------------------- 312 // Pointer Register Classes 313 // ---------------------------- 314 #ifdef _LP64 315 // 64-bit build means 64-bit pointers means hi/lo pairs 316 reg_class ptr_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5, 317 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, 318 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7, 319 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 ); 320 // Lock encodings use G3 and G4 internally 321 reg_class lock_ptr_reg( R_G1H,R_G1, R_G5H,R_G5, 322 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, 323 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7, 324 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 ); 325 // Special class for storeP instructions, which can store SP or RPC to TLS. 326 // It is also used for memory addressing, allowing direct TLS addressing. 327 reg_class sp_ptr_reg( R_G1H,R_G1, R_G2H,R_G2, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5, 328 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, R_SPH,R_SP, 329 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7, 330 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5, R_FPH,R_FP ); 331 // R_L7 is the lowest-priority callee-save (i.e., NS) register 332 // We use it to save R_G2 across calls out of Java. 333 reg_class l7_regP(R_L7H,R_L7); 334 335 // Other special pointer regs 336 reg_class g1_regP(R_G1H,R_G1); 337 reg_class g2_regP(R_G2H,R_G2); 338 reg_class g3_regP(R_G3H,R_G3); 339 reg_class g4_regP(R_G4H,R_G4); 340 reg_class g5_regP(R_G5H,R_G5); 341 reg_class i0_regP(R_I0H,R_I0); 342 reg_class o0_regP(R_O0H,R_O0); 343 reg_class o1_regP(R_O1H,R_O1); 344 reg_class o2_regP(R_O2H,R_O2); 345 reg_class o7_regP(R_O7H,R_O7); 346 347 #else // _LP64 348 // 32-bit build means 32-bit pointers means 1 register. 349 reg_class ptr_reg( R_G1, R_G3,R_G4,R_G5, 350 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5, 351 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7, 352 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); 353 // Lock encodings use G3 and G4 internally 354 reg_class lock_ptr_reg(R_G1, R_G5, 355 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5, 356 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7, 357 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); 358 // Special class for storeP instructions, which can store SP or RPC to TLS. 359 // It is also used for memory addressing, allowing direct TLS addressing. 360 reg_class sp_ptr_reg( R_G1,R_G2,R_G3,R_G4,R_G5, 361 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_SP, 362 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7, 363 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5,R_FP); 364 // R_L7 is the lowest-priority callee-save (i.e., NS) register 365 // We use it to save R_G2 across calls out of Java. 366 reg_class l7_regP(R_L7); 367 368 // Other special pointer regs 369 reg_class g1_regP(R_G1); 370 reg_class g2_regP(R_G2); 371 reg_class g3_regP(R_G3); 372 reg_class g4_regP(R_G4); 373 reg_class g5_regP(R_G5); 374 reg_class i0_regP(R_I0); 375 reg_class o0_regP(R_O0); 376 reg_class o1_regP(R_O1); 377 reg_class o2_regP(R_O2); 378 reg_class o7_regP(R_O7); 379 #endif // _LP64 380 381 382 // ---------------------------- 383 // Long Register Classes 384 // ---------------------------- 385 // Longs in 1 register. Aligned adjacent hi/lo pairs. 386 // Note: O7 is never in this class; it is sometimes used as an encoding temp. 387 reg_class long_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5 388 ,R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5 389 #ifdef _LP64 390 // 64-bit, longs in 1 register: use all 64-bit integer registers 391 // 32-bit, longs in 1 register: cannot use I's and L's. Restrict to O's and G's. 392 ,R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7 393 ,R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 394 #endif // _LP64 395 ); 396 397 reg_class g1_regL(R_G1H,R_G1); 398 reg_class g3_regL(R_G3H,R_G3); 399 reg_class o2_regL(R_O2H,R_O2); 400 reg_class o7_regL(R_O7H,R_O7); 401 402 // ---------------------------- 403 // Special Class for Condition Code Flags Register 404 reg_class int_flags(CCR); 405 reg_class float_flags(FCC0,FCC1,FCC2,FCC3); 406 reg_class float_flag0(FCC0); 407 408 409 // ---------------------------- 410 // Float Point Register Classes 411 // ---------------------------- 412 // Skip F30/F31, they are reserved for mem-mem copies 413 reg_class sflt_reg(R_F0,R_F1,R_F2,R_F3,R_F4,R_F5,R_F6,R_F7,R_F8,R_F9,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29); 414 415 // Paired floating point registers--they show up in the same order as the floats, 416 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs. 417 reg_class dflt_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15, 418 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29, 419 /* Use extra V9 double registers; this AD file does not support V8 */ 420 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x, 421 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x 422 ); 423 424 // Paired floating point registers--they show up in the same order as the floats, 425 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs. 426 // This class is usable for mis-aligned loads as happen in I2C adapters. 427 reg_class dflt_low_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15, 428 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,R_F30,R_F31 ); 429 %} 430 431 //----------DEFINITION BLOCK--------------------------------------------------- 432 // Define name --> value mappings to inform the ADLC of an integer valued name 433 // Current support includes integer values in the range [0, 0x7FFFFFFF] 434 // Format: 435 // int_def <name> ( <int_value>, <expression>); 436 // Generated Code in ad_<arch>.hpp 437 // #define <name> (<expression>) 438 // // value == <int_value> 439 // Generated code in ad_<arch>.cpp adlc_verification() 440 // assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>"); 441 // 442 definitions %{ 443 // The default cost (of an ALU instruction). 444 int_def DEFAULT_COST ( 100, 100); 445 int_def HUGE_COST (1000000, 1000000); 446 447 // Memory refs are twice as expensive as run-of-the-mill. 448 int_def MEMORY_REF_COST ( 200, DEFAULT_COST * 2); 449 450 // Branches are even more expensive. 451 int_def BRANCH_COST ( 300, DEFAULT_COST * 3); 452 int_def CALL_COST ( 300, DEFAULT_COST * 3); 453 %} 454 455 456 //----------SOURCE BLOCK------------------------------------------------------- 457 // This is a block of C++ code which provides values, functions, and 458 // definitions necessary in the rest of the architecture description 459 source_hpp %{ 460 // Must be visible to the DFA in dfa_sparc.cpp 461 extern bool can_branch_register( Node *bol, Node *cmp ); 462 463 // Macros to extract hi & lo halves from a long pair. 464 // G0 is not part of any long pair, so assert on that. 465 // Prevents accidentally using G1 instead of G0. 466 #define LONG_HI_REG(x) (x) 467 #define LONG_LO_REG(x) (x) 468 469 %} 470 471 source %{ 472 #define __ _masm. 473 474 // tertiary op of a LoadP or StoreP encoding 475 #define REGP_OP true 476 477 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding); 478 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding); 479 static Register reg_to_register_object(int register_encoding); 480 481 // Used by the DFA in dfa_sparc.cpp. 482 // Check for being able to use a V9 branch-on-register. Requires a 483 // compare-vs-zero, equal/not-equal, of a value which was zero- or sign- 484 // extended. Doesn't work following an integer ADD, for example, because of 485 // overflow (-1 incremented yields 0 plus a carry in the high-order word). On 486 // 32-bit V9 systems, interrupts currently blow away the high-order 32 bits and 487 // replace them with zero, which could become sign-extension in a different OS 488 // release. There's no obvious reason why an interrupt will ever fill these 489 // bits with non-zero junk (the registers are reloaded with standard LD 490 // instructions which either zero-fill or sign-fill). 491 bool can_branch_register( Node *bol, Node *cmp ) { 492 if( !BranchOnRegister ) return false; 493 #ifdef _LP64 494 if( cmp->Opcode() == Op_CmpP ) 495 return true; // No problems with pointer compares 496 #endif 497 if( cmp->Opcode() == Op_CmpL ) 498 return true; // No problems with long compares 499 500 if( !SparcV9RegsHiBitsZero ) return false; 501 if( bol->as_Bool()->_test._test != BoolTest::ne && 502 bol->as_Bool()->_test._test != BoolTest::eq ) 503 return false; 504 505 // Check for comparing against a 'safe' value. Any operation which 506 // clears out the high word is safe. Thus, loads and certain shifts 507 // are safe, as are non-negative constants. Any operation which 508 // preserves zero bits in the high word is safe as long as each of its 509 // inputs are safe. Thus, phis and bitwise booleans are safe if their 510 // inputs are safe. At present, the only important case to recognize 511 // seems to be loads. Constants should fold away, and shifts & 512 // logicals can use the 'cc' forms. 513 Node *x = cmp->in(1); 514 if( x->is_Load() ) return true; 515 if( x->is_Phi() ) { 516 for( uint i = 1; i < x->req(); i++ ) 517 if( !x->in(i)->is_Load() ) 518 return false; 519 return true; 520 } 521 return false; 522 } 523 524 // **************************************************************************** 525 526 // REQUIRED FUNCTIONALITY 527 528 // !!!!! Special hack to get all type of calls to specify the byte offset 529 // from the start of the call to the point where the return address 530 // will point. 531 // The "return address" is the address of the call instruction, plus 8. 532 533 int MachCallStaticJavaNode::ret_addr_offset() { 534 return NativeCall::instruction_size; // call; delay slot 535 } 536 537 int MachCallDynamicJavaNode::ret_addr_offset() { 538 int vtable_index = this->_vtable_index; 539 if (vtable_index < 0) { 540 // must be invalid_vtable_index, not nonvirtual_vtable_index 541 assert(vtable_index == methodOopDesc::invalid_vtable_index, "correct sentinel value"); 542 return (NativeMovConstReg::instruction_size + 543 NativeCall::instruction_size); // sethi; setlo; call; delay slot 544 } else { 545 assert(!UseInlineCaches, "expect vtable calls only if not using ICs"); 546 int entry_offset = instanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size(); 547 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes(); 548 int klass_load_size; 549 if (UseCompressedOops) { 550 assert(Universe::heap() != NULL, "java heap should be initialized"); 551 if (Universe::narrow_oop_base() == NULL) 552 klass_load_size = 2*BytesPerInstWord; // see MacroAssembler::load_klass() 553 else 554 klass_load_size = 3*BytesPerInstWord; 555 } else { 556 klass_load_size = 1*BytesPerInstWord; 557 } 558 if( Assembler::is_simm13(v_off) ) { 559 return klass_load_size + 560 (2*BytesPerInstWord + // ld_ptr, ld_ptr 561 NativeCall::instruction_size); // call; delay slot 562 } else { 563 return klass_load_size + 564 (4*BytesPerInstWord + // set_hi, set, ld_ptr, ld_ptr 565 NativeCall::instruction_size); // call; delay slot 566 } 567 } 568 } 569 570 int MachCallRuntimeNode::ret_addr_offset() { 571 #ifdef _LP64 572 return NativeFarCall::instruction_size; // farcall; delay slot 573 #else 574 return NativeCall::instruction_size; // call; delay slot 575 #endif 576 } 577 578 // Indicate if the safepoint node needs the polling page as an input. 579 // Since Sparc does not have absolute addressing, it does. 580 bool SafePointNode::needs_polling_address_input() { 581 return true; 582 } 583 584 // emit an interrupt that is caught by the debugger (for debugging compiler) 585 void emit_break(CodeBuffer &cbuf) { 586 MacroAssembler _masm(&cbuf); 587 __ breakpoint_trap(); 588 } 589 590 #ifndef PRODUCT 591 void MachBreakpointNode::format( PhaseRegAlloc *, outputStream *st ) const { 592 st->print("TA"); 593 } 594 #endif 595 596 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 597 emit_break(cbuf); 598 } 599 600 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const { 601 return MachNode::size(ra_); 602 } 603 604 // Traceable jump 605 void emit_jmpl(CodeBuffer &cbuf, int jump_target) { 606 MacroAssembler _masm(&cbuf); 607 Register rdest = reg_to_register_object(jump_target); 608 __ JMP(rdest, 0); 609 __ delayed()->nop(); 610 } 611 612 // Traceable jump and set exception pc 613 void emit_jmpl_set_exception_pc(CodeBuffer &cbuf, int jump_target) { 614 MacroAssembler _masm(&cbuf); 615 Register rdest = reg_to_register_object(jump_target); 616 __ JMP(rdest, 0); 617 __ delayed()->add(O7, frame::pc_return_offset, Oissuing_pc ); 618 } 619 620 void emit_nop(CodeBuffer &cbuf) { 621 MacroAssembler _masm(&cbuf); 622 __ nop(); 623 } 624 625 void emit_illtrap(CodeBuffer &cbuf) { 626 MacroAssembler _masm(&cbuf); 627 __ illtrap(0); 628 } 629 630 631 intptr_t get_offset_from_base(const MachNode* n, const TypePtr* atype, int disp32) { 632 assert(n->rule() != loadUB_rule, ""); 633 634 intptr_t offset = 0; 635 const TypePtr *adr_type = TYPE_PTR_SENTINAL; // Check for base==RegI, disp==immP 636 const Node* addr = n->get_base_and_disp(offset, adr_type); 637 assert(adr_type == (const TypePtr*)-1, "VerifyOops: no support for sparc operands with base==RegI, disp==immP"); 638 assert(addr != NULL && addr != (Node*)-1, "invalid addr"); 639 assert(addr->bottom_type()->isa_oopptr() == atype, ""); 640 atype = atype->add_offset(offset); 641 assert(disp32 == offset, "wrong disp32"); 642 return atype->_offset; 643 } 644 645 646 intptr_t get_offset_from_base_2(const MachNode* n, const TypePtr* atype, int disp32) { 647 assert(n->rule() != loadUB_rule, ""); 648 649 intptr_t offset = 0; 650 Node* addr = n->in(2); 651 assert(addr->bottom_type()->isa_oopptr() == atype, ""); 652 if (addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP) { 653 Node* a = addr->in(2/*AddPNode::Address*/); 654 Node* o = addr->in(3/*AddPNode::Offset*/); 655 offset = o->is_Con() ? o->bottom_type()->is_intptr_t()->get_con() : Type::OffsetBot; 656 atype = a->bottom_type()->is_ptr()->add_offset(offset); 657 assert(atype->isa_oop_ptr(), "still an oop"); 658 } 659 offset = atype->is_ptr()->_offset; 660 if (offset != Type::OffsetBot) offset += disp32; 661 return offset; 662 } 663 664 // Standard Sparc opcode form2 field breakdown 665 static inline void emit2_19(CodeBuffer &cbuf, int f30, int f29, int f25, int f22, int f20, int f19, int f0 ) { 666 f0 &= (1<<19)-1; // Mask displacement to 19 bits 667 int op = (f30 << 30) | 668 (f29 << 29) | 669 (f25 << 25) | 670 (f22 << 22) | 671 (f20 << 20) | 672 (f19 << 19) | 673 (f0 << 0); 674 *((int*)(cbuf.code_end())) = op; 675 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); 676 } 677 678 // Standard Sparc opcode form2 field breakdown 679 static inline void emit2_22(CodeBuffer &cbuf, int f30, int f25, int f22, int f0 ) { 680 f0 >>= 10; // Drop 10 bits 681 f0 &= (1<<22)-1; // Mask displacement to 22 bits 682 int op = (f30 << 30) | 683 (f25 << 25) | 684 (f22 << 22) | 685 (f0 << 0); 686 *((int*)(cbuf.code_end())) = op; 687 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); 688 } 689 690 // Standard Sparc opcode form3 field breakdown 691 static inline void emit3(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int f5, int f0 ) { 692 int op = (f30 << 30) | 693 (f25 << 25) | 694 (f19 << 19) | 695 (f14 << 14) | 696 (f5 << 5) | 697 (f0 << 0); 698 *((int*)(cbuf.code_end())) = op; 699 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); 700 } 701 702 // Standard Sparc opcode form3 field breakdown 703 static inline void emit3_simm13(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm13 ) { 704 simm13 &= (1<<13)-1; // Mask to 13 bits 705 int op = (f30 << 30) | 706 (f25 << 25) | 707 (f19 << 19) | 708 (f14 << 14) | 709 (1 << 13) | // bit to indicate immediate-mode 710 (simm13<<0); 711 *((int*)(cbuf.code_end())) = op; 712 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); 713 } 714 715 static inline void emit3_simm10(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm10 ) { 716 simm10 &= (1<<10)-1; // Mask to 10 bits 717 emit3_simm13(cbuf,f30,f25,f19,f14,simm10); 718 } 719 720 #ifdef ASSERT 721 // Helper function for VerifyOops in emit_form3_mem_reg 722 void verify_oops_warning(const MachNode *n, int ideal_op, int mem_op) { 723 warning("VerifyOops encountered unexpected instruction:"); 724 n->dump(2); 725 warning("Instruction has ideal_Opcode==Op_%s and op_ld==Op_%s \n", NodeClassNames[ideal_op], NodeClassNames[mem_op]); 726 } 727 #endif 728 729 730 void emit_form3_mem_reg(CodeBuffer &cbuf, const MachNode* n, int primary, int tertiary, 731 int src1_enc, int disp32, int src2_enc, int dst_enc) { 732 733 #ifdef ASSERT 734 // The following code implements the +VerifyOops feature. 735 // It verifies oop values which are loaded into or stored out of 736 // the current method activation. +VerifyOops complements techniques 737 // like ScavengeALot, because it eagerly inspects oops in transit, 738 // as they enter or leave the stack, as opposed to ScavengeALot, 739 // which inspects oops "at rest", in the stack or heap, at safepoints. 740 // For this reason, +VerifyOops can sometimes detect bugs very close 741 // to their point of creation. It can also serve as a cross-check 742 // on the validity of oop maps, when used toegether with ScavengeALot. 743 744 // It would be good to verify oops at other points, especially 745 // when an oop is used as a base pointer for a load or store. 746 // This is presently difficult, because it is hard to know when 747 // a base address is biased or not. (If we had such information, 748 // it would be easy and useful to make a two-argument version of 749 // verify_oop which unbiases the base, and performs verification.) 750 751 assert((uint)tertiary == 0xFFFFFFFF || tertiary == REGP_OP, "valid tertiary"); 752 bool is_verified_oop_base = false; 753 bool is_verified_oop_load = false; 754 bool is_verified_oop_store = false; 755 int tmp_enc = -1; 756 if (VerifyOops && src1_enc != R_SP_enc) { 757 // classify the op, mainly for an assert check 758 int st_op = 0, ld_op = 0; 759 switch (primary) { 760 case Assembler::stb_op3: st_op = Op_StoreB; break; 761 case Assembler::sth_op3: st_op = Op_StoreC; break; 762 case Assembler::stx_op3: // may become StoreP or stay StoreI or StoreD0 763 case Assembler::stw_op3: st_op = Op_StoreI; break; 764 case Assembler::std_op3: st_op = Op_StoreL; break; 765 case Assembler::stf_op3: st_op = Op_StoreF; break; 766 case Assembler::stdf_op3: st_op = Op_StoreD; break; 767 768 case Assembler::ldsb_op3: ld_op = Op_LoadB; break; 769 case Assembler::lduh_op3: ld_op = Op_LoadUS; break; 770 case Assembler::ldsh_op3: ld_op = Op_LoadS; break; 771 case Assembler::ldx_op3: // may become LoadP or stay LoadI 772 case Assembler::ldsw_op3: // may become LoadP or stay LoadI 773 case Assembler::lduw_op3: ld_op = Op_LoadI; break; 774 case Assembler::ldd_op3: ld_op = Op_LoadL; break; 775 case Assembler::ldf_op3: ld_op = Op_LoadF; break; 776 case Assembler::lddf_op3: ld_op = Op_LoadD; break; 777 case Assembler::ldub_op3: ld_op = Op_LoadB; break; 778 case Assembler::prefetch_op3: ld_op = Op_LoadI; break; 779 780 default: ShouldNotReachHere(); 781 } 782 if (tertiary == REGP_OP) { 783 if (st_op == Op_StoreI) st_op = Op_StoreP; 784 else if (ld_op == Op_LoadI) ld_op = Op_LoadP; 785 else ShouldNotReachHere(); 786 if (st_op) { 787 // a store 788 // inputs are (0:control, 1:memory, 2:address, 3:value) 789 Node* n2 = n->in(3); 790 if (n2 != NULL) { 791 const Type* t = n2->bottom_type(); 792 is_verified_oop_store = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false; 793 } 794 } else { 795 // a load 796 const Type* t = n->bottom_type(); 797 is_verified_oop_load = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false; 798 } 799 } 800 801 if (ld_op) { 802 // a Load 803 // inputs are (0:control, 1:memory, 2:address) 804 if (!(n->ideal_Opcode()==ld_op) && // Following are special cases 805 !(n->ideal_Opcode()==Op_LoadLLocked && ld_op==Op_LoadI) && 806 !(n->ideal_Opcode()==Op_LoadPLocked && ld_op==Op_LoadP) && 807 !(n->ideal_Opcode()==Op_LoadI && ld_op==Op_LoadF) && 808 !(n->ideal_Opcode()==Op_LoadF && ld_op==Op_LoadI) && 809 !(n->ideal_Opcode()==Op_LoadRange && ld_op==Op_LoadI) && 810 !(n->ideal_Opcode()==Op_LoadKlass && ld_op==Op_LoadP) && 811 !(n->ideal_Opcode()==Op_LoadL && ld_op==Op_LoadI) && 812 !(n->ideal_Opcode()==Op_LoadL_unaligned && ld_op==Op_LoadI) && 813 !(n->ideal_Opcode()==Op_LoadD_unaligned && ld_op==Op_LoadF) && 814 !(n->ideal_Opcode()==Op_ConvI2F && ld_op==Op_LoadF) && 815 !(n->ideal_Opcode()==Op_ConvI2D && ld_op==Op_LoadF) && 816 !(n->ideal_Opcode()==Op_PrefetchRead && ld_op==Op_LoadI) && 817 !(n->ideal_Opcode()==Op_PrefetchWrite && ld_op==Op_LoadI) && 818 !(n->rule() == loadUB_rule)) { 819 verify_oops_warning(n, n->ideal_Opcode(), ld_op); 820 } 821 } else if (st_op) { 822 // a Store 823 // inputs are (0:control, 1:memory, 2:address, 3:value) 824 if (!(n->ideal_Opcode()==st_op) && // Following are special cases 825 !(n->ideal_Opcode()==Op_StoreCM && st_op==Op_StoreB) && 826 !(n->ideal_Opcode()==Op_StoreI && st_op==Op_StoreF) && 827 !(n->ideal_Opcode()==Op_StoreF && st_op==Op_StoreI) && 828 !(n->ideal_Opcode()==Op_StoreL && st_op==Op_StoreI) && 829 !(n->ideal_Opcode()==Op_StoreD && st_op==Op_StoreI && n->rule() == storeD0_rule)) { 830 verify_oops_warning(n, n->ideal_Opcode(), st_op); 831 } 832 } 833 834 if (src2_enc == R_G0_enc && n->rule() != loadUB_rule && n->ideal_Opcode() != Op_StoreCM ) { 835 Node* addr = n->in(2); 836 if (!(addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP)) { 837 const TypeOopPtr* atype = addr->bottom_type()->isa_instptr(); // %%% oopptr? 838 if (atype != NULL) { 839 intptr_t offset = get_offset_from_base(n, atype, disp32); 840 intptr_t offset_2 = get_offset_from_base_2(n, atype, disp32); 841 if (offset != offset_2) { 842 get_offset_from_base(n, atype, disp32); 843 get_offset_from_base_2(n, atype, disp32); 844 } 845 assert(offset == offset_2, "different offsets"); 846 if (offset == disp32) { 847 // we now know that src1 is a true oop pointer 848 is_verified_oop_base = true; 849 if (ld_op && src1_enc == dst_enc && ld_op != Op_LoadF && ld_op != Op_LoadD) { 850 if( primary == Assembler::ldd_op3 ) { 851 is_verified_oop_base = false; // Cannot 'ldd' into O7 852 } else { 853 tmp_enc = dst_enc; 854 dst_enc = R_O7_enc; // Load into O7; preserve source oop 855 assert(src1_enc != dst_enc, ""); 856 } 857 } 858 } 859 if (st_op && (( offset == oopDesc::klass_offset_in_bytes()) 860 || offset == oopDesc::mark_offset_in_bytes())) { 861 // loading the mark should not be allowed either, but 862 // we don't check this since it conflicts with InlineObjectHash 863 // usage of LoadINode to get the mark. We could keep the 864 // check if we create a new LoadMarkNode 865 // but do not verify the object before its header is initialized 866 ShouldNotReachHere(); 867 } 868 } 869 } 870 } 871 } 872 #endif 873 874 uint instr; 875 instr = (Assembler::ldst_op << 30) 876 | (dst_enc << 25) 877 | (primary << 19) 878 | (src1_enc << 14); 879 880 uint index = src2_enc; 881 int disp = disp32; 882 883 if (src1_enc == R_SP_enc || src1_enc == R_FP_enc) 884 disp += STACK_BIAS; 885 886 // We should have a compiler bailout here rather than a guarantee. 887 // Better yet would be some mechanism to handle variable-size matches correctly. 888 guarantee(Assembler::is_simm13(disp), "Do not match large constant offsets" ); 889 890 if( disp == 0 ) { 891 // use reg-reg form 892 // bit 13 is already zero 893 instr |= index; 894 } else { 895 // use reg-imm form 896 instr |= 0x00002000; // set bit 13 to one 897 instr |= disp & 0x1FFF; 898 } 899 900 uint *code = (uint*)cbuf.code_end(); 901 *code = instr; 902 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); 903 904 #ifdef ASSERT 905 { 906 MacroAssembler _masm(&cbuf); 907 if (is_verified_oop_base) { 908 __ verify_oop(reg_to_register_object(src1_enc)); 909 } 910 if (is_verified_oop_store) { 911 __ verify_oop(reg_to_register_object(dst_enc)); 912 } 913 if (tmp_enc != -1) { 914 __ mov(O7, reg_to_register_object(tmp_enc)); 915 } 916 if (is_verified_oop_load) { 917 __ verify_oop(reg_to_register_object(dst_enc)); 918 } 919 } 920 #endif 921 } 922 923 void emit_form3_mem_reg_asi(CodeBuffer &cbuf, const MachNode* n, int primary, int tertiary, 924 int src1_enc, int disp32, int src2_enc, int dst_enc, int asi) { 925 926 uint instr; 927 instr = (Assembler::ldst_op << 30) 928 | (dst_enc << 25) 929 | (primary << 19) 930 | (src1_enc << 14); 931 932 int disp = disp32; 933 int index = src2_enc; 934 935 if (src1_enc == R_SP_enc || src1_enc == R_FP_enc) 936 disp += STACK_BIAS; 937 938 // We should have a compiler bailout here rather than a guarantee. 939 // Better yet would be some mechanism to handle variable-size matches correctly. 940 guarantee(Assembler::is_simm13(disp), "Do not match large constant offsets" ); 941 942 if( disp != 0 ) { 943 // use reg-reg form 944 // set src2=R_O7 contains offset 945 index = R_O7_enc; 946 emit3_simm13( cbuf, Assembler::arith_op, index, Assembler::or_op3, 0, disp); 947 } 948 instr |= (asi << 5); 949 instr |= index; 950 uint *code = (uint*)cbuf.code_end(); 951 *code = instr; 952 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); 953 } 954 955 void emit_call_reloc(CodeBuffer &cbuf, intptr_t entry_point, relocInfo::relocType rtype, bool preserve_g2 = false, bool force_far_call = false) { 956 // The method which records debug information at every safepoint 957 // expects the call to be the first instruction in the snippet as 958 // it creates a PcDesc structure which tracks the offset of a call 959 // from the start of the codeBlob. This offset is computed as 960 // code_end() - code_begin() of the code which has been emitted 961 // so far. 962 // In this particular case we have skirted around the problem by 963 // putting the "mov" instruction in the delay slot but the problem 964 // may bite us again at some other point and a cleaner/generic 965 // solution using relocations would be needed. 966 MacroAssembler _masm(&cbuf); 967 __ set_inst_mark(); 968 969 // We flush the current window just so that there is a valid stack copy 970 // the fact that the current window becomes active again instantly is 971 // not a problem there is nothing live in it. 972 973 #ifdef ASSERT 974 int startpos = __ offset(); 975 #endif /* ASSERT */ 976 977 #ifdef _LP64 978 // Calls to the runtime or native may not be reachable from compiled code, 979 // so we generate the far call sequence on 64 bit sparc. 980 // This code sequence is relocatable to any address, even on LP64. 981 if ( force_far_call ) { 982 __ relocate(rtype); 983 AddressLiteral dest(entry_point); 984 __ jumpl_to(dest, O7, O7); 985 } 986 else 987 #endif 988 { 989 __ call((address)entry_point, rtype); 990 } 991 992 if (preserve_g2) __ delayed()->mov(G2, L7); 993 else __ delayed()->nop(); 994 995 if (preserve_g2) __ mov(L7, G2); 996 997 #ifdef ASSERT 998 if (preserve_g2 && (VerifyCompiledCode || VerifyOops)) { 999 #ifdef _LP64 1000 // Trash argument dump slots. 1001 __ set(0xb0b8ac0db0b8ac0d, G1); 1002 __ mov(G1, G5); 1003 __ stx(G1, SP, STACK_BIAS + 0x80); 1004 __ stx(G1, SP, STACK_BIAS + 0x88); 1005 __ stx(G1, SP, STACK_BIAS + 0x90); 1006 __ stx(G1, SP, STACK_BIAS + 0x98); 1007 __ stx(G1, SP, STACK_BIAS + 0xA0); 1008 __ stx(G1, SP, STACK_BIAS + 0xA8); 1009 #else // _LP64 1010 // this is also a native call, so smash the first 7 stack locations, 1011 // and the various registers 1012 1013 // Note: [SP+0x40] is sp[callee_aggregate_return_pointer_sp_offset], 1014 // while [SP+0x44..0x58] are the argument dump slots. 1015 __ set((intptr_t)0xbaadf00d, G1); 1016 __ mov(G1, G5); 1017 __ sllx(G1, 32, G1); 1018 __ or3(G1, G5, G1); 1019 __ mov(G1, G5); 1020 __ stx(G1, SP, 0x40); 1021 __ stx(G1, SP, 0x48); 1022 __ stx(G1, SP, 0x50); 1023 __ stw(G1, SP, 0x58); // Do not trash [SP+0x5C] which is a usable spill slot 1024 #endif // _LP64 1025 } 1026 #endif /*ASSERT*/ 1027 } 1028 1029 //============================================================================= 1030 // REQUIRED FUNCTIONALITY for encoding 1031 void emit_lo(CodeBuffer &cbuf, int val) { } 1032 void emit_hi(CodeBuffer &cbuf, int val) { } 1033 1034 1035 //============================================================================= 1036 1037 #ifndef PRODUCT 1038 void MachPrologNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { 1039 Compile* C = ra_->C; 1040 1041 for (int i = 0; i < OptoPrologueNops; i++) { 1042 st->print_cr("NOP"); st->print("\t"); 1043 } 1044 1045 if( VerifyThread ) { 1046 st->print_cr("Verify_Thread"); st->print("\t"); 1047 } 1048 1049 size_t framesize = C->frame_slots() << LogBytesPerInt; 1050 1051 // Calls to C2R adapters often do not accept exceptional returns. 1052 // We require that their callers must bang for them. But be careful, because 1053 // some VM calls (such as call site linkage) can use several kilobytes of 1054 // stack. But the stack safety zone should account for that. 1055 // See bugs 4446381, 4468289, 4497237. 1056 if (C->need_stack_bang(framesize)) { 1057 st->print_cr("! stack bang"); st->print("\t"); 1058 } 1059 1060 if (Assembler::is_simm13(-framesize)) { 1061 st->print ("SAVE R_SP,-%d,R_SP",framesize); 1062 } else { 1063 st->print_cr("SETHI R_SP,hi%%(-%d),R_G3",framesize); st->print("\t"); 1064 st->print_cr("ADD R_G3,lo%%(-%d),R_G3",framesize); st->print("\t"); 1065 st->print ("SAVE R_SP,R_G3,R_SP"); 1066 } 1067 1068 } 1069 #endif 1070 1071 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1072 Compile* C = ra_->C; 1073 MacroAssembler _masm(&cbuf); 1074 1075 for (int i = 0; i < OptoPrologueNops; i++) { 1076 __ nop(); 1077 } 1078 1079 __ verify_thread(); 1080 1081 size_t framesize = C->frame_slots() << LogBytesPerInt; 1082 assert(framesize >= 16*wordSize, "must have room for reg. save area"); 1083 assert(framesize%(2*wordSize) == 0, "must preserve 2*wordSize alignment"); 1084 1085 // Calls to C2R adapters often do not accept exceptional returns. 1086 // We require that their callers must bang for them. But be careful, because 1087 // some VM calls (such as call site linkage) can use several kilobytes of 1088 // stack. But the stack safety zone should account for that. 1089 // See bugs 4446381, 4468289, 4497237. 1090 if (C->need_stack_bang(framesize)) { 1091 __ generate_stack_overflow_check(framesize); 1092 } 1093 1094 if (Assembler::is_simm13(-framesize)) { 1095 __ save(SP, -framesize, SP); 1096 } else { 1097 __ sethi(-framesize & ~0x3ff, G3); 1098 __ add(G3, -framesize & 0x3ff, G3); 1099 __ save(SP, G3, SP); 1100 } 1101 C->set_frame_complete( __ offset() ); 1102 } 1103 1104 uint MachPrologNode::size(PhaseRegAlloc *ra_) const { 1105 return MachNode::size(ra_); 1106 } 1107 1108 int MachPrologNode::reloc() const { 1109 return 10; // a large enough number 1110 } 1111 1112 //============================================================================= 1113 #ifndef PRODUCT 1114 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { 1115 Compile* C = ra_->C; 1116 1117 if( do_polling() && ra_->C->is_method_compilation() ) { 1118 st->print("SETHI #PollAddr,L0\t! Load Polling address\n\t"); 1119 #ifdef _LP64 1120 st->print("LDX [L0],G0\t!Poll for Safepointing\n\t"); 1121 #else 1122 st->print("LDUW [L0],G0\t!Poll for Safepointing\n\t"); 1123 #endif 1124 } 1125 1126 if( do_polling() ) 1127 st->print("RET\n\t"); 1128 1129 st->print("RESTORE"); 1130 } 1131 #endif 1132 1133 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1134 MacroAssembler _masm(&cbuf); 1135 Compile* C = ra_->C; 1136 1137 __ verify_thread(); 1138 1139 // If this does safepoint polling, then do it here 1140 if( do_polling() && ra_->C->is_method_compilation() ) { 1141 AddressLiteral polling_page(os::get_polling_page()); 1142 __ sethi(polling_page, L0); 1143 __ relocate(relocInfo::poll_return_type); 1144 __ ld_ptr( L0, 0, G0 ); 1145 } 1146 1147 // If this is a return, then stuff the restore in the delay slot 1148 if( do_polling() ) { 1149 __ ret(); 1150 __ delayed()->restore(); 1151 } else { 1152 __ restore(); 1153 } 1154 } 1155 1156 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const { 1157 return MachNode::size(ra_); 1158 } 1159 1160 int MachEpilogNode::reloc() const { 1161 return 16; // a large enough number 1162 } 1163 1164 const Pipeline * MachEpilogNode::pipeline() const { 1165 return MachNode::pipeline_class(); 1166 } 1167 1168 int MachEpilogNode::safepoint_offset() const { 1169 assert( do_polling(), "no return for this epilog node"); 1170 return MacroAssembler::size_of_sethi(os::get_polling_page()); 1171 } 1172 1173 //============================================================================= 1174 1175 // Figure out which register class each belongs in: rc_int, rc_float, rc_stack 1176 enum RC { rc_bad, rc_int, rc_float, rc_stack }; 1177 static enum RC rc_class( OptoReg::Name reg ) { 1178 if( !OptoReg::is_valid(reg) ) return rc_bad; 1179 if (OptoReg::is_stack(reg)) return rc_stack; 1180 VMReg r = OptoReg::as_VMReg(reg); 1181 if (r->is_Register()) return rc_int; 1182 assert(r->is_FloatRegister(), "must be"); 1183 return rc_float; 1184 } 1185 1186 static int impl_helper( const MachNode *mach, CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, bool is_load, int offset, int reg, int opcode, const char *op_str, int size, outputStream* st ) { 1187 if( cbuf ) { 1188 // Better yet would be some mechanism to handle variable-size matches correctly 1189 if (!Assembler::is_simm13(offset + STACK_BIAS)) { 1190 ra_->C->record_method_not_compilable("unable to handle large constant offsets"); 1191 } else { 1192 emit_form3_mem_reg(*cbuf, mach, opcode, -1, R_SP_enc, offset, 0, Matcher::_regEncode[reg]); 1193 } 1194 } 1195 #ifndef PRODUCT 1196 else if( !do_size ) { 1197 if( size != 0 ) st->print("\n\t"); 1198 if( is_load ) st->print("%s [R_SP + #%d],R_%s\t! spill",op_str,offset,OptoReg::regname(reg)); 1199 else st->print("%s R_%s,[R_SP + #%d]\t! spill",op_str,OptoReg::regname(reg),offset); 1200 } 1201 #endif 1202 return size+4; 1203 } 1204 1205 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int op1, int op2, const char *op_str, int size, outputStream* st ) { 1206 if( cbuf ) emit3( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst], op1, 0, op2, Matcher::_regEncode[src] ); 1207 #ifndef PRODUCT 1208 else if( !do_size ) { 1209 if( size != 0 ) st->print("\n\t"); 1210 st->print("%s R_%s,R_%s\t! spill",op_str,OptoReg::regname(src),OptoReg::regname(dst)); 1211 } 1212 #endif 1213 return size+4; 1214 } 1215 1216 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf, 1217 PhaseRegAlloc *ra_, 1218 bool do_size, 1219 outputStream* st ) const { 1220 // Get registers to move 1221 OptoReg::Name src_second = ra_->get_reg_second(in(1)); 1222 OptoReg::Name src_first = ra_->get_reg_first(in(1)); 1223 OptoReg::Name dst_second = ra_->get_reg_second(this ); 1224 OptoReg::Name dst_first = ra_->get_reg_first(this ); 1225 1226 enum RC src_second_rc = rc_class(src_second); 1227 enum RC src_first_rc = rc_class(src_first); 1228 enum RC dst_second_rc = rc_class(dst_second); 1229 enum RC dst_first_rc = rc_class(dst_first); 1230 1231 assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" ); 1232 1233 // Generate spill code! 1234 int size = 0; 1235 1236 if( src_first == dst_first && src_second == dst_second ) 1237 return size; // Self copy, no move 1238 1239 // -------------------------------------- 1240 // Check for mem-mem move. Load into unused float registers and fall into 1241 // the float-store case. 1242 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) { 1243 int offset = ra_->reg2offset(src_first); 1244 // Further check for aligned-adjacent pair, so we can use a double load 1245 if( (src_first&1)==0 && src_first+1 == src_second ) { 1246 src_second = OptoReg::Name(R_F31_num); 1247 src_second_rc = rc_float; 1248 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::lddf_op3,"LDDF",size, st); 1249 } else { 1250 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::ldf_op3 ,"LDF ",size, st); 1251 } 1252 src_first = OptoReg::Name(R_F30_num); 1253 src_first_rc = rc_float; 1254 } 1255 1256 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) { 1257 int offset = ra_->reg2offset(src_second); 1258 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F31_num,Assembler::ldf_op3,"LDF ",size, st); 1259 src_second = OptoReg::Name(R_F31_num); 1260 src_second_rc = rc_float; 1261 } 1262 1263 // -------------------------------------- 1264 // Check for float->int copy; requires a trip through memory 1265 if( src_first_rc == rc_float && dst_first_rc == rc_int ) { 1266 int offset = frame::register_save_words*wordSize; 1267 if( cbuf ) { 1268 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::sub_op3, R_SP_enc, 16 ); 1269 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st); 1270 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st); 1271 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::add_op3, R_SP_enc, 16 ); 1272 } 1273 #ifndef PRODUCT 1274 else if( !do_size ) { 1275 if( size != 0 ) st->print("\n\t"); 1276 st->print( "SUB R_SP,16,R_SP\n"); 1277 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st); 1278 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st); 1279 st->print("\tADD R_SP,16,R_SP\n"); 1280 } 1281 #endif 1282 size += 16; 1283 } 1284 1285 // -------------------------------------- 1286 // In the 32-bit 1-reg-longs build ONLY, I see mis-aligned long destinations. 1287 // In such cases, I have to do the big-endian swap. For aligned targets, the 1288 // hardware does the flop for me. Doubles are always aligned, so no problem 1289 // there. Misaligned sources only come from native-long-returns (handled 1290 // special below). 1291 #ifndef _LP64 1292 if( src_first_rc == rc_int && // source is already big-endian 1293 src_second_rc != rc_bad && // 64-bit move 1294 ((dst_first&1)!=0 || dst_second != dst_first+1) ) { // misaligned dst 1295 assert( (src_first&1)==0 && src_second == src_first+1, "source must be aligned" ); 1296 // Do the big-endian flop. 1297 OptoReg::Name tmp = dst_first ; dst_first = dst_second ; dst_second = tmp ; 1298 enum RC tmp_rc = dst_first_rc; dst_first_rc = dst_second_rc; dst_second_rc = tmp_rc; 1299 } 1300 #endif 1301 1302 // -------------------------------------- 1303 // Check for integer reg-reg copy 1304 if( src_first_rc == rc_int && dst_first_rc == rc_int ) { 1305 #ifndef _LP64 1306 if( src_first == R_O0_num && src_second == R_O1_num ) { // Check for the evil O0/O1 native long-return case 1307 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value 1308 // as stored in memory. On a big-endian machine like SPARC, this means that the _second 1309 // operand contains the least significant word of the 64-bit value and vice versa. 1310 OptoReg::Name tmp = OptoReg::Name(R_O7_num); 1311 assert( (dst_first&1)==0 && dst_second == dst_first+1, "return a native O0/O1 long to an aligned-adjacent 64-bit reg" ); 1312 // Shift O0 left in-place, zero-extend O1, then OR them into the dst 1313 if( cbuf ) { 1314 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tmp], Assembler::sllx_op3, Matcher::_regEncode[src_first], 0x1020 ); 1315 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[src_second], Assembler::srl_op3, Matcher::_regEncode[src_second], 0x0000 ); 1316 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler:: or_op3, Matcher::_regEncode[tmp], 0, Matcher::_regEncode[src_second] ); 1317 #ifndef PRODUCT 1318 } else if( !do_size ) { 1319 if( size != 0 ) st->print("\n\t"); 1320 st->print("SLLX R_%s,32,R_%s\t! Move O0-first to O7-high\n\t", OptoReg::regname(src_first), OptoReg::regname(tmp)); 1321 st->print("SRL R_%s, 0,R_%s\t! Zero-extend O1\n\t", OptoReg::regname(src_second), OptoReg::regname(src_second)); 1322 st->print("OR R_%s,R_%s,R_%s\t! spill",OptoReg::regname(tmp), OptoReg::regname(src_second), OptoReg::regname(dst_first)); 1323 #endif 1324 } 1325 return size+12; 1326 } 1327 else if( dst_first == R_I0_num && dst_second == R_I1_num ) { 1328 // returning a long value in I0/I1 1329 // a SpillCopy must be able to target a return instruction's reg_class 1330 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value 1331 // as stored in memory. On a big-endian machine like SPARC, this means that the _second 1332 // operand contains the least significant word of the 64-bit value and vice versa. 1333 OptoReg::Name tdest = dst_first; 1334 1335 if (src_first == dst_first) { 1336 tdest = OptoReg::Name(R_O7_num); 1337 size += 4; 1338 } 1339 1340 if( cbuf ) { 1341 assert( (src_first&1) == 0 && (src_first+1) == src_second, "return value was in an aligned-adjacent 64-bit reg"); 1342 // Shift value in upper 32-bits of src to lower 32-bits of I0; move lower 32-bits to I1 1343 // ShrL_reg_imm6 1344 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tdest], Assembler::srlx_op3, Matcher::_regEncode[src_second], 32 | 0x1000 ); 1345 // ShrR_reg_imm6 src, 0, dst 1346 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srl_op3, Matcher::_regEncode[src_first], 0x0000 ); 1347 if (tdest != dst_first) { 1348 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler::or_op3, 0/*G0*/, 0/*op2*/, Matcher::_regEncode[tdest] ); 1349 } 1350 } 1351 #ifndef PRODUCT 1352 else if( !do_size ) { 1353 if( size != 0 ) st->print("\n\t"); // %%%%% !!!!! 1354 st->print("SRLX R_%s,32,R_%s\t! Extract MSW\n\t",OptoReg::regname(src_second),OptoReg::regname(tdest)); 1355 st->print("SRL R_%s, 0,R_%s\t! Extract LSW\n\t",OptoReg::regname(src_first),OptoReg::regname(dst_second)); 1356 if (tdest != dst_first) { 1357 st->print("MOV R_%s,R_%s\t! spill\n\t", OptoReg::regname(tdest), OptoReg::regname(dst_first)); 1358 } 1359 } 1360 #endif // PRODUCT 1361 return size+8; 1362 } 1363 #endif // !_LP64 1364 // Else normal reg-reg copy 1365 assert( src_second != dst_first, "smashed second before evacuating it" ); 1366 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::or_op3,0,"MOV ",size, st); 1367 assert( (src_first&1) == 0 && (dst_first&1) == 0, "never move second-halves of int registers" ); 1368 // This moves an aligned adjacent pair. 1369 // See if we are done. 1370 if( src_first+1 == src_second && dst_first+1 == dst_second ) 1371 return size; 1372 } 1373 1374 // Check for integer store 1375 if( src_first_rc == rc_int && dst_first_rc == rc_stack ) { 1376 int offset = ra_->reg2offset(dst_first); 1377 // Further check for aligned-adjacent pair, so we can use a double store 1378 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) 1379 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stx_op3,"STX ",size, st); 1380 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stw_op3,"STW ",size, st); 1381 } 1382 1383 // Check for integer load 1384 if( dst_first_rc == rc_int && src_first_rc == rc_stack ) { 1385 int offset = ra_->reg2offset(src_first); 1386 // Further check for aligned-adjacent pair, so we can use a double load 1387 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) 1388 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldx_op3 ,"LDX ",size, st); 1389 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st); 1390 } 1391 1392 // Check for float reg-reg copy 1393 if( src_first_rc == rc_float && dst_first_rc == rc_float ) { 1394 // Further check for aligned-adjacent pair, so we can use a double move 1395 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) 1396 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovd_opf,"FMOVD",size, st); 1397 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovs_opf,"FMOVS",size, st); 1398 } 1399 1400 // Check for float store 1401 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) { 1402 int offset = ra_->reg2offset(dst_first); 1403 // Further check for aligned-adjacent pair, so we can use a double store 1404 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) 1405 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stdf_op3,"STDF",size, st); 1406 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st); 1407 } 1408 1409 // Check for float load 1410 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) { 1411 int offset = ra_->reg2offset(src_first); 1412 // Further check for aligned-adjacent pair, so we can use a double load 1413 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) 1414 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lddf_op3,"LDDF",size, st); 1415 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldf_op3 ,"LDF ",size, st); 1416 } 1417 1418 // -------------------------------------------------------------------- 1419 // Check for hi bits still needing moving. Only happens for misaligned 1420 // arguments to native calls. 1421 if( src_second == dst_second ) 1422 return size; // Self copy; no move 1423 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" ); 1424 1425 #ifndef _LP64 1426 // In the LP64 build, all registers can be moved as aligned/adjacent 1427 // pairs, so there's never any need to move the high bits separately. 1428 // The 32-bit builds have to deal with the 32-bit ABI which can force 1429 // all sorts of silly alignment problems. 1430 1431 // Check for integer reg-reg copy. Hi bits are stuck up in the top 1432 // 32-bits of a 64-bit register, but are needed in low bits of another 1433 // register (else it's a hi-bits-to-hi-bits copy which should have 1434 // happened already as part of a 64-bit move) 1435 if( src_second_rc == rc_int && dst_second_rc == rc_int ) { 1436 assert( (src_second&1)==1, "its the evil O0/O1 native return case" ); 1437 assert( (dst_second&1)==0, "should have moved with 1 64-bit move" ); 1438 // Shift src_second down to dst_second's low bits. 1439 if( cbuf ) { 1440 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 ); 1441 #ifndef PRODUCT 1442 } else if( !do_size ) { 1443 if( size != 0 ) st->print("\n\t"); 1444 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(dst_second)); 1445 #endif 1446 } 1447 return size+4; 1448 } 1449 1450 // Check for high word integer store. Must down-shift the hi bits 1451 // into a temp register, then fall into the case of storing int bits. 1452 if( src_second_rc == rc_int && dst_second_rc == rc_stack && (src_second&1)==1 ) { 1453 // Shift src_second down to dst_second's low bits. 1454 if( cbuf ) { 1455 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[R_O7_num], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 ); 1456 #ifndef PRODUCT 1457 } else if( !do_size ) { 1458 if( size != 0 ) st->print("\n\t"); 1459 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(R_O7_num)); 1460 #endif 1461 } 1462 size+=4; 1463 src_second = OptoReg::Name(R_O7_num); // Not R_O7H_num! 1464 } 1465 1466 // Check for high word integer load 1467 if( dst_second_rc == rc_int && src_second_rc == rc_stack ) 1468 return impl_helper(this,cbuf,ra_,do_size,true ,ra_->reg2offset(src_second),dst_second,Assembler::lduw_op3,"LDUW",size, st); 1469 1470 // Check for high word integer store 1471 if( src_second_rc == rc_int && dst_second_rc == rc_stack ) 1472 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stw_op3 ,"STW ",size, st); 1473 1474 // Check for high word float store 1475 if( src_second_rc == rc_float && dst_second_rc == rc_stack ) 1476 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stf_op3 ,"STF ",size, st); 1477 1478 #endif // !_LP64 1479 1480 Unimplemented(); 1481 } 1482 1483 #ifndef PRODUCT 1484 void MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { 1485 implementation( NULL, ra_, false, st ); 1486 } 1487 #endif 1488 1489 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1490 implementation( &cbuf, ra_, false, NULL ); 1491 } 1492 1493 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const { 1494 return implementation( NULL, ra_, true, NULL ); 1495 } 1496 1497 //============================================================================= 1498 #ifndef PRODUCT 1499 void MachNopNode::format( PhaseRegAlloc *, outputStream *st ) const { 1500 st->print("NOP \t# %d bytes pad for loops and calls", 4 * _count); 1501 } 1502 #endif 1503 1504 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc * ) const { 1505 MacroAssembler _masm(&cbuf); 1506 for(int i = 0; i < _count; i += 1) { 1507 __ nop(); 1508 } 1509 } 1510 1511 uint MachNopNode::size(PhaseRegAlloc *ra_) const { 1512 return 4 * _count; 1513 } 1514 1515 1516 //============================================================================= 1517 #ifndef PRODUCT 1518 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { 1519 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); 1520 int reg = ra_->get_reg_first(this); 1521 st->print("LEA [R_SP+#%d+BIAS],%s",offset,Matcher::regName[reg]); 1522 } 1523 #endif 1524 1525 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1526 MacroAssembler _masm(&cbuf); 1527 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()) + STACK_BIAS; 1528 int reg = ra_->get_encode(this); 1529 1530 if (Assembler::is_simm13(offset)) { 1531 __ add(SP, offset, reg_to_register_object(reg)); 1532 } else { 1533 __ set(offset, O7); 1534 __ add(SP, O7, reg_to_register_object(reg)); 1535 } 1536 } 1537 1538 uint BoxLockNode::size(PhaseRegAlloc *ra_) const { 1539 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_) 1540 assert(ra_ == ra_->C->regalloc(), "sanity"); 1541 return ra_->C->scratch_emit_size(this); 1542 } 1543 1544 //============================================================================= 1545 1546 // emit call stub, compiled java to interpretor 1547 void emit_java_to_interp(CodeBuffer &cbuf ) { 1548 1549 // Stub is fixed up when the corresponding call is converted from calling 1550 // compiled code to calling interpreted code. 1551 // set (empty), G5 1552 // jmp -1 1553 1554 address mark = cbuf.inst_mark(); // get mark within main instrs section 1555 1556 MacroAssembler _masm(&cbuf); 1557 1558 address base = 1559 __ start_a_stub(Compile::MAX_stubs_size); 1560 if (base == NULL) return; // CodeBuffer::expand failed 1561 1562 // static stub relocation stores the instruction address of the call 1563 __ relocate(static_stub_Relocation::spec(mark)); 1564 1565 __ set_oop(NULL, reg_to_register_object(Matcher::inline_cache_reg_encode())); 1566 1567 __ set_inst_mark(); 1568 AddressLiteral addrlit(-1); 1569 __ JUMP(addrlit, G3, 0); 1570 1571 __ delayed()->nop(); 1572 1573 // Update current stubs pointer and restore code_end. 1574 __ end_a_stub(); 1575 } 1576 1577 // size of call stub, compiled java to interpretor 1578 uint size_java_to_interp() { 1579 // This doesn't need to be accurate but it must be larger or equal to 1580 // the real size of the stub. 1581 return (NativeMovConstReg::instruction_size + // sethi/setlo; 1582 NativeJump::instruction_size + // sethi; jmp; nop 1583 (TraceJumps ? 20 * BytesPerInstWord : 0) ); 1584 } 1585 // relocation entries for call stub, compiled java to interpretor 1586 uint reloc_java_to_interp() { 1587 return 10; // 4 in emit_java_to_interp + 1 in Java_Static_Call 1588 } 1589 1590 1591 //============================================================================= 1592 #ifndef PRODUCT 1593 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { 1594 st->print_cr("\nUEP:"); 1595 #ifdef _LP64 1596 if (UseCompressedOops) { 1597 assert(Universe::heap() != NULL, "java heap should be initialized"); 1598 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check - compressed klass"); 1599 st->print_cr("\tSLL R_G5,3,R_G5"); 1600 if (Universe::narrow_oop_base() != NULL) 1601 st->print_cr("\tADD R_G5,R_G6_heap_base,R_G5"); 1602 } else { 1603 st->print_cr("\tLDX [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check"); 1604 } 1605 st->print_cr("\tCMP R_G5,R_G3" ); 1606 st->print ("\tTne xcc,R_G0+ST_RESERVED_FOR_USER_0+2"); 1607 #else // _LP64 1608 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check"); 1609 st->print_cr("\tCMP R_G5,R_G3" ); 1610 st->print ("\tTne icc,R_G0+ST_RESERVED_FOR_USER_0+2"); 1611 #endif // _LP64 1612 } 1613 #endif 1614 1615 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1616 MacroAssembler _masm(&cbuf); 1617 Label L; 1618 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode()); 1619 Register temp_reg = G3; 1620 assert( G5_ic_reg != temp_reg, "conflicting registers" ); 1621 1622 // Load klass from receiver 1623 __ load_klass(O0, temp_reg); 1624 // Compare against expected klass 1625 __ cmp(temp_reg, G5_ic_reg); 1626 // Branch to miss code, checks xcc or icc depending 1627 __ trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2); 1628 } 1629 1630 uint MachUEPNode::size(PhaseRegAlloc *ra_) const { 1631 return MachNode::size(ra_); 1632 } 1633 1634 1635 //============================================================================= 1636 1637 uint size_exception_handler() { 1638 if (TraceJumps) { 1639 return (400); // just a guess 1640 } 1641 return ( NativeJump::instruction_size ); // sethi;jmp;nop 1642 } 1643 1644 uint size_deopt_handler() { 1645 if (TraceJumps) { 1646 return (400); // just a guess 1647 } 1648 return ( 4+ NativeJump::instruction_size ); // save;sethi;jmp;restore 1649 } 1650 1651 // Emit exception handler code. 1652 int emit_exception_handler(CodeBuffer& cbuf) { 1653 Register temp_reg = G3; 1654 AddressLiteral exception_blob(OptoRuntime::exception_blob()->instructions_begin()); 1655 MacroAssembler _masm(&cbuf); 1656 1657 address base = 1658 __ start_a_stub(size_exception_handler()); 1659 if (base == NULL) return 0; // CodeBuffer::expand failed 1660 1661 int offset = __ offset(); 1662 1663 __ JUMP(exception_blob, temp_reg, 0); // sethi;jmp 1664 __ delayed()->nop(); 1665 1666 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow"); 1667 1668 __ end_a_stub(); 1669 1670 return offset; 1671 } 1672 1673 int emit_deopt_handler(CodeBuffer& cbuf) { 1674 // Can't use any of the current frame's registers as we may have deopted 1675 // at a poll and everything (including G3) can be live. 1676 Register temp_reg = L0; 1677 AddressLiteral deopt_blob(SharedRuntime::deopt_blob()->unpack()); 1678 MacroAssembler _masm(&cbuf); 1679 1680 address base = 1681 __ start_a_stub(size_deopt_handler()); 1682 if (base == NULL) return 0; // CodeBuffer::expand failed 1683 1684 int offset = __ offset(); 1685 __ save_frame(0); 1686 __ JUMP(deopt_blob, temp_reg, 0); // sethi;jmp 1687 __ delayed()->restore(); 1688 1689 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow"); 1690 1691 __ end_a_stub(); 1692 return offset; 1693 1694 } 1695 1696 // Given a register encoding, produce a Integer Register object 1697 static Register reg_to_register_object(int register_encoding) { 1698 assert(L5->encoding() == R_L5_enc && G1->encoding() == R_G1_enc, "right coding"); 1699 return as_Register(register_encoding); 1700 } 1701 1702 // Given a register encoding, produce a single-precision Float Register object 1703 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding) { 1704 assert(F5->encoding(FloatRegisterImpl::S) == R_F5_enc && F12->encoding(FloatRegisterImpl::S) == R_F12_enc, "right coding"); 1705 return as_SingleFloatRegister(register_encoding); 1706 } 1707 1708 // Given a register encoding, produce a double-precision Float Register object 1709 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding) { 1710 assert(F4->encoding(FloatRegisterImpl::D) == R_F4_enc, "right coding"); 1711 assert(F32->encoding(FloatRegisterImpl::D) == R_D32_enc, "right coding"); 1712 return as_DoubleFloatRegister(register_encoding); 1713 } 1714 1715 const bool Matcher::match_rule_supported(int opcode) { 1716 if (!has_match_rule(opcode)) 1717 return false; 1718 1719 switch (opcode) { 1720 case Op_CountLeadingZerosI: 1721 case Op_CountLeadingZerosL: 1722 case Op_CountTrailingZerosI: 1723 case Op_CountTrailingZerosL: 1724 if (!UsePopCountInstruction) 1725 return false; 1726 break; 1727 } 1728 1729 return true; // Per default match rules are supported. 1730 } 1731 1732 int Matcher::regnum_to_fpu_offset(int regnum) { 1733 return regnum - 32; // The FP registers are in the second chunk 1734 } 1735 1736 #ifdef ASSERT 1737 address last_rethrow = NULL; // debugging aid for Rethrow encoding 1738 #endif 1739 1740 // Vector width in bytes 1741 const uint Matcher::vector_width_in_bytes(void) { 1742 return 8; 1743 } 1744 1745 // Vector ideal reg 1746 const uint Matcher::vector_ideal_reg(void) { 1747 return Op_RegD; 1748 } 1749 1750 // USII supports fxtof through the whole range of number, USIII doesn't 1751 const bool Matcher::convL2FSupported(void) { 1752 return VM_Version::has_fast_fxtof(); 1753 } 1754 1755 // Is this branch offset short enough that a short branch can be used? 1756 // 1757 // NOTE: If the platform does not provide any short branch variants, then 1758 // this method should return false for offset 0. 1759 bool Matcher::is_short_branch_offset(int rule, int offset) { 1760 return false; 1761 } 1762 1763 const bool Matcher::isSimpleConstant64(jlong value) { 1764 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?. 1765 // Depends on optimizations in MacroAssembler::setx. 1766 int hi = (int)(value >> 32); 1767 int lo = (int)(value & ~0); 1768 return (hi == 0) || (hi == -1) || (lo == 0); 1769 } 1770 1771 // No scaling for the parameter the ClearArray node. 1772 const bool Matcher::init_array_count_is_in_bytes = true; 1773 1774 // Threshold size for cleararray. 1775 const int Matcher::init_array_short_size = 8 * BytesPerLong; 1776 1777 // Should the Matcher clone shifts on addressing modes, expecting them to 1778 // be subsumed into complex addressing expressions or compute them into 1779 // registers? True for Intel but false for most RISCs 1780 const bool Matcher::clone_shift_expressions = false; 1781 1782 // Is it better to copy float constants, or load them directly from memory? 1783 // Intel can load a float constant from a direct address, requiring no 1784 // extra registers. Most RISCs will have to materialize an address into a 1785 // register first, so they would do better to copy the constant from stack. 1786 const bool Matcher::rematerialize_float_constants = false; 1787 1788 // If CPU can load and store mis-aligned doubles directly then no fixup is 1789 // needed. Else we split the double into 2 integer pieces and move it 1790 // piece-by-piece. Only happens when passing doubles into C code as the 1791 // Java calling convention forces doubles to be aligned. 1792 #ifdef _LP64 1793 const bool Matcher::misaligned_doubles_ok = true; 1794 #else 1795 const bool Matcher::misaligned_doubles_ok = false; 1796 #endif 1797 1798 // No-op on SPARC. 1799 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) { 1800 } 1801 1802 // Advertise here if the CPU requires explicit rounding operations 1803 // to implement the UseStrictFP mode. 1804 const bool Matcher::strict_fp_requires_explicit_rounding = false; 1805 1806 // Do floats take an entire double register or just half? 1807 const bool Matcher::float_in_double = false; 1808 1809 // Do ints take an entire long register or just half? 1810 // Note that we if-def off of _LP64. 1811 // The relevant question is how the int is callee-saved. In _LP64 1812 // the whole long is written but de-opt'ing will have to extract 1813 // the relevant 32 bits, in not-_LP64 only the low 32 bits is written. 1814 #ifdef _LP64 1815 const bool Matcher::int_in_long = true; 1816 #else 1817 const bool Matcher::int_in_long = false; 1818 #endif 1819 1820 // Return whether or not this register is ever used as an argument. This 1821 // function is used on startup to build the trampoline stubs in generateOptoStub. 1822 // Registers not mentioned will be killed by the VM call in the trampoline, and 1823 // arguments in those registers not be available to the callee. 1824 bool Matcher::can_be_java_arg( int reg ) { 1825 // Standard sparc 6 args in registers 1826 if( reg == R_I0_num || 1827 reg == R_I1_num || 1828 reg == R_I2_num || 1829 reg == R_I3_num || 1830 reg == R_I4_num || 1831 reg == R_I5_num ) return true; 1832 #ifdef _LP64 1833 // 64-bit builds can pass 64-bit pointers and longs in 1834 // the high I registers 1835 if( reg == R_I0H_num || 1836 reg == R_I1H_num || 1837 reg == R_I2H_num || 1838 reg == R_I3H_num || 1839 reg == R_I4H_num || 1840 reg == R_I5H_num ) return true; 1841 1842 if ((UseCompressedOops) && (reg == R_G6_num || reg == R_G6H_num)) { 1843 return true; 1844 } 1845 1846 #else 1847 // 32-bit builds with longs-in-one-entry pass longs in G1 & G4. 1848 // Longs cannot be passed in O regs, because O regs become I regs 1849 // after a 'save' and I regs get their high bits chopped off on 1850 // interrupt. 1851 if( reg == R_G1H_num || reg == R_G1_num ) return true; 1852 if( reg == R_G4H_num || reg == R_G4_num ) return true; 1853 #endif 1854 // A few float args in registers 1855 if( reg >= R_F0_num && reg <= R_F7_num ) return true; 1856 1857 return false; 1858 } 1859 1860 bool Matcher::is_spillable_arg( int reg ) { 1861 return can_be_java_arg(reg); 1862 } 1863 1864 // Register for DIVI projection of divmodI 1865 RegMask Matcher::divI_proj_mask() { 1866 ShouldNotReachHere(); 1867 return RegMask(); 1868 } 1869 1870 // Register for MODI projection of divmodI 1871 RegMask Matcher::modI_proj_mask() { 1872 ShouldNotReachHere(); 1873 return RegMask(); 1874 } 1875 1876 // Register for DIVL projection of divmodL 1877 RegMask Matcher::divL_proj_mask() { 1878 ShouldNotReachHere(); 1879 return RegMask(); 1880 } 1881 1882 // Register for MODL projection of divmodL 1883 RegMask Matcher::modL_proj_mask() { 1884 ShouldNotReachHere(); 1885 return RegMask(); 1886 } 1887 1888 %} 1889 1890 1891 // The intptr_t operand types, defined by textual substitution. 1892 // (Cf. opto/type.hpp. This lets us avoid many, many other ifdefs.) 1893 #ifdef _LP64 1894 #define immX immL 1895 #define immX13 immL13 1896 #define immX13m7 immL13m7 1897 #define iRegX iRegL 1898 #define g1RegX g1RegL 1899 #else 1900 #define immX immI 1901 #define immX13 immI13 1902 #define immX13m7 immI13m7 1903 #define iRegX iRegI 1904 #define g1RegX g1RegI 1905 #endif 1906 1907 //----------ENCODING BLOCK----------------------------------------------------- 1908 // This block specifies the encoding classes used by the compiler to output 1909 // byte streams. Encoding classes are parameterized macros used by 1910 // Machine Instruction Nodes in order to generate the bit encoding of the 1911 // instruction. Operands specify their base encoding interface with the 1912 // interface keyword. There are currently supported four interfaces, 1913 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an 1914 // operand to generate a function which returns its register number when 1915 // queried. CONST_INTER causes an operand to generate a function which 1916 // returns the value of the constant when queried. MEMORY_INTER causes an 1917 // operand to generate four functions which return the Base Register, the 1918 // Index Register, the Scale Value, and the Offset Value of the operand when 1919 // queried. COND_INTER causes an operand to generate six functions which 1920 // return the encoding code (ie - encoding bits for the instruction) 1921 // associated with each basic boolean condition for a conditional instruction. 1922 // 1923 // Instructions specify two basic values for encoding. Again, a function 1924 // is available to check if the constant displacement is an oop. They use the 1925 // ins_encode keyword to specify their encoding classes (which must be 1926 // a sequence of enc_class names, and their parameters, specified in 1927 // the encoding block), and they use the 1928 // opcode keyword to specify, in order, their primary, secondary, and 1929 // tertiary opcode. Only the opcode sections which a particular instruction 1930 // needs for encoding need to be specified. 1931 encode %{ 1932 enc_class enc_untested %{ 1933 #ifdef ASSERT 1934 MacroAssembler _masm(&cbuf); 1935 __ untested("encoding"); 1936 #endif 1937 %} 1938 1939 enc_class form3_mem_reg( memory mem, iRegI dst ) %{ 1940 emit_form3_mem_reg(cbuf, this, $primary, $tertiary, 1941 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg); 1942 %} 1943 1944 enc_class simple_form3_mem_reg( memory mem, iRegI dst ) %{ 1945 emit_form3_mem_reg(cbuf, this, $primary, -1, 1946 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg); 1947 %} 1948 1949 enc_class form3_mem_reg_little( memory mem, iRegI dst) %{ 1950 emit_form3_mem_reg_asi(cbuf, this, $primary, -1, 1951 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg, Assembler::ASI_PRIMARY_LITTLE); 1952 %} 1953 1954 enc_class form3_mem_prefetch_read( memory mem ) %{ 1955 emit_form3_mem_reg(cbuf, this, $primary, -1, 1956 $mem$$base, $mem$$disp, $mem$$index, 0/*prefetch function many-reads*/); 1957 %} 1958 1959 enc_class form3_mem_prefetch_write( memory mem ) %{ 1960 emit_form3_mem_reg(cbuf, this, $primary, -1, 1961 $mem$$base, $mem$$disp, $mem$$index, 2/*prefetch function many-writes*/); 1962 %} 1963 1964 enc_class form3_mem_reg_long_unaligned_marshal( memory mem, iRegL reg ) %{ 1965 assert( Assembler::is_simm13($mem$$disp ), "need disp and disp+4" ); 1966 assert( Assembler::is_simm13($mem$$disp+4), "need disp and disp+4" ); 1967 guarantee($mem$$index == R_G0_enc, "double index?"); 1968 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, R_O7_enc ); 1969 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg ); 1970 emit3_simm13( cbuf, Assembler::arith_op, $reg$$reg, Assembler::sllx_op3, $reg$$reg, 0x1020 ); 1971 emit3( cbuf, Assembler::arith_op, $reg$$reg, Assembler::or_op3, $reg$$reg, 0, R_O7_enc ); 1972 %} 1973 1974 enc_class form3_mem_reg_double_unaligned( memory mem, RegD_low reg ) %{ 1975 assert( Assembler::is_simm13($mem$$disp ), "need disp and disp+4" ); 1976 assert( Assembler::is_simm13($mem$$disp+4), "need disp and disp+4" ); 1977 guarantee($mem$$index == R_G0_enc, "double index?"); 1978 // Load long with 2 instructions 1979 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg+0 ); 1980 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, $reg$$reg+1 ); 1981 %} 1982 1983 //%%% form3_mem_plus_4_reg is a hack--get rid of it 1984 enc_class form3_mem_plus_4_reg( memory mem, iRegI dst ) %{ 1985 guarantee($mem$$disp, "cannot offset a reg-reg operand by 4"); 1986 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp + 4, $mem$$index, $dst$$reg); 1987 %} 1988 1989 enc_class form3_g0_rs2_rd_move( iRegI rs2, iRegI rd ) %{ 1990 // Encode a reg-reg copy. If it is useless, then empty encoding. 1991 if( $rs2$$reg != $rd$$reg ) 1992 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, $rs2$$reg ); 1993 %} 1994 1995 // Target lo half of long 1996 enc_class form3_g0_rs2_rd_move_lo( iRegI rs2, iRegL rd ) %{ 1997 // Encode a reg-reg copy. If it is useless, then empty encoding. 1998 if( $rs2$$reg != LONG_LO_REG($rd$$reg) ) 1999 emit3( cbuf, Assembler::arith_op, LONG_LO_REG($rd$$reg), Assembler::or_op3, 0, 0, $rs2$$reg ); 2000 %} 2001 2002 // Source lo half of long 2003 enc_class form3_g0_rs2_rd_move_lo2( iRegL rs2, iRegI rd ) %{ 2004 // Encode a reg-reg copy. If it is useless, then empty encoding. 2005 if( LONG_LO_REG($rs2$$reg) != $rd$$reg ) 2006 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_LO_REG($rs2$$reg) ); 2007 %} 2008 2009 // Target hi half of long 2010 enc_class form3_rs1_rd_copysign_hi( iRegI rs1, iRegL rd ) %{ 2011 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 31 ); 2012 %} 2013 2014 // Source lo half of long, and leave it sign extended. 2015 enc_class form3_rs1_rd_signextend_lo1( iRegL rs1, iRegI rd ) %{ 2016 // Sign extend low half 2017 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 0, 0 ); 2018 %} 2019 2020 // Source hi half of long, and leave it sign extended. 2021 enc_class form3_rs1_rd_copy_hi1( iRegL rs1, iRegI rd ) %{ 2022 // Shift high half to low half 2023 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::srlx_op3, $rs1$$reg, 32 ); 2024 %} 2025 2026 // Source hi half of long 2027 enc_class form3_g0_rs2_rd_move_hi2( iRegL rs2, iRegI rd ) %{ 2028 // Encode a reg-reg copy. If it is useless, then empty encoding. 2029 if( LONG_HI_REG($rs2$$reg) != $rd$$reg ) 2030 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_HI_REG($rs2$$reg) ); 2031 %} 2032 2033 enc_class form3_rs1_rs2_rd( iRegI rs1, iRegI rs2, iRegI rd ) %{ 2034 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0, $rs2$$reg ); 2035 %} 2036 2037 enc_class enc_to_bool( iRegI src, iRegI dst ) %{ 2038 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, 0, 0, $src$$reg ); 2039 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::addc_op3 , 0, 0 ); 2040 %} 2041 2042 enc_class enc_ltmask( iRegI p, iRegI q, iRegI dst ) %{ 2043 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $p$$reg, 0, $q$$reg ); 2044 // clear if nothing else is happening 2045 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 0 ); 2046 // blt,a,pn done 2047 emit2_19 ( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less, Assembler::bp_op2, Assembler::icc, 0/*predict not taken*/, 2 ); 2048 // mov dst,-1 in delay slot 2049 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 ); 2050 %} 2051 2052 enc_class form3_rs1_imm5_rd( iRegI rs1, immU5 imm5, iRegI rd ) %{ 2053 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $imm5$$constant & 0x1F ); 2054 %} 2055 2056 enc_class form3_sd_rs1_imm6_rd( iRegL rs1, immU6 imm6, iRegL rd ) %{ 2057 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, ($imm6$$constant & 0x3F) | 0x1000 ); 2058 %} 2059 2060 enc_class form3_sd_rs1_rs2_rd( iRegL rs1, iRegI rs2, iRegL rd ) %{ 2061 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0x80, $rs2$$reg ); 2062 %} 2063 2064 enc_class form3_rs1_simm13_rd( iRegI rs1, immI13 simm13, iRegI rd ) %{ 2065 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $simm13$$constant ); 2066 %} 2067 2068 enc_class move_return_pc_to_o1() %{ 2069 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::add_op3, R_O7_enc, frame::pc_return_offset ); 2070 %} 2071 2072 #ifdef _LP64 2073 /* %%% merge with enc_to_bool */ 2074 enc_class enc_convP2B( iRegI dst, iRegP src ) %{ 2075 MacroAssembler _masm(&cbuf); 2076 2077 Register src_reg = reg_to_register_object($src$$reg); 2078 Register dst_reg = reg_to_register_object($dst$$reg); 2079 __ movr(Assembler::rc_nz, src_reg, 1, dst_reg); 2080 %} 2081 #endif 2082 2083 enc_class enc_cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp ) %{ 2084 // (Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q))) 2085 MacroAssembler _masm(&cbuf); 2086 2087 Register p_reg = reg_to_register_object($p$$reg); 2088 Register q_reg = reg_to_register_object($q$$reg); 2089 Register y_reg = reg_to_register_object($y$$reg); 2090 Register tmp_reg = reg_to_register_object($tmp$$reg); 2091 2092 __ subcc( p_reg, q_reg, p_reg ); 2093 __ add ( p_reg, y_reg, tmp_reg ); 2094 __ movcc( Assembler::less, false, Assembler::icc, tmp_reg, p_reg ); 2095 %} 2096 2097 enc_class form_d2i_helper(regD src, regF dst) %{ 2098 // fcmp %fcc0,$src,$src 2099 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg ); 2100 // branch %fcc0 not-nan, predict taken 2101 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); 2102 // fdtoi $src,$dst 2103 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtoi_opf, $src$$reg ); 2104 // fitos $dst,$dst (if nan) 2105 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg ); 2106 // clear $dst (if nan) 2107 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg ); 2108 // carry on here... 2109 %} 2110 2111 enc_class form_d2l_helper(regD src, regD dst) %{ 2112 // fcmp %fcc0,$src,$src check for NAN 2113 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg ); 2114 // branch %fcc0 not-nan, predict taken 2115 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); 2116 // fdtox $src,$dst convert in delay slot 2117 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtox_opf, $src$$reg ); 2118 // fxtod $dst,$dst (if nan) 2119 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg ); 2120 // clear $dst (if nan) 2121 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg ); 2122 // carry on here... 2123 %} 2124 2125 enc_class form_f2i_helper(regF src, regF dst) %{ 2126 // fcmps %fcc0,$src,$src 2127 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg ); 2128 // branch %fcc0 not-nan, predict taken 2129 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); 2130 // fstoi $src,$dst 2131 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstoi_opf, $src$$reg ); 2132 // fitos $dst,$dst (if nan) 2133 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg ); 2134 // clear $dst (if nan) 2135 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg ); 2136 // carry on here... 2137 %} 2138 2139 enc_class form_f2l_helper(regF src, regD dst) %{ 2140 // fcmps %fcc0,$src,$src 2141 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg ); 2142 // branch %fcc0 not-nan, predict taken 2143 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); 2144 // fstox $src,$dst 2145 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstox_opf, $src$$reg ); 2146 // fxtod $dst,$dst (if nan) 2147 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg ); 2148 // clear $dst (if nan) 2149 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg ); 2150 // carry on here... 2151 %} 2152 2153 enc_class form3_opf_rs2F_rdF(regF rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} 2154 enc_class form3_opf_rs2F_rdD(regF rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} 2155 enc_class form3_opf_rs2D_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} 2156 enc_class form3_opf_rs2D_rdD(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} 2157 2158 enc_class form3_opf_rs2D_lo_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg+1); %} 2159 2160 enc_class form3_opf_rs2D_hi_rdD_hi(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} 2161 enc_class form3_opf_rs2D_lo_rdD_lo(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg+1,$primary,0,$tertiary,$rs2$$reg+1); %} 2162 2163 enc_class form3_opf_rs1F_rs2F_rdF( regF rs1, regF rs2, regF rd ) %{ 2164 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); 2165 %} 2166 2167 enc_class form3_opf_rs1D_rs2D_rdD( regD rs1, regD rs2, regD rd ) %{ 2168 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); 2169 %} 2170 2171 enc_class form3_opf_rs1F_rs2F_fcc( regF rs1, regF rs2, flagsRegF fcc ) %{ 2172 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); 2173 %} 2174 2175 enc_class form3_opf_rs1D_rs2D_fcc( regD rs1, regD rs2, flagsRegF fcc ) %{ 2176 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); 2177 %} 2178 2179 enc_class form3_convI2F(regF rs2, regF rd) %{ 2180 emit3(cbuf,Assembler::arith_op,$rd$$reg,Assembler::fpop1_op3,0,$secondary,$rs2$$reg); 2181 %} 2182 2183 // Encloding class for traceable jumps 2184 enc_class form_jmpl(g3RegP dest) %{ 2185 emit_jmpl(cbuf, $dest$$reg); 2186 %} 2187 2188 enc_class form_jmpl_set_exception_pc(g1RegP dest) %{ 2189 emit_jmpl_set_exception_pc(cbuf, $dest$$reg); 2190 %} 2191 2192 enc_class form2_nop() %{ 2193 emit_nop(cbuf); 2194 %} 2195 2196 enc_class form2_illtrap() %{ 2197 emit_illtrap(cbuf); 2198 %} 2199 2200 2201 // Compare longs and convert into -1, 0, 1. 2202 enc_class cmpl_flag( iRegL src1, iRegL src2, iRegI dst ) %{ 2203 // CMP $src1,$src2 2204 emit3( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $src1$$reg, 0, $src2$$reg ); 2205 // blt,a,pn done 2206 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less , Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 5 ); 2207 // mov dst,-1 in delay slot 2208 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 ); 2209 // bgt,a,pn done 2210 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::greater, Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 3 ); 2211 // mov dst,1 in delay slot 2212 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 1 ); 2213 // CLR $dst 2214 emit3( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3 , 0, 0, 0 ); 2215 %} 2216 2217 enc_class enc_PartialSubtypeCheck() %{ 2218 MacroAssembler _masm(&cbuf); 2219 __ call(StubRoutines::Sparc::partial_subtype_check(), relocInfo::runtime_call_type); 2220 __ delayed()->nop(); 2221 %} 2222 2223 enc_class enc_bp( Label labl, cmpOp cmp, flagsReg cc ) %{ 2224 MacroAssembler _masm(&cbuf); 2225 Label &L = *($labl$$label); 2226 Assembler::Predict predict_taken = 2227 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn; 2228 2229 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, L); 2230 __ delayed()->nop(); 2231 %} 2232 2233 enc_class enc_bpl( Label labl, cmpOp cmp, flagsRegL cc ) %{ 2234 MacroAssembler _masm(&cbuf); 2235 Label &L = *($labl$$label); 2236 Assembler::Predict predict_taken = 2237 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn; 2238 2239 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, L); 2240 __ delayed()->nop(); 2241 %} 2242 2243 enc_class enc_bpx( Label labl, cmpOp cmp, flagsRegP cc ) %{ 2244 MacroAssembler _masm(&cbuf); 2245 Label &L = *($labl$$label); 2246 Assembler::Predict predict_taken = 2247 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn; 2248 2249 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, L); 2250 __ delayed()->nop(); 2251 %} 2252 2253 enc_class enc_fbp( Label labl, cmpOpF cmp, flagsRegF cc ) %{ 2254 MacroAssembler _masm(&cbuf); 2255 Label &L = *($labl$$label); 2256 Assembler::Predict predict_taken = 2257 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn; 2258 2259 __ fbp( (Assembler::Condition)($cmp$$cmpcode), false, (Assembler::CC)($cc$$reg), predict_taken, L); 2260 __ delayed()->nop(); 2261 %} 2262 2263 enc_class jump_enc( iRegX switch_val, o7RegI table) %{ 2264 MacroAssembler _masm(&cbuf); 2265 2266 Register switch_reg = as_Register($switch_val$$reg); 2267 Register table_reg = O7; 2268 2269 address table_base = __ address_table_constant(_index2label); 2270 RelocationHolder rspec = internal_word_Relocation::spec(table_base); 2271 2272 // Move table address into a register. 2273 __ set(table_base, table_reg, rspec); 2274 2275 // Jump to base address + switch value 2276 __ ld_ptr(table_reg, switch_reg, table_reg); 2277 __ jmp(table_reg, G0); 2278 __ delayed()->nop(); 2279 2280 %} 2281 2282 enc_class enc_ba( Label labl ) %{ 2283 MacroAssembler _masm(&cbuf); 2284 Label &L = *($labl$$label); 2285 __ ba(false, L); 2286 __ delayed()->nop(); 2287 %} 2288 2289 enc_class enc_bpr( Label labl, cmpOp_reg cmp, iRegI op1 ) %{ 2290 MacroAssembler _masm(&cbuf); 2291 Label &L = *$labl$$label; 2292 Assembler::Predict predict_taken = 2293 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn; 2294 2295 __ bpr( (Assembler::RCondition)($cmp$$cmpcode), false, predict_taken, as_Register($op1$$reg), L); 2296 __ delayed()->nop(); 2297 %} 2298 2299 enc_class enc_cmov_reg( cmpOp cmp, iRegI dst, iRegI src, immI pcc) %{ 2300 int op = (Assembler::arith_op << 30) | 2301 ($dst$$reg << 25) | 2302 (Assembler::movcc_op3 << 19) | 2303 (1 << 18) | // cc2 bit for 'icc' 2304 ($cmp$$cmpcode << 14) | 2305 (0 << 13) | // select register move 2306 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc' or 'xcc' 2307 ($src$$reg << 0); 2308 *((int*)(cbuf.code_end())) = op; 2309 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); 2310 %} 2311 2312 enc_class enc_cmov_imm( cmpOp cmp, iRegI dst, immI11 src, immI pcc ) %{ 2313 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits 2314 int op = (Assembler::arith_op << 30) | 2315 ($dst$$reg << 25) | 2316 (Assembler::movcc_op3 << 19) | 2317 (1 << 18) | // cc2 bit for 'icc' 2318 ($cmp$$cmpcode << 14) | 2319 (1 << 13) | // select immediate move 2320 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc' 2321 (simm11 << 0); 2322 *((int*)(cbuf.code_end())) = op; 2323 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); 2324 %} 2325 2326 enc_class enc_cmov_reg_f( cmpOpF cmp, iRegI dst, iRegI src, flagsRegF fcc ) %{ 2327 int op = (Assembler::arith_op << 30) | 2328 ($dst$$reg << 25) | 2329 (Assembler::movcc_op3 << 19) | 2330 (0 << 18) | // cc2 bit for 'fccX' 2331 ($cmp$$cmpcode << 14) | 2332 (0 << 13) | // select register move 2333 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3 2334 ($src$$reg << 0); 2335 *((int*)(cbuf.code_end())) = op; 2336 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); 2337 %} 2338 2339 enc_class enc_cmov_imm_f( cmpOp cmp, iRegI dst, immI11 src, flagsRegF fcc ) %{ 2340 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits 2341 int op = (Assembler::arith_op << 30) | 2342 ($dst$$reg << 25) | 2343 (Assembler::movcc_op3 << 19) | 2344 (0 << 18) | // cc2 bit for 'fccX' 2345 ($cmp$$cmpcode << 14) | 2346 (1 << 13) | // select immediate move 2347 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3 2348 (simm11 << 0); 2349 *((int*)(cbuf.code_end())) = op; 2350 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); 2351 %} 2352 2353 enc_class enc_cmovf_reg( cmpOp cmp, regD dst, regD src, immI pcc ) %{ 2354 int op = (Assembler::arith_op << 30) | 2355 ($dst$$reg << 25) | 2356 (Assembler::fpop2_op3 << 19) | 2357 (0 << 18) | 2358 ($cmp$$cmpcode << 14) | 2359 (1 << 13) | // select register move 2360 ($pcc$$constant << 11) | // cc1-cc0 bits for 'icc' or 'xcc' 2361 ($primary << 5) | // select single, double or quad 2362 ($src$$reg << 0); 2363 *((int*)(cbuf.code_end())) = op; 2364 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); 2365 %} 2366 2367 enc_class enc_cmovff_reg( cmpOpF cmp, flagsRegF fcc, regD dst, regD src ) %{ 2368 int op = (Assembler::arith_op << 30) | 2369 ($dst$$reg << 25) | 2370 (Assembler::fpop2_op3 << 19) | 2371 (0 << 18) | 2372 ($cmp$$cmpcode << 14) | 2373 ($fcc$$reg << 11) | // cc2-cc0 bits for 'fccX' 2374 ($primary << 5) | // select single, double or quad 2375 ($src$$reg << 0); 2376 *((int*)(cbuf.code_end())) = op; 2377 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); 2378 %} 2379 2380 // Used by the MIN/MAX encodings. Same as a CMOV, but 2381 // the condition comes from opcode-field instead of an argument. 2382 enc_class enc_cmov_reg_minmax( iRegI dst, iRegI src ) %{ 2383 int op = (Assembler::arith_op << 30) | 2384 ($dst$$reg << 25) | 2385 (Assembler::movcc_op3 << 19) | 2386 (1 << 18) | // cc2 bit for 'icc' 2387 ($primary << 14) | 2388 (0 << 13) | // select register move 2389 (0 << 11) | // cc1, cc0 bits for 'icc' 2390 ($src$$reg << 0); 2391 *((int*)(cbuf.code_end())) = op; 2392 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); 2393 %} 2394 2395 enc_class enc_cmov_reg_minmax_long( iRegL dst, iRegL src ) %{ 2396 int op = (Assembler::arith_op << 30) | 2397 ($dst$$reg << 25) | 2398 (Assembler::movcc_op3 << 19) | 2399 (6 << 16) | // cc2 bit for 'xcc' 2400 ($primary << 14) | 2401 (0 << 13) | // select register move 2402 (0 << 11) | // cc1, cc0 bits for 'icc' 2403 ($src$$reg << 0); 2404 *((int*)(cbuf.code_end())) = op; 2405 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); 2406 %} 2407 2408 // Utility encoding for loading a 64 bit Pointer into a register 2409 // The 64 bit pointer is stored in the generated code stream 2410 enc_class SetPtr( immP src, iRegP rd ) %{ 2411 Register dest = reg_to_register_object($rd$$reg); 2412 MacroAssembler _masm(&cbuf); 2413 // [RGV] This next line should be generated from ADLC 2414 if ( _opnds[1]->constant_is_oop() ) { 2415 intptr_t val = $src$$constant; 2416 __ set_oop_constant((jobject)val, dest); 2417 } else { // non-oop pointers, e.g. card mark base, heap top 2418 __ set($src$$constant, dest); 2419 } 2420 %} 2421 2422 enc_class Set13( immI13 src, iRegI rd ) %{ 2423 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, $src$$constant ); 2424 %} 2425 2426 enc_class SetHi22( immI src, iRegI rd ) %{ 2427 emit2_22( cbuf, Assembler::branch_op, $rd$$reg, Assembler::sethi_op2, $src$$constant ); 2428 %} 2429 2430 enc_class Set32( immI src, iRegI rd ) %{ 2431 MacroAssembler _masm(&cbuf); 2432 __ set($src$$constant, reg_to_register_object($rd$$reg)); 2433 %} 2434 2435 enc_class SetNull( iRegI rd ) %{ 2436 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0 ); 2437 %} 2438 2439 enc_class call_epilog %{ 2440 if( VerifyStackAtCalls ) { 2441 MacroAssembler _masm(&cbuf); 2442 int framesize = ra_->C->frame_slots() << LogBytesPerInt; 2443 Register temp_reg = G3; 2444 __ add(SP, framesize, temp_reg); 2445 __ cmp(temp_reg, FP); 2446 __ breakpoint_trap(Assembler::notEqual, Assembler::ptr_cc); 2447 } 2448 %} 2449 2450 // Long values come back from native calls in O0:O1 in the 32-bit VM, copy the value 2451 // to G1 so the register allocator will not have to deal with the misaligned register 2452 // pair. 2453 enc_class adjust_long_from_native_call %{ 2454 #ifndef _LP64 2455 if (returns_long()) { 2456 // sllx O0,32,O0 2457 emit3_simm13( cbuf, Assembler::arith_op, R_O0_enc, Assembler::sllx_op3, R_O0_enc, 0x1020 ); 2458 // srl O1,0,O1 2459 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::srl_op3, R_O1_enc, 0x0000 ); 2460 // or O0,O1,G1 2461 emit3 ( cbuf, Assembler::arith_op, R_G1_enc, Assembler:: or_op3, R_O0_enc, 0, R_O1_enc ); 2462 } 2463 #endif 2464 %} 2465 2466 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime 2467 // CALL directly to the runtime 2468 // The user of this is responsible for ensuring that R_L7 is empty (killed). 2469 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type, 2470 /*preserve_g2=*/true, /*force far call*/true); 2471 %} 2472 2473 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL 2474 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine 2475 // who we intended to call. 2476 if ( !_method ) { 2477 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type); 2478 } else if (_optimized_virtual) { 2479 emit_call_reloc(cbuf, $meth$$method, relocInfo::opt_virtual_call_type); 2480 } else { 2481 emit_call_reloc(cbuf, $meth$$method, relocInfo::static_call_type); 2482 } 2483 if( _method ) { // Emit stub for static call 2484 emit_java_to_interp(cbuf); 2485 } 2486 %} 2487 2488 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL 2489 MacroAssembler _masm(&cbuf); 2490 __ set_inst_mark(); 2491 int vtable_index = this->_vtable_index; 2492 // MachCallDynamicJavaNode::ret_addr_offset uses this same test 2493 if (vtable_index < 0) { 2494 // must be invalid_vtable_index, not nonvirtual_vtable_index 2495 assert(vtable_index == methodOopDesc::invalid_vtable_index, "correct sentinel value"); 2496 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode()); 2497 assert(G5_ic_reg == G5_inline_cache_reg, "G5_inline_cache_reg used in assemble_ic_buffer_code()"); 2498 assert(G5_ic_reg == G5_megamorphic_method, "G5_megamorphic_method used in megamorphic call stub"); 2499 // !!!!! 2500 // Generate "set 0x01, R_G5", placeholder instruction to load oop-info 2501 // emit_call_dynamic_prologue( cbuf ); 2502 __ set_oop((jobject)Universe::non_oop_word(), G5_ic_reg); 2503 2504 address virtual_call_oop_addr = __ inst_mark(); 2505 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine 2506 // who we intended to call. 2507 __ relocate(virtual_call_Relocation::spec(virtual_call_oop_addr)); 2508 emit_call_reloc(cbuf, $meth$$method, relocInfo::none); 2509 } else { 2510 assert(!UseInlineCaches, "expect vtable calls only if not using ICs"); 2511 // Just go thru the vtable 2512 // get receiver klass (receiver already checked for non-null) 2513 // If we end up going thru a c2i adapter interpreter expects method in G5 2514 int off = __ offset(); 2515 __ load_klass(O0, G3_scratch); 2516 int klass_load_size; 2517 if (UseCompressedOops) { 2518 assert(Universe::heap() != NULL, "java heap should be initialized"); 2519 if (Universe::narrow_oop_base() == NULL) 2520 klass_load_size = 2*BytesPerInstWord; 2521 else 2522 klass_load_size = 3*BytesPerInstWord; 2523 } else { 2524 klass_load_size = 1*BytesPerInstWord; 2525 } 2526 int entry_offset = instanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size(); 2527 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes(); 2528 if( __ is_simm13(v_off) ) { 2529 __ ld_ptr(G3, v_off, G5_method); 2530 } else { 2531 // Generate 2 instructions 2532 __ Assembler::sethi(v_off & ~0x3ff, G5_method); 2533 __ or3(G5_method, v_off & 0x3ff, G5_method); 2534 // ld_ptr, set_hi, set 2535 assert(__ offset() - off == klass_load_size + 2*BytesPerInstWord, 2536 "Unexpected instruction size(s)"); 2537 __ ld_ptr(G3, G5_method, G5_method); 2538 } 2539 // NOTE: for vtable dispatches, the vtable entry will never be null. 2540 // However it may very well end up in handle_wrong_method if the 2541 // method is abstract for the particular class. 2542 __ ld_ptr(G5_method, in_bytes(methodOopDesc::from_compiled_offset()), G3_scratch); 2543 // jump to target (either compiled code or c2iadapter) 2544 __ jmpl(G3_scratch, G0, O7); 2545 __ delayed()->nop(); 2546 } 2547 %} 2548 2549 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL 2550 MacroAssembler _masm(&cbuf); 2551 2552 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode()); 2553 Register temp_reg = G3; // caller must kill G3! We cannot reuse G5_ic_reg here because 2554 // we might be calling a C2I adapter which needs it. 2555 2556 assert(temp_reg != G5_ic_reg, "conflicting registers"); 2557 // Load nmethod 2558 __ ld_ptr(G5_ic_reg, in_bytes(methodOopDesc::from_compiled_offset()), temp_reg); 2559 2560 // CALL to compiled java, indirect the contents of G3 2561 __ set_inst_mark(); 2562 __ callr(temp_reg, G0); 2563 __ delayed()->nop(); 2564 %} 2565 2566 enc_class idiv_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst) %{ 2567 MacroAssembler _masm(&cbuf); 2568 Register Rdividend = reg_to_register_object($src1$$reg); 2569 Register Rdivisor = reg_to_register_object($src2$$reg); 2570 Register Rresult = reg_to_register_object($dst$$reg); 2571 2572 __ sra(Rdivisor, 0, Rdivisor); 2573 __ sra(Rdividend, 0, Rdividend); 2574 __ sdivx(Rdividend, Rdivisor, Rresult); 2575 %} 2576 2577 enc_class idiv_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst) %{ 2578 MacroAssembler _masm(&cbuf); 2579 2580 Register Rdividend = reg_to_register_object($src1$$reg); 2581 int divisor = $imm$$constant; 2582 Register Rresult = reg_to_register_object($dst$$reg); 2583 2584 __ sra(Rdividend, 0, Rdividend); 2585 __ sdivx(Rdividend, divisor, Rresult); 2586 %} 2587 2588 enc_class enc_mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2) %{ 2589 MacroAssembler _masm(&cbuf); 2590 Register Rsrc1 = reg_to_register_object($src1$$reg); 2591 Register Rsrc2 = reg_to_register_object($src2$$reg); 2592 Register Rdst = reg_to_register_object($dst$$reg); 2593 2594 __ sra( Rsrc1, 0, Rsrc1 ); 2595 __ sra( Rsrc2, 0, Rsrc2 ); 2596 __ mulx( Rsrc1, Rsrc2, Rdst ); 2597 __ srlx( Rdst, 32, Rdst ); 2598 %} 2599 2600 enc_class irem_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst, o7RegL scratch) %{ 2601 MacroAssembler _masm(&cbuf); 2602 Register Rdividend = reg_to_register_object($src1$$reg); 2603 Register Rdivisor = reg_to_register_object($src2$$reg); 2604 Register Rresult = reg_to_register_object($dst$$reg); 2605 Register Rscratch = reg_to_register_object($scratch$$reg); 2606 2607 assert(Rdividend != Rscratch, ""); 2608 assert(Rdivisor != Rscratch, ""); 2609 2610 __ sra(Rdividend, 0, Rdividend); 2611 __ sra(Rdivisor, 0, Rdivisor); 2612 __ sdivx(Rdividend, Rdivisor, Rscratch); 2613 __ mulx(Rscratch, Rdivisor, Rscratch); 2614 __ sub(Rdividend, Rscratch, Rresult); 2615 %} 2616 2617 enc_class irem_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst, o7RegL scratch) %{ 2618 MacroAssembler _masm(&cbuf); 2619 2620 Register Rdividend = reg_to_register_object($src1$$reg); 2621 int divisor = $imm$$constant; 2622 Register Rresult = reg_to_register_object($dst$$reg); 2623 Register Rscratch = reg_to_register_object($scratch$$reg); 2624 2625 assert(Rdividend != Rscratch, ""); 2626 2627 __ sra(Rdividend, 0, Rdividend); 2628 __ sdivx(Rdividend, divisor, Rscratch); 2629 __ mulx(Rscratch, divisor, Rscratch); 2630 __ sub(Rdividend, Rscratch, Rresult); 2631 %} 2632 2633 enc_class fabss (sflt_reg dst, sflt_reg src) %{ 2634 MacroAssembler _masm(&cbuf); 2635 2636 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg); 2637 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg); 2638 2639 __ fabs(FloatRegisterImpl::S, Fsrc, Fdst); 2640 %} 2641 2642 enc_class fabsd (dflt_reg dst, dflt_reg src) %{ 2643 MacroAssembler _masm(&cbuf); 2644 2645 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); 2646 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); 2647 2648 __ fabs(FloatRegisterImpl::D, Fsrc, Fdst); 2649 %} 2650 2651 enc_class fnegd (dflt_reg dst, dflt_reg src) %{ 2652 MacroAssembler _masm(&cbuf); 2653 2654 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); 2655 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); 2656 2657 __ fneg(FloatRegisterImpl::D, Fsrc, Fdst); 2658 %} 2659 2660 enc_class fsqrts (sflt_reg dst, sflt_reg src) %{ 2661 MacroAssembler _masm(&cbuf); 2662 2663 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg); 2664 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg); 2665 2666 __ fsqrt(FloatRegisterImpl::S, Fsrc, Fdst); 2667 %} 2668 2669 enc_class fsqrtd (dflt_reg dst, dflt_reg src) %{ 2670 MacroAssembler _masm(&cbuf); 2671 2672 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); 2673 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); 2674 2675 __ fsqrt(FloatRegisterImpl::D, Fsrc, Fdst); 2676 %} 2677 2678 enc_class fmovs (dflt_reg dst, dflt_reg src) %{ 2679 MacroAssembler _masm(&cbuf); 2680 2681 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg); 2682 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg); 2683 2684 __ fmov(FloatRegisterImpl::S, Fsrc, Fdst); 2685 %} 2686 2687 enc_class fmovd (dflt_reg dst, dflt_reg src) %{ 2688 MacroAssembler _masm(&cbuf); 2689 2690 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); 2691 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); 2692 2693 __ fmov(FloatRegisterImpl::D, Fsrc, Fdst); 2694 %} 2695 2696 enc_class Fast_Lock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{ 2697 MacroAssembler _masm(&cbuf); 2698 2699 Register Roop = reg_to_register_object($oop$$reg); 2700 Register Rbox = reg_to_register_object($box$$reg); 2701 Register Rscratch = reg_to_register_object($scratch$$reg); 2702 Register Rmark = reg_to_register_object($scratch2$$reg); 2703 2704 assert(Roop != Rscratch, ""); 2705 assert(Roop != Rmark, ""); 2706 assert(Rbox != Rscratch, ""); 2707 assert(Rbox != Rmark, ""); 2708 2709 __ compiler_lock_object(Roop, Rmark, Rbox, Rscratch, _counters, UseBiasedLocking && !UseOptoBiasInlining); 2710 %} 2711 2712 enc_class Fast_Unlock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{ 2713 MacroAssembler _masm(&cbuf); 2714 2715 Register Roop = reg_to_register_object($oop$$reg); 2716 Register Rbox = reg_to_register_object($box$$reg); 2717 Register Rscratch = reg_to_register_object($scratch$$reg); 2718 Register Rmark = reg_to_register_object($scratch2$$reg); 2719 2720 assert(Roop != Rscratch, ""); 2721 assert(Roop != Rmark, ""); 2722 assert(Rbox != Rscratch, ""); 2723 assert(Rbox != Rmark, ""); 2724 2725 __ compiler_unlock_object(Roop, Rmark, Rbox, Rscratch, UseBiasedLocking && !UseOptoBiasInlining); 2726 %} 2727 2728 enc_class enc_cas( iRegP mem, iRegP old, iRegP new ) %{ 2729 MacroAssembler _masm(&cbuf); 2730 Register Rmem = reg_to_register_object($mem$$reg); 2731 Register Rold = reg_to_register_object($old$$reg); 2732 Register Rnew = reg_to_register_object($new$$reg); 2733 2734 // casx_under_lock picks 1 of 3 encodings: 2735 // For 32-bit pointers you get a 32-bit CAS 2736 // For 64-bit pointers you get a 64-bit CASX 2737 __ casn(Rmem, Rold, Rnew); // Swap(*Rmem,Rnew) if *Rmem == Rold 2738 __ cmp( Rold, Rnew ); 2739 %} 2740 2741 enc_class enc_casx( iRegP mem, iRegL old, iRegL new) %{ 2742 Register Rmem = reg_to_register_object($mem$$reg); 2743 Register Rold = reg_to_register_object($old$$reg); 2744 Register Rnew = reg_to_register_object($new$$reg); 2745 2746 MacroAssembler _masm(&cbuf); 2747 __ mov(Rnew, O7); 2748 __ casx(Rmem, Rold, O7); 2749 __ cmp( Rold, O7 ); 2750 %} 2751 2752 // raw int cas, used for compareAndSwap 2753 enc_class enc_casi( iRegP mem, iRegL old, iRegL new) %{ 2754 Register Rmem = reg_to_register_object($mem$$reg); 2755 Register Rold = reg_to_register_object($old$$reg); 2756 Register Rnew = reg_to_register_object($new$$reg); 2757 2758 MacroAssembler _masm(&cbuf); 2759 __ mov(Rnew, O7); 2760 __ cas(Rmem, Rold, O7); 2761 __ cmp( Rold, O7 ); 2762 %} 2763 2764 enc_class enc_lflags_ne_to_boolean( iRegI res ) %{ 2765 Register Rres = reg_to_register_object($res$$reg); 2766 2767 MacroAssembler _masm(&cbuf); 2768 __ mov(1, Rres); 2769 __ movcc( Assembler::notEqual, false, Assembler::xcc, G0, Rres ); 2770 %} 2771 2772 enc_class enc_iflags_ne_to_boolean( iRegI res ) %{ 2773 Register Rres = reg_to_register_object($res$$reg); 2774 2775 MacroAssembler _masm(&cbuf); 2776 __ mov(1, Rres); 2777 __ movcc( Assembler::notEqual, false, Assembler::icc, G0, Rres ); 2778 %} 2779 2780 enc_class floating_cmp ( iRegP dst, regF src1, regF src2 ) %{ 2781 MacroAssembler _masm(&cbuf); 2782 Register Rdst = reg_to_register_object($dst$$reg); 2783 FloatRegister Fsrc1 = $primary ? reg_to_SingleFloatRegister_object($src1$$reg) 2784 : reg_to_DoubleFloatRegister_object($src1$$reg); 2785 FloatRegister Fsrc2 = $primary ? reg_to_SingleFloatRegister_object($src2$$reg) 2786 : reg_to_DoubleFloatRegister_object($src2$$reg); 2787 2788 // Convert condition code fcc0 into -1,0,1; unordered reports less-than (-1) 2789 __ float_cmp( $primary, -1, Fsrc1, Fsrc2, Rdst); 2790 %} 2791 2792 enc_class LdImmL (immL src, iRegL dst, o7RegL tmp) %{ // Load Immediate 2793 MacroAssembler _masm(&cbuf); 2794 Register dest = reg_to_register_object($dst$$reg); 2795 Register temp = reg_to_register_object($tmp$$reg); 2796 __ set64( $src$$constant, dest, temp ); 2797 %} 2798 2799 enc_class LdReplImmI(immI src, regD dst, o7RegP tmp, int count, int width) %{ 2800 // Load a constant replicated "count" times with width "width" 2801 int bit_width = $width$$constant * 8; 2802 jlong elt_val = $src$$constant; 2803 elt_val &= (((jlong)1) << bit_width) - 1; // mask off sign bits 2804 jlong val = elt_val; 2805 for (int i = 0; i < $count$$constant - 1; i++) { 2806 val <<= bit_width; 2807 val |= elt_val; 2808 } 2809 jdouble dval = *(jdouble*)&val; // coerce to double type 2810 MacroAssembler _masm(&cbuf); 2811 address double_address = __ double_constant(dval); 2812 RelocationHolder rspec = internal_word_Relocation::spec(double_address); 2813 AddressLiteral addrlit(double_address, rspec); 2814 2815 __ sethi(addrlit, $tmp$$Register); 2816 // XXX This is a quick fix for 6833573. 2817 //__ ldf(FloatRegisterImpl::D, $tmp$$Register, addrlit.low10(), $dst$$FloatRegister, rspec); 2818 __ ldf(FloatRegisterImpl::D, $tmp$$Register, addrlit.low10(), as_DoubleFloatRegister($dst$$reg), rspec); 2819 %} 2820 2821 // Compiler ensures base is doubleword aligned and cnt is count of doublewords 2822 enc_class enc_Clear_Array(iRegX cnt, iRegP base, iRegX temp) %{ 2823 MacroAssembler _masm(&cbuf); 2824 Register nof_bytes_arg = reg_to_register_object($cnt$$reg); 2825 Register nof_bytes_tmp = reg_to_register_object($temp$$reg); 2826 Register base_pointer_arg = reg_to_register_object($base$$reg); 2827 2828 Label loop; 2829 __ mov(nof_bytes_arg, nof_bytes_tmp); 2830 2831 // Loop and clear, walking backwards through the array. 2832 // nof_bytes_tmp (if >0) is always the number of bytes to zero 2833 __ bind(loop); 2834 __ deccc(nof_bytes_tmp, 8); 2835 __ br(Assembler::greaterEqual, true, Assembler::pt, loop); 2836 __ delayed()-> stx(G0, base_pointer_arg, nof_bytes_tmp); 2837 // %%%% this mini-loop must not cross a cache boundary! 2838 %} 2839 2840 2841 enc_class enc_String_Compare(o0RegP str1, o1RegP str2, g3RegP tmp1, g4RegP tmp2, notemp_iRegI result) %{ 2842 Label Ldone, Lloop; 2843 MacroAssembler _masm(&cbuf); 2844 2845 Register str1_reg = reg_to_register_object($str1$$reg); 2846 Register str2_reg = reg_to_register_object($str2$$reg); 2847 Register tmp1_reg = reg_to_register_object($tmp1$$reg); 2848 Register tmp2_reg = reg_to_register_object($tmp2$$reg); 2849 Register result_reg = reg_to_register_object($result$$reg); 2850 2851 // Get the first character position in both strings 2852 // [8] char array, [12] offset, [16] count 2853 int value_offset = java_lang_String:: value_offset_in_bytes(); 2854 int offset_offset = java_lang_String::offset_offset_in_bytes(); 2855 int count_offset = java_lang_String:: count_offset_in_bytes(); 2856 2857 // load str1 (jchar*) base address into tmp1_reg 2858 __ load_heap_oop(str1_reg, value_offset, tmp1_reg); 2859 __ ld(str1_reg, offset_offset, result_reg); 2860 __ add(tmp1_reg, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp1_reg); 2861 __ ld(str1_reg, count_offset, str1_reg); // hoisted 2862 __ sll(result_reg, exact_log2(sizeof(jchar)), result_reg); 2863 __ load_heap_oop(str2_reg, value_offset, tmp2_reg); // hoisted 2864 __ add(result_reg, tmp1_reg, tmp1_reg); 2865 2866 // load str2 (jchar*) base address into tmp2_reg 2867 // __ ld_ptr(str2_reg, value_offset, tmp2_reg); // hoisted 2868 __ ld(str2_reg, offset_offset, result_reg); 2869 __ add(tmp2_reg, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp2_reg); 2870 __ ld(str2_reg, count_offset, str2_reg); // hoisted 2871 __ sll(result_reg, exact_log2(sizeof(jchar)), result_reg); 2872 __ subcc(str1_reg, str2_reg, O7); // hoisted 2873 __ add(result_reg, tmp2_reg, tmp2_reg); 2874 2875 // Compute the minimum of the string lengths(str1_reg) and the 2876 // difference of the string lengths (stack) 2877 2878 // discard string base pointers, after loading up the lengths 2879 // __ ld(str1_reg, count_offset, str1_reg); // hoisted 2880 // __ ld(str2_reg, count_offset, str2_reg); // hoisted 2881 2882 // See if the lengths are different, and calculate min in str1_reg. 2883 // Stash diff in O7 in case we need it for a tie-breaker. 2884 Label Lskip; 2885 // __ subcc(str1_reg, str2_reg, O7); // hoisted 2886 __ sll(str1_reg, exact_log2(sizeof(jchar)), str1_reg); // scale the limit 2887 __ br(Assembler::greater, true, Assembler::pt, Lskip); 2888 // str2 is shorter, so use its count: 2889 __ delayed()->sll(str2_reg, exact_log2(sizeof(jchar)), str1_reg); // scale the limit 2890 __ bind(Lskip); 2891 2892 // reallocate str1_reg, str2_reg, result_reg 2893 // Note: limit_reg holds the string length pre-scaled by 2 2894 Register limit_reg = str1_reg; 2895 Register chr2_reg = str2_reg; 2896 Register chr1_reg = result_reg; 2897 // tmp{12} are the base pointers 2898 2899 // Is the minimum length zero? 2900 __ cmp(limit_reg, (int)(0 * sizeof(jchar))); // use cast to resolve overloading ambiguity 2901 __ br(Assembler::equal, true, Assembler::pn, Ldone); 2902 __ delayed()->mov(O7, result_reg); // result is difference in lengths 2903 2904 // Load first characters 2905 __ lduh(tmp1_reg, 0, chr1_reg); 2906 __ lduh(tmp2_reg, 0, chr2_reg); 2907 2908 // Compare first characters 2909 __ subcc(chr1_reg, chr2_reg, chr1_reg); 2910 __ br(Assembler::notZero, false, Assembler::pt, Ldone); 2911 assert(chr1_reg == result_reg, "result must be pre-placed"); 2912 __ delayed()->nop(); 2913 2914 { 2915 // Check after comparing first character to see if strings are equivalent 2916 Label LSkip2; 2917 // Check if the strings start at same location 2918 __ cmp(tmp1_reg, tmp2_reg); 2919 __ brx(Assembler::notEqual, true, Assembler::pt, LSkip2); 2920 __ delayed()->nop(); 2921 2922 // Check if the length difference is zero (in O7) 2923 __ cmp(G0, O7); 2924 __ br(Assembler::equal, true, Assembler::pn, Ldone); 2925 __ delayed()->mov(G0, result_reg); // result is zero 2926 2927 // Strings might not be equal 2928 __ bind(LSkip2); 2929 } 2930 2931 __ subcc(limit_reg, 1 * sizeof(jchar), chr1_reg); 2932 __ br(Assembler::equal, true, Assembler::pn, Ldone); 2933 __ delayed()->mov(O7, result_reg); // result is difference in lengths 2934 2935 // Shift tmp1_reg and tmp2_reg to the end of the arrays, negate limit 2936 __ add(tmp1_reg, limit_reg, tmp1_reg); 2937 __ add(tmp2_reg, limit_reg, tmp2_reg); 2938 __ neg(chr1_reg, limit_reg); // limit = -(limit-2) 2939 2940 // Compare the rest of the characters 2941 __ lduh(tmp1_reg, limit_reg, chr1_reg); 2942 __ bind(Lloop); 2943 // __ lduh(tmp1_reg, limit_reg, chr1_reg); // hoisted 2944 __ lduh(tmp2_reg, limit_reg, chr2_reg); 2945 __ subcc(chr1_reg, chr2_reg, chr1_reg); 2946 __ br(Assembler::notZero, false, Assembler::pt, Ldone); 2947 assert(chr1_reg == result_reg, "result must be pre-placed"); 2948 __ delayed()->inccc(limit_reg, sizeof(jchar)); 2949 // annul LDUH if branch is not taken to prevent access past end of string 2950 __ br(Assembler::notZero, true, Assembler::pt, Lloop); 2951 __ delayed()->lduh(tmp1_reg, limit_reg, chr1_reg); // hoisted 2952 2953 // If strings are equal up to min length, return the length difference. 2954 __ mov(O7, result_reg); 2955 2956 // Otherwise, return the difference between the first mismatched chars. 2957 __ bind(Ldone); 2958 %} 2959 2960 enc_class enc_String_Equals(o0RegP str1, o1RegP str2, g3RegP tmp1, g4RegP tmp2, notemp_iRegI result) %{ 2961 Label Lword, Lword_loop, Lpost_word, Lchar, Lchar_loop, Ldone; 2962 MacroAssembler _masm(&cbuf); 2963 2964 Register str1_reg = reg_to_register_object($str1$$reg); 2965 Register str2_reg = reg_to_register_object($str2$$reg); 2966 Register tmp1_reg = reg_to_register_object($tmp1$$reg); 2967 Register tmp2_reg = reg_to_register_object($tmp2$$reg); 2968 Register result_reg = reg_to_register_object($result$$reg); 2969 2970 // Get the first character position in both strings 2971 // [8] char array, [12] offset, [16] count 2972 int value_offset = java_lang_String:: value_offset_in_bytes(); 2973 int offset_offset = java_lang_String::offset_offset_in_bytes(); 2974 int count_offset = java_lang_String:: count_offset_in_bytes(); 2975 2976 // load str1 (jchar*) base address into tmp1_reg 2977 __ load_heap_oop(Address(str1_reg, value_offset), tmp1_reg); 2978 __ ld(Address(str1_reg, offset_offset), result_reg); 2979 __ add(tmp1_reg, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp1_reg); 2980 __ ld(Address(str1_reg, count_offset), str1_reg); // hoisted 2981 __ sll(result_reg, exact_log2(sizeof(jchar)), result_reg); 2982 __ load_heap_oop(Address(str2_reg, value_offset), tmp2_reg); // hoisted 2983 __ add(result_reg, tmp1_reg, tmp1_reg); 2984 2985 // load str2 (jchar*) base address into tmp2_reg 2986 // __ ld_ptr(Address(str2_reg, value_offset), tmp2_reg); // hoisted 2987 __ ld(Address(str2_reg, offset_offset), result_reg); 2988 __ add(tmp2_reg, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp2_reg); 2989 __ ld(Address(str2_reg, count_offset), str2_reg); // hoisted 2990 __ sll(result_reg, exact_log2(sizeof(jchar)), result_reg); 2991 __ cmp(str1_reg, str2_reg); // hoisted 2992 __ add(result_reg, tmp2_reg, tmp2_reg); 2993 2994 __ sll(str1_reg, exact_log2(sizeof(jchar)), str1_reg); 2995 __ br(Assembler::notEqual, true, Assembler::pt, Ldone); 2996 __ delayed()->mov(G0, result_reg); // not equal 2997 2998 __ br_zero(Assembler::equal, true, Assembler::pn, str1_reg, Ldone); 2999 __ delayed()->add(G0, 1, result_reg); //equals 3000 3001 __ cmp(tmp1_reg, tmp2_reg); //same string ? 3002 __ brx(Assembler::equal, true, Assembler::pn, Ldone); 3003 __ delayed()->add(G0, 1, result_reg); 3004 3005 //rename registers 3006 Register limit_reg = str1_reg; 3007 Register chr2_reg = str2_reg; 3008 Register chr1_reg = result_reg; 3009 // tmp{12} are the base pointers 3010 3011 //check for alignment and position the pointers to the ends 3012 __ or3(tmp1_reg, tmp2_reg, chr1_reg); 3013 __ andcc(chr1_reg, 0x3, chr1_reg); // notZero means at least one not 4-byte aligned 3014 __ br(Assembler::notZero, false, Assembler::pn, Lchar); 3015 __ delayed()->nop(); 3016 3017 __ bind(Lword); 3018 __ and3(limit_reg, 0x2, O7); //remember the remainder (either 0 or 2) 3019 __ andn(limit_reg, 0x3, limit_reg); 3020 __ br_zero(Assembler::zero, false, Assembler::pn, limit_reg, Lpost_word); 3021 __ delayed()->nop(); 3022 3023 __ add(tmp1_reg, limit_reg, tmp1_reg); 3024 __ add(tmp2_reg, limit_reg, tmp2_reg); 3025 __ neg(limit_reg); 3026 3027 __ lduw(tmp1_reg, limit_reg, chr1_reg); 3028 __ bind(Lword_loop); 3029 __ lduw(tmp2_reg, limit_reg, chr2_reg); 3030 __ cmp(chr1_reg, chr2_reg); 3031 __ br(Assembler::notEqual, true, Assembler::pt, Ldone); 3032 __ delayed()->mov(G0, result_reg); 3033 __ inccc(limit_reg, 2*sizeof(jchar)); 3034 // annul LDUW if branch i s not taken to prevent access past end of string 3035 __ br(Assembler::notZero, true, Assembler::pt, Lword_loop); //annul on taken 3036 __ delayed()->lduw(tmp1_reg, limit_reg, chr1_reg); // hoisted 3037 3038 __ bind(Lpost_word); 3039 __ br_zero(Assembler::zero, true, Assembler::pt, O7, Ldone); 3040 __ delayed()->add(G0, 1, result_reg); 3041 3042 __ lduh(tmp1_reg, 0, chr1_reg); 3043 __ lduh(tmp2_reg, 0, chr2_reg); 3044 __ cmp (chr1_reg, chr2_reg); 3045 __ br(Assembler::notEqual, true, Assembler::pt, Ldone); 3046 __ delayed()->mov(G0, result_reg); 3047 __ ba(false,Ldone); 3048 __ delayed()->add(G0, 1, result_reg); 3049 3050 __ bind(Lchar); 3051 __ add(tmp1_reg, limit_reg, tmp1_reg); 3052 __ add(tmp2_reg, limit_reg, tmp2_reg); 3053 __ neg(limit_reg); //negate count 3054 3055 __ lduh(tmp1_reg, limit_reg, chr1_reg); 3056 __ bind(Lchar_loop); 3057 __ lduh(tmp2_reg, limit_reg, chr2_reg); 3058 __ cmp(chr1_reg, chr2_reg); 3059 __ br(Assembler::notEqual, true, Assembler::pt, Ldone); 3060 __ delayed()->mov(G0, result_reg); //not equal 3061 __ inccc(limit_reg, sizeof(jchar)); 3062 // annul LDUH if branch is not taken to prevent access past end of string 3063 __ br(Assembler::notZero, true, Assembler::pt, Lchar_loop); //annul on taken 3064 __ delayed()->lduh(tmp1_reg, limit_reg, chr1_reg); // hoisted 3065 3066 __ add(G0, 1, result_reg); //equal 3067 3068 __ bind(Ldone); 3069 %} 3070 3071 enc_class enc_Array_Equals(o0RegP ary1, o1RegP ary2, g3RegP tmp1, g4RegP tmp2, notemp_iRegI result) %{ 3072 Label Lvector, Ldone, Lloop; 3073 MacroAssembler _masm(&cbuf); 3074 3075 Register ary1_reg = reg_to_register_object($ary1$$reg); 3076 Register ary2_reg = reg_to_register_object($ary2$$reg); 3077 Register tmp1_reg = reg_to_register_object($tmp1$$reg); 3078 Register tmp2_reg = reg_to_register_object($tmp2$$reg); 3079 Register result_reg = reg_to_register_object($result$$reg); 3080 3081 int length_offset = arrayOopDesc::length_offset_in_bytes(); 3082 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR); 3083 3084 // return true if the same array 3085 __ cmp(ary1_reg, ary2_reg); 3086 __ br(Assembler::equal, true, Assembler::pn, Ldone); 3087 __ delayed()->add(G0, 1, result_reg); // equal 3088 3089 __ br_null(ary1_reg, true, Assembler::pn, Ldone); 3090 __ delayed()->mov(G0, result_reg); // not equal 3091 3092 __ br_null(ary2_reg, true, Assembler::pn, Ldone); 3093 __ delayed()->mov(G0, result_reg); // not equal 3094 3095 //load the lengths of arrays 3096 __ ld(Address(ary1_reg, length_offset), tmp1_reg); 3097 __ ld(Address(ary2_reg, length_offset), tmp2_reg); 3098 3099 // return false if the two arrays are not equal length 3100 __ cmp(tmp1_reg, tmp2_reg); 3101 __ br(Assembler::notEqual, true, Assembler::pn, Ldone); 3102 __ delayed()->mov(G0, result_reg); // not equal 3103 3104 __ br_zero(Assembler::zero, true, Assembler::pn, tmp1_reg, Ldone); 3105 __ delayed()->add(G0, 1, result_reg); // zero-length arrays are equal 3106 3107 // load array addresses 3108 __ add(ary1_reg, base_offset, ary1_reg); 3109 __ add(ary2_reg, base_offset, ary2_reg); 3110 3111 // renaming registers 3112 Register chr1_reg = tmp2_reg; // for characters in ary1 3113 Register chr2_reg = result_reg; // for characters in ary2 3114 Register limit_reg = tmp1_reg; // length 3115 3116 // set byte count 3117 __ sll(limit_reg, exact_log2(sizeof(jchar)), limit_reg); 3118 __ andcc(limit_reg, 0x2, chr1_reg); //trailing character ? 3119 __ br(Assembler::zero, false, Assembler::pt, Lvector); 3120 __ delayed()->nop(); 3121 3122 //compare the trailing char 3123 __ sub(limit_reg, sizeof(jchar), limit_reg); 3124 __ lduh(ary1_reg, limit_reg, chr1_reg); 3125 __ lduh(ary2_reg, limit_reg, chr2_reg); 3126 __ cmp(chr1_reg, chr2_reg); 3127 __ br(Assembler::notEqual, true, Assembler::pt, Ldone); 3128 __ delayed()->mov(G0, result_reg); // not equal 3129 3130 // only one char ? 3131 __ br_zero(Assembler::zero, true, Assembler::pn, limit_reg, Ldone); 3132 __ delayed()->add(G0, 1, result_reg); // zero-length arrays are equal 3133 3134 __ bind(Lvector); 3135 // Shift ary1_reg and ary2_reg to the end of the arrays, negate limit 3136 __ add(ary1_reg, limit_reg, ary1_reg); 3137 __ add(ary2_reg, limit_reg, ary2_reg); 3138 __ neg(limit_reg, limit_reg); 3139 3140 __ lduw(ary1_reg, limit_reg, chr1_reg); 3141 __ bind(Lloop); 3142 __ lduw(ary2_reg, limit_reg, chr2_reg); 3143 __ cmp(chr1_reg, chr2_reg); 3144 __ br(Assembler::notEqual, false, Assembler::pt, Ldone); 3145 __ delayed()->mov(G0, result_reg); // not equal 3146 __ inccc(limit_reg, 2*sizeof(jchar)); 3147 // annul LDUW if branch is not taken to prevent access past end of string 3148 __ br(Assembler::notZero, true, Assembler::pt, Lloop); //annul on taken 3149 __ delayed()->lduw(ary1_reg, limit_reg, chr1_reg); // hoisted 3150 3151 __ add(G0, 1, result_reg); // equals 3152 3153 __ bind(Ldone); 3154 %} 3155 3156 enc_class enc_rethrow() %{ 3157 cbuf.set_inst_mark(); 3158 Register temp_reg = G3; 3159 AddressLiteral rethrow_stub(OptoRuntime::rethrow_stub()); 3160 assert(temp_reg != reg_to_register_object(R_I0_num), "temp must not break oop_reg"); 3161 MacroAssembler _masm(&cbuf); 3162 #ifdef ASSERT 3163 __ save_frame(0); 3164 AddressLiteral last_rethrow_addrlit(&last_rethrow); 3165 __ sethi(last_rethrow_addrlit, L1); 3166 Address addr(L1, last_rethrow_addrlit.low10()); 3167 __ get_pc(L2); 3168 __ inc(L2, 3 * BytesPerInstWord); // skip this & 2 more insns to point at jump_to 3169 __ st_ptr(L2, addr); 3170 __ restore(); 3171 #endif 3172 __ JUMP(rethrow_stub, temp_reg, 0); // sethi;jmp 3173 __ delayed()->nop(); 3174 %} 3175 3176 enc_class emit_mem_nop() %{ 3177 // Generates the instruction LDUXA [o6,g0],#0x82,g0 3178 unsigned int *code = (unsigned int*)cbuf.code_end(); 3179 *code = (unsigned int)0xc0839040; 3180 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); 3181 %} 3182 3183 enc_class emit_fadd_nop() %{ 3184 // Generates the instruction FMOVS f31,f31 3185 unsigned int *code = (unsigned int*)cbuf.code_end(); 3186 *code = (unsigned int)0xbfa0003f; 3187 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); 3188 %} 3189 3190 enc_class emit_br_nop() %{ 3191 // Generates the instruction BPN,PN . 3192 unsigned int *code = (unsigned int*)cbuf.code_end(); 3193 *code = (unsigned int)0x00400000; 3194 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); 3195 %} 3196 3197 enc_class enc_membar_acquire %{ 3198 MacroAssembler _masm(&cbuf); 3199 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::LoadLoad) ); 3200 %} 3201 3202 enc_class enc_membar_release %{ 3203 MacroAssembler _masm(&cbuf); 3204 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::StoreStore) ); 3205 %} 3206 3207 enc_class enc_membar_volatile %{ 3208 MacroAssembler _masm(&cbuf); 3209 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad) ); 3210 %} 3211 3212 enc_class enc_repl8b( iRegI src, iRegL dst ) %{ 3213 MacroAssembler _masm(&cbuf); 3214 Register src_reg = reg_to_register_object($src$$reg); 3215 Register dst_reg = reg_to_register_object($dst$$reg); 3216 __ sllx(src_reg, 56, dst_reg); 3217 __ srlx(dst_reg, 8, O7); 3218 __ or3 (dst_reg, O7, dst_reg); 3219 __ srlx(dst_reg, 16, O7); 3220 __ or3 (dst_reg, O7, dst_reg); 3221 __ srlx(dst_reg, 32, O7); 3222 __ or3 (dst_reg, O7, dst_reg); 3223 %} 3224 3225 enc_class enc_repl4b( iRegI src, iRegL dst ) %{ 3226 MacroAssembler _masm(&cbuf); 3227 Register src_reg = reg_to_register_object($src$$reg); 3228 Register dst_reg = reg_to_register_object($dst$$reg); 3229 __ sll(src_reg, 24, dst_reg); 3230 __ srl(dst_reg, 8, O7); 3231 __ or3(dst_reg, O7, dst_reg); 3232 __ srl(dst_reg, 16, O7); 3233 __ or3(dst_reg, O7, dst_reg); 3234 %} 3235 3236 enc_class enc_repl4s( iRegI src, iRegL dst ) %{ 3237 MacroAssembler _masm(&cbuf); 3238 Register src_reg = reg_to_register_object($src$$reg); 3239 Register dst_reg = reg_to_register_object($dst$$reg); 3240 __ sllx(src_reg, 48, dst_reg); 3241 __ srlx(dst_reg, 16, O7); 3242 __ or3 (dst_reg, O7, dst_reg); 3243 __ srlx(dst_reg, 32, O7); 3244 __ or3 (dst_reg, O7, dst_reg); 3245 %} 3246 3247 enc_class enc_repl2i( iRegI src, iRegL dst ) %{ 3248 MacroAssembler _masm(&cbuf); 3249 Register src_reg = reg_to_register_object($src$$reg); 3250 Register dst_reg = reg_to_register_object($dst$$reg); 3251 __ sllx(src_reg, 32, dst_reg); 3252 __ srlx(dst_reg, 32, O7); 3253 __ or3 (dst_reg, O7, dst_reg); 3254 %} 3255 3256 %} 3257 3258 //----------FRAME-------------------------------------------------------------- 3259 // Definition of frame structure and management information. 3260 // 3261 // S T A C K L A Y O U T Allocators stack-slot number 3262 // | (to get allocators register number 3263 // G Owned by | | v add VMRegImpl::stack0) 3264 // r CALLER | | 3265 // o | +--------+ pad to even-align allocators stack-slot 3266 // w V | pad0 | numbers; owned by CALLER 3267 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned 3268 // h ^ | in | 5 3269 // | | args | 4 Holes in incoming args owned by SELF 3270 // | | | | 3 3271 // | | +--------+ 3272 // V | | old out| Empty on Intel, window on Sparc 3273 // | old |preserve| Must be even aligned. 3274 // | SP-+--------+----> Matcher::_old_SP, 8 (or 16 in LP64)-byte aligned 3275 // | | in | 3 area for Intel ret address 3276 // Owned by |preserve| Empty on Sparc. 3277 // SELF +--------+ 3278 // | | pad2 | 2 pad to align old SP 3279 // | +--------+ 1 3280 // | | locks | 0 3281 // | +--------+----> VMRegImpl::stack0, 8 (or 16 in LP64)-byte aligned 3282 // | | pad1 | 11 pad to align new SP 3283 // | +--------+ 3284 // | | | 10 3285 // | | spills | 9 spills 3286 // V | | 8 (pad0 slot for callee) 3287 // -----------+--------+----> Matcher::_out_arg_limit, unaligned 3288 // ^ | out | 7 3289 // | | args | 6 Holes in outgoing args owned by CALLEE 3290 // Owned by +--------+ 3291 // CALLEE | new out| 6 Empty on Intel, window on Sparc 3292 // | new |preserve| Must be even-aligned. 3293 // | SP-+--------+----> Matcher::_new_SP, even aligned 3294 // | | | 3295 // 3296 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is 3297 // known from SELF's arguments and the Java calling convention. 3298 // Region 6-7 is determined per call site. 3299 // Note 2: If the calling convention leaves holes in the incoming argument 3300 // area, those holes are owned by SELF. Holes in the outgoing area 3301 // are owned by the CALLEE. Holes should not be nessecary in the 3302 // incoming area, as the Java calling convention is completely under 3303 // the control of the AD file. Doubles can be sorted and packed to 3304 // avoid holes. Holes in the outgoing arguments may be nessecary for 3305 // varargs C calling conventions. 3306 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is 3307 // even aligned with pad0 as needed. 3308 // Region 6 is even aligned. Region 6-7 is NOT even aligned; 3309 // region 6-11 is even aligned; it may be padded out more so that 3310 // the region from SP to FP meets the minimum stack alignment. 3311 3312 frame %{ 3313 // What direction does stack grow in (assumed to be same for native & Java) 3314 stack_direction(TOWARDS_LOW); 3315 3316 // These two registers define part of the calling convention 3317 // between compiled code and the interpreter. 3318 inline_cache_reg(R_G5); // Inline Cache Register or methodOop for I2C 3319 interpreter_method_oop_reg(R_G5); // Method Oop Register when calling interpreter 3320 3321 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset] 3322 cisc_spilling_operand_name(indOffset); 3323 3324 // Number of stack slots consumed by a Monitor enter 3325 #ifdef _LP64 3326 sync_stack_slots(2); 3327 #else 3328 sync_stack_slots(1); 3329 #endif 3330 3331 // Compiled code's Frame Pointer 3332 frame_pointer(R_SP); 3333 3334 // Stack alignment requirement 3335 stack_alignment(StackAlignmentInBytes); 3336 // LP64: Alignment size in bytes (128-bit -> 16 bytes) 3337 // !LP64: Alignment size in bytes (64-bit -> 8 bytes) 3338 3339 // Number of stack slots between incoming argument block and the start of 3340 // a new frame. The PROLOG must add this many slots to the stack. The 3341 // EPILOG must remove this many slots. 3342 in_preserve_stack_slots(0); 3343 3344 // Number of outgoing stack slots killed above the out_preserve_stack_slots 3345 // for calls to C. Supports the var-args backing area for register parms. 3346 // ADLC doesn't support parsing expressions, so I folded the math by hand. 3347 #ifdef _LP64 3348 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (0)) * 2-stack-slots-per-word 3349 varargs_C_out_slots_killed(12); 3350 #else 3351 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (1)) * 1-stack-slots-per-word 3352 varargs_C_out_slots_killed( 7); 3353 #endif 3354 3355 // The after-PROLOG location of the return address. Location of 3356 // return address specifies a type (REG or STACK) and a number 3357 // representing the register number (i.e. - use a register name) or 3358 // stack slot. 3359 return_addr(REG R_I7); // Ret Addr is in register I7 3360 3361 // Body of function which returns an OptoRegs array locating 3362 // arguments either in registers or in stack slots for calling 3363 // java 3364 calling_convention %{ 3365 (void) SharedRuntime::java_calling_convention(sig_bt, regs, length, is_outgoing); 3366 3367 %} 3368 3369 // Body of function which returns an OptoRegs array locating 3370 // arguments either in registers or in stack slots for callin 3371 // C. 3372 c_calling_convention %{ 3373 // This is obviously always outgoing 3374 (void) SharedRuntime::c_calling_convention(sig_bt, regs, length); 3375 %} 3376 3377 // Location of native (C/C++) and interpreter return values. This is specified to 3378 // be the same as Java. In the 32-bit VM, long values are actually returned from 3379 // native calls in O0:O1 and returned to the interpreter in I0:I1. The copying 3380 // to and from the register pairs is done by the appropriate call and epilog 3381 // opcodes. This simplifies the register allocator. 3382 c_return_value %{ 3383 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" ); 3384 #ifdef _LP64 3385 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num }; 3386 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num}; 3387 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num }; 3388 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num}; 3389 #else // !_LP64 3390 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num }; 3391 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num }; 3392 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num }; 3393 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num }; 3394 #endif 3395 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg], 3396 (is_outgoing?lo_out:lo_in)[ideal_reg] ); 3397 %} 3398 3399 // Location of compiled Java return values. Same as C 3400 return_value %{ 3401 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" ); 3402 #ifdef _LP64 3403 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num }; 3404 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num}; 3405 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num }; 3406 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num}; 3407 #else // !_LP64 3408 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num }; 3409 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num}; 3410 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num }; 3411 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num}; 3412 #endif 3413 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg], 3414 (is_outgoing?lo_out:lo_in)[ideal_reg] ); 3415 %} 3416 3417 %} 3418 3419 3420 //----------ATTRIBUTES--------------------------------------------------------- 3421 //----------Operand Attributes------------------------------------------------- 3422 op_attrib op_cost(1); // Required cost attribute 3423 3424 //----------Instruction Attributes--------------------------------------------- 3425 ins_attrib ins_cost(DEFAULT_COST); // Required cost attribute 3426 ins_attrib ins_size(32); // Required size attribute (in bits) 3427 ins_attrib ins_pc_relative(0); // Required PC Relative flag 3428 ins_attrib ins_short_branch(0); // Required flag: is this instruction a 3429 // non-matching short branch variant of some 3430 // long branch? 3431 3432 //----------OPERANDS----------------------------------------------------------- 3433 // Operand definitions must precede instruction definitions for correct parsing 3434 // in the ADLC because operands constitute user defined types which are used in 3435 // instruction definitions. 3436 3437 //----------Simple Operands---------------------------------------------------- 3438 // Immediate Operands 3439 // Integer Immediate: 32-bit 3440 operand immI() %{ 3441 match(ConI); 3442 3443 op_cost(0); 3444 // formats are generated automatically for constants and base registers 3445 format %{ %} 3446 interface(CONST_INTER); 3447 %} 3448 3449 // Integer Immediate: 8-bit 3450 operand immI8() %{ 3451 predicate(Assembler::is_simm(n->get_int(), 8)); 3452 match(ConI); 3453 op_cost(0); 3454 format %{ %} 3455 interface(CONST_INTER); 3456 %} 3457 3458 // Integer Immediate: 13-bit 3459 operand immI13() %{ 3460 predicate(Assembler::is_simm13(n->get_int())); 3461 match(ConI); 3462 op_cost(0); 3463 3464 format %{ %} 3465 interface(CONST_INTER); 3466 %} 3467 3468 // Integer Immediate: 13-bit minus 7 3469 operand immI13m7() %{ 3470 predicate((-4096 < n->get_int()) && ((n->get_int() + 7) <= 4095)); 3471 match(ConI); 3472 op_cost(0); 3473 3474 format %{ %} 3475 interface(CONST_INTER); 3476 %} 3477 3478 // Integer Immediate: 16-bit 3479 operand immI16() %{ 3480 predicate(Assembler::is_simm(n->get_int(), 16)); 3481 match(ConI); 3482 op_cost(0); 3483 format %{ %} 3484 interface(CONST_INTER); 3485 %} 3486 3487 // Unsigned (positive) Integer Immediate: 13-bit 3488 operand immU13() %{ 3489 predicate((0 <= n->get_int()) && Assembler::is_simm13(n->get_int())); 3490 match(ConI); 3491 op_cost(0); 3492 3493 format %{ %} 3494 interface(CONST_INTER); 3495 %} 3496 3497 // Integer Immediate: 6-bit 3498 operand immU6() %{ 3499 predicate(n->get_int() >= 0 && n->get_int() <= 63); 3500 match(ConI); 3501 op_cost(0); 3502 format %{ %} 3503 interface(CONST_INTER); 3504 %} 3505 3506 // Integer Immediate: 11-bit 3507 operand immI11() %{ 3508 predicate(Assembler::is_simm(n->get_int(),11)); 3509 match(ConI); 3510 op_cost(0); 3511 format %{ %} 3512 interface(CONST_INTER); 3513 %} 3514 3515 // Integer Immediate: 0-bit 3516 operand immI0() %{ 3517 predicate(n->get_int() == 0); 3518 match(ConI); 3519 op_cost(0); 3520 3521 format %{ %} 3522 interface(CONST_INTER); 3523 %} 3524 3525 // Integer Immediate: the value 10 3526 operand immI10() %{ 3527 predicate(n->get_int() == 10); 3528 match(ConI); 3529 op_cost(0); 3530 3531 format %{ %} 3532 interface(CONST_INTER); 3533 %} 3534 3535 // Integer Immediate: the values 0-31 3536 operand immU5() %{ 3537 predicate(n->get_int() >= 0 && n->get_int() <= 31); 3538 match(ConI); 3539 op_cost(0); 3540 3541 format %{ %} 3542 interface(CONST_INTER); 3543 %} 3544 3545 // Integer Immediate: the values 1-31 3546 operand immI_1_31() %{ 3547 predicate(n->get_int() >= 1 && n->get_int() <= 31); 3548 match(ConI); 3549 op_cost(0); 3550 3551 format %{ %} 3552 interface(CONST_INTER); 3553 %} 3554 3555 // Integer Immediate: the values 32-63 3556 operand immI_32_63() %{ 3557 predicate(n->get_int() >= 32 && n->get_int() <= 63); 3558 match(ConI); 3559 op_cost(0); 3560 3561 format %{ %} 3562 interface(CONST_INTER); 3563 %} 3564 3565 // Immediates for special shifts (sign extend) 3566 3567 // Integer Immediate: the value 16 3568 operand immI_16() %{ 3569 predicate(n->get_int() == 16); 3570 match(ConI); 3571 op_cost(0); 3572 3573 format %{ %} 3574 interface(CONST_INTER); 3575 %} 3576 3577 // Integer Immediate: the value 24 3578 operand immI_24() %{ 3579 predicate(n->get_int() == 24); 3580 match(ConI); 3581 op_cost(0); 3582 3583 format %{ %} 3584 interface(CONST_INTER); 3585 %} 3586 3587 // Integer Immediate: the value 255 3588 operand immI_255() %{ 3589 predicate( n->get_int() == 255 ); 3590 match(ConI); 3591 op_cost(0); 3592 3593 format %{ %} 3594 interface(CONST_INTER); 3595 %} 3596 3597 // Integer Immediate: the value 65535 3598 operand immI_65535() %{ 3599 predicate(n->get_int() == 65535); 3600 match(ConI); 3601 op_cost(0); 3602 3603 format %{ %} 3604 interface(CONST_INTER); 3605 %} 3606 3607 // Long Immediate: the value FF 3608 operand immL_FF() %{ 3609 predicate( n->get_long() == 0xFFL ); 3610 match(ConL); 3611 op_cost(0); 3612 3613 format %{ %} 3614 interface(CONST_INTER); 3615 %} 3616 3617 // Long Immediate: the value FFFF 3618 operand immL_FFFF() %{ 3619 predicate( n->get_long() == 0xFFFFL ); 3620 match(ConL); 3621 op_cost(0); 3622 3623 format %{ %} 3624 interface(CONST_INTER); 3625 %} 3626 3627 // Pointer Immediate: 32 or 64-bit 3628 operand immP() %{ 3629 match(ConP); 3630 3631 op_cost(5); 3632 // formats are generated automatically for constants and base registers 3633 format %{ %} 3634 interface(CONST_INTER); 3635 %} 3636 3637 operand immP13() %{ 3638 predicate((-4096 < n->get_ptr()) && (n->get_ptr() <= 4095)); 3639 match(ConP); 3640 op_cost(0); 3641 3642 format %{ %} 3643 interface(CONST_INTER); 3644 %} 3645 3646 operand immP0() %{ 3647 predicate(n->get_ptr() == 0); 3648 match(ConP); 3649 op_cost(0); 3650 3651 format %{ %} 3652 interface(CONST_INTER); 3653 %} 3654 3655 operand immP_poll() %{ 3656 predicate(n->get_ptr() != 0 && n->get_ptr() == (intptr_t)os::get_polling_page()); 3657 match(ConP); 3658 3659 // formats are generated automatically for constants and base registers 3660 format %{ %} 3661 interface(CONST_INTER); 3662 %} 3663 3664 // Pointer Immediate 3665 operand immN() 3666 %{ 3667 match(ConN); 3668 3669 op_cost(10); 3670 format %{ %} 3671 interface(CONST_INTER); 3672 %} 3673 3674 // NULL Pointer Immediate 3675 operand immN0() 3676 %{ 3677 predicate(n->get_narrowcon() == 0); 3678 match(ConN); 3679 3680 op_cost(0); 3681 format %{ %} 3682 interface(CONST_INTER); 3683 %} 3684 3685 operand immL() %{ 3686 match(ConL); 3687 op_cost(40); 3688 // formats are generated automatically for constants and base registers 3689 format %{ %} 3690 interface(CONST_INTER); 3691 %} 3692 3693 operand immL0() %{ 3694 predicate(n->get_long() == 0L); 3695 match(ConL); 3696 op_cost(0); 3697 // formats are generated automatically for constants and base registers 3698 format %{ %} 3699 interface(CONST_INTER); 3700 %} 3701 3702 // Long Immediate: 13-bit 3703 operand immL13() %{ 3704 predicate((-4096L < n->get_long()) && (n->get_long() <= 4095L)); 3705 match(ConL); 3706 op_cost(0); 3707 3708 format %{ %} 3709 interface(CONST_INTER); 3710 %} 3711 3712 // Long Immediate: 13-bit minus 7 3713 operand immL13m7() %{ 3714 predicate((-4096L < n->get_long()) && ((n->get_long() + 7L) <= 4095L)); 3715 match(ConL); 3716 op_cost(0); 3717 3718 format %{ %} 3719 interface(CONST_INTER); 3720 %} 3721 3722 // Long Immediate: low 32-bit mask 3723 operand immL_32bits() %{ 3724 predicate(n->get_long() == 0xFFFFFFFFL); 3725 match(ConL); 3726 op_cost(0); 3727 3728 format %{ %} 3729 interface(CONST_INTER); 3730 %} 3731 3732 // Double Immediate 3733 operand immD() %{ 3734 match(ConD); 3735 3736 op_cost(40); 3737 format %{ %} 3738 interface(CONST_INTER); 3739 %} 3740 3741 operand immD0() %{ 3742 #ifdef _LP64 3743 // on 64-bit architectures this comparision is faster 3744 predicate(jlong_cast(n->getd()) == 0); 3745 #else 3746 predicate((n->getd() == 0) && (fpclass(n->getd()) == FP_PZERO)); 3747 #endif 3748 match(ConD); 3749 3750 op_cost(0); 3751 format %{ %} 3752 interface(CONST_INTER); 3753 %} 3754 3755 // Float Immediate 3756 operand immF() %{ 3757 match(ConF); 3758 3759 op_cost(20); 3760 format %{ %} 3761 interface(CONST_INTER); 3762 %} 3763 3764 // Float Immediate: 0 3765 operand immF0() %{ 3766 predicate((n->getf() == 0) && (fpclass(n->getf()) == FP_PZERO)); 3767 match(ConF); 3768 3769 op_cost(0); 3770 format %{ %} 3771 interface(CONST_INTER); 3772 %} 3773 3774 // Integer Register Operands 3775 // Integer Register 3776 operand iRegI() %{ 3777 constraint(ALLOC_IN_RC(int_reg)); 3778 match(RegI); 3779 3780 match(notemp_iRegI); 3781 match(g1RegI); 3782 match(o0RegI); 3783 match(iRegIsafe); 3784 3785 format %{ %} 3786 interface(REG_INTER); 3787 %} 3788 3789 operand notemp_iRegI() %{ 3790 constraint(ALLOC_IN_RC(notemp_int_reg)); 3791 match(RegI); 3792 3793 match(o0RegI); 3794 3795 format %{ %} 3796 interface(REG_INTER); 3797 %} 3798 3799 operand o0RegI() %{ 3800 constraint(ALLOC_IN_RC(o0_regI)); 3801 match(iRegI); 3802 3803 format %{ %} 3804 interface(REG_INTER); 3805 %} 3806 3807 // Pointer Register 3808 operand iRegP() %{ 3809 constraint(ALLOC_IN_RC(ptr_reg)); 3810 match(RegP); 3811 3812 match(lock_ptr_RegP); 3813 match(g1RegP); 3814 match(g2RegP); 3815 match(g3RegP); 3816 match(g4RegP); 3817 match(i0RegP); 3818 match(o0RegP); 3819 match(o1RegP); 3820 match(l7RegP); 3821 3822 format %{ %} 3823 interface(REG_INTER); 3824 %} 3825 3826 operand sp_ptr_RegP() %{ 3827 constraint(ALLOC_IN_RC(sp_ptr_reg)); 3828 match(RegP); 3829 match(iRegP); 3830 3831 format %{ %} 3832 interface(REG_INTER); 3833 %} 3834 3835 operand lock_ptr_RegP() %{ 3836 constraint(ALLOC_IN_RC(lock_ptr_reg)); 3837 match(RegP); 3838 match(i0RegP); 3839 match(o0RegP); 3840 match(o1RegP); 3841 match(l7RegP); 3842 3843 format %{ %} 3844 interface(REG_INTER); 3845 %} 3846 3847 operand g1RegP() %{ 3848 constraint(ALLOC_IN_RC(g1_regP)); 3849 match(iRegP); 3850 3851 format %{ %} 3852 interface(REG_INTER); 3853 %} 3854 3855 operand g2RegP() %{ 3856 constraint(ALLOC_IN_RC(g2_regP)); 3857 match(iRegP); 3858 3859 format %{ %} 3860 interface(REG_INTER); 3861 %} 3862 3863 operand g3RegP() %{ 3864 constraint(ALLOC_IN_RC(g3_regP)); 3865 match(iRegP); 3866 3867 format %{ %} 3868 interface(REG_INTER); 3869 %} 3870 3871 operand g1RegI() %{ 3872 constraint(ALLOC_IN_RC(g1_regI)); 3873 match(iRegI); 3874 3875 format %{ %} 3876 interface(REG_INTER); 3877 %} 3878 3879 operand g3RegI() %{ 3880 constraint(ALLOC_IN_RC(g3_regI)); 3881 match(iRegI); 3882 3883 format %{ %} 3884 interface(REG_INTER); 3885 %} 3886 3887 operand g4RegI() %{ 3888 constraint(ALLOC_IN_RC(g4_regI)); 3889 match(iRegI); 3890 3891 format %{ %} 3892 interface(REG_INTER); 3893 %} 3894 3895 operand g4RegP() %{ 3896 constraint(ALLOC_IN_RC(g4_regP)); 3897 match(iRegP); 3898 3899 format %{ %} 3900 interface(REG_INTER); 3901 %} 3902 3903 operand i0RegP() %{ 3904 constraint(ALLOC_IN_RC(i0_regP)); 3905 match(iRegP); 3906 3907 format %{ %} 3908 interface(REG_INTER); 3909 %} 3910 3911 operand o0RegP() %{ 3912 constraint(ALLOC_IN_RC(o0_regP)); 3913 match(iRegP); 3914 3915 format %{ %} 3916 interface(REG_INTER); 3917 %} 3918 3919 operand o1RegP() %{ 3920 constraint(ALLOC_IN_RC(o1_regP)); 3921 match(iRegP); 3922 3923 format %{ %} 3924 interface(REG_INTER); 3925 %} 3926 3927 operand o2RegP() %{ 3928 constraint(ALLOC_IN_RC(o2_regP)); 3929 match(iRegP); 3930 3931 format %{ %} 3932 interface(REG_INTER); 3933 %} 3934 3935 operand o7RegP() %{ 3936 constraint(ALLOC_IN_RC(o7_regP)); 3937 match(iRegP); 3938 3939 format %{ %} 3940 interface(REG_INTER); 3941 %} 3942 3943 operand l7RegP() %{ 3944 constraint(ALLOC_IN_RC(l7_regP)); 3945 match(iRegP); 3946 3947 format %{ %} 3948 interface(REG_INTER); 3949 %} 3950 3951 operand o7RegI() %{ 3952 constraint(ALLOC_IN_RC(o7_regI)); 3953 match(iRegI); 3954 3955 format %{ %} 3956 interface(REG_INTER); 3957 %} 3958 3959 operand iRegN() %{ 3960 constraint(ALLOC_IN_RC(int_reg)); 3961 match(RegN); 3962 3963 format %{ %} 3964 interface(REG_INTER); 3965 %} 3966 3967 // Long Register 3968 operand iRegL() %{ 3969 constraint(ALLOC_IN_RC(long_reg)); 3970 match(RegL); 3971 3972 format %{ %} 3973 interface(REG_INTER); 3974 %} 3975 3976 operand o2RegL() %{ 3977 constraint(ALLOC_IN_RC(o2_regL)); 3978 match(iRegL); 3979 3980 format %{ %} 3981 interface(REG_INTER); 3982 %} 3983 3984 operand o7RegL() %{ 3985 constraint(ALLOC_IN_RC(o7_regL)); 3986 match(iRegL); 3987 3988 format %{ %} 3989 interface(REG_INTER); 3990 %} 3991 3992 operand g1RegL() %{ 3993 constraint(ALLOC_IN_RC(g1_regL)); 3994 match(iRegL); 3995 3996 format %{ %} 3997 interface(REG_INTER); 3998 %} 3999 4000 operand g3RegL() %{ 4001 constraint(ALLOC_IN_RC(g3_regL)); 4002 match(iRegL); 4003 4004 format %{ %} 4005 interface(REG_INTER); 4006 %} 4007 4008 // Int Register safe 4009 // This is 64bit safe 4010 operand iRegIsafe() %{ 4011 constraint(ALLOC_IN_RC(long_reg)); 4012 4013 match(iRegI); 4014 4015 format %{ %} 4016 interface(REG_INTER); 4017 %} 4018 4019 // Condition Code Flag Register 4020 operand flagsReg() %{ 4021 constraint(ALLOC_IN_RC(int_flags)); 4022 match(RegFlags); 4023 4024 format %{ "ccr" %} // both ICC and XCC 4025 interface(REG_INTER); 4026 %} 4027 4028 // Condition Code Register, unsigned comparisons. 4029 operand flagsRegU() %{ 4030 constraint(ALLOC_IN_RC(int_flags)); 4031 match(RegFlags); 4032 4033 format %{ "icc_U" %} 4034 interface(REG_INTER); 4035 %} 4036 4037 // Condition Code Register, pointer comparisons. 4038 operand flagsRegP() %{ 4039 constraint(ALLOC_IN_RC(int_flags)); 4040 match(RegFlags); 4041 4042 #ifdef _LP64 4043 format %{ "xcc_P" %} 4044 #else 4045 format %{ "icc_P" %} 4046 #endif 4047 interface(REG_INTER); 4048 %} 4049 4050 // Condition Code Register, long comparisons. 4051 operand flagsRegL() %{ 4052 constraint(ALLOC_IN_RC(int_flags)); 4053 match(RegFlags); 4054 4055 format %{ "xcc_L" %} 4056 interface(REG_INTER); 4057 %} 4058 4059 // Condition Code Register, floating comparisons, unordered same as "less". 4060 operand flagsRegF() %{ 4061 constraint(ALLOC_IN_RC(float_flags)); 4062 match(RegFlags); 4063 match(flagsRegF0); 4064 4065 format %{ %} 4066 interface(REG_INTER); 4067 %} 4068 4069 operand flagsRegF0() %{ 4070 constraint(ALLOC_IN_RC(float_flag0)); 4071 match(RegFlags); 4072 4073 format %{ %} 4074 interface(REG_INTER); 4075 %} 4076 4077 4078 // Condition Code Flag Register used by long compare 4079 operand flagsReg_long_LTGE() %{ 4080 constraint(ALLOC_IN_RC(int_flags)); 4081 match(RegFlags); 4082 format %{ "icc_LTGE" %} 4083 interface(REG_INTER); 4084 %} 4085 operand flagsReg_long_EQNE() %{ 4086 constraint(ALLOC_IN_RC(int_flags)); 4087 match(RegFlags); 4088 format %{ "icc_EQNE" %} 4089 interface(REG_INTER); 4090 %} 4091 operand flagsReg_long_LEGT() %{ 4092 constraint(ALLOC_IN_RC(int_flags)); 4093 match(RegFlags); 4094 format %{ "icc_LEGT" %} 4095 interface(REG_INTER); 4096 %} 4097 4098 4099 operand regD() %{ 4100 constraint(ALLOC_IN_RC(dflt_reg)); 4101 match(RegD); 4102 4103 match(regD_low); 4104 4105 format %{ %} 4106 interface(REG_INTER); 4107 %} 4108 4109 operand regF() %{ 4110 constraint(ALLOC_IN_RC(sflt_reg)); 4111 match(RegF); 4112 4113 format %{ %} 4114 interface(REG_INTER); 4115 %} 4116 4117 operand regD_low() %{ 4118 constraint(ALLOC_IN_RC(dflt_low_reg)); 4119 match(regD); 4120 4121 format %{ %} 4122 interface(REG_INTER); 4123 %} 4124 4125 // Special Registers 4126 4127 // Method Register 4128 operand inline_cache_regP(iRegP reg) %{ 4129 constraint(ALLOC_IN_RC(g5_regP)); // G5=inline_cache_reg but uses 2 bits instead of 1 4130 match(reg); 4131 format %{ %} 4132 interface(REG_INTER); 4133 %} 4134 4135 operand interpreter_method_oop_regP(iRegP reg) %{ 4136 constraint(ALLOC_IN_RC(g5_regP)); // G5=interpreter_method_oop_reg but uses 2 bits instead of 1 4137 match(reg); 4138 format %{ %} 4139 interface(REG_INTER); 4140 %} 4141 4142 4143 //----------Complex Operands--------------------------------------------------- 4144 // Indirect Memory Reference 4145 operand indirect(sp_ptr_RegP reg) %{ 4146 constraint(ALLOC_IN_RC(sp_ptr_reg)); 4147 match(reg); 4148 4149 op_cost(100); 4150 format %{ "[$reg]" %} 4151 interface(MEMORY_INTER) %{ 4152 base($reg); 4153 index(0x0); 4154 scale(0x0); 4155 disp(0x0); 4156 %} 4157 %} 4158 4159 // Indirect with simm13 Offset 4160 operand indOffset13(sp_ptr_RegP reg, immX13 offset) %{ 4161 constraint(ALLOC_IN_RC(sp_ptr_reg)); 4162 match(AddP reg offset); 4163 4164 op_cost(100); 4165 format %{ "[$reg + $offset]" %} 4166 interface(MEMORY_INTER) %{ 4167 base($reg); 4168 index(0x0); 4169 scale(0x0); 4170 disp($offset); 4171 %} 4172 %} 4173 4174 // Indirect with simm13 Offset minus 7 4175 operand indOffset13m7(sp_ptr_RegP reg, immX13m7 offset) %{ 4176 constraint(ALLOC_IN_RC(sp_ptr_reg)); 4177 match(AddP reg offset); 4178 4179 op_cost(100); 4180 format %{ "[$reg + $offset]" %} 4181 interface(MEMORY_INTER) %{ 4182 base($reg); 4183 index(0x0); 4184 scale(0x0); 4185 disp($offset); 4186 %} 4187 %} 4188 4189 // Note: Intel has a swapped version also, like this: 4190 //operand indOffsetX(iRegI reg, immP offset) %{ 4191 // constraint(ALLOC_IN_RC(int_reg)); 4192 // match(AddP offset reg); 4193 // 4194 // op_cost(100); 4195 // format %{ "[$reg + $offset]" %} 4196 // interface(MEMORY_INTER) %{ 4197 // base($reg); 4198 // index(0x0); 4199 // scale(0x0); 4200 // disp($offset); 4201 // %} 4202 //%} 4203 //// However, it doesn't make sense for SPARC, since 4204 // we have no particularly good way to embed oops in 4205 // single instructions. 4206 4207 // Indirect with Register Index 4208 operand indIndex(iRegP addr, iRegX index) %{ 4209 constraint(ALLOC_IN_RC(ptr_reg)); 4210 match(AddP addr index); 4211 4212 op_cost(100); 4213 format %{ "[$addr + $index]" %} 4214 interface(MEMORY_INTER) %{ 4215 base($addr); 4216 index($index); 4217 scale(0x0); 4218 disp(0x0); 4219 %} 4220 %} 4221 4222 //----------Special Memory Operands-------------------------------------------- 4223 // Stack Slot Operand - This operand is used for loading and storing temporary 4224 // values on the stack where a match requires a value to 4225 // flow through memory. 4226 operand stackSlotI(sRegI reg) %{ 4227 constraint(ALLOC_IN_RC(stack_slots)); 4228 op_cost(100); 4229 //match(RegI); 4230 format %{ "[$reg]" %} 4231 interface(MEMORY_INTER) %{ 4232 base(0xE); // R_SP 4233 index(0x0); 4234 scale(0x0); 4235 disp($reg); // Stack Offset 4236 %} 4237 %} 4238 4239 operand stackSlotP(sRegP reg) %{ 4240 constraint(ALLOC_IN_RC(stack_slots)); 4241 op_cost(100); 4242 //match(RegP); 4243 format %{ "[$reg]" %} 4244 interface(MEMORY_INTER) %{ 4245 base(0xE); // R_SP 4246 index(0x0); 4247 scale(0x0); 4248 disp($reg); // Stack Offset 4249 %} 4250 %} 4251 4252 operand stackSlotF(sRegF reg) %{ 4253 constraint(ALLOC_IN_RC(stack_slots)); 4254 op_cost(100); 4255 //match(RegF); 4256 format %{ "[$reg]" %} 4257 interface(MEMORY_INTER) %{ 4258 base(0xE); // R_SP 4259 index(0x0); 4260 scale(0x0); 4261 disp($reg); // Stack Offset 4262 %} 4263 %} 4264 operand stackSlotD(sRegD reg) %{ 4265 constraint(ALLOC_IN_RC(stack_slots)); 4266 op_cost(100); 4267 //match(RegD); 4268 format %{ "[$reg]" %} 4269 interface(MEMORY_INTER) %{ 4270 base(0xE); // R_SP 4271 index(0x0); 4272 scale(0x0); 4273 disp($reg); // Stack Offset 4274 %} 4275 %} 4276 operand stackSlotL(sRegL reg) %{ 4277 constraint(ALLOC_IN_RC(stack_slots)); 4278 op_cost(100); 4279 //match(RegL); 4280 format %{ "[$reg]" %} 4281 interface(MEMORY_INTER) %{ 4282 base(0xE); // R_SP 4283 index(0x0); 4284 scale(0x0); 4285 disp($reg); // Stack Offset 4286 %} 4287 %} 4288 4289 // Operands for expressing Control Flow 4290 // NOTE: Label is a predefined operand which should not be redefined in 4291 // the AD file. It is generically handled within the ADLC. 4292 4293 //----------Conditional Branch Operands---------------------------------------- 4294 // Comparison Op - This is the operation of the comparison, and is limited to 4295 // the following set of codes: 4296 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=) 4297 // 4298 // Other attributes of the comparison, such as unsignedness, are specified 4299 // by the comparison instruction that sets a condition code flags register. 4300 // That result is represented by a flags operand whose subtype is appropriate 4301 // to the unsignedness (etc.) of the comparison. 4302 // 4303 // Later, the instruction which matches both the Comparison Op (a Bool) and 4304 // the flags (produced by the Cmp) specifies the coding of the comparison op 4305 // by matching a specific subtype of Bool operand below, such as cmpOpU. 4306 4307 operand cmpOp() %{ 4308 match(Bool); 4309 4310 format %{ "" %} 4311 interface(COND_INTER) %{ 4312 equal(0x1); 4313 not_equal(0x9); 4314 less(0x3); 4315 greater_equal(0xB); 4316 less_equal(0x2); 4317 greater(0xA); 4318 %} 4319 %} 4320 4321 // Comparison Op, unsigned 4322 operand cmpOpU() %{ 4323 match(Bool); 4324 4325 format %{ "u" %} 4326 interface(COND_INTER) %{ 4327 equal(0x1); 4328 not_equal(0x9); 4329 less(0x5); 4330 greater_equal(0xD); 4331 less_equal(0x4); 4332 greater(0xC); 4333 %} 4334 %} 4335 4336 // Comparison Op, pointer (same as unsigned) 4337 operand cmpOpP() %{ 4338 match(Bool); 4339 4340 format %{ "p" %} 4341 interface(COND_INTER) %{ 4342 equal(0x1); 4343 not_equal(0x9); 4344 less(0x5); 4345 greater_equal(0xD); 4346 less_equal(0x4); 4347 greater(0xC); 4348 %} 4349 %} 4350 4351 // Comparison Op, branch-register encoding 4352 operand cmpOp_reg() %{ 4353 match(Bool); 4354 4355 format %{ "" %} 4356 interface(COND_INTER) %{ 4357 equal (0x1); 4358 not_equal (0x5); 4359 less (0x3); 4360 greater_equal(0x7); 4361 less_equal (0x2); 4362 greater (0x6); 4363 %} 4364 %} 4365 4366 // Comparison Code, floating, unordered same as less 4367 operand cmpOpF() %{ 4368 match(Bool); 4369 4370 format %{ "fl" %} 4371 interface(COND_INTER) %{ 4372 equal(0x9); 4373 not_equal(0x1); 4374 less(0x3); 4375 greater_equal(0xB); 4376 less_equal(0xE); 4377 greater(0x6); 4378 %} 4379 %} 4380 4381 // Used by long compare 4382 operand cmpOp_commute() %{ 4383 match(Bool); 4384 4385 format %{ "" %} 4386 interface(COND_INTER) %{ 4387 equal(0x1); 4388 not_equal(0x9); 4389 less(0xA); 4390 greater_equal(0x2); 4391 less_equal(0xB); 4392 greater(0x3); 4393 %} 4394 %} 4395 4396 //----------OPERAND CLASSES---------------------------------------------------- 4397 // Operand Classes are groups of operands that are used to simplify 4398 // instruction definitions by not requiring the AD writer to specify separate 4399 // instructions for every form of operand when the instruction accepts 4400 // multiple operand types with the same basic encoding and format. The classic 4401 // case of this is memory operands. 4402 // Indirect is not included since its use is limited to Compare & Swap 4403 opclass memory( indirect, indOffset13, indIndex ); 4404 4405 //----------PIPELINE----------------------------------------------------------- 4406 pipeline %{ 4407 4408 //----------ATTRIBUTES--------------------------------------------------------- 4409 attributes %{ 4410 fixed_size_instructions; // Fixed size instructions 4411 branch_has_delay_slot; // Branch has delay slot following 4412 max_instructions_per_bundle = 4; // Up to 4 instructions per bundle 4413 instruction_unit_size = 4; // An instruction is 4 bytes long 4414 instruction_fetch_unit_size = 16; // The processor fetches one line 4415 instruction_fetch_units = 1; // of 16 bytes 4416 4417 // List of nop instructions 4418 nops( Nop_A0, Nop_A1, Nop_MS, Nop_FA, Nop_BR ); 4419 %} 4420 4421 //----------RESOURCES---------------------------------------------------------- 4422 // Resources are the functional units available to the machine 4423 resources(A0, A1, MS, BR, FA, FM, IDIV, FDIV, IALU = A0 | A1); 4424 4425 //----------PIPELINE DESCRIPTION----------------------------------------------- 4426 // Pipeline Description specifies the stages in the machine's pipeline 4427 4428 pipe_desc(A, P, F, B, I, J, S, R, E, C, M, W, X, T, D); 4429 4430 //----------PIPELINE CLASSES--------------------------------------------------- 4431 // Pipeline Classes describe the stages in which input and output are 4432 // referenced by the hardware pipeline. 4433 4434 // Integer ALU reg-reg operation 4435 pipe_class ialu_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 4436 single_instruction; 4437 dst : E(write); 4438 src1 : R(read); 4439 src2 : R(read); 4440 IALU : R; 4441 %} 4442 4443 // Integer ALU reg-reg long operation 4444 pipe_class ialu_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{ 4445 instruction_count(2); 4446 dst : E(write); 4447 src1 : R(read); 4448 src2 : R(read); 4449 IALU : R; 4450 IALU : R; 4451 %} 4452 4453 // Integer ALU reg-reg long dependent operation 4454 pipe_class ialu_reg_reg_2_dep(iRegL dst, iRegL src1, iRegL src2, flagsReg cr) %{ 4455 instruction_count(1); multiple_bundles; 4456 dst : E(write); 4457 src1 : R(read); 4458 src2 : R(read); 4459 cr : E(write); 4460 IALU : R(2); 4461 %} 4462 4463 // Integer ALU reg-imm operaion 4464 pipe_class ialu_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{ 4465 single_instruction; 4466 dst : E(write); 4467 src1 : R(read); 4468 IALU : R; 4469 %} 4470 4471 // Integer ALU reg-reg operation with condition code 4472 pipe_class ialu_cc_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{ 4473 single_instruction; 4474 dst : E(write); 4475 cr : E(write); 4476 src1 : R(read); 4477 src2 : R(read); 4478 IALU : R; 4479 %} 4480 4481 // Integer ALU reg-imm operation with condition code 4482 pipe_class ialu_cc_reg_imm(iRegI dst, iRegI src1, immI13 src2, flagsReg cr) %{ 4483 single_instruction; 4484 dst : E(write); 4485 cr : E(write); 4486 src1 : R(read); 4487 IALU : R; 4488 %} 4489 4490 // Integer ALU zero-reg operation 4491 pipe_class ialu_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{ 4492 single_instruction; 4493 dst : E(write); 4494 src2 : R(read); 4495 IALU : R; 4496 %} 4497 4498 // Integer ALU zero-reg operation with condition code only 4499 pipe_class ialu_cconly_zero_reg(flagsReg cr, iRegI src) %{ 4500 single_instruction; 4501 cr : E(write); 4502 src : R(read); 4503 IALU : R; 4504 %} 4505 4506 // Integer ALU reg-reg operation with condition code only 4507 pipe_class ialu_cconly_reg_reg(flagsReg cr, iRegI src1, iRegI src2) %{ 4508 single_instruction; 4509 cr : E(write); 4510 src1 : R(read); 4511 src2 : R(read); 4512 IALU : R; 4513 %} 4514 4515 // Integer ALU reg-imm operation with condition code only 4516 pipe_class ialu_cconly_reg_imm(flagsReg cr, iRegI src1, immI13 src2) %{ 4517 single_instruction; 4518 cr : E(write); 4519 src1 : R(read); 4520 IALU : R; 4521 %} 4522 4523 // Integer ALU reg-reg-zero operation with condition code only 4524 pipe_class ialu_cconly_reg_reg_zero(flagsReg cr, iRegI src1, iRegI src2, immI0 zero) %{ 4525 single_instruction; 4526 cr : E(write); 4527 src1 : R(read); 4528 src2 : R(read); 4529 IALU : R; 4530 %} 4531 4532 // Integer ALU reg-imm-zero operation with condition code only 4533 pipe_class ialu_cconly_reg_imm_zero(flagsReg cr, iRegI src1, immI13 src2, immI0 zero) %{ 4534 single_instruction; 4535 cr : E(write); 4536 src1 : R(read); 4537 IALU : R; 4538 %} 4539 4540 // Integer ALU reg-reg operation with condition code, src1 modified 4541 pipe_class ialu_cc_rwreg_reg(flagsReg cr, iRegI src1, iRegI src2) %{ 4542 single_instruction; 4543 cr : E(write); 4544 src1 : E(write); 4545 src1 : R(read); 4546 src2 : R(read); 4547 IALU : R; 4548 %} 4549 4550 // Integer ALU reg-imm operation with condition code, src1 modified 4551 pipe_class ialu_cc_rwreg_imm(flagsReg cr, iRegI src1, immI13 src2) %{ 4552 single_instruction; 4553 cr : E(write); 4554 src1 : E(write); 4555 src1 : R(read); 4556 IALU : R; 4557 %} 4558 4559 pipe_class cmpL_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg cr ) %{ 4560 multiple_bundles; 4561 dst : E(write)+4; 4562 cr : E(write); 4563 src1 : R(read); 4564 src2 : R(read); 4565 IALU : R(3); 4566 BR : R(2); 4567 %} 4568 4569 // Integer ALU operation 4570 pipe_class ialu_none(iRegI dst) %{ 4571 single_instruction; 4572 dst : E(write); 4573 IALU : R; 4574 %} 4575 4576 // Integer ALU reg operation 4577 pipe_class ialu_reg(iRegI dst, iRegI src) %{ 4578 single_instruction; may_have_no_code; 4579 dst : E(write); 4580 src : R(read); 4581 IALU : R; 4582 %} 4583 4584 // Integer ALU reg conditional operation 4585 // This instruction has a 1 cycle stall, and cannot execute 4586 // in the same cycle as the instruction setting the condition 4587 // code. We kludge this by pretending to read the condition code 4588 // 1 cycle earlier, and by marking the functional units as busy 4589 // for 2 cycles with the result available 1 cycle later than 4590 // is really the case. 4591 pipe_class ialu_reg_flags( iRegI op2_out, iRegI op2_in, iRegI op1, flagsReg cr ) %{ 4592 single_instruction; 4593 op2_out : C(write); 4594 op1 : R(read); 4595 cr : R(read); // This is really E, with a 1 cycle stall 4596 BR : R(2); 4597 MS : R(2); 4598 %} 4599 4600 #ifdef _LP64 4601 pipe_class ialu_clr_and_mover( iRegI dst, iRegP src ) %{ 4602 instruction_count(1); multiple_bundles; 4603 dst : C(write)+1; 4604 src : R(read)+1; 4605 IALU : R(1); 4606 BR : E(2); 4607 MS : E(2); 4608 %} 4609 #endif 4610 4611 // Integer ALU reg operation 4612 pipe_class ialu_move_reg_L_to_I(iRegI dst, iRegL src) %{ 4613 single_instruction; may_have_no_code; 4614 dst : E(write); 4615 src : R(read); 4616 IALU : R; 4617 %} 4618 pipe_class ialu_move_reg_I_to_L(iRegL dst, iRegI src) %{ 4619 single_instruction; may_have_no_code; 4620 dst : E(write); 4621 src : R(read); 4622 IALU : R; 4623 %} 4624 4625 // Two integer ALU reg operations 4626 pipe_class ialu_reg_2(iRegL dst, iRegL src) %{ 4627 instruction_count(2); 4628 dst : E(write); 4629 src : R(read); 4630 A0 : R; 4631 A1 : R; 4632 %} 4633 4634 // Two integer ALU reg operations 4635 pipe_class ialu_move_reg_L_to_L(iRegL dst, iRegL src) %{ 4636 instruction_count(2); may_have_no_code; 4637 dst : E(write); 4638 src : R(read); 4639 A0 : R; 4640 A1 : R; 4641 %} 4642 4643 // Integer ALU imm operation 4644 pipe_class ialu_imm(iRegI dst, immI13 src) %{ 4645 single_instruction; 4646 dst : E(write); 4647 IALU : R; 4648 %} 4649 4650 // Integer ALU reg-reg with carry operation 4651 pipe_class ialu_reg_reg_cy(iRegI dst, iRegI src1, iRegI src2, iRegI cy) %{ 4652 single_instruction; 4653 dst : E(write); 4654 src1 : R(read); 4655 src2 : R(read); 4656 IALU : R; 4657 %} 4658 4659 // Integer ALU cc operation 4660 pipe_class ialu_cc(iRegI dst, flagsReg cc) %{ 4661 single_instruction; 4662 dst : E(write); 4663 cc : R(read); 4664 IALU : R; 4665 %} 4666 4667 // Integer ALU cc / second IALU operation 4668 pipe_class ialu_reg_ialu( iRegI dst, iRegI src ) %{ 4669 instruction_count(1); multiple_bundles; 4670 dst : E(write)+1; 4671 src : R(read); 4672 IALU : R; 4673 %} 4674 4675 // Integer ALU cc / second IALU operation 4676 pipe_class ialu_reg_reg_ialu( iRegI dst, iRegI p, iRegI q ) %{ 4677 instruction_count(1); multiple_bundles; 4678 dst : E(write)+1; 4679 p : R(read); 4680 q : R(read); 4681 IALU : R; 4682 %} 4683 4684 // Integer ALU hi-lo-reg operation 4685 pipe_class ialu_hi_lo_reg(iRegI dst, immI src) %{ 4686 instruction_count(1); multiple_bundles; 4687 dst : E(write)+1; 4688 IALU : R(2); 4689 %} 4690 4691 // Float ALU hi-lo-reg operation (with temp) 4692 pipe_class ialu_hi_lo_reg_temp(regF dst, immF src, g3RegP tmp) %{ 4693 instruction_count(1); multiple_bundles; 4694 dst : E(write)+1; 4695 IALU : R(2); 4696 %} 4697 4698 // Long Constant 4699 pipe_class loadConL( iRegL dst, immL src ) %{ 4700 instruction_count(2); multiple_bundles; 4701 dst : E(write)+1; 4702 IALU : R(2); 4703 IALU : R(2); 4704 %} 4705 4706 // Pointer Constant 4707 pipe_class loadConP( iRegP dst, immP src ) %{ 4708 instruction_count(0); multiple_bundles; 4709 fixed_latency(6); 4710 %} 4711 4712 // Polling Address 4713 pipe_class loadConP_poll( iRegP dst, immP_poll src ) %{ 4714 #ifdef _LP64 4715 instruction_count(0); multiple_bundles; 4716 fixed_latency(6); 4717 #else 4718 dst : E(write); 4719 IALU : R; 4720 #endif 4721 %} 4722 4723 // Long Constant small 4724 pipe_class loadConLlo( iRegL dst, immL src ) %{ 4725 instruction_count(2); 4726 dst : E(write); 4727 IALU : R; 4728 IALU : R; 4729 %} 4730 4731 // [PHH] This is wrong for 64-bit. See LdImmF/D. 4732 pipe_class loadConFD(regF dst, immF src, g3RegP tmp) %{ 4733 instruction_count(1); multiple_bundles; 4734 src : R(read); 4735 dst : M(write)+1; 4736 IALU : R; 4737 MS : E; 4738 %} 4739 4740 // Integer ALU nop operation 4741 pipe_class ialu_nop() %{ 4742 single_instruction; 4743 IALU : R; 4744 %} 4745 4746 // Integer ALU nop operation 4747 pipe_class ialu_nop_A0() %{ 4748 single_instruction; 4749 A0 : R; 4750 %} 4751 4752 // Integer ALU nop operation 4753 pipe_class ialu_nop_A1() %{ 4754 single_instruction; 4755 A1 : R; 4756 %} 4757 4758 // Integer Multiply reg-reg operation 4759 pipe_class imul_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 4760 single_instruction; 4761 dst : E(write); 4762 src1 : R(read); 4763 src2 : R(read); 4764 MS : R(5); 4765 %} 4766 4767 // Integer Multiply reg-imm operation 4768 pipe_class imul_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{ 4769 single_instruction; 4770 dst : E(write); 4771 src1 : R(read); 4772 MS : R(5); 4773 %} 4774 4775 pipe_class mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 4776 single_instruction; 4777 dst : E(write)+4; 4778 src1 : R(read); 4779 src2 : R(read); 4780 MS : R(6); 4781 %} 4782 4783 pipe_class mulL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{ 4784 single_instruction; 4785 dst : E(write)+4; 4786 src1 : R(read); 4787 MS : R(6); 4788 %} 4789 4790 // Integer Divide reg-reg 4791 pipe_class sdiv_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI temp, flagsReg cr) %{ 4792 instruction_count(1); multiple_bundles; 4793 dst : E(write); 4794 temp : E(write); 4795 src1 : R(read); 4796 src2 : R(read); 4797 temp : R(read); 4798 MS : R(38); 4799 %} 4800 4801 // Integer Divide reg-imm 4802 pipe_class sdiv_reg_imm(iRegI dst, iRegI src1, immI13 src2, iRegI temp, flagsReg cr) %{ 4803 instruction_count(1); multiple_bundles; 4804 dst : E(write); 4805 temp : E(write); 4806 src1 : R(read); 4807 temp : R(read); 4808 MS : R(38); 4809 %} 4810 4811 // Long Divide 4812 pipe_class divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 4813 dst : E(write)+71; 4814 src1 : R(read); 4815 src2 : R(read)+1; 4816 MS : R(70); 4817 %} 4818 4819 pipe_class divL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{ 4820 dst : E(write)+71; 4821 src1 : R(read); 4822 MS : R(70); 4823 %} 4824 4825 // Floating Point Add Float 4826 pipe_class faddF_reg_reg(regF dst, regF src1, regF src2) %{ 4827 single_instruction; 4828 dst : X(write); 4829 src1 : E(read); 4830 src2 : E(read); 4831 FA : R; 4832 %} 4833 4834 // Floating Point Add Double 4835 pipe_class faddD_reg_reg(regD dst, regD src1, regD src2) %{ 4836 single_instruction; 4837 dst : X(write); 4838 src1 : E(read); 4839 src2 : E(read); 4840 FA : R; 4841 %} 4842 4843 // Floating Point Conditional Move based on integer flags 4844 pipe_class int_conditional_float_move (cmpOp cmp, flagsReg cr, regF dst, regF src) %{ 4845 single_instruction; 4846 dst : X(write); 4847 src : E(read); 4848 cr : R(read); 4849 FA : R(2); 4850 BR : R(2); 4851 %} 4852 4853 // Floating Point Conditional Move based on integer flags 4854 pipe_class int_conditional_double_move (cmpOp cmp, flagsReg cr, regD dst, regD src) %{ 4855 single_instruction; 4856 dst : X(write); 4857 src : E(read); 4858 cr : R(read); 4859 FA : R(2); 4860 BR : R(2); 4861 %} 4862 4863 // Floating Point Multiply Float 4864 pipe_class fmulF_reg_reg(regF dst, regF src1, regF src2) %{ 4865 single_instruction; 4866 dst : X(write); 4867 src1 : E(read); 4868 src2 : E(read); 4869 FM : R; 4870 %} 4871 4872 // Floating Point Multiply Double 4873 pipe_class fmulD_reg_reg(regD dst, regD src1, regD src2) %{ 4874 single_instruction; 4875 dst : X(write); 4876 src1 : E(read); 4877 src2 : E(read); 4878 FM : R; 4879 %} 4880 4881 // Floating Point Divide Float 4882 pipe_class fdivF_reg_reg(regF dst, regF src1, regF src2) %{ 4883 single_instruction; 4884 dst : X(write); 4885 src1 : E(read); 4886 src2 : E(read); 4887 FM : R; 4888 FDIV : C(14); 4889 %} 4890 4891 // Floating Point Divide Double 4892 pipe_class fdivD_reg_reg(regD dst, regD src1, regD src2) %{ 4893 single_instruction; 4894 dst : X(write); 4895 src1 : E(read); 4896 src2 : E(read); 4897 FM : R; 4898 FDIV : C(17); 4899 %} 4900 4901 // Floating Point Move/Negate/Abs Float 4902 pipe_class faddF_reg(regF dst, regF src) %{ 4903 single_instruction; 4904 dst : W(write); 4905 src : E(read); 4906 FA : R(1); 4907 %} 4908 4909 // Floating Point Move/Negate/Abs Double 4910 pipe_class faddD_reg(regD dst, regD src) %{ 4911 single_instruction; 4912 dst : W(write); 4913 src : E(read); 4914 FA : R; 4915 %} 4916 4917 // Floating Point Convert F->D 4918 pipe_class fcvtF2D(regD dst, regF src) %{ 4919 single_instruction; 4920 dst : X(write); 4921 src : E(read); 4922 FA : R; 4923 %} 4924 4925 // Floating Point Convert I->D 4926 pipe_class fcvtI2D(regD dst, regF src) %{ 4927 single_instruction; 4928 dst : X(write); 4929 src : E(read); 4930 FA : R; 4931 %} 4932 4933 // Floating Point Convert LHi->D 4934 pipe_class fcvtLHi2D(regD dst, regD src) %{ 4935 single_instruction; 4936 dst : X(write); 4937 src : E(read); 4938 FA : R; 4939 %} 4940 4941 // Floating Point Convert L->D 4942 pipe_class fcvtL2D(regD dst, regF src) %{ 4943 single_instruction; 4944 dst : X(write); 4945 src : E(read); 4946 FA : R; 4947 %} 4948 4949 // Floating Point Convert L->F 4950 pipe_class fcvtL2F(regD dst, regF src) %{ 4951 single_instruction; 4952 dst : X(write); 4953 src : E(read); 4954 FA : R; 4955 %} 4956 4957 // Floating Point Convert D->F 4958 pipe_class fcvtD2F(regD dst, regF src) %{ 4959 single_instruction; 4960 dst : X(write); 4961 src : E(read); 4962 FA : R; 4963 %} 4964 4965 // Floating Point Convert I->L 4966 pipe_class fcvtI2L(regD dst, regF src) %{ 4967 single_instruction; 4968 dst : X(write); 4969 src : E(read); 4970 FA : R; 4971 %} 4972 4973 // Floating Point Convert D->F 4974 pipe_class fcvtD2I(regF dst, regD src, flagsReg cr) %{ 4975 instruction_count(1); multiple_bundles; 4976 dst : X(write)+6; 4977 src : E(read); 4978 FA : R; 4979 %} 4980 4981 // Floating Point Convert D->L 4982 pipe_class fcvtD2L(regD dst, regD src, flagsReg cr) %{ 4983 instruction_count(1); multiple_bundles; 4984 dst : X(write)+6; 4985 src : E(read); 4986 FA : R; 4987 %} 4988 4989 // Floating Point Convert F->I 4990 pipe_class fcvtF2I(regF dst, regF src, flagsReg cr) %{ 4991 instruction_count(1); multiple_bundles; 4992 dst : X(write)+6; 4993 src : E(read); 4994 FA : R; 4995 %} 4996 4997 // Floating Point Convert F->L 4998 pipe_class fcvtF2L(regD dst, regF src, flagsReg cr) %{ 4999 instruction_count(1); multiple_bundles; 5000 dst : X(write)+6; 5001 src : E(read); 5002 FA : R; 5003 %} 5004 5005 // Floating Point Convert I->F 5006 pipe_class fcvtI2F(regF dst, regF src) %{ 5007 single_instruction; 5008 dst : X(write); 5009 src : E(read); 5010 FA : R; 5011 %} 5012 5013 // Floating Point Compare 5014 pipe_class faddF_fcc_reg_reg_zero(flagsRegF cr, regF src1, regF src2, immI0 zero) %{ 5015 single_instruction; 5016 cr : X(write); 5017 src1 : E(read); 5018 src2 : E(read); 5019 FA : R; 5020 %} 5021 5022 // Floating Point Compare 5023 pipe_class faddD_fcc_reg_reg_zero(flagsRegF cr, regD src1, regD src2, immI0 zero) %{ 5024 single_instruction; 5025 cr : X(write); 5026 src1 : E(read); 5027 src2 : E(read); 5028 FA : R; 5029 %} 5030 5031 // Floating Add Nop 5032 pipe_class fadd_nop() %{ 5033 single_instruction; 5034 FA : R; 5035 %} 5036 5037 // Integer Store to Memory 5038 pipe_class istore_mem_reg(memory mem, iRegI src) %{ 5039 single_instruction; 5040 mem : R(read); 5041 src : C(read); 5042 MS : R; 5043 %} 5044 5045 // Integer Store to Memory 5046 pipe_class istore_mem_spORreg(memory mem, sp_ptr_RegP src) %{ 5047 single_instruction; 5048 mem : R(read); 5049 src : C(read); 5050 MS : R; 5051 %} 5052 5053 // Integer Store Zero to Memory 5054 pipe_class istore_mem_zero(memory mem, immI0 src) %{ 5055 single_instruction; 5056 mem : R(read); 5057 MS : R; 5058 %} 5059 5060 // Special Stack Slot Store 5061 pipe_class istore_stk_reg(stackSlotI stkSlot, iRegI src) %{ 5062 single_instruction; 5063 stkSlot : R(read); 5064 src : C(read); 5065 MS : R; 5066 %} 5067 5068 // Special Stack Slot Store 5069 pipe_class lstoreI_stk_reg(stackSlotL stkSlot, iRegI src) %{ 5070 instruction_count(2); multiple_bundles; 5071 stkSlot : R(read); 5072 src : C(read); 5073 MS : R(2); 5074 %} 5075 5076 // Float Store 5077 pipe_class fstoreF_mem_reg(memory mem, RegF src) %{ 5078 single_instruction; 5079 mem : R(read); 5080 src : C(read); 5081 MS : R; 5082 %} 5083 5084 // Float Store 5085 pipe_class fstoreF_mem_zero(memory mem, immF0 src) %{ 5086 single_instruction; 5087 mem : R(read); 5088 MS : R; 5089 %} 5090 5091 // Double Store 5092 pipe_class fstoreD_mem_reg(memory mem, RegD src) %{ 5093 instruction_count(1); 5094 mem : R(read); 5095 src : C(read); 5096 MS : R; 5097 %} 5098 5099 // Double Store 5100 pipe_class fstoreD_mem_zero(memory mem, immD0 src) %{ 5101 single_instruction; 5102 mem : R(read); 5103 MS : R; 5104 %} 5105 5106 // Special Stack Slot Float Store 5107 pipe_class fstoreF_stk_reg(stackSlotI stkSlot, RegF src) %{ 5108 single_instruction; 5109 stkSlot : R(read); 5110 src : C(read); 5111 MS : R; 5112 %} 5113 5114 // Special Stack Slot Double Store 5115 pipe_class fstoreD_stk_reg(stackSlotI stkSlot, RegD src) %{ 5116 single_instruction; 5117 stkSlot : R(read); 5118 src : C(read); 5119 MS : R; 5120 %} 5121 5122 // Integer Load (when sign bit propagation not needed) 5123 pipe_class iload_mem(iRegI dst, memory mem) %{ 5124 single_instruction; 5125 mem : R(read); 5126 dst : C(write); 5127 MS : R; 5128 %} 5129 5130 // Integer Load from stack operand 5131 pipe_class iload_stkD(iRegI dst, stackSlotD mem ) %{ 5132 single_instruction; 5133 mem : R(read); 5134 dst : C(write); 5135 MS : R; 5136 %} 5137 5138 // Integer Load (when sign bit propagation or masking is needed) 5139 pipe_class iload_mask_mem(iRegI dst, memory mem) %{ 5140 single_instruction; 5141 mem : R(read); 5142 dst : M(write); 5143 MS : R; 5144 %} 5145 5146 // Float Load 5147 pipe_class floadF_mem(regF dst, memory mem) %{ 5148 single_instruction; 5149 mem : R(read); 5150 dst : M(write); 5151 MS : R; 5152 %} 5153 5154 // Float Load 5155 pipe_class floadD_mem(regD dst, memory mem) %{ 5156 instruction_count(1); multiple_bundles; // Again, unaligned argument is only multiple case 5157 mem : R(read); 5158 dst : M(write); 5159 MS : R; 5160 %} 5161 5162 // Float Load 5163 pipe_class floadF_stk(regF dst, stackSlotI stkSlot) %{ 5164 single_instruction; 5165 stkSlot : R(read); 5166 dst : M(write); 5167 MS : R; 5168 %} 5169 5170 // Float Load 5171 pipe_class floadD_stk(regD dst, stackSlotI stkSlot) %{ 5172 single_instruction; 5173 stkSlot : R(read); 5174 dst : M(write); 5175 MS : R; 5176 %} 5177 5178 // Memory Nop 5179 pipe_class mem_nop() %{ 5180 single_instruction; 5181 MS : R; 5182 %} 5183 5184 pipe_class sethi(iRegP dst, immI src) %{ 5185 single_instruction; 5186 dst : E(write); 5187 IALU : R; 5188 %} 5189 5190 pipe_class loadPollP(iRegP poll) %{ 5191 single_instruction; 5192 poll : R(read); 5193 MS : R; 5194 %} 5195 5196 pipe_class br(Universe br, label labl) %{ 5197 single_instruction_with_delay_slot; 5198 BR : R; 5199 %} 5200 5201 pipe_class br_cc(Universe br, cmpOp cmp, flagsReg cr, label labl) %{ 5202 single_instruction_with_delay_slot; 5203 cr : E(read); 5204 BR : R; 5205 %} 5206 5207 pipe_class br_reg(Universe br, cmpOp cmp, iRegI op1, label labl) %{ 5208 single_instruction_with_delay_slot; 5209 op1 : E(read); 5210 BR : R; 5211 MS : R; 5212 %} 5213 5214 pipe_class br_fcc(Universe br, cmpOpF cc, flagsReg cr, label labl) %{ 5215 single_instruction_with_delay_slot; 5216 cr : E(read); 5217 BR : R; 5218 %} 5219 5220 pipe_class br_nop() %{ 5221 single_instruction; 5222 BR : R; 5223 %} 5224 5225 pipe_class simple_call(method meth) %{ 5226 instruction_count(2); multiple_bundles; force_serialization; 5227 fixed_latency(100); 5228 BR : R(1); 5229 MS : R(1); 5230 A0 : R(1); 5231 %} 5232 5233 pipe_class compiled_call(method meth) %{ 5234 instruction_count(1); multiple_bundles; force_serialization; 5235 fixed_latency(100); 5236 MS : R(1); 5237 %} 5238 5239 pipe_class call(method meth) %{ 5240 instruction_count(0); multiple_bundles; force_serialization; 5241 fixed_latency(100); 5242 %} 5243 5244 pipe_class tail_call(Universe ignore, label labl) %{ 5245 single_instruction; has_delay_slot; 5246 fixed_latency(100); 5247 BR : R(1); 5248 MS : R(1); 5249 %} 5250 5251 pipe_class ret(Universe ignore) %{ 5252 single_instruction; has_delay_slot; 5253 BR : R(1); 5254 MS : R(1); 5255 %} 5256 5257 pipe_class ret_poll(g3RegP poll) %{ 5258 instruction_count(3); has_delay_slot; 5259 poll : E(read); 5260 MS : R; 5261 %} 5262 5263 // The real do-nothing guy 5264 pipe_class empty( ) %{ 5265 instruction_count(0); 5266 %} 5267 5268 pipe_class long_memory_op() %{ 5269 instruction_count(0); multiple_bundles; force_serialization; 5270 fixed_latency(25); 5271 MS : R(1); 5272 %} 5273 5274 // Check-cast 5275 pipe_class partial_subtype_check_pipe(Universe ignore, iRegP array, iRegP match ) %{ 5276 array : R(read); 5277 match : R(read); 5278 IALU : R(2); 5279 BR : R(2); 5280 MS : R; 5281 %} 5282 5283 // Convert FPU flags into +1,0,-1 5284 pipe_class floating_cmp( iRegI dst, regF src1, regF src2 ) %{ 5285 src1 : E(read); 5286 src2 : E(read); 5287 dst : E(write); 5288 FA : R; 5289 MS : R(2); 5290 BR : R(2); 5291 %} 5292 5293 // Compare for p < q, and conditionally add y 5294 pipe_class cadd_cmpltmask( iRegI p, iRegI q, iRegI y ) %{ 5295 p : E(read); 5296 q : E(read); 5297 y : E(read); 5298 IALU : R(3) 5299 %} 5300 5301 // Perform a compare, then move conditionally in a branch delay slot. 5302 pipe_class min_max( iRegI src2, iRegI srcdst ) %{ 5303 src2 : E(read); 5304 srcdst : E(read); 5305 IALU : R; 5306 BR : R; 5307 %} 5308 5309 // Define the class for the Nop node 5310 define %{ 5311 MachNop = ialu_nop; 5312 %} 5313 5314 %} 5315 5316 //----------INSTRUCTIONS------------------------------------------------------- 5317 5318 //------------Special Stack Slot instructions - no match rules----------------- 5319 instruct stkI_to_regF(regF dst, stackSlotI src) %{ 5320 // No match rule to avoid chain rule match. 5321 effect(DEF dst, USE src); 5322 ins_cost(MEMORY_REF_COST); 5323 size(4); 5324 format %{ "LDF $src,$dst\t! stkI to regF" %} 5325 opcode(Assembler::ldf_op3); 5326 ins_encode(simple_form3_mem_reg(src, dst)); 5327 ins_pipe(floadF_stk); 5328 %} 5329 5330 instruct stkL_to_regD(regD dst, stackSlotL src) %{ 5331 // No match rule to avoid chain rule match. 5332 effect(DEF dst, USE src); 5333 ins_cost(MEMORY_REF_COST); 5334 size(4); 5335 format %{ "LDDF $src,$dst\t! stkL to regD" %} 5336 opcode(Assembler::lddf_op3); 5337 ins_encode(simple_form3_mem_reg(src, dst)); 5338 ins_pipe(floadD_stk); 5339 %} 5340 5341 instruct regF_to_stkI(stackSlotI dst, regF src) %{ 5342 // No match rule to avoid chain rule match. 5343 effect(DEF dst, USE src); 5344 ins_cost(MEMORY_REF_COST); 5345 size(4); 5346 format %{ "STF $src,$dst\t! regF to stkI" %} 5347 opcode(Assembler::stf_op3); 5348 ins_encode(simple_form3_mem_reg(dst, src)); 5349 ins_pipe(fstoreF_stk_reg); 5350 %} 5351 5352 instruct regD_to_stkL(stackSlotL dst, regD src) %{ 5353 // No match rule to avoid chain rule match. 5354 effect(DEF dst, USE src); 5355 ins_cost(MEMORY_REF_COST); 5356 size(4); 5357 format %{ "STDF $src,$dst\t! regD to stkL" %} 5358 opcode(Assembler::stdf_op3); 5359 ins_encode(simple_form3_mem_reg(dst, src)); 5360 ins_pipe(fstoreD_stk_reg); 5361 %} 5362 5363 instruct regI_to_stkLHi(stackSlotL dst, iRegI src) %{ 5364 effect(DEF dst, USE src); 5365 ins_cost(MEMORY_REF_COST*2); 5366 size(8); 5367 format %{ "STW $src,$dst.hi\t! long\n\t" 5368 "STW R_G0,$dst.lo" %} 5369 opcode(Assembler::stw_op3); 5370 ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, R_G0)); 5371 ins_pipe(lstoreI_stk_reg); 5372 %} 5373 5374 instruct regL_to_stkD(stackSlotD dst, iRegL src) %{ 5375 // No match rule to avoid chain rule match. 5376 effect(DEF dst, USE src); 5377 ins_cost(MEMORY_REF_COST); 5378 size(4); 5379 format %{ "STX $src,$dst\t! regL to stkD" %} 5380 opcode(Assembler::stx_op3); 5381 ins_encode(simple_form3_mem_reg( dst, src ) ); 5382 ins_pipe(istore_stk_reg); 5383 %} 5384 5385 //---------- Chain stack slots between similar types -------- 5386 5387 // Load integer from stack slot 5388 instruct stkI_to_regI( iRegI dst, stackSlotI src ) %{ 5389 match(Set dst src); 5390 ins_cost(MEMORY_REF_COST); 5391 5392 size(4); 5393 format %{ "LDUW $src,$dst\t!stk" %} 5394 opcode(Assembler::lduw_op3); 5395 ins_encode(simple_form3_mem_reg( src, dst ) ); 5396 ins_pipe(iload_mem); 5397 %} 5398 5399 // Store integer to stack slot 5400 instruct regI_to_stkI( stackSlotI dst, iRegI src ) %{ 5401 match(Set dst src); 5402 ins_cost(MEMORY_REF_COST); 5403 5404 size(4); 5405 format %{ "STW $src,$dst\t!stk" %} 5406 opcode(Assembler::stw_op3); 5407 ins_encode(simple_form3_mem_reg( dst, src ) ); 5408 ins_pipe(istore_mem_reg); 5409 %} 5410 5411 // Load long from stack slot 5412 instruct stkL_to_regL( iRegL dst, stackSlotL src ) %{ 5413 match(Set dst src); 5414 5415 ins_cost(MEMORY_REF_COST); 5416 size(4); 5417 format %{ "LDX $src,$dst\t! long" %} 5418 opcode(Assembler::ldx_op3); 5419 ins_encode(simple_form3_mem_reg( src, dst ) ); 5420 ins_pipe(iload_mem); 5421 %} 5422 5423 // Store long to stack slot 5424 instruct regL_to_stkL(stackSlotL dst, iRegL src) %{ 5425 match(Set dst src); 5426 5427 ins_cost(MEMORY_REF_COST); 5428 size(4); 5429 format %{ "STX $src,$dst\t! long" %} 5430 opcode(Assembler::stx_op3); 5431 ins_encode(simple_form3_mem_reg( dst, src ) ); 5432 ins_pipe(istore_mem_reg); 5433 %} 5434 5435 #ifdef _LP64 5436 // Load pointer from stack slot, 64-bit encoding 5437 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{ 5438 match(Set dst src); 5439 ins_cost(MEMORY_REF_COST); 5440 size(4); 5441 format %{ "LDX $src,$dst\t!ptr" %} 5442 opcode(Assembler::ldx_op3); 5443 ins_encode(simple_form3_mem_reg( src, dst ) ); 5444 ins_pipe(iload_mem); 5445 %} 5446 5447 // Store pointer to stack slot 5448 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{ 5449 match(Set dst src); 5450 ins_cost(MEMORY_REF_COST); 5451 size(4); 5452 format %{ "STX $src,$dst\t!ptr" %} 5453 opcode(Assembler::stx_op3); 5454 ins_encode(simple_form3_mem_reg( dst, src ) ); 5455 ins_pipe(istore_mem_reg); 5456 %} 5457 #else // _LP64 5458 // Load pointer from stack slot, 32-bit encoding 5459 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{ 5460 match(Set dst src); 5461 ins_cost(MEMORY_REF_COST); 5462 format %{ "LDUW $src,$dst\t!ptr" %} 5463 opcode(Assembler::lduw_op3, Assembler::ldst_op); 5464 ins_encode(simple_form3_mem_reg( src, dst ) ); 5465 ins_pipe(iload_mem); 5466 %} 5467 5468 // Store pointer to stack slot 5469 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{ 5470 match(Set dst src); 5471 ins_cost(MEMORY_REF_COST); 5472 format %{ "STW $src,$dst\t!ptr" %} 5473 opcode(Assembler::stw_op3, Assembler::ldst_op); 5474 ins_encode(simple_form3_mem_reg( dst, src ) ); 5475 ins_pipe(istore_mem_reg); 5476 %} 5477 #endif // _LP64 5478 5479 //------------Special Nop instructions for bundling - no match rules----------- 5480 // Nop using the A0 functional unit 5481 instruct Nop_A0() %{ 5482 ins_cost(0); 5483 5484 format %{ "NOP ! Alu Pipeline" %} 5485 opcode(Assembler::or_op3, Assembler::arith_op); 5486 ins_encode( form2_nop() ); 5487 ins_pipe(ialu_nop_A0); 5488 %} 5489 5490 // Nop using the A1 functional unit 5491 instruct Nop_A1( ) %{ 5492 ins_cost(0); 5493 5494 format %{ "NOP ! Alu Pipeline" %} 5495 opcode(Assembler::or_op3, Assembler::arith_op); 5496 ins_encode( form2_nop() ); 5497 ins_pipe(ialu_nop_A1); 5498 %} 5499 5500 // Nop using the memory functional unit 5501 instruct Nop_MS( ) %{ 5502 ins_cost(0); 5503 5504 format %{ "NOP ! Memory Pipeline" %} 5505 ins_encode( emit_mem_nop ); 5506 ins_pipe(mem_nop); 5507 %} 5508 5509 // Nop using the floating add functional unit 5510 instruct Nop_FA( ) %{ 5511 ins_cost(0); 5512 5513 format %{ "NOP ! Floating Add Pipeline" %} 5514 ins_encode( emit_fadd_nop ); 5515 ins_pipe(fadd_nop); 5516 %} 5517 5518 // Nop using the branch functional unit 5519 instruct Nop_BR( ) %{ 5520 ins_cost(0); 5521 5522 format %{ "NOP ! Branch Pipeline" %} 5523 ins_encode( emit_br_nop ); 5524 ins_pipe(br_nop); 5525 %} 5526 5527 //----------Load/Store/Move Instructions--------------------------------------- 5528 //----------Load Instructions-------------------------------------------------- 5529 // Load Byte (8bit signed) 5530 instruct loadB(iRegI dst, memory mem) %{ 5531 match(Set dst (LoadB mem)); 5532 ins_cost(MEMORY_REF_COST); 5533 5534 size(4); 5535 format %{ "LDSB $mem,$dst\t! byte" %} 5536 ins_encode %{ 5537 __ ldsb($mem$$Address, $dst$$Register); 5538 %} 5539 ins_pipe(iload_mask_mem); 5540 %} 5541 5542 // Load Byte (8bit signed) into a Long Register 5543 instruct loadB2L(iRegL dst, memory mem) %{ 5544 match(Set dst (ConvI2L (LoadB mem))); 5545 ins_cost(MEMORY_REF_COST); 5546 5547 size(4); 5548 format %{ "LDSB $mem,$dst\t! byte -> long" %} 5549 ins_encode %{ 5550 __ ldsb($mem$$Address, $dst$$Register); 5551 %} 5552 ins_pipe(iload_mask_mem); 5553 %} 5554 5555 // Load Unsigned Byte (8bit UNsigned) into an int reg 5556 instruct loadUB(iRegI dst, memory mem) %{ 5557 match(Set dst (LoadUB mem)); 5558 ins_cost(MEMORY_REF_COST); 5559 5560 size(4); 5561 format %{ "LDUB $mem,$dst\t! ubyte" %} 5562 ins_encode %{ 5563 __ ldub($mem$$Address, $dst$$Register); 5564 %} 5565 ins_pipe(iload_mem); 5566 %} 5567 5568 // Load Unsigned Byte (8bit UNsigned) into a Long Register 5569 instruct loadUB2L(iRegL dst, memory mem) %{ 5570 match(Set dst (ConvI2L (LoadUB mem))); 5571 ins_cost(MEMORY_REF_COST); 5572 5573 size(4); 5574 format %{ "LDUB $mem,$dst\t! ubyte -> long" %} 5575 ins_encode %{ 5576 __ ldub($mem$$Address, $dst$$Register); 5577 %} 5578 ins_pipe(iload_mem); 5579 %} 5580 5581 // Load Unsigned Byte (8 bit UNsigned) with 8-bit mask into Long Register 5582 instruct loadUB2L_immI8(iRegL dst, memory mem, immI8 mask) %{ 5583 match(Set dst (ConvI2L (AndI (LoadUB mem) mask))); 5584 ins_cost(MEMORY_REF_COST + DEFAULT_COST); 5585 5586 size(2*4); 5587 format %{ "LDUB $mem,$dst\t# ubyte & 8-bit mask -> long\n\t" 5588 "AND $dst,$mask,$dst" %} 5589 ins_encode %{ 5590 __ ldub($mem$$Address, $dst$$Register); 5591 __ and3($dst$$Register, $mask$$constant, $dst$$Register); 5592 %} 5593 ins_pipe(iload_mem); 5594 %} 5595 5596 // Load Short (16bit signed) 5597 instruct loadS(iRegI dst, memory mem) %{ 5598 match(Set dst (LoadS mem)); 5599 ins_cost(MEMORY_REF_COST); 5600 5601 size(4); 5602 format %{ "LDSH $mem,$dst\t! short" %} 5603 ins_encode %{ 5604 __ ldsh($mem$$Address, $dst$$Register); 5605 %} 5606 ins_pipe(iload_mask_mem); 5607 %} 5608 5609 // Load Short (16 bit signed) to Byte (8 bit signed) 5610 instruct loadS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{ 5611 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour)); 5612 ins_cost(MEMORY_REF_COST); 5613 5614 size(4); 5615 5616 format %{ "LDSB $mem+1,$dst\t! short -> byte" %} 5617 ins_encode %{ 5618 __ ldsb($mem$$Address, $dst$$Register, 1); 5619 %} 5620 ins_pipe(iload_mask_mem); 5621 %} 5622 5623 // Load Short (16bit signed) into a Long Register 5624 instruct loadS2L(iRegL dst, memory mem) %{ 5625 match(Set dst (ConvI2L (LoadS mem))); 5626 ins_cost(MEMORY_REF_COST); 5627 5628 size(4); 5629 format %{ "LDSH $mem,$dst\t! short -> long" %} 5630 ins_encode %{ 5631 __ ldsh($mem$$Address, $dst$$Register); 5632 %} 5633 ins_pipe(iload_mask_mem); 5634 %} 5635 5636 // Load Unsigned Short/Char (16bit UNsigned) 5637 instruct loadUS(iRegI dst, memory mem) %{ 5638 match(Set dst (LoadUS mem)); 5639 ins_cost(MEMORY_REF_COST); 5640 5641 size(4); 5642 format %{ "LDUH $mem,$dst\t! ushort/char" %} 5643 ins_encode %{ 5644 __ lduh($mem$$Address, $dst$$Register); 5645 %} 5646 ins_pipe(iload_mem); 5647 %} 5648 5649 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed) 5650 instruct loadUS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{ 5651 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour)); 5652 ins_cost(MEMORY_REF_COST); 5653 5654 size(4); 5655 format %{ "LDSB $mem+1,$dst\t! ushort -> byte" %} 5656 ins_encode %{ 5657 __ ldsb($mem$$Address, $dst$$Register, 1); 5658 %} 5659 ins_pipe(iload_mask_mem); 5660 %} 5661 5662 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register 5663 instruct loadUS2L(iRegL dst, memory mem) %{ 5664 match(Set dst (ConvI2L (LoadUS mem))); 5665 ins_cost(MEMORY_REF_COST); 5666 5667 size(4); 5668 format %{ "LDUH $mem,$dst\t! ushort/char -> long" %} 5669 ins_encode %{ 5670 __ lduh($mem$$Address, $dst$$Register); 5671 %} 5672 ins_pipe(iload_mem); 5673 %} 5674 5675 // Load Unsigned Short/Char (16bit UNsigned) with mask 0xFF into a Long Register 5676 instruct loadUS2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{ 5677 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); 5678 ins_cost(MEMORY_REF_COST); 5679 5680 size(4); 5681 format %{ "LDUB $mem+1,$dst\t! ushort/char & 0xFF -> long" %} 5682 ins_encode %{ 5683 __ ldub($mem$$Address, $dst$$Register, 1); // LSB is index+1 on BE 5684 %} 5685 ins_pipe(iload_mem); 5686 %} 5687 5688 // Load Unsigned Short/Char (16bit UNsigned) with a 13-bit mask into a Long Register 5689 instruct loadUS2L_immI13(iRegL dst, memory mem, immI13 mask) %{ 5690 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); 5691 ins_cost(MEMORY_REF_COST + DEFAULT_COST); 5692 5693 size(2*4); 5694 format %{ "LDUH $mem,$dst\t! ushort/char & 13-bit mask -> long\n\t" 5695 "AND $dst,$mask,$dst" %} 5696 ins_encode %{ 5697 Register Rdst = $dst$$Register; 5698 __ lduh($mem$$Address, Rdst); 5699 __ and3(Rdst, $mask$$constant, Rdst); 5700 %} 5701 ins_pipe(iload_mem); 5702 %} 5703 5704 // Load Unsigned Short/Char (16bit UNsigned) with a 16-bit mask into a Long Register 5705 instruct loadUS2L_immI16(iRegL dst, memory mem, immI16 mask, iRegL tmp) %{ 5706 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); 5707 effect(TEMP dst, TEMP tmp); 5708 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST); 5709 5710 size(3*4); 5711 format %{ "LDUH $mem,$dst\t! ushort/char & 16-bit mask -> long\n\t" 5712 "SET $mask,$tmp\n\t" 5713 "AND $dst,$tmp,$dst" %} 5714 ins_encode %{ 5715 Register Rdst = $dst$$Register; 5716 Register Rtmp = $tmp$$Register; 5717 __ lduh($mem$$Address, Rdst); 5718 __ set($mask$$constant, Rtmp); 5719 __ and3(Rdst, Rtmp, Rdst); 5720 %} 5721 ins_pipe(iload_mem); 5722 %} 5723 5724 // Load Integer 5725 instruct loadI(iRegI dst, memory mem) %{ 5726 match(Set dst (LoadI mem)); 5727 ins_cost(MEMORY_REF_COST); 5728 5729 size(4); 5730 format %{ "LDUW $mem,$dst\t! int" %} 5731 ins_encode %{ 5732 __ lduw($mem$$Address, $dst$$Register); 5733 %} 5734 ins_pipe(iload_mem); 5735 %} 5736 5737 // Load Integer to Byte (8 bit signed) 5738 instruct loadI2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{ 5739 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour)); 5740 ins_cost(MEMORY_REF_COST); 5741 5742 size(4); 5743 5744 format %{ "LDSB $mem+3,$dst\t! int -> byte" %} 5745 ins_encode %{ 5746 __ ldsb($mem$$Address, $dst$$Register, 3); 5747 %} 5748 ins_pipe(iload_mask_mem); 5749 %} 5750 5751 // Load Integer to Unsigned Byte (8 bit UNsigned) 5752 instruct loadI2UB(iRegI dst, indOffset13m7 mem, immI_255 mask) %{ 5753 match(Set dst (AndI (LoadI mem) mask)); 5754 ins_cost(MEMORY_REF_COST); 5755 5756 size(4); 5757 5758 format %{ "LDUB $mem+3,$dst\t! int -> ubyte" %} 5759 ins_encode %{ 5760 __ ldub($mem$$Address, $dst$$Register, 3); 5761 %} 5762 ins_pipe(iload_mask_mem); 5763 %} 5764 5765 // Load Integer to Short (16 bit signed) 5766 instruct loadI2S(iRegI dst, indOffset13m7 mem, immI_16 sixteen) %{ 5767 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen)); 5768 ins_cost(MEMORY_REF_COST); 5769 5770 size(4); 5771 5772 format %{ "LDSH $mem+2,$dst\t! int -> short" %} 5773 ins_encode %{ 5774 __ ldsh($mem$$Address, $dst$$Register, 2); 5775 %} 5776 ins_pipe(iload_mask_mem); 5777 %} 5778 5779 // Load Integer to Unsigned Short (16 bit UNsigned) 5780 instruct loadI2US(iRegI dst, indOffset13m7 mem, immI_65535 mask) %{ 5781 match(Set dst (AndI (LoadI mem) mask)); 5782 ins_cost(MEMORY_REF_COST); 5783 5784 size(4); 5785 5786 format %{ "LDUH $mem+2,$dst\t! int -> ushort/char" %} 5787 ins_encode %{ 5788 __ lduh($mem$$Address, $dst$$Register, 2); 5789 %} 5790 ins_pipe(iload_mask_mem); 5791 %} 5792 5793 // Load Integer into a Long Register 5794 instruct loadI2L(iRegL dst, memory mem) %{ 5795 match(Set dst (ConvI2L (LoadI mem))); 5796 ins_cost(MEMORY_REF_COST); 5797 5798 size(4); 5799 format %{ "LDSW $mem,$dst\t! int -> long" %} 5800 ins_encode %{ 5801 __ ldsw($mem$$Address, $dst$$Register); 5802 %} 5803 ins_pipe(iload_mask_mem); 5804 %} 5805 5806 // Load Integer with mask 0xFF into a Long Register 5807 instruct loadI2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{ 5808 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); 5809 ins_cost(MEMORY_REF_COST); 5810 5811 size(4); 5812 format %{ "LDUB $mem+3,$dst\t! int & 0xFF -> long" %} 5813 ins_encode %{ 5814 __ ldub($mem$$Address, $dst$$Register, 3); // LSB is index+3 on BE 5815 %} 5816 ins_pipe(iload_mem); 5817 %} 5818 5819 // Load Integer with mask 0xFFFF into a Long Register 5820 instruct loadI2L_immI_65535(iRegL dst, indOffset13m7 mem, immI_65535 mask) %{ 5821 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); 5822 ins_cost(MEMORY_REF_COST); 5823 5824 size(4); 5825 format %{ "LDUH $mem+2,$dst\t! int & 0xFFFF -> long" %} 5826 ins_encode %{ 5827 __ lduh($mem$$Address, $dst$$Register, 2); // LSW is index+2 on BE 5828 %} 5829 ins_pipe(iload_mem); 5830 %} 5831 5832 // Load Integer with a 13-bit mask into a Long Register 5833 instruct loadI2L_immI13(iRegL dst, memory mem, immI13 mask) %{ 5834 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); 5835 ins_cost(MEMORY_REF_COST + DEFAULT_COST); 5836 5837 size(2*4); 5838 format %{ "LDUW $mem,$dst\t! int & 13-bit mask -> long\n\t" 5839 "AND $dst,$mask,$dst" %} 5840 ins_encode %{ 5841 Register Rdst = $dst$$Register; 5842 __ lduw($mem$$Address, Rdst); 5843 __ and3(Rdst, $mask$$constant, Rdst); 5844 %} 5845 ins_pipe(iload_mem); 5846 %} 5847 5848 // Load Integer with a 32-bit mask into a Long Register 5849 instruct loadI2L_immI(iRegL dst, memory mem, immI mask, iRegL tmp) %{ 5850 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); 5851 effect(TEMP dst, TEMP tmp); 5852 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST); 5853 5854 size(3*4); 5855 format %{ "LDUW $mem,$dst\t! int & 32-bit mask -> long\n\t" 5856 "SET $mask,$tmp\n\t" 5857 "AND $dst,$tmp,$dst" %} 5858 ins_encode %{ 5859 Register Rdst = $dst$$Register; 5860 Register Rtmp = $tmp$$Register; 5861 __ lduw($mem$$Address, Rdst); 5862 __ set($mask$$constant, Rtmp); 5863 __ and3(Rdst, Rtmp, Rdst); 5864 %} 5865 ins_pipe(iload_mem); 5866 %} 5867 5868 // Load Unsigned Integer into a Long Register 5869 instruct loadUI2L(iRegL dst, memory mem) %{ 5870 match(Set dst (LoadUI2L mem)); 5871 ins_cost(MEMORY_REF_COST); 5872 5873 size(4); 5874 format %{ "LDUW $mem,$dst\t! uint -> long" %} 5875 ins_encode %{ 5876 __ lduw($mem$$Address, $dst$$Register); 5877 %} 5878 ins_pipe(iload_mem); 5879 %} 5880 5881 // Load Long - aligned 5882 instruct loadL(iRegL dst, memory mem ) %{ 5883 match(Set dst (LoadL mem)); 5884 ins_cost(MEMORY_REF_COST); 5885 5886 size(4); 5887 format %{ "LDX $mem,$dst\t! long" %} 5888 ins_encode %{ 5889 __ ldx($mem$$Address, $dst$$Register); 5890 %} 5891 ins_pipe(iload_mem); 5892 %} 5893 5894 // Load Long - UNaligned 5895 instruct loadL_unaligned(iRegL dst, memory mem, o7RegI tmp) %{ 5896 match(Set dst (LoadL_unaligned mem)); 5897 effect(KILL tmp); 5898 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST); 5899 size(16); 5900 format %{ "LDUW $mem+4,R_O7\t! misaligned long\n" 5901 "\tLDUW $mem ,$dst\n" 5902 "\tSLLX #32, $dst, $dst\n" 5903 "\tOR $dst, R_O7, $dst" %} 5904 opcode(Assembler::lduw_op3); 5905 ins_encode(form3_mem_reg_long_unaligned_marshal( mem, dst )); 5906 ins_pipe(iload_mem); 5907 %} 5908 5909 // Load Aligned Packed Byte into a Double Register 5910 instruct loadA8B(regD dst, memory mem) %{ 5911 match(Set dst (Load8B mem)); 5912 ins_cost(MEMORY_REF_COST); 5913 size(4); 5914 format %{ "LDDF $mem,$dst\t! packed8B" %} 5915 opcode(Assembler::lddf_op3); 5916 ins_encode(simple_form3_mem_reg( mem, dst ) ); 5917 ins_pipe(floadD_mem); 5918 %} 5919 5920 // Load Aligned Packed Char into a Double Register 5921 instruct loadA4C(regD dst, memory mem) %{ 5922 match(Set dst (Load4C mem)); 5923 ins_cost(MEMORY_REF_COST); 5924 size(4); 5925 format %{ "LDDF $mem,$dst\t! packed4C" %} 5926 opcode(Assembler::lddf_op3); 5927 ins_encode(simple_form3_mem_reg( mem, dst ) ); 5928 ins_pipe(floadD_mem); 5929 %} 5930 5931 // Load Aligned Packed Short into a Double Register 5932 instruct loadA4S(regD dst, memory mem) %{ 5933 match(Set dst (Load4S mem)); 5934 ins_cost(MEMORY_REF_COST); 5935 size(4); 5936 format %{ "LDDF $mem,$dst\t! packed4S" %} 5937 opcode(Assembler::lddf_op3); 5938 ins_encode(simple_form3_mem_reg( mem, dst ) ); 5939 ins_pipe(floadD_mem); 5940 %} 5941 5942 // Load Aligned Packed Int into a Double Register 5943 instruct loadA2I(regD dst, memory mem) %{ 5944 match(Set dst (Load2I mem)); 5945 ins_cost(MEMORY_REF_COST); 5946 size(4); 5947 format %{ "LDDF $mem,$dst\t! packed2I" %} 5948 opcode(Assembler::lddf_op3); 5949 ins_encode(simple_form3_mem_reg( mem, dst ) ); 5950 ins_pipe(floadD_mem); 5951 %} 5952 5953 // Load Range 5954 instruct loadRange(iRegI dst, memory mem) %{ 5955 match(Set dst (LoadRange mem)); 5956 ins_cost(MEMORY_REF_COST); 5957 5958 size(4); 5959 format %{ "LDUW $mem,$dst\t! range" %} 5960 opcode(Assembler::lduw_op3); 5961 ins_encode(simple_form3_mem_reg( mem, dst ) ); 5962 ins_pipe(iload_mem); 5963 %} 5964 5965 // Load Integer into %f register (for fitos/fitod) 5966 instruct loadI_freg(regF dst, memory mem) %{ 5967 match(Set dst (LoadI mem)); 5968 ins_cost(MEMORY_REF_COST); 5969 size(4); 5970 5971 format %{ "LDF $mem,$dst\t! for fitos/fitod" %} 5972 opcode(Assembler::ldf_op3); 5973 ins_encode(simple_form3_mem_reg( mem, dst ) ); 5974 ins_pipe(floadF_mem); 5975 %} 5976 5977 // Load Pointer 5978 instruct loadP(iRegP dst, memory mem) %{ 5979 match(Set dst (LoadP mem)); 5980 ins_cost(MEMORY_REF_COST); 5981 size(4); 5982 5983 #ifndef _LP64 5984 format %{ "LDUW $mem,$dst\t! ptr" %} 5985 ins_encode %{ 5986 __ lduw($mem$$Address, $dst$$Register); 5987 %} 5988 #else 5989 format %{ "LDX $mem,$dst\t! ptr" %} 5990 ins_encode %{ 5991 __ ldx($mem$$Address, $dst$$Register); 5992 %} 5993 #endif 5994 ins_pipe(iload_mem); 5995 %} 5996 5997 // Load Compressed Pointer 5998 instruct loadN(iRegN dst, memory mem) %{ 5999 match(Set dst (LoadN mem)); 6000 ins_cost(MEMORY_REF_COST); 6001 size(4); 6002 6003 format %{ "LDUW $mem,$dst\t! compressed ptr" %} 6004 ins_encode %{ 6005 __ lduw($mem$$Address, $dst$$Register); 6006 %} 6007 ins_pipe(iload_mem); 6008 %} 6009 6010 // Load Klass Pointer 6011 instruct loadKlass(iRegP dst, memory mem) %{ 6012 match(Set dst (LoadKlass mem)); 6013 ins_cost(MEMORY_REF_COST); 6014 size(4); 6015 6016 #ifndef _LP64 6017 format %{ "LDUW $mem,$dst\t! klass ptr" %} 6018 ins_encode %{ 6019 __ lduw($mem$$Address, $dst$$Register); 6020 %} 6021 #else 6022 format %{ "LDX $mem,$dst\t! klass ptr" %} 6023 ins_encode %{ 6024 __ ldx($mem$$Address, $dst$$Register); 6025 %} 6026 #endif 6027 ins_pipe(iload_mem); 6028 %} 6029 6030 // Load narrow Klass Pointer 6031 instruct loadNKlass(iRegN dst, memory mem) %{ 6032 match(Set dst (LoadNKlass mem)); 6033 ins_cost(MEMORY_REF_COST); 6034 size(4); 6035 6036 format %{ "LDUW $mem,$dst\t! compressed klass ptr" %} 6037 ins_encode %{ 6038 __ lduw($mem$$Address, $dst$$Register); 6039 %} 6040 ins_pipe(iload_mem); 6041 %} 6042 6043 // Load Double 6044 instruct loadD(regD dst, memory mem) %{ 6045 match(Set dst (LoadD mem)); 6046 ins_cost(MEMORY_REF_COST); 6047 6048 size(4); 6049 format %{ "LDDF $mem,$dst" %} 6050 opcode(Assembler::lddf_op3); 6051 ins_encode(simple_form3_mem_reg( mem, dst ) ); 6052 ins_pipe(floadD_mem); 6053 %} 6054 6055 // Load Double - UNaligned 6056 instruct loadD_unaligned(regD_low dst, memory mem ) %{ 6057 match(Set dst (LoadD_unaligned mem)); 6058 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST); 6059 size(8); 6060 format %{ "LDF $mem ,$dst.hi\t! misaligned double\n" 6061 "\tLDF $mem+4,$dst.lo\t!" %} 6062 opcode(Assembler::ldf_op3); 6063 ins_encode( form3_mem_reg_double_unaligned( mem, dst )); 6064 ins_pipe(iload_mem); 6065 %} 6066 6067 // Load Float 6068 instruct loadF(regF dst, memory mem) %{ 6069 match(Set dst (LoadF mem)); 6070 ins_cost(MEMORY_REF_COST); 6071 6072 size(4); 6073 format %{ "LDF $mem,$dst" %} 6074 opcode(Assembler::ldf_op3); 6075 ins_encode(simple_form3_mem_reg( mem, dst ) ); 6076 ins_pipe(floadF_mem); 6077 %} 6078 6079 // Load Constant 6080 instruct loadConI( iRegI dst, immI src ) %{ 6081 match(Set dst src); 6082 ins_cost(DEFAULT_COST * 3/2); 6083 format %{ "SET $src,$dst" %} 6084 ins_encode( Set32(src, dst) ); 6085 ins_pipe(ialu_hi_lo_reg); 6086 %} 6087 6088 instruct loadConI13( iRegI dst, immI13 src ) %{ 6089 match(Set dst src); 6090 6091 size(4); 6092 format %{ "MOV $src,$dst" %} 6093 ins_encode( Set13( src, dst ) ); 6094 ins_pipe(ialu_imm); 6095 %} 6096 6097 instruct loadConP(iRegP dst, immP src) %{ 6098 match(Set dst src); 6099 ins_cost(DEFAULT_COST * 3/2); 6100 format %{ "SET $src,$dst\t!ptr" %} 6101 // This rule does not use "expand" unlike loadConI because then 6102 // the result type is not known to be an Oop. An ADLC 6103 // enhancement will be needed to make that work - not worth it! 6104 6105 ins_encode( SetPtr( src, dst ) ); 6106 ins_pipe(loadConP); 6107 6108 %} 6109 6110 instruct loadConP0(iRegP dst, immP0 src) %{ 6111 match(Set dst src); 6112 6113 size(4); 6114 format %{ "CLR $dst\t!ptr" %} 6115 ins_encode( SetNull( dst ) ); 6116 ins_pipe(ialu_imm); 6117 %} 6118 6119 instruct loadConP_poll(iRegP dst, immP_poll src) %{ 6120 match(Set dst src); 6121 ins_cost(DEFAULT_COST); 6122 format %{ "SET $src,$dst\t!ptr" %} 6123 ins_encode %{ 6124 AddressLiteral polling_page(os::get_polling_page()); 6125 __ sethi(polling_page, reg_to_register_object($dst$$reg)); 6126 %} 6127 ins_pipe(loadConP_poll); 6128 %} 6129 6130 instruct loadConN0(iRegN dst, immN0 src) %{ 6131 match(Set dst src); 6132 6133 size(4); 6134 format %{ "CLR $dst\t! compressed NULL ptr" %} 6135 ins_encode( SetNull( dst ) ); 6136 ins_pipe(ialu_imm); 6137 %} 6138 6139 instruct loadConN(iRegN dst, immN src) %{ 6140 match(Set dst src); 6141 ins_cost(DEFAULT_COST * 3/2); 6142 format %{ "SET $src,$dst\t! compressed ptr" %} 6143 ins_encode %{ 6144 Register dst = $dst$$Register; 6145 __ set_narrow_oop((jobject)$src$$constant, dst); 6146 %} 6147 ins_pipe(ialu_hi_lo_reg); 6148 %} 6149 6150 instruct loadConL(iRegL dst, immL src, o7RegL tmp) %{ 6151 // %%% maybe this should work like loadConD 6152 match(Set dst src); 6153 effect(KILL tmp); 6154 ins_cost(DEFAULT_COST * 4); 6155 format %{ "SET64 $src,$dst KILL $tmp\t! long" %} 6156 ins_encode( LdImmL(src, dst, tmp) ); 6157 ins_pipe(loadConL); 6158 %} 6159 6160 instruct loadConL0( iRegL dst, immL0 src ) %{ 6161 match(Set dst src); 6162 ins_cost(DEFAULT_COST); 6163 size(4); 6164 format %{ "CLR $dst\t! long" %} 6165 ins_encode( Set13( src, dst ) ); 6166 ins_pipe(ialu_imm); 6167 %} 6168 6169 instruct loadConL13( iRegL dst, immL13 src ) %{ 6170 match(Set dst src); 6171 ins_cost(DEFAULT_COST * 2); 6172 6173 size(4); 6174 format %{ "MOV $src,$dst\t! long" %} 6175 ins_encode( Set13( src, dst ) ); 6176 ins_pipe(ialu_imm); 6177 %} 6178 6179 instruct loadConF(regF dst, immF src, o7RegP tmp) %{ 6180 match(Set dst src); 6181 effect(KILL tmp); 6182 6183 #ifdef _LP64 6184 size(8*4); 6185 #else 6186 size(2*4); 6187 #endif 6188 6189 format %{ "SETHI hi(&$src),$tmp\t!get float $src from table\n\t" 6190 "LDF [$tmp+lo(&$src)],$dst" %} 6191 ins_encode %{ 6192 address float_address = __ float_constant($src$$constant); 6193 RelocationHolder rspec = internal_word_Relocation::spec(float_address); 6194 AddressLiteral addrlit(float_address, rspec); 6195 6196 __ sethi(addrlit, $tmp$$Register); 6197 __ ldf(FloatRegisterImpl::S, $tmp$$Register, addrlit.low10(), $dst$$FloatRegister, rspec); 6198 %} 6199 ins_pipe(loadConFD); 6200 %} 6201 6202 instruct loadConD(regD dst, immD src, o7RegP tmp) %{ 6203 match(Set dst src); 6204 effect(KILL tmp); 6205 6206 #ifdef _LP64 6207 size(8*4); 6208 #else 6209 size(2*4); 6210 #endif 6211 6212 format %{ "SETHI hi(&$src),$tmp\t!get double $src from table\n\t" 6213 "LDDF [$tmp+lo(&$src)],$dst" %} 6214 ins_encode %{ 6215 address double_address = __ double_constant($src$$constant); 6216 RelocationHolder rspec = internal_word_Relocation::spec(double_address); 6217 AddressLiteral addrlit(double_address, rspec); 6218 6219 __ sethi(addrlit, $tmp$$Register); 6220 // XXX This is a quick fix for 6833573. 6221 //__ ldf(FloatRegisterImpl::D, $tmp$$Register, addrlit.low10(), $dst$$FloatRegister, rspec); 6222 __ ldf(FloatRegisterImpl::D, $tmp$$Register, addrlit.low10(), as_DoubleFloatRegister($dst$$reg), rspec); 6223 %} 6224 ins_pipe(loadConFD); 6225 %} 6226 6227 // Prefetch instructions. 6228 // Must be safe to execute with invalid address (cannot fault). 6229 6230 instruct prefetchr( memory mem ) %{ 6231 match( PrefetchRead mem ); 6232 ins_cost(MEMORY_REF_COST); 6233 6234 format %{ "PREFETCH $mem,0\t! Prefetch read-many" %} 6235 opcode(Assembler::prefetch_op3); 6236 ins_encode( form3_mem_prefetch_read( mem ) ); 6237 ins_pipe(iload_mem); 6238 %} 6239 6240 instruct prefetchw( memory mem ) %{ 6241 match( PrefetchWrite mem ); 6242 ins_cost(MEMORY_REF_COST); 6243 6244 format %{ "PREFETCH $mem,2\t! Prefetch write-many (and read)" %} 6245 opcode(Assembler::prefetch_op3); 6246 ins_encode( form3_mem_prefetch_write( mem ) ); 6247 ins_pipe(iload_mem); 6248 %} 6249 6250 6251 //----------Store Instructions------------------------------------------------- 6252 // Store Byte 6253 instruct storeB(memory mem, iRegI src) %{ 6254 match(Set mem (StoreB mem src)); 6255 ins_cost(MEMORY_REF_COST); 6256 6257 size(4); 6258 format %{ "STB $src,$mem\t! byte" %} 6259 opcode(Assembler::stb_op3); 6260 ins_encode(simple_form3_mem_reg( mem, src ) ); 6261 ins_pipe(istore_mem_reg); 6262 %} 6263 6264 instruct storeB0(memory mem, immI0 src) %{ 6265 match(Set mem (StoreB mem src)); 6266 ins_cost(MEMORY_REF_COST); 6267 6268 size(4); 6269 format %{ "STB $src,$mem\t! byte" %} 6270 opcode(Assembler::stb_op3); 6271 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); 6272 ins_pipe(istore_mem_zero); 6273 %} 6274 6275 instruct storeCM0(memory mem, immI0 src) %{ 6276 match(Set mem (StoreCM mem src)); 6277 ins_cost(MEMORY_REF_COST); 6278 6279 size(4); 6280 format %{ "STB $src,$mem\t! CMS card-mark byte 0" %} 6281 opcode(Assembler::stb_op3); 6282 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); 6283 ins_pipe(istore_mem_zero); 6284 %} 6285 6286 // Store Char/Short 6287 instruct storeC(memory mem, iRegI src) %{ 6288 match(Set mem (StoreC mem src)); 6289 ins_cost(MEMORY_REF_COST); 6290 6291 size(4); 6292 format %{ "STH $src,$mem\t! short" %} 6293 opcode(Assembler::sth_op3); 6294 ins_encode(simple_form3_mem_reg( mem, src ) ); 6295 ins_pipe(istore_mem_reg); 6296 %} 6297 6298 instruct storeC0(memory mem, immI0 src) %{ 6299 match(Set mem (StoreC mem src)); 6300 ins_cost(MEMORY_REF_COST); 6301 6302 size(4); 6303 format %{ "STH $src,$mem\t! short" %} 6304 opcode(Assembler::sth_op3); 6305 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); 6306 ins_pipe(istore_mem_zero); 6307 %} 6308 6309 // Store Integer 6310 instruct storeI(memory mem, iRegI src) %{ 6311 match(Set mem (StoreI mem src)); 6312 ins_cost(MEMORY_REF_COST); 6313 6314 size(4); 6315 format %{ "STW $src,$mem" %} 6316 opcode(Assembler::stw_op3); 6317 ins_encode(simple_form3_mem_reg( mem, src ) ); 6318 ins_pipe(istore_mem_reg); 6319 %} 6320 6321 // Store Long 6322 instruct storeL(memory mem, iRegL src) %{ 6323 match(Set mem (StoreL mem src)); 6324 ins_cost(MEMORY_REF_COST); 6325 size(4); 6326 format %{ "STX $src,$mem\t! long" %} 6327 opcode(Assembler::stx_op3); 6328 ins_encode(simple_form3_mem_reg( mem, src ) ); 6329 ins_pipe(istore_mem_reg); 6330 %} 6331 6332 instruct storeI0(memory mem, immI0 src) %{ 6333 match(Set mem (StoreI mem src)); 6334 ins_cost(MEMORY_REF_COST); 6335 6336 size(4); 6337 format %{ "STW $src,$mem" %} 6338 opcode(Assembler::stw_op3); 6339 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); 6340 ins_pipe(istore_mem_zero); 6341 %} 6342 6343 instruct storeL0(memory mem, immL0 src) %{ 6344 match(Set mem (StoreL mem src)); 6345 ins_cost(MEMORY_REF_COST); 6346 6347 size(4); 6348 format %{ "STX $src,$mem" %} 6349 opcode(Assembler::stx_op3); 6350 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); 6351 ins_pipe(istore_mem_zero); 6352 %} 6353 6354 // Store Integer from float register (used after fstoi) 6355 instruct storeI_Freg(memory mem, regF src) %{ 6356 match(Set mem (StoreI mem src)); 6357 ins_cost(MEMORY_REF_COST); 6358 6359 size(4); 6360 format %{ "STF $src,$mem\t! after fstoi/fdtoi" %} 6361 opcode(Assembler::stf_op3); 6362 ins_encode(simple_form3_mem_reg( mem, src ) ); 6363 ins_pipe(fstoreF_mem_reg); 6364 %} 6365 6366 // Store Pointer 6367 instruct storeP(memory dst, sp_ptr_RegP src) %{ 6368 match(Set dst (StoreP dst src)); 6369 ins_cost(MEMORY_REF_COST); 6370 size(4); 6371 6372 #ifndef _LP64 6373 format %{ "STW $src,$dst\t! ptr" %} 6374 opcode(Assembler::stw_op3, 0, REGP_OP); 6375 #else 6376 format %{ "STX $src,$dst\t! ptr" %} 6377 opcode(Assembler::stx_op3, 0, REGP_OP); 6378 #endif 6379 ins_encode( form3_mem_reg( dst, src ) ); 6380 ins_pipe(istore_mem_spORreg); 6381 %} 6382 6383 instruct storeP0(memory dst, immP0 src) %{ 6384 match(Set dst (StoreP dst src)); 6385 ins_cost(MEMORY_REF_COST); 6386 size(4); 6387 6388 #ifndef _LP64 6389 format %{ "STW $src,$dst\t! ptr" %} 6390 opcode(Assembler::stw_op3, 0, REGP_OP); 6391 #else 6392 format %{ "STX $src,$dst\t! ptr" %} 6393 opcode(Assembler::stx_op3, 0, REGP_OP); 6394 #endif 6395 ins_encode( form3_mem_reg( dst, R_G0 ) ); 6396 ins_pipe(istore_mem_zero); 6397 %} 6398 6399 // Store Compressed Pointer 6400 instruct storeN(memory dst, iRegN src) %{ 6401 match(Set dst (StoreN dst src)); 6402 ins_cost(MEMORY_REF_COST); 6403 size(4); 6404 6405 format %{ "STW $src,$dst\t! compressed ptr" %} 6406 ins_encode %{ 6407 Register base = as_Register($dst$$base); 6408 Register index = as_Register($dst$$index); 6409 Register src = $src$$Register; 6410 if (index != G0) { 6411 __ stw(src, base, index); 6412 } else { 6413 __ stw(src, base, $dst$$disp); 6414 } 6415 %} 6416 ins_pipe(istore_mem_spORreg); 6417 %} 6418 6419 instruct storeN0(memory dst, immN0 src) %{ 6420 match(Set dst (StoreN dst src)); 6421 ins_cost(MEMORY_REF_COST); 6422 size(4); 6423 6424 format %{ "STW $src,$dst\t! compressed ptr" %} 6425 ins_encode %{ 6426 Register base = as_Register($dst$$base); 6427 Register index = as_Register($dst$$index); 6428 if (index != G0) { 6429 __ stw(0, base, index); 6430 } else { 6431 __ stw(0, base, $dst$$disp); 6432 } 6433 %} 6434 ins_pipe(istore_mem_zero); 6435 %} 6436 6437 // Store Double 6438 instruct storeD( memory mem, regD src) %{ 6439 match(Set mem (StoreD mem src)); 6440 ins_cost(MEMORY_REF_COST); 6441 6442 size(4); 6443 format %{ "STDF $src,$mem" %} 6444 opcode(Assembler::stdf_op3); 6445 ins_encode(simple_form3_mem_reg( mem, src ) ); 6446 ins_pipe(fstoreD_mem_reg); 6447 %} 6448 6449 instruct storeD0( memory mem, immD0 src) %{ 6450 match(Set mem (StoreD mem src)); 6451 ins_cost(MEMORY_REF_COST); 6452 6453 size(4); 6454 format %{ "STX $src,$mem" %} 6455 opcode(Assembler::stx_op3); 6456 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); 6457 ins_pipe(fstoreD_mem_zero); 6458 %} 6459 6460 // Store Float 6461 instruct storeF( memory mem, regF src) %{ 6462 match(Set mem (StoreF mem src)); 6463 ins_cost(MEMORY_REF_COST); 6464 6465 size(4); 6466 format %{ "STF $src,$mem" %} 6467 opcode(Assembler::stf_op3); 6468 ins_encode(simple_form3_mem_reg( mem, src ) ); 6469 ins_pipe(fstoreF_mem_reg); 6470 %} 6471 6472 instruct storeF0( memory mem, immF0 src) %{ 6473 match(Set mem (StoreF mem src)); 6474 ins_cost(MEMORY_REF_COST); 6475 6476 size(4); 6477 format %{ "STW $src,$mem\t! storeF0" %} 6478 opcode(Assembler::stw_op3); 6479 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); 6480 ins_pipe(fstoreF_mem_zero); 6481 %} 6482 6483 // Store Aligned Packed Bytes in Double register to memory 6484 instruct storeA8B(memory mem, regD src) %{ 6485 match(Set mem (Store8B mem src)); 6486 ins_cost(MEMORY_REF_COST); 6487 size(4); 6488 format %{ "STDF $src,$mem\t! packed8B" %} 6489 opcode(Assembler::stdf_op3); 6490 ins_encode(simple_form3_mem_reg( mem, src ) ); 6491 ins_pipe(fstoreD_mem_reg); 6492 %} 6493 6494 // Convert oop pointer into compressed form 6495 instruct encodeHeapOop(iRegN dst, iRegP src) %{ 6496 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull); 6497 match(Set dst (EncodeP src)); 6498 format %{ "encode_heap_oop $src, $dst" %} 6499 ins_encode %{ 6500 __ encode_heap_oop($src$$Register, $dst$$Register); 6501 %} 6502 ins_pipe(ialu_reg); 6503 %} 6504 6505 instruct encodeHeapOop_not_null(iRegN dst, iRegP src) %{ 6506 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull); 6507 match(Set dst (EncodeP src)); 6508 format %{ "encode_heap_oop_not_null $src, $dst" %} 6509 ins_encode %{ 6510 __ encode_heap_oop_not_null($src$$Register, $dst$$Register); 6511 %} 6512 ins_pipe(ialu_reg); 6513 %} 6514 6515 instruct decodeHeapOop(iRegP dst, iRegN src) %{ 6516 predicate(n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull && 6517 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant); 6518 match(Set dst (DecodeN src)); 6519 format %{ "decode_heap_oop $src, $dst" %} 6520 ins_encode %{ 6521 __ decode_heap_oop($src$$Register, $dst$$Register); 6522 %} 6523 ins_pipe(ialu_reg); 6524 %} 6525 6526 instruct decodeHeapOop_not_null(iRegP dst, iRegN src) %{ 6527 predicate(n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull || 6528 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant); 6529 match(Set dst (DecodeN src)); 6530 format %{ "decode_heap_oop_not_null $src, $dst" %} 6531 ins_encode %{ 6532 __ decode_heap_oop_not_null($src$$Register, $dst$$Register); 6533 %} 6534 ins_pipe(ialu_reg); 6535 %} 6536 6537 6538 // Store Zero into Aligned Packed Bytes 6539 instruct storeA8B0(memory mem, immI0 zero) %{ 6540 match(Set mem (Store8B mem zero)); 6541 ins_cost(MEMORY_REF_COST); 6542 size(4); 6543 format %{ "STX $zero,$mem\t! packed8B" %} 6544 opcode(Assembler::stx_op3); 6545 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); 6546 ins_pipe(fstoreD_mem_zero); 6547 %} 6548 6549 // Store Aligned Packed Chars/Shorts in Double register to memory 6550 instruct storeA4C(memory mem, regD src) %{ 6551 match(Set mem (Store4C mem src)); 6552 ins_cost(MEMORY_REF_COST); 6553 size(4); 6554 format %{ "STDF $src,$mem\t! packed4C" %} 6555 opcode(Assembler::stdf_op3); 6556 ins_encode(simple_form3_mem_reg( mem, src ) ); 6557 ins_pipe(fstoreD_mem_reg); 6558 %} 6559 6560 // Store Zero into Aligned Packed Chars/Shorts 6561 instruct storeA4C0(memory mem, immI0 zero) %{ 6562 match(Set mem (Store4C mem (Replicate4C zero))); 6563 ins_cost(MEMORY_REF_COST); 6564 size(4); 6565 format %{ "STX $zero,$mem\t! packed4C" %} 6566 opcode(Assembler::stx_op3); 6567 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); 6568 ins_pipe(fstoreD_mem_zero); 6569 %} 6570 6571 // Store Aligned Packed Ints in Double register to memory 6572 instruct storeA2I(memory mem, regD src) %{ 6573 match(Set mem (Store2I mem src)); 6574 ins_cost(MEMORY_REF_COST); 6575 size(4); 6576 format %{ "STDF $src,$mem\t! packed2I" %} 6577 opcode(Assembler::stdf_op3); 6578 ins_encode(simple_form3_mem_reg( mem, src ) ); 6579 ins_pipe(fstoreD_mem_reg); 6580 %} 6581 6582 // Store Zero into Aligned Packed Ints 6583 instruct storeA2I0(memory mem, immI0 zero) %{ 6584 match(Set mem (Store2I mem zero)); 6585 ins_cost(MEMORY_REF_COST); 6586 size(4); 6587 format %{ "STX $zero,$mem\t! packed2I" %} 6588 opcode(Assembler::stx_op3); 6589 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); 6590 ins_pipe(fstoreD_mem_zero); 6591 %} 6592 6593 6594 //----------MemBar Instructions----------------------------------------------- 6595 // Memory barrier flavors 6596 6597 instruct membar_acquire() %{ 6598 match(MemBarAcquire); 6599 ins_cost(4*MEMORY_REF_COST); 6600 6601 size(0); 6602 format %{ "MEMBAR-acquire" %} 6603 ins_encode( enc_membar_acquire ); 6604 ins_pipe(long_memory_op); 6605 %} 6606 6607 instruct membar_acquire_lock() %{ 6608 match(MemBarAcquire); 6609 predicate(Matcher::prior_fast_lock(n)); 6610 ins_cost(0); 6611 6612 size(0); 6613 format %{ "!MEMBAR-acquire (CAS in prior FastLock so empty encoding)" %} 6614 ins_encode( ); 6615 ins_pipe(empty); 6616 %} 6617 6618 instruct membar_release() %{ 6619 match(MemBarRelease); 6620 ins_cost(4*MEMORY_REF_COST); 6621 6622 size(0); 6623 format %{ "MEMBAR-release" %} 6624 ins_encode( enc_membar_release ); 6625 ins_pipe(long_memory_op); 6626 %} 6627 6628 instruct membar_release_lock() %{ 6629 match(MemBarRelease); 6630 predicate(Matcher::post_fast_unlock(n)); 6631 ins_cost(0); 6632 6633 size(0); 6634 format %{ "!MEMBAR-release (CAS in succeeding FastUnlock so empty encoding)" %} 6635 ins_encode( ); 6636 ins_pipe(empty); 6637 %} 6638 6639 instruct membar_volatile() %{ 6640 match(MemBarVolatile); 6641 ins_cost(4*MEMORY_REF_COST); 6642 6643 size(4); 6644 format %{ "MEMBAR-volatile" %} 6645 ins_encode( enc_membar_volatile ); 6646 ins_pipe(long_memory_op); 6647 %} 6648 6649 instruct unnecessary_membar_volatile() %{ 6650 match(MemBarVolatile); 6651 predicate(Matcher::post_store_load_barrier(n)); 6652 ins_cost(0); 6653 6654 size(0); 6655 format %{ "!MEMBAR-volatile (unnecessary so empty encoding)" %} 6656 ins_encode( ); 6657 ins_pipe(empty); 6658 %} 6659 6660 //----------Register Move Instructions----------------------------------------- 6661 instruct roundDouble_nop(regD dst) %{ 6662 match(Set dst (RoundDouble dst)); 6663 ins_cost(0); 6664 // SPARC results are already "rounded" (i.e., normal-format IEEE) 6665 ins_encode( ); 6666 ins_pipe(empty); 6667 %} 6668 6669 6670 instruct roundFloat_nop(regF dst) %{ 6671 match(Set dst (RoundFloat dst)); 6672 ins_cost(0); 6673 // SPARC results are already "rounded" (i.e., normal-format IEEE) 6674 ins_encode( ); 6675 ins_pipe(empty); 6676 %} 6677 6678 6679 // Cast Index to Pointer for unsafe natives 6680 instruct castX2P(iRegX src, iRegP dst) %{ 6681 match(Set dst (CastX2P src)); 6682 6683 format %{ "MOV $src,$dst\t! IntX->Ptr" %} 6684 ins_encode( form3_g0_rs2_rd_move( src, dst ) ); 6685 ins_pipe(ialu_reg); 6686 %} 6687 6688 // Cast Pointer to Index for unsafe natives 6689 instruct castP2X(iRegP src, iRegX dst) %{ 6690 match(Set dst (CastP2X src)); 6691 6692 format %{ "MOV $src,$dst\t! Ptr->IntX" %} 6693 ins_encode( form3_g0_rs2_rd_move( src, dst ) ); 6694 ins_pipe(ialu_reg); 6695 %} 6696 6697 instruct stfSSD(stackSlotD stkSlot, regD src) %{ 6698 // %%%% TO DO: Tell the coalescer that this kind of node is a copy! 6699 match(Set stkSlot src); // chain rule 6700 ins_cost(MEMORY_REF_COST); 6701 format %{ "STDF $src,$stkSlot\t!stk" %} 6702 opcode(Assembler::stdf_op3); 6703 ins_encode(simple_form3_mem_reg(stkSlot, src)); 6704 ins_pipe(fstoreD_stk_reg); 6705 %} 6706 6707 instruct ldfSSD(regD dst, stackSlotD stkSlot) %{ 6708 // %%%% TO DO: Tell the coalescer that this kind of node is a copy! 6709 match(Set dst stkSlot); // chain rule 6710 ins_cost(MEMORY_REF_COST); 6711 format %{ "LDDF $stkSlot,$dst\t!stk" %} 6712 opcode(Assembler::lddf_op3); 6713 ins_encode(simple_form3_mem_reg(stkSlot, dst)); 6714 ins_pipe(floadD_stk); 6715 %} 6716 6717 instruct stfSSF(stackSlotF stkSlot, regF src) %{ 6718 // %%%% TO DO: Tell the coalescer that this kind of node is a copy! 6719 match(Set stkSlot src); // chain rule 6720 ins_cost(MEMORY_REF_COST); 6721 format %{ "STF $src,$stkSlot\t!stk" %} 6722 opcode(Assembler::stf_op3); 6723 ins_encode(simple_form3_mem_reg(stkSlot, src)); 6724 ins_pipe(fstoreF_stk_reg); 6725 %} 6726 6727 //----------Conditional Move--------------------------------------------------- 6728 // Conditional move 6729 instruct cmovIP_reg(cmpOpP cmp, flagsRegP pcc, iRegI dst, iRegI src) %{ 6730 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src))); 6731 ins_cost(150); 6732 format %{ "MOV$cmp $pcc,$src,$dst" %} 6733 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); 6734 ins_pipe(ialu_reg); 6735 %} 6736 6737 instruct cmovIP_imm(cmpOpP cmp, flagsRegP pcc, iRegI dst, immI11 src) %{ 6738 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src))); 6739 ins_cost(140); 6740 format %{ "MOV$cmp $pcc,$src,$dst" %} 6741 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) ); 6742 ins_pipe(ialu_imm); 6743 %} 6744 6745 instruct cmovII_reg(cmpOp cmp, flagsReg icc, iRegI dst, iRegI src) %{ 6746 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); 6747 ins_cost(150); 6748 size(4); 6749 format %{ "MOV$cmp $icc,$src,$dst" %} 6750 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); 6751 ins_pipe(ialu_reg); 6752 %} 6753 6754 instruct cmovII_imm(cmpOp cmp, flagsReg icc, iRegI dst, immI11 src) %{ 6755 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); 6756 ins_cost(140); 6757 size(4); 6758 format %{ "MOV$cmp $icc,$src,$dst" %} 6759 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); 6760 ins_pipe(ialu_imm); 6761 %} 6762 6763 instruct cmovII_U_reg(cmpOpU cmp, flagsRegU icc, iRegI dst, iRegI src) %{ 6764 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); 6765 ins_cost(150); 6766 size(4); 6767 format %{ "MOV$cmp $icc,$src,$dst" %} 6768 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); 6769 ins_pipe(ialu_reg); 6770 %} 6771 6772 instruct cmovII_U_imm(cmpOpU cmp, flagsRegU icc, iRegI dst, immI11 src) %{ 6773 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); 6774 ins_cost(140); 6775 size(4); 6776 format %{ "MOV$cmp $icc,$src,$dst" %} 6777 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); 6778 ins_pipe(ialu_imm); 6779 %} 6780 6781 instruct cmovIF_reg(cmpOpF cmp, flagsRegF fcc, iRegI dst, iRegI src) %{ 6782 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src))); 6783 ins_cost(150); 6784 size(4); 6785 format %{ "MOV$cmp $fcc,$src,$dst" %} 6786 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); 6787 ins_pipe(ialu_reg); 6788 %} 6789 6790 instruct cmovIF_imm(cmpOpF cmp, flagsRegF fcc, iRegI dst, immI11 src) %{ 6791 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src))); 6792 ins_cost(140); 6793 size(4); 6794 format %{ "MOV$cmp $fcc,$src,$dst" %} 6795 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) ); 6796 ins_pipe(ialu_imm); 6797 %} 6798 6799 // Conditional move for RegN. Only cmov(reg,reg). 6800 instruct cmovNP_reg(cmpOpP cmp, flagsRegP pcc, iRegN dst, iRegN src) %{ 6801 match(Set dst (CMoveN (Binary cmp pcc) (Binary dst src))); 6802 ins_cost(150); 6803 format %{ "MOV$cmp $pcc,$src,$dst" %} 6804 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); 6805 ins_pipe(ialu_reg); 6806 %} 6807 6808 // This instruction also works with CmpN so we don't need cmovNN_reg. 6809 instruct cmovNI_reg(cmpOp cmp, flagsReg icc, iRegN dst, iRegN src) %{ 6810 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src))); 6811 ins_cost(150); 6812 size(4); 6813 format %{ "MOV$cmp $icc,$src,$dst" %} 6814 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); 6815 ins_pipe(ialu_reg); 6816 %} 6817 6818 instruct cmovNF_reg(cmpOpF cmp, flagsRegF fcc, iRegN dst, iRegN src) %{ 6819 match(Set dst (CMoveN (Binary cmp fcc) (Binary dst src))); 6820 ins_cost(150); 6821 size(4); 6822 format %{ "MOV$cmp $fcc,$src,$dst" %} 6823 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); 6824 ins_pipe(ialu_reg); 6825 %} 6826 6827 // Conditional move 6828 instruct cmovPP_reg(cmpOpP cmp, flagsRegP pcc, iRegP dst, iRegP src) %{ 6829 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src))); 6830 ins_cost(150); 6831 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %} 6832 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); 6833 ins_pipe(ialu_reg); 6834 %} 6835 6836 instruct cmovPP_imm(cmpOpP cmp, flagsRegP pcc, iRegP dst, immP0 src) %{ 6837 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src))); 6838 ins_cost(140); 6839 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %} 6840 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) ); 6841 ins_pipe(ialu_imm); 6842 %} 6843 6844 // This instruction also works with CmpN so we don't need cmovPN_reg. 6845 instruct cmovPI_reg(cmpOp cmp, flagsReg icc, iRegP dst, iRegP src) %{ 6846 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); 6847 ins_cost(150); 6848 6849 size(4); 6850 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %} 6851 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); 6852 ins_pipe(ialu_reg); 6853 %} 6854 6855 instruct cmovPI_imm(cmpOp cmp, flagsReg icc, iRegP dst, immP0 src) %{ 6856 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); 6857 ins_cost(140); 6858 6859 size(4); 6860 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %} 6861 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); 6862 ins_pipe(ialu_imm); 6863 %} 6864 6865 instruct cmovPF_reg(cmpOpF cmp, flagsRegF fcc, iRegP dst, iRegP src) %{ 6866 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src))); 6867 ins_cost(150); 6868 size(4); 6869 format %{ "MOV$cmp $fcc,$src,$dst" %} 6870 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); 6871 ins_pipe(ialu_imm); 6872 %} 6873 6874 instruct cmovPF_imm(cmpOpF cmp, flagsRegF fcc, iRegP dst, immP0 src) %{ 6875 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src))); 6876 ins_cost(140); 6877 size(4); 6878 format %{ "MOV$cmp $fcc,$src,$dst" %} 6879 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) ); 6880 ins_pipe(ialu_imm); 6881 %} 6882 6883 // Conditional move 6884 instruct cmovFP_reg(cmpOpP cmp, flagsRegP pcc, regF dst, regF src) %{ 6885 match(Set dst (CMoveF (Binary cmp pcc) (Binary dst src))); 6886 ins_cost(150); 6887 opcode(0x101); 6888 format %{ "FMOVD$cmp $pcc,$src,$dst" %} 6889 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) ); 6890 ins_pipe(int_conditional_float_move); 6891 %} 6892 6893 instruct cmovFI_reg(cmpOp cmp, flagsReg icc, regF dst, regF src) %{ 6894 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src))); 6895 ins_cost(150); 6896 6897 size(4); 6898 format %{ "FMOVS$cmp $icc,$src,$dst" %} 6899 opcode(0x101); 6900 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) ); 6901 ins_pipe(int_conditional_float_move); 6902 %} 6903 6904 // Conditional move, 6905 instruct cmovFF_reg(cmpOpF cmp, flagsRegF fcc, regF dst, regF src) %{ 6906 match(Set dst (CMoveF (Binary cmp fcc) (Binary dst src))); 6907 ins_cost(150); 6908 size(4); 6909 format %{ "FMOVF$cmp $fcc,$src,$dst" %} 6910 opcode(0x1); 6911 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) ); 6912 ins_pipe(int_conditional_double_move); 6913 %} 6914 6915 // Conditional move 6916 instruct cmovDP_reg(cmpOpP cmp, flagsRegP pcc, regD dst, regD src) %{ 6917 match(Set dst (CMoveD (Binary cmp pcc) (Binary dst src))); 6918 ins_cost(150); 6919 size(4); 6920 opcode(0x102); 6921 format %{ "FMOVD$cmp $pcc,$src,$dst" %} 6922 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) ); 6923 ins_pipe(int_conditional_double_move); 6924 %} 6925 6926 instruct cmovDI_reg(cmpOp cmp, flagsReg icc, regD dst, regD src) %{ 6927 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src))); 6928 ins_cost(150); 6929 6930 size(4); 6931 format %{ "FMOVD$cmp $icc,$src,$dst" %} 6932 opcode(0x102); 6933 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) ); 6934 ins_pipe(int_conditional_double_move); 6935 %} 6936 6937 // Conditional move, 6938 instruct cmovDF_reg(cmpOpF cmp, flagsRegF fcc, regD dst, regD src) %{ 6939 match(Set dst (CMoveD (Binary cmp fcc) (Binary dst src))); 6940 ins_cost(150); 6941 size(4); 6942 format %{ "FMOVD$cmp $fcc,$src,$dst" %} 6943 opcode(0x2); 6944 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) ); 6945 ins_pipe(int_conditional_double_move); 6946 %} 6947 6948 // Conditional move 6949 instruct cmovLP_reg(cmpOpP cmp, flagsRegP pcc, iRegL dst, iRegL src) %{ 6950 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src))); 6951 ins_cost(150); 6952 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %} 6953 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); 6954 ins_pipe(ialu_reg); 6955 %} 6956 6957 instruct cmovLP_imm(cmpOpP cmp, flagsRegP pcc, iRegL dst, immI11 src) %{ 6958 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src))); 6959 ins_cost(140); 6960 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %} 6961 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) ); 6962 ins_pipe(ialu_imm); 6963 %} 6964 6965 instruct cmovLI_reg(cmpOp cmp, flagsReg icc, iRegL dst, iRegL src) %{ 6966 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src))); 6967 ins_cost(150); 6968 6969 size(4); 6970 format %{ "MOV$cmp $icc,$src,$dst\t! long" %} 6971 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); 6972 ins_pipe(ialu_reg); 6973 %} 6974 6975 6976 instruct cmovLF_reg(cmpOpF cmp, flagsRegF fcc, iRegL dst, iRegL src) %{ 6977 match(Set dst (CMoveL (Binary cmp fcc) (Binary dst src))); 6978 ins_cost(150); 6979 6980 size(4); 6981 format %{ "MOV$cmp $fcc,$src,$dst\t! long" %} 6982 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); 6983 ins_pipe(ialu_reg); 6984 %} 6985 6986 6987 6988 //----------OS and Locking Instructions---------------------------------------- 6989 6990 // This name is KNOWN by the ADLC and cannot be changed. 6991 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type 6992 // for this guy. 6993 instruct tlsLoadP(g2RegP dst) %{ 6994 match(Set dst (ThreadLocal)); 6995 6996 size(0); 6997 ins_cost(0); 6998 format %{ "# TLS is in G2" %} 6999 ins_encode( /*empty encoding*/ ); 7000 ins_pipe(ialu_none); 7001 %} 7002 7003 instruct checkCastPP( iRegP dst ) %{ 7004 match(Set dst (CheckCastPP dst)); 7005 7006 size(0); 7007 format %{ "# checkcastPP of $dst" %} 7008 ins_encode( /*empty encoding*/ ); 7009 ins_pipe(empty); 7010 %} 7011 7012 7013 instruct castPP( iRegP dst ) %{ 7014 match(Set dst (CastPP dst)); 7015 format %{ "# castPP of $dst" %} 7016 ins_encode( /*empty encoding*/ ); 7017 ins_pipe(empty); 7018 %} 7019 7020 instruct castII( iRegI dst ) %{ 7021 match(Set dst (CastII dst)); 7022 format %{ "# castII of $dst" %} 7023 ins_encode( /*empty encoding*/ ); 7024 ins_cost(0); 7025 ins_pipe(empty); 7026 %} 7027 7028 //----------Arithmetic Instructions-------------------------------------------- 7029 // Addition Instructions 7030 // Register Addition 7031 instruct addI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 7032 match(Set dst (AddI src1 src2)); 7033 7034 size(4); 7035 format %{ "ADD $src1,$src2,$dst" %} 7036 ins_encode %{ 7037 __ add($src1$$Register, $src2$$Register, $dst$$Register); 7038 %} 7039 ins_pipe(ialu_reg_reg); 7040 %} 7041 7042 // Immediate Addition 7043 instruct addI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ 7044 match(Set dst (AddI src1 src2)); 7045 7046 size(4); 7047 format %{ "ADD $src1,$src2,$dst" %} 7048 opcode(Assembler::add_op3, Assembler::arith_op); 7049 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7050 ins_pipe(ialu_reg_imm); 7051 %} 7052 7053 // Pointer Register Addition 7054 instruct addP_reg_reg(iRegP dst, iRegP src1, iRegX src2) %{ 7055 match(Set dst (AddP src1 src2)); 7056 7057 size(4); 7058 format %{ "ADD $src1,$src2,$dst" %} 7059 opcode(Assembler::add_op3, Assembler::arith_op); 7060 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7061 ins_pipe(ialu_reg_reg); 7062 %} 7063 7064 // Pointer Immediate Addition 7065 instruct addP_reg_imm13(iRegP dst, iRegP src1, immX13 src2) %{ 7066 match(Set dst (AddP src1 src2)); 7067 7068 size(4); 7069 format %{ "ADD $src1,$src2,$dst" %} 7070 opcode(Assembler::add_op3, Assembler::arith_op); 7071 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7072 ins_pipe(ialu_reg_imm); 7073 %} 7074 7075 // Long Addition 7076 instruct addL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 7077 match(Set dst (AddL src1 src2)); 7078 7079 size(4); 7080 format %{ "ADD $src1,$src2,$dst\t! long" %} 7081 opcode(Assembler::add_op3, Assembler::arith_op); 7082 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7083 ins_pipe(ialu_reg_reg); 7084 %} 7085 7086 instruct addL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ 7087 match(Set dst (AddL src1 con)); 7088 7089 size(4); 7090 format %{ "ADD $src1,$con,$dst" %} 7091 opcode(Assembler::add_op3, Assembler::arith_op); 7092 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); 7093 ins_pipe(ialu_reg_imm); 7094 %} 7095 7096 //----------Conditional_store-------------------------------------------------- 7097 // Conditional-store of the updated heap-top. 7098 // Used during allocation of the shared heap. 7099 // Sets flags (EQ) on success. Implemented with a CASA on Sparc. 7100 7101 // LoadP-locked. Same as a regular pointer load when used with a compare-swap 7102 instruct loadPLocked(iRegP dst, memory mem) %{ 7103 match(Set dst (LoadPLocked mem)); 7104 ins_cost(MEMORY_REF_COST); 7105 7106 #ifndef _LP64 7107 size(4); 7108 format %{ "LDUW $mem,$dst\t! ptr" %} 7109 opcode(Assembler::lduw_op3, 0, REGP_OP); 7110 #else 7111 format %{ "LDX $mem,$dst\t! ptr" %} 7112 opcode(Assembler::ldx_op3, 0, REGP_OP); 7113 #endif 7114 ins_encode( form3_mem_reg( mem, dst ) ); 7115 ins_pipe(iload_mem); 7116 %} 7117 7118 // LoadL-locked. Same as a regular long load when used with a compare-swap 7119 instruct loadLLocked(iRegL dst, memory mem) %{ 7120 match(Set dst (LoadLLocked mem)); 7121 ins_cost(MEMORY_REF_COST); 7122 size(4); 7123 format %{ "LDX $mem,$dst\t! long" %} 7124 opcode(Assembler::ldx_op3); 7125 ins_encode(simple_form3_mem_reg( mem, dst ) ); 7126 ins_pipe(iload_mem); 7127 %} 7128 7129 instruct storePConditional( iRegP heap_top_ptr, iRegP oldval, g3RegP newval, flagsRegP pcc ) %{ 7130 match(Set pcc (StorePConditional heap_top_ptr (Binary oldval newval))); 7131 effect( KILL newval ); 7132 format %{ "CASA [$heap_top_ptr],$oldval,R_G3\t! If $oldval==[$heap_top_ptr] Then store R_G3 into [$heap_top_ptr], set R_G3=[$heap_top_ptr] in any case\n\t" 7133 "CMP R_G3,$oldval\t\t! See if we made progress" %} 7134 ins_encode( enc_cas(heap_top_ptr,oldval,newval) ); 7135 ins_pipe( long_memory_op ); 7136 %} 7137 7138 // Conditional-store of an int value. 7139 instruct storeIConditional( iRegP mem_ptr, iRegI oldval, g3RegI newval, flagsReg icc ) %{ 7140 match(Set icc (StoreIConditional mem_ptr (Binary oldval newval))); 7141 effect( KILL newval ); 7142 format %{ "CASA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t" 7143 "CMP $oldval,$newval\t\t! See if we made progress" %} 7144 ins_encode( enc_cas(mem_ptr,oldval,newval) ); 7145 ins_pipe( long_memory_op ); 7146 %} 7147 7148 // Conditional-store of a long value. 7149 instruct storeLConditional( iRegP mem_ptr, iRegL oldval, g3RegL newval, flagsRegL xcc ) %{ 7150 match(Set xcc (StoreLConditional mem_ptr (Binary oldval newval))); 7151 effect( KILL newval ); 7152 format %{ "CASXA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t" 7153 "CMP $oldval,$newval\t\t! See if we made progress" %} 7154 ins_encode( enc_cas(mem_ptr,oldval,newval) ); 7155 ins_pipe( long_memory_op ); 7156 %} 7157 7158 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them 7159 7160 instruct compareAndSwapL_bool(iRegP mem_ptr, iRegL oldval, iRegL newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ 7161 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval))); 7162 effect( USE mem_ptr, KILL ccr, KILL tmp1); 7163 format %{ 7164 "MOV $newval,O7\n\t" 7165 "CASXA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" 7166 "CMP $oldval,O7\t\t! See if we made progress\n\t" 7167 "MOV 1,$res\n\t" 7168 "MOVne xcc,R_G0,$res" 7169 %} 7170 ins_encode( enc_casx(mem_ptr, oldval, newval), 7171 enc_lflags_ne_to_boolean(res) ); 7172 ins_pipe( long_memory_op ); 7173 %} 7174 7175 7176 instruct compareAndSwapI_bool(iRegP mem_ptr, iRegI oldval, iRegI newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ 7177 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval))); 7178 effect( USE mem_ptr, KILL ccr, KILL tmp1); 7179 format %{ 7180 "MOV $newval,O7\n\t" 7181 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" 7182 "CMP $oldval,O7\t\t! See if we made progress\n\t" 7183 "MOV 1,$res\n\t" 7184 "MOVne icc,R_G0,$res" 7185 %} 7186 ins_encode( enc_casi(mem_ptr, oldval, newval), 7187 enc_iflags_ne_to_boolean(res) ); 7188 ins_pipe( long_memory_op ); 7189 %} 7190 7191 instruct compareAndSwapP_bool(iRegP mem_ptr, iRegP oldval, iRegP newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ 7192 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval))); 7193 effect( USE mem_ptr, KILL ccr, KILL tmp1); 7194 format %{ 7195 "MOV $newval,O7\n\t" 7196 "CASA_PTR [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" 7197 "CMP $oldval,O7\t\t! See if we made progress\n\t" 7198 "MOV 1,$res\n\t" 7199 "MOVne xcc,R_G0,$res" 7200 %} 7201 #ifdef _LP64 7202 ins_encode( enc_casx(mem_ptr, oldval, newval), 7203 enc_lflags_ne_to_boolean(res) ); 7204 #else 7205 ins_encode( enc_casi(mem_ptr, oldval, newval), 7206 enc_iflags_ne_to_boolean(res) ); 7207 #endif 7208 ins_pipe( long_memory_op ); 7209 %} 7210 7211 instruct compareAndSwapN_bool(iRegP mem_ptr, iRegN oldval, iRegN newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ 7212 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval))); 7213 effect( USE mem_ptr, KILL ccr, KILL tmp1); 7214 format %{ 7215 "MOV $newval,O7\n\t" 7216 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" 7217 "CMP $oldval,O7\t\t! See if we made progress\n\t" 7218 "MOV 1,$res\n\t" 7219 "MOVne icc,R_G0,$res" 7220 %} 7221 ins_encode( enc_casi(mem_ptr, oldval, newval), 7222 enc_iflags_ne_to_boolean(res) ); 7223 ins_pipe( long_memory_op ); 7224 %} 7225 7226 //--------------------- 7227 // Subtraction Instructions 7228 // Register Subtraction 7229 instruct subI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 7230 match(Set dst (SubI src1 src2)); 7231 7232 size(4); 7233 format %{ "SUB $src1,$src2,$dst" %} 7234 opcode(Assembler::sub_op3, Assembler::arith_op); 7235 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7236 ins_pipe(ialu_reg_reg); 7237 %} 7238 7239 // Immediate Subtraction 7240 instruct subI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ 7241 match(Set dst (SubI src1 src2)); 7242 7243 size(4); 7244 format %{ "SUB $src1,$src2,$dst" %} 7245 opcode(Assembler::sub_op3, Assembler::arith_op); 7246 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7247 ins_pipe(ialu_reg_imm); 7248 %} 7249 7250 instruct subI_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{ 7251 match(Set dst (SubI zero src2)); 7252 7253 size(4); 7254 format %{ "NEG $src2,$dst" %} 7255 opcode(Assembler::sub_op3, Assembler::arith_op); 7256 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) ); 7257 ins_pipe(ialu_zero_reg); 7258 %} 7259 7260 // Long subtraction 7261 instruct subL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 7262 match(Set dst (SubL src1 src2)); 7263 7264 size(4); 7265 format %{ "SUB $src1,$src2,$dst\t! long" %} 7266 opcode(Assembler::sub_op3, Assembler::arith_op); 7267 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7268 ins_pipe(ialu_reg_reg); 7269 %} 7270 7271 // Immediate Subtraction 7272 instruct subL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ 7273 match(Set dst (SubL src1 con)); 7274 7275 size(4); 7276 format %{ "SUB $src1,$con,$dst\t! long" %} 7277 opcode(Assembler::sub_op3, Assembler::arith_op); 7278 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); 7279 ins_pipe(ialu_reg_imm); 7280 %} 7281 7282 // Long negation 7283 instruct negL_reg_reg(iRegL dst, immL0 zero, iRegL src2) %{ 7284 match(Set dst (SubL zero src2)); 7285 7286 size(4); 7287 format %{ "NEG $src2,$dst\t! long" %} 7288 opcode(Assembler::sub_op3, Assembler::arith_op); 7289 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) ); 7290 ins_pipe(ialu_zero_reg); 7291 %} 7292 7293 // Multiplication Instructions 7294 // Integer Multiplication 7295 // Register Multiplication 7296 instruct mulI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 7297 match(Set dst (MulI src1 src2)); 7298 7299 size(4); 7300 format %{ "MULX $src1,$src2,$dst" %} 7301 opcode(Assembler::mulx_op3, Assembler::arith_op); 7302 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7303 ins_pipe(imul_reg_reg); 7304 %} 7305 7306 // Immediate Multiplication 7307 instruct mulI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ 7308 match(Set dst (MulI src1 src2)); 7309 7310 size(4); 7311 format %{ "MULX $src1,$src2,$dst" %} 7312 opcode(Assembler::mulx_op3, Assembler::arith_op); 7313 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7314 ins_pipe(imul_reg_imm); 7315 %} 7316 7317 instruct mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 7318 match(Set dst (MulL src1 src2)); 7319 ins_cost(DEFAULT_COST * 5); 7320 size(4); 7321 format %{ "MULX $src1,$src2,$dst\t! long" %} 7322 opcode(Assembler::mulx_op3, Assembler::arith_op); 7323 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7324 ins_pipe(mulL_reg_reg); 7325 %} 7326 7327 // Immediate Multiplication 7328 instruct mulL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{ 7329 match(Set dst (MulL src1 src2)); 7330 ins_cost(DEFAULT_COST * 5); 7331 size(4); 7332 format %{ "MULX $src1,$src2,$dst" %} 7333 opcode(Assembler::mulx_op3, Assembler::arith_op); 7334 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7335 ins_pipe(mulL_reg_imm); 7336 %} 7337 7338 // Integer Division 7339 // Register Division 7340 instruct divI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2) %{ 7341 match(Set dst (DivI src1 src2)); 7342 ins_cost((2+71)*DEFAULT_COST); 7343 7344 format %{ "SRA $src2,0,$src2\n\t" 7345 "SRA $src1,0,$src1\n\t" 7346 "SDIVX $src1,$src2,$dst" %} 7347 ins_encode( idiv_reg( src1, src2, dst ) ); 7348 ins_pipe(sdiv_reg_reg); 7349 %} 7350 7351 // Immediate Division 7352 instruct divI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2) %{ 7353 match(Set dst (DivI src1 src2)); 7354 ins_cost((2+71)*DEFAULT_COST); 7355 7356 format %{ "SRA $src1,0,$src1\n\t" 7357 "SDIVX $src1,$src2,$dst" %} 7358 ins_encode( idiv_imm( src1, src2, dst ) ); 7359 ins_pipe(sdiv_reg_imm); 7360 %} 7361 7362 //----------Div-By-10-Expansion------------------------------------------------ 7363 // Extract hi bits of a 32x32->64 bit multiply. 7364 // Expand rule only, not matched 7365 instruct mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2 ) %{ 7366 effect( DEF dst, USE src1, USE src2 ); 7367 format %{ "MULX $src1,$src2,$dst\t! Used in div-by-10\n\t" 7368 "SRLX $dst,#32,$dst\t\t! Extract only hi word of result" %} 7369 ins_encode( enc_mul_hi(dst,src1,src2)); 7370 ins_pipe(sdiv_reg_reg); 7371 %} 7372 7373 // Magic constant, reciprocal of 10 7374 instruct loadConI_x66666667(iRegIsafe dst) %{ 7375 effect( DEF dst ); 7376 7377 size(8); 7378 format %{ "SET 0x66666667,$dst\t! Used in div-by-10" %} 7379 ins_encode( Set32(0x66666667, dst) ); 7380 ins_pipe(ialu_hi_lo_reg); 7381 %} 7382 7383 // Register Shift Right Arithmetic Long by 32-63 7384 instruct sra_31( iRegI dst, iRegI src ) %{ 7385 effect( DEF dst, USE src ); 7386 format %{ "SRA $src,31,$dst\t! Used in div-by-10" %} 7387 ins_encode( form3_rs1_rd_copysign_hi(src,dst) ); 7388 ins_pipe(ialu_reg_reg); 7389 %} 7390 7391 // Arithmetic Shift Right by 8-bit immediate 7392 instruct sra_reg_2( iRegI dst, iRegI src ) %{ 7393 effect( DEF dst, USE src ); 7394 format %{ "SRA $src,2,$dst\t! Used in div-by-10" %} 7395 opcode(Assembler::sra_op3, Assembler::arith_op); 7396 ins_encode( form3_rs1_simm13_rd( src, 0x2, dst ) ); 7397 ins_pipe(ialu_reg_imm); 7398 %} 7399 7400 // Integer DIV with 10 7401 instruct divI_10( iRegI dst, iRegIsafe src, immI10 div ) %{ 7402 match(Set dst (DivI src div)); 7403 ins_cost((6+6)*DEFAULT_COST); 7404 expand %{ 7405 iRegIsafe tmp1; // Killed temps; 7406 iRegIsafe tmp2; // Killed temps; 7407 iRegI tmp3; // Killed temps; 7408 iRegI tmp4; // Killed temps; 7409 loadConI_x66666667( tmp1 ); // SET 0x66666667 -> tmp1 7410 mul_hi( tmp2, src, tmp1 ); // MUL hibits(src * tmp1) -> tmp2 7411 sra_31( tmp3, src ); // SRA src,31 -> tmp3 7412 sra_reg_2( tmp4, tmp2 ); // SRA tmp2,2 -> tmp4 7413 subI_reg_reg( dst,tmp4,tmp3); // SUB tmp4 - tmp3 -> dst 7414 %} 7415 %} 7416 7417 // Register Long Division 7418 instruct divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 7419 match(Set dst (DivL src1 src2)); 7420 ins_cost(DEFAULT_COST*71); 7421 size(4); 7422 format %{ "SDIVX $src1,$src2,$dst\t! long" %} 7423 opcode(Assembler::sdivx_op3, Assembler::arith_op); 7424 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7425 ins_pipe(divL_reg_reg); 7426 %} 7427 7428 // Register Long Division 7429 instruct divL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{ 7430 match(Set dst (DivL src1 src2)); 7431 ins_cost(DEFAULT_COST*71); 7432 size(4); 7433 format %{ "SDIVX $src1,$src2,$dst\t! long" %} 7434 opcode(Assembler::sdivx_op3, Assembler::arith_op); 7435 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7436 ins_pipe(divL_reg_imm); 7437 %} 7438 7439 // Integer Remainder 7440 // Register Remainder 7441 instruct modI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2, o7RegP temp, flagsReg ccr ) %{ 7442 match(Set dst (ModI src1 src2)); 7443 effect( KILL ccr, KILL temp); 7444 7445 format %{ "SREM $src1,$src2,$dst" %} 7446 ins_encode( irem_reg(src1, src2, dst, temp) ); 7447 ins_pipe(sdiv_reg_reg); 7448 %} 7449 7450 // Immediate Remainder 7451 instruct modI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2, o7RegP temp, flagsReg ccr ) %{ 7452 match(Set dst (ModI src1 src2)); 7453 effect( KILL ccr, KILL temp); 7454 7455 format %{ "SREM $src1,$src2,$dst" %} 7456 ins_encode( irem_imm(src1, src2, dst, temp) ); 7457 ins_pipe(sdiv_reg_imm); 7458 %} 7459 7460 // Register Long Remainder 7461 instruct divL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{ 7462 effect(DEF dst, USE src1, USE src2); 7463 size(4); 7464 format %{ "SDIVX $src1,$src2,$dst\t! long" %} 7465 opcode(Assembler::sdivx_op3, Assembler::arith_op); 7466 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7467 ins_pipe(divL_reg_reg); 7468 %} 7469 7470 // Register Long Division 7471 instruct divL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{ 7472 effect(DEF dst, USE src1, USE src2); 7473 size(4); 7474 format %{ "SDIVX $src1,$src2,$dst\t! long" %} 7475 opcode(Assembler::sdivx_op3, Assembler::arith_op); 7476 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7477 ins_pipe(divL_reg_imm); 7478 %} 7479 7480 instruct mulL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{ 7481 effect(DEF dst, USE src1, USE src2); 7482 size(4); 7483 format %{ "MULX $src1,$src2,$dst\t! long" %} 7484 opcode(Assembler::mulx_op3, Assembler::arith_op); 7485 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7486 ins_pipe(mulL_reg_reg); 7487 %} 7488 7489 // Immediate Multiplication 7490 instruct mulL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{ 7491 effect(DEF dst, USE src1, USE src2); 7492 size(4); 7493 format %{ "MULX $src1,$src2,$dst" %} 7494 opcode(Assembler::mulx_op3, Assembler::arith_op); 7495 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7496 ins_pipe(mulL_reg_imm); 7497 %} 7498 7499 instruct subL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{ 7500 effect(DEF dst, USE src1, USE src2); 7501 size(4); 7502 format %{ "SUB $src1,$src2,$dst\t! long" %} 7503 opcode(Assembler::sub_op3, Assembler::arith_op); 7504 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7505 ins_pipe(ialu_reg_reg); 7506 %} 7507 7508 instruct subL_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{ 7509 effect(DEF dst, USE src1, USE src2); 7510 size(4); 7511 format %{ "SUB $src1,$src2,$dst\t! long" %} 7512 opcode(Assembler::sub_op3, Assembler::arith_op); 7513 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7514 ins_pipe(ialu_reg_reg); 7515 %} 7516 7517 // Register Long Remainder 7518 instruct modL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 7519 match(Set dst (ModL src1 src2)); 7520 ins_cost(DEFAULT_COST*(71 + 6 + 1)); 7521 expand %{ 7522 iRegL tmp1; 7523 iRegL tmp2; 7524 divL_reg_reg_1(tmp1, src1, src2); 7525 mulL_reg_reg_1(tmp2, tmp1, src2); 7526 subL_reg_reg_1(dst, src1, tmp2); 7527 %} 7528 %} 7529 7530 // Register Long Remainder 7531 instruct modL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{ 7532 match(Set dst (ModL src1 src2)); 7533 ins_cost(DEFAULT_COST*(71 + 6 + 1)); 7534 expand %{ 7535 iRegL tmp1; 7536 iRegL tmp2; 7537 divL_reg_imm13_1(tmp1, src1, src2); 7538 mulL_reg_imm13_1(tmp2, tmp1, src2); 7539 subL_reg_reg_2 (dst, src1, tmp2); 7540 %} 7541 %} 7542 7543 // Integer Shift Instructions 7544 // Register Shift Left 7545 instruct shlI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 7546 match(Set dst (LShiftI src1 src2)); 7547 7548 size(4); 7549 format %{ "SLL $src1,$src2,$dst" %} 7550 opcode(Assembler::sll_op3, Assembler::arith_op); 7551 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7552 ins_pipe(ialu_reg_reg); 7553 %} 7554 7555 // Register Shift Left Immediate 7556 instruct shlI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{ 7557 match(Set dst (LShiftI src1 src2)); 7558 7559 size(4); 7560 format %{ "SLL $src1,$src2,$dst" %} 7561 opcode(Assembler::sll_op3, Assembler::arith_op); 7562 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); 7563 ins_pipe(ialu_reg_imm); 7564 %} 7565 7566 // Register Shift Left 7567 instruct shlL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{ 7568 match(Set dst (LShiftL src1 src2)); 7569 7570 size(4); 7571 format %{ "SLLX $src1,$src2,$dst" %} 7572 opcode(Assembler::sllx_op3, Assembler::arith_op); 7573 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) ); 7574 ins_pipe(ialu_reg_reg); 7575 %} 7576 7577 // Register Shift Left Immediate 7578 instruct shlL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{ 7579 match(Set dst (LShiftL src1 src2)); 7580 7581 size(4); 7582 format %{ "SLLX $src1,$src2,$dst" %} 7583 opcode(Assembler::sllx_op3, Assembler::arith_op); 7584 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); 7585 ins_pipe(ialu_reg_imm); 7586 %} 7587 7588 // Register Arithmetic Shift Right 7589 instruct sarI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 7590 match(Set dst (RShiftI src1 src2)); 7591 size(4); 7592 format %{ "SRA $src1,$src2,$dst" %} 7593 opcode(Assembler::sra_op3, Assembler::arith_op); 7594 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7595 ins_pipe(ialu_reg_reg); 7596 %} 7597 7598 // Register Arithmetic Shift Right Immediate 7599 instruct sarI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{ 7600 match(Set dst (RShiftI src1 src2)); 7601 7602 size(4); 7603 format %{ "SRA $src1,$src2,$dst" %} 7604 opcode(Assembler::sra_op3, Assembler::arith_op); 7605 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); 7606 ins_pipe(ialu_reg_imm); 7607 %} 7608 7609 // Register Shift Right Arithmatic Long 7610 instruct sarL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{ 7611 match(Set dst (RShiftL src1 src2)); 7612 7613 size(4); 7614 format %{ "SRAX $src1,$src2,$dst" %} 7615 opcode(Assembler::srax_op3, Assembler::arith_op); 7616 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) ); 7617 ins_pipe(ialu_reg_reg); 7618 %} 7619 7620 // Register Shift Left Immediate 7621 instruct sarL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{ 7622 match(Set dst (RShiftL src1 src2)); 7623 7624 size(4); 7625 format %{ "SRAX $src1,$src2,$dst" %} 7626 opcode(Assembler::srax_op3, Assembler::arith_op); 7627 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); 7628 ins_pipe(ialu_reg_imm); 7629 %} 7630 7631 // Register Shift Right 7632 instruct shrI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 7633 match(Set dst (URShiftI src1 src2)); 7634 7635 size(4); 7636 format %{ "SRL $src1,$src2,$dst" %} 7637 opcode(Assembler::srl_op3, Assembler::arith_op); 7638 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7639 ins_pipe(ialu_reg_reg); 7640 %} 7641 7642 // Register Shift Right Immediate 7643 instruct shrI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{ 7644 match(Set dst (URShiftI src1 src2)); 7645 7646 size(4); 7647 format %{ "SRL $src1,$src2,$dst" %} 7648 opcode(Assembler::srl_op3, Assembler::arith_op); 7649 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); 7650 ins_pipe(ialu_reg_imm); 7651 %} 7652 7653 // Register Shift Right 7654 instruct shrL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{ 7655 match(Set dst (URShiftL src1 src2)); 7656 7657 size(4); 7658 format %{ "SRLX $src1,$src2,$dst" %} 7659 opcode(Assembler::srlx_op3, Assembler::arith_op); 7660 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) ); 7661 ins_pipe(ialu_reg_reg); 7662 %} 7663 7664 // Register Shift Right Immediate 7665 instruct shrL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{ 7666 match(Set dst (URShiftL src1 src2)); 7667 7668 size(4); 7669 format %{ "SRLX $src1,$src2,$dst" %} 7670 opcode(Assembler::srlx_op3, Assembler::arith_op); 7671 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); 7672 ins_pipe(ialu_reg_imm); 7673 %} 7674 7675 // Register Shift Right Immediate with a CastP2X 7676 #ifdef _LP64 7677 instruct shrP_reg_imm6(iRegL dst, iRegP src1, immU6 src2) %{ 7678 match(Set dst (URShiftL (CastP2X src1) src2)); 7679 size(4); 7680 format %{ "SRLX $src1,$src2,$dst\t! Cast ptr $src1 to long and shift" %} 7681 opcode(Assembler::srlx_op3, Assembler::arith_op); 7682 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); 7683 ins_pipe(ialu_reg_imm); 7684 %} 7685 #else 7686 instruct shrP_reg_imm5(iRegI dst, iRegP src1, immU5 src2) %{ 7687 match(Set dst (URShiftI (CastP2X src1) src2)); 7688 size(4); 7689 format %{ "SRL $src1,$src2,$dst\t! Cast ptr $src1 to int and shift" %} 7690 opcode(Assembler::srl_op3, Assembler::arith_op); 7691 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); 7692 ins_pipe(ialu_reg_imm); 7693 %} 7694 #endif 7695 7696 7697 //----------Floating Point Arithmetic Instructions----------------------------- 7698 7699 // Add float single precision 7700 instruct addF_reg_reg(regF dst, regF src1, regF src2) %{ 7701 match(Set dst (AddF src1 src2)); 7702 7703 size(4); 7704 format %{ "FADDS $src1,$src2,$dst" %} 7705 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fadds_opf); 7706 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); 7707 ins_pipe(faddF_reg_reg); 7708 %} 7709 7710 // Add float double precision 7711 instruct addD_reg_reg(regD dst, regD src1, regD src2) %{ 7712 match(Set dst (AddD src1 src2)); 7713 7714 size(4); 7715 format %{ "FADDD $src1,$src2,$dst" %} 7716 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf); 7717 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); 7718 ins_pipe(faddD_reg_reg); 7719 %} 7720 7721 // Sub float single precision 7722 instruct subF_reg_reg(regF dst, regF src1, regF src2) %{ 7723 match(Set dst (SubF src1 src2)); 7724 7725 size(4); 7726 format %{ "FSUBS $src1,$src2,$dst" %} 7727 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubs_opf); 7728 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); 7729 ins_pipe(faddF_reg_reg); 7730 %} 7731 7732 // Sub float double precision 7733 instruct subD_reg_reg(regD dst, regD src1, regD src2) %{ 7734 match(Set dst (SubD src1 src2)); 7735 7736 size(4); 7737 format %{ "FSUBD $src1,$src2,$dst" %} 7738 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf); 7739 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); 7740 ins_pipe(faddD_reg_reg); 7741 %} 7742 7743 // Mul float single precision 7744 instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{ 7745 match(Set dst (MulF src1 src2)); 7746 7747 size(4); 7748 format %{ "FMULS $src1,$src2,$dst" %} 7749 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuls_opf); 7750 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); 7751 ins_pipe(fmulF_reg_reg); 7752 %} 7753 7754 // Mul float double precision 7755 instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{ 7756 match(Set dst (MulD src1 src2)); 7757 7758 size(4); 7759 format %{ "FMULD $src1,$src2,$dst" %} 7760 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf); 7761 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); 7762 ins_pipe(fmulD_reg_reg); 7763 %} 7764 7765 // Div float single precision 7766 instruct divF_reg_reg(regF dst, regF src1, regF src2) %{ 7767 match(Set dst (DivF src1 src2)); 7768 7769 size(4); 7770 format %{ "FDIVS $src1,$src2,$dst" %} 7771 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivs_opf); 7772 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); 7773 ins_pipe(fdivF_reg_reg); 7774 %} 7775 7776 // Div float double precision 7777 instruct divD_reg_reg(regD dst, regD src1, regD src2) %{ 7778 match(Set dst (DivD src1 src2)); 7779 7780 size(4); 7781 format %{ "FDIVD $src1,$src2,$dst" %} 7782 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivd_opf); 7783 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); 7784 ins_pipe(fdivD_reg_reg); 7785 %} 7786 7787 // Absolute float double precision 7788 instruct absD_reg(regD dst, regD src) %{ 7789 match(Set dst (AbsD src)); 7790 7791 format %{ "FABSd $src,$dst" %} 7792 ins_encode(fabsd(dst, src)); 7793 ins_pipe(faddD_reg); 7794 %} 7795 7796 // Absolute float single precision 7797 instruct absF_reg(regF dst, regF src) %{ 7798 match(Set dst (AbsF src)); 7799 7800 format %{ "FABSs $src,$dst" %} 7801 ins_encode(fabss(dst, src)); 7802 ins_pipe(faddF_reg); 7803 %} 7804 7805 instruct negF_reg(regF dst, regF src) %{ 7806 match(Set dst (NegF src)); 7807 7808 size(4); 7809 format %{ "FNEGs $src,$dst" %} 7810 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fnegs_opf); 7811 ins_encode(form3_opf_rs2F_rdF(src, dst)); 7812 ins_pipe(faddF_reg); 7813 %} 7814 7815 instruct negD_reg(regD dst, regD src) %{ 7816 match(Set dst (NegD src)); 7817 7818 format %{ "FNEGd $src,$dst" %} 7819 ins_encode(fnegd(dst, src)); 7820 ins_pipe(faddD_reg); 7821 %} 7822 7823 // Sqrt float double precision 7824 instruct sqrtF_reg_reg(regF dst, regF src) %{ 7825 match(Set dst (ConvD2F (SqrtD (ConvF2D src)))); 7826 7827 size(4); 7828 format %{ "FSQRTS $src,$dst" %} 7829 ins_encode(fsqrts(dst, src)); 7830 ins_pipe(fdivF_reg_reg); 7831 %} 7832 7833 // Sqrt float double precision 7834 instruct sqrtD_reg_reg(regD dst, regD src) %{ 7835 match(Set dst (SqrtD src)); 7836 7837 size(4); 7838 format %{ "FSQRTD $src,$dst" %} 7839 ins_encode(fsqrtd(dst, src)); 7840 ins_pipe(fdivD_reg_reg); 7841 %} 7842 7843 //----------Logical Instructions----------------------------------------------- 7844 // And Instructions 7845 // Register And 7846 instruct andI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 7847 match(Set dst (AndI src1 src2)); 7848 7849 size(4); 7850 format %{ "AND $src1,$src2,$dst" %} 7851 opcode(Assembler::and_op3, Assembler::arith_op); 7852 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7853 ins_pipe(ialu_reg_reg); 7854 %} 7855 7856 // Immediate And 7857 instruct andI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ 7858 match(Set dst (AndI src1 src2)); 7859 7860 size(4); 7861 format %{ "AND $src1,$src2,$dst" %} 7862 opcode(Assembler::and_op3, Assembler::arith_op); 7863 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7864 ins_pipe(ialu_reg_imm); 7865 %} 7866 7867 // Register And Long 7868 instruct andL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 7869 match(Set dst (AndL src1 src2)); 7870 7871 ins_cost(DEFAULT_COST); 7872 size(4); 7873 format %{ "AND $src1,$src2,$dst\t! long" %} 7874 opcode(Assembler::and_op3, Assembler::arith_op); 7875 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7876 ins_pipe(ialu_reg_reg); 7877 %} 7878 7879 instruct andL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ 7880 match(Set dst (AndL src1 con)); 7881 7882 ins_cost(DEFAULT_COST); 7883 size(4); 7884 format %{ "AND $src1,$con,$dst\t! long" %} 7885 opcode(Assembler::and_op3, Assembler::arith_op); 7886 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); 7887 ins_pipe(ialu_reg_imm); 7888 %} 7889 7890 // Or Instructions 7891 // Register Or 7892 instruct orI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 7893 match(Set dst (OrI src1 src2)); 7894 7895 size(4); 7896 format %{ "OR $src1,$src2,$dst" %} 7897 opcode(Assembler::or_op3, Assembler::arith_op); 7898 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7899 ins_pipe(ialu_reg_reg); 7900 %} 7901 7902 // Immediate Or 7903 instruct orI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ 7904 match(Set dst (OrI src1 src2)); 7905 7906 size(4); 7907 format %{ "OR $src1,$src2,$dst" %} 7908 opcode(Assembler::or_op3, Assembler::arith_op); 7909 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7910 ins_pipe(ialu_reg_imm); 7911 %} 7912 7913 // Register Or Long 7914 instruct orL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 7915 match(Set dst (OrL src1 src2)); 7916 7917 ins_cost(DEFAULT_COST); 7918 size(4); 7919 format %{ "OR $src1,$src2,$dst\t! long" %} 7920 opcode(Assembler::or_op3, Assembler::arith_op); 7921 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7922 ins_pipe(ialu_reg_reg); 7923 %} 7924 7925 instruct orL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ 7926 match(Set dst (OrL src1 con)); 7927 ins_cost(DEFAULT_COST*2); 7928 7929 ins_cost(DEFAULT_COST); 7930 size(4); 7931 format %{ "OR $src1,$con,$dst\t! long" %} 7932 opcode(Assembler::or_op3, Assembler::arith_op); 7933 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); 7934 ins_pipe(ialu_reg_imm); 7935 %} 7936 7937 #ifndef _LP64 7938 7939 // Use sp_ptr_RegP to match G2 (TLS register) without spilling. 7940 instruct orI_reg_castP2X(iRegI dst, iRegI src1, sp_ptr_RegP src2) %{ 7941 match(Set dst (OrI src1 (CastP2X src2))); 7942 7943 size(4); 7944 format %{ "OR $src1,$src2,$dst" %} 7945 opcode(Assembler::or_op3, Assembler::arith_op); 7946 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7947 ins_pipe(ialu_reg_reg); 7948 %} 7949 7950 #else 7951 7952 instruct orL_reg_castP2X(iRegL dst, iRegL src1, sp_ptr_RegP src2) %{ 7953 match(Set dst (OrL src1 (CastP2X src2))); 7954 7955 ins_cost(DEFAULT_COST); 7956 size(4); 7957 format %{ "OR $src1,$src2,$dst\t! long" %} 7958 opcode(Assembler::or_op3, Assembler::arith_op); 7959 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7960 ins_pipe(ialu_reg_reg); 7961 %} 7962 7963 #endif 7964 7965 // Xor Instructions 7966 // Register Xor 7967 instruct xorI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 7968 match(Set dst (XorI src1 src2)); 7969 7970 size(4); 7971 format %{ "XOR $src1,$src2,$dst" %} 7972 opcode(Assembler::xor_op3, Assembler::arith_op); 7973 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7974 ins_pipe(ialu_reg_reg); 7975 %} 7976 7977 // Immediate Xor 7978 instruct xorI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ 7979 match(Set dst (XorI src1 src2)); 7980 7981 size(4); 7982 format %{ "XOR $src1,$src2,$dst" %} 7983 opcode(Assembler::xor_op3, Assembler::arith_op); 7984 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7985 ins_pipe(ialu_reg_imm); 7986 %} 7987 7988 // Register Xor Long 7989 instruct xorL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 7990 match(Set dst (XorL src1 src2)); 7991 7992 ins_cost(DEFAULT_COST); 7993 size(4); 7994 format %{ "XOR $src1,$src2,$dst\t! long" %} 7995 opcode(Assembler::xor_op3, Assembler::arith_op); 7996 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7997 ins_pipe(ialu_reg_reg); 7998 %} 7999 8000 instruct xorL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ 8001 match(Set dst (XorL src1 con)); 8002 8003 ins_cost(DEFAULT_COST); 8004 size(4); 8005 format %{ "XOR $src1,$con,$dst\t! long" %} 8006 opcode(Assembler::xor_op3, Assembler::arith_op); 8007 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); 8008 ins_pipe(ialu_reg_imm); 8009 %} 8010 8011 //----------Convert to Boolean------------------------------------------------- 8012 // Nice hack for 32-bit tests but doesn't work for 8013 // 64-bit pointers. 8014 instruct convI2B( iRegI dst, iRegI src, flagsReg ccr ) %{ 8015 match(Set dst (Conv2B src)); 8016 effect( KILL ccr ); 8017 ins_cost(DEFAULT_COST*2); 8018 format %{ "CMP R_G0,$src\n\t" 8019 "ADDX R_G0,0,$dst" %} 8020 ins_encode( enc_to_bool( src, dst ) ); 8021 ins_pipe(ialu_reg_ialu); 8022 %} 8023 8024 #ifndef _LP64 8025 instruct convP2B( iRegI dst, iRegP src, flagsReg ccr ) %{ 8026 match(Set dst (Conv2B src)); 8027 effect( KILL ccr ); 8028 ins_cost(DEFAULT_COST*2); 8029 format %{ "CMP R_G0,$src\n\t" 8030 "ADDX R_G0,0,$dst" %} 8031 ins_encode( enc_to_bool( src, dst ) ); 8032 ins_pipe(ialu_reg_ialu); 8033 %} 8034 #else 8035 instruct convP2B( iRegI dst, iRegP src ) %{ 8036 match(Set dst (Conv2B src)); 8037 ins_cost(DEFAULT_COST*2); 8038 format %{ "MOV $src,$dst\n\t" 8039 "MOVRNZ $src,1,$dst" %} 8040 ins_encode( form3_g0_rs2_rd_move( src, dst ), enc_convP2B( dst, src ) ); 8041 ins_pipe(ialu_clr_and_mover); 8042 %} 8043 #endif 8044 8045 instruct cmpLTMask_reg_reg( iRegI dst, iRegI p, iRegI q, flagsReg ccr ) %{ 8046 match(Set dst (CmpLTMask p q)); 8047 effect( KILL ccr ); 8048 ins_cost(DEFAULT_COST*4); 8049 format %{ "CMP $p,$q\n\t" 8050 "MOV #0,$dst\n\t" 8051 "BLT,a .+8\n\t" 8052 "MOV #-1,$dst" %} 8053 ins_encode( enc_ltmask(p,q,dst) ); 8054 ins_pipe(ialu_reg_reg_ialu); 8055 %} 8056 8057 instruct cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp, flagsReg ccr ) %{ 8058 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q))); 8059 effect(KILL ccr, TEMP tmp); 8060 ins_cost(DEFAULT_COST*3); 8061 8062 format %{ "SUBcc $p,$q,$p\t! p' = p-q\n\t" 8063 "ADD $p,$y,$tmp\t! g3=p-q+y\n\t" 8064 "MOVl $tmp,$p\t! p' < 0 ? p'+y : p'" %} 8065 ins_encode( enc_cadd_cmpLTMask(p, q, y, tmp) ); 8066 ins_pipe( cadd_cmpltmask ); 8067 %} 8068 8069 instruct cadd_cmpLTMask2( iRegI p, iRegI q, iRegI y, iRegI tmp, flagsReg ccr ) %{ 8070 match(Set p (AddI (SubI p q) (AndI (CmpLTMask p q) y))); 8071 effect( KILL ccr, TEMP tmp); 8072 ins_cost(DEFAULT_COST*3); 8073 8074 format %{ "SUBcc $p,$q,$p\t! p' = p-q\n\t" 8075 "ADD $p,$y,$tmp\t! g3=p-q+y\n\t" 8076 "MOVl $tmp,$p\t! p' < 0 ? p'+y : p'" %} 8077 ins_encode( enc_cadd_cmpLTMask(p, q, y, tmp) ); 8078 ins_pipe( cadd_cmpltmask ); 8079 %} 8080 8081 //----------Arithmetic Conversion Instructions--------------------------------- 8082 // The conversions operations are all Alpha sorted. Please keep it that way! 8083 8084 instruct convD2F_reg(regF dst, regD src) %{ 8085 match(Set dst (ConvD2F src)); 8086 size(4); 8087 format %{ "FDTOS $src,$dst" %} 8088 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdtos_opf); 8089 ins_encode(form3_opf_rs2D_rdF(src, dst)); 8090 ins_pipe(fcvtD2F); 8091 %} 8092 8093 8094 // Convert a double to an int in a float register. 8095 // If the double is a NAN, stuff a zero in instead. 8096 instruct convD2I_helper(regF dst, regD src, flagsRegF0 fcc0) %{ 8097 effect(DEF dst, USE src, KILL fcc0); 8098 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t" 8099 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" 8100 "FDTOI $src,$dst\t! convert in delay slot\n\t" 8101 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t" 8102 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n" 8103 "skip:" %} 8104 ins_encode(form_d2i_helper(src,dst)); 8105 ins_pipe(fcvtD2I); 8106 %} 8107 8108 instruct convD2I_reg(stackSlotI dst, regD src) %{ 8109 match(Set dst (ConvD2I src)); 8110 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); 8111 expand %{ 8112 regF tmp; 8113 convD2I_helper(tmp, src); 8114 regF_to_stkI(dst, tmp); 8115 %} 8116 %} 8117 8118 // Convert a double to a long in a double register. 8119 // If the double is a NAN, stuff a zero in instead. 8120 instruct convD2L_helper(regD dst, regD src, flagsRegF0 fcc0) %{ 8121 effect(DEF dst, USE src, KILL fcc0); 8122 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t" 8123 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" 8124 "FDTOX $src,$dst\t! convert in delay slot\n\t" 8125 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t" 8126 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n" 8127 "skip:" %} 8128 ins_encode(form_d2l_helper(src,dst)); 8129 ins_pipe(fcvtD2L); 8130 %} 8131 8132 8133 // Double to Long conversion 8134 instruct convD2L_reg(stackSlotL dst, regD src) %{ 8135 match(Set dst (ConvD2L src)); 8136 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); 8137 expand %{ 8138 regD tmp; 8139 convD2L_helper(tmp, src); 8140 regD_to_stkL(dst, tmp); 8141 %} 8142 %} 8143 8144 8145 instruct convF2D_reg(regD dst, regF src) %{ 8146 match(Set dst (ConvF2D src)); 8147 format %{ "FSTOD $src,$dst" %} 8148 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fstod_opf); 8149 ins_encode(form3_opf_rs2F_rdD(src, dst)); 8150 ins_pipe(fcvtF2D); 8151 %} 8152 8153 8154 instruct convF2I_helper(regF dst, regF src, flagsRegF0 fcc0) %{ 8155 effect(DEF dst, USE src, KILL fcc0); 8156 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t" 8157 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" 8158 "FSTOI $src,$dst\t! convert in delay slot\n\t" 8159 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t" 8160 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n" 8161 "skip:" %} 8162 ins_encode(form_f2i_helper(src,dst)); 8163 ins_pipe(fcvtF2I); 8164 %} 8165 8166 instruct convF2I_reg(stackSlotI dst, regF src) %{ 8167 match(Set dst (ConvF2I src)); 8168 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); 8169 expand %{ 8170 regF tmp; 8171 convF2I_helper(tmp, src); 8172 regF_to_stkI(dst, tmp); 8173 %} 8174 %} 8175 8176 8177 instruct convF2L_helper(regD dst, regF src, flagsRegF0 fcc0) %{ 8178 effect(DEF dst, USE src, KILL fcc0); 8179 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t" 8180 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" 8181 "FSTOX $src,$dst\t! convert in delay slot\n\t" 8182 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t" 8183 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n" 8184 "skip:" %} 8185 ins_encode(form_f2l_helper(src,dst)); 8186 ins_pipe(fcvtF2L); 8187 %} 8188 8189 // Float to Long conversion 8190 instruct convF2L_reg(stackSlotL dst, regF src) %{ 8191 match(Set dst (ConvF2L src)); 8192 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); 8193 expand %{ 8194 regD tmp; 8195 convF2L_helper(tmp, src); 8196 regD_to_stkL(dst, tmp); 8197 %} 8198 %} 8199 8200 8201 instruct convI2D_helper(regD dst, regF tmp) %{ 8202 effect(USE tmp, DEF dst); 8203 format %{ "FITOD $tmp,$dst" %} 8204 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf); 8205 ins_encode(form3_opf_rs2F_rdD(tmp, dst)); 8206 ins_pipe(fcvtI2D); 8207 %} 8208 8209 instruct convI2D_reg(stackSlotI src, regD dst) %{ 8210 match(Set dst (ConvI2D src)); 8211 ins_cost(DEFAULT_COST + MEMORY_REF_COST); 8212 expand %{ 8213 regF tmp; 8214 stkI_to_regF( tmp, src); 8215 convI2D_helper( dst, tmp); 8216 %} 8217 %} 8218 8219 instruct convI2D_mem( regD_low dst, memory mem ) %{ 8220 match(Set dst (ConvI2D (LoadI mem))); 8221 ins_cost(DEFAULT_COST + MEMORY_REF_COST); 8222 size(8); 8223 format %{ "LDF $mem,$dst\n\t" 8224 "FITOD $dst,$dst" %} 8225 opcode(Assembler::ldf_op3, Assembler::fitod_opf); 8226 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst)); 8227 ins_pipe(floadF_mem); 8228 %} 8229 8230 8231 instruct convI2F_helper(regF dst, regF tmp) %{ 8232 effect(DEF dst, USE tmp); 8233 format %{ "FITOS $tmp,$dst" %} 8234 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitos_opf); 8235 ins_encode(form3_opf_rs2F_rdF(tmp, dst)); 8236 ins_pipe(fcvtI2F); 8237 %} 8238 8239 instruct convI2F_reg( regF dst, stackSlotI src ) %{ 8240 match(Set dst (ConvI2F src)); 8241 ins_cost(DEFAULT_COST + MEMORY_REF_COST); 8242 expand %{ 8243 regF tmp; 8244 stkI_to_regF(tmp,src); 8245 convI2F_helper(dst, tmp); 8246 %} 8247 %} 8248 8249 instruct convI2F_mem( regF dst, memory mem ) %{ 8250 match(Set dst (ConvI2F (LoadI mem))); 8251 ins_cost(DEFAULT_COST + MEMORY_REF_COST); 8252 size(8); 8253 format %{ "LDF $mem,$dst\n\t" 8254 "FITOS $dst,$dst" %} 8255 opcode(Assembler::ldf_op3, Assembler::fitos_opf); 8256 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst)); 8257 ins_pipe(floadF_mem); 8258 %} 8259 8260 8261 instruct convI2L_reg(iRegL dst, iRegI src) %{ 8262 match(Set dst (ConvI2L src)); 8263 size(4); 8264 format %{ "SRA $src,0,$dst\t! int->long" %} 8265 opcode(Assembler::sra_op3, Assembler::arith_op); 8266 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) ); 8267 ins_pipe(ialu_reg_reg); 8268 %} 8269 8270 // Zero-extend convert int to long 8271 instruct convI2L_reg_zex(iRegL dst, iRegI src, immL_32bits mask ) %{ 8272 match(Set dst (AndL (ConvI2L src) mask) ); 8273 size(4); 8274 format %{ "SRL $src,0,$dst\t! zero-extend int to long" %} 8275 opcode(Assembler::srl_op3, Assembler::arith_op); 8276 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) ); 8277 ins_pipe(ialu_reg_reg); 8278 %} 8279 8280 // Zero-extend long 8281 instruct zerox_long(iRegL dst, iRegL src, immL_32bits mask ) %{ 8282 match(Set dst (AndL src mask) ); 8283 size(4); 8284 format %{ "SRL $src,0,$dst\t! zero-extend long" %} 8285 opcode(Assembler::srl_op3, Assembler::arith_op); 8286 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) ); 8287 ins_pipe(ialu_reg_reg); 8288 %} 8289 8290 instruct MoveF2I_stack_reg(iRegI dst, stackSlotF src) %{ 8291 match(Set dst (MoveF2I src)); 8292 effect(DEF dst, USE src); 8293 ins_cost(MEMORY_REF_COST); 8294 8295 size(4); 8296 format %{ "LDUW $src,$dst\t! MoveF2I" %} 8297 opcode(Assembler::lduw_op3); 8298 ins_encode(simple_form3_mem_reg( src, dst ) ); 8299 ins_pipe(iload_mem); 8300 %} 8301 8302 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{ 8303 match(Set dst (MoveI2F src)); 8304 effect(DEF dst, USE src); 8305 ins_cost(MEMORY_REF_COST); 8306 8307 size(4); 8308 format %{ "LDF $src,$dst\t! MoveI2F" %} 8309 opcode(Assembler::ldf_op3); 8310 ins_encode(simple_form3_mem_reg(src, dst)); 8311 ins_pipe(floadF_stk); 8312 %} 8313 8314 instruct MoveD2L_stack_reg(iRegL dst, stackSlotD src) %{ 8315 match(Set dst (MoveD2L src)); 8316 effect(DEF dst, USE src); 8317 ins_cost(MEMORY_REF_COST); 8318 8319 size(4); 8320 format %{ "LDX $src,$dst\t! MoveD2L" %} 8321 opcode(Assembler::ldx_op3); 8322 ins_encode(simple_form3_mem_reg( src, dst ) ); 8323 ins_pipe(iload_mem); 8324 %} 8325 8326 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{ 8327 match(Set dst (MoveL2D src)); 8328 effect(DEF dst, USE src); 8329 ins_cost(MEMORY_REF_COST); 8330 8331 size(4); 8332 format %{ "LDDF $src,$dst\t! MoveL2D" %} 8333 opcode(Assembler::lddf_op3); 8334 ins_encode(simple_form3_mem_reg(src, dst)); 8335 ins_pipe(floadD_stk); 8336 %} 8337 8338 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{ 8339 match(Set dst (MoveF2I src)); 8340 effect(DEF dst, USE src); 8341 ins_cost(MEMORY_REF_COST); 8342 8343 size(4); 8344 format %{ "STF $src,$dst\t!MoveF2I" %} 8345 opcode(Assembler::stf_op3); 8346 ins_encode(simple_form3_mem_reg(dst, src)); 8347 ins_pipe(fstoreF_stk_reg); 8348 %} 8349 8350 instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{ 8351 match(Set dst (MoveI2F src)); 8352 effect(DEF dst, USE src); 8353 ins_cost(MEMORY_REF_COST); 8354 8355 size(4); 8356 format %{ "STW $src,$dst\t!MoveI2F" %} 8357 opcode(Assembler::stw_op3); 8358 ins_encode(simple_form3_mem_reg( dst, src ) ); 8359 ins_pipe(istore_mem_reg); 8360 %} 8361 8362 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{ 8363 match(Set dst (MoveD2L src)); 8364 effect(DEF dst, USE src); 8365 ins_cost(MEMORY_REF_COST); 8366 8367 size(4); 8368 format %{ "STDF $src,$dst\t!MoveD2L" %} 8369 opcode(Assembler::stdf_op3); 8370 ins_encode(simple_form3_mem_reg(dst, src)); 8371 ins_pipe(fstoreD_stk_reg); 8372 %} 8373 8374 instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{ 8375 match(Set dst (MoveL2D src)); 8376 effect(DEF dst, USE src); 8377 ins_cost(MEMORY_REF_COST); 8378 8379 size(4); 8380 format %{ "STX $src,$dst\t!MoveL2D" %} 8381 opcode(Assembler::stx_op3); 8382 ins_encode(simple_form3_mem_reg( dst, src ) ); 8383 ins_pipe(istore_mem_reg); 8384 %} 8385 8386 8387 //----------- 8388 // Long to Double conversion using V8 opcodes. 8389 // Still useful because cheetah traps and becomes 8390 // amazingly slow for some common numbers. 8391 8392 // Magic constant, 0x43300000 8393 instruct loadConI_x43300000(iRegI dst) %{ 8394 effect(DEF dst); 8395 size(4); 8396 format %{ "SETHI HI(0x43300000),$dst\t! 2^52" %} 8397 ins_encode(SetHi22(0x43300000, dst)); 8398 ins_pipe(ialu_none); 8399 %} 8400 8401 // Magic constant, 0x41f00000 8402 instruct loadConI_x41f00000(iRegI dst) %{ 8403 effect(DEF dst); 8404 size(4); 8405 format %{ "SETHI HI(0x41f00000),$dst\t! 2^32" %} 8406 ins_encode(SetHi22(0x41f00000, dst)); 8407 ins_pipe(ialu_none); 8408 %} 8409 8410 // Construct a double from two float halves 8411 instruct regDHi_regDLo_to_regD(regD_low dst, regD_low src1, regD_low src2) %{ 8412 effect(DEF dst, USE src1, USE src2); 8413 size(8); 8414 format %{ "FMOVS $src1.hi,$dst.hi\n\t" 8415 "FMOVS $src2.lo,$dst.lo" %} 8416 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmovs_opf); 8417 ins_encode(form3_opf_rs2D_hi_rdD_hi(src1, dst), form3_opf_rs2D_lo_rdD_lo(src2, dst)); 8418 ins_pipe(faddD_reg_reg); 8419 %} 8420 8421 // Convert integer in high half of a double register (in the lower half of 8422 // the double register file) to double 8423 instruct convI2D_regDHi_regD(regD dst, regD_low src) %{ 8424 effect(DEF dst, USE src); 8425 size(4); 8426 format %{ "FITOD $src,$dst" %} 8427 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf); 8428 ins_encode(form3_opf_rs2D_rdD(src, dst)); 8429 ins_pipe(fcvtLHi2D); 8430 %} 8431 8432 // Add float double precision 8433 instruct addD_regD_regD(regD dst, regD src1, regD src2) %{ 8434 effect(DEF dst, USE src1, USE src2); 8435 size(4); 8436 format %{ "FADDD $src1,$src2,$dst" %} 8437 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf); 8438 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); 8439 ins_pipe(faddD_reg_reg); 8440 %} 8441 8442 // Sub float double precision 8443 instruct subD_regD_regD(regD dst, regD src1, regD src2) %{ 8444 effect(DEF dst, USE src1, USE src2); 8445 size(4); 8446 format %{ "FSUBD $src1,$src2,$dst" %} 8447 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf); 8448 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); 8449 ins_pipe(faddD_reg_reg); 8450 %} 8451 8452 // Mul float double precision 8453 instruct mulD_regD_regD(regD dst, regD src1, regD src2) %{ 8454 effect(DEF dst, USE src1, USE src2); 8455 size(4); 8456 format %{ "FMULD $src1,$src2,$dst" %} 8457 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf); 8458 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); 8459 ins_pipe(fmulD_reg_reg); 8460 %} 8461 8462 instruct convL2D_reg_slow_fxtof(regD dst, stackSlotL src) %{ 8463 match(Set dst (ConvL2D src)); 8464 ins_cost(DEFAULT_COST*8 + MEMORY_REF_COST*6); 8465 8466 expand %{ 8467 regD_low tmpsrc; 8468 iRegI ix43300000; 8469 iRegI ix41f00000; 8470 stackSlotL lx43300000; 8471 stackSlotL lx41f00000; 8472 regD_low dx43300000; 8473 regD dx41f00000; 8474 regD tmp1; 8475 regD_low tmp2; 8476 regD tmp3; 8477 regD tmp4; 8478 8479 stkL_to_regD(tmpsrc, src); 8480 8481 loadConI_x43300000(ix43300000); 8482 loadConI_x41f00000(ix41f00000); 8483 regI_to_stkLHi(lx43300000, ix43300000); 8484 regI_to_stkLHi(lx41f00000, ix41f00000); 8485 stkL_to_regD(dx43300000, lx43300000); 8486 stkL_to_regD(dx41f00000, lx41f00000); 8487 8488 convI2D_regDHi_regD(tmp1, tmpsrc); 8489 regDHi_regDLo_to_regD(tmp2, dx43300000, tmpsrc); 8490 subD_regD_regD(tmp3, tmp2, dx43300000); 8491 mulD_regD_regD(tmp4, tmp1, dx41f00000); 8492 addD_regD_regD(dst, tmp3, tmp4); 8493 %} 8494 %} 8495 8496 // Long to Double conversion using fast fxtof 8497 instruct convL2D_helper(regD dst, regD tmp) %{ 8498 effect(DEF dst, USE tmp); 8499 size(4); 8500 format %{ "FXTOD $tmp,$dst" %} 8501 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtod_opf); 8502 ins_encode(form3_opf_rs2D_rdD(tmp, dst)); 8503 ins_pipe(fcvtL2D); 8504 %} 8505 8506 instruct convL2D_reg_fast_fxtof(regD dst, stackSlotL src) %{ 8507 predicate(VM_Version::has_fast_fxtof()); 8508 match(Set dst (ConvL2D src)); 8509 ins_cost(DEFAULT_COST + 3 * MEMORY_REF_COST); 8510 expand %{ 8511 regD tmp; 8512 stkL_to_regD(tmp, src); 8513 convL2D_helper(dst, tmp); 8514 %} 8515 %} 8516 8517 //----------- 8518 // Long to Float conversion using V8 opcodes. 8519 // Still useful because cheetah traps and becomes 8520 // amazingly slow for some common numbers. 8521 8522 // Long to Float conversion using fast fxtof 8523 instruct convL2F_helper(regF dst, regD tmp) %{ 8524 effect(DEF dst, USE tmp); 8525 size(4); 8526 format %{ "FXTOS $tmp,$dst" %} 8527 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtos_opf); 8528 ins_encode(form3_opf_rs2D_rdF(tmp, dst)); 8529 ins_pipe(fcvtL2F); 8530 %} 8531 8532 instruct convL2F_reg_fast_fxtof(regF dst, stackSlotL src) %{ 8533 match(Set dst (ConvL2F src)); 8534 ins_cost(DEFAULT_COST + MEMORY_REF_COST); 8535 expand %{ 8536 regD tmp; 8537 stkL_to_regD(tmp, src); 8538 convL2F_helper(dst, tmp); 8539 %} 8540 %} 8541 //----------- 8542 8543 instruct convL2I_reg(iRegI dst, iRegL src) %{ 8544 match(Set dst (ConvL2I src)); 8545 #ifndef _LP64 8546 format %{ "MOV $src.lo,$dst\t! long->int" %} 8547 ins_encode( form3_g0_rs2_rd_move_lo2( src, dst ) ); 8548 ins_pipe(ialu_move_reg_I_to_L); 8549 #else 8550 size(4); 8551 format %{ "SRA $src,R_G0,$dst\t! long->int" %} 8552 ins_encode( form3_rs1_rd_signextend_lo1( src, dst ) ); 8553 ins_pipe(ialu_reg); 8554 #endif 8555 %} 8556 8557 // Register Shift Right Immediate 8558 instruct shrL_reg_imm6_L2I(iRegI dst, iRegL src, immI_32_63 cnt) %{ 8559 match(Set dst (ConvL2I (RShiftL src cnt))); 8560 8561 size(4); 8562 format %{ "SRAX $src,$cnt,$dst" %} 8563 opcode(Assembler::srax_op3, Assembler::arith_op); 8564 ins_encode( form3_sd_rs1_imm6_rd( src, cnt, dst ) ); 8565 ins_pipe(ialu_reg_imm); 8566 %} 8567 8568 // Replicate scalar to packed byte values in Double register 8569 instruct Repl8B_reg_helper(iRegL dst, iRegI src) %{ 8570 effect(DEF dst, USE src); 8571 format %{ "SLLX $src,56,$dst\n\t" 8572 "SRLX $dst, 8,O7\n\t" 8573 "OR $dst,O7,$dst\n\t" 8574 "SRLX $dst,16,O7\n\t" 8575 "OR $dst,O7,$dst\n\t" 8576 "SRLX $dst,32,O7\n\t" 8577 "OR $dst,O7,$dst\t! replicate8B" %} 8578 ins_encode( enc_repl8b(src, dst)); 8579 ins_pipe(ialu_reg); 8580 %} 8581 8582 // Replicate scalar to packed byte values in Double register 8583 instruct Repl8B_reg(stackSlotD dst, iRegI src) %{ 8584 match(Set dst (Replicate8B src)); 8585 expand %{ 8586 iRegL tmp; 8587 Repl8B_reg_helper(tmp, src); 8588 regL_to_stkD(dst, tmp); 8589 %} 8590 %} 8591 8592 // Replicate scalar constant to packed byte values in Double register 8593 instruct Repl8B_immI(regD dst, immI13 src, o7RegP tmp) %{ 8594 match(Set dst (Replicate8B src)); 8595 #ifdef _LP64 8596 size(36); 8597 #else 8598 size(8); 8599 #endif 8600 format %{ "SETHI hi(&Repl8($src)),$tmp\t!get Repl8B($src) from table\n\t" 8601 "LDDF [$tmp+lo(&Repl8($src))],$dst" %} 8602 ins_encode( LdReplImmI(src, dst, tmp, (8), (1)) ); 8603 ins_pipe(loadConFD); 8604 %} 8605 8606 // Replicate scalar to packed char values into stack slot 8607 instruct Repl4C_reg_helper(iRegL dst, iRegI src) %{ 8608 effect(DEF dst, USE src); 8609 format %{ "SLLX $src,48,$dst\n\t" 8610 "SRLX $dst,16,O7\n\t" 8611 "OR $dst,O7,$dst\n\t" 8612 "SRLX $dst,32,O7\n\t" 8613 "OR $dst,O7,$dst\t! replicate4C" %} 8614 ins_encode( enc_repl4s(src, dst) ); 8615 ins_pipe(ialu_reg); 8616 %} 8617 8618 // Replicate scalar to packed char values into stack slot 8619 instruct Repl4C_reg(stackSlotD dst, iRegI src) %{ 8620 match(Set dst (Replicate4C src)); 8621 expand %{ 8622 iRegL tmp; 8623 Repl4C_reg_helper(tmp, src); 8624 regL_to_stkD(dst, tmp); 8625 %} 8626 %} 8627 8628 // Replicate scalar constant to packed char values in Double register 8629 instruct Repl4C_immI(regD dst, immI src, o7RegP tmp) %{ 8630 match(Set dst (Replicate4C src)); 8631 #ifdef _LP64 8632 size(36); 8633 #else 8634 size(8); 8635 #endif 8636 format %{ "SETHI hi(&Repl4($src)),$tmp\t!get Repl4C($src) from table\n\t" 8637 "LDDF [$tmp+lo(&Repl4($src))],$dst" %} 8638 ins_encode( LdReplImmI(src, dst, tmp, (4), (2)) ); 8639 ins_pipe(loadConFD); 8640 %} 8641 8642 // Replicate scalar to packed short values into stack slot 8643 instruct Repl4S_reg_helper(iRegL dst, iRegI src) %{ 8644 effect(DEF dst, USE src); 8645 format %{ "SLLX $src,48,$dst\n\t" 8646 "SRLX $dst,16,O7\n\t" 8647 "OR $dst,O7,$dst\n\t" 8648 "SRLX $dst,32,O7\n\t" 8649 "OR $dst,O7,$dst\t! replicate4S" %} 8650 ins_encode( enc_repl4s(src, dst) ); 8651 ins_pipe(ialu_reg); 8652 %} 8653 8654 // Replicate scalar to packed short values into stack slot 8655 instruct Repl4S_reg(stackSlotD dst, iRegI src) %{ 8656 match(Set dst (Replicate4S src)); 8657 expand %{ 8658 iRegL tmp; 8659 Repl4S_reg_helper(tmp, src); 8660 regL_to_stkD(dst, tmp); 8661 %} 8662 %} 8663 8664 // Replicate scalar constant to packed short values in Double register 8665 instruct Repl4S_immI(regD dst, immI src, o7RegP tmp) %{ 8666 match(Set dst (Replicate4S src)); 8667 #ifdef _LP64 8668 size(36); 8669 #else 8670 size(8); 8671 #endif 8672 format %{ "SETHI hi(&Repl4($src)),$tmp\t!get Repl4S($src) from table\n\t" 8673 "LDDF [$tmp+lo(&Repl4($src))],$dst" %} 8674 ins_encode( LdReplImmI(src, dst, tmp, (4), (2)) ); 8675 ins_pipe(loadConFD); 8676 %} 8677 8678 // Replicate scalar to packed int values in Double register 8679 instruct Repl2I_reg_helper(iRegL dst, iRegI src) %{ 8680 effect(DEF dst, USE src); 8681 format %{ "SLLX $src,32,$dst\n\t" 8682 "SRLX $dst,32,O7\n\t" 8683 "OR $dst,O7,$dst\t! replicate2I" %} 8684 ins_encode( enc_repl2i(src, dst)); 8685 ins_pipe(ialu_reg); 8686 %} 8687 8688 // Replicate scalar to packed int values in Double register 8689 instruct Repl2I_reg(stackSlotD dst, iRegI src) %{ 8690 match(Set dst (Replicate2I src)); 8691 expand %{ 8692 iRegL tmp; 8693 Repl2I_reg_helper(tmp, src); 8694 regL_to_stkD(dst, tmp); 8695 %} 8696 %} 8697 8698 // Replicate scalar zero constant to packed int values in Double register 8699 instruct Repl2I_immI(regD dst, immI src, o7RegP tmp) %{ 8700 match(Set dst (Replicate2I src)); 8701 #ifdef _LP64 8702 size(36); 8703 #else 8704 size(8); 8705 #endif 8706 format %{ "SETHI hi(&Repl2($src)),$tmp\t!get Repl2I($src) from table\n\t" 8707 "LDDF [$tmp+lo(&Repl2($src))],$dst" %} 8708 ins_encode( LdReplImmI(src, dst, tmp, (2), (4)) ); 8709 ins_pipe(loadConFD); 8710 %} 8711 8712 //----------Control Flow Instructions------------------------------------------ 8713 // Compare Instructions 8714 // Compare Integers 8715 instruct compI_iReg(flagsReg icc, iRegI op1, iRegI op2) %{ 8716 match(Set icc (CmpI op1 op2)); 8717 effect( DEF icc, USE op1, USE op2 ); 8718 8719 size(4); 8720 format %{ "CMP $op1,$op2" %} 8721 opcode(Assembler::subcc_op3, Assembler::arith_op); 8722 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); 8723 ins_pipe(ialu_cconly_reg_reg); 8724 %} 8725 8726 instruct compU_iReg(flagsRegU icc, iRegI op1, iRegI op2) %{ 8727 match(Set icc (CmpU op1 op2)); 8728 8729 size(4); 8730 format %{ "CMP $op1,$op2\t! unsigned" %} 8731 opcode(Assembler::subcc_op3, Assembler::arith_op); 8732 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); 8733 ins_pipe(ialu_cconly_reg_reg); 8734 %} 8735 8736 instruct compI_iReg_imm13(flagsReg icc, iRegI op1, immI13 op2) %{ 8737 match(Set icc (CmpI op1 op2)); 8738 effect( DEF icc, USE op1 ); 8739 8740 size(4); 8741 format %{ "CMP $op1,$op2" %} 8742 opcode(Assembler::subcc_op3, Assembler::arith_op); 8743 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); 8744 ins_pipe(ialu_cconly_reg_imm); 8745 %} 8746 8747 instruct testI_reg_reg( flagsReg icc, iRegI op1, iRegI op2, immI0 zero ) %{ 8748 match(Set icc (CmpI (AndI op1 op2) zero)); 8749 8750 size(4); 8751 format %{ "BTST $op2,$op1" %} 8752 opcode(Assembler::andcc_op3, Assembler::arith_op); 8753 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); 8754 ins_pipe(ialu_cconly_reg_reg_zero); 8755 %} 8756 8757 instruct testI_reg_imm( flagsReg icc, iRegI op1, immI13 op2, immI0 zero ) %{ 8758 match(Set icc (CmpI (AndI op1 op2) zero)); 8759 8760 size(4); 8761 format %{ "BTST $op2,$op1" %} 8762 opcode(Assembler::andcc_op3, Assembler::arith_op); 8763 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); 8764 ins_pipe(ialu_cconly_reg_imm_zero); 8765 %} 8766 8767 instruct compL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2 ) %{ 8768 match(Set xcc (CmpL op1 op2)); 8769 effect( DEF xcc, USE op1, USE op2 ); 8770 8771 size(4); 8772 format %{ "CMP $op1,$op2\t\t! long" %} 8773 opcode(Assembler::subcc_op3, Assembler::arith_op); 8774 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); 8775 ins_pipe(ialu_cconly_reg_reg); 8776 %} 8777 8778 instruct compL_reg_con(flagsRegL xcc, iRegL op1, immL13 con) %{ 8779 match(Set xcc (CmpL op1 con)); 8780 effect( DEF xcc, USE op1, USE con ); 8781 8782 size(4); 8783 format %{ "CMP $op1,$con\t\t! long" %} 8784 opcode(Assembler::subcc_op3, Assembler::arith_op); 8785 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) ); 8786 ins_pipe(ialu_cconly_reg_reg); 8787 %} 8788 8789 instruct testL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2, immL0 zero) %{ 8790 match(Set xcc (CmpL (AndL op1 op2) zero)); 8791 effect( DEF xcc, USE op1, USE op2 ); 8792 8793 size(4); 8794 format %{ "BTST $op1,$op2\t\t! long" %} 8795 opcode(Assembler::andcc_op3, Assembler::arith_op); 8796 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); 8797 ins_pipe(ialu_cconly_reg_reg); 8798 %} 8799 8800 // useful for checking the alignment of a pointer: 8801 instruct testL_reg_con(flagsRegL xcc, iRegL op1, immL13 con, immL0 zero) %{ 8802 match(Set xcc (CmpL (AndL op1 con) zero)); 8803 effect( DEF xcc, USE op1, USE con ); 8804 8805 size(4); 8806 format %{ "BTST $op1,$con\t\t! long" %} 8807 opcode(Assembler::andcc_op3, Assembler::arith_op); 8808 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) ); 8809 ins_pipe(ialu_cconly_reg_reg); 8810 %} 8811 8812 instruct compU_iReg_imm13(flagsRegU icc, iRegI op1, immU13 op2 ) %{ 8813 match(Set icc (CmpU op1 op2)); 8814 8815 size(4); 8816 format %{ "CMP $op1,$op2\t! unsigned" %} 8817 opcode(Assembler::subcc_op3, Assembler::arith_op); 8818 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); 8819 ins_pipe(ialu_cconly_reg_imm); 8820 %} 8821 8822 // Compare Pointers 8823 instruct compP_iRegP(flagsRegP pcc, iRegP op1, iRegP op2 ) %{ 8824 match(Set pcc (CmpP op1 op2)); 8825 8826 size(4); 8827 format %{ "CMP $op1,$op2\t! ptr" %} 8828 opcode(Assembler::subcc_op3, Assembler::arith_op); 8829 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); 8830 ins_pipe(ialu_cconly_reg_reg); 8831 %} 8832 8833 instruct compP_iRegP_imm13(flagsRegP pcc, iRegP op1, immP13 op2 ) %{ 8834 match(Set pcc (CmpP op1 op2)); 8835 8836 size(4); 8837 format %{ "CMP $op1,$op2\t! ptr" %} 8838 opcode(Assembler::subcc_op3, Assembler::arith_op); 8839 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); 8840 ins_pipe(ialu_cconly_reg_imm); 8841 %} 8842 8843 // Compare Narrow oops 8844 instruct compN_iRegN(flagsReg icc, iRegN op1, iRegN op2 ) %{ 8845 match(Set icc (CmpN op1 op2)); 8846 8847 size(4); 8848 format %{ "CMP $op1,$op2\t! compressed ptr" %} 8849 opcode(Assembler::subcc_op3, Assembler::arith_op); 8850 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); 8851 ins_pipe(ialu_cconly_reg_reg); 8852 %} 8853 8854 instruct compN_iRegN_immN0(flagsReg icc, iRegN op1, immN0 op2 ) %{ 8855 match(Set icc (CmpN op1 op2)); 8856 8857 size(4); 8858 format %{ "CMP $op1,$op2\t! compressed ptr" %} 8859 opcode(Assembler::subcc_op3, Assembler::arith_op); 8860 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); 8861 ins_pipe(ialu_cconly_reg_imm); 8862 %} 8863 8864 //----------Max and Min-------------------------------------------------------- 8865 // Min Instructions 8866 // Conditional move for min 8867 instruct cmovI_reg_lt( iRegI op2, iRegI op1, flagsReg icc ) %{ 8868 effect( USE_DEF op2, USE op1, USE icc ); 8869 8870 size(4); 8871 format %{ "MOVlt icc,$op1,$op2\t! min" %} 8872 opcode(Assembler::less); 8873 ins_encode( enc_cmov_reg_minmax(op2,op1) ); 8874 ins_pipe(ialu_reg_flags); 8875 %} 8876 8877 // Min Register with Register. 8878 instruct minI_eReg(iRegI op1, iRegI op2) %{ 8879 match(Set op2 (MinI op1 op2)); 8880 ins_cost(DEFAULT_COST*2); 8881 expand %{ 8882 flagsReg icc; 8883 compI_iReg(icc,op1,op2); 8884 cmovI_reg_lt(op2,op1,icc); 8885 %} 8886 %} 8887 8888 // Max Instructions 8889 // Conditional move for max 8890 instruct cmovI_reg_gt( iRegI op2, iRegI op1, flagsReg icc ) %{ 8891 effect( USE_DEF op2, USE op1, USE icc ); 8892 format %{ "MOVgt icc,$op1,$op2\t! max" %} 8893 opcode(Assembler::greater); 8894 ins_encode( enc_cmov_reg_minmax(op2,op1) ); 8895 ins_pipe(ialu_reg_flags); 8896 %} 8897 8898 // Max Register with Register 8899 instruct maxI_eReg(iRegI op1, iRegI op2) %{ 8900 match(Set op2 (MaxI op1 op2)); 8901 ins_cost(DEFAULT_COST*2); 8902 expand %{ 8903 flagsReg icc; 8904 compI_iReg(icc,op1,op2); 8905 cmovI_reg_gt(op2,op1,icc); 8906 %} 8907 %} 8908 8909 8910 //----------Float Compares---------------------------------------------------- 8911 // Compare floating, generate condition code 8912 instruct cmpF_cc(flagsRegF fcc, regF src1, regF src2) %{ 8913 match(Set fcc (CmpF src1 src2)); 8914 8915 size(4); 8916 format %{ "FCMPs $fcc,$src1,$src2" %} 8917 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmps_opf); 8918 ins_encode( form3_opf_rs1F_rs2F_fcc( src1, src2, fcc ) ); 8919 ins_pipe(faddF_fcc_reg_reg_zero); 8920 %} 8921 8922 instruct cmpD_cc(flagsRegF fcc, regD src1, regD src2) %{ 8923 match(Set fcc (CmpD src1 src2)); 8924 8925 size(4); 8926 format %{ "FCMPd $fcc,$src1,$src2" %} 8927 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmpd_opf); 8928 ins_encode( form3_opf_rs1D_rs2D_fcc( src1, src2, fcc ) ); 8929 ins_pipe(faddD_fcc_reg_reg_zero); 8930 %} 8931 8932 8933 // Compare floating, generate -1,0,1 8934 instruct cmpF_reg(iRegI dst, regF src1, regF src2, flagsRegF0 fcc0) %{ 8935 match(Set dst (CmpF3 src1 src2)); 8936 effect(KILL fcc0); 8937 ins_cost(DEFAULT_COST*3+BRANCH_COST*3); 8938 format %{ "fcmpl $dst,$src1,$src2" %} 8939 // Primary = float 8940 opcode( true ); 8941 ins_encode( floating_cmp( dst, src1, src2 ) ); 8942 ins_pipe( floating_cmp ); 8943 %} 8944 8945 instruct cmpD_reg(iRegI dst, regD src1, regD src2, flagsRegF0 fcc0) %{ 8946 match(Set dst (CmpD3 src1 src2)); 8947 effect(KILL fcc0); 8948 ins_cost(DEFAULT_COST*3+BRANCH_COST*3); 8949 format %{ "dcmpl $dst,$src1,$src2" %} 8950 // Primary = double (not float) 8951 opcode( false ); 8952 ins_encode( floating_cmp( dst, src1, src2 ) ); 8953 ins_pipe( floating_cmp ); 8954 %} 8955 8956 //----------Branches--------------------------------------------------------- 8957 // Jump 8958 // (compare 'operand indIndex' and 'instruct addP_reg_reg' above) 8959 instruct jumpXtnd(iRegX switch_val, o7RegI table) %{ 8960 match(Jump switch_val); 8961 8962 ins_cost(350); 8963 8964 format %{ "SETHI [hi(table_base)],O7\n\t" 8965 "ADD O7, lo(table_base), O7\n\t" 8966 "LD [O7+$switch_val], O7\n\t" 8967 "JUMP O7" 8968 %} 8969 ins_encode( jump_enc( switch_val, table) ); 8970 ins_pc_relative(1); 8971 ins_pipe(ialu_reg_reg); 8972 %} 8973 8974 // Direct Branch. Use V8 version with longer range. 8975 instruct branch(label labl) %{ 8976 match(Goto); 8977 effect(USE labl); 8978 8979 size(8); 8980 ins_cost(BRANCH_COST); 8981 format %{ "BA $labl" %} 8982 // Prim = bits 24-22, Secnd = bits 31-30, Tert = cond 8983 opcode(Assembler::br_op2, Assembler::branch_op, Assembler::always); 8984 ins_encode( enc_ba( labl ) ); 8985 ins_pc_relative(1); 8986 ins_pipe(br); 8987 %} 8988 8989 // Conditional Direct Branch 8990 instruct branchCon(cmpOp cmp, flagsReg icc, label labl) %{ 8991 match(If cmp icc); 8992 effect(USE labl); 8993 8994 size(8); 8995 ins_cost(BRANCH_COST); 8996 format %{ "BP$cmp $icc,$labl" %} 8997 // Prim = bits 24-22, Secnd = bits 31-30 8998 ins_encode( enc_bp( labl, cmp, icc ) ); 8999 ins_pc_relative(1); 9000 ins_pipe(br_cc); 9001 %} 9002 9003 // Branch-on-register tests all 64 bits. We assume that values 9004 // in 64-bit registers always remains zero or sign extended 9005 // unless our code munges the high bits. Interrupts can chop 9006 // the high order bits to zero or sign at any time. 9007 instruct branchCon_regI(cmpOp_reg cmp, iRegI op1, immI0 zero, label labl) %{ 9008 match(If cmp (CmpI op1 zero)); 9009 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf)); 9010 effect(USE labl); 9011 9012 size(8); 9013 ins_cost(BRANCH_COST); 9014 format %{ "BR$cmp $op1,$labl" %} 9015 ins_encode( enc_bpr( labl, cmp, op1 ) ); 9016 ins_pc_relative(1); 9017 ins_pipe(br_reg); 9018 %} 9019 9020 instruct branchCon_regP(cmpOp_reg cmp, iRegP op1, immP0 null, label labl) %{ 9021 match(If cmp (CmpP op1 null)); 9022 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf)); 9023 effect(USE labl); 9024 9025 size(8); 9026 ins_cost(BRANCH_COST); 9027 format %{ "BR$cmp $op1,$labl" %} 9028 ins_encode( enc_bpr( labl, cmp, op1 ) ); 9029 ins_pc_relative(1); 9030 ins_pipe(br_reg); 9031 %} 9032 9033 instruct branchCon_regL(cmpOp_reg cmp, iRegL op1, immL0 zero, label labl) %{ 9034 match(If cmp (CmpL op1 zero)); 9035 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf)); 9036 effect(USE labl); 9037 9038 size(8); 9039 ins_cost(BRANCH_COST); 9040 format %{ "BR$cmp $op1,$labl" %} 9041 ins_encode( enc_bpr( labl, cmp, op1 ) ); 9042 ins_pc_relative(1); 9043 ins_pipe(br_reg); 9044 %} 9045 9046 instruct branchConU(cmpOpU cmp, flagsRegU icc, label labl) %{ 9047 match(If cmp icc); 9048 effect(USE labl); 9049 9050 format %{ "BP$cmp $icc,$labl" %} 9051 // Prim = bits 24-22, Secnd = bits 31-30 9052 ins_encode( enc_bp( labl, cmp, icc ) ); 9053 ins_pc_relative(1); 9054 ins_pipe(br_cc); 9055 %} 9056 9057 instruct branchConP(cmpOpP cmp, flagsRegP pcc, label labl) %{ 9058 match(If cmp pcc); 9059 effect(USE labl); 9060 9061 size(8); 9062 ins_cost(BRANCH_COST); 9063 format %{ "BP$cmp $pcc,$labl" %} 9064 // Prim = bits 24-22, Secnd = bits 31-30 9065 ins_encode( enc_bpx( labl, cmp, pcc ) ); 9066 ins_pc_relative(1); 9067 ins_pipe(br_cc); 9068 %} 9069 9070 instruct branchConF(cmpOpF cmp, flagsRegF fcc, label labl) %{ 9071 match(If cmp fcc); 9072 effect(USE labl); 9073 9074 size(8); 9075 ins_cost(BRANCH_COST); 9076 format %{ "FBP$cmp $fcc,$labl" %} 9077 // Prim = bits 24-22, Secnd = bits 31-30 9078 ins_encode( enc_fbp( labl, cmp, fcc ) ); 9079 ins_pc_relative(1); 9080 ins_pipe(br_fcc); 9081 %} 9082 9083 instruct branchLoopEnd(cmpOp cmp, flagsReg icc, label labl) %{ 9084 match(CountedLoopEnd cmp icc); 9085 effect(USE labl); 9086 9087 size(8); 9088 ins_cost(BRANCH_COST); 9089 format %{ "BP$cmp $icc,$labl\t! Loop end" %} 9090 // Prim = bits 24-22, Secnd = bits 31-30 9091 ins_encode( enc_bp( labl, cmp, icc ) ); 9092 ins_pc_relative(1); 9093 ins_pipe(br_cc); 9094 %} 9095 9096 instruct branchLoopEndU(cmpOpU cmp, flagsRegU icc, label labl) %{ 9097 match(CountedLoopEnd cmp icc); 9098 effect(USE labl); 9099 9100 size(8); 9101 ins_cost(BRANCH_COST); 9102 format %{ "BP$cmp $icc,$labl\t! Loop end" %} 9103 // Prim = bits 24-22, Secnd = bits 31-30 9104 ins_encode( enc_bp( labl, cmp, icc ) ); 9105 ins_pc_relative(1); 9106 ins_pipe(br_cc); 9107 %} 9108 9109 // ============================================================================ 9110 // Long Compare 9111 // 9112 // Currently we hold longs in 2 registers. Comparing such values efficiently 9113 // is tricky. The flavor of compare used depends on whether we are testing 9114 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit. 9115 // The GE test is the negated LT test. The LE test can be had by commuting 9116 // the operands (yielding a GE test) and then negating; negate again for the 9117 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the 9118 // NE test is negated from that. 9119 9120 // Due to a shortcoming in the ADLC, it mixes up expressions like: 9121 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the 9122 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections 9123 // are collapsed internally in the ADLC's dfa-gen code. The match for 9124 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the 9125 // foo match ends up with the wrong leaf. One fix is to not match both 9126 // reg-reg and reg-zero forms of long-compare. This is unfortunate because 9127 // both forms beat the trinary form of long-compare and both are very useful 9128 // on Intel which has so few registers. 9129 9130 instruct branchCon_long(cmpOp cmp, flagsRegL xcc, label labl) %{ 9131 match(If cmp xcc); 9132 effect(USE labl); 9133 9134 size(8); 9135 ins_cost(BRANCH_COST); 9136 format %{ "BP$cmp $xcc,$labl" %} 9137 // Prim = bits 24-22, Secnd = bits 31-30 9138 ins_encode( enc_bpl( labl, cmp, xcc ) ); 9139 ins_pc_relative(1); 9140 ins_pipe(br_cc); 9141 %} 9142 9143 // Manifest a CmpL3 result in an integer register. Very painful. 9144 // This is the test to avoid. 9145 instruct cmpL3_reg_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg ccr ) %{ 9146 match(Set dst (CmpL3 src1 src2) ); 9147 effect( KILL ccr ); 9148 ins_cost(6*DEFAULT_COST); 9149 size(24); 9150 format %{ "CMP $src1,$src2\t\t! long\n" 9151 "\tBLT,a,pn done\n" 9152 "\tMOV -1,$dst\t! delay slot\n" 9153 "\tBGT,a,pn done\n" 9154 "\tMOV 1,$dst\t! delay slot\n" 9155 "\tCLR $dst\n" 9156 "done:" %} 9157 ins_encode( cmpl_flag(src1,src2,dst) ); 9158 ins_pipe(cmpL_reg); 9159 %} 9160 9161 // Conditional move 9162 instruct cmovLL_reg(cmpOp cmp, flagsRegL xcc, iRegL dst, iRegL src) %{ 9163 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src))); 9164 ins_cost(150); 9165 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %} 9166 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); 9167 ins_pipe(ialu_reg); 9168 %} 9169 9170 instruct cmovLL_imm(cmpOp cmp, flagsRegL xcc, iRegL dst, immL0 src) %{ 9171 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src))); 9172 ins_cost(140); 9173 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %} 9174 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) ); 9175 ins_pipe(ialu_imm); 9176 %} 9177 9178 instruct cmovIL_reg(cmpOp cmp, flagsRegL xcc, iRegI dst, iRegI src) %{ 9179 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src))); 9180 ins_cost(150); 9181 format %{ "MOV$cmp $xcc,$src,$dst" %} 9182 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); 9183 ins_pipe(ialu_reg); 9184 %} 9185 9186 instruct cmovIL_imm(cmpOp cmp, flagsRegL xcc, iRegI dst, immI11 src) %{ 9187 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src))); 9188 ins_cost(140); 9189 format %{ "MOV$cmp $xcc,$src,$dst" %} 9190 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) ); 9191 ins_pipe(ialu_imm); 9192 %} 9193 9194 instruct cmovNL_reg(cmpOp cmp, flagsRegL xcc, iRegN dst, iRegN src) %{ 9195 match(Set dst (CMoveN (Binary cmp xcc) (Binary dst src))); 9196 ins_cost(150); 9197 format %{ "MOV$cmp $xcc,$src,$dst" %} 9198 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); 9199 ins_pipe(ialu_reg); 9200 %} 9201 9202 instruct cmovPL_reg(cmpOp cmp, flagsRegL xcc, iRegP dst, iRegP src) %{ 9203 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src))); 9204 ins_cost(150); 9205 format %{ "MOV$cmp $xcc,$src,$dst" %} 9206 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); 9207 ins_pipe(ialu_reg); 9208 %} 9209 9210 instruct cmovPL_imm(cmpOp cmp, flagsRegL xcc, iRegP dst, immP0 src) %{ 9211 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src))); 9212 ins_cost(140); 9213 format %{ "MOV$cmp $xcc,$src,$dst" %} 9214 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) ); 9215 ins_pipe(ialu_imm); 9216 %} 9217 9218 instruct cmovFL_reg(cmpOp cmp, flagsRegL xcc, regF dst, regF src) %{ 9219 match(Set dst (CMoveF (Binary cmp xcc) (Binary dst src))); 9220 ins_cost(150); 9221 opcode(0x101); 9222 format %{ "FMOVS$cmp $xcc,$src,$dst" %} 9223 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) ); 9224 ins_pipe(int_conditional_float_move); 9225 %} 9226 9227 instruct cmovDL_reg(cmpOp cmp, flagsRegL xcc, regD dst, regD src) %{ 9228 match(Set dst (CMoveD (Binary cmp xcc) (Binary dst src))); 9229 ins_cost(150); 9230 opcode(0x102); 9231 format %{ "FMOVD$cmp $xcc,$src,$dst" %} 9232 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) ); 9233 ins_pipe(int_conditional_float_move); 9234 %} 9235 9236 // ============================================================================ 9237 // Safepoint Instruction 9238 instruct safePoint_poll(iRegP poll) %{ 9239 match(SafePoint poll); 9240 effect(USE poll); 9241 9242 size(4); 9243 #ifdef _LP64 9244 format %{ "LDX [$poll],R_G0\t! Safepoint: poll for GC" %} 9245 #else 9246 format %{ "LDUW [$poll],R_G0\t! Safepoint: poll for GC" %} 9247 #endif 9248 ins_encode %{ 9249 __ relocate(relocInfo::poll_type); 9250 __ ld_ptr($poll$$Register, 0, G0); 9251 %} 9252 ins_pipe(loadPollP); 9253 %} 9254 9255 // ============================================================================ 9256 // Call Instructions 9257 // Call Java Static Instruction 9258 instruct CallStaticJavaDirect( method meth ) %{ 9259 match(CallStaticJava); 9260 effect(USE meth); 9261 9262 size(8); 9263 ins_cost(CALL_COST); 9264 format %{ "CALL,static ; NOP ==> " %} 9265 ins_encode( Java_Static_Call( meth ), call_epilog ); 9266 ins_pc_relative(1); 9267 ins_pipe(simple_call); 9268 %} 9269 9270 // Call Java Dynamic Instruction 9271 instruct CallDynamicJavaDirect( method meth ) %{ 9272 match(CallDynamicJava); 9273 effect(USE meth); 9274 9275 ins_cost(CALL_COST); 9276 format %{ "SET (empty),R_G5\n\t" 9277 "CALL,dynamic ; NOP ==> " %} 9278 ins_encode( Java_Dynamic_Call( meth ), call_epilog ); 9279 ins_pc_relative(1); 9280 ins_pipe(call); 9281 %} 9282 9283 // Call Runtime Instruction 9284 instruct CallRuntimeDirect(method meth, l7RegP l7) %{ 9285 match(CallRuntime); 9286 effect(USE meth, KILL l7); 9287 ins_cost(CALL_COST); 9288 format %{ "CALL,runtime" %} 9289 ins_encode( Java_To_Runtime( meth ), 9290 call_epilog, adjust_long_from_native_call ); 9291 ins_pc_relative(1); 9292 ins_pipe(simple_call); 9293 %} 9294 9295 // Call runtime without safepoint - same as CallRuntime 9296 instruct CallLeafDirect(method meth, l7RegP l7) %{ 9297 match(CallLeaf); 9298 effect(USE meth, KILL l7); 9299 ins_cost(CALL_COST); 9300 format %{ "CALL,runtime leaf" %} 9301 ins_encode( Java_To_Runtime( meth ), 9302 call_epilog, 9303 adjust_long_from_native_call ); 9304 ins_pc_relative(1); 9305 ins_pipe(simple_call); 9306 %} 9307 9308 // Call runtime without safepoint - same as CallLeaf 9309 instruct CallLeafNoFPDirect(method meth, l7RegP l7) %{ 9310 match(CallLeafNoFP); 9311 effect(USE meth, KILL l7); 9312 ins_cost(CALL_COST); 9313 format %{ "CALL,runtime leaf nofp" %} 9314 ins_encode( Java_To_Runtime( meth ), 9315 call_epilog, 9316 adjust_long_from_native_call ); 9317 ins_pc_relative(1); 9318 ins_pipe(simple_call); 9319 %} 9320 9321 // Tail Call; Jump from runtime stub to Java code. 9322 // Also known as an 'interprocedural jump'. 9323 // Target of jump will eventually return to caller. 9324 // TailJump below removes the return address. 9325 instruct TailCalljmpInd(g3RegP jump_target, inline_cache_regP method_oop) %{ 9326 match(TailCall jump_target method_oop ); 9327 9328 ins_cost(CALL_COST); 9329 format %{ "Jmp $jump_target ; NOP \t! $method_oop holds method oop" %} 9330 ins_encode(form_jmpl(jump_target)); 9331 ins_pipe(tail_call); 9332 %} 9333 9334 9335 // Return Instruction 9336 instruct Ret() %{ 9337 match(Return); 9338 9339 // The epilogue node did the ret already. 9340 size(0); 9341 format %{ "! return" %} 9342 ins_encode(); 9343 ins_pipe(empty); 9344 %} 9345 9346 9347 // Tail Jump; remove the return address; jump to target. 9348 // TailCall above leaves the return address around. 9349 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2). 9350 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a 9351 // "restore" before this instruction (in Epilogue), we need to materialize it 9352 // in %i0. 9353 instruct tailjmpInd(g1RegP jump_target, i0RegP ex_oop) %{ 9354 match( TailJump jump_target ex_oop ); 9355 ins_cost(CALL_COST); 9356 format %{ "! discard R_O7\n\t" 9357 "Jmp $jump_target ; ADD O7,8,O1 \t! $ex_oop holds exc. oop" %} 9358 ins_encode(form_jmpl_set_exception_pc(jump_target)); 9359 // opcode(Assembler::jmpl_op3, Assembler::arith_op); 9360 // The hack duplicates the exception oop into G3, so that CreateEx can use it there. 9361 // ins_encode( form3_rs1_simm13_rd( jump_target, 0x00, R_G0 ), move_return_pc_to_o1() ); 9362 ins_pipe(tail_call); 9363 %} 9364 9365 // Create exception oop: created by stack-crawling runtime code. 9366 // Created exception is now available to this handler, and is setup 9367 // just prior to jumping to this handler. No code emitted. 9368 instruct CreateException( o0RegP ex_oop ) 9369 %{ 9370 match(Set ex_oop (CreateEx)); 9371 ins_cost(0); 9372 9373 size(0); 9374 // use the following format syntax 9375 format %{ "! exception oop is in R_O0; no code emitted" %} 9376 ins_encode(); 9377 ins_pipe(empty); 9378 %} 9379 9380 9381 // Rethrow exception: 9382 // The exception oop will come in the first argument position. 9383 // Then JUMP (not call) to the rethrow stub code. 9384 instruct RethrowException() 9385 %{ 9386 match(Rethrow); 9387 ins_cost(CALL_COST); 9388 9389 // use the following format syntax 9390 format %{ "Jmp rethrow_stub" %} 9391 ins_encode(enc_rethrow); 9392 ins_pipe(tail_call); 9393 %} 9394 9395 9396 // Die now 9397 instruct ShouldNotReachHere( ) 9398 %{ 9399 match(Halt); 9400 ins_cost(CALL_COST); 9401 9402 size(4); 9403 // Use the following format syntax 9404 format %{ "ILLTRAP ; ShouldNotReachHere" %} 9405 ins_encode( form2_illtrap() ); 9406 ins_pipe(tail_call); 9407 %} 9408 9409 // ============================================================================ 9410 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass 9411 // array for an instance of the superklass. Set a hidden internal cache on a 9412 // hit (cache is checked with exposed code in gen_subtype_check()). Return 9413 // not zero for a miss or zero for a hit. The encoding ALSO sets flags. 9414 instruct partialSubtypeCheck( o0RegP index, o1RegP sub, o2RegP super, flagsRegP pcc, o7RegP o7 ) %{ 9415 match(Set index (PartialSubtypeCheck sub super)); 9416 effect( KILL pcc, KILL o7 ); 9417 ins_cost(DEFAULT_COST*10); 9418 format %{ "CALL PartialSubtypeCheck\n\tNOP" %} 9419 ins_encode( enc_PartialSubtypeCheck() ); 9420 ins_pipe(partial_subtype_check_pipe); 9421 %} 9422 9423 instruct partialSubtypeCheck_vs_zero( flagsRegP pcc, o1RegP sub, o2RegP super, immP0 zero, o0RegP idx, o7RegP o7 ) %{ 9424 match(Set pcc (CmpP (PartialSubtypeCheck sub super) zero)); 9425 effect( KILL idx, KILL o7 ); 9426 ins_cost(DEFAULT_COST*10); 9427 format %{ "CALL PartialSubtypeCheck\n\tNOP\t# (sets condition codes)" %} 9428 ins_encode( enc_PartialSubtypeCheck() ); 9429 ins_pipe(partial_subtype_check_pipe); 9430 %} 9431 9432 9433 // ============================================================================ 9434 // inlined locking and unlocking 9435 9436 instruct cmpFastLock(flagsRegP pcc, iRegP object, iRegP box, iRegP scratch2, o7RegP scratch ) %{ 9437 match(Set pcc (FastLock object box)); 9438 9439 effect(KILL scratch, TEMP scratch2); 9440 ins_cost(100); 9441 9442 size(4*112); // conservative overestimation ... 9443 format %{ "FASTLOCK $object, $box; KILL $scratch, $scratch2, $box" %} 9444 ins_encode( Fast_Lock(object, box, scratch, scratch2) ); 9445 ins_pipe(long_memory_op); 9446 %} 9447 9448 9449 instruct cmpFastUnlock(flagsRegP pcc, iRegP object, iRegP box, iRegP scratch2, o7RegP scratch ) %{ 9450 match(Set pcc (FastUnlock object box)); 9451 effect(KILL scratch, TEMP scratch2); 9452 ins_cost(100); 9453 9454 size(4*120); // conservative overestimation ... 9455 format %{ "FASTUNLOCK $object, $box; KILL $scratch, $scratch2, $box" %} 9456 ins_encode( Fast_Unlock(object, box, scratch, scratch2) ); 9457 ins_pipe(long_memory_op); 9458 %} 9459 9460 // Count and Base registers are fixed because the allocator cannot 9461 // kill unknown registers. The encodings are generic. 9462 instruct clear_array(iRegX cnt, iRegP base, iRegX temp, Universe dummy, flagsReg ccr) %{ 9463 match(Set dummy (ClearArray cnt base)); 9464 effect(TEMP temp, KILL ccr); 9465 ins_cost(300); 9466 format %{ "MOV $cnt,$temp\n" 9467 "loop: SUBcc $temp,8,$temp\t! Count down a dword of bytes\n" 9468 " BRge loop\t\t! Clearing loop\n" 9469 " STX G0,[$base+$temp]\t! delay slot" %} 9470 ins_encode( enc_Clear_Array(cnt, base, temp) ); 9471 ins_pipe(long_memory_op); 9472 %} 9473 9474 instruct string_compare(o0RegP str1, o1RegP str2, g3RegP tmp1, g4RegP tmp2, notemp_iRegI result, 9475 o7RegI tmp3, flagsReg ccr) %{ 9476 match(Set result (StrComp str1 str2)); 9477 effect(USE_KILL str1, USE_KILL str2, KILL tmp1, KILL tmp2, KILL ccr, KILL tmp3); 9478 ins_cost(300); 9479 format %{ "String Compare $str1,$str2 -> $result" %} 9480 ins_encode( enc_String_Compare(str1, str2, tmp1, tmp2, result) ); 9481 ins_pipe(long_memory_op); 9482 %} 9483 9484 instruct string_equals(o0RegP str1, o1RegP str2, g3RegP tmp1, g4RegP tmp2, notemp_iRegI result, 9485 o7RegI tmp3, flagsReg ccr) %{ 9486 match(Set result (StrEquals str1 str2)); 9487 effect(USE_KILL str1, USE_KILL str2, KILL tmp1, KILL tmp2, KILL ccr, KILL tmp3); 9488 ins_cost(300); 9489 format %{ "String Equals $str1,$str2 -> $result" %} 9490 ins_encode( enc_String_Equals(str1, str2, tmp1, tmp2, result) ); 9491 ins_pipe(long_memory_op); 9492 %} 9493 9494 instruct array_equals(o0RegP ary1, o1RegP ary2, g3RegP tmp1, g4RegP tmp2, notemp_iRegI result, 9495 flagsReg ccr) %{ 9496 match(Set result (AryEq ary1 ary2)); 9497 effect(USE_KILL ary1, USE_KILL ary2, KILL tmp1, KILL tmp2, KILL ccr); 9498 ins_cost(300); 9499 format %{ "Array Equals $ary1,$ary2 -> $result" %} 9500 ins_encode( enc_Array_Equals(ary1, ary2, tmp1, tmp2, result)); 9501 ins_pipe(long_memory_op); 9502 %} 9503 9504 9505 //---------- Zeros Count Instructions ------------------------------------------ 9506 9507 instruct countLeadingZerosI(iRegI dst, iRegI src, iRegI tmp, flagsReg cr) %{ 9508 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported 9509 match(Set dst (CountLeadingZerosI src)); 9510 effect(TEMP dst, TEMP tmp, KILL cr); 9511 9512 // x |= (x >> 1); 9513 // x |= (x >> 2); 9514 // x |= (x >> 4); 9515 // x |= (x >> 8); 9516 // x |= (x >> 16); 9517 // return (WORDBITS - popc(x)); 9518 format %{ "SRL $src,1,$dst\t! count leading zeros (int)\n\t" 9519 "OR $src,$tmp,$dst\n\t" 9520 "SRL $dst,2,$tmp\n\t" 9521 "OR $dst,$tmp,$dst\n\t" 9522 "SRL $dst,4,$tmp\n\t" 9523 "OR $dst,$tmp,$dst\n\t" 9524 "SRL $dst,8,$tmp\n\t" 9525 "OR $dst,$tmp,$dst\n\t" 9526 "SRL $dst,16,$tmp\n\t" 9527 "OR $dst,$tmp,$dst\n\t" 9528 "POPC $dst,$dst\n\t" 9529 "MOV 32,$tmp\n\t" 9530 "SUB $tmp,$dst,$dst" %} 9531 ins_encode %{ 9532 Register Rdst = $dst$$Register; 9533 Register Rsrc = $src$$Register; 9534 Register Rtmp = $tmp$$Register; 9535 __ srl(Rsrc, 1, Rtmp); 9536 __ or3(Rsrc, Rtmp, Rdst); 9537 __ srl(Rdst, 2, Rtmp); 9538 __ or3(Rdst, Rtmp, Rdst); 9539 __ srl(Rdst, 4, Rtmp); 9540 __ or3(Rdst, Rtmp, Rdst); 9541 __ srl(Rdst, 8, Rtmp); 9542 __ or3(Rdst, Rtmp, Rdst); 9543 __ srl(Rdst, 16, Rtmp); 9544 __ or3(Rdst, Rtmp, Rdst); 9545 __ popc(Rdst, Rdst); 9546 __ mov(BitsPerInt, Rtmp); 9547 __ sub(Rtmp, Rdst, Rdst); 9548 %} 9549 ins_pipe(ialu_reg); 9550 %} 9551 9552 instruct countLeadingZerosL(iRegI dst, iRegL src, iRegL tmp, flagsReg cr) %{ 9553 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported 9554 match(Set dst (CountLeadingZerosL src)); 9555 effect(TEMP dst, TEMP tmp, KILL cr); 9556 9557 // x |= (x >> 1); 9558 // x |= (x >> 2); 9559 // x |= (x >> 4); 9560 // x |= (x >> 8); 9561 // x |= (x >> 16); 9562 // x |= (x >> 32); 9563 // return (WORDBITS - popc(x)); 9564 format %{ "SRLX $src,1,$dst\t! count leading zeros (long)\n\t" 9565 "OR $src,$tmp,$dst\n\t" 9566 "SRLX $dst,2,$tmp\n\t" 9567 "OR $dst,$tmp,$dst\n\t" 9568 "SRLX $dst,4,$tmp\n\t" 9569 "OR $dst,$tmp,$dst\n\t" 9570 "SRLX $dst,8,$tmp\n\t" 9571 "OR $dst,$tmp,$dst\n\t" 9572 "SRLX $dst,16,$tmp\n\t" 9573 "OR $dst,$tmp,$dst\n\t" 9574 "SRLX $dst,32,$tmp\n\t" 9575 "OR $dst,$tmp,$dst\n\t" 9576 "POPC $dst,$dst\n\t" 9577 "MOV 64,$tmp\n\t" 9578 "SUB $tmp,$dst,$dst" %} 9579 ins_encode %{ 9580 Register Rdst = $dst$$Register; 9581 Register Rsrc = $src$$Register; 9582 Register Rtmp = $tmp$$Register; 9583 __ srlx(Rsrc, 1, Rtmp); 9584 __ or3(Rsrc, Rtmp, Rdst); 9585 __ srlx(Rdst, 2, Rtmp); 9586 __ or3(Rdst, Rtmp, Rdst); 9587 __ srlx(Rdst, 4, Rtmp); 9588 __ or3(Rdst, Rtmp, Rdst); 9589 __ srlx(Rdst, 8, Rtmp); 9590 __ or3(Rdst, Rtmp, Rdst); 9591 __ srlx(Rdst, 16, Rtmp); 9592 __ or3(Rdst, Rtmp, Rdst); 9593 __ srlx(Rdst, 32, Rtmp); 9594 __ or3(Rdst, Rtmp, Rdst); 9595 __ popc(Rdst, Rdst); 9596 __ mov(BitsPerLong, Rtmp); 9597 __ sub(Rtmp, Rdst, Rdst); 9598 %} 9599 ins_pipe(ialu_reg); 9600 %} 9601 9602 instruct countTrailingZerosI(iRegI dst, iRegI src, flagsReg cr) %{ 9603 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported 9604 match(Set dst (CountTrailingZerosI src)); 9605 effect(TEMP dst, KILL cr); 9606 9607 // return popc(~x & (x - 1)); 9608 format %{ "SUB $src,1,$dst\t! count trailing zeros (int)\n\t" 9609 "ANDN $dst,$src,$dst\n\t" 9610 "SRL $dst,R_G0,$dst\n\t" 9611 "POPC $dst,$dst" %} 9612 ins_encode %{ 9613 Register Rdst = $dst$$Register; 9614 Register Rsrc = $src$$Register; 9615 __ sub(Rsrc, 1, Rdst); 9616 __ andn(Rdst, Rsrc, Rdst); 9617 __ srl(Rdst, G0, Rdst); 9618 __ popc(Rdst, Rdst); 9619 %} 9620 ins_pipe(ialu_reg); 9621 %} 9622 9623 instruct countTrailingZerosL(iRegI dst, iRegL src, flagsReg cr) %{ 9624 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported 9625 match(Set dst (CountTrailingZerosL src)); 9626 effect(TEMP dst, KILL cr); 9627 9628 // return popc(~x & (x - 1)); 9629 format %{ "SUB $src,1,$dst\t! count trailing zeros (long)\n\t" 9630 "ANDN $dst,$src,$dst\n\t" 9631 "POPC $dst,$dst" %} 9632 ins_encode %{ 9633 Register Rdst = $dst$$Register; 9634 Register Rsrc = $src$$Register; 9635 __ sub(Rsrc, 1, Rdst); 9636 __ andn(Rdst, Rsrc, Rdst); 9637 __ popc(Rdst, Rdst); 9638 %} 9639 ins_pipe(ialu_reg); 9640 %} 9641 9642 9643 //---------- Population Count Instructions ------------------------------------- 9644 9645 instruct popCountI(iRegI dst, iRegI src) %{ 9646 predicate(UsePopCountInstruction); 9647 match(Set dst (PopCountI src)); 9648 9649 format %{ "POPC $src, $dst" %} 9650 ins_encode %{ 9651 __ popc($src$$Register, $dst$$Register); 9652 %} 9653 ins_pipe(ialu_reg); 9654 %} 9655 9656 // Note: Long.bitCount(long) returns an int. 9657 instruct popCountL(iRegI dst, iRegL src) %{ 9658 predicate(UsePopCountInstruction); 9659 match(Set dst (PopCountL src)); 9660 9661 format %{ "POPC $src, $dst" %} 9662 ins_encode %{ 9663 __ popc($src$$Register, $dst$$Register); 9664 %} 9665 ins_pipe(ialu_reg); 9666 %} 9667 9668 9669 // ============================================================================ 9670 //------------Bytes reverse-------------------------------------------------- 9671 9672 instruct bytes_reverse_int(iRegI dst, stackSlotI src) %{ 9673 match(Set dst (ReverseBytesI src)); 9674 effect(DEF dst, USE src); 9675 9676 // Op cost is artificially doubled to make sure that load or store 9677 // instructions are preferred over this one which requires a spill 9678 // onto a stack slot. 9679 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST); 9680 size(8); 9681 format %{ "LDUWA $src, $dst\t!asi=primary_little" %} 9682 opcode(Assembler::lduwa_op3); 9683 ins_encode( form3_mem_reg_little(src, dst) ); 9684 ins_pipe( iload_mem ); 9685 %} 9686 9687 instruct bytes_reverse_long(iRegL dst, stackSlotL src) %{ 9688 match(Set dst (ReverseBytesL src)); 9689 effect(DEF dst, USE src); 9690 9691 // Op cost is artificially doubled to make sure that load or store 9692 // instructions are preferred over this one which requires a spill 9693 // onto a stack slot. 9694 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST); 9695 size(8); 9696 format %{ "LDXA $src, $dst\t!asi=primary_little" %} 9697 9698 opcode(Assembler::ldxa_op3); 9699 ins_encode( form3_mem_reg_little(src, dst) ); 9700 ins_pipe( iload_mem ); 9701 %} 9702 9703 // Load Integer reversed byte order 9704 instruct loadI_reversed(iRegI dst, memory src) %{ 9705 match(Set dst (ReverseBytesI (LoadI src))); 9706 9707 ins_cost(DEFAULT_COST + MEMORY_REF_COST); 9708 size(8); 9709 format %{ "LDUWA $src, $dst\t!asi=primary_little" %} 9710 9711 opcode(Assembler::lduwa_op3); 9712 ins_encode( form3_mem_reg_little( src, dst) ); 9713 ins_pipe(iload_mem); 9714 %} 9715 9716 // Load Long - aligned and reversed 9717 instruct loadL_reversed(iRegL dst, memory src) %{ 9718 match(Set dst (ReverseBytesL (LoadL src))); 9719 9720 ins_cost(DEFAULT_COST + MEMORY_REF_COST); 9721 size(8); 9722 format %{ "LDXA $src, $dst\t!asi=primary_little" %} 9723 9724 opcode(Assembler::ldxa_op3); 9725 ins_encode( form3_mem_reg_little( src, dst ) ); 9726 ins_pipe(iload_mem); 9727 %} 9728 9729 // Store Integer reversed byte order 9730 instruct storeI_reversed(memory dst, iRegI src) %{ 9731 match(Set dst (StoreI dst (ReverseBytesI src))); 9732 9733 ins_cost(MEMORY_REF_COST); 9734 size(8); 9735 format %{ "STWA $src, $dst\t!asi=primary_little" %} 9736 9737 opcode(Assembler::stwa_op3); 9738 ins_encode( form3_mem_reg_little( dst, src) ); 9739 ins_pipe(istore_mem_reg); 9740 %} 9741 9742 // Store Long reversed byte order 9743 instruct storeL_reversed(memory dst, iRegL src) %{ 9744 match(Set dst (StoreL dst (ReverseBytesL src))); 9745 9746 ins_cost(MEMORY_REF_COST); 9747 size(8); 9748 format %{ "STXA $src, $dst\t!asi=primary_little" %} 9749 9750 opcode(Assembler::stxa_op3); 9751 ins_encode( form3_mem_reg_little( dst, src) ); 9752 ins_pipe(istore_mem_reg); 9753 %} 9754 9755 //----------PEEPHOLE RULES----------------------------------------------------- 9756 // These must follow all instruction definitions as they use the names 9757 // defined in the instructions definitions. 9758 // 9759 // peepmatch ( root_instr_name [preceding_instruction]* ); 9760 // 9761 // peepconstraint %{ 9762 // (instruction_number.operand_name relational_op instruction_number.operand_name 9763 // [, ...] ); 9764 // // instruction numbers are zero-based using left to right order in peepmatch 9765 // 9766 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) ); 9767 // // provide an instruction_number.operand_name for each operand that appears 9768 // // in the replacement instruction's match rule 9769 // 9770 // ---------VM FLAGS--------------------------------------------------------- 9771 // 9772 // All peephole optimizations can be turned off using -XX:-OptoPeephole 9773 // 9774 // Each peephole rule is given an identifying number starting with zero and 9775 // increasing by one in the order seen by the parser. An individual peephole 9776 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=# 9777 // on the command-line. 9778 // 9779 // ---------CURRENT LIMITATIONS---------------------------------------------- 9780 // 9781 // Only match adjacent instructions in same basic block 9782 // Only equality constraints 9783 // Only constraints between operands, not (0.dest_reg == EAX_enc) 9784 // Only one replacement instruction 9785 // 9786 // ---------EXAMPLE---------------------------------------------------------- 9787 // 9788 // // pertinent parts of existing instructions in architecture description 9789 // instruct movI(eRegI dst, eRegI src) %{ 9790 // match(Set dst (CopyI src)); 9791 // %} 9792 // 9793 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{ 9794 // match(Set dst (AddI dst src)); 9795 // effect(KILL cr); 9796 // %} 9797 // 9798 // // Change (inc mov) to lea 9799 // peephole %{ 9800 // // increment preceeded by register-register move 9801 // peepmatch ( incI_eReg movI ); 9802 // // require that the destination register of the increment 9803 // // match the destination register of the move 9804 // peepconstraint ( 0.dst == 1.dst ); 9805 // // construct a replacement instruction that sets 9806 // // the destination to ( move's source register + one ) 9807 // peepreplace ( incI_eReg_immI1( 0.dst 1.src 0.src ) ); 9808 // %} 9809 // 9810 9811 // // Change load of spilled value to only a spill 9812 // instruct storeI(memory mem, eRegI src) %{ 9813 // match(Set mem (StoreI mem src)); 9814 // %} 9815 // 9816 // instruct loadI(eRegI dst, memory mem) %{ 9817 // match(Set dst (LoadI mem)); 9818 // %} 9819 // 9820 // peephole %{ 9821 // peepmatch ( loadI storeI ); 9822 // peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem ); 9823 // peepreplace ( storeI( 1.mem 1.mem 1.src ) ); 9824 // %} 9825 9826 //----------SMARTSPILL RULES--------------------------------------------------- 9827 // These must follow all instruction definitions as they use the names 9828 // defined in the instructions definitions. 9829 // 9830 // SPARC will probably not have any of these rules due to RISC instruction set. 9831 9832 //----------PIPELINE----------------------------------------------------------- 9833 // Rules which define the behavior of the target architectures pipeline.