413 if( r0->is_con() && r0->get_con() > 0 )
414 return TypeInt::make(0, r0->get_con(), widen);
415
416 if( r1->is_con() && r1->get_con() > 0 )
417 return TypeInt::make(0, r1->get_con(), widen);
418
419 if( r0 == TypeInt::BOOL || r1 == TypeInt::BOOL ) {
420 return TypeInt::BOOL;
421 }
422
423 return TypeInt::INT; // No constants to be had
424 }
425
426 //------------------------------Identity---------------------------------------
427 // Masking off the high bits of an unsigned load is not required
428 Node *AndINode::Identity( PhaseTransform *phase ) {
429
430 // x & x => x
431 if (phase->eqv(in(1), in(2))) return in(1);
432
433 Node *load = in(1);
434 const TypeInt *t2 = phase->type( in(2) )->isa_int();
435 if( t2 && t2->is_con() ) {
436 int con = t2->get_con();
437 // Masking off high bits which are always zero is useless.
438 const TypeInt* t1 = phase->type( in(1) )->isa_int();
439 if (t1 != NULL && t1->_lo >= 0) {
440 jint t1_support = ((jint)1 << (1 + log2_intptr(t1->_hi))) - 1;
441 if ((t1_support & con) == t1_support)
442 return load;
443 }
444 uint lop = load->Opcode();
445 if( lop == Op_LoadUS &&
446 con == 0x0000FFFF ) // Already zero-extended
447 return load;
448 // Masking off the high bits of a unsigned-shift-right is not
449 // needed either.
450 if( lop == Op_URShiftI ) {
451 const TypeInt *t12 = phase->type( load->in(2) )->isa_int();
452 if( t12 && t12->is_con() ) { // Shift is by a constant
453 int shift = t12->get_con();
454 shift &= BitsPerJavaInteger - 1; // semantics of Java shifts
455 int mask = max_juint >> shift;
456 if( (mask&con) == mask ) // If AND is useless, skip it
457 return load;
458 }
459 }
460 }
461 return MulNode::Identity(phase);
462 }
463
464 //------------------------------Ideal------------------------------------------
465 Node *AndINode::Ideal(PhaseGVN *phase, bool can_reshape) {
466 // Special case constant AND mask
467 const TypeInt *t2 = phase->type( in(2) )->isa_int();
468 if( !t2 || !t2->is_con() ) return MulNode::Ideal(phase, can_reshape);
469 const int mask = t2->get_con();
470 Node *load = in(1);
471 uint lop = load->Opcode();
472
473 // Masking bits off of a Character? Hi bits are already zero.
474 if( lop == Op_LoadUS &&
475 (mask & 0xFFFF0000) ) // Can we make a smaller mask?
476 return new (phase->C, 3) AndINode(load,phase->intcon(mask&0xFFFF));
477
478 // Masking bits off of a Short? Loading a Character does some masking
479 if( lop == Op_LoadS &&
480 (mask & 0xFFFF0000) == 0 ) {
481 Node *ldus = new (phase->C, 3) LoadUSNode(load->in(MemNode::Control),
482 load->in(MemNode::Memory),
483 load->in(MemNode::Address),
484 load->adr_type());
485 ldus = phase->transform(ldus);
486 return new (phase->C, 3) AndINode(ldus, phase->intcon(mask&0xFFFF));
487 }
488
489 // Masking sign bits off of a Byte? Do an unsigned byte load.
490 if (lop == Op_LoadB && mask == 0x000000FF) {
491 return new (phase->C, 3) LoadUBNode(load->in(MemNode::Control),
492 load->in(MemNode::Memory),
493 load->in(MemNode::Address),
494 load->adr_type());
495 }
496
497 // Masking sign bits off of a Byte plus additional lower bits? Do
498 // an unsigned byte load plus an and.
499 if (lop == Op_LoadB && (mask & 0xFFFFFF00) == 0) {
500 Node* ldub = new (phase->C, 3) LoadUBNode(load->in(MemNode::Control),
501 load->in(MemNode::Memory),
502 load->in(MemNode::Address),
503 load->adr_type());
504 ldub = phase->transform(ldub);
505 return new (phase->C, 3) AndINode(ldub, phase->intcon(mask));
506 }
507
508 // Masking off sign bits? Dont make them!
509 if( lop == Op_RShiftI ) {
510 const TypeInt *t12 = phase->type(load->in(2))->isa_int();
511 if( t12 && t12->is_con() ) { // Shift is by a constant
512 int shift = t12->get_con();
513 shift &= BitsPerJavaInteger-1; // semantics of Java shifts
514 const int sign_bits_mask = ~right_n_bits(BitsPerJavaInteger - shift);
515 // If the AND'ing of the 2 masks has no bits, then only original shifted
516 // bits survive. NO sign-extension bits survive the maskings.
517 if( (sign_bits_mask & mask) == 0 ) {
518 // Use zero-fill shift instead
588 shift &= BitsPerJavaLong - 1; // semantics of Java shifts
589 jlong mask = max_julong >> shift;
590 if( (mask&con) == mask ) // If AND is useless, skip it
591 return usr;
592 }
593 }
594 }
595 return MulNode::Identity(phase);
596 }
597
598 //------------------------------Ideal------------------------------------------
599 Node *AndLNode::Ideal(PhaseGVN *phase, bool can_reshape) {
600 // Special case constant AND mask
601 const TypeLong *t2 = phase->type( in(2) )->isa_long();
602 if( !t2 || !t2->is_con() ) return MulNode::Ideal(phase, can_reshape);
603 const jlong mask = t2->get_con();
604
605 Node* in1 = in(1);
606 uint op = in1->Opcode();
607
608 // Masking sign bits off of an integer? Do an unsigned integer to long load.
609 if (op == Op_ConvI2L && in1->in(1)->Opcode() == Op_LoadI && mask == 0x00000000FFFFFFFFL) {
610 Node* load = in1->in(1);
611 return new (phase->C, 3) LoadUI2LNode(load->in(MemNode::Control),
612 load->in(MemNode::Memory),
613 load->in(MemNode::Address),
614 load->adr_type());
615 }
616
617 // Masking off sign bits? Dont make them!
618 if (op == Op_RShiftL) {
619 const TypeInt *t12 = phase->type(in1->in(2))->isa_int();
620 if( t12 && t12->is_con() ) { // Shift is by a constant
621 int shift = t12->get_con();
622 shift &= BitsPerJavaLong - 1; // semantics of Java shifts
623 const jlong sign_bits_mask = ~(((jlong)CONST64(1) << (jlong)(BitsPerJavaLong - shift)) -1);
624 // If the AND'ing of the 2 masks has no bits, then only original shifted
625 // bits survive. NO sign-extension bits survive the maskings.
626 if( (sign_bits_mask & mask) == 0 ) {
627 // Use zero-fill shift instead
628 Node *zshift = phase->transform(new (phase->C, 3) URShiftLNode(in1->in(1), in1->in(2)));
629 return new (phase->C, 3) AndLNode( zshift, in(2) );
630 }
631 }
632 }
633
634 return MulNode::Ideal(phase, can_reshape);
635 }
636
637 //=============================================================================
638 //------------------------------Identity---------------------------------------
639 Node *LShiftINode::Identity( PhaseTransform *phase ) {
640 const TypeInt *ti = phase->type( in(2) )->isa_int(); // shift count is an int
641 return ( ti && ti->is_con() && ( ti->get_con() & ( BitsPerInt - 1 ) ) == 0 ) ? in(1) : this;
642 }
643
644 //------------------------------Ideal------------------------------------------
645 // If the right input is a constant, and the left input is an add of a
646 // constant, flatten the tree: (X+con1)<<con0 ==> X<<con0 + con1<<con0
647 Node *LShiftINode::Ideal(PhaseGVN *phase, bool can_reshape) {
648 const Type *t = phase->type( in(2) );
649 if( t == Type::TOP ) return NULL; // Right input is dead
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413 if( r0->is_con() && r0->get_con() > 0 )
414 return TypeInt::make(0, r0->get_con(), widen);
415
416 if( r1->is_con() && r1->get_con() > 0 )
417 return TypeInt::make(0, r1->get_con(), widen);
418
419 if( r0 == TypeInt::BOOL || r1 == TypeInt::BOOL ) {
420 return TypeInt::BOOL;
421 }
422
423 return TypeInt::INT; // No constants to be had
424 }
425
426 //------------------------------Identity---------------------------------------
427 // Masking off the high bits of an unsigned load is not required
428 Node *AndINode::Identity( PhaseTransform *phase ) {
429
430 // x & x => x
431 if (phase->eqv(in(1), in(2))) return in(1);
432
433 Node* in1 = in(1);
434 uint op = in1->Opcode();
435 const TypeInt* t2 = phase->type(in(2))->isa_int();
436 if (t2 && t2->is_con()) {
437 int con = t2->get_con();
438 // Masking off high bits which are always zero is useless.
439 const TypeInt* t1 = phase->type( in(1) )->isa_int();
440 if (t1 != NULL && t1->_lo >= 0) {
441 jint t1_support = right_n_bits(1 + log2_intptr(t1->_hi - 1));
442 if ((t1_support & con) == t1_support)
443 return in1;
444 }
445 // if( lop == Op_LoadUS &&
446 // con == 0x0000FFFF ) // Already zero-extended
447 // return load;
448 // Masking off the high bits of a unsigned-shift-right is not
449 // needed either.
450 if (op == Op_URShiftI) {
451 const TypeInt* t12 = phase->type(in1->in(2))->isa_int();
452 if (t12 && t12->is_con()) { // Shift is by a constant
453 int shift = t12->get_con();
454 shift &= BitsPerJavaInteger - 1; // semantics of Java shifts
455 int mask = max_juint >> shift;
456 if ((mask & con) == mask) // If AND is useless, skip it
457 return in1;
458 }
459 }
460 }
461 return MulNode::Identity(phase);
462 }
463
464 //------------------------------Ideal------------------------------------------
465 Node *AndINode::Ideal(PhaseGVN *phase, bool can_reshape) {
466 // Special case constant AND mask
467 const TypeInt *t2 = phase->type( in(2) )->isa_int();
468 if( !t2 || !t2->is_con() ) return MulNode::Ideal(phase, can_reshape);
469 const int mask = t2->get_con();
470 Node *load = in(1);
471 uint lop = load->Opcode();
472
473 // Masking bits off of a Character? Hi bits are already zero.
474 if( lop == Op_LoadUS &&
475 (mask & 0xFFFF0000) ) // Can we make a smaller mask?
476 return new (phase->C, 3) AndINode(load,phase->intcon(mask&0xFFFF));
477
478 // Masking bits off of a Short? Loading a Character does some masking
479 if( lop == Op_LoadS &&
480 (mask & 0xFFFF0000) == 0 ) {
481 Node *ldus = new (phase->C, 3) LoadUSNode(load->in(MemNode::Control),
482 load->in(MemNode::Memory),
483 load->in(MemNode::Address),
484 load->adr_type());
485 ldus = phase->transform(ldus);
486 return new (phase->C, 3) AndINode(ldus, phase->intcon(mask&0xFFFF));
487 }
488
489 // Masking sign bits off of a Byte? Do an unsigned byte load plus
490 // an and.
491 if (lop == Op_LoadB && (mask & 0xFFFFFF00) == 0) {
492 Node* ldub = new (phase->C, 3) LoadUBNode(load->in(MemNode::Control),
493 load->in(MemNode::Memory),
494 load->in(MemNode::Address),
495 load->adr_type());
496 ldub = phase->transform(ldub);
497 return new (phase->C, 3) AndINode(ldub, phase->intcon(mask));
498 }
499
500 // Masking off sign bits? Dont make them!
501 if( lop == Op_RShiftI ) {
502 const TypeInt *t12 = phase->type(load->in(2))->isa_int();
503 if( t12 && t12->is_con() ) { // Shift is by a constant
504 int shift = t12->get_con();
505 shift &= BitsPerJavaInteger-1; // semantics of Java shifts
506 const int sign_bits_mask = ~right_n_bits(BitsPerJavaInteger - shift);
507 // If the AND'ing of the 2 masks has no bits, then only original shifted
508 // bits survive. NO sign-extension bits survive the maskings.
509 if( (sign_bits_mask & mask) == 0 ) {
510 // Use zero-fill shift instead
580 shift &= BitsPerJavaLong - 1; // semantics of Java shifts
581 jlong mask = max_julong >> shift;
582 if( (mask&con) == mask ) // If AND is useless, skip it
583 return usr;
584 }
585 }
586 }
587 return MulNode::Identity(phase);
588 }
589
590 //------------------------------Ideal------------------------------------------
591 Node *AndLNode::Ideal(PhaseGVN *phase, bool can_reshape) {
592 // Special case constant AND mask
593 const TypeLong *t2 = phase->type( in(2) )->isa_long();
594 if( !t2 || !t2->is_con() ) return MulNode::Ideal(phase, can_reshape);
595 const jlong mask = t2->get_con();
596
597 Node* in1 = in(1);
598 uint op = in1->Opcode();
599
600 // Masking sign bits off of an integer? Do an unsigned integer to
601 // long load.
602 // NOTE: This check must be *before* we try to convert the AndLNode
603 // to an AndINode and commute it with ConvI2LNode because
604 // 0xFFFFFFFFL masks the whole integer and we get a sign extension,
605 // which is wrong.
606 if (op == Op_ConvI2L && in1->in(1)->Opcode() == Op_LoadI && mask == 0x00000000FFFFFFFFL) {
607 Node* load = in1->in(1);
608 return new (phase->C, 3) LoadUI2LNode(load->in(MemNode::Control),
609 load->in(MemNode::Memory),
610 load->in(MemNode::Address),
611 load->adr_type());
612 }
613
614 // Are we masking a long that was converted from an int with a mask
615 // that fits in 32-bits? Commute them and use an AndINode.
616 if (op == Op_ConvI2L && (mask & 0xFFFFFFFF00000000L) == 0) {
617 Node* andi = new (phase->C, 3) AndINode(in1->in(1), phase->intcon(mask));
618 andi = phase->transform(andi);
619 return new (phase->C, 2) ConvI2LNode(andi);
620 }
621
622 // Masking off sign bits? Dont make them!
623 if (op == Op_RShiftL) {
624 const TypeInt* t12 = phase->type(in1->in(2))->isa_int();
625 if( t12 && t12->is_con() ) { // Shift is by a constant
626 int shift = t12->get_con();
627 shift &= BitsPerJavaLong - 1; // semantics of Java shifts
628 const jlong sign_bits_mask = ~(((jlong)CONST64(1) << (jlong)(BitsPerJavaLong - shift)) -1);
629 // If the AND'ing of the 2 masks has no bits, then only original shifted
630 // bits survive. NO sign-extension bits survive the maskings.
631 if( (sign_bits_mask & mask) == 0 ) {
632 // Use zero-fill shift instead
633 Node *zshift = phase->transform(new (phase->C, 3) URShiftLNode(in1->in(1), in1->in(2)));
634 return new (phase->C, 3) AndLNode(zshift, in(2));
635 }
636 }
637 }
638
639 return MulNode::Ideal(phase, can_reshape);
640 }
641
642 //=============================================================================
643 //------------------------------Identity---------------------------------------
644 Node *LShiftINode::Identity( PhaseTransform *phase ) {
645 const TypeInt *ti = phase->type( in(2) )->isa_int(); // shift count is an int
646 return ( ti && ti->is_con() && ( ti->get_con() & ( BitsPerInt - 1 ) ) == 0 ) ? in(1) : this;
647 }
648
649 //------------------------------Ideal------------------------------------------
650 // If the right input is a constant, and the left input is an add of a
651 // constant, flatten the tree: (X+con1)<<con0 ==> X<<con0 + con1<<con0
652 Node *LShiftINode::Ideal(PhaseGVN *phase, bool can_reshape) {
653 const Type *t = phase->type( in(2) );
654 if( t == Type::TOP ) return NULL; // Right input is dead
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