1 //
2 // Copyright 1998-2009 Sun Microsystems, Inc. All Rights Reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
9 // This code is distributed in the hope that it will be useful, but WITHOUT
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
15 // You should have received a copy of the GNU General Public License version
16 // 2 along with this work; if not, write to the Free Software Foundation,
17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 //
19 // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
20 // CA 95054 USA or visit www.sun.com if you need additional information or
21 // have any questions.
22 //
23 //
24
25 // SPARC Architecture Description File
26
27 //----------REGISTER DEFINITION BLOCK------------------------------------------
28 // This information is used by the matcher and the register allocator to
29 // describe individual registers and classes of registers within the target
30 // archtecture.
31 register %{
32 //----------Architecture Description Register Definitions----------------------
33 // General Registers
34 // "reg_def" name ( register save type, C convention save type,
35 // ideal register type, encoding, vm name );
36 // Register Save Types:
37 //
38 // NS = No-Save: The register allocator assumes that these registers
39 // can be used without saving upon entry to the method, &
40 // that they do not need to be saved at call sites.
41 //
42 // SOC = Save-On-Call: The register allocator assumes that these registers
43 // can be used without saving upon entry to the method,
44 // but that they must be saved at call sites.
45 //
46 // SOE = Save-On-Entry: The register allocator assumes that these registers
47 // must be saved before using them upon entry to the
48 // method, but they do not need to be saved at call
49 // sites.
50 //
51 // AS = Always-Save: The register allocator assumes that these registers
52 // must be saved before using them upon entry to the
53 // method, & that they must be saved at call sites.
54 //
55 // Ideal Register Type is used to determine how to save & restore a
56 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
57 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
58 //
59 // The encoding number is the actual bit-pattern placed into the opcodes.
60
61
62 // ----------------------------
63 // Integer/Long Registers
64 // ----------------------------
65
66 // Need to expose the hi/lo aspect of 64-bit registers
67 // This register set is used for both the 64-bit build and
68 // the 32-bit build with 1-register longs.
69
70 // Global Registers 0-7
71 reg_def R_G0H( NS, NS, Op_RegI,128, G0->as_VMReg()->next());
72 reg_def R_G0 ( NS, NS, Op_RegI, 0, G0->as_VMReg());
73 reg_def R_G1H(SOC, SOC, Op_RegI,129, G1->as_VMReg()->next());
74 reg_def R_G1 (SOC, SOC, Op_RegI, 1, G1->as_VMReg());
75 reg_def R_G2H( NS, NS, Op_RegI,130, G2->as_VMReg()->next());
76 reg_def R_G2 ( NS, NS, Op_RegI, 2, G2->as_VMReg());
77 reg_def R_G3H(SOC, SOC, Op_RegI,131, G3->as_VMReg()->next());
78 reg_def R_G3 (SOC, SOC, Op_RegI, 3, G3->as_VMReg());
79 reg_def R_G4H(SOC, SOC, Op_RegI,132, G4->as_VMReg()->next());
80 reg_def R_G4 (SOC, SOC, Op_RegI, 4, G4->as_VMReg());
81 reg_def R_G5H(SOC, SOC, Op_RegI,133, G5->as_VMReg()->next());
82 reg_def R_G5 (SOC, SOC, Op_RegI, 5, G5->as_VMReg());
83 reg_def R_G6H( NS, NS, Op_RegI,134, G6->as_VMReg()->next());
84 reg_def R_G6 ( NS, NS, Op_RegI, 6, G6->as_VMReg());
85 reg_def R_G7H( NS, NS, Op_RegI,135, G7->as_VMReg()->next());
86 reg_def R_G7 ( NS, NS, Op_RegI, 7, G7->as_VMReg());
87
88 // Output Registers 0-7
89 reg_def R_O0H(SOC, SOC, Op_RegI,136, O0->as_VMReg()->next());
90 reg_def R_O0 (SOC, SOC, Op_RegI, 8, O0->as_VMReg());
91 reg_def R_O1H(SOC, SOC, Op_RegI,137, O1->as_VMReg()->next());
92 reg_def R_O1 (SOC, SOC, Op_RegI, 9, O1->as_VMReg());
93 reg_def R_O2H(SOC, SOC, Op_RegI,138, O2->as_VMReg()->next());
94 reg_def R_O2 (SOC, SOC, Op_RegI, 10, O2->as_VMReg());
95 reg_def R_O3H(SOC, SOC, Op_RegI,139, O3->as_VMReg()->next());
96 reg_def R_O3 (SOC, SOC, Op_RegI, 11, O3->as_VMReg());
97 reg_def R_O4H(SOC, SOC, Op_RegI,140, O4->as_VMReg()->next());
98 reg_def R_O4 (SOC, SOC, Op_RegI, 12, O4->as_VMReg());
99 reg_def R_O5H(SOC, SOC, Op_RegI,141, O5->as_VMReg()->next());
100 reg_def R_O5 (SOC, SOC, Op_RegI, 13, O5->as_VMReg());
101 reg_def R_SPH( NS, NS, Op_RegI,142, SP->as_VMReg()->next());
102 reg_def R_SP ( NS, NS, Op_RegI, 14, SP->as_VMReg());
103 reg_def R_O7H(SOC, SOC, Op_RegI,143, O7->as_VMReg()->next());
104 reg_def R_O7 (SOC, SOC, Op_RegI, 15, O7->as_VMReg());
105
106 // Local Registers 0-7
107 reg_def R_L0H( NS, NS, Op_RegI,144, L0->as_VMReg()->next());
108 reg_def R_L0 ( NS, NS, Op_RegI, 16, L0->as_VMReg());
109 reg_def R_L1H( NS, NS, Op_RegI,145, L1->as_VMReg()->next());
110 reg_def R_L1 ( NS, NS, Op_RegI, 17, L1->as_VMReg());
111 reg_def R_L2H( NS, NS, Op_RegI,146, L2->as_VMReg()->next());
112 reg_def R_L2 ( NS, NS, Op_RegI, 18, L2->as_VMReg());
113 reg_def R_L3H( NS, NS, Op_RegI,147, L3->as_VMReg()->next());
114 reg_def R_L3 ( NS, NS, Op_RegI, 19, L3->as_VMReg());
115 reg_def R_L4H( NS, NS, Op_RegI,148, L4->as_VMReg()->next());
116 reg_def R_L4 ( NS, NS, Op_RegI, 20, L4->as_VMReg());
117 reg_def R_L5H( NS, NS, Op_RegI,149, L5->as_VMReg()->next());
118 reg_def R_L5 ( NS, NS, Op_RegI, 21, L5->as_VMReg());
119 reg_def R_L6H( NS, NS, Op_RegI,150, L6->as_VMReg()->next());
120 reg_def R_L6 ( NS, NS, Op_RegI, 22, L6->as_VMReg());
121 reg_def R_L7H( NS, NS, Op_RegI,151, L7->as_VMReg()->next());
122 reg_def R_L7 ( NS, NS, Op_RegI, 23, L7->as_VMReg());
123
124 // Input Registers 0-7
125 reg_def R_I0H( NS, NS, Op_RegI,152, I0->as_VMReg()->next());
126 reg_def R_I0 ( NS, NS, Op_RegI, 24, I0->as_VMReg());
127 reg_def R_I1H( NS, NS, Op_RegI,153, I1->as_VMReg()->next());
128 reg_def R_I1 ( NS, NS, Op_RegI, 25, I1->as_VMReg());
129 reg_def R_I2H( NS, NS, Op_RegI,154, I2->as_VMReg()->next());
130 reg_def R_I2 ( NS, NS, Op_RegI, 26, I2->as_VMReg());
131 reg_def R_I3H( NS, NS, Op_RegI,155, I3->as_VMReg()->next());
132 reg_def R_I3 ( NS, NS, Op_RegI, 27, I3->as_VMReg());
133 reg_def R_I4H( NS, NS, Op_RegI,156, I4->as_VMReg()->next());
134 reg_def R_I4 ( NS, NS, Op_RegI, 28, I4->as_VMReg());
135 reg_def R_I5H( NS, NS, Op_RegI,157, I5->as_VMReg()->next());
136 reg_def R_I5 ( NS, NS, Op_RegI, 29, I5->as_VMReg());
137 reg_def R_FPH( NS, NS, Op_RegI,158, FP->as_VMReg()->next());
138 reg_def R_FP ( NS, NS, Op_RegI, 30, FP->as_VMReg());
139 reg_def R_I7H( NS, NS, Op_RegI,159, I7->as_VMReg()->next());
140 reg_def R_I7 ( NS, NS, Op_RegI, 31, I7->as_VMReg());
141
142 // ----------------------------
143 // Float/Double Registers
144 // ----------------------------
145
146 // Float Registers
147 reg_def R_F0 ( SOC, SOC, Op_RegF, 0, F0->as_VMReg());
148 reg_def R_F1 ( SOC, SOC, Op_RegF, 1, F1->as_VMReg());
149 reg_def R_F2 ( SOC, SOC, Op_RegF, 2, F2->as_VMReg());
150 reg_def R_F3 ( SOC, SOC, Op_RegF, 3, F3->as_VMReg());
151 reg_def R_F4 ( SOC, SOC, Op_RegF, 4, F4->as_VMReg());
152 reg_def R_F5 ( SOC, SOC, Op_RegF, 5, F5->as_VMReg());
153 reg_def R_F6 ( SOC, SOC, Op_RegF, 6, F6->as_VMReg());
154 reg_def R_F7 ( SOC, SOC, Op_RegF, 7, F7->as_VMReg());
155 reg_def R_F8 ( SOC, SOC, Op_RegF, 8, F8->as_VMReg());
156 reg_def R_F9 ( SOC, SOC, Op_RegF, 9, F9->as_VMReg());
157 reg_def R_F10( SOC, SOC, Op_RegF, 10, F10->as_VMReg());
158 reg_def R_F11( SOC, SOC, Op_RegF, 11, F11->as_VMReg());
159 reg_def R_F12( SOC, SOC, Op_RegF, 12, F12->as_VMReg());
160 reg_def R_F13( SOC, SOC, Op_RegF, 13, F13->as_VMReg());
161 reg_def R_F14( SOC, SOC, Op_RegF, 14, F14->as_VMReg());
162 reg_def R_F15( SOC, SOC, Op_RegF, 15, F15->as_VMReg());
163 reg_def R_F16( SOC, SOC, Op_RegF, 16, F16->as_VMReg());
164 reg_def R_F17( SOC, SOC, Op_RegF, 17, F17->as_VMReg());
165 reg_def R_F18( SOC, SOC, Op_RegF, 18, F18->as_VMReg());
166 reg_def R_F19( SOC, SOC, Op_RegF, 19, F19->as_VMReg());
167 reg_def R_F20( SOC, SOC, Op_RegF, 20, F20->as_VMReg());
168 reg_def R_F21( SOC, SOC, Op_RegF, 21, F21->as_VMReg());
169 reg_def R_F22( SOC, SOC, Op_RegF, 22, F22->as_VMReg());
170 reg_def R_F23( SOC, SOC, Op_RegF, 23, F23->as_VMReg());
171 reg_def R_F24( SOC, SOC, Op_RegF, 24, F24->as_VMReg());
172 reg_def R_F25( SOC, SOC, Op_RegF, 25, F25->as_VMReg());
173 reg_def R_F26( SOC, SOC, Op_RegF, 26, F26->as_VMReg());
174 reg_def R_F27( SOC, SOC, Op_RegF, 27, F27->as_VMReg());
175 reg_def R_F28( SOC, SOC, Op_RegF, 28, F28->as_VMReg());
176 reg_def R_F29( SOC, SOC, Op_RegF, 29, F29->as_VMReg());
177 reg_def R_F30( SOC, SOC, Op_RegF, 30, F30->as_VMReg());
178 reg_def R_F31( SOC, SOC, Op_RegF, 31, F31->as_VMReg());
179
180 // Double Registers
181 // The rules of ADL require that double registers be defined in pairs.
182 // Each pair must be two 32-bit values, but not necessarily a pair of
183 // single float registers. In each pair, ADLC-assigned register numbers
184 // must be adjacent, with the lower number even. Finally, when the
185 // CPU stores such a register pair to memory, the word associated with
186 // the lower ADLC-assigned number must be stored to the lower address.
187
188 // These definitions specify the actual bit encodings of the sparc
189 // double fp register numbers. FloatRegisterImpl in register_sparc.hpp
190 // wants 0-63, so we have to convert every time we want to use fp regs
191 // with the macroassembler, using reg_to_DoubleFloatRegister_object().
192 // 255 is a flag meaning "don't go here".
193 // I believe we can't handle callee-save doubles D32 and up until
194 // the place in the sparc stack crawler that asserts on the 255 is
195 // fixed up.
196 reg_def R_D32x(SOC, SOC, Op_RegD,255, F32->as_VMReg());
197 reg_def R_D32 (SOC, SOC, Op_RegD, 1, F32->as_VMReg()->next());
198 reg_def R_D34x(SOC, SOC, Op_RegD,255, F34->as_VMReg());
199 reg_def R_D34 (SOC, SOC, Op_RegD, 3, F34->as_VMReg()->next());
200 reg_def R_D36x(SOC, SOC, Op_RegD,255, F36->as_VMReg());
201 reg_def R_D36 (SOC, SOC, Op_RegD, 5, F36->as_VMReg()->next());
202 reg_def R_D38x(SOC, SOC, Op_RegD,255, F38->as_VMReg());
203 reg_def R_D38 (SOC, SOC, Op_RegD, 7, F38->as_VMReg()->next());
204 reg_def R_D40x(SOC, SOC, Op_RegD,255, F40->as_VMReg());
205 reg_def R_D40 (SOC, SOC, Op_RegD, 9, F40->as_VMReg()->next());
206 reg_def R_D42x(SOC, SOC, Op_RegD,255, F42->as_VMReg());
207 reg_def R_D42 (SOC, SOC, Op_RegD, 11, F42->as_VMReg()->next());
208 reg_def R_D44x(SOC, SOC, Op_RegD,255, F44->as_VMReg());
209 reg_def R_D44 (SOC, SOC, Op_RegD, 13, F44->as_VMReg()->next());
210 reg_def R_D46x(SOC, SOC, Op_RegD,255, F46->as_VMReg());
211 reg_def R_D46 (SOC, SOC, Op_RegD, 15, F46->as_VMReg()->next());
212 reg_def R_D48x(SOC, SOC, Op_RegD,255, F48->as_VMReg());
213 reg_def R_D48 (SOC, SOC, Op_RegD, 17, F48->as_VMReg()->next());
214 reg_def R_D50x(SOC, SOC, Op_RegD,255, F50->as_VMReg());
215 reg_def R_D50 (SOC, SOC, Op_RegD, 19, F50->as_VMReg()->next());
216 reg_def R_D52x(SOC, SOC, Op_RegD,255, F52->as_VMReg());
217 reg_def R_D52 (SOC, SOC, Op_RegD, 21, F52->as_VMReg()->next());
218 reg_def R_D54x(SOC, SOC, Op_RegD,255, F54->as_VMReg());
219 reg_def R_D54 (SOC, SOC, Op_RegD, 23, F54->as_VMReg()->next());
220 reg_def R_D56x(SOC, SOC, Op_RegD,255, F56->as_VMReg());
221 reg_def R_D56 (SOC, SOC, Op_RegD, 25, F56->as_VMReg()->next());
222 reg_def R_D58x(SOC, SOC, Op_RegD,255, F58->as_VMReg());
223 reg_def R_D58 (SOC, SOC, Op_RegD, 27, F58->as_VMReg()->next());
224 reg_def R_D60x(SOC, SOC, Op_RegD,255, F60->as_VMReg());
225 reg_def R_D60 (SOC, SOC, Op_RegD, 29, F60->as_VMReg()->next());
226 reg_def R_D62x(SOC, SOC, Op_RegD,255, F62->as_VMReg());
227 reg_def R_D62 (SOC, SOC, Op_RegD, 31, F62->as_VMReg()->next());
228
229
230 // ----------------------------
231 // Special Registers
232 // Condition Codes Flag Registers
233 // I tried to break out ICC and XCC but it's not very pretty.
234 // Every Sparc instruction which defs/kills one also kills the other.
235 // Hence every compare instruction which defs one kind of flags ends
236 // up needing a kill of the other.
237 reg_def CCR (SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad());
238
239 reg_def FCC0(SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad());
240 reg_def FCC1(SOC, SOC, Op_RegFlags, 1, VMRegImpl::Bad());
241 reg_def FCC2(SOC, SOC, Op_RegFlags, 2, VMRegImpl::Bad());
242 reg_def FCC3(SOC, SOC, Op_RegFlags, 3, VMRegImpl::Bad());
243
244 // ----------------------------
245 // Specify the enum values for the registers. These enums are only used by the
246 // OptoReg "class". We can convert these enum values at will to VMReg when needed
247 // for visibility to the rest of the vm. The order of this enum influences the
248 // register allocator so having the freedom to set this order and not be stuck
249 // with the order that is natural for the rest of the vm is worth it.
250 alloc_class chunk0(
251 R_L0,R_L0H, R_L1,R_L1H, R_L2,R_L2H, R_L3,R_L3H, R_L4,R_L4H, R_L5,R_L5H, R_L6,R_L6H, R_L7,R_L7H,
252 R_G0,R_G0H, R_G1,R_G1H, R_G2,R_G2H, R_G3,R_G3H, R_G4,R_G4H, R_G5,R_G5H, R_G6,R_G6H, R_G7,R_G7H,
253 R_O7,R_O7H, R_SP,R_SPH, R_O0,R_O0H, R_O1,R_O1H, R_O2,R_O2H, R_O3,R_O3H, R_O4,R_O4H, R_O5,R_O5H,
254 R_I0,R_I0H, R_I1,R_I1H, R_I2,R_I2H, R_I3,R_I3H, R_I4,R_I4H, R_I5,R_I5H, R_FP,R_FPH, R_I7,R_I7H);
255
256 // Note that a register is not allocatable unless it is also mentioned
257 // in a widely-used reg_class below. Thus, R_G7 and R_G0 are outside i_reg.
258
259 alloc_class chunk1(
260 // The first registers listed here are those most likely to be used
261 // as temporaries. We move F0..F7 away from the front of the list,
262 // to reduce the likelihood of interferences with parameters and
263 // return values. Likewise, we avoid using F0/F1 for parameters,
264 // since they are used for return values.
265 // This FPU fine-tuning is worth about 1% on the SPEC geomean.
266 R_F8 ,R_F9 ,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
267 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,
268 R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,R_F30,R_F31,
269 R_F0 ,R_F1 ,R_F2 ,R_F3 ,R_F4 ,R_F5 ,R_F6 ,R_F7 , // used for arguments and return values
270 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,
271 R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x,
272 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,
273 R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x);
274
275 alloc_class chunk2(CCR, FCC0, FCC1, FCC2, FCC3);
276
277 //----------Architecture Description Register Classes--------------------------
278 // Several register classes are automatically defined based upon information in
279 // this architecture description.
280 // 1) reg_class inline_cache_reg ( as defined in frame section )
281 // 2) reg_class interpreter_method_oop_reg ( as defined in frame section )
282 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
283 //
284
285 // G0 is not included in integer class since it has special meaning.
286 reg_class g0_reg(R_G0);
287
288 // ----------------------------
289 // Integer Register Classes
290 // ----------------------------
291 // Exclusions from i_reg:
292 // R_G0: hardwired zero
293 // R_G2: reserved by HotSpot to the TLS register (invariant within Java)
294 // R_G6: reserved by Solaris ABI to tools
295 // R_G7: reserved by Solaris ABI to libthread
296 // R_O7: Used as a temp in many encodings
297 reg_class int_reg(R_G1,R_G3,R_G4,R_G5,R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
298
299 // Class for all integer registers, except the G registers. This is used for
300 // encodings which use G registers as temps. The regular inputs to such
301 // instructions use a "notemp_" prefix, as a hack to ensure that the allocator
302 // will not put an input into a temp register.
303 reg_class notemp_int_reg(R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
304
305 reg_class g1_regI(R_G1);
306 reg_class g3_regI(R_G3);
307 reg_class g4_regI(R_G4);
308 reg_class o0_regI(R_O0);
309 reg_class o7_regI(R_O7);
310
311 // ----------------------------
312 // Pointer Register Classes
313 // ----------------------------
314 #ifdef _LP64
315 // 64-bit build means 64-bit pointers means hi/lo pairs
316 reg_class ptr_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5,
317 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5,
318 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
319 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 );
320 // Lock encodings use G3 and G4 internally
321 reg_class lock_ptr_reg( R_G1H,R_G1, R_G5H,R_G5,
322 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5,
323 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
324 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 );
325 // Special class for storeP instructions, which can store SP or RPC to TLS.
326 // It is also used for memory addressing, allowing direct TLS addressing.
327 reg_class sp_ptr_reg( R_G1H,R_G1, R_G2H,R_G2, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5,
328 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, R_SPH,R_SP,
329 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
330 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5, R_FPH,R_FP );
331 // R_L7 is the lowest-priority callee-save (i.e., NS) register
332 // We use it to save R_G2 across calls out of Java.
333 reg_class l7_regP(R_L7H,R_L7);
334
335 // Other special pointer regs
336 reg_class g1_regP(R_G1H,R_G1);
337 reg_class g2_regP(R_G2H,R_G2);
338 reg_class g3_regP(R_G3H,R_G3);
339 reg_class g4_regP(R_G4H,R_G4);
340 reg_class g5_regP(R_G5H,R_G5);
341 reg_class i0_regP(R_I0H,R_I0);
342 reg_class o0_regP(R_O0H,R_O0);
343 reg_class o1_regP(R_O1H,R_O1);
344 reg_class o2_regP(R_O2H,R_O2);
345 reg_class o7_regP(R_O7H,R_O7);
346
347 #else // _LP64
348 // 32-bit build means 32-bit pointers means 1 register.
349 reg_class ptr_reg( R_G1, R_G3,R_G4,R_G5,
350 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,
351 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
352 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
353 // Lock encodings use G3 and G4 internally
354 reg_class lock_ptr_reg(R_G1, R_G5,
355 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,
356 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
357 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
358 // Special class for storeP instructions, which can store SP or RPC to TLS.
359 // It is also used for memory addressing, allowing direct TLS addressing.
360 reg_class sp_ptr_reg( R_G1,R_G2,R_G3,R_G4,R_G5,
361 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_SP,
362 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
363 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5,R_FP);
364 // R_L7 is the lowest-priority callee-save (i.e., NS) register
365 // We use it to save R_G2 across calls out of Java.
366 reg_class l7_regP(R_L7);
367
368 // Other special pointer regs
369 reg_class g1_regP(R_G1);
370 reg_class g2_regP(R_G2);
371 reg_class g3_regP(R_G3);
372 reg_class g4_regP(R_G4);
373 reg_class g5_regP(R_G5);
374 reg_class i0_regP(R_I0);
375 reg_class o0_regP(R_O0);
376 reg_class o1_regP(R_O1);
377 reg_class o2_regP(R_O2);
378 reg_class o7_regP(R_O7);
379 #endif // _LP64
380
381
382 // ----------------------------
383 // Long Register Classes
384 // ----------------------------
385 // Longs in 1 register. Aligned adjacent hi/lo pairs.
386 // Note: O7 is never in this class; it is sometimes used as an encoding temp.
387 reg_class long_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5
388 ,R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5
389 #ifdef _LP64
390 // 64-bit, longs in 1 register: use all 64-bit integer registers
391 // 32-bit, longs in 1 register: cannot use I's and L's. Restrict to O's and G's.
392 ,R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7
393 ,R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5
394 #endif // _LP64
395 );
396
397 reg_class g1_regL(R_G1H,R_G1);
398 reg_class g3_regL(R_G3H,R_G3);
399 reg_class o2_regL(R_O2H,R_O2);
400 reg_class o7_regL(R_O7H,R_O7);
401
402 // ----------------------------
403 // Special Class for Condition Code Flags Register
404 reg_class int_flags(CCR);
405 reg_class float_flags(FCC0,FCC1,FCC2,FCC3);
406 reg_class float_flag0(FCC0);
407
408
409 // ----------------------------
410 // Float Point Register Classes
411 // ----------------------------
412 // Skip F30/F31, they are reserved for mem-mem copies
413 reg_class sflt_reg(R_F0,R_F1,R_F2,R_F3,R_F4,R_F5,R_F6,R_F7,R_F8,R_F9,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29);
414
415 // Paired floating point registers--they show up in the same order as the floats,
416 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs.
417 reg_class dflt_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
418 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,
419 /* Use extra V9 double registers; this AD file does not support V8 */
420 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x,
421 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x
422 );
423
424 // Paired floating point registers--they show up in the same order as the floats,
425 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs.
426 // This class is usable for mis-aligned loads as happen in I2C adapters.
427 reg_class dflt_low_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
428 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,R_F30,R_F31 );
429 %}
430
431 //----------DEFINITION BLOCK---------------------------------------------------
432 // Define name --> value mappings to inform the ADLC of an integer valued name
433 // Current support includes integer values in the range [0, 0x7FFFFFFF]
434 // Format:
435 // int_def <name> ( <int_value>, <expression>);
436 // Generated Code in ad_<arch>.hpp
437 // #define <name> (<expression>)
438 // // value == <int_value>
439 // Generated code in ad_<arch>.cpp adlc_verification()
440 // assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>");
441 //
442 definitions %{
443 // The default cost (of an ALU instruction).
444 int_def DEFAULT_COST ( 100, 100);
445 int_def HUGE_COST (1000000, 1000000);
446
447 // Memory refs are twice as expensive as run-of-the-mill.
448 int_def MEMORY_REF_COST ( 200, DEFAULT_COST * 2);
449
450 // Branches are even more expensive.
451 int_def BRANCH_COST ( 300, DEFAULT_COST * 3);
452 int_def CALL_COST ( 300, DEFAULT_COST * 3);
453 %}
454
455
456 //----------SOURCE BLOCK-------------------------------------------------------
457 // This is a block of C++ code which provides values, functions, and
458 // definitions necessary in the rest of the architecture description
459 source_hpp %{
460 // Must be visible to the DFA in dfa_sparc.cpp
461 extern bool can_branch_register( Node *bol, Node *cmp );
462
463 // Macros to extract hi & lo halves from a long pair.
464 // G0 is not part of any long pair, so assert on that.
465 // Prevents accidentally using G1 instead of G0.
466 #define LONG_HI_REG(x) (x)
467 #define LONG_LO_REG(x) (x)
468
469 %}
470
471 source %{
472 #define __ _masm.
473
474 // tertiary op of a LoadP or StoreP encoding
475 #define REGP_OP true
476
477 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding);
478 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding);
479 static Register reg_to_register_object(int register_encoding);
480
481 // Used by the DFA in dfa_sparc.cpp.
482 // Check for being able to use a V9 branch-on-register. Requires a
483 // compare-vs-zero, equal/not-equal, of a value which was zero- or sign-
484 // extended. Doesn't work following an integer ADD, for example, because of
485 // overflow (-1 incremented yields 0 plus a carry in the high-order word). On
486 // 32-bit V9 systems, interrupts currently blow away the high-order 32 bits and
487 // replace them with zero, which could become sign-extension in a different OS
488 // release. There's no obvious reason why an interrupt will ever fill these
489 // bits with non-zero junk (the registers are reloaded with standard LD
490 // instructions which either zero-fill or sign-fill).
491 bool can_branch_register( Node *bol, Node *cmp ) {
492 if( !BranchOnRegister ) return false;
493 #ifdef _LP64
494 if( cmp->Opcode() == Op_CmpP )
495 return true; // No problems with pointer compares
496 #endif
497 if( cmp->Opcode() == Op_CmpL )
498 return true; // No problems with long compares
499
500 if( !SparcV9RegsHiBitsZero ) return false;
501 if( bol->as_Bool()->_test._test != BoolTest::ne &&
502 bol->as_Bool()->_test._test != BoolTest::eq )
503 return false;
504
505 // Check for comparing against a 'safe' value. Any operation which
506 // clears out the high word is safe. Thus, loads and certain shifts
507 // are safe, as are non-negative constants. Any operation which
508 // preserves zero bits in the high word is safe as long as each of its
509 // inputs are safe. Thus, phis and bitwise booleans are safe if their
510 // inputs are safe. At present, the only important case to recognize
511 // seems to be loads. Constants should fold away, and shifts &
512 // logicals can use the 'cc' forms.
513 Node *x = cmp->in(1);
514 if( x->is_Load() ) return true;
515 if( x->is_Phi() ) {
516 for( uint i = 1; i < x->req(); i++ )
517 if( !x->in(i)->is_Load() )
518 return false;
519 return true;
520 }
521 return false;
522 }
523
524 // ****************************************************************************
525
526 // REQUIRED FUNCTIONALITY
527
528 // !!!!! Special hack to get all type of calls to specify the byte offset
529 // from the start of the call to the point where the return address
530 // will point.
531 // The "return address" is the address of the call instruction, plus 8.
532
533 int MachCallStaticJavaNode::ret_addr_offset() {
534 return NativeCall::instruction_size; // call; delay slot
535 }
536
537 int MachCallDynamicJavaNode::ret_addr_offset() {
538 int vtable_index = this->_vtable_index;
539 if (vtable_index < 0) {
540 // must be invalid_vtable_index, not nonvirtual_vtable_index
541 assert(vtable_index == methodOopDesc::invalid_vtable_index, "correct sentinel value");
542 return (NativeMovConstReg::instruction_size +
543 NativeCall::instruction_size); // sethi; setlo; call; delay slot
544 } else {
545 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
546 int entry_offset = instanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size();
547 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes();
548 int klass_load_size;
549 if (UseCompressedOops) {
550 assert(Universe::heap() != NULL, "java heap should be initialized");
551 if (Universe::narrow_oop_base() == NULL)
552 klass_load_size = 2*BytesPerInstWord; // see MacroAssembler::load_klass()
553 else
554 klass_load_size = 3*BytesPerInstWord;
555 } else {
556 klass_load_size = 1*BytesPerInstWord;
557 }
558 if( Assembler::is_simm13(v_off) ) {
559 return klass_load_size +
560 (2*BytesPerInstWord + // ld_ptr, ld_ptr
561 NativeCall::instruction_size); // call; delay slot
562 } else {
563 return klass_load_size +
564 (4*BytesPerInstWord + // set_hi, set, ld_ptr, ld_ptr
565 NativeCall::instruction_size); // call; delay slot
566 }
567 }
568 }
569
570 int MachCallRuntimeNode::ret_addr_offset() {
571 #ifdef _LP64
572 return NativeFarCall::instruction_size; // farcall; delay slot
573 #else
574 return NativeCall::instruction_size; // call; delay slot
575 #endif
576 }
577
578 // Indicate if the safepoint node needs the polling page as an input.
579 // Since Sparc does not have absolute addressing, it does.
580 bool SafePointNode::needs_polling_address_input() {
581 return true;
582 }
583
584 // emit an interrupt that is caught by the debugger (for debugging compiler)
585 void emit_break(CodeBuffer &cbuf) {
586 MacroAssembler _masm(&cbuf);
587 __ breakpoint_trap();
588 }
589
590 #ifndef PRODUCT
591 void MachBreakpointNode::format( PhaseRegAlloc *, outputStream *st ) const {
592 st->print("TA");
593 }
594 #endif
595
596 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
597 emit_break(cbuf);
598 }
599
600 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {
601 return MachNode::size(ra_);
602 }
603
604 // Traceable jump
605 void emit_jmpl(CodeBuffer &cbuf, int jump_target) {
606 MacroAssembler _masm(&cbuf);
607 Register rdest = reg_to_register_object(jump_target);
608 __ JMP(rdest, 0);
609 __ delayed()->nop();
610 }
611
612 // Traceable jump and set exception pc
613 void emit_jmpl_set_exception_pc(CodeBuffer &cbuf, int jump_target) {
614 MacroAssembler _masm(&cbuf);
615 Register rdest = reg_to_register_object(jump_target);
616 __ JMP(rdest, 0);
617 __ delayed()->add(O7, frame::pc_return_offset, Oissuing_pc );
618 }
619
620 void emit_nop(CodeBuffer &cbuf) {
621 MacroAssembler _masm(&cbuf);
622 __ nop();
623 }
624
625 void emit_illtrap(CodeBuffer &cbuf) {
626 MacroAssembler _masm(&cbuf);
627 __ illtrap(0);
628 }
629
630
631 intptr_t get_offset_from_base(const MachNode* n, const TypePtr* atype, int disp32) {
632 assert(n->rule() != loadUB_rule, "");
633
634 intptr_t offset = 0;
635 const TypePtr *adr_type = TYPE_PTR_SENTINAL; // Check for base==RegI, disp==immP
636 const Node* addr = n->get_base_and_disp(offset, adr_type);
637 assert(adr_type == (const TypePtr*)-1, "VerifyOops: no support for sparc operands with base==RegI, disp==immP");
638 assert(addr != NULL && addr != (Node*)-1, "invalid addr");
639 assert(addr->bottom_type()->isa_oopptr() == atype, "");
640 atype = atype->add_offset(offset);
641 assert(disp32 == offset, "wrong disp32");
642 return atype->_offset;
643 }
644
645
646 intptr_t get_offset_from_base_2(const MachNode* n, const TypePtr* atype, int disp32) {
647 assert(n->rule() != loadUB_rule, "");
648
649 intptr_t offset = 0;
650 Node* addr = n->in(2);
651 assert(addr->bottom_type()->isa_oopptr() == atype, "");
652 if (addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP) {
653 Node* a = addr->in(2/*AddPNode::Address*/);
654 Node* o = addr->in(3/*AddPNode::Offset*/);
655 offset = o->is_Con() ? o->bottom_type()->is_intptr_t()->get_con() : Type::OffsetBot;
656 atype = a->bottom_type()->is_ptr()->add_offset(offset);
657 assert(atype->isa_oop_ptr(), "still an oop");
658 }
659 offset = atype->is_ptr()->_offset;
660 if (offset != Type::OffsetBot) offset += disp32;
661 return offset;
662 }
663
664 // Standard Sparc opcode form2 field breakdown
665 static inline void emit2_19(CodeBuffer &cbuf, int f30, int f29, int f25, int f22, int f20, int f19, int f0 ) {
666 f0 &= (1<<19)-1; // Mask displacement to 19 bits
667 int op = (f30 << 30) |
668 (f29 << 29) |
669 (f25 << 25) |
670 (f22 << 22) |
671 (f20 << 20) |
672 (f19 << 19) |
673 (f0 << 0);
674 *((int*)(cbuf.code_end())) = op;
675 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
676 }
677
678 // Standard Sparc opcode form2 field breakdown
679 static inline void emit2_22(CodeBuffer &cbuf, int f30, int f25, int f22, int f0 ) {
680 f0 >>= 10; // Drop 10 bits
681 f0 &= (1<<22)-1; // Mask displacement to 22 bits
682 int op = (f30 << 30) |
683 (f25 << 25) |
684 (f22 << 22) |
685 (f0 << 0);
686 *((int*)(cbuf.code_end())) = op;
687 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
688 }
689
690 // Standard Sparc opcode form3 field breakdown
691 static inline void emit3(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int f5, int f0 ) {
692 int op = (f30 << 30) |
693 (f25 << 25) |
694 (f19 << 19) |
695 (f14 << 14) |
696 (f5 << 5) |
697 (f0 << 0);
698 *((int*)(cbuf.code_end())) = op;
699 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
700 }
701
702 // Standard Sparc opcode form3 field breakdown
703 static inline void emit3_simm13(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm13 ) {
704 simm13 &= (1<<13)-1; // Mask to 13 bits
705 int op = (f30 << 30) |
706 (f25 << 25) |
707 (f19 << 19) |
708 (f14 << 14) |
709 (1 << 13) | // bit to indicate immediate-mode
710 (simm13<<0);
711 *((int*)(cbuf.code_end())) = op;
712 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
713 }
714
715 static inline void emit3_simm10(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm10 ) {
716 simm10 &= (1<<10)-1; // Mask to 10 bits
717 emit3_simm13(cbuf,f30,f25,f19,f14,simm10);
718 }
719
720 #ifdef ASSERT
721 // Helper function for VerifyOops in emit_form3_mem_reg
722 void verify_oops_warning(const MachNode *n, int ideal_op, int mem_op) {
723 warning("VerifyOops encountered unexpected instruction:");
724 n->dump(2);
725 warning("Instruction has ideal_Opcode==Op_%s and op_ld==Op_%s \n", NodeClassNames[ideal_op], NodeClassNames[mem_op]);
726 }
727 #endif
728
729
730 void emit_form3_mem_reg(CodeBuffer &cbuf, const MachNode* n, int primary, int tertiary,
731 int src1_enc, int disp32, int src2_enc, int dst_enc) {
732
733 #ifdef ASSERT
734 // The following code implements the +VerifyOops feature.
735 // It verifies oop values which are loaded into or stored out of
736 // the current method activation. +VerifyOops complements techniques
737 // like ScavengeALot, because it eagerly inspects oops in transit,
738 // as they enter or leave the stack, as opposed to ScavengeALot,
739 // which inspects oops "at rest", in the stack or heap, at safepoints.
740 // For this reason, +VerifyOops can sometimes detect bugs very close
741 // to their point of creation. It can also serve as a cross-check
742 // on the validity of oop maps, when used toegether with ScavengeALot.
743
744 // It would be good to verify oops at other points, especially
745 // when an oop is used as a base pointer for a load or store.
746 // This is presently difficult, because it is hard to know when
747 // a base address is biased or not. (If we had such information,
748 // it would be easy and useful to make a two-argument version of
749 // verify_oop which unbiases the base, and performs verification.)
750
751 assert((uint)tertiary == 0xFFFFFFFF || tertiary == REGP_OP, "valid tertiary");
752 bool is_verified_oop_base = false;
753 bool is_verified_oop_load = false;
754 bool is_verified_oop_store = false;
755 int tmp_enc = -1;
756 if (VerifyOops && src1_enc != R_SP_enc) {
757 // classify the op, mainly for an assert check
758 int st_op = 0, ld_op = 0;
759 switch (primary) {
760 case Assembler::stb_op3: st_op = Op_StoreB; break;
761 case Assembler::sth_op3: st_op = Op_StoreC; break;
762 case Assembler::stx_op3: // may become StoreP or stay StoreI or StoreD0
763 case Assembler::stw_op3: st_op = Op_StoreI; break;
764 case Assembler::std_op3: st_op = Op_StoreL; break;
765 case Assembler::stf_op3: st_op = Op_StoreF; break;
766 case Assembler::stdf_op3: st_op = Op_StoreD; break;
767
768 case Assembler::ldsb_op3: ld_op = Op_LoadB; break;
769 case Assembler::lduh_op3: ld_op = Op_LoadUS; break;
770 case Assembler::ldsh_op3: ld_op = Op_LoadS; break;
771 case Assembler::ldx_op3: // may become LoadP or stay LoadI
772 case Assembler::ldsw_op3: // may become LoadP or stay LoadI
773 case Assembler::lduw_op3: ld_op = Op_LoadI; break;
774 case Assembler::ldd_op3: ld_op = Op_LoadL; break;
775 case Assembler::ldf_op3: ld_op = Op_LoadF; break;
776 case Assembler::lddf_op3: ld_op = Op_LoadD; break;
777 case Assembler::ldub_op3: ld_op = Op_LoadB; break;
778 case Assembler::prefetch_op3: ld_op = Op_LoadI; break;
779
780 default: ShouldNotReachHere();
781 }
782 if (tertiary == REGP_OP) {
783 if (st_op == Op_StoreI) st_op = Op_StoreP;
784 else if (ld_op == Op_LoadI) ld_op = Op_LoadP;
785 else ShouldNotReachHere();
786 if (st_op) {
787 // a store
788 // inputs are (0:control, 1:memory, 2:address, 3:value)
789 Node* n2 = n->in(3);
790 if (n2 != NULL) {
791 const Type* t = n2->bottom_type();
792 is_verified_oop_store = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false;
793 }
794 } else {
795 // a load
796 const Type* t = n->bottom_type();
797 is_verified_oop_load = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false;
798 }
799 }
800
801 if (ld_op) {
802 // a Load
803 // inputs are (0:control, 1:memory, 2:address)
804 if (!(n->ideal_Opcode()==ld_op) && // Following are special cases
805 !(n->ideal_Opcode()==Op_LoadLLocked && ld_op==Op_LoadI) &&
806 !(n->ideal_Opcode()==Op_LoadPLocked && ld_op==Op_LoadP) &&
807 !(n->ideal_Opcode()==Op_LoadI && ld_op==Op_LoadF) &&
808 !(n->ideal_Opcode()==Op_LoadF && ld_op==Op_LoadI) &&
809 !(n->ideal_Opcode()==Op_LoadRange && ld_op==Op_LoadI) &&
810 !(n->ideal_Opcode()==Op_LoadKlass && ld_op==Op_LoadP) &&
811 !(n->ideal_Opcode()==Op_LoadL && ld_op==Op_LoadI) &&
812 !(n->ideal_Opcode()==Op_LoadL_unaligned && ld_op==Op_LoadI) &&
813 !(n->ideal_Opcode()==Op_LoadD_unaligned && ld_op==Op_LoadF) &&
814 !(n->ideal_Opcode()==Op_ConvI2F && ld_op==Op_LoadF) &&
815 !(n->ideal_Opcode()==Op_ConvI2D && ld_op==Op_LoadF) &&
816 !(n->ideal_Opcode()==Op_PrefetchRead && ld_op==Op_LoadI) &&
817 !(n->ideal_Opcode()==Op_PrefetchWrite && ld_op==Op_LoadI) &&
818 !(n->rule() == loadUB_rule)) {
819 verify_oops_warning(n, n->ideal_Opcode(), ld_op);
820 }
821 } else if (st_op) {
822 // a Store
823 // inputs are (0:control, 1:memory, 2:address, 3:value)
824 if (!(n->ideal_Opcode()==st_op) && // Following are special cases
825 !(n->ideal_Opcode()==Op_StoreCM && st_op==Op_StoreB) &&
826 !(n->ideal_Opcode()==Op_StoreI && st_op==Op_StoreF) &&
827 !(n->ideal_Opcode()==Op_StoreF && st_op==Op_StoreI) &&
828 !(n->ideal_Opcode()==Op_StoreL && st_op==Op_StoreI) &&
829 !(n->ideal_Opcode()==Op_StoreD && st_op==Op_StoreI && n->rule() == storeD0_rule)) {
830 verify_oops_warning(n, n->ideal_Opcode(), st_op);
831 }
832 }
833
834 if (src2_enc == R_G0_enc && n->rule() != loadUB_rule && n->ideal_Opcode() != Op_StoreCM ) {
835 Node* addr = n->in(2);
836 if (!(addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP)) {
837 const TypeOopPtr* atype = addr->bottom_type()->isa_instptr(); // %%% oopptr?
838 if (atype != NULL) {
839 intptr_t offset = get_offset_from_base(n, atype, disp32);
840 intptr_t offset_2 = get_offset_from_base_2(n, atype, disp32);
841 if (offset != offset_2) {
842 get_offset_from_base(n, atype, disp32);
843 get_offset_from_base_2(n, atype, disp32);
844 }
845 assert(offset == offset_2, "different offsets");
846 if (offset == disp32) {
847 // we now know that src1 is a true oop pointer
848 is_verified_oop_base = true;
849 if (ld_op && src1_enc == dst_enc && ld_op != Op_LoadF && ld_op != Op_LoadD) {
850 if( primary == Assembler::ldd_op3 ) {
851 is_verified_oop_base = false; // Cannot 'ldd' into O7
852 } else {
853 tmp_enc = dst_enc;
854 dst_enc = R_O7_enc; // Load into O7; preserve source oop
855 assert(src1_enc != dst_enc, "");
856 }
857 }
858 }
859 if (st_op && (( offset == oopDesc::klass_offset_in_bytes())
860 || offset == oopDesc::mark_offset_in_bytes())) {
861 // loading the mark should not be allowed either, but
862 // we don't check this since it conflicts with InlineObjectHash
863 // usage of LoadINode to get the mark. We could keep the
864 // check if we create a new LoadMarkNode
865 // but do not verify the object before its header is initialized
866 ShouldNotReachHere();
867 }
868 }
869 }
870 }
871 }
872 #endif
873
874 uint instr;
875 instr = (Assembler::ldst_op << 30)
876 | (dst_enc << 25)
877 | (primary << 19)
878 | (src1_enc << 14);
879
880 uint index = src2_enc;
881 int disp = disp32;
882
883 if (src1_enc == R_SP_enc || src1_enc == R_FP_enc)
884 disp += STACK_BIAS;
885
886 // We should have a compiler bailout here rather than a guarantee.
887 // Better yet would be some mechanism to handle variable-size matches correctly.
888 guarantee(Assembler::is_simm13(disp), "Do not match large constant offsets" );
889
890 if( disp == 0 ) {
891 // use reg-reg form
892 // bit 13 is already zero
893 instr |= index;
894 } else {
895 // use reg-imm form
896 instr |= 0x00002000; // set bit 13 to one
897 instr |= disp & 0x1FFF;
898 }
899
900 uint *code = (uint*)cbuf.code_end();
901 *code = instr;
902 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
903
904 #ifdef ASSERT
905 {
906 MacroAssembler _masm(&cbuf);
907 if (is_verified_oop_base) {
908 __ verify_oop(reg_to_register_object(src1_enc));
909 }
910 if (is_verified_oop_store) {
911 __ verify_oop(reg_to_register_object(dst_enc));
912 }
913 if (tmp_enc != -1) {
914 __ mov(O7, reg_to_register_object(tmp_enc));
915 }
916 if (is_verified_oop_load) {
917 __ verify_oop(reg_to_register_object(dst_enc));
918 }
919 }
920 #endif
921 }
922
923 void emit_form3_mem_reg_asi(CodeBuffer &cbuf, const MachNode* n, int primary, int tertiary,
924 int src1_enc, int disp32, int src2_enc, int dst_enc, int asi) {
925
926 uint instr;
927 instr = (Assembler::ldst_op << 30)
928 | (dst_enc << 25)
929 | (primary << 19)
930 | (src1_enc << 14);
931
932 int disp = disp32;
933 int index = src2_enc;
934
935 if (src1_enc == R_SP_enc || src1_enc == R_FP_enc)
936 disp += STACK_BIAS;
937
938 // We should have a compiler bailout here rather than a guarantee.
939 // Better yet would be some mechanism to handle variable-size matches correctly.
940 guarantee(Assembler::is_simm13(disp), "Do not match large constant offsets" );
941
942 if( disp != 0 ) {
943 // use reg-reg form
944 // set src2=R_O7 contains offset
945 index = R_O7_enc;
946 emit3_simm13( cbuf, Assembler::arith_op, index, Assembler::or_op3, 0, disp);
947 }
948 instr |= (asi << 5);
949 instr |= index;
950 uint *code = (uint*)cbuf.code_end();
951 *code = instr;
952 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
953 }
954
955 void emit_call_reloc(CodeBuffer &cbuf, intptr_t entry_point, relocInfo::relocType rtype, bool preserve_g2 = false, bool force_far_call = false) {
956 // The method which records debug information at every safepoint
957 // expects the call to be the first instruction in the snippet as
958 // it creates a PcDesc structure which tracks the offset of a call
959 // from the start of the codeBlob. This offset is computed as
960 // code_end() - code_begin() of the code which has been emitted
961 // so far.
962 // In this particular case we have skirted around the problem by
963 // putting the "mov" instruction in the delay slot but the problem
964 // may bite us again at some other point and a cleaner/generic
965 // solution using relocations would be needed.
966 MacroAssembler _masm(&cbuf);
967 __ set_inst_mark();
968
969 // We flush the current window just so that there is a valid stack copy
970 // the fact that the current window becomes active again instantly is
971 // not a problem there is nothing live in it.
972
973 #ifdef ASSERT
974 int startpos = __ offset();
975 #endif /* ASSERT */
976
977 #ifdef _LP64
978 // Calls to the runtime or native may not be reachable from compiled code,
979 // so we generate the far call sequence on 64 bit sparc.
980 // This code sequence is relocatable to any address, even on LP64.
981 if ( force_far_call ) {
982 __ relocate(rtype);
983 AddressLiteral dest(entry_point);
984 __ jumpl_to(dest, O7, O7);
985 }
986 else
987 #endif
988 {
989 __ call((address)entry_point, rtype);
990 }
991
992 if (preserve_g2) __ delayed()->mov(G2, L7);
993 else __ delayed()->nop();
994
995 if (preserve_g2) __ mov(L7, G2);
996
997 #ifdef ASSERT
998 if (preserve_g2 && (VerifyCompiledCode || VerifyOops)) {
999 #ifdef _LP64
1000 // Trash argument dump slots.
1001 __ set(0xb0b8ac0db0b8ac0d, G1);
1002 __ mov(G1, G5);
1003 __ stx(G1, SP, STACK_BIAS + 0x80);
1004 __ stx(G1, SP, STACK_BIAS + 0x88);
1005 __ stx(G1, SP, STACK_BIAS + 0x90);
1006 __ stx(G1, SP, STACK_BIAS + 0x98);
1007 __ stx(G1, SP, STACK_BIAS + 0xA0);
1008 __ stx(G1, SP, STACK_BIAS + 0xA8);
1009 #else // _LP64
1010 // this is also a native call, so smash the first 7 stack locations,
1011 // and the various registers
1012
1013 // Note: [SP+0x40] is sp[callee_aggregate_return_pointer_sp_offset],
1014 // while [SP+0x44..0x58] are the argument dump slots.
1015 __ set((intptr_t)0xbaadf00d, G1);
1016 __ mov(G1, G5);
1017 __ sllx(G1, 32, G1);
1018 __ or3(G1, G5, G1);
1019 __ mov(G1, G5);
1020 __ stx(G1, SP, 0x40);
1021 __ stx(G1, SP, 0x48);
1022 __ stx(G1, SP, 0x50);
1023 __ stw(G1, SP, 0x58); // Do not trash [SP+0x5C] which is a usable spill slot
1024 #endif // _LP64
1025 }
1026 #endif /*ASSERT*/
1027 }
1028
1029 //=============================================================================
1030 // REQUIRED FUNCTIONALITY for encoding
1031 void emit_lo(CodeBuffer &cbuf, int val) { }
1032 void emit_hi(CodeBuffer &cbuf, int val) { }
1033
1034
1035 //=============================================================================
1036
1037 #ifndef PRODUCT
1038 void MachPrologNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1039 Compile* C = ra_->C;
1040
1041 for (int i = 0; i < OptoPrologueNops; i++) {
1042 st->print_cr("NOP"); st->print("\t");
1043 }
1044
1045 if( VerifyThread ) {
1046 st->print_cr("Verify_Thread"); st->print("\t");
1047 }
1048
1049 size_t framesize = C->frame_slots() << LogBytesPerInt;
1050
1051 // Calls to C2R adapters often do not accept exceptional returns.
1052 // We require that their callers must bang for them. But be careful, because
1053 // some VM calls (such as call site linkage) can use several kilobytes of
1054 // stack. But the stack safety zone should account for that.
1055 // See bugs 4446381, 4468289, 4497237.
1056 if (C->need_stack_bang(framesize)) {
1057 st->print_cr("! stack bang"); st->print("\t");
1058 }
1059
1060 if (Assembler::is_simm13(-framesize)) {
1061 st->print ("SAVE R_SP,-%d,R_SP",framesize);
1062 } else {
1063 st->print_cr("SETHI R_SP,hi%%(-%d),R_G3",framesize); st->print("\t");
1064 st->print_cr("ADD R_G3,lo%%(-%d),R_G3",framesize); st->print("\t");
1065 st->print ("SAVE R_SP,R_G3,R_SP");
1066 }
1067
1068 }
1069 #endif
1070
1071 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1072 Compile* C = ra_->C;
1073 MacroAssembler _masm(&cbuf);
1074
1075 for (int i = 0; i < OptoPrologueNops; i++) {
1076 __ nop();
1077 }
1078
1079 __ verify_thread();
1080
1081 size_t framesize = C->frame_slots() << LogBytesPerInt;
1082 assert(framesize >= 16*wordSize, "must have room for reg. save area");
1083 assert(framesize%(2*wordSize) == 0, "must preserve 2*wordSize alignment");
1084
1085 // Calls to C2R adapters often do not accept exceptional returns.
1086 // We require that their callers must bang for them. But be careful, because
1087 // some VM calls (such as call site linkage) can use several kilobytes of
1088 // stack. But the stack safety zone should account for that.
1089 // See bugs 4446381, 4468289, 4497237.
1090 if (C->need_stack_bang(framesize)) {
1091 __ generate_stack_overflow_check(framesize);
1092 }
1093
1094 if (Assembler::is_simm13(-framesize)) {
1095 __ save(SP, -framesize, SP);
1096 } else {
1097 __ sethi(-framesize & ~0x3ff, G3);
1098 __ add(G3, -framesize & 0x3ff, G3);
1099 __ save(SP, G3, SP);
1100 }
1101 C->set_frame_complete( __ offset() );
1102 }
1103
1104 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
1105 return MachNode::size(ra_);
1106 }
1107
1108 int MachPrologNode::reloc() const {
1109 return 10; // a large enough number
1110 }
1111
1112 //=============================================================================
1113 #ifndef PRODUCT
1114 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1115 Compile* C = ra_->C;
1116
1117 if( do_polling() && ra_->C->is_method_compilation() ) {
1118 st->print("SETHI #PollAddr,L0\t! Load Polling address\n\t");
1119 #ifdef _LP64
1120 st->print("LDX [L0],G0\t!Poll for Safepointing\n\t");
1121 #else
1122 st->print("LDUW [L0],G0\t!Poll for Safepointing\n\t");
1123 #endif
1124 }
1125
1126 if( do_polling() )
1127 st->print("RET\n\t");
1128
1129 st->print("RESTORE");
1130 }
1131 #endif
1132
1133 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1134 MacroAssembler _masm(&cbuf);
1135 Compile* C = ra_->C;
1136
1137 __ verify_thread();
1138
1139 // If this does safepoint polling, then do it here
1140 if( do_polling() && ra_->C->is_method_compilation() ) {
1141 AddressLiteral polling_page(os::get_polling_page());
1142 __ sethi(polling_page, L0);
1143 __ relocate(relocInfo::poll_return_type);
1144 __ ld_ptr( L0, 0, G0 );
1145 }
1146
1147 // If this is a return, then stuff the restore in the delay slot
1148 if( do_polling() ) {
1149 __ ret();
1150 __ delayed()->restore();
1151 } else {
1152 __ restore();
1153 }
1154 }
1155
1156 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
1157 return MachNode::size(ra_);
1158 }
1159
1160 int MachEpilogNode::reloc() const {
1161 return 16; // a large enough number
1162 }
1163
1164 const Pipeline * MachEpilogNode::pipeline() const {
1165 return MachNode::pipeline_class();
1166 }
1167
1168 int MachEpilogNode::safepoint_offset() const {
1169 assert( do_polling(), "no return for this epilog node");
1170 return MacroAssembler::size_of_sethi(os::get_polling_page());
1171 }
1172
1173 //=============================================================================
1174
1175 // Figure out which register class each belongs in: rc_int, rc_float, rc_stack
1176 enum RC { rc_bad, rc_int, rc_float, rc_stack };
1177 static enum RC rc_class( OptoReg::Name reg ) {
1178 if( !OptoReg::is_valid(reg) ) return rc_bad;
1179 if (OptoReg::is_stack(reg)) return rc_stack;
1180 VMReg r = OptoReg::as_VMReg(reg);
1181 if (r->is_Register()) return rc_int;
1182 assert(r->is_FloatRegister(), "must be");
1183 return rc_float;
1184 }
1185
1186 static int impl_helper( const MachNode *mach, CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, bool is_load, int offset, int reg, int opcode, const char *op_str, int size, outputStream* st ) {
1187 if( cbuf ) {
1188 // Better yet would be some mechanism to handle variable-size matches correctly
1189 if (!Assembler::is_simm13(offset + STACK_BIAS)) {
1190 ra_->C->record_method_not_compilable("unable to handle large constant offsets");
1191 } else {
1192 emit_form3_mem_reg(*cbuf, mach, opcode, -1, R_SP_enc, offset, 0, Matcher::_regEncode[reg]);
1193 }
1194 }
1195 #ifndef PRODUCT
1196 else if( !do_size ) {
1197 if( size != 0 ) st->print("\n\t");
1198 if( is_load ) st->print("%s [R_SP + #%d],R_%s\t! spill",op_str,offset,OptoReg::regname(reg));
1199 else st->print("%s R_%s,[R_SP + #%d]\t! spill",op_str,OptoReg::regname(reg),offset);
1200 }
1201 #endif
1202 return size+4;
1203 }
1204
1205 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int op1, int op2, const char *op_str, int size, outputStream* st ) {
1206 if( cbuf ) emit3( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst], op1, 0, op2, Matcher::_regEncode[src] );
1207 #ifndef PRODUCT
1208 else if( !do_size ) {
1209 if( size != 0 ) st->print("\n\t");
1210 st->print("%s R_%s,R_%s\t! spill",op_str,OptoReg::regname(src),OptoReg::regname(dst));
1211 }
1212 #endif
1213 return size+4;
1214 }
1215
1216 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf,
1217 PhaseRegAlloc *ra_,
1218 bool do_size,
1219 outputStream* st ) const {
1220 // Get registers to move
1221 OptoReg::Name src_second = ra_->get_reg_second(in(1));
1222 OptoReg::Name src_first = ra_->get_reg_first(in(1));
1223 OptoReg::Name dst_second = ra_->get_reg_second(this );
1224 OptoReg::Name dst_first = ra_->get_reg_first(this );
1225
1226 enum RC src_second_rc = rc_class(src_second);
1227 enum RC src_first_rc = rc_class(src_first);
1228 enum RC dst_second_rc = rc_class(dst_second);
1229 enum RC dst_first_rc = rc_class(dst_first);
1230
1231 assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" );
1232
1233 // Generate spill code!
1234 int size = 0;
1235
1236 if( src_first == dst_first && src_second == dst_second )
1237 return size; // Self copy, no move
1238
1239 // --------------------------------------
1240 // Check for mem-mem move. Load into unused float registers and fall into
1241 // the float-store case.
1242 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
1243 int offset = ra_->reg2offset(src_first);
1244 // Further check for aligned-adjacent pair, so we can use a double load
1245 if( (src_first&1)==0 && src_first+1 == src_second ) {
1246 src_second = OptoReg::Name(R_F31_num);
1247 src_second_rc = rc_float;
1248 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::lddf_op3,"LDDF",size, st);
1249 } else {
1250 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::ldf_op3 ,"LDF ",size, st);
1251 }
1252 src_first = OptoReg::Name(R_F30_num);
1253 src_first_rc = rc_float;
1254 }
1255
1256 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) {
1257 int offset = ra_->reg2offset(src_second);
1258 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F31_num,Assembler::ldf_op3,"LDF ",size, st);
1259 src_second = OptoReg::Name(R_F31_num);
1260 src_second_rc = rc_float;
1261 }
1262
1263 // --------------------------------------
1264 // Check for float->int copy; requires a trip through memory
1265 if( src_first_rc == rc_float && dst_first_rc == rc_int ) {
1266 int offset = frame::register_save_words*wordSize;
1267 if( cbuf ) {
1268 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::sub_op3, R_SP_enc, 16 );
1269 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
1270 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
1271 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::add_op3, R_SP_enc, 16 );
1272 }
1273 #ifndef PRODUCT
1274 else if( !do_size ) {
1275 if( size != 0 ) st->print("\n\t");
1276 st->print( "SUB R_SP,16,R_SP\n");
1277 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
1278 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
1279 st->print("\tADD R_SP,16,R_SP\n");
1280 }
1281 #endif
1282 size += 16;
1283 }
1284
1285 // --------------------------------------
1286 // In the 32-bit 1-reg-longs build ONLY, I see mis-aligned long destinations.
1287 // In such cases, I have to do the big-endian swap. For aligned targets, the
1288 // hardware does the flop for me. Doubles are always aligned, so no problem
1289 // there. Misaligned sources only come from native-long-returns (handled
1290 // special below).
1291 #ifndef _LP64
1292 if( src_first_rc == rc_int && // source is already big-endian
1293 src_second_rc != rc_bad && // 64-bit move
1294 ((dst_first&1)!=0 || dst_second != dst_first+1) ) { // misaligned dst
1295 assert( (src_first&1)==0 && src_second == src_first+1, "source must be aligned" );
1296 // Do the big-endian flop.
1297 OptoReg::Name tmp = dst_first ; dst_first = dst_second ; dst_second = tmp ;
1298 enum RC tmp_rc = dst_first_rc; dst_first_rc = dst_second_rc; dst_second_rc = tmp_rc;
1299 }
1300 #endif
1301
1302 // --------------------------------------
1303 // Check for integer reg-reg copy
1304 if( src_first_rc == rc_int && dst_first_rc == rc_int ) {
1305 #ifndef _LP64
1306 if( src_first == R_O0_num && src_second == R_O1_num ) { // Check for the evil O0/O1 native long-return case
1307 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value
1308 // as stored in memory. On a big-endian machine like SPARC, this means that the _second
1309 // operand contains the least significant word of the 64-bit value and vice versa.
1310 OptoReg::Name tmp = OptoReg::Name(R_O7_num);
1311 assert( (dst_first&1)==0 && dst_second == dst_first+1, "return a native O0/O1 long to an aligned-adjacent 64-bit reg" );
1312 // Shift O0 left in-place, zero-extend O1, then OR them into the dst
1313 if( cbuf ) {
1314 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tmp], Assembler::sllx_op3, Matcher::_regEncode[src_first], 0x1020 );
1315 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[src_second], Assembler::srl_op3, Matcher::_regEncode[src_second], 0x0000 );
1316 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler:: or_op3, Matcher::_regEncode[tmp], 0, Matcher::_regEncode[src_second] );
1317 #ifndef PRODUCT
1318 } else if( !do_size ) {
1319 if( size != 0 ) st->print("\n\t");
1320 st->print("SLLX R_%s,32,R_%s\t! Move O0-first to O7-high\n\t", OptoReg::regname(src_first), OptoReg::regname(tmp));
1321 st->print("SRL R_%s, 0,R_%s\t! Zero-extend O1\n\t", OptoReg::regname(src_second), OptoReg::regname(src_second));
1322 st->print("OR R_%s,R_%s,R_%s\t! spill",OptoReg::regname(tmp), OptoReg::regname(src_second), OptoReg::regname(dst_first));
1323 #endif
1324 }
1325 return size+12;
1326 }
1327 else if( dst_first == R_I0_num && dst_second == R_I1_num ) {
1328 // returning a long value in I0/I1
1329 // a SpillCopy must be able to target a return instruction's reg_class
1330 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value
1331 // as stored in memory. On a big-endian machine like SPARC, this means that the _second
1332 // operand contains the least significant word of the 64-bit value and vice versa.
1333 OptoReg::Name tdest = dst_first;
1334
1335 if (src_first == dst_first) {
1336 tdest = OptoReg::Name(R_O7_num);
1337 size += 4;
1338 }
1339
1340 if( cbuf ) {
1341 assert( (src_first&1) == 0 && (src_first+1) == src_second, "return value was in an aligned-adjacent 64-bit reg");
1342 // Shift value in upper 32-bits of src to lower 32-bits of I0; move lower 32-bits to I1
1343 // ShrL_reg_imm6
1344 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tdest], Assembler::srlx_op3, Matcher::_regEncode[src_second], 32 | 0x1000 );
1345 // ShrR_reg_imm6 src, 0, dst
1346 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srl_op3, Matcher::_regEncode[src_first], 0x0000 );
1347 if (tdest != dst_first) {
1348 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler::or_op3, 0/*G0*/, 0/*op2*/, Matcher::_regEncode[tdest] );
1349 }
1350 }
1351 #ifndef PRODUCT
1352 else if( !do_size ) {
1353 if( size != 0 ) st->print("\n\t"); // %%%%% !!!!!
1354 st->print("SRLX R_%s,32,R_%s\t! Extract MSW\n\t",OptoReg::regname(src_second),OptoReg::regname(tdest));
1355 st->print("SRL R_%s, 0,R_%s\t! Extract LSW\n\t",OptoReg::regname(src_first),OptoReg::regname(dst_second));
1356 if (tdest != dst_first) {
1357 st->print("MOV R_%s,R_%s\t! spill\n\t", OptoReg::regname(tdest), OptoReg::regname(dst_first));
1358 }
1359 }
1360 #endif // PRODUCT
1361 return size+8;
1362 }
1363 #endif // !_LP64
1364 // Else normal reg-reg copy
1365 assert( src_second != dst_first, "smashed second before evacuating it" );
1366 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::or_op3,0,"MOV ",size, st);
1367 assert( (src_first&1) == 0 && (dst_first&1) == 0, "never move second-halves of int registers" );
1368 // This moves an aligned adjacent pair.
1369 // See if we are done.
1370 if( src_first+1 == src_second && dst_first+1 == dst_second )
1371 return size;
1372 }
1373
1374 // Check for integer store
1375 if( src_first_rc == rc_int && dst_first_rc == rc_stack ) {
1376 int offset = ra_->reg2offset(dst_first);
1377 // Further check for aligned-adjacent pair, so we can use a double store
1378 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1379 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stx_op3,"STX ",size, st);
1380 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stw_op3,"STW ",size, st);
1381 }
1382
1383 // Check for integer load
1384 if( dst_first_rc == rc_int && src_first_rc == rc_stack ) {
1385 int offset = ra_->reg2offset(src_first);
1386 // Further check for aligned-adjacent pair, so we can use a double load
1387 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1388 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldx_op3 ,"LDX ",size, st);
1389 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
1390 }
1391
1392 // Check for float reg-reg copy
1393 if( src_first_rc == rc_float && dst_first_rc == rc_float ) {
1394 // Further check for aligned-adjacent pair, so we can use a double move
1395 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1396 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovd_opf,"FMOVD",size, st);
1397 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovs_opf,"FMOVS",size, st);
1398 }
1399
1400 // Check for float store
1401 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) {
1402 int offset = ra_->reg2offset(dst_first);
1403 // Further check for aligned-adjacent pair, so we can use a double store
1404 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1405 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stdf_op3,"STDF",size, st);
1406 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
1407 }
1408
1409 // Check for float load
1410 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) {
1411 int offset = ra_->reg2offset(src_first);
1412 // Further check for aligned-adjacent pair, so we can use a double load
1413 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1414 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lddf_op3,"LDDF",size, st);
1415 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldf_op3 ,"LDF ",size, st);
1416 }
1417
1418 // --------------------------------------------------------------------
1419 // Check for hi bits still needing moving. Only happens for misaligned
1420 // arguments to native calls.
1421 if( src_second == dst_second )
1422 return size; // Self copy; no move
1423 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" );
1424
1425 #ifndef _LP64
1426 // In the LP64 build, all registers can be moved as aligned/adjacent
1427 // pairs, so there's never any need to move the high bits separately.
1428 // The 32-bit builds have to deal with the 32-bit ABI which can force
1429 // all sorts of silly alignment problems.
1430
1431 // Check for integer reg-reg copy. Hi bits are stuck up in the top
1432 // 32-bits of a 64-bit register, but are needed in low bits of another
1433 // register (else it's a hi-bits-to-hi-bits copy which should have
1434 // happened already as part of a 64-bit move)
1435 if( src_second_rc == rc_int && dst_second_rc == rc_int ) {
1436 assert( (src_second&1)==1, "its the evil O0/O1 native return case" );
1437 assert( (dst_second&1)==0, "should have moved with 1 64-bit move" );
1438 // Shift src_second down to dst_second's low bits.
1439 if( cbuf ) {
1440 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 );
1441 #ifndef PRODUCT
1442 } else if( !do_size ) {
1443 if( size != 0 ) st->print("\n\t");
1444 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(dst_second));
1445 #endif
1446 }
1447 return size+4;
1448 }
1449
1450 // Check for high word integer store. Must down-shift the hi bits
1451 // into a temp register, then fall into the case of storing int bits.
1452 if( src_second_rc == rc_int && dst_second_rc == rc_stack && (src_second&1)==1 ) {
1453 // Shift src_second down to dst_second's low bits.
1454 if( cbuf ) {
1455 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[R_O7_num], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 );
1456 #ifndef PRODUCT
1457 } else if( !do_size ) {
1458 if( size != 0 ) st->print("\n\t");
1459 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(R_O7_num));
1460 #endif
1461 }
1462 size+=4;
1463 src_second = OptoReg::Name(R_O7_num); // Not R_O7H_num!
1464 }
1465
1466 // Check for high word integer load
1467 if( dst_second_rc == rc_int && src_second_rc == rc_stack )
1468 return impl_helper(this,cbuf,ra_,do_size,true ,ra_->reg2offset(src_second),dst_second,Assembler::lduw_op3,"LDUW",size, st);
1469
1470 // Check for high word integer store
1471 if( src_second_rc == rc_int && dst_second_rc == rc_stack )
1472 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stw_op3 ,"STW ",size, st);
1473
1474 // Check for high word float store
1475 if( src_second_rc == rc_float && dst_second_rc == rc_stack )
1476 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stf_op3 ,"STF ",size, st);
1477
1478 #endif // !_LP64
1479
1480 Unimplemented();
1481 }
1482
1483 #ifndef PRODUCT
1484 void MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1485 implementation( NULL, ra_, false, st );
1486 }
1487 #endif
1488
1489 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1490 implementation( &cbuf, ra_, false, NULL );
1491 }
1492
1493 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1494 return implementation( NULL, ra_, true, NULL );
1495 }
1496
1497 //=============================================================================
1498 #ifndef PRODUCT
1499 void MachNopNode::format( PhaseRegAlloc *, outputStream *st ) const {
1500 st->print("NOP \t# %d bytes pad for loops and calls", 4 * _count);
1501 }
1502 #endif
1503
1504 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc * ) const {
1505 MacroAssembler _masm(&cbuf);
1506 for(int i = 0; i < _count; i += 1) {
1507 __ nop();
1508 }
1509 }
1510
1511 uint MachNopNode::size(PhaseRegAlloc *ra_) const {
1512 return 4 * _count;
1513 }
1514
1515
1516 //=============================================================================
1517 #ifndef PRODUCT
1518 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1519 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1520 int reg = ra_->get_reg_first(this);
1521 st->print("LEA [R_SP+#%d+BIAS],%s",offset,Matcher::regName[reg]);
1522 }
1523 #endif
1524
1525 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1526 MacroAssembler _masm(&cbuf);
1527 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()) + STACK_BIAS;
1528 int reg = ra_->get_encode(this);
1529
1530 if (Assembler::is_simm13(offset)) {
1531 __ add(SP, offset, reg_to_register_object(reg));
1532 } else {
1533 __ set(offset, O7);
1534 __ add(SP, O7, reg_to_register_object(reg));
1535 }
1536 }
1537
1538 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1539 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_)
1540 assert(ra_ == ra_->C->regalloc(), "sanity");
1541 return ra_->C->scratch_emit_size(this);
1542 }
1543
1544 //=============================================================================
1545
1546 // emit call stub, compiled java to interpretor
1547 void emit_java_to_interp(CodeBuffer &cbuf ) {
1548
1549 // Stub is fixed up when the corresponding call is converted from calling
1550 // compiled code to calling interpreted code.
1551 // set (empty), G5
1552 // jmp -1
1553
1554 address mark = cbuf.inst_mark(); // get mark within main instrs section
1555
1556 MacroAssembler _masm(&cbuf);
1557
1558 address base =
1559 __ start_a_stub(Compile::MAX_stubs_size);
1560 if (base == NULL) return; // CodeBuffer::expand failed
1561
1562 // static stub relocation stores the instruction address of the call
1563 __ relocate(static_stub_Relocation::spec(mark));
1564
1565 __ set_oop(NULL, reg_to_register_object(Matcher::inline_cache_reg_encode()));
1566
1567 __ set_inst_mark();
1568 AddressLiteral addrlit(-1);
1569 __ JUMP(addrlit, G3, 0);
1570
1571 __ delayed()->nop();
1572
1573 // Update current stubs pointer and restore code_end.
1574 __ end_a_stub();
1575 }
1576
1577 // size of call stub, compiled java to interpretor
1578 uint size_java_to_interp() {
1579 // This doesn't need to be accurate but it must be larger or equal to
1580 // the real size of the stub.
1581 return (NativeMovConstReg::instruction_size + // sethi/setlo;
1582 NativeJump::instruction_size + // sethi; jmp; nop
1583 (TraceJumps ? 20 * BytesPerInstWord : 0) );
1584 }
1585 // relocation entries for call stub, compiled java to interpretor
1586 uint reloc_java_to_interp() {
1587 return 10; // 4 in emit_java_to_interp + 1 in Java_Static_Call
1588 }
1589
1590
1591 //=============================================================================
1592 #ifndef PRODUCT
1593 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1594 st->print_cr("\nUEP:");
1595 #ifdef _LP64
1596 if (UseCompressedOops) {
1597 assert(Universe::heap() != NULL, "java heap should be initialized");
1598 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check - compressed klass");
1599 st->print_cr("\tSLL R_G5,3,R_G5");
1600 if (Universe::narrow_oop_base() != NULL)
1601 st->print_cr("\tADD R_G5,R_G6_heap_base,R_G5");
1602 } else {
1603 st->print_cr("\tLDX [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check");
1604 }
1605 st->print_cr("\tCMP R_G5,R_G3" );
1606 st->print ("\tTne xcc,R_G0+ST_RESERVED_FOR_USER_0+2");
1607 #else // _LP64
1608 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check");
1609 st->print_cr("\tCMP R_G5,R_G3" );
1610 st->print ("\tTne icc,R_G0+ST_RESERVED_FOR_USER_0+2");
1611 #endif // _LP64
1612 }
1613 #endif
1614
1615 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1616 MacroAssembler _masm(&cbuf);
1617 Label L;
1618 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
1619 Register temp_reg = G3;
1620 assert( G5_ic_reg != temp_reg, "conflicting registers" );
1621
1622 // Load klass from receiver
1623 __ load_klass(O0, temp_reg);
1624 // Compare against expected klass
1625 __ cmp(temp_reg, G5_ic_reg);
1626 // Branch to miss code, checks xcc or icc depending
1627 __ trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2);
1628 }
1629
1630 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
1631 return MachNode::size(ra_);
1632 }
1633
1634
1635 //=============================================================================
1636
1637 uint size_exception_handler() {
1638 if (TraceJumps) {
1639 return (400); // just a guess
1640 }
1641 return ( NativeJump::instruction_size ); // sethi;jmp;nop
1642 }
1643
1644 uint size_deopt_handler() {
1645 if (TraceJumps) {
1646 return (400); // just a guess
1647 }
1648 return ( 4+ NativeJump::instruction_size ); // save;sethi;jmp;restore
1649 }
1650
1651 // Emit exception handler code.
1652 int emit_exception_handler(CodeBuffer& cbuf) {
1653 Register temp_reg = G3;
1654 AddressLiteral exception_blob(OptoRuntime::exception_blob()->instructions_begin());
1655 MacroAssembler _masm(&cbuf);
1656
1657 address base =
1658 __ start_a_stub(size_exception_handler());
1659 if (base == NULL) return 0; // CodeBuffer::expand failed
1660
1661 int offset = __ offset();
1662
1663 __ JUMP(exception_blob, temp_reg, 0); // sethi;jmp
1664 __ delayed()->nop();
1665
1666 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
1667
1668 __ end_a_stub();
1669
1670 return offset;
1671 }
1672
1673 int emit_deopt_handler(CodeBuffer& cbuf) {
1674 // Can't use any of the current frame's registers as we may have deopted
1675 // at a poll and everything (including G3) can be live.
1676 Register temp_reg = L0;
1677 AddressLiteral deopt_blob(SharedRuntime::deopt_blob()->unpack());
1678 MacroAssembler _masm(&cbuf);
1679
1680 address base =
1681 __ start_a_stub(size_deopt_handler());
1682 if (base == NULL) return 0; // CodeBuffer::expand failed
1683
1684 int offset = __ offset();
1685 __ save_frame(0);
1686 __ JUMP(deopt_blob, temp_reg, 0); // sethi;jmp
1687 __ delayed()->restore();
1688
1689 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
1690
1691 __ end_a_stub();
1692 return offset;
1693
1694 }
1695
1696 // Given a register encoding, produce a Integer Register object
1697 static Register reg_to_register_object(int register_encoding) {
1698 assert(L5->encoding() == R_L5_enc && G1->encoding() == R_G1_enc, "right coding");
1699 return as_Register(register_encoding);
1700 }
1701
1702 // Given a register encoding, produce a single-precision Float Register object
1703 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding) {
1704 assert(F5->encoding(FloatRegisterImpl::S) == R_F5_enc && F12->encoding(FloatRegisterImpl::S) == R_F12_enc, "right coding");
1705 return as_SingleFloatRegister(register_encoding);
1706 }
1707
1708 // Given a register encoding, produce a double-precision Float Register object
1709 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding) {
1710 assert(F4->encoding(FloatRegisterImpl::D) == R_F4_enc, "right coding");
1711 assert(F32->encoding(FloatRegisterImpl::D) == R_D32_enc, "right coding");
1712 return as_DoubleFloatRegister(register_encoding);
1713 }
1714
1715 const bool Matcher::match_rule_supported(int opcode) {
1716 if (!has_match_rule(opcode))
1717 return false;
1718
1719 switch (opcode) {
1720 case Op_CountLeadingZerosI:
1721 case Op_CountLeadingZerosL:
1722 case Op_CountTrailingZerosI:
1723 case Op_CountTrailingZerosL:
1724 if (!UsePopCountInstruction)
1725 return false;
1726 break;
1727 }
1728
1729 return true; // Per default match rules are supported.
1730 }
1731
1732 int Matcher::regnum_to_fpu_offset(int regnum) {
1733 return regnum - 32; // The FP registers are in the second chunk
1734 }
1735
1736 #ifdef ASSERT
1737 address last_rethrow = NULL; // debugging aid for Rethrow encoding
1738 #endif
1739
1740 // Vector width in bytes
1741 const uint Matcher::vector_width_in_bytes(void) {
1742 return 8;
1743 }
1744
1745 // Vector ideal reg
1746 const uint Matcher::vector_ideal_reg(void) {
1747 return Op_RegD;
1748 }
1749
1750 // USII supports fxtof through the whole range of number, USIII doesn't
1751 const bool Matcher::convL2FSupported(void) {
1752 return VM_Version::has_fast_fxtof();
1753 }
1754
1755 // Is this branch offset short enough that a short branch can be used?
1756 //
1757 // NOTE: If the platform does not provide any short branch variants, then
1758 // this method should return false for offset 0.
1759 bool Matcher::is_short_branch_offset(int rule, int offset) {
1760 return false;
1761 }
1762
1763 const bool Matcher::isSimpleConstant64(jlong value) {
1764 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1765 // Depends on optimizations in MacroAssembler::setx.
1766 int hi = (int)(value >> 32);
1767 int lo = (int)(value & ~0);
1768 return (hi == 0) || (hi == -1) || (lo == 0);
1769 }
1770
1771 // No scaling for the parameter the ClearArray node.
1772 const bool Matcher::init_array_count_is_in_bytes = true;
1773
1774 // Threshold size for cleararray.
1775 const int Matcher::init_array_short_size = 8 * BytesPerLong;
1776
1777 // Should the Matcher clone shifts on addressing modes, expecting them to
1778 // be subsumed into complex addressing expressions or compute them into
1779 // registers? True for Intel but false for most RISCs
1780 const bool Matcher::clone_shift_expressions = false;
1781
1782 // Is it better to copy float constants, or load them directly from memory?
1783 // Intel can load a float constant from a direct address, requiring no
1784 // extra registers. Most RISCs will have to materialize an address into a
1785 // register first, so they would do better to copy the constant from stack.
1786 const bool Matcher::rematerialize_float_constants = false;
1787
1788 // If CPU can load and store mis-aligned doubles directly then no fixup is
1789 // needed. Else we split the double into 2 integer pieces and move it
1790 // piece-by-piece. Only happens when passing doubles into C code as the
1791 // Java calling convention forces doubles to be aligned.
1792 #ifdef _LP64
1793 const bool Matcher::misaligned_doubles_ok = true;
1794 #else
1795 const bool Matcher::misaligned_doubles_ok = false;
1796 #endif
1797
1798 // No-op on SPARC.
1799 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
1800 }
1801
1802 // Advertise here if the CPU requires explicit rounding operations
1803 // to implement the UseStrictFP mode.
1804 const bool Matcher::strict_fp_requires_explicit_rounding = false;
1805
1806 // Do floats take an entire double register or just half?
1807 const bool Matcher::float_in_double = false;
1808
1809 // Do ints take an entire long register or just half?
1810 // Note that we if-def off of _LP64.
1811 // The relevant question is how the int is callee-saved. In _LP64
1812 // the whole long is written but de-opt'ing will have to extract
1813 // the relevant 32 bits, in not-_LP64 only the low 32 bits is written.
1814 #ifdef _LP64
1815 const bool Matcher::int_in_long = true;
1816 #else
1817 const bool Matcher::int_in_long = false;
1818 #endif
1819
1820 // Return whether or not this register is ever used as an argument. This
1821 // function is used on startup to build the trampoline stubs in generateOptoStub.
1822 // Registers not mentioned will be killed by the VM call in the trampoline, and
1823 // arguments in those registers not be available to the callee.
1824 bool Matcher::can_be_java_arg( int reg ) {
1825 // Standard sparc 6 args in registers
1826 if( reg == R_I0_num ||
1827 reg == R_I1_num ||
1828 reg == R_I2_num ||
1829 reg == R_I3_num ||
1830 reg == R_I4_num ||
1831 reg == R_I5_num ) return true;
1832 #ifdef _LP64
1833 // 64-bit builds can pass 64-bit pointers and longs in
1834 // the high I registers
1835 if( reg == R_I0H_num ||
1836 reg == R_I1H_num ||
1837 reg == R_I2H_num ||
1838 reg == R_I3H_num ||
1839 reg == R_I4H_num ||
1840 reg == R_I5H_num ) return true;
1841
1842 if ((UseCompressedOops) && (reg == R_G6_num || reg == R_G6H_num)) {
1843 return true;
1844 }
1845
1846 #else
1847 // 32-bit builds with longs-in-one-entry pass longs in G1 & G4.
1848 // Longs cannot be passed in O regs, because O regs become I regs
1849 // after a 'save' and I regs get their high bits chopped off on
1850 // interrupt.
1851 if( reg == R_G1H_num || reg == R_G1_num ) return true;
1852 if( reg == R_G4H_num || reg == R_G4_num ) return true;
1853 #endif
1854 // A few float args in registers
1855 if( reg >= R_F0_num && reg <= R_F7_num ) return true;
1856
1857 return false;
1858 }
1859
1860 bool Matcher::is_spillable_arg( int reg ) {
1861 return can_be_java_arg(reg);
1862 }
1863
1864 // Register for DIVI projection of divmodI
1865 RegMask Matcher::divI_proj_mask() {
1866 ShouldNotReachHere();
1867 return RegMask();
1868 }
1869
1870 // Register for MODI projection of divmodI
1871 RegMask Matcher::modI_proj_mask() {
1872 ShouldNotReachHere();
1873 return RegMask();
1874 }
1875
1876 // Register for DIVL projection of divmodL
1877 RegMask Matcher::divL_proj_mask() {
1878 ShouldNotReachHere();
1879 return RegMask();
1880 }
1881
1882 // Register for MODL projection of divmodL
1883 RegMask Matcher::modL_proj_mask() {
1884 ShouldNotReachHere();
1885 return RegMask();
1886 }
1887
1888 %}
1889
1890
1891 // The intptr_t operand types, defined by textual substitution.
1892 // (Cf. opto/type.hpp. This lets us avoid many, many other ifdefs.)
1893 #ifdef _LP64
1894 #define immX immL
1895 #define immX13 immL13
1896 #define immX13m7 immL13m7
1897 #define iRegX iRegL
1898 #define g1RegX g1RegL
1899 #else
1900 #define immX immI
1901 #define immX13 immI13
1902 #define immX13m7 immI13m7
1903 #define iRegX iRegI
1904 #define g1RegX g1RegI
1905 #endif
1906
1907 //----------ENCODING BLOCK-----------------------------------------------------
1908 // This block specifies the encoding classes used by the compiler to output
1909 // byte streams. Encoding classes are parameterized macros used by
1910 // Machine Instruction Nodes in order to generate the bit encoding of the
1911 // instruction. Operands specify their base encoding interface with the
1912 // interface keyword. There are currently supported four interfaces,
1913 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
1914 // operand to generate a function which returns its register number when
1915 // queried. CONST_INTER causes an operand to generate a function which
1916 // returns the value of the constant when queried. MEMORY_INTER causes an
1917 // operand to generate four functions which return the Base Register, the
1918 // Index Register, the Scale Value, and the Offset Value of the operand when
1919 // queried. COND_INTER causes an operand to generate six functions which
1920 // return the encoding code (ie - encoding bits for the instruction)
1921 // associated with each basic boolean condition for a conditional instruction.
1922 //
1923 // Instructions specify two basic values for encoding. Again, a function
1924 // is available to check if the constant displacement is an oop. They use the
1925 // ins_encode keyword to specify their encoding classes (which must be
1926 // a sequence of enc_class names, and their parameters, specified in
1927 // the encoding block), and they use the
1928 // opcode keyword to specify, in order, their primary, secondary, and
1929 // tertiary opcode. Only the opcode sections which a particular instruction
1930 // needs for encoding need to be specified.
1931 encode %{
1932 enc_class enc_untested %{
1933 #ifdef ASSERT
1934 MacroAssembler _masm(&cbuf);
1935 __ untested("encoding");
1936 #endif
1937 %}
1938
1939 enc_class form3_mem_reg( memory mem, iRegI dst ) %{
1940 emit_form3_mem_reg(cbuf, this, $primary, $tertiary,
1941 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg);
1942 %}
1943
1944 enc_class simple_form3_mem_reg( memory mem, iRegI dst ) %{
1945 emit_form3_mem_reg(cbuf, this, $primary, -1,
1946 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg);
1947 %}
1948
1949 enc_class form3_mem_reg_little( memory mem, iRegI dst) %{
1950 emit_form3_mem_reg_asi(cbuf, this, $primary, -1,
1951 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg, Assembler::ASI_PRIMARY_LITTLE);
1952 %}
1953
1954 enc_class form3_mem_prefetch_read( memory mem ) %{
1955 emit_form3_mem_reg(cbuf, this, $primary, -1,
1956 $mem$$base, $mem$$disp, $mem$$index, 0/*prefetch function many-reads*/);
1957 %}
1958
1959 enc_class form3_mem_prefetch_write( memory mem ) %{
1960 emit_form3_mem_reg(cbuf, this, $primary, -1,
1961 $mem$$base, $mem$$disp, $mem$$index, 2/*prefetch function many-writes*/);
1962 %}
1963
1964 enc_class form3_mem_reg_long_unaligned_marshal( memory mem, iRegL reg ) %{
1965 assert( Assembler::is_simm13($mem$$disp ), "need disp and disp+4" );
1966 assert( Assembler::is_simm13($mem$$disp+4), "need disp and disp+4" );
1967 guarantee($mem$$index == R_G0_enc, "double index?");
1968 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, R_O7_enc );
1969 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg );
1970 emit3_simm13( cbuf, Assembler::arith_op, $reg$$reg, Assembler::sllx_op3, $reg$$reg, 0x1020 );
1971 emit3( cbuf, Assembler::arith_op, $reg$$reg, Assembler::or_op3, $reg$$reg, 0, R_O7_enc );
1972 %}
1973
1974 enc_class form3_mem_reg_double_unaligned( memory mem, RegD_low reg ) %{
1975 assert( Assembler::is_simm13($mem$$disp ), "need disp and disp+4" );
1976 assert( Assembler::is_simm13($mem$$disp+4), "need disp and disp+4" );
1977 guarantee($mem$$index == R_G0_enc, "double index?");
1978 // Load long with 2 instructions
1979 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg+0 );
1980 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, $reg$$reg+1 );
1981 %}
1982
1983 //%%% form3_mem_plus_4_reg is a hack--get rid of it
1984 enc_class form3_mem_plus_4_reg( memory mem, iRegI dst ) %{
1985 guarantee($mem$$disp, "cannot offset a reg-reg operand by 4");
1986 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp + 4, $mem$$index, $dst$$reg);
1987 %}
1988
1989 enc_class form3_g0_rs2_rd_move( iRegI rs2, iRegI rd ) %{
1990 // Encode a reg-reg copy. If it is useless, then empty encoding.
1991 if( $rs2$$reg != $rd$$reg )
1992 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, $rs2$$reg );
1993 %}
1994
1995 // Target lo half of long
1996 enc_class form3_g0_rs2_rd_move_lo( iRegI rs2, iRegL rd ) %{
1997 // Encode a reg-reg copy. If it is useless, then empty encoding.
1998 if( $rs2$$reg != LONG_LO_REG($rd$$reg) )
1999 emit3( cbuf, Assembler::arith_op, LONG_LO_REG($rd$$reg), Assembler::or_op3, 0, 0, $rs2$$reg );
2000 %}
2001
2002 // Source lo half of long
2003 enc_class form3_g0_rs2_rd_move_lo2( iRegL rs2, iRegI rd ) %{
2004 // Encode a reg-reg copy. If it is useless, then empty encoding.
2005 if( LONG_LO_REG($rs2$$reg) != $rd$$reg )
2006 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_LO_REG($rs2$$reg) );
2007 %}
2008
2009 // Target hi half of long
2010 enc_class form3_rs1_rd_copysign_hi( iRegI rs1, iRegL rd ) %{
2011 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 31 );
2012 %}
2013
2014 // Source lo half of long, and leave it sign extended.
2015 enc_class form3_rs1_rd_signextend_lo1( iRegL rs1, iRegI rd ) %{
2016 // Sign extend low half
2017 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 0, 0 );
2018 %}
2019
2020 // Source hi half of long, and leave it sign extended.
2021 enc_class form3_rs1_rd_copy_hi1( iRegL rs1, iRegI rd ) %{
2022 // Shift high half to low half
2023 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::srlx_op3, $rs1$$reg, 32 );
2024 %}
2025
2026 // Source hi half of long
2027 enc_class form3_g0_rs2_rd_move_hi2( iRegL rs2, iRegI rd ) %{
2028 // Encode a reg-reg copy. If it is useless, then empty encoding.
2029 if( LONG_HI_REG($rs2$$reg) != $rd$$reg )
2030 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_HI_REG($rs2$$reg) );
2031 %}
2032
2033 enc_class form3_rs1_rs2_rd( iRegI rs1, iRegI rs2, iRegI rd ) %{
2034 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0, $rs2$$reg );
2035 %}
2036
2037 enc_class enc_to_bool( iRegI src, iRegI dst ) %{
2038 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, 0, 0, $src$$reg );
2039 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::addc_op3 , 0, 0 );
2040 %}
2041
2042 enc_class enc_ltmask( iRegI p, iRegI q, iRegI dst ) %{
2043 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $p$$reg, 0, $q$$reg );
2044 // clear if nothing else is happening
2045 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 0 );
2046 // blt,a,pn done
2047 emit2_19 ( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less, Assembler::bp_op2, Assembler::icc, 0/*predict not taken*/, 2 );
2048 // mov dst,-1 in delay slot
2049 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 );
2050 %}
2051
2052 enc_class form3_rs1_imm5_rd( iRegI rs1, immU5 imm5, iRegI rd ) %{
2053 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $imm5$$constant & 0x1F );
2054 %}
2055
2056 enc_class form3_sd_rs1_imm6_rd( iRegL rs1, immU6 imm6, iRegL rd ) %{
2057 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, ($imm6$$constant & 0x3F) | 0x1000 );
2058 %}
2059
2060 enc_class form3_sd_rs1_rs2_rd( iRegL rs1, iRegI rs2, iRegL rd ) %{
2061 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0x80, $rs2$$reg );
2062 %}
2063
2064 enc_class form3_rs1_simm13_rd( iRegI rs1, immI13 simm13, iRegI rd ) %{
2065 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $simm13$$constant );
2066 %}
2067
2068 enc_class move_return_pc_to_o1() %{
2069 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::add_op3, R_O7_enc, frame::pc_return_offset );
2070 %}
2071
2072 #ifdef _LP64
2073 /* %%% merge with enc_to_bool */
2074 enc_class enc_convP2B( iRegI dst, iRegP src ) %{
2075 MacroAssembler _masm(&cbuf);
2076
2077 Register src_reg = reg_to_register_object($src$$reg);
2078 Register dst_reg = reg_to_register_object($dst$$reg);
2079 __ movr(Assembler::rc_nz, src_reg, 1, dst_reg);
2080 %}
2081 #endif
2082
2083 enc_class enc_cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp ) %{
2084 // (Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)))
2085 MacroAssembler _masm(&cbuf);
2086
2087 Register p_reg = reg_to_register_object($p$$reg);
2088 Register q_reg = reg_to_register_object($q$$reg);
2089 Register y_reg = reg_to_register_object($y$$reg);
2090 Register tmp_reg = reg_to_register_object($tmp$$reg);
2091
2092 __ subcc( p_reg, q_reg, p_reg );
2093 __ add ( p_reg, y_reg, tmp_reg );
2094 __ movcc( Assembler::less, false, Assembler::icc, tmp_reg, p_reg );
2095 %}
2096
2097 enc_class form_d2i_helper(regD src, regF dst) %{
2098 // fcmp %fcc0,$src,$src
2099 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg );
2100 // branch %fcc0 not-nan, predict taken
2101 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2102 // fdtoi $src,$dst
2103 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtoi_opf, $src$$reg );
2104 // fitos $dst,$dst (if nan)
2105 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg );
2106 // clear $dst (if nan)
2107 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg );
2108 // carry on here...
2109 %}
2110
2111 enc_class form_d2l_helper(regD src, regD dst) %{
2112 // fcmp %fcc0,$src,$src check for NAN
2113 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg );
2114 // branch %fcc0 not-nan, predict taken
2115 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2116 // fdtox $src,$dst convert in delay slot
2117 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtox_opf, $src$$reg );
2118 // fxtod $dst,$dst (if nan)
2119 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg );
2120 // clear $dst (if nan)
2121 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg );
2122 // carry on here...
2123 %}
2124
2125 enc_class form_f2i_helper(regF src, regF dst) %{
2126 // fcmps %fcc0,$src,$src
2127 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg );
2128 // branch %fcc0 not-nan, predict taken
2129 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2130 // fstoi $src,$dst
2131 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstoi_opf, $src$$reg );
2132 // fitos $dst,$dst (if nan)
2133 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg );
2134 // clear $dst (if nan)
2135 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg );
2136 // carry on here...
2137 %}
2138
2139 enc_class form_f2l_helper(regF src, regD dst) %{
2140 // fcmps %fcc0,$src,$src
2141 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg );
2142 // branch %fcc0 not-nan, predict taken
2143 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2144 // fstox $src,$dst
2145 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstox_opf, $src$$reg );
2146 // fxtod $dst,$dst (if nan)
2147 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg );
2148 // clear $dst (if nan)
2149 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg );
2150 // carry on here...
2151 %}
2152
2153 enc_class form3_opf_rs2F_rdF(regF rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2154 enc_class form3_opf_rs2F_rdD(regF rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2155 enc_class form3_opf_rs2D_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2156 enc_class form3_opf_rs2D_rdD(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2157
2158 enc_class form3_opf_rs2D_lo_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg+1); %}
2159
2160 enc_class form3_opf_rs2D_hi_rdD_hi(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2161 enc_class form3_opf_rs2D_lo_rdD_lo(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg+1,$primary,0,$tertiary,$rs2$$reg+1); %}
2162
2163 enc_class form3_opf_rs1F_rs2F_rdF( regF rs1, regF rs2, regF rd ) %{
2164 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2165 %}
2166
2167 enc_class form3_opf_rs1D_rs2D_rdD( regD rs1, regD rs2, regD rd ) %{
2168 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2169 %}
2170
2171 enc_class form3_opf_rs1F_rs2F_fcc( regF rs1, regF rs2, flagsRegF fcc ) %{
2172 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2173 %}
2174
2175 enc_class form3_opf_rs1D_rs2D_fcc( regD rs1, regD rs2, flagsRegF fcc ) %{
2176 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2177 %}
2178
2179 enc_class form3_convI2F(regF rs2, regF rd) %{
2180 emit3(cbuf,Assembler::arith_op,$rd$$reg,Assembler::fpop1_op3,0,$secondary,$rs2$$reg);
2181 %}
2182
2183 // Encloding class for traceable jumps
2184 enc_class form_jmpl(g3RegP dest) %{
2185 emit_jmpl(cbuf, $dest$$reg);
2186 %}
2187
2188 enc_class form_jmpl_set_exception_pc(g1RegP dest) %{
2189 emit_jmpl_set_exception_pc(cbuf, $dest$$reg);
2190 %}
2191
2192 enc_class form2_nop() %{
2193 emit_nop(cbuf);
2194 %}
2195
2196 enc_class form2_illtrap() %{
2197 emit_illtrap(cbuf);
2198 %}
2199
2200
2201 // Compare longs and convert into -1, 0, 1.
2202 enc_class cmpl_flag( iRegL src1, iRegL src2, iRegI dst ) %{
2203 // CMP $src1,$src2
2204 emit3( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $src1$$reg, 0, $src2$$reg );
2205 // blt,a,pn done
2206 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less , Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 5 );
2207 // mov dst,-1 in delay slot
2208 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 );
2209 // bgt,a,pn done
2210 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::greater, Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 3 );
2211 // mov dst,1 in delay slot
2212 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 1 );
2213 // CLR $dst
2214 emit3( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3 , 0, 0, 0 );
2215 %}
2216
2217 enc_class enc_PartialSubtypeCheck() %{
2218 MacroAssembler _masm(&cbuf);
2219 __ call(StubRoutines::Sparc::partial_subtype_check(), relocInfo::runtime_call_type);
2220 __ delayed()->nop();
2221 %}
2222
2223 enc_class enc_bp( Label labl, cmpOp cmp, flagsReg cc ) %{
2224 MacroAssembler _masm(&cbuf);
2225 Label &L = *($labl$$label);
2226 Assembler::Predict predict_taken =
2227 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn;
2228
2229 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, L);
2230 __ delayed()->nop();
2231 %}
2232
2233 enc_class enc_bpl( Label labl, cmpOp cmp, flagsRegL cc ) %{
2234 MacroAssembler _masm(&cbuf);
2235 Label &L = *($labl$$label);
2236 Assembler::Predict predict_taken =
2237 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn;
2238
2239 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, L);
2240 __ delayed()->nop();
2241 %}
2242
2243 enc_class enc_bpx( Label labl, cmpOp cmp, flagsRegP cc ) %{
2244 MacroAssembler _masm(&cbuf);
2245 Label &L = *($labl$$label);
2246 Assembler::Predict predict_taken =
2247 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn;
2248
2249 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, L);
2250 __ delayed()->nop();
2251 %}
2252
2253 enc_class enc_fbp( Label labl, cmpOpF cmp, flagsRegF cc ) %{
2254 MacroAssembler _masm(&cbuf);
2255 Label &L = *($labl$$label);
2256 Assembler::Predict predict_taken =
2257 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn;
2258
2259 __ fbp( (Assembler::Condition)($cmp$$cmpcode), false, (Assembler::CC)($cc$$reg), predict_taken, L);
2260 __ delayed()->nop();
2261 %}
2262
2263 enc_class jump_enc( iRegX switch_val, o7RegI table) %{
2264 MacroAssembler _masm(&cbuf);
2265
2266 Register switch_reg = as_Register($switch_val$$reg);
2267 Register table_reg = O7;
2268
2269 address table_base = __ address_table_constant(_index2label);
2270 RelocationHolder rspec = internal_word_Relocation::spec(table_base);
2271
2272 // Move table address into a register.
2273 __ set(table_base, table_reg, rspec);
2274
2275 // Jump to base address + switch value
2276 __ ld_ptr(table_reg, switch_reg, table_reg);
2277 __ jmp(table_reg, G0);
2278 __ delayed()->nop();
2279
2280 %}
2281
2282 enc_class enc_ba( Label labl ) %{
2283 MacroAssembler _masm(&cbuf);
2284 Label &L = *($labl$$label);
2285 __ ba(false, L);
2286 __ delayed()->nop();
2287 %}
2288
2289 enc_class enc_bpr( Label labl, cmpOp_reg cmp, iRegI op1 ) %{
2290 MacroAssembler _masm(&cbuf);
2291 Label &L = *$labl$$label;
2292 Assembler::Predict predict_taken =
2293 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn;
2294
2295 __ bpr( (Assembler::RCondition)($cmp$$cmpcode), false, predict_taken, as_Register($op1$$reg), L);
2296 __ delayed()->nop();
2297 %}
2298
2299 enc_class enc_cmov_reg( cmpOp cmp, iRegI dst, iRegI src, immI pcc) %{
2300 int op = (Assembler::arith_op << 30) |
2301 ($dst$$reg << 25) |
2302 (Assembler::movcc_op3 << 19) |
2303 (1 << 18) | // cc2 bit for 'icc'
2304 ($cmp$$cmpcode << 14) |
2305 (0 << 13) | // select register move
2306 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc' or 'xcc'
2307 ($src$$reg << 0);
2308 *((int*)(cbuf.code_end())) = op;
2309 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
2310 %}
2311
2312 enc_class enc_cmov_imm( cmpOp cmp, iRegI dst, immI11 src, immI pcc ) %{
2313 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits
2314 int op = (Assembler::arith_op << 30) |
2315 ($dst$$reg << 25) |
2316 (Assembler::movcc_op3 << 19) |
2317 (1 << 18) | // cc2 bit for 'icc'
2318 ($cmp$$cmpcode << 14) |
2319 (1 << 13) | // select immediate move
2320 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc'
2321 (simm11 << 0);
2322 *((int*)(cbuf.code_end())) = op;
2323 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
2324 %}
2325
2326 enc_class enc_cmov_reg_f( cmpOpF cmp, iRegI dst, iRegI src, flagsRegF fcc ) %{
2327 int op = (Assembler::arith_op << 30) |
2328 ($dst$$reg << 25) |
2329 (Assembler::movcc_op3 << 19) |
2330 (0 << 18) | // cc2 bit for 'fccX'
2331 ($cmp$$cmpcode << 14) |
2332 (0 << 13) | // select register move
2333 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3
2334 ($src$$reg << 0);
2335 *((int*)(cbuf.code_end())) = op;
2336 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
2337 %}
2338
2339 enc_class enc_cmov_imm_f( cmpOp cmp, iRegI dst, immI11 src, flagsRegF fcc ) %{
2340 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits
2341 int op = (Assembler::arith_op << 30) |
2342 ($dst$$reg << 25) |
2343 (Assembler::movcc_op3 << 19) |
2344 (0 << 18) | // cc2 bit for 'fccX'
2345 ($cmp$$cmpcode << 14) |
2346 (1 << 13) | // select immediate move
2347 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3
2348 (simm11 << 0);
2349 *((int*)(cbuf.code_end())) = op;
2350 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
2351 %}
2352
2353 enc_class enc_cmovf_reg( cmpOp cmp, regD dst, regD src, immI pcc ) %{
2354 int op = (Assembler::arith_op << 30) |
2355 ($dst$$reg << 25) |
2356 (Assembler::fpop2_op3 << 19) |
2357 (0 << 18) |
2358 ($cmp$$cmpcode << 14) |
2359 (1 << 13) | // select register move
2360 ($pcc$$constant << 11) | // cc1-cc0 bits for 'icc' or 'xcc'
2361 ($primary << 5) | // select single, double or quad
2362 ($src$$reg << 0);
2363 *((int*)(cbuf.code_end())) = op;
2364 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
2365 %}
2366
2367 enc_class enc_cmovff_reg( cmpOpF cmp, flagsRegF fcc, regD dst, regD src ) %{
2368 int op = (Assembler::arith_op << 30) |
2369 ($dst$$reg << 25) |
2370 (Assembler::fpop2_op3 << 19) |
2371 (0 << 18) |
2372 ($cmp$$cmpcode << 14) |
2373 ($fcc$$reg << 11) | // cc2-cc0 bits for 'fccX'
2374 ($primary << 5) | // select single, double or quad
2375 ($src$$reg << 0);
2376 *((int*)(cbuf.code_end())) = op;
2377 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
2378 %}
2379
2380 // Used by the MIN/MAX encodings. Same as a CMOV, but
2381 // the condition comes from opcode-field instead of an argument.
2382 enc_class enc_cmov_reg_minmax( iRegI dst, iRegI src ) %{
2383 int op = (Assembler::arith_op << 30) |
2384 ($dst$$reg << 25) |
2385 (Assembler::movcc_op3 << 19) |
2386 (1 << 18) | // cc2 bit for 'icc'
2387 ($primary << 14) |
2388 (0 << 13) | // select register move
2389 (0 << 11) | // cc1, cc0 bits for 'icc'
2390 ($src$$reg << 0);
2391 *((int*)(cbuf.code_end())) = op;
2392 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
2393 %}
2394
2395 enc_class enc_cmov_reg_minmax_long( iRegL dst, iRegL src ) %{
2396 int op = (Assembler::arith_op << 30) |
2397 ($dst$$reg << 25) |
2398 (Assembler::movcc_op3 << 19) |
2399 (6 << 16) | // cc2 bit for 'xcc'
2400 ($primary << 14) |
2401 (0 << 13) | // select register move
2402 (0 << 11) | // cc1, cc0 bits for 'icc'
2403 ($src$$reg << 0);
2404 *((int*)(cbuf.code_end())) = op;
2405 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
2406 %}
2407
2408 // Utility encoding for loading a 64 bit Pointer into a register
2409 // The 64 bit pointer is stored in the generated code stream
2410 enc_class SetPtr( immP src, iRegP rd ) %{
2411 Register dest = reg_to_register_object($rd$$reg);
2412 MacroAssembler _masm(&cbuf);
2413 // [RGV] This next line should be generated from ADLC
2414 if ( _opnds[1]->constant_is_oop() ) {
2415 intptr_t val = $src$$constant;
2416 __ set_oop_constant((jobject)val, dest);
2417 } else { // non-oop pointers, e.g. card mark base, heap top
2418 __ set($src$$constant, dest);
2419 }
2420 %}
2421
2422 enc_class Set13( immI13 src, iRegI rd ) %{
2423 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, $src$$constant );
2424 %}
2425
2426 enc_class SetHi22( immI src, iRegI rd ) %{
2427 emit2_22( cbuf, Assembler::branch_op, $rd$$reg, Assembler::sethi_op2, $src$$constant );
2428 %}
2429
2430 enc_class Set32( immI src, iRegI rd ) %{
2431 MacroAssembler _masm(&cbuf);
2432 __ set($src$$constant, reg_to_register_object($rd$$reg));
2433 %}
2434
2435 enc_class SetNull( iRegI rd ) %{
2436 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0 );
2437 %}
2438
2439 enc_class call_epilog %{
2440 if( VerifyStackAtCalls ) {
2441 MacroAssembler _masm(&cbuf);
2442 int framesize = ra_->C->frame_slots() << LogBytesPerInt;
2443 Register temp_reg = G3;
2444 __ add(SP, framesize, temp_reg);
2445 __ cmp(temp_reg, FP);
2446 __ breakpoint_trap(Assembler::notEqual, Assembler::ptr_cc);
2447 }
2448 %}
2449
2450 // Long values come back from native calls in O0:O1 in the 32-bit VM, copy the value
2451 // to G1 so the register allocator will not have to deal with the misaligned register
2452 // pair.
2453 enc_class adjust_long_from_native_call %{
2454 #ifndef _LP64
2455 if (returns_long()) {
2456 // sllx O0,32,O0
2457 emit3_simm13( cbuf, Assembler::arith_op, R_O0_enc, Assembler::sllx_op3, R_O0_enc, 0x1020 );
2458 // srl O1,0,O1
2459 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::srl_op3, R_O1_enc, 0x0000 );
2460 // or O0,O1,G1
2461 emit3 ( cbuf, Assembler::arith_op, R_G1_enc, Assembler:: or_op3, R_O0_enc, 0, R_O1_enc );
2462 }
2463 #endif
2464 %}
2465
2466 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime
2467 // CALL directly to the runtime
2468 // The user of this is responsible for ensuring that R_L7 is empty (killed).
2469 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type,
2470 /*preserve_g2=*/true, /*force far call*/true);
2471 %}
2472
2473 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL
2474 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
2475 // who we intended to call.
2476 if ( !_method ) {
2477 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type);
2478 } else if (_optimized_virtual) {
2479 emit_call_reloc(cbuf, $meth$$method, relocInfo::opt_virtual_call_type);
2480 } else {
2481 emit_call_reloc(cbuf, $meth$$method, relocInfo::static_call_type);
2482 }
2483 if( _method ) { // Emit stub for static call
2484 emit_java_to_interp(cbuf);
2485 }
2486 %}
2487
2488 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL
2489 MacroAssembler _masm(&cbuf);
2490 __ set_inst_mark();
2491 int vtable_index = this->_vtable_index;
2492 // MachCallDynamicJavaNode::ret_addr_offset uses this same test
2493 if (vtable_index < 0) {
2494 // must be invalid_vtable_index, not nonvirtual_vtable_index
2495 assert(vtable_index == methodOopDesc::invalid_vtable_index, "correct sentinel value");
2496 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
2497 assert(G5_ic_reg == G5_inline_cache_reg, "G5_inline_cache_reg used in assemble_ic_buffer_code()");
2498 assert(G5_ic_reg == G5_megamorphic_method, "G5_megamorphic_method used in megamorphic call stub");
2499 // !!!!!
2500 // Generate "set 0x01, R_G5", placeholder instruction to load oop-info
2501 // emit_call_dynamic_prologue( cbuf );
2502 __ set_oop((jobject)Universe::non_oop_word(), G5_ic_reg);
2503
2504 address virtual_call_oop_addr = __ inst_mark();
2505 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
2506 // who we intended to call.
2507 __ relocate(virtual_call_Relocation::spec(virtual_call_oop_addr));
2508 emit_call_reloc(cbuf, $meth$$method, relocInfo::none);
2509 } else {
2510 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
2511 // Just go thru the vtable
2512 // get receiver klass (receiver already checked for non-null)
2513 // If we end up going thru a c2i adapter interpreter expects method in G5
2514 int off = __ offset();
2515 __ load_klass(O0, G3_scratch);
2516 int klass_load_size;
2517 if (UseCompressedOops) {
2518 assert(Universe::heap() != NULL, "java heap should be initialized");
2519 if (Universe::narrow_oop_base() == NULL)
2520 klass_load_size = 2*BytesPerInstWord;
2521 else
2522 klass_load_size = 3*BytesPerInstWord;
2523 } else {
2524 klass_load_size = 1*BytesPerInstWord;
2525 }
2526 int entry_offset = instanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size();
2527 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes();
2528 if( __ is_simm13(v_off) ) {
2529 __ ld_ptr(G3, v_off, G5_method);
2530 } else {
2531 // Generate 2 instructions
2532 __ Assembler::sethi(v_off & ~0x3ff, G5_method);
2533 __ or3(G5_method, v_off & 0x3ff, G5_method);
2534 // ld_ptr, set_hi, set
2535 assert(__ offset() - off == klass_load_size + 2*BytesPerInstWord,
2536 "Unexpected instruction size(s)");
2537 __ ld_ptr(G3, G5_method, G5_method);
2538 }
2539 // NOTE: for vtable dispatches, the vtable entry will never be null.
2540 // However it may very well end up in handle_wrong_method if the
2541 // method is abstract for the particular class.
2542 __ ld_ptr(G5_method, in_bytes(methodOopDesc::from_compiled_offset()), G3_scratch);
2543 // jump to target (either compiled code or c2iadapter)
2544 __ jmpl(G3_scratch, G0, O7);
2545 __ delayed()->nop();
2546 }
2547 %}
2548
2549 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL
2550 MacroAssembler _masm(&cbuf);
2551
2552 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
2553 Register temp_reg = G3; // caller must kill G3! We cannot reuse G5_ic_reg here because
2554 // we might be calling a C2I adapter which needs it.
2555
2556 assert(temp_reg != G5_ic_reg, "conflicting registers");
2557 // Load nmethod
2558 __ ld_ptr(G5_ic_reg, in_bytes(methodOopDesc::from_compiled_offset()), temp_reg);
2559
2560 // CALL to compiled java, indirect the contents of G3
2561 __ set_inst_mark();
2562 __ callr(temp_reg, G0);
2563 __ delayed()->nop();
2564 %}
2565
2566 enc_class idiv_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst) %{
2567 MacroAssembler _masm(&cbuf);
2568 Register Rdividend = reg_to_register_object($src1$$reg);
2569 Register Rdivisor = reg_to_register_object($src2$$reg);
2570 Register Rresult = reg_to_register_object($dst$$reg);
2571
2572 __ sra(Rdivisor, 0, Rdivisor);
2573 __ sra(Rdividend, 0, Rdividend);
2574 __ sdivx(Rdividend, Rdivisor, Rresult);
2575 %}
2576
2577 enc_class idiv_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst) %{
2578 MacroAssembler _masm(&cbuf);
2579
2580 Register Rdividend = reg_to_register_object($src1$$reg);
2581 int divisor = $imm$$constant;
2582 Register Rresult = reg_to_register_object($dst$$reg);
2583
2584 __ sra(Rdividend, 0, Rdividend);
2585 __ sdivx(Rdividend, divisor, Rresult);
2586 %}
2587
2588 enc_class enc_mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2) %{
2589 MacroAssembler _masm(&cbuf);
2590 Register Rsrc1 = reg_to_register_object($src1$$reg);
2591 Register Rsrc2 = reg_to_register_object($src2$$reg);
2592 Register Rdst = reg_to_register_object($dst$$reg);
2593
2594 __ sra( Rsrc1, 0, Rsrc1 );
2595 __ sra( Rsrc2, 0, Rsrc2 );
2596 __ mulx( Rsrc1, Rsrc2, Rdst );
2597 __ srlx( Rdst, 32, Rdst );
2598 %}
2599
2600 enc_class irem_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst, o7RegL scratch) %{
2601 MacroAssembler _masm(&cbuf);
2602 Register Rdividend = reg_to_register_object($src1$$reg);
2603 Register Rdivisor = reg_to_register_object($src2$$reg);
2604 Register Rresult = reg_to_register_object($dst$$reg);
2605 Register Rscratch = reg_to_register_object($scratch$$reg);
2606
2607 assert(Rdividend != Rscratch, "");
2608 assert(Rdivisor != Rscratch, "");
2609
2610 __ sra(Rdividend, 0, Rdividend);
2611 __ sra(Rdivisor, 0, Rdivisor);
2612 __ sdivx(Rdividend, Rdivisor, Rscratch);
2613 __ mulx(Rscratch, Rdivisor, Rscratch);
2614 __ sub(Rdividend, Rscratch, Rresult);
2615 %}
2616
2617 enc_class irem_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst, o7RegL scratch) %{
2618 MacroAssembler _masm(&cbuf);
2619
2620 Register Rdividend = reg_to_register_object($src1$$reg);
2621 int divisor = $imm$$constant;
2622 Register Rresult = reg_to_register_object($dst$$reg);
2623 Register Rscratch = reg_to_register_object($scratch$$reg);
2624
2625 assert(Rdividend != Rscratch, "");
2626
2627 __ sra(Rdividend, 0, Rdividend);
2628 __ sdivx(Rdividend, divisor, Rscratch);
2629 __ mulx(Rscratch, divisor, Rscratch);
2630 __ sub(Rdividend, Rscratch, Rresult);
2631 %}
2632
2633 enc_class fabss (sflt_reg dst, sflt_reg src) %{
2634 MacroAssembler _masm(&cbuf);
2635
2636 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2637 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2638
2639 __ fabs(FloatRegisterImpl::S, Fsrc, Fdst);
2640 %}
2641
2642 enc_class fabsd (dflt_reg dst, dflt_reg src) %{
2643 MacroAssembler _masm(&cbuf);
2644
2645 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2646 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2647
2648 __ fabs(FloatRegisterImpl::D, Fsrc, Fdst);
2649 %}
2650
2651 enc_class fnegd (dflt_reg dst, dflt_reg src) %{
2652 MacroAssembler _masm(&cbuf);
2653
2654 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2655 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2656
2657 __ fneg(FloatRegisterImpl::D, Fsrc, Fdst);
2658 %}
2659
2660 enc_class fsqrts (sflt_reg dst, sflt_reg src) %{
2661 MacroAssembler _masm(&cbuf);
2662
2663 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2664 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2665
2666 __ fsqrt(FloatRegisterImpl::S, Fsrc, Fdst);
2667 %}
2668
2669 enc_class fsqrtd (dflt_reg dst, dflt_reg src) %{
2670 MacroAssembler _masm(&cbuf);
2671
2672 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2673 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2674
2675 __ fsqrt(FloatRegisterImpl::D, Fsrc, Fdst);
2676 %}
2677
2678 enc_class fmovs (dflt_reg dst, dflt_reg src) %{
2679 MacroAssembler _masm(&cbuf);
2680
2681 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2682 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2683
2684 __ fmov(FloatRegisterImpl::S, Fsrc, Fdst);
2685 %}
2686
2687 enc_class fmovd (dflt_reg dst, dflt_reg src) %{
2688 MacroAssembler _masm(&cbuf);
2689
2690 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2691 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2692
2693 __ fmov(FloatRegisterImpl::D, Fsrc, Fdst);
2694 %}
2695
2696 enc_class Fast_Lock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{
2697 MacroAssembler _masm(&cbuf);
2698
2699 Register Roop = reg_to_register_object($oop$$reg);
2700 Register Rbox = reg_to_register_object($box$$reg);
2701 Register Rscratch = reg_to_register_object($scratch$$reg);
2702 Register Rmark = reg_to_register_object($scratch2$$reg);
2703
2704 assert(Roop != Rscratch, "");
2705 assert(Roop != Rmark, "");
2706 assert(Rbox != Rscratch, "");
2707 assert(Rbox != Rmark, "");
2708
2709 __ compiler_lock_object(Roop, Rmark, Rbox, Rscratch, _counters, UseBiasedLocking && !UseOptoBiasInlining);
2710 %}
2711
2712 enc_class Fast_Unlock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{
2713 MacroAssembler _masm(&cbuf);
2714
2715 Register Roop = reg_to_register_object($oop$$reg);
2716 Register Rbox = reg_to_register_object($box$$reg);
2717 Register Rscratch = reg_to_register_object($scratch$$reg);
2718 Register Rmark = reg_to_register_object($scratch2$$reg);
2719
2720 assert(Roop != Rscratch, "");
2721 assert(Roop != Rmark, "");
2722 assert(Rbox != Rscratch, "");
2723 assert(Rbox != Rmark, "");
2724
2725 __ compiler_unlock_object(Roop, Rmark, Rbox, Rscratch, UseBiasedLocking && !UseOptoBiasInlining);
2726 %}
2727
2728 enc_class enc_cas( iRegP mem, iRegP old, iRegP new ) %{
2729 MacroAssembler _masm(&cbuf);
2730 Register Rmem = reg_to_register_object($mem$$reg);
2731 Register Rold = reg_to_register_object($old$$reg);
2732 Register Rnew = reg_to_register_object($new$$reg);
2733
2734 // casx_under_lock picks 1 of 3 encodings:
2735 // For 32-bit pointers you get a 32-bit CAS
2736 // For 64-bit pointers you get a 64-bit CASX
2737 __ casn(Rmem, Rold, Rnew); // Swap(*Rmem,Rnew) if *Rmem == Rold
2738 __ cmp( Rold, Rnew );
2739 %}
2740
2741 enc_class enc_casx( iRegP mem, iRegL old, iRegL new) %{
2742 Register Rmem = reg_to_register_object($mem$$reg);
2743 Register Rold = reg_to_register_object($old$$reg);
2744 Register Rnew = reg_to_register_object($new$$reg);
2745
2746 MacroAssembler _masm(&cbuf);
2747 __ mov(Rnew, O7);
2748 __ casx(Rmem, Rold, O7);
2749 __ cmp( Rold, O7 );
2750 %}
2751
2752 // raw int cas, used for compareAndSwap
2753 enc_class enc_casi( iRegP mem, iRegL old, iRegL new) %{
2754 Register Rmem = reg_to_register_object($mem$$reg);
2755 Register Rold = reg_to_register_object($old$$reg);
2756 Register Rnew = reg_to_register_object($new$$reg);
2757
2758 MacroAssembler _masm(&cbuf);
2759 __ mov(Rnew, O7);
2760 __ cas(Rmem, Rold, O7);
2761 __ cmp( Rold, O7 );
2762 %}
2763
2764 enc_class enc_lflags_ne_to_boolean( iRegI res ) %{
2765 Register Rres = reg_to_register_object($res$$reg);
2766
2767 MacroAssembler _masm(&cbuf);
2768 __ mov(1, Rres);
2769 __ movcc( Assembler::notEqual, false, Assembler::xcc, G0, Rres );
2770 %}
2771
2772 enc_class enc_iflags_ne_to_boolean( iRegI res ) %{
2773 Register Rres = reg_to_register_object($res$$reg);
2774
2775 MacroAssembler _masm(&cbuf);
2776 __ mov(1, Rres);
2777 __ movcc( Assembler::notEqual, false, Assembler::icc, G0, Rres );
2778 %}
2779
2780 enc_class floating_cmp ( iRegP dst, regF src1, regF src2 ) %{
2781 MacroAssembler _masm(&cbuf);
2782 Register Rdst = reg_to_register_object($dst$$reg);
2783 FloatRegister Fsrc1 = $primary ? reg_to_SingleFloatRegister_object($src1$$reg)
2784 : reg_to_DoubleFloatRegister_object($src1$$reg);
2785 FloatRegister Fsrc2 = $primary ? reg_to_SingleFloatRegister_object($src2$$reg)
2786 : reg_to_DoubleFloatRegister_object($src2$$reg);
2787
2788 // Convert condition code fcc0 into -1,0,1; unordered reports less-than (-1)
2789 __ float_cmp( $primary, -1, Fsrc1, Fsrc2, Rdst);
2790 %}
2791
2792 enc_class LdImmL (immL src, iRegL dst, o7RegL tmp) %{ // Load Immediate
2793 MacroAssembler _masm(&cbuf);
2794 Register dest = reg_to_register_object($dst$$reg);
2795 Register temp = reg_to_register_object($tmp$$reg);
2796 __ set64( $src$$constant, dest, temp );
2797 %}
2798
2799 enc_class LdReplImmI(immI src, regD dst, o7RegP tmp, int count, int width) %{
2800 // Load a constant replicated "count" times with width "width"
2801 int bit_width = $width$$constant * 8;
2802 jlong elt_val = $src$$constant;
2803 elt_val &= (((jlong)1) << bit_width) - 1; // mask off sign bits
2804 jlong val = elt_val;
2805 for (int i = 0; i < $count$$constant - 1; i++) {
2806 val <<= bit_width;
2807 val |= elt_val;
2808 }
2809 jdouble dval = *(jdouble*)&val; // coerce to double type
2810 MacroAssembler _masm(&cbuf);
2811 address double_address = __ double_constant(dval);
2812 RelocationHolder rspec = internal_word_Relocation::spec(double_address);
2813 AddressLiteral addrlit(double_address, rspec);
2814
2815 __ sethi(addrlit, $tmp$$Register);
2816 // XXX This is a quick fix for 6833573.
2817 //__ ldf(FloatRegisterImpl::D, $tmp$$Register, addrlit.low10(), $dst$$FloatRegister, rspec);
2818 __ ldf(FloatRegisterImpl::D, $tmp$$Register, addrlit.low10(), as_DoubleFloatRegister($dst$$reg), rspec);
2819 %}
2820
2821 // Compiler ensures base is doubleword aligned and cnt is count of doublewords
2822 enc_class enc_Clear_Array(iRegX cnt, iRegP base, iRegX temp) %{
2823 MacroAssembler _masm(&cbuf);
2824 Register nof_bytes_arg = reg_to_register_object($cnt$$reg);
2825 Register nof_bytes_tmp = reg_to_register_object($temp$$reg);
2826 Register base_pointer_arg = reg_to_register_object($base$$reg);
2827
2828 Label loop;
2829 __ mov(nof_bytes_arg, nof_bytes_tmp);
2830
2831 // Loop and clear, walking backwards through the array.
2832 // nof_bytes_tmp (if >0) is always the number of bytes to zero
2833 __ bind(loop);
2834 __ deccc(nof_bytes_tmp, 8);
2835 __ br(Assembler::greaterEqual, true, Assembler::pt, loop);
2836 __ delayed()-> stx(G0, base_pointer_arg, nof_bytes_tmp);
2837 // %%%% this mini-loop must not cross a cache boundary!
2838 %}
2839
2840
2841 enc_class enc_String_Compare(o0RegP str1, o1RegP str2, g3RegP tmp1, g4RegP tmp2, notemp_iRegI result) %{
2842 Label Ldone, Lloop;
2843 MacroAssembler _masm(&cbuf);
2844
2845 Register str1_reg = reg_to_register_object($str1$$reg);
2846 Register str2_reg = reg_to_register_object($str2$$reg);
2847 Register tmp1_reg = reg_to_register_object($tmp1$$reg);
2848 Register tmp2_reg = reg_to_register_object($tmp2$$reg);
2849 Register result_reg = reg_to_register_object($result$$reg);
2850
2851 // Get the first character position in both strings
2852 // [8] char array, [12] offset, [16] count
2853 int value_offset = java_lang_String:: value_offset_in_bytes();
2854 int offset_offset = java_lang_String::offset_offset_in_bytes();
2855 int count_offset = java_lang_String:: count_offset_in_bytes();
2856
2857 // load str1 (jchar*) base address into tmp1_reg
2858 __ load_heap_oop(str1_reg, value_offset, tmp1_reg);
2859 __ ld(str1_reg, offset_offset, result_reg);
2860 __ add(tmp1_reg, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp1_reg);
2861 __ ld(str1_reg, count_offset, str1_reg); // hoisted
2862 __ sll(result_reg, exact_log2(sizeof(jchar)), result_reg);
2863 __ load_heap_oop(str2_reg, value_offset, tmp2_reg); // hoisted
2864 __ add(result_reg, tmp1_reg, tmp1_reg);
2865
2866 // load str2 (jchar*) base address into tmp2_reg
2867 // __ ld_ptr(str2_reg, value_offset, tmp2_reg); // hoisted
2868 __ ld(str2_reg, offset_offset, result_reg);
2869 __ add(tmp2_reg, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp2_reg);
2870 __ ld(str2_reg, count_offset, str2_reg); // hoisted
2871 __ sll(result_reg, exact_log2(sizeof(jchar)), result_reg);
2872 __ subcc(str1_reg, str2_reg, O7); // hoisted
2873 __ add(result_reg, tmp2_reg, tmp2_reg);
2874
2875 // Compute the minimum of the string lengths(str1_reg) and the
2876 // difference of the string lengths (stack)
2877
2878 // discard string base pointers, after loading up the lengths
2879 // __ ld(str1_reg, count_offset, str1_reg); // hoisted
2880 // __ ld(str2_reg, count_offset, str2_reg); // hoisted
2881
2882 // See if the lengths are different, and calculate min in str1_reg.
2883 // Stash diff in O7 in case we need it for a tie-breaker.
2884 Label Lskip;
2885 // __ subcc(str1_reg, str2_reg, O7); // hoisted
2886 __ sll(str1_reg, exact_log2(sizeof(jchar)), str1_reg); // scale the limit
2887 __ br(Assembler::greater, true, Assembler::pt, Lskip);
2888 // str2 is shorter, so use its count:
2889 __ delayed()->sll(str2_reg, exact_log2(sizeof(jchar)), str1_reg); // scale the limit
2890 __ bind(Lskip);
2891
2892 // reallocate str1_reg, str2_reg, result_reg
2893 // Note: limit_reg holds the string length pre-scaled by 2
2894 Register limit_reg = str1_reg;
2895 Register chr2_reg = str2_reg;
2896 Register chr1_reg = result_reg;
2897 // tmp{12} are the base pointers
2898
2899 // Is the minimum length zero?
2900 __ cmp(limit_reg, (int)(0 * sizeof(jchar))); // use cast to resolve overloading ambiguity
2901 __ br(Assembler::equal, true, Assembler::pn, Ldone);
2902 __ delayed()->mov(O7, result_reg); // result is difference in lengths
2903
2904 // Load first characters
2905 __ lduh(tmp1_reg, 0, chr1_reg);
2906 __ lduh(tmp2_reg, 0, chr2_reg);
2907
2908 // Compare first characters
2909 __ subcc(chr1_reg, chr2_reg, chr1_reg);
2910 __ br(Assembler::notZero, false, Assembler::pt, Ldone);
2911 assert(chr1_reg == result_reg, "result must be pre-placed");
2912 __ delayed()->nop();
2913
2914 {
2915 // Check after comparing first character to see if strings are equivalent
2916 Label LSkip2;
2917 // Check if the strings start at same location
2918 __ cmp(tmp1_reg, tmp2_reg);
2919 __ brx(Assembler::notEqual, true, Assembler::pt, LSkip2);
2920 __ delayed()->nop();
2921
2922 // Check if the length difference is zero (in O7)
2923 __ cmp(G0, O7);
2924 __ br(Assembler::equal, true, Assembler::pn, Ldone);
2925 __ delayed()->mov(G0, result_reg); // result is zero
2926
2927 // Strings might not be equal
2928 __ bind(LSkip2);
2929 }
2930
2931 __ subcc(limit_reg, 1 * sizeof(jchar), chr1_reg);
2932 __ br(Assembler::equal, true, Assembler::pn, Ldone);
2933 __ delayed()->mov(O7, result_reg); // result is difference in lengths
2934
2935 // Shift tmp1_reg and tmp2_reg to the end of the arrays, negate limit
2936 __ add(tmp1_reg, limit_reg, tmp1_reg);
2937 __ add(tmp2_reg, limit_reg, tmp2_reg);
2938 __ neg(chr1_reg, limit_reg); // limit = -(limit-2)
2939
2940 // Compare the rest of the characters
2941 __ lduh(tmp1_reg, limit_reg, chr1_reg);
2942 __ bind(Lloop);
2943 // __ lduh(tmp1_reg, limit_reg, chr1_reg); // hoisted
2944 __ lduh(tmp2_reg, limit_reg, chr2_reg);
2945 __ subcc(chr1_reg, chr2_reg, chr1_reg);
2946 __ br(Assembler::notZero, false, Assembler::pt, Ldone);
2947 assert(chr1_reg == result_reg, "result must be pre-placed");
2948 __ delayed()->inccc(limit_reg, sizeof(jchar));
2949 // annul LDUH if branch is not taken to prevent access past end of string
2950 __ br(Assembler::notZero, true, Assembler::pt, Lloop);
2951 __ delayed()->lduh(tmp1_reg, limit_reg, chr1_reg); // hoisted
2952
2953 // If strings are equal up to min length, return the length difference.
2954 __ mov(O7, result_reg);
2955
2956 // Otherwise, return the difference between the first mismatched chars.
2957 __ bind(Ldone);
2958 %}
2959
2960 enc_class enc_String_Equals(o0RegP str1, o1RegP str2, g3RegP tmp1, g4RegP tmp2, notemp_iRegI result) %{
2961 Label Lword, Lword_loop, Lpost_word, Lchar, Lchar_loop, Ldone;
2962 MacroAssembler _masm(&cbuf);
2963
2964 Register str1_reg = reg_to_register_object($str1$$reg);
2965 Register str2_reg = reg_to_register_object($str2$$reg);
2966 Register tmp1_reg = reg_to_register_object($tmp1$$reg);
2967 Register tmp2_reg = reg_to_register_object($tmp2$$reg);
2968 Register result_reg = reg_to_register_object($result$$reg);
2969
2970 // Get the first character position in both strings
2971 // [8] char array, [12] offset, [16] count
2972 int value_offset = java_lang_String:: value_offset_in_bytes();
2973 int offset_offset = java_lang_String::offset_offset_in_bytes();
2974 int count_offset = java_lang_String:: count_offset_in_bytes();
2975
2976 // load str1 (jchar*) base address into tmp1_reg
2977 __ load_heap_oop(Address(str1_reg, value_offset), tmp1_reg);
2978 __ ld(Address(str1_reg, offset_offset), result_reg);
2979 __ add(tmp1_reg, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp1_reg);
2980 __ ld(Address(str1_reg, count_offset), str1_reg); // hoisted
2981 __ sll(result_reg, exact_log2(sizeof(jchar)), result_reg);
2982 __ load_heap_oop(Address(str2_reg, value_offset), tmp2_reg); // hoisted
2983 __ add(result_reg, tmp1_reg, tmp1_reg);
2984
2985 // load str2 (jchar*) base address into tmp2_reg
2986 // __ ld_ptr(Address(str2_reg, value_offset), tmp2_reg); // hoisted
2987 __ ld(Address(str2_reg, offset_offset), result_reg);
2988 __ add(tmp2_reg, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp2_reg);
2989 __ ld(Address(str2_reg, count_offset), str2_reg); // hoisted
2990 __ sll(result_reg, exact_log2(sizeof(jchar)), result_reg);
2991 __ cmp(str1_reg, str2_reg); // hoisted
2992 __ add(result_reg, tmp2_reg, tmp2_reg);
2993
2994 __ sll(str1_reg, exact_log2(sizeof(jchar)), str1_reg);
2995 __ br(Assembler::notEqual, true, Assembler::pt, Ldone);
2996 __ delayed()->mov(G0, result_reg); // not equal
2997
2998 __ br_zero(Assembler::equal, true, Assembler::pn, str1_reg, Ldone);
2999 __ delayed()->add(G0, 1, result_reg); //equals
3000
3001 __ cmp(tmp1_reg, tmp2_reg); //same string ?
3002 __ brx(Assembler::equal, true, Assembler::pn, Ldone);
3003 __ delayed()->add(G0, 1, result_reg);
3004
3005 //rename registers
3006 Register limit_reg = str1_reg;
3007 Register chr2_reg = str2_reg;
3008 Register chr1_reg = result_reg;
3009 // tmp{12} are the base pointers
3010
3011 //check for alignment and position the pointers to the ends
3012 __ or3(tmp1_reg, tmp2_reg, chr1_reg);
3013 __ andcc(chr1_reg, 0x3, chr1_reg); // notZero means at least one not 4-byte aligned
3014 __ br(Assembler::notZero, false, Assembler::pn, Lchar);
3015 __ delayed()->nop();
3016
3017 __ bind(Lword);
3018 __ and3(limit_reg, 0x2, O7); //remember the remainder (either 0 or 2)
3019 __ andn(limit_reg, 0x3, limit_reg);
3020 __ br_zero(Assembler::zero, false, Assembler::pn, limit_reg, Lpost_word);
3021 __ delayed()->nop();
3022
3023 __ add(tmp1_reg, limit_reg, tmp1_reg);
3024 __ add(tmp2_reg, limit_reg, tmp2_reg);
3025 __ neg(limit_reg);
3026
3027 __ lduw(tmp1_reg, limit_reg, chr1_reg);
3028 __ bind(Lword_loop);
3029 __ lduw(tmp2_reg, limit_reg, chr2_reg);
3030 __ cmp(chr1_reg, chr2_reg);
3031 __ br(Assembler::notEqual, true, Assembler::pt, Ldone);
3032 __ delayed()->mov(G0, result_reg);
3033 __ inccc(limit_reg, 2*sizeof(jchar));
3034 // annul LDUW if branch i s not taken to prevent access past end of string
3035 __ br(Assembler::notZero, true, Assembler::pt, Lword_loop); //annul on taken
3036 __ delayed()->lduw(tmp1_reg, limit_reg, chr1_reg); // hoisted
3037
3038 __ bind(Lpost_word);
3039 __ br_zero(Assembler::zero, true, Assembler::pt, O7, Ldone);
3040 __ delayed()->add(G0, 1, result_reg);
3041
3042 __ lduh(tmp1_reg, 0, chr1_reg);
3043 __ lduh(tmp2_reg, 0, chr2_reg);
3044 __ cmp (chr1_reg, chr2_reg);
3045 __ br(Assembler::notEqual, true, Assembler::pt, Ldone);
3046 __ delayed()->mov(G0, result_reg);
3047 __ ba(false,Ldone);
3048 __ delayed()->add(G0, 1, result_reg);
3049
3050 __ bind(Lchar);
3051 __ add(tmp1_reg, limit_reg, tmp1_reg);
3052 __ add(tmp2_reg, limit_reg, tmp2_reg);
3053 __ neg(limit_reg); //negate count
3054
3055 __ lduh(tmp1_reg, limit_reg, chr1_reg);
3056 __ bind(Lchar_loop);
3057 __ lduh(tmp2_reg, limit_reg, chr2_reg);
3058 __ cmp(chr1_reg, chr2_reg);
3059 __ br(Assembler::notEqual, true, Assembler::pt, Ldone);
3060 __ delayed()->mov(G0, result_reg); //not equal
3061 __ inccc(limit_reg, sizeof(jchar));
3062 // annul LDUH if branch is not taken to prevent access past end of string
3063 __ br(Assembler::notZero, true, Assembler::pt, Lchar_loop); //annul on taken
3064 __ delayed()->lduh(tmp1_reg, limit_reg, chr1_reg); // hoisted
3065
3066 __ add(G0, 1, result_reg); //equal
3067
3068 __ bind(Ldone);
3069 %}
3070
3071 enc_class enc_Array_Equals(o0RegP ary1, o1RegP ary2, g3RegP tmp1, g4RegP tmp2, notemp_iRegI result) %{
3072 Label Lvector, Ldone, Lloop;
3073 MacroAssembler _masm(&cbuf);
3074
3075 Register ary1_reg = reg_to_register_object($ary1$$reg);
3076 Register ary2_reg = reg_to_register_object($ary2$$reg);
3077 Register tmp1_reg = reg_to_register_object($tmp1$$reg);
3078 Register tmp2_reg = reg_to_register_object($tmp2$$reg);
3079 Register result_reg = reg_to_register_object($result$$reg);
3080
3081 int length_offset = arrayOopDesc::length_offset_in_bytes();
3082 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR);
3083
3084 // return true if the same array
3085 __ cmp(ary1_reg, ary2_reg);
3086 __ br(Assembler::equal, true, Assembler::pn, Ldone);
3087 __ delayed()->add(G0, 1, result_reg); // equal
3088
3089 __ br_null(ary1_reg, true, Assembler::pn, Ldone);
3090 __ delayed()->mov(G0, result_reg); // not equal
3091
3092 __ br_null(ary2_reg, true, Assembler::pn, Ldone);
3093 __ delayed()->mov(G0, result_reg); // not equal
3094
3095 //load the lengths of arrays
3096 __ ld(Address(ary1_reg, length_offset), tmp1_reg);
3097 __ ld(Address(ary2_reg, length_offset), tmp2_reg);
3098
3099 // return false if the two arrays are not equal length
3100 __ cmp(tmp1_reg, tmp2_reg);
3101 __ br(Assembler::notEqual, true, Assembler::pn, Ldone);
3102 __ delayed()->mov(G0, result_reg); // not equal
3103
3104 __ br_zero(Assembler::zero, true, Assembler::pn, tmp1_reg, Ldone);
3105 __ delayed()->add(G0, 1, result_reg); // zero-length arrays are equal
3106
3107 // load array addresses
3108 __ add(ary1_reg, base_offset, ary1_reg);
3109 __ add(ary2_reg, base_offset, ary2_reg);
3110
3111 // renaming registers
3112 Register chr1_reg = tmp2_reg; // for characters in ary1
3113 Register chr2_reg = result_reg; // for characters in ary2
3114 Register limit_reg = tmp1_reg; // length
3115
3116 // set byte count
3117 __ sll(limit_reg, exact_log2(sizeof(jchar)), limit_reg);
3118 __ andcc(limit_reg, 0x2, chr1_reg); //trailing character ?
3119 __ br(Assembler::zero, false, Assembler::pt, Lvector);
3120 __ delayed()->nop();
3121
3122 //compare the trailing char
3123 __ sub(limit_reg, sizeof(jchar), limit_reg);
3124 __ lduh(ary1_reg, limit_reg, chr1_reg);
3125 __ lduh(ary2_reg, limit_reg, chr2_reg);
3126 __ cmp(chr1_reg, chr2_reg);
3127 __ br(Assembler::notEqual, true, Assembler::pt, Ldone);
3128 __ delayed()->mov(G0, result_reg); // not equal
3129
3130 // only one char ?
3131 __ br_zero(Assembler::zero, true, Assembler::pn, limit_reg, Ldone);
3132 __ delayed()->add(G0, 1, result_reg); // zero-length arrays are equal
3133
3134 __ bind(Lvector);
3135 // Shift ary1_reg and ary2_reg to the end of the arrays, negate limit
3136 __ add(ary1_reg, limit_reg, ary1_reg);
3137 __ add(ary2_reg, limit_reg, ary2_reg);
3138 __ neg(limit_reg, limit_reg);
3139
3140 __ lduw(ary1_reg, limit_reg, chr1_reg);
3141 __ bind(Lloop);
3142 __ lduw(ary2_reg, limit_reg, chr2_reg);
3143 __ cmp(chr1_reg, chr2_reg);
3144 __ br(Assembler::notEqual, false, Assembler::pt, Ldone);
3145 __ delayed()->mov(G0, result_reg); // not equal
3146 __ inccc(limit_reg, 2*sizeof(jchar));
3147 // annul LDUW if branch is not taken to prevent access past end of string
3148 __ br(Assembler::notZero, true, Assembler::pt, Lloop); //annul on taken
3149 __ delayed()->lduw(ary1_reg, limit_reg, chr1_reg); // hoisted
3150
3151 __ add(G0, 1, result_reg); // equals
3152
3153 __ bind(Ldone);
3154 %}
3155
3156 enc_class enc_rethrow() %{
3157 cbuf.set_inst_mark();
3158 Register temp_reg = G3;
3159 AddressLiteral rethrow_stub(OptoRuntime::rethrow_stub());
3160 assert(temp_reg != reg_to_register_object(R_I0_num), "temp must not break oop_reg");
3161 MacroAssembler _masm(&cbuf);
3162 #ifdef ASSERT
3163 __ save_frame(0);
3164 AddressLiteral last_rethrow_addrlit(&last_rethrow);
3165 __ sethi(last_rethrow_addrlit, L1);
3166 Address addr(L1, last_rethrow_addrlit.low10());
3167 __ get_pc(L2);
3168 __ inc(L2, 3 * BytesPerInstWord); // skip this & 2 more insns to point at jump_to
3169 __ st_ptr(L2, addr);
3170 __ restore();
3171 #endif
3172 __ JUMP(rethrow_stub, temp_reg, 0); // sethi;jmp
3173 __ delayed()->nop();
3174 %}
3175
3176 enc_class emit_mem_nop() %{
3177 // Generates the instruction LDUXA [o6,g0],#0x82,g0
3178 unsigned int *code = (unsigned int*)cbuf.code_end();
3179 *code = (unsigned int)0xc0839040;
3180 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
3181 %}
3182
3183 enc_class emit_fadd_nop() %{
3184 // Generates the instruction FMOVS f31,f31
3185 unsigned int *code = (unsigned int*)cbuf.code_end();
3186 *code = (unsigned int)0xbfa0003f;
3187 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
3188 %}
3189
3190 enc_class emit_br_nop() %{
3191 // Generates the instruction BPN,PN .
3192 unsigned int *code = (unsigned int*)cbuf.code_end();
3193 *code = (unsigned int)0x00400000;
3194 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
3195 %}
3196
3197 enc_class enc_membar_acquire %{
3198 MacroAssembler _masm(&cbuf);
3199 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::LoadLoad) );
3200 %}
3201
3202 enc_class enc_membar_release %{
3203 MacroAssembler _masm(&cbuf);
3204 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::StoreStore) );
3205 %}
3206
3207 enc_class enc_membar_volatile %{
3208 MacroAssembler _masm(&cbuf);
3209 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad) );
3210 %}
3211
3212 enc_class enc_repl8b( iRegI src, iRegL dst ) %{
3213 MacroAssembler _masm(&cbuf);
3214 Register src_reg = reg_to_register_object($src$$reg);
3215 Register dst_reg = reg_to_register_object($dst$$reg);
3216 __ sllx(src_reg, 56, dst_reg);
3217 __ srlx(dst_reg, 8, O7);
3218 __ or3 (dst_reg, O7, dst_reg);
3219 __ srlx(dst_reg, 16, O7);
3220 __ or3 (dst_reg, O7, dst_reg);
3221 __ srlx(dst_reg, 32, O7);
3222 __ or3 (dst_reg, O7, dst_reg);
3223 %}
3224
3225 enc_class enc_repl4b( iRegI src, iRegL dst ) %{
3226 MacroAssembler _masm(&cbuf);
3227 Register src_reg = reg_to_register_object($src$$reg);
3228 Register dst_reg = reg_to_register_object($dst$$reg);
3229 __ sll(src_reg, 24, dst_reg);
3230 __ srl(dst_reg, 8, O7);
3231 __ or3(dst_reg, O7, dst_reg);
3232 __ srl(dst_reg, 16, O7);
3233 __ or3(dst_reg, O7, dst_reg);
3234 %}
3235
3236 enc_class enc_repl4s( iRegI src, iRegL dst ) %{
3237 MacroAssembler _masm(&cbuf);
3238 Register src_reg = reg_to_register_object($src$$reg);
3239 Register dst_reg = reg_to_register_object($dst$$reg);
3240 __ sllx(src_reg, 48, dst_reg);
3241 __ srlx(dst_reg, 16, O7);
3242 __ or3 (dst_reg, O7, dst_reg);
3243 __ srlx(dst_reg, 32, O7);
3244 __ or3 (dst_reg, O7, dst_reg);
3245 %}
3246
3247 enc_class enc_repl2i( iRegI src, iRegL dst ) %{
3248 MacroAssembler _masm(&cbuf);
3249 Register src_reg = reg_to_register_object($src$$reg);
3250 Register dst_reg = reg_to_register_object($dst$$reg);
3251 __ sllx(src_reg, 32, dst_reg);
3252 __ srlx(dst_reg, 32, O7);
3253 __ or3 (dst_reg, O7, dst_reg);
3254 %}
3255
3256 %}
3257
3258 //----------FRAME--------------------------------------------------------------
3259 // Definition of frame structure and management information.
3260 //
3261 // S T A C K L A Y O U T Allocators stack-slot number
3262 // | (to get allocators register number
3263 // G Owned by | | v add VMRegImpl::stack0)
3264 // r CALLER | |
3265 // o | +--------+ pad to even-align allocators stack-slot
3266 // w V | pad0 | numbers; owned by CALLER
3267 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
3268 // h ^ | in | 5
3269 // | | args | 4 Holes in incoming args owned by SELF
3270 // | | | | 3
3271 // | | +--------+
3272 // V | | old out| Empty on Intel, window on Sparc
3273 // | old |preserve| Must be even aligned.
3274 // | SP-+--------+----> Matcher::_old_SP, 8 (or 16 in LP64)-byte aligned
3275 // | | in | 3 area for Intel ret address
3276 // Owned by |preserve| Empty on Sparc.
3277 // SELF +--------+
3278 // | | pad2 | 2 pad to align old SP
3279 // | +--------+ 1
3280 // | | locks | 0
3281 // | +--------+----> VMRegImpl::stack0, 8 (or 16 in LP64)-byte aligned
3282 // | | pad1 | 11 pad to align new SP
3283 // | +--------+
3284 // | | | 10
3285 // | | spills | 9 spills
3286 // V | | 8 (pad0 slot for callee)
3287 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
3288 // ^ | out | 7
3289 // | | args | 6 Holes in outgoing args owned by CALLEE
3290 // Owned by +--------+
3291 // CALLEE | new out| 6 Empty on Intel, window on Sparc
3292 // | new |preserve| Must be even-aligned.
3293 // | SP-+--------+----> Matcher::_new_SP, even aligned
3294 // | | |
3295 //
3296 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
3297 // known from SELF's arguments and the Java calling convention.
3298 // Region 6-7 is determined per call site.
3299 // Note 2: If the calling convention leaves holes in the incoming argument
3300 // area, those holes are owned by SELF. Holes in the outgoing area
3301 // are owned by the CALLEE. Holes should not be nessecary in the
3302 // incoming area, as the Java calling convention is completely under
3303 // the control of the AD file. Doubles can be sorted and packed to
3304 // avoid holes. Holes in the outgoing arguments may be nessecary for
3305 // varargs C calling conventions.
3306 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
3307 // even aligned with pad0 as needed.
3308 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
3309 // region 6-11 is even aligned; it may be padded out more so that
3310 // the region from SP to FP meets the minimum stack alignment.
3311
3312 frame %{
3313 // What direction does stack grow in (assumed to be same for native & Java)
3314 stack_direction(TOWARDS_LOW);
3315
3316 // These two registers define part of the calling convention
3317 // between compiled code and the interpreter.
3318 inline_cache_reg(R_G5); // Inline Cache Register or methodOop for I2C
3319 interpreter_method_oop_reg(R_G5); // Method Oop Register when calling interpreter
3320
3321 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
3322 cisc_spilling_operand_name(indOffset);
3323
3324 // Number of stack slots consumed by a Monitor enter
3325 #ifdef _LP64
3326 sync_stack_slots(2);
3327 #else
3328 sync_stack_slots(1);
3329 #endif
3330
3331 // Compiled code's Frame Pointer
3332 frame_pointer(R_SP);
3333
3334 // Stack alignment requirement
3335 stack_alignment(StackAlignmentInBytes);
3336 // LP64: Alignment size in bytes (128-bit -> 16 bytes)
3337 // !LP64: Alignment size in bytes (64-bit -> 8 bytes)
3338
3339 // Number of stack slots between incoming argument block and the start of
3340 // a new frame. The PROLOG must add this many slots to the stack. The
3341 // EPILOG must remove this many slots.
3342 in_preserve_stack_slots(0);
3343
3344 // Number of outgoing stack slots killed above the out_preserve_stack_slots
3345 // for calls to C. Supports the var-args backing area for register parms.
3346 // ADLC doesn't support parsing expressions, so I folded the math by hand.
3347 #ifdef _LP64
3348 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (0)) * 2-stack-slots-per-word
3349 varargs_C_out_slots_killed(12);
3350 #else
3351 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (1)) * 1-stack-slots-per-word
3352 varargs_C_out_slots_killed( 7);
3353 #endif
3354
3355 // The after-PROLOG location of the return address. Location of
3356 // return address specifies a type (REG or STACK) and a number
3357 // representing the register number (i.e. - use a register name) or
3358 // stack slot.
3359 return_addr(REG R_I7); // Ret Addr is in register I7
3360
3361 // Body of function which returns an OptoRegs array locating
3362 // arguments either in registers or in stack slots for calling
3363 // java
3364 calling_convention %{
3365 (void) SharedRuntime::java_calling_convention(sig_bt, regs, length, is_outgoing);
3366
3367 %}
3368
3369 // Body of function which returns an OptoRegs array locating
3370 // arguments either in registers or in stack slots for callin
3371 // C.
3372 c_calling_convention %{
3373 // This is obviously always outgoing
3374 (void) SharedRuntime::c_calling_convention(sig_bt, regs, length);
3375 %}
3376
3377 // Location of native (C/C++) and interpreter return values. This is specified to
3378 // be the same as Java. In the 32-bit VM, long values are actually returned from
3379 // native calls in O0:O1 and returned to the interpreter in I0:I1. The copying
3380 // to and from the register pairs is done by the appropriate call and epilog
3381 // opcodes. This simplifies the register allocator.
3382 c_return_value %{
3383 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3384 #ifdef _LP64
3385 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num };
3386 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num};
3387 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num };
3388 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num};
3389 #else // !_LP64
3390 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num };
3391 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num };
3392 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num };
3393 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num };
3394 #endif
3395 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg],
3396 (is_outgoing?lo_out:lo_in)[ideal_reg] );
3397 %}
3398
3399 // Location of compiled Java return values. Same as C
3400 return_value %{
3401 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3402 #ifdef _LP64
3403 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num };
3404 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num};
3405 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num };
3406 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num};
3407 #else // !_LP64
3408 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num };
3409 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num};
3410 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num };
3411 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num};
3412 #endif
3413 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg],
3414 (is_outgoing?lo_out:lo_in)[ideal_reg] );
3415 %}
3416
3417 %}
3418
3419
3420 //----------ATTRIBUTES---------------------------------------------------------
3421 //----------Operand Attributes-------------------------------------------------
3422 op_attrib op_cost(1); // Required cost attribute
3423
3424 //----------Instruction Attributes---------------------------------------------
3425 ins_attrib ins_cost(DEFAULT_COST); // Required cost attribute
3426 ins_attrib ins_size(32); // Required size attribute (in bits)
3427 ins_attrib ins_pc_relative(0); // Required PC Relative flag
3428 ins_attrib ins_short_branch(0); // Required flag: is this instruction a
3429 // non-matching short branch variant of some
3430 // long branch?
3431
3432 //----------OPERANDS-----------------------------------------------------------
3433 // Operand definitions must precede instruction definitions for correct parsing
3434 // in the ADLC because operands constitute user defined types which are used in
3435 // instruction definitions.
3436
3437 //----------Simple Operands----------------------------------------------------
3438 // Immediate Operands
3439 // Integer Immediate: 32-bit
3440 operand immI() %{
3441 match(ConI);
3442
3443 op_cost(0);
3444 // formats are generated automatically for constants and base registers
3445 format %{ %}
3446 interface(CONST_INTER);
3447 %}
3448
3449 // Integer Immediate: 13-bit
3450 operand immI13() %{
3451 predicate(Assembler::is_simm13(n->get_int()));
3452 match(ConI);
3453 op_cost(0);
3454
3455 format %{ %}
3456 interface(CONST_INTER);
3457 %}
3458
3459 // Integer Immediate: 13-bit minus 7
3460 operand immI13m7() %{
3461 predicate(Assembler::is_simm13(n->get_int() + 7));
3462 match(ConI);
3463 op_cost(0);
3464
3465 format %{ %}
3466 interface(CONST_INTER);
3467 %}
3468
3469 // Unsigned (positive) Integer Immediate: 13-bit
3470 operand immU13() %{
3471 predicate((0 <= n->get_int()) && Assembler::is_simm13(n->get_int()));
3472 match(ConI);
3473 op_cost(0);
3474
3475 format %{ %}
3476 interface(CONST_INTER);
3477 %}
3478
3479 // Integer Immediate: 6-bit
3480 operand immU6() %{
3481 predicate(n->get_int() >= 0 && n->get_int() <= 63);
3482 match(ConI);
3483 op_cost(0);
3484 format %{ %}
3485 interface(CONST_INTER);
3486 %}
3487
3488 // Integer Immediate: 11-bit
3489 operand immI11() %{
3490 predicate(Assembler::is_simm(n->get_int(),11));
3491 match(ConI);
3492 op_cost(0);
3493 format %{ %}
3494 interface(CONST_INTER);
3495 %}
3496
3497 // Integer Immediate: 0-bit
3498 operand immI0() %{
3499 predicate(n->get_int() == 0);
3500 match(ConI);
3501 op_cost(0);
3502
3503 format %{ %}
3504 interface(CONST_INTER);
3505 %}
3506
3507 // Integer Immediate: the value 10
3508 operand immI10() %{
3509 predicate(n->get_int() == 10);
3510 match(ConI);
3511 op_cost(0);
3512
3513 format %{ %}
3514 interface(CONST_INTER);
3515 %}
3516
3517 // Integer Immediate: the values 0-31
3518 operand immU5() %{
3519 predicate(n->get_int() >= 0 && n->get_int() <= 31);
3520 match(ConI);
3521 op_cost(0);
3522
3523 format %{ %}
3524 interface(CONST_INTER);
3525 %}
3526
3527 // Integer Immediate: the values 1-31
3528 operand immI_1_31() %{
3529 predicate(n->get_int() >= 1 && n->get_int() <= 31);
3530 match(ConI);
3531 op_cost(0);
3532
3533 format %{ %}
3534 interface(CONST_INTER);
3535 %}
3536
3537 // Integer Immediate: the values 32-63
3538 operand immI_32_63() %{
3539 predicate(n->get_int() >= 32 && n->get_int() <= 63);
3540 match(ConI);
3541 op_cost(0);
3542
3543 format %{ %}
3544 interface(CONST_INTER);
3545 %}
3546
3547 // Immediates for special shifts (sign extend)
3548
3549 // Integer Immediate: the value 16
3550 operand immI_16() %{
3551 predicate(n->get_int() == 16);
3552 match(ConI);
3553 op_cost(0);
3554
3555 format %{ %}
3556 interface(CONST_INTER);
3557 %}
3558
3559 // Integer Immediate: the value 24
3560 operand immI_24() %{
3561 predicate(n->get_int() == 24);
3562 match(ConI);
3563 op_cost(0);
3564
3565 format %{ %}
3566 interface(CONST_INTER);
3567 %}
3568
3569 // Integer Immediate: the value 255
3570 operand immI_255() %{
3571 predicate( n->get_int() == 255 );
3572 match(ConI);
3573 op_cost(0);
3574
3575 format %{ %}
3576 interface(CONST_INTER);
3577 %}
3578
3579 // Integer Immediate: the value 65535
3580 operand immI_65535() %{
3581 predicate(n->get_int() == 65535);
3582 match(ConI);
3583 op_cost(0);
3584
3585 format %{ %}
3586 interface(CONST_INTER);
3587 %}
3588
3589 // Long Immediate: the value FF
3590 operand immL_FF() %{
3591 predicate( n->get_long() == 0xFFL );
3592 match(ConL);
3593 op_cost(0);
3594
3595 format %{ %}
3596 interface(CONST_INTER);
3597 %}
3598
3599 // Long Immediate: the value FFFF
3600 operand immL_FFFF() %{
3601 predicate( n->get_long() == 0xFFFFL );
3602 match(ConL);
3603 op_cost(0);
3604
3605 format %{ %}
3606 interface(CONST_INTER);
3607 %}
3608
3609 // Pointer Immediate: 32 or 64-bit
3610 operand immP() %{
3611 match(ConP);
3612
3613 op_cost(5);
3614 // formats are generated automatically for constants and base registers
3615 format %{ %}
3616 interface(CONST_INTER);
3617 %}
3618
3619 operand immP13() %{
3620 predicate((-4096 < n->get_ptr()) && (n->get_ptr() <= 4095));
3621 match(ConP);
3622 op_cost(0);
3623
3624 format %{ %}
3625 interface(CONST_INTER);
3626 %}
3627
3628 operand immP0() %{
3629 predicate(n->get_ptr() == 0);
3630 match(ConP);
3631 op_cost(0);
3632
3633 format %{ %}
3634 interface(CONST_INTER);
3635 %}
3636
3637 operand immP_poll() %{
3638 predicate(n->get_ptr() != 0 && n->get_ptr() == (intptr_t)os::get_polling_page());
3639 match(ConP);
3640
3641 // formats are generated automatically for constants and base registers
3642 format %{ %}
3643 interface(CONST_INTER);
3644 %}
3645
3646 // Pointer Immediate
3647 operand immN()
3648 %{
3649 match(ConN);
3650
3651 op_cost(10);
3652 format %{ %}
3653 interface(CONST_INTER);
3654 %}
3655
3656 // NULL Pointer Immediate
3657 operand immN0()
3658 %{
3659 predicate(n->get_narrowcon() == 0);
3660 match(ConN);
3661
3662 op_cost(0);
3663 format %{ %}
3664 interface(CONST_INTER);
3665 %}
3666
3667 operand immL() %{
3668 match(ConL);
3669 op_cost(40);
3670 // formats are generated automatically for constants and base registers
3671 format %{ %}
3672 interface(CONST_INTER);
3673 %}
3674
3675 operand immL0() %{
3676 predicate(n->get_long() == 0L);
3677 match(ConL);
3678 op_cost(0);
3679 // formats are generated automatically for constants and base registers
3680 format %{ %}
3681 interface(CONST_INTER);
3682 %}
3683
3684 // Long Immediate: 13-bit
3685 operand immL13() %{
3686 predicate((-4096L < n->get_long()) && (n->get_long() <= 4095L));
3687 match(ConL);
3688 op_cost(0);
3689
3690 format %{ %}
3691 interface(CONST_INTER);
3692 %}
3693
3694 // Long Immediate: 13-bit minus 7
3695 operand immL13m7() %{
3696 predicate((-4096L < (n->get_long() + 7L)) && ((n->get_long() + 7L) <= 4095L));
3697 match(ConL);
3698 op_cost(0);
3699
3700 format %{ %}
3701 interface(CONST_INTER);
3702 %}
3703
3704 // Long Immediate: low 32-bit mask
3705 operand immL_32bits() %{
3706 predicate(n->get_long() == 0xFFFFFFFFL);
3707 match(ConL);
3708 op_cost(0);
3709
3710 format %{ %}
3711 interface(CONST_INTER);
3712 %}
3713
3714 // Double Immediate
3715 operand immD() %{
3716 match(ConD);
3717
3718 op_cost(40);
3719 format %{ %}
3720 interface(CONST_INTER);
3721 %}
3722
3723 operand immD0() %{
3724 #ifdef _LP64
3725 // on 64-bit architectures this comparision is faster
3726 predicate(jlong_cast(n->getd()) == 0);
3727 #else
3728 predicate((n->getd() == 0) && (fpclass(n->getd()) == FP_PZERO));
3729 #endif
3730 match(ConD);
3731
3732 op_cost(0);
3733 format %{ %}
3734 interface(CONST_INTER);
3735 %}
3736
3737 // Float Immediate
3738 operand immF() %{
3739 match(ConF);
3740
3741 op_cost(20);
3742 format %{ %}
3743 interface(CONST_INTER);
3744 %}
3745
3746 // Float Immediate: 0
3747 operand immF0() %{
3748 predicate((n->getf() == 0) && (fpclass(n->getf()) == FP_PZERO));
3749 match(ConF);
3750
3751 op_cost(0);
3752 format %{ %}
3753 interface(CONST_INTER);
3754 %}
3755
3756 // Integer Register Operands
3757 // Integer Register
3758 operand iRegI() %{
3759 constraint(ALLOC_IN_RC(int_reg));
3760 match(RegI);
3761
3762 match(notemp_iRegI);
3763 match(g1RegI);
3764 match(o0RegI);
3765 match(iRegIsafe);
3766
3767 format %{ %}
3768 interface(REG_INTER);
3769 %}
3770
3771 operand notemp_iRegI() %{
3772 constraint(ALLOC_IN_RC(notemp_int_reg));
3773 match(RegI);
3774
3775 match(o0RegI);
3776
3777 format %{ %}
3778 interface(REG_INTER);
3779 %}
3780
3781 operand o0RegI() %{
3782 constraint(ALLOC_IN_RC(o0_regI));
3783 match(iRegI);
3784
3785 format %{ %}
3786 interface(REG_INTER);
3787 %}
3788
3789 // Pointer Register
3790 operand iRegP() %{
3791 constraint(ALLOC_IN_RC(ptr_reg));
3792 match(RegP);
3793
3794 match(lock_ptr_RegP);
3795 match(g1RegP);
3796 match(g2RegP);
3797 match(g3RegP);
3798 match(g4RegP);
3799 match(i0RegP);
3800 match(o0RegP);
3801 match(o1RegP);
3802 match(l7RegP);
3803
3804 format %{ %}
3805 interface(REG_INTER);
3806 %}
3807
3808 operand sp_ptr_RegP() %{
3809 constraint(ALLOC_IN_RC(sp_ptr_reg));
3810 match(RegP);
3811 match(iRegP);
3812
3813 format %{ %}
3814 interface(REG_INTER);
3815 %}
3816
3817 operand lock_ptr_RegP() %{
3818 constraint(ALLOC_IN_RC(lock_ptr_reg));
3819 match(RegP);
3820 match(i0RegP);
3821 match(o0RegP);
3822 match(o1RegP);
3823 match(l7RegP);
3824
3825 format %{ %}
3826 interface(REG_INTER);
3827 %}
3828
3829 operand g1RegP() %{
3830 constraint(ALLOC_IN_RC(g1_regP));
3831 match(iRegP);
3832
3833 format %{ %}
3834 interface(REG_INTER);
3835 %}
3836
3837 operand g2RegP() %{
3838 constraint(ALLOC_IN_RC(g2_regP));
3839 match(iRegP);
3840
3841 format %{ %}
3842 interface(REG_INTER);
3843 %}
3844
3845 operand g3RegP() %{
3846 constraint(ALLOC_IN_RC(g3_regP));
3847 match(iRegP);
3848
3849 format %{ %}
3850 interface(REG_INTER);
3851 %}
3852
3853 operand g1RegI() %{
3854 constraint(ALLOC_IN_RC(g1_regI));
3855 match(iRegI);
3856
3857 format %{ %}
3858 interface(REG_INTER);
3859 %}
3860
3861 operand g3RegI() %{
3862 constraint(ALLOC_IN_RC(g3_regI));
3863 match(iRegI);
3864
3865 format %{ %}
3866 interface(REG_INTER);
3867 %}
3868
3869 operand g4RegI() %{
3870 constraint(ALLOC_IN_RC(g4_regI));
3871 match(iRegI);
3872
3873 format %{ %}
3874 interface(REG_INTER);
3875 %}
3876
3877 operand g4RegP() %{
3878 constraint(ALLOC_IN_RC(g4_regP));
3879 match(iRegP);
3880
3881 format %{ %}
3882 interface(REG_INTER);
3883 %}
3884
3885 operand i0RegP() %{
3886 constraint(ALLOC_IN_RC(i0_regP));
3887 match(iRegP);
3888
3889 format %{ %}
3890 interface(REG_INTER);
3891 %}
3892
3893 operand o0RegP() %{
3894 constraint(ALLOC_IN_RC(o0_regP));
3895 match(iRegP);
3896
3897 format %{ %}
3898 interface(REG_INTER);
3899 %}
3900
3901 operand o1RegP() %{
3902 constraint(ALLOC_IN_RC(o1_regP));
3903 match(iRegP);
3904
3905 format %{ %}
3906 interface(REG_INTER);
3907 %}
3908
3909 operand o2RegP() %{
3910 constraint(ALLOC_IN_RC(o2_regP));
3911 match(iRegP);
3912
3913 format %{ %}
3914 interface(REG_INTER);
3915 %}
3916
3917 operand o7RegP() %{
3918 constraint(ALLOC_IN_RC(o7_regP));
3919 match(iRegP);
3920
3921 format %{ %}
3922 interface(REG_INTER);
3923 %}
3924
3925 operand l7RegP() %{
3926 constraint(ALLOC_IN_RC(l7_regP));
3927 match(iRegP);
3928
3929 format %{ %}
3930 interface(REG_INTER);
3931 %}
3932
3933 operand o7RegI() %{
3934 constraint(ALLOC_IN_RC(o7_regI));
3935 match(iRegI);
3936
3937 format %{ %}
3938 interface(REG_INTER);
3939 %}
3940
3941 operand iRegN() %{
3942 constraint(ALLOC_IN_RC(int_reg));
3943 match(RegN);
3944
3945 format %{ %}
3946 interface(REG_INTER);
3947 %}
3948
3949 // Long Register
3950 operand iRegL() %{
3951 constraint(ALLOC_IN_RC(long_reg));
3952 match(RegL);
3953
3954 format %{ %}
3955 interface(REG_INTER);
3956 %}
3957
3958 operand o2RegL() %{
3959 constraint(ALLOC_IN_RC(o2_regL));
3960 match(iRegL);
3961
3962 format %{ %}
3963 interface(REG_INTER);
3964 %}
3965
3966 operand o7RegL() %{
3967 constraint(ALLOC_IN_RC(o7_regL));
3968 match(iRegL);
3969
3970 format %{ %}
3971 interface(REG_INTER);
3972 %}
3973
3974 operand g1RegL() %{
3975 constraint(ALLOC_IN_RC(g1_regL));
3976 match(iRegL);
3977
3978 format %{ %}
3979 interface(REG_INTER);
3980 %}
3981
3982 operand g3RegL() %{
3983 constraint(ALLOC_IN_RC(g3_regL));
3984 match(iRegL);
3985
3986 format %{ %}
3987 interface(REG_INTER);
3988 %}
3989
3990 // Int Register safe
3991 // This is 64bit safe
3992 operand iRegIsafe() %{
3993 constraint(ALLOC_IN_RC(long_reg));
3994
3995 match(iRegI);
3996
3997 format %{ %}
3998 interface(REG_INTER);
3999 %}
4000
4001 // Condition Code Flag Register
4002 operand flagsReg() %{
4003 constraint(ALLOC_IN_RC(int_flags));
4004 match(RegFlags);
4005
4006 format %{ "ccr" %} // both ICC and XCC
4007 interface(REG_INTER);
4008 %}
4009
4010 // Condition Code Register, unsigned comparisons.
4011 operand flagsRegU() %{
4012 constraint(ALLOC_IN_RC(int_flags));
4013 match(RegFlags);
4014
4015 format %{ "icc_U" %}
4016 interface(REG_INTER);
4017 %}
4018
4019 // Condition Code Register, pointer comparisons.
4020 operand flagsRegP() %{
4021 constraint(ALLOC_IN_RC(int_flags));
4022 match(RegFlags);
4023
4024 #ifdef _LP64
4025 format %{ "xcc_P" %}
4026 #else
4027 format %{ "icc_P" %}
4028 #endif
4029 interface(REG_INTER);
4030 %}
4031
4032 // Condition Code Register, long comparisons.
4033 operand flagsRegL() %{
4034 constraint(ALLOC_IN_RC(int_flags));
4035 match(RegFlags);
4036
4037 format %{ "xcc_L" %}
4038 interface(REG_INTER);
4039 %}
4040
4041 // Condition Code Register, floating comparisons, unordered same as "less".
4042 operand flagsRegF() %{
4043 constraint(ALLOC_IN_RC(float_flags));
4044 match(RegFlags);
4045 match(flagsRegF0);
4046
4047 format %{ %}
4048 interface(REG_INTER);
4049 %}
4050
4051 operand flagsRegF0() %{
4052 constraint(ALLOC_IN_RC(float_flag0));
4053 match(RegFlags);
4054
4055 format %{ %}
4056 interface(REG_INTER);
4057 %}
4058
4059
4060 // Condition Code Flag Register used by long compare
4061 operand flagsReg_long_LTGE() %{
4062 constraint(ALLOC_IN_RC(int_flags));
4063 match(RegFlags);
4064 format %{ "icc_LTGE" %}
4065 interface(REG_INTER);
4066 %}
4067 operand flagsReg_long_EQNE() %{
4068 constraint(ALLOC_IN_RC(int_flags));
4069 match(RegFlags);
4070 format %{ "icc_EQNE" %}
4071 interface(REG_INTER);
4072 %}
4073 operand flagsReg_long_LEGT() %{
4074 constraint(ALLOC_IN_RC(int_flags));
4075 match(RegFlags);
4076 format %{ "icc_LEGT" %}
4077 interface(REG_INTER);
4078 %}
4079
4080
4081 operand regD() %{
4082 constraint(ALLOC_IN_RC(dflt_reg));
4083 match(RegD);
4084
4085 match(regD_low);
4086
4087 format %{ %}
4088 interface(REG_INTER);
4089 %}
4090
4091 operand regF() %{
4092 constraint(ALLOC_IN_RC(sflt_reg));
4093 match(RegF);
4094
4095 format %{ %}
4096 interface(REG_INTER);
4097 %}
4098
4099 operand regD_low() %{
4100 constraint(ALLOC_IN_RC(dflt_low_reg));
4101 match(regD);
4102
4103 format %{ %}
4104 interface(REG_INTER);
4105 %}
4106
4107 // Special Registers
4108
4109 // Method Register
4110 operand inline_cache_regP(iRegP reg) %{
4111 constraint(ALLOC_IN_RC(g5_regP)); // G5=inline_cache_reg but uses 2 bits instead of 1
4112 match(reg);
4113 format %{ %}
4114 interface(REG_INTER);
4115 %}
4116
4117 operand interpreter_method_oop_regP(iRegP reg) %{
4118 constraint(ALLOC_IN_RC(g5_regP)); // G5=interpreter_method_oop_reg but uses 2 bits instead of 1
4119 match(reg);
4120 format %{ %}
4121 interface(REG_INTER);
4122 %}
4123
4124
4125 //----------Complex Operands---------------------------------------------------
4126 // Indirect Memory Reference
4127 operand indirect(sp_ptr_RegP reg) %{
4128 constraint(ALLOC_IN_RC(sp_ptr_reg));
4129 match(reg);
4130
4131 op_cost(100);
4132 format %{ "[$reg]" %}
4133 interface(MEMORY_INTER) %{
4134 base($reg);
4135 index(0x0);
4136 scale(0x0);
4137 disp(0x0);
4138 %}
4139 %}
4140
4141 // Indirect with simm13 Offset
4142 operand indOffset13(sp_ptr_RegP reg, immX13 offset) %{
4143 constraint(ALLOC_IN_RC(sp_ptr_reg));
4144 match(AddP reg offset);
4145
4146 op_cost(100);
4147 format %{ "[$reg + $offset]" %}
4148 interface(MEMORY_INTER) %{
4149 base($reg);
4150 index(0x0);
4151 scale(0x0);
4152 disp($offset);
4153 %}
4154 %}
4155
4156 // Indirect with simm13 Offset minus 7
4157 operand indOffset13m7(sp_ptr_RegP reg, immX13m7 offset) %{
4158 constraint(ALLOC_IN_RC(sp_ptr_reg));
4159 match(AddP reg offset);
4160
4161 op_cost(100);
4162 format %{ "[$reg + $offset]" %}
4163 interface(MEMORY_INTER) %{
4164 base($reg);
4165 index(0x0);
4166 scale(0x0);
4167 disp($offset);
4168 %}
4169 %}
4170
4171 // Note: Intel has a swapped version also, like this:
4172 //operand indOffsetX(iRegI reg, immP offset) %{
4173 // constraint(ALLOC_IN_RC(int_reg));
4174 // match(AddP offset reg);
4175 //
4176 // op_cost(100);
4177 // format %{ "[$reg + $offset]" %}
4178 // interface(MEMORY_INTER) %{
4179 // base($reg);
4180 // index(0x0);
4181 // scale(0x0);
4182 // disp($offset);
4183 // %}
4184 //%}
4185 //// However, it doesn't make sense for SPARC, since
4186 // we have no particularly good way to embed oops in
4187 // single instructions.
4188
4189 // Indirect with Register Index
4190 operand indIndex(iRegP addr, iRegX index) %{
4191 constraint(ALLOC_IN_RC(ptr_reg));
4192 match(AddP addr index);
4193
4194 op_cost(100);
4195 format %{ "[$addr + $index]" %}
4196 interface(MEMORY_INTER) %{
4197 base($addr);
4198 index($index);
4199 scale(0x0);
4200 disp(0x0);
4201 %}
4202 %}
4203
4204 //----------Special Memory Operands--------------------------------------------
4205 // Stack Slot Operand - This operand is used for loading and storing temporary
4206 // values on the stack where a match requires a value to
4207 // flow through memory.
4208 operand stackSlotI(sRegI reg) %{
4209 constraint(ALLOC_IN_RC(stack_slots));
4210 op_cost(100);
4211 //match(RegI);
4212 format %{ "[$reg]" %}
4213 interface(MEMORY_INTER) %{
4214 base(0xE); // R_SP
4215 index(0x0);
4216 scale(0x0);
4217 disp($reg); // Stack Offset
4218 %}
4219 %}
4220
4221 operand stackSlotP(sRegP reg) %{
4222 constraint(ALLOC_IN_RC(stack_slots));
4223 op_cost(100);
4224 //match(RegP);
4225 format %{ "[$reg]" %}
4226 interface(MEMORY_INTER) %{
4227 base(0xE); // R_SP
4228 index(0x0);
4229 scale(0x0);
4230 disp($reg); // Stack Offset
4231 %}
4232 %}
4233
4234 operand stackSlotF(sRegF reg) %{
4235 constraint(ALLOC_IN_RC(stack_slots));
4236 op_cost(100);
4237 //match(RegF);
4238 format %{ "[$reg]" %}
4239 interface(MEMORY_INTER) %{
4240 base(0xE); // R_SP
4241 index(0x0);
4242 scale(0x0);
4243 disp($reg); // Stack Offset
4244 %}
4245 %}
4246 operand stackSlotD(sRegD reg) %{
4247 constraint(ALLOC_IN_RC(stack_slots));
4248 op_cost(100);
4249 //match(RegD);
4250 format %{ "[$reg]" %}
4251 interface(MEMORY_INTER) %{
4252 base(0xE); // R_SP
4253 index(0x0);
4254 scale(0x0);
4255 disp($reg); // Stack Offset
4256 %}
4257 %}
4258 operand stackSlotL(sRegL reg) %{
4259 constraint(ALLOC_IN_RC(stack_slots));
4260 op_cost(100);
4261 //match(RegL);
4262 format %{ "[$reg]" %}
4263 interface(MEMORY_INTER) %{
4264 base(0xE); // R_SP
4265 index(0x0);
4266 scale(0x0);
4267 disp($reg); // Stack Offset
4268 %}
4269 %}
4270
4271 // Operands for expressing Control Flow
4272 // NOTE: Label is a predefined operand which should not be redefined in
4273 // the AD file. It is generically handled within the ADLC.
4274
4275 //----------Conditional Branch Operands----------------------------------------
4276 // Comparison Op - This is the operation of the comparison, and is limited to
4277 // the following set of codes:
4278 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
4279 //
4280 // Other attributes of the comparison, such as unsignedness, are specified
4281 // by the comparison instruction that sets a condition code flags register.
4282 // That result is represented by a flags operand whose subtype is appropriate
4283 // to the unsignedness (etc.) of the comparison.
4284 //
4285 // Later, the instruction which matches both the Comparison Op (a Bool) and
4286 // the flags (produced by the Cmp) specifies the coding of the comparison op
4287 // by matching a specific subtype of Bool operand below, such as cmpOpU.
4288
4289 operand cmpOp() %{
4290 match(Bool);
4291
4292 format %{ "" %}
4293 interface(COND_INTER) %{
4294 equal(0x1);
4295 not_equal(0x9);
4296 less(0x3);
4297 greater_equal(0xB);
4298 less_equal(0x2);
4299 greater(0xA);
4300 %}
4301 %}
4302
4303 // Comparison Op, unsigned
4304 operand cmpOpU() %{
4305 match(Bool);
4306
4307 format %{ "u" %}
4308 interface(COND_INTER) %{
4309 equal(0x1);
4310 not_equal(0x9);
4311 less(0x5);
4312 greater_equal(0xD);
4313 less_equal(0x4);
4314 greater(0xC);
4315 %}
4316 %}
4317
4318 // Comparison Op, pointer (same as unsigned)
4319 operand cmpOpP() %{
4320 match(Bool);
4321
4322 format %{ "p" %}
4323 interface(COND_INTER) %{
4324 equal(0x1);
4325 not_equal(0x9);
4326 less(0x5);
4327 greater_equal(0xD);
4328 less_equal(0x4);
4329 greater(0xC);
4330 %}
4331 %}
4332
4333 // Comparison Op, branch-register encoding
4334 operand cmpOp_reg() %{
4335 match(Bool);
4336
4337 format %{ "" %}
4338 interface(COND_INTER) %{
4339 equal (0x1);
4340 not_equal (0x5);
4341 less (0x3);
4342 greater_equal(0x7);
4343 less_equal (0x2);
4344 greater (0x6);
4345 %}
4346 %}
4347
4348 // Comparison Code, floating, unordered same as less
4349 operand cmpOpF() %{
4350 match(Bool);
4351
4352 format %{ "fl" %}
4353 interface(COND_INTER) %{
4354 equal(0x9);
4355 not_equal(0x1);
4356 less(0x3);
4357 greater_equal(0xB);
4358 less_equal(0xE);
4359 greater(0x6);
4360 %}
4361 %}
4362
4363 // Used by long compare
4364 operand cmpOp_commute() %{
4365 match(Bool);
4366
4367 format %{ "" %}
4368 interface(COND_INTER) %{
4369 equal(0x1);
4370 not_equal(0x9);
4371 less(0xA);
4372 greater_equal(0x2);
4373 less_equal(0xB);
4374 greater(0x3);
4375 %}
4376 %}
4377
4378 //----------OPERAND CLASSES----------------------------------------------------
4379 // Operand Classes are groups of operands that are used to simplify
4380 // instruction definitions by not requiring the AD writer to specify separate
4381 // instructions for every form of operand when the instruction accepts
4382 // multiple operand types with the same basic encoding and format. The classic
4383 // case of this is memory operands.
4384 // Indirect is not included since its use is limited to Compare & Swap
4385 opclass memory( indirect, indOffset13, indIndex );
4386
4387 //----------PIPELINE-----------------------------------------------------------
4388 pipeline %{
4389
4390 //----------ATTRIBUTES---------------------------------------------------------
4391 attributes %{
4392 fixed_size_instructions; // Fixed size instructions
4393 branch_has_delay_slot; // Branch has delay slot following
4394 max_instructions_per_bundle = 4; // Up to 4 instructions per bundle
4395 instruction_unit_size = 4; // An instruction is 4 bytes long
4396 instruction_fetch_unit_size = 16; // The processor fetches one line
4397 instruction_fetch_units = 1; // of 16 bytes
4398
4399 // List of nop instructions
4400 nops( Nop_A0, Nop_A1, Nop_MS, Nop_FA, Nop_BR );
4401 %}
4402
4403 //----------RESOURCES----------------------------------------------------------
4404 // Resources are the functional units available to the machine
4405 resources(A0, A1, MS, BR, FA, FM, IDIV, FDIV, IALU = A0 | A1);
4406
4407 //----------PIPELINE DESCRIPTION-----------------------------------------------
4408 // Pipeline Description specifies the stages in the machine's pipeline
4409
4410 pipe_desc(A, P, F, B, I, J, S, R, E, C, M, W, X, T, D);
4411
4412 //----------PIPELINE CLASSES---------------------------------------------------
4413 // Pipeline Classes describe the stages in which input and output are
4414 // referenced by the hardware pipeline.
4415
4416 // Integer ALU reg-reg operation
4417 pipe_class ialu_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
4418 single_instruction;
4419 dst : E(write);
4420 src1 : R(read);
4421 src2 : R(read);
4422 IALU : R;
4423 %}
4424
4425 // Integer ALU reg-reg long operation
4426 pipe_class ialu_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{
4427 instruction_count(2);
4428 dst : E(write);
4429 src1 : R(read);
4430 src2 : R(read);
4431 IALU : R;
4432 IALU : R;
4433 %}
4434
4435 // Integer ALU reg-reg long dependent operation
4436 pipe_class ialu_reg_reg_2_dep(iRegL dst, iRegL src1, iRegL src2, flagsReg cr) %{
4437 instruction_count(1); multiple_bundles;
4438 dst : E(write);
4439 src1 : R(read);
4440 src2 : R(read);
4441 cr : E(write);
4442 IALU : R(2);
4443 %}
4444
4445 // Integer ALU reg-imm operaion
4446 pipe_class ialu_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{
4447 single_instruction;
4448 dst : E(write);
4449 src1 : R(read);
4450 IALU : R;
4451 %}
4452
4453 // Integer ALU reg-reg operation with condition code
4454 pipe_class ialu_cc_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
4455 single_instruction;
4456 dst : E(write);
4457 cr : E(write);
4458 src1 : R(read);
4459 src2 : R(read);
4460 IALU : R;
4461 %}
4462
4463 // Integer ALU reg-imm operation with condition code
4464 pipe_class ialu_cc_reg_imm(iRegI dst, iRegI src1, immI13 src2, flagsReg cr) %{
4465 single_instruction;
4466 dst : E(write);
4467 cr : E(write);
4468 src1 : R(read);
4469 IALU : R;
4470 %}
4471
4472 // Integer ALU zero-reg operation
4473 pipe_class ialu_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{
4474 single_instruction;
4475 dst : E(write);
4476 src2 : R(read);
4477 IALU : R;
4478 %}
4479
4480 // Integer ALU zero-reg operation with condition code only
4481 pipe_class ialu_cconly_zero_reg(flagsReg cr, iRegI src) %{
4482 single_instruction;
4483 cr : E(write);
4484 src : R(read);
4485 IALU : R;
4486 %}
4487
4488 // Integer ALU reg-reg operation with condition code only
4489 pipe_class ialu_cconly_reg_reg(flagsReg cr, iRegI src1, iRegI src2) %{
4490 single_instruction;
4491 cr : E(write);
4492 src1 : R(read);
4493 src2 : R(read);
4494 IALU : R;
4495 %}
4496
4497 // Integer ALU reg-imm operation with condition code only
4498 pipe_class ialu_cconly_reg_imm(flagsReg cr, iRegI src1, immI13 src2) %{
4499 single_instruction;
4500 cr : E(write);
4501 src1 : R(read);
4502 IALU : R;
4503 %}
4504
4505 // Integer ALU reg-reg-zero operation with condition code only
4506 pipe_class ialu_cconly_reg_reg_zero(flagsReg cr, iRegI src1, iRegI src2, immI0 zero) %{
4507 single_instruction;
4508 cr : E(write);
4509 src1 : R(read);
4510 src2 : R(read);
4511 IALU : R;
4512 %}
4513
4514 // Integer ALU reg-imm-zero operation with condition code only
4515 pipe_class ialu_cconly_reg_imm_zero(flagsReg cr, iRegI src1, immI13 src2, immI0 zero) %{
4516 single_instruction;
4517 cr : E(write);
4518 src1 : R(read);
4519 IALU : R;
4520 %}
4521
4522 // Integer ALU reg-reg operation with condition code, src1 modified
4523 pipe_class ialu_cc_rwreg_reg(flagsReg cr, iRegI src1, iRegI src2) %{
4524 single_instruction;
4525 cr : E(write);
4526 src1 : E(write);
4527 src1 : R(read);
4528 src2 : R(read);
4529 IALU : R;
4530 %}
4531
4532 // Integer ALU reg-imm operation with condition code, src1 modified
4533 pipe_class ialu_cc_rwreg_imm(flagsReg cr, iRegI src1, immI13 src2) %{
4534 single_instruction;
4535 cr : E(write);
4536 src1 : E(write);
4537 src1 : R(read);
4538 IALU : R;
4539 %}
4540
4541 pipe_class cmpL_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg cr ) %{
4542 multiple_bundles;
4543 dst : E(write)+4;
4544 cr : E(write);
4545 src1 : R(read);
4546 src2 : R(read);
4547 IALU : R(3);
4548 BR : R(2);
4549 %}
4550
4551 // Integer ALU operation
4552 pipe_class ialu_none(iRegI dst) %{
4553 single_instruction;
4554 dst : E(write);
4555 IALU : R;
4556 %}
4557
4558 // Integer ALU reg operation
4559 pipe_class ialu_reg(iRegI dst, iRegI src) %{
4560 single_instruction; may_have_no_code;
4561 dst : E(write);
4562 src : R(read);
4563 IALU : R;
4564 %}
4565
4566 // Integer ALU reg conditional operation
4567 // This instruction has a 1 cycle stall, and cannot execute
4568 // in the same cycle as the instruction setting the condition
4569 // code. We kludge this by pretending to read the condition code
4570 // 1 cycle earlier, and by marking the functional units as busy
4571 // for 2 cycles with the result available 1 cycle later than
4572 // is really the case.
4573 pipe_class ialu_reg_flags( iRegI op2_out, iRegI op2_in, iRegI op1, flagsReg cr ) %{
4574 single_instruction;
4575 op2_out : C(write);
4576 op1 : R(read);
4577 cr : R(read); // This is really E, with a 1 cycle stall
4578 BR : R(2);
4579 MS : R(2);
4580 %}
4581
4582 #ifdef _LP64
4583 pipe_class ialu_clr_and_mover( iRegI dst, iRegP src ) %{
4584 instruction_count(1); multiple_bundles;
4585 dst : C(write)+1;
4586 src : R(read)+1;
4587 IALU : R(1);
4588 BR : E(2);
4589 MS : E(2);
4590 %}
4591 #endif
4592
4593 // Integer ALU reg operation
4594 pipe_class ialu_move_reg_L_to_I(iRegI dst, iRegL src) %{
4595 single_instruction; may_have_no_code;
4596 dst : E(write);
4597 src : R(read);
4598 IALU : R;
4599 %}
4600 pipe_class ialu_move_reg_I_to_L(iRegL dst, iRegI src) %{
4601 single_instruction; may_have_no_code;
4602 dst : E(write);
4603 src : R(read);
4604 IALU : R;
4605 %}
4606
4607 // Two integer ALU reg operations
4608 pipe_class ialu_reg_2(iRegL dst, iRegL src) %{
4609 instruction_count(2);
4610 dst : E(write);
4611 src : R(read);
4612 A0 : R;
4613 A1 : R;
4614 %}
4615
4616 // Two integer ALU reg operations
4617 pipe_class ialu_move_reg_L_to_L(iRegL dst, iRegL src) %{
4618 instruction_count(2); may_have_no_code;
4619 dst : E(write);
4620 src : R(read);
4621 A0 : R;
4622 A1 : R;
4623 %}
4624
4625 // Integer ALU imm operation
4626 pipe_class ialu_imm(iRegI dst, immI13 src) %{
4627 single_instruction;
4628 dst : E(write);
4629 IALU : R;
4630 %}
4631
4632 // Integer ALU reg-reg with carry operation
4633 pipe_class ialu_reg_reg_cy(iRegI dst, iRegI src1, iRegI src2, iRegI cy) %{
4634 single_instruction;
4635 dst : E(write);
4636 src1 : R(read);
4637 src2 : R(read);
4638 IALU : R;
4639 %}
4640
4641 // Integer ALU cc operation
4642 pipe_class ialu_cc(iRegI dst, flagsReg cc) %{
4643 single_instruction;
4644 dst : E(write);
4645 cc : R(read);
4646 IALU : R;
4647 %}
4648
4649 // Integer ALU cc / second IALU operation
4650 pipe_class ialu_reg_ialu( iRegI dst, iRegI src ) %{
4651 instruction_count(1); multiple_bundles;
4652 dst : E(write)+1;
4653 src : R(read);
4654 IALU : R;
4655 %}
4656
4657 // Integer ALU cc / second IALU operation
4658 pipe_class ialu_reg_reg_ialu( iRegI dst, iRegI p, iRegI q ) %{
4659 instruction_count(1); multiple_bundles;
4660 dst : E(write)+1;
4661 p : R(read);
4662 q : R(read);
4663 IALU : R;
4664 %}
4665
4666 // Integer ALU hi-lo-reg operation
4667 pipe_class ialu_hi_lo_reg(iRegI dst, immI src) %{
4668 instruction_count(1); multiple_bundles;
4669 dst : E(write)+1;
4670 IALU : R(2);
4671 %}
4672
4673 // Float ALU hi-lo-reg operation (with temp)
4674 pipe_class ialu_hi_lo_reg_temp(regF dst, immF src, g3RegP tmp) %{
4675 instruction_count(1); multiple_bundles;
4676 dst : E(write)+1;
4677 IALU : R(2);
4678 %}
4679
4680 // Long Constant
4681 pipe_class loadConL( iRegL dst, immL src ) %{
4682 instruction_count(2); multiple_bundles;
4683 dst : E(write)+1;
4684 IALU : R(2);
4685 IALU : R(2);
4686 %}
4687
4688 // Pointer Constant
4689 pipe_class loadConP( iRegP dst, immP src ) %{
4690 instruction_count(0); multiple_bundles;
4691 fixed_latency(6);
4692 %}
4693
4694 // Polling Address
4695 pipe_class loadConP_poll( iRegP dst, immP_poll src ) %{
4696 #ifdef _LP64
4697 instruction_count(0); multiple_bundles;
4698 fixed_latency(6);
4699 #else
4700 dst : E(write);
4701 IALU : R;
4702 #endif
4703 %}
4704
4705 // Long Constant small
4706 pipe_class loadConLlo( iRegL dst, immL src ) %{
4707 instruction_count(2);
4708 dst : E(write);
4709 IALU : R;
4710 IALU : R;
4711 %}
4712
4713 // [PHH] This is wrong for 64-bit. See LdImmF/D.
4714 pipe_class loadConFD(regF dst, immF src, g3RegP tmp) %{
4715 instruction_count(1); multiple_bundles;
4716 src : R(read);
4717 dst : M(write)+1;
4718 IALU : R;
4719 MS : E;
4720 %}
4721
4722 // Integer ALU nop operation
4723 pipe_class ialu_nop() %{
4724 single_instruction;
4725 IALU : R;
4726 %}
4727
4728 // Integer ALU nop operation
4729 pipe_class ialu_nop_A0() %{
4730 single_instruction;
4731 A0 : R;
4732 %}
4733
4734 // Integer ALU nop operation
4735 pipe_class ialu_nop_A1() %{
4736 single_instruction;
4737 A1 : R;
4738 %}
4739
4740 // Integer Multiply reg-reg operation
4741 pipe_class imul_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
4742 single_instruction;
4743 dst : E(write);
4744 src1 : R(read);
4745 src2 : R(read);
4746 MS : R(5);
4747 %}
4748
4749 // Integer Multiply reg-imm operation
4750 pipe_class imul_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{
4751 single_instruction;
4752 dst : E(write);
4753 src1 : R(read);
4754 MS : R(5);
4755 %}
4756
4757 pipe_class mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
4758 single_instruction;
4759 dst : E(write)+4;
4760 src1 : R(read);
4761 src2 : R(read);
4762 MS : R(6);
4763 %}
4764
4765 pipe_class mulL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{
4766 single_instruction;
4767 dst : E(write)+4;
4768 src1 : R(read);
4769 MS : R(6);
4770 %}
4771
4772 // Integer Divide reg-reg
4773 pipe_class sdiv_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI temp, flagsReg cr) %{
4774 instruction_count(1); multiple_bundles;
4775 dst : E(write);
4776 temp : E(write);
4777 src1 : R(read);
4778 src2 : R(read);
4779 temp : R(read);
4780 MS : R(38);
4781 %}
4782
4783 // Integer Divide reg-imm
4784 pipe_class sdiv_reg_imm(iRegI dst, iRegI src1, immI13 src2, iRegI temp, flagsReg cr) %{
4785 instruction_count(1); multiple_bundles;
4786 dst : E(write);
4787 temp : E(write);
4788 src1 : R(read);
4789 temp : R(read);
4790 MS : R(38);
4791 %}
4792
4793 // Long Divide
4794 pipe_class divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
4795 dst : E(write)+71;
4796 src1 : R(read);
4797 src2 : R(read)+1;
4798 MS : R(70);
4799 %}
4800
4801 pipe_class divL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{
4802 dst : E(write)+71;
4803 src1 : R(read);
4804 MS : R(70);
4805 %}
4806
4807 // Floating Point Add Float
4808 pipe_class faddF_reg_reg(regF dst, regF src1, regF src2) %{
4809 single_instruction;
4810 dst : X(write);
4811 src1 : E(read);
4812 src2 : E(read);
4813 FA : R;
4814 %}
4815
4816 // Floating Point Add Double
4817 pipe_class faddD_reg_reg(regD dst, regD src1, regD src2) %{
4818 single_instruction;
4819 dst : X(write);
4820 src1 : E(read);
4821 src2 : E(read);
4822 FA : R;
4823 %}
4824
4825 // Floating Point Conditional Move based on integer flags
4826 pipe_class int_conditional_float_move (cmpOp cmp, flagsReg cr, regF dst, regF src) %{
4827 single_instruction;
4828 dst : X(write);
4829 src : E(read);
4830 cr : R(read);
4831 FA : R(2);
4832 BR : R(2);
4833 %}
4834
4835 // Floating Point Conditional Move based on integer flags
4836 pipe_class int_conditional_double_move (cmpOp cmp, flagsReg cr, regD dst, regD src) %{
4837 single_instruction;
4838 dst : X(write);
4839 src : E(read);
4840 cr : R(read);
4841 FA : R(2);
4842 BR : R(2);
4843 %}
4844
4845 // Floating Point Multiply Float
4846 pipe_class fmulF_reg_reg(regF dst, regF src1, regF src2) %{
4847 single_instruction;
4848 dst : X(write);
4849 src1 : E(read);
4850 src2 : E(read);
4851 FM : R;
4852 %}
4853
4854 // Floating Point Multiply Double
4855 pipe_class fmulD_reg_reg(regD dst, regD src1, regD src2) %{
4856 single_instruction;
4857 dst : X(write);
4858 src1 : E(read);
4859 src2 : E(read);
4860 FM : R;
4861 %}
4862
4863 // Floating Point Divide Float
4864 pipe_class fdivF_reg_reg(regF dst, regF src1, regF src2) %{
4865 single_instruction;
4866 dst : X(write);
4867 src1 : E(read);
4868 src2 : E(read);
4869 FM : R;
4870 FDIV : C(14);
4871 %}
4872
4873 // Floating Point Divide Double
4874 pipe_class fdivD_reg_reg(regD dst, regD src1, regD src2) %{
4875 single_instruction;
4876 dst : X(write);
4877 src1 : E(read);
4878 src2 : E(read);
4879 FM : R;
4880 FDIV : C(17);
4881 %}
4882
4883 // Floating Point Move/Negate/Abs Float
4884 pipe_class faddF_reg(regF dst, regF src) %{
4885 single_instruction;
4886 dst : W(write);
4887 src : E(read);
4888 FA : R(1);
4889 %}
4890
4891 // Floating Point Move/Negate/Abs Double
4892 pipe_class faddD_reg(regD dst, regD src) %{
4893 single_instruction;
4894 dst : W(write);
4895 src : E(read);
4896 FA : R;
4897 %}
4898
4899 // Floating Point Convert F->D
4900 pipe_class fcvtF2D(regD dst, regF src) %{
4901 single_instruction;
4902 dst : X(write);
4903 src : E(read);
4904 FA : R;
4905 %}
4906
4907 // Floating Point Convert I->D
4908 pipe_class fcvtI2D(regD dst, regF src) %{
4909 single_instruction;
4910 dst : X(write);
4911 src : E(read);
4912 FA : R;
4913 %}
4914
4915 // Floating Point Convert LHi->D
4916 pipe_class fcvtLHi2D(regD dst, regD src) %{
4917 single_instruction;
4918 dst : X(write);
4919 src : E(read);
4920 FA : R;
4921 %}
4922
4923 // Floating Point Convert L->D
4924 pipe_class fcvtL2D(regD dst, regF src) %{
4925 single_instruction;
4926 dst : X(write);
4927 src : E(read);
4928 FA : R;
4929 %}
4930
4931 // Floating Point Convert L->F
4932 pipe_class fcvtL2F(regD dst, regF src) %{
4933 single_instruction;
4934 dst : X(write);
4935 src : E(read);
4936 FA : R;
4937 %}
4938
4939 // Floating Point Convert D->F
4940 pipe_class fcvtD2F(regD dst, regF src) %{
4941 single_instruction;
4942 dst : X(write);
4943 src : E(read);
4944 FA : R;
4945 %}
4946
4947 // Floating Point Convert I->L
4948 pipe_class fcvtI2L(regD dst, regF src) %{
4949 single_instruction;
4950 dst : X(write);
4951 src : E(read);
4952 FA : R;
4953 %}
4954
4955 // Floating Point Convert D->F
4956 pipe_class fcvtD2I(regF dst, regD src, flagsReg cr) %{
4957 instruction_count(1); multiple_bundles;
4958 dst : X(write)+6;
4959 src : E(read);
4960 FA : R;
4961 %}
4962
4963 // Floating Point Convert D->L
4964 pipe_class fcvtD2L(regD dst, regD src, flagsReg cr) %{
4965 instruction_count(1); multiple_bundles;
4966 dst : X(write)+6;
4967 src : E(read);
4968 FA : R;
4969 %}
4970
4971 // Floating Point Convert F->I
4972 pipe_class fcvtF2I(regF dst, regF src, flagsReg cr) %{
4973 instruction_count(1); multiple_bundles;
4974 dst : X(write)+6;
4975 src : E(read);
4976 FA : R;
4977 %}
4978
4979 // Floating Point Convert F->L
4980 pipe_class fcvtF2L(regD dst, regF src, flagsReg cr) %{
4981 instruction_count(1); multiple_bundles;
4982 dst : X(write)+6;
4983 src : E(read);
4984 FA : R;
4985 %}
4986
4987 // Floating Point Convert I->F
4988 pipe_class fcvtI2F(regF dst, regF src) %{
4989 single_instruction;
4990 dst : X(write);
4991 src : E(read);
4992 FA : R;
4993 %}
4994
4995 // Floating Point Compare
4996 pipe_class faddF_fcc_reg_reg_zero(flagsRegF cr, regF src1, regF src2, immI0 zero) %{
4997 single_instruction;
4998 cr : X(write);
4999 src1 : E(read);
5000 src2 : E(read);
5001 FA : R;
5002 %}
5003
5004 // Floating Point Compare
5005 pipe_class faddD_fcc_reg_reg_zero(flagsRegF cr, regD src1, regD src2, immI0 zero) %{
5006 single_instruction;
5007 cr : X(write);
5008 src1 : E(read);
5009 src2 : E(read);
5010 FA : R;
5011 %}
5012
5013 // Floating Add Nop
5014 pipe_class fadd_nop() %{
5015 single_instruction;
5016 FA : R;
5017 %}
5018
5019 // Integer Store to Memory
5020 pipe_class istore_mem_reg(memory mem, iRegI src) %{
5021 single_instruction;
5022 mem : R(read);
5023 src : C(read);
5024 MS : R;
5025 %}
5026
5027 // Integer Store to Memory
5028 pipe_class istore_mem_spORreg(memory mem, sp_ptr_RegP src) %{
5029 single_instruction;
5030 mem : R(read);
5031 src : C(read);
5032 MS : R;
5033 %}
5034
5035 // Integer Store Zero to Memory
5036 pipe_class istore_mem_zero(memory mem, immI0 src) %{
5037 single_instruction;
5038 mem : R(read);
5039 MS : R;
5040 %}
5041
5042 // Special Stack Slot Store
5043 pipe_class istore_stk_reg(stackSlotI stkSlot, iRegI src) %{
5044 single_instruction;
5045 stkSlot : R(read);
5046 src : C(read);
5047 MS : R;
5048 %}
5049
5050 // Special Stack Slot Store
5051 pipe_class lstoreI_stk_reg(stackSlotL stkSlot, iRegI src) %{
5052 instruction_count(2); multiple_bundles;
5053 stkSlot : R(read);
5054 src : C(read);
5055 MS : R(2);
5056 %}
5057
5058 // Float Store
5059 pipe_class fstoreF_mem_reg(memory mem, RegF src) %{
5060 single_instruction;
5061 mem : R(read);
5062 src : C(read);
5063 MS : R;
5064 %}
5065
5066 // Float Store
5067 pipe_class fstoreF_mem_zero(memory mem, immF0 src) %{
5068 single_instruction;
5069 mem : R(read);
5070 MS : R;
5071 %}
5072
5073 // Double Store
5074 pipe_class fstoreD_mem_reg(memory mem, RegD src) %{
5075 instruction_count(1);
5076 mem : R(read);
5077 src : C(read);
5078 MS : R;
5079 %}
5080
5081 // Double Store
5082 pipe_class fstoreD_mem_zero(memory mem, immD0 src) %{
5083 single_instruction;
5084 mem : R(read);
5085 MS : R;
5086 %}
5087
5088 // Special Stack Slot Float Store
5089 pipe_class fstoreF_stk_reg(stackSlotI stkSlot, RegF src) %{
5090 single_instruction;
5091 stkSlot : R(read);
5092 src : C(read);
5093 MS : R;
5094 %}
5095
5096 // Special Stack Slot Double Store
5097 pipe_class fstoreD_stk_reg(stackSlotI stkSlot, RegD src) %{
5098 single_instruction;
5099 stkSlot : R(read);
5100 src : C(read);
5101 MS : R;
5102 %}
5103
5104 // Integer Load (when sign bit propagation not needed)
5105 pipe_class iload_mem(iRegI dst, memory mem) %{
5106 single_instruction;
5107 mem : R(read);
5108 dst : C(write);
5109 MS : R;
5110 %}
5111
5112 // Integer Load from stack operand
5113 pipe_class iload_stkD(iRegI dst, stackSlotD mem ) %{
5114 single_instruction;
5115 mem : R(read);
5116 dst : C(write);
5117 MS : R;
5118 %}
5119
5120 // Integer Load (when sign bit propagation or masking is needed)
5121 pipe_class iload_mask_mem(iRegI dst, memory mem) %{
5122 single_instruction;
5123 mem : R(read);
5124 dst : M(write);
5125 MS : R;
5126 %}
5127
5128 // Float Load
5129 pipe_class floadF_mem(regF dst, memory mem) %{
5130 single_instruction;
5131 mem : R(read);
5132 dst : M(write);
5133 MS : R;
5134 %}
5135
5136 // Float Load
5137 pipe_class floadD_mem(regD dst, memory mem) %{
5138 instruction_count(1); multiple_bundles; // Again, unaligned argument is only multiple case
5139 mem : R(read);
5140 dst : M(write);
5141 MS : R;
5142 %}
5143
5144 // Float Load
5145 pipe_class floadF_stk(regF dst, stackSlotI stkSlot) %{
5146 single_instruction;
5147 stkSlot : R(read);
5148 dst : M(write);
5149 MS : R;
5150 %}
5151
5152 // Float Load
5153 pipe_class floadD_stk(regD dst, stackSlotI stkSlot) %{
5154 single_instruction;
5155 stkSlot : R(read);
5156 dst : M(write);
5157 MS : R;
5158 %}
5159
5160 // Memory Nop
5161 pipe_class mem_nop() %{
5162 single_instruction;
5163 MS : R;
5164 %}
5165
5166 pipe_class sethi(iRegP dst, immI src) %{
5167 single_instruction;
5168 dst : E(write);
5169 IALU : R;
5170 %}
5171
5172 pipe_class loadPollP(iRegP poll) %{
5173 single_instruction;
5174 poll : R(read);
5175 MS : R;
5176 %}
5177
5178 pipe_class br(Universe br, label labl) %{
5179 single_instruction_with_delay_slot;
5180 BR : R;
5181 %}
5182
5183 pipe_class br_cc(Universe br, cmpOp cmp, flagsReg cr, label labl) %{
5184 single_instruction_with_delay_slot;
5185 cr : E(read);
5186 BR : R;
5187 %}
5188
5189 pipe_class br_reg(Universe br, cmpOp cmp, iRegI op1, label labl) %{
5190 single_instruction_with_delay_slot;
5191 op1 : E(read);
5192 BR : R;
5193 MS : R;
5194 %}
5195
5196 pipe_class br_fcc(Universe br, cmpOpF cc, flagsReg cr, label labl) %{
5197 single_instruction_with_delay_slot;
5198 cr : E(read);
5199 BR : R;
5200 %}
5201
5202 pipe_class br_nop() %{
5203 single_instruction;
5204 BR : R;
5205 %}
5206
5207 pipe_class simple_call(method meth) %{
5208 instruction_count(2); multiple_bundles; force_serialization;
5209 fixed_latency(100);
5210 BR : R(1);
5211 MS : R(1);
5212 A0 : R(1);
5213 %}
5214
5215 pipe_class compiled_call(method meth) %{
5216 instruction_count(1); multiple_bundles; force_serialization;
5217 fixed_latency(100);
5218 MS : R(1);
5219 %}
5220
5221 pipe_class call(method meth) %{
5222 instruction_count(0); multiple_bundles; force_serialization;
5223 fixed_latency(100);
5224 %}
5225
5226 pipe_class tail_call(Universe ignore, label labl) %{
5227 single_instruction; has_delay_slot;
5228 fixed_latency(100);
5229 BR : R(1);
5230 MS : R(1);
5231 %}
5232
5233 pipe_class ret(Universe ignore) %{
5234 single_instruction; has_delay_slot;
5235 BR : R(1);
5236 MS : R(1);
5237 %}
5238
5239 pipe_class ret_poll(g3RegP poll) %{
5240 instruction_count(3); has_delay_slot;
5241 poll : E(read);
5242 MS : R;
5243 %}
5244
5245 // The real do-nothing guy
5246 pipe_class empty( ) %{
5247 instruction_count(0);
5248 %}
5249
5250 pipe_class long_memory_op() %{
5251 instruction_count(0); multiple_bundles; force_serialization;
5252 fixed_latency(25);
5253 MS : R(1);
5254 %}
5255
5256 // Check-cast
5257 pipe_class partial_subtype_check_pipe(Universe ignore, iRegP array, iRegP match ) %{
5258 array : R(read);
5259 match : R(read);
5260 IALU : R(2);
5261 BR : R(2);
5262 MS : R;
5263 %}
5264
5265 // Convert FPU flags into +1,0,-1
5266 pipe_class floating_cmp( iRegI dst, regF src1, regF src2 ) %{
5267 src1 : E(read);
5268 src2 : E(read);
5269 dst : E(write);
5270 FA : R;
5271 MS : R(2);
5272 BR : R(2);
5273 %}
5274
5275 // Compare for p < q, and conditionally add y
5276 pipe_class cadd_cmpltmask( iRegI p, iRegI q, iRegI y ) %{
5277 p : E(read);
5278 q : E(read);
5279 y : E(read);
5280 IALU : R(3)
5281 %}
5282
5283 // Perform a compare, then move conditionally in a branch delay slot.
5284 pipe_class min_max( iRegI src2, iRegI srcdst ) %{
5285 src2 : E(read);
5286 srcdst : E(read);
5287 IALU : R;
5288 BR : R;
5289 %}
5290
5291 // Define the class for the Nop node
5292 define %{
5293 MachNop = ialu_nop;
5294 %}
5295
5296 %}
5297
5298 //----------INSTRUCTIONS-------------------------------------------------------
5299
5300 //------------Special Stack Slot instructions - no match rules-----------------
5301 instruct stkI_to_regF(regF dst, stackSlotI src) %{
5302 // No match rule to avoid chain rule match.
5303 effect(DEF dst, USE src);
5304 ins_cost(MEMORY_REF_COST);
5305 size(4);
5306 format %{ "LDF $src,$dst\t! stkI to regF" %}
5307 opcode(Assembler::ldf_op3);
5308 ins_encode(simple_form3_mem_reg(src, dst));
5309 ins_pipe(floadF_stk);
5310 %}
5311
5312 instruct stkL_to_regD(regD dst, stackSlotL src) %{
5313 // No match rule to avoid chain rule match.
5314 effect(DEF dst, USE src);
5315 ins_cost(MEMORY_REF_COST);
5316 size(4);
5317 format %{ "LDDF $src,$dst\t! stkL to regD" %}
5318 opcode(Assembler::lddf_op3);
5319 ins_encode(simple_form3_mem_reg(src, dst));
5320 ins_pipe(floadD_stk);
5321 %}
5322
5323 instruct regF_to_stkI(stackSlotI dst, regF src) %{
5324 // No match rule to avoid chain rule match.
5325 effect(DEF dst, USE src);
5326 ins_cost(MEMORY_REF_COST);
5327 size(4);
5328 format %{ "STF $src,$dst\t! regF to stkI" %}
5329 opcode(Assembler::stf_op3);
5330 ins_encode(simple_form3_mem_reg(dst, src));
5331 ins_pipe(fstoreF_stk_reg);
5332 %}
5333
5334 instruct regD_to_stkL(stackSlotL dst, regD src) %{
5335 // No match rule to avoid chain rule match.
5336 effect(DEF dst, USE src);
5337 ins_cost(MEMORY_REF_COST);
5338 size(4);
5339 format %{ "STDF $src,$dst\t! regD to stkL" %}
5340 opcode(Assembler::stdf_op3);
5341 ins_encode(simple_form3_mem_reg(dst, src));
5342 ins_pipe(fstoreD_stk_reg);
5343 %}
5344
5345 instruct regI_to_stkLHi(stackSlotL dst, iRegI src) %{
5346 effect(DEF dst, USE src);
5347 ins_cost(MEMORY_REF_COST*2);
5348 size(8);
5349 format %{ "STW $src,$dst.hi\t! long\n\t"
5350 "STW R_G0,$dst.lo" %}
5351 opcode(Assembler::stw_op3);
5352 ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, R_G0));
5353 ins_pipe(lstoreI_stk_reg);
5354 %}
5355
5356 instruct regL_to_stkD(stackSlotD dst, iRegL src) %{
5357 // No match rule to avoid chain rule match.
5358 effect(DEF dst, USE src);
5359 ins_cost(MEMORY_REF_COST);
5360 size(4);
5361 format %{ "STX $src,$dst\t! regL to stkD" %}
5362 opcode(Assembler::stx_op3);
5363 ins_encode(simple_form3_mem_reg( dst, src ) );
5364 ins_pipe(istore_stk_reg);
5365 %}
5366
5367 //---------- Chain stack slots between similar types --------
5368
5369 // Load integer from stack slot
5370 instruct stkI_to_regI( iRegI dst, stackSlotI src ) %{
5371 match(Set dst src);
5372 ins_cost(MEMORY_REF_COST);
5373
5374 size(4);
5375 format %{ "LDUW $src,$dst\t!stk" %}
5376 opcode(Assembler::lduw_op3);
5377 ins_encode(simple_form3_mem_reg( src, dst ) );
5378 ins_pipe(iload_mem);
5379 %}
5380
5381 // Store integer to stack slot
5382 instruct regI_to_stkI( stackSlotI dst, iRegI src ) %{
5383 match(Set dst src);
5384 ins_cost(MEMORY_REF_COST);
5385
5386 size(4);
5387 format %{ "STW $src,$dst\t!stk" %}
5388 opcode(Assembler::stw_op3);
5389 ins_encode(simple_form3_mem_reg( dst, src ) );
5390 ins_pipe(istore_mem_reg);
5391 %}
5392
5393 // Load long from stack slot
5394 instruct stkL_to_regL( iRegL dst, stackSlotL src ) %{
5395 match(Set dst src);
5396
5397 ins_cost(MEMORY_REF_COST);
5398 size(4);
5399 format %{ "LDX $src,$dst\t! long" %}
5400 opcode(Assembler::ldx_op3);
5401 ins_encode(simple_form3_mem_reg( src, dst ) );
5402 ins_pipe(iload_mem);
5403 %}
5404
5405 // Store long to stack slot
5406 instruct regL_to_stkL(stackSlotL dst, iRegL src) %{
5407 match(Set dst src);
5408
5409 ins_cost(MEMORY_REF_COST);
5410 size(4);
5411 format %{ "STX $src,$dst\t! long" %}
5412 opcode(Assembler::stx_op3);
5413 ins_encode(simple_form3_mem_reg( dst, src ) );
5414 ins_pipe(istore_mem_reg);
5415 %}
5416
5417 #ifdef _LP64
5418 // Load pointer from stack slot, 64-bit encoding
5419 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{
5420 match(Set dst src);
5421 ins_cost(MEMORY_REF_COST);
5422 size(4);
5423 format %{ "LDX $src,$dst\t!ptr" %}
5424 opcode(Assembler::ldx_op3);
5425 ins_encode(simple_form3_mem_reg( src, dst ) );
5426 ins_pipe(iload_mem);
5427 %}
5428
5429 // Store pointer to stack slot
5430 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{
5431 match(Set dst src);
5432 ins_cost(MEMORY_REF_COST);
5433 size(4);
5434 format %{ "STX $src,$dst\t!ptr" %}
5435 opcode(Assembler::stx_op3);
5436 ins_encode(simple_form3_mem_reg( dst, src ) );
5437 ins_pipe(istore_mem_reg);
5438 %}
5439 #else // _LP64
5440 // Load pointer from stack slot, 32-bit encoding
5441 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{
5442 match(Set dst src);
5443 ins_cost(MEMORY_REF_COST);
5444 format %{ "LDUW $src,$dst\t!ptr" %}
5445 opcode(Assembler::lduw_op3, Assembler::ldst_op);
5446 ins_encode(simple_form3_mem_reg( src, dst ) );
5447 ins_pipe(iload_mem);
5448 %}
5449
5450 // Store pointer to stack slot
5451 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{
5452 match(Set dst src);
5453 ins_cost(MEMORY_REF_COST);
5454 format %{ "STW $src,$dst\t!ptr" %}
5455 opcode(Assembler::stw_op3, Assembler::ldst_op);
5456 ins_encode(simple_form3_mem_reg( dst, src ) );
5457 ins_pipe(istore_mem_reg);
5458 %}
5459 #endif // _LP64
5460
5461 //------------Special Nop instructions for bundling - no match rules-----------
5462 // Nop using the A0 functional unit
5463 instruct Nop_A0() %{
5464 ins_cost(0);
5465
5466 format %{ "NOP ! Alu Pipeline" %}
5467 opcode(Assembler::or_op3, Assembler::arith_op);
5468 ins_encode( form2_nop() );
5469 ins_pipe(ialu_nop_A0);
5470 %}
5471
5472 // Nop using the A1 functional unit
5473 instruct Nop_A1( ) %{
5474 ins_cost(0);
5475
5476 format %{ "NOP ! Alu Pipeline" %}
5477 opcode(Assembler::or_op3, Assembler::arith_op);
5478 ins_encode( form2_nop() );
5479 ins_pipe(ialu_nop_A1);
5480 %}
5481
5482 // Nop using the memory functional unit
5483 instruct Nop_MS( ) %{
5484 ins_cost(0);
5485
5486 format %{ "NOP ! Memory Pipeline" %}
5487 ins_encode( emit_mem_nop );
5488 ins_pipe(mem_nop);
5489 %}
5490
5491 // Nop using the floating add functional unit
5492 instruct Nop_FA( ) %{
5493 ins_cost(0);
5494
5495 format %{ "NOP ! Floating Add Pipeline" %}
5496 ins_encode( emit_fadd_nop );
5497 ins_pipe(fadd_nop);
5498 %}
5499
5500 // Nop using the branch functional unit
5501 instruct Nop_BR( ) %{
5502 ins_cost(0);
5503
5504 format %{ "NOP ! Branch Pipeline" %}
5505 ins_encode( emit_br_nop );
5506 ins_pipe(br_nop);
5507 %}
5508
5509 //----------Load/Store/Move Instructions---------------------------------------
5510 //----------Load Instructions--------------------------------------------------
5511 // Load Byte (8bit signed)
5512 instruct loadB(iRegI dst, memory mem) %{
5513 match(Set dst (LoadB mem));
5514 ins_cost(MEMORY_REF_COST);
5515
5516 size(4);
5517 format %{ "LDSB $mem,$dst\t! byte" %}
5518 ins_encode %{
5519 __ ldsb($mem$$Address, $dst$$Register);
5520 %}
5521 ins_pipe(iload_mask_mem);
5522 %}
5523
5524 // Load Byte (8bit signed) into a Long Register
5525 instruct loadB2L(iRegL dst, memory mem) %{
5526 match(Set dst (ConvI2L (LoadB mem)));
5527 ins_cost(MEMORY_REF_COST);
5528
5529 size(4);
5530 format %{ "LDSB $mem,$dst\t! byte -> long" %}
5531 ins_encode %{
5532 __ ldsb($mem$$Address, $dst$$Register);
5533 %}
5534 ins_pipe(iload_mask_mem);
5535 %}
5536
5537 // Load Unsigned Byte (8bit UNsigned) into an int reg
5538 instruct loadUB(iRegI dst, memory mem) %{
5539 match(Set dst (LoadUB mem));
5540 ins_cost(MEMORY_REF_COST);
5541
5542 size(4);
5543 format %{ "LDUB $mem,$dst\t! ubyte" %}
5544 ins_encode %{
5545 __ ldub($mem$$Address, $dst$$Register);
5546 %}
5547 ins_pipe(iload_mask_mem);
5548 %}
5549
5550 // Load Unsigned Byte (8bit UNsigned) into a Long Register
5551 instruct loadUB2L(iRegL dst, memory mem) %{
5552 match(Set dst (ConvI2L (LoadUB mem)));
5553 ins_cost(MEMORY_REF_COST);
5554
5555 size(4);
5556 format %{ "LDUB $mem,$dst\t! ubyte -> long" %}
5557 ins_encode %{
5558 __ ldub($mem$$Address, $dst$$Register);
5559 %}
5560 ins_pipe(iload_mask_mem);
5561 %}
5562
5563 // Load Short (16bit signed)
5564 instruct loadS(iRegI dst, memory mem) %{
5565 match(Set dst (LoadS mem));
5566 ins_cost(MEMORY_REF_COST);
5567
5568 size(4);
5569 format %{ "LDSH $mem,$dst\t! short" %}
5570 ins_encode %{
5571 __ ldsh($mem$$Address, $dst$$Register);
5572 %}
5573 ins_pipe(iload_mask_mem);
5574 %}
5575
5576 // Load Short (16 bit signed) to Byte (8 bit signed)
5577 instruct loadS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
5578 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
5579 ins_cost(MEMORY_REF_COST);
5580
5581 size(4);
5582
5583 format %{ "LDSB $mem+1,$dst\t! short -> byte" %}
5584 ins_encode %{
5585 __ ldsb($mem$$Address, $dst$$Register, 1);
5586 %}
5587 ins_pipe(iload_mask_mem);
5588 %}
5589
5590 // Load Short (16bit signed) into a Long Register
5591 instruct loadS2L(iRegL dst, memory mem) %{
5592 match(Set dst (ConvI2L (LoadS mem)));
5593 ins_cost(MEMORY_REF_COST);
5594
5595 size(4);
5596 format %{ "LDSH $mem,$dst\t! short -> long" %}
5597 ins_encode %{
5598 __ ldsh($mem$$Address, $dst$$Register);
5599 %}
5600 ins_pipe(iload_mask_mem);
5601 %}
5602
5603 // Load Unsigned Short/Char (16bit UNsigned)
5604 instruct loadUS(iRegI dst, memory mem) %{
5605 match(Set dst (LoadUS mem));
5606 ins_cost(MEMORY_REF_COST);
5607
5608 size(4);
5609 format %{ "LDUH $mem,$dst\t! ushort/char" %}
5610 ins_encode %{
5611 __ lduh($mem$$Address, $dst$$Register);
5612 %}
5613 ins_pipe(iload_mask_mem);
5614 %}
5615
5616 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
5617 instruct loadUS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
5618 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
5619 ins_cost(MEMORY_REF_COST);
5620
5621 size(4);
5622 format %{ "LDSB $mem+1,$dst\t! ushort -> byte" %}
5623 ins_encode %{
5624 __ ldsb($mem$$Address, $dst$$Register, 1);
5625 %}
5626 ins_pipe(iload_mask_mem);
5627 %}
5628
5629 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register
5630 instruct loadUS2L(iRegL dst, memory mem) %{
5631 match(Set dst (ConvI2L (LoadUS mem)));
5632 ins_cost(MEMORY_REF_COST);
5633
5634 size(4);
5635 format %{ "LDUH $mem,$dst\t! ushort/char -> long" %}
5636 ins_encode %{
5637 __ lduh($mem$$Address, $dst$$Register);
5638 %}
5639 ins_pipe(iload_mask_mem);
5640 %}
5641
5642 // Load Integer
5643 instruct loadI(iRegI dst, memory mem) %{
5644 match(Set dst (LoadI mem));
5645 ins_cost(MEMORY_REF_COST);
5646
5647 size(4);
5648 format %{ "LDUW $mem,$dst\t! int" %}
5649 ins_encode %{
5650 __ lduw($mem$$Address, $dst$$Register);
5651 %}
5652 ins_pipe(iload_mem);
5653 %}
5654
5655 // Load Integer to Byte (8 bit signed)
5656 instruct loadI2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
5657 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
5658 ins_cost(MEMORY_REF_COST);
5659
5660 size(4);
5661
5662 format %{ "LDSB $mem+3,$dst\t! int -> byte" %}
5663 ins_encode %{
5664 __ ldsb($mem$$Address, $dst$$Register, 3);
5665 %}
5666 ins_pipe(iload_mask_mem);
5667 %}
5668
5669 // Load Integer to Unsigned Byte (8 bit UNsigned)
5670 instruct loadI2UB(iRegI dst, indOffset13m7 mem, immI_255 mask) %{
5671 match(Set dst (AndI (LoadI mem) mask));
5672 ins_cost(MEMORY_REF_COST);
5673
5674 size(4);
5675
5676 format %{ "LDUB $mem+3,$dst\t! int -> ubyte" %}
5677 ins_encode %{
5678 __ ldub($mem$$Address, $dst$$Register, 3);
5679 %}
5680 ins_pipe(iload_mask_mem);
5681 %}
5682
5683 // Load Integer to Short (16 bit signed)
5684 instruct loadI2S(iRegI dst, indOffset13m7 mem, immI_16 sixteen) %{
5685 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
5686 ins_cost(MEMORY_REF_COST);
5687
5688 size(4);
5689
5690 format %{ "LDSH $mem+2,$dst\t! int -> short" %}
5691 ins_encode %{
5692 __ ldsh($mem$$Address, $dst$$Register, 2);
5693 %}
5694 ins_pipe(iload_mask_mem);
5695 %}
5696
5697 // Load Integer to Unsigned Short (16 bit UNsigned)
5698 instruct loadI2US(iRegI dst, indOffset13m7 mem, immI_65535 mask) %{
5699 match(Set dst (AndI (LoadI mem) mask));
5700 ins_cost(MEMORY_REF_COST);
5701
5702 size(4);
5703
5704 format %{ "LDUH $mem+2,$dst\t! int -> ushort/char" %}
5705 ins_encode %{
5706 __ lduh($mem$$Address, $dst$$Register, 2);
5707 %}
5708 ins_pipe(iload_mask_mem);
5709 %}
5710
5711 // Load Integer into a Long Register
5712 instruct loadI2L(iRegL dst, memory mem) %{
5713 match(Set dst (ConvI2L (LoadI mem)));
5714 ins_cost(MEMORY_REF_COST);
5715
5716 size(4);
5717 format %{ "LDSW $mem,$dst\t! int -> long" %}
5718 ins_encode %{
5719 __ ldsw($mem$$Address, $dst$$Register);
5720 %}
5721 ins_pipe(iload_mem);
5722 %}
5723
5724 // Load Unsigned Integer into a Long Register
5725 instruct loadUI2L(iRegL dst, memory mem) %{
5726 match(Set dst (LoadUI2L mem));
5727 ins_cost(MEMORY_REF_COST);
5728
5729 size(4);
5730 format %{ "LDUW $mem,$dst\t! uint -> long" %}
5731 ins_encode %{
5732 __ lduw($mem$$Address, $dst$$Register);
5733 %}
5734 ins_pipe(iload_mem);
5735 %}
5736
5737 // Load Long - aligned
5738 instruct loadL(iRegL dst, memory mem ) %{
5739 match(Set dst (LoadL mem));
5740 ins_cost(MEMORY_REF_COST);
5741
5742 size(4);
5743 format %{ "LDX $mem,$dst\t! long" %}
5744 ins_encode %{
5745 __ ldx($mem$$Address, $dst$$Register);
5746 %}
5747 ins_pipe(iload_mem);
5748 %}
5749
5750 // Load Long - UNaligned
5751 instruct loadL_unaligned(iRegL dst, memory mem, o7RegI tmp) %{
5752 match(Set dst (LoadL_unaligned mem));
5753 effect(KILL tmp);
5754 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST);
5755 size(16);
5756 format %{ "LDUW $mem+4,R_O7\t! misaligned long\n"
5757 "\tLDUW $mem ,$dst\n"
5758 "\tSLLX #32, $dst, $dst\n"
5759 "\tOR $dst, R_O7, $dst" %}
5760 opcode(Assembler::lduw_op3);
5761 ins_encode(form3_mem_reg_long_unaligned_marshal( mem, dst ));
5762 ins_pipe(iload_mem);
5763 %}
5764
5765 // Load Aligned Packed Byte into a Double Register
5766 instruct loadA8B(regD dst, memory mem) %{
5767 match(Set dst (Load8B mem));
5768 ins_cost(MEMORY_REF_COST);
5769 size(4);
5770 format %{ "LDDF $mem,$dst\t! packed8B" %}
5771 opcode(Assembler::lddf_op3);
5772 ins_encode(simple_form3_mem_reg( mem, dst ) );
5773 ins_pipe(floadD_mem);
5774 %}
5775
5776 // Load Aligned Packed Char into a Double Register
5777 instruct loadA4C(regD dst, memory mem) %{
5778 match(Set dst (Load4C mem));
5779 ins_cost(MEMORY_REF_COST);
5780 size(4);
5781 format %{ "LDDF $mem,$dst\t! packed4C" %}
5782 opcode(Assembler::lddf_op3);
5783 ins_encode(simple_form3_mem_reg( mem, dst ) );
5784 ins_pipe(floadD_mem);
5785 %}
5786
5787 // Load Aligned Packed Short into a Double Register
5788 instruct loadA4S(regD dst, memory mem) %{
5789 match(Set dst (Load4S mem));
5790 ins_cost(MEMORY_REF_COST);
5791 size(4);
5792 format %{ "LDDF $mem,$dst\t! packed4S" %}
5793 opcode(Assembler::lddf_op3);
5794 ins_encode(simple_form3_mem_reg( mem, dst ) );
5795 ins_pipe(floadD_mem);
5796 %}
5797
5798 // Load Aligned Packed Int into a Double Register
5799 instruct loadA2I(regD dst, memory mem) %{
5800 match(Set dst (Load2I mem));
5801 ins_cost(MEMORY_REF_COST);
5802 size(4);
5803 format %{ "LDDF $mem,$dst\t! packed2I" %}
5804 opcode(Assembler::lddf_op3);
5805 ins_encode(simple_form3_mem_reg( mem, dst ) );
5806 ins_pipe(floadD_mem);
5807 %}
5808
5809 // Load Range
5810 instruct loadRange(iRegI dst, memory mem) %{
5811 match(Set dst (LoadRange mem));
5812 ins_cost(MEMORY_REF_COST);
5813
5814 size(4);
5815 format %{ "LDUW $mem,$dst\t! range" %}
5816 opcode(Assembler::lduw_op3);
5817 ins_encode(simple_form3_mem_reg( mem, dst ) );
5818 ins_pipe(iload_mem);
5819 %}
5820
5821 // Load Integer into %f register (for fitos/fitod)
5822 instruct loadI_freg(regF dst, memory mem) %{
5823 match(Set dst (LoadI mem));
5824 ins_cost(MEMORY_REF_COST);
5825 size(4);
5826
5827 format %{ "LDF $mem,$dst\t! for fitos/fitod" %}
5828 opcode(Assembler::ldf_op3);
5829 ins_encode(simple_form3_mem_reg( mem, dst ) );
5830 ins_pipe(floadF_mem);
5831 %}
5832
5833 // Load Pointer
5834 instruct loadP(iRegP dst, memory mem) %{
5835 match(Set dst (LoadP mem));
5836 ins_cost(MEMORY_REF_COST);
5837 size(4);
5838
5839 #ifndef _LP64
5840 format %{ "LDUW $mem,$dst\t! ptr" %}
5841 ins_encode %{
5842 __ lduw($mem$$Address, $dst$$Register);
5843 %}
5844 #else
5845 format %{ "LDX $mem,$dst\t! ptr" %}
5846 ins_encode %{
5847 __ ldx($mem$$Address, $dst$$Register);
5848 %}
5849 #endif
5850 ins_pipe(iload_mem);
5851 %}
5852
5853 // Load Compressed Pointer
5854 instruct loadN(iRegN dst, memory mem) %{
5855 match(Set dst (LoadN mem));
5856 ins_cost(MEMORY_REF_COST);
5857 size(4);
5858
5859 format %{ "LDUW $mem,$dst\t! compressed ptr" %}
5860 ins_encode %{
5861 __ lduw($mem$$Address, $dst$$Register);
5862 %}
5863 ins_pipe(iload_mem);
5864 %}
5865
5866 // Load Klass Pointer
5867 instruct loadKlass(iRegP dst, memory mem) %{
5868 match(Set dst (LoadKlass mem));
5869 ins_cost(MEMORY_REF_COST);
5870 size(4);
5871
5872 #ifndef _LP64
5873 format %{ "LDUW $mem,$dst\t! klass ptr" %}
5874 ins_encode %{
5875 __ lduw($mem$$Address, $dst$$Register);
5876 %}
5877 #else
5878 format %{ "LDX $mem,$dst\t! klass ptr" %}
5879 ins_encode %{
5880 __ ldx($mem$$Address, $dst$$Register);
5881 %}
5882 #endif
5883 ins_pipe(iload_mem);
5884 %}
5885
5886 // Load narrow Klass Pointer
5887 instruct loadNKlass(iRegN dst, memory mem) %{
5888 match(Set dst (LoadNKlass mem));
5889 ins_cost(MEMORY_REF_COST);
5890 size(4);
5891
5892 format %{ "LDUW $mem,$dst\t! compressed klass ptr" %}
5893 ins_encode %{
5894 __ lduw($mem$$Address, $dst$$Register);
5895 %}
5896 ins_pipe(iload_mem);
5897 %}
5898
5899 // Load Double
5900 instruct loadD(regD dst, memory mem) %{
5901 match(Set dst (LoadD mem));
5902 ins_cost(MEMORY_REF_COST);
5903
5904 size(4);
5905 format %{ "LDDF $mem,$dst" %}
5906 opcode(Assembler::lddf_op3);
5907 ins_encode(simple_form3_mem_reg( mem, dst ) );
5908 ins_pipe(floadD_mem);
5909 %}
5910
5911 // Load Double - UNaligned
5912 instruct loadD_unaligned(regD_low dst, memory mem ) %{
5913 match(Set dst (LoadD_unaligned mem));
5914 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST);
5915 size(8);
5916 format %{ "LDF $mem ,$dst.hi\t! misaligned double\n"
5917 "\tLDF $mem+4,$dst.lo\t!" %}
5918 opcode(Assembler::ldf_op3);
5919 ins_encode( form3_mem_reg_double_unaligned( mem, dst ));
5920 ins_pipe(iload_mem);
5921 %}
5922
5923 // Load Float
5924 instruct loadF(regF dst, memory mem) %{
5925 match(Set dst (LoadF mem));
5926 ins_cost(MEMORY_REF_COST);
5927
5928 size(4);
5929 format %{ "LDF $mem,$dst" %}
5930 opcode(Assembler::ldf_op3);
5931 ins_encode(simple_form3_mem_reg( mem, dst ) );
5932 ins_pipe(floadF_mem);
5933 %}
5934
5935 // Load Constant
5936 instruct loadConI( iRegI dst, immI src ) %{
5937 match(Set dst src);
5938 ins_cost(DEFAULT_COST * 3/2);
5939 format %{ "SET $src,$dst" %}
5940 ins_encode( Set32(src, dst) );
5941 ins_pipe(ialu_hi_lo_reg);
5942 %}
5943
5944 instruct loadConI13( iRegI dst, immI13 src ) %{
5945 match(Set dst src);
5946
5947 size(4);
5948 format %{ "MOV $src,$dst" %}
5949 ins_encode( Set13( src, dst ) );
5950 ins_pipe(ialu_imm);
5951 %}
5952
5953 instruct loadConP(iRegP dst, immP src) %{
5954 match(Set dst src);
5955 ins_cost(DEFAULT_COST * 3/2);
5956 format %{ "SET $src,$dst\t!ptr" %}
5957 // This rule does not use "expand" unlike loadConI because then
5958 // the result type is not known to be an Oop. An ADLC
5959 // enhancement will be needed to make that work - not worth it!
5960
5961 ins_encode( SetPtr( src, dst ) );
5962 ins_pipe(loadConP);
5963
5964 %}
5965
5966 instruct loadConP0(iRegP dst, immP0 src) %{
5967 match(Set dst src);
5968
5969 size(4);
5970 format %{ "CLR $dst\t!ptr" %}
5971 ins_encode( SetNull( dst ) );
5972 ins_pipe(ialu_imm);
5973 %}
5974
5975 instruct loadConP_poll(iRegP dst, immP_poll src) %{
5976 match(Set dst src);
5977 ins_cost(DEFAULT_COST);
5978 format %{ "SET $src,$dst\t!ptr" %}
5979 ins_encode %{
5980 AddressLiteral polling_page(os::get_polling_page());
5981 __ sethi(polling_page, reg_to_register_object($dst$$reg));
5982 %}
5983 ins_pipe(loadConP_poll);
5984 %}
5985
5986 instruct loadConN0(iRegN dst, immN0 src) %{
5987 match(Set dst src);
5988
5989 size(4);
5990 format %{ "CLR $dst\t! compressed NULL ptr" %}
5991 ins_encode( SetNull( dst ) );
5992 ins_pipe(ialu_imm);
5993 %}
5994
5995 instruct loadConN(iRegN dst, immN src) %{
5996 match(Set dst src);
5997 ins_cost(DEFAULT_COST * 3/2);
5998 format %{ "SET $src,$dst\t! compressed ptr" %}
5999 ins_encode %{
6000 Register dst = $dst$$Register;
6001 __ set_narrow_oop((jobject)$src$$constant, dst);
6002 %}
6003 ins_pipe(ialu_hi_lo_reg);
6004 %}
6005
6006 instruct loadConL(iRegL dst, immL src, o7RegL tmp) %{
6007 // %%% maybe this should work like loadConD
6008 match(Set dst src);
6009 effect(KILL tmp);
6010 ins_cost(DEFAULT_COST * 4);
6011 format %{ "SET64 $src,$dst KILL $tmp\t! long" %}
6012 ins_encode( LdImmL(src, dst, tmp) );
6013 ins_pipe(loadConL);
6014 %}
6015
6016 instruct loadConL0( iRegL dst, immL0 src ) %{
6017 match(Set dst src);
6018 ins_cost(DEFAULT_COST);
6019 size(4);
6020 format %{ "CLR $dst\t! long" %}
6021 ins_encode( Set13( src, dst ) );
6022 ins_pipe(ialu_imm);
6023 %}
6024
6025 instruct loadConL13( iRegL dst, immL13 src ) %{
6026 match(Set dst src);
6027 ins_cost(DEFAULT_COST * 2);
6028
6029 size(4);
6030 format %{ "MOV $src,$dst\t! long" %}
6031 ins_encode( Set13( src, dst ) );
6032 ins_pipe(ialu_imm);
6033 %}
6034
6035 instruct loadConF(regF dst, immF src, o7RegP tmp) %{
6036 match(Set dst src);
6037 effect(KILL tmp);
6038
6039 #ifdef _LP64
6040 size(8*4);
6041 #else
6042 size(2*4);
6043 #endif
6044
6045 format %{ "SETHI hi(&$src),$tmp\t!get float $src from table\n\t"
6046 "LDF [$tmp+lo(&$src)],$dst" %}
6047 ins_encode %{
6048 address float_address = __ float_constant($src$$constant);
6049 RelocationHolder rspec = internal_word_Relocation::spec(float_address);
6050 AddressLiteral addrlit(float_address, rspec);
6051
6052 __ sethi(addrlit, $tmp$$Register);
6053 __ ldf(FloatRegisterImpl::S, $tmp$$Register, addrlit.low10(), $dst$$FloatRegister, rspec);
6054 %}
6055 ins_pipe(loadConFD);
6056 %}
6057
6058 instruct loadConD(regD dst, immD src, o7RegP tmp) %{
6059 match(Set dst src);
6060 effect(KILL tmp);
6061
6062 #ifdef _LP64
6063 size(8*4);
6064 #else
6065 size(2*4);
6066 #endif
6067
6068 format %{ "SETHI hi(&$src),$tmp\t!get double $src from table\n\t"
6069 "LDDF [$tmp+lo(&$src)],$dst" %}
6070 ins_encode %{
6071 address double_address = __ double_constant($src$$constant);
6072 RelocationHolder rspec = internal_word_Relocation::spec(double_address);
6073 AddressLiteral addrlit(double_address, rspec);
6074
6075 __ sethi(addrlit, $tmp$$Register);
6076 // XXX This is a quick fix for 6833573.
6077 //__ ldf(FloatRegisterImpl::D, $tmp$$Register, addrlit.low10(), $dst$$FloatRegister, rspec);
6078 __ ldf(FloatRegisterImpl::D, $tmp$$Register, addrlit.low10(), as_DoubleFloatRegister($dst$$reg), rspec);
6079 %}
6080 ins_pipe(loadConFD);
6081 %}
6082
6083 // Prefetch instructions.
6084 // Must be safe to execute with invalid address (cannot fault).
6085
6086 instruct prefetchr( memory mem ) %{
6087 match( PrefetchRead mem );
6088 ins_cost(MEMORY_REF_COST);
6089
6090 format %{ "PREFETCH $mem,0\t! Prefetch read-many" %}
6091 opcode(Assembler::prefetch_op3);
6092 ins_encode( form3_mem_prefetch_read( mem ) );
6093 ins_pipe(iload_mem);
6094 %}
6095
6096 instruct prefetchw( memory mem ) %{
6097 match( PrefetchWrite mem );
6098 ins_cost(MEMORY_REF_COST);
6099
6100 format %{ "PREFETCH $mem,2\t! Prefetch write-many (and read)" %}
6101 opcode(Assembler::prefetch_op3);
6102 ins_encode( form3_mem_prefetch_write( mem ) );
6103 ins_pipe(iload_mem);
6104 %}
6105
6106
6107 //----------Store Instructions-------------------------------------------------
6108 // Store Byte
6109 instruct storeB(memory mem, iRegI src) %{
6110 match(Set mem (StoreB mem src));
6111 ins_cost(MEMORY_REF_COST);
6112
6113 size(4);
6114 format %{ "STB $src,$mem\t! byte" %}
6115 opcode(Assembler::stb_op3);
6116 ins_encode(simple_form3_mem_reg( mem, src ) );
6117 ins_pipe(istore_mem_reg);
6118 %}
6119
6120 instruct storeB0(memory mem, immI0 src) %{
6121 match(Set mem (StoreB mem src));
6122 ins_cost(MEMORY_REF_COST);
6123
6124 size(4);
6125 format %{ "STB $src,$mem\t! byte" %}
6126 opcode(Assembler::stb_op3);
6127 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6128 ins_pipe(istore_mem_zero);
6129 %}
6130
6131 instruct storeCM0(memory mem, immI0 src) %{
6132 match(Set mem (StoreCM mem src));
6133 ins_cost(MEMORY_REF_COST);
6134
6135 size(4);
6136 format %{ "STB $src,$mem\t! CMS card-mark byte 0" %}
6137 opcode(Assembler::stb_op3);
6138 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6139 ins_pipe(istore_mem_zero);
6140 %}
6141
6142 // Store Char/Short
6143 instruct storeC(memory mem, iRegI src) %{
6144 match(Set mem (StoreC mem src));
6145 ins_cost(MEMORY_REF_COST);
6146
6147 size(4);
6148 format %{ "STH $src,$mem\t! short" %}
6149 opcode(Assembler::sth_op3);
6150 ins_encode(simple_form3_mem_reg( mem, src ) );
6151 ins_pipe(istore_mem_reg);
6152 %}
6153
6154 instruct storeC0(memory mem, immI0 src) %{
6155 match(Set mem (StoreC mem src));
6156 ins_cost(MEMORY_REF_COST);
6157
6158 size(4);
6159 format %{ "STH $src,$mem\t! short" %}
6160 opcode(Assembler::sth_op3);
6161 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6162 ins_pipe(istore_mem_zero);
6163 %}
6164
6165 // Store Integer
6166 instruct storeI(memory mem, iRegI src) %{
6167 match(Set mem (StoreI mem src));
6168 ins_cost(MEMORY_REF_COST);
6169
6170 size(4);
6171 format %{ "STW $src,$mem" %}
6172 opcode(Assembler::stw_op3);
6173 ins_encode(simple_form3_mem_reg( mem, src ) );
6174 ins_pipe(istore_mem_reg);
6175 %}
6176
6177 // Store Long
6178 instruct storeL(memory mem, iRegL src) %{
6179 match(Set mem (StoreL mem src));
6180 ins_cost(MEMORY_REF_COST);
6181 size(4);
6182 format %{ "STX $src,$mem\t! long" %}
6183 opcode(Assembler::stx_op3);
6184 ins_encode(simple_form3_mem_reg( mem, src ) );
6185 ins_pipe(istore_mem_reg);
6186 %}
6187
6188 instruct storeI0(memory mem, immI0 src) %{
6189 match(Set mem (StoreI mem src));
6190 ins_cost(MEMORY_REF_COST);
6191
6192 size(4);
6193 format %{ "STW $src,$mem" %}
6194 opcode(Assembler::stw_op3);
6195 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6196 ins_pipe(istore_mem_zero);
6197 %}
6198
6199 instruct storeL0(memory mem, immL0 src) %{
6200 match(Set mem (StoreL mem src));
6201 ins_cost(MEMORY_REF_COST);
6202
6203 size(4);
6204 format %{ "STX $src,$mem" %}
6205 opcode(Assembler::stx_op3);
6206 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6207 ins_pipe(istore_mem_zero);
6208 %}
6209
6210 // Store Integer from float register (used after fstoi)
6211 instruct storeI_Freg(memory mem, regF src) %{
6212 match(Set mem (StoreI mem src));
6213 ins_cost(MEMORY_REF_COST);
6214
6215 size(4);
6216 format %{ "STF $src,$mem\t! after fstoi/fdtoi" %}
6217 opcode(Assembler::stf_op3);
6218 ins_encode(simple_form3_mem_reg( mem, src ) );
6219 ins_pipe(fstoreF_mem_reg);
6220 %}
6221
6222 // Store Pointer
6223 instruct storeP(memory dst, sp_ptr_RegP src) %{
6224 match(Set dst (StoreP dst src));
6225 ins_cost(MEMORY_REF_COST);
6226 size(4);
6227
6228 #ifndef _LP64
6229 format %{ "STW $src,$dst\t! ptr" %}
6230 opcode(Assembler::stw_op3, 0, REGP_OP);
6231 #else
6232 format %{ "STX $src,$dst\t! ptr" %}
6233 opcode(Assembler::stx_op3, 0, REGP_OP);
6234 #endif
6235 ins_encode( form3_mem_reg( dst, src ) );
6236 ins_pipe(istore_mem_spORreg);
6237 %}
6238
6239 instruct storeP0(memory dst, immP0 src) %{
6240 match(Set dst (StoreP dst src));
6241 ins_cost(MEMORY_REF_COST);
6242 size(4);
6243
6244 #ifndef _LP64
6245 format %{ "STW $src,$dst\t! ptr" %}
6246 opcode(Assembler::stw_op3, 0, REGP_OP);
6247 #else
6248 format %{ "STX $src,$dst\t! ptr" %}
6249 opcode(Assembler::stx_op3, 0, REGP_OP);
6250 #endif
6251 ins_encode( form3_mem_reg( dst, R_G0 ) );
6252 ins_pipe(istore_mem_zero);
6253 %}
6254
6255 // Store Compressed Pointer
6256 instruct storeN(memory dst, iRegN src) %{
6257 match(Set dst (StoreN dst src));
6258 ins_cost(MEMORY_REF_COST);
6259 size(4);
6260
6261 format %{ "STW $src,$dst\t! compressed ptr" %}
6262 ins_encode %{
6263 Register base = as_Register($dst$$base);
6264 Register index = as_Register($dst$$index);
6265 Register src = $src$$Register;
6266 if (index != G0) {
6267 __ stw(src, base, index);
6268 } else {
6269 __ stw(src, base, $dst$$disp);
6270 }
6271 %}
6272 ins_pipe(istore_mem_spORreg);
6273 %}
6274
6275 instruct storeN0(memory dst, immN0 src) %{
6276 match(Set dst (StoreN dst src));
6277 ins_cost(MEMORY_REF_COST);
6278 size(4);
6279
6280 format %{ "STW $src,$dst\t! compressed ptr" %}
6281 ins_encode %{
6282 Register base = as_Register($dst$$base);
6283 Register index = as_Register($dst$$index);
6284 if (index != G0) {
6285 __ stw(0, base, index);
6286 } else {
6287 __ stw(0, base, $dst$$disp);
6288 }
6289 %}
6290 ins_pipe(istore_mem_zero);
6291 %}
6292
6293 // Store Double
6294 instruct storeD( memory mem, regD src) %{
6295 match(Set mem (StoreD mem src));
6296 ins_cost(MEMORY_REF_COST);
6297
6298 size(4);
6299 format %{ "STDF $src,$mem" %}
6300 opcode(Assembler::stdf_op3);
6301 ins_encode(simple_form3_mem_reg( mem, src ) );
6302 ins_pipe(fstoreD_mem_reg);
6303 %}
6304
6305 instruct storeD0( memory mem, immD0 src) %{
6306 match(Set mem (StoreD mem src));
6307 ins_cost(MEMORY_REF_COST);
6308
6309 size(4);
6310 format %{ "STX $src,$mem" %}
6311 opcode(Assembler::stx_op3);
6312 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6313 ins_pipe(fstoreD_mem_zero);
6314 %}
6315
6316 // Store Float
6317 instruct storeF( memory mem, regF src) %{
6318 match(Set mem (StoreF mem src));
6319 ins_cost(MEMORY_REF_COST);
6320
6321 size(4);
6322 format %{ "STF $src,$mem" %}
6323 opcode(Assembler::stf_op3);
6324 ins_encode(simple_form3_mem_reg( mem, src ) );
6325 ins_pipe(fstoreF_mem_reg);
6326 %}
6327
6328 instruct storeF0( memory mem, immF0 src) %{
6329 match(Set mem (StoreF mem src));
6330 ins_cost(MEMORY_REF_COST);
6331
6332 size(4);
6333 format %{ "STW $src,$mem\t! storeF0" %}
6334 opcode(Assembler::stw_op3);
6335 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6336 ins_pipe(fstoreF_mem_zero);
6337 %}
6338
6339 // Store Aligned Packed Bytes in Double register to memory
6340 instruct storeA8B(memory mem, regD src) %{
6341 match(Set mem (Store8B mem src));
6342 ins_cost(MEMORY_REF_COST);
6343 size(4);
6344 format %{ "STDF $src,$mem\t! packed8B" %}
6345 opcode(Assembler::stdf_op3);
6346 ins_encode(simple_form3_mem_reg( mem, src ) );
6347 ins_pipe(fstoreD_mem_reg);
6348 %}
6349
6350 // Convert oop pointer into compressed form
6351 instruct encodeHeapOop(iRegN dst, iRegP src) %{
6352 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
6353 match(Set dst (EncodeP src));
6354 format %{ "encode_heap_oop $src, $dst" %}
6355 ins_encode %{
6356 __ encode_heap_oop($src$$Register, $dst$$Register);
6357 %}
6358 ins_pipe(ialu_reg);
6359 %}
6360
6361 instruct encodeHeapOop_not_null(iRegN dst, iRegP src) %{
6362 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
6363 match(Set dst (EncodeP src));
6364 format %{ "encode_heap_oop_not_null $src, $dst" %}
6365 ins_encode %{
6366 __ encode_heap_oop_not_null($src$$Register, $dst$$Register);
6367 %}
6368 ins_pipe(ialu_reg);
6369 %}
6370
6371 instruct decodeHeapOop(iRegP dst, iRegN src) %{
6372 predicate(n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull &&
6373 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant);
6374 match(Set dst (DecodeN src));
6375 format %{ "decode_heap_oop $src, $dst" %}
6376 ins_encode %{
6377 __ decode_heap_oop($src$$Register, $dst$$Register);
6378 %}
6379 ins_pipe(ialu_reg);
6380 %}
6381
6382 instruct decodeHeapOop_not_null(iRegP dst, iRegN src) %{
6383 predicate(n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull ||
6384 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant);
6385 match(Set dst (DecodeN src));
6386 format %{ "decode_heap_oop_not_null $src, $dst" %}
6387 ins_encode %{
6388 __ decode_heap_oop_not_null($src$$Register, $dst$$Register);
6389 %}
6390 ins_pipe(ialu_reg);
6391 %}
6392
6393
6394 // Store Zero into Aligned Packed Bytes
6395 instruct storeA8B0(memory mem, immI0 zero) %{
6396 match(Set mem (Store8B mem zero));
6397 ins_cost(MEMORY_REF_COST);
6398 size(4);
6399 format %{ "STX $zero,$mem\t! packed8B" %}
6400 opcode(Assembler::stx_op3);
6401 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6402 ins_pipe(fstoreD_mem_zero);
6403 %}
6404
6405 // Store Aligned Packed Chars/Shorts in Double register to memory
6406 instruct storeA4C(memory mem, regD src) %{
6407 match(Set mem (Store4C mem src));
6408 ins_cost(MEMORY_REF_COST);
6409 size(4);
6410 format %{ "STDF $src,$mem\t! packed4C" %}
6411 opcode(Assembler::stdf_op3);
6412 ins_encode(simple_form3_mem_reg( mem, src ) );
6413 ins_pipe(fstoreD_mem_reg);
6414 %}
6415
6416 // Store Zero into Aligned Packed Chars/Shorts
6417 instruct storeA4C0(memory mem, immI0 zero) %{
6418 match(Set mem (Store4C mem (Replicate4C zero)));
6419 ins_cost(MEMORY_REF_COST);
6420 size(4);
6421 format %{ "STX $zero,$mem\t! packed4C" %}
6422 opcode(Assembler::stx_op3);
6423 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6424 ins_pipe(fstoreD_mem_zero);
6425 %}
6426
6427 // Store Aligned Packed Ints in Double register to memory
6428 instruct storeA2I(memory mem, regD src) %{
6429 match(Set mem (Store2I mem src));
6430 ins_cost(MEMORY_REF_COST);
6431 size(4);
6432 format %{ "STDF $src,$mem\t! packed2I" %}
6433 opcode(Assembler::stdf_op3);
6434 ins_encode(simple_form3_mem_reg( mem, src ) );
6435 ins_pipe(fstoreD_mem_reg);
6436 %}
6437
6438 // Store Zero into Aligned Packed Ints
6439 instruct storeA2I0(memory mem, immI0 zero) %{
6440 match(Set mem (Store2I mem zero));
6441 ins_cost(MEMORY_REF_COST);
6442 size(4);
6443 format %{ "STX $zero,$mem\t! packed2I" %}
6444 opcode(Assembler::stx_op3);
6445 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6446 ins_pipe(fstoreD_mem_zero);
6447 %}
6448
6449
6450 //----------MemBar Instructions-----------------------------------------------
6451 // Memory barrier flavors
6452
6453 instruct membar_acquire() %{
6454 match(MemBarAcquire);
6455 ins_cost(4*MEMORY_REF_COST);
6456
6457 size(0);
6458 format %{ "MEMBAR-acquire" %}
6459 ins_encode( enc_membar_acquire );
6460 ins_pipe(long_memory_op);
6461 %}
6462
6463 instruct membar_acquire_lock() %{
6464 match(MemBarAcquire);
6465 predicate(Matcher::prior_fast_lock(n));
6466 ins_cost(0);
6467
6468 size(0);
6469 format %{ "!MEMBAR-acquire (CAS in prior FastLock so empty encoding)" %}
6470 ins_encode( );
6471 ins_pipe(empty);
6472 %}
6473
6474 instruct membar_release() %{
6475 match(MemBarRelease);
6476 ins_cost(4*MEMORY_REF_COST);
6477
6478 size(0);
6479 format %{ "MEMBAR-release" %}
6480 ins_encode( enc_membar_release );
6481 ins_pipe(long_memory_op);
6482 %}
6483
6484 instruct membar_release_lock() %{
6485 match(MemBarRelease);
6486 predicate(Matcher::post_fast_unlock(n));
6487 ins_cost(0);
6488
6489 size(0);
6490 format %{ "!MEMBAR-release (CAS in succeeding FastUnlock so empty encoding)" %}
6491 ins_encode( );
6492 ins_pipe(empty);
6493 %}
6494
6495 instruct membar_volatile() %{
6496 match(MemBarVolatile);
6497 ins_cost(4*MEMORY_REF_COST);
6498
6499 size(4);
6500 format %{ "MEMBAR-volatile" %}
6501 ins_encode( enc_membar_volatile );
6502 ins_pipe(long_memory_op);
6503 %}
6504
6505 instruct unnecessary_membar_volatile() %{
6506 match(MemBarVolatile);
6507 predicate(Matcher::post_store_load_barrier(n));
6508 ins_cost(0);
6509
6510 size(0);
6511 format %{ "!MEMBAR-volatile (unnecessary so empty encoding)" %}
6512 ins_encode( );
6513 ins_pipe(empty);
6514 %}
6515
6516 //----------Register Move Instructions-----------------------------------------
6517 instruct roundDouble_nop(regD dst) %{
6518 match(Set dst (RoundDouble dst));
6519 ins_cost(0);
6520 // SPARC results are already "rounded" (i.e., normal-format IEEE)
6521 ins_encode( );
6522 ins_pipe(empty);
6523 %}
6524
6525
6526 instruct roundFloat_nop(regF dst) %{
6527 match(Set dst (RoundFloat dst));
6528 ins_cost(0);
6529 // SPARC results are already "rounded" (i.e., normal-format IEEE)
6530 ins_encode( );
6531 ins_pipe(empty);
6532 %}
6533
6534
6535 // Cast Index to Pointer for unsafe natives
6536 instruct castX2P(iRegX src, iRegP dst) %{
6537 match(Set dst (CastX2P src));
6538
6539 format %{ "MOV $src,$dst\t! IntX->Ptr" %}
6540 ins_encode( form3_g0_rs2_rd_move( src, dst ) );
6541 ins_pipe(ialu_reg);
6542 %}
6543
6544 // Cast Pointer to Index for unsafe natives
6545 instruct castP2X(iRegP src, iRegX dst) %{
6546 match(Set dst (CastP2X src));
6547
6548 format %{ "MOV $src,$dst\t! Ptr->IntX" %}
6549 ins_encode( form3_g0_rs2_rd_move( src, dst ) );
6550 ins_pipe(ialu_reg);
6551 %}
6552
6553 instruct stfSSD(stackSlotD stkSlot, regD src) %{
6554 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6555 match(Set stkSlot src); // chain rule
6556 ins_cost(MEMORY_REF_COST);
6557 format %{ "STDF $src,$stkSlot\t!stk" %}
6558 opcode(Assembler::stdf_op3);
6559 ins_encode(simple_form3_mem_reg(stkSlot, src));
6560 ins_pipe(fstoreD_stk_reg);
6561 %}
6562
6563 instruct ldfSSD(regD dst, stackSlotD stkSlot) %{
6564 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6565 match(Set dst stkSlot); // chain rule
6566 ins_cost(MEMORY_REF_COST);
6567 format %{ "LDDF $stkSlot,$dst\t!stk" %}
6568 opcode(Assembler::lddf_op3);
6569 ins_encode(simple_form3_mem_reg(stkSlot, dst));
6570 ins_pipe(floadD_stk);
6571 %}
6572
6573 instruct stfSSF(stackSlotF stkSlot, regF src) %{
6574 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6575 match(Set stkSlot src); // chain rule
6576 ins_cost(MEMORY_REF_COST);
6577 format %{ "STF $src,$stkSlot\t!stk" %}
6578 opcode(Assembler::stf_op3);
6579 ins_encode(simple_form3_mem_reg(stkSlot, src));
6580 ins_pipe(fstoreF_stk_reg);
6581 %}
6582
6583 //----------Conditional Move---------------------------------------------------
6584 // Conditional move
6585 instruct cmovIP_reg(cmpOpP cmp, flagsRegP pcc, iRegI dst, iRegI src) %{
6586 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src)));
6587 ins_cost(150);
6588 format %{ "MOV$cmp $pcc,$src,$dst" %}
6589 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6590 ins_pipe(ialu_reg);
6591 %}
6592
6593 instruct cmovIP_imm(cmpOpP cmp, flagsRegP pcc, iRegI dst, immI11 src) %{
6594 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src)));
6595 ins_cost(140);
6596 format %{ "MOV$cmp $pcc,$src,$dst" %}
6597 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
6598 ins_pipe(ialu_imm);
6599 %}
6600
6601 instruct cmovII_reg(cmpOp cmp, flagsReg icc, iRegI dst, iRegI src) %{
6602 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6603 ins_cost(150);
6604 size(4);
6605 format %{ "MOV$cmp $icc,$src,$dst" %}
6606 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6607 ins_pipe(ialu_reg);
6608 %}
6609
6610 instruct cmovII_imm(cmpOp cmp, flagsReg icc, iRegI dst, immI11 src) %{
6611 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6612 ins_cost(140);
6613 size(4);
6614 format %{ "MOV$cmp $icc,$src,$dst" %}
6615 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6616 ins_pipe(ialu_imm);
6617 %}
6618
6619 instruct cmovII_U_reg(cmpOpU cmp, flagsRegU icc, iRegI dst, iRegI src) %{
6620 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6621 ins_cost(150);
6622 size(4);
6623 format %{ "MOV$cmp $icc,$src,$dst" %}
6624 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6625 ins_pipe(ialu_reg);
6626 %}
6627
6628 instruct cmovII_U_imm(cmpOpU cmp, flagsRegU icc, iRegI dst, immI11 src) %{
6629 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6630 ins_cost(140);
6631 size(4);
6632 format %{ "MOV$cmp $icc,$src,$dst" %}
6633 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6634 ins_pipe(ialu_imm);
6635 %}
6636
6637 instruct cmovIF_reg(cmpOpF cmp, flagsRegF fcc, iRegI dst, iRegI src) %{
6638 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src)));
6639 ins_cost(150);
6640 size(4);
6641 format %{ "MOV$cmp $fcc,$src,$dst" %}
6642 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6643 ins_pipe(ialu_reg);
6644 %}
6645
6646 instruct cmovIF_imm(cmpOpF cmp, flagsRegF fcc, iRegI dst, immI11 src) %{
6647 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src)));
6648 ins_cost(140);
6649 size(4);
6650 format %{ "MOV$cmp $fcc,$src,$dst" %}
6651 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) );
6652 ins_pipe(ialu_imm);
6653 %}
6654
6655 // Conditional move for RegN. Only cmov(reg,reg).
6656 instruct cmovNP_reg(cmpOpP cmp, flagsRegP pcc, iRegN dst, iRegN src) %{
6657 match(Set dst (CMoveN (Binary cmp pcc) (Binary dst src)));
6658 ins_cost(150);
6659 format %{ "MOV$cmp $pcc,$src,$dst" %}
6660 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6661 ins_pipe(ialu_reg);
6662 %}
6663
6664 // This instruction also works with CmpN so we don't need cmovNN_reg.
6665 instruct cmovNI_reg(cmpOp cmp, flagsReg icc, iRegN dst, iRegN src) %{
6666 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src)));
6667 ins_cost(150);
6668 size(4);
6669 format %{ "MOV$cmp $icc,$src,$dst" %}
6670 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6671 ins_pipe(ialu_reg);
6672 %}
6673
6674 instruct cmovNF_reg(cmpOpF cmp, flagsRegF fcc, iRegN dst, iRegN src) %{
6675 match(Set dst (CMoveN (Binary cmp fcc) (Binary dst src)));
6676 ins_cost(150);
6677 size(4);
6678 format %{ "MOV$cmp $fcc,$src,$dst" %}
6679 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6680 ins_pipe(ialu_reg);
6681 %}
6682
6683 // Conditional move
6684 instruct cmovPP_reg(cmpOpP cmp, flagsRegP pcc, iRegP dst, iRegP src) %{
6685 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src)));
6686 ins_cost(150);
6687 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %}
6688 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6689 ins_pipe(ialu_reg);
6690 %}
6691
6692 instruct cmovPP_imm(cmpOpP cmp, flagsRegP pcc, iRegP dst, immP0 src) %{
6693 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src)));
6694 ins_cost(140);
6695 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %}
6696 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
6697 ins_pipe(ialu_imm);
6698 %}
6699
6700 // This instruction also works with CmpN so we don't need cmovPN_reg.
6701 instruct cmovPI_reg(cmpOp cmp, flagsReg icc, iRegP dst, iRegP src) %{
6702 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6703 ins_cost(150);
6704
6705 size(4);
6706 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6707 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6708 ins_pipe(ialu_reg);
6709 %}
6710
6711 instruct cmovPI_imm(cmpOp cmp, flagsReg icc, iRegP dst, immP0 src) %{
6712 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6713 ins_cost(140);
6714
6715 size(4);
6716 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6717 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6718 ins_pipe(ialu_imm);
6719 %}
6720
6721 instruct cmovPF_reg(cmpOpF cmp, flagsRegF fcc, iRegP dst, iRegP src) %{
6722 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src)));
6723 ins_cost(150);
6724 size(4);
6725 format %{ "MOV$cmp $fcc,$src,$dst" %}
6726 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6727 ins_pipe(ialu_imm);
6728 %}
6729
6730 instruct cmovPF_imm(cmpOpF cmp, flagsRegF fcc, iRegP dst, immP0 src) %{
6731 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src)));
6732 ins_cost(140);
6733 size(4);
6734 format %{ "MOV$cmp $fcc,$src,$dst" %}
6735 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) );
6736 ins_pipe(ialu_imm);
6737 %}
6738
6739 // Conditional move
6740 instruct cmovFP_reg(cmpOpP cmp, flagsRegP pcc, regF dst, regF src) %{
6741 match(Set dst (CMoveF (Binary cmp pcc) (Binary dst src)));
6742 ins_cost(150);
6743 opcode(0x101);
6744 format %{ "FMOVD$cmp $pcc,$src,$dst" %}
6745 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6746 ins_pipe(int_conditional_float_move);
6747 %}
6748
6749 instruct cmovFI_reg(cmpOp cmp, flagsReg icc, regF dst, regF src) %{
6750 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src)));
6751 ins_cost(150);
6752
6753 size(4);
6754 format %{ "FMOVS$cmp $icc,$src,$dst" %}
6755 opcode(0x101);
6756 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6757 ins_pipe(int_conditional_float_move);
6758 %}
6759
6760 // Conditional move,
6761 instruct cmovFF_reg(cmpOpF cmp, flagsRegF fcc, regF dst, regF src) %{
6762 match(Set dst (CMoveF (Binary cmp fcc) (Binary dst src)));
6763 ins_cost(150);
6764 size(4);
6765 format %{ "FMOVF$cmp $fcc,$src,$dst" %}
6766 opcode(0x1);
6767 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) );
6768 ins_pipe(int_conditional_double_move);
6769 %}
6770
6771 // Conditional move
6772 instruct cmovDP_reg(cmpOpP cmp, flagsRegP pcc, regD dst, regD src) %{
6773 match(Set dst (CMoveD (Binary cmp pcc) (Binary dst src)));
6774 ins_cost(150);
6775 size(4);
6776 opcode(0x102);
6777 format %{ "FMOVD$cmp $pcc,$src,$dst" %}
6778 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6779 ins_pipe(int_conditional_double_move);
6780 %}
6781
6782 instruct cmovDI_reg(cmpOp cmp, flagsReg icc, regD dst, regD src) %{
6783 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src)));
6784 ins_cost(150);
6785
6786 size(4);
6787 format %{ "FMOVD$cmp $icc,$src,$dst" %}
6788 opcode(0x102);
6789 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6790 ins_pipe(int_conditional_double_move);
6791 %}
6792
6793 // Conditional move,
6794 instruct cmovDF_reg(cmpOpF cmp, flagsRegF fcc, regD dst, regD src) %{
6795 match(Set dst (CMoveD (Binary cmp fcc) (Binary dst src)));
6796 ins_cost(150);
6797 size(4);
6798 format %{ "FMOVD$cmp $fcc,$src,$dst" %}
6799 opcode(0x2);
6800 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) );
6801 ins_pipe(int_conditional_double_move);
6802 %}
6803
6804 // Conditional move
6805 instruct cmovLP_reg(cmpOpP cmp, flagsRegP pcc, iRegL dst, iRegL src) %{
6806 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src)));
6807 ins_cost(150);
6808 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %}
6809 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6810 ins_pipe(ialu_reg);
6811 %}
6812
6813 instruct cmovLP_imm(cmpOpP cmp, flagsRegP pcc, iRegL dst, immI11 src) %{
6814 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src)));
6815 ins_cost(140);
6816 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %}
6817 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
6818 ins_pipe(ialu_imm);
6819 %}
6820
6821 instruct cmovLI_reg(cmpOp cmp, flagsReg icc, iRegL dst, iRegL src) %{
6822 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src)));
6823 ins_cost(150);
6824
6825 size(4);
6826 format %{ "MOV$cmp $icc,$src,$dst\t! long" %}
6827 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6828 ins_pipe(ialu_reg);
6829 %}
6830
6831
6832 instruct cmovLF_reg(cmpOpF cmp, flagsRegF fcc, iRegL dst, iRegL src) %{
6833 match(Set dst (CMoveL (Binary cmp fcc) (Binary dst src)));
6834 ins_cost(150);
6835
6836 size(4);
6837 format %{ "MOV$cmp $fcc,$src,$dst\t! long" %}
6838 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6839 ins_pipe(ialu_reg);
6840 %}
6841
6842
6843
6844 //----------OS and Locking Instructions----------------------------------------
6845
6846 // This name is KNOWN by the ADLC and cannot be changed.
6847 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
6848 // for this guy.
6849 instruct tlsLoadP(g2RegP dst) %{
6850 match(Set dst (ThreadLocal));
6851
6852 size(0);
6853 ins_cost(0);
6854 format %{ "# TLS is in G2" %}
6855 ins_encode( /*empty encoding*/ );
6856 ins_pipe(ialu_none);
6857 %}
6858
6859 instruct checkCastPP( iRegP dst ) %{
6860 match(Set dst (CheckCastPP dst));
6861
6862 size(0);
6863 format %{ "# checkcastPP of $dst" %}
6864 ins_encode( /*empty encoding*/ );
6865 ins_pipe(empty);
6866 %}
6867
6868
6869 instruct castPP( iRegP dst ) %{
6870 match(Set dst (CastPP dst));
6871 format %{ "# castPP of $dst" %}
6872 ins_encode( /*empty encoding*/ );
6873 ins_pipe(empty);
6874 %}
6875
6876 instruct castII( iRegI dst ) %{
6877 match(Set dst (CastII dst));
6878 format %{ "# castII of $dst" %}
6879 ins_encode( /*empty encoding*/ );
6880 ins_cost(0);
6881 ins_pipe(empty);
6882 %}
6883
6884 //----------Arithmetic Instructions--------------------------------------------
6885 // Addition Instructions
6886 // Register Addition
6887 instruct addI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
6888 match(Set dst (AddI src1 src2));
6889
6890 size(4);
6891 format %{ "ADD $src1,$src2,$dst" %}
6892 ins_encode %{
6893 __ add($src1$$Register, $src2$$Register, $dst$$Register);
6894 %}
6895 ins_pipe(ialu_reg_reg);
6896 %}
6897
6898 // Immediate Addition
6899 instruct addI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
6900 match(Set dst (AddI src1 src2));
6901
6902 size(4);
6903 format %{ "ADD $src1,$src2,$dst" %}
6904 opcode(Assembler::add_op3, Assembler::arith_op);
6905 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
6906 ins_pipe(ialu_reg_imm);
6907 %}
6908
6909 // Pointer Register Addition
6910 instruct addP_reg_reg(iRegP dst, iRegP src1, iRegX src2) %{
6911 match(Set dst (AddP src1 src2));
6912
6913 size(4);
6914 format %{ "ADD $src1,$src2,$dst" %}
6915 opcode(Assembler::add_op3, Assembler::arith_op);
6916 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
6917 ins_pipe(ialu_reg_reg);
6918 %}
6919
6920 // Pointer Immediate Addition
6921 instruct addP_reg_imm13(iRegP dst, iRegP src1, immX13 src2) %{
6922 match(Set dst (AddP src1 src2));
6923
6924 size(4);
6925 format %{ "ADD $src1,$src2,$dst" %}
6926 opcode(Assembler::add_op3, Assembler::arith_op);
6927 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
6928 ins_pipe(ialu_reg_imm);
6929 %}
6930
6931 // Long Addition
6932 instruct addL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
6933 match(Set dst (AddL src1 src2));
6934
6935 size(4);
6936 format %{ "ADD $src1,$src2,$dst\t! long" %}
6937 opcode(Assembler::add_op3, Assembler::arith_op);
6938 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
6939 ins_pipe(ialu_reg_reg);
6940 %}
6941
6942 instruct addL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
6943 match(Set dst (AddL src1 con));
6944
6945 size(4);
6946 format %{ "ADD $src1,$con,$dst" %}
6947 opcode(Assembler::add_op3, Assembler::arith_op);
6948 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
6949 ins_pipe(ialu_reg_imm);
6950 %}
6951
6952 //----------Conditional_store--------------------------------------------------
6953 // Conditional-store of the updated heap-top.
6954 // Used during allocation of the shared heap.
6955 // Sets flags (EQ) on success. Implemented with a CASA on Sparc.
6956
6957 // LoadP-locked. Same as a regular pointer load when used with a compare-swap
6958 instruct loadPLocked(iRegP dst, memory mem) %{
6959 match(Set dst (LoadPLocked mem));
6960 ins_cost(MEMORY_REF_COST);
6961
6962 #ifndef _LP64
6963 size(4);
6964 format %{ "LDUW $mem,$dst\t! ptr" %}
6965 opcode(Assembler::lduw_op3, 0, REGP_OP);
6966 #else
6967 format %{ "LDX $mem,$dst\t! ptr" %}
6968 opcode(Assembler::ldx_op3, 0, REGP_OP);
6969 #endif
6970 ins_encode( form3_mem_reg( mem, dst ) );
6971 ins_pipe(iload_mem);
6972 %}
6973
6974 // LoadL-locked. Same as a regular long load when used with a compare-swap
6975 instruct loadLLocked(iRegL dst, memory mem) %{
6976 match(Set dst (LoadLLocked mem));
6977 ins_cost(MEMORY_REF_COST);
6978 size(4);
6979 format %{ "LDX $mem,$dst\t! long" %}
6980 opcode(Assembler::ldx_op3);
6981 ins_encode(simple_form3_mem_reg( mem, dst ) );
6982 ins_pipe(iload_mem);
6983 %}
6984
6985 instruct storePConditional( iRegP heap_top_ptr, iRegP oldval, g3RegP newval, flagsRegP pcc ) %{
6986 match(Set pcc (StorePConditional heap_top_ptr (Binary oldval newval)));
6987 effect( KILL newval );
6988 format %{ "CASA [$heap_top_ptr],$oldval,R_G3\t! If $oldval==[$heap_top_ptr] Then store R_G3 into [$heap_top_ptr], set R_G3=[$heap_top_ptr] in any case\n\t"
6989 "CMP R_G3,$oldval\t\t! See if we made progress" %}
6990 ins_encode( enc_cas(heap_top_ptr,oldval,newval) );
6991 ins_pipe( long_memory_op );
6992 %}
6993
6994 // Conditional-store of an int value.
6995 instruct storeIConditional( iRegP mem_ptr, iRegI oldval, g3RegI newval, flagsReg icc ) %{
6996 match(Set icc (StoreIConditional mem_ptr (Binary oldval newval)));
6997 effect( KILL newval );
6998 format %{ "CASA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t"
6999 "CMP $oldval,$newval\t\t! See if we made progress" %}
7000 ins_encode( enc_cas(mem_ptr,oldval,newval) );
7001 ins_pipe( long_memory_op );
7002 %}
7003
7004 // Conditional-store of a long value.
7005 instruct storeLConditional( iRegP mem_ptr, iRegL oldval, g3RegL newval, flagsRegL xcc ) %{
7006 match(Set xcc (StoreLConditional mem_ptr (Binary oldval newval)));
7007 effect( KILL newval );
7008 format %{ "CASXA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t"
7009 "CMP $oldval,$newval\t\t! See if we made progress" %}
7010 ins_encode( enc_cas(mem_ptr,oldval,newval) );
7011 ins_pipe( long_memory_op );
7012 %}
7013
7014 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
7015
7016 instruct compareAndSwapL_bool(iRegP mem_ptr, iRegL oldval, iRegL newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7017 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
7018 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7019 format %{
7020 "MOV $newval,O7\n\t"
7021 "CASXA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7022 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7023 "MOV 1,$res\n\t"
7024 "MOVne xcc,R_G0,$res"
7025 %}
7026 ins_encode( enc_casx(mem_ptr, oldval, newval),
7027 enc_lflags_ne_to_boolean(res) );
7028 ins_pipe( long_memory_op );
7029 %}
7030
7031
7032 instruct compareAndSwapI_bool(iRegP mem_ptr, iRegI oldval, iRegI newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7033 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
7034 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7035 format %{
7036 "MOV $newval,O7\n\t"
7037 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7038 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7039 "MOV 1,$res\n\t"
7040 "MOVne icc,R_G0,$res"
7041 %}
7042 ins_encode( enc_casi(mem_ptr, oldval, newval),
7043 enc_iflags_ne_to_boolean(res) );
7044 ins_pipe( long_memory_op );
7045 %}
7046
7047 instruct compareAndSwapP_bool(iRegP mem_ptr, iRegP oldval, iRegP newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7048 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
7049 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7050 format %{
7051 "MOV $newval,O7\n\t"
7052 "CASA_PTR [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7053 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7054 "MOV 1,$res\n\t"
7055 "MOVne xcc,R_G0,$res"
7056 %}
7057 #ifdef _LP64
7058 ins_encode( enc_casx(mem_ptr, oldval, newval),
7059 enc_lflags_ne_to_boolean(res) );
7060 #else
7061 ins_encode( enc_casi(mem_ptr, oldval, newval),
7062 enc_iflags_ne_to_boolean(res) );
7063 #endif
7064 ins_pipe( long_memory_op );
7065 %}
7066
7067 instruct compareAndSwapN_bool(iRegP mem_ptr, iRegN oldval, iRegN newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7068 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval)));
7069 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7070 format %{
7071 "MOV $newval,O7\n\t"
7072 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7073 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7074 "MOV 1,$res\n\t"
7075 "MOVne icc,R_G0,$res"
7076 %}
7077 ins_encode( enc_casi(mem_ptr, oldval, newval),
7078 enc_iflags_ne_to_boolean(res) );
7079 ins_pipe( long_memory_op );
7080 %}
7081
7082 //---------------------
7083 // Subtraction Instructions
7084 // Register Subtraction
7085 instruct subI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7086 match(Set dst (SubI src1 src2));
7087
7088 size(4);
7089 format %{ "SUB $src1,$src2,$dst" %}
7090 opcode(Assembler::sub_op3, Assembler::arith_op);
7091 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7092 ins_pipe(ialu_reg_reg);
7093 %}
7094
7095 // Immediate Subtraction
7096 instruct subI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7097 match(Set dst (SubI src1 src2));
7098
7099 size(4);
7100 format %{ "SUB $src1,$src2,$dst" %}
7101 opcode(Assembler::sub_op3, Assembler::arith_op);
7102 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7103 ins_pipe(ialu_reg_imm);
7104 %}
7105
7106 instruct subI_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{
7107 match(Set dst (SubI zero src2));
7108
7109 size(4);
7110 format %{ "NEG $src2,$dst" %}
7111 opcode(Assembler::sub_op3, Assembler::arith_op);
7112 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) );
7113 ins_pipe(ialu_zero_reg);
7114 %}
7115
7116 // Long subtraction
7117 instruct subL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7118 match(Set dst (SubL src1 src2));
7119
7120 size(4);
7121 format %{ "SUB $src1,$src2,$dst\t! long" %}
7122 opcode(Assembler::sub_op3, Assembler::arith_op);
7123 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7124 ins_pipe(ialu_reg_reg);
7125 %}
7126
7127 // Immediate Subtraction
7128 instruct subL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7129 match(Set dst (SubL src1 con));
7130
7131 size(4);
7132 format %{ "SUB $src1,$con,$dst\t! long" %}
7133 opcode(Assembler::sub_op3, Assembler::arith_op);
7134 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7135 ins_pipe(ialu_reg_imm);
7136 %}
7137
7138 // Long negation
7139 instruct negL_reg_reg(iRegL dst, immL0 zero, iRegL src2) %{
7140 match(Set dst (SubL zero src2));
7141
7142 size(4);
7143 format %{ "NEG $src2,$dst\t! long" %}
7144 opcode(Assembler::sub_op3, Assembler::arith_op);
7145 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) );
7146 ins_pipe(ialu_zero_reg);
7147 %}
7148
7149 // Multiplication Instructions
7150 // Integer Multiplication
7151 // Register Multiplication
7152 instruct mulI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7153 match(Set dst (MulI src1 src2));
7154
7155 size(4);
7156 format %{ "MULX $src1,$src2,$dst" %}
7157 opcode(Assembler::mulx_op3, Assembler::arith_op);
7158 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7159 ins_pipe(imul_reg_reg);
7160 %}
7161
7162 // Immediate Multiplication
7163 instruct mulI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7164 match(Set dst (MulI src1 src2));
7165
7166 size(4);
7167 format %{ "MULX $src1,$src2,$dst" %}
7168 opcode(Assembler::mulx_op3, Assembler::arith_op);
7169 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7170 ins_pipe(imul_reg_imm);
7171 %}
7172
7173 instruct mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7174 match(Set dst (MulL src1 src2));
7175 ins_cost(DEFAULT_COST * 5);
7176 size(4);
7177 format %{ "MULX $src1,$src2,$dst\t! long" %}
7178 opcode(Assembler::mulx_op3, Assembler::arith_op);
7179 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7180 ins_pipe(mulL_reg_reg);
7181 %}
7182
7183 // Immediate Multiplication
7184 instruct mulL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7185 match(Set dst (MulL src1 src2));
7186 ins_cost(DEFAULT_COST * 5);
7187 size(4);
7188 format %{ "MULX $src1,$src2,$dst" %}
7189 opcode(Assembler::mulx_op3, Assembler::arith_op);
7190 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7191 ins_pipe(mulL_reg_imm);
7192 %}
7193
7194 // Integer Division
7195 // Register Division
7196 instruct divI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2) %{
7197 match(Set dst (DivI src1 src2));
7198 ins_cost((2+71)*DEFAULT_COST);
7199
7200 format %{ "SRA $src2,0,$src2\n\t"
7201 "SRA $src1,0,$src1\n\t"
7202 "SDIVX $src1,$src2,$dst" %}
7203 ins_encode( idiv_reg( src1, src2, dst ) );
7204 ins_pipe(sdiv_reg_reg);
7205 %}
7206
7207 // Immediate Division
7208 instruct divI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2) %{
7209 match(Set dst (DivI src1 src2));
7210 ins_cost((2+71)*DEFAULT_COST);
7211
7212 format %{ "SRA $src1,0,$src1\n\t"
7213 "SDIVX $src1,$src2,$dst" %}
7214 ins_encode( idiv_imm( src1, src2, dst ) );
7215 ins_pipe(sdiv_reg_imm);
7216 %}
7217
7218 //----------Div-By-10-Expansion------------------------------------------------
7219 // Extract hi bits of a 32x32->64 bit multiply.
7220 // Expand rule only, not matched
7221 instruct mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2 ) %{
7222 effect( DEF dst, USE src1, USE src2 );
7223 format %{ "MULX $src1,$src2,$dst\t! Used in div-by-10\n\t"
7224 "SRLX $dst,#32,$dst\t\t! Extract only hi word of result" %}
7225 ins_encode( enc_mul_hi(dst,src1,src2));
7226 ins_pipe(sdiv_reg_reg);
7227 %}
7228
7229 // Magic constant, reciprocal of 10
7230 instruct loadConI_x66666667(iRegIsafe dst) %{
7231 effect( DEF dst );
7232
7233 size(8);
7234 format %{ "SET 0x66666667,$dst\t! Used in div-by-10" %}
7235 ins_encode( Set32(0x66666667, dst) );
7236 ins_pipe(ialu_hi_lo_reg);
7237 %}
7238
7239 // Register Shift Right Arithmetic Long by 32-63
7240 instruct sra_31( iRegI dst, iRegI src ) %{
7241 effect( DEF dst, USE src );
7242 format %{ "SRA $src,31,$dst\t! Used in div-by-10" %}
7243 ins_encode( form3_rs1_rd_copysign_hi(src,dst) );
7244 ins_pipe(ialu_reg_reg);
7245 %}
7246
7247 // Arithmetic Shift Right by 8-bit immediate
7248 instruct sra_reg_2( iRegI dst, iRegI src ) %{
7249 effect( DEF dst, USE src );
7250 format %{ "SRA $src,2,$dst\t! Used in div-by-10" %}
7251 opcode(Assembler::sra_op3, Assembler::arith_op);
7252 ins_encode( form3_rs1_simm13_rd( src, 0x2, dst ) );
7253 ins_pipe(ialu_reg_imm);
7254 %}
7255
7256 // Integer DIV with 10
7257 instruct divI_10( iRegI dst, iRegIsafe src, immI10 div ) %{
7258 match(Set dst (DivI src div));
7259 ins_cost((6+6)*DEFAULT_COST);
7260 expand %{
7261 iRegIsafe tmp1; // Killed temps;
7262 iRegIsafe tmp2; // Killed temps;
7263 iRegI tmp3; // Killed temps;
7264 iRegI tmp4; // Killed temps;
7265 loadConI_x66666667( tmp1 ); // SET 0x66666667 -> tmp1
7266 mul_hi( tmp2, src, tmp1 ); // MUL hibits(src * tmp1) -> tmp2
7267 sra_31( tmp3, src ); // SRA src,31 -> tmp3
7268 sra_reg_2( tmp4, tmp2 ); // SRA tmp2,2 -> tmp4
7269 subI_reg_reg( dst,tmp4,tmp3); // SUB tmp4 - tmp3 -> dst
7270 %}
7271 %}
7272
7273 // Register Long Division
7274 instruct divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7275 match(Set dst (DivL src1 src2));
7276 ins_cost(DEFAULT_COST*71);
7277 size(4);
7278 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7279 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7280 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7281 ins_pipe(divL_reg_reg);
7282 %}
7283
7284 // Register Long Division
7285 instruct divL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7286 match(Set dst (DivL src1 src2));
7287 ins_cost(DEFAULT_COST*71);
7288 size(4);
7289 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7290 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7291 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7292 ins_pipe(divL_reg_imm);
7293 %}
7294
7295 // Integer Remainder
7296 // Register Remainder
7297 instruct modI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2, o7RegP temp, flagsReg ccr ) %{
7298 match(Set dst (ModI src1 src2));
7299 effect( KILL ccr, KILL temp);
7300
7301 format %{ "SREM $src1,$src2,$dst" %}
7302 ins_encode( irem_reg(src1, src2, dst, temp) );
7303 ins_pipe(sdiv_reg_reg);
7304 %}
7305
7306 // Immediate Remainder
7307 instruct modI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2, o7RegP temp, flagsReg ccr ) %{
7308 match(Set dst (ModI src1 src2));
7309 effect( KILL ccr, KILL temp);
7310
7311 format %{ "SREM $src1,$src2,$dst" %}
7312 ins_encode( irem_imm(src1, src2, dst, temp) );
7313 ins_pipe(sdiv_reg_imm);
7314 %}
7315
7316 // Register Long Remainder
7317 instruct divL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7318 effect(DEF dst, USE src1, USE src2);
7319 size(4);
7320 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7321 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7322 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7323 ins_pipe(divL_reg_reg);
7324 %}
7325
7326 // Register Long Division
7327 instruct divL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{
7328 effect(DEF dst, USE src1, USE src2);
7329 size(4);
7330 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7331 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7332 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7333 ins_pipe(divL_reg_imm);
7334 %}
7335
7336 instruct mulL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7337 effect(DEF dst, USE src1, USE src2);
7338 size(4);
7339 format %{ "MULX $src1,$src2,$dst\t! long" %}
7340 opcode(Assembler::mulx_op3, Assembler::arith_op);
7341 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7342 ins_pipe(mulL_reg_reg);
7343 %}
7344
7345 // Immediate Multiplication
7346 instruct mulL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{
7347 effect(DEF dst, USE src1, USE src2);
7348 size(4);
7349 format %{ "MULX $src1,$src2,$dst" %}
7350 opcode(Assembler::mulx_op3, Assembler::arith_op);
7351 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7352 ins_pipe(mulL_reg_imm);
7353 %}
7354
7355 instruct subL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7356 effect(DEF dst, USE src1, USE src2);
7357 size(4);
7358 format %{ "SUB $src1,$src2,$dst\t! long" %}
7359 opcode(Assembler::sub_op3, Assembler::arith_op);
7360 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7361 ins_pipe(ialu_reg_reg);
7362 %}
7363
7364 instruct subL_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{
7365 effect(DEF dst, USE src1, USE src2);
7366 size(4);
7367 format %{ "SUB $src1,$src2,$dst\t! long" %}
7368 opcode(Assembler::sub_op3, Assembler::arith_op);
7369 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7370 ins_pipe(ialu_reg_reg);
7371 %}
7372
7373 // Register Long Remainder
7374 instruct modL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7375 match(Set dst (ModL src1 src2));
7376 ins_cost(DEFAULT_COST*(71 + 6 + 1));
7377 expand %{
7378 iRegL tmp1;
7379 iRegL tmp2;
7380 divL_reg_reg_1(tmp1, src1, src2);
7381 mulL_reg_reg_1(tmp2, tmp1, src2);
7382 subL_reg_reg_1(dst, src1, tmp2);
7383 %}
7384 %}
7385
7386 // Register Long Remainder
7387 instruct modL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7388 match(Set dst (ModL src1 src2));
7389 ins_cost(DEFAULT_COST*(71 + 6 + 1));
7390 expand %{
7391 iRegL tmp1;
7392 iRegL tmp2;
7393 divL_reg_imm13_1(tmp1, src1, src2);
7394 mulL_reg_imm13_1(tmp2, tmp1, src2);
7395 subL_reg_reg_2 (dst, src1, tmp2);
7396 %}
7397 %}
7398
7399 // Integer Shift Instructions
7400 // Register Shift Left
7401 instruct shlI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7402 match(Set dst (LShiftI src1 src2));
7403
7404 size(4);
7405 format %{ "SLL $src1,$src2,$dst" %}
7406 opcode(Assembler::sll_op3, Assembler::arith_op);
7407 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7408 ins_pipe(ialu_reg_reg);
7409 %}
7410
7411 // Register Shift Left Immediate
7412 instruct shlI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7413 match(Set dst (LShiftI src1 src2));
7414
7415 size(4);
7416 format %{ "SLL $src1,$src2,$dst" %}
7417 opcode(Assembler::sll_op3, Assembler::arith_op);
7418 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7419 ins_pipe(ialu_reg_imm);
7420 %}
7421
7422 // Register Shift Left
7423 instruct shlL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7424 match(Set dst (LShiftL src1 src2));
7425
7426 size(4);
7427 format %{ "SLLX $src1,$src2,$dst" %}
7428 opcode(Assembler::sllx_op3, Assembler::arith_op);
7429 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7430 ins_pipe(ialu_reg_reg);
7431 %}
7432
7433 // Register Shift Left Immediate
7434 instruct shlL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7435 match(Set dst (LShiftL src1 src2));
7436
7437 size(4);
7438 format %{ "SLLX $src1,$src2,$dst" %}
7439 opcode(Assembler::sllx_op3, Assembler::arith_op);
7440 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7441 ins_pipe(ialu_reg_imm);
7442 %}
7443
7444 // Register Arithmetic Shift Right
7445 instruct sarI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7446 match(Set dst (RShiftI src1 src2));
7447 size(4);
7448 format %{ "SRA $src1,$src2,$dst" %}
7449 opcode(Assembler::sra_op3, Assembler::arith_op);
7450 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7451 ins_pipe(ialu_reg_reg);
7452 %}
7453
7454 // Register Arithmetic Shift Right Immediate
7455 instruct sarI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7456 match(Set dst (RShiftI src1 src2));
7457
7458 size(4);
7459 format %{ "SRA $src1,$src2,$dst" %}
7460 opcode(Assembler::sra_op3, Assembler::arith_op);
7461 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7462 ins_pipe(ialu_reg_imm);
7463 %}
7464
7465 // Register Shift Right Arithmatic Long
7466 instruct sarL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7467 match(Set dst (RShiftL src1 src2));
7468
7469 size(4);
7470 format %{ "SRAX $src1,$src2,$dst" %}
7471 opcode(Assembler::srax_op3, Assembler::arith_op);
7472 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7473 ins_pipe(ialu_reg_reg);
7474 %}
7475
7476 // Register Shift Left Immediate
7477 instruct sarL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7478 match(Set dst (RShiftL src1 src2));
7479
7480 size(4);
7481 format %{ "SRAX $src1,$src2,$dst" %}
7482 opcode(Assembler::srax_op3, Assembler::arith_op);
7483 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7484 ins_pipe(ialu_reg_imm);
7485 %}
7486
7487 // Register Shift Right
7488 instruct shrI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7489 match(Set dst (URShiftI src1 src2));
7490
7491 size(4);
7492 format %{ "SRL $src1,$src2,$dst" %}
7493 opcode(Assembler::srl_op3, Assembler::arith_op);
7494 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7495 ins_pipe(ialu_reg_reg);
7496 %}
7497
7498 // Register Shift Right Immediate
7499 instruct shrI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7500 match(Set dst (URShiftI src1 src2));
7501
7502 size(4);
7503 format %{ "SRL $src1,$src2,$dst" %}
7504 opcode(Assembler::srl_op3, Assembler::arith_op);
7505 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7506 ins_pipe(ialu_reg_imm);
7507 %}
7508
7509 // Register Shift Right
7510 instruct shrL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7511 match(Set dst (URShiftL src1 src2));
7512
7513 size(4);
7514 format %{ "SRLX $src1,$src2,$dst" %}
7515 opcode(Assembler::srlx_op3, Assembler::arith_op);
7516 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7517 ins_pipe(ialu_reg_reg);
7518 %}
7519
7520 // Register Shift Right Immediate
7521 instruct shrL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7522 match(Set dst (URShiftL src1 src2));
7523
7524 size(4);
7525 format %{ "SRLX $src1,$src2,$dst" %}
7526 opcode(Assembler::srlx_op3, Assembler::arith_op);
7527 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7528 ins_pipe(ialu_reg_imm);
7529 %}
7530
7531 // Register Shift Right Immediate with a CastP2X
7532 #ifdef _LP64
7533 instruct shrP_reg_imm6(iRegL dst, iRegP src1, immU6 src2) %{
7534 match(Set dst (URShiftL (CastP2X src1) src2));
7535 size(4);
7536 format %{ "SRLX $src1,$src2,$dst\t! Cast ptr $src1 to long and shift" %}
7537 opcode(Assembler::srlx_op3, Assembler::arith_op);
7538 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7539 ins_pipe(ialu_reg_imm);
7540 %}
7541 #else
7542 instruct shrP_reg_imm5(iRegI dst, iRegP src1, immU5 src2) %{
7543 match(Set dst (URShiftI (CastP2X src1) src2));
7544 size(4);
7545 format %{ "SRL $src1,$src2,$dst\t! Cast ptr $src1 to int and shift" %}
7546 opcode(Assembler::srl_op3, Assembler::arith_op);
7547 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7548 ins_pipe(ialu_reg_imm);
7549 %}
7550 #endif
7551
7552
7553 //----------Floating Point Arithmetic Instructions-----------------------------
7554
7555 // Add float single precision
7556 instruct addF_reg_reg(regF dst, regF src1, regF src2) %{
7557 match(Set dst (AddF src1 src2));
7558
7559 size(4);
7560 format %{ "FADDS $src1,$src2,$dst" %}
7561 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fadds_opf);
7562 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7563 ins_pipe(faddF_reg_reg);
7564 %}
7565
7566 // Add float double precision
7567 instruct addD_reg_reg(regD dst, regD src1, regD src2) %{
7568 match(Set dst (AddD src1 src2));
7569
7570 size(4);
7571 format %{ "FADDD $src1,$src2,$dst" %}
7572 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf);
7573 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7574 ins_pipe(faddD_reg_reg);
7575 %}
7576
7577 // Sub float single precision
7578 instruct subF_reg_reg(regF dst, regF src1, regF src2) %{
7579 match(Set dst (SubF src1 src2));
7580
7581 size(4);
7582 format %{ "FSUBS $src1,$src2,$dst" %}
7583 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubs_opf);
7584 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7585 ins_pipe(faddF_reg_reg);
7586 %}
7587
7588 // Sub float double precision
7589 instruct subD_reg_reg(regD dst, regD src1, regD src2) %{
7590 match(Set dst (SubD src1 src2));
7591
7592 size(4);
7593 format %{ "FSUBD $src1,$src2,$dst" %}
7594 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf);
7595 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7596 ins_pipe(faddD_reg_reg);
7597 %}
7598
7599 // Mul float single precision
7600 instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{
7601 match(Set dst (MulF src1 src2));
7602
7603 size(4);
7604 format %{ "FMULS $src1,$src2,$dst" %}
7605 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuls_opf);
7606 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7607 ins_pipe(fmulF_reg_reg);
7608 %}
7609
7610 // Mul float double precision
7611 instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{
7612 match(Set dst (MulD src1 src2));
7613
7614 size(4);
7615 format %{ "FMULD $src1,$src2,$dst" %}
7616 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf);
7617 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7618 ins_pipe(fmulD_reg_reg);
7619 %}
7620
7621 // Div float single precision
7622 instruct divF_reg_reg(regF dst, regF src1, regF src2) %{
7623 match(Set dst (DivF src1 src2));
7624
7625 size(4);
7626 format %{ "FDIVS $src1,$src2,$dst" %}
7627 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivs_opf);
7628 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7629 ins_pipe(fdivF_reg_reg);
7630 %}
7631
7632 // Div float double precision
7633 instruct divD_reg_reg(regD dst, regD src1, regD src2) %{
7634 match(Set dst (DivD src1 src2));
7635
7636 size(4);
7637 format %{ "FDIVD $src1,$src2,$dst" %}
7638 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivd_opf);
7639 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7640 ins_pipe(fdivD_reg_reg);
7641 %}
7642
7643 // Absolute float double precision
7644 instruct absD_reg(regD dst, regD src) %{
7645 match(Set dst (AbsD src));
7646
7647 format %{ "FABSd $src,$dst" %}
7648 ins_encode(fabsd(dst, src));
7649 ins_pipe(faddD_reg);
7650 %}
7651
7652 // Absolute float single precision
7653 instruct absF_reg(regF dst, regF src) %{
7654 match(Set dst (AbsF src));
7655
7656 format %{ "FABSs $src,$dst" %}
7657 ins_encode(fabss(dst, src));
7658 ins_pipe(faddF_reg);
7659 %}
7660
7661 instruct negF_reg(regF dst, regF src) %{
7662 match(Set dst (NegF src));
7663
7664 size(4);
7665 format %{ "FNEGs $src,$dst" %}
7666 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fnegs_opf);
7667 ins_encode(form3_opf_rs2F_rdF(src, dst));
7668 ins_pipe(faddF_reg);
7669 %}
7670
7671 instruct negD_reg(regD dst, regD src) %{
7672 match(Set dst (NegD src));
7673
7674 format %{ "FNEGd $src,$dst" %}
7675 ins_encode(fnegd(dst, src));
7676 ins_pipe(faddD_reg);
7677 %}
7678
7679 // Sqrt float double precision
7680 instruct sqrtF_reg_reg(regF dst, regF src) %{
7681 match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
7682
7683 size(4);
7684 format %{ "FSQRTS $src,$dst" %}
7685 ins_encode(fsqrts(dst, src));
7686 ins_pipe(fdivF_reg_reg);
7687 %}
7688
7689 // Sqrt float double precision
7690 instruct sqrtD_reg_reg(regD dst, regD src) %{
7691 match(Set dst (SqrtD src));
7692
7693 size(4);
7694 format %{ "FSQRTD $src,$dst" %}
7695 ins_encode(fsqrtd(dst, src));
7696 ins_pipe(fdivD_reg_reg);
7697 %}
7698
7699 //----------Logical Instructions-----------------------------------------------
7700 // And Instructions
7701 // Register And
7702 instruct andI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7703 match(Set dst (AndI src1 src2));
7704
7705 size(4);
7706 format %{ "AND $src1,$src2,$dst" %}
7707 opcode(Assembler::and_op3, Assembler::arith_op);
7708 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7709 ins_pipe(ialu_reg_reg);
7710 %}
7711
7712 // Immediate And
7713 instruct andI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7714 match(Set dst (AndI src1 src2));
7715
7716 size(4);
7717 format %{ "AND $src1,$src2,$dst" %}
7718 opcode(Assembler::and_op3, Assembler::arith_op);
7719 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7720 ins_pipe(ialu_reg_imm);
7721 %}
7722
7723 // Register And Long
7724 instruct andL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7725 match(Set dst (AndL src1 src2));
7726
7727 ins_cost(DEFAULT_COST);
7728 size(4);
7729 format %{ "AND $src1,$src2,$dst\t! long" %}
7730 opcode(Assembler::and_op3, Assembler::arith_op);
7731 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7732 ins_pipe(ialu_reg_reg);
7733 %}
7734
7735 instruct andL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7736 match(Set dst (AndL src1 con));
7737
7738 ins_cost(DEFAULT_COST);
7739 size(4);
7740 format %{ "AND $src1,$con,$dst\t! long" %}
7741 opcode(Assembler::and_op3, Assembler::arith_op);
7742 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7743 ins_pipe(ialu_reg_imm);
7744 %}
7745
7746 // Or Instructions
7747 // Register Or
7748 instruct orI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7749 match(Set dst (OrI src1 src2));
7750
7751 size(4);
7752 format %{ "OR $src1,$src2,$dst" %}
7753 opcode(Assembler::or_op3, Assembler::arith_op);
7754 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7755 ins_pipe(ialu_reg_reg);
7756 %}
7757
7758 // Immediate Or
7759 instruct orI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7760 match(Set dst (OrI src1 src2));
7761
7762 size(4);
7763 format %{ "OR $src1,$src2,$dst" %}
7764 opcode(Assembler::or_op3, Assembler::arith_op);
7765 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7766 ins_pipe(ialu_reg_imm);
7767 %}
7768
7769 // Register Or Long
7770 instruct orL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7771 match(Set dst (OrL src1 src2));
7772
7773 ins_cost(DEFAULT_COST);
7774 size(4);
7775 format %{ "OR $src1,$src2,$dst\t! long" %}
7776 opcode(Assembler::or_op3, Assembler::arith_op);
7777 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7778 ins_pipe(ialu_reg_reg);
7779 %}
7780
7781 instruct orL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7782 match(Set dst (OrL src1 con));
7783 ins_cost(DEFAULT_COST*2);
7784
7785 ins_cost(DEFAULT_COST);
7786 size(4);
7787 format %{ "OR $src1,$con,$dst\t! long" %}
7788 opcode(Assembler::or_op3, Assembler::arith_op);
7789 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7790 ins_pipe(ialu_reg_imm);
7791 %}
7792
7793 #ifndef _LP64
7794
7795 // Use sp_ptr_RegP to match G2 (TLS register) without spilling.
7796 instruct orI_reg_castP2X(iRegI dst, iRegI src1, sp_ptr_RegP src2) %{
7797 match(Set dst (OrI src1 (CastP2X src2)));
7798
7799 size(4);
7800 format %{ "OR $src1,$src2,$dst" %}
7801 opcode(Assembler::or_op3, Assembler::arith_op);
7802 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7803 ins_pipe(ialu_reg_reg);
7804 %}
7805
7806 #else
7807
7808 instruct orL_reg_castP2X(iRegL dst, iRegL src1, sp_ptr_RegP src2) %{
7809 match(Set dst (OrL src1 (CastP2X src2)));
7810
7811 ins_cost(DEFAULT_COST);
7812 size(4);
7813 format %{ "OR $src1,$src2,$dst\t! long" %}
7814 opcode(Assembler::or_op3, Assembler::arith_op);
7815 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7816 ins_pipe(ialu_reg_reg);
7817 %}
7818
7819 #endif
7820
7821 // Xor Instructions
7822 // Register Xor
7823 instruct xorI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7824 match(Set dst (XorI src1 src2));
7825
7826 size(4);
7827 format %{ "XOR $src1,$src2,$dst" %}
7828 opcode(Assembler::xor_op3, Assembler::arith_op);
7829 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7830 ins_pipe(ialu_reg_reg);
7831 %}
7832
7833 // Immediate Xor
7834 instruct xorI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7835 match(Set dst (XorI src1 src2));
7836
7837 size(4);
7838 format %{ "XOR $src1,$src2,$dst" %}
7839 opcode(Assembler::xor_op3, Assembler::arith_op);
7840 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7841 ins_pipe(ialu_reg_imm);
7842 %}
7843
7844 // Register Xor Long
7845 instruct xorL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7846 match(Set dst (XorL src1 src2));
7847
7848 ins_cost(DEFAULT_COST);
7849 size(4);
7850 format %{ "XOR $src1,$src2,$dst\t! long" %}
7851 opcode(Assembler::xor_op3, Assembler::arith_op);
7852 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7853 ins_pipe(ialu_reg_reg);
7854 %}
7855
7856 instruct xorL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7857 match(Set dst (XorL src1 con));
7858
7859 ins_cost(DEFAULT_COST);
7860 size(4);
7861 format %{ "XOR $src1,$con,$dst\t! long" %}
7862 opcode(Assembler::xor_op3, Assembler::arith_op);
7863 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7864 ins_pipe(ialu_reg_imm);
7865 %}
7866
7867 //----------Convert to Boolean-------------------------------------------------
7868 // Nice hack for 32-bit tests but doesn't work for
7869 // 64-bit pointers.
7870 instruct convI2B( iRegI dst, iRegI src, flagsReg ccr ) %{
7871 match(Set dst (Conv2B src));
7872 effect( KILL ccr );
7873 ins_cost(DEFAULT_COST*2);
7874 format %{ "CMP R_G0,$src\n\t"
7875 "ADDX R_G0,0,$dst" %}
7876 ins_encode( enc_to_bool( src, dst ) );
7877 ins_pipe(ialu_reg_ialu);
7878 %}
7879
7880 #ifndef _LP64
7881 instruct convP2B( iRegI dst, iRegP src, flagsReg ccr ) %{
7882 match(Set dst (Conv2B src));
7883 effect( KILL ccr );
7884 ins_cost(DEFAULT_COST*2);
7885 format %{ "CMP R_G0,$src\n\t"
7886 "ADDX R_G0,0,$dst" %}
7887 ins_encode( enc_to_bool( src, dst ) );
7888 ins_pipe(ialu_reg_ialu);
7889 %}
7890 #else
7891 instruct convP2B( iRegI dst, iRegP src ) %{
7892 match(Set dst (Conv2B src));
7893 ins_cost(DEFAULT_COST*2);
7894 format %{ "MOV $src,$dst\n\t"
7895 "MOVRNZ $src,1,$dst" %}
7896 ins_encode( form3_g0_rs2_rd_move( src, dst ), enc_convP2B( dst, src ) );
7897 ins_pipe(ialu_clr_and_mover);
7898 %}
7899 #endif
7900
7901 instruct cmpLTMask_reg_reg( iRegI dst, iRegI p, iRegI q, flagsReg ccr ) %{
7902 match(Set dst (CmpLTMask p q));
7903 effect( KILL ccr );
7904 ins_cost(DEFAULT_COST*4);
7905 format %{ "CMP $p,$q\n\t"
7906 "MOV #0,$dst\n\t"
7907 "BLT,a .+8\n\t"
7908 "MOV #-1,$dst" %}
7909 ins_encode( enc_ltmask(p,q,dst) );
7910 ins_pipe(ialu_reg_reg_ialu);
7911 %}
7912
7913 instruct cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp, flagsReg ccr ) %{
7914 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
7915 effect(KILL ccr, TEMP tmp);
7916 ins_cost(DEFAULT_COST*3);
7917
7918 format %{ "SUBcc $p,$q,$p\t! p' = p-q\n\t"
7919 "ADD $p,$y,$tmp\t! g3=p-q+y\n\t"
7920 "MOVl $tmp,$p\t! p' < 0 ? p'+y : p'" %}
7921 ins_encode( enc_cadd_cmpLTMask(p, q, y, tmp) );
7922 ins_pipe( cadd_cmpltmask );
7923 %}
7924
7925 instruct cadd_cmpLTMask2( iRegI p, iRegI q, iRegI y, iRegI tmp, flagsReg ccr ) %{
7926 match(Set p (AddI (SubI p q) (AndI (CmpLTMask p q) y)));
7927 effect( KILL ccr, TEMP tmp);
7928 ins_cost(DEFAULT_COST*3);
7929
7930 format %{ "SUBcc $p,$q,$p\t! p' = p-q\n\t"
7931 "ADD $p,$y,$tmp\t! g3=p-q+y\n\t"
7932 "MOVl $tmp,$p\t! p' < 0 ? p'+y : p'" %}
7933 ins_encode( enc_cadd_cmpLTMask(p, q, y, tmp) );
7934 ins_pipe( cadd_cmpltmask );
7935 %}
7936
7937 //----------Arithmetic Conversion Instructions---------------------------------
7938 // The conversions operations are all Alpha sorted. Please keep it that way!
7939
7940 instruct convD2F_reg(regF dst, regD src) %{
7941 match(Set dst (ConvD2F src));
7942 size(4);
7943 format %{ "FDTOS $src,$dst" %}
7944 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdtos_opf);
7945 ins_encode(form3_opf_rs2D_rdF(src, dst));
7946 ins_pipe(fcvtD2F);
7947 %}
7948
7949
7950 // Convert a double to an int in a float register.
7951 // If the double is a NAN, stuff a zero in instead.
7952 instruct convD2I_helper(regF dst, regD src, flagsRegF0 fcc0) %{
7953 effect(DEF dst, USE src, KILL fcc0);
7954 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t"
7955 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
7956 "FDTOI $src,$dst\t! convert in delay slot\n\t"
7957 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t"
7958 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n"
7959 "skip:" %}
7960 ins_encode(form_d2i_helper(src,dst));
7961 ins_pipe(fcvtD2I);
7962 %}
7963
7964 instruct convD2I_reg(stackSlotI dst, regD src) %{
7965 match(Set dst (ConvD2I src));
7966 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
7967 expand %{
7968 regF tmp;
7969 convD2I_helper(tmp, src);
7970 regF_to_stkI(dst, tmp);
7971 %}
7972 %}
7973
7974 // Convert a double to a long in a double register.
7975 // If the double is a NAN, stuff a zero in instead.
7976 instruct convD2L_helper(regD dst, regD src, flagsRegF0 fcc0) %{
7977 effect(DEF dst, USE src, KILL fcc0);
7978 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t"
7979 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
7980 "FDTOX $src,$dst\t! convert in delay slot\n\t"
7981 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t"
7982 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n"
7983 "skip:" %}
7984 ins_encode(form_d2l_helper(src,dst));
7985 ins_pipe(fcvtD2L);
7986 %}
7987
7988
7989 // Double to Long conversion
7990 instruct convD2L_reg(stackSlotL dst, regD src) %{
7991 match(Set dst (ConvD2L src));
7992 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
7993 expand %{
7994 regD tmp;
7995 convD2L_helper(tmp, src);
7996 regD_to_stkL(dst, tmp);
7997 %}
7998 %}
7999
8000
8001 instruct convF2D_reg(regD dst, regF src) %{
8002 match(Set dst (ConvF2D src));
8003 format %{ "FSTOD $src,$dst" %}
8004 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fstod_opf);
8005 ins_encode(form3_opf_rs2F_rdD(src, dst));
8006 ins_pipe(fcvtF2D);
8007 %}
8008
8009
8010 instruct convF2I_helper(regF dst, regF src, flagsRegF0 fcc0) %{
8011 effect(DEF dst, USE src, KILL fcc0);
8012 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t"
8013 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8014 "FSTOI $src,$dst\t! convert in delay slot\n\t"
8015 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t"
8016 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n"
8017 "skip:" %}
8018 ins_encode(form_f2i_helper(src,dst));
8019 ins_pipe(fcvtF2I);
8020 %}
8021
8022 instruct convF2I_reg(stackSlotI dst, regF src) %{
8023 match(Set dst (ConvF2I src));
8024 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8025 expand %{
8026 regF tmp;
8027 convF2I_helper(tmp, src);
8028 regF_to_stkI(dst, tmp);
8029 %}
8030 %}
8031
8032
8033 instruct convF2L_helper(regD dst, regF src, flagsRegF0 fcc0) %{
8034 effect(DEF dst, USE src, KILL fcc0);
8035 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t"
8036 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8037 "FSTOX $src,$dst\t! convert in delay slot\n\t"
8038 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t"
8039 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n"
8040 "skip:" %}
8041 ins_encode(form_f2l_helper(src,dst));
8042 ins_pipe(fcvtF2L);
8043 %}
8044
8045 // Float to Long conversion
8046 instruct convF2L_reg(stackSlotL dst, regF src) %{
8047 match(Set dst (ConvF2L src));
8048 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8049 expand %{
8050 regD tmp;
8051 convF2L_helper(tmp, src);
8052 regD_to_stkL(dst, tmp);
8053 %}
8054 %}
8055
8056
8057 instruct convI2D_helper(regD dst, regF tmp) %{
8058 effect(USE tmp, DEF dst);
8059 format %{ "FITOD $tmp,$dst" %}
8060 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf);
8061 ins_encode(form3_opf_rs2F_rdD(tmp, dst));
8062 ins_pipe(fcvtI2D);
8063 %}
8064
8065 instruct convI2D_reg(stackSlotI src, regD dst) %{
8066 match(Set dst (ConvI2D src));
8067 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8068 expand %{
8069 regF tmp;
8070 stkI_to_regF( tmp, src);
8071 convI2D_helper( dst, tmp);
8072 %}
8073 %}
8074
8075 instruct convI2D_mem( regD_low dst, memory mem ) %{
8076 match(Set dst (ConvI2D (LoadI mem)));
8077 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8078 size(8);
8079 format %{ "LDF $mem,$dst\n\t"
8080 "FITOD $dst,$dst" %}
8081 opcode(Assembler::ldf_op3, Assembler::fitod_opf);
8082 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst));
8083 ins_pipe(floadF_mem);
8084 %}
8085
8086
8087 instruct convI2F_helper(regF dst, regF tmp) %{
8088 effect(DEF dst, USE tmp);
8089 format %{ "FITOS $tmp,$dst" %}
8090 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitos_opf);
8091 ins_encode(form3_opf_rs2F_rdF(tmp, dst));
8092 ins_pipe(fcvtI2F);
8093 %}
8094
8095 instruct convI2F_reg( regF dst, stackSlotI src ) %{
8096 match(Set dst (ConvI2F src));
8097 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8098 expand %{
8099 regF tmp;
8100 stkI_to_regF(tmp,src);
8101 convI2F_helper(dst, tmp);
8102 %}
8103 %}
8104
8105 instruct convI2F_mem( regF dst, memory mem ) %{
8106 match(Set dst (ConvI2F (LoadI mem)));
8107 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8108 size(8);
8109 format %{ "LDF $mem,$dst\n\t"
8110 "FITOS $dst,$dst" %}
8111 opcode(Assembler::ldf_op3, Assembler::fitos_opf);
8112 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst));
8113 ins_pipe(floadF_mem);
8114 %}
8115
8116
8117 instruct convI2L_reg(iRegL dst, iRegI src) %{
8118 match(Set dst (ConvI2L src));
8119 size(4);
8120 format %{ "SRA $src,0,$dst\t! int->long" %}
8121 opcode(Assembler::sra_op3, Assembler::arith_op);
8122 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
8123 ins_pipe(ialu_reg_reg);
8124 %}
8125
8126 // Zero-extend convert int to long
8127 instruct convI2L_reg_zex(iRegL dst, iRegI src, immL_32bits mask ) %{
8128 match(Set dst (AndL (ConvI2L src) mask) );
8129 size(4);
8130 format %{ "SRL $src,0,$dst\t! zero-extend int to long" %}
8131 opcode(Assembler::srl_op3, Assembler::arith_op);
8132 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
8133 ins_pipe(ialu_reg_reg);
8134 %}
8135
8136 // Zero-extend long
8137 instruct zerox_long(iRegL dst, iRegL src, immL_32bits mask ) %{
8138 match(Set dst (AndL src mask) );
8139 size(4);
8140 format %{ "SRL $src,0,$dst\t! zero-extend long" %}
8141 opcode(Assembler::srl_op3, Assembler::arith_op);
8142 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
8143 ins_pipe(ialu_reg_reg);
8144 %}
8145
8146 instruct MoveF2I_stack_reg(iRegI dst, stackSlotF src) %{
8147 match(Set dst (MoveF2I src));
8148 effect(DEF dst, USE src);
8149 ins_cost(MEMORY_REF_COST);
8150
8151 size(4);
8152 format %{ "LDUW $src,$dst\t! MoveF2I" %}
8153 opcode(Assembler::lduw_op3);
8154 ins_encode(simple_form3_mem_reg( src, dst ) );
8155 ins_pipe(iload_mem);
8156 %}
8157
8158 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
8159 match(Set dst (MoveI2F src));
8160 effect(DEF dst, USE src);
8161 ins_cost(MEMORY_REF_COST);
8162
8163 size(4);
8164 format %{ "LDF $src,$dst\t! MoveI2F" %}
8165 opcode(Assembler::ldf_op3);
8166 ins_encode(simple_form3_mem_reg(src, dst));
8167 ins_pipe(floadF_stk);
8168 %}
8169
8170 instruct MoveD2L_stack_reg(iRegL dst, stackSlotD src) %{
8171 match(Set dst (MoveD2L src));
8172 effect(DEF dst, USE src);
8173 ins_cost(MEMORY_REF_COST);
8174
8175 size(4);
8176 format %{ "LDX $src,$dst\t! MoveD2L" %}
8177 opcode(Assembler::ldx_op3);
8178 ins_encode(simple_form3_mem_reg( src, dst ) );
8179 ins_pipe(iload_mem);
8180 %}
8181
8182 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
8183 match(Set dst (MoveL2D src));
8184 effect(DEF dst, USE src);
8185 ins_cost(MEMORY_REF_COST);
8186
8187 size(4);
8188 format %{ "LDDF $src,$dst\t! MoveL2D" %}
8189 opcode(Assembler::lddf_op3);
8190 ins_encode(simple_form3_mem_reg(src, dst));
8191 ins_pipe(floadD_stk);
8192 %}
8193
8194 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{
8195 match(Set dst (MoveF2I src));
8196 effect(DEF dst, USE src);
8197 ins_cost(MEMORY_REF_COST);
8198
8199 size(4);
8200 format %{ "STF $src,$dst\t!MoveF2I" %}
8201 opcode(Assembler::stf_op3);
8202 ins_encode(simple_form3_mem_reg(dst, src));
8203 ins_pipe(fstoreF_stk_reg);
8204 %}
8205
8206 instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{
8207 match(Set dst (MoveI2F src));
8208 effect(DEF dst, USE src);
8209 ins_cost(MEMORY_REF_COST);
8210
8211 size(4);
8212 format %{ "STW $src,$dst\t!MoveI2F" %}
8213 opcode(Assembler::stw_op3);
8214 ins_encode(simple_form3_mem_reg( dst, src ) );
8215 ins_pipe(istore_mem_reg);
8216 %}
8217
8218 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
8219 match(Set dst (MoveD2L src));
8220 effect(DEF dst, USE src);
8221 ins_cost(MEMORY_REF_COST);
8222
8223 size(4);
8224 format %{ "STDF $src,$dst\t!MoveD2L" %}
8225 opcode(Assembler::stdf_op3);
8226 ins_encode(simple_form3_mem_reg(dst, src));
8227 ins_pipe(fstoreD_stk_reg);
8228 %}
8229
8230 instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{
8231 match(Set dst (MoveL2D src));
8232 effect(DEF dst, USE src);
8233 ins_cost(MEMORY_REF_COST);
8234
8235 size(4);
8236 format %{ "STX $src,$dst\t!MoveL2D" %}
8237 opcode(Assembler::stx_op3);
8238 ins_encode(simple_form3_mem_reg( dst, src ) );
8239 ins_pipe(istore_mem_reg);
8240 %}
8241
8242
8243 //-----------
8244 // Long to Double conversion using V8 opcodes.
8245 // Still useful because cheetah traps and becomes
8246 // amazingly slow for some common numbers.
8247
8248 // Magic constant, 0x43300000
8249 instruct loadConI_x43300000(iRegI dst) %{
8250 effect(DEF dst);
8251 size(4);
8252 format %{ "SETHI HI(0x43300000),$dst\t! 2^52" %}
8253 ins_encode(SetHi22(0x43300000, dst));
8254 ins_pipe(ialu_none);
8255 %}
8256
8257 // Magic constant, 0x41f00000
8258 instruct loadConI_x41f00000(iRegI dst) %{
8259 effect(DEF dst);
8260 size(4);
8261 format %{ "SETHI HI(0x41f00000),$dst\t! 2^32" %}
8262 ins_encode(SetHi22(0x41f00000, dst));
8263 ins_pipe(ialu_none);
8264 %}
8265
8266 // Construct a double from two float halves
8267 instruct regDHi_regDLo_to_regD(regD_low dst, regD_low src1, regD_low src2) %{
8268 effect(DEF dst, USE src1, USE src2);
8269 size(8);
8270 format %{ "FMOVS $src1.hi,$dst.hi\n\t"
8271 "FMOVS $src2.lo,$dst.lo" %}
8272 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmovs_opf);
8273 ins_encode(form3_opf_rs2D_hi_rdD_hi(src1, dst), form3_opf_rs2D_lo_rdD_lo(src2, dst));
8274 ins_pipe(faddD_reg_reg);
8275 %}
8276
8277 // Convert integer in high half of a double register (in the lower half of
8278 // the double register file) to double
8279 instruct convI2D_regDHi_regD(regD dst, regD_low src) %{
8280 effect(DEF dst, USE src);
8281 size(4);
8282 format %{ "FITOD $src,$dst" %}
8283 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf);
8284 ins_encode(form3_opf_rs2D_rdD(src, dst));
8285 ins_pipe(fcvtLHi2D);
8286 %}
8287
8288 // Add float double precision
8289 instruct addD_regD_regD(regD dst, regD src1, regD src2) %{
8290 effect(DEF dst, USE src1, USE src2);
8291 size(4);
8292 format %{ "FADDD $src1,$src2,$dst" %}
8293 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf);
8294 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8295 ins_pipe(faddD_reg_reg);
8296 %}
8297
8298 // Sub float double precision
8299 instruct subD_regD_regD(regD dst, regD src1, regD src2) %{
8300 effect(DEF dst, USE src1, USE src2);
8301 size(4);
8302 format %{ "FSUBD $src1,$src2,$dst" %}
8303 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf);
8304 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8305 ins_pipe(faddD_reg_reg);
8306 %}
8307
8308 // Mul float double precision
8309 instruct mulD_regD_regD(regD dst, regD src1, regD src2) %{
8310 effect(DEF dst, USE src1, USE src2);
8311 size(4);
8312 format %{ "FMULD $src1,$src2,$dst" %}
8313 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf);
8314 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8315 ins_pipe(fmulD_reg_reg);
8316 %}
8317
8318 instruct convL2D_reg_slow_fxtof(regD dst, stackSlotL src) %{
8319 match(Set dst (ConvL2D src));
8320 ins_cost(DEFAULT_COST*8 + MEMORY_REF_COST*6);
8321
8322 expand %{
8323 regD_low tmpsrc;
8324 iRegI ix43300000;
8325 iRegI ix41f00000;
8326 stackSlotL lx43300000;
8327 stackSlotL lx41f00000;
8328 regD_low dx43300000;
8329 regD dx41f00000;
8330 regD tmp1;
8331 regD_low tmp2;
8332 regD tmp3;
8333 regD tmp4;
8334
8335 stkL_to_regD(tmpsrc, src);
8336
8337 loadConI_x43300000(ix43300000);
8338 loadConI_x41f00000(ix41f00000);
8339 regI_to_stkLHi(lx43300000, ix43300000);
8340 regI_to_stkLHi(lx41f00000, ix41f00000);
8341 stkL_to_regD(dx43300000, lx43300000);
8342 stkL_to_regD(dx41f00000, lx41f00000);
8343
8344 convI2D_regDHi_regD(tmp1, tmpsrc);
8345 regDHi_regDLo_to_regD(tmp2, dx43300000, tmpsrc);
8346 subD_regD_regD(tmp3, tmp2, dx43300000);
8347 mulD_regD_regD(tmp4, tmp1, dx41f00000);
8348 addD_regD_regD(dst, tmp3, tmp4);
8349 %}
8350 %}
8351
8352 // Long to Double conversion using fast fxtof
8353 instruct convL2D_helper(regD dst, regD tmp) %{
8354 effect(DEF dst, USE tmp);
8355 size(4);
8356 format %{ "FXTOD $tmp,$dst" %}
8357 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtod_opf);
8358 ins_encode(form3_opf_rs2D_rdD(tmp, dst));
8359 ins_pipe(fcvtL2D);
8360 %}
8361
8362 instruct convL2D_reg_fast_fxtof(regD dst, stackSlotL src) %{
8363 predicate(VM_Version::has_fast_fxtof());
8364 match(Set dst (ConvL2D src));
8365 ins_cost(DEFAULT_COST + 3 * MEMORY_REF_COST);
8366 expand %{
8367 regD tmp;
8368 stkL_to_regD(tmp, src);
8369 convL2D_helper(dst, tmp);
8370 %}
8371 %}
8372
8373 //-----------
8374 // Long to Float conversion using V8 opcodes.
8375 // Still useful because cheetah traps and becomes
8376 // amazingly slow for some common numbers.
8377
8378 // Long to Float conversion using fast fxtof
8379 instruct convL2F_helper(regF dst, regD tmp) %{
8380 effect(DEF dst, USE tmp);
8381 size(4);
8382 format %{ "FXTOS $tmp,$dst" %}
8383 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtos_opf);
8384 ins_encode(form3_opf_rs2D_rdF(tmp, dst));
8385 ins_pipe(fcvtL2F);
8386 %}
8387
8388 instruct convL2F_reg_fast_fxtof(regF dst, stackSlotL src) %{
8389 match(Set dst (ConvL2F src));
8390 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8391 expand %{
8392 regD tmp;
8393 stkL_to_regD(tmp, src);
8394 convL2F_helper(dst, tmp);
8395 %}
8396 %}
8397 //-----------
8398
8399 instruct convL2I_reg(iRegI dst, iRegL src) %{
8400 match(Set dst (ConvL2I src));
8401 #ifndef _LP64
8402 format %{ "MOV $src.lo,$dst\t! long->int" %}
8403 ins_encode( form3_g0_rs2_rd_move_lo2( src, dst ) );
8404 ins_pipe(ialu_move_reg_I_to_L);
8405 #else
8406 size(4);
8407 format %{ "SRA $src,R_G0,$dst\t! long->int" %}
8408 ins_encode( form3_rs1_rd_signextend_lo1( src, dst ) );
8409 ins_pipe(ialu_reg);
8410 #endif
8411 %}
8412
8413 // Register Shift Right Immediate
8414 instruct shrL_reg_imm6_L2I(iRegI dst, iRegL src, immI_32_63 cnt) %{
8415 match(Set dst (ConvL2I (RShiftL src cnt)));
8416
8417 size(4);
8418 format %{ "SRAX $src,$cnt,$dst" %}
8419 opcode(Assembler::srax_op3, Assembler::arith_op);
8420 ins_encode( form3_sd_rs1_imm6_rd( src, cnt, dst ) );
8421 ins_pipe(ialu_reg_imm);
8422 %}
8423
8424 // Replicate scalar to packed byte values in Double register
8425 instruct Repl8B_reg_helper(iRegL dst, iRegI src) %{
8426 effect(DEF dst, USE src);
8427 format %{ "SLLX $src,56,$dst\n\t"
8428 "SRLX $dst, 8,O7\n\t"
8429 "OR $dst,O7,$dst\n\t"
8430 "SRLX $dst,16,O7\n\t"
8431 "OR $dst,O7,$dst\n\t"
8432 "SRLX $dst,32,O7\n\t"
8433 "OR $dst,O7,$dst\t! replicate8B" %}
8434 ins_encode( enc_repl8b(src, dst));
8435 ins_pipe(ialu_reg);
8436 %}
8437
8438 // Replicate scalar to packed byte values in Double register
8439 instruct Repl8B_reg(stackSlotD dst, iRegI src) %{
8440 match(Set dst (Replicate8B src));
8441 expand %{
8442 iRegL tmp;
8443 Repl8B_reg_helper(tmp, src);
8444 regL_to_stkD(dst, tmp);
8445 %}
8446 %}
8447
8448 // Replicate scalar constant to packed byte values in Double register
8449 instruct Repl8B_immI(regD dst, immI13 src, o7RegP tmp) %{
8450 match(Set dst (Replicate8B src));
8451 #ifdef _LP64
8452 size(36);
8453 #else
8454 size(8);
8455 #endif
8456 format %{ "SETHI hi(&Repl8($src)),$tmp\t!get Repl8B($src) from table\n\t"
8457 "LDDF [$tmp+lo(&Repl8($src))],$dst" %}
8458 ins_encode( LdReplImmI(src, dst, tmp, (8), (1)) );
8459 ins_pipe(loadConFD);
8460 %}
8461
8462 // Replicate scalar to packed char values into stack slot
8463 instruct Repl4C_reg_helper(iRegL dst, iRegI src) %{
8464 effect(DEF dst, USE src);
8465 format %{ "SLLX $src,48,$dst\n\t"
8466 "SRLX $dst,16,O7\n\t"
8467 "OR $dst,O7,$dst\n\t"
8468 "SRLX $dst,32,O7\n\t"
8469 "OR $dst,O7,$dst\t! replicate4C" %}
8470 ins_encode( enc_repl4s(src, dst) );
8471 ins_pipe(ialu_reg);
8472 %}
8473
8474 // Replicate scalar to packed char values into stack slot
8475 instruct Repl4C_reg(stackSlotD dst, iRegI src) %{
8476 match(Set dst (Replicate4C src));
8477 expand %{
8478 iRegL tmp;
8479 Repl4C_reg_helper(tmp, src);
8480 regL_to_stkD(dst, tmp);
8481 %}
8482 %}
8483
8484 // Replicate scalar constant to packed char values in Double register
8485 instruct Repl4C_immI(regD dst, immI src, o7RegP tmp) %{
8486 match(Set dst (Replicate4C src));
8487 #ifdef _LP64
8488 size(36);
8489 #else
8490 size(8);
8491 #endif
8492 format %{ "SETHI hi(&Repl4($src)),$tmp\t!get Repl4C($src) from table\n\t"
8493 "LDDF [$tmp+lo(&Repl4($src))],$dst" %}
8494 ins_encode( LdReplImmI(src, dst, tmp, (4), (2)) );
8495 ins_pipe(loadConFD);
8496 %}
8497
8498 // Replicate scalar to packed short values into stack slot
8499 instruct Repl4S_reg_helper(iRegL dst, iRegI src) %{
8500 effect(DEF dst, USE src);
8501 format %{ "SLLX $src,48,$dst\n\t"
8502 "SRLX $dst,16,O7\n\t"
8503 "OR $dst,O7,$dst\n\t"
8504 "SRLX $dst,32,O7\n\t"
8505 "OR $dst,O7,$dst\t! replicate4S" %}
8506 ins_encode( enc_repl4s(src, dst) );
8507 ins_pipe(ialu_reg);
8508 %}
8509
8510 // Replicate scalar to packed short values into stack slot
8511 instruct Repl4S_reg(stackSlotD dst, iRegI src) %{
8512 match(Set dst (Replicate4S src));
8513 expand %{
8514 iRegL tmp;
8515 Repl4S_reg_helper(tmp, src);
8516 regL_to_stkD(dst, tmp);
8517 %}
8518 %}
8519
8520 // Replicate scalar constant to packed short values in Double register
8521 instruct Repl4S_immI(regD dst, immI src, o7RegP tmp) %{
8522 match(Set dst (Replicate4S src));
8523 #ifdef _LP64
8524 size(36);
8525 #else
8526 size(8);
8527 #endif
8528 format %{ "SETHI hi(&Repl4($src)),$tmp\t!get Repl4S($src) from table\n\t"
8529 "LDDF [$tmp+lo(&Repl4($src))],$dst" %}
8530 ins_encode( LdReplImmI(src, dst, tmp, (4), (2)) );
8531 ins_pipe(loadConFD);
8532 %}
8533
8534 // Replicate scalar to packed int values in Double register
8535 instruct Repl2I_reg_helper(iRegL dst, iRegI src) %{
8536 effect(DEF dst, USE src);
8537 format %{ "SLLX $src,32,$dst\n\t"
8538 "SRLX $dst,32,O7\n\t"
8539 "OR $dst,O7,$dst\t! replicate2I" %}
8540 ins_encode( enc_repl2i(src, dst));
8541 ins_pipe(ialu_reg);
8542 %}
8543
8544 // Replicate scalar to packed int values in Double register
8545 instruct Repl2I_reg(stackSlotD dst, iRegI src) %{
8546 match(Set dst (Replicate2I src));
8547 expand %{
8548 iRegL tmp;
8549 Repl2I_reg_helper(tmp, src);
8550 regL_to_stkD(dst, tmp);
8551 %}
8552 %}
8553
8554 // Replicate scalar zero constant to packed int values in Double register
8555 instruct Repl2I_immI(regD dst, immI src, o7RegP tmp) %{
8556 match(Set dst (Replicate2I src));
8557 #ifdef _LP64
8558 size(36);
8559 #else
8560 size(8);
8561 #endif
8562 format %{ "SETHI hi(&Repl2($src)),$tmp\t!get Repl2I($src) from table\n\t"
8563 "LDDF [$tmp+lo(&Repl2($src))],$dst" %}
8564 ins_encode( LdReplImmI(src, dst, tmp, (2), (4)) );
8565 ins_pipe(loadConFD);
8566 %}
8567
8568 //----------Control Flow Instructions------------------------------------------
8569 // Compare Instructions
8570 // Compare Integers
8571 instruct compI_iReg(flagsReg icc, iRegI op1, iRegI op2) %{
8572 match(Set icc (CmpI op1 op2));
8573 effect( DEF icc, USE op1, USE op2 );
8574
8575 size(4);
8576 format %{ "CMP $op1,$op2" %}
8577 opcode(Assembler::subcc_op3, Assembler::arith_op);
8578 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8579 ins_pipe(ialu_cconly_reg_reg);
8580 %}
8581
8582 instruct compU_iReg(flagsRegU icc, iRegI op1, iRegI op2) %{
8583 match(Set icc (CmpU op1 op2));
8584
8585 size(4);
8586 format %{ "CMP $op1,$op2\t! unsigned" %}
8587 opcode(Assembler::subcc_op3, Assembler::arith_op);
8588 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8589 ins_pipe(ialu_cconly_reg_reg);
8590 %}
8591
8592 instruct compI_iReg_imm13(flagsReg icc, iRegI op1, immI13 op2) %{
8593 match(Set icc (CmpI op1 op2));
8594 effect( DEF icc, USE op1 );
8595
8596 size(4);
8597 format %{ "CMP $op1,$op2" %}
8598 opcode(Assembler::subcc_op3, Assembler::arith_op);
8599 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8600 ins_pipe(ialu_cconly_reg_imm);
8601 %}
8602
8603 instruct testI_reg_reg( flagsReg icc, iRegI op1, iRegI op2, immI0 zero ) %{
8604 match(Set icc (CmpI (AndI op1 op2) zero));
8605
8606 size(4);
8607 format %{ "BTST $op2,$op1" %}
8608 opcode(Assembler::andcc_op3, Assembler::arith_op);
8609 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8610 ins_pipe(ialu_cconly_reg_reg_zero);
8611 %}
8612
8613 instruct testI_reg_imm( flagsReg icc, iRegI op1, immI13 op2, immI0 zero ) %{
8614 match(Set icc (CmpI (AndI op1 op2) zero));
8615
8616 size(4);
8617 format %{ "BTST $op2,$op1" %}
8618 opcode(Assembler::andcc_op3, Assembler::arith_op);
8619 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8620 ins_pipe(ialu_cconly_reg_imm_zero);
8621 %}
8622
8623 instruct compL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2 ) %{
8624 match(Set xcc (CmpL op1 op2));
8625 effect( DEF xcc, USE op1, USE op2 );
8626
8627 size(4);
8628 format %{ "CMP $op1,$op2\t\t! long" %}
8629 opcode(Assembler::subcc_op3, Assembler::arith_op);
8630 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8631 ins_pipe(ialu_cconly_reg_reg);
8632 %}
8633
8634 instruct compL_reg_con(flagsRegL xcc, iRegL op1, immL13 con) %{
8635 match(Set xcc (CmpL op1 con));
8636 effect( DEF xcc, USE op1, USE con );
8637
8638 size(4);
8639 format %{ "CMP $op1,$con\t\t! long" %}
8640 opcode(Assembler::subcc_op3, Assembler::arith_op);
8641 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) );
8642 ins_pipe(ialu_cconly_reg_reg);
8643 %}
8644
8645 instruct testL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2, immL0 zero) %{
8646 match(Set xcc (CmpL (AndL op1 op2) zero));
8647 effect( DEF xcc, USE op1, USE op2 );
8648
8649 size(4);
8650 format %{ "BTST $op1,$op2\t\t! long" %}
8651 opcode(Assembler::andcc_op3, Assembler::arith_op);
8652 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8653 ins_pipe(ialu_cconly_reg_reg);
8654 %}
8655
8656 // useful for checking the alignment of a pointer:
8657 instruct testL_reg_con(flagsRegL xcc, iRegL op1, immL13 con, immL0 zero) %{
8658 match(Set xcc (CmpL (AndL op1 con) zero));
8659 effect( DEF xcc, USE op1, USE con );
8660
8661 size(4);
8662 format %{ "BTST $op1,$con\t\t! long" %}
8663 opcode(Assembler::andcc_op3, Assembler::arith_op);
8664 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) );
8665 ins_pipe(ialu_cconly_reg_reg);
8666 %}
8667
8668 instruct compU_iReg_imm13(flagsRegU icc, iRegI op1, immU13 op2 ) %{
8669 match(Set icc (CmpU op1 op2));
8670
8671 size(4);
8672 format %{ "CMP $op1,$op2\t! unsigned" %}
8673 opcode(Assembler::subcc_op3, Assembler::arith_op);
8674 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8675 ins_pipe(ialu_cconly_reg_imm);
8676 %}
8677
8678 // Compare Pointers
8679 instruct compP_iRegP(flagsRegP pcc, iRegP op1, iRegP op2 ) %{
8680 match(Set pcc (CmpP op1 op2));
8681
8682 size(4);
8683 format %{ "CMP $op1,$op2\t! ptr" %}
8684 opcode(Assembler::subcc_op3, Assembler::arith_op);
8685 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8686 ins_pipe(ialu_cconly_reg_reg);
8687 %}
8688
8689 instruct compP_iRegP_imm13(flagsRegP pcc, iRegP op1, immP13 op2 ) %{
8690 match(Set pcc (CmpP op1 op2));
8691
8692 size(4);
8693 format %{ "CMP $op1,$op2\t! ptr" %}
8694 opcode(Assembler::subcc_op3, Assembler::arith_op);
8695 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8696 ins_pipe(ialu_cconly_reg_imm);
8697 %}
8698
8699 // Compare Narrow oops
8700 instruct compN_iRegN(flagsReg icc, iRegN op1, iRegN op2 ) %{
8701 match(Set icc (CmpN op1 op2));
8702
8703 size(4);
8704 format %{ "CMP $op1,$op2\t! compressed ptr" %}
8705 opcode(Assembler::subcc_op3, Assembler::arith_op);
8706 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8707 ins_pipe(ialu_cconly_reg_reg);
8708 %}
8709
8710 instruct compN_iRegN_immN0(flagsReg icc, iRegN op1, immN0 op2 ) %{
8711 match(Set icc (CmpN op1 op2));
8712
8713 size(4);
8714 format %{ "CMP $op1,$op2\t! compressed ptr" %}
8715 opcode(Assembler::subcc_op3, Assembler::arith_op);
8716 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8717 ins_pipe(ialu_cconly_reg_imm);
8718 %}
8719
8720 //----------Max and Min--------------------------------------------------------
8721 // Min Instructions
8722 // Conditional move for min
8723 instruct cmovI_reg_lt( iRegI op2, iRegI op1, flagsReg icc ) %{
8724 effect( USE_DEF op2, USE op1, USE icc );
8725
8726 size(4);
8727 format %{ "MOVlt icc,$op1,$op2\t! min" %}
8728 opcode(Assembler::less);
8729 ins_encode( enc_cmov_reg_minmax(op2,op1) );
8730 ins_pipe(ialu_reg_flags);
8731 %}
8732
8733 // Min Register with Register.
8734 instruct minI_eReg(iRegI op1, iRegI op2) %{
8735 match(Set op2 (MinI op1 op2));
8736 ins_cost(DEFAULT_COST*2);
8737 expand %{
8738 flagsReg icc;
8739 compI_iReg(icc,op1,op2);
8740 cmovI_reg_lt(op2,op1,icc);
8741 %}
8742 %}
8743
8744 // Max Instructions
8745 // Conditional move for max
8746 instruct cmovI_reg_gt( iRegI op2, iRegI op1, flagsReg icc ) %{
8747 effect( USE_DEF op2, USE op1, USE icc );
8748 format %{ "MOVgt icc,$op1,$op2\t! max" %}
8749 opcode(Assembler::greater);
8750 ins_encode( enc_cmov_reg_minmax(op2,op1) );
8751 ins_pipe(ialu_reg_flags);
8752 %}
8753
8754 // Max Register with Register
8755 instruct maxI_eReg(iRegI op1, iRegI op2) %{
8756 match(Set op2 (MaxI op1 op2));
8757 ins_cost(DEFAULT_COST*2);
8758 expand %{
8759 flagsReg icc;
8760 compI_iReg(icc,op1,op2);
8761 cmovI_reg_gt(op2,op1,icc);
8762 %}
8763 %}
8764
8765
8766 //----------Float Compares----------------------------------------------------
8767 // Compare floating, generate condition code
8768 instruct cmpF_cc(flagsRegF fcc, regF src1, regF src2) %{
8769 match(Set fcc (CmpF src1 src2));
8770
8771 size(4);
8772 format %{ "FCMPs $fcc,$src1,$src2" %}
8773 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmps_opf);
8774 ins_encode( form3_opf_rs1F_rs2F_fcc( src1, src2, fcc ) );
8775 ins_pipe(faddF_fcc_reg_reg_zero);
8776 %}
8777
8778 instruct cmpD_cc(flagsRegF fcc, regD src1, regD src2) %{
8779 match(Set fcc (CmpD src1 src2));
8780
8781 size(4);
8782 format %{ "FCMPd $fcc,$src1,$src2" %}
8783 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmpd_opf);
8784 ins_encode( form3_opf_rs1D_rs2D_fcc( src1, src2, fcc ) );
8785 ins_pipe(faddD_fcc_reg_reg_zero);
8786 %}
8787
8788
8789 // Compare floating, generate -1,0,1
8790 instruct cmpF_reg(iRegI dst, regF src1, regF src2, flagsRegF0 fcc0) %{
8791 match(Set dst (CmpF3 src1 src2));
8792 effect(KILL fcc0);
8793 ins_cost(DEFAULT_COST*3+BRANCH_COST*3);
8794 format %{ "fcmpl $dst,$src1,$src2" %}
8795 // Primary = float
8796 opcode( true );
8797 ins_encode( floating_cmp( dst, src1, src2 ) );
8798 ins_pipe( floating_cmp );
8799 %}
8800
8801 instruct cmpD_reg(iRegI dst, regD src1, regD src2, flagsRegF0 fcc0) %{
8802 match(Set dst (CmpD3 src1 src2));
8803 effect(KILL fcc0);
8804 ins_cost(DEFAULT_COST*3+BRANCH_COST*3);
8805 format %{ "dcmpl $dst,$src1,$src2" %}
8806 // Primary = double (not float)
8807 opcode( false );
8808 ins_encode( floating_cmp( dst, src1, src2 ) );
8809 ins_pipe( floating_cmp );
8810 %}
8811
8812 //----------Branches---------------------------------------------------------
8813 // Jump
8814 // (compare 'operand indIndex' and 'instruct addP_reg_reg' above)
8815 instruct jumpXtnd(iRegX switch_val, o7RegI table) %{
8816 match(Jump switch_val);
8817
8818 ins_cost(350);
8819
8820 format %{ "SETHI [hi(table_base)],O7\n\t"
8821 "ADD O7, lo(table_base), O7\n\t"
8822 "LD [O7+$switch_val], O7\n\t"
8823 "JUMP O7"
8824 %}
8825 ins_encode( jump_enc( switch_val, table) );
8826 ins_pc_relative(1);
8827 ins_pipe(ialu_reg_reg);
8828 %}
8829
8830 // Direct Branch. Use V8 version with longer range.
8831 instruct branch(label labl) %{
8832 match(Goto);
8833 effect(USE labl);
8834
8835 size(8);
8836 ins_cost(BRANCH_COST);
8837 format %{ "BA $labl" %}
8838 // Prim = bits 24-22, Secnd = bits 31-30, Tert = cond
8839 opcode(Assembler::br_op2, Assembler::branch_op, Assembler::always);
8840 ins_encode( enc_ba( labl ) );
8841 ins_pc_relative(1);
8842 ins_pipe(br);
8843 %}
8844
8845 // Conditional Direct Branch
8846 instruct branchCon(cmpOp cmp, flagsReg icc, label labl) %{
8847 match(If cmp icc);
8848 effect(USE labl);
8849
8850 size(8);
8851 ins_cost(BRANCH_COST);
8852 format %{ "BP$cmp $icc,$labl" %}
8853 // Prim = bits 24-22, Secnd = bits 31-30
8854 ins_encode( enc_bp( labl, cmp, icc ) );
8855 ins_pc_relative(1);
8856 ins_pipe(br_cc);
8857 %}
8858
8859 // Branch-on-register tests all 64 bits. We assume that values
8860 // in 64-bit registers always remains zero or sign extended
8861 // unless our code munges the high bits. Interrupts can chop
8862 // the high order bits to zero or sign at any time.
8863 instruct branchCon_regI(cmpOp_reg cmp, iRegI op1, immI0 zero, label labl) %{
8864 match(If cmp (CmpI op1 zero));
8865 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
8866 effect(USE labl);
8867
8868 size(8);
8869 ins_cost(BRANCH_COST);
8870 format %{ "BR$cmp $op1,$labl" %}
8871 ins_encode( enc_bpr( labl, cmp, op1 ) );
8872 ins_pc_relative(1);
8873 ins_pipe(br_reg);
8874 %}
8875
8876 instruct branchCon_regP(cmpOp_reg cmp, iRegP op1, immP0 null, label labl) %{
8877 match(If cmp (CmpP op1 null));
8878 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
8879 effect(USE labl);
8880
8881 size(8);
8882 ins_cost(BRANCH_COST);
8883 format %{ "BR$cmp $op1,$labl" %}
8884 ins_encode( enc_bpr( labl, cmp, op1 ) );
8885 ins_pc_relative(1);
8886 ins_pipe(br_reg);
8887 %}
8888
8889 instruct branchCon_regL(cmpOp_reg cmp, iRegL op1, immL0 zero, label labl) %{
8890 match(If cmp (CmpL op1 zero));
8891 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
8892 effect(USE labl);
8893
8894 size(8);
8895 ins_cost(BRANCH_COST);
8896 format %{ "BR$cmp $op1,$labl" %}
8897 ins_encode( enc_bpr( labl, cmp, op1 ) );
8898 ins_pc_relative(1);
8899 ins_pipe(br_reg);
8900 %}
8901
8902 instruct branchConU(cmpOpU cmp, flagsRegU icc, label labl) %{
8903 match(If cmp icc);
8904 effect(USE labl);
8905
8906 format %{ "BP$cmp $icc,$labl" %}
8907 // Prim = bits 24-22, Secnd = bits 31-30
8908 ins_encode( enc_bp( labl, cmp, icc ) );
8909 ins_pc_relative(1);
8910 ins_pipe(br_cc);
8911 %}
8912
8913 instruct branchConP(cmpOpP cmp, flagsRegP pcc, label labl) %{
8914 match(If cmp pcc);
8915 effect(USE labl);
8916
8917 size(8);
8918 ins_cost(BRANCH_COST);
8919 format %{ "BP$cmp $pcc,$labl" %}
8920 // Prim = bits 24-22, Secnd = bits 31-30
8921 ins_encode( enc_bpx( labl, cmp, pcc ) );
8922 ins_pc_relative(1);
8923 ins_pipe(br_cc);
8924 %}
8925
8926 instruct branchConF(cmpOpF cmp, flagsRegF fcc, label labl) %{
8927 match(If cmp fcc);
8928 effect(USE labl);
8929
8930 size(8);
8931 ins_cost(BRANCH_COST);
8932 format %{ "FBP$cmp $fcc,$labl" %}
8933 // Prim = bits 24-22, Secnd = bits 31-30
8934 ins_encode( enc_fbp( labl, cmp, fcc ) );
8935 ins_pc_relative(1);
8936 ins_pipe(br_fcc);
8937 %}
8938
8939 instruct branchLoopEnd(cmpOp cmp, flagsReg icc, label labl) %{
8940 match(CountedLoopEnd cmp icc);
8941 effect(USE labl);
8942
8943 size(8);
8944 ins_cost(BRANCH_COST);
8945 format %{ "BP$cmp $icc,$labl\t! Loop end" %}
8946 // Prim = bits 24-22, Secnd = bits 31-30
8947 ins_encode( enc_bp( labl, cmp, icc ) );
8948 ins_pc_relative(1);
8949 ins_pipe(br_cc);
8950 %}
8951
8952 instruct branchLoopEndU(cmpOpU cmp, flagsRegU icc, label labl) %{
8953 match(CountedLoopEnd cmp icc);
8954 effect(USE labl);
8955
8956 size(8);
8957 ins_cost(BRANCH_COST);
8958 format %{ "BP$cmp $icc,$labl\t! Loop end" %}
8959 // Prim = bits 24-22, Secnd = bits 31-30
8960 ins_encode( enc_bp( labl, cmp, icc ) );
8961 ins_pc_relative(1);
8962 ins_pipe(br_cc);
8963 %}
8964
8965 // ============================================================================
8966 // Long Compare
8967 //
8968 // Currently we hold longs in 2 registers. Comparing such values efficiently
8969 // is tricky. The flavor of compare used depends on whether we are testing
8970 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit.
8971 // The GE test is the negated LT test. The LE test can be had by commuting
8972 // the operands (yielding a GE test) and then negating; negate again for the
8973 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the
8974 // NE test is negated from that.
8975
8976 // Due to a shortcoming in the ADLC, it mixes up expressions like:
8977 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the
8978 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections
8979 // are collapsed internally in the ADLC's dfa-gen code. The match for
8980 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the
8981 // foo match ends up with the wrong leaf. One fix is to not match both
8982 // reg-reg and reg-zero forms of long-compare. This is unfortunate because
8983 // both forms beat the trinary form of long-compare and both are very useful
8984 // on Intel which has so few registers.
8985
8986 instruct branchCon_long(cmpOp cmp, flagsRegL xcc, label labl) %{
8987 match(If cmp xcc);
8988 effect(USE labl);
8989
8990 size(8);
8991 ins_cost(BRANCH_COST);
8992 format %{ "BP$cmp $xcc,$labl" %}
8993 // Prim = bits 24-22, Secnd = bits 31-30
8994 ins_encode( enc_bpl( labl, cmp, xcc ) );
8995 ins_pc_relative(1);
8996 ins_pipe(br_cc);
8997 %}
8998
8999 // Manifest a CmpL3 result in an integer register. Very painful.
9000 // This is the test to avoid.
9001 instruct cmpL3_reg_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg ccr ) %{
9002 match(Set dst (CmpL3 src1 src2) );
9003 effect( KILL ccr );
9004 ins_cost(6*DEFAULT_COST);
9005 size(24);
9006 format %{ "CMP $src1,$src2\t\t! long\n"
9007 "\tBLT,a,pn done\n"
9008 "\tMOV -1,$dst\t! delay slot\n"
9009 "\tBGT,a,pn done\n"
9010 "\tMOV 1,$dst\t! delay slot\n"
9011 "\tCLR $dst\n"
9012 "done:" %}
9013 ins_encode( cmpl_flag(src1,src2,dst) );
9014 ins_pipe(cmpL_reg);
9015 %}
9016
9017 // Conditional move
9018 instruct cmovLL_reg(cmpOp cmp, flagsRegL xcc, iRegL dst, iRegL src) %{
9019 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src)));
9020 ins_cost(150);
9021 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %}
9022 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9023 ins_pipe(ialu_reg);
9024 %}
9025
9026 instruct cmovLL_imm(cmpOp cmp, flagsRegL xcc, iRegL dst, immL0 src) %{
9027 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src)));
9028 ins_cost(140);
9029 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %}
9030 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
9031 ins_pipe(ialu_imm);
9032 %}
9033
9034 instruct cmovIL_reg(cmpOp cmp, flagsRegL xcc, iRegI dst, iRegI src) %{
9035 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src)));
9036 ins_cost(150);
9037 format %{ "MOV$cmp $xcc,$src,$dst" %}
9038 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9039 ins_pipe(ialu_reg);
9040 %}
9041
9042 instruct cmovIL_imm(cmpOp cmp, flagsRegL xcc, iRegI dst, immI11 src) %{
9043 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src)));
9044 ins_cost(140);
9045 format %{ "MOV$cmp $xcc,$src,$dst" %}
9046 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
9047 ins_pipe(ialu_imm);
9048 %}
9049
9050 instruct cmovNL_reg(cmpOp cmp, flagsRegL xcc, iRegN dst, iRegN src) %{
9051 match(Set dst (CMoveN (Binary cmp xcc) (Binary dst src)));
9052 ins_cost(150);
9053 format %{ "MOV$cmp $xcc,$src,$dst" %}
9054 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9055 ins_pipe(ialu_reg);
9056 %}
9057
9058 instruct cmovPL_reg(cmpOp cmp, flagsRegL xcc, iRegP dst, iRegP src) %{
9059 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src)));
9060 ins_cost(150);
9061 format %{ "MOV$cmp $xcc,$src,$dst" %}
9062 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9063 ins_pipe(ialu_reg);
9064 %}
9065
9066 instruct cmovPL_imm(cmpOp cmp, flagsRegL xcc, iRegP dst, immP0 src) %{
9067 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src)));
9068 ins_cost(140);
9069 format %{ "MOV$cmp $xcc,$src,$dst" %}
9070 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
9071 ins_pipe(ialu_imm);
9072 %}
9073
9074 instruct cmovFL_reg(cmpOp cmp, flagsRegL xcc, regF dst, regF src) %{
9075 match(Set dst (CMoveF (Binary cmp xcc) (Binary dst src)));
9076 ins_cost(150);
9077 opcode(0x101);
9078 format %{ "FMOVS$cmp $xcc,$src,$dst" %}
9079 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) );
9080 ins_pipe(int_conditional_float_move);
9081 %}
9082
9083 instruct cmovDL_reg(cmpOp cmp, flagsRegL xcc, regD dst, regD src) %{
9084 match(Set dst (CMoveD (Binary cmp xcc) (Binary dst src)));
9085 ins_cost(150);
9086 opcode(0x102);
9087 format %{ "FMOVD$cmp $xcc,$src,$dst" %}
9088 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) );
9089 ins_pipe(int_conditional_float_move);
9090 %}
9091
9092 // ============================================================================
9093 // Safepoint Instruction
9094 instruct safePoint_poll(iRegP poll) %{
9095 match(SafePoint poll);
9096 effect(USE poll);
9097
9098 size(4);
9099 #ifdef _LP64
9100 format %{ "LDX [$poll],R_G0\t! Safepoint: poll for GC" %}
9101 #else
9102 format %{ "LDUW [$poll],R_G0\t! Safepoint: poll for GC" %}
9103 #endif
9104 ins_encode %{
9105 __ relocate(relocInfo::poll_type);
9106 __ ld_ptr($poll$$Register, 0, G0);
9107 %}
9108 ins_pipe(loadPollP);
9109 %}
9110
9111 // ============================================================================
9112 // Call Instructions
9113 // Call Java Static Instruction
9114 instruct CallStaticJavaDirect( method meth ) %{
9115 match(CallStaticJava);
9116 effect(USE meth);
9117
9118 size(8);
9119 ins_cost(CALL_COST);
9120 format %{ "CALL,static ; NOP ==> " %}
9121 ins_encode( Java_Static_Call( meth ), call_epilog );
9122 ins_pc_relative(1);
9123 ins_pipe(simple_call);
9124 %}
9125
9126 // Call Java Dynamic Instruction
9127 instruct CallDynamicJavaDirect( method meth ) %{
9128 match(CallDynamicJava);
9129 effect(USE meth);
9130
9131 ins_cost(CALL_COST);
9132 format %{ "SET (empty),R_G5\n\t"
9133 "CALL,dynamic ; NOP ==> " %}
9134 ins_encode( Java_Dynamic_Call( meth ), call_epilog );
9135 ins_pc_relative(1);
9136 ins_pipe(call);
9137 %}
9138
9139 // Call Runtime Instruction
9140 instruct CallRuntimeDirect(method meth, l7RegP l7) %{
9141 match(CallRuntime);
9142 effect(USE meth, KILL l7);
9143 ins_cost(CALL_COST);
9144 format %{ "CALL,runtime" %}
9145 ins_encode( Java_To_Runtime( meth ),
9146 call_epilog, adjust_long_from_native_call );
9147 ins_pc_relative(1);
9148 ins_pipe(simple_call);
9149 %}
9150
9151 // Call runtime without safepoint - same as CallRuntime
9152 instruct CallLeafDirect(method meth, l7RegP l7) %{
9153 match(CallLeaf);
9154 effect(USE meth, KILL l7);
9155 ins_cost(CALL_COST);
9156 format %{ "CALL,runtime leaf" %}
9157 ins_encode( Java_To_Runtime( meth ),
9158 call_epilog,
9159 adjust_long_from_native_call );
9160 ins_pc_relative(1);
9161 ins_pipe(simple_call);
9162 %}
9163
9164 // Call runtime without safepoint - same as CallLeaf
9165 instruct CallLeafNoFPDirect(method meth, l7RegP l7) %{
9166 match(CallLeafNoFP);
9167 effect(USE meth, KILL l7);
9168 ins_cost(CALL_COST);
9169 format %{ "CALL,runtime leaf nofp" %}
9170 ins_encode( Java_To_Runtime( meth ),
9171 call_epilog,
9172 adjust_long_from_native_call );
9173 ins_pc_relative(1);
9174 ins_pipe(simple_call);
9175 %}
9176
9177 // Tail Call; Jump from runtime stub to Java code.
9178 // Also known as an 'interprocedural jump'.
9179 // Target of jump will eventually return to caller.
9180 // TailJump below removes the return address.
9181 instruct TailCalljmpInd(g3RegP jump_target, inline_cache_regP method_oop) %{
9182 match(TailCall jump_target method_oop );
9183
9184 ins_cost(CALL_COST);
9185 format %{ "Jmp $jump_target ; NOP \t! $method_oop holds method oop" %}
9186 ins_encode(form_jmpl(jump_target));
9187 ins_pipe(tail_call);
9188 %}
9189
9190
9191 // Return Instruction
9192 instruct Ret() %{
9193 match(Return);
9194
9195 // The epilogue node did the ret already.
9196 size(0);
9197 format %{ "! return" %}
9198 ins_encode();
9199 ins_pipe(empty);
9200 %}
9201
9202
9203 // Tail Jump; remove the return address; jump to target.
9204 // TailCall above leaves the return address around.
9205 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2).
9206 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a
9207 // "restore" before this instruction (in Epilogue), we need to materialize it
9208 // in %i0.
9209 instruct tailjmpInd(g1RegP jump_target, i0RegP ex_oop) %{
9210 match( TailJump jump_target ex_oop );
9211 ins_cost(CALL_COST);
9212 format %{ "! discard R_O7\n\t"
9213 "Jmp $jump_target ; ADD O7,8,O1 \t! $ex_oop holds exc. oop" %}
9214 ins_encode(form_jmpl_set_exception_pc(jump_target));
9215 // opcode(Assembler::jmpl_op3, Assembler::arith_op);
9216 // The hack duplicates the exception oop into G3, so that CreateEx can use it there.
9217 // ins_encode( form3_rs1_simm13_rd( jump_target, 0x00, R_G0 ), move_return_pc_to_o1() );
9218 ins_pipe(tail_call);
9219 %}
9220
9221 // Create exception oop: created by stack-crawling runtime code.
9222 // Created exception is now available to this handler, and is setup
9223 // just prior to jumping to this handler. No code emitted.
9224 instruct CreateException( o0RegP ex_oop )
9225 %{
9226 match(Set ex_oop (CreateEx));
9227 ins_cost(0);
9228
9229 size(0);
9230 // use the following format syntax
9231 format %{ "! exception oop is in R_O0; no code emitted" %}
9232 ins_encode();
9233 ins_pipe(empty);
9234 %}
9235
9236
9237 // Rethrow exception:
9238 // The exception oop will come in the first argument position.
9239 // Then JUMP (not call) to the rethrow stub code.
9240 instruct RethrowException()
9241 %{
9242 match(Rethrow);
9243 ins_cost(CALL_COST);
9244
9245 // use the following format syntax
9246 format %{ "Jmp rethrow_stub" %}
9247 ins_encode(enc_rethrow);
9248 ins_pipe(tail_call);
9249 %}
9250
9251
9252 // Die now
9253 instruct ShouldNotReachHere( )
9254 %{
9255 match(Halt);
9256 ins_cost(CALL_COST);
9257
9258 size(4);
9259 // Use the following format syntax
9260 format %{ "ILLTRAP ; ShouldNotReachHere" %}
9261 ins_encode( form2_illtrap() );
9262 ins_pipe(tail_call);
9263 %}
9264
9265 // ============================================================================
9266 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
9267 // array for an instance of the superklass. Set a hidden internal cache on a
9268 // hit (cache is checked with exposed code in gen_subtype_check()). Return
9269 // not zero for a miss or zero for a hit. The encoding ALSO sets flags.
9270 instruct partialSubtypeCheck( o0RegP index, o1RegP sub, o2RegP super, flagsRegP pcc, o7RegP o7 ) %{
9271 match(Set index (PartialSubtypeCheck sub super));
9272 effect( KILL pcc, KILL o7 );
9273 ins_cost(DEFAULT_COST*10);
9274 format %{ "CALL PartialSubtypeCheck\n\tNOP" %}
9275 ins_encode( enc_PartialSubtypeCheck() );
9276 ins_pipe(partial_subtype_check_pipe);
9277 %}
9278
9279 instruct partialSubtypeCheck_vs_zero( flagsRegP pcc, o1RegP sub, o2RegP super, immP0 zero, o0RegP idx, o7RegP o7 ) %{
9280 match(Set pcc (CmpP (PartialSubtypeCheck sub super) zero));
9281 effect( KILL idx, KILL o7 );
9282 ins_cost(DEFAULT_COST*10);
9283 format %{ "CALL PartialSubtypeCheck\n\tNOP\t# (sets condition codes)" %}
9284 ins_encode( enc_PartialSubtypeCheck() );
9285 ins_pipe(partial_subtype_check_pipe);
9286 %}
9287
9288
9289 // ============================================================================
9290 // inlined locking and unlocking
9291
9292 instruct cmpFastLock(flagsRegP pcc, iRegP object, iRegP box, iRegP scratch2, o7RegP scratch ) %{
9293 match(Set pcc (FastLock object box));
9294
9295 effect(KILL scratch, TEMP scratch2);
9296 ins_cost(100);
9297
9298 size(4*112); // conservative overestimation ...
9299 format %{ "FASTLOCK $object, $box; KILL $scratch, $scratch2, $box" %}
9300 ins_encode( Fast_Lock(object, box, scratch, scratch2) );
9301 ins_pipe(long_memory_op);
9302 %}
9303
9304
9305 instruct cmpFastUnlock(flagsRegP pcc, iRegP object, iRegP box, iRegP scratch2, o7RegP scratch ) %{
9306 match(Set pcc (FastUnlock object box));
9307 effect(KILL scratch, TEMP scratch2);
9308 ins_cost(100);
9309
9310 size(4*120); // conservative overestimation ...
9311 format %{ "FASTUNLOCK $object, $box; KILL $scratch, $scratch2, $box" %}
9312 ins_encode( Fast_Unlock(object, box, scratch, scratch2) );
9313 ins_pipe(long_memory_op);
9314 %}
9315
9316 // Count and Base registers are fixed because the allocator cannot
9317 // kill unknown registers. The encodings are generic.
9318 instruct clear_array(iRegX cnt, iRegP base, iRegX temp, Universe dummy, flagsReg ccr) %{
9319 match(Set dummy (ClearArray cnt base));
9320 effect(TEMP temp, KILL ccr);
9321 ins_cost(300);
9322 format %{ "MOV $cnt,$temp\n"
9323 "loop: SUBcc $temp,8,$temp\t! Count down a dword of bytes\n"
9324 " BRge loop\t\t! Clearing loop\n"
9325 " STX G0,[$base+$temp]\t! delay slot" %}
9326 ins_encode( enc_Clear_Array(cnt, base, temp) );
9327 ins_pipe(long_memory_op);
9328 %}
9329
9330 instruct string_compare(o0RegP str1, o1RegP str2, g3RegP tmp1, g4RegP tmp2, notemp_iRegI result,
9331 o7RegI tmp3, flagsReg ccr) %{
9332 match(Set result (StrComp str1 str2));
9333 effect(USE_KILL str1, USE_KILL str2, KILL tmp1, KILL tmp2, KILL ccr, KILL tmp3);
9334 ins_cost(300);
9335 format %{ "String Compare $str1,$str2 -> $result" %}
9336 ins_encode( enc_String_Compare(str1, str2, tmp1, tmp2, result) );
9337 ins_pipe(long_memory_op);
9338 %}
9339
9340 instruct string_equals(o0RegP str1, o1RegP str2, g3RegP tmp1, g4RegP tmp2, notemp_iRegI result,
9341 o7RegI tmp3, flagsReg ccr) %{
9342 match(Set result (StrEquals str1 str2));
9343 effect(USE_KILL str1, USE_KILL str2, KILL tmp1, KILL tmp2, KILL ccr, KILL tmp3);
9344 ins_cost(300);
9345 format %{ "String Equals $str1,$str2 -> $result" %}
9346 ins_encode( enc_String_Equals(str1, str2, tmp1, tmp2, result) );
9347 ins_pipe(long_memory_op);
9348 %}
9349
9350 instruct array_equals(o0RegP ary1, o1RegP ary2, g3RegP tmp1, g4RegP tmp2, notemp_iRegI result,
9351 flagsReg ccr) %{
9352 match(Set result (AryEq ary1 ary2));
9353 effect(USE_KILL ary1, USE_KILL ary2, KILL tmp1, KILL tmp2, KILL ccr);
9354 ins_cost(300);
9355 format %{ "Array Equals $ary1,$ary2 -> $result" %}
9356 ins_encode( enc_Array_Equals(ary1, ary2, tmp1, tmp2, result));
9357 ins_pipe(long_memory_op);
9358 %}
9359
9360
9361 //---------- Zeros Count Instructions ------------------------------------------
9362
9363 instruct countLeadingZerosI(iRegI dst, iRegI src, iRegI tmp, flagsReg cr) %{
9364 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
9365 match(Set dst (CountLeadingZerosI src));
9366 effect(TEMP dst, TEMP tmp, KILL cr);
9367
9368 // x |= (x >> 1);
9369 // x |= (x >> 2);
9370 // x |= (x >> 4);
9371 // x |= (x >> 8);
9372 // x |= (x >> 16);
9373 // return (WORDBITS - popc(x));
9374 format %{ "SRL $src,1,$dst\t! count leading zeros (int)\n\t"
9375 "OR $src,$tmp,$dst\n\t"
9376 "SRL $dst,2,$tmp\n\t"
9377 "OR $dst,$tmp,$dst\n\t"
9378 "SRL $dst,4,$tmp\n\t"
9379 "OR $dst,$tmp,$dst\n\t"
9380 "SRL $dst,8,$tmp\n\t"
9381 "OR $dst,$tmp,$dst\n\t"
9382 "SRL $dst,16,$tmp\n\t"
9383 "OR $dst,$tmp,$dst\n\t"
9384 "POPC $dst,$dst\n\t"
9385 "MOV 32,$tmp\n\t"
9386 "SUB $tmp,$dst,$dst" %}
9387 ins_encode %{
9388 Register Rdst = $dst$$Register;
9389 Register Rsrc = $src$$Register;
9390 Register Rtmp = $tmp$$Register;
9391 __ srl(Rsrc, 1, Rtmp);
9392 __ or3(Rsrc, Rtmp, Rdst);
9393 __ srl(Rdst, 2, Rtmp);
9394 __ or3(Rdst, Rtmp, Rdst);
9395 __ srl(Rdst, 4, Rtmp);
9396 __ or3(Rdst, Rtmp, Rdst);
9397 __ srl(Rdst, 8, Rtmp);
9398 __ or3(Rdst, Rtmp, Rdst);
9399 __ srl(Rdst, 16, Rtmp);
9400 __ or3(Rdst, Rtmp, Rdst);
9401 __ popc(Rdst, Rdst);
9402 __ mov(BitsPerInt, Rtmp);
9403 __ sub(Rtmp, Rdst, Rdst);
9404 %}
9405 ins_pipe(ialu_reg);
9406 %}
9407
9408 instruct countLeadingZerosL(iRegI dst, iRegL src, iRegL tmp, flagsReg cr) %{
9409 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
9410 match(Set dst (CountLeadingZerosL src));
9411 effect(TEMP dst, TEMP tmp, KILL cr);
9412
9413 // x |= (x >> 1);
9414 // x |= (x >> 2);
9415 // x |= (x >> 4);
9416 // x |= (x >> 8);
9417 // x |= (x >> 16);
9418 // x |= (x >> 32);
9419 // return (WORDBITS - popc(x));
9420 format %{ "SRLX $src,1,$dst\t! count leading zeros (long)\n\t"
9421 "OR $src,$tmp,$dst\n\t"
9422 "SRLX $dst,2,$tmp\n\t"
9423 "OR $dst,$tmp,$dst\n\t"
9424 "SRLX $dst,4,$tmp\n\t"
9425 "OR $dst,$tmp,$dst\n\t"
9426 "SRLX $dst,8,$tmp\n\t"
9427 "OR $dst,$tmp,$dst\n\t"
9428 "SRLX $dst,16,$tmp\n\t"
9429 "OR $dst,$tmp,$dst\n\t"
9430 "SRLX $dst,32,$tmp\n\t"
9431 "OR $dst,$tmp,$dst\n\t"
9432 "POPC $dst,$dst\n\t"
9433 "MOV 64,$tmp\n\t"
9434 "SUB $tmp,$dst,$dst" %}
9435 ins_encode %{
9436 Register Rdst = $dst$$Register;
9437 Register Rsrc = $src$$Register;
9438 Register Rtmp = $tmp$$Register;
9439 __ srlx(Rsrc, 1, Rtmp);
9440 __ or3(Rsrc, Rtmp, Rdst);
9441 __ srlx(Rdst, 2, Rtmp);
9442 __ or3(Rdst, Rtmp, Rdst);
9443 __ srlx(Rdst, 4, Rtmp);
9444 __ or3(Rdst, Rtmp, Rdst);
9445 __ srlx(Rdst, 8, Rtmp);
9446 __ or3(Rdst, Rtmp, Rdst);
9447 __ srlx(Rdst, 16, Rtmp);
9448 __ or3(Rdst, Rtmp, Rdst);
9449 __ srlx(Rdst, 32, Rtmp);
9450 __ or3(Rdst, Rtmp, Rdst);
9451 __ popc(Rdst, Rdst);
9452 __ mov(BitsPerLong, Rtmp);
9453 __ sub(Rtmp, Rdst, Rdst);
9454 %}
9455 ins_pipe(ialu_reg);
9456 %}
9457
9458 instruct countTrailingZerosI(iRegI dst, iRegI src, flagsReg cr) %{
9459 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
9460 match(Set dst (CountTrailingZerosI src));
9461 effect(TEMP dst, KILL cr);
9462
9463 // return popc(~x & (x - 1));
9464 format %{ "SUB $src,1,$dst\t! count trailing zeros (int)\n\t"
9465 "ANDN $dst,$src,$dst\n\t"
9466 "SRL $dst,R_G0,$dst\n\t"
9467 "POPC $dst,$dst" %}
9468 ins_encode %{
9469 Register Rdst = $dst$$Register;
9470 Register Rsrc = $src$$Register;
9471 __ sub(Rsrc, 1, Rdst);
9472 __ andn(Rdst, Rsrc, Rdst);
9473 __ srl(Rdst, G0, Rdst);
9474 __ popc(Rdst, Rdst);
9475 %}
9476 ins_pipe(ialu_reg);
9477 %}
9478
9479 instruct countTrailingZerosL(iRegI dst, iRegL src, flagsReg cr) %{
9480 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
9481 match(Set dst (CountTrailingZerosL src));
9482 effect(TEMP dst, KILL cr);
9483
9484 // return popc(~x & (x - 1));
9485 format %{ "SUB $src,1,$dst\t! count trailing zeros (long)\n\t"
9486 "ANDN $dst,$src,$dst\n\t"
9487 "POPC $dst,$dst" %}
9488 ins_encode %{
9489 Register Rdst = $dst$$Register;
9490 Register Rsrc = $src$$Register;
9491 __ sub(Rsrc, 1, Rdst);
9492 __ andn(Rdst, Rsrc, Rdst);
9493 __ popc(Rdst, Rdst);
9494 %}
9495 ins_pipe(ialu_reg);
9496 %}
9497
9498
9499 //---------- Population Count Instructions -------------------------------------
9500
9501 instruct popCountI(iRegI dst, iRegI src) %{
9502 predicate(UsePopCountInstruction);
9503 match(Set dst (PopCountI src));
9504
9505 format %{ "POPC $src, $dst" %}
9506 ins_encode %{
9507 __ popc($src$$Register, $dst$$Register);
9508 %}
9509 ins_pipe(ialu_reg);
9510 %}
9511
9512 // Note: Long.bitCount(long) returns an int.
9513 instruct popCountL(iRegI dst, iRegL src) %{
9514 predicate(UsePopCountInstruction);
9515 match(Set dst (PopCountL src));
9516
9517 format %{ "POPC $src, $dst" %}
9518 ins_encode %{
9519 __ popc($src$$Register, $dst$$Register);
9520 %}
9521 ins_pipe(ialu_reg);
9522 %}
9523
9524
9525 // ============================================================================
9526 //------------Bytes reverse--------------------------------------------------
9527
9528 instruct bytes_reverse_int(iRegI dst, stackSlotI src) %{
9529 match(Set dst (ReverseBytesI src));
9530 effect(DEF dst, USE src);
9531
9532 // Op cost is artificially doubled to make sure that load or store
9533 // instructions are preferred over this one which requires a spill
9534 // onto a stack slot.
9535 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
9536 size(8);
9537 format %{ "LDUWA $src, $dst\t!asi=primary_little" %}
9538 opcode(Assembler::lduwa_op3);
9539 ins_encode( form3_mem_reg_little(src, dst) );
9540 ins_pipe( iload_mem );
9541 %}
9542
9543 instruct bytes_reverse_long(iRegL dst, stackSlotL src) %{
9544 match(Set dst (ReverseBytesL src));
9545 effect(DEF dst, USE src);
9546
9547 // Op cost is artificially doubled to make sure that load or store
9548 // instructions are preferred over this one which requires a spill
9549 // onto a stack slot.
9550 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
9551 size(8);
9552 format %{ "LDXA $src, $dst\t!asi=primary_little" %}
9553
9554 opcode(Assembler::ldxa_op3);
9555 ins_encode( form3_mem_reg_little(src, dst) );
9556 ins_pipe( iload_mem );
9557 %}
9558
9559 // Load Integer reversed byte order
9560 instruct loadI_reversed(iRegI dst, memory src) %{
9561 match(Set dst (ReverseBytesI (LoadI src)));
9562
9563 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
9564 size(8);
9565 format %{ "LDUWA $src, $dst\t!asi=primary_little" %}
9566
9567 opcode(Assembler::lduwa_op3);
9568 ins_encode( form3_mem_reg_little( src, dst) );
9569 ins_pipe(iload_mem);
9570 %}
9571
9572 // Load Long - aligned and reversed
9573 instruct loadL_reversed(iRegL dst, memory src) %{
9574 match(Set dst (ReverseBytesL (LoadL src)));
9575
9576 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
9577 size(8);
9578 format %{ "LDXA $src, $dst\t!asi=primary_little" %}
9579
9580 opcode(Assembler::ldxa_op3);
9581 ins_encode( form3_mem_reg_little( src, dst ) );
9582 ins_pipe(iload_mem);
9583 %}
9584
9585 // Store Integer reversed byte order
9586 instruct storeI_reversed(memory dst, iRegI src) %{
9587 match(Set dst (StoreI dst (ReverseBytesI src)));
9588
9589 ins_cost(MEMORY_REF_COST);
9590 size(8);
9591 format %{ "STWA $src, $dst\t!asi=primary_little" %}
9592
9593 opcode(Assembler::stwa_op3);
9594 ins_encode( form3_mem_reg_little( dst, src) );
9595 ins_pipe(istore_mem_reg);
9596 %}
9597
9598 // Store Long reversed byte order
9599 instruct storeL_reversed(memory dst, iRegL src) %{
9600 match(Set dst (StoreL dst (ReverseBytesL src)));
9601
9602 ins_cost(MEMORY_REF_COST);
9603 size(8);
9604 format %{ "STXA $src, $dst\t!asi=primary_little" %}
9605
9606 opcode(Assembler::stxa_op3);
9607 ins_encode( form3_mem_reg_little( dst, src) );
9608 ins_pipe(istore_mem_reg);
9609 %}
9610
9611 //----------PEEPHOLE RULES-----------------------------------------------------
9612 // These must follow all instruction definitions as they use the names
9613 // defined in the instructions definitions.
9614 //
9615 // peepmatch ( root_instr_name [preceding_instruction]* );
9616 //
9617 // peepconstraint %{
9618 // (instruction_number.operand_name relational_op instruction_number.operand_name
9619 // [, ...] );
9620 // // instruction numbers are zero-based using left to right order in peepmatch
9621 //
9622 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
9623 // // provide an instruction_number.operand_name for each operand that appears
9624 // // in the replacement instruction's match rule
9625 //
9626 // ---------VM FLAGS---------------------------------------------------------
9627 //
9628 // All peephole optimizations can be turned off using -XX:-OptoPeephole
9629 //
9630 // Each peephole rule is given an identifying number starting with zero and
9631 // increasing by one in the order seen by the parser. An individual peephole
9632 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
9633 // on the command-line.
9634 //
9635 // ---------CURRENT LIMITATIONS----------------------------------------------
9636 //
9637 // Only match adjacent instructions in same basic block
9638 // Only equality constraints
9639 // Only constraints between operands, not (0.dest_reg == EAX_enc)
9640 // Only one replacement instruction
9641 //
9642 // ---------EXAMPLE----------------------------------------------------------
9643 //
9644 // // pertinent parts of existing instructions in architecture description
9645 // instruct movI(eRegI dst, eRegI src) %{
9646 // match(Set dst (CopyI src));
9647 // %}
9648 //
9649 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
9650 // match(Set dst (AddI dst src));
9651 // effect(KILL cr);
9652 // %}
9653 //
9654 // // Change (inc mov) to lea
9655 // peephole %{
9656 // // increment preceeded by register-register move
9657 // peepmatch ( incI_eReg movI );
9658 // // require that the destination register of the increment
9659 // // match the destination register of the move
9660 // peepconstraint ( 0.dst == 1.dst );
9661 // // construct a replacement instruction that sets
9662 // // the destination to ( move's source register + one )
9663 // peepreplace ( incI_eReg_immI1( 0.dst 1.src 0.src ) );
9664 // %}
9665 //
9666
9667 // // Change load of spilled value to only a spill
9668 // instruct storeI(memory mem, eRegI src) %{
9669 // match(Set mem (StoreI mem src));
9670 // %}
9671 //
9672 // instruct loadI(eRegI dst, memory mem) %{
9673 // match(Set dst (LoadI mem));
9674 // %}
9675 //
9676 // peephole %{
9677 // peepmatch ( loadI storeI );
9678 // peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
9679 // peepreplace ( storeI( 1.mem 1.mem 1.src ) );
9680 // %}
9681
9682 //----------SMARTSPILL RULES---------------------------------------------------
9683 // These must follow all instruction definitions as they use the names
9684 // defined in the instructions definitions.
9685 //
9686 // SPARC will probably not have any of these rules due to RISC instruction set.
9687
9688 //----------PIPELINE-----------------------------------------------------------
9689 // Rules which define the behavior of the target architectures pipeline.