1876 // Register for DIVL projection of divmodL
1877 RegMask Matcher::divL_proj_mask() {
1878 ShouldNotReachHere();
1879 return RegMask();
1880 }
1881
1882 // Register for MODL projection of divmodL
1883 RegMask Matcher::modL_proj_mask() {
1884 ShouldNotReachHere();
1885 return RegMask();
1886 }
1887
1888 %}
1889
1890
1891 // The intptr_t operand types, defined by textual substitution.
1892 // (Cf. opto/type.hpp. This lets us avoid many, many other ifdefs.)
1893 #ifdef _LP64
1894 #define immX immL
1895 #define immX13 immL13
1896 #define iRegX iRegL
1897 #define g1RegX g1RegL
1898 #else
1899 #define immX immI
1900 #define immX13 immI13
1901 #define iRegX iRegI
1902 #define g1RegX g1RegI
1903 #endif
1904
1905 //----------ENCODING BLOCK-----------------------------------------------------
1906 // This block specifies the encoding classes used by the compiler to output
1907 // byte streams. Encoding classes are parameterized macros used by
1908 // Machine Instruction Nodes in order to generate the bit encoding of the
1909 // instruction. Operands specify their base encoding interface with the
1910 // interface keyword. There are currently supported four interfaces,
1911 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
1912 // operand to generate a function which returns its register number when
1913 // queried. CONST_INTER causes an operand to generate a function which
1914 // returns the value of the constant when queried. MEMORY_INTER causes an
1915 // operand to generate four functions which return the Base Register, the
1916 // Index Register, the Scale Value, and the Offset Value of the operand when
1917 // queried. COND_INTER causes an operand to generate six functions which
1918 // return the encoding code (ie - encoding bits for the instruction)
1919 // associated with each basic boolean condition for a conditional instruction.
1920 //
3437 // Integer Immediate: 32-bit
3438 operand immI() %{
3439 match(ConI);
3440
3441 op_cost(0);
3442 // formats are generated automatically for constants and base registers
3443 format %{ %}
3444 interface(CONST_INTER);
3445 %}
3446
3447 // Integer Immediate: 13-bit
3448 operand immI13() %{
3449 predicate(Assembler::is_simm13(n->get_int()));
3450 match(ConI);
3451 op_cost(0);
3452
3453 format %{ %}
3454 interface(CONST_INTER);
3455 %}
3456
3457 // Unsigned (positive) Integer Immediate: 13-bit
3458 operand immU13() %{
3459 predicate((0 <= n->get_int()) && Assembler::is_simm13(n->get_int()));
3460 match(ConI);
3461 op_cost(0);
3462
3463 format %{ %}
3464 interface(CONST_INTER);
3465 %}
3466
3467 // Integer Immediate: 6-bit
3468 operand immU6() %{
3469 predicate(n->get_int() >= 0 && n->get_int() <= 63);
3470 match(ConI);
3471 op_cost(0);
3472 format %{ %}
3473 interface(CONST_INTER);
3474 %}
3475
3476 // Integer Immediate: 11-bit
3515 // Integer Immediate: the values 1-31
3516 operand immI_1_31() %{
3517 predicate(n->get_int() >= 1 && n->get_int() <= 31);
3518 match(ConI);
3519 op_cost(0);
3520
3521 format %{ %}
3522 interface(CONST_INTER);
3523 %}
3524
3525 // Integer Immediate: the values 32-63
3526 operand immI_32_63() %{
3527 predicate(n->get_int() >= 32 && n->get_int() <= 63);
3528 match(ConI);
3529 op_cost(0);
3530
3531 format %{ %}
3532 interface(CONST_INTER);
3533 %}
3534
3535 // Integer Immediate: the value 255
3536 operand immI_255() %{
3537 predicate( n->get_int() == 255 );
3538 match(ConI);
3539 op_cost(0);
3540
3541 format %{ %}
3542 interface(CONST_INTER);
3543 %}
3544
3545 // Long Immediate: the value FF
3546 operand immL_FF() %{
3547 predicate( n->get_long() == 0xFFL );
3548 match(ConL);
3549 op_cost(0);
3550
3551 format %{ %}
3552 interface(CONST_INTER);
3553 %}
3554
3555 // Long Immediate: the value FFFF
3556 operand immL_FFFF() %{
3557 predicate( n->get_long() == 0xFFFFL );
3558 match(ConL);
3559 op_cost(0);
3560
3561 format %{ %}
3562 interface(CONST_INTER);
3563 %}
3564
3630
3631 operand immL0() %{
3632 predicate(n->get_long() == 0L);
3633 match(ConL);
3634 op_cost(0);
3635 // formats are generated automatically for constants and base registers
3636 format %{ %}
3637 interface(CONST_INTER);
3638 %}
3639
3640 // Long Immediate: 13-bit
3641 operand immL13() %{
3642 predicate((-4096L < n->get_long()) && (n->get_long() <= 4095L));
3643 match(ConL);
3644 op_cost(0);
3645
3646 format %{ %}
3647 interface(CONST_INTER);
3648 %}
3649
3650 // Long Immediate: low 32-bit mask
3651 operand immL_32bits() %{
3652 predicate(n->get_long() == 0xFFFFFFFFL);
3653 match(ConL);
3654 op_cost(0);
3655
3656 format %{ %}
3657 interface(CONST_INTER);
3658 %}
3659
3660 // Double Immediate
3661 operand immD() %{
3662 match(ConD);
3663
3664 op_cost(40);
3665 format %{ %}
3666 interface(CONST_INTER);
3667 %}
3668
3669 operand immD0() %{
4067 interface(REG_INTER);
4068 %}
4069
4070
4071 //----------Complex Operands---------------------------------------------------
4072 // Indirect Memory Reference
4073 operand indirect(sp_ptr_RegP reg) %{
4074 constraint(ALLOC_IN_RC(sp_ptr_reg));
4075 match(reg);
4076
4077 op_cost(100);
4078 format %{ "[$reg]" %}
4079 interface(MEMORY_INTER) %{
4080 base($reg);
4081 index(0x0);
4082 scale(0x0);
4083 disp(0x0);
4084 %}
4085 %}
4086
4087 // Indirect with Offset
4088 operand indOffset13(sp_ptr_RegP reg, immX13 offset) %{
4089 constraint(ALLOC_IN_RC(sp_ptr_reg));
4090 match(AddP reg offset);
4091
4092 op_cost(100);
4093 format %{ "[$reg + $offset]" %}
4094 interface(MEMORY_INTER) %{
4095 base($reg);
4096 index(0x0);
4097 scale(0x0);
4098 disp($offset);
4099 %}
4100 %}
4101
4102 // Note: Intel has a swapped version also, like this:
4103 //operand indOffsetX(iRegI reg, immP offset) %{
4104 // constraint(ALLOC_IN_RC(int_reg));
4105 // match(AddP offset reg);
4106 //
4107 // op_cost(100);
4108 // format %{ "[$reg + $offset]" %}
4109 // interface(MEMORY_INTER) %{
4110 // base($reg);
4111 // index(0x0);
4112 // scale(0x0);
4113 // disp($offset);
4114 // %}
4115 //%}
4116 //// However, it doesn't make sense for SPARC, since
4117 // we have no particularly good way to embed oops in
4118 // single instructions.
4119
4120 // Indirect with Register Index
4121 operand indIndex(iRegP addr, iRegX index) %{
5487 format %{ "LDUB $mem,$dst\t! ubyte -> long" %}
5488 ins_encode %{
5489 __ ldub($mem$$Address, $dst$$Register);
5490 %}
5491 ins_pipe(iload_mask_mem);
5492 %}
5493
5494 // Load Short (16bit signed)
5495 instruct loadS(iRegI dst, memory mem) %{
5496 match(Set dst (LoadS mem));
5497 ins_cost(MEMORY_REF_COST);
5498
5499 size(4);
5500 format %{ "LDSH $mem,$dst\t! short" %}
5501 ins_encode %{
5502 __ ldsh($mem$$Address, $dst$$Register);
5503 %}
5504 ins_pipe(iload_mask_mem);
5505 %}
5506
5507 // Load Short (16bit signed) into a Long Register
5508 instruct loadS2L(iRegL dst, memory mem) %{
5509 match(Set dst (ConvI2L (LoadS mem)));
5510 ins_cost(MEMORY_REF_COST);
5511
5512 size(4);
5513 format %{ "LDSH $mem,$dst\t! short -> long" %}
5514 ins_encode %{
5515 __ ldsh($mem$$Address, $dst$$Register);
5516 %}
5517 ins_pipe(iload_mask_mem);
5518 %}
5519
5520 // Load Unsigned Short/Char (16bit UNsigned)
5521 instruct loadUS(iRegI dst, memory mem) %{
5522 match(Set dst (LoadUS mem));
5523 ins_cost(MEMORY_REF_COST);
5524
5525 size(4);
5526 format %{ "LDUH $mem,$dst\t! ushort/char" %}
5527 ins_encode %{
5528 __ lduh($mem$$Address, $dst$$Register);
5529 %}
5530 ins_pipe(iload_mask_mem);
5531 %}
5532
5533 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register
5534 instruct loadUS2L(iRegL dst, memory mem) %{
5535 match(Set dst (ConvI2L (LoadUS mem)));
5536 ins_cost(MEMORY_REF_COST);
5537
5538 size(4);
5539 format %{ "LDUH $mem,$dst\t! ushort/char -> long" %}
5540 ins_encode %{
5541 __ lduh($mem$$Address, $dst$$Register);
5542 %}
5543 ins_pipe(iload_mask_mem);
5544 %}
5545
5546 // Load Integer
5547 instruct loadI(iRegI dst, memory mem) %{
5548 match(Set dst (LoadI mem));
5549 ins_cost(MEMORY_REF_COST);
5550
5551 size(4);
5552 format %{ "LDUW $mem,$dst\t! int" %}
5553 ins_encode %{
5554 __ lduw($mem$$Address, $dst$$Register);
5555 %}
5556 ins_pipe(iload_mem);
5557 %}
5558
5559 // Load Integer into a Long Register
5560 instruct loadI2L(iRegL dst, memory mem) %{
5561 match(Set dst (ConvI2L (LoadI mem)));
5562 ins_cost(MEMORY_REF_COST);
5563
5564 size(4);
5565 format %{ "LDSW $mem,$dst\t! int -> long" %}
5566 ins_encode %{
5567 __ ldsw($mem$$Address, $dst$$Register);
5568 %}
5569 ins_pipe(iload_mem);
5570 %}
5571
5572 // Load Unsigned Integer into a Long Register
5573 instruct loadUI2L(iRegL dst, memory mem) %{
5574 match(Set dst (LoadUI2L mem));
5575 ins_cost(MEMORY_REF_COST);
5576
5577 size(4);
5578 format %{ "LDUW $mem,$dst\t! uint -> long" %}
|
1876 // Register for DIVL projection of divmodL
1877 RegMask Matcher::divL_proj_mask() {
1878 ShouldNotReachHere();
1879 return RegMask();
1880 }
1881
1882 // Register for MODL projection of divmodL
1883 RegMask Matcher::modL_proj_mask() {
1884 ShouldNotReachHere();
1885 return RegMask();
1886 }
1887
1888 %}
1889
1890
1891 // The intptr_t operand types, defined by textual substitution.
1892 // (Cf. opto/type.hpp. This lets us avoid many, many other ifdefs.)
1893 #ifdef _LP64
1894 #define immX immL
1895 #define immX13 immL13
1896 #define immX13m7 immL13m7
1897 #define iRegX iRegL
1898 #define g1RegX g1RegL
1899 #else
1900 #define immX immI
1901 #define immX13 immI13
1902 #define immX13m7 immI13m7
1903 #define iRegX iRegI
1904 #define g1RegX g1RegI
1905 #endif
1906
1907 //----------ENCODING BLOCK-----------------------------------------------------
1908 // This block specifies the encoding classes used by the compiler to output
1909 // byte streams. Encoding classes are parameterized macros used by
1910 // Machine Instruction Nodes in order to generate the bit encoding of the
1911 // instruction. Operands specify their base encoding interface with the
1912 // interface keyword. There are currently supported four interfaces,
1913 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
1914 // operand to generate a function which returns its register number when
1915 // queried. CONST_INTER causes an operand to generate a function which
1916 // returns the value of the constant when queried. MEMORY_INTER causes an
1917 // operand to generate four functions which return the Base Register, the
1918 // Index Register, the Scale Value, and the Offset Value of the operand when
1919 // queried. COND_INTER causes an operand to generate six functions which
1920 // return the encoding code (ie - encoding bits for the instruction)
1921 // associated with each basic boolean condition for a conditional instruction.
1922 //
3439 // Integer Immediate: 32-bit
3440 operand immI() %{
3441 match(ConI);
3442
3443 op_cost(0);
3444 // formats are generated automatically for constants and base registers
3445 format %{ %}
3446 interface(CONST_INTER);
3447 %}
3448
3449 // Integer Immediate: 13-bit
3450 operand immI13() %{
3451 predicate(Assembler::is_simm13(n->get_int()));
3452 match(ConI);
3453 op_cost(0);
3454
3455 format %{ %}
3456 interface(CONST_INTER);
3457 %}
3458
3459 // Integer Immediate: 13-bit minus 7
3460 operand immI13m7() %{
3461 predicate(Assembler::is_simm13(n->get_int() + 7));
3462 match(ConI);
3463 op_cost(0);
3464
3465 format %{ %}
3466 interface(CONST_INTER);
3467 %}
3468
3469 // Unsigned (positive) Integer Immediate: 13-bit
3470 operand immU13() %{
3471 predicate((0 <= n->get_int()) && Assembler::is_simm13(n->get_int()));
3472 match(ConI);
3473 op_cost(0);
3474
3475 format %{ %}
3476 interface(CONST_INTER);
3477 %}
3478
3479 // Integer Immediate: 6-bit
3480 operand immU6() %{
3481 predicate(n->get_int() >= 0 && n->get_int() <= 63);
3482 match(ConI);
3483 op_cost(0);
3484 format %{ %}
3485 interface(CONST_INTER);
3486 %}
3487
3488 // Integer Immediate: 11-bit
3527 // Integer Immediate: the values 1-31
3528 operand immI_1_31() %{
3529 predicate(n->get_int() >= 1 && n->get_int() <= 31);
3530 match(ConI);
3531 op_cost(0);
3532
3533 format %{ %}
3534 interface(CONST_INTER);
3535 %}
3536
3537 // Integer Immediate: the values 32-63
3538 operand immI_32_63() %{
3539 predicate(n->get_int() >= 32 && n->get_int() <= 63);
3540 match(ConI);
3541 op_cost(0);
3542
3543 format %{ %}
3544 interface(CONST_INTER);
3545 %}
3546
3547 // Immediates for special shifts (sign extend)
3548
3549 // Integer Immediate: the value 16
3550 operand immI_16() %{
3551 predicate(n->get_int() == 16);
3552 match(ConI);
3553 op_cost(0);
3554
3555 format %{ %}
3556 interface(CONST_INTER);
3557 %}
3558
3559 // Integer Immediate: the value 24
3560 operand immI_24() %{
3561 predicate(n->get_int() == 24);
3562 match(ConI);
3563 op_cost(0);
3564
3565 format %{ %}
3566 interface(CONST_INTER);
3567 %}
3568
3569 // Integer Immediate: the value 255
3570 operand immI_255() %{
3571 predicate( n->get_int() == 255 );
3572 match(ConI);
3573 op_cost(0);
3574
3575 format %{ %}
3576 interface(CONST_INTER);
3577 %}
3578
3579 // Integer Immediate: the value 65535
3580 operand immI_65535() %{
3581 predicate(n->get_int() == 65535);
3582 match(ConI);
3583 op_cost(0);
3584
3585 format %{ %}
3586 interface(CONST_INTER);
3587 %}
3588
3589 // Long Immediate: the value FF
3590 operand immL_FF() %{
3591 predicate( n->get_long() == 0xFFL );
3592 match(ConL);
3593 op_cost(0);
3594
3595 format %{ %}
3596 interface(CONST_INTER);
3597 %}
3598
3599 // Long Immediate: the value FFFF
3600 operand immL_FFFF() %{
3601 predicate( n->get_long() == 0xFFFFL );
3602 match(ConL);
3603 op_cost(0);
3604
3605 format %{ %}
3606 interface(CONST_INTER);
3607 %}
3608
3674
3675 operand immL0() %{
3676 predicate(n->get_long() == 0L);
3677 match(ConL);
3678 op_cost(0);
3679 // formats are generated automatically for constants and base registers
3680 format %{ %}
3681 interface(CONST_INTER);
3682 %}
3683
3684 // Long Immediate: 13-bit
3685 operand immL13() %{
3686 predicate((-4096L < n->get_long()) && (n->get_long() <= 4095L));
3687 match(ConL);
3688 op_cost(0);
3689
3690 format %{ %}
3691 interface(CONST_INTER);
3692 %}
3693
3694 // Long Immediate: 13-bit minus 7
3695 operand immL13m7() %{
3696 predicate((-4096L < (n->get_long() + 7L)) && ((n->get_long() + 7L) <= 4095L));
3697 match(ConL);
3698 op_cost(0);
3699
3700 format %{ %}
3701 interface(CONST_INTER);
3702 %}
3703
3704 // Long Immediate: low 32-bit mask
3705 operand immL_32bits() %{
3706 predicate(n->get_long() == 0xFFFFFFFFL);
3707 match(ConL);
3708 op_cost(0);
3709
3710 format %{ %}
3711 interface(CONST_INTER);
3712 %}
3713
3714 // Double Immediate
3715 operand immD() %{
3716 match(ConD);
3717
3718 op_cost(40);
3719 format %{ %}
3720 interface(CONST_INTER);
3721 %}
3722
3723 operand immD0() %{
4121 interface(REG_INTER);
4122 %}
4123
4124
4125 //----------Complex Operands---------------------------------------------------
4126 // Indirect Memory Reference
4127 operand indirect(sp_ptr_RegP reg) %{
4128 constraint(ALLOC_IN_RC(sp_ptr_reg));
4129 match(reg);
4130
4131 op_cost(100);
4132 format %{ "[$reg]" %}
4133 interface(MEMORY_INTER) %{
4134 base($reg);
4135 index(0x0);
4136 scale(0x0);
4137 disp(0x0);
4138 %}
4139 %}
4140
4141 // Indirect with simm13 Offset
4142 operand indOffset13(sp_ptr_RegP reg, immX13 offset) %{
4143 constraint(ALLOC_IN_RC(sp_ptr_reg));
4144 match(AddP reg offset);
4145
4146 op_cost(100);
4147 format %{ "[$reg + $offset]" %}
4148 interface(MEMORY_INTER) %{
4149 base($reg);
4150 index(0x0);
4151 scale(0x0);
4152 disp($offset);
4153 %}
4154 %}
4155
4156 // Indirect with simm13 Offset minus 7
4157 operand indOffset13m7(sp_ptr_RegP reg, immX13m7 offset) %{
4158 constraint(ALLOC_IN_RC(sp_ptr_reg));
4159 match(AddP reg offset);
4160
4161 op_cost(100);
4162 format %{ "[$reg + $offset]" %}
4163 interface(MEMORY_INTER) %{
4164 base($reg);
4165 index(0x0);
4166 scale(0x0);
4167 disp($offset);
4168 %}
4169 %}
4170
4171 // Note: Intel has a swapped version also, like this:
4172 //operand indOffsetX(iRegI reg, immP offset) %{
4173 // constraint(ALLOC_IN_RC(int_reg));
4174 // match(AddP offset reg);
4175 //
4176 // op_cost(100);
4177 // format %{ "[$reg + $offset]" %}
4178 // interface(MEMORY_INTER) %{
4179 // base($reg);
4180 // index(0x0);
4181 // scale(0x0);
4182 // disp($offset);
4183 // %}
4184 //%}
4185 //// However, it doesn't make sense for SPARC, since
4186 // we have no particularly good way to embed oops in
4187 // single instructions.
4188
4189 // Indirect with Register Index
4190 operand indIndex(iRegP addr, iRegX index) %{
5556 format %{ "LDUB $mem,$dst\t! ubyte -> long" %}
5557 ins_encode %{
5558 __ ldub($mem$$Address, $dst$$Register);
5559 %}
5560 ins_pipe(iload_mask_mem);
5561 %}
5562
5563 // Load Short (16bit signed)
5564 instruct loadS(iRegI dst, memory mem) %{
5565 match(Set dst (LoadS mem));
5566 ins_cost(MEMORY_REF_COST);
5567
5568 size(4);
5569 format %{ "LDSH $mem,$dst\t! short" %}
5570 ins_encode %{
5571 __ ldsh($mem$$Address, $dst$$Register);
5572 %}
5573 ins_pipe(iload_mask_mem);
5574 %}
5575
5576 // Load Short (16 bit signed) to Byte (8 bit signed)
5577 instruct loadS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
5578 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
5579 ins_cost(MEMORY_REF_COST);
5580
5581 size(4);
5582
5583 format %{ "LDSB $mem+1,$dst\t! short -> byte" %}
5584 ins_encode %{
5585 __ ldsb($mem$$Address, $dst$$Register, 1);
5586 %}
5587 ins_pipe(iload_mask_mem);
5588 %}
5589
5590 // Load Short (16bit signed) into a Long Register
5591 instruct loadS2L(iRegL dst, memory mem) %{
5592 match(Set dst (ConvI2L (LoadS mem)));
5593 ins_cost(MEMORY_REF_COST);
5594
5595 size(4);
5596 format %{ "LDSH $mem,$dst\t! short -> long" %}
5597 ins_encode %{
5598 __ ldsh($mem$$Address, $dst$$Register);
5599 %}
5600 ins_pipe(iload_mask_mem);
5601 %}
5602
5603 // Load Unsigned Short/Char (16bit UNsigned)
5604 instruct loadUS(iRegI dst, memory mem) %{
5605 match(Set dst (LoadUS mem));
5606 ins_cost(MEMORY_REF_COST);
5607
5608 size(4);
5609 format %{ "LDUH $mem,$dst\t! ushort/char" %}
5610 ins_encode %{
5611 __ lduh($mem$$Address, $dst$$Register);
5612 %}
5613 ins_pipe(iload_mask_mem);
5614 %}
5615
5616 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
5617 instruct loadUS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
5618 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
5619 ins_cost(MEMORY_REF_COST);
5620
5621 size(4);
5622 format %{ "LDSB $mem+1,$dst\t! ushort -> byte" %}
5623 ins_encode %{
5624 __ ldsb($mem$$Address, $dst$$Register, 1);
5625 %}
5626 ins_pipe(iload_mask_mem);
5627 %}
5628
5629 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register
5630 instruct loadUS2L(iRegL dst, memory mem) %{
5631 match(Set dst (ConvI2L (LoadUS mem)));
5632 ins_cost(MEMORY_REF_COST);
5633
5634 size(4);
5635 format %{ "LDUH $mem,$dst\t! ushort/char -> long" %}
5636 ins_encode %{
5637 __ lduh($mem$$Address, $dst$$Register);
5638 %}
5639 ins_pipe(iload_mask_mem);
5640 %}
5641
5642 // Load Integer
5643 instruct loadI(iRegI dst, memory mem) %{
5644 match(Set dst (LoadI mem));
5645 ins_cost(MEMORY_REF_COST);
5646
5647 size(4);
5648 format %{ "LDUW $mem,$dst\t! int" %}
5649 ins_encode %{
5650 __ lduw($mem$$Address, $dst$$Register);
5651 %}
5652 ins_pipe(iload_mem);
5653 %}
5654
5655 // Load Integer to Byte (8 bit signed)
5656 instruct loadI2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
5657 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
5658 ins_cost(MEMORY_REF_COST);
5659
5660 size(4);
5661
5662 format %{ "LDSB $mem+3,$dst\t! int -> byte" %}
5663 ins_encode %{
5664 __ ldsb($mem$$Address, $dst$$Register, 3);
5665 %}
5666 ins_pipe(iload_mask_mem);
5667 %}
5668
5669 // Load Integer to Unsigned Byte (8 bit UNsigned)
5670 instruct loadI2UB(iRegI dst, indOffset13m7 mem, immI_255 mask) %{
5671 match(Set dst (AndI (LoadI mem) mask));
5672 ins_cost(MEMORY_REF_COST);
5673
5674 size(4);
5675
5676 format %{ "LDUB $mem+3,$dst\t! int -> ubyte" %}
5677 ins_encode %{
5678 __ ldub($mem$$Address, $dst$$Register, 3);
5679 %}
5680 ins_pipe(iload_mask_mem);
5681 %}
5682
5683 // Load Integer to Short (16 bit signed)
5684 instruct loadI2S(iRegI dst, indOffset13m7 mem, immI_16 sixteen) %{
5685 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
5686 ins_cost(MEMORY_REF_COST);
5687
5688 size(4);
5689
5690 format %{ "LDSH $mem+2,$dst\t! int -> short" %}
5691 ins_encode %{
5692 __ ldsh($mem$$Address, $dst$$Register, 2);
5693 %}
5694 ins_pipe(iload_mask_mem);
5695 %}
5696
5697 // Load Integer to Unsigned Short (16 bit UNsigned)
5698 instruct loadI2US(iRegI dst, indOffset13m7 mem, immI_65535 mask) %{
5699 match(Set dst (AndI (LoadI mem) mask));
5700 ins_cost(MEMORY_REF_COST);
5701
5702 size(4);
5703
5704 format %{ "LDUH $mem+2,$dst\t! int -> ushort/char" %}
5705 ins_encode %{
5706 __ lduh($mem$$Address, $dst$$Register, 2);
5707 %}
5708 ins_pipe(iload_mask_mem);
5709 %}
5710
5711 // Load Integer into a Long Register
5712 instruct loadI2L(iRegL dst, memory mem) %{
5713 match(Set dst (ConvI2L (LoadI mem)));
5714 ins_cost(MEMORY_REF_COST);
5715
5716 size(4);
5717 format %{ "LDSW $mem,$dst\t! int -> long" %}
5718 ins_encode %{
5719 __ ldsw($mem$$Address, $dst$$Register);
5720 %}
5721 ins_pipe(iload_mem);
5722 %}
5723
5724 // Load Unsigned Integer into a Long Register
5725 instruct loadUI2L(iRegL dst, memory mem) %{
5726 match(Set dst (LoadUI2L mem));
5727 ins_cost(MEMORY_REF_COST);
5728
5729 size(4);
5730 format %{ "LDUW $mem,$dst\t! uint -> long" %}
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