1 //
2 // Copyright 1997-2009 Sun Microsystems, Inc. All Rights Reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
9 // This code is distributed in the hope that it will be useful, but WITHOUT
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
15 // You should have received a copy of the GNU General Public License version
16 // 2 along with this work; if not, write to the Free Software Foundation,
17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 //
19 // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
20 // CA 95054 USA or visit www.sun.com if you need additional information or
21 // have any questions.
22 //
23 //
24
25 // X86 Architecture Description File
26
27 //----------REGISTER DEFINITION BLOCK------------------------------------------
28 // This information is used by the matcher and the register allocator to
29 // describe individual registers and classes of registers within the target
30 // archtecture.
31
32 register %{
33 //----------Architecture Description Register Definitions----------------------
34 // General Registers
35 // "reg_def" name ( register save type, C convention save type,
36 // ideal register type, encoding );
37 // Register Save Types:
38 //
39 // NS = No-Save: The register allocator assumes that these registers
40 // can be used without saving upon entry to the method, &
41 // that they do not need to be saved at call sites.
42 //
43 // SOC = Save-On-Call: The register allocator assumes that these registers
44 // can be used without saving upon entry to the method,
45 // but that they must be saved at call sites.
46 //
47 // SOE = Save-On-Entry: The register allocator assumes that these registers
48 // must be saved before using them upon entry to the
49 // method, but they do not need to be saved at call
50 // sites.
51 //
52 // AS = Always-Save: The register allocator assumes that these registers
53 // must be saved before using them upon entry to the
54 // method, & that they must be saved at call sites.
55 //
56 // Ideal Register Type is used to determine how to save & restore a
57 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
58 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
59 //
60 // The encoding number is the actual bit-pattern placed into the opcodes.
61
62 // General Registers
63 // Previously set EBX, ESI, and EDI as save-on-entry for java code
64 // Turn off SOE in java-code due to frequent use of uncommon-traps.
65 // Now that allocator is better, turn on ESI and EDI as SOE registers.
66
67 reg_def EBX(SOC, SOE, Op_RegI, 3, rbx->as_VMReg());
68 reg_def ECX(SOC, SOC, Op_RegI, 1, rcx->as_VMReg());
69 reg_def ESI(SOC, SOE, Op_RegI, 6, rsi->as_VMReg());
70 reg_def EDI(SOC, SOE, Op_RegI, 7, rdi->as_VMReg());
71 // now that adapter frames are gone EBP is always saved and restored by the prolog/epilog code
72 reg_def EBP(NS, SOE, Op_RegI, 5, rbp->as_VMReg());
73 reg_def EDX(SOC, SOC, Op_RegI, 2, rdx->as_VMReg());
74 reg_def EAX(SOC, SOC, Op_RegI, 0, rax->as_VMReg());
75 reg_def ESP( NS, NS, Op_RegI, 4, rsp->as_VMReg());
76
77 // Special Registers
78 reg_def EFLAGS(SOC, SOC, 0, 8, VMRegImpl::Bad());
79
80 // Float registers. We treat TOS/FPR0 special. It is invisible to the
81 // allocator, and only shows up in the encodings.
82 reg_def FPR0L( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad());
83 reg_def FPR0H( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad());
84 // Ok so here's the trick FPR1 is really st(0) except in the midst
85 // of emission of assembly for a machnode. During the emission the fpu stack
86 // is pushed making FPR1 == st(1) temporarily. However at any safepoint
87 // the stack will not have this element so FPR1 == st(0) from the
88 // oopMap viewpoint. This same weirdness with numbering causes
89 // instruction encoding to have to play games with the register
90 // encode to correct for this 0/1 issue. See MachSpillCopyNode::implementation
91 // where it does flt->flt moves to see an example
92 //
93 reg_def FPR1L( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg());
94 reg_def FPR1H( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg()->next());
95 reg_def FPR2L( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg());
96 reg_def FPR2H( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg()->next());
97 reg_def FPR3L( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg());
98 reg_def FPR3H( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg()->next());
99 reg_def FPR4L( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg());
100 reg_def FPR4H( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg()->next());
101 reg_def FPR5L( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg());
102 reg_def FPR5H( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg()->next());
103 reg_def FPR6L( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg());
104 reg_def FPR6H( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg()->next());
105 reg_def FPR7L( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg());
106 reg_def FPR7H( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg()->next());
107
108 // XMM registers. 128-bit registers or 4 words each, labeled a-d.
109 // Word a in each register holds a Float, words ab hold a Double.
110 // We currently do not use the SIMD capabilities, so registers cd
111 // are unused at the moment.
112 reg_def XMM0a( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg());
113 reg_def XMM0b( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()->next());
114 reg_def XMM1a( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg());
115 reg_def XMM1b( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()->next());
116 reg_def XMM2a( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg());
117 reg_def XMM2b( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()->next());
118 reg_def XMM3a( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg());
119 reg_def XMM3b( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()->next());
120 reg_def XMM4a( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg());
121 reg_def XMM4b( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()->next());
122 reg_def XMM5a( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg());
123 reg_def XMM5b( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()->next());
124 reg_def XMM6a( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg());
125 reg_def XMM6b( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()->next());
126 reg_def XMM7a( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg());
127 reg_def XMM7b( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()->next());
128
129 // Specify priority of register selection within phases of register
130 // allocation. Highest priority is first. A useful heuristic is to
131 // give registers a low priority when they are required by machine
132 // instructions, like EAX and EDX. Registers which are used as
133 // pairs must fall on an even boundary (witness the FPR#L's in this list).
134 // For the Intel integer registers, the equivalent Long pairs are
135 // EDX:EAX, EBX:ECX, and EDI:EBP.
136 alloc_class chunk0( ECX, EBX, EBP, EDI, EAX, EDX, ESI, ESP,
137 FPR0L, FPR0H, FPR1L, FPR1H, FPR2L, FPR2H,
138 FPR3L, FPR3H, FPR4L, FPR4H, FPR5L, FPR5H,
139 FPR6L, FPR6H, FPR7L, FPR7H );
140
141 alloc_class chunk1( XMM0a, XMM0b,
142 XMM1a, XMM1b,
143 XMM2a, XMM2b,
144 XMM3a, XMM3b,
145 XMM4a, XMM4b,
146 XMM5a, XMM5b,
147 XMM6a, XMM6b,
148 XMM7a, XMM7b, EFLAGS);
149
150
151 //----------Architecture Description Register Classes--------------------------
152 // Several register classes are automatically defined based upon information in
153 // this architecture description.
154 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ )
155 // 2) reg_class compiler_method_oop_reg ( /* as def'd in frame section */ )
156 // 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ )
157 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
158 //
159 // Class for all registers
160 reg_class any_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX, ESP);
161 // Class for general registers
162 reg_class e_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX);
163 // Class for general registers which may be used for implicit null checks on win95
164 // Also safe for use by tailjump. We don't want to allocate in rbp,
165 reg_class e_reg_no_rbp(EAX, EDX, EDI, ESI, ECX, EBX);
166 // Class of "X" registers
167 reg_class x_reg(EBX, ECX, EDX, EAX);
168 // Class of registers that can appear in an address with no offset.
169 // EBP and ESP require an extra instruction byte for zero offset.
170 // Used in fast-unlock
171 reg_class p_reg(EDX, EDI, ESI, EBX);
172 // Class for general registers not including ECX
173 reg_class ncx_reg(EAX, EDX, EBP, EDI, ESI, EBX);
174 // Class for general registers not including EAX
175 reg_class nax_reg(EDX, EDI, ESI, ECX, EBX);
176 // Class for general registers not including EAX or EBX.
177 reg_class nabx_reg(EDX, EDI, ESI, ECX, EBP);
178 // Class of EAX (for multiply and divide operations)
179 reg_class eax_reg(EAX);
180 // Class of EBX (for atomic add)
181 reg_class ebx_reg(EBX);
182 // Class of ECX (for shift and JCXZ operations and cmpLTMask)
183 reg_class ecx_reg(ECX);
184 // Class of EDX (for multiply and divide operations)
185 reg_class edx_reg(EDX);
186 // Class of EDI (for synchronization)
187 reg_class edi_reg(EDI);
188 // Class of ESI (for synchronization)
189 reg_class esi_reg(ESI);
190 // Singleton class for interpreter's stack pointer
191 reg_class ebp_reg(EBP);
192 // Singleton class for stack pointer
193 reg_class sp_reg(ESP);
194 // Singleton class for instruction pointer
195 // reg_class ip_reg(EIP);
196 // Singleton class for condition codes
197 reg_class int_flags(EFLAGS);
198 // Class of integer register pairs
199 reg_class long_reg( EAX,EDX, ECX,EBX, EBP,EDI );
200 // Class of integer register pairs that aligns with calling convention
201 reg_class eadx_reg( EAX,EDX );
202 reg_class ebcx_reg( ECX,EBX );
203 // Not AX or DX, used in divides
204 reg_class nadx_reg( EBX,ECX,ESI,EDI,EBP );
205
206 // Floating point registers. Notice FPR0 is not a choice.
207 // FPR0 is not ever allocated; we use clever encodings to fake
208 // a 2-address instructions out of Intels FP stack.
209 reg_class flt_reg( FPR1L,FPR2L,FPR3L,FPR4L,FPR5L,FPR6L,FPR7L );
210
211 // make a register class for SSE registers
212 reg_class xmm_reg(XMM0a, XMM1a, XMM2a, XMM3a, XMM4a, XMM5a, XMM6a, XMM7a);
213
214 // make a double register class for SSE2 registers
215 reg_class xdb_reg(XMM0a,XMM0b, XMM1a,XMM1b, XMM2a,XMM2b, XMM3a,XMM3b,
216 XMM4a,XMM4b, XMM5a,XMM5b, XMM6a,XMM6b, XMM7a,XMM7b );
217
218 reg_class dbl_reg( FPR1L,FPR1H, FPR2L,FPR2H, FPR3L,FPR3H,
219 FPR4L,FPR4H, FPR5L,FPR5H, FPR6L,FPR6H,
220 FPR7L,FPR7H );
221
222 reg_class flt_reg0( FPR1L );
223 reg_class dbl_reg0( FPR1L,FPR1H );
224 reg_class dbl_reg1( FPR2L,FPR2H );
225 reg_class dbl_notreg0( FPR2L,FPR2H, FPR3L,FPR3H, FPR4L,FPR4H,
226 FPR5L,FPR5H, FPR6L,FPR6H, FPR7L,FPR7H );
227
228 // XMM6 and XMM7 could be used as temporary registers for long, float and
229 // double values for SSE2.
230 reg_class xdb_reg6( XMM6a,XMM6b );
231 reg_class xdb_reg7( XMM7a,XMM7b );
232 %}
233
234
235 //----------SOURCE BLOCK-------------------------------------------------------
236 // This is a block of C++ code which provides values, functions, and
237 // definitions necessary in the rest of the architecture description
238 source %{
239 #define RELOC_IMM32 Assembler::imm_operand
240 #define RELOC_DISP32 Assembler::disp32_operand
241
242 #define __ _masm.
243
244 // How to find the high register of a Long pair, given the low register
245 #define HIGH_FROM_LOW(x) ((x)+2)
246
247 // These masks are used to provide 128-bit aligned bitmasks to the XMM
248 // instructions, to allow sign-masking or sign-bit flipping. They allow
249 // fast versions of NegF/NegD and AbsF/AbsD.
250
251 // Note: 'double' and 'long long' have 32-bits alignment on x86.
252 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) {
253 // Use the expression (adr)&(~0xF) to provide 128-bits aligned address
254 // of 128-bits operands for SSE instructions.
255 jlong *operand = (jlong*)(((uintptr_t)adr)&((uintptr_t)(~0xF)));
256 // Store the value to a 128-bits operand.
257 operand[0] = lo;
258 operand[1] = hi;
259 return operand;
260 }
261
262 // Buffer for 128-bits masks used by SSE instructions.
263 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment)
264
265 // Static initialization during VM startup.
266 static jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF));
267 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF));
268 static jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], CONST64(0x8000000080000000), CONST64(0x8000000080000000));
269 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], CONST64(0x8000000000000000), CONST64(0x8000000000000000));
270
271 // !!!!! Special hack to get all type of calls to specify the byte offset
272 // from the start of the call to the point where the return address
273 // will point.
274 int MachCallStaticJavaNode::ret_addr_offset() {
275 return 5 + (Compile::current()->in_24_bit_fp_mode() ? 6 : 0); // 5 bytes from start of call to where return address points
276 }
277
278 int MachCallDynamicJavaNode::ret_addr_offset() {
279 return 10 + (Compile::current()->in_24_bit_fp_mode() ? 6 : 0); // 10 bytes from start of call to where return address points
280 }
281
282 static int sizeof_FFree_Float_Stack_All = -1;
283
284 int MachCallRuntimeNode::ret_addr_offset() {
285 assert(sizeof_FFree_Float_Stack_All != -1, "must have been emitted already");
286 return sizeof_FFree_Float_Stack_All + 5 + (Compile::current()->in_24_bit_fp_mode() ? 6 : 0);
287 }
288
289 // Indicate if the safepoint node needs the polling page as an input.
290 // Since x86 does have absolute addressing, it doesn't.
291 bool SafePointNode::needs_polling_address_input() {
292 return false;
293 }
294
295 //
296 // Compute padding required for nodes which need alignment
297 //
298
299 // The address of the call instruction needs to be 4-byte aligned to
300 // ensure that it does not span a cache line so that it can be patched.
301 int CallStaticJavaDirectNode::compute_padding(int current_offset) const {
302 if (Compile::current()->in_24_bit_fp_mode())
303 current_offset += 6; // skip fldcw in pre_call_FPU, if any
304 current_offset += 1; // skip call opcode byte
305 return round_to(current_offset, alignment_required()) - current_offset;
306 }
307
308 // The address of the call instruction needs to be 4-byte aligned to
309 // ensure that it does not span a cache line so that it can be patched.
310 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const {
311 if (Compile::current()->in_24_bit_fp_mode())
312 current_offset += 6; // skip fldcw in pre_call_FPU, if any
313 current_offset += 5; // skip MOV instruction
314 current_offset += 1; // skip call opcode byte
315 return round_to(current_offset, alignment_required()) - current_offset;
316 }
317
318 #ifndef PRODUCT
319 void MachBreakpointNode::format( PhaseRegAlloc *, outputStream* st ) const {
320 st->print("INT3");
321 }
322 #endif
323
324 // EMIT_RM()
325 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) {
326 unsigned char c = (unsigned char)((f1 << 6) | (f2 << 3) | f3);
327 *(cbuf.code_end()) = c;
328 cbuf.set_code_end(cbuf.code_end() + 1);
329 }
330
331 // EMIT_CC()
332 void emit_cc(CodeBuffer &cbuf, int f1, int f2) {
333 unsigned char c = (unsigned char)( f1 | f2 );
334 *(cbuf.code_end()) = c;
335 cbuf.set_code_end(cbuf.code_end() + 1);
336 }
337
338 // EMIT_OPCODE()
339 void emit_opcode(CodeBuffer &cbuf, int code) {
340 *(cbuf.code_end()) = (unsigned char)code;
341 cbuf.set_code_end(cbuf.code_end() + 1);
342 }
343
344 // EMIT_OPCODE() w/ relocation information
345 void emit_opcode(CodeBuffer &cbuf, int code, relocInfo::relocType reloc, int offset = 0) {
346 cbuf.relocate(cbuf.inst_mark() + offset, reloc);
347 emit_opcode(cbuf, code);
348 }
349
350 // EMIT_D8()
351 void emit_d8(CodeBuffer &cbuf, int d8) {
352 *(cbuf.code_end()) = (unsigned char)d8;
353 cbuf.set_code_end(cbuf.code_end() + 1);
354 }
355
356 // EMIT_D16()
357 void emit_d16(CodeBuffer &cbuf, int d16) {
358 *((short *)(cbuf.code_end())) = d16;
359 cbuf.set_code_end(cbuf.code_end() + 2);
360 }
361
362 // EMIT_D32()
363 void emit_d32(CodeBuffer &cbuf, int d32) {
364 *((int *)(cbuf.code_end())) = d32;
365 cbuf.set_code_end(cbuf.code_end() + 4);
366 }
367
368 // emit 32 bit value and construct relocation entry from relocInfo::relocType
369 void emit_d32_reloc(CodeBuffer &cbuf, int d32, relocInfo::relocType reloc,
370 int format) {
371 cbuf.relocate(cbuf.inst_mark(), reloc, format);
372
373 *((int *)(cbuf.code_end())) = d32;
374 cbuf.set_code_end(cbuf.code_end() + 4);
375 }
376
377 // emit 32 bit value and construct relocation entry from RelocationHolder
378 void emit_d32_reloc(CodeBuffer &cbuf, int d32, RelocationHolder const& rspec,
379 int format) {
380 #ifdef ASSERT
381 if (rspec.reloc()->type() == relocInfo::oop_type && d32 != 0 && d32 != (int)Universe::non_oop_word()) {
382 assert(oop(d32)->is_oop() && oop(d32)->is_perm(), "cannot embed non-perm oops in code");
383 }
384 #endif
385 cbuf.relocate(cbuf.inst_mark(), rspec, format);
386
387 *((int *)(cbuf.code_end())) = d32;
388 cbuf.set_code_end(cbuf.code_end() + 4);
389 }
390
391 // Access stack slot for load or store
392 void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp) {
393 emit_opcode( cbuf, opcode ); // (e.g., FILD [ESP+src])
394 if( -128 <= disp && disp <= 127 ) {
395 emit_rm( cbuf, 0x01, rm_field, ESP_enc ); // R/M byte
396 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
397 emit_d8 (cbuf, disp); // Displacement // R/M byte
398 } else {
399 emit_rm( cbuf, 0x02, rm_field, ESP_enc ); // R/M byte
400 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
401 emit_d32(cbuf, disp); // Displacement // R/M byte
402 }
403 }
404
405 // eRegI ereg, memory mem) %{ // emit_reg_mem
406 void encode_RegMem( CodeBuffer &cbuf, int reg_encoding, int base, int index, int scale, int displace, bool displace_is_oop ) {
407 // There is no index & no scale, use form without SIB byte
408 if ((index == 0x4) &&
409 (scale == 0) && (base != ESP_enc)) {
410 // If no displacement, mode is 0x0; unless base is [EBP]
411 if ( (displace == 0) && (base != EBP_enc) ) {
412 emit_rm(cbuf, 0x0, reg_encoding, base);
413 }
414 else { // If 8-bit displacement, mode 0x1
415 if ((displace >= -128) && (displace <= 127)
416 && !(displace_is_oop) ) {
417 emit_rm(cbuf, 0x1, reg_encoding, base);
418 emit_d8(cbuf, displace);
419 }
420 else { // If 32-bit displacement
421 if (base == -1) { // Special flag for absolute address
422 emit_rm(cbuf, 0x0, reg_encoding, 0x5);
423 // (manual lies; no SIB needed here)
424 if ( displace_is_oop ) {
425 emit_d32_reloc(cbuf, displace, relocInfo::oop_type, 1);
426 } else {
427 emit_d32 (cbuf, displace);
428 }
429 }
430 else { // Normal base + offset
431 emit_rm(cbuf, 0x2, reg_encoding, base);
432 if ( displace_is_oop ) {
433 emit_d32_reloc(cbuf, displace, relocInfo::oop_type, 1);
434 } else {
435 emit_d32 (cbuf, displace);
436 }
437 }
438 }
439 }
440 }
441 else { // Else, encode with the SIB byte
442 // If no displacement, mode is 0x0; unless base is [EBP]
443 if (displace == 0 && (base != EBP_enc)) { // If no displacement
444 emit_rm(cbuf, 0x0, reg_encoding, 0x4);
445 emit_rm(cbuf, scale, index, base);
446 }
447 else { // If 8-bit displacement, mode 0x1
448 if ((displace >= -128) && (displace <= 127)
449 && !(displace_is_oop) ) {
450 emit_rm(cbuf, 0x1, reg_encoding, 0x4);
451 emit_rm(cbuf, scale, index, base);
452 emit_d8(cbuf, displace);
453 }
454 else { // If 32-bit displacement
455 if (base == 0x04 ) {
456 emit_rm(cbuf, 0x2, reg_encoding, 0x4);
457 emit_rm(cbuf, scale, index, 0x04);
458 } else {
459 emit_rm(cbuf, 0x2, reg_encoding, 0x4);
460 emit_rm(cbuf, scale, index, base);
461 }
462 if ( displace_is_oop ) {
463 emit_d32_reloc(cbuf, displace, relocInfo::oop_type, 1);
464 } else {
465 emit_d32 (cbuf, displace);
466 }
467 }
468 }
469 }
470 }
471
472
473 void encode_Copy( CodeBuffer &cbuf, int dst_encoding, int src_encoding ) {
474 if( dst_encoding == src_encoding ) {
475 // reg-reg copy, use an empty encoding
476 } else {
477 emit_opcode( cbuf, 0x8B );
478 emit_rm(cbuf, 0x3, dst_encoding, src_encoding );
479 }
480 }
481
482 void encode_CopyXD( CodeBuffer &cbuf, int dst_encoding, int src_encoding ) {
483 if( dst_encoding == src_encoding ) {
484 // reg-reg copy, use an empty encoding
485 } else {
486 MacroAssembler _masm(&cbuf);
487
488 __ movdqa(as_XMMRegister(dst_encoding), as_XMMRegister(src_encoding));
489 }
490 }
491
492
493 //=============================================================================
494 #ifndef PRODUCT
495 void MachPrologNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
496 Compile* C = ra_->C;
497 if( C->in_24_bit_fp_mode() ) {
498 st->print("FLDCW 24 bit fpu control word");
499 st->print_cr(""); st->print("\t");
500 }
501
502 int framesize = C->frame_slots() << LogBytesPerInt;
503 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
504 // Remove two words for return addr and rbp,
505 framesize -= 2*wordSize;
506
507 // Calls to C2R adapters often do not accept exceptional returns.
508 // We require that their callers must bang for them. But be careful, because
509 // some VM calls (such as call site linkage) can use several kilobytes of
510 // stack. But the stack safety zone should account for that.
511 // See bugs 4446381, 4468289, 4497237.
512 if (C->need_stack_bang(framesize)) {
513 st->print_cr("# stack bang"); st->print("\t");
514 }
515 st->print_cr("PUSHL EBP"); st->print("\t");
516
517 if( VerifyStackAtCalls ) { // Majik cookie to verify stack depth
518 st->print("PUSH 0xBADB100D\t# Majik cookie for stack depth check");
519 st->print_cr(""); st->print("\t");
520 framesize -= wordSize;
521 }
522
523 if ((C->in_24_bit_fp_mode() || VerifyStackAtCalls ) && framesize < 128 ) {
524 if (framesize) {
525 st->print("SUB ESP,%d\t# Create frame",framesize);
526 }
527 } else {
528 st->print("SUB ESP,%d\t# Create frame",framesize);
529 }
530 }
531 #endif
532
533
534 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
535 Compile* C = ra_->C;
536
537 if (UseSSE >= 2 && VerifyFPU) {
538 MacroAssembler masm(&cbuf);
539 masm.verify_FPU(0, "FPU stack must be clean on entry");
540 }
541
542 // WARNING: Initial instruction MUST be 5 bytes or longer so that
543 // NativeJump::patch_verified_entry will be able to patch out the entry
544 // code safely. The fldcw is ok at 6 bytes, the push to verify stack
545 // depth is ok at 5 bytes, the frame allocation can be either 3 or
546 // 6 bytes. So if we don't do the fldcw or the push then we must
547 // use the 6 byte frame allocation even if we have no frame. :-(
548 // If method sets FPU control word do it now
549 if( C->in_24_bit_fp_mode() ) {
550 MacroAssembler masm(&cbuf);
551 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
552 }
553
554 int framesize = C->frame_slots() << LogBytesPerInt;
555 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
556 // Remove two words for return addr and rbp,
557 framesize -= 2*wordSize;
558
559 // Calls to C2R adapters often do not accept exceptional returns.
560 // We require that their callers must bang for them. But be careful, because
561 // some VM calls (such as call site linkage) can use several kilobytes of
562 // stack. But the stack safety zone should account for that.
563 // See bugs 4446381, 4468289, 4497237.
564 if (C->need_stack_bang(framesize)) {
565 MacroAssembler masm(&cbuf);
566 masm.generate_stack_overflow_check(framesize);
567 }
568
569 // We always push rbp, so that on return to interpreter rbp, will be
570 // restored correctly and we can correct the stack.
571 emit_opcode(cbuf, 0x50 | EBP_enc);
572
573 if( VerifyStackAtCalls ) { // Majik cookie to verify stack depth
574 emit_opcode(cbuf, 0x68); // push 0xbadb100d
575 emit_d32(cbuf, 0xbadb100d);
576 framesize -= wordSize;
577 }
578
579 if ((C->in_24_bit_fp_mode() || VerifyStackAtCalls ) && framesize < 128 ) {
580 if (framesize) {
581 emit_opcode(cbuf, 0x83); // sub SP,#framesize
582 emit_rm(cbuf, 0x3, 0x05, ESP_enc);
583 emit_d8(cbuf, framesize);
584 }
585 } else {
586 emit_opcode(cbuf, 0x81); // sub SP,#framesize
587 emit_rm(cbuf, 0x3, 0x05, ESP_enc);
588 emit_d32(cbuf, framesize);
589 }
590 C->set_frame_complete(cbuf.code_end() - cbuf.code_begin());
591
592 #ifdef ASSERT
593 if (VerifyStackAtCalls) {
594 Label L;
595 MacroAssembler masm(&cbuf);
596 masm.push(rax);
597 masm.mov(rax, rsp);
598 masm.andptr(rax, StackAlignmentInBytes-1);
599 masm.cmpptr(rax, StackAlignmentInBytes-wordSize);
600 masm.pop(rax);
601 masm.jcc(Assembler::equal, L);
602 masm.stop("Stack is not properly aligned!");
603 masm.bind(L);
604 }
605 #endif
606
607 }
608
609 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
610 return MachNode::size(ra_); // too many variables; just compute it the hard way
611 }
612
613 int MachPrologNode::reloc() const {
614 return 0; // a large enough number
615 }
616
617 //=============================================================================
618 #ifndef PRODUCT
619 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
620 Compile *C = ra_->C;
621 int framesize = C->frame_slots() << LogBytesPerInt;
622 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
623 // Remove two words for return addr and rbp,
624 framesize -= 2*wordSize;
625
626 if( C->in_24_bit_fp_mode() ) {
627 st->print("FLDCW standard control word");
628 st->cr(); st->print("\t");
629 }
630 if( framesize ) {
631 st->print("ADD ESP,%d\t# Destroy frame",framesize);
632 st->cr(); st->print("\t");
633 }
634 st->print_cr("POPL EBP"); st->print("\t");
635 if( do_polling() && C->is_method_compilation() ) {
636 st->print("TEST PollPage,EAX\t! Poll Safepoint");
637 st->cr(); st->print("\t");
638 }
639 }
640 #endif
641
642 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
643 Compile *C = ra_->C;
644
645 // If method set FPU control word, restore to standard control word
646 if( C->in_24_bit_fp_mode() ) {
647 MacroAssembler masm(&cbuf);
648 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
649 }
650
651 int framesize = C->frame_slots() << LogBytesPerInt;
652 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
653 // Remove two words for return addr and rbp,
654 framesize -= 2*wordSize;
655
656 // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here
657
658 if( framesize >= 128 ) {
659 emit_opcode(cbuf, 0x81); // add SP, #framesize
660 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
661 emit_d32(cbuf, framesize);
662 }
663 else if( framesize ) {
664 emit_opcode(cbuf, 0x83); // add SP, #framesize
665 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
666 emit_d8(cbuf, framesize);
667 }
668
669 emit_opcode(cbuf, 0x58 | EBP_enc);
670
671 if( do_polling() && C->is_method_compilation() ) {
672 cbuf.relocate(cbuf.code_end(), relocInfo::poll_return_type, 0);
673 emit_opcode(cbuf,0x85);
674 emit_rm(cbuf, 0x0, EAX_enc, 0x5); // EAX
675 emit_d32(cbuf, (intptr_t)os::get_polling_page());
676 }
677 }
678
679 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
680 Compile *C = ra_->C;
681 // If method set FPU control word, restore to standard control word
682 int size = C->in_24_bit_fp_mode() ? 6 : 0;
683 if( do_polling() && C->is_method_compilation() ) size += 6;
684
685 int framesize = C->frame_slots() << LogBytesPerInt;
686 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
687 // Remove two words for return addr and rbp,
688 framesize -= 2*wordSize;
689
690 size++; // popl rbp,
691
692 if( framesize >= 128 ) {
693 size += 6;
694 } else {
695 size += framesize ? 3 : 0;
696 }
697 return size;
698 }
699
700 int MachEpilogNode::reloc() const {
701 return 0; // a large enough number
702 }
703
704 const Pipeline * MachEpilogNode::pipeline() const {
705 return MachNode::pipeline_class();
706 }
707
708 int MachEpilogNode::safepoint_offset() const { return 0; }
709
710 //=============================================================================
711
712 enum RC { rc_bad, rc_int, rc_float, rc_xmm, rc_stack };
713 static enum RC rc_class( OptoReg::Name reg ) {
714
715 if( !OptoReg::is_valid(reg) ) return rc_bad;
716 if (OptoReg::is_stack(reg)) return rc_stack;
717
718 VMReg r = OptoReg::as_VMReg(reg);
719 if (r->is_Register()) return rc_int;
720 if (r->is_FloatRegister()) {
721 assert(UseSSE < 2, "shouldn't be used in SSE2+ mode");
722 return rc_float;
723 }
724 assert(r->is_XMMRegister(), "must be");
725 return rc_xmm;
726 }
727
728 static int impl_helper( CodeBuffer *cbuf, bool do_size, bool is_load, int offset, int reg,
729 int opcode, const char *op_str, int size, outputStream* st ) {
730 if( cbuf ) {
731 emit_opcode (*cbuf, opcode );
732 encode_RegMem(*cbuf, Matcher::_regEncode[reg], ESP_enc, 0x4, 0, offset, false);
733 #ifndef PRODUCT
734 } else if( !do_size ) {
735 if( size != 0 ) st->print("\n\t");
736 if( opcode == 0x8B || opcode == 0x89 ) { // MOV
737 if( is_load ) st->print("%s %s,[ESP + #%d]",op_str,Matcher::regName[reg],offset);
738 else st->print("%s [ESP + #%d],%s",op_str,offset,Matcher::regName[reg]);
739 } else { // FLD, FST, PUSH, POP
740 st->print("%s [ESP + #%d]",op_str,offset);
741 }
742 #endif
743 }
744 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
745 return size+3+offset_size;
746 }
747
748 // Helper for XMM registers. Extra opcode bits, limited syntax.
749 static int impl_x_helper( CodeBuffer *cbuf, bool do_size, bool is_load,
750 int offset, int reg_lo, int reg_hi, int size, outputStream* st ) {
751 if( cbuf ) {
752 if( reg_lo+1 == reg_hi ) { // double move?
753 if( is_load && !UseXmmLoadAndClearUpper )
754 emit_opcode(*cbuf, 0x66 ); // use 'movlpd' for load
755 else
756 emit_opcode(*cbuf, 0xF2 ); // use 'movsd' otherwise
757 } else {
758 emit_opcode(*cbuf, 0xF3 );
759 }
760 emit_opcode(*cbuf, 0x0F );
761 if( reg_lo+1 == reg_hi && is_load && !UseXmmLoadAndClearUpper )
762 emit_opcode(*cbuf, 0x12 ); // use 'movlpd' for load
763 else
764 emit_opcode(*cbuf, is_load ? 0x10 : 0x11 );
765 encode_RegMem(*cbuf, Matcher::_regEncode[reg_lo], ESP_enc, 0x4, 0, offset, false);
766 #ifndef PRODUCT
767 } else if( !do_size ) {
768 if( size != 0 ) st->print("\n\t");
769 if( reg_lo+1 == reg_hi ) { // double move?
770 if( is_load ) st->print("%s %s,[ESP + #%d]",
771 UseXmmLoadAndClearUpper ? "MOVSD " : "MOVLPD",
772 Matcher::regName[reg_lo], offset);
773 else st->print("MOVSD [ESP + #%d],%s",
774 offset, Matcher::regName[reg_lo]);
775 } else {
776 if( is_load ) st->print("MOVSS %s,[ESP + #%d]",
777 Matcher::regName[reg_lo], offset);
778 else st->print("MOVSS [ESP + #%d],%s",
779 offset, Matcher::regName[reg_lo]);
780 }
781 #endif
782 }
783 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
784 return size+5+offset_size;
785 }
786
787
788 static int impl_movx_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
789 int src_hi, int dst_hi, int size, outputStream* st ) {
790 if( UseXmmRegToRegMoveAll ) {//Use movaps,movapd to move between xmm registers
791 if( cbuf ) {
792 if( (src_lo+1 == src_hi && dst_lo+1 == dst_hi) ) {
793 emit_opcode(*cbuf, 0x66 );
794 }
795 emit_opcode(*cbuf, 0x0F );
796 emit_opcode(*cbuf, 0x28 );
797 emit_rm (*cbuf, 0x3, Matcher::_regEncode[dst_lo], Matcher::_regEncode[src_lo] );
798 #ifndef PRODUCT
799 } else if( !do_size ) {
800 if( size != 0 ) st->print("\n\t");
801 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double move?
802 st->print("MOVAPD %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
803 } else {
804 st->print("MOVAPS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
805 }
806 #endif
807 }
808 return size + ((src_lo+1 == src_hi && dst_lo+1 == dst_hi) ? 4 : 3);
809 } else {
810 if( cbuf ) {
811 emit_opcode(*cbuf, (src_lo+1 == src_hi && dst_lo+1 == dst_hi) ? 0xF2 : 0xF3 );
812 emit_opcode(*cbuf, 0x0F );
813 emit_opcode(*cbuf, 0x10 );
814 emit_rm (*cbuf, 0x3, Matcher::_regEncode[dst_lo], Matcher::_regEncode[src_lo] );
815 #ifndef PRODUCT
816 } else if( !do_size ) {
817 if( size != 0 ) st->print("\n\t");
818 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double move?
819 st->print("MOVSD %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
820 } else {
821 st->print("MOVSS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
822 }
823 #endif
824 }
825 return size+4;
826 }
827 }
828
829 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int size, outputStream* st ) {
830 if( cbuf ) {
831 emit_opcode(*cbuf, 0x8B );
832 emit_rm (*cbuf, 0x3, Matcher::_regEncode[dst], Matcher::_regEncode[src] );
833 #ifndef PRODUCT
834 } else if( !do_size ) {
835 if( size != 0 ) st->print("\n\t");
836 st->print("MOV %s,%s",Matcher::regName[dst],Matcher::regName[src]);
837 #endif
838 }
839 return size+2;
840 }
841
842 static int impl_fp_store_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int src_hi, int dst_lo, int dst_hi,
843 int offset, int size, outputStream* st ) {
844 if( src_lo != FPR1L_num ) { // Move value to top of FP stack, if not already there
845 if( cbuf ) {
846 emit_opcode( *cbuf, 0xD9 ); // FLD (i.e., push it)
847 emit_d8( *cbuf, 0xC0-1+Matcher::_regEncode[src_lo] );
848 #ifndef PRODUCT
849 } else if( !do_size ) {
850 if( size != 0 ) st->print("\n\t");
851 st->print("FLD %s",Matcher::regName[src_lo]);
852 #endif
853 }
854 size += 2;
855 }
856
857 int st_op = (src_lo != FPR1L_num) ? EBX_num /*store & pop*/ : EDX_num /*store no pop*/;
858 const char *op_str;
859 int op;
860 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double store?
861 op_str = (src_lo != FPR1L_num) ? "FSTP_D" : "FST_D ";
862 op = 0xDD;
863 } else { // 32-bit store
864 op_str = (src_lo != FPR1L_num) ? "FSTP_S" : "FST_S ";
865 op = 0xD9;
866 assert( !OptoReg::is_valid(src_hi) && !OptoReg::is_valid(dst_hi), "no non-adjacent float-stores" );
867 }
868
869 return impl_helper(cbuf,do_size,false,offset,st_op,op,op_str,size, st);
870 }
871
872 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream* st ) const {
873 // Get registers to move
874 OptoReg::Name src_second = ra_->get_reg_second(in(1));
875 OptoReg::Name src_first = ra_->get_reg_first(in(1));
876 OptoReg::Name dst_second = ra_->get_reg_second(this );
877 OptoReg::Name dst_first = ra_->get_reg_first(this );
878
879 enum RC src_second_rc = rc_class(src_second);
880 enum RC src_first_rc = rc_class(src_first);
881 enum RC dst_second_rc = rc_class(dst_second);
882 enum RC dst_first_rc = rc_class(dst_first);
883
884 assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" );
885
886 // Generate spill code!
887 int size = 0;
888
889 if( src_first == dst_first && src_second == dst_second )
890 return size; // Self copy, no move
891
892 // --------------------------------------
893 // Check for mem-mem move. push/pop to move.
894 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
895 if( src_second == dst_first ) { // overlapping stack copy ranges
896 assert( src_second_rc == rc_stack && dst_second_rc == rc_stack, "we only expect a stk-stk copy here" );
897 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH ",size, st);
898 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP ",size, st);
899 src_second_rc = dst_second_rc = rc_bad; // flag as already moved the second bits
900 }
901 // move low bits
902 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),ESI_num,0xFF,"PUSH ",size, st);
903 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),EAX_num,0x8F,"POP ",size, st);
904 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) { // mov second bits
905 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH ",size, st);
906 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP ",size, st);
907 }
908 return size;
909 }
910
911 // --------------------------------------
912 // Check for integer reg-reg copy
913 if( src_first_rc == rc_int && dst_first_rc == rc_int )
914 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,size, st);
915
916 // Check for integer store
917 if( src_first_rc == rc_int && dst_first_rc == rc_stack )
918 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first,0x89,"MOV ",size, st);
919
920 // Check for integer load
921 if( dst_first_rc == rc_int && src_first_rc == rc_stack )
922 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first,0x8B,"MOV ",size, st);
923
924 // --------------------------------------
925 // Check for float reg-reg copy
926 if( src_first_rc == rc_float && dst_first_rc == rc_float ) {
927 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) ||
928 (src_first+1 == src_second && dst_first+1 == dst_second), "no non-adjacent float-moves" );
929 if( cbuf ) {
930
931 // Note the mucking with the register encode to compensate for the 0/1
932 // indexing issue mentioned in a comment in the reg_def sections
933 // for FPR registers many lines above here.
934
935 if( src_first != FPR1L_num ) {
936 emit_opcode (*cbuf, 0xD9 ); // FLD ST(i)
937 emit_d8 (*cbuf, 0xC0+Matcher::_regEncode[src_first]-1 );
938 emit_opcode (*cbuf, 0xDD ); // FSTP ST(i)
939 emit_d8 (*cbuf, 0xD8+Matcher::_regEncode[dst_first] );
940 } else {
941 emit_opcode (*cbuf, 0xDD ); // FST ST(i)
942 emit_d8 (*cbuf, 0xD0+Matcher::_regEncode[dst_first]-1 );
943 }
944 #ifndef PRODUCT
945 } else if( !do_size ) {
946 if( size != 0 ) st->print("\n\t");
947 if( src_first != FPR1L_num ) st->print("FLD %s\n\tFSTP %s",Matcher::regName[src_first],Matcher::regName[dst_first]);
948 else st->print( "FST %s", Matcher::regName[dst_first]);
949 #endif
950 }
951 return size + ((src_first != FPR1L_num) ? 2+2 : 2);
952 }
953
954 // Check for float store
955 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) {
956 return impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,ra_->reg2offset(dst_first),size, st);
957 }
958
959 // Check for float load
960 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) {
961 int offset = ra_->reg2offset(src_first);
962 const char *op_str;
963 int op;
964 if( src_first+1 == src_second && dst_first+1 == dst_second ) { // double load?
965 op_str = "FLD_D";
966 op = 0xDD;
967 } else { // 32-bit load
968 op_str = "FLD_S";
969 op = 0xD9;
970 assert( src_second_rc == rc_bad && dst_second_rc == rc_bad, "no non-adjacent float-loads" );
971 }
972 if( cbuf ) {
973 emit_opcode (*cbuf, op );
974 encode_RegMem(*cbuf, 0x0, ESP_enc, 0x4, 0, offset, false);
975 emit_opcode (*cbuf, 0xDD ); // FSTP ST(i)
976 emit_d8 (*cbuf, 0xD8+Matcher::_regEncode[dst_first] );
977 #ifndef PRODUCT
978 } else if( !do_size ) {
979 if( size != 0 ) st->print("\n\t");
980 st->print("%s ST,[ESP + #%d]\n\tFSTP %s",op_str, offset,Matcher::regName[dst_first]);
981 #endif
982 }
983 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
984 return size + 3+offset_size+2;
985 }
986
987 // Check for xmm reg-reg copy
988 if( src_first_rc == rc_xmm && dst_first_rc == rc_xmm ) {
989 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) ||
990 (src_first+1 == src_second && dst_first+1 == dst_second),
991 "no non-adjacent float-moves" );
992 return impl_movx_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st);
993 }
994
995 // Check for xmm store
996 if( src_first_rc == rc_xmm && dst_first_rc == rc_stack ) {
997 return impl_x_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first, src_second, size, st);
998 }
999
1000 // Check for float xmm load
1001 if( dst_first_rc == rc_xmm && src_first_rc == rc_stack ) {
1002 return impl_x_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first, dst_second, size, st);
1003 }
1004
1005 // Copy from float reg to xmm reg
1006 if( dst_first_rc == rc_xmm && src_first_rc == rc_float ) {
1007 // copy to the top of stack from floating point reg
1008 // and use LEA to preserve flags
1009 if( cbuf ) {
1010 emit_opcode(*cbuf,0x8D); // LEA ESP,[ESP-8]
1011 emit_rm(*cbuf, 0x1, ESP_enc, 0x04);
1012 emit_rm(*cbuf, 0x0, 0x04, ESP_enc);
1013 emit_d8(*cbuf,0xF8);
1014 #ifndef PRODUCT
1015 } else if( !do_size ) {
1016 if( size != 0 ) st->print("\n\t");
1017 st->print("LEA ESP,[ESP-8]");
1018 #endif
1019 }
1020 size += 4;
1021
1022 size = impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,0,size, st);
1023
1024 // Copy from the temp memory to the xmm reg.
1025 size = impl_x_helper(cbuf,do_size,true ,0,dst_first, dst_second, size, st);
1026
1027 if( cbuf ) {
1028 emit_opcode(*cbuf,0x8D); // LEA ESP,[ESP+8]
1029 emit_rm(*cbuf, 0x1, ESP_enc, 0x04);
1030 emit_rm(*cbuf, 0x0, 0x04, ESP_enc);
1031 emit_d8(*cbuf,0x08);
1032 #ifndef PRODUCT
1033 } else if( !do_size ) {
1034 if( size != 0 ) st->print("\n\t");
1035 st->print("LEA ESP,[ESP+8]");
1036 #endif
1037 }
1038 size += 4;
1039 return size;
1040 }
1041
1042 assert( size > 0, "missed a case" );
1043
1044 // --------------------------------------------------------------------
1045 // Check for second bits still needing moving.
1046 if( src_second == dst_second )
1047 return size; // Self copy; no move
1048 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" );
1049
1050 // Check for second word int-int move
1051 if( src_second_rc == rc_int && dst_second_rc == rc_int )
1052 return impl_mov_helper(cbuf,do_size,src_second,dst_second,size, st);
1053
1054 // Check for second word integer store
1055 if( src_second_rc == rc_int && dst_second_rc == rc_stack )
1056 return impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),src_second,0x89,"MOV ",size, st);
1057
1058 // Check for second word integer load
1059 if( dst_second_rc == rc_int && src_second_rc == rc_stack )
1060 return impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),dst_second,0x8B,"MOV ",size, st);
1061
1062
1063 Unimplemented();
1064 }
1065
1066 #ifndef PRODUCT
1067 void MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1068 implementation( NULL, ra_, false, st );
1069 }
1070 #endif
1071
1072 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1073 implementation( &cbuf, ra_, false, NULL );
1074 }
1075
1076 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1077 return implementation( NULL, ra_, true, NULL );
1078 }
1079
1080 //=============================================================================
1081 #ifndef PRODUCT
1082 void MachNopNode::format( PhaseRegAlloc *, outputStream* st ) const {
1083 st->print("NOP \t# %d bytes pad for loops and calls", _count);
1084 }
1085 #endif
1086
1087 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc * ) const {
1088 MacroAssembler _masm(&cbuf);
1089 __ nop(_count);
1090 }
1091
1092 uint MachNopNode::size(PhaseRegAlloc *) const {
1093 return _count;
1094 }
1095
1096
1097 //=============================================================================
1098 #ifndef PRODUCT
1099 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1100 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1101 int reg = ra_->get_reg_first(this);
1102 st->print("LEA %s,[ESP + #%d]",Matcher::regName[reg],offset);
1103 }
1104 #endif
1105
1106 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1107 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1108 int reg = ra_->get_encode(this);
1109 if( offset >= 128 ) {
1110 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1111 emit_rm(cbuf, 0x2, reg, 0x04);
1112 emit_rm(cbuf, 0x0, 0x04, ESP_enc);
1113 emit_d32(cbuf, offset);
1114 }
1115 else {
1116 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1117 emit_rm(cbuf, 0x1, reg, 0x04);
1118 emit_rm(cbuf, 0x0, 0x04, ESP_enc);
1119 emit_d8(cbuf, offset);
1120 }
1121 }
1122
1123 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1124 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1125 if( offset >= 128 ) {
1126 return 7;
1127 }
1128 else {
1129 return 4;
1130 }
1131 }
1132
1133 //=============================================================================
1134
1135 // emit call stub, compiled java to interpreter
1136 void emit_java_to_interp(CodeBuffer &cbuf ) {
1137 // Stub is fixed up when the corresponding call is converted from calling
1138 // compiled code to calling interpreted code.
1139 // mov rbx,0
1140 // jmp -1
1141
1142 address mark = cbuf.inst_mark(); // get mark within main instrs section
1143
1144 // Note that the code buffer's inst_mark is always relative to insts.
1145 // That's why we must use the macroassembler to generate a stub.
1146 MacroAssembler _masm(&cbuf);
1147
1148 address base =
1149 __ start_a_stub(Compile::MAX_stubs_size);
1150 if (base == NULL) return; // CodeBuffer::expand failed
1151 // static stub relocation stores the instruction address of the call
1152 __ relocate(static_stub_Relocation::spec(mark), RELOC_IMM32);
1153 // static stub relocation also tags the methodOop in the code-stream.
1154 __ movoop(rbx, (jobject)NULL); // method is zapped till fixup time
1155 // This is recognized as unresolved by relocs/nativeInst/ic code
1156 __ jump(RuntimeAddress(__ pc()));
1157
1158 __ end_a_stub();
1159 // Update current stubs pointer and restore code_end.
1160 }
1161 // size of call stub, compiled java to interpretor
1162 uint size_java_to_interp() {
1163 return 10; // movl; jmp
1164 }
1165 // relocation entries for call stub, compiled java to interpretor
1166 uint reloc_java_to_interp() {
1167 return 4; // 3 in emit_java_to_interp + 1 in Java_Static_Call
1168 }
1169
1170 //=============================================================================
1171 #ifndef PRODUCT
1172 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1173 st->print_cr( "CMP EAX,[ECX+4]\t# Inline cache check");
1174 st->print_cr("\tJNE SharedRuntime::handle_ic_miss_stub");
1175 st->print_cr("\tNOP");
1176 st->print_cr("\tNOP");
1177 if( !OptoBreakpoint )
1178 st->print_cr("\tNOP");
1179 }
1180 #endif
1181
1182 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1183 MacroAssembler masm(&cbuf);
1184 #ifdef ASSERT
1185 uint code_size = cbuf.code_size();
1186 #endif
1187 masm.cmpptr(rax, Address(rcx, oopDesc::klass_offset_in_bytes()));
1188 masm.jump_cc(Assembler::notEqual,
1189 RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1190 /* WARNING these NOPs are critical so that verified entry point is properly
1191 aligned for patching by NativeJump::patch_verified_entry() */
1192 int nops_cnt = 2;
1193 if( !OptoBreakpoint ) // Leave space for int3
1194 nops_cnt += 1;
1195 masm.nop(nops_cnt);
1196
1197 assert(cbuf.code_size() - code_size == size(ra_), "checking code size of inline cache node");
1198 }
1199
1200 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
1201 return OptoBreakpoint ? 11 : 12;
1202 }
1203
1204
1205 //=============================================================================
1206 uint size_exception_handler() {
1207 // NativeCall instruction size is the same as NativeJump.
1208 // exception handler starts out as jump and can be patched to
1209 // a call be deoptimization. (4932387)
1210 // Note that this value is also credited (in output.cpp) to
1211 // the size of the code section.
1212 return NativeJump::instruction_size;
1213 }
1214
1215 // Emit exception handler code. Stuff framesize into a register
1216 // and call a VM stub routine.
1217 int emit_exception_handler(CodeBuffer& cbuf) {
1218
1219 // Note that the code buffer's inst_mark is always relative to insts.
1220 // That's why we must use the macroassembler to generate a handler.
1221 MacroAssembler _masm(&cbuf);
1222 address base =
1223 __ start_a_stub(size_exception_handler());
1224 if (base == NULL) return 0; // CodeBuffer::expand failed
1225 int offset = __ offset();
1226 __ jump(RuntimeAddress(OptoRuntime::exception_blob()->instructions_begin()));
1227 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
1228 __ end_a_stub();
1229 return offset;
1230 }
1231
1232 uint size_deopt_handler() {
1233 // NativeCall instruction size is the same as NativeJump.
1234 // exception handler starts out as jump and can be patched to
1235 // a call be deoptimization. (4932387)
1236 // Note that this value is also credited (in output.cpp) to
1237 // the size of the code section.
1238 return 5 + NativeJump::instruction_size; // pushl(); jmp;
1239 }
1240
1241 // Emit deopt handler code.
1242 int emit_deopt_handler(CodeBuffer& cbuf) {
1243
1244 // Note that the code buffer's inst_mark is always relative to insts.
1245 // That's why we must use the macroassembler to generate a handler.
1246 MacroAssembler _masm(&cbuf);
1247 address base =
1248 __ start_a_stub(size_exception_handler());
1249 if (base == NULL) return 0; // CodeBuffer::expand failed
1250 int offset = __ offset();
1251 InternalAddress here(__ pc());
1252 __ pushptr(here.addr());
1253
1254 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
1255 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
1256 __ end_a_stub();
1257 return offset;
1258 }
1259
1260
1261 static void emit_double_constant(CodeBuffer& cbuf, double x) {
1262 int mark = cbuf.insts()->mark_off();
1263 MacroAssembler _masm(&cbuf);
1264 address double_address = __ double_constant(x);
1265 cbuf.insts()->set_mark_off(mark); // preserve mark across masm shift
1266 emit_d32_reloc(cbuf,
1267 (int)double_address,
1268 internal_word_Relocation::spec(double_address),
1269 RELOC_DISP32);
1270 }
1271
1272 static void emit_float_constant(CodeBuffer& cbuf, float x) {
1273 int mark = cbuf.insts()->mark_off();
1274 MacroAssembler _masm(&cbuf);
1275 address float_address = __ float_constant(x);
1276 cbuf.insts()->set_mark_off(mark); // preserve mark across masm shift
1277 emit_d32_reloc(cbuf,
1278 (int)float_address,
1279 internal_word_Relocation::spec(float_address),
1280 RELOC_DISP32);
1281 }
1282
1283
1284 const bool Matcher::match_rule_supported(int opcode) {
1285 if (!has_match_rule(opcode))
1286 return false;
1287
1288 return true; // Per default match rules are supported.
1289 }
1290
1291 int Matcher::regnum_to_fpu_offset(int regnum) {
1292 return regnum - 32; // The FP registers are in the second chunk
1293 }
1294
1295 bool is_positive_zero_float(jfloat f) {
1296 return jint_cast(f) == jint_cast(0.0F);
1297 }
1298
1299 bool is_positive_one_float(jfloat f) {
1300 return jint_cast(f) == jint_cast(1.0F);
1301 }
1302
1303 bool is_positive_zero_double(jdouble d) {
1304 return jlong_cast(d) == jlong_cast(0.0);
1305 }
1306
1307 bool is_positive_one_double(jdouble d) {
1308 return jlong_cast(d) == jlong_cast(1.0);
1309 }
1310
1311 // This is UltraSparc specific, true just means we have fast l2f conversion
1312 const bool Matcher::convL2FSupported(void) {
1313 return true;
1314 }
1315
1316 // Vector width in bytes
1317 const uint Matcher::vector_width_in_bytes(void) {
1318 return UseSSE >= 2 ? 8 : 0;
1319 }
1320
1321 // Vector ideal reg
1322 const uint Matcher::vector_ideal_reg(void) {
1323 return Op_RegD;
1324 }
1325
1326 // Is this branch offset short enough that a short branch can be used?
1327 //
1328 // NOTE: If the platform does not provide any short branch variants, then
1329 // this method should return false for offset 0.
1330 bool Matcher::is_short_branch_offset(int rule, int offset) {
1331 // the short version of jmpConUCF2 contains multiple branches,
1332 // making the reach slightly less
1333 if (rule == jmpConUCF2_rule)
1334 return (-126 <= offset && offset <= 125);
1335 return (-128 <= offset && offset <= 127);
1336 }
1337
1338 const bool Matcher::isSimpleConstant64(jlong value) {
1339 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1340 return false;
1341 }
1342
1343 // The ecx parameter to rep stos for the ClearArray node is in dwords.
1344 const bool Matcher::init_array_count_is_in_bytes = false;
1345
1346 // Threshold size for cleararray.
1347 const int Matcher::init_array_short_size = 8 * BytesPerLong;
1348
1349 // Should the Matcher clone shifts on addressing modes, expecting them to
1350 // be subsumed into complex addressing expressions or compute them into
1351 // registers? True for Intel but false for most RISCs
1352 const bool Matcher::clone_shift_expressions = true;
1353
1354 // Is it better to copy float constants, or load them directly from memory?
1355 // Intel can load a float constant from a direct address, requiring no
1356 // extra registers. Most RISCs will have to materialize an address into a
1357 // register first, so they would do better to copy the constant from stack.
1358 const bool Matcher::rematerialize_float_constants = true;
1359
1360 // If CPU can load and store mis-aligned doubles directly then no fixup is
1361 // needed. Else we split the double into 2 integer pieces and move it
1362 // piece-by-piece. Only happens when passing doubles into C code as the
1363 // Java calling convention forces doubles to be aligned.
1364 const bool Matcher::misaligned_doubles_ok = true;
1365
1366
1367 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
1368 // Get the memory operand from the node
1369 uint numopnds = node->num_opnds(); // Virtual call for number of operands
1370 uint skipped = node->oper_input_base(); // Sum of leaves skipped so far
1371 assert( idx >= skipped, "idx too low in pd_implicit_null_fixup" );
1372 uint opcnt = 1; // First operand
1373 uint num_edges = node->_opnds[1]->num_edges(); // leaves for first operand
1374 while( idx >= skipped+num_edges ) {
1375 skipped += num_edges;
1376 opcnt++; // Bump operand count
1377 assert( opcnt < numopnds, "Accessing non-existent operand" );
1378 num_edges = node->_opnds[opcnt]->num_edges(); // leaves for next operand
1379 }
1380
1381 MachOper *memory = node->_opnds[opcnt];
1382 MachOper *new_memory = NULL;
1383 switch (memory->opcode()) {
1384 case DIRECT:
1385 case INDOFFSET32X:
1386 // No transformation necessary.
1387 return;
1388 case INDIRECT:
1389 new_memory = new (C) indirect_win95_safeOper( );
1390 break;
1391 case INDOFFSET8:
1392 new_memory = new (C) indOffset8_win95_safeOper(memory->disp(NULL, NULL, 0));
1393 break;
1394 case INDOFFSET32:
1395 new_memory = new (C) indOffset32_win95_safeOper(memory->disp(NULL, NULL, 0));
1396 break;
1397 case INDINDEXOFFSET:
1398 new_memory = new (C) indIndexOffset_win95_safeOper(memory->disp(NULL, NULL, 0));
1399 break;
1400 case INDINDEXSCALE:
1401 new_memory = new (C) indIndexScale_win95_safeOper(memory->scale());
1402 break;
1403 case INDINDEXSCALEOFFSET:
1404 new_memory = new (C) indIndexScaleOffset_win95_safeOper(memory->scale(), memory->disp(NULL, NULL, 0));
1405 break;
1406 case LOAD_LONG_INDIRECT:
1407 case LOAD_LONG_INDOFFSET32:
1408 // Does not use EBP as address register, use { EDX, EBX, EDI, ESI}
1409 return;
1410 default:
1411 assert(false, "unexpected memory operand in pd_implicit_null_fixup()");
1412 return;
1413 }
1414 node->_opnds[opcnt] = new_memory;
1415 }
1416
1417 // Advertise here if the CPU requires explicit rounding operations
1418 // to implement the UseStrictFP mode.
1419 const bool Matcher::strict_fp_requires_explicit_rounding = true;
1420
1421 // Do floats take an entire double register or just half?
1422 const bool Matcher::float_in_double = true;
1423 // Do ints take an entire long register or just half?
1424 const bool Matcher::int_in_long = false;
1425
1426 // Return whether or not this register is ever used as an argument. This
1427 // function is used on startup to build the trampoline stubs in generateOptoStub.
1428 // Registers not mentioned will be killed by the VM call in the trampoline, and
1429 // arguments in those registers not be available to the callee.
1430 bool Matcher::can_be_java_arg( int reg ) {
1431 if( reg == ECX_num || reg == EDX_num ) return true;
1432 if( (reg == XMM0a_num || reg == XMM1a_num) && UseSSE>=1 ) return true;
1433 if( (reg == XMM0b_num || reg == XMM1b_num) && UseSSE>=2 ) return true;
1434 return false;
1435 }
1436
1437 bool Matcher::is_spillable_arg( int reg ) {
1438 return can_be_java_arg(reg);
1439 }
1440
1441 // Register for DIVI projection of divmodI
1442 RegMask Matcher::divI_proj_mask() {
1443 return EAX_REG_mask;
1444 }
1445
1446 // Register for MODI projection of divmodI
1447 RegMask Matcher::modI_proj_mask() {
1448 return EDX_REG_mask;
1449 }
1450
1451 // Register for DIVL projection of divmodL
1452 RegMask Matcher::divL_proj_mask() {
1453 ShouldNotReachHere();
1454 return RegMask();
1455 }
1456
1457 // Register for MODL projection of divmodL
1458 RegMask Matcher::modL_proj_mask() {
1459 ShouldNotReachHere();
1460 return RegMask();
1461 }
1462
1463 %}
1464
1465 //----------ENCODING BLOCK-----------------------------------------------------
1466 // This block specifies the encoding classes used by the compiler to output
1467 // byte streams. Encoding classes generate functions which are called by
1468 // Machine Instruction Nodes in order to generate the bit encoding of the
1469 // instruction. Operands specify their base encoding interface with the
1470 // interface keyword. There are currently supported four interfaces,
1471 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
1472 // operand to generate a function which returns its register number when
1473 // queried. CONST_INTER causes an operand to generate a function which
1474 // returns the value of the constant when queried. MEMORY_INTER causes an
1475 // operand to generate four functions which return the Base Register, the
1476 // Index Register, the Scale Value, and the Offset Value of the operand when
1477 // queried. COND_INTER causes an operand to generate six functions which
1478 // return the encoding code (ie - encoding bits for the instruction)
1479 // associated with each basic boolean condition for a conditional instruction.
1480 // Instructions specify two basic values for encoding. They use the
1481 // ins_encode keyword to specify their encoding class (which must be one of
1482 // the class names specified in the encoding block), and they use the
1483 // opcode keyword to specify, in order, their primary, secondary, and
1484 // tertiary opcode. Only the opcode sections which a particular instruction
1485 // needs for encoding need to be specified.
1486 encode %{
1487 // Build emit functions for each basic byte or larger field in the intel
1488 // encoding scheme (opcode, rm, sib, immediate), and call them from C++
1489 // code in the enc_class source block. Emit functions will live in the
1490 // main source block for now. In future, we can generalize this by
1491 // adding a syntax that specifies the sizes of fields in an order,
1492 // so that the adlc can build the emit functions automagically
1493
1494 // Emit primary opcode
1495 enc_class OpcP %{
1496 emit_opcode(cbuf, $primary);
1497 %}
1498
1499 // Emit secondary opcode
1500 enc_class OpcS %{
1501 emit_opcode(cbuf, $secondary);
1502 %}
1503
1504 // Emit opcode directly
1505 enc_class Opcode(immI d8) %{
1506 emit_opcode(cbuf, $d8$$constant);
1507 %}
1508
1509 enc_class SizePrefix %{
1510 emit_opcode(cbuf,0x66);
1511 %}
1512
1513 enc_class RegReg (eRegI dst, eRegI src) %{ // RegReg(Many)
1514 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1515 %}
1516
1517 enc_class OpcRegReg (immI opcode, eRegI dst, eRegI src) %{ // OpcRegReg(Many)
1518 emit_opcode(cbuf,$opcode$$constant);
1519 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1520 %}
1521
1522 enc_class mov_r32_imm0( eRegI dst ) %{
1523 emit_opcode( cbuf, 0xB8 + $dst$$reg ); // 0xB8+ rd -- MOV r32 ,imm32
1524 emit_d32 ( cbuf, 0x0 ); // imm32==0x0
1525 %}
1526
1527 enc_class cdq_enc %{
1528 // Full implementation of Java idiv and irem; checks for
1529 // special case as described in JVM spec., p.243 & p.271.
1530 //
1531 // normal case special case
1532 //
1533 // input : rax,: dividend min_int
1534 // reg: divisor -1
1535 //
1536 // output: rax,: quotient (= rax, idiv reg) min_int
1537 // rdx: remainder (= rax, irem reg) 0
1538 //
1539 // Code sequnce:
1540 //
1541 // 81 F8 00 00 00 80 cmp rax,80000000h
1542 // 0F 85 0B 00 00 00 jne normal_case
1543 // 33 D2 xor rdx,edx
1544 // 83 F9 FF cmp rcx,0FFh
1545 // 0F 84 03 00 00 00 je done
1546 // normal_case:
1547 // 99 cdq
1548 // F7 F9 idiv rax,ecx
1549 // done:
1550 //
1551 emit_opcode(cbuf,0x81); emit_d8(cbuf,0xF8);
1552 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00);
1553 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x80); // cmp rax,80000000h
1554 emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x85);
1555 emit_opcode(cbuf,0x0B); emit_d8(cbuf,0x00);
1556 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); // jne normal_case
1557 emit_opcode(cbuf,0x33); emit_d8(cbuf,0xD2); // xor rdx,edx
1558 emit_opcode(cbuf,0x83); emit_d8(cbuf,0xF9); emit_d8(cbuf,0xFF); // cmp rcx,0FFh
1559 emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x84);
1560 emit_opcode(cbuf,0x03); emit_d8(cbuf,0x00);
1561 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); // je done
1562 // normal_case:
1563 emit_opcode(cbuf,0x99); // cdq
1564 // idiv (note: must be emitted by the user of this rule)
1565 // normal:
1566 %}
1567
1568 // Dense encoding for older common ops
1569 enc_class Opc_plus(immI opcode, eRegI reg) %{
1570 emit_opcode(cbuf, $opcode$$constant + $reg$$reg);
1571 %}
1572
1573
1574 // Opcde enc_class for 8/32 bit immediate instructions with sign-extension
1575 enc_class OpcSE (immI imm) %{ // Emit primary opcode and set sign-extend bit
1576 // Check for 8-bit immediate, and set sign extend bit in opcode
1577 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1578 emit_opcode(cbuf, $primary | 0x02);
1579 }
1580 else { // If 32-bit immediate
1581 emit_opcode(cbuf, $primary);
1582 }
1583 %}
1584
1585 enc_class OpcSErm (eRegI dst, immI imm) %{ // OpcSEr/m
1586 // Emit primary opcode and set sign-extend bit
1587 // Check for 8-bit immediate, and set sign extend bit in opcode
1588 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1589 emit_opcode(cbuf, $primary | 0x02); }
1590 else { // If 32-bit immediate
1591 emit_opcode(cbuf, $primary);
1592 }
1593 // Emit r/m byte with secondary opcode, after primary opcode.
1594 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1595 %}
1596
1597 enc_class Con8or32 (immI imm) %{ // Con8or32(storeImmI), 8 or 32 bits
1598 // Check for 8-bit immediate, and set sign extend bit in opcode
1599 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1600 $$$emit8$imm$$constant;
1601 }
1602 else { // If 32-bit immediate
1603 // Output immediate
1604 $$$emit32$imm$$constant;
1605 }
1606 %}
1607
1608 enc_class Long_OpcSErm_Lo(eRegL dst, immL imm) %{
1609 // Emit primary opcode and set sign-extend bit
1610 // Check for 8-bit immediate, and set sign extend bit in opcode
1611 int con = (int)$imm$$constant; // Throw away top bits
1612 emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary);
1613 // Emit r/m byte with secondary opcode, after primary opcode.
1614 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1615 if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con);
1616 else emit_d32(cbuf,con);
1617 %}
1618
1619 enc_class Long_OpcSErm_Hi(eRegL dst, immL imm) %{
1620 // Emit primary opcode and set sign-extend bit
1621 // Check for 8-bit immediate, and set sign extend bit in opcode
1622 int con = (int)($imm$$constant >> 32); // Throw away bottom bits
1623 emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary);
1624 // Emit r/m byte with tertiary opcode, after primary opcode.
1625 emit_rm(cbuf, 0x3, $tertiary, HIGH_FROM_LOW($dst$$reg));
1626 if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con);
1627 else emit_d32(cbuf,con);
1628 %}
1629
1630 enc_class Lbl (label labl) %{ // JMP, CALL
1631 Label *l = $labl$$label;
1632 emit_d32(cbuf, l ? (l->loc_pos() - (cbuf.code_size()+4)) : 0);
1633 %}
1634
1635 enc_class LblShort (label labl) %{ // JMP, CALL
1636 Label *l = $labl$$label;
1637 int disp = l ? (l->loc_pos() - (cbuf.code_size()+1)) : 0;
1638 assert(-128 <= disp && disp <= 127, "Displacement too large for short jmp");
1639 emit_d8(cbuf, disp);
1640 %}
1641
1642 enc_class OpcSReg (eRegI dst) %{ // BSWAP
1643 emit_cc(cbuf, $secondary, $dst$$reg );
1644 %}
1645
1646 enc_class bswap_long_bytes(eRegL dst) %{ // BSWAP
1647 int destlo = $dst$$reg;
1648 int desthi = HIGH_FROM_LOW(destlo);
1649 // bswap lo
1650 emit_opcode(cbuf, 0x0F);
1651 emit_cc(cbuf, 0xC8, destlo);
1652 // bswap hi
1653 emit_opcode(cbuf, 0x0F);
1654 emit_cc(cbuf, 0xC8, desthi);
1655 // xchg lo and hi
1656 emit_opcode(cbuf, 0x87);
1657 emit_rm(cbuf, 0x3, destlo, desthi);
1658 %}
1659
1660 enc_class RegOpc (eRegI div) %{ // IDIV, IMOD, JMP indirect, ...
1661 emit_rm(cbuf, 0x3, $secondary, $div$$reg );
1662 %}
1663
1664 enc_class Jcc (cmpOp cop, label labl) %{ // JCC
1665 Label *l = $labl$$label;
1666 $$$emit8$primary;
1667 emit_cc(cbuf, $secondary, $cop$$cmpcode);
1668 emit_d32(cbuf, l ? (l->loc_pos() - (cbuf.code_size()+4)) : 0);
1669 %}
1670
1671 enc_class JccShort (cmpOp cop, label labl) %{ // JCC
1672 Label *l = $labl$$label;
1673 emit_cc(cbuf, $primary, $cop$$cmpcode);
1674 int disp = l ? (l->loc_pos() - (cbuf.code_size()+1)) : 0;
1675 assert(-128 <= disp && disp <= 127, "Displacement too large for short jmp");
1676 emit_d8(cbuf, disp);
1677 %}
1678
1679 enc_class enc_cmov(cmpOp cop ) %{ // CMOV
1680 $$$emit8$primary;
1681 emit_cc(cbuf, $secondary, $cop$$cmpcode);
1682 %}
1683
1684 enc_class enc_cmov_d(cmpOp cop, regD src ) %{ // CMOV
1685 int op = 0xDA00 + $cop$$cmpcode + ($src$$reg-1);
1686 emit_d8(cbuf, op >> 8 );
1687 emit_d8(cbuf, op & 255);
1688 %}
1689
1690 // emulate a CMOV with a conditional branch around a MOV
1691 enc_class enc_cmov_branch( cmpOp cop, immI brOffs ) %{ // CMOV
1692 // Invert sense of branch from sense of CMOV
1693 emit_cc( cbuf, 0x70, ($cop$$cmpcode^1) );
1694 emit_d8( cbuf, $brOffs$$constant );
1695 %}
1696
1697 enc_class enc_PartialSubtypeCheck( ) %{
1698 Register Redi = as_Register(EDI_enc); // result register
1699 Register Reax = as_Register(EAX_enc); // super class
1700 Register Recx = as_Register(ECX_enc); // killed
1701 Register Resi = as_Register(ESI_enc); // sub class
1702 Label miss;
1703
1704 MacroAssembler _masm(&cbuf);
1705 __ check_klass_subtype_slow_path(Resi, Reax, Recx, Redi,
1706 NULL, &miss,
1707 /*set_cond_codes:*/ true);
1708 if ($primary) {
1709 __ xorptr(Redi, Redi);
1710 }
1711 __ bind(miss);
1712 %}
1713
1714 enc_class FFree_Float_Stack_All %{ // Free_Float_Stack_All
1715 MacroAssembler masm(&cbuf);
1716 int start = masm.offset();
1717 if (UseSSE >= 2) {
1718 if (VerifyFPU) {
1719 masm.verify_FPU(0, "must be empty in SSE2+ mode");
1720 }
1721 } else {
1722 // External c_calling_convention expects the FPU stack to be 'clean'.
1723 // Compiled code leaves it dirty. Do cleanup now.
1724 masm.empty_FPU_stack();
1725 }
1726 if (sizeof_FFree_Float_Stack_All == -1) {
1727 sizeof_FFree_Float_Stack_All = masm.offset() - start;
1728 } else {
1729 assert(masm.offset() - start == sizeof_FFree_Float_Stack_All, "wrong size");
1730 }
1731 %}
1732
1733 enc_class Verify_FPU_For_Leaf %{
1734 if( VerifyFPU ) {
1735 MacroAssembler masm(&cbuf);
1736 masm.verify_FPU( -3, "Returning from Runtime Leaf call");
1737 }
1738 %}
1739
1740 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime, Java_To_Runtime_Leaf
1741 // This is the instruction starting address for relocation info.
1742 cbuf.set_inst_mark();
1743 $$$emit8$primary;
1744 // CALL directly to the runtime
1745 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.code_end()) - 4),
1746 runtime_call_Relocation::spec(), RELOC_IMM32 );
1747
1748 if (UseSSE >= 2) {
1749 MacroAssembler _masm(&cbuf);
1750 BasicType rt = tf()->return_type();
1751
1752 if ((rt == T_FLOAT || rt == T_DOUBLE) && !return_value_is_used()) {
1753 // A C runtime call where the return value is unused. In SSE2+
1754 // mode the result needs to be removed from the FPU stack. It's
1755 // likely that this function call could be removed by the
1756 // optimizer if the C function is a pure function.
1757 __ ffree(0);
1758 } else if (rt == T_FLOAT) {
1759 __ lea(rsp, Address(rsp, -4));
1760 __ fstp_s(Address(rsp, 0));
1761 __ movflt(xmm0, Address(rsp, 0));
1762 __ lea(rsp, Address(rsp, 4));
1763 } else if (rt == T_DOUBLE) {
1764 __ lea(rsp, Address(rsp, -8));
1765 __ fstp_d(Address(rsp, 0));
1766 __ movdbl(xmm0, Address(rsp, 0));
1767 __ lea(rsp, Address(rsp, 8));
1768 }
1769 }
1770 %}
1771
1772
1773 enc_class pre_call_FPU %{
1774 // If method sets FPU control word restore it here
1775 if( Compile::current()->in_24_bit_fp_mode() ) {
1776 MacroAssembler masm(&cbuf);
1777 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
1778 }
1779 %}
1780
1781 enc_class post_call_FPU %{
1782 // If method sets FPU control word do it here also
1783 if( Compile::current()->in_24_bit_fp_mode() ) {
1784 MacroAssembler masm(&cbuf);
1785 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
1786 }
1787 %}
1788
1789 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL
1790 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
1791 // who we intended to call.
1792 cbuf.set_inst_mark();
1793 $$$emit8$primary;
1794 if ( !_method ) {
1795 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.code_end()) - 4),
1796 runtime_call_Relocation::spec(), RELOC_IMM32 );
1797 } else if(_optimized_virtual) {
1798 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.code_end()) - 4),
1799 opt_virtual_call_Relocation::spec(), RELOC_IMM32 );
1800 } else {
1801 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.code_end()) - 4),
1802 static_call_Relocation::spec(), RELOC_IMM32 );
1803 }
1804 if( _method ) { // Emit stub for static call
1805 emit_java_to_interp(cbuf);
1806 }
1807 %}
1808
1809 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL
1810 // !!!!!
1811 // Generate "Mov EAX,0x00", placeholder instruction to load oop-info
1812 // emit_call_dynamic_prologue( cbuf );
1813 cbuf.set_inst_mark();
1814 emit_opcode(cbuf, 0xB8 + EAX_enc); // mov EAX,-1
1815 emit_d32_reloc(cbuf, (int)Universe::non_oop_word(), oop_Relocation::spec_for_immediate(), RELOC_IMM32);
1816 address virtual_call_oop_addr = cbuf.inst_mark();
1817 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
1818 // who we intended to call.
1819 cbuf.set_inst_mark();
1820 $$$emit8$primary;
1821 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.code_end()) - 4),
1822 virtual_call_Relocation::spec(virtual_call_oop_addr), RELOC_IMM32 );
1823 %}
1824
1825 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL
1826 int disp = in_bytes(methodOopDesc::from_compiled_offset());
1827 assert( -128 <= disp && disp <= 127, "compiled_code_offset isn't small");
1828
1829 // CALL *[EAX+in_bytes(methodOopDesc::from_compiled_code_entry_point_offset())]
1830 cbuf.set_inst_mark();
1831 $$$emit8$primary;
1832 emit_rm(cbuf, 0x01, $secondary, EAX_enc ); // R/M byte
1833 emit_d8(cbuf, disp); // Displacement
1834
1835 %}
1836
1837 enc_class Xor_Reg (eRegI dst) %{
1838 emit_opcode(cbuf, 0x33);
1839 emit_rm(cbuf, 0x3, $dst$$reg, $dst$$reg);
1840 %}
1841
1842 // Following encoding is no longer used, but may be restored if calling
1843 // convention changes significantly.
1844 // Became: Xor_Reg(EBP), Java_To_Runtime( labl )
1845 //
1846 // enc_class Java_Interpreter_Call (label labl) %{ // JAVA INTERPRETER CALL
1847 // // int ic_reg = Matcher::inline_cache_reg();
1848 // // int ic_encode = Matcher::_regEncode[ic_reg];
1849 // // int imo_reg = Matcher::interpreter_method_oop_reg();
1850 // // int imo_encode = Matcher::_regEncode[imo_reg];
1851 //
1852 // // // Interpreter expects method_oop in EBX, currently a callee-saved register,
1853 // // // so we load it immediately before the call
1854 // // emit_opcode(cbuf, 0x8B); // MOV imo_reg,ic_reg # method_oop
1855 // // emit_rm(cbuf, 0x03, imo_encode, ic_encode ); // R/M byte
1856 //
1857 // // xor rbp,ebp
1858 // emit_opcode(cbuf, 0x33);
1859 // emit_rm(cbuf, 0x3, EBP_enc, EBP_enc);
1860 //
1861 // // CALL to interpreter.
1862 // cbuf.set_inst_mark();
1863 // $$$emit8$primary;
1864 // emit_d32_reloc(cbuf, ($labl$$label - (int)(cbuf.code_end()) - 4),
1865 // runtime_call_Relocation::spec(), RELOC_IMM32 );
1866 // %}
1867
1868 enc_class RegOpcImm (eRegI dst, immI8 shift) %{ // SHL, SAR, SHR
1869 $$$emit8$primary;
1870 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1871 $$$emit8$shift$$constant;
1872 %}
1873
1874 enc_class LdImmI (eRegI dst, immI src) %{ // Load Immediate
1875 // Load immediate does not have a zero or sign extended version
1876 // for 8-bit immediates
1877 emit_opcode(cbuf, 0xB8 + $dst$$reg);
1878 $$$emit32$src$$constant;
1879 %}
1880
1881 enc_class LdImmP (eRegI dst, immI src) %{ // Load Immediate
1882 // Load immediate does not have a zero or sign extended version
1883 // for 8-bit immediates
1884 emit_opcode(cbuf, $primary + $dst$$reg);
1885 $$$emit32$src$$constant;
1886 %}
1887
1888 enc_class LdImmL_Lo( eRegL dst, immL src) %{ // Load Immediate
1889 // Load immediate does not have a zero or sign extended version
1890 // for 8-bit immediates
1891 int dst_enc = $dst$$reg;
1892 int src_con = $src$$constant & 0x0FFFFFFFFL;
1893 if (src_con == 0) {
1894 // xor dst, dst
1895 emit_opcode(cbuf, 0x33);
1896 emit_rm(cbuf, 0x3, dst_enc, dst_enc);
1897 } else {
1898 emit_opcode(cbuf, $primary + dst_enc);
1899 emit_d32(cbuf, src_con);
1900 }
1901 %}
1902
1903 enc_class LdImmL_Hi( eRegL dst, immL src) %{ // Load Immediate
1904 // Load immediate does not have a zero or sign extended version
1905 // for 8-bit immediates
1906 int dst_enc = $dst$$reg + 2;
1907 int src_con = ((julong)($src$$constant)) >> 32;
1908 if (src_con == 0) {
1909 // xor dst, dst
1910 emit_opcode(cbuf, 0x33);
1911 emit_rm(cbuf, 0x3, dst_enc, dst_enc);
1912 } else {
1913 emit_opcode(cbuf, $primary + dst_enc);
1914 emit_d32(cbuf, src_con);
1915 }
1916 %}
1917
1918
1919 enc_class LdImmD (immD src) %{ // Load Immediate
1920 if( is_positive_zero_double($src$$constant)) {
1921 // FLDZ
1922 emit_opcode(cbuf,0xD9);
1923 emit_opcode(cbuf,0xEE);
1924 } else if( is_positive_one_double($src$$constant)) {
1925 // FLD1
1926 emit_opcode(cbuf,0xD9);
1927 emit_opcode(cbuf,0xE8);
1928 } else {
1929 emit_opcode(cbuf,0xDD);
1930 emit_rm(cbuf, 0x0, 0x0, 0x5);
1931 emit_double_constant(cbuf, $src$$constant);
1932 }
1933 %}
1934
1935
1936 enc_class LdImmF (immF src) %{ // Load Immediate
1937 if( is_positive_zero_float($src$$constant)) {
1938 emit_opcode(cbuf,0xD9);
1939 emit_opcode(cbuf,0xEE);
1940 } else if( is_positive_one_float($src$$constant)) {
1941 emit_opcode(cbuf,0xD9);
1942 emit_opcode(cbuf,0xE8);
1943 } else {
1944 $$$emit8$primary;
1945 // Load immediate does not have a zero or sign extended version
1946 // for 8-bit immediates
1947 // First load to TOS, then move to dst
1948 emit_rm(cbuf, 0x0, 0x0, 0x5);
1949 emit_float_constant(cbuf, $src$$constant);
1950 }
1951 %}
1952
1953 enc_class LdImmX (regX dst, immXF con) %{ // Load Immediate
1954 emit_rm(cbuf, 0x0, $dst$$reg, 0x5);
1955 emit_float_constant(cbuf, $con$$constant);
1956 %}
1957
1958 enc_class LdImmXD (regXD dst, immXD con) %{ // Load Immediate
1959 emit_rm(cbuf, 0x0, $dst$$reg, 0x5);
1960 emit_double_constant(cbuf, $con$$constant);
1961 %}
1962
1963 enc_class load_conXD (regXD dst, immXD con) %{ // Load double constant
1964 // UseXmmLoadAndClearUpper ? movsd(dst, con) : movlpd(dst, con)
1965 emit_opcode(cbuf, UseXmmLoadAndClearUpper ? 0xF2 : 0x66);
1966 emit_opcode(cbuf, 0x0F);
1967 emit_opcode(cbuf, UseXmmLoadAndClearUpper ? 0x10 : 0x12);
1968 emit_rm(cbuf, 0x0, $dst$$reg, 0x5);
1969 emit_double_constant(cbuf, $con$$constant);
1970 %}
1971
1972 enc_class Opc_MemImm_F(immF src) %{
1973 cbuf.set_inst_mark();
1974 $$$emit8$primary;
1975 emit_rm(cbuf, 0x0, $secondary, 0x5);
1976 emit_float_constant(cbuf, $src$$constant);
1977 %}
1978
1979
1980 enc_class MovI2X_reg(regX dst, eRegI src) %{
1981 emit_opcode(cbuf, 0x66 ); // MOVD dst,src
1982 emit_opcode(cbuf, 0x0F );
1983 emit_opcode(cbuf, 0x6E );
1984 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1985 %}
1986
1987 enc_class MovX2I_reg(eRegI dst, regX src) %{
1988 emit_opcode(cbuf, 0x66 ); // MOVD dst,src
1989 emit_opcode(cbuf, 0x0F );
1990 emit_opcode(cbuf, 0x7E );
1991 emit_rm(cbuf, 0x3, $src$$reg, $dst$$reg);
1992 %}
1993
1994 enc_class MovL2XD_reg(regXD dst, eRegL src, regXD tmp) %{
1995 { // MOVD $dst,$src.lo
1996 emit_opcode(cbuf,0x66);
1997 emit_opcode(cbuf,0x0F);
1998 emit_opcode(cbuf,0x6E);
1999 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2000 }
2001 { // MOVD $tmp,$src.hi
2002 emit_opcode(cbuf,0x66);
2003 emit_opcode(cbuf,0x0F);
2004 emit_opcode(cbuf,0x6E);
2005 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg));
2006 }
2007 { // PUNPCKLDQ $dst,$tmp
2008 emit_opcode(cbuf,0x66);
2009 emit_opcode(cbuf,0x0F);
2010 emit_opcode(cbuf,0x62);
2011 emit_rm(cbuf, 0x3, $dst$$reg, $tmp$$reg);
2012 }
2013 %}
2014
2015 enc_class MovXD2L_reg(eRegL dst, regXD src, regXD tmp) %{
2016 { // MOVD $dst.lo,$src
2017 emit_opcode(cbuf,0x66);
2018 emit_opcode(cbuf,0x0F);
2019 emit_opcode(cbuf,0x7E);
2020 emit_rm(cbuf, 0x3, $src$$reg, $dst$$reg);
2021 }
2022 { // PSHUFLW $tmp,$src,0x4E (01001110b)
2023 emit_opcode(cbuf,0xF2);
2024 emit_opcode(cbuf,0x0F);
2025 emit_opcode(cbuf,0x70);
2026 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg);
2027 emit_d8(cbuf, 0x4E);
2028 }
2029 { // MOVD $dst.hi,$tmp
2030 emit_opcode(cbuf,0x66);
2031 emit_opcode(cbuf,0x0F);
2032 emit_opcode(cbuf,0x7E);
2033 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg));
2034 }
2035 %}
2036
2037
2038 // Encode a reg-reg copy. If it is useless, then empty encoding.
2039 enc_class enc_Copy( eRegI dst, eRegI src ) %{
2040 encode_Copy( cbuf, $dst$$reg, $src$$reg );
2041 %}
2042
2043 enc_class enc_CopyL_Lo( eRegI dst, eRegL src ) %{
2044 encode_Copy( cbuf, $dst$$reg, $src$$reg );
2045 %}
2046
2047 // Encode xmm reg-reg copy. If it is useless, then empty encoding.
2048 enc_class enc_CopyXD( RegXD dst, RegXD src ) %{
2049 encode_CopyXD( cbuf, $dst$$reg, $src$$reg );
2050 %}
2051
2052 enc_class RegReg (eRegI dst, eRegI src) %{ // RegReg(Many)
2053 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2054 %}
2055
2056 enc_class RegReg_Lo(eRegL dst, eRegL src) %{ // RegReg(Many)
2057 $$$emit8$primary;
2058 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2059 %}
2060
2061 enc_class RegReg_Hi(eRegL dst, eRegL src) %{ // RegReg(Many)
2062 $$$emit8$secondary;
2063 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg));
2064 %}
2065
2066 enc_class RegReg_Lo2(eRegL dst, eRegL src) %{ // RegReg(Many)
2067 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2068 %}
2069
2070 enc_class RegReg_Hi2(eRegL dst, eRegL src) %{ // RegReg(Many)
2071 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg));
2072 %}
2073
2074 enc_class RegReg_HiLo( eRegL src, eRegI dst ) %{
2075 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($src$$reg));
2076 %}
2077
2078 enc_class Con32 (immI src) %{ // Con32(storeImmI)
2079 // Output immediate
2080 $$$emit32$src$$constant;
2081 %}
2082
2083 enc_class Con32F_as_bits(immF src) %{ // storeF_imm
2084 // Output Float immediate bits
2085 jfloat jf = $src$$constant;
2086 int jf_as_bits = jint_cast( jf );
2087 emit_d32(cbuf, jf_as_bits);
2088 %}
2089
2090 enc_class Con32XF_as_bits(immXF src) %{ // storeX_imm
2091 // Output Float immediate bits
2092 jfloat jf = $src$$constant;
2093 int jf_as_bits = jint_cast( jf );
2094 emit_d32(cbuf, jf_as_bits);
2095 %}
2096
2097 enc_class Con16 (immI src) %{ // Con16(storeImmI)
2098 // Output immediate
2099 $$$emit16$src$$constant;
2100 %}
2101
2102 enc_class Con_d32(immI src) %{
2103 emit_d32(cbuf,$src$$constant);
2104 %}
2105
2106 enc_class conmemref (eRegP t1) %{ // Con32(storeImmI)
2107 // Output immediate memory reference
2108 emit_rm(cbuf, 0x00, $t1$$reg, 0x05 );
2109 emit_d32(cbuf, 0x00);
2110 %}
2111
2112 enc_class lock_prefix( ) %{
2113 if( os::is_MP() )
2114 emit_opcode(cbuf,0xF0); // [Lock]
2115 %}
2116
2117 // Cmp-xchg long value.
2118 // Note: we need to swap rbx, and rcx before and after the
2119 // cmpxchg8 instruction because the instruction uses
2120 // rcx as the high order word of the new value to store but
2121 // our register encoding uses rbx,.
2122 enc_class enc_cmpxchg8(eSIRegP mem_ptr) %{
2123
2124 // XCHG rbx,ecx
2125 emit_opcode(cbuf,0x87);
2126 emit_opcode(cbuf,0xD9);
2127 // [Lock]
2128 if( os::is_MP() )
2129 emit_opcode(cbuf,0xF0);
2130 // CMPXCHG8 [Eptr]
2131 emit_opcode(cbuf,0x0F);
2132 emit_opcode(cbuf,0xC7);
2133 emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg );
2134 // XCHG rbx,ecx
2135 emit_opcode(cbuf,0x87);
2136 emit_opcode(cbuf,0xD9);
2137 %}
2138
2139 enc_class enc_cmpxchg(eSIRegP mem_ptr) %{
2140 // [Lock]
2141 if( os::is_MP() )
2142 emit_opcode(cbuf,0xF0);
2143
2144 // CMPXCHG [Eptr]
2145 emit_opcode(cbuf,0x0F);
2146 emit_opcode(cbuf,0xB1);
2147 emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg );
2148 %}
2149
2150 enc_class enc_flags_ne_to_boolean( iRegI res ) %{
2151 int res_encoding = $res$$reg;
2152
2153 // MOV res,0
2154 emit_opcode( cbuf, 0xB8 + res_encoding);
2155 emit_d32( cbuf, 0 );
2156 // JNE,s fail
2157 emit_opcode(cbuf,0x75);
2158 emit_d8(cbuf, 5 );
2159 // MOV res,1
2160 emit_opcode( cbuf, 0xB8 + res_encoding);
2161 emit_d32( cbuf, 1 );
2162 // fail:
2163 %}
2164
2165 enc_class set_instruction_start( ) %{
2166 cbuf.set_inst_mark(); // Mark start of opcode for reloc info in mem operand
2167 %}
2168
2169 enc_class RegMem (eRegI ereg, memory mem) %{ // emit_reg_mem
2170 int reg_encoding = $ereg$$reg;
2171 int base = $mem$$base;
2172 int index = $mem$$index;
2173 int scale = $mem$$scale;
2174 int displace = $mem$$disp;
2175 bool disp_is_oop = $mem->disp_is_oop();
2176 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2177 %}
2178
2179 enc_class RegMem_Hi(eRegL ereg, memory mem) %{ // emit_reg_mem
2180 int reg_encoding = HIGH_FROM_LOW($ereg$$reg); // Hi register of pair, computed from lo
2181 int base = $mem$$base;
2182 int index = $mem$$index;
2183 int scale = $mem$$scale;
2184 int displace = $mem$$disp + 4; // Offset is 4 further in memory
2185 assert( !$mem->disp_is_oop(), "Cannot add 4 to oop" );
2186 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, false/*disp_is_oop*/);
2187 %}
2188
2189 enc_class move_long_small_shift( eRegL dst, immI_1_31 cnt ) %{
2190 int r1, r2;
2191 if( $tertiary == 0xA4 ) { r1 = $dst$$reg; r2 = HIGH_FROM_LOW($dst$$reg); }
2192 else { r2 = $dst$$reg; r1 = HIGH_FROM_LOW($dst$$reg); }
2193 emit_opcode(cbuf,0x0F);
2194 emit_opcode(cbuf,$tertiary);
2195 emit_rm(cbuf, 0x3, r1, r2);
2196 emit_d8(cbuf,$cnt$$constant);
2197 emit_d8(cbuf,$primary);
2198 emit_rm(cbuf, 0x3, $secondary, r1);
2199 emit_d8(cbuf,$cnt$$constant);
2200 %}
2201
2202 enc_class move_long_big_shift_sign( eRegL dst, immI_32_63 cnt ) %{
2203 emit_opcode( cbuf, 0x8B ); // Move
2204 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg));
2205 emit_d8(cbuf,$primary);
2206 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
2207 emit_d8(cbuf,$cnt$$constant-32);
2208 emit_d8(cbuf,$primary);
2209 emit_rm(cbuf, 0x3, $secondary, HIGH_FROM_LOW($dst$$reg));
2210 emit_d8(cbuf,31);
2211 %}
2212
2213 enc_class move_long_big_shift_clr( eRegL dst, immI_32_63 cnt ) %{
2214 int r1, r2;
2215 if( $secondary == 0x5 ) { r1 = $dst$$reg; r2 = HIGH_FROM_LOW($dst$$reg); }
2216 else { r2 = $dst$$reg; r1 = HIGH_FROM_LOW($dst$$reg); }
2217
2218 emit_opcode( cbuf, 0x8B ); // Move r1,r2
2219 emit_rm(cbuf, 0x3, r1, r2);
2220 if( $cnt$$constant > 32 ) { // Shift, if not by zero
2221 emit_opcode(cbuf,$primary);
2222 emit_rm(cbuf, 0x3, $secondary, r1);
2223 emit_d8(cbuf,$cnt$$constant-32);
2224 }
2225 emit_opcode(cbuf,0x33); // XOR r2,r2
2226 emit_rm(cbuf, 0x3, r2, r2);
2227 %}
2228
2229 // Clone of RegMem but accepts an extra parameter to access each
2230 // half of a double in memory; it never needs relocation info.
2231 enc_class Mov_MemD_half_to_Reg (immI opcode, memory mem, immI disp_for_half, eRegI rm_reg) %{
2232 emit_opcode(cbuf,$opcode$$constant);
2233 int reg_encoding = $rm_reg$$reg;
2234 int base = $mem$$base;
2235 int index = $mem$$index;
2236 int scale = $mem$$scale;
2237 int displace = $mem$$disp + $disp_for_half$$constant;
2238 bool disp_is_oop = false;
2239 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2240 %}
2241
2242 // !!!!! Special Custom Code used by MemMove, and stack access instructions !!!!!
2243 //
2244 // Clone of RegMem except the RM-byte's reg/opcode field is an ADLC-time constant
2245 // and it never needs relocation information.
2246 // Frequently used to move data between FPU's Stack Top and memory.
2247 enc_class RMopc_Mem_no_oop (immI rm_opcode, memory mem) %{
2248 int rm_byte_opcode = $rm_opcode$$constant;
2249 int base = $mem$$base;
2250 int index = $mem$$index;
2251 int scale = $mem$$scale;
2252 int displace = $mem$$disp;
2253 assert( !$mem->disp_is_oop(), "No oops here because no relo info allowed" );
2254 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, false);
2255 %}
2256
2257 enc_class RMopc_Mem (immI rm_opcode, memory mem) %{
2258 int rm_byte_opcode = $rm_opcode$$constant;
2259 int base = $mem$$base;
2260 int index = $mem$$index;
2261 int scale = $mem$$scale;
2262 int displace = $mem$$disp;
2263 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
2264 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_is_oop);
2265 %}
2266
2267 enc_class RegLea (eRegI dst, eRegI src0, immI src1 ) %{ // emit_reg_lea
2268 int reg_encoding = $dst$$reg;
2269 int base = $src0$$reg; // 0xFFFFFFFF indicates no base
2270 int index = 0x04; // 0x04 indicates no index
2271 int scale = 0x00; // 0x00 indicates no scale
2272 int displace = $src1$$constant; // 0x00 indicates no displacement
2273 bool disp_is_oop = false;
2274 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2275 %}
2276
2277 enc_class min_enc (eRegI dst, eRegI src) %{ // MIN
2278 // Compare dst,src
2279 emit_opcode(cbuf,0x3B);
2280 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2281 // jmp dst < src around move
2282 emit_opcode(cbuf,0x7C);
2283 emit_d8(cbuf,2);
2284 // move dst,src
2285 emit_opcode(cbuf,0x8B);
2286 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2287 %}
2288
2289 enc_class max_enc (eRegI dst, eRegI src) %{ // MAX
2290 // Compare dst,src
2291 emit_opcode(cbuf,0x3B);
2292 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2293 // jmp dst > src around move
2294 emit_opcode(cbuf,0x7F);
2295 emit_d8(cbuf,2);
2296 // move dst,src
2297 emit_opcode(cbuf,0x8B);
2298 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2299 %}
2300
2301 enc_class enc_FP_store(memory mem, regD src) %{
2302 // If src is FPR1, we can just FST to store it.
2303 // Else we need to FLD it to FPR1, then FSTP to store/pop it.
2304 int reg_encoding = 0x2; // Just store
2305 int base = $mem$$base;
2306 int index = $mem$$index;
2307 int scale = $mem$$scale;
2308 int displace = $mem$$disp;
2309 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
2310 if( $src$$reg != FPR1L_enc ) {
2311 reg_encoding = 0x3; // Store & pop
2312 emit_opcode( cbuf, 0xD9 ); // FLD (i.e., push it)
2313 emit_d8( cbuf, 0xC0-1+$src$$reg );
2314 }
2315 cbuf.set_inst_mark(); // Mark start of opcode for reloc info in mem operand
2316 emit_opcode(cbuf,$primary);
2317 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2318 %}
2319
2320 enc_class neg_reg(eRegI dst) %{
2321 // NEG $dst
2322 emit_opcode(cbuf,0xF7);
2323 emit_rm(cbuf, 0x3, 0x03, $dst$$reg );
2324 %}
2325
2326 enc_class setLT_reg(eCXRegI dst) %{
2327 // SETLT $dst
2328 emit_opcode(cbuf,0x0F);
2329 emit_opcode(cbuf,0x9C);
2330 emit_rm( cbuf, 0x3, 0x4, $dst$$reg );
2331 %}
2332
2333 enc_class enc_cmpLTP(ncxRegI p, ncxRegI q, ncxRegI y, eCXRegI tmp) %{ // cadd_cmpLT
2334 int tmpReg = $tmp$$reg;
2335
2336 // SUB $p,$q
2337 emit_opcode(cbuf,0x2B);
2338 emit_rm(cbuf, 0x3, $p$$reg, $q$$reg);
2339 // SBB $tmp,$tmp
2340 emit_opcode(cbuf,0x1B);
2341 emit_rm(cbuf, 0x3, tmpReg, tmpReg);
2342 // AND $tmp,$y
2343 emit_opcode(cbuf,0x23);
2344 emit_rm(cbuf, 0x3, tmpReg, $y$$reg);
2345 // ADD $p,$tmp
2346 emit_opcode(cbuf,0x03);
2347 emit_rm(cbuf, 0x3, $p$$reg, tmpReg);
2348 %}
2349
2350 enc_class enc_cmpLTP_mem(eRegI p, eRegI q, memory mem, eCXRegI tmp) %{ // cadd_cmpLT
2351 int tmpReg = $tmp$$reg;
2352
2353 // SUB $p,$q
2354 emit_opcode(cbuf,0x2B);
2355 emit_rm(cbuf, 0x3, $p$$reg, $q$$reg);
2356 // SBB $tmp,$tmp
2357 emit_opcode(cbuf,0x1B);
2358 emit_rm(cbuf, 0x3, tmpReg, tmpReg);
2359 // AND $tmp,$y
2360 cbuf.set_inst_mark(); // Mark start of opcode for reloc info in mem operand
2361 emit_opcode(cbuf,0x23);
2362 int reg_encoding = tmpReg;
2363 int base = $mem$$base;
2364 int index = $mem$$index;
2365 int scale = $mem$$scale;
2366 int displace = $mem$$disp;
2367 bool disp_is_oop = $mem->disp_is_oop();
2368 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2369 // ADD $p,$tmp
2370 emit_opcode(cbuf,0x03);
2371 emit_rm(cbuf, 0x3, $p$$reg, tmpReg);
2372 %}
2373
2374 enc_class shift_left_long( eRegL dst, eCXRegI shift ) %{
2375 // TEST shift,32
2376 emit_opcode(cbuf,0xF7);
2377 emit_rm(cbuf, 0x3, 0, ECX_enc);
2378 emit_d32(cbuf,0x20);
2379 // JEQ,s small
2380 emit_opcode(cbuf, 0x74);
2381 emit_d8(cbuf, 0x04);
2382 // MOV $dst.hi,$dst.lo
2383 emit_opcode( cbuf, 0x8B );
2384 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg );
2385 // CLR $dst.lo
2386 emit_opcode(cbuf, 0x33);
2387 emit_rm(cbuf, 0x3, $dst$$reg, $dst$$reg);
2388 // small:
2389 // SHLD $dst.hi,$dst.lo,$shift
2390 emit_opcode(cbuf,0x0F);
2391 emit_opcode(cbuf,0xA5);
2392 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg));
2393 // SHL $dst.lo,$shift"
2394 emit_opcode(cbuf,0xD3);
2395 emit_rm(cbuf, 0x3, 0x4, $dst$$reg );
2396 %}
2397
2398 enc_class shift_right_long( eRegL dst, eCXRegI shift ) %{
2399 // TEST shift,32
2400 emit_opcode(cbuf,0xF7);
2401 emit_rm(cbuf, 0x3, 0, ECX_enc);
2402 emit_d32(cbuf,0x20);
2403 // JEQ,s small
2404 emit_opcode(cbuf, 0x74);
2405 emit_d8(cbuf, 0x04);
2406 // MOV $dst.lo,$dst.hi
2407 emit_opcode( cbuf, 0x8B );
2408 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) );
2409 // CLR $dst.hi
2410 emit_opcode(cbuf, 0x33);
2411 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($dst$$reg));
2412 // small:
2413 // SHRD $dst.lo,$dst.hi,$shift
2414 emit_opcode(cbuf,0x0F);
2415 emit_opcode(cbuf,0xAD);
2416 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg);
2417 // SHR $dst.hi,$shift"
2418 emit_opcode(cbuf,0xD3);
2419 emit_rm(cbuf, 0x3, 0x5, HIGH_FROM_LOW($dst$$reg) );
2420 %}
2421
2422 enc_class shift_right_arith_long( eRegL dst, eCXRegI shift ) %{
2423 // TEST shift,32
2424 emit_opcode(cbuf,0xF7);
2425 emit_rm(cbuf, 0x3, 0, ECX_enc);
2426 emit_d32(cbuf,0x20);
2427 // JEQ,s small
2428 emit_opcode(cbuf, 0x74);
2429 emit_d8(cbuf, 0x05);
2430 // MOV $dst.lo,$dst.hi
2431 emit_opcode( cbuf, 0x8B );
2432 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) );
2433 // SAR $dst.hi,31
2434 emit_opcode(cbuf, 0xC1);
2435 emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW($dst$$reg) );
2436 emit_d8(cbuf, 0x1F );
2437 // small:
2438 // SHRD $dst.lo,$dst.hi,$shift
2439 emit_opcode(cbuf,0x0F);
2440 emit_opcode(cbuf,0xAD);
2441 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg);
2442 // SAR $dst.hi,$shift"
2443 emit_opcode(cbuf,0xD3);
2444 emit_rm(cbuf, 0x3, 0x7, HIGH_FROM_LOW($dst$$reg) );
2445 %}
2446
2447
2448 // ----------------- Encodings for floating point unit -----------------
2449 // May leave result in FPU-TOS or FPU reg depending on opcodes
2450 enc_class OpcReg_F (regF src) %{ // FMUL, FDIV
2451 $$$emit8$primary;
2452 emit_rm(cbuf, 0x3, $secondary, $src$$reg );
2453 %}
2454
2455 // Pop argument in FPR0 with FSTP ST(0)
2456 enc_class PopFPU() %{
2457 emit_opcode( cbuf, 0xDD );
2458 emit_d8( cbuf, 0xD8 );
2459 %}
2460
2461 // !!!!! equivalent to Pop_Reg_F
2462 enc_class Pop_Reg_D( regD dst ) %{
2463 emit_opcode( cbuf, 0xDD ); // FSTP ST(i)
2464 emit_d8( cbuf, 0xD8+$dst$$reg );
2465 %}
2466
2467 enc_class Push_Reg_D( regD dst ) %{
2468 emit_opcode( cbuf, 0xD9 );
2469 emit_d8( cbuf, 0xC0-1+$dst$$reg ); // FLD ST(i-1)
2470 %}
2471
2472 enc_class strictfp_bias1( regD dst ) %{
2473 emit_opcode( cbuf, 0xDB ); // FLD m80real
2474 emit_opcode( cbuf, 0x2D );
2475 emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias1() );
2476 emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0
2477 emit_opcode( cbuf, 0xC8+$dst$$reg );
2478 %}
2479
2480 enc_class strictfp_bias2( regD dst ) %{
2481 emit_opcode( cbuf, 0xDB ); // FLD m80real
2482 emit_opcode( cbuf, 0x2D );
2483 emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias2() );
2484 emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0
2485 emit_opcode( cbuf, 0xC8+$dst$$reg );
2486 %}
2487
2488 // Special case for moving an integer register to a stack slot.
2489 enc_class OpcPRegSS( stackSlotI dst, eRegI src ) %{ // RegSS
2490 store_to_stackslot( cbuf, $primary, $src$$reg, $dst$$disp );
2491 %}
2492
2493 // Special case for moving a register to a stack slot.
2494 enc_class RegSS( stackSlotI dst, eRegI src ) %{ // RegSS
2495 // Opcode already emitted
2496 emit_rm( cbuf, 0x02, $src$$reg, ESP_enc ); // R/M byte
2497 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
2498 emit_d32(cbuf, $dst$$disp); // Displacement
2499 %}
2500
2501 // Push the integer in stackSlot 'src' onto FP-stack
2502 enc_class Push_Mem_I( memory src ) %{ // FILD [ESP+src]
2503 store_to_stackslot( cbuf, $primary, $secondary, $src$$disp );
2504 %}
2505
2506 // Push the float in stackSlot 'src' onto FP-stack
2507 enc_class Push_Mem_F( memory src ) %{ // FLD_S [ESP+src]
2508 store_to_stackslot( cbuf, 0xD9, 0x00, $src$$disp );
2509 %}
2510
2511 // Push the double in stackSlot 'src' onto FP-stack
2512 enc_class Push_Mem_D( memory src ) %{ // FLD_D [ESP+src]
2513 store_to_stackslot( cbuf, 0xDD, 0x00, $src$$disp );
2514 %}
2515
2516 // Push FPU's TOS float to a stack-slot, and pop FPU-stack
2517 enc_class Pop_Mem_F( stackSlotF dst ) %{ // FSTP_S [ESP+dst]
2518 store_to_stackslot( cbuf, 0xD9, 0x03, $dst$$disp );
2519 %}
2520
2521 // Same as Pop_Mem_F except for opcode
2522 // Push FPU's TOS double to a stack-slot, and pop FPU-stack
2523 enc_class Pop_Mem_D( stackSlotD dst ) %{ // FSTP_D [ESP+dst]
2524 store_to_stackslot( cbuf, 0xDD, 0x03, $dst$$disp );
2525 %}
2526
2527 enc_class Pop_Reg_F( regF dst ) %{
2528 emit_opcode( cbuf, 0xDD ); // FSTP ST(i)
2529 emit_d8( cbuf, 0xD8+$dst$$reg );
2530 %}
2531
2532 enc_class Push_Reg_F( regF dst ) %{
2533 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2534 emit_d8( cbuf, 0xC0-1+$dst$$reg );
2535 %}
2536
2537 // Push FPU's float to a stack-slot, and pop FPU-stack
2538 enc_class Pop_Mem_Reg_F( stackSlotF dst, regF src ) %{
2539 int pop = 0x02;
2540 if ($src$$reg != FPR1L_enc) {
2541 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2542 emit_d8( cbuf, 0xC0-1+$src$$reg );
2543 pop = 0x03;
2544 }
2545 store_to_stackslot( cbuf, 0xD9, pop, $dst$$disp ); // FST<P>_S [ESP+dst]
2546 %}
2547
2548 // Push FPU's double to a stack-slot, and pop FPU-stack
2549 enc_class Pop_Mem_Reg_D( stackSlotD dst, regD src ) %{
2550 int pop = 0x02;
2551 if ($src$$reg != FPR1L_enc) {
2552 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2553 emit_d8( cbuf, 0xC0-1+$src$$reg );
2554 pop = 0x03;
2555 }
2556 store_to_stackslot( cbuf, 0xDD, pop, $dst$$disp ); // FST<P>_D [ESP+dst]
2557 %}
2558
2559 // Push FPU's double to a FPU-stack-slot, and pop FPU-stack
2560 enc_class Pop_Reg_Reg_D( regD dst, regF src ) %{
2561 int pop = 0xD0 - 1; // -1 since we skip FLD
2562 if ($src$$reg != FPR1L_enc) {
2563 emit_opcode( cbuf, 0xD9 ); // FLD ST(src-1)
2564 emit_d8( cbuf, 0xC0-1+$src$$reg );
2565 pop = 0xD8;
2566 }
2567 emit_opcode( cbuf, 0xDD );
2568 emit_d8( cbuf, pop+$dst$$reg ); // FST<P> ST(i)
2569 %}
2570
2571
2572 enc_class Mul_Add_F( regF dst, regF src, regF src1, regF src2 ) %{
2573 MacroAssembler masm(&cbuf);
2574 masm.fld_s( $src1$$reg-1); // nothing at TOS, load TOS from src1.reg
2575 masm.fmul( $src2$$reg+0); // value at TOS
2576 masm.fadd( $src$$reg+0); // value at TOS
2577 masm.fstp_d( $dst$$reg+0); // value at TOS, popped off after store
2578 %}
2579
2580
2581 enc_class Push_Reg_Mod_D( regD dst, regD src) %{
2582 // load dst in FPR0
2583 emit_opcode( cbuf, 0xD9 );
2584 emit_d8( cbuf, 0xC0-1+$dst$$reg );
2585 if ($src$$reg != FPR1L_enc) {
2586 // fincstp
2587 emit_opcode (cbuf, 0xD9);
2588 emit_opcode (cbuf, 0xF7);
2589 // swap src with FPR1:
2590 // FXCH FPR1 with src
2591 emit_opcode(cbuf, 0xD9);
2592 emit_d8(cbuf, 0xC8-1+$src$$reg );
2593 // fdecstp
2594 emit_opcode (cbuf, 0xD9);
2595 emit_opcode (cbuf, 0xF6);
2596 }
2597 %}
2598
2599 enc_class Push_ModD_encoding( regXD src0, regXD src1) %{
2600 // Allocate a word
2601 emit_opcode(cbuf,0x83); // SUB ESP,8
2602 emit_opcode(cbuf,0xEC);
2603 emit_d8(cbuf,0x08);
2604
2605 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], src1
2606 emit_opcode (cbuf, 0x0F );
2607 emit_opcode (cbuf, 0x11 );
2608 encode_RegMem(cbuf, $src1$$reg, ESP_enc, 0x4, 0, 0, false);
2609
2610 emit_opcode(cbuf,0xDD ); // FLD_D [ESP]
2611 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
2612
2613 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], src0
2614 emit_opcode (cbuf, 0x0F );
2615 emit_opcode (cbuf, 0x11 );
2616 encode_RegMem(cbuf, $src0$$reg, ESP_enc, 0x4, 0, 0, false);
2617
2618 emit_opcode(cbuf,0xDD ); // FLD_D [ESP]
2619 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
2620
2621 %}
2622
2623 enc_class Push_ModX_encoding( regX src0, regX src1) %{
2624 // Allocate a word
2625 emit_opcode(cbuf,0x83); // SUB ESP,4
2626 emit_opcode(cbuf,0xEC);
2627 emit_d8(cbuf,0x04);
2628
2629 emit_opcode (cbuf, 0xF3 ); // MOVSS [ESP], src1
2630 emit_opcode (cbuf, 0x0F );
2631 emit_opcode (cbuf, 0x11 );
2632 encode_RegMem(cbuf, $src1$$reg, ESP_enc, 0x4, 0, 0, false);
2633
2634 emit_opcode(cbuf,0xD9 ); // FLD [ESP]
2635 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
2636
2637 emit_opcode (cbuf, 0xF3 ); // MOVSS [ESP], src0
2638 emit_opcode (cbuf, 0x0F );
2639 emit_opcode (cbuf, 0x11 );
2640 encode_RegMem(cbuf, $src0$$reg, ESP_enc, 0x4, 0, 0, false);
2641
2642 emit_opcode(cbuf,0xD9 ); // FLD [ESP]
2643 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
2644
2645 %}
2646
2647 enc_class Push_ResultXD(regXD dst) %{
2648 store_to_stackslot( cbuf, 0xDD, 0x03, 0 ); //FSTP [ESP]
2649
2650 // UseXmmLoadAndClearUpper ? movsd dst,[esp] : movlpd dst,[esp]
2651 emit_opcode (cbuf, UseXmmLoadAndClearUpper ? 0xF2 : 0x66);
2652 emit_opcode (cbuf, 0x0F );
2653 emit_opcode (cbuf, UseXmmLoadAndClearUpper ? 0x10 : 0x12);
2654 encode_RegMem(cbuf, $dst$$reg, ESP_enc, 0x4, 0, 0, false);
2655
2656 emit_opcode(cbuf,0x83); // ADD ESP,8
2657 emit_opcode(cbuf,0xC4);
2658 emit_d8(cbuf,0x08);
2659 %}
2660
2661 enc_class Push_ResultX(regX dst, immI d8) %{
2662 store_to_stackslot( cbuf, 0xD9, 0x03, 0 ); //FSTP_S [ESP]
2663
2664 emit_opcode (cbuf, 0xF3 ); // MOVSS dst(xmm), [ESP]
2665 emit_opcode (cbuf, 0x0F );
2666 emit_opcode (cbuf, 0x10 );
2667 encode_RegMem(cbuf, $dst$$reg, ESP_enc, 0x4, 0, 0, false);
2668
2669 emit_opcode(cbuf,0x83); // ADD ESP,d8 (4 or 8)
2670 emit_opcode(cbuf,0xC4);
2671 emit_d8(cbuf,$d8$$constant);
2672 %}
2673
2674 enc_class Push_SrcXD(regXD src) %{
2675 // Allocate a word
2676 emit_opcode(cbuf,0x83); // SUB ESP,8
2677 emit_opcode(cbuf,0xEC);
2678 emit_d8(cbuf,0x08);
2679
2680 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], src
2681 emit_opcode (cbuf, 0x0F );
2682 emit_opcode (cbuf, 0x11 );
2683 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false);
2684
2685 emit_opcode(cbuf,0xDD ); // FLD_D [ESP]
2686 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
2687 %}
2688
2689 enc_class push_stack_temp_qword() %{
2690 emit_opcode(cbuf,0x83); // SUB ESP,8
2691 emit_opcode(cbuf,0xEC);
2692 emit_d8 (cbuf,0x08);
2693 %}
2694
2695 enc_class pop_stack_temp_qword() %{
2696 emit_opcode(cbuf,0x83); // ADD ESP,8
2697 emit_opcode(cbuf,0xC4);
2698 emit_d8 (cbuf,0x08);
2699 %}
2700
2701 enc_class push_xmm_to_fpr1( regXD xmm_src ) %{
2702 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], xmm_src
2703 emit_opcode (cbuf, 0x0F );
2704 emit_opcode (cbuf, 0x11 );
2705 encode_RegMem(cbuf, $xmm_src$$reg, ESP_enc, 0x4, 0, 0, false);
2706
2707 emit_opcode(cbuf,0xDD ); // FLD_D [ESP]
2708 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
2709 %}
2710
2711 // Compute X^Y using Intel's fast hardware instructions, if possible.
2712 // Otherwise return a NaN.
2713 enc_class pow_exp_core_encoding %{
2714 // FPR1 holds Y*ln2(X). Compute FPR1 = 2^(Y*ln2(X))
2715 emit_opcode(cbuf,0xD9); emit_opcode(cbuf,0xC0); // fdup = fld st(0) Q Q
2716 emit_opcode(cbuf,0xD9); emit_opcode(cbuf,0xFC); // frndint int(Q) Q
2717 emit_opcode(cbuf,0xDC); emit_opcode(cbuf,0xE9); // fsub st(1) -= st(0); int(Q) frac(Q)
2718 emit_opcode(cbuf,0xDB); // FISTP [ESP] frac(Q)
2719 emit_opcode(cbuf,0x1C);
2720 emit_d8(cbuf,0x24);
2721 emit_opcode(cbuf,0xD9); emit_opcode(cbuf,0xF0); // f2xm1 2^frac(Q)-1
2722 emit_opcode(cbuf,0xD9); emit_opcode(cbuf,0xE8); // fld1 1 2^frac(Q)-1
2723 emit_opcode(cbuf,0xDE); emit_opcode(cbuf,0xC1); // faddp 2^frac(Q)
2724 emit_opcode(cbuf,0x8B); // mov rax,[esp+0]=int(Q)
2725 encode_RegMem(cbuf, EAX_enc, ESP_enc, 0x4, 0, 0, false);
2726 emit_opcode(cbuf,0xC7); // mov rcx,0xFFFFF800 - overflow mask
2727 emit_rm(cbuf, 0x3, 0x0, ECX_enc);
2728 emit_d32(cbuf,0xFFFFF800);
2729 emit_opcode(cbuf,0x81); // add rax,1023 - the double exponent bias
2730 emit_rm(cbuf, 0x3, 0x0, EAX_enc);
2731 emit_d32(cbuf,1023);
2732 emit_opcode(cbuf,0x8B); // mov rbx,eax
2733 emit_rm(cbuf, 0x3, EBX_enc, EAX_enc);
2734 emit_opcode(cbuf,0xC1); // shl rax,20 - Slide to exponent position
2735 emit_rm(cbuf,0x3,0x4,EAX_enc);
2736 emit_d8(cbuf,20);
2737 emit_opcode(cbuf,0x85); // test rbx,ecx - check for overflow
2738 emit_rm(cbuf, 0x3, EBX_enc, ECX_enc);
2739 emit_opcode(cbuf,0x0F); emit_opcode(cbuf,0x45); // CMOVne rax,ecx - overflow; stuff NAN into EAX
2740 emit_rm(cbuf, 0x3, EAX_enc, ECX_enc);
2741 emit_opcode(cbuf,0x89); // mov [esp+4],eax - Store as part of double word
2742 encode_RegMem(cbuf, EAX_enc, ESP_enc, 0x4, 0, 4, false);
2743 emit_opcode(cbuf,0xC7); // mov [esp+0],0 - [ESP] = (double)(1<<int(Q)) = 2^int(Q)
2744 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
2745 emit_d32(cbuf,0);
2746 emit_opcode(cbuf,0xDC); // fmul dword st(0),[esp+0]; FPR1 = 2^int(Q)*2^frac(Q) = 2^Q
2747 encode_RegMem(cbuf, 0x1, ESP_enc, 0x4, 0, 0, false);
2748 %}
2749
2750 // enc_class Pop_Reg_Mod_D( regD dst, regD src)
2751 // was replaced by Push_Result_Mod_D followed by Pop_Reg_X() or Pop_Mem_X()
2752
2753 enc_class Push_Result_Mod_D( regD src) %{
2754 if ($src$$reg != FPR1L_enc) {
2755 // fincstp
2756 emit_opcode (cbuf, 0xD9);
2757 emit_opcode (cbuf, 0xF7);
2758 // FXCH FPR1 with src
2759 emit_opcode(cbuf, 0xD9);
2760 emit_d8(cbuf, 0xC8-1+$src$$reg );
2761 // fdecstp
2762 emit_opcode (cbuf, 0xD9);
2763 emit_opcode (cbuf, 0xF6);
2764 }
2765 // // following asm replaced with Pop_Reg_F or Pop_Mem_F
2766 // // FSTP FPR$dst$$reg
2767 // emit_opcode( cbuf, 0xDD );
2768 // emit_d8( cbuf, 0xD8+$dst$$reg );
2769 %}
2770
2771 enc_class fnstsw_sahf_skip_parity() %{
2772 // fnstsw ax
2773 emit_opcode( cbuf, 0xDF );
2774 emit_opcode( cbuf, 0xE0 );
2775 // sahf
2776 emit_opcode( cbuf, 0x9E );
2777 // jnp ::skip
2778 emit_opcode( cbuf, 0x7B );
2779 emit_opcode( cbuf, 0x05 );
2780 %}
2781
2782 enc_class emitModD() %{
2783 // fprem must be iterative
2784 // :: loop
2785 // fprem
2786 emit_opcode( cbuf, 0xD9 );
2787 emit_opcode( cbuf, 0xF8 );
2788 // wait
2789 emit_opcode( cbuf, 0x9b );
2790 // fnstsw ax
2791 emit_opcode( cbuf, 0xDF );
2792 emit_opcode( cbuf, 0xE0 );
2793 // sahf
2794 emit_opcode( cbuf, 0x9E );
2795 // jp ::loop
2796 emit_opcode( cbuf, 0x0F );
2797 emit_opcode( cbuf, 0x8A );
2798 emit_opcode( cbuf, 0xF4 );
2799 emit_opcode( cbuf, 0xFF );
2800 emit_opcode( cbuf, 0xFF );
2801 emit_opcode( cbuf, 0xFF );
2802 %}
2803
2804 enc_class fpu_flags() %{
2805 // fnstsw_ax
2806 emit_opcode( cbuf, 0xDF);
2807 emit_opcode( cbuf, 0xE0);
2808 // test ax,0x0400
2809 emit_opcode( cbuf, 0x66 ); // operand-size prefix for 16-bit immediate
2810 emit_opcode( cbuf, 0xA9 );
2811 emit_d16 ( cbuf, 0x0400 );
2812 // // // This sequence works, but stalls for 12-16 cycles on PPro
2813 // // test rax,0x0400
2814 // emit_opcode( cbuf, 0xA9 );
2815 // emit_d32 ( cbuf, 0x00000400 );
2816 //
2817 // jz exit (no unordered comparison)
2818 emit_opcode( cbuf, 0x74 );
2819 emit_d8 ( cbuf, 0x02 );
2820 // mov ah,1 - treat as LT case (set carry flag)
2821 emit_opcode( cbuf, 0xB4 );
2822 emit_d8 ( cbuf, 0x01 );
2823 // sahf
2824 emit_opcode( cbuf, 0x9E);
2825 %}
2826
2827 enc_class cmpF_P6_fixup() %{
2828 // Fixup the integer flags in case comparison involved a NaN
2829 //
2830 // JNP exit (no unordered comparison, P-flag is set by NaN)
2831 emit_opcode( cbuf, 0x7B );
2832 emit_d8 ( cbuf, 0x03 );
2833 // MOV AH,1 - treat as LT case (set carry flag)
2834 emit_opcode( cbuf, 0xB4 );
2835 emit_d8 ( cbuf, 0x01 );
2836 // SAHF
2837 emit_opcode( cbuf, 0x9E);
2838 // NOP // target for branch to avoid branch to branch
2839 emit_opcode( cbuf, 0x90);
2840 %}
2841
2842 // fnstsw_ax();
2843 // sahf();
2844 // movl(dst, nan_result);
2845 // jcc(Assembler::parity, exit);
2846 // movl(dst, less_result);
2847 // jcc(Assembler::below, exit);
2848 // movl(dst, equal_result);
2849 // jcc(Assembler::equal, exit);
2850 // movl(dst, greater_result);
2851
2852 // less_result = 1;
2853 // greater_result = -1;
2854 // equal_result = 0;
2855 // nan_result = -1;
2856
2857 enc_class CmpF_Result(eRegI dst) %{
2858 // fnstsw_ax();
2859 emit_opcode( cbuf, 0xDF);
2860 emit_opcode( cbuf, 0xE0);
2861 // sahf
2862 emit_opcode( cbuf, 0x9E);
2863 // movl(dst, nan_result);
2864 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2865 emit_d32( cbuf, -1 );
2866 // jcc(Assembler::parity, exit);
2867 emit_opcode( cbuf, 0x7A );
2868 emit_d8 ( cbuf, 0x13 );
2869 // movl(dst, less_result);
2870 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2871 emit_d32( cbuf, -1 );
2872 // jcc(Assembler::below, exit);
2873 emit_opcode( cbuf, 0x72 );
2874 emit_d8 ( cbuf, 0x0C );
2875 // movl(dst, equal_result);
2876 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2877 emit_d32( cbuf, 0 );
2878 // jcc(Assembler::equal, exit);
2879 emit_opcode( cbuf, 0x74 );
2880 emit_d8 ( cbuf, 0x05 );
2881 // movl(dst, greater_result);
2882 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2883 emit_d32( cbuf, 1 );
2884 %}
2885
2886
2887 // XMM version of CmpF_Result. Because the XMM compare
2888 // instructions set the EFLAGS directly. It becomes simpler than
2889 // the float version above.
2890 enc_class CmpX_Result(eRegI dst) %{
2891 MacroAssembler _masm(&cbuf);
2892 Label nan, inc, done;
2893
2894 __ jccb(Assembler::parity, nan);
2895 __ jccb(Assembler::equal, done);
2896 __ jccb(Assembler::above, inc);
2897 __ bind(nan);
2898 __ decrement(as_Register($dst$$reg)); // NO L qqq
2899 __ jmpb(done);
2900 __ bind(inc);
2901 __ increment(as_Register($dst$$reg)); // NO L qqq
2902 __ bind(done);
2903 %}
2904
2905 // Compare the longs and set flags
2906 // BROKEN! Do Not use as-is
2907 enc_class cmpl_test( eRegL src1, eRegL src2 ) %{
2908 // CMP $src1.hi,$src2.hi
2909 emit_opcode( cbuf, 0x3B );
2910 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) );
2911 // JNE,s done
2912 emit_opcode(cbuf,0x75);
2913 emit_d8(cbuf, 2 );
2914 // CMP $src1.lo,$src2.lo
2915 emit_opcode( cbuf, 0x3B );
2916 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
2917 // done:
2918 %}
2919
2920 enc_class convert_int_long( regL dst, eRegI src ) %{
2921 // mov $dst.lo,$src
2922 int dst_encoding = $dst$$reg;
2923 int src_encoding = $src$$reg;
2924 encode_Copy( cbuf, dst_encoding , src_encoding );
2925 // mov $dst.hi,$src
2926 encode_Copy( cbuf, HIGH_FROM_LOW(dst_encoding), src_encoding );
2927 // sar $dst.hi,31
2928 emit_opcode( cbuf, 0xC1 );
2929 emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW(dst_encoding) );
2930 emit_d8(cbuf, 0x1F );
2931 %}
2932
2933 enc_class convert_long_double( eRegL src ) %{
2934 // push $src.hi
2935 emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg));
2936 // push $src.lo
2937 emit_opcode(cbuf, 0x50+$src$$reg );
2938 // fild 64-bits at [SP]
2939 emit_opcode(cbuf,0xdf);
2940 emit_d8(cbuf, 0x6C);
2941 emit_d8(cbuf, 0x24);
2942 emit_d8(cbuf, 0x00);
2943 // pop stack
2944 emit_opcode(cbuf, 0x83); // add SP, #8
2945 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
2946 emit_d8(cbuf, 0x8);
2947 %}
2948
2949 enc_class multiply_con_and_shift_high( eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr ) %{
2950 // IMUL EDX:EAX,$src1
2951 emit_opcode( cbuf, 0xF7 );
2952 emit_rm( cbuf, 0x3, 0x5, $src1$$reg );
2953 // SAR EDX,$cnt-32
2954 int shift_count = ((int)$cnt$$constant) - 32;
2955 if (shift_count > 0) {
2956 emit_opcode(cbuf, 0xC1);
2957 emit_rm(cbuf, 0x3, 7, $dst$$reg );
2958 emit_d8(cbuf, shift_count);
2959 }
2960 %}
2961
2962 // this version doesn't have add sp, 8
2963 enc_class convert_long_double2( eRegL src ) %{
2964 // push $src.hi
2965 emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg));
2966 // push $src.lo
2967 emit_opcode(cbuf, 0x50+$src$$reg );
2968 // fild 64-bits at [SP]
2969 emit_opcode(cbuf,0xdf);
2970 emit_d8(cbuf, 0x6C);
2971 emit_d8(cbuf, 0x24);
2972 emit_d8(cbuf, 0x00);
2973 %}
2974
2975 enc_class long_int_multiply( eADXRegL dst, nadxRegI src) %{
2976 // Basic idea: long = (long)int * (long)int
2977 // IMUL EDX:EAX, src
2978 emit_opcode( cbuf, 0xF7 );
2979 emit_rm( cbuf, 0x3, 0x5, $src$$reg);
2980 %}
2981
2982 enc_class long_uint_multiply( eADXRegL dst, nadxRegI src) %{
2983 // Basic Idea: long = (int & 0xffffffffL) * (int & 0xffffffffL)
2984 // MUL EDX:EAX, src
2985 emit_opcode( cbuf, 0xF7 );
2986 emit_rm( cbuf, 0x3, 0x4, $src$$reg);
2987 %}
2988
2989 enc_class long_multiply( eADXRegL dst, eRegL src, eRegI tmp ) %{
2990 // Basic idea: lo(result) = lo(x_lo * y_lo)
2991 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
2992 // MOV $tmp,$src.lo
2993 encode_Copy( cbuf, $tmp$$reg, $src$$reg );
2994 // IMUL $tmp,EDX
2995 emit_opcode( cbuf, 0x0F );
2996 emit_opcode( cbuf, 0xAF );
2997 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
2998 // MOV EDX,$src.hi
2999 encode_Copy( cbuf, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg) );
3000 // IMUL EDX,EAX
3001 emit_opcode( cbuf, 0x0F );
3002 emit_opcode( cbuf, 0xAF );
3003 emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg );
3004 // ADD $tmp,EDX
3005 emit_opcode( cbuf, 0x03 );
3006 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
3007 // MUL EDX:EAX,$src.lo
3008 emit_opcode( cbuf, 0xF7 );
3009 emit_rm( cbuf, 0x3, 0x4, $src$$reg );
3010 // ADD EDX,ESI
3011 emit_opcode( cbuf, 0x03 );
3012 emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $tmp$$reg );
3013 %}
3014
3015 enc_class long_multiply_con( eADXRegL dst, immL_127 src, eRegI tmp ) %{
3016 // Basic idea: lo(result) = lo(src * y_lo)
3017 // hi(result) = hi(src * y_lo) + lo(src * y_hi)
3018 // IMUL $tmp,EDX,$src
3019 emit_opcode( cbuf, 0x6B );
3020 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
3021 emit_d8( cbuf, (int)$src$$constant );
3022 // MOV EDX,$src
3023 emit_opcode(cbuf, 0xB8 + EDX_enc);
3024 emit_d32( cbuf, (int)$src$$constant );
3025 // MUL EDX:EAX,EDX
3026 emit_opcode( cbuf, 0xF7 );
3027 emit_rm( cbuf, 0x3, 0x4, EDX_enc );
3028 // ADD EDX,ESI
3029 emit_opcode( cbuf, 0x03 );
3030 emit_rm( cbuf, 0x3, EDX_enc, $tmp$$reg );
3031 %}
3032
3033 enc_class long_div( eRegL src1, eRegL src2 ) %{
3034 // PUSH src1.hi
3035 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) );
3036 // PUSH src1.lo
3037 emit_opcode(cbuf, 0x50+$src1$$reg );
3038 // PUSH src2.hi
3039 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) );
3040 // PUSH src2.lo
3041 emit_opcode(cbuf, 0x50+$src2$$reg );
3042 // CALL directly to the runtime
3043 cbuf.set_inst_mark();
3044 emit_opcode(cbuf,0xE8); // Call into runtime
3045 emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::ldiv) - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
3046 // Restore stack
3047 emit_opcode(cbuf, 0x83); // add SP, #framesize
3048 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
3049 emit_d8(cbuf, 4*4);
3050 %}
3051
3052 enc_class long_mod( eRegL src1, eRegL src2 ) %{
3053 // PUSH src1.hi
3054 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) );
3055 // PUSH src1.lo
3056 emit_opcode(cbuf, 0x50+$src1$$reg );
3057 // PUSH src2.hi
3058 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) );
3059 // PUSH src2.lo
3060 emit_opcode(cbuf, 0x50+$src2$$reg );
3061 // CALL directly to the runtime
3062 cbuf.set_inst_mark();
3063 emit_opcode(cbuf,0xE8); // Call into runtime
3064 emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::lrem ) - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
3065 // Restore stack
3066 emit_opcode(cbuf, 0x83); // add SP, #framesize
3067 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
3068 emit_d8(cbuf, 4*4);
3069 %}
3070
3071 enc_class long_cmp_flags0( eRegL src, eRegI tmp ) %{
3072 // MOV $tmp,$src.lo
3073 emit_opcode(cbuf, 0x8B);
3074 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg);
3075 // OR $tmp,$src.hi
3076 emit_opcode(cbuf, 0x0B);
3077 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg));
3078 %}
3079
3080 enc_class long_cmp_flags1( eRegL src1, eRegL src2 ) %{
3081 // CMP $src1.lo,$src2.lo
3082 emit_opcode( cbuf, 0x3B );
3083 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
3084 // JNE,s skip
3085 emit_cc(cbuf, 0x70, 0x5);
3086 emit_d8(cbuf,2);
3087 // CMP $src1.hi,$src2.hi
3088 emit_opcode( cbuf, 0x3B );
3089 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) );
3090 %}
3091
3092 enc_class long_cmp_flags2( eRegL src1, eRegL src2, eRegI tmp ) %{
3093 // CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits
3094 emit_opcode( cbuf, 0x3B );
3095 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
3096 // MOV $tmp,$src1.hi
3097 emit_opcode( cbuf, 0x8B );
3098 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src1$$reg) );
3099 // SBB $tmp,$src2.hi\t! Compute flags for long compare
3100 emit_opcode( cbuf, 0x1B );
3101 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src2$$reg) );
3102 %}
3103
3104 enc_class long_cmp_flags3( eRegL src, eRegI tmp ) %{
3105 // XOR $tmp,$tmp
3106 emit_opcode(cbuf,0x33); // XOR
3107 emit_rm(cbuf,0x3, $tmp$$reg, $tmp$$reg);
3108 // CMP $tmp,$src.lo
3109 emit_opcode( cbuf, 0x3B );
3110 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg );
3111 // SBB $tmp,$src.hi
3112 emit_opcode( cbuf, 0x1B );
3113 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg) );
3114 %}
3115
3116 // Sniff, sniff... smells like Gnu Superoptimizer
3117 enc_class neg_long( eRegL dst ) %{
3118 emit_opcode(cbuf,0xF7); // NEG hi
3119 emit_rm (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg));
3120 emit_opcode(cbuf,0xF7); // NEG lo
3121 emit_rm (cbuf,0x3, 0x3, $dst$$reg );
3122 emit_opcode(cbuf,0x83); // SBB hi,0
3123 emit_rm (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg));
3124 emit_d8 (cbuf,0 );
3125 %}
3126
3127 enc_class movq_ld(regXD dst, memory mem) %{
3128 MacroAssembler _masm(&cbuf);
3129 __ movq($dst$$XMMRegister, $mem$$Address);
3130 %}
3131
3132 enc_class movq_st(memory mem, regXD src) %{
3133 MacroAssembler _masm(&cbuf);
3134 __ movq($mem$$Address, $src$$XMMRegister);
3135 %}
3136
3137 enc_class pshufd_8x8(regX dst, regX src) %{
3138 MacroAssembler _masm(&cbuf);
3139
3140 encode_CopyXD(cbuf, $dst$$reg, $src$$reg);
3141 __ punpcklbw(as_XMMRegister($dst$$reg), as_XMMRegister($dst$$reg));
3142 __ pshuflw(as_XMMRegister($dst$$reg), as_XMMRegister($dst$$reg), 0x00);
3143 %}
3144
3145 enc_class pshufd_4x16(regX dst, regX src) %{
3146 MacroAssembler _masm(&cbuf);
3147
3148 __ pshuflw(as_XMMRegister($dst$$reg), as_XMMRegister($src$$reg), 0x00);
3149 %}
3150
3151 enc_class pshufd(regXD dst, regXD src, int mode) %{
3152 MacroAssembler _masm(&cbuf);
3153
3154 __ pshufd(as_XMMRegister($dst$$reg), as_XMMRegister($src$$reg), $mode);
3155 %}
3156
3157 enc_class pxor(regXD dst, regXD src) %{
3158 MacroAssembler _masm(&cbuf);
3159
3160 __ pxor(as_XMMRegister($dst$$reg), as_XMMRegister($src$$reg));
3161 %}
3162
3163 enc_class mov_i2x(regXD dst, eRegI src) %{
3164 MacroAssembler _masm(&cbuf);
3165
3166 __ movdl(as_XMMRegister($dst$$reg), as_Register($src$$reg));
3167 %}
3168
3169
3170 // Because the transitions from emitted code to the runtime
3171 // monitorenter/exit helper stubs are so slow it's critical that
3172 // we inline both the stack-locking fast-path and the inflated fast path.
3173 //
3174 // See also: cmpFastLock and cmpFastUnlock.
3175 //
3176 // What follows is a specialized inline transliteration of the code
3177 // in slow_enter() and slow_exit(). If we're concerned about I$ bloat
3178 // another option would be to emit TrySlowEnter and TrySlowExit methods
3179 // at startup-time. These methods would accept arguments as
3180 // (rax,=Obj, rbx=Self, rcx=box, rdx=Scratch) and return success-failure
3181 // indications in the icc.ZFlag. Fast_Lock and Fast_Unlock would simply
3182 // marshal the arguments and emit calls to TrySlowEnter and TrySlowExit.
3183 // In practice, however, the # of lock sites is bounded and is usually small.
3184 // Besides the call overhead, TrySlowEnter and TrySlowExit might suffer
3185 // if the processor uses simple bimodal branch predictors keyed by EIP
3186 // Since the helper routines would be called from multiple synchronization
3187 // sites.
3188 //
3189 // An even better approach would be write "MonitorEnter()" and "MonitorExit()"
3190 // in java - using j.u.c and unsafe - and just bind the lock and unlock sites
3191 // to those specialized methods. That'd give us a mostly platform-independent
3192 // implementation that the JITs could optimize and inline at their pleasure.
3193 // Done correctly, the only time we'd need to cross to native could would be
3194 // to park() or unpark() threads. We'd also need a few more unsafe operators
3195 // to (a) prevent compiler-JIT reordering of non-volatile accesses, and
3196 // (b) explicit barriers or fence operations.
3197 //
3198 // TODO:
3199 //
3200 // * Arrange for C2 to pass "Self" into Fast_Lock and Fast_Unlock in one of the registers (scr).
3201 // This avoids manifesting the Self pointer in the Fast_Lock and Fast_Unlock terminals.
3202 // Given TLAB allocation, Self is usually manifested in a register, so passing it into
3203 // the lock operators would typically be faster than reifying Self.
3204 //
3205 // * Ideally I'd define the primitives as:
3206 // fast_lock (nax Obj, nax box, EAX tmp, nax scr) where box, tmp and scr are KILLED.
3207 // fast_unlock (nax Obj, EAX box, nax tmp) where box and tmp are KILLED
3208 // Unfortunately ADLC bugs prevent us from expressing the ideal form.
3209 // Instead, we're stuck with a rather awkward and brittle register assignments below.
3210 // Furthermore the register assignments are overconstrained, possibly resulting in
3211 // sub-optimal code near the synchronization site.
3212 //
3213 // * Eliminate the sp-proximity tests and just use "== Self" tests instead.
3214 // Alternately, use a better sp-proximity test.
3215 //
3216 // * Currently ObjectMonitor._Owner can hold either an sp value or a (THREAD *) value.
3217 // Either one is sufficient to uniquely identify a thread.
3218 // TODO: eliminate use of sp in _owner and use get_thread(tr) instead.
3219 //
3220 // * Intrinsify notify() and notifyAll() for the common cases where the
3221 // object is locked by the calling thread but the waitlist is empty.
3222 // avoid the expensive JNI call to JVM_Notify() and JVM_NotifyAll().
3223 //
3224 // * use jccb and jmpb instead of jcc and jmp to improve code density.
3225 // But beware of excessive branch density on AMD Opterons.
3226 //
3227 // * Both Fast_Lock and Fast_Unlock set the ICC.ZF to indicate success
3228 // or failure of the fast-path. If the fast-path fails then we pass
3229 // control to the slow-path, typically in C. In Fast_Lock and
3230 // Fast_Unlock we often branch to DONE_LABEL, just to find that C2
3231 // will emit a conditional branch immediately after the node.
3232 // So we have branches to branches and lots of ICC.ZF games.
3233 // Instead, it might be better to have C2 pass a "FailureLabel"
3234 // into Fast_Lock and Fast_Unlock. In the case of success, control
3235 // will drop through the node. ICC.ZF is undefined at exit.
3236 // In the case of failure, the node will branch directly to the
3237 // FailureLabel
3238
3239
3240 // obj: object to lock
3241 // box: on-stack box address (displaced header location) - KILLED
3242 // rax,: tmp -- KILLED
3243 // scr: tmp -- KILLED
3244 enc_class Fast_Lock( eRegP obj, eRegP box, eAXRegI tmp, eRegP scr ) %{
3245
3246 Register objReg = as_Register($obj$$reg);
3247 Register boxReg = as_Register($box$$reg);
3248 Register tmpReg = as_Register($tmp$$reg);
3249 Register scrReg = as_Register($scr$$reg);
3250
3251 // Ensure the register assignents are disjoint
3252 guarantee (objReg != boxReg, "") ;
3253 guarantee (objReg != tmpReg, "") ;
3254 guarantee (objReg != scrReg, "") ;
3255 guarantee (boxReg != tmpReg, "") ;
3256 guarantee (boxReg != scrReg, "") ;
3257 guarantee (tmpReg == as_Register(EAX_enc), "") ;
3258
3259 MacroAssembler masm(&cbuf);
3260
3261 if (_counters != NULL) {
3262 masm.atomic_incl(ExternalAddress((address) _counters->total_entry_count_addr()));
3263 }
3264 if (EmitSync & 1) {
3265 // set box->dhw = unused_mark (3)
3266 // Force all sync thru slow-path: slow_enter() and slow_exit()
3267 masm.movptr (Address(boxReg, 0), int32_t(markOopDesc::unused_mark())) ;
3268 masm.cmpptr (rsp, (int32_t)0) ;
3269 } else
3270 if (EmitSync & 2) {
3271 Label DONE_LABEL ;
3272 if (UseBiasedLocking) {
3273 // Note: tmpReg maps to the swap_reg argument and scrReg to the tmp_reg argument.
3274 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters);
3275 }
3276
3277 masm.movptr(tmpReg, Address(objReg, 0)) ; // fetch markword
3278 masm.orptr (tmpReg, 0x1);
3279 masm.movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS
3280 if (os::is_MP()) { masm.lock(); }
3281 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
3282 masm.jcc(Assembler::equal, DONE_LABEL);
3283 // Recursive locking
3284 masm.subptr(tmpReg, rsp);
3285 masm.andptr(tmpReg, (int32_t) 0xFFFFF003 );
3286 masm.movptr(Address(boxReg, 0), tmpReg);
3287 masm.bind(DONE_LABEL) ;
3288 } else {
3289 // Possible cases that we'll encounter in fast_lock
3290 // ------------------------------------------------
3291 // * Inflated
3292 // -- unlocked
3293 // -- Locked
3294 // = by self
3295 // = by other
3296 // * biased
3297 // -- by Self
3298 // -- by other
3299 // * neutral
3300 // * stack-locked
3301 // -- by self
3302 // = sp-proximity test hits
3303 // = sp-proximity test generates false-negative
3304 // -- by other
3305 //
3306
3307 Label IsInflated, DONE_LABEL, PopDone ;
3308
3309 // TODO: optimize away redundant LDs of obj->mark and improve the markword triage
3310 // order to reduce the number of conditional branches in the most common cases.
3311 // Beware -- there's a subtle invariant that fetch of the markword
3312 // at [FETCH], below, will never observe a biased encoding (*101b).
3313 // If this invariant is not held we risk exclusion (safety) failure.
3314 if (UseBiasedLocking && !UseOptoBiasInlining) {
3315 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters);
3316 }
3317
3318 masm.movptr(tmpReg, Address(objReg, 0)) ; // [FETCH]
3319 masm.testptr(tmpReg, 0x02) ; // Inflated v (Stack-locked or neutral)
3320 masm.jccb (Assembler::notZero, IsInflated) ;
3321
3322 // Attempt stack-locking ...
3323 masm.orptr (tmpReg, 0x1);
3324 masm.movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS
3325 if (os::is_MP()) { masm.lock(); }
3326 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
3327 if (_counters != NULL) {
3328 masm.cond_inc32(Assembler::equal,
3329 ExternalAddress((address)_counters->fast_path_entry_count_addr()));
3330 }
3331 masm.jccb (Assembler::equal, DONE_LABEL);
3332
3333 // Recursive locking
3334 masm.subptr(tmpReg, rsp);
3335 masm.andptr(tmpReg, 0xFFFFF003 );
3336 masm.movptr(Address(boxReg, 0), tmpReg);
3337 if (_counters != NULL) {
3338 masm.cond_inc32(Assembler::equal,
3339 ExternalAddress((address)_counters->fast_path_entry_count_addr()));
3340 }
3341 masm.jmp (DONE_LABEL) ;
3342
3343 masm.bind (IsInflated) ;
3344
3345 // The object is inflated.
3346 //
3347 // TODO-FIXME: eliminate the ugly use of manifest constants:
3348 // Use markOopDesc::monitor_value instead of "2".
3349 // use markOop::unused_mark() instead of "3".
3350 // The tmpReg value is an objectMonitor reference ORed with
3351 // markOopDesc::monitor_value (2). We can either convert tmpReg to an
3352 // objectmonitor pointer by masking off the "2" bit or we can just
3353 // use tmpReg as an objectmonitor pointer but bias the objectmonitor
3354 // field offsets with "-2" to compensate for and annul the low-order tag bit.
3355 //
3356 // I use the latter as it avoids AGI stalls.
3357 // As such, we write "mov r, [tmpReg+OFFSETOF(Owner)-2]"
3358 // instead of "mov r, [tmpReg+OFFSETOF(Owner)]".
3359 //
3360 #define OFFSET_SKEWED(f) ((ObjectMonitor::f ## _offset_in_bytes())-2)
3361
3362 // boxReg refers to the on-stack BasicLock in the current frame.
3363 // We'd like to write:
3364 // set box->_displaced_header = markOop::unused_mark(). Any non-0 value suffices.
3365 // This is convenient but results a ST-before-CAS penalty. The following CAS suffers
3366 // additional latency as we have another ST in the store buffer that must drain.
3367
3368 if (EmitSync & 8192) {
3369 masm.movptr(Address(boxReg, 0), 3) ; // results in ST-before-CAS penalty
3370 masm.get_thread (scrReg) ;
3371 masm.movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
3372 masm.movptr(tmpReg, NULL_WORD); // consider: xor vs mov
3373 if (os::is_MP()) { masm.lock(); }
3374 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3375 } else
3376 if ((EmitSync & 128) == 0) { // avoid ST-before-CAS
3377 masm.movptr(scrReg, boxReg) ;
3378 masm.movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
3379
3380 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
3381 if ((EmitSync & 2048) && VM_Version::supports_3dnow() && os::is_MP()) {
3382 // prefetchw [eax + Offset(_owner)-2]
3383 masm.prefetchw(Address(rax, ObjectMonitor::owner_offset_in_bytes()-2));
3384 }
3385
3386 if ((EmitSync & 64) == 0) {
3387 // Optimistic form: consider XORL tmpReg,tmpReg
3388 masm.movptr(tmpReg, NULL_WORD) ;
3389 } else {
3390 // Can suffer RTS->RTO upgrades on shared or cold $ lines
3391 // Test-And-CAS instead of CAS
3392 masm.movptr(tmpReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; // rax, = m->_owner
3393 masm.testptr(tmpReg, tmpReg) ; // Locked ?
3394 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3395 }
3396
3397 // Appears unlocked - try to swing _owner from null to non-null.
3398 // Ideally, I'd manifest "Self" with get_thread and then attempt
3399 // to CAS the register containing Self into m->Owner.
3400 // But we don't have enough registers, so instead we can either try to CAS
3401 // rsp or the address of the box (in scr) into &m->owner. If the CAS succeeds
3402 // we later store "Self" into m->Owner. Transiently storing a stack address
3403 // (rsp or the address of the box) into m->owner is harmless.
3404 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
3405 if (os::is_MP()) { masm.lock(); }
3406 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3407 masm.movptr(Address(scrReg, 0), 3) ; // box->_displaced_header = 3
3408 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3409 masm.get_thread (scrReg) ; // beware: clobbers ICCs
3410 masm.movptr(Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2), scrReg) ;
3411 masm.xorptr(boxReg, boxReg) ; // set icc.ZFlag = 1 to indicate success
3412
3413 // If the CAS fails we can either retry or pass control to the slow-path.
3414 // We use the latter tactic.
3415 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
3416 // If the CAS was successful ...
3417 // Self has acquired the lock
3418 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
3419 // Intentional fall-through into DONE_LABEL ...
3420 } else {
3421 masm.movptr(Address(boxReg, 0), 3) ; // results in ST-before-CAS penalty
3422 masm.movptr(boxReg, tmpReg) ;
3423
3424 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
3425 if ((EmitSync & 2048) && VM_Version::supports_3dnow() && os::is_MP()) {
3426 // prefetchw [eax + Offset(_owner)-2]
3427 masm.prefetchw(Address(rax, ObjectMonitor::owner_offset_in_bytes()-2));
3428 }
3429
3430 if ((EmitSync & 64) == 0) {
3431 // Optimistic form
3432 masm.xorptr (tmpReg, tmpReg) ;
3433 } else {
3434 // Can suffer RTS->RTO upgrades on shared or cold $ lines
3435 masm.movptr(tmpReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; // rax, = m->_owner
3436 masm.testptr(tmpReg, tmpReg) ; // Locked ?
3437 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3438 }
3439
3440 // Appears unlocked - try to swing _owner from null to non-null.
3441 // Use either "Self" (in scr) or rsp as thread identity in _owner.
3442 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
3443 masm.get_thread (scrReg) ;
3444 if (os::is_MP()) { masm.lock(); }
3445 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3446
3447 // If the CAS fails we can either retry or pass control to the slow-path.
3448 // We use the latter tactic.
3449 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
3450 // If the CAS was successful ...
3451 // Self has acquired the lock
3452 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
3453 // Intentional fall-through into DONE_LABEL ...
3454 }
3455
3456 // DONE_LABEL is a hot target - we'd really like to place it at the
3457 // start of cache line by padding with NOPs.
3458 // See the AMD and Intel software optimization manuals for the
3459 // most efficient "long" NOP encodings.
3460 // Unfortunately none of our alignment mechanisms suffice.
3461 masm.bind(DONE_LABEL);
3462
3463 // Avoid branch-to-branch on AMD processors
3464 // This appears to be superstition.
3465 if (EmitSync & 32) masm.nop() ;
3466
3467
3468 // At DONE_LABEL the icc ZFlag is set as follows ...
3469 // Fast_Unlock uses the same protocol.
3470 // ZFlag == 1 -> Success
3471 // ZFlag == 0 -> Failure - force control through the slow-path
3472 }
3473 %}
3474
3475 // obj: object to unlock
3476 // box: box address (displaced header location), killed. Must be EAX.
3477 // rbx,: killed tmp; cannot be obj nor box.
3478 //
3479 // Some commentary on balanced locking:
3480 //
3481 // Fast_Lock and Fast_Unlock are emitted only for provably balanced lock sites.
3482 // Methods that don't have provably balanced locking are forced to run in the
3483 // interpreter - such methods won't be compiled to use fast_lock and fast_unlock.
3484 // The interpreter provides two properties:
3485 // I1: At return-time the interpreter automatically and quietly unlocks any
3486 // objects acquired the current activation (frame). Recall that the
3487 // interpreter maintains an on-stack list of locks currently held by
3488 // a frame.
3489 // I2: If a method attempts to unlock an object that is not held by the
3490 // the frame the interpreter throws IMSX.
3491 //
3492 // Lets say A(), which has provably balanced locking, acquires O and then calls B().
3493 // B() doesn't have provably balanced locking so it runs in the interpreter.
3494 // Control returns to A() and A() unlocks O. By I1 and I2, above, we know that O
3495 // is still locked by A().
3496 //
3497 // The only other source of unbalanced locking would be JNI. The "Java Native Interface:
3498 // Programmer's Guide and Specification" claims that an object locked by jni_monitorenter
3499 // should not be unlocked by "normal" java-level locking and vice-versa. The specification
3500 // doesn't specify what will occur if a program engages in such mixed-mode locking, however.
3501
3502 enc_class Fast_Unlock( nabxRegP obj, eAXRegP box, eRegP tmp) %{
3503
3504 Register objReg = as_Register($obj$$reg);
3505 Register boxReg = as_Register($box$$reg);
3506 Register tmpReg = as_Register($tmp$$reg);
3507
3508 guarantee (objReg != boxReg, "") ;
3509 guarantee (objReg != tmpReg, "") ;
3510 guarantee (boxReg != tmpReg, "") ;
3511 guarantee (boxReg == as_Register(EAX_enc), "") ;
3512 MacroAssembler masm(&cbuf);
3513
3514 if (EmitSync & 4) {
3515 // Disable - inhibit all inlining. Force control through the slow-path
3516 masm.cmpptr (rsp, 0) ;
3517 } else
3518 if (EmitSync & 8) {
3519 Label DONE_LABEL ;
3520 if (UseBiasedLocking) {
3521 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL);
3522 }
3523 // classic stack-locking code ...
3524 masm.movptr(tmpReg, Address(boxReg, 0)) ;
3525 masm.testptr(tmpReg, tmpReg) ;
3526 masm.jcc (Assembler::zero, DONE_LABEL) ;
3527 if (os::is_MP()) { masm.lock(); }
3528 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses EAX which is box
3529 masm.bind(DONE_LABEL);
3530 } else {
3531 Label DONE_LABEL, Stacked, CheckSucc, Inflated ;
3532
3533 // Critically, the biased locking test must have precedence over
3534 // and appear before the (box->dhw == 0) recursive stack-lock test.
3535 if (UseBiasedLocking && !UseOptoBiasInlining) {
3536 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL);
3537 }
3538
3539 masm.cmpptr(Address(boxReg, 0), 0) ; // Examine the displaced header
3540 masm.movptr(tmpReg, Address(objReg, 0)) ; // Examine the object's markword
3541 masm.jccb (Assembler::zero, DONE_LABEL) ; // 0 indicates recursive stack-lock
3542
3543 masm.testptr(tmpReg, 0x02) ; // Inflated?
3544 masm.jccb (Assembler::zero, Stacked) ;
3545
3546 masm.bind (Inflated) ;
3547 // It's inflated.
3548 // Despite our balanced locking property we still check that m->_owner == Self
3549 // as java routines or native JNI code called by this thread might
3550 // have released the lock.
3551 // Refer to the comments in synchronizer.cpp for how we might encode extra
3552 // state in _succ so we can avoid fetching EntryList|cxq.
3553 //
3554 // I'd like to add more cases in fast_lock() and fast_unlock() --
3555 // such as recursive enter and exit -- but we have to be wary of
3556 // I$ bloat, T$ effects and BP$ effects.
3557 //
3558 // If there's no contention try a 1-0 exit. That is, exit without
3559 // a costly MEMBAR or CAS. See synchronizer.cpp for details on how
3560 // we detect and recover from the race that the 1-0 exit admits.
3561 //
3562 // Conceptually Fast_Unlock() must execute a STST|LDST "release" barrier
3563 // before it STs null into _owner, releasing the lock. Updates
3564 // to data protected by the critical section must be visible before
3565 // we drop the lock (and thus before any other thread could acquire
3566 // the lock and observe the fields protected by the lock).
3567 // IA32's memory-model is SPO, so STs are ordered with respect to
3568 // each other and there's no need for an explicit barrier (fence).
3569 // See also http://gee.cs.oswego.edu/dl/jmm/cookbook.html.
3570
3571 masm.get_thread (boxReg) ;
3572 if ((EmitSync & 4096) && VM_Version::supports_3dnow() && os::is_MP()) {
3573 // prefetchw [ebx + Offset(_owner)-2]
3574 masm.prefetchw(Address(rbx, ObjectMonitor::owner_offset_in_bytes()-2));
3575 }
3576
3577 // Note that we could employ various encoding schemes to reduce
3578 // the number of loads below (currently 4) to just 2 or 3.
3579 // Refer to the comments in synchronizer.cpp.
3580 // In practice the chain of fetches doesn't seem to impact performance, however.
3581 if ((EmitSync & 65536) == 0 && (EmitSync & 256)) {
3582 // Attempt to reduce branch density - AMD's branch predictor.
3583 masm.xorptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3584 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ;
3585 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ;
3586 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ;
3587 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3588 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ;
3589 masm.jmpb (DONE_LABEL) ;
3590 } else {
3591 masm.xorptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3592 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ;
3593 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3594 masm.movptr(boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ;
3595 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ;
3596 masm.jccb (Assembler::notZero, CheckSucc) ;
3597 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ;
3598 masm.jmpb (DONE_LABEL) ;
3599 }
3600
3601 // The Following code fragment (EmitSync & 65536) improves the performance of
3602 // contended applications and contended synchronization microbenchmarks.
3603 // Unfortunately the emission of the code - even though not executed - causes regressions
3604 // in scimark and jetstream, evidently because of $ effects. Replacing the code
3605 // with an equal number of never-executed NOPs results in the same regression.
3606 // We leave it off by default.
3607
3608 if ((EmitSync & 65536) != 0) {
3609 Label LSuccess, LGoSlowPath ;
3610
3611 masm.bind (CheckSucc) ;
3612
3613 // Optional pre-test ... it's safe to elide this
3614 if ((EmitSync & 16) == 0) {
3615 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), 0) ;
3616 masm.jccb (Assembler::zero, LGoSlowPath) ;
3617 }
3618
3619 // We have a classic Dekker-style idiom:
3620 // ST m->_owner = 0 ; MEMBAR; LD m->_succ
3621 // There are a number of ways to implement the barrier:
3622 // (1) lock:andl &m->_owner, 0
3623 // is fast, but mask doesn't currently support the "ANDL M,IMM32" form.
3624 // LOCK: ANDL [ebx+Offset(_Owner)-2], 0
3625 // Encodes as 81 31 OFF32 IMM32 or 83 63 OFF8 IMM8
3626 // (2) If supported, an explicit MFENCE is appealing.
3627 // In older IA32 processors MFENCE is slower than lock:add or xchg
3628 // particularly if the write-buffer is full as might be the case if
3629 // if stores closely precede the fence or fence-equivalent instruction.
3630 // In more modern implementations MFENCE appears faster, however.
3631 // (3) In lieu of an explicit fence, use lock:addl to the top-of-stack
3632 // The $lines underlying the top-of-stack should be in M-state.
3633 // The locked add instruction is serializing, of course.
3634 // (4) Use xchg, which is serializing
3635 // mov boxReg, 0; xchgl boxReg, [tmpReg + Offset(_owner)-2] also works
3636 // (5) ST m->_owner = 0 and then execute lock:orl &m->_succ, 0.
3637 // The integer condition codes will tell us if succ was 0.
3638 // Since _succ and _owner should reside in the same $line and
3639 // we just stored into _owner, it's likely that the $line
3640 // remains in M-state for the lock:orl.
3641 //
3642 // We currently use (3), although it's likely that switching to (2)
3643 // is correct for the future.
3644
3645 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ;
3646 if (os::is_MP()) {
3647 if (VM_Version::supports_sse2() && 1 == FenceInstruction) {
3648 masm.mfence();
3649 } else {
3650 masm.lock () ; masm.addptr(Address(rsp, 0), 0) ;
3651 }
3652 }
3653 // Ratify _succ remains non-null
3654 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), 0) ;
3655 masm.jccb (Assembler::notZero, LSuccess) ;
3656
3657 masm.xorptr(boxReg, boxReg) ; // box is really EAX
3658 if (os::is_MP()) { masm.lock(); }
3659 masm.cmpxchgptr(rsp, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2));
3660 masm.jccb (Assembler::notEqual, LSuccess) ;
3661 // Since we're low on registers we installed rsp as a placeholding in _owner.
3662 // Now install Self over rsp. This is safe as we're transitioning from
3663 // non-null to non=null
3664 masm.get_thread (boxReg) ;
3665 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), boxReg) ;
3666 // Intentional fall-through into LGoSlowPath ...
3667
3668 masm.bind (LGoSlowPath) ;
3669 masm.orptr(boxReg, 1) ; // set ICC.ZF=0 to indicate failure
3670 masm.jmpb (DONE_LABEL) ;
3671
3672 masm.bind (LSuccess) ;
3673 masm.xorptr(boxReg, boxReg) ; // set ICC.ZF=1 to indicate success
3674 masm.jmpb (DONE_LABEL) ;
3675 }
3676
3677 masm.bind (Stacked) ;
3678 // It's not inflated and it's not recursively stack-locked and it's not biased.
3679 // It must be stack-locked.
3680 // Try to reset the header to displaced header.
3681 // The "box" value on the stack is stable, so we can reload
3682 // and be assured we observe the same value as above.
3683 masm.movptr(tmpReg, Address(boxReg, 0)) ;
3684 if (os::is_MP()) { masm.lock(); }
3685 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses EAX which is box
3686 // Intention fall-thru into DONE_LABEL
3687
3688
3689 // DONE_LABEL is a hot target - we'd really like to place it at the
3690 // start of cache line by padding with NOPs.
3691 // See the AMD and Intel software optimization manuals for the
3692 // most efficient "long" NOP encodings.
3693 // Unfortunately none of our alignment mechanisms suffice.
3694 if ((EmitSync & 65536) == 0) {
3695 masm.bind (CheckSucc) ;
3696 }
3697 masm.bind(DONE_LABEL);
3698
3699 // Avoid branch to branch on AMD processors
3700 if (EmitSync & 32768) { masm.nop() ; }
3701 }
3702 %}
3703
3704 enc_class enc_String_Compare(eDIRegP str1, eSIRegP str2, regXD tmp1, regXD tmp2,
3705 eAXRegI tmp3, eBXRegI tmp4, eCXRegI result) %{
3706 Label ECX_GOOD_LABEL, LENGTH_DIFF_LABEL,
3707 POP_LABEL, DONE_LABEL, CONT_LABEL,
3708 WHILE_HEAD_LABEL;
3709 MacroAssembler masm(&cbuf);
3710
3711 XMMRegister tmp1Reg = as_XMMRegister($tmp1$$reg);
3712 XMMRegister tmp2Reg = as_XMMRegister($tmp2$$reg);
3713
3714 // Get the first character position in both strings
3715 // [8] char array, [12] offset, [16] count
3716 int value_offset = java_lang_String::value_offset_in_bytes();
3717 int offset_offset = java_lang_String::offset_offset_in_bytes();
3718 int count_offset = java_lang_String::count_offset_in_bytes();
3719 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR);
3720
3721 masm.movptr(rax, Address(rsi, value_offset));
3722 masm.movl(rcx, Address(rsi, offset_offset));
3723 masm.lea(rax, Address(rax, rcx, Address::times_2, base_offset));
3724 masm.movptr(rbx, Address(rdi, value_offset));
3725 masm.movl(rcx, Address(rdi, offset_offset));
3726 masm.lea(rbx, Address(rbx, rcx, Address::times_2, base_offset));
3727
3728 // Compute the minimum of the string lengths(rsi) and the
3729 // difference of the string lengths (stack)
3730
3731 if (VM_Version::supports_cmov()) {
3732 masm.movl(rdi, Address(rdi, count_offset));
3733 masm.movl(rsi, Address(rsi, count_offset));
3734 masm.movl(rcx, rdi);
3735 masm.subl(rdi, rsi);
3736 masm.push(rdi);
3737 masm.cmovl(Assembler::lessEqual, rsi, rcx);
3738 } else {
3739 masm.movl(rdi, Address(rdi, count_offset));
3740 masm.movl(rcx, Address(rsi, count_offset));
3741 masm.movl(rsi, rdi);
3742 masm.subl(rdi, rcx);
3743 masm.push(rdi);
3744 masm.jccb(Assembler::lessEqual, ECX_GOOD_LABEL);
3745 masm.movl(rsi, rcx);
3746 // rsi holds min, rcx is unused
3747 }
3748
3749 // Is the minimum length zero?
3750 masm.bind(ECX_GOOD_LABEL);
3751 masm.testl(rsi, rsi);
3752 masm.jcc(Assembler::zero, LENGTH_DIFF_LABEL);
3753
3754 // Load first characters
3755 masm.load_unsigned_short(rcx, Address(rbx, 0));
3756 masm.load_unsigned_short(rdi, Address(rax, 0));
3757
3758 // Compare first characters
3759 masm.subl(rcx, rdi);
3760 masm.jcc(Assembler::notZero, POP_LABEL);
3761 masm.decrementl(rsi);
3762 masm.jcc(Assembler::zero, LENGTH_DIFF_LABEL);
3763
3764 {
3765 // Check after comparing first character to see if strings are equivalent
3766 Label LSkip2;
3767 // Check if the strings start at same location
3768 masm.cmpptr(rbx,rax);
3769 masm.jccb(Assembler::notEqual, LSkip2);
3770
3771 // Check if the length difference is zero (from stack)
3772 masm.cmpl(Address(rsp, 0), 0x0);
3773 masm.jcc(Assembler::equal, LENGTH_DIFF_LABEL);
3774
3775 // Strings might not be equivalent
3776 masm.bind(LSkip2);
3777 }
3778
3779 // Advance to next character
3780 masm.addptr(rax, 2);
3781 masm.addptr(rbx, 2);
3782
3783 if (UseSSE42Intrinsics) {
3784 // With SSE4.2, use double quad vector compare
3785 Label COMPARE_VECTORS, VECTOR_NOT_EQUAL, COMPARE_TAIL;
3786 // Setup to compare 16-byte vectors
3787 masm.movl(rdi, rsi);
3788 masm.andl(rsi, 0xfffffff8); // rsi holds the vector count
3789 masm.andl(rdi, 0x00000007); // rdi holds the tail count
3790 masm.testl(rsi, rsi);
3791 masm.jccb(Assembler::zero, COMPARE_TAIL);
3792
3793 masm.lea(rax, Address(rax, rsi, Address::times_2));
3794 masm.lea(rbx, Address(rbx, rsi, Address::times_2));
3795 masm.negl(rsi);
3796
3797 masm.bind(COMPARE_VECTORS);
3798 masm.movdqu(tmp1Reg, Address(rax, rsi, Address::times_2));
3799 masm.movdqu(tmp2Reg, Address(rbx, rsi, Address::times_2));
3800 masm.pxor(tmp1Reg, tmp2Reg);
3801 masm.ptest(tmp1Reg, tmp1Reg);
3802 masm.jccb(Assembler::notZero, VECTOR_NOT_EQUAL);
3803 masm.addl(rsi, 8);
3804 masm.jcc(Assembler::notZero, COMPARE_VECTORS);
3805 masm.jmpb(COMPARE_TAIL);
3806
3807 // Mismatched characters in the vectors
3808 masm.bind(VECTOR_NOT_EQUAL);
3809 masm.lea(rax, Address(rax, rsi, Address::times_2));
3810 masm.lea(rbx, Address(rbx, rsi, Address::times_2));
3811 masm.movl(rdi, 8);
3812
3813 // Compare tail (< 8 chars), or rescan last vectors to
3814 // find 1st mismatched characters
3815 masm.bind(COMPARE_TAIL);
3816 masm.testl(rdi, rdi);
3817 masm.jccb(Assembler::zero, LENGTH_DIFF_LABEL);
3818 masm.movl(rsi, rdi);
3819 // Fallthru to tail compare
3820 }
3821
3822 //Shift rax, and rbx, to the end of the arrays, negate min
3823 masm.lea(rax, Address(rax, rsi, Address::times_2, 0));
3824 masm.lea(rbx, Address(rbx, rsi, Address::times_2, 0));
3825 masm.negl(rsi);
3826
3827 // Compare the rest of the characters
3828 masm.bind(WHILE_HEAD_LABEL);
3829 masm.load_unsigned_short(rcx, Address(rbx, rsi, Address::times_2, 0));
3830 masm.load_unsigned_short(rdi, Address(rax, rsi, Address::times_2, 0));
3831 masm.subl(rcx, rdi);
3832 masm.jccb(Assembler::notZero, POP_LABEL);
3833 masm.incrementl(rsi);
3834 masm.jcc(Assembler::notZero, WHILE_HEAD_LABEL);
3835
3836 // Strings are equal up to min length. Return the length difference.
3837 masm.bind(LENGTH_DIFF_LABEL);
3838 masm.pop(rcx);
3839 masm.jmpb(DONE_LABEL);
3840
3841 // Discard the stored length difference
3842 masm.bind(POP_LABEL);
3843 masm.addptr(rsp, 4);
3844
3845 // That's it
3846 masm.bind(DONE_LABEL);
3847 %}
3848
3849 enc_class enc_String_Equals(eDIRegP str1, eSIRegP str2, regXD tmp1, regXD tmp2,
3850 eBXRegI tmp3, eCXRegI tmp4, eAXRegI result) %{
3851 Label RET_TRUE, RET_FALSE, DONE, COMPARE_VECTORS, COMPARE_CHAR;
3852 MacroAssembler masm(&cbuf);
3853
3854 XMMRegister tmp1Reg = as_XMMRegister($tmp1$$reg);
3855 XMMRegister tmp2Reg = as_XMMRegister($tmp2$$reg);
3856
3857 int value_offset = java_lang_String::value_offset_in_bytes();
3858 int offset_offset = java_lang_String::offset_offset_in_bytes();
3859 int count_offset = java_lang_String::count_offset_in_bytes();
3860 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR);
3861
3862 // does source == target string?
3863 masm.cmpptr(rdi, rsi);
3864 masm.jcc(Assembler::equal, RET_TRUE);
3865
3866 // get and compare counts
3867 masm.movl(rcx, Address(rdi, count_offset));
3868 masm.movl(rax, Address(rsi, count_offset));
3869 masm.cmpl(rcx, rax);
3870 masm.jcc(Assembler::notEqual, RET_FALSE);
3871 masm.testl(rax, rax);
3872 masm.jcc(Assembler::zero, RET_TRUE);
3873
3874 // get source string offset and value
3875 masm.movptr(rbx, Address(rsi, value_offset));
3876 masm.movl(rax, Address(rsi, offset_offset));
3877 masm.leal(rsi, Address(rbx, rax, Address::times_2, base_offset));
3878
3879 // get compare string offset and value
3880 masm.movptr(rbx, Address(rdi, value_offset));
3881 masm.movl(rax, Address(rdi, offset_offset));
3882 masm.leal(rdi, Address(rbx, rax, Address::times_2, base_offset));
3883
3884 // Set byte count
3885 masm.shll(rcx, 1);
3886 masm.movl(rax, rcx);
3887
3888 if (UseSSE42Intrinsics) {
3889 // With SSE4.2, use double quad vector compare
3890 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
3891 // Compare 16-byte vectors
3892 masm.andl(rcx, 0xfffffff0); // vector count (in bytes)
3893 masm.andl(rax, 0x0000000e); // tail count (in bytes)
3894 masm.testl(rcx, rcx);
3895 masm.jccb(Assembler::zero, COMPARE_TAIL);
3896 masm.lea(rdi, Address(rdi, rcx, Address::times_1));
3897 masm.lea(rsi, Address(rsi, rcx, Address::times_1));
3898 masm.negl(rcx);
3899
3900 masm.bind(COMPARE_WIDE_VECTORS);
3901 masm.movdqu(tmp1Reg, Address(rdi, rcx, Address::times_1));
3902 masm.movdqu(tmp2Reg, Address(rsi, rcx, Address::times_1));
3903 masm.pxor(tmp1Reg, tmp2Reg);
3904 masm.ptest(tmp1Reg, tmp1Reg);
3905 masm.jccb(Assembler::notZero, RET_FALSE);
3906 masm.addl(rcx, 16);
3907 masm.jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
3908 masm.bind(COMPARE_TAIL);
3909 masm.movl(rcx, rax);
3910 // Fallthru to tail compare
3911 }
3912
3913 // Compare 4-byte vectors
3914 masm.andl(rcx, 0xfffffffc); // vector count (in bytes)
3915 masm.andl(rax, 0x00000002); // tail char (in bytes)
3916 masm.testl(rcx, rcx);
3917 masm.jccb(Assembler::zero, COMPARE_CHAR);
3918 masm.lea(rdi, Address(rdi, rcx, Address::times_1));
3919 masm.lea(rsi, Address(rsi, rcx, Address::times_1));
3920 masm.negl(rcx);
3921
3922 masm.bind(COMPARE_VECTORS);
3923 masm.movl(rbx, Address(rdi, rcx, Address::times_1));
3924 masm.cmpl(rbx, Address(rsi, rcx, Address::times_1));
3925 masm.jccb(Assembler::notEqual, RET_FALSE);
3926 masm.addl(rcx, 4);
3927 masm.jcc(Assembler::notZero, COMPARE_VECTORS);
3928
3929 // Compare trailing char (final 2 bytes), if any
3930 masm.bind(COMPARE_CHAR);
3931 masm.testl(rax, rax);
3932 masm.jccb(Assembler::zero, RET_TRUE);
3933 masm.load_unsigned_short(rbx, Address(rdi, 0));
3934 masm.load_unsigned_short(rcx, Address(rsi, 0));
3935 masm.cmpl(rbx, rcx);
3936 masm.jccb(Assembler::notEqual, RET_FALSE);
3937
3938 masm.bind(RET_TRUE);
3939 masm.movl(rax, 1); // return true
3940 masm.jmpb(DONE);
3941
3942 masm.bind(RET_FALSE);
3943 masm.xorl(rax, rax); // return false
3944
3945 masm.bind(DONE);
3946 %}
3947
3948 enc_class enc_String_IndexOf(eSIRegP str1, eDIRegP str2, regXD tmp1, eAXRegI tmp2,
3949 eCXRegI tmp3, eDXRegI tmp4, eBXRegI result) %{
3950 // SSE4.2 version
3951 Label LOAD_SUBSTR, PREP_FOR_SCAN, SCAN_TO_SUBSTR,
3952 SCAN_SUBSTR, RET_NEG_ONE, RET_NOT_FOUND, CLEANUP, DONE;
3953 MacroAssembler masm(&cbuf);
3954
3955 XMMRegister tmp1Reg = as_XMMRegister($tmp1$$reg);
3956
3957 // Get the first character position in both strings
3958 // [8] char array, [12] offset, [16] count
3959 int value_offset = java_lang_String::value_offset_in_bytes();
3960 int offset_offset = java_lang_String::offset_offset_in_bytes();
3961 int count_offset = java_lang_String::count_offset_in_bytes();
3962 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR);
3963
3964 // Get counts for string and substr
3965 masm.movl(rdx, Address(rsi, count_offset));
3966 masm.movl(rax, Address(rdi, count_offset));
3967 // Check for substr count > string count
3968 masm.cmpl(rax, rdx);
3969 masm.jcc(Assembler::greater, RET_NEG_ONE);
3970
3971 // Start the indexOf operation
3972 // Get start addr of string
3973 masm.movptr(rbx, Address(rsi, value_offset));
3974 masm.movl(rcx, Address(rsi, offset_offset));
3975 masm.lea(rsi, Address(rbx, rcx, Address::times_2, base_offset));
3976 masm.push(rsi);
3977
3978 // Get start addr of substr
3979 masm.movptr(rbx, Address(rdi, value_offset));
3980 masm.movl(rcx, Address(rdi, offset_offset));
3981 masm.lea(rdi, Address(rbx, rcx, Address::times_2, base_offset));
3982 masm.push(rdi);
3983 masm.push(rax);
3984 masm.jmpb(PREP_FOR_SCAN);
3985
3986 // Substr count saved at sp
3987 // Substr saved at sp+4
3988 // String saved at sp+8
3989
3990 // Prep to load substr for scan
3991 masm.bind(LOAD_SUBSTR);
3992 masm.movptr(rdi, Address(rsp, 4));
3993 masm.movl(rax, Address(rsp, 0));
3994
3995 // Load substr
3996 masm.bind(PREP_FOR_SCAN);
3997 masm.movdqu(tmp1Reg, Address(rdi, 0));
3998 masm.addl(rdx, 8); // prime the loop
3999 masm.subptr(rsi, 16);
4000
4001 // Scan string for substr in 16-byte vectors
4002 masm.bind(SCAN_TO_SUBSTR);
4003 masm.subl(rdx, 8);
4004 masm.addptr(rsi, 16);
4005 masm.pcmpestri(tmp1Reg, Address(rsi, 0), 0x0d);
4006 masm.jcc(Assembler::above, SCAN_TO_SUBSTR); // CF == 0 && ZF == 0
4007 masm.jccb(Assembler::aboveEqual, RET_NOT_FOUND); // CF == 0
4008
4009 // Fallthru: found a potential substr
4010
4011 // Make sure string is still long enough
4012 masm.subl(rdx, rcx);
4013 masm.cmpl(rdx, rax);
4014 masm.jccb(Assembler::negative, RET_NOT_FOUND);
4015 // Compute start addr of substr
4016 masm.lea(rsi, Address(rsi, rcx, Address::times_2));
4017 masm.movptr(rbx, rsi);
4018
4019 // Compare potential substr
4020 masm.addl(rdx, 8); // prime the loop
4021 masm.addl(rax, 8);
4022 masm.subptr(rsi, 16);
4023 masm.subptr(rdi, 16);
4024
4025 // Scan 16-byte vectors of string and substr
4026 masm.bind(SCAN_SUBSTR);
4027 masm.subl(rax, 8);
4028 masm.subl(rdx, 8);
4029 masm.addptr(rsi, 16);
4030 masm.addptr(rdi, 16);
4031 masm.movdqu(tmp1Reg, Address(rdi, 0));
4032 masm.pcmpestri(tmp1Reg, Address(rsi, 0), 0x0d);
4033 masm.jcc(Assembler::noOverflow, LOAD_SUBSTR); // OF == 0
4034 masm.jcc(Assembler::positive, SCAN_SUBSTR); // SF == 0
4035
4036 // Compute substr offset
4037 masm.movptr(rsi, Address(rsp, 8));
4038 masm.subptr(rbx, rsi);
4039 masm.shrl(rbx, 1);
4040 masm.jmpb(CLEANUP);
4041
4042 masm.bind(RET_NEG_ONE);
4043 masm.movl(rbx, -1);
4044 masm.jmpb(DONE);
4045
4046 masm.bind(RET_NOT_FOUND);
4047 masm.movl(rbx, -1);
4048
4049 masm.bind(CLEANUP);
4050 masm.addptr(rsp, 12);
4051
4052 masm.bind(DONE);
4053 %}
4054
4055 enc_class enc_Array_Equals(eDIRegP ary1, eSIRegP ary2, regXD tmp1, regXD tmp2,
4056 eBXRegI tmp3, eDXRegI tmp4, eAXRegI result) %{
4057 Label TRUE_LABEL, FALSE_LABEL, DONE, COMPARE_VECTORS, COMPARE_CHAR;
4058 MacroAssembler masm(&cbuf);
4059
4060 XMMRegister tmp1Reg = as_XMMRegister($tmp1$$reg);
4061 XMMRegister tmp2Reg = as_XMMRegister($tmp2$$reg);
4062 Register ary1Reg = as_Register($ary1$$reg);
4063 Register ary2Reg = as_Register($ary2$$reg);
4064 Register tmp3Reg = as_Register($tmp3$$reg);
4065 Register tmp4Reg = as_Register($tmp4$$reg);
4066 Register resultReg = as_Register($result$$reg);
4067
4068 int length_offset = arrayOopDesc::length_offset_in_bytes();
4069 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR);
4070
4071 // Check the input args
4072 masm.cmpptr(ary1Reg, ary2Reg);
4073 masm.jcc(Assembler::equal, TRUE_LABEL);
4074 masm.testptr(ary1Reg, ary1Reg);
4075 masm.jcc(Assembler::zero, FALSE_LABEL);
4076 masm.testptr(ary2Reg, ary2Reg);
4077 masm.jcc(Assembler::zero, FALSE_LABEL);
4078
4079 // Check the lengths
4080 masm.movl(tmp4Reg, Address(ary1Reg, length_offset));
4081 masm.movl(resultReg, Address(ary2Reg, length_offset));
4082 masm.cmpl(tmp4Reg, resultReg);
4083 masm.jcc(Assembler::notEqual, FALSE_LABEL);
4084 masm.testl(resultReg, resultReg);
4085 masm.jcc(Assembler::zero, TRUE_LABEL);
4086
4087 // Load array addrs
4088 masm.lea(ary1Reg, Address(ary1Reg, base_offset));
4089 masm.lea(ary2Reg, Address(ary2Reg, base_offset));
4090
4091 // Set byte count
4092 masm.shll(tmp4Reg, 1);
4093 masm.movl(resultReg, tmp4Reg);
4094
4095 if (UseSSE42Intrinsics) {
4096 // With SSE4.2, use double quad vector compare
4097 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
4098 // Compare 16-byte vectors
4099 masm.andl(tmp4Reg, 0xfffffff0); // vector count (in bytes)
4100 masm.andl(resultReg, 0x0000000e); // tail count (in bytes)
4101 masm.testl(tmp4Reg, tmp4Reg);
4102 masm.jccb(Assembler::zero, COMPARE_TAIL);
4103 masm.lea(ary1Reg, Address(ary1Reg, tmp4Reg, Address::times_1));
4104 masm.lea(ary2Reg, Address(ary2Reg, tmp4Reg, Address::times_1));
4105 masm.negl(tmp4Reg);
4106
4107 masm.bind(COMPARE_WIDE_VECTORS);
4108 masm.movdqu(tmp1Reg, Address(ary1Reg, tmp4Reg, Address::times_1));
4109 masm.movdqu(tmp2Reg, Address(ary2Reg, tmp4Reg, Address::times_1));
4110 masm.pxor(tmp1Reg, tmp2Reg);
4111 masm.ptest(tmp1Reg, tmp1Reg);
4112
4113 masm.jccb(Assembler::notZero, FALSE_LABEL);
4114 masm.addl(tmp4Reg, 16);
4115 masm.jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
4116 masm.bind(COMPARE_TAIL);
4117 masm.movl(tmp4Reg, resultReg);
4118 // Fallthru to tail compare
4119 }
4120
4121 // Compare 4-byte vectors
4122 masm.andl(tmp4Reg, 0xfffffffc); // vector count (in bytes)
4123 masm.andl(resultReg, 0x00000002); // tail char (in bytes)
4124 masm.testl(tmp4Reg, tmp4Reg);
4125 masm.jccb(Assembler::zero, COMPARE_CHAR);
4126 masm.lea(ary1Reg, Address(ary1Reg, tmp4Reg, Address::times_1));
4127 masm.lea(ary2Reg, Address(ary2Reg, tmp4Reg, Address::times_1));
4128 masm.negl(tmp4Reg);
4129
4130 masm.bind(COMPARE_VECTORS);
4131 masm.movl(tmp3Reg, Address(ary1Reg, tmp4Reg, Address::times_1));
4132 masm.cmpl(tmp3Reg, Address(ary2Reg, tmp4Reg, Address::times_1));
4133 masm.jccb(Assembler::notEqual, FALSE_LABEL);
4134 masm.addl(tmp4Reg, 4);
4135 masm.jcc(Assembler::notZero, COMPARE_VECTORS);
4136
4137 // Compare trailing char (final 2 bytes), if any
4138 masm.bind(COMPARE_CHAR);
4139 masm.testl(resultReg, resultReg);
4140 masm.jccb(Assembler::zero, TRUE_LABEL);
4141 masm.load_unsigned_short(tmp3Reg, Address(ary1Reg, 0));
4142 masm.load_unsigned_short(tmp4Reg, Address(ary2Reg, 0));
4143 masm.cmpl(tmp3Reg, tmp4Reg);
4144 masm.jccb(Assembler::notEqual, FALSE_LABEL);
4145
4146 masm.bind(TRUE_LABEL);
4147 masm.movl(resultReg, 1); // return true
4148 masm.jmpb(DONE);
4149
4150 masm.bind(FALSE_LABEL);
4151 masm.xorl(resultReg, resultReg); // return false
4152
4153 // That's it
4154 masm.bind(DONE);
4155 %}
4156
4157 enc_class enc_pop_rdx() %{
4158 emit_opcode(cbuf,0x5A);
4159 %}
4160
4161 enc_class enc_rethrow() %{
4162 cbuf.set_inst_mark();
4163 emit_opcode(cbuf, 0xE9); // jmp entry
4164 emit_d32_reloc(cbuf, (int)OptoRuntime::rethrow_stub() - ((int)cbuf.code_end())-4,
4165 runtime_call_Relocation::spec(), RELOC_IMM32 );
4166 %}
4167
4168
4169 // Convert a double to an int. Java semantics require we do complex
4170 // manglelations in the corner cases. So we set the rounding mode to
4171 // 'zero', store the darned double down as an int, and reset the
4172 // rounding mode to 'nearest'. The hardware throws an exception which
4173 // patches up the correct value directly to the stack.
4174 enc_class D2I_encoding( regD src ) %{
4175 // Flip to round-to-zero mode. We attempted to allow invalid-op
4176 // exceptions here, so that a NAN or other corner-case value will
4177 // thrown an exception (but normal values get converted at full speed).
4178 // However, I2C adapters and other float-stack manglers leave pending
4179 // invalid-op exceptions hanging. We would have to clear them before
4180 // enabling them and that is more expensive than just testing for the
4181 // invalid value Intel stores down in the corner cases.
4182 emit_opcode(cbuf,0xD9); // FLDCW trunc
4183 emit_opcode(cbuf,0x2D);
4184 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
4185 // Allocate a word
4186 emit_opcode(cbuf,0x83); // SUB ESP,4
4187 emit_opcode(cbuf,0xEC);
4188 emit_d8(cbuf,0x04);
4189 // Encoding assumes a double has been pushed into FPR0.
4190 // Store down the double as an int, popping the FPU stack
4191 emit_opcode(cbuf,0xDB); // FISTP [ESP]
4192 emit_opcode(cbuf,0x1C);
4193 emit_d8(cbuf,0x24);
4194 // Restore the rounding mode; mask the exception
4195 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode
4196 emit_opcode(cbuf,0x2D);
4197 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
4198 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
4199 : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
4200
4201 // Load the converted int; adjust CPU stack
4202 emit_opcode(cbuf,0x58); // POP EAX
4203 emit_opcode(cbuf,0x3D); // CMP EAX,imm
4204 emit_d32 (cbuf,0x80000000); // 0x80000000
4205 emit_opcode(cbuf,0x75); // JNE around_slow_call
4206 emit_d8 (cbuf,0x07); // Size of slow_call
4207 // Push src onto stack slow-path
4208 emit_opcode(cbuf,0xD9 ); // FLD ST(i)
4209 emit_d8 (cbuf,0xC0-1+$src$$reg );
4210 // CALL directly to the runtime
4211 cbuf.set_inst_mark();
4212 emit_opcode(cbuf,0xE8); // Call into runtime
4213 emit_d32_reloc(cbuf, (StubRoutines::d2i_wrapper() - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
4214 // Carry on here...
4215 %}
4216
4217 enc_class D2L_encoding( regD src ) %{
4218 emit_opcode(cbuf,0xD9); // FLDCW trunc
4219 emit_opcode(cbuf,0x2D);
4220 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
4221 // Allocate a word
4222 emit_opcode(cbuf,0x83); // SUB ESP,8
4223 emit_opcode(cbuf,0xEC);
4224 emit_d8(cbuf,0x08);
4225 // Encoding assumes a double has been pushed into FPR0.
4226 // Store down the double as a long, popping the FPU stack
4227 emit_opcode(cbuf,0xDF); // FISTP [ESP]
4228 emit_opcode(cbuf,0x3C);
4229 emit_d8(cbuf,0x24);
4230 // Restore the rounding mode; mask the exception
4231 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode
4232 emit_opcode(cbuf,0x2D);
4233 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
4234 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
4235 : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
4236
4237 // Load the converted int; adjust CPU stack
4238 emit_opcode(cbuf,0x58); // POP EAX
4239 emit_opcode(cbuf,0x5A); // POP EDX
4240 emit_opcode(cbuf,0x81); // CMP EDX,imm
4241 emit_d8 (cbuf,0xFA); // rdx
4242 emit_d32 (cbuf,0x80000000); // 0x80000000
4243 emit_opcode(cbuf,0x75); // JNE around_slow_call
4244 emit_d8 (cbuf,0x07+4); // Size of slow_call
4245 emit_opcode(cbuf,0x85); // TEST EAX,EAX
4246 emit_opcode(cbuf,0xC0); // 2/rax,/rax,
4247 emit_opcode(cbuf,0x75); // JNE around_slow_call
4248 emit_d8 (cbuf,0x07); // Size of slow_call
4249 // Push src onto stack slow-path
4250 emit_opcode(cbuf,0xD9 ); // FLD ST(i)
4251 emit_d8 (cbuf,0xC0-1+$src$$reg );
4252 // CALL directly to the runtime
4253 cbuf.set_inst_mark();
4254 emit_opcode(cbuf,0xE8); // Call into runtime
4255 emit_d32_reloc(cbuf, (StubRoutines::d2l_wrapper() - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
4256 // Carry on here...
4257 %}
4258
4259 enc_class X2L_encoding( regX src ) %{
4260 // Allocate a word
4261 emit_opcode(cbuf,0x83); // SUB ESP,8
4262 emit_opcode(cbuf,0xEC);
4263 emit_d8(cbuf,0x08);
4264
4265 emit_opcode (cbuf, 0xF3 ); // MOVSS [ESP], src
4266 emit_opcode (cbuf, 0x0F );
4267 emit_opcode (cbuf, 0x11 );
4268 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false);
4269
4270 emit_opcode(cbuf,0xD9 ); // FLD_S [ESP]
4271 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
4272
4273 emit_opcode(cbuf,0xD9); // FLDCW trunc
4274 emit_opcode(cbuf,0x2D);
4275 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
4276
4277 // Encoding assumes a double has been pushed into FPR0.
4278 // Store down the double as a long, popping the FPU stack
4279 emit_opcode(cbuf,0xDF); // FISTP [ESP]
4280 emit_opcode(cbuf,0x3C);
4281 emit_d8(cbuf,0x24);
4282
4283 // Restore the rounding mode; mask the exception
4284 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode
4285 emit_opcode(cbuf,0x2D);
4286 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
4287 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
4288 : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
4289
4290 // Load the converted int; adjust CPU stack
4291 emit_opcode(cbuf,0x58); // POP EAX
4292
4293 emit_opcode(cbuf,0x5A); // POP EDX
4294
4295 emit_opcode(cbuf,0x81); // CMP EDX,imm
4296 emit_d8 (cbuf,0xFA); // rdx
4297 emit_d32 (cbuf,0x80000000);// 0x80000000
4298
4299 emit_opcode(cbuf,0x75); // JNE around_slow_call
4300 emit_d8 (cbuf,0x13+4); // Size of slow_call
4301
4302 emit_opcode(cbuf,0x85); // TEST EAX,EAX
4303 emit_opcode(cbuf,0xC0); // 2/rax,/rax,
4304
4305 emit_opcode(cbuf,0x75); // JNE around_slow_call
4306 emit_d8 (cbuf,0x13); // Size of slow_call
4307
4308 // Allocate a word
4309 emit_opcode(cbuf,0x83); // SUB ESP,4
4310 emit_opcode(cbuf,0xEC);
4311 emit_d8(cbuf,0x04);
4312
4313 emit_opcode (cbuf, 0xF3 ); // MOVSS [ESP], src
4314 emit_opcode (cbuf, 0x0F );
4315 emit_opcode (cbuf, 0x11 );
4316 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false);
4317
4318 emit_opcode(cbuf,0xD9 ); // FLD_S [ESP]
4319 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
4320
4321 emit_opcode(cbuf,0x83); // ADD ESP,4
4322 emit_opcode(cbuf,0xC4);
4323 emit_d8(cbuf,0x04);
4324
4325 // CALL directly to the runtime
4326 cbuf.set_inst_mark();
4327 emit_opcode(cbuf,0xE8); // Call into runtime
4328 emit_d32_reloc(cbuf, (StubRoutines::d2l_wrapper() - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
4329 // Carry on here...
4330 %}
4331
4332 enc_class XD2L_encoding( regXD src ) %{
4333 // Allocate a word
4334 emit_opcode(cbuf,0x83); // SUB ESP,8
4335 emit_opcode(cbuf,0xEC);
4336 emit_d8(cbuf,0x08);
4337
4338 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], src
4339 emit_opcode (cbuf, 0x0F );
4340 emit_opcode (cbuf, 0x11 );
4341 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false);
4342
4343 emit_opcode(cbuf,0xDD ); // FLD_D [ESP]
4344 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
4345
4346 emit_opcode(cbuf,0xD9); // FLDCW trunc
4347 emit_opcode(cbuf,0x2D);
4348 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
4349
4350 // Encoding assumes a double has been pushed into FPR0.
4351 // Store down the double as a long, popping the FPU stack
4352 emit_opcode(cbuf,0xDF); // FISTP [ESP]
4353 emit_opcode(cbuf,0x3C);
4354 emit_d8(cbuf,0x24);
4355
4356 // Restore the rounding mode; mask the exception
4357 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode
4358 emit_opcode(cbuf,0x2D);
4359 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
4360 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
4361 : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
4362
4363 // Load the converted int; adjust CPU stack
4364 emit_opcode(cbuf,0x58); // POP EAX
4365
4366 emit_opcode(cbuf,0x5A); // POP EDX
4367
4368 emit_opcode(cbuf,0x81); // CMP EDX,imm
4369 emit_d8 (cbuf,0xFA); // rdx
4370 emit_d32 (cbuf,0x80000000); // 0x80000000
4371
4372 emit_opcode(cbuf,0x75); // JNE around_slow_call
4373 emit_d8 (cbuf,0x13+4); // Size of slow_call
4374
4375 emit_opcode(cbuf,0x85); // TEST EAX,EAX
4376 emit_opcode(cbuf,0xC0); // 2/rax,/rax,
4377
4378 emit_opcode(cbuf,0x75); // JNE around_slow_call
4379 emit_d8 (cbuf,0x13); // Size of slow_call
4380
4381 // Push src onto stack slow-path
4382 // Allocate a word
4383 emit_opcode(cbuf,0x83); // SUB ESP,8
4384 emit_opcode(cbuf,0xEC);
4385 emit_d8(cbuf,0x08);
4386
4387 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], src
4388 emit_opcode (cbuf, 0x0F );
4389 emit_opcode (cbuf, 0x11 );
4390 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false);
4391
4392 emit_opcode(cbuf,0xDD ); // FLD_D [ESP]
4393 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
4394
4395 emit_opcode(cbuf,0x83); // ADD ESP,8
4396 emit_opcode(cbuf,0xC4);
4397 emit_d8(cbuf,0x08);
4398
4399 // CALL directly to the runtime
4400 cbuf.set_inst_mark();
4401 emit_opcode(cbuf,0xE8); // Call into runtime
4402 emit_d32_reloc(cbuf, (StubRoutines::d2l_wrapper() - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
4403 // Carry on here...
4404 %}
4405
4406 enc_class D2X_encoding( regX dst, regD src ) %{
4407 // Allocate a word
4408 emit_opcode(cbuf,0x83); // SUB ESP,4
4409 emit_opcode(cbuf,0xEC);
4410 emit_d8(cbuf,0x04);
4411 int pop = 0x02;
4412 if ($src$$reg != FPR1L_enc) {
4413 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
4414 emit_d8( cbuf, 0xC0-1+$src$$reg );
4415 pop = 0x03;
4416 }
4417 store_to_stackslot( cbuf, 0xD9, pop, 0 ); // FST<P>_S [ESP]
4418
4419 emit_opcode (cbuf, 0xF3 ); // MOVSS dst(xmm), [ESP]
4420 emit_opcode (cbuf, 0x0F );
4421 emit_opcode (cbuf, 0x10 );
4422 encode_RegMem(cbuf, $dst$$reg, ESP_enc, 0x4, 0, 0, false);
4423
4424 emit_opcode(cbuf,0x83); // ADD ESP,4
4425 emit_opcode(cbuf,0xC4);
4426 emit_d8(cbuf,0x04);
4427 // Carry on here...
4428 %}
4429
4430 enc_class FX2I_encoding( regX src, eRegI dst ) %{
4431 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
4432
4433 // Compare the result to see if we need to go to the slow path
4434 emit_opcode(cbuf,0x81); // CMP dst,imm
4435 emit_rm (cbuf,0x3,0x7,$dst$$reg);
4436 emit_d32 (cbuf,0x80000000); // 0x80000000
4437
4438 emit_opcode(cbuf,0x75); // JNE around_slow_call
4439 emit_d8 (cbuf,0x13); // Size of slow_call
4440 // Store xmm to a temp memory
4441 // location and push it onto stack.
4442
4443 emit_opcode(cbuf,0x83); // SUB ESP,4
4444 emit_opcode(cbuf,0xEC);
4445 emit_d8(cbuf, $primary ? 0x8 : 0x4);
4446
4447 emit_opcode (cbuf, $primary ? 0xF2 : 0xF3 ); // MOVSS [ESP], xmm
4448 emit_opcode (cbuf, 0x0F );
4449 emit_opcode (cbuf, 0x11 );
4450 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false);
4451
4452 emit_opcode(cbuf, $primary ? 0xDD : 0xD9 ); // FLD [ESP]
4453 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
4454
4455 emit_opcode(cbuf,0x83); // ADD ESP,4
4456 emit_opcode(cbuf,0xC4);
4457 emit_d8(cbuf, $primary ? 0x8 : 0x4);
4458
4459 // CALL directly to the runtime
4460 cbuf.set_inst_mark();
4461 emit_opcode(cbuf,0xE8); // Call into runtime
4462 emit_d32_reloc(cbuf, (StubRoutines::d2i_wrapper() - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
4463
4464 // Carry on here...
4465 %}
4466
4467 enc_class X2D_encoding( regD dst, regX src ) %{
4468 // Allocate a word
4469 emit_opcode(cbuf,0x83); // SUB ESP,4
4470 emit_opcode(cbuf,0xEC);
4471 emit_d8(cbuf,0x04);
4472
4473 emit_opcode (cbuf, 0xF3 ); // MOVSS [ESP], xmm
4474 emit_opcode (cbuf, 0x0F );
4475 emit_opcode (cbuf, 0x11 );
4476 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false);
4477
4478 emit_opcode(cbuf,0xD9 ); // FLD_S [ESP]
4479 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
4480
4481 emit_opcode(cbuf,0x83); // ADD ESP,4
4482 emit_opcode(cbuf,0xC4);
4483 emit_d8(cbuf,0x04);
4484
4485 // Carry on here...
4486 %}
4487
4488 enc_class AbsXF_encoding(regX dst) %{
4489 address signmask_address=(address)float_signmask_pool;
4490 // andpd:\tANDPS $dst,[signconst]
4491 emit_opcode(cbuf, 0x0F);
4492 emit_opcode(cbuf, 0x54);
4493 emit_rm(cbuf, 0x0, $dst$$reg, 0x5);
4494 emit_d32(cbuf, (int)signmask_address);
4495 %}
4496
4497 enc_class AbsXD_encoding(regXD dst) %{
4498 address signmask_address=(address)double_signmask_pool;
4499 // andpd:\tANDPD $dst,[signconst]
4500 emit_opcode(cbuf, 0x66);
4501 emit_opcode(cbuf, 0x0F);
4502 emit_opcode(cbuf, 0x54);
4503 emit_rm(cbuf, 0x0, $dst$$reg, 0x5);
4504 emit_d32(cbuf, (int)signmask_address);
4505 %}
4506
4507 enc_class NegXF_encoding(regX dst) %{
4508 address signmask_address=(address)float_signflip_pool;
4509 // andpd:\tXORPS $dst,[signconst]
4510 emit_opcode(cbuf, 0x0F);
4511 emit_opcode(cbuf, 0x57);
4512 emit_rm(cbuf, 0x0, $dst$$reg, 0x5);
4513 emit_d32(cbuf, (int)signmask_address);
4514 %}
4515
4516 enc_class NegXD_encoding(regXD dst) %{
4517 address signmask_address=(address)double_signflip_pool;
4518 // andpd:\tXORPD $dst,[signconst]
4519 emit_opcode(cbuf, 0x66);
4520 emit_opcode(cbuf, 0x0F);
4521 emit_opcode(cbuf, 0x57);
4522 emit_rm(cbuf, 0x0, $dst$$reg, 0x5);
4523 emit_d32(cbuf, (int)signmask_address);
4524 %}
4525
4526 enc_class FMul_ST_reg( eRegF src1 ) %{
4527 // Operand was loaded from memory into fp ST (stack top)
4528 // FMUL ST,$src /* D8 C8+i */
4529 emit_opcode(cbuf, 0xD8);
4530 emit_opcode(cbuf, 0xC8 + $src1$$reg);
4531 %}
4532
4533 enc_class FAdd_ST_reg( eRegF src2 ) %{
4534 // FADDP ST,src2 /* D8 C0+i */
4535 emit_opcode(cbuf, 0xD8);
4536 emit_opcode(cbuf, 0xC0 + $src2$$reg);
4537 //could use FADDP src2,fpST /* DE C0+i */
4538 %}
4539
4540 enc_class FAddP_reg_ST( eRegF src2 ) %{
4541 // FADDP src2,ST /* DE C0+i */
4542 emit_opcode(cbuf, 0xDE);
4543 emit_opcode(cbuf, 0xC0 + $src2$$reg);
4544 %}
4545
4546 enc_class subF_divF_encode( eRegF src1, eRegF src2) %{
4547 // Operand has been loaded into fp ST (stack top)
4548 // FSUB ST,$src1
4549 emit_opcode(cbuf, 0xD8);
4550 emit_opcode(cbuf, 0xE0 + $src1$$reg);
4551
4552 // FDIV
4553 emit_opcode(cbuf, 0xD8);
4554 emit_opcode(cbuf, 0xF0 + $src2$$reg);
4555 %}
4556
4557 enc_class MulFAddF (eRegF src1, eRegF src2) %{
4558 // Operand was loaded from memory into fp ST (stack top)
4559 // FADD ST,$src /* D8 C0+i */
4560 emit_opcode(cbuf, 0xD8);
4561 emit_opcode(cbuf, 0xC0 + $src1$$reg);
4562
4563 // FMUL ST,src2 /* D8 C*+i */
4564 emit_opcode(cbuf, 0xD8);
4565 emit_opcode(cbuf, 0xC8 + $src2$$reg);
4566 %}
4567
4568
4569 enc_class MulFAddFreverse (eRegF src1, eRegF src2) %{
4570 // Operand was loaded from memory into fp ST (stack top)
4571 // FADD ST,$src /* D8 C0+i */
4572 emit_opcode(cbuf, 0xD8);
4573 emit_opcode(cbuf, 0xC0 + $src1$$reg);
4574
4575 // FMULP src2,ST /* DE C8+i */
4576 emit_opcode(cbuf, 0xDE);
4577 emit_opcode(cbuf, 0xC8 + $src2$$reg);
4578 %}
4579
4580 // Atomically load the volatile long
4581 enc_class enc_loadL_volatile( memory mem, stackSlotL dst ) %{
4582 emit_opcode(cbuf,0xDF);
4583 int rm_byte_opcode = 0x05;
4584 int base = $mem$$base;
4585 int index = $mem$$index;
4586 int scale = $mem$$scale;
4587 int displace = $mem$$disp;
4588 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
4589 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_is_oop);
4590 store_to_stackslot( cbuf, 0x0DF, 0x07, $dst$$disp );
4591 %}
4592
4593 enc_class enc_loadLX_volatile( memory mem, stackSlotL dst, regXD tmp ) %{
4594 { // Atomic long load
4595 // UseXmmLoadAndClearUpper ? movsd $tmp,$mem : movlpd $tmp,$mem
4596 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0xF2 : 0x66);
4597 emit_opcode(cbuf,0x0F);
4598 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0x10 : 0x12);
4599 int base = $mem$$base;
4600 int index = $mem$$index;
4601 int scale = $mem$$scale;
4602 int displace = $mem$$disp;
4603 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
4604 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop);
4605 }
4606 { // MOVSD $dst,$tmp ! atomic long store
4607 emit_opcode(cbuf,0xF2);
4608 emit_opcode(cbuf,0x0F);
4609 emit_opcode(cbuf,0x11);
4610 int base = $dst$$base;
4611 int index = $dst$$index;
4612 int scale = $dst$$scale;
4613 int displace = $dst$$disp;
4614 bool disp_is_oop = $dst->disp_is_oop(); // disp-as-oop when working with static globals
4615 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop);
4616 }
4617 %}
4618
4619 enc_class enc_loadLX_reg_volatile( memory mem, eRegL dst, regXD tmp ) %{
4620 { // Atomic long load
4621 // UseXmmLoadAndClearUpper ? movsd $tmp,$mem : movlpd $tmp,$mem
4622 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0xF2 : 0x66);
4623 emit_opcode(cbuf,0x0F);
4624 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0x10 : 0x12);
4625 int base = $mem$$base;
4626 int index = $mem$$index;
4627 int scale = $mem$$scale;
4628 int displace = $mem$$disp;
4629 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
4630 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop);
4631 }
4632 { // MOVD $dst.lo,$tmp
4633 emit_opcode(cbuf,0x66);
4634 emit_opcode(cbuf,0x0F);
4635 emit_opcode(cbuf,0x7E);
4636 emit_rm(cbuf, 0x3, $tmp$$reg, $dst$$reg);
4637 }
4638 { // PSRLQ $tmp,32
4639 emit_opcode(cbuf,0x66);
4640 emit_opcode(cbuf,0x0F);
4641 emit_opcode(cbuf,0x73);
4642 emit_rm(cbuf, 0x3, 0x02, $tmp$$reg);
4643 emit_d8(cbuf, 0x20);
4644 }
4645 { // MOVD $dst.hi,$tmp
4646 emit_opcode(cbuf,0x66);
4647 emit_opcode(cbuf,0x0F);
4648 emit_opcode(cbuf,0x7E);
4649 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg));
4650 }
4651 %}
4652
4653 // Volatile Store Long. Must be atomic, so move it into
4654 // the FP TOS and then do a 64-bit FIST. Has to probe the
4655 // target address before the store (for null-ptr checks)
4656 // so the memory operand is used twice in the encoding.
4657 enc_class enc_storeL_volatile( memory mem, stackSlotL src ) %{
4658 store_to_stackslot( cbuf, 0x0DF, 0x05, $src$$disp );
4659 cbuf.set_inst_mark(); // Mark start of FIST in case $mem has an oop
4660 emit_opcode(cbuf,0xDF);
4661 int rm_byte_opcode = 0x07;
4662 int base = $mem$$base;
4663 int index = $mem$$index;
4664 int scale = $mem$$scale;
4665 int displace = $mem$$disp;
4666 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
4667 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_is_oop);
4668 %}
4669
4670 enc_class enc_storeLX_volatile( memory mem, stackSlotL src, regXD tmp) %{
4671 { // Atomic long load
4672 // UseXmmLoadAndClearUpper ? movsd $tmp,[$src] : movlpd $tmp,[$src]
4673 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0xF2 : 0x66);
4674 emit_opcode(cbuf,0x0F);
4675 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0x10 : 0x12);
4676 int base = $src$$base;
4677 int index = $src$$index;
4678 int scale = $src$$scale;
4679 int displace = $src$$disp;
4680 bool disp_is_oop = $src->disp_is_oop(); // disp-as-oop when working with static globals
4681 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop);
4682 }
4683 cbuf.set_inst_mark(); // Mark start of MOVSD in case $mem has an oop
4684 { // MOVSD $mem,$tmp ! atomic long store
4685 emit_opcode(cbuf,0xF2);
4686 emit_opcode(cbuf,0x0F);
4687 emit_opcode(cbuf,0x11);
4688 int base = $mem$$base;
4689 int index = $mem$$index;
4690 int scale = $mem$$scale;
4691 int displace = $mem$$disp;
4692 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
4693 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop);
4694 }
4695 %}
4696
4697 enc_class enc_storeLX_reg_volatile( memory mem, eRegL src, regXD tmp, regXD tmp2) %{
4698 { // MOVD $tmp,$src.lo
4699 emit_opcode(cbuf,0x66);
4700 emit_opcode(cbuf,0x0F);
4701 emit_opcode(cbuf,0x6E);
4702 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg);
4703 }
4704 { // MOVD $tmp2,$src.hi
4705 emit_opcode(cbuf,0x66);
4706 emit_opcode(cbuf,0x0F);
4707 emit_opcode(cbuf,0x6E);
4708 emit_rm(cbuf, 0x3, $tmp2$$reg, HIGH_FROM_LOW($src$$reg));
4709 }
4710 { // PUNPCKLDQ $tmp,$tmp2
4711 emit_opcode(cbuf,0x66);
4712 emit_opcode(cbuf,0x0F);
4713 emit_opcode(cbuf,0x62);
4714 emit_rm(cbuf, 0x3, $tmp$$reg, $tmp2$$reg);
4715 }
4716 cbuf.set_inst_mark(); // Mark start of MOVSD in case $mem has an oop
4717 { // MOVSD $mem,$tmp ! atomic long store
4718 emit_opcode(cbuf,0xF2);
4719 emit_opcode(cbuf,0x0F);
4720 emit_opcode(cbuf,0x11);
4721 int base = $mem$$base;
4722 int index = $mem$$index;
4723 int scale = $mem$$scale;
4724 int displace = $mem$$disp;
4725 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
4726 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop);
4727 }
4728 %}
4729
4730 // Safepoint Poll. This polls the safepoint page, and causes an
4731 // exception if it is not readable. Unfortunately, it kills the condition code
4732 // in the process
4733 // We current use TESTL [spp],EDI
4734 // A better choice might be TESTB [spp + pagesize() - CacheLineSize()],0
4735
4736 enc_class Safepoint_Poll() %{
4737 cbuf.relocate(cbuf.inst_mark(), relocInfo::poll_type, 0);
4738 emit_opcode(cbuf,0x85);
4739 emit_rm (cbuf, 0x0, 0x7, 0x5);
4740 emit_d32(cbuf, (intptr_t)os::get_polling_page());
4741 %}
4742 %}
4743
4744
4745 //----------FRAME--------------------------------------------------------------
4746 // Definition of frame structure and management information.
4747 //
4748 // S T A C K L A Y O U T Allocators stack-slot number
4749 // | (to get allocators register number
4750 // G Owned by | | v add OptoReg::stack0())
4751 // r CALLER | |
4752 // o | +--------+ pad to even-align allocators stack-slot
4753 // w V | pad0 | numbers; owned by CALLER
4754 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
4755 // h ^ | in | 5
4756 // | | args | 4 Holes in incoming args owned by SELF
4757 // | | | | 3
4758 // | | +--------+
4759 // V | | old out| Empty on Intel, window on Sparc
4760 // | old |preserve| Must be even aligned.
4761 // | SP-+--------+----> Matcher::_old_SP, even aligned
4762 // | | in | 3 area for Intel ret address
4763 // Owned by |preserve| Empty on Sparc.
4764 // SELF +--------+
4765 // | | pad2 | 2 pad to align old SP
4766 // | +--------+ 1
4767 // | | locks | 0
4768 // | +--------+----> OptoReg::stack0(), even aligned
4769 // | | pad1 | 11 pad to align new SP
4770 // | +--------+
4771 // | | | 10
4772 // | | spills | 9 spills
4773 // V | | 8 (pad0 slot for callee)
4774 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
4775 // ^ | out | 7
4776 // | | args | 6 Holes in outgoing args owned by CALLEE
4777 // Owned by +--------+
4778 // CALLEE | new out| 6 Empty on Intel, window on Sparc
4779 // | new |preserve| Must be even-aligned.
4780 // | SP-+--------+----> Matcher::_new_SP, even aligned
4781 // | | |
4782 //
4783 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
4784 // known from SELF's arguments and the Java calling convention.
4785 // Region 6-7 is determined per call site.
4786 // Note 2: If the calling convention leaves holes in the incoming argument
4787 // area, those holes are owned by SELF. Holes in the outgoing area
4788 // are owned by the CALLEE. Holes should not be nessecary in the
4789 // incoming area, as the Java calling convention is completely under
4790 // the control of the AD file. Doubles can be sorted and packed to
4791 // avoid holes. Holes in the outgoing arguments may be nessecary for
4792 // varargs C calling conventions.
4793 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
4794 // even aligned with pad0 as needed.
4795 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
4796 // region 6-11 is even aligned; it may be padded out more so that
4797 // the region from SP to FP meets the minimum stack alignment.
4798
4799 frame %{
4800 // What direction does stack grow in (assumed to be same for C & Java)
4801 stack_direction(TOWARDS_LOW);
4802
4803 // These three registers define part of the calling convention
4804 // between compiled code and the interpreter.
4805 inline_cache_reg(EAX); // Inline Cache Register
4806 interpreter_method_oop_reg(EBX); // Method Oop Register when calling interpreter
4807
4808 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
4809 cisc_spilling_operand_name(indOffset32);
4810
4811 // Number of stack slots consumed by locking an object
4812 sync_stack_slots(1);
4813
4814 // Compiled code's Frame Pointer
4815 frame_pointer(ESP);
4816 // Interpreter stores its frame pointer in a register which is
4817 // stored to the stack by I2CAdaptors.
4818 // I2CAdaptors convert from interpreted java to compiled java.
4819 interpreter_frame_pointer(EBP);
4820
4821 // Stack alignment requirement
4822 // Alignment size in bytes (128-bit -> 16 bytes)
4823 stack_alignment(StackAlignmentInBytes);
4824
4825 // Number of stack slots between incoming argument block and the start of
4826 // a new frame. The PROLOG must add this many slots to the stack. The
4827 // EPILOG must remove this many slots. Intel needs one slot for
4828 // return address and one for rbp, (must save rbp)
4829 in_preserve_stack_slots(2+VerifyStackAtCalls);
4830
4831 // Number of outgoing stack slots killed above the out_preserve_stack_slots
4832 // for calls to C. Supports the var-args backing area for register parms.
4833 varargs_C_out_slots_killed(0);
4834
4835 // The after-PROLOG location of the return address. Location of
4836 // return address specifies a type (REG or STACK) and a number
4837 // representing the register number (i.e. - use a register name) or
4838 // stack slot.
4839 // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
4840 // Otherwise, it is above the locks and verification slot and alignment word
4841 return_addr(STACK - 1 +
4842 round_to(1+VerifyStackAtCalls+
4843 Compile::current()->fixed_slots(),
4844 (StackAlignmentInBytes/wordSize)));
4845
4846 // Body of function which returns an integer array locating
4847 // arguments either in registers or in stack slots. Passed an array
4848 // of ideal registers called "sig" and a "length" count. Stack-slot
4849 // offsets are based on outgoing arguments, i.e. a CALLER setting up
4850 // arguments for a CALLEE. Incoming stack arguments are
4851 // automatically biased by the preserve_stack_slots field above.
4852 calling_convention %{
4853 // No difference between ingoing/outgoing just pass false
4854 SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
4855 %}
4856
4857
4858 // Body of function which returns an integer array locating
4859 // arguments either in registers or in stack slots. Passed an array
4860 // of ideal registers called "sig" and a "length" count. Stack-slot
4861 // offsets are based on outgoing arguments, i.e. a CALLER setting up
4862 // arguments for a CALLEE. Incoming stack arguments are
4863 // automatically biased by the preserve_stack_slots field above.
4864 c_calling_convention %{
4865 // This is obviously always outgoing
4866 (void) SharedRuntime::c_calling_convention(sig_bt, regs, length);
4867 %}
4868
4869 // Location of C & interpreter return values
4870 c_return_value %{
4871 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
4872 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num };
4873 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num };
4874
4875 // in SSE2+ mode we want to keep the FPU stack clean so pretend
4876 // that C functions return float and double results in XMM0.
4877 if( ideal_reg == Op_RegD && UseSSE>=2 )
4878 return OptoRegPair(XMM0b_num,XMM0a_num);
4879 if( ideal_reg == Op_RegF && UseSSE>=2 )
4880 return OptoRegPair(OptoReg::Bad,XMM0a_num);
4881
4882 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]);
4883 %}
4884
4885 // Location of return values
4886 return_value %{
4887 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
4888 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num };
4889 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num };
4890 if( ideal_reg == Op_RegD && UseSSE>=2 )
4891 return OptoRegPair(XMM0b_num,XMM0a_num);
4892 if( ideal_reg == Op_RegF && UseSSE>=1 )
4893 return OptoRegPair(OptoReg::Bad,XMM0a_num);
4894 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]);
4895 %}
4896
4897 %}
4898
4899 //----------ATTRIBUTES---------------------------------------------------------
4900 //----------Operand Attributes-------------------------------------------------
4901 op_attrib op_cost(0); // Required cost attribute
4902
4903 //----------Instruction Attributes---------------------------------------------
4904 ins_attrib ins_cost(100); // Required cost attribute
4905 ins_attrib ins_size(8); // Required size attribute (in bits)
4906 ins_attrib ins_pc_relative(0); // Required PC Relative flag
4907 ins_attrib ins_short_branch(0); // Required flag: is this instruction a
4908 // non-matching short branch variant of some
4909 // long branch?
4910 ins_attrib ins_alignment(1); // Required alignment attribute (must be a power of 2)
4911 // specifies the alignment that some part of the instruction (not
4912 // necessarily the start) requires. If > 1, a compute_padding()
4913 // function must be provided for the instruction
4914
4915 //----------OPERANDS-----------------------------------------------------------
4916 // Operand definitions must precede instruction definitions for correct parsing
4917 // in the ADLC because operands constitute user defined types which are used in
4918 // instruction definitions.
4919
4920 //----------Simple Operands----------------------------------------------------
4921 // Immediate Operands
4922 // Integer Immediate
4923 operand immI() %{
4924 match(ConI);
4925
4926 op_cost(10);
4927 format %{ %}
4928 interface(CONST_INTER);
4929 %}
4930
4931 // Constant for test vs zero
4932 operand immI0() %{
4933 predicate(n->get_int() == 0);
4934 match(ConI);
4935
4936 op_cost(0);
4937 format %{ %}
4938 interface(CONST_INTER);
4939 %}
4940
4941 // Constant for increment
4942 operand immI1() %{
4943 predicate(n->get_int() == 1);
4944 match(ConI);
4945
4946 op_cost(0);
4947 format %{ %}
4948 interface(CONST_INTER);
4949 %}
4950
4951 // Constant for decrement
4952 operand immI_M1() %{
4953 predicate(n->get_int() == -1);
4954 match(ConI);
4955
4956 op_cost(0);
4957 format %{ %}
4958 interface(CONST_INTER);
4959 %}
4960
4961 // Valid scale values for addressing modes
4962 operand immI2() %{
4963 predicate(0 <= n->get_int() && (n->get_int() <= 3));
4964 match(ConI);
4965
4966 format %{ %}
4967 interface(CONST_INTER);
4968 %}
4969
4970 operand immI8() %{
4971 predicate((-128 <= n->get_int()) && (n->get_int() <= 127));
4972 match(ConI);
4973
4974 op_cost(5);
4975 format %{ %}
4976 interface(CONST_INTER);
4977 %}
4978
4979 operand immI16() %{
4980 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767));
4981 match(ConI);
4982
4983 op_cost(10);
4984 format %{ %}
4985 interface(CONST_INTER);
4986 %}
4987
4988 // Constant for long shifts
4989 operand immI_32() %{
4990 predicate( n->get_int() == 32 );
4991 match(ConI);
4992
4993 op_cost(0);
4994 format %{ %}
4995 interface(CONST_INTER);
4996 %}
4997
4998 operand immI_1_31() %{
4999 predicate( n->get_int() >= 1 && n->get_int() <= 31 );
5000 match(ConI);
5001
5002 op_cost(0);
5003 format %{ %}
5004 interface(CONST_INTER);
5005 %}
5006
5007 operand immI_32_63() %{
5008 predicate( n->get_int() >= 32 && n->get_int() <= 63 );
5009 match(ConI);
5010 op_cost(0);
5011
5012 format %{ %}
5013 interface(CONST_INTER);
5014 %}
5015
5016 operand immI_1() %{
5017 predicate( n->get_int() == 1 );
5018 match(ConI);
5019
5020 op_cost(0);
5021 format %{ %}
5022 interface(CONST_INTER);
5023 %}
5024
5025 operand immI_2() %{
5026 predicate( n->get_int() == 2 );
5027 match(ConI);
5028
5029 op_cost(0);
5030 format %{ %}
5031 interface(CONST_INTER);
5032 %}
5033
5034 operand immI_3() %{
5035 predicate( n->get_int() == 3 );
5036 match(ConI);
5037
5038 op_cost(0);
5039 format %{ %}
5040 interface(CONST_INTER);
5041 %}
5042
5043 // Pointer Immediate
5044 operand immP() %{
5045 match(ConP);
5046
5047 op_cost(10);
5048 format %{ %}
5049 interface(CONST_INTER);
5050 %}
5051
5052 // NULL Pointer Immediate
5053 operand immP0() %{
5054 predicate( n->get_ptr() == 0 );
5055 match(ConP);
5056 op_cost(0);
5057
5058 format %{ %}
5059 interface(CONST_INTER);
5060 %}
5061
5062 // Long Immediate
5063 operand immL() %{
5064 match(ConL);
5065
5066 op_cost(20);
5067 format %{ %}
5068 interface(CONST_INTER);
5069 %}
5070
5071 // Long Immediate zero
5072 operand immL0() %{
5073 predicate( n->get_long() == 0L );
5074 match(ConL);
5075 op_cost(0);
5076
5077 format %{ %}
5078 interface(CONST_INTER);
5079 %}
5080
5081 // Long Immediate zero
5082 operand immL_M1() %{
5083 predicate( n->get_long() == -1L );
5084 match(ConL);
5085 op_cost(0);
5086
5087 format %{ %}
5088 interface(CONST_INTER);
5089 %}
5090
5091 // Long immediate from 0 to 127.
5092 // Used for a shorter form of long mul by 10.
5093 operand immL_127() %{
5094 predicate((0 <= n->get_long()) && (n->get_long() <= 127));
5095 match(ConL);
5096 op_cost(0);
5097
5098 format %{ %}
5099 interface(CONST_INTER);
5100 %}
5101
5102 // Long Immediate: low 32-bit mask
5103 operand immL_32bits() %{
5104 predicate(n->get_long() == 0xFFFFFFFFL);
5105 match(ConL);
5106 op_cost(0);
5107
5108 format %{ %}
5109 interface(CONST_INTER);
5110 %}
5111
5112 // Long Immediate: low 32-bit mask
5113 operand immL32() %{
5114 predicate(n->get_long() == (int)(n->get_long()));
5115 match(ConL);
5116 op_cost(20);
5117
5118 format %{ %}
5119 interface(CONST_INTER);
5120 %}
5121
5122 //Double Immediate zero
5123 operand immD0() %{
5124 // Do additional (and counter-intuitive) test against NaN to work around VC++
5125 // bug that generates code such that NaNs compare equal to 0.0
5126 predicate( UseSSE<=1 && n->getd() == 0.0 && !g_isnan(n->getd()) );
5127 match(ConD);
5128
5129 op_cost(5);
5130 format %{ %}
5131 interface(CONST_INTER);
5132 %}
5133
5134 // Double Immediate
5135 operand immD1() %{
5136 predicate( UseSSE<=1 && n->getd() == 1.0 );
5137 match(ConD);
5138
5139 op_cost(5);
5140 format %{ %}
5141 interface(CONST_INTER);
5142 %}
5143
5144 // Double Immediate
5145 operand immD() %{
5146 predicate(UseSSE<=1);
5147 match(ConD);
5148
5149 op_cost(5);
5150 format %{ %}
5151 interface(CONST_INTER);
5152 %}
5153
5154 operand immXD() %{
5155 predicate(UseSSE>=2);
5156 match(ConD);
5157
5158 op_cost(5);
5159 format %{ %}
5160 interface(CONST_INTER);
5161 %}
5162
5163 // Double Immediate zero
5164 operand immXD0() %{
5165 // Do additional (and counter-intuitive) test against NaN to work around VC++
5166 // bug that generates code such that NaNs compare equal to 0.0 AND do not
5167 // compare equal to -0.0.
5168 predicate( UseSSE>=2 && jlong_cast(n->getd()) == 0 );
5169 match(ConD);
5170
5171 format %{ %}
5172 interface(CONST_INTER);
5173 %}
5174
5175 // Float Immediate zero
5176 operand immF0() %{
5177 predicate( UseSSE == 0 && n->getf() == 0.0 );
5178 match(ConF);
5179
5180 op_cost(5);
5181 format %{ %}
5182 interface(CONST_INTER);
5183 %}
5184
5185 // Float Immediate
5186 operand immF() %{
5187 predicate( UseSSE == 0 );
5188 match(ConF);
5189
5190 op_cost(5);
5191 format %{ %}
5192 interface(CONST_INTER);
5193 %}
5194
5195 // Float Immediate
5196 operand immXF() %{
5197 predicate(UseSSE >= 1);
5198 match(ConF);
5199
5200 op_cost(5);
5201 format %{ %}
5202 interface(CONST_INTER);
5203 %}
5204
5205 // Float Immediate zero. Zero and not -0.0
5206 operand immXF0() %{
5207 predicate( UseSSE >= 1 && jint_cast(n->getf()) == 0 );
5208 match(ConF);
5209
5210 op_cost(5);
5211 format %{ %}
5212 interface(CONST_INTER);
5213 %}
5214
5215 // Immediates for special shifts (sign extend)
5216
5217 // Constants for increment
5218 operand immI_16() %{
5219 predicate( n->get_int() == 16 );
5220 match(ConI);
5221
5222 format %{ %}
5223 interface(CONST_INTER);
5224 %}
5225
5226 operand immI_24() %{
5227 predicate( n->get_int() == 24 );
5228 match(ConI);
5229
5230 format %{ %}
5231 interface(CONST_INTER);
5232 %}
5233
5234 // Constant for byte-wide masking
5235 operand immI_255() %{
5236 predicate( n->get_int() == 255 );
5237 match(ConI);
5238
5239 format %{ %}
5240 interface(CONST_INTER);
5241 %}
5242
5243 // Constant for short-wide masking
5244 operand immI_65535() %{
5245 predicate(n->get_int() == 65535);
5246 match(ConI);
5247
5248 format %{ %}
5249 interface(CONST_INTER);
5250 %}
5251
5252 // Register Operands
5253 // Integer Register
5254 operand eRegI() %{
5255 constraint(ALLOC_IN_RC(e_reg));
5256 match(RegI);
5257 match(xRegI);
5258 match(eAXRegI);
5259 match(eBXRegI);
5260 match(eCXRegI);
5261 match(eDXRegI);
5262 match(eDIRegI);
5263 match(eSIRegI);
5264
5265 format %{ %}
5266 interface(REG_INTER);
5267 %}
5268
5269 // Subset of Integer Register
5270 operand xRegI(eRegI reg) %{
5271 constraint(ALLOC_IN_RC(x_reg));
5272 match(reg);
5273 match(eAXRegI);
5274 match(eBXRegI);
5275 match(eCXRegI);
5276 match(eDXRegI);
5277
5278 format %{ %}
5279 interface(REG_INTER);
5280 %}
5281
5282 // Special Registers
5283 operand eAXRegI(xRegI reg) %{
5284 constraint(ALLOC_IN_RC(eax_reg));
5285 match(reg);
5286 match(eRegI);
5287
5288 format %{ "EAX" %}
5289 interface(REG_INTER);
5290 %}
5291
5292 // Special Registers
5293 operand eBXRegI(xRegI reg) %{
5294 constraint(ALLOC_IN_RC(ebx_reg));
5295 match(reg);
5296 match(eRegI);
5297
5298 format %{ "EBX" %}
5299 interface(REG_INTER);
5300 %}
5301
5302 operand eCXRegI(xRegI reg) %{
5303 constraint(ALLOC_IN_RC(ecx_reg));
5304 match(reg);
5305 match(eRegI);
5306
5307 format %{ "ECX" %}
5308 interface(REG_INTER);
5309 %}
5310
5311 operand eDXRegI(xRegI reg) %{
5312 constraint(ALLOC_IN_RC(edx_reg));
5313 match(reg);
5314 match(eRegI);
5315
5316 format %{ "EDX" %}
5317 interface(REG_INTER);
5318 %}
5319
5320 operand eDIRegI(xRegI reg) %{
5321 constraint(ALLOC_IN_RC(edi_reg));
5322 match(reg);
5323 match(eRegI);
5324
5325 format %{ "EDI" %}
5326 interface(REG_INTER);
5327 %}
5328
5329 operand naxRegI() %{
5330 constraint(ALLOC_IN_RC(nax_reg));
5331 match(RegI);
5332 match(eCXRegI);
5333 match(eDXRegI);
5334 match(eSIRegI);
5335 match(eDIRegI);
5336
5337 format %{ %}
5338 interface(REG_INTER);
5339 %}
5340
5341 operand nadxRegI() %{
5342 constraint(ALLOC_IN_RC(nadx_reg));
5343 match(RegI);
5344 match(eBXRegI);
5345 match(eCXRegI);
5346 match(eSIRegI);
5347 match(eDIRegI);
5348
5349 format %{ %}
5350 interface(REG_INTER);
5351 %}
5352
5353 operand ncxRegI() %{
5354 constraint(ALLOC_IN_RC(ncx_reg));
5355 match(RegI);
5356 match(eAXRegI);
5357 match(eDXRegI);
5358 match(eSIRegI);
5359 match(eDIRegI);
5360
5361 format %{ %}
5362 interface(REG_INTER);
5363 %}
5364
5365 // // This operand was used by cmpFastUnlock, but conflicted with 'object' reg
5366 // //
5367 operand eSIRegI(xRegI reg) %{
5368 constraint(ALLOC_IN_RC(esi_reg));
5369 match(reg);
5370 match(eRegI);
5371
5372 format %{ "ESI" %}
5373 interface(REG_INTER);
5374 %}
5375
5376 // Pointer Register
5377 operand anyRegP() %{
5378 constraint(ALLOC_IN_RC(any_reg));
5379 match(RegP);
5380 match(eAXRegP);
5381 match(eBXRegP);
5382 match(eCXRegP);
5383 match(eDIRegP);
5384 match(eRegP);
5385
5386 format %{ %}
5387 interface(REG_INTER);
5388 %}
5389
5390 operand eRegP() %{
5391 constraint(ALLOC_IN_RC(e_reg));
5392 match(RegP);
5393 match(eAXRegP);
5394 match(eBXRegP);
5395 match(eCXRegP);
5396 match(eDIRegP);
5397
5398 format %{ %}
5399 interface(REG_INTER);
5400 %}
5401
5402 // On windows95, EBP is not safe to use for implicit null tests.
5403 operand eRegP_no_EBP() %{
5404 constraint(ALLOC_IN_RC(e_reg_no_rbp));
5405 match(RegP);
5406 match(eAXRegP);
5407 match(eBXRegP);
5408 match(eCXRegP);
5409 match(eDIRegP);
5410
5411 op_cost(100);
5412 format %{ %}
5413 interface(REG_INTER);
5414 %}
5415
5416 operand naxRegP() %{
5417 constraint(ALLOC_IN_RC(nax_reg));
5418 match(RegP);
5419 match(eBXRegP);
5420 match(eDXRegP);
5421 match(eCXRegP);
5422 match(eSIRegP);
5423 match(eDIRegP);
5424
5425 format %{ %}
5426 interface(REG_INTER);
5427 %}
5428
5429 operand nabxRegP() %{
5430 constraint(ALLOC_IN_RC(nabx_reg));
5431 match(RegP);
5432 match(eCXRegP);
5433 match(eDXRegP);
5434 match(eSIRegP);
5435 match(eDIRegP);
5436
5437 format %{ %}
5438 interface(REG_INTER);
5439 %}
5440
5441 operand pRegP() %{
5442 constraint(ALLOC_IN_RC(p_reg));
5443 match(RegP);
5444 match(eBXRegP);
5445 match(eDXRegP);
5446 match(eSIRegP);
5447 match(eDIRegP);
5448
5449 format %{ %}
5450 interface(REG_INTER);
5451 %}
5452
5453 // Special Registers
5454 // Return a pointer value
5455 operand eAXRegP(eRegP reg) %{
5456 constraint(ALLOC_IN_RC(eax_reg));
5457 match(reg);
5458 format %{ "EAX" %}
5459 interface(REG_INTER);
5460 %}
5461
5462 // Used in AtomicAdd
5463 operand eBXRegP(eRegP reg) %{
5464 constraint(ALLOC_IN_RC(ebx_reg));
5465 match(reg);
5466 format %{ "EBX" %}
5467 interface(REG_INTER);
5468 %}
5469
5470 // Tail-call (interprocedural jump) to interpreter
5471 operand eCXRegP(eRegP reg) %{
5472 constraint(ALLOC_IN_RC(ecx_reg));
5473 match(reg);
5474 format %{ "ECX" %}
5475 interface(REG_INTER);
5476 %}
5477
5478 operand eSIRegP(eRegP reg) %{
5479 constraint(ALLOC_IN_RC(esi_reg));
5480 match(reg);
5481 format %{ "ESI" %}
5482 interface(REG_INTER);
5483 %}
5484
5485 // Used in rep stosw
5486 operand eDIRegP(eRegP reg) %{
5487 constraint(ALLOC_IN_RC(edi_reg));
5488 match(reg);
5489 format %{ "EDI" %}
5490 interface(REG_INTER);
5491 %}
5492
5493 operand eBPRegP() %{
5494 constraint(ALLOC_IN_RC(ebp_reg));
5495 match(RegP);
5496 format %{ "EBP" %}
5497 interface(REG_INTER);
5498 %}
5499
5500 operand eRegL() %{
5501 constraint(ALLOC_IN_RC(long_reg));
5502 match(RegL);
5503 match(eADXRegL);
5504
5505 format %{ %}
5506 interface(REG_INTER);
5507 %}
5508
5509 operand eADXRegL( eRegL reg ) %{
5510 constraint(ALLOC_IN_RC(eadx_reg));
5511 match(reg);
5512
5513 format %{ "EDX:EAX" %}
5514 interface(REG_INTER);
5515 %}
5516
5517 operand eBCXRegL( eRegL reg ) %{
5518 constraint(ALLOC_IN_RC(ebcx_reg));
5519 match(reg);
5520
5521 format %{ "EBX:ECX" %}
5522 interface(REG_INTER);
5523 %}
5524
5525 // Special case for integer high multiply
5526 operand eADXRegL_low_only() %{
5527 constraint(ALLOC_IN_RC(eadx_reg));
5528 match(RegL);
5529
5530 format %{ "EAX" %}
5531 interface(REG_INTER);
5532 %}
5533
5534 // Flags register, used as output of compare instructions
5535 operand eFlagsReg() %{
5536 constraint(ALLOC_IN_RC(int_flags));
5537 match(RegFlags);
5538
5539 format %{ "EFLAGS" %}
5540 interface(REG_INTER);
5541 %}
5542
5543 // Flags register, used as output of FLOATING POINT compare instructions
5544 operand eFlagsRegU() %{
5545 constraint(ALLOC_IN_RC(int_flags));
5546 match(RegFlags);
5547
5548 format %{ "EFLAGS_U" %}
5549 interface(REG_INTER);
5550 %}
5551
5552 operand eFlagsRegUCF() %{
5553 constraint(ALLOC_IN_RC(int_flags));
5554 match(RegFlags);
5555 predicate(false);
5556
5557 format %{ "EFLAGS_U_CF" %}
5558 interface(REG_INTER);
5559 %}
5560
5561 // Condition Code Register used by long compare
5562 operand flagsReg_long_LTGE() %{
5563 constraint(ALLOC_IN_RC(int_flags));
5564 match(RegFlags);
5565 format %{ "FLAGS_LTGE" %}
5566 interface(REG_INTER);
5567 %}
5568 operand flagsReg_long_EQNE() %{
5569 constraint(ALLOC_IN_RC(int_flags));
5570 match(RegFlags);
5571 format %{ "FLAGS_EQNE" %}
5572 interface(REG_INTER);
5573 %}
5574 operand flagsReg_long_LEGT() %{
5575 constraint(ALLOC_IN_RC(int_flags));
5576 match(RegFlags);
5577 format %{ "FLAGS_LEGT" %}
5578 interface(REG_INTER);
5579 %}
5580
5581 // Float register operands
5582 operand regD() %{
5583 predicate( UseSSE < 2 );
5584 constraint(ALLOC_IN_RC(dbl_reg));
5585 match(RegD);
5586 match(regDPR1);
5587 match(regDPR2);
5588 format %{ %}
5589 interface(REG_INTER);
5590 %}
5591
5592 operand regDPR1(regD reg) %{
5593 predicate( UseSSE < 2 );
5594 constraint(ALLOC_IN_RC(dbl_reg0));
5595 match(reg);
5596 format %{ "FPR1" %}
5597 interface(REG_INTER);
5598 %}
5599
5600 operand regDPR2(regD reg) %{
5601 predicate( UseSSE < 2 );
5602 constraint(ALLOC_IN_RC(dbl_reg1));
5603 match(reg);
5604 format %{ "FPR2" %}
5605 interface(REG_INTER);
5606 %}
5607
5608 operand regnotDPR1(regD reg) %{
5609 predicate( UseSSE < 2 );
5610 constraint(ALLOC_IN_RC(dbl_notreg0));
5611 match(reg);
5612 format %{ %}
5613 interface(REG_INTER);
5614 %}
5615
5616 // XMM Double register operands
5617 operand regXD() %{
5618 predicate( UseSSE>=2 );
5619 constraint(ALLOC_IN_RC(xdb_reg));
5620 match(RegD);
5621 match(regXD6);
5622 match(regXD7);
5623 format %{ %}
5624 interface(REG_INTER);
5625 %}
5626
5627 // XMM6 double register operands
5628 operand regXD6(regXD reg) %{
5629 predicate( UseSSE>=2 );
5630 constraint(ALLOC_IN_RC(xdb_reg6));
5631 match(reg);
5632 format %{ "XMM6" %}
5633 interface(REG_INTER);
5634 %}
5635
5636 // XMM7 double register operands
5637 operand regXD7(regXD reg) %{
5638 predicate( UseSSE>=2 );
5639 constraint(ALLOC_IN_RC(xdb_reg7));
5640 match(reg);
5641 format %{ "XMM7" %}
5642 interface(REG_INTER);
5643 %}
5644
5645 // Float register operands
5646 operand regF() %{
5647 predicate( UseSSE < 2 );
5648 constraint(ALLOC_IN_RC(flt_reg));
5649 match(RegF);
5650 match(regFPR1);
5651 format %{ %}
5652 interface(REG_INTER);
5653 %}
5654
5655 // Float register operands
5656 operand regFPR1(regF reg) %{
5657 predicate( UseSSE < 2 );
5658 constraint(ALLOC_IN_RC(flt_reg0));
5659 match(reg);
5660 format %{ "FPR1" %}
5661 interface(REG_INTER);
5662 %}
5663
5664 // XMM register operands
5665 operand regX() %{
5666 predicate( UseSSE>=1 );
5667 constraint(ALLOC_IN_RC(xmm_reg));
5668 match(RegF);
5669 format %{ %}
5670 interface(REG_INTER);
5671 %}
5672
5673
5674 //----------Memory Operands----------------------------------------------------
5675 // Direct Memory Operand
5676 operand direct(immP addr) %{
5677 match(addr);
5678
5679 format %{ "[$addr]" %}
5680 interface(MEMORY_INTER) %{
5681 base(0xFFFFFFFF);
5682 index(0x4);
5683 scale(0x0);
5684 disp($addr);
5685 %}
5686 %}
5687
5688 // Indirect Memory Operand
5689 operand indirect(eRegP reg) %{
5690 constraint(ALLOC_IN_RC(e_reg));
5691 match(reg);
5692
5693 format %{ "[$reg]" %}
5694 interface(MEMORY_INTER) %{
5695 base($reg);
5696 index(0x4);
5697 scale(0x0);
5698 disp(0x0);
5699 %}
5700 %}
5701
5702 // Indirect Memory Plus Short Offset Operand
5703 operand indOffset8(eRegP reg, immI8 off) %{
5704 match(AddP reg off);
5705
5706 format %{ "[$reg + $off]" %}
5707 interface(MEMORY_INTER) %{
5708 base($reg);
5709 index(0x4);
5710 scale(0x0);
5711 disp($off);
5712 %}
5713 %}
5714
5715 // Indirect Memory Plus Long Offset Operand
5716 operand indOffset32(eRegP reg, immI off) %{
5717 match(AddP reg off);
5718
5719 format %{ "[$reg + $off]" %}
5720 interface(MEMORY_INTER) %{
5721 base($reg);
5722 index(0x4);
5723 scale(0x0);
5724 disp($off);
5725 %}
5726 %}
5727
5728 // Indirect Memory Plus Long Offset Operand
5729 operand indOffset32X(eRegI reg, immP off) %{
5730 match(AddP off reg);
5731
5732 format %{ "[$reg + $off]" %}
5733 interface(MEMORY_INTER) %{
5734 base($reg);
5735 index(0x4);
5736 scale(0x0);
5737 disp($off);
5738 %}
5739 %}
5740
5741 // Indirect Memory Plus Index Register Plus Offset Operand
5742 operand indIndexOffset(eRegP reg, eRegI ireg, immI off) %{
5743 match(AddP (AddP reg ireg) off);
5744
5745 op_cost(10);
5746 format %{"[$reg + $off + $ireg]" %}
5747 interface(MEMORY_INTER) %{
5748 base($reg);
5749 index($ireg);
5750 scale(0x0);
5751 disp($off);
5752 %}
5753 %}
5754
5755 // Indirect Memory Plus Index Register Plus Offset Operand
5756 operand indIndex(eRegP reg, eRegI ireg) %{
5757 match(AddP reg ireg);
5758
5759 op_cost(10);
5760 format %{"[$reg + $ireg]" %}
5761 interface(MEMORY_INTER) %{
5762 base($reg);
5763 index($ireg);
5764 scale(0x0);
5765 disp(0x0);
5766 %}
5767 %}
5768
5769 // // -------------------------------------------------------------------------
5770 // // 486 architecture doesn't support "scale * index + offset" with out a base
5771 // // -------------------------------------------------------------------------
5772 // // Scaled Memory Operands
5773 // // Indirect Memory Times Scale Plus Offset Operand
5774 // operand indScaleOffset(immP off, eRegI ireg, immI2 scale) %{
5775 // match(AddP off (LShiftI ireg scale));
5776 //
5777 // op_cost(10);
5778 // format %{"[$off + $ireg << $scale]" %}
5779 // interface(MEMORY_INTER) %{
5780 // base(0x4);
5781 // index($ireg);
5782 // scale($scale);
5783 // disp($off);
5784 // %}
5785 // %}
5786
5787 // Indirect Memory Times Scale Plus Index Register
5788 operand indIndexScale(eRegP reg, eRegI ireg, immI2 scale) %{
5789 match(AddP reg (LShiftI ireg scale));
5790
5791 op_cost(10);
5792 format %{"[$reg + $ireg << $scale]" %}
5793 interface(MEMORY_INTER) %{
5794 base($reg);
5795 index($ireg);
5796 scale($scale);
5797 disp(0x0);
5798 %}
5799 %}
5800
5801 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
5802 operand indIndexScaleOffset(eRegP reg, immI off, eRegI ireg, immI2 scale) %{
5803 match(AddP (AddP reg (LShiftI ireg scale)) off);
5804
5805 op_cost(10);
5806 format %{"[$reg + $off + $ireg << $scale]" %}
5807 interface(MEMORY_INTER) %{
5808 base($reg);
5809 index($ireg);
5810 scale($scale);
5811 disp($off);
5812 %}
5813 %}
5814
5815 //----------Load Long Memory Operands------------------------------------------
5816 // The load-long idiom will use it's address expression again after loading
5817 // the first word of the long. If the load-long destination overlaps with
5818 // registers used in the addressing expression, the 2nd half will be loaded
5819 // from a clobbered address. Fix this by requiring that load-long use
5820 // address registers that do not overlap with the load-long target.
5821
5822 // load-long support
5823 operand load_long_RegP() %{
5824 constraint(ALLOC_IN_RC(esi_reg));
5825 match(RegP);
5826 match(eSIRegP);
5827 op_cost(100);
5828 format %{ %}
5829 interface(REG_INTER);
5830 %}
5831
5832 // Indirect Memory Operand Long
5833 operand load_long_indirect(load_long_RegP reg) %{
5834 constraint(ALLOC_IN_RC(esi_reg));
5835 match(reg);
5836
5837 format %{ "[$reg]" %}
5838 interface(MEMORY_INTER) %{
5839 base($reg);
5840 index(0x4);
5841 scale(0x0);
5842 disp(0x0);
5843 %}
5844 %}
5845
5846 // Indirect Memory Plus Long Offset Operand
5847 operand load_long_indOffset32(load_long_RegP reg, immI off) %{
5848 match(AddP reg off);
5849
5850 format %{ "[$reg + $off]" %}
5851 interface(MEMORY_INTER) %{
5852 base($reg);
5853 index(0x4);
5854 scale(0x0);
5855 disp($off);
5856 %}
5857 %}
5858
5859 opclass load_long_memory(load_long_indirect, load_long_indOffset32);
5860
5861
5862 //----------Special Memory Operands--------------------------------------------
5863 // Stack Slot Operand - This operand is used for loading and storing temporary
5864 // values on the stack where a match requires a value to
5865 // flow through memory.
5866 operand stackSlotP(sRegP reg) %{
5867 constraint(ALLOC_IN_RC(stack_slots));
5868 // No match rule because this operand is only generated in matching
5869 format %{ "[$reg]" %}
5870 interface(MEMORY_INTER) %{
5871 base(0x4); // ESP
5872 index(0x4); // No Index
5873 scale(0x0); // No Scale
5874 disp($reg); // Stack Offset
5875 %}
5876 %}
5877
5878 operand stackSlotI(sRegI reg) %{
5879 constraint(ALLOC_IN_RC(stack_slots));
5880 // No match rule because this operand is only generated in matching
5881 format %{ "[$reg]" %}
5882 interface(MEMORY_INTER) %{
5883 base(0x4); // ESP
5884 index(0x4); // No Index
5885 scale(0x0); // No Scale
5886 disp($reg); // Stack Offset
5887 %}
5888 %}
5889
5890 operand stackSlotF(sRegF reg) %{
5891 constraint(ALLOC_IN_RC(stack_slots));
5892 // No match rule because this operand is only generated in matching
5893 format %{ "[$reg]" %}
5894 interface(MEMORY_INTER) %{
5895 base(0x4); // ESP
5896 index(0x4); // No Index
5897 scale(0x0); // No Scale
5898 disp($reg); // Stack Offset
5899 %}
5900 %}
5901
5902 operand stackSlotD(sRegD reg) %{
5903 constraint(ALLOC_IN_RC(stack_slots));
5904 // No match rule because this operand is only generated in matching
5905 format %{ "[$reg]" %}
5906 interface(MEMORY_INTER) %{
5907 base(0x4); // ESP
5908 index(0x4); // No Index
5909 scale(0x0); // No Scale
5910 disp($reg); // Stack Offset
5911 %}
5912 %}
5913
5914 operand stackSlotL(sRegL reg) %{
5915 constraint(ALLOC_IN_RC(stack_slots));
5916 // No match rule because this operand is only generated in matching
5917 format %{ "[$reg]" %}
5918 interface(MEMORY_INTER) %{
5919 base(0x4); // ESP
5920 index(0x4); // No Index
5921 scale(0x0); // No Scale
5922 disp($reg); // Stack Offset
5923 %}
5924 %}
5925
5926 //----------Memory Operands - Win95 Implicit Null Variants----------------
5927 // Indirect Memory Operand
5928 operand indirect_win95_safe(eRegP_no_EBP reg)
5929 %{
5930 constraint(ALLOC_IN_RC(e_reg));
5931 match(reg);
5932
5933 op_cost(100);
5934 format %{ "[$reg]" %}
5935 interface(MEMORY_INTER) %{
5936 base($reg);
5937 index(0x4);
5938 scale(0x0);
5939 disp(0x0);
5940 %}
5941 %}
5942
5943 // Indirect Memory Plus Short Offset Operand
5944 operand indOffset8_win95_safe(eRegP_no_EBP reg, immI8 off)
5945 %{
5946 match(AddP reg off);
5947
5948 op_cost(100);
5949 format %{ "[$reg + $off]" %}
5950 interface(MEMORY_INTER) %{
5951 base($reg);
5952 index(0x4);
5953 scale(0x0);
5954 disp($off);
5955 %}
5956 %}
5957
5958 // Indirect Memory Plus Long Offset Operand
5959 operand indOffset32_win95_safe(eRegP_no_EBP reg, immI off)
5960 %{
5961 match(AddP reg off);
5962
5963 op_cost(100);
5964 format %{ "[$reg + $off]" %}
5965 interface(MEMORY_INTER) %{
5966 base($reg);
5967 index(0x4);
5968 scale(0x0);
5969 disp($off);
5970 %}
5971 %}
5972
5973 // Indirect Memory Plus Index Register Plus Offset Operand
5974 operand indIndexOffset_win95_safe(eRegP_no_EBP reg, eRegI ireg, immI off)
5975 %{
5976 match(AddP (AddP reg ireg) off);
5977
5978 op_cost(100);
5979 format %{"[$reg + $off + $ireg]" %}
5980 interface(MEMORY_INTER) %{
5981 base($reg);
5982 index($ireg);
5983 scale(0x0);
5984 disp($off);
5985 %}
5986 %}
5987
5988 // Indirect Memory Times Scale Plus Index Register
5989 operand indIndexScale_win95_safe(eRegP_no_EBP reg, eRegI ireg, immI2 scale)
5990 %{
5991 match(AddP reg (LShiftI ireg scale));
5992
5993 op_cost(100);
5994 format %{"[$reg + $ireg << $scale]" %}
5995 interface(MEMORY_INTER) %{
5996 base($reg);
5997 index($ireg);
5998 scale($scale);
5999 disp(0x0);
6000 %}
6001 %}
6002
6003 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
6004 operand indIndexScaleOffset_win95_safe(eRegP_no_EBP reg, immI off, eRegI ireg, immI2 scale)
6005 %{
6006 match(AddP (AddP reg (LShiftI ireg scale)) off);
6007
6008 op_cost(100);
6009 format %{"[$reg + $off + $ireg << $scale]" %}
6010 interface(MEMORY_INTER) %{
6011 base($reg);
6012 index($ireg);
6013 scale($scale);
6014 disp($off);
6015 %}
6016 %}
6017
6018 //----------Conditional Branch Operands----------------------------------------
6019 // Comparison Op - This is the operation of the comparison, and is limited to
6020 // the following set of codes:
6021 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
6022 //
6023 // Other attributes of the comparison, such as unsignedness, are specified
6024 // by the comparison instruction that sets a condition code flags register.
6025 // That result is represented by a flags operand whose subtype is appropriate
6026 // to the unsignedness (etc.) of the comparison.
6027 //
6028 // Later, the instruction which matches both the Comparison Op (a Bool) and
6029 // the flags (produced by the Cmp) specifies the coding of the comparison op
6030 // by matching a specific subtype of Bool operand below, such as cmpOpU.
6031
6032 // Comparision Code
6033 operand cmpOp() %{
6034 match(Bool);
6035
6036 format %{ "" %}
6037 interface(COND_INTER) %{
6038 equal(0x4, "e");
6039 not_equal(0x5, "ne");
6040 less(0xC, "l");
6041 greater_equal(0xD, "ge");
6042 less_equal(0xE, "le");
6043 greater(0xF, "g");
6044 %}
6045 %}
6046
6047 // Comparison Code, unsigned compare. Used by FP also, with
6048 // C2 (unordered) turned into GT or LT already. The other bits
6049 // C0 and C3 are turned into Carry & Zero flags.
6050 operand cmpOpU() %{
6051 match(Bool);
6052
6053 format %{ "" %}
6054 interface(COND_INTER) %{
6055 equal(0x4, "e");
6056 not_equal(0x5, "ne");
6057 less(0x2, "b");
6058 greater_equal(0x3, "nb");
6059 less_equal(0x6, "be");
6060 greater(0x7, "nbe");
6061 %}
6062 %}
6063
6064 // Floating comparisons that don't require any fixup for the unordered case
6065 operand cmpOpUCF() %{
6066 match(Bool);
6067 predicate(n->as_Bool()->_test._test == BoolTest::lt ||
6068 n->as_Bool()->_test._test == BoolTest::ge ||
6069 n->as_Bool()->_test._test == BoolTest::le ||
6070 n->as_Bool()->_test._test == BoolTest::gt);
6071 format %{ "" %}
6072 interface(COND_INTER) %{
6073 equal(0x4, "e");
6074 not_equal(0x5, "ne");
6075 less(0x2, "b");
6076 greater_equal(0x3, "nb");
6077 less_equal(0x6, "be");
6078 greater(0x7, "nbe");
6079 %}
6080 %}
6081
6082
6083 // Floating comparisons that can be fixed up with extra conditional jumps
6084 operand cmpOpUCF2() %{
6085 match(Bool);
6086 predicate(n->as_Bool()->_test._test == BoolTest::ne ||
6087 n->as_Bool()->_test._test == BoolTest::eq);
6088 format %{ "" %}
6089 interface(COND_INTER) %{
6090 equal(0x4, "e");
6091 not_equal(0x5, "ne");
6092 less(0x2, "b");
6093 greater_equal(0x3, "nb");
6094 less_equal(0x6, "be");
6095 greater(0x7, "nbe");
6096 %}
6097 %}
6098
6099 // Comparison Code for FP conditional move
6100 operand cmpOp_fcmov() %{
6101 match(Bool);
6102
6103 format %{ "" %}
6104 interface(COND_INTER) %{
6105 equal (0x0C8);
6106 not_equal (0x1C8);
6107 less (0x0C0);
6108 greater_equal(0x1C0);
6109 less_equal (0x0D0);
6110 greater (0x1D0);
6111 %}
6112 %}
6113
6114 // Comparision Code used in long compares
6115 operand cmpOp_commute() %{
6116 match(Bool);
6117
6118 format %{ "" %}
6119 interface(COND_INTER) %{
6120 equal(0x4, "e");
6121 not_equal(0x5, "ne");
6122 less(0xF, "g");
6123 greater_equal(0xE, "le");
6124 less_equal(0xD, "ge");
6125 greater(0xC, "l");
6126 %}
6127 %}
6128
6129 //----------OPERAND CLASSES----------------------------------------------------
6130 // Operand Classes are groups of operands that are used as to simplify
6131 // instruction definitions by not requiring the AD writer to specify separate
6132 // instructions for every form of operand when the instruction accepts
6133 // multiple operand types with the same basic encoding and format. The classic
6134 // case of this is memory operands.
6135
6136 opclass memory(direct, indirect, indOffset8, indOffset32, indOffset32X, indIndexOffset,
6137 indIndex, indIndexScale, indIndexScaleOffset);
6138
6139 // Long memory operations are encoded in 2 instructions and a +4 offset.
6140 // This means some kind of offset is always required and you cannot use
6141 // an oop as the offset (done when working on static globals).
6142 opclass long_memory(direct, indirect, indOffset8, indOffset32, indIndexOffset,
6143 indIndex, indIndexScale, indIndexScaleOffset);
6144
6145
6146 //----------PIPELINE-----------------------------------------------------------
6147 // Rules which define the behavior of the target architectures pipeline.
6148 pipeline %{
6149
6150 //----------ATTRIBUTES---------------------------------------------------------
6151 attributes %{
6152 variable_size_instructions; // Fixed size instructions
6153 max_instructions_per_bundle = 3; // Up to 3 instructions per bundle
6154 instruction_unit_size = 1; // An instruction is 1 bytes long
6155 instruction_fetch_unit_size = 16; // The processor fetches one line
6156 instruction_fetch_units = 1; // of 16 bytes
6157
6158 // List of nop instructions
6159 nops( MachNop );
6160 %}
6161
6162 //----------RESOURCES----------------------------------------------------------
6163 // Resources are the functional units available to the machine
6164
6165 // Generic P2/P3 pipeline
6166 // 3 decoders, only D0 handles big operands; a "bundle" is the limit of
6167 // 3 instructions decoded per cycle.
6168 // 2 load/store ops per cycle, 1 branch, 1 FPU,
6169 // 2 ALU op, only ALU0 handles mul/div instructions.
6170 resources( D0, D1, D2, DECODE = D0 | D1 | D2,
6171 MS0, MS1, MEM = MS0 | MS1,
6172 BR, FPU,
6173 ALU0, ALU1, ALU = ALU0 | ALU1 );
6174
6175 //----------PIPELINE DESCRIPTION-----------------------------------------------
6176 // Pipeline Description specifies the stages in the machine's pipeline
6177
6178 // Generic P2/P3 pipeline
6179 pipe_desc(S0, S1, S2, S3, S4, S5);
6180
6181 //----------PIPELINE CLASSES---------------------------------------------------
6182 // Pipeline Classes describe the stages in which input and output are
6183 // referenced by the hardware pipeline.
6184
6185 // Naming convention: ialu or fpu
6186 // Then: _reg
6187 // Then: _reg if there is a 2nd register
6188 // Then: _long if it's a pair of instructions implementing a long
6189 // Then: _fat if it requires the big decoder
6190 // Or: _mem if it requires the big decoder and a memory unit.
6191
6192 // Integer ALU reg operation
6193 pipe_class ialu_reg(eRegI dst) %{
6194 single_instruction;
6195 dst : S4(write);
6196 dst : S3(read);
6197 DECODE : S0; // any decoder
6198 ALU : S3; // any alu
6199 %}
6200
6201 // Long ALU reg operation
6202 pipe_class ialu_reg_long(eRegL dst) %{
6203 instruction_count(2);
6204 dst : S4(write);
6205 dst : S3(read);
6206 DECODE : S0(2); // any 2 decoders
6207 ALU : S3(2); // both alus
6208 %}
6209
6210 // Integer ALU reg operation using big decoder
6211 pipe_class ialu_reg_fat(eRegI dst) %{
6212 single_instruction;
6213 dst : S4(write);
6214 dst : S3(read);
6215 D0 : S0; // big decoder only
6216 ALU : S3; // any alu
6217 %}
6218
6219 // Long ALU reg operation using big decoder
6220 pipe_class ialu_reg_long_fat(eRegL dst) %{
6221 instruction_count(2);
6222 dst : S4(write);
6223 dst : S3(read);
6224 D0 : S0(2); // big decoder only; twice
6225 ALU : S3(2); // any 2 alus
6226 %}
6227
6228 // Integer ALU reg-reg operation
6229 pipe_class ialu_reg_reg(eRegI dst, eRegI src) %{
6230 single_instruction;
6231 dst : S4(write);
6232 src : S3(read);
6233 DECODE : S0; // any decoder
6234 ALU : S3; // any alu
6235 %}
6236
6237 // Long ALU reg-reg operation
6238 pipe_class ialu_reg_reg_long(eRegL dst, eRegL src) %{
6239 instruction_count(2);
6240 dst : S4(write);
6241 src : S3(read);
6242 DECODE : S0(2); // any 2 decoders
6243 ALU : S3(2); // both alus
6244 %}
6245
6246 // Integer ALU reg-reg operation
6247 pipe_class ialu_reg_reg_fat(eRegI dst, memory src) %{
6248 single_instruction;
6249 dst : S4(write);
6250 src : S3(read);
6251 D0 : S0; // big decoder only
6252 ALU : S3; // any alu
6253 %}
6254
6255 // Long ALU reg-reg operation
6256 pipe_class ialu_reg_reg_long_fat(eRegL dst, eRegL src) %{
6257 instruction_count(2);
6258 dst : S4(write);
6259 src : S3(read);
6260 D0 : S0(2); // big decoder only; twice
6261 ALU : S3(2); // both alus
6262 %}
6263
6264 // Integer ALU reg-mem operation
6265 pipe_class ialu_reg_mem(eRegI dst, memory mem) %{
6266 single_instruction;
6267 dst : S5(write);
6268 mem : S3(read);
6269 D0 : S0; // big decoder only
6270 ALU : S4; // any alu
6271 MEM : S3; // any mem
6272 %}
6273
6274 // Long ALU reg-mem operation
6275 pipe_class ialu_reg_long_mem(eRegL dst, load_long_memory mem) %{
6276 instruction_count(2);
6277 dst : S5(write);
6278 mem : S3(read);
6279 D0 : S0(2); // big decoder only; twice
6280 ALU : S4(2); // any 2 alus
6281 MEM : S3(2); // both mems
6282 %}
6283
6284 // Integer mem operation (prefetch)
6285 pipe_class ialu_mem(memory mem)
6286 %{
6287 single_instruction;
6288 mem : S3(read);
6289 D0 : S0; // big decoder only
6290 MEM : S3; // any mem
6291 %}
6292
6293 // Integer Store to Memory
6294 pipe_class ialu_mem_reg(memory mem, eRegI src) %{
6295 single_instruction;
6296 mem : S3(read);
6297 src : S5(read);
6298 D0 : S0; // big decoder only
6299 ALU : S4; // any alu
6300 MEM : S3;
6301 %}
6302
6303 // Long Store to Memory
6304 pipe_class ialu_mem_long_reg(memory mem, eRegL src) %{
6305 instruction_count(2);
6306 mem : S3(read);
6307 src : S5(read);
6308 D0 : S0(2); // big decoder only; twice
6309 ALU : S4(2); // any 2 alus
6310 MEM : S3(2); // Both mems
6311 %}
6312
6313 // Integer Store to Memory
6314 pipe_class ialu_mem_imm(memory mem) %{
6315 single_instruction;
6316 mem : S3(read);
6317 D0 : S0; // big decoder only
6318 ALU : S4; // any alu
6319 MEM : S3;
6320 %}
6321
6322 // Integer ALU0 reg-reg operation
6323 pipe_class ialu_reg_reg_alu0(eRegI dst, eRegI src) %{
6324 single_instruction;
6325 dst : S4(write);
6326 src : S3(read);
6327 D0 : S0; // Big decoder only
6328 ALU0 : S3; // only alu0
6329 %}
6330
6331 // Integer ALU0 reg-mem operation
6332 pipe_class ialu_reg_mem_alu0(eRegI dst, memory mem) %{
6333 single_instruction;
6334 dst : S5(write);
6335 mem : S3(read);
6336 D0 : S0; // big decoder only
6337 ALU0 : S4; // ALU0 only
6338 MEM : S3; // any mem
6339 %}
6340
6341 // Integer ALU reg-reg operation
6342 pipe_class ialu_cr_reg_reg(eFlagsReg cr, eRegI src1, eRegI src2) %{
6343 single_instruction;
6344 cr : S4(write);
6345 src1 : S3(read);
6346 src2 : S3(read);
6347 DECODE : S0; // any decoder
6348 ALU : S3; // any alu
6349 %}
6350
6351 // Integer ALU reg-imm operation
6352 pipe_class ialu_cr_reg_imm(eFlagsReg cr, eRegI src1) %{
6353 single_instruction;
6354 cr : S4(write);
6355 src1 : S3(read);
6356 DECODE : S0; // any decoder
6357 ALU : S3; // any alu
6358 %}
6359
6360 // Integer ALU reg-mem operation
6361 pipe_class ialu_cr_reg_mem(eFlagsReg cr, eRegI src1, memory src2) %{
6362 single_instruction;
6363 cr : S4(write);
6364 src1 : S3(read);
6365 src2 : S3(read);
6366 D0 : S0; // big decoder only
6367 ALU : S4; // any alu
6368 MEM : S3;
6369 %}
6370
6371 // Conditional move reg-reg
6372 pipe_class pipe_cmplt( eRegI p, eRegI q, eRegI y ) %{
6373 instruction_count(4);
6374 y : S4(read);
6375 q : S3(read);
6376 p : S3(read);
6377 DECODE : S0(4); // any decoder
6378 %}
6379
6380 // Conditional move reg-reg
6381 pipe_class pipe_cmov_reg( eRegI dst, eRegI src, eFlagsReg cr ) %{
6382 single_instruction;
6383 dst : S4(write);
6384 src : S3(read);
6385 cr : S3(read);
6386 DECODE : S0; // any decoder
6387 %}
6388
6389 // Conditional move reg-mem
6390 pipe_class pipe_cmov_mem( eFlagsReg cr, eRegI dst, memory src) %{
6391 single_instruction;
6392 dst : S4(write);
6393 src : S3(read);
6394 cr : S3(read);
6395 DECODE : S0; // any decoder
6396 MEM : S3;
6397 %}
6398
6399 // Conditional move reg-reg long
6400 pipe_class pipe_cmov_reg_long( eFlagsReg cr, eRegL dst, eRegL src) %{
6401 single_instruction;
6402 dst : S4(write);
6403 src : S3(read);
6404 cr : S3(read);
6405 DECODE : S0(2); // any 2 decoders
6406 %}
6407
6408 // Conditional move double reg-reg
6409 pipe_class pipe_cmovD_reg( eFlagsReg cr, regDPR1 dst, regD src) %{
6410 single_instruction;
6411 dst : S4(write);
6412 src : S3(read);
6413 cr : S3(read);
6414 DECODE : S0; // any decoder
6415 %}
6416
6417 // Float reg-reg operation
6418 pipe_class fpu_reg(regD dst) %{
6419 instruction_count(2);
6420 dst : S3(read);
6421 DECODE : S0(2); // any 2 decoders
6422 FPU : S3;
6423 %}
6424
6425 // Float reg-reg operation
6426 pipe_class fpu_reg_reg(regD dst, regD src) %{
6427 instruction_count(2);
6428 dst : S4(write);
6429 src : S3(read);
6430 DECODE : S0(2); // any 2 decoders
6431 FPU : S3;
6432 %}
6433
6434 // Float reg-reg operation
6435 pipe_class fpu_reg_reg_reg(regD dst, regD src1, regD src2) %{
6436 instruction_count(3);
6437 dst : S4(write);
6438 src1 : S3(read);
6439 src2 : S3(read);
6440 DECODE : S0(3); // any 3 decoders
6441 FPU : S3(2);
6442 %}
6443
6444 // Float reg-reg operation
6445 pipe_class fpu_reg_reg_reg_reg(regD dst, regD src1, regD src2, regD src3) %{
6446 instruction_count(4);
6447 dst : S4(write);
6448 src1 : S3(read);
6449 src2 : S3(read);
6450 src3 : S3(read);
6451 DECODE : S0(4); // any 3 decoders
6452 FPU : S3(2);
6453 %}
6454
6455 // Float reg-reg operation
6456 pipe_class fpu_reg_mem_reg_reg(regD dst, memory src1, regD src2, regD src3) %{
6457 instruction_count(4);
6458 dst : S4(write);
6459 src1 : S3(read);
6460 src2 : S3(read);
6461 src3 : S3(read);
6462 DECODE : S1(3); // any 3 decoders
6463 D0 : S0; // Big decoder only
6464 FPU : S3(2);
6465 MEM : S3;
6466 %}
6467
6468 // Float reg-mem operation
6469 pipe_class fpu_reg_mem(regD dst, memory mem) %{
6470 instruction_count(2);
6471 dst : S5(write);
6472 mem : S3(read);
6473 D0 : S0; // big decoder only
6474 DECODE : S1; // any decoder for FPU POP
6475 FPU : S4;
6476 MEM : S3; // any mem
6477 %}
6478
6479 // Float reg-mem operation
6480 pipe_class fpu_reg_reg_mem(regD dst, regD src1, memory mem) %{
6481 instruction_count(3);
6482 dst : S5(write);
6483 src1 : S3(read);
6484 mem : S3(read);
6485 D0 : S0; // big decoder only
6486 DECODE : S1(2); // any decoder for FPU POP
6487 FPU : S4;
6488 MEM : S3; // any mem
6489 %}
6490
6491 // Float mem-reg operation
6492 pipe_class fpu_mem_reg(memory mem, regD src) %{
6493 instruction_count(2);
6494 src : S5(read);
6495 mem : S3(read);
6496 DECODE : S0; // any decoder for FPU PUSH
6497 D0 : S1; // big decoder only
6498 FPU : S4;
6499 MEM : S3; // any mem
6500 %}
6501
6502 pipe_class fpu_mem_reg_reg(memory mem, regD src1, regD src2) %{
6503 instruction_count(3);
6504 src1 : S3(read);
6505 src2 : S3(read);
6506 mem : S3(read);
6507 DECODE : S0(2); // any decoder for FPU PUSH
6508 D0 : S1; // big decoder only
6509 FPU : S4;
6510 MEM : S3; // any mem
6511 %}
6512
6513 pipe_class fpu_mem_reg_mem(memory mem, regD src1, memory src2) %{
6514 instruction_count(3);
6515 src1 : S3(read);
6516 src2 : S3(read);
6517 mem : S4(read);
6518 DECODE : S0; // any decoder for FPU PUSH
6519 D0 : S0(2); // big decoder only
6520 FPU : S4;
6521 MEM : S3(2); // any mem
6522 %}
6523
6524 pipe_class fpu_mem_mem(memory dst, memory src1) %{
6525 instruction_count(2);
6526 src1 : S3(read);
6527 dst : S4(read);
6528 D0 : S0(2); // big decoder only
6529 MEM : S3(2); // any mem
6530 %}
6531
6532 pipe_class fpu_mem_mem_mem(memory dst, memory src1, memory src2) %{
6533 instruction_count(3);
6534 src1 : S3(read);
6535 src2 : S3(read);
6536 dst : S4(read);
6537 D0 : S0(3); // big decoder only
6538 FPU : S4;
6539 MEM : S3(3); // any mem
6540 %}
6541
6542 pipe_class fpu_mem_reg_con(memory mem, regD src1) %{
6543 instruction_count(3);
6544 src1 : S4(read);
6545 mem : S4(read);
6546 DECODE : S0; // any decoder for FPU PUSH
6547 D0 : S0(2); // big decoder only
6548 FPU : S4;
6549 MEM : S3(2); // any mem
6550 %}
6551
6552 // Float load constant
6553 pipe_class fpu_reg_con(regD dst) %{
6554 instruction_count(2);
6555 dst : S5(write);
6556 D0 : S0; // big decoder only for the load
6557 DECODE : S1; // any decoder for FPU POP
6558 FPU : S4;
6559 MEM : S3; // any mem
6560 %}
6561
6562 // Float load constant
6563 pipe_class fpu_reg_reg_con(regD dst, regD src) %{
6564 instruction_count(3);
6565 dst : S5(write);
6566 src : S3(read);
6567 D0 : S0; // big decoder only for the load
6568 DECODE : S1(2); // any decoder for FPU POP
6569 FPU : S4;
6570 MEM : S3; // any mem
6571 %}
6572
6573 // UnConditional branch
6574 pipe_class pipe_jmp( label labl ) %{
6575 single_instruction;
6576 BR : S3;
6577 %}
6578
6579 // Conditional branch
6580 pipe_class pipe_jcc( cmpOp cmp, eFlagsReg cr, label labl ) %{
6581 single_instruction;
6582 cr : S1(read);
6583 BR : S3;
6584 %}
6585
6586 // Allocation idiom
6587 pipe_class pipe_cmpxchg( eRegP dst, eRegP heap_ptr ) %{
6588 instruction_count(1); force_serialization;
6589 fixed_latency(6);
6590 heap_ptr : S3(read);
6591 DECODE : S0(3);
6592 D0 : S2;
6593 MEM : S3;
6594 ALU : S3(2);
6595 dst : S5(write);
6596 BR : S5;
6597 %}
6598
6599 // Generic big/slow expanded idiom
6600 pipe_class pipe_slow( ) %{
6601 instruction_count(10); multiple_bundles; force_serialization;
6602 fixed_latency(100);
6603 D0 : S0(2);
6604 MEM : S3(2);
6605 %}
6606
6607 // The real do-nothing guy
6608 pipe_class empty( ) %{
6609 instruction_count(0);
6610 %}
6611
6612 // Define the class for the Nop node
6613 define %{
6614 MachNop = empty;
6615 %}
6616
6617 %}
6618
6619 //----------INSTRUCTIONS-------------------------------------------------------
6620 //
6621 // match -- States which machine-independent subtree may be replaced
6622 // by this instruction.
6623 // ins_cost -- The estimated cost of this instruction is used by instruction
6624 // selection to identify a minimum cost tree of machine
6625 // instructions that matches a tree of machine-independent
6626 // instructions.
6627 // format -- A string providing the disassembly for this instruction.
6628 // The value of an instruction's operand may be inserted
6629 // by referring to it with a '$' prefix.
6630 // opcode -- Three instruction opcodes may be provided. These are referred
6631 // to within an encode class as $primary, $secondary, and $tertiary
6632 // respectively. The primary opcode is commonly used to
6633 // indicate the type of machine instruction, while secondary
6634 // and tertiary are often used for prefix options or addressing
6635 // modes.
6636 // ins_encode -- A list of encode classes with parameters. The encode class
6637 // name must have been defined in an 'enc_class' specification
6638 // in the encode section of the architecture description.
6639
6640 //----------BSWAP-Instruction--------------------------------------------------
6641 instruct bytes_reverse_int(eRegI dst) %{
6642 match(Set dst (ReverseBytesI dst));
6643
6644 format %{ "BSWAP $dst" %}
6645 opcode(0x0F, 0xC8);
6646 ins_encode( OpcP, OpcSReg(dst) );
6647 ins_pipe( ialu_reg );
6648 %}
6649
6650 instruct bytes_reverse_long(eRegL dst) %{
6651 match(Set dst (ReverseBytesL dst));
6652
6653 format %{ "BSWAP $dst.lo\n\t"
6654 "BSWAP $dst.hi\n\t"
6655 "XCHG $dst.lo $dst.hi" %}
6656
6657 ins_cost(125);
6658 ins_encode( bswap_long_bytes(dst) );
6659 ins_pipe( ialu_reg_reg);
6660 %}
6661
6662
6663 //---------- Zeros Count Instructions ------------------------------------------
6664
6665 instruct countLeadingZerosI(eRegI dst, eRegI src, eFlagsReg cr) %{
6666 predicate(UseCountLeadingZerosInstruction);
6667 match(Set dst (CountLeadingZerosI src));
6668 effect(KILL cr);
6669
6670 format %{ "LZCNT $dst, $src\t# count leading zeros (int)" %}
6671 ins_encode %{
6672 __ lzcntl($dst$$Register, $src$$Register);
6673 %}
6674 ins_pipe(ialu_reg);
6675 %}
6676
6677 instruct countLeadingZerosI_bsr(eRegI dst, eRegI src, eFlagsReg cr) %{
6678 predicate(!UseCountLeadingZerosInstruction);
6679 match(Set dst (CountLeadingZerosI src));
6680 effect(KILL cr);
6681
6682 format %{ "BSR $dst, $src\t# count leading zeros (int)\n\t"
6683 "JNZ skip\n\t"
6684 "MOV $dst, -1\n"
6685 "skip:\n\t"
6686 "NEG $dst\n\t"
6687 "ADD $dst, 31" %}
6688 ins_encode %{
6689 Register Rdst = $dst$$Register;
6690 Register Rsrc = $src$$Register;
6691 Label skip;
6692 __ bsrl(Rdst, Rsrc);
6693 __ jccb(Assembler::notZero, skip);
6694 __ movl(Rdst, -1);
6695 __ bind(skip);
6696 __ negl(Rdst);
6697 __ addl(Rdst, BitsPerInt - 1);
6698 %}
6699 ins_pipe(ialu_reg);
6700 %}
6701
6702 instruct countLeadingZerosL(eRegI dst, eRegL src, eFlagsReg cr) %{
6703 predicate(UseCountLeadingZerosInstruction);
6704 match(Set dst (CountLeadingZerosL src));
6705 effect(TEMP dst, KILL cr);
6706
6707 format %{ "LZCNT $dst, $src.hi\t# count leading zeros (long)\n\t"
6708 "JNC done\n\t"
6709 "LZCNT $dst, $src.lo\n\t"
6710 "ADD $dst, 32\n"
6711 "done:" %}
6712 ins_encode %{
6713 Register Rdst = $dst$$Register;
6714 Register Rsrc = $src$$Register;
6715 Label done;
6716 __ lzcntl(Rdst, HIGH_FROM_LOW(Rsrc));
6717 __ jccb(Assembler::carryClear, done);
6718 __ lzcntl(Rdst, Rsrc);
6719 __ addl(Rdst, BitsPerInt);
6720 __ bind(done);
6721 %}
6722 ins_pipe(ialu_reg);
6723 %}
6724
6725 instruct countLeadingZerosL_bsr(eRegI dst, eRegL src, eFlagsReg cr) %{
6726 predicate(!UseCountLeadingZerosInstruction);
6727 match(Set dst (CountLeadingZerosL src));
6728 effect(TEMP dst, KILL cr);
6729
6730 format %{ "BSR $dst, $src.hi\t# count leading zeros (long)\n\t"
6731 "JZ msw_is_zero\n\t"
6732 "ADD $dst, 32\n\t"
6733 "JMP not_zero\n"
6734 "msw_is_zero:\n\t"
6735 "BSR $dst, $src.lo\n\t"
6736 "JNZ not_zero\n\t"
6737 "MOV $dst, -1\n"
6738 "not_zero:\n\t"
6739 "NEG $dst\n\t"
6740 "ADD $dst, 63\n" %}
6741 ins_encode %{
6742 Register Rdst = $dst$$Register;
6743 Register Rsrc = $src$$Register;
6744 Label msw_is_zero;
6745 Label not_zero;
6746 __ bsrl(Rdst, HIGH_FROM_LOW(Rsrc));
6747 __ jccb(Assembler::zero, msw_is_zero);
6748 __ addl(Rdst, BitsPerInt);
6749 __ jmpb(not_zero);
6750 __ bind(msw_is_zero);
6751 __ bsrl(Rdst, Rsrc);
6752 __ jccb(Assembler::notZero, not_zero);
6753 __ movl(Rdst, -1);
6754 __ bind(not_zero);
6755 __ negl(Rdst);
6756 __ addl(Rdst, BitsPerLong - 1);
6757 %}
6758 ins_pipe(ialu_reg);
6759 %}
6760
6761 instruct countTrailingZerosI(eRegI dst, eRegI src, eFlagsReg cr) %{
6762 match(Set dst (CountTrailingZerosI src));
6763 effect(KILL cr);
6764
6765 format %{ "BSF $dst, $src\t# count trailing zeros (int)\n\t"
6766 "JNZ done\n\t"
6767 "MOV $dst, 32\n"
6768 "done:" %}
6769 ins_encode %{
6770 Register Rdst = $dst$$Register;
6771 Label done;
6772 __ bsfl(Rdst, $src$$Register);
6773 __ jccb(Assembler::notZero, done);
6774 __ movl(Rdst, BitsPerInt);
6775 __ bind(done);
6776 %}
6777 ins_pipe(ialu_reg);
6778 %}
6779
6780 instruct countTrailingZerosL(eRegI dst, eRegL src, eFlagsReg cr) %{
6781 match(Set dst (CountTrailingZerosL src));
6782 effect(TEMP dst, KILL cr);
6783
6784 format %{ "BSF $dst, $src.lo\t# count trailing zeros (long)\n\t"
6785 "JNZ done\n\t"
6786 "BSF $dst, $src.hi\n\t"
6787 "JNZ msw_not_zero\n\t"
6788 "MOV $dst, 32\n"
6789 "msw_not_zero:\n\t"
6790 "ADD $dst, 32\n"
6791 "done:" %}
6792 ins_encode %{
6793 Register Rdst = $dst$$Register;
6794 Register Rsrc = $src$$Register;
6795 Label msw_not_zero;
6796 Label done;
6797 __ bsfl(Rdst, Rsrc);
6798 __ jccb(Assembler::notZero, done);
6799 __ bsfl(Rdst, HIGH_FROM_LOW(Rsrc));
6800 __ jccb(Assembler::notZero, msw_not_zero);
6801 __ movl(Rdst, BitsPerInt);
6802 __ bind(msw_not_zero);
6803 __ addl(Rdst, BitsPerInt);
6804 __ bind(done);
6805 %}
6806 ins_pipe(ialu_reg);
6807 %}
6808
6809
6810 //---------- Population Count Instructions -------------------------------------
6811
6812 instruct popCountI(eRegI dst, eRegI src) %{
6813 predicate(UsePopCountInstruction);
6814 match(Set dst (PopCountI src));
6815
6816 format %{ "POPCNT $dst, $src" %}
6817 ins_encode %{
6818 __ popcntl($dst$$Register, $src$$Register);
6819 %}
6820 ins_pipe(ialu_reg);
6821 %}
6822
6823 instruct popCountI_mem(eRegI dst, memory mem) %{
6824 predicate(UsePopCountInstruction);
6825 match(Set dst (PopCountI (LoadI mem)));
6826
6827 format %{ "POPCNT $dst, $mem" %}
6828 ins_encode %{
6829 __ popcntl($dst$$Register, $mem$$Address);
6830 %}
6831 ins_pipe(ialu_reg);
6832 %}
6833
6834 // Note: Long.bitCount(long) returns an int.
6835 instruct popCountL(eRegI dst, eRegL src, eRegI tmp, eFlagsReg cr) %{
6836 predicate(UsePopCountInstruction);
6837 match(Set dst (PopCountL src));
6838 effect(KILL cr, TEMP tmp, TEMP dst);
6839
6840 format %{ "POPCNT $dst, $src.lo\n\t"
6841 "POPCNT $tmp, $src.hi\n\t"
6842 "ADD $dst, $tmp" %}
6843 ins_encode %{
6844 __ popcntl($dst$$Register, $src$$Register);
6845 __ popcntl($tmp$$Register, HIGH_FROM_LOW($src$$Register));
6846 __ addl($dst$$Register, $tmp$$Register);
6847 %}
6848 ins_pipe(ialu_reg);
6849 %}
6850
6851 // Note: Long.bitCount(long) returns an int.
6852 instruct popCountL_mem(eRegI dst, memory mem, eRegI tmp, eFlagsReg cr) %{
6853 predicate(UsePopCountInstruction);
6854 match(Set dst (PopCountL (LoadL mem)));
6855 effect(KILL cr, TEMP tmp, TEMP dst);
6856
6857 format %{ "POPCNT $dst, $mem\n\t"
6858 "POPCNT $tmp, $mem+4\n\t"
6859 "ADD $dst, $tmp" %}
6860 ins_encode %{
6861 //__ popcntl($dst$$Register, $mem$$Address$$first);
6862 //__ popcntl($tmp$$Register, $mem$$Address$$second);
6863 __ popcntl($dst$$Register, Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp, false));
6864 __ popcntl($tmp$$Register, Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp + 4, false));
6865 __ addl($dst$$Register, $tmp$$Register);
6866 %}
6867 ins_pipe(ialu_reg);
6868 %}
6869
6870
6871 //----------Load/Store/Move Instructions---------------------------------------
6872 //----------Load Instructions--------------------------------------------------
6873 // Load Byte (8bit signed)
6874 instruct loadB(xRegI dst, memory mem) %{
6875 match(Set dst (LoadB mem));
6876
6877 ins_cost(125);
6878 format %{ "MOVSX8 $dst,$mem\t# byte" %}
6879
6880 ins_encode %{
6881 __ movsbl($dst$$Register, $mem$$Address);
6882 %}
6883
6884 ins_pipe(ialu_reg_mem);
6885 %}
6886
6887 // Load Byte (8bit signed) into Long Register
6888 instruct loadB2L(eRegL dst, memory mem) %{
6889 match(Set dst (ConvI2L (LoadB mem)));
6890
6891 ins_cost(375);
6892 format %{ "MOVSX8 $dst.lo,$mem\t# byte -> long\n\t"
6893 "MOV $dst.hi,$dst.lo\n\t"
6894 "SAR $dst.hi,7" %}
6895
6896 ins_encode %{
6897 __ movsbl($dst$$Register, $mem$$Address);
6898 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
6899 __ sarl(HIGH_FROM_LOW($dst$$Register), 7); // 24+1 MSB are already signed extended.
6900 %}
6901
6902 ins_pipe(ialu_reg_mem);
6903 %}
6904
6905 // Load Unsigned Byte (8bit UNsigned)
6906 instruct loadUB(xRegI dst, memory mem) %{
6907 match(Set dst (LoadUB mem));
6908
6909 ins_cost(125);
6910 format %{ "MOVZX8 $dst,$mem\t# ubyte -> int" %}
6911
6912 ins_encode %{
6913 __ movzbl($dst$$Register, $mem$$Address);
6914 %}
6915
6916 ins_pipe(ialu_reg_mem);
6917 %}
6918
6919 // Load Unsigned Byte (8 bit UNsigned) into Long Register
6920 instruct loadUB2L(eRegL dst, memory mem)
6921 %{
6922 match(Set dst (ConvI2L (LoadUB mem)));
6923
6924 ins_cost(250);
6925 format %{ "MOVZX8 $dst.lo,$mem\t# ubyte -> long\n\t"
6926 "XOR $dst.hi,$dst.hi" %}
6927
6928 ins_encode %{
6929 __ movzbl($dst$$Register, $mem$$Address);
6930 __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register));
6931 %}
6932
6933 ins_pipe(ialu_reg_mem);
6934 %}
6935
6936 // Load Short (16bit signed)
6937 instruct loadS(eRegI dst, memory mem) %{
6938 match(Set dst (LoadS mem));
6939
6940 ins_cost(125);
6941 format %{ "MOVSX $dst,$mem\t# short" %}
6942
6943 ins_encode %{
6944 __ movswl($dst$$Register, $mem$$Address);
6945 %}
6946
6947 ins_pipe(ialu_reg_mem);
6948 %}
6949
6950 // Load Short (16 bit signed) to Byte (8 bit signed)
6951 instruct loadS2B(eRegI dst, memory mem, immI_24 twentyfour) %{
6952 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
6953
6954 ins_cost(125);
6955 format %{ "MOVSX $dst, $mem\t# short -> byte" %}
6956 ins_encode %{
6957 __ movsbl($dst$$Register, $mem$$Address);
6958 %}
6959 ins_pipe(ialu_reg_mem);
6960 %}
6961
6962 // Load Short (16bit signed) into Long Register
6963 instruct loadS2L(eRegL dst, memory mem) %{
6964 match(Set dst (ConvI2L (LoadS mem)));
6965
6966 ins_cost(375);
6967 format %{ "MOVSX $dst.lo,$mem\t# short -> long\n\t"
6968 "MOV $dst.hi,$dst.lo\n\t"
6969 "SAR $dst.hi,15" %}
6970
6971 ins_encode %{
6972 __ movswl($dst$$Register, $mem$$Address);
6973 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
6974 __ sarl(HIGH_FROM_LOW($dst$$Register), 15); // 16+1 MSB are already signed extended.
6975 %}
6976
6977 ins_pipe(ialu_reg_mem);
6978 %}
6979
6980 // Load Unsigned Short/Char (16bit unsigned)
6981 instruct loadUS(eRegI dst, memory mem) %{
6982 match(Set dst (LoadUS mem));
6983
6984 ins_cost(125);
6985 format %{ "MOVZX $dst,$mem\t# ushort/char -> int" %}
6986
6987 ins_encode %{
6988 __ movzwl($dst$$Register, $mem$$Address);
6989 %}
6990
6991 ins_pipe(ialu_reg_mem);
6992 %}
6993
6994 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
6995 instruct loadUS2B(eRegI dst, memory mem, immI_24 twentyfour) %{
6996 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
6997
6998 ins_cost(125);
6999 format %{ "MOVSX $dst, $mem\t# ushort -> byte" %}
7000 ins_encode %{
7001 __ movsbl($dst$$Register, $mem$$Address);
7002 %}
7003 ins_pipe(ialu_reg_mem);
7004 %}
7005
7006 // Load Unsigned Short/Char (16 bit UNsigned) into Long Register
7007 instruct loadUS2L(eRegL dst, memory mem) %{
7008 match(Set dst (ConvI2L (LoadUS mem)));
7009
7010 ins_cost(250);
7011 format %{ "MOVZX $dst.lo,$mem\t# ushort/char -> long\n\t"
7012 "XOR $dst.hi,$dst.hi" %}
7013
7014 ins_encode %{
7015 __ movzwl($dst$$Register, $mem$$Address);
7016 __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register));
7017 %}
7018
7019 ins_pipe(ialu_reg_mem);
7020 %}
7021
7022 // Load Integer
7023 instruct loadI(eRegI dst, memory mem) %{
7024 match(Set dst (LoadI mem));
7025
7026 ins_cost(125);
7027 format %{ "MOV $dst,$mem\t# int" %}
7028
7029 ins_encode %{
7030 __ movl($dst$$Register, $mem$$Address);
7031 %}
7032
7033 ins_pipe(ialu_reg_mem);
7034 %}
7035
7036 // Load Integer (32 bit signed) to Byte (8 bit signed)
7037 instruct loadI2B(eRegI dst, memory mem, immI_24 twentyfour) %{
7038 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
7039
7040 ins_cost(125);
7041 format %{ "MOVSX $dst, $mem\t# int -> byte" %}
7042 ins_encode %{
7043 __ movsbl($dst$$Register, $mem$$Address);
7044 %}
7045 ins_pipe(ialu_reg_mem);
7046 %}
7047
7048 // Load Integer (32 bit signed) to Unsigned Byte (8 bit UNsigned)
7049 instruct loadI2UB(eRegI dst, memory mem, immI_255 mask) %{
7050 match(Set dst (AndI (LoadI mem) mask));
7051
7052 ins_cost(125);
7053 format %{ "MOVZX $dst, $mem\t# int -> ubyte" %}
7054 ins_encode %{
7055 __ movzbl($dst$$Register, $mem$$Address);
7056 %}
7057 ins_pipe(ialu_reg_mem);
7058 %}
7059
7060 // Load Integer (32 bit signed) to Short (16 bit signed)
7061 instruct loadI2S(eRegI dst, memory mem, immI_16 sixteen) %{
7062 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
7063
7064 ins_cost(125);
7065 format %{ "MOVSX $dst, $mem\t# int -> short" %}
7066 ins_encode %{
7067 __ movswl($dst$$Register, $mem$$Address);
7068 %}
7069 ins_pipe(ialu_reg_mem);
7070 %}
7071
7072 // Load Integer (32 bit signed) to Unsigned Short/Char (16 bit UNsigned)
7073 instruct loadI2US(eRegI dst, memory mem, immI_65535 mask) %{
7074 match(Set dst (AndI (LoadI mem) mask));
7075
7076 ins_cost(125);
7077 format %{ "MOVZX $dst, $mem\t# int -> ushort/char" %}
7078 ins_encode %{
7079 __ movzwl($dst$$Register, $mem$$Address);
7080 %}
7081 ins_pipe(ialu_reg_mem);
7082 %}
7083
7084 // Load Integer into Long Register
7085 instruct loadI2L(eRegL dst, memory mem) %{
7086 match(Set dst (ConvI2L (LoadI mem)));
7087
7088 ins_cost(375);
7089 format %{ "MOV $dst.lo,$mem\t# int -> long\n\t"
7090 "MOV $dst.hi,$dst.lo\n\t"
7091 "SAR $dst.hi,31" %}
7092
7093 ins_encode %{
7094 __ movl($dst$$Register, $mem$$Address);
7095 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
7096 __ sarl(HIGH_FROM_LOW($dst$$Register), 31);
7097 %}
7098
7099 ins_pipe(ialu_reg_mem);
7100 %}
7101
7102 // Load Unsigned Integer into Long Register
7103 instruct loadUI2L(eRegL dst, memory mem) %{
7104 match(Set dst (LoadUI2L mem));
7105
7106 ins_cost(250);
7107 format %{ "MOV $dst.lo,$mem\t# uint -> long\n\t"
7108 "XOR $dst.hi,$dst.hi" %}
7109
7110 ins_encode %{
7111 __ movl($dst$$Register, $mem$$Address);
7112 __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register));
7113 %}
7114
7115 ins_pipe(ialu_reg_mem);
7116 %}
7117
7118 // Load Long. Cannot clobber address while loading, so restrict address
7119 // register to ESI
7120 instruct loadL(eRegL dst, load_long_memory mem) %{
7121 predicate(!((LoadLNode*)n)->require_atomic_access());
7122 match(Set dst (LoadL mem));
7123
7124 ins_cost(250);
7125 format %{ "MOV $dst.lo,$mem\t# long\n\t"
7126 "MOV $dst.hi,$mem+4" %}
7127
7128 ins_encode %{
7129 Address Amemlo = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp, false);
7130 Address Amemhi = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp + 4, false);
7131 __ movl($dst$$Register, Amemlo);
7132 __ movl(HIGH_FROM_LOW($dst$$Register), Amemhi);
7133 %}
7134
7135 ins_pipe(ialu_reg_long_mem);
7136 %}
7137
7138 // Volatile Load Long. Must be atomic, so do 64-bit FILD
7139 // then store it down to the stack and reload on the int
7140 // side.
7141 instruct loadL_volatile(stackSlotL dst, memory mem) %{
7142 predicate(UseSSE<=1 && ((LoadLNode*)n)->require_atomic_access());
7143 match(Set dst (LoadL mem));
7144
7145 ins_cost(200);
7146 format %{ "FILD $mem\t# Atomic volatile long load\n\t"
7147 "FISTp $dst" %}
7148 ins_encode(enc_loadL_volatile(mem,dst));
7149 ins_pipe( fpu_reg_mem );
7150 %}
7151
7152 instruct loadLX_volatile(stackSlotL dst, memory mem, regXD tmp) %{
7153 predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access());
7154 match(Set dst (LoadL mem));
7155 effect(TEMP tmp);
7156 ins_cost(180);
7157 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
7158 "MOVSD $dst,$tmp" %}
7159 ins_encode(enc_loadLX_volatile(mem, dst, tmp));
7160 ins_pipe( pipe_slow );
7161 %}
7162
7163 instruct loadLX_reg_volatile(eRegL dst, memory mem, regXD tmp) %{
7164 predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access());
7165 match(Set dst (LoadL mem));
7166 effect(TEMP tmp);
7167 ins_cost(160);
7168 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
7169 "MOVD $dst.lo,$tmp\n\t"
7170 "PSRLQ $tmp,32\n\t"
7171 "MOVD $dst.hi,$tmp" %}
7172 ins_encode(enc_loadLX_reg_volatile(mem, dst, tmp));
7173 ins_pipe( pipe_slow );
7174 %}
7175
7176 // Load Range
7177 instruct loadRange(eRegI dst, memory mem) %{
7178 match(Set dst (LoadRange mem));
7179
7180 ins_cost(125);
7181 format %{ "MOV $dst,$mem" %}
7182 opcode(0x8B);
7183 ins_encode( OpcP, RegMem(dst,mem));
7184 ins_pipe( ialu_reg_mem );
7185 %}
7186
7187
7188 // Load Pointer
7189 instruct loadP(eRegP dst, memory mem) %{
7190 match(Set dst (LoadP mem));
7191
7192 ins_cost(125);
7193 format %{ "MOV $dst,$mem" %}
7194 opcode(0x8B);
7195 ins_encode( OpcP, RegMem(dst,mem));
7196 ins_pipe( ialu_reg_mem );
7197 %}
7198
7199 // Load Klass Pointer
7200 instruct loadKlass(eRegP dst, memory mem) %{
7201 match(Set dst (LoadKlass mem));
7202
7203 ins_cost(125);
7204 format %{ "MOV $dst,$mem" %}
7205 opcode(0x8B);
7206 ins_encode( OpcP, RegMem(dst,mem));
7207 ins_pipe( ialu_reg_mem );
7208 %}
7209
7210 // Load Double
7211 instruct loadD(regD dst, memory mem) %{
7212 predicate(UseSSE<=1);
7213 match(Set dst (LoadD mem));
7214
7215 ins_cost(150);
7216 format %{ "FLD_D ST,$mem\n\t"
7217 "FSTP $dst" %}
7218 opcode(0xDD); /* DD /0 */
7219 ins_encode( OpcP, RMopc_Mem(0x00,mem),
7220 Pop_Reg_D(dst) );
7221 ins_pipe( fpu_reg_mem );
7222 %}
7223
7224 // Load Double to XMM
7225 instruct loadXD(regXD dst, memory mem) %{
7226 predicate(UseSSE>=2 && UseXmmLoadAndClearUpper);
7227 match(Set dst (LoadD mem));
7228 ins_cost(145);
7229 format %{ "MOVSD $dst,$mem" %}
7230 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x10), RegMem(dst,mem));
7231 ins_pipe( pipe_slow );
7232 %}
7233
7234 instruct loadXD_partial(regXD dst, memory mem) %{
7235 predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper);
7236 match(Set dst (LoadD mem));
7237 ins_cost(145);
7238 format %{ "MOVLPD $dst,$mem" %}
7239 ins_encode( Opcode(0x66), Opcode(0x0F), Opcode(0x12), RegMem(dst,mem));
7240 ins_pipe( pipe_slow );
7241 %}
7242
7243 // Load to XMM register (single-precision floating point)
7244 // MOVSS instruction
7245 instruct loadX(regX dst, memory mem) %{
7246 predicate(UseSSE>=1);
7247 match(Set dst (LoadF mem));
7248 ins_cost(145);
7249 format %{ "MOVSS $dst,$mem" %}
7250 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x10), RegMem(dst,mem));
7251 ins_pipe( pipe_slow );
7252 %}
7253
7254 // Load Float
7255 instruct loadF(regF dst, memory mem) %{
7256 predicate(UseSSE==0);
7257 match(Set dst (LoadF mem));
7258
7259 ins_cost(150);
7260 format %{ "FLD_S ST,$mem\n\t"
7261 "FSTP $dst" %}
7262 opcode(0xD9); /* D9 /0 */
7263 ins_encode( OpcP, RMopc_Mem(0x00,mem),
7264 Pop_Reg_F(dst) );
7265 ins_pipe( fpu_reg_mem );
7266 %}
7267
7268 // Load Aligned Packed Byte to XMM register
7269 instruct loadA8B(regXD dst, memory mem) %{
7270 predicate(UseSSE>=1);
7271 match(Set dst (Load8B mem));
7272 ins_cost(125);
7273 format %{ "MOVQ $dst,$mem\t! packed8B" %}
7274 ins_encode( movq_ld(dst, mem));
7275 ins_pipe( pipe_slow );
7276 %}
7277
7278 // Load Aligned Packed Short to XMM register
7279 instruct loadA4S(regXD dst, memory mem) %{
7280 predicate(UseSSE>=1);
7281 match(Set dst (Load4S mem));
7282 ins_cost(125);
7283 format %{ "MOVQ $dst,$mem\t! packed4S" %}
7284 ins_encode( movq_ld(dst, mem));
7285 ins_pipe( pipe_slow );
7286 %}
7287
7288 // Load Aligned Packed Char to XMM register
7289 instruct loadA4C(regXD dst, memory mem) %{
7290 predicate(UseSSE>=1);
7291 match(Set dst (Load4C mem));
7292 ins_cost(125);
7293 format %{ "MOVQ $dst,$mem\t! packed4C" %}
7294 ins_encode( movq_ld(dst, mem));
7295 ins_pipe( pipe_slow );
7296 %}
7297
7298 // Load Aligned Packed Integer to XMM register
7299 instruct load2IU(regXD dst, memory mem) %{
7300 predicate(UseSSE>=1);
7301 match(Set dst (Load2I mem));
7302 ins_cost(125);
7303 format %{ "MOVQ $dst,$mem\t! packed2I" %}
7304 ins_encode( movq_ld(dst, mem));
7305 ins_pipe( pipe_slow );
7306 %}
7307
7308 // Load Aligned Packed Single to XMM
7309 instruct loadA2F(regXD dst, memory mem) %{
7310 predicate(UseSSE>=1);
7311 match(Set dst (Load2F mem));
7312 ins_cost(145);
7313 format %{ "MOVQ $dst,$mem\t! packed2F" %}
7314 ins_encode( movq_ld(dst, mem));
7315 ins_pipe( pipe_slow );
7316 %}
7317
7318 // Load Effective Address
7319 instruct leaP8(eRegP dst, indOffset8 mem) %{
7320 match(Set dst mem);
7321
7322 ins_cost(110);
7323 format %{ "LEA $dst,$mem" %}
7324 opcode(0x8D);
7325 ins_encode( OpcP, RegMem(dst,mem));
7326 ins_pipe( ialu_reg_reg_fat );
7327 %}
7328
7329 instruct leaP32(eRegP dst, indOffset32 mem) %{
7330 match(Set dst mem);
7331
7332 ins_cost(110);
7333 format %{ "LEA $dst,$mem" %}
7334 opcode(0x8D);
7335 ins_encode( OpcP, RegMem(dst,mem));
7336 ins_pipe( ialu_reg_reg_fat );
7337 %}
7338
7339 instruct leaPIdxOff(eRegP dst, indIndexOffset mem) %{
7340 match(Set dst mem);
7341
7342 ins_cost(110);
7343 format %{ "LEA $dst,$mem" %}
7344 opcode(0x8D);
7345 ins_encode( OpcP, RegMem(dst,mem));
7346 ins_pipe( ialu_reg_reg_fat );
7347 %}
7348
7349 instruct leaPIdxScale(eRegP dst, indIndexScale mem) %{
7350 match(Set dst mem);
7351
7352 ins_cost(110);
7353 format %{ "LEA $dst,$mem" %}
7354 opcode(0x8D);
7355 ins_encode( OpcP, RegMem(dst,mem));
7356 ins_pipe( ialu_reg_reg_fat );
7357 %}
7358
7359 instruct leaPIdxScaleOff(eRegP dst, indIndexScaleOffset mem) %{
7360 match(Set dst mem);
7361
7362 ins_cost(110);
7363 format %{ "LEA $dst,$mem" %}
7364 opcode(0x8D);
7365 ins_encode( OpcP, RegMem(dst,mem));
7366 ins_pipe( ialu_reg_reg_fat );
7367 %}
7368
7369 // Load Constant
7370 instruct loadConI(eRegI dst, immI src) %{
7371 match(Set dst src);
7372
7373 format %{ "MOV $dst,$src" %}
7374 ins_encode( LdImmI(dst, src) );
7375 ins_pipe( ialu_reg_fat );
7376 %}
7377
7378 // Load Constant zero
7379 instruct loadConI0(eRegI dst, immI0 src, eFlagsReg cr) %{
7380 match(Set dst src);
7381 effect(KILL cr);
7382
7383 ins_cost(50);
7384 format %{ "XOR $dst,$dst" %}
7385 opcode(0x33); /* + rd */
7386 ins_encode( OpcP, RegReg( dst, dst ) );
7387 ins_pipe( ialu_reg );
7388 %}
7389
7390 instruct loadConP(eRegP dst, immP src) %{
7391 match(Set dst src);
7392
7393 format %{ "MOV $dst,$src" %}
7394 opcode(0xB8); /* + rd */
7395 ins_encode( LdImmP(dst, src) );
7396 ins_pipe( ialu_reg_fat );
7397 %}
7398
7399 instruct loadConL(eRegL dst, immL src, eFlagsReg cr) %{
7400 match(Set dst src);
7401 effect(KILL cr);
7402 ins_cost(200);
7403 format %{ "MOV $dst.lo,$src.lo\n\t"
7404 "MOV $dst.hi,$src.hi" %}
7405 opcode(0xB8);
7406 ins_encode( LdImmL_Lo(dst, src), LdImmL_Hi(dst, src) );
7407 ins_pipe( ialu_reg_long_fat );
7408 %}
7409
7410 instruct loadConL0(eRegL dst, immL0 src, eFlagsReg cr) %{
7411 match(Set dst src);
7412 effect(KILL cr);
7413 ins_cost(150);
7414 format %{ "XOR $dst.lo,$dst.lo\n\t"
7415 "XOR $dst.hi,$dst.hi" %}
7416 opcode(0x33,0x33);
7417 ins_encode( RegReg_Lo(dst,dst), RegReg_Hi(dst, dst) );
7418 ins_pipe( ialu_reg_long );
7419 %}
7420
7421 // The instruction usage is guarded by predicate in operand immF().
7422 instruct loadConF(regF dst, immF src) %{
7423 match(Set dst src);
7424 ins_cost(125);
7425
7426 format %{ "FLD_S ST,$src\n\t"
7427 "FSTP $dst" %}
7428 opcode(0xD9, 0x00); /* D9 /0 */
7429 ins_encode(LdImmF(src), Pop_Reg_F(dst) );
7430 ins_pipe( fpu_reg_con );
7431 %}
7432
7433 // The instruction usage is guarded by predicate in operand immXF().
7434 instruct loadConX(regX dst, immXF con) %{
7435 match(Set dst con);
7436 ins_cost(125);
7437 format %{ "MOVSS $dst,[$con]" %}
7438 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x10), LdImmX(dst, con));
7439 ins_pipe( pipe_slow );
7440 %}
7441
7442 // The instruction usage is guarded by predicate in operand immXF0().
7443 instruct loadConX0(regX dst, immXF0 src) %{
7444 match(Set dst src);
7445 ins_cost(100);
7446 format %{ "XORPS $dst,$dst\t# float 0.0" %}
7447 ins_encode( Opcode(0x0F), Opcode(0x57), RegReg(dst,dst));
7448 ins_pipe( pipe_slow );
7449 %}
7450
7451 // The instruction usage is guarded by predicate in operand immD().
7452 instruct loadConD(regD dst, immD src) %{
7453 match(Set dst src);
7454 ins_cost(125);
7455
7456 format %{ "FLD_D ST,$src\n\t"
7457 "FSTP $dst" %}
7458 ins_encode(LdImmD(src), Pop_Reg_D(dst) );
7459 ins_pipe( fpu_reg_con );
7460 %}
7461
7462 // The instruction usage is guarded by predicate in operand immXD().
7463 instruct loadConXD(regXD dst, immXD con) %{
7464 match(Set dst con);
7465 ins_cost(125);
7466 format %{ "MOVSD $dst,[$con]" %}
7467 ins_encode(load_conXD(dst, con));
7468 ins_pipe( pipe_slow );
7469 %}
7470
7471 // The instruction usage is guarded by predicate in operand immXD0().
7472 instruct loadConXD0(regXD dst, immXD0 src) %{
7473 match(Set dst src);
7474 ins_cost(100);
7475 format %{ "XORPD $dst,$dst\t# double 0.0" %}
7476 ins_encode( Opcode(0x66), Opcode(0x0F), Opcode(0x57), RegReg(dst,dst));
7477 ins_pipe( pipe_slow );
7478 %}
7479
7480 // Load Stack Slot
7481 instruct loadSSI(eRegI dst, stackSlotI src) %{
7482 match(Set dst src);
7483 ins_cost(125);
7484
7485 format %{ "MOV $dst,$src" %}
7486 opcode(0x8B);
7487 ins_encode( OpcP, RegMem(dst,src));
7488 ins_pipe( ialu_reg_mem );
7489 %}
7490
7491 instruct loadSSL(eRegL dst, stackSlotL src) %{
7492 match(Set dst src);
7493
7494 ins_cost(200);
7495 format %{ "MOV $dst,$src.lo\n\t"
7496 "MOV $dst+4,$src.hi" %}
7497 opcode(0x8B, 0x8B);
7498 ins_encode( OpcP, RegMem( dst, src ), OpcS, RegMem_Hi( dst, src ) );
7499 ins_pipe( ialu_mem_long_reg );
7500 %}
7501
7502 // Load Stack Slot
7503 instruct loadSSP(eRegP dst, stackSlotP src) %{
7504 match(Set dst src);
7505 ins_cost(125);
7506
7507 format %{ "MOV $dst,$src" %}
7508 opcode(0x8B);
7509 ins_encode( OpcP, RegMem(dst,src));
7510 ins_pipe( ialu_reg_mem );
7511 %}
7512
7513 // Load Stack Slot
7514 instruct loadSSF(regF dst, stackSlotF src) %{
7515 match(Set dst src);
7516 ins_cost(125);
7517
7518 format %{ "FLD_S $src\n\t"
7519 "FSTP $dst" %}
7520 opcode(0xD9); /* D9 /0, FLD m32real */
7521 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
7522 Pop_Reg_F(dst) );
7523 ins_pipe( fpu_reg_mem );
7524 %}
7525
7526 // Load Stack Slot
7527 instruct loadSSD(regD dst, stackSlotD src) %{
7528 match(Set dst src);
7529 ins_cost(125);
7530
7531 format %{ "FLD_D $src\n\t"
7532 "FSTP $dst" %}
7533 opcode(0xDD); /* DD /0, FLD m64real */
7534 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
7535 Pop_Reg_D(dst) );
7536 ins_pipe( fpu_reg_mem );
7537 %}
7538
7539 // Prefetch instructions.
7540 // Must be safe to execute with invalid address (cannot fault).
7541
7542 instruct prefetchr0( memory mem ) %{
7543 predicate(UseSSE==0 && !VM_Version::supports_3dnow());
7544 match(PrefetchRead mem);
7545 ins_cost(0);
7546 size(0);
7547 format %{ "PREFETCHR (non-SSE is empty encoding)" %}
7548 ins_encode();
7549 ins_pipe(empty);
7550 %}
7551
7552 instruct prefetchr( memory mem ) %{
7553 predicate(UseSSE==0 && VM_Version::supports_3dnow() || ReadPrefetchInstr==3);
7554 match(PrefetchRead mem);
7555 ins_cost(100);
7556
7557 format %{ "PREFETCHR $mem\t! Prefetch into level 1 cache for read" %}
7558 opcode(0x0F, 0x0d); /* Opcode 0F 0d /0 */
7559 ins_encode(OpcP, OpcS, RMopc_Mem(0x00,mem));
7560 ins_pipe(ialu_mem);
7561 %}
7562
7563 instruct prefetchrNTA( memory mem ) %{
7564 predicate(UseSSE>=1 && ReadPrefetchInstr==0);
7565 match(PrefetchRead mem);
7566 ins_cost(100);
7567
7568 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for read" %}
7569 opcode(0x0F, 0x18); /* Opcode 0F 18 /0 */
7570 ins_encode(OpcP, OpcS, RMopc_Mem(0x00,mem));
7571 ins_pipe(ialu_mem);
7572 %}
7573
7574 instruct prefetchrT0( memory mem ) %{
7575 predicate(UseSSE>=1 && ReadPrefetchInstr==1);
7576 match(PrefetchRead mem);
7577 ins_cost(100);
7578
7579 format %{ "PREFETCHT0 $mem\t! Prefetch into L1 and L2 caches for read" %}
7580 opcode(0x0F, 0x18); /* Opcode 0F 18 /1 */
7581 ins_encode(OpcP, OpcS, RMopc_Mem(0x01,mem));
7582 ins_pipe(ialu_mem);
7583 %}
7584
7585 instruct prefetchrT2( memory mem ) %{
7586 predicate(UseSSE>=1 && ReadPrefetchInstr==2);
7587 match(PrefetchRead mem);
7588 ins_cost(100);
7589
7590 format %{ "PREFETCHT2 $mem\t! Prefetch into L2 cache for read" %}
7591 opcode(0x0F, 0x18); /* Opcode 0F 18 /3 */
7592 ins_encode(OpcP, OpcS, RMopc_Mem(0x03,mem));
7593 ins_pipe(ialu_mem);
7594 %}
7595
7596 instruct prefetchw0( memory mem ) %{
7597 predicate(UseSSE==0 && !VM_Version::supports_3dnow());
7598 match(PrefetchWrite mem);
7599 ins_cost(0);
7600 size(0);
7601 format %{ "Prefetch (non-SSE is empty encoding)" %}
7602 ins_encode();
7603 ins_pipe(empty);
7604 %}
7605
7606 instruct prefetchw( memory mem ) %{
7607 predicate(UseSSE==0 && VM_Version::supports_3dnow() || AllocatePrefetchInstr==3);
7608 match( PrefetchWrite mem );
7609 ins_cost(100);
7610
7611 format %{ "PREFETCHW $mem\t! Prefetch into L1 cache and mark modified" %}
7612 opcode(0x0F, 0x0D); /* Opcode 0F 0D /1 */
7613 ins_encode(OpcP, OpcS, RMopc_Mem(0x01,mem));
7614 ins_pipe(ialu_mem);
7615 %}
7616
7617 instruct prefetchwNTA( memory mem ) %{
7618 predicate(UseSSE>=1 && AllocatePrefetchInstr==0);
7619 match(PrefetchWrite mem);
7620 ins_cost(100);
7621
7622 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for write" %}
7623 opcode(0x0F, 0x18); /* Opcode 0F 18 /0 */
7624 ins_encode(OpcP, OpcS, RMopc_Mem(0x00,mem));
7625 ins_pipe(ialu_mem);
7626 %}
7627
7628 instruct prefetchwT0( memory mem ) %{
7629 predicate(UseSSE>=1 && AllocatePrefetchInstr==1);
7630 match(PrefetchWrite mem);
7631 ins_cost(100);
7632
7633 format %{ "PREFETCHT0 $mem\t! Prefetch into L1 and L2 caches for write" %}
7634 opcode(0x0F, 0x18); /* Opcode 0F 18 /1 */
7635 ins_encode(OpcP, OpcS, RMopc_Mem(0x01,mem));
7636 ins_pipe(ialu_mem);
7637 %}
7638
7639 instruct prefetchwT2( memory mem ) %{
7640 predicate(UseSSE>=1 && AllocatePrefetchInstr==2);
7641 match(PrefetchWrite mem);
7642 ins_cost(100);
7643
7644 format %{ "PREFETCHT2 $mem\t! Prefetch into L2 cache for write" %}
7645 opcode(0x0F, 0x18); /* Opcode 0F 18 /3 */
7646 ins_encode(OpcP, OpcS, RMopc_Mem(0x03,mem));
7647 ins_pipe(ialu_mem);
7648 %}
7649
7650 //----------Store Instructions-------------------------------------------------
7651
7652 // Store Byte
7653 instruct storeB(memory mem, xRegI src) %{
7654 match(Set mem (StoreB mem src));
7655
7656 ins_cost(125);
7657 format %{ "MOV8 $mem,$src" %}
7658 opcode(0x88);
7659 ins_encode( OpcP, RegMem( src, mem ) );
7660 ins_pipe( ialu_mem_reg );
7661 %}
7662
7663 // Store Char/Short
7664 instruct storeC(memory mem, eRegI src) %{
7665 match(Set mem (StoreC mem src));
7666
7667 ins_cost(125);
7668 format %{ "MOV16 $mem,$src" %}
7669 opcode(0x89, 0x66);
7670 ins_encode( OpcS, OpcP, RegMem( src, mem ) );
7671 ins_pipe( ialu_mem_reg );
7672 %}
7673
7674 // Store Integer
7675 instruct storeI(memory mem, eRegI src) %{
7676 match(Set mem (StoreI mem src));
7677
7678 ins_cost(125);
7679 format %{ "MOV $mem,$src" %}
7680 opcode(0x89);
7681 ins_encode( OpcP, RegMem( src, mem ) );
7682 ins_pipe( ialu_mem_reg );
7683 %}
7684
7685 // Store Long
7686 instruct storeL(long_memory mem, eRegL src) %{
7687 predicate(!((StoreLNode*)n)->require_atomic_access());
7688 match(Set mem (StoreL mem src));
7689
7690 ins_cost(200);
7691 format %{ "MOV $mem,$src.lo\n\t"
7692 "MOV $mem+4,$src.hi" %}
7693 opcode(0x89, 0x89);
7694 ins_encode( OpcP, RegMem( src, mem ), OpcS, RegMem_Hi( src, mem ) );
7695 ins_pipe( ialu_mem_long_reg );
7696 %}
7697
7698 // Volatile Store Long. Must be atomic, so move it into
7699 // the FP TOS and then do a 64-bit FIST. Has to probe the
7700 // target address before the store (for null-ptr checks)
7701 // so the memory operand is used twice in the encoding.
7702 instruct storeL_volatile(memory mem, stackSlotL src, eFlagsReg cr ) %{
7703 predicate(UseSSE<=1 && ((StoreLNode*)n)->require_atomic_access());
7704 match(Set mem (StoreL mem src));
7705 effect( KILL cr );
7706 ins_cost(400);
7707 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
7708 "FILD $src\n\t"
7709 "FISTp $mem\t # 64-bit atomic volatile long store" %}
7710 opcode(0x3B);
7711 ins_encode( OpcP, RegMem( EAX, mem ), enc_storeL_volatile(mem,src));
7712 ins_pipe( fpu_reg_mem );
7713 %}
7714
7715 instruct storeLX_volatile(memory mem, stackSlotL src, regXD tmp, eFlagsReg cr) %{
7716 predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access());
7717 match(Set mem (StoreL mem src));
7718 effect( TEMP tmp, KILL cr );
7719 ins_cost(380);
7720 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
7721 "MOVSD $tmp,$src\n\t"
7722 "MOVSD $mem,$tmp\t # 64-bit atomic volatile long store" %}
7723 opcode(0x3B);
7724 ins_encode( OpcP, RegMem( EAX, mem ), enc_storeLX_volatile(mem, src, tmp));
7725 ins_pipe( pipe_slow );
7726 %}
7727
7728 instruct storeLX_reg_volatile(memory mem, eRegL src, regXD tmp2, regXD tmp, eFlagsReg cr) %{
7729 predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access());
7730 match(Set mem (StoreL mem src));
7731 effect( TEMP tmp2 , TEMP tmp, KILL cr );
7732 ins_cost(360);
7733 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
7734 "MOVD $tmp,$src.lo\n\t"
7735 "MOVD $tmp2,$src.hi\n\t"
7736 "PUNPCKLDQ $tmp,$tmp2\n\t"
7737 "MOVSD $mem,$tmp\t # 64-bit atomic volatile long store" %}
7738 opcode(0x3B);
7739 ins_encode( OpcP, RegMem( EAX, mem ), enc_storeLX_reg_volatile(mem, src, tmp, tmp2));
7740 ins_pipe( pipe_slow );
7741 %}
7742
7743 // Store Pointer; for storing unknown oops and raw pointers
7744 instruct storeP(memory mem, anyRegP src) %{
7745 match(Set mem (StoreP mem src));
7746
7747 ins_cost(125);
7748 format %{ "MOV $mem,$src" %}
7749 opcode(0x89);
7750 ins_encode( OpcP, RegMem( src, mem ) );
7751 ins_pipe( ialu_mem_reg );
7752 %}
7753
7754 // Store Integer Immediate
7755 instruct storeImmI(memory mem, immI src) %{
7756 match(Set mem (StoreI mem src));
7757
7758 ins_cost(150);
7759 format %{ "MOV $mem,$src" %}
7760 opcode(0xC7); /* C7 /0 */
7761 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32( src ));
7762 ins_pipe( ialu_mem_imm );
7763 %}
7764
7765 // Store Short/Char Immediate
7766 instruct storeImmI16(memory mem, immI16 src) %{
7767 predicate(UseStoreImmI16);
7768 match(Set mem (StoreC mem src));
7769
7770 ins_cost(150);
7771 format %{ "MOV16 $mem,$src" %}
7772 opcode(0xC7); /* C7 /0 Same as 32 store immediate with prefix */
7773 ins_encode( SizePrefix, OpcP, RMopc_Mem(0x00,mem), Con16( src ));
7774 ins_pipe( ialu_mem_imm );
7775 %}
7776
7777 // Store Pointer Immediate; null pointers or constant oops that do not
7778 // need card-mark barriers.
7779 instruct storeImmP(memory mem, immP src) %{
7780 match(Set mem (StoreP mem src));
7781
7782 ins_cost(150);
7783 format %{ "MOV $mem,$src" %}
7784 opcode(0xC7); /* C7 /0 */
7785 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32( src ));
7786 ins_pipe( ialu_mem_imm );
7787 %}
7788
7789 // Store Byte Immediate
7790 instruct storeImmB(memory mem, immI8 src) %{
7791 match(Set mem (StoreB mem src));
7792
7793 ins_cost(150);
7794 format %{ "MOV8 $mem,$src" %}
7795 opcode(0xC6); /* C6 /0 */
7796 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con8or32( src ));
7797 ins_pipe( ialu_mem_imm );
7798 %}
7799
7800 // Store Aligned Packed Byte XMM register to memory
7801 instruct storeA8B(memory mem, regXD src) %{
7802 predicate(UseSSE>=1);
7803 match(Set mem (Store8B mem src));
7804 ins_cost(145);
7805 format %{ "MOVQ $mem,$src\t! packed8B" %}
7806 ins_encode( movq_st(mem, src));
7807 ins_pipe( pipe_slow );
7808 %}
7809
7810 // Store Aligned Packed Char/Short XMM register to memory
7811 instruct storeA4C(memory mem, regXD src) %{
7812 predicate(UseSSE>=1);
7813 match(Set mem (Store4C mem src));
7814 ins_cost(145);
7815 format %{ "MOVQ $mem,$src\t! packed4C" %}
7816 ins_encode( movq_st(mem, src));
7817 ins_pipe( pipe_slow );
7818 %}
7819
7820 // Store Aligned Packed Integer XMM register to memory
7821 instruct storeA2I(memory mem, regXD src) %{
7822 predicate(UseSSE>=1);
7823 match(Set mem (Store2I mem src));
7824 ins_cost(145);
7825 format %{ "MOVQ $mem,$src\t! packed2I" %}
7826 ins_encode( movq_st(mem, src));
7827 ins_pipe( pipe_slow );
7828 %}
7829
7830 // Store CMS card-mark Immediate
7831 instruct storeImmCM(memory mem, immI8 src) %{
7832 match(Set mem (StoreCM mem src));
7833
7834 ins_cost(150);
7835 format %{ "MOV8 $mem,$src\t! CMS card-mark imm0" %}
7836 opcode(0xC6); /* C6 /0 */
7837 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con8or32( src ));
7838 ins_pipe( ialu_mem_imm );
7839 %}
7840
7841 // Store Double
7842 instruct storeD( memory mem, regDPR1 src) %{
7843 predicate(UseSSE<=1);
7844 match(Set mem (StoreD mem src));
7845
7846 ins_cost(100);
7847 format %{ "FST_D $mem,$src" %}
7848 opcode(0xDD); /* DD /2 */
7849 ins_encode( enc_FP_store(mem,src) );
7850 ins_pipe( fpu_mem_reg );
7851 %}
7852
7853 // Store double does rounding on x86
7854 instruct storeD_rounded( memory mem, regDPR1 src) %{
7855 predicate(UseSSE<=1);
7856 match(Set mem (StoreD mem (RoundDouble src)));
7857
7858 ins_cost(100);
7859 format %{ "FST_D $mem,$src\t# round" %}
7860 opcode(0xDD); /* DD /2 */
7861 ins_encode( enc_FP_store(mem,src) );
7862 ins_pipe( fpu_mem_reg );
7863 %}
7864
7865 // Store XMM register to memory (double-precision floating points)
7866 // MOVSD instruction
7867 instruct storeXD(memory mem, regXD src) %{
7868 predicate(UseSSE>=2);
7869 match(Set mem (StoreD mem src));
7870 ins_cost(95);
7871 format %{ "MOVSD $mem,$src" %}
7872 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x11), RegMem(src, mem));
7873 ins_pipe( pipe_slow );
7874 %}
7875
7876 // Store XMM register to memory (single-precision floating point)
7877 // MOVSS instruction
7878 instruct storeX(memory mem, regX src) %{
7879 predicate(UseSSE>=1);
7880 match(Set mem (StoreF mem src));
7881 ins_cost(95);
7882 format %{ "MOVSS $mem,$src" %}
7883 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x11), RegMem(src, mem));
7884 ins_pipe( pipe_slow );
7885 %}
7886
7887 // Store Aligned Packed Single Float XMM register to memory
7888 instruct storeA2F(memory mem, regXD src) %{
7889 predicate(UseSSE>=1);
7890 match(Set mem (Store2F mem src));
7891 ins_cost(145);
7892 format %{ "MOVQ $mem,$src\t! packed2F" %}
7893 ins_encode( movq_st(mem, src));
7894 ins_pipe( pipe_slow );
7895 %}
7896
7897 // Store Float
7898 instruct storeF( memory mem, regFPR1 src) %{
7899 predicate(UseSSE==0);
7900 match(Set mem (StoreF mem src));
7901
7902 ins_cost(100);
7903 format %{ "FST_S $mem,$src" %}
7904 opcode(0xD9); /* D9 /2 */
7905 ins_encode( enc_FP_store(mem,src) );
7906 ins_pipe( fpu_mem_reg );
7907 %}
7908
7909 // Store Float does rounding on x86
7910 instruct storeF_rounded( memory mem, regFPR1 src) %{
7911 predicate(UseSSE==0);
7912 match(Set mem (StoreF mem (RoundFloat src)));
7913
7914 ins_cost(100);
7915 format %{ "FST_S $mem,$src\t# round" %}
7916 opcode(0xD9); /* D9 /2 */
7917 ins_encode( enc_FP_store(mem,src) );
7918 ins_pipe( fpu_mem_reg );
7919 %}
7920
7921 // Store Float does rounding on x86
7922 instruct storeF_Drounded( memory mem, regDPR1 src) %{
7923 predicate(UseSSE<=1);
7924 match(Set mem (StoreF mem (ConvD2F src)));
7925
7926 ins_cost(100);
7927 format %{ "FST_S $mem,$src\t# D-round" %}
7928 opcode(0xD9); /* D9 /2 */
7929 ins_encode( enc_FP_store(mem,src) );
7930 ins_pipe( fpu_mem_reg );
7931 %}
7932
7933 // Store immediate Float value (it is faster than store from FPU register)
7934 // The instruction usage is guarded by predicate in operand immF().
7935 instruct storeF_imm( memory mem, immF src) %{
7936 match(Set mem (StoreF mem src));
7937
7938 ins_cost(50);
7939 format %{ "MOV $mem,$src\t# store float" %}
7940 opcode(0xC7); /* C7 /0 */
7941 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32F_as_bits( src ));
7942 ins_pipe( ialu_mem_imm );
7943 %}
7944
7945 // Store immediate Float value (it is faster than store from XMM register)
7946 // The instruction usage is guarded by predicate in operand immXF().
7947 instruct storeX_imm( memory mem, immXF src) %{
7948 match(Set mem (StoreF mem src));
7949
7950 ins_cost(50);
7951 format %{ "MOV $mem,$src\t# store float" %}
7952 opcode(0xC7); /* C7 /0 */
7953 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32XF_as_bits( src ));
7954 ins_pipe( ialu_mem_imm );
7955 %}
7956
7957 // Store Integer to stack slot
7958 instruct storeSSI(stackSlotI dst, eRegI src) %{
7959 match(Set dst src);
7960
7961 ins_cost(100);
7962 format %{ "MOV $dst,$src" %}
7963 opcode(0x89);
7964 ins_encode( OpcPRegSS( dst, src ) );
7965 ins_pipe( ialu_mem_reg );
7966 %}
7967
7968 // Store Integer to stack slot
7969 instruct storeSSP(stackSlotP dst, eRegP src) %{
7970 match(Set dst src);
7971
7972 ins_cost(100);
7973 format %{ "MOV $dst,$src" %}
7974 opcode(0x89);
7975 ins_encode( OpcPRegSS( dst, src ) );
7976 ins_pipe( ialu_mem_reg );
7977 %}
7978
7979 // Store Long to stack slot
7980 instruct storeSSL(stackSlotL dst, eRegL src) %{
7981 match(Set dst src);
7982
7983 ins_cost(200);
7984 format %{ "MOV $dst,$src.lo\n\t"
7985 "MOV $dst+4,$src.hi" %}
7986 opcode(0x89, 0x89);
7987 ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) );
7988 ins_pipe( ialu_mem_long_reg );
7989 %}
7990
7991 //----------MemBar Instructions-----------------------------------------------
7992 // Memory barrier flavors
7993
7994 instruct membar_acquire() %{
7995 match(MemBarAcquire);
7996 ins_cost(400);
7997
7998 size(0);
7999 format %{ "MEMBAR-acquire ! (empty encoding)" %}
8000 ins_encode();
8001 ins_pipe(empty);
8002 %}
8003
8004 instruct membar_acquire_lock() %{
8005 match(MemBarAcquire);
8006 predicate(Matcher::prior_fast_lock(n));
8007 ins_cost(0);
8008
8009 size(0);
8010 format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)" %}
8011 ins_encode( );
8012 ins_pipe(empty);
8013 %}
8014
8015 instruct membar_release() %{
8016 match(MemBarRelease);
8017 ins_cost(400);
8018
8019 size(0);
8020 format %{ "MEMBAR-release ! (empty encoding)" %}
8021 ins_encode( );
8022 ins_pipe(empty);
8023 %}
8024
8025 instruct membar_release_lock() %{
8026 match(MemBarRelease);
8027 predicate(Matcher::post_fast_unlock(n));
8028 ins_cost(0);
8029
8030 size(0);
8031 format %{ "MEMBAR-release (a FastUnlock follows so empty encoding)" %}
8032 ins_encode( );
8033 ins_pipe(empty);
8034 %}
8035
8036 instruct membar_volatile(eFlagsReg cr) %{
8037 match(MemBarVolatile);
8038 effect(KILL cr);
8039 ins_cost(400);
8040
8041 format %{
8042 $$template
8043 if (os::is_MP()) {
8044 $$emit$$"LOCK ADDL [ESP + #0], 0\t! membar_volatile"
8045 } else {
8046 $$emit$$"MEMBAR-volatile ! (empty encoding)"
8047 }
8048 %}
8049 ins_encode %{
8050 __ membar(Assembler::StoreLoad);
8051 %}
8052 ins_pipe(pipe_slow);
8053 %}
8054
8055 instruct unnecessary_membar_volatile() %{
8056 match(MemBarVolatile);
8057 predicate(Matcher::post_store_load_barrier(n));
8058 ins_cost(0);
8059
8060 size(0);
8061 format %{ "MEMBAR-volatile (unnecessary so empty encoding)" %}
8062 ins_encode( );
8063 ins_pipe(empty);
8064 %}
8065
8066 //----------Move Instructions--------------------------------------------------
8067 instruct castX2P(eAXRegP dst, eAXRegI src) %{
8068 match(Set dst (CastX2P src));
8069 format %{ "# X2P $dst, $src" %}
8070 ins_encode( /*empty encoding*/ );
8071 ins_cost(0);
8072 ins_pipe(empty);
8073 %}
8074
8075 instruct castP2X(eRegI dst, eRegP src ) %{
8076 match(Set dst (CastP2X src));
8077 ins_cost(50);
8078 format %{ "MOV $dst, $src\t# CastP2X" %}
8079 ins_encode( enc_Copy( dst, src) );
8080 ins_pipe( ialu_reg_reg );
8081 %}
8082
8083 //----------Conditional Move---------------------------------------------------
8084 // Conditional move
8085 instruct cmovI_reg(eRegI dst, eRegI src, eFlagsReg cr, cmpOp cop ) %{
8086 predicate(VM_Version::supports_cmov() );
8087 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
8088 ins_cost(200);
8089 format %{ "CMOV$cop $dst,$src" %}
8090 opcode(0x0F,0x40);
8091 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
8092 ins_pipe( pipe_cmov_reg );
8093 %}
8094
8095 instruct cmovI_regU( cmpOpU cop, eFlagsRegU cr, eRegI dst, eRegI src ) %{
8096 predicate(VM_Version::supports_cmov() );
8097 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
8098 ins_cost(200);
8099 format %{ "CMOV$cop $dst,$src" %}
8100 opcode(0x0F,0x40);
8101 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
8102 ins_pipe( pipe_cmov_reg );
8103 %}
8104
8105 instruct cmovI_regUCF( cmpOpUCF cop, eFlagsRegUCF cr, eRegI dst, eRegI src ) %{
8106 predicate(VM_Version::supports_cmov() );
8107 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
8108 ins_cost(200);
8109 expand %{
8110 cmovI_regU(cop, cr, dst, src);
8111 %}
8112 %}
8113
8114 // Conditional move
8115 instruct cmovI_mem(cmpOp cop, eFlagsReg cr, eRegI dst, memory src) %{
8116 predicate(VM_Version::supports_cmov() );
8117 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
8118 ins_cost(250);
8119 format %{ "CMOV$cop $dst,$src" %}
8120 opcode(0x0F,0x40);
8121 ins_encode( enc_cmov(cop), RegMem( dst, src ) );
8122 ins_pipe( pipe_cmov_mem );
8123 %}
8124
8125 // Conditional move
8126 instruct cmovI_memU(cmpOpU cop, eFlagsRegU cr, eRegI dst, memory src) %{
8127 predicate(VM_Version::supports_cmov() );
8128 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
8129 ins_cost(250);
8130 format %{ "CMOV$cop $dst,$src" %}
8131 opcode(0x0F,0x40);
8132 ins_encode( enc_cmov(cop), RegMem( dst, src ) );
8133 ins_pipe( pipe_cmov_mem );
8134 %}
8135
8136 instruct cmovI_memUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegI dst, memory src) %{
8137 predicate(VM_Version::supports_cmov() );
8138 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
8139 ins_cost(250);
8140 expand %{
8141 cmovI_memU(cop, cr, dst, src);
8142 %}
8143 %}
8144
8145 // Conditional move
8146 instruct cmovP_reg(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{
8147 predicate(VM_Version::supports_cmov() );
8148 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
8149 ins_cost(200);
8150 format %{ "CMOV$cop $dst,$src\t# ptr" %}
8151 opcode(0x0F,0x40);
8152 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
8153 ins_pipe( pipe_cmov_reg );
8154 %}
8155
8156 // Conditional move (non-P6 version)
8157 // Note: a CMoveP is generated for stubs and native wrappers
8158 // regardless of whether we are on a P6, so we
8159 // emulate a cmov here
8160 instruct cmovP_reg_nonP6(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{
8161 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
8162 ins_cost(300);
8163 format %{ "Jn$cop skip\n\t"
8164 "MOV $dst,$src\t# pointer\n"
8165 "skip:" %}
8166 opcode(0x8b);
8167 ins_encode( enc_cmov_branch(cop, 0x2), OpcP, RegReg(dst, src));
8168 ins_pipe( pipe_cmov_reg );
8169 %}
8170
8171 // Conditional move
8172 instruct cmovP_regU(cmpOpU cop, eFlagsRegU cr, eRegP dst, eRegP src ) %{
8173 predicate(VM_Version::supports_cmov() );
8174 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
8175 ins_cost(200);
8176 format %{ "CMOV$cop $dst,$src\t# ptr" %}
8177 opcode(0x0F,0x40);
8178 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
8179 ins_pipe( pipe_cmov_reg );
8180 %}
8181
8182 instruct cmovP_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegP dst, eRegP src ) %{
8183 predicate(VM_Version::supports_cmov() );
8184 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
8185 ins_cost(200);
8186 expand %{
8187 cmovP_regU(cop, cr, dst, src);
8188 %}
8189 %}
8190
8191 // DISABLED: Requires the ADLC to emit a bottom_type call that
8192 // correctly meets the two pointer arguments; one is an incoming
8193 // register but the other is a memory operand. ALSO appears to
8194 // be buggy with implicit null checks.
8195 //
8196 //// Conditional move
8197 //instruct cmovP_mem(cmpOp cop, eFlagsReg cr, eRegP dst, memory src) %{
8198 // predicate(VM_Version::supports_cmov() );
8199 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
8200 // ins_cost(250);
8201 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
8202 // opcode(0x0F,0x40);
8203 // ins_encode( enc_cmov(cop), RegMem( dst, src ) );
8204 // ins_pipe( pipe_cmov_mem );
8205 //%}
8206 //
8207 //// Conditional move
8208 //instruct cmovP_memU(cmpOpU cop, eFlagsRegU cr, eRegP dst, memory src) %{
8209 // predicate(VM_Version::supports_cmov() );
8210 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
8211 // ins_cost(250);
8212 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
8213 // opcode(0x0F,0x40);
8214 // ins_encode( enc_cmov(cop), RegMem( dst, src ) );
8215 // ins_pipe( pipe_cmov_mem );
8216 //%}
8217
8218 // Conditional move
8219 instruct fcmovD_regU(cmpOp_fcmov cop, eFlagsRegU cr, regDPR1 dst, regD src) %{
8220 predicate(UseSSE<=1);
8221 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
8222 ins_cost(200);
8223 format %{ "FCMOV$cop $dst,$src\t# double" %}
8224 opcode(0xDA);
8225 ins_encode( enc_cmov_d(cop,src) );
8226 ins_pipe( pipe_cmovD_reg );
8227 %}
8228
8229 // Conditional move
8230 instruct fcmovF_regU(cmpOp_fcmov cop, eFlagsRegU cr, regFPR1 dst, regF src) %{
8231 predicate(UseSSE==0);
8232 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
8233 ins_cost(200);
8234 format %{ "FCMOV$cop $dst,$src\t# float" %}
8235 opcode(0xDA);
8236 ins_encode( enc_cmov_d(cop,src) );
8237 ins_pipe( pipe_cmovD_reg );
8238 %}
8239
8240 // Float CMOV on Intel doesn't handle *signed* compares, only unsigned.
8241 instruct fcmovD_regS(cmpOp cop, eFlagsReg cr, regD dst, regD src) %{
8242 predicate(UseSSE<=1);
8243 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
8244 ins_cost(200);
8245 format %{ "Jn$cop skip\n\t"
8246 "MOV $dst,$src\t# double\n"
8247 "skip:" %}
8248 opcode (0xdd, 0x3); /* DD D8+i or DD /3 */
8249 ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_D(src), OpcP, RegOpc(dst) );
8250 ins_pipe( pipe_cmovD_reg );
8251 %}
8252
8253 // Float CMOV on Intel doesn't handle *signed* compares, only unsigned.
8254 instruct fcmovF_regS(cmpOp cop, eFlagsReg cr, regF dst, regF src) %{
8255 predicate(UseSSE==0);
8256 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
8257 ins_cost(200);
8258 format %{ "Jn$cop skip\n\t"
8259 "MOV $dst,$src\t# float\n"
8260 "skip:" %}
8261 opcode (0xdd, 0x3); /* DD D8+i or DD /3 */
8262 ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_F(src), OpcP, RegOpc(dst) );
8263 ins_pipe( pipe_cmovD_reg );
8264 %}
8265
8266 // No CMOVE with SSE/SSE2
8267 instruct fcmovX_regS(cmpOp cop, eFlagsReg cr, regX dst, regX src) %{
8268 predicate (UseSSE>=1);
8269 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
8270 ins_cost(200);
8271 format %{ "Jn$cop skip\n\t"
8272 "MOVSS $dst,$src\t# float\n"
8273 "skip:" %}
8274 ins_encode %{
8275 Label skip;
8276 // Invert sense of branch from sense of CMOV
8277 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
8278 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
8279 __ bind(skip);
8280 %}
8281 ins_pipe( pipe_slow );
8282 %}
8283
8284 // No CMOVE with SSE/SSE2
8285 instruct fcmovXD_regS(cmpOp cop, eFlagsReg cr, regXD dst, regXD src) %{
8286 predicate (UseSSE>=2);
8287 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
8288 ins_cost(200);
8289 format %{ "Jn$cop skip\n\t"
8290 "MOVSD $dst,$src\t# float\n"
8291 "skip:" %}
8292 ins_encode %{
8293 Label skip;
8294 // Invert sense of branch from sense of CMOV
8295 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
8296 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
8297 __ bind(skip);
8298 %}
8299 ins_pipe( pipe_slow );
8300 %}
8301
8302 // unsigned version
8303 instruct fcmovX_regU(cmpOpU cop, eFlagsRegU cr, regX dst, regX src) %{
8304 predicate (UseSSE>=1);
8305 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
8306 ins_cost(200);
8307 format %{ "Jn$cop skip\n\t"
8308 "MOVSS $dst,$src\t# float\n"
8309 "skip:" %}
8310 ins_encode %{
8311 Label skip;
8312 // Invert sense of branch from sense of CMOV
8313 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
8314 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
8315 __ bind(skip);
8316 %}
8317 ins_pipe( pipe_slow );
8318 %}
8319
8320 instruct fcmovX_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, regX dst, regX src) %{
8321 predicate (UseSSE>=1);
8322 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
8323 ins_cost(200);
8324 expand %{
8325 fcmovX_regU(cop, cr, dst, src);
8326 %}
8327 %}
8328
8329 // unsigned version
8330 instruct fcmovXD_regU(cmpOpU cop, eFlagsRegU cr, regXD dst, regXD src) %{
8331 predicate (UseSSE>=2);
8332 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
8333 ins_cost(200);
8334 format %{ "Jn$cop skip\n\t"
8335 "MOVSD $dst,$src\t# float\n"
8336 "skip:" %}
8337 ins_encode %{
8338 Label skip;
8339 // Invert sense of branch from sense of CMOV
8340 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
8341 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
8342 __ bind(skip);
8343 %}
8344 ins_pipe( pipe_slow );
8345 %}
8346
8347 instruct fcmovXD_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, regXD dst, regXD src) %{
8348 predicate (UseSSE>=2);
8349 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
8350 ins_cost(200);
8351 expand %{
8352 fcmovXD_regU(cop, cr, dst, src);
8353 %}
8354 %}
8355
8356 instruct cmovL_reg(cmpOp cop, eFlagsReg cr, eRegL dst, eRegL src) %{
8357 predicate(VM_Version::supports_cmov() );
8358 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
8359 ins_cost(200);
8360 format %{ "CMOV$cop $dst.lo,$src.lo\n\t"
8361 "CMOV$cop $dst.hi,$src.hi" %}
8362 opcode(0x0F,0x40);
8363 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) );
8364 ins_pipe( pipe_cmov_reg_long );
8365 %}
8366
8367 instruct cmovL_regU(cmpOpU cop, eFlagsRegU cr, eRegL dst, eRegL src) %{
8368 predicate(VM_Version::supports_cmov() );
8369 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
8370 ins_cost(200);
8371 format %{ "CMOV$cop $dst.lo,$src.lo\n\t"
8372 "CMOV$cop $dst.hi,$src.hi" %}
8373 opcode(0x0F,0x40);
8374 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) );
8375 ins_pipe( pipe_cmov_reg_long );
8376 %}
8377
8378 instruct cmovL_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegL dst, eRegL src) %{
8379 predicate(VM_Version::supports_cmov() );
8380 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
8381 ins_cost(200);
8382 expand %{
8383 cmovL_regU(cop, cr, dst, src);
8384 %}
8385 %}
8386
8387 //----------Arithmetic Instructions--------------------------------------------
8388 //----------Addition Instructions----------------------------------------------
8389 // Integer Addition Instructions
8390 instruct addI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
8391 match(Set dst (AddI dst src));
8392 effect(KILL cr);
8393
8394 size(2);
8395 format %{ "ADD $dst,$src" %}
8396 opcode(0x03);
8397 ins_encode( OpcP, RegReg( dst, src) );
8398 ins_pipe( ialu_reg_reg );
8399 %}
8400
8401 instruct addI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{
8402 match(Set dst (AddI dst src));
8403 effect(KILL cr);
8404
8405 format %{ "ADD $dst,$src" %}
8406 opcode(0x81, 0x00); /* /0 id */
8407 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8408 ins_pipe( ialu_reg );
8409 %}
8410
8411 instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
8412 predicate(UseIncDec);
8413 match(Set dst (AddI dst src));
8414 effect(KILL cr);
8415
8416 size(1);
8417 format %{ "INC $dst" %}
8418 opcode(0x40); /* */
8419 ins_encode( Opc_plus( primary, dst ) );
8420 ins_pipe( ialu_reg );
8421 %}
8422
8423 instruct leaI_eReg_immI(eRegI dst, eRegI src0, immI src1) %{
8424 match(Set dst (AddI src0 src1));
8425 ins_cost(110);
8426
8427 format %{ "LEA $dst,[$src0 + $src1]" %}
8428 opcode(0x8D); /* 0x8D /r */
8429 ins_encode( OpcP, RegLea( dst, src0, src1 ) );
8430 ins_pipe( ialu_reg_reg );
8431 %}
8432
8433 instruct leaP_eReg_immI(eRegP dst, eRegP src0, immI src1) %{
8434 match(Set dst (AddP src0 src1));
8435 ins_cost(110);
8436
8437 format %{ "LEA $dst,[$src0 + $src1]\t# ptr" %}
8438 opcode(0x8D); /* 0x8D /r */
8439 ins_encode( OpcP, RegLea( dst, src0, src1 ) );
8440 ins_pipe( ialu_reg_reg );
8441 %}
8442
8443 instruct decI_eReg(eRegI dst, immI_M1 src, eFlagsReg cr) %{
8444 predicate(UseIncDec);
8445 match(Set dst (AddI dst src));
8446 effect(KILL cr);
8447
8448 size(1);
8449 format %{ "DEC $dst" %}
8450 opcode(0x48); /* */
8451 ins_encode( Opc_plus( primary, dst ) );
8452 ins_pipe( ialu_reg );
8453 %}
8454
8455 instruct addP_eReg(eRegP dst, eRegI src, eFlagsReg cr) %{
8456 match(Set dst (AddP dst src));
8457 effect(KILL cr);
8458
8459 size(2);
8460 format %{ "ADD $dst,$src" %}
8461 opcode(0x03);
8462 ins_encode( OpcP, RegReg( dst, src) );
8463 ins_pipe( ialu_reg_reg );
8464 %}
8465
8466 instruct addP_eReg_imm(eRegP dst, immI src, eFlagsReg cr) %{
8467 match(Set dst (AddP dst src));
8468 effect(KILL cr);
8469
8470 format %{ "ADD $dst,$src" %}
8471 opcode(0x81,0x00); /* Opcode 81 /0 id */
8472 // ins_encode( RegImm( dst, src) );
8473 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8474 ins_pipe( ialu_reg );
8475 %}
8476
8477 instruct addI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{
8478 match(Set dst (AddI dst (LoadI src)));
8479 effect(KILL cr);
8480
8481 ins_cost(125);
8482 format %{ "ADD $dst,$src" %}
8483 opcode(0x03);
8484 ins_encode( OpcP, RegMem( dst, src) );
8485 ins_pipe( ialu_reg_mem );
8486 %}
8487
8488 instruct addI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{
8489 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
8490 effect(KILL cr);
8491
8492 ins_cost(150);
8493 format %{ "ADD $dst,$src" %}
8494 opcode(0x01); /* Opcode 01 /r */
8495 ins_encode( OpcP, RegMem( src, dst ) );
8496 ins_pipe( ialu_mem_reg );
8497 %}
8498
8499 // Add Memory with Immediate
8500 instruct addI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
8501 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
8502 effect(KILL cr);
8503
8504 ins_cost(125);
8505 format %{ "ADD $dst,$src" %}
8506 opcode(0x81); /* Opcode 81 /0 id */
8507 ins_encode( OpcSE( src ), RMopc_Mem(0x00,dst), Con8or32( src ) );
8508 ins_pipe( ialu_mem_imm );
8509 %}
8510
8511 instruct incI_mem(memory dst, immI1 src, eFlagsReg cr) %{
8512 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
8513 effect(KILL cr);
8514
8515 ins_cost(125);
8516 format %{ "INC $dst" %}
8517 opcode(0xFF); /* Opcode FF /0 */
8518 ins_encode( OpcP, RMopc_Mem(0x00,dst));
8519 ins_pipe( ialu_mem_imm );
8520 %}
8521
8522 instruct decI_mem(memory dst, immI_M1 src, eFlagsReg cr) %{
8523 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
8524 effect(KILL cr);
8525
8526 ins_cost(125);
8527 format %{ "DEC $dst" %}
8528 opcode(0xFF); /* Opcode FF /1 */
8529 ins_encode( OpcP, RMopc_Mem(0x01,dst));
8530 ins_pipe( ialu_mem_imm );
8531 %}
8532
8533
8534 instruct checkCastPP( eRegP dst ) %{
8535 match(Set dst (CheckCastPP dst));
8536
8537 size(0);
8538 format %{ "#checkcastPP of $dst" %}
8539 ins_encode( /*empty encoding*/ );
8540 ins_pipe( empty );
8541 %}
8542
8543 instruct castPP( eRegP dst ) %{
8544 match(Set dst (CastPP dst));
8545 format %{ "#castPP of $dst" %}
8546 ins_encode( /*empty encoding*/ );
8547 ins_pipe( empty );
8548 %}
8549
8550 instruct castII( eRegI dst ) %{
8551 match(Set dst (CastII dst));
8552 format %{ "#castII of $dst" %}
8553 ins_encode( /*empty encoding*/ );
8554 ins_cost(0);
8555 ins_pipe( empty );
8556 %}
8557
8558
8559 // Load-locked - same as a regular pointer load when used with compare-swap
8560 instruct loadPLocked(eRegP dst, memory mem) %{
8561 match(Set dst (LoadPLocked mem));
8562
8563 ins_cost(125);
8564 format %{ "MOV $dst,$mem\t# Load ptr. locked" %}
8565 opcode(0x8B);
8566 ins_encode( OpcP, RegMem(dst,mem));
8567 ins_pipe( ialu_reg_mem );
8568 %}
8569
8570 // LoadLong-locked - same as a volatile long load when used with compare-swap
8571 instruct loadLLocked(stackSlotL dst, load_long_memory mem) %{
8572 predicate(UseSSE<=1);
8573 match(Set dst (LoadLLocked mem));
8574
8575 ins_cost(200);
8576 format %{ "FILD $mem\t# Atomic volatile long load\n\t"
8577 "FISTp $dst" %}
8578 ins_encode(enc_loadL_volatile(mem,dst));
8579 ins_pipe( fpu_reg_mem );
8580 %}
8581
8582 instruct loadLX_Locked(stackSlotL dst, load_long_memory mem, regXD tmp) %{
8583 predicate(UseSSE>=2);
8584 match(Set dst (LoadLLocked mem));
8585 effect(TEMP tmp);
8586 ins_cost(180);
8587 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
8588 "MOVSD $dst,$tmp" %}
8589 ins_encode(enc_loadLX_volatile(mem, dst, tmp));
8590 ins_pipe( pipe_slow );
8591 %}
8592
8593 instruct loadLX_reg_Locked(eRegL dst, load_long_memory mem, regXD tmp) %{
8594 predicate(UseSSE>=2);
8595 match(Set dst (LoadLLocked mem));
8596 effect(TEMP tmp);
8597 ins_cost(160);
8598 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
8599 "MOVD $dst.lo,$tmp\n\t"
8600 "PSRLQ $tmp,32\n\t"
8601 "MOVD $dst.hi,$tmp" %}
8602 ins_encode(enc_loadLX_reg_volatile(mem, dst, tmp));
8603 ins_pipe( pipe_slow );
8604 %}
8605
8606 // Conditional-store of the updated heap-top.
8607 // Used during allocation of the shared heap.
8608 // Sets flags (EQ) on success. Implemented with a CMPXCHG on Intel.
8609 instruct storePConditional( memory heap_top_ptr, eAXRegP oldval, eRegP newval, eFlagsReg cr ) %{
8610 match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval)));
8611 // EAX is killed if there is contention, but then it's also unused.
8612 // In the common case of no contention, EAX holds the new oop address.
8613 format %{ "CMPXCHG $heap_top_ptr,$newval\t# If EAX==$heap_top_ptr Then store $newval into $heap_top_ptr" %}
8614 ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval,heap_top_ptr) );
8615 ins_pipe( pipe_cmpxchg );
8616 %}
8617
8618 // Conditional-store of an int value.
8619 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG on Intel.
8620 instruct storeIConditional( memory mem, eAXRegI oldval, eRegI newval, eFlagsReg cr ) %{
8621 match(Set cr (StoreIConditional mem (Binary oldval newval)));
8622 effect(KILL oldval);
8623 format %{ "CMPXCHG $mem,$newval\t# If EAX==$mem Then store $newval into $mem" %}
8624 ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval, mem) );
8625 ins_pipe( pipe_cmpxchg );
8626 %}
8627
8628 // Conditional-store of a long value.
8629 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG8 on Intel.
8630 instruct storeLConditional( memory mem, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{
8631 match(Set cr (StoreLConditional mem (Binary oldval newval)));
8632 effect(KILL oldval);
8633 format %{ "XCHG EBX,ECX\t# correct order for CMPXCHG8 instruction\n\t"
8634 "CMPXCHG8 $mem,ECX:EBX\t# If EDX:EAX==$mem Then store ECX:EBX into $mem\n\t"
8635 "XCHG EBX,ECX"
8636 %}
8637 ins_encode %{
8638 // Note: we need to swap rbx, and rcx before and after the
8639 // cmpxchg8 instruction because the instruction uses
8640 // rcx as the high order word of the new value to store but
8641 // our register encoding uses rbx.
8642 __ xchgl(as_Register(EBX_enc), as_Register(ECX_enc));
8643 if( os::is_MP() )
8644 __ lock();
8645 __ cmpxchg8($mem$$Address);
8646 __ xchgl(as_Register(EBX_enc), as_Register(ECX_enc));
8647 %}
8648 ins_pipe( pipe_cmpxchg );
8649 %}
8650
8651 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
8652
8653 instruct compareAndSwapL( eRegI res, eSIRegP mem_ptr, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{
8654 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
8655 effect(KILL cr, KILL oldval);
8656 format %{ "CMPXCHG8 [$mem_ptr],$newval\t# If EDX:EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
8657 "MOV $res,0\n\t"
8658 "JNE,s fail\n\t"
8659 "MOV $res,1\n"
8660 "fail:" %}
8661 ins_encode( enc_cmpxchg8(mem_ptr),
8662 enc_flags_ne_to_boolean(res) );
8663 ins_pipe( pipe_cmpxchg );
8664 %}
8665
8666 instruct compareAndSwapP( eRegI res, pRegP mem_ptr, eAXRegP oldval, eCXRegP newval, eFlagsReg cr) %{
8667 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
8668 effect(KILL cr, KILL oldval);
8669 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
8670 "MOV $res,0\n\t"
8671 "JNE,s fail\n\t"
8672 "MOV $res,1\n"
8673 "fail:" %}
8674 ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) );
8675 ins_pipe( pipe_cmpxchg );
8676 %}
8677
8678 instruct compareAndSwapI( eRegI res, pRegP mem_ptr, eAXRegI oldval, eCXRegI newval, eFlagsReg cr) %{
8679 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
8680 effect(KILL cr, KILL oldval);
8681 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
8682 "MOV $res,0\n\t"
8683 "JNE,s fail\n\t"
8684 "MOV $res,1\n"
8685 "fail:" %}
8686 ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) );
8687 ins_pipe( pipe_cmpxchg );
8688 %}
8689
8690 //----------Subtraction Instructions-------------------------------------------
8691 // Integer Subtraction Instructions
8692 instruct subI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
8693 match(Set dst (SubI dst src));
8694 effect(KILL cr);
8695
8696 size(2);
8697 format %{ "SUB $dst,$src" %}
8698 opcode(0x2B);
8699 ins_encode( OpcP, RegReg( dst, src) );
8700 ins_pipe( ialu_reg_reg );
8701 %}
8702
8703 instruct subI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{
8704 match(Set dst (SubI dst src));
8705 effect(KILL cr);
8706
8707 format %{ "SUB $dst,$src" %}
8708 opcode(0x81,0x05); /* Opcode 81 /5 */
8709 // ins_encode( RegImm( dst, src) );
8710 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8711 ins_pipe( ialu_reg );
8712 %}
8713
8714 instruct subI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{
8715 match(Set dst (SubI dst (LoadI src)));
8716 effect(KILL cr);
8717
8718 ins_cost(125);
8719 format %{ "SUB $dst,$src" %}
8720 opcode(0x2B);
8721 ins_encode( OpcP, RegMem( dst, src) );
8722 ins_pipe( ialu_reg_mem );
8723 %}
8724
8725 instruct subI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{
8726 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
8727 effect(KILL cr);
8728
8729 ins_cost(150);
8730 format %{ "SUB $dst,$src" %}
8731 opcode(0x29); /* Opcode 29 /r */
8732 ins_encode( OpcP, RegMem( src, dst ) );
8733 ins_pipe( ialu_mem_reg );
8734 %}
8735
8736 // Subtract from a pointer
8737 instruct subP_eReg(eRegP dst, eRegI src, immI0 zero, eFlagsReg cr) %{
8738 match(Set dst (AddP dst (SubI zero src)));
8739 effect(KILL cr);
8740
8741 size(2);
8742 format %{ "SUB $dst,$src" %}
8743 opcode(0x2B);
8744 ins_encode( OpcP, RegReg( dst, src) );
8745 ins_pipe( ialu_reg_reg );
8746 %}
8747
8748 instruct negI_eReg(eRegI dst, immI0 zero, eFlagsReg cr) %{
8749 match(Set dst (SubI zero dst));
8750 effect(KILL cr);
8751
8752 size(2);
8753 format %{ "NEG $dst" %}
8754 opcode(0xF7,0x03); // Opcode F7 /3
8755 ins_encode( OpcP, RegOpc( dst ) );
8756 ins_pipe( ialu_reg );
8757 %}
8758
8759
8760 //----------Multiplication/Division Instructions-------------------------------
8761 // Integer Multiplication Instructions
8762 // Multiply Register
8763 instruct mulI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
8764 match(Set dst (MulI dst src));
8765 effect(KILL cr);
8766
8767 size(3);
8768 ins_cost(300);
8769 format %{ "IMUL $dst,$src" %}
8770 opcode(0xAF, 0x0F);
8771 ins_encode( OpcS, OpcP, RegReg( dst, src) );
8772 ins_pipe( ialu_reg_reg_alu0 );
8773 %}
8774
8775 // Multiply 32-bit Immediate
8776 instruct mulI_eReg_imm(eRegI dst, eRegI src, immI imm, eFlagsReg cr) %{
8777 match(Set dst (MulI src imm));
8778 effect(KILL cr);
8779
8780 ins_cost(300);
8781 format %{ "IMUL $dst,$src,$imm" %}
8782 opcode(0x69); /* 69 /r id */
8783 ins_encode( OpcSE(imm), RegReg( dst, src ), Con8or32( imm ) );
8784 ins_pipe( ialu_reg_reg_alu0 );
8785 %}
8786
8787 instruct loadConL_low_only(eADXRegL_low_only dst, immL32 src, eFlagsReg cr) %{
8788 match(Set dst src);
8789 effect(KILL cr);
8790
8791 // Note that this is artificially increased to make it more expensive than loadConL
8792 ins_cost(250);
8793 format %{ "MOV EAX,$src\t// low word only" %}
8794 opcode(0xB8);
8795 ins_encode( LdImmL_Lo(dst, src) );
8796 ins_pipe( ialu_reg_fat );
8797 %}
8798
8799 // Multiply by 32-bit Immediate, taking the shifted high order results
8800 // (special case for shift by 32)
8801 instruct mulI_imm_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32 cnt, eFlagsReg cr) %{
8802 match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt)));
8803 predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL &&
8804 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint &&
8805 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint );
8806 effect(USE src1, KILL cr);
8807
8808 // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only
8809 ins_cost(0*100 + 1*400 - 150);
8810 format %{ "IMUL EDX:EAX,$src1" %}
8811 ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) );
8812 ins_pipe( pipe_slow );
8813 %}
8814
8815 // Multiply by 32-bit Immediate, taking the shifted high order results
8816 instruct mulI_imm_RShift_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr) %{
8817 match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt)));
8818 predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL &&
8819 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint &&
8820 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint );
8821 effect(USE src1, KILL cr);
8822
8823 // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only
8824 ins_cost(1*100 + 1*400 - 150);
8825 format %{ "IMUL EDX:EAX,$src1\n\t"
8826 "SAR EDX,$cnt-32" %}
8827 ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) );
8828 ins_pipe( pipe_slow );
8829 %}
8830
8831 // Multiply Memory 32-bit Immediate
8832 instruct mulI_mem_imm(eRegI dst, memory src, immI imm, eFlagsReg cr) %{
8833 match(Set dst (MulI (LoadI src) imm));
8834 effect(KILL cr);
8835
8836 ins_cost(300);
8837 format %{ "IMUL $dst,$src,$imm" %}
8838 opcode(0x69); /* 69 /r id */
8839 ins_encode( OpcSE(imm), RegMem( dst, src ), Con8or32( imm ) );
8840 ins_pipe( ialu_reg_mem_alu0 );
8841 %}
8842
8843 // Multiply Memory
8844 instruct mulI(eRegI dst, memory src, eFlagsReg cr) %{
8845 match(Set dst (MulI dst (LoadI src)));
8846 effect(KILL cr);
8847
8848 ins_cost(350);
8849 format %{ "IMUL $dst,$src" %}
8850 opcode(0xAF, 0x0F);
8851 ins_encode( OpcS, OpcP, RegMem( dst, src) );
8852 ins_pipe( ialu_reg_mem_alu0 );
8853 %}
8854
8855 // Multiply Register Int to Long
8856 instruct mulI2L(eADXRegL dst, eAXRegI src, nadxRegI src1, eFlagsReg flags) %{
8857 // Basic Idea: long = (long)int * (long)int
8858 match(Set dst (MulL (ConvI2L src) (ConvI2L src1)));
8859 effect(DEF dst, USE src, USE src1, KILL flags);
8860
8861 ins_cost(300);
8862 format %{ "IMUL $dst,$src1" %}
8863
8864 ins_encode( long_int_multiply( dst, src1 ) );
8865 ins_pipe( ialu_reg_reg_alu0 );
8866 %}
8867
8868 instruct mulIS_eReg(eADXRegL dst, immL_32bits mask, eFlagsReg flags, eAXRegI src, nadxRegI src1) %{
8869 // Basic Idea: long = (int & 0xffffffffL) * (int & 0xffffffffL)
8870 match(Set dst (MulL (AndL (ConvI2L src) mask) (AndL (ConvI2L src1) mask)));
8871 effect(KILL flags);
8872
8873 ins_cost(300);
8874 format %{ "MUL $dst,$src1" %}
8875
8876 ins_encode( long_uint_multiply(dst, src1) );
8877 ins_pipe( ialu_reg_reg_alu0 );
8878 %}
8879
8880 // Multiply Register Long
8881 instruct mulL_eReg(eADXRegL dst, eRegL src, eRegI tmp, eFlagsReg cr) %{
8882 match(Set dst (MulL dst src));
8883 effect(KILL cr, TEMP tmp);
8884 ins_cost(4*100+3*400);
8885 // Basic idea: lo(result) = lo(x_lo * y_lo)
8886 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
8887 format %{ "MOV $tmp,$src.lo\n\t"
8888 "IMUL $tmp,EDX\n\t"
8889 "MOV EDX,$src.hi\n\t"
8890 "IMUL EDX,EAX\n\t"
8891 "ADD $tmp,EDX\n\t"
8892 "MUL EDX:EAX,$src.lo\n\t"
8893 "ADD EDX,$tmp" %}
8894 ins_encode( long_multiply( dst, src, tmp ) );
8895 ins_pipe( pipe_slow );
8896 %}
8897
8898 // Multiply Register Long by small constant
8899 instruct mulL_eReg_con(eADXRegL dst, immL_127 src, eRegI tmp, eFlagsReg cr) %{
8900 match(Set dst (MulL dst src));
8901 effect(KILL cr, TEMP tmp);
8902 ins_cost(2*100+2*400);
8903 size(12);
8904 // Basic idea: lo(result) = lo(src * EAX)
8905 // hi(result) = hi(src * EAX) + lo(src * EDX)
8906 format %{ "IMUL $tmp,EDX,$src\n\t"
8907 "MOV EDX,$src\n\t"
8908 "MUL EDX\t# EDX*EAX -> EDX:EAX\n\t"
8909 "ADD EDX,$tmp" %}
8910 ins_encode( long_multiply_con( dst, src, tmp ) );
8911 ins_pipe( pipe_slow );
8912 %}
8913
8914 // Integer DIV with Register
8915 instruct divI_eReg(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{
8916 match(Set rax (DivI rax div));
8917 effect(KILL rdx, KILL cr);
8918 size(26);
8919 ins_cost(30*100+10*100);
8920 format %{ "CMP EAX,0x80000000\n\t"
8921 "JNE,s normal\n\t"
8922 "XOR EDX,EDX\n\t"
8923 "CMP ECX,-1\n\t"
8924 "JE,s done\n"
8925 "normal: CDQ\n\t"
8926 "IDIV $div\n\t"
8927 "done:" %}
8928 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8929 ins_encode( cdq_enc, OpcP, RegOpc(div) );
8930 ins_pipe( ialu_reg_reg_alu0 );
8931 %}
8932
8933 // Divide Register Long
8934 instruct divL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{
8935 match(Set dst (DivL src1 src2));
8936 effect( KILL cr, KILL cx, KILL bx );
8937 ins_cost(10000);
8938 format %{ "PUSH $src1.hi\n\t"
8939 "PUSH $src1.lo\n\t"
8940 "PUSH $src2.hi\n\t"
8941 "PUSH $src2.lo\n\t"
8942 "CALL SharedRuntime::ldiv\n\t"
8943 "ADD ESP,16" %}
8944 ins_encode( long_div(src1,src2) );
8945 ins_pipe( pipe_slow );
8946 %}
8947
8948 // Integer DIVMOD with Register, both quotient and mod results
8949 instruct divModI_eReg_divmod(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{
8950 match(DivModI rax div);
8951 effect(KILL cr);
8952 size(26);
8953 ins_cost(30*100+10*100);
8954 format %{ "CMP EAX,0x80000000\n\t"
8955 "JNE,s normal\n\t"
8956 "XOR EDX,EDX\n\t"
8957 "CMP ECX,-1\n\t"
8958 "JE,s done\n"
8959 "normal: CDQ\n\t"
8960 "IDIV $div\n\t"
8961 "done:" %}
8962 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8963 ins_encode( cdq_enc, OpcP, RegOpc(div) );
8964 ins_pipe( pipe_slow );
8965 %}
8966
8967 // Integer MOD with Register
8968 instruct modI_eReg(eDXRegI rdx, eAXRegI rax, eCXRegI div, eFlagsReg cr) %{
8969 match(Set rdx (ModI rax div));
8970 effect(KILL rax, KILL cr);
8971
8972 size(26);
8973 ins_cost(300);
8974 format %{ "CDQ\n\t"
8975 "IDIV $div" %}
8976 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8977 ins_encode( cdq_enc, OpcP, RegOpc(div) );
8978 ins_pipe( ialu_reg_reg_alu0 );
8979 %}
8980
8981 // Remainder Register Long
8982 instruct modL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{
8983 match(Set dst (ModL src1 src2));
8984 effect( KILL cr, KILL cx, KILL bx );
8985 ins_cost(10000);
8986 format %{ "PUSH $src1.hi\n\t"
8987 "PUSH $src1.lo\n\t"
8988 "PUSH $src2.hi\n\t"
8989 "PUSH $src2.lo\n\t"
8990 "CALL SharedRuntime::lrem\n\t"
8991 "ADD ESP,16" %}
8992 ins_encode( long_mod(src1,src2) );
8993 ins_pipe( pipe_slow );
8994 %}
8995
8996 // Integer Shift Instructions
8997 // Shift Left by one
8998 instruct shlI_eReg_1(eRegI dst, immI1 shift, eFlagsReg cr) %{
8999 match(Set dst (LShiftI dst shift));
9000 effect(KILL cr);
9001
9002 size(2);
9003 format %{ "SHL $dst,$shift" %}
9004 opcode(0xD1, 0x4); /* D1 /4 */
9005 ins_encode( OpcP, RegOpc( dst ) );
9006 ins_pipe( ialu_reg );
9007 %}
9008
9009 // Shift Left by 8-bit immediate
9010 instruct salI_eReg_imm(eRegI dst, immI8 shift, eFlagsReg cr) %{
9011 match(Set dst (LShiftI dst shift));
9012 effect(KILL cr);
9013
9014 size(3);
9015 format %{ "SHL $dst,$shift" %}
9016 opcode(0xC1, 0x4); /* C1 /4 ib */
9017 ins_encode( RegOpcImm( dst, shift) );
9018 ins_pipe( ialu_reg );
9019 %}
9020
9021 // Shift Left by variable
9022 instruct salI_eReg_CL(eRegI dst, eCXRegI shift, eFlagsReg cr) %{
9023 match(Set dst (LShiftI dst shift));
9024 effect(KILL cr);
9025
9026 size(2);
9027 format %{ "SHL $dst,$shift" %}
9028 opcode(0xD3, 0x4); /* D3 /4 */
9029 ins_encode( OpcP, RegOpc( dst ) );
9030 ins_pipe( ialu_reg_reg );
9031 %}
9032
9033 // Arithmetic shift right by one
9034 instruct sarI_eReg_1(eRegI dst, immI1 shift, eFlagsReg cr) %{
9035 match(Set dst (RShiftI dst shift));
9036 effect(KILL cr);
9037
9038 size(2);
9039 format %{ "SAR $dst,$shift" %}
9040 opcode(0xD1, 0x7); /* D1 /7 */
9041 ins_encode( OpcP, RegOpc( dst ) );
9042 ins_pipe( ialu_reg );
9043 %}
9044
9045 // Arithmetic shift right by one
9046 instruct sarI_mem_1(memory dst, immI1 shift, eFlagsReg cr) %{
9047 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
9048 effect(KILL cr);
9049 format %{ "SAR $dst,$shift" %}
9050 opcode(0xD1, 0x7); /* D1 /7 */
9051 ins_encode( OpcP, RMopc_Mem(secondary,dst) );
9052 ins_pipe( ialu_mem_imm );
9053 %}
9054
9055 // Arithmetic Shift Right by 8-bit immediate
9056 instruct sarI_eReg_imm(eRegI dst, immI8 shift, eFlagsReg cr) %{
9057 match(Set dst (RShiftI dst shift));
9058 effect(KILL cr);
9059
9060 size(3);
9061 format %{ "SAR $dst,$shift" %}
9062 opcode(0xC1, 0x7); /* C1 /7 ib */
9063 ins_encode( RegOpcImm( dst, shift ) );
9064 ins_pipe( ialu_mem_imm );
9065 %}
9066
9067 // Arithmetic Shift Right by 8-bit immediate
9068 instruct sarI_mem_imm(memory dst, immI8 shift, eFlagsReg cr) %{
9069 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
9070 effect(KILL cr);
9071
9072 format %{ "SAR $dst,$shift" %}
9073 opcode(0xC1, 0x7); /* C1 /7 ib */
9074 ins_encode( OpcP, RMopc_Mem(secondary, dst ), Con8or32( shift ) );
9075 ins_pipe( ialu_mem_imm );
9076 %}
9077
9078 // Arithmetic Shift Right by variable
9079 instruct sarI_eReg_CL(eRegI dst, eCXRegI shift, eFlagsReg cr) %{
9080 match(Set dst (RShiftI dst shift));
9081 effect(KILL cr);
9082
9083 size(2);
9084 format %{ "SAR $dst,$shift" %}
9085 opcode(0xD3, 0x7); /* D3 /7 */
9086 ins_encode( OpcP, RegOpc( dst ) );
9087 ins_pipe( ialu_reg_reg );
9088 %}
9089
9090 // Logical shift right by one
9091 instruct shrI_eReg_1(eRegI dst, immI1 shift, eFlagsReg cr) %{
9092 match(Set dst (URShiftI dst shift));
9093 effect(KILL cr);
9094
9095 size(2);
9096 format %{ "SHR $dst,$shift" %}
9097 opcode(0xD1, 0x5); /* D1 /5 */
9098 ins_encode( OpcP, RegOpc( dst ) );
9099 ins_pipe( ialu_reg );
9100 %}
9101
9102 // Logical Shift Right by 8-bit immediate
9103 instruct shrI_eReg_imm(eRegI dst, immI8 shift, eFlagsReg cr) %{
9104 match(Set dst (URShiftI dst shift));
9105 effect(KILL cr);
9106
9107 size(3);
9108 format %{ "SHR $dst,$shift" %}
9109 opcode(0xC1, 0x5); /* C1 /5 ib */
9110 ins_encode( RegOpcImm( dst, shift) );
9111 ins_pipe( ialu_reg );
9112 %}
9113
9114
9115 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24.
9116 // This idiom is used by the compiler for the i2b bytecode.
9117 instruct i2b(eRegI dst, xRegI src, immI_24 twentyfour) %{
9118 match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour));
9119
9120 size(3);
9121 format %{ "MOVSX $dst,$src :8" %}
9122 ins_encode %{
9123 __ movsbl($dst$$Register, $src$$Register);
9124 %}
9125 ins_pipe(ialu_reg_reg);
9126 %}
9127
9128 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16.
9129 // This idiom is used by the compiler the i2s bytecode.
9130 instruct i2s(eRegI dst, xRegI src, immI_16 sixteen) %{
9131 match(Set dst (RShiftI (LShiftI src sixteen) sixteen));
9132
9133 size(3);
9134 format %{ "MOVSX $dst,$src :16" %}
9135 ins_encode %{
9136 __ movswl($dst$$Register, $src$$Register);
9137 %}
9138 ins_pipe(ialu_reg_reg);
9139 %}
9140
9141
9142 // Logical Shift Right by variable
9143 instruct shrI_eReg_CL(eRegI dst, eCXRegI shift, eFlagsReg cr) %{
9144 match(Set dst (URShiftI dst shift));
9145 effect(KILL cr);
9146
9147 size(2);
9148 format %{ "SHR $dst,$shift" %}
9149 opcode(0xD3, 0x5); /* D3 /5 */
9150 ins_encode( OpcP, RegOpc( dst ) );
9151 ins_pipe( ialu_reg_reg );
9152 %}
9153
9154
9155 //----------Logical Instructions-----------------------------------------------
9156 //----------Integer Logical Instructions---------------------------------------
9157 // And Instructions
9158 // And Register with Register
9159 instruct andI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
9160 match(Set dst (AndI dst src));
9161 effect(KILL cr);
9162
9163 size(2);
9164 format %{ "AND $dst,$src" %}
9165 opcode(0x23);
9166 ins_encode( OpcP, RegReg( dst, src) );
9167 ins_pipe( ialu_reg_reg );
9168 %}
9169
9170 // And Register with Immediate
9171 instruct andI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{
9172 match(Set dst (AndI dst src));
9173 effect(KILL cr);
9174
9175 format %{ "AND $dst,$src" %}
9176 opcode(0x81,0x04); /* Opcode 81 /4 */
9177 // ins_encode( RegImm( dst, src) );
9178 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
9179 ins_pipe( ialu_reg );
9180 %}
9181
9182 // And Register with Memory
9183 instruct andI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{
9184 match(Set dst (AndI dst (LoadI src)));
9185 effect(KILL cr);
9186
9187 ins_cost(125);
9188 format %{ "AND $dst,$src" %}
9189 opcode(0x23);
9190 ins_encode( OpcP, RegMem( dst, src) );
9191 ins_pipe( ialu_reg_mem );
9192 %}
9193
9194 // And Memory with Register
9195 instruct andI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{
9196 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
9197 effect(KILL cr);
9198
9199 ins_cost(150);
9200 format %{ "AND $dst,$src" %}
9201 opcode(0x21); /* Opcode 21 /r */
9202 ins_encode( OpcP, RegMem( src, dst ) );
9203 ins_pipe( ialu_mem_reg );
9204 %}
9205
9206 // And Memory with Immediate
9207 instruct andI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
9208 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
9209 effect(KILL cr);
9210
9211 ins_cost(125);
9212 format %{ "AND $dst,$src" %}
9213 opcode(0x81, 0x4); /* Opcode 81 /4 id */
9214 // ins_encode( MemImm( dst, src) );
9215 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
9216 ins_pipe( ialu_mem_imm );
9217 %}
9218
9219 // Or Instructions
9220 // Or Register with Register
9221 instruct orI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
9222 match(Set dst (OrI dst src));
9223 effect(KILL cr);
9224
9225 size(2);
9226 format %{ "OR $dst,$src" %}
9227 opcode(0x0B);
9228 ins_encode( OpcP, RegReg( dst, src) );
9229 ins_pipe( ialu_reg_reg );
9230 %}
9231
9232 instruct orI_eReg_castP2X(eRegI dst, eRegP src, eFlagsReg cr) %{
9233 match(Set dst (OrI dst (CastP2X src)));
9234 effect(KILL cr);
9235
9236 size(2);
9237 format %{ "OR $dst,$src" %}
9238 opcode(0x0B);
9239 ins_encode( OpcP, RegReg( dst, src) );
9240 ins_pipe( ialu_reg_reg );
9241 %}
9242
9243
9244 // Or Register with Immediate
9245 instruct orI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{
9246 match(Set dst (OrI dst src));
9247 effect(KILL cr);
9248
9249 format %{ "OR $dst,$src" %}
9250 opcode(0x81,0x01); /* Opcode 81 /1 id */
9251 // ins_encode( RegImm( dst, src) );
9252 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
9253 ins_pipe( ialu_reg );
9254 %}
9255
9256 // Or Register with Memory
9257 instruct orI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{
9258 match(Set dst (OrI dst (LoadI src)));
9259 effect(KILL cr);
9260
9261 ins_cost(125);
9262 format %{ "OR $dst,$src" %}
9263 opcode(0x0B);
9264 ins_encode( OpcP, RegMem( dst, src) );
9265 ins_pipe( ialu_reg_mem );
9266 %}
9267
9268 // Or Memory with Register
9269 instruct orI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{
9270 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
9271 effect(KILL cr);
9272
9273 ins_cost(150);
9274 format %{ "OR $dst,$src" %}
9275 opcode(0x09); /* Opcode 09 /r */
9276 ins_encode( OpcP, RegMem( src, dst ) );
9277 ins_pipe( ialu_mem_reg );
9278 %}
9279
9280 // Or Memory with Immediate
9281 instruct orI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
9282 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
9283 effect(KILL cr);
9284
9285 ins_cost(125);
9286 format %{ "OR $dst,$src" %}
9287 opcode(0x81,0x1); /* Opcode 81 /1 id */
9288 // ins_encode( MemImm( dst, src) );
9289 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
9290 ins_pipe( ialu_mem_imm );
9291 %}
9292
9293 // ROL/ROR
9294 // ROL expand
9295 instruct rolI_eReg_imm1(eRegI dst, immI1 shift, eFlagsReg cr) %{
9296 effect(USE_DEF dst, USE shift, KILL cr);
9297
9298 format %{ "ROL $dst, $shift" %}
9299 opcode(0xD1, 0x0); /* Opcode D1 /0 */
9300 ins_encode( OpcP, RegOpc( dst ));
9301 ins_pipe( ialu_reg );
9302 %}
9303
9304 instruct rolI_eReg_imm8(eRegI dst, immI8 shift, eFlagsReg cr) %{
9305 effect(USE_DEF dst, USE shift, KILL cr);
9306
9307 format %{ "ROL $dst, $shift" %}
9308 opcode(0xC1, 0x0); /*Opcode /C1 /0 */
9309 ins_encode( RegOpcImm(dst, shift) );
9310 ins_pipe(ialu_reg);
9311 %}
9312
9313 instruct rolI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr) %{
9314 effect(USE_DEF dst, USE shift, KILL cr);
9315
9316 format %{ "ROL $dst, $shift" %}
9317 opcode(0xD3, 0x0); /* Opcode D3 /0 */
9318 ins_encode(OpcP, RegOpc(dst));
9319 ins_pipe( ialu_reg_reg );
9320 %}
9321 // end of ROL expand
9322
9323 // ROL 32bit by one once
9324 instruct rolI_eReg_i1(eRegI dst, immI1 lshift, immI_M1 rshift, eFlagsReg cr) %{
9325 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift)));
9326
9327 expand %{
9328 rolI_eReg_imm1(dst, lshift, cr);
9329 %}
9330 %}
9331
9332 // ROL 32bit var by imm8 once
9333 instruct rolI_eReg_i8(eRegI dst, immI8 lshift, immI8 rshift, eFlagsReg cr) %{
9334 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
9335 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift)));
9336
9337 expand %{
9338 rolI_eReg_imm8(dst, lshift, cr);
9339 %}
9340 %}
9341
9342 // ROL 32bit var by var once
9343 instruct rolI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{
9344 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI zero shift))));
9345
9346 expand %{
9347 rolI_eReg_CL(dst, shift, cr);
9348 %}
9349 %}
9350
9351 // ROL 32bit var by var once
9352 instruct rolI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{
9353 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI c32 shift))));
9354
9355 expand %{
9356 rolI_eReg_CL(dst, shift, cr);
9357 %}
9358 %}
9359
9360 // ROR expand
9361 instruct rorI_eReg_imm1(eRegI dst, immI1 shift, eFlagsReg cr) %{
9362 effect(USE_DEF dst, USE shift, KILL cr);
9363
9364 format %{ "ROR $dst, $shift" %}
9365 opcode(0xD1,0x1); /* Opcode D1 /1 */
9366 ins_encode( OpcP, RegOpc( dst ) );
9367 ins_pipe( ialu_reg );
9368 %}
9369
9370 instruct rorI_eReg_imm8(eRegI dst, immI8 shift, eFlagsReg cr) %{
9371 effect (USE_DEF dst, USE shift, KILL cr);
9372
9373 format %{ "ROR $dst, $shift" %}
9374 opcode(0xC1, 0x1); /* Opcode /C1 /1 ib */
9375 ins_encode( RegOpcImm(dst, shift) );
9376 ins_pipe( ialu_reg );
9377 %}
9378
9379 instruct rorI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr)%{
9380 effect(USE_DEF dst, USE shift, KILL cr);
9381
9382 format %{ "ROR $dst, $shift" %}
9383 opcode(0xD3, 0x1); /* Opcode D3 /1 */
9384 ins_encode(OpcP, RegOpc(dst));
9385 ins_pipe( ialu_reg_reg );
9386 %}
9387 // end of ROR expand
9388
9389 // ROR right once
9390 instruct rorI_eReg_i1(eRegI dst, immI1 rshift, immI_M1 lshift, eFlagsReg cr) %{
9391 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift)));
9392
9393 expand %{
9394 rorI_eReg_imm1(dst, rshift, cr);
9395 %}
9396 %}
9397
9398 // ROR 32bit by immI8 once
9399 instruct rorI_eReg_i8(eRegI dst, immI8 rshift, immI8 lshift, eFlagsReg cr) %{
9400 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
9401 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift)));
9402
9403 expand %{
9404 rorI_eReg_imm8(dst, rshift, cr);
9405 %}
9406 %}
9407
9408 // ROR 32bit var by var once
9409 instruct rorI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{
9410 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI zero shift))));
9411
9412 expand %{
9413 rorI_eReg_CL(dst, shift, cr);
9414 %}
9415 %}
9416
9417 // ROR 32bit var by var once
9418 instruct rorI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{
9419 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI c32 shift))));
9420
9421 expand %{
9422 rorI_eReg_CL(dst, shift, cr);
9423 %}
9424 %}
9425
9426 // Xor Instructions
9427 // Xor Register with Register
9428 instruct xorI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
9429 match(Set dst (XorI dst src));
9430 effect(KILL cr);
9431
9432 size(2);
9433 format %{ "XOR $dst,$src" %}
9434 opcode(0x33);
9435 ins_encode( OpcP, RegReg( dst, src) );
9436 ins_pipe( ialu_reg_reg );
9437 %}
9438
9439 // Xor Register with Immediate -1
9440 instruct xorI_eReg_im1(eRegI dst, immI_M1 imm) %{
9441 match(Set dst (XorI dst imm));
9442
9443 size(2);
9444 format %{ "NOT $dst" %}
9445 ins_encode %{
9446 __ notl($dst$$Register);
9447 %}
9448 ins_pipe( ialu_reg );
9449 %}
9450
9451 // Xor Register with Immediate
9452 instruct xorI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{
9453 match(Set dst (XorI dst src));
9454 effect(KILL cr);
9455
9456 format %{ "XOR $dst,$src" %}
9457 opcode(0x81,0x06); /* Opcode 81 /6 id */
9458 // ins_encode( RegImm( dst, src) );
9459 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
9460 ins_pipe( ialu_reg );
9461 %}
9462
9463 // Xor Register with Memory
9464 instruct xorI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{
9465 match(Set dst (XorI dst (LoadI src)));
9466 effect(KILL cr);
9467
9468 ins_cost(125);
9469 format %{ "XOR $dst,$src" %}
9470 opcode(0x33);
9471 ins_encode( OpcP, RegMem(dst, src) );
9472 ins_pipe( ialu_reg_mem );
9473 %}
9474
9475 // Xor Memory with Register
9476 instruct xorI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{
9477 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
9478 effect(KILL cr);
9479
9480 ins_cost(150);
9481 format %{ "XOR $dst,$src" %}
9482 opcode(0x31); /* Opcode 31 /r */
9483 ins_encode( OpcP, RegMem( src, dst ) );
9484 ins_pipe( ialu_mem_reg );
9485 %}
9486
9487 // Xor Memory with Immediate
9488 instruct xorI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
9489 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
9490 effect(KILL cr);
9491
9492 ins_cost(125);
9493 format %{ "XOR $dst,$src" %}
9494 opcode(0x81,0x6); /* Opcode 81 /6 id */
9495 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
9496 ins_pipe( ialu_mem_imm );
9497 %}
9498
9499 //----------Convert Int to Boolean---------------------------------------------
9500
9501 instruct movI_nocopy(eRegI dst, eRegI src) %{
9502 effect( DEF dst, USE src );
9503 format %{ "MOV $dst,$src" %}
9504 ins_encode( enc_Copy( dst, src) );
9505 ins_pipe( ialu_reg_reg );
9506 %}
9507
9508 instruct ci2b( eRegI dst, eRegI src, eFlagsReg cr ) %{
9509 effect( USE_DEF dst, USE src, KILL cr );
9510
9511 size(4);
9512 format %{ "NEG $dst\n\t"
9513 "ADC $dst,$src" %}
9514 ins_encode( neg_reg(dst),
9515 OpcRegReg(0x13,dst,src) );
9516 ins_pipe( ialu_reg_reg_long );
9517 %}
9518
9519 instruct convI2B( eRegI dst, eRegI src, eFlagsReg cr ) %{
9520 match(Set dst (Conv2B src));
9521
9522 expand %{
9523 movI_nocopy(dst,src);
9524 ci2b(dst,src,cr);
9525 %}
9526 %}
9527
9528 instruct movP_nocopy(eRegI dst, eRegP src) %{
9529 effect( DEF dst, USE src );
9530 format %{ "MOV $dst,$src" %}
9531 ins_encode( enc_Copy( dst, src) );
9532 ins_pipe( ialu_reg_reg );
9533 %}
9534
9535 instruct cp2b( eRegI dst, eRegP src, eFlagsReg cr ) %{
9536 effect( USE_DEF dst, USE src, KILL cr );
9537 format %{ "NEG $dst\n\t"
9538 "ADC $dst,$src" %}
9539 ins_encode( neg_reg(dst),
9540 OpcRegReg(0x13,dst,src) );
9541 ins_pipe( ialu_reg_reg_long );
9542 %}
9543
9544 instruct convP2B( eRegI dst, eRegP src, eFlagsReg cr ) %{
9545 match(Set dst (Conv2B src));
9546
9547 expand %{
9548 movP_nocopy(dst,src);
9549 cp2b(dst,src,cr);
9550 %}
9551 %}
9552
9553 instruct cmpLTMask( eCXRegI dst, ncxRegI p, ncxRegI q, eFlagsReg cr ) %{
9554 match(Set dst (CmpLTMask p q));
9555 effect( KILL cr );
9556 ins_cost(400);
9557
9558 // SETlt can only use low byte of EAX,EBX, ECX, or EDX as destination
9559 format %{ "XOR $dst,$dst\n\t"
9560 "CMP $p,$q\n\t"
9561 "SETlt $dst\n\t"
9562 "NEG $dst" %}
9563 ins_encode( OpcRegReg(0x33,dst,dst),
9564 OpcRegReg(0x3B,p,q),
9565 setLT_reg(dst), neg_reg(dst) );
9566 ins_pipe( pipe_slow );
9567 %}
9568
9569 instruct cmpLTMask0( eRegI dst, immI0 zero, eFlagsReg cr ) %{
9570 match(Set dst (CmpLTMask dst zero));
9571 effect( DEF dst, KILL cr );
9572 ins_cost(100);
9573
9574 format %{ "SAR $dst,31" %}
9575 opcode(0xC1, 0x7); /* C1 /7 ib */
9576 ins_encode( RegOpcImm( dst, 0x1F ) );
9577 ins_pipe( ialu_reg );
9578 %}
9579
9580
9581 instruct cadd_cmpLTMask( ncxRegI p, ncxRegI q, ncxRegI y, eCXRegI tmp, eFlagsReg cr ) %{
9582 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
9583 effect( KILL tmp, KILL cr );
9584 ins_cost(400);
9585 // annoyingly, $tmp has no edges so you cant ask for it in
9586 // any format or encoding
9587 format %{ "SUB $p,$q\n\t"
9588 "SBB ECX,ECX\n\t"
9589 "AND ECX,$y\n\t"
9590 "ADD $p,ECX" %}
9591 ins_encode( enc_cmpLTP(p,q,y,tmp) );
9592 ins_pipe( pipe_cmplt );
9593 %}
9594
9595 /* If I enable this, I encourage spilling in the inner loop of compress.
9596 instruct cadd_cmpLTMask_mem( ncxRegI p, ncxRegI q, memory y, eCXRegI tmp, eFlagsReg cr ) %{
9597 match(Set p (AddI (AndI (CmpLTMask p q) (LoadI y)) (SubI p q)));
9598 effect( USE_KILL tmp, KILL cr );
9599 ins_cost(400);
9600
9601 format %{ "SUB $p,$q\n\t"
9602 "SBB ECX,ECX\n\t"
9603 "AND ECX,$y\n\t"
9604 "ADD $p,ECX" %}
9605 ins_encode( enc_cmpLTP_mem(p,q,y,tmp) );
9606 %}
9607 */
9608
9609 //----------Long Instructions------------------------------------------------
9610 // Add Long Register with Register
9611 instruct addL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9612 match(Set dst (AddL dst src));
9613 effect(KILL cr);
9614 ins_cost(200);
9615 format %{ "ADD $dst.lo,$src.lo\n\t"
9616 "ADC $dst.hi,$src.hi" %}
9617 opcode(0x03, 0x13);
9618 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) );
9619 ins_pipe( ialu_reg_reg_long );
9620 %}
9621
9622 // Add Long Register with Immediate
9623 instruct addL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9624 match(Set dst (AddL dst src));
9625 effect(KILL cr);
9626 format %{ "ADD $dst.lo,$src.lo\n\t"
9627 "ADC $dst.hi,$src.hi" %}
9628 opcode(0x81,0x00,0x02); /* Opcode 81 /0, 81 /2 */
9629 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9630 ins_pipe( ialu_reg_long );
9631 %}
9632
9633 // Add Long Register with Memory
9634 instruct addL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9635 match(Set dst (AddL dst (LoadL mem)));
9636 effect(KILL cr);
9637 ins_cost(125);
9638 format %{ "ADD $dst.lo,$mem\n\t"
9639 "ADC $dst.hi,$mem+4" %}
9640 opcode(0x03, 0x13);
9641 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9642 ins_pipe( ialu_reg_long_mem );
9643 %}
9644
9645 // Subtract Long Register with Register.
9646 instruct subL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9647 match(Set dst (SubL dst src));
9648 effect(KILL cr);
9649 ins_cost(200);
9650 format %{ "SUB $dst.lo,$src.lo\n\t"
9651 "SBB $dst.hi,$src.hi" %}
9652 opcode(0x2B, 0x1B);
9653 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) );
9654 ins_pipe( ialu_reg_reg_long );
9655 %}
9656
9657 // Subtract Long Register with Immediate
9658 instruct subL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9659 match(Set dst (SubL dst src));
9660 effect(KILL cr);
9661 format %{ "SUB $dst.lo,$src.lo\n\t"
9662 "SBB $dst.hi,$src.hi" %}
9663 opcode(0x81,0x05,0x03); /* Opcode 81 /5, 81 /3 */
9664 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9665 ins_pipe( ialu_reg_long );
9666 %}
9667
9668 // Subtract Long Register with Memory
9669 instruct subL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9670 match(Set dst (SubL dst (LoadL mem)));
9671 effect(KILL cr);
9672 ins_cost(125);
9673 format %{ "SUB $dst.lo,$mem\n\t"
9674 "SBB $dst.hi,$mem+4" %}
9675 opcode(0x2B, 0x1B);
9676 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9677 ins_pipe( ialu_reg_long_mem );
9678 %}
9679
9680 instruct negL_eReg(eRegL dst, immL0 zero, eFlagsReg cr) %{
9681 match(Set dst (SubL zero dst));
9682 effect(KILL cr);
9683 ins_cost(300);
9684 format %{ "NEG $dst.hi\n\tNEG $dst.lo\n\tSBB $dst.hi,0" %}
9685 ins_encode( neg_long(dst) );
9686 ins_pipe( ialu_reg_reg_long );
9687 %}
9688
9689 // And Long Register with Register
9690 instruct andL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9691 match(Set dst (AndL dst src));
9692 effect(KILL cr);
9693 format %{ "AND $dst.lo,$src.lo\n\t"
9694 "AND $dst.hi,$src.hi" %}
9695 opcode(0x23,0x23);
9696 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
9697 ins_pipe( ialu_reg_reg_long );
9698 %}
9699
9700 // And Long Register with Immediate
9701 instruct andL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9702 match(Set dst (AndL dst src));
9703 effect(KILL cr);
9704 format %{ "AND $dst.lo,$src.lo\n\t"
9705 "AND $dst.hi,$src.hi" %}
9706 opcode(0x81,0x04,0x04); /* Opcode 81 /4, 81 /4 */
9707 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9708 ins_pipe( ialu_reg_long );
9709 %}
9710
9711 // And Long Register with Memory
9712 instruct andL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9713 match(Set dst (AndL dst (LoadL mem)));
9714 effect(KILL cr);
9715 ins_cost(125);
9716 format %{ "AND $dst.lo,$mem\n\t"
9717 "AND $dst.hi,$mem+4" %}
9718 opcode(0x23, 0x23);
9719 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9720 ins_pipe( ialu_reg_long_mem );
9721 %}
9722
9723 // Or Long Register with Register
9724 instruct orl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9725 match(Set dst (OrL dst src));
9726 effect(KILL cr);
9727 format %{ "OR $dst.lo,$src.lo\n\t"
9728 "OR $dst.hi,$src.hi" %}
9729 opcode(0x0B,0x0B);
9730 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
9731 ins_pipe( ialu_reg_reg_long );
9732 %}
9733
9734 // Or Long Register with Immediate
9735 instruct orl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9736 match(Set dst (OrL dst src));
9737 effect(KILL cr);
9738 format %{ "OR $dst.lo,$src.lo\n\t"
9739 "OR $dst.hi,$src.hi" %}
9740 opcode(0x81,0x01,0x01); /* Opcode 81 /1, 81 /1 */
9741 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9742 ins_pipe( ialu_reg_long );
9743 %}
9744
9745 // Or Long Register with Memory
9746 instruct orl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9747 match(Set dst (OrL dst (LoadL mem)));
9748 effect(KILL cr);
9749 ins_cost(125);
9750 format %{ "OR $dst.lo,$mem\n\t"
9751 "OR $dst.hi,$mem+4" %}
9752 opcode(0x0B,0x0B);
9753 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9754 ins_pipe( ialu_reg_long_mem );
9755 %}
9756
9757 // Xor Long Register with Register
9758 instruct xorl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9759 match(Set dst (XorL dst src));
9760 effect(KILL cr);
9761 format %{ "XOR $dst.lo,$src.lo\n\t"
9762 "XOR $dst.hi,$src.hi" %}
9763 opcode(0x33,0x33);
9764 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
9765 ins_pipe( ialu_reg_reg_long );
9766 %}
9767
9768 // Xor Long Register with Immediate -1
9769 instruct xorl_eReg_im1(eRegL dst, immL_M1 imm) %{
9770 match(Set dst (XorL dst imm));
9771 format %{ "NOT $dst.lo\n\t"
9772 "NOT $dst.hi" %}
9773 ins_encode %{
9774 __ notl($dst$$Register);
9775 __ notl(HIGH_FROM_LOW($dst$$Register));
9776 %}
9777 ins_pipe( ialu_reg_long );
9778 %}
9779
9780 // Xor Long Register with Immediate
9781 instruct xorl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9782 match(Set dst (XorL dst src));
9783 effect(KILL cr);
9784 format %{ "XOR $dst.lo,$src.lo\n\t"
9785 "XOR $dst.hi,$src.hi" %}
9786 opcode(0x81,0x06,0x06); /* Opcode 81 /6, 81 /6 */
9787 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9788 ins_pipe( ialu_reg_long );
9789 %}
9790
9791 // Xor Long Register with Memory
9792 instruct xorl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9793 match(Set dst (XorL dst (LoadL mem)));
9794 effect(KILL cr);
9795 ins_cost(125);
9796 format %{ "XOR $dst.lo,$mem\n\t"
9797 "XOR $dst.hi,$mem+4" %}
9798 opcode(0x33,0x33);
9799 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9800 ins_pipe( ialu_reg_long_mem );
9801 %}
9802
9803 // Shift Left Long by 1
9804 instruct shlL_eReg_1(eRegL dst, immI_1 cnt, eFlagsReg cr) %{
9805 predicate(UseNewLongLShift);
9806 match(Set dst (LShiftL dst cnt));
9807 effect(KILL cr);
9808 ins_cost(100);
9809 format %{ "ADD $dst.lo,$dst.lo\n\t"
9810 "ADC $dst.hi,$dst.hi" %}
9811 ins_encode %{
9812 __ addl($dst$$Register,$dst$$Register);
9813 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9814 %}
9815 ins_pipe( ialu_reg_long );
9816 %}
9817
9818 // Shift Left Long by 2
9819 instruct shlL_eReg_2(eRegL dst, immI_2 cnt, eFlagsReg cr) %{
9820 predicate(UseNewLongLShift);
9821 match(Set dst (LShiftL dst cnt));
9822 effect(KILL cr);
9823 ins_cost(100);
9824 format %{ "ADD $dst.lo,$dst.lo\n\t"
9825 "ADC $dst.hi,$dst.hi\n\t"
9826 "ADD $dst.lo,$dst.lo\n\t"
9827 "ADC $dst.hi,$dst.hi" %}
9828 ins_encode %{
9829 __ addl($dst$$Register,$dst$$Register);
9830 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9831 __ addl($dst$$Register,$dst$$Register);
9832 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9833 %}
9834 ins_pipe( ialu_reg_long );
9835 %}
9836
9837 // Shift Left Long by 3
9838 instruct shlL_eReg_3(eRegL dst, immI_3 cnt, eFlagsReg cr) %{
9839 predicate(UseNewLongLShift);
9840 match(Set dst (LShiftL dst cnt));
9841 effect(KILL cr);
9842 ins_cost(100);
9843 format %{ "ADD $dst.lo,$dst.lo\n\t"
9844 "ADC $dst.hi,$dst.hi\n\t"
9845 "ADD $dst.lo,$dst.lo\n\t"
9846 "ADC $dst.hi,$dst.hi\n\t"
9847 "ADD $dst.lo,$dst.lo\n\t"
9848 "ADC $dst.hi,$dst.hi" %}
9849 ins_encode %{
9850 __ addl($dst$$Register,$dst$$Register);
9851 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9852 __ addl($dst$$Register,$dst$$Register);
9853 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9854 __ addl($dst$$Register,$dst$$Register);
9855 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9856 %}
9857 ins_pipe( ialu_reg_long );
9858 %}
9859
9860 // Shift Left Long by 1-31
9861 instruct shlL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9862 match(Set dst (LShiftL dst cnt));
9863 effect(KILL cr);
9864 ins_cost(200);
9865 format %{ "SHLD $dst.hi,$dst.lo,$cnt\n\t"
9866 "SHL $dst.lo,$cnt" %}
9867 opcode(0xC1, 0x4, 0xA4); /* 0F/A4, then C1 /4 ib */
9868 ins_encode( move_long_small_shift(dst,cnt) );
9869 ins_pipe( ialu_reg_long );
9870 %}
9871
9872 // Shift Left Long by 32-63
9873 instruct shlL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9874 match(Set dst (LShiftL dst cnt));
9875 effect(KILL cr);
9876 ins_cost(300);
9877 format %{ "MOV $dst.hi,$dst.lo\n"
9878 "\tSHL $dst.hi,$cnt-32\n"
9879 "\tXOR $dst.lo,$dst.lo" %}
9880 opcode(0xC1, 0x4); /* C1 /4 ib */
9881 ins_encode( move_long_big_shift_clr(dst,cnt) );
9882 ins_pipe( ialu_reg_long );
9883 %}
9884
9885 // Shift Left Long by variable
9886 instruct salL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9887 match(Set dst (LShiftL dst shift));
9888 effect(KILL cr);
9889 ins_cost(500+200);
9890 size(17);
9891 format %{ "TEST $shift,32\n\t"
9892 "JEQ,s small\n\t"
9893 "MOV $dst.hi,$dst.lo\n\t"
9894 "XOR $dst.lo,$dst.lo\n"
9895 "small:\tSHLD $dst.hi,$dst.lo,$shift\n\t"
9896 "SHL $dst.lo,$shift" %}
9897 ins_encode( shift_left_long( dst, shift ) );
9898 ins_pipe( pipe_slow );
9899 %}
9900
9901 // Shift Right Long by 1-31
9902 instruct shrL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9903 match(Set dst (URShiftL dst cnt));
9904 effect(KILL cr);
9905 ins_cost(200);
9906 format %{ "SHRD $dst.lo,$dst.hi,$cnt\n\t"
9907 "SHR $dst.hi,$cnt" %}
9908 opcode(0xC1, 0x5, 0xAC); /* 0F/AC, then C1 /5 ib */
9909 ins_encode( move_long_small_shift(dst,cnt) );
9910 ins_pipe( ialu_reg_long );
9911 %}
9912
9913 // Shift Right Long by 32-63
9914 instruct shrL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9915 match(Set dst (URShiftL dst cnt));
9916 effect(KILL cr);
9917 ins_cost(300);
9918 format %{ "MOV $dst.lo,$dst.hi\n"
9919 "\tSHR $dst.lo,$cnt-32\n"
9920 "\tXOR $dst.hi,$dst.hi" %}
9921 opcode(0xC1, 0x5); /* C1 /5 ib */
9922 ins_encode( move_long_big_shift_clr(dst,cnt) );
9923 ins_pipe( ialu_reg_long );
9924 %}
9925
9926 // Shift Right Long by variable
9927 instruct shrL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9928 match(Set dst (URShiftL dst shift));
9929 effect(KILL cr);
9930 ins_cost(600);
9931 size(17);
9932 format %{ "TEST $shift,32\n\t"
9933 "JEQ,s small\n\t"
9934 "MOV $dst.lo,$dst.hi\n\t"
9935 "XOR $dst.hi,$dst.hi\n"
9936 "small:\tSHRD $dst.lo,$dst.hi,$shift\n\t"
9937 "SHR $dst.hi,$shift" %}
9938 ins_encode( shift_right_long( dst, shift ) );
9939 ins_pipe( pipe_slow );
9940 %}
9941
9942 // Shift Right Long by 1-31
9943 instruct sarL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9944 match(Set dst (RShiftL dst cnt));
9945 effect(KILL cr);
9946 ins_cost(200);
9947 format %{ "SHRD $dst.lo,$dst.hi,$cnt\n\t"
9948 "SAR $dst.hi,$cnt" %}
9949 opcode(0xC1, 0x7, 0xAC); /* 0F/AC, then C1 /7 ib */
9950 ins_encode( move_long_small_shift(dst,cnt) );
9951 ins_pipe( ialu_reg_long );
9952 %}
9953
9954 // Shift Right Long by 32-63
9955 instruct sarL_eReg_32_63( eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9956 match(Set dst (RShiftL dst cnt));
9957 effect(KILL cr);
9958 ins_cost(300);
9959 format %{ "MOV $dst.lo,$dst.hi\n"
9960 "\tSAR $dst.lo,$cnt-32\n"
9961 "\tSAR $dst.hi,31" %}
9962 opcode(0xC1, 0x7); /* C1 /7 ib */
9963 ins_encode( move_long_big_shift_sign(dst,cnt) );
9964 ins_pipe( ialu_reg_long );
9965 %}
9966
9967 // Shift Right arithmetic Long by variable
9968 instruct sarL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9969 match(Set dst (RShiftL dst shift));
9970 effect(KILL cr);
9971 ins_cost(600);
9972 size(18);
9973 format %{ "TEST $shift,32\n\t"
9974 "JEQ,s small\n\t"
9975 "MOV $dst.lo,$dst.hi\n\t"
9976 "SAR $dst.hi,31\n"
9977 "small:\tSHRD $dst.lo,$dst.hi,$shift\n\t"
9978 "SAR $dst.hi,$shift" %}
9979 ins_encode( shift_right_arith_long( dst, shift ) );
9980 ins_pipe( pipe_slow );
9981 %}
9982
9983
9984 //----------Double Instructions------------------------------------------------
9985 // Double Math
9986
9987 // Compare & branch
9988
9989 // P6 version of float compare, sets condition codes in EFLAGS
9990 instruct cmpD_cc_P6(eFlagsRegU cr, regD src1, regD src2, eAXRegI rax) %{
9991 predicate(VM_Version::supports_cmov() && UseSSE <=1);
9992 match(Set cr (CmpD src1 src2));
9993 effect(KILL rax);
9994 ins_cost(150);
9995 format %{ "FLD $src1\n\t"
9996 "FUCOMIP ST,$src2 // P6 instruction\n\t"
9997 "JNP exit\n\t"
9998 "MOV ah,1 // saw a NaN, set CF\n\t"
9999 "SAHF\n"
10000 "exit:\tNOP // avoid branch to branch" %}
10001 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
10002 ins_encode( Push_Reg_D(src1),
10003 OpcP, RegOpc(src2),
10004 cmpF_P6_fixup );
10005 ins_pipe( pipe_slow );
10006 %}
10007
10008 instruct cmpD_cc_P6CF(eFlagsRegUCF cr, regD src1, regD src2) %{
10009 predicate(VM_Version::supports_cmov() && UseSSE <=1);
10010 match(Set cr (CmpD src1 src2));
10011 ins_cost(150);
10012 format %{ "FLD $src1\n\t"
10013 "FUCOMIP ST,$src2 // P6 instruction" %}
10014 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
10015 ins_encode( Push_Reg_D(src1),
10016 OpcP, RegOpc(src2));
10017 ins_pipe( pipe_slow );
10018 %}
10019
10020 // Compare & branch
10021 instruct cmpD_cc(eFlagsRegU cr, regD src1, regD src2, eAXRegI rax) %{
10022 predicate(UseSSE<=1);
10023 match(Set cr (CmpD src1 src2));
10024 effect(KILL rax);
10025 ins_cost(200);
10026 format %{ "FLD $src1\n\t"
10027 "FCOMp $src2\n\t"
10028 "FNSTSW AX\n\t"
10029 "TEST AX,0x400\n\t"
10030 "JZ,s flags\n\t"
10031 "MOV AH,1\t# unordered treat as LT\n"
10032 "flags:\tSAHF" %}
10033 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
10034 ins_encode( Push_Reg_D(src1),
10035 OpcP, RegOpc(src2),
10036 fpu_flags);
10037 ins_pipe( pipe_slow );
10038 %}
10039
10040 // Compare vs zero into -1,0,1
10041 instruct cmpD_0(eRegI dst, regD src1, immD0 zero, eAXRegI rax, eFlagsReg cr) %{
10042 predicate(UseSSE<=1);
10043 match(Set dst (CmpD3 src1 zero));
10044 effect(KILL cr, KILL rax);
10045 ins_cost(280);
10046 format %{ "FTSTD $dst,$src1" %}
10047 opcode(0xE4, 0xD9);
10048 ins_encode( Push_Reg_D(src1),
10049 OpcS, OpcP, PopFPU,
10050 CmpF_Result(dst));
10051 ins_pipe( pipe_slow );
10052 %}
10053
10054 // Compare into -1,0,1
10055 instruct cmpD_reg(eRegI dst, regD src1, regD src2, eAXRegI rax, eFlagsReg cr) %{
10056 predicate(UseSSE<=1);
10057 match(Set dst (CmpD3 src1 src2));
10058 effect(KILL cr, KILL rax);
10059 ins_cost(300);
10060 format %{ "FCMPD $dst,$src1,$src2" %}
10061 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
10062 ins_encode( Push_Reg_D(src1),
10063 OpcP, RegOpc(src2),
10064 CmpF_Result(dst));
10065 ins_pipe( pipe_slow );
10066 %}
10067
10068 // float compare and set condition codes in EFLAGS by XMM regs
10069 instruct cmpXD_cc(eFlagsRegU cr, regXD dst, regXD src, eAXRegI rax) %{
10070 predicate(UseSSE>=2);
10071 match(Set cr (CmpD dst src));
10072 effect(KILL rax);
10073 ins_cost(125);
10074 format %{ "COMISD $dst,$src\n"
10075 "\tJNP exit\n"
10076 "\tMOV ah,1 // saw a NaN, set CF\n"
10077 "\tSAHF\n"
10078 "exit:\tNOP // avoid branch to branch" %}
10079 opcode(0x66, 0x0F, 0x2F);
10080 ins_encode(OpcP, OpcS, Opcode(tertiary), RegReg(dst, src), cmpF_P6_fixup);
10081 ins_pipe( pipe_slow );
10082 %}
10083
10084 instruct cmpXD_ccCF(eFlagsRegUCF cr, regXD dst, regXD src) %{
10085 predicate(UseSSE>=2);
10086 match(Set cr (CmpD dst src));
10087 ins_cost(100);
10088 format %{ "COMISD $dst,$src" %}
10089 opcode(0x66, 0x0F, 0x2F);
10090 ins_encode(OpcP, OpcS, Opcode(tertiary), RegReg(dst, src));
10091 ins_pipe( pipe_slow );
10092 %}
10093
10094 // float compare and set condition codes in EFLAGS by XMM regs
10095 instruct cmpXD_ccmem(eFlagsRegU cr, regXD dst, memory src, eAXRegI rax) %{
10096 predicate(UseSSE>=2);
10097 match(Set cr (CmpD dst (LoadD src)));
10098 effect(KILL rax);
10099 ins_cost(145);
10100 format %{ "COMISD $dst,$src\n"
10101 "\tJNP exit\n"
10102 "\tMOV ah,1 // saw a NaN, set CF\n"
10103 "\tSAHF\n"
10104 "exit:\tNOP // avoid branch to branch" %}
10105 opcode(0x66, 0x0F, 0x2F);
10106 ins_encode(OpcP, OpcS, Opcode(tertiary), RegMem(dst, src), cmpF_P6_fixup);
10107 ins_pipe( pipe_slow );
10108 %}
10109
10110 instruct cmpXD_ccmemCF(eFlagsRegUCF cr, regXD dst, memory src) %{
10111 predicate(UseSSE>=2);
10112 match(Set cr (CmpD dst (LoadD src)));
10113 ins_cost(100);
10114 format %{ "COMISD $dst,$src" %}
10115 opcode(0x66, 0x0F, 0x2F);
10116 ins_encode(OpcP, OpcS, Opcode(tertiary), RegMem(dst, src));
10117 ins_pipe( pipe_slow );
10118 %}
10119
10120 // Compare into -1,0,1 in XMM
10121 instruct cmpXD_reg(eRegI dst, regXD src1, regXD src2, eFlagsReg cr) %{
10122 predicate(UseSSE>=2);
10123 match(Set dst (CmpD3 src1 src2));
10124 effect(KILL cr);
10125 ins_cost(255);
10126 format %{ "XOR $dst,$dst\n"
10127 "\tCOMISD $src1,$src2\n"
10128 "\tJP,s nan\n"
10129 "\tJEQ,s exit\n"
10130 "\tJA,s inc\n"
10131 "nan:\tDEC $dst\n"
10132 "\tJMP,s exit\n"
10133 "inc:\tINC $dst\n"
10134 "exit:"
10135 %}
10136 opcode(0x66, 0x0F, 0x2F);
10137 ins_encode(Xor_Reg(dst), OpcP, OpcS, Opcode(tertiary), RegReg(src1, src2),
10138 CmpX_Result(dst));
10139 ins_pipe( pipe_slow );
10140 %}
10141
10142 // Compare into -1,0,1 in XMM and memory
10143 instruct cmpXD_regmem(eRegI dst, regXD src1, memory mem, eFlagsReg cr) %{
10144 predicate(UseSSE>=2);
10145 match(Set dst (CmpD3 src1 (LoadD mem)));
10146 effect(KILL cr);
10147 ins_cost(275);
10148 format %{ "COMISD $src1,$mem\n"
10149 "\tMOV $dst,0\t\t# do not blow flags\n"
10150 "\tJP,s nan\n"
10151 "\tJEQ,s exit\n"
10152 "\tJA,s inc\n"
10153 "nan:\tDEC $dst\n"
10154 "\tJMP,s exit\n"
10155 "inc:\tINC $dst\n"
10156 "exit:"
10157 %}
10158 opcode(0x66, 0x0F, 0x2F);
10159 ins_encode(OpcP, OpcS, Opcode(tertiary), RegMem(src1, mem),
10160 LdImmI(dst,0x0), CmpX_Result(dst));
10161 ins_pipe( pipe_slow );
10162 %}
10163
10164
10165 instruct subD_reg(regD dst, regD src) %{
10166 predicate (UseSSE <=1);
10167 match(Set dst (SubD dst src));
10168
10169 format %{ "FLD $src\n\t"
10170 "DSUBp $dst,ST" %}
10171 opcode(0xDE, 0x5); /* DE E8+i or DE /5 */
10172 ins_cost(150);
10173 ins_encode( Push_Reg_D(src),
10174 OpcP, RegOpc(dst) );
10175 ins_pipe( fpu_reg_reg );
10176 %}
10177
10178 instruct subD_reg_round(stackSlotD dst, regD src1, regD src2) %{
10179 predicate (UseSSE <=1);
10180 match(Set dst (RoundDouble (SubD src1 src2)));
10181 ins_cost(250);
10182
10183 format %{ "FLD $src2\n\t"
10184 "DSUB ST,$src1\n\t"
10185 "FSTP_D $dst\t# D-round" %}
10186 opcode(0xD8, 0x5);
10187 ins_encode( Push_Reg_D(src2),
10188 OpcP, RegOpc(src1), Pop_Mem_D(dst) );
10189 ins_pipe( fpu_mem_reg_reg );
10190 %}
10191
10192
10193 instruct subD_reg_mem(regD dst, memory src) %{
10194 predicate (UseSSE <=1);
10195 match(Set dst (SubD dst (LoadD src)));
10196 ins_cost(150);
10197
10198 format %{ "FLD $src\n\t"
10199 "DSUBp $dst,ST" %}
10200 opcode(0xDE, 0x5, 0xDD); /* DE C0+i */ /* LoadD DD /0 */
10201 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
10202 OpcP, RegOpc(dst) );
10203 ins_pipe( fpu_reg_mem );
10204 %}
10205
10206 instruct absD_reg(regDPR1 dst, regDPR1 src) %{
10207 predicate (UseSSE<=1);
10208 match(Set dst (AbsD src));
10209 ins_cost(100);
10210 format %{ "FABS" %}
10211 opcode(0xE1, 0xD9);
10212 ins_encode( OpcS, OpcP );
10213 ins_pipe( fpu_reg_reg );
10214 %}
10215
10216 instruct absXD_reg( regXD dst ) %{
10217 predicate(UseSSE>=2);
10218 match(Set dst (AbsD dst));
10219 format %{ "ANDPD $dst,[0x7FFFFFFFFFFFFFFF]\t# ABS D by sign masking" %}
10220 ins_encode( AbsXD_encoding(dst));
10221 ins_pipe( pipe_slow );
10222 %}
10223
10224 instruct negD_reg(regDPR1 dst, regDPR1 src) %{
10225 predicate(UseSSE<=1);
10226 match(Set dst (NegD src));
10227 ins_cost(100);
10228 format %{ "FCHS" %}
10229 opcode(0xE0, 0xD9);
10230 ins_encode( OpcS, OpcP );
10231 ins_pipe( fpu_reg_reg );
10232 %}
10233
10234 instruct negXD_reg( regXD dst ) %{
10235 predicate(UseSSE>=2);
10236 match(Set dst (NegD dst));
10237 format %{ "XORPD $dst,[0x8000000000000000]\t# CHS D by sign flipping" %}
10238 ins_encode %{
10239 __ xorpd($dst$$XMMRegister,
10240 ExternalAddress((address)double_signflip_pool));
10241 %}
10242 ins_pipe( pipe_slow );
10243 %}
10244
10245 instruct addD_reg(regD dst, regD src) %{
10246 predicate(UseSSE<=1);
10247 match(Set dst (AddD dst src));
10248 format %{ "FLD $src\n\t"
10249 "DADD $dst,ST" %}
10250 size(4);
10251 ins_cost(150);
10252 opcode(0xDE, 0x0); /* DE C0+i or DE /0*/
10253 ins_encode( Push_Reg_D(src),
10254 OpcP, RegOpc(dst) );
10255 ins_pipe( fpu_reg_reg );
10256 %}
10257
10258
10259 instruct addD_reg_round(stackSlotD dst, regD src1, regD src2) %{
10260 predicate(UseSSE<=1);
10261 match(Set dst (RoundDouble (AddD src1 src2)));
10262 ins_cost(250);
10263
10264 format %{ "FLD $src2\n\t"
10265 "DADD ST,$src1\n\t"
10266 "FSTP_D $dst\t# D-round" %}
10267 opcode(0xD8, 0x0); /* D8 C0+i or D8 /0*/
10268 ins_encode( Push_Reg_D(src2),
10269 OpcP, RegOpc(src1), Pop_Mem_D(dst) );
10270 ins_pipe( fpu_mem_reg_reg );
10271 %}
10272
10273
10274 instruct addD_reg_mem(regD dst, memory src) %{
10275 predicate(UseSSE<=1);
10276 match(Set dst (AddD dst (LoadD src)));
10277 ins_cost(150);
10278
10279 format %{ "FLD $src\n\t"
10280 "DADDp $dst,ST" %}
10281 opcode(0xDE, 0x0, 0xDD); /* DE C0+i */ /* LoadD DD /0 */
10282 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
10283 OpcP, RegOpc(dst) );
10284 ins_pipe( fpu_reg_mem );
10285 %}
10286
10287 // add-to-memory
10288 instruct addD_mem_reg(memory dst, regD src) %{
10289 predicate(UseSSE<=1);
10290 match(Set dst (StoreD dst (RoundDouble (AddD (LoadD dst) src))));
10291 ins_cost(150);
10292
10293 format %{ "FLD_D $dst\n\t"
10294 "DADD ST,$src\n\t"
10295 "FST_D $dst" %}
10296 opcode(0xDD, 0x0);
10297 ins_encode( Opcode(0xDD), RMopc_Mem(0x00,dst),
10298 Opcode(0xD8), RegOpc(src),
10299 set_instruction_start,
10300 Opcode(0xDD), RMopc_Mem(0x03,dst) );
10301 ins_pipe( fpu_reg_mem );
10302 %}
10303
10304 instruct addD_reg_imm1(regD dst, immD1 src) %{
10305 predicate(UseSSE<=1);
10306 match(Set dst (AddD dst src));
10307 ins_cost(125);
10308 format %{ "FLD1\n\t"
10309 "DADDp $dst,ST" %}
10310 opcode(0xDE, 0x00);
10311 ins_encode( LdImmD(src),
10312 OpcP, RegOpc(dst) );
10313 ins_pipe( fpu_reg );
10314 %}
10315
10316 instruct addD_reg_imm(regD dst, immD src) %{
10317 predicate(UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 );
10318 match(Set dst (AddD dst src));
10319 ins_cost(200);
10320 format %{ "FLD_D [$src]\n\t"
10321 "DADDp $dst,ST" %}
10322 opcode(0xDE, 0x00); /* DE /0 */
10323 ins_encode( LdImmD(src),
10324 OpcP, RegOpc(dst));
10325 ins_pipe( fpu_reg_mem );
10326 %}
10327
10328 instruct addD_reg_imm_round(stackSlotD dst, regD src, immD con) %{
10329 predicate(UseSSE<=1 && _kids[0]->_kids[1]->_leaf->getd() != 0.0 && _kids[0]->_kids[1]->_leaf->getd() != 1.0 );
10330 match(Set dst (RoundDouble (AddD src con)));
10331 ins_cost(200);
10332 format %{ "FLD_D [$con]\n\t"
10333 "DADD ST,$src\n\t"
10334 "FSTP_D $dst\t# D-round" %}
10335 opcode(0xD8, 0x00); /* D8 /0 */
10336 ins_encode( LdImmD(con),
10337 OpcP, RegOpc(src), Pop_Mem_D(dst));
10338 ins_pipe( fpu_mem_reg_con );
10339 %}
10340
10341 // Add two double precision floating point values in xmm
10342 instruct addXD_reg(regXD dst, regXD src) %{
10343 predicate(UseSSE>=2);
10344 match(Set dst (AddD dst src));
10345 format %{ "ADDSD $dst,$src" %}
10346 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x58), RegReg(dst, src));
10347 ins_pipe( pipe_slow );
10348 %}
10349
10350 instruct addXD_imm(regXD dst, immXD con) %{
10351 predicate(UseSSE>=2);
10352 match(Set dst (AddD dst con));
10353 format %{ "ADDSD $dst,[$con]" %}
10354 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x58), LdImmXD(dst, con) );
10355 ins_pipe( pipe_slow );
10356 %}
10357
10358 instruct addXD_mem(regXD dst, memory mem) %{
10359 predicate(UseSSE>=2);
10360 match(Set dst (AddD dst (LoadD mem)));
10361 format %{ "ADDSD $dst,$mem" %}
10362 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x58), RegMem(dst,mem));
10363 ins_pipe( pipe_slow );
10364 %}
10365
10366 // Sub two double precision floating point values in xmm
10367 instruct subXD_reg(regXD dst, regXD src) %{
10368 predicate(UseSSE>=2);
10369 match(Set dst (SubD dst src));
10370 format %{ "SUBSD $dst,$src" %}
10371 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5C), RegReg(dst, src));
10372 ins_pipe( pipe_slow );
10373 %}
10374
10375 instruct subXD_imm(regXD dst, immXD con) %{
10376 predicate(UseSSE>=2);
10377 match(Set dst (SubD dst con));
10378 format %{ "SUBSD $dst,[$con]" %}
10379 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5C), LdImmXD(dst, con) );
10380 ins_pipe( pipe_slow );
10381 %}
10382
10383 instruct subXD_mem(regXD dst, memory mem) %{
10384 predicate(UseSSE>=2);
10385 match(Set dst (SubD dst (LoadD mem)));
10386 format %{ "SUBSD $dst,$mem" %}
10387 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5C), RegMem(dst,mem));
10388 ins_pipe( pipe_slow );
10389 %}
10390
10391 // Mul two double precision floating point values in xmm
10392 instruct mulXD_reg(regXD dst, regXD src) %{
10393 predicate(UseSSE>=2);
10394 match(Set dst (MulD dst src));
10395 format %{ "MULSD $dst,$src" %}
10396 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x59), RegReg(dst, src));
10397 ins_pipe( pipe_slow );
10398 %}
10399
10400 instruct mulXD_imm(regXD dst, immXD con) %{
10401 predicate(UseSSE>=2);
10402 match(Set dst (MulD dst con));
10403 format %{ "MULSD $dst,[$con]" %}
10404 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x59), LdImmXD(dst, con) );
10405 ins_pipe( pipe_slow );
10406 %}
10407
10408 instruct mulXD_mem(regXD dst, memory mem) %{
10409 predicate(UseSSE>=2);
10410 match(Set dst (MulD dst (LoadD mem)));
10411 format %{ "MULSD $dst,$mem" %}
10412 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x59), RegMem(dst,mem));
10413 ins_pipe( pipe_slow );
10414 %}
10415
10416 // Div two double precision floating point values in xmm
10417 instruct divXD_reg(regXD dst, regXD src) %{
10418 predicate(UseSSE>=2);
10419 match(Set dst (DivD dst src));
10420 format %{ "DIVSD $dst,$src" %}
10421 opcode(0xF2, 0x0F, 0x5E);
10422 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5E), RegReg(dst, src));
10423 ins_pipe( pipe_slow );
10424 %}
10425
10426 instruct divXD_imm(regXD dst, immXD con) %{
10427 predicate(UseSSE>=2);
10428 match(Set dst (DivD dst con));
10429 format %{ "DIVSD $dst,[$con]" %}
10430 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5E), LdImmXD(dst, con));
10431 ins_pipe( pipe_slow );
10432 %}
10433
10434 instruct divXD_mem(regXD dst, memory mem) %{
10435 predicate(UseSSE>=2);
10436 match(Set dst (DivD dst (LoadD mem)));
10437 format %{ "DIVSD $dst,$mem" %}
10438 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5E), RegMem(dst,mem));
10439 ins_pipe( pipe_slow );
10440 %}
10441
10442
10443 instruct mulD_reg(regD dst, regD src) %{
10444 predicate(UseSSE<=1);
10445 match(Set dst (MulD dst src));
10446 format %{ "FLD $src\n\t"
10447 "DMULp $dst,ST" %}
10448 opcode(0xDE, 0x1); /* DE C8+i or DE /1*/
10449 ins_cost(150);
10450 ins_encode( Push_Reg_D(src),
10451 OpcP, RegOpc(dst) );
10452 ins_pipe( fpu_reg_reg );
10453 %}
10454
10455 // Strict FP instruction biases argument before multiply then
10456 // biases result to avoid double rounding of subnormals.
10457 //
10458 // scale arg1 by multiplying arg1 by 2^(-15360)
10459 // load arg2
10460 // multiply scaled arg1 by arg2
10461 // rescale product by 2^(15360)
10462 //
10463 instruct strictfp_mulD_reg(regDPR1 dst, regnotDPR1 src) %{
10464 predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() );
10465 match(Set dst (MulD dst src));
10466 ins_cost(1); // Select this instruction for all strict FP double multiplies
10467
10468 format %{ "FLD StubRoutines::_fpu_subnormal_bias1\n\t"
10469 "DMULp $dst,ST\n\t"
10470 "FLD $src\n\t"
10471 "DMULp $dst,ST\n\t"
10472 "FLD StubRoutines::_fpu_subnormal_bias2\n\t"
10473 "DMULp $dst,ST\n\t" %}
10474 opcode(0xDE, 0x1); /* DE C8+i or DE /1*/
10475 ins_encode( strictfp_bias1(dst),
10476 Push_Reg_D(src),
10477 OpcP, RegOpc(dst),
10478 strictfp_bias2(dst) );
10479 ins_pipe( fpu_reg_reg );
10480 %}
10481
10482 instruct mulD_reg_imm(regD dst, immD src) %{
10483 predicate( UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 );
10484 match(Set dst (MulD dst src));
10485 ins_cost(200);
10486 format %{ "FLD_D [$src]\n\t"
10487 "DMULp $dst,ST" %}
10488 opcode(0xDE, 0x1); /* DE /1 */
10489 ins_encode( LdImmD(src),
10490 OpcP, RegOpc(dst) );
10491 ins_pipe( fpu_reg_mem );
10492 %}
10493
10494
10495 instruct mulD_reg_mem(regD dst, memory src) %{
10496 predicate( UseSSE<=1 );
10497 match(Set dst (MulD dst (LoadD src)));
10498 ins_cost(200);
10499 format %{ "FLD_D $src\n\t"
10500 "DMULp $dst,ST" %}
10501 opcode(0xDE, 0x1, 0xDD); /* DE C8+i or DE /1*/ /* LoadD DD /0 */
10502 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
10503 OpcP, RegOpc(dst) );
10504 ins_pipe( fpu_reg_mem );
10505 %}
10506
10507 //
10508 // Cisc-alternate to reg-reg multiply
10509 instruct mulD_reg_mem_cisc(regD dst, regD src, memory mem) %{
10510 predicate( UseSSE<=1 );
10511 match(Set dst (MulD src (LoadD mem)));
10512 ins_cost(250);
10513 format %{ "FLD_D $mem\n\t"
10514 "DMUL ST,$src\n\t"
10515 "FSTP_D $dst" %}
10516 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */ /* LoadD D9 /0 */
10517 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem),
10518 OpcReg_F(src),
10519 Pop_Reg_D(dst) );
10520 ins_pipe( fpu_reg_reg_mem );
10521 %}
10522
10523
10524 // MACRO3 -- addD a mulD
10525 // This instruction is a '2-address' instruction in that the result goes
10526 // back to src2. This eliminates a move from the macro; possibly the
10527 // register allocator will have to add it back (and maybe not).
10528 instruct addD_mulD_reg(regD src2, regD src1, regD src0) %{
10529 predicate( UseSSE<=1 );
10530 match(Set src2 (AddD (MulD src0 src1) src2));
10531 format %{ "FLD $src0\t# ===MACRO3d===\n\t"
10532 "DMUL ST,$src1\n\t"
10533 "DADDp $src2,ST" %}
10534 ins_cost(250);
10535 opcode(0xDD); /* LoadD DD /0 */
10536 ins_encode( Push_Reg_F(src0),
10537 FMul_ST_reg(src1),
10538 FAddP_reg_ST(src2) );
10539 ins_pipe( fpu_reg_reg_reg );
10540 %}
10541
10542
10543 // MACRO3 -- subD a mulD
10544 instruct subD_mulD_reg(regD src2, regD src1, regD src0) %{
10545 predicate( UseSSE<=1 );
10546 match(Set src2 (SubD (MulD src0 src1) src2));
10547 format %{ "FLD $src0\t# ===MACRO3d===\n\t"
10548 "DMUL ST,$src1\n\t"
10549 "DSUBRp $src2,ST" %}
10550 ins_cost(250);
10551 ins_encode( Push_Reg_F(src0),
10552 FMul_ST_reg(src1),
10553 Opcode(0xDE), Opc_plus(0xE0,src2));
10554 ins_pipe( fpu_reg_reg_reg );
10555 %}
10556
10557
10558 instruct divD_reg(regD dst, regD src) %{
10559 predicate( UseSSE<=1 );
10560 match(Set dst (DivD dst src));
10561
10562 format %{ "FLD $src\n\t"
10563 "FDIVp $dst,ST" %}
10564 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
10565 ins_cost(150);
10566 ins_encode( Push_Reg_D(src),
10567 OpcP, RegOpc(dst) );
10568 ins_pipe( fpu_reg_reg );
10569 %}
10570
10571 // Strict FP instruction biases argument before division then
10572 // biases result, to avoid double rounding of subnormals.
10573 //
10574 // scale dividend by multiplying dividend by 2^(-15360)
10575 // load divisor
10576 // divide scaled dividend by divisor
10577 // rescale quotient by 2^(15360)
10578 //
10579 instruct strictfp_divD_reg(regDPR1 dst, regnotDPR1 src) %{
10580 predicate (UseSSE<=1);
10581 match(Set dst (DivD dst src));
10582 predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() );
10583 ins_cost(01);
10584
10585 format %{ "FLD StubRoutines::_fpu_subnormal_bias1\n\t"
10586 "DMULp $dst,ST\n\t"
10587 "FLD $src\n\t"
10588 "FDIVp $dst,ST\n\t"
10589 "FLD StubRoutines::_fpu_subnormal_bias2\n\t"
10590 "DMULp $dst,ST\n\t" %}
10591 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
10592 ins_encode( strictfp_bias1(dst),
10593 Push_Reg_D(src),
10594 OpcP, RegOpc(dst),
10595 strictfp_bias2(dst) );
10596 ins_pipe( fpu_reg_reg );
10597 %}
10598
10599 instruct divD_reg_round(stackSlotD dst, regD src1, regD src2) %{
10600 predicate( UseSSE<=1 && !(Compile::current()->has_method() && Compile::current()->method()->is_strict()) );
10601 match(Set dst (RoundDouble (DivD src1 src2)));
10602
10603 format %{ "FLD $src1\n\t"
10604 "FDIV ST,$src2\n\t"
10605 "FSTP_D $dst\t# D-round" %}
10606 opcode(0xD8, 0x6); /* D8 F0+i or D8 /6 */
10607 ins_encode( Push_Reg_D(src1),
10608 OpcP, RegOpc(src2), Pop_Mem_D(dst) );
10609 ins_pipe( fpu_mem_reg_reg );
10610 %}
10611
10612
10613 instruct modD_reg(regD dst, regD src, eAXRegI rax, eFlagsReg cr) %{
10614 predicate(UseSSE<=1);
10615 match(Set dst (ModD dst src));
10616 effect(KILL rax, KILL cr); // emitModD() uses EAX and EFLAGS
10617
10618 format %{ "DMOD $dst,$src" %}
10619 ins_cost(250);
10620 ins_encode(Push_Reg_Mod_D(dst, src),
10621 emitModD(),
10622 Push_Result_Mod_D(src),
10623 Pop_Reg_D(dst));
10624 ins_pipe( pipe_slow );
10625 %}
10626
10627 instruct modXD_reg(regXD dst, regXD src0, regXD src1, eAXRegI rax, eFlagsReg cr) %{
10628 predicate(UseSSE>=2);
10629 match(Set dst (ModD src0 src1));
10630 effect(KILL rax, KILL cr);
10631
10632 format %{ "SUB ESP,8\t # DMOD\n"
10633 "\tMOVSD [ESP+0],$src1\n"
10634 "\tFLD_D [ESP+0]\n"
10635 "\tMOVSD [ESP+0],$src0\n"
10636 "\tFLD_D [ESP+0]\n"
10637 "loop:\tFPREM\n"
10638 "\tFWAIT\n"
10639 "\tFNSTSW AX\n"
10640 "\tSAHF\n"
10641 "\tJP loop\n"
10642 "\tFSTP_D [ESP+0]\n"
10643 "\tMOVSD $dst,[ESP+0]\n"
10644 "\tADD ESP,8\n"
10645 "\tFSTP ST0\t # Restore FPU Stack"
10646 %}
10647 ins_cost(250);
10648 ins_encode( Push_ModD_encoding(src0, src1), emitModD(), Push_ResultXD(dst), PopFPU);
10649 ins_pipe( pipe_slow );
10650 %}
10651
10652 instruct sinD_reg(regDPR1 dst, regDPR1 src) %{
10653 predicate (UseSSE<=1);
10654 match(Set dst (SinD src));
10655 ins_cost(1800);
10656 format %{ "DSIN $dst" %}
10657 opcode(0xD9, 0xFE);
10658 ins_encode( OpcP, OpcS );
10659 ins_pipe( pipe_slow );
10660 %}
10661
10662 instruct sinXD_reg(regXD dst, eFlagsReg cr) %{
10663 predicate (UseSSE>=2);
10664 match(Set dst (SinD dst));
10665 effect(KILL cr); // Push_{Src|Result}XD() uses "{SUB|ADD} ESP,8"
10666 ins_cost(1800);
10667 format %{ "DSIN $dst" %}
10668 opcode(0xD9, 0xFE);
10669 ins_encode( Push_SrcXD(dst), OpcP, OpcS, Push_ResultXD(dst) );
10670 ins_pipe( pipe_slow );
10671 %}
10672
10673 instruct cosD_reg(regDPR1 dst, regDPR1 src) %{
10674 predicate (UseSSE<=1);
10675 match(Set dst (CosD src));
10676 ins_cost(1800);
10677 format %{ "DCOS $dst" %}
10678 opcode(0xD9, 0xFF);
10679 ins_encode( OpcP, OpcS );
10680 ins_pipe( pipe_slow );
10681 %}
10682
10683 instruct cosXD_reg(regXD dst, eFlagsReg cr) %{
10684 predicate (UseSSE>=2);
10685 match(Set dst (CosD dst));
10686 effect(KILL cr); // Push_{Src|Result}XD() uses "{SUB|ADD} ESP,8"
10687 ins_cost(1800);
10688 format %{ "DCOS $dst" %}
10689 opcode(0xD9, 0xFF);
10690 ins_encode( Push_SrcXD(dst), OpcP, OpcS, Push_ResultXD(dst) );
10691 ins_pipe( pipe_slow );
10692 %}
10693
10694 instruct tanD_reg(regDPR1 dst, regDPR1 src) %{
10695 predicate (UseSSE<=1);
10696 match(Set dst(TanD src));
10697 format %{ "DTAN $dst" %}
10698 ins_encode( Opcode(0xD9), Opcode(0xF2), // fptan
10699 Opcode(0xDD), Opcode(0xD8)); // fstp st
10700 ins_pipe( pipe_slow );
10701 %}
10702
10703 instruct tanXD_reg(regXD dst, eFlagsReg cr) %{
10704 predicate (UseSSE>=2);
10705 match(Set dst(TanD dst));
10706 effect(KILL cr); // Push_{Src|Result}XD() uses "{SUB|ADD} ESP,8"
10707 format %{ "DTAN $dst" %}
10708 ins_encode( Push_SrcXD(dst),
10709 Opcode(0xD9), Opcode(0xF2), // fptan
10710 Opcode(0xDD), Opcode(0xD8), // fstp st
10711 Push_ResultXD(dst) );
10712 ins_pipe( pipe_slow );
10713 %}
10714
10715 instruct atanD_reg(regD dst, regD src) %{
10716 predicate (UseSSE<=1);
10717 match(Set dst(AtanD dst src));
10718 format %{ "DATA $dst,$src" %}
10719 opcode(0xD9, 0xF3);
10720 ins_encode( Push_Reg_D(src),
10721 OpcP, OpcS, RegOpc(dst) );
10722 ins_pipe( pipe_slow );
10723 %}
10724
10725 instruct atanXD_reg(regXD dst, regXD src, eFlagsReg cr) %{
10726 predicate (UseSSE>=2);
10727 match(Set dst(AtanD dst src));
10728 effect(KILL cr); // Push_{Src|Result}XD() uses "{SUB|ADD} ESP,8"
10729 format %{ "DATA $dst,$src" %}
10730 opcode(0xD9, 0xF3);
10731 ins_encode( Push_SrcXD(src),
10732 OpcP, OpcS, Push_ResultXD(dst) );
10733 ins_pipe( pipe_slow );
10734 %}
10735
10736 instruct sqrtD_reg(regD dst, regD src) %{
10737 predicate (UseSSE<=1);
10738 match(Set dst (SqrtD src));
10739 format %{ "DSQRT $dst,$src" %}
10740 opcode(0xFA, 0xD9);
10741 ins_encode( Push_Reg_D(src),
10742 OpcS, OpcP, Pop_Reg_D(dst) );
10743 ins_pipe( pipe_slow );
10744 %}
10745
10746 instruct powD_reg(regD X, regDPR1 Y, eAXRegI rax, eBXRegI rbx, eCXRegI rcx) %{
10747 predicate (UseSSE<=1);
10748 match(Set Y (PowD X Y)); // Raise X to the Yth power
10749 effect(KILL rax, KILL rbx, KILL rcx);
10750 format %{ "SUB ESP,8\t\t# Fast-path POW encoding\n\t"
10751 "FLD_D $X\n\t"
10752 "FYL2X \t\t\t# Q=Y*ln2(X)\n\t"
10753
10754 "FDUP \t\t\t# Q Q\n\t"
10755 "FRNDINT\t\t\t# int(Q) Q\n\t"
10756 "FSUB ST(1),ST(0)\t# int(Q) frac(Q)\n\t"
10757 "FISTP dword [ESP]\n\t"
10758 "F2XM1 \t\t\t# 2^frac(Q)-1 int(Q)\n\t"
10759 "FLD1 \t\t\t# 1 2^frac(Q)-1 int(Q)\n\t"
10760 "FADDP \t\t\t# 2^frac(Q) int(Q)\n\t" // could use FADD [1.000] instead
10761 "MOV EAX,[ESP]\t# Pick up int(Q)\n\t"
10762 "MOV ECX,0xFFFFF800\t# Overflow mask\n\t"
10763 "ADD EAX,1023\t\t# Double exponent bias\n\t"
10764 "MOV EBX,EAX\t\t# Preshifted biased expo\n\t"
10765 "SHL EAX,20\t\t# Shift exponent into place\n\t"
10766 "TEST EBX,ECX\t\t# Check for overflow\n\t"
10767 "CMOVne EAX,ECX\t\t# If overflow, stuff NaN into EAX\n\t"
10768 "MOV [ESP+4],EAX\t# Marshal 64-bit scaling double\n\t"
10769 "MOV [ESP+0],0\n\t"
10770 "FMUL ST(0),[ESP+0]\t# Scale\n\t"
10771
10772 "ADD ESP,8"
10773 %}
10774 ins_encode( push_stack_temp_qword,
10775 Push_Reg_D(X),
10776 Opcode(0xD9), Opcode(0xF1), // fyl2x
10777 pow_exp_core_encoding,
10778 pop_stack_temp_qword);
10779 ins_pipe( pipe_slow );
10780 %}
10781
10782 instruct powXD_reg(regXD dst, regXD src0, regXD src1, regDPR1 tmp1, eAXRegI rax, eBXRegI rbx, eCXRegI rcx ) %{
10783 predicate (UseSSE>=2);
10784 match(Set dst (PowD src0 src1)); // Raise src0 to the src1'th power
10785 effect(KILL tmp1, KILL rax, KILL rbx, KILL rcx );
10786 format %{ "SUB ESP,8\t\t# Fast-path POW encoding\n\t"
10787 "MOVSD [ESP],$src1\n\t"
10788 "FLD FPR1,$src1\n\t"
10789 "MOVSD [ESP],$src0\n\t"
10790 "FLD FPR1,$src0\n\t"
10791 "FYL2X \t\t\t# Q=Y*ln2(X)\n\t"
10792
10793 "FDUP \t\t\t# Q Q\n\t"
10794 "FRNDINT\t\t\t# int(Q) Q\n\t"
10795 "FSUB ST(1),ST(0)\t# int(Q) frac(Q)\n\t"
10796 "FISTP dword [ESP]\n\t"
10797 "F2XM1 \t\t\t# 2^frac(Q)-1 int(Q)\n\t"
10798 "FLD1 \t\t\t# 1 2^frac(Q)-1 int(Q)\n\t"
10799 "FADDP \t\t\t# 2^frac(Q) int(Q)\n\t" // could use FADD [1.000] instead
10800 "MOV EAX,[ESP]\t# Pick up int(Q)\n\t"
10801 "MOV ECX,0xFFFFF800\t# Overflow mask\n\t"
10802 "ADD EAX,1023\t\t# Double exponent bias\n\t"
10803 "MOV EBX,EAX\t\t# Preshifted biased expo\n\t"
10804 "SHL EAX,20\t\t# Shift exponent into place\n\t"
10805 "TEST EBX,ECX\t\t# Check for overflow\n\t"
10806 "CMOVne EAX,ECX\t\t# If overflow, stuff NaN into EAX\n\t"
10807 "MOV [ESP+4],EAX\t# Marshal 64-bit scaling double\n\t"
10808 "MOV [ESP+0],0\n\t"
10809 "FMUL ST(0),[ESP+0]\t# Scale\n\t"
10810
10811 "FST_D [ESP]\n\t"
10812 "MOVSD $dst,[ESP]\n\t"
10813 "ADD ESP,8"
10814 %}
10815 ins_encode( push_stack_temp_qword,
10816 push_xmm_to_fpr1(src1),
10817 push_xmm_to_fpr1(src0),
10818 Opcode(0xD9), Opcode(0xF1), // fyl2x
10819 pow_exp_core_encoding,
10820 Push_ResultXD(dst) );
10821 ins_pipe( pipe_slow );
10822 %}
10823
10824
10825 instruct expD_reg(regDPR1 dpr1, eAXRegI rax, eBXRegI rbx, eCXRegI rcx) %{
10826 predicate (UseSSE<=1);
10827 match(Set dpr1 (ExpD dpr1));
10828 effect(KILL rax, KILL rbx, KILL rcx);
10829 format %{ "SUB ESP,8\t\t# Fast-path EXP encoding"
10830 "FLDL2E \t\t\t# Ld log2(e) X\n\t"
10831 "FMULP \t\t\t# Q=X*log2(e)\n\t"
10832
10833 "FDUP \t\t\t# Q Q\n\t"
10834 "FRNDINT\t\t\t# int(Q) Q\n\t"
10835 "FSUB ST(1),ST(0)\t# int(Q) frac(Q)\n\t"
10836 "FISTP dword [ESP]\n\t"
10837 "F2XM1 \t\t\t# 2^frac(Q)-1 int(Q)\n\t"
10838 "FLD1 \t\t\t# 1 2^frac(Q)-1 int(Q)\n\t"
10839 "FADDP \t\t\t# 2^frac(Q) int(Q)\n\t" // could use FADD [1.000] instead
10840 "MOV EAX,[ESP]\t# Pick up int(Q)\n\t"
10841 "MOV ECX,0xFFFFF800\t# Overflow mask\n\t"
10842 "ADD EAX,1023\t\t# Double exponent bias\n\t"
10843 "MOV EBX,EAX\t\t# Preshifted biased expo\n\t"
10844 "SHL EAX,20\t\t# Shift exponent into place\n\t"
10845 "TEST EBX,ECX\t\t# Check for overflow\n\t"
10846 "CMOVne EAX,ECX\t\t# If overflow, stuff NaN into EAX\n\t"
10847 "MOV [ESP+4],EAX\t# Marshal 64-bit scaling double\n\t"
10848 "MOV [ESP+0],0\n\t"
10849 "FMUL ST(0),[ESP+0]\t# Scale\n\t"
10850
10851 "ADD ESP,8"
10852 %}
10853 ins_encode( push_stack_temp_qword,
10854 Opcode(0xD9), Opcode(0xEA), // fldl2e
10855 Opcode(0xDE), Opcode(0xC9), // fmulp
10856 pow_exp_core_encoding,
10857 pop_stack_temp_qword);
10858 ins_pipe( pipe_slow );
10859 %}
10860
10861 instruct expXD_reg(regXD dst, regXD src, regDPR1 tmp1, eAXRegI rax, eBXRegI rbx, eCXRegI rcx) %{
10862 predicate (UseSSE>=2);
10863 match(Set dst (ExpD src));
10864 effect(KILL tmp1, KILL rax, KILL rbx, KILL rcx);
10865 format %{ "SUB ESP,8\t\t# Fast-path EXP encoding\n\t"
10866 "MOVSD [ESP],$src\n\t"
10867 "FLDL2E \t\t\t# Ld log2(e) X\n\t"
10868 "FMULP \t\t\t# Q=X*log2(e) X\n\t"
10869
10870 "FDUP \t\t\t# Q Q\n\t"
10871 "FRNDINT\t\t\t# int(Q) Q\n\t"
10872 "FSUB ST(1),ST(0)\t# int(Q) frac(Q)\n\t"
10873 "FISTP dword [ESP]\n\t"
10874 "F2XM1 \t\t\t# 2^frac(Q)-1 int(Q)\n\t"
10875 "FLD1 \t\t\t# 1 2^frac(Q)-1 int(Q)\n\t"
10876 "FADDP \t\t\t# 2^frac(Q) int(Q)\n\t" // could use FADD [1.000] instead
10877 "MOV EAX,[ESP]\t# Pick up int(Q)\n\t"
10878 "MOV ECX,0xFFFFF800\t# Overflow mask\n\t"
10879 "ADD EAX,1023\t\t# Double exponent bias\n\t"
10880 "MOV EBX,EAX\t\t# Preshifted biased expo\n\t"
10881 "SHL EAX,20\t\t# Shift exponent into place\n\t"
10882 "TEST EBX,ECX\t\t# Check for overflow\n\t"
10883 "CMOVne EAX,ECX\t\t# If overflow, stuff NaN into EAX\n\t"
10884 "MOV [ESP+4],EAX\t# Marshal 64-bit scaling double\n\t"
10885 "MOV [ESP+0],0\n\t"
10886 "FMUL ST(0),[ESP+0]\t# Scale\n\t"
10887
10888 "FST_D [ESP]\n\t"
10889 "MOVSD $dst,[ESP]\n\t"
10890 "ADD ESP,8"
10891 %}
10892 ins_encode( Push_SrcXD(src),
10893 Opcode(0xD9), Opcode(0xEA), // fldl2e
10894 Opcode(0xDE), Opcode(0xC9), // fmulp
10895 pow_exp_core_encoding,
10896 Push_ResultXD(dst) );
10897 ins_pipe( pipe_slow );
10898 %}
10899
10900
10901
10902 instruct log10D_reg(regDPR1 dst, regDPR1 src) %{
10903 predicate (UseSSE<=1);
10904 // The source Double operand on FPU stack
10905 match(Set dst (Log10D src));
10906 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number
10907 // fxch ; swap ST(0) with ST(1)
10908 // fyl2x ; compute log_10(2) * log_2(x)
10909 format %{ "FLDLG2 \t\t\t#Log10\n\t"
10910 "FXCH \n\t"
10911 "FYL2X \t\t\t# Q=Log10*Log_2(x)"
10912 %}
10913 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2
10914 Opcode(0xD9), Opcode(0xC9), // fxch
10915 Opcode(0xD9), Opcode(0xF1)); // fyl2x
10916
10917 ins_pipe( pipe_slow );
10918 %}
10919
10920 instruct log10XD_reg(regXD dst, regXD src, eFlagsReg cr) %{
10921 predicate (UseSSE>=2);
10922 effect(KILL cr);
10923 match(Set dst (Log10D src));
10924 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number
10925 // fyl2x ; compute log_10(2) * log_2(x)
10926 format %{ "FLDLG2 \t\t\t#Log10\n\t"
10927 "FYL2X \t\t\t# Q=Log10*Log_2(x)"
10928 %}
10929 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2
10930 Push_SrcXD(src),
10931 Opcode(0xD9), Opcode(0xF1), // fyl2x
10932 Push_ResultXD(dst));
10933
10934 ins_pipe( pipe_slow );
10935 %}
10936
10937 instruct logD_reg(regDPR1 dst, regDPR1 src) %{
10938 predicate (UseSSE<=1);
10939 // The source Double operand on FPU stack
10940 match(Set dst (LogD src));
10941 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number
10942 // fxch ; swap ST(0) with ST(1)
10943 // fyl2x ; compute log_e(2) * log_2(x)
10944 format %{ "FLDLN2 \t\t\t#Log_e\n\t"
10945 "FXCH \n\t"
10946 "FYL2X \t\t\t# Q=Log_e*Log_2(x)"
10947 %}
10948 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2
10949 Opcode(0xD9), Opcode(0xC9), // fxch
10950 Opcode(0xD9), Opcode(0xF1)); // fyl2x
10951
10952 ins_pipe( pipe_slow );
10953 %}
10954
10955 instruct logXD_reg(regXD dst, regXD src, eFlagsReg cr) %{
10956 predicate (UseSSE>=2);
10957 effect(KILL cr);
10958 // The source and result Double operands in XMM registers
10959 match(Set dst (LogD src));
10960 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number
10961 // fyl2x ; compute log_e(2) * log_2(x)
10962 format %{ "FLDLN2 \t\t\t#Log_e\n\t"
10963 "FYL2X \t\t\t# Q=Log_e*Log_2(x)"
10964 %}
10965 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2
10966 Push_SrcXD(src),
10967 Opcode(0xD9), Opcode(0xF1), // fyl2x
10968 Push_ResultXD(dst));
10969 ins_pipe( pipe_slow );
10970 %}
10971
10972 //-------------Float Instructions-------------------------------
10973 // Float Math
10974
10975 // Code for float compare:
10976 // fcompp();
10977 // fwait(); fnstsw_ax();
10978 // sahf();
10979 // movl(dst, unordered_result);
10980 // jcc(Assembler::parity, exit);
10981 // movl(dst, less_result);
10982 // jcc(Assembler::below, exit);
10983 // movl(dst, equal_result);
10984 // jcc(Assembler::equal, exit);
10985 // movl(dst, greater_result);
10986 // exit:
10987
10988 // P6 version of float compare, sets condition codes in EFLAGS
10989 instruct cmpF_cc_P6(eFlagsRegU cr, regF src1, regF src2, eAXRegI rax) %{
10990 predicate(VM_Version::supports_cmov() && UseSSE == 0);
10991 match(Set cr (CmpF src1 src2));
10992 effect(KILL rax);
10993 ins_cost(150);
10994 format %{ "FLD $src1\n\t"
10995 "FUCOMIP ST,$src2 // P6 instruction\n\t"
10996 "JNP exit\n\t"
10997 "MOV ah,1 // saw a NaN, set CF (treat as LT)\n\t"
10998 "SAHF\n"
10999 "exit:\tNOP // avoid branch to branch" %}
11000 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
11001 ins_encode( Push_Reg_D(src1),
11002 OpcP, RegOpc(src2),
11003 cmpF_P6_fixup );
11004 ins_pipe( pipe_slow );
11005 %}
11006
11007 instruct cmpF_cc_P6CF(eFlagsRegUCF cr, regF src1, regF src2) %{
11008 predicate(VM_Version::supports_cmov() && UseSSE == 0);
11009 match(Set cr (CmpF src1 src2));
11010 ins_cost(100);
11011 format %{ "FLD $src1\n\t"
11012 "FUCOMIP ST,$src2 // P6 instruction" %}
11013 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
11014 ins_encode( Push_Reg_D(src1),
11015 OpcP, RegOpc(src2));
11016 ins_pipe( pipe_slow );
11017 %}
11018
11019
11020 // Compare & branch
11021 instruct cmpF_cc(eFlagsRegU cr, regF src1, regF src2, eAXRegI rax) %{
11022 predicate(UseSSE == 0);
11023 match(Set cr (CmpF src1 src2));
11024 effect(KILL rax);
11025 ins_cost(200);
11026 format %{ "FLD $src1\n\t"
11027 "FCOMp $src2\n\t"
11028 "FNSTSW AX\n\t"
11029 "TEST AX,0x400\n\t"
11030 "JZ,s flags\n\t"
11031 "MOV AH,1\t# unordered treat as LT\n"
11032 "flags:\tSAHF" %}
11033 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
11034 ins_encode( Push_Reg_D(src1),
11035 OpcP, RegOpc(src2),
11036 fpu_flags);
11037 ins_pipe( pipe_slow );
11038 %}
11039
11040 // Compare vs zero into -1,0,1
11041 instruct cmpF_0(eRegI dst, regF src1, immF0 zero, eAXRegI rax, eFlagsReg cr) %{
11042 predicate(UseSSE == 0);
11043 match(Set dst (CmpF3 src1 zero));
11044 effect(KILL cr, KILL rax);
11045 ins_cost(280);
11046 format %{ "FTSTF $dst,$src1" %}
11047 opcode(0xE4, 0xD9);
11048 ins_encode( Push_Reg_D(src1),
11049 OpcS, OpcP, PopFPU,
11050 CmpF_Result(dst));
11051 ins_pipe( pipe_slow );
11052 %}
11053
11054 // Compare into -1,0,1
11055 instruct cmpF_reg(eRegI dst, regF src1, regF src2, eAXRegI rax, eFlagsReg cr) %{
11056 predicate(UseSSE == 0);
11057 match(Set dst (CmpF3 src1 src2));
11058 effect(KILL cr, KILL rax);
11059 ins_cost(300);
11060 format %{ "FCMPF $dst,$src1,$src2" %}
11061 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
11062 ins_encode( Push_Reg_D(src1),
11063 OpcP, RegOpc(src2),
11064 CmpF_Result(dst));
11065 ins_pipe( pipe_slow );
11066 %}
11067
11068 // float compare and set condition codes in EFLAGS by XMM regs
11069 instruct cmpX_cc(eFlagsRegU cr, regX dst, regX src, eAXRegI rax) %{
11070 predicate(UseSSE>=1);
11071 match(Set cr (CmpF dst src));
11072 effect(KILL rax);
11073 ins_cost(145);
11074 format %{ "COMISS $dst,$src\n"
11075 "\tJNP exit\n"
11076 "\tMOV ah,1 // saw a NaN, set CF\n"
11077 "\tSAHF\n"
11078 "exit:\tNOP // avoid branch to branch" %}
11079 opcode(0x0F, 0x2F);
11080 ins_encode(OpcP, OpcS, RegReg(dst, src), cmpF_P6_fixup);
11081 ins_pipe( pipe_slow );
11082 %}
11083
11084 instruct cmpX_ccCF(eFlagsRegUCF cr, regX dst, regX src) %{
11085 predicate(UseSSE>=1);
11086 match(Set cr (CmpF dst src));
11087 ins_cost(100);
11088 format %{ "COMISS $dst,$src" %}
11089 opcode(0x0F, 0x2F);
11090 ins_encode(OpcP, OpcS, RegReg(dst, src));
11091 ins_pipe( pipe_slow );
11092 %}
11093
11094 // float compare and set condition codes in EFLAGS by XMM regs
11095 instruct cmpX_ccmem(eFlagsRegU cr, regX dst, memory src, eAXRegI rax) %{
11096 predicate(UseSSE>=1);
11097 match(Set cr (CmpF dst (LoadF src)));
11098 effect(KILL rax);
11099 ins_cost(165);
11100 format %{ "COMISS $dst,$src\n"
11101 "\tJNP exit\n"
11102 "\tMOV ah,1 // saw a NaN, set CF\n"
11103 "\tSAHF\n"
11104 "exit:\tNOP // avoid branch to branch" %}
11105 opcode(0x0F, 0x2F);
11106 ins_encode(OpcP, OpcS, RegMem(dst, src), cmpF_P6_fixup);
11107 ins_pipe( pipe_slow );
11108 %}
11109
11110 instruct cmpX_ccmemCF(eFlagsRegUCF cr, regX dst, memory src) %{
11111 predicate(UseSSE>=1);
11112 match(Set cr (CmpF dst (LoadF src)));
11113 ins_cost(100);
11114 format %{ "COMISS $dst,$src" %}
11115 opcode(0x0F, 0x2F);
11116 ins_encode(OpcP, OpcS, RegMem(dst, src));
11117 ins_pipe( pipe_slow );
11118 %}
11119
11120 // Compare into -1,0,1 in XMM
11121 instruct cmpX_reg(eRegI dst, regX src1, regX src2, eFlagsReg cr) %{
11122 predicate(UseSSE>=1);
11123 match(Set dst (CmpF3 src1 src2));
11124 effect(KILL cr);
11125 ins_cost(255);
11126 format %{ "XOR $dst,$dst\n"
11127 "\tCOMISS $src1,$src2\n"
11128 "\tJP,s nan\n"
11129 "\tJEQ,s exit\n"
11130 "\tJA,s inc\n"
11131 "nan:\tDEC $dst\n"
11132 "\tJMP,s exit\n"
11133 "inc:\tINC $dst\n"
11134 "exit:"
11135 %}
11136 opcode(0x0F, 0x2F);
11137 ins_encode(Xor_Reg(dst), OpcP, OpcS, RegReg(src1, src2), CmpX_Result(dst));
11138 ins_pipe( pipe_slow );
11139 %}
11140
11141 // Compare into -1,0,1 in XMM and memory
11142 instruct cmpX_regmem(eRegI dst, regX src1, memory mem, eFlagsReg cr) %{
11143 predicate(UseSSE>=1);
11144 match(Set dst (CmpF3 src1 (LoadF mem)));
11145 effect(KILL cr);
11146 ins_cost(275);
11147 format %{ "COMISS $src1,$mem\n"
11148 "\tMOV $dst,0\t\t# do not blow flags\n"
11149 "\tJP,s nan\n"
11150 "\tJEQ,s exit\n"
11151 "\tJA,s inc\n"
11152 "nan:\tDEC $dst\n"
11153 "\tJMP,s exit\n"
11154 "inc:\tINC $dst\n"
11155 "exit:"
11156 %}
11157 opcode(0x0F, 0x2F);
11158 ins_encode(OpcP, OpcS, RegMem(src1, mem), LdImmI(dst,0x0), CmpX_Result(dst));
11159 ins_pipe( pipe_slow );
11160 %}
11161
11162 // Spill to obtain 24-bit precision
11163 instruct subF24_reg(stackSlotF dst, regF src1, regF src2) %{
11164 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11165 match(Set dst (SubF src1 src2));
11166
11167 format %{ "FSUB $dst,$src1 - $src2" %}
11168 opcode(0xD8, 0x4); /* D8 E0+i or D8 /4 mod==0x3 ;; result in TOS */
11169 ins_encode( Push_Reg_F(src1),
11170 OpcReg_F(src2),
11171 Pop_Mem_F(dst) );
11172 ins_pipe( fpu_mem_reg_reg );
11173 %}
11174 //
11175 // This instruction does not round to 24-bits
11176 instruct subF_reg(regF dst, regF src) %{
11177 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11178 match(Set dst (SubF dst src));
11179
11180 format %{ "FSUB $dst,$src" %}
11181 opcode(0xDE, 0x5); /* DE E8+i or DE /5 */
11182 ins_encode( Push_Reg_F(src),
11183 OpcP, RegOpc(dst) );
11184 ins_pipe( fpu_reg_reg );
11185 %}
11186
11187 // Spill to obtain 24-bit precision
11188 instruct addF24_reg(stackSlotF dst, regF src1, regF src2) %{
11189 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11190 match(Set dst (AddF src1 src2));
11191
11192 format %{ "FADD $dst,$src1,$src2" %}
11193 opcode(0xD8, 0x0); /* D8 C0+i */
11194 ins_encode( Push_Reg_F(src2),
11195 OpcReg_F(src1),
11196 Pop_Mem_F(dst) );
11197 ins_pipe( fpu_mem_reg_reg );
11198 %}
11199 //
11200 // This instruction does not round to 24-bits
11201 instruct addF_reg(regF dst, regF src) %{
11202 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11203 match(Set dst (AddF dst src));
11204
11205 format %{ "FLD $src\n\t"
11206 "FADDp $dst,ST" %}
11207 opcode(0xDE, 0x0); /* DE C0+i or DE /0*/
11208 ins_encode( Push_Reg_F(src),
11209 OpcP, RegOpc(dst) );
11210 ins_pipe( fpu_reg_reg );
11211 %}
11212
11213 // Add two single precision floating point values in xmm
11214 instruct addX_reg(regX dst, regX src) %{
11215 predicate(UseSSE>=1);
11216 match(Set dst (AddF dst src));
11217 format %{ "ADDSS $dst,$src" %}
11218 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x58), RegReg(dst, src));
11219 ins_pipe( pipe_slow );
11220 %}
11221
11222 instruct addX_imm(regX dst, immXF con) %{
11223 predicate(UseSSE>=1);
11224 match(Set dst (AddF dst con));
11225 format %{ "ADDSS $dst,[$con]" %}
11226 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x58), LdImmX(dst, con) );
11227 ins_pipe( pipe_slow );
11228 %}
11229
11230 instruct addX_mem(regX dst, memory mem) %{
11231 predicate(UseSSE>=1);
11232 match(Set dst (AddF dst (LoadF mem)));
11233 format %{ "ADDSS $dst,$mem" %}
11234 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x58), RegMem(dst, mem));
11235 ins_pipe( pipe_slow );
11236 %}
11237
11238 // Subtract two single precision floating point values in xmm
11239 instruct subX_reg(regX dst, regX src) %{
11240 predicate(UseSSE>=1);
11241 match(Set dst (SubF dst src));
11242 format %{ "SUBSS $dst,$src" %}
11243 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5C), RegReg(dst, src));
11244 ins_pipe( pipe_slow );
11245 %}
11246
11247 instruct subX_imm(regX dst, immXF con) %{
11248 predicate(UseSSE>=1);
11249 match(Set dst (SubF dst con));
11250 format %{ "SUBSS $dst,[$con]" %}
11251 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5C), LdImmX(dst, con) );
11252 ins_pipe( pipe_slow );
11253 %}
11254
11255 instruct subX_mem(regX dst, memory mem) %{
11256 predicate(UseSSE>=1);
11257 match(Set dst (SubF dst (LoadF mem)));
11258 format %{ "SUBSS $dst,$mem" %}
11259 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5C), RegMem(dst,mem));
11260 ins_pipe( pipe_slow );
11261 %}
11262
11263 // Multiply two single precision floating point values in xmm
11264 instruct mulX_reg(regX dst, regX src) %{
11265 predicate(UseSSE>=1);
11266 match(Set dst (MulF dst src));
11267 format %{ "MULSS $dst,$src" %}
11268 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x59), RegReg(dst, src));
11269 ins_pipe( pipe_slow );
11270 %}
11271
11272 instruct mulX_imm(regX dst, immXF con) %{
11273 predicate(UseSSE>=1);
11274 match(Set dst (MulF dst con));
11275 format %{ "MULSS $dst,[$con]" %}
11276 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x59), LdImmX(dst, con) );
11277 ins_pipe( pipe_slow );
11278 %}
11279
11280 instruct mulX_mem(regX dst, memory mem) %{
11281 predicate(UseSSE>=1);
11282 match(Set dst (MulF dst (LoadF mem)));
11283 format %{ "MULSS $dst,$mem" %}
11284 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x59), RegMem(dst,mem));
11285 ins_pipe( pipe_slow );
11286 %}
11287
11288 // Divide two single precision floating point values in xmm
11289 instruct divX_reg(regX dst, regX src) %{
11290 predicate(UseSSE>=1);
11291 match(Set dst (DivF dst src));
11292 format %{ "DIVSS $dst,$src" %}
11293 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5E), RegReg(dst, src));
11294 ins_pipe( pipe_slow );
11295 %}
11296
11297 instruct divX_imm(regX dst, immXF con) %{
11298 predicate(UseSSE>=1);
11299 match(Set dst (DivF dst con));
11300 format %{ "DIVSS $dst,[$con]" %}
11301 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5E), LdImmX(dst, con) );
11302 ins_pipe( pipe_slow );
11303 %}
11304
11305 instruct divX_mem(regX dst, memory mem) %{
11306 predicate(UseSSE>=1);
11307 match(Set dst (DivF dst (LoadF mem)));
11308 format %{ "DIVSS $dst,$mem" %}
11309 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5E), RegMem(dst,mem));
11310 ins_pipe( pipe_slow );
11311 %}
11312
11313 // Get the square root of a single precision floating point values in xmm
11314 instruct sqrtX_reg(regX dst, regX src) %{
11315 predicate(UseSSE>=1);
11316 match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
11317 format %{ "SQRTSS $dst,$src" %}
11318 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x51), RegReg(dst, src));
11319 ins_pipe( pipe_slow );
11320 %}
11321
11322 instruct sqrtX_mem(regX dst, memory mem) %{
11323 predicate(UseSSE>=1);
11324 match(Set dst (ConvD2F (SqrtD (ConvF2D (LoadF mem)))));
11325 format %{ "SQRTSS $dst,$mem" %}
11326 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x51), RegMem(dst, mem));
11327 ins_pipe( pipe_slow );
11328 %}
11329
11330 // Get the square root of a double precision floating point values in xmm
11331 instruct sqrtXD_reg(regXD dst, regXD src) %{
11332 predicate(UseSSE>=2);
11333 match(Set dst (SqrtD src));
11334 format %{ "SQRTSD $dst,$src" %}
11335 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x51), RegReg(dst, src));
11336 ins_pipe( pipe_slow );
11337 %}
11338
11339 instruct sqrtXD_mem(regXD dst, memory mem) %{
11340 predicate(UseSSE>=2);
11341 match(Set dst (SqrtD (LoadD mem)));
11342 format %{ "SQRTSD $dst,$mem" %}
11343 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x51), RegMem(dst, mem));
11344 ins_pipe( pipe_slow );
11345 %}
11346
11347 instruct absF_reg(regFPR1 dst, regFPR1 src) %{
11348 predicate(UseSSE==0);
11349 match(Set dst (AbsF src));
11350 ins_cost(100);
11351 format %{ "FABS" %}
11352 opcode(0xE1, 0xD9);
11353 ins_encode( OpcS, OpcP );
11354 ins_pipe( fpu_reg_reg );
11355 %}
11356
11357 instruct absX_reg(regX dst ) %{
11358 predicate(UseSSE>=1);
11359 match(Set dst (AbsF dst));
11360 format %{ "ANDPS $dst,[0x7FFFFFFF]\t# ABS F by sign masking" %}
11361 ins_encode( AbsXF_encoding(dst));
11362 ins_pipe( pipe_slow );
11363 %}
11364
11365 instruct negF_reg(regFPR1 dst, regFPR1 src) %{
11366 predicate(UseSSE==0);
11367 match(Set dst (NegF src));
11368 ins_cost(100);
11369 format %{ "FCHS" %}
11370 opcode(0xE0, 0xD9);
11371 ins_encode( OpcS, OpcP );
11372 ins_pipe( fpu_reg_reg );
11373 %}
11374
11375 instruct negX_reg( regX dst ) %{
11376 predicate(UseSSE>=1);
11377 match(Set dst (NegF dst));
11378 format %{ "XORPS $dst,[0x80000000]\t# CHS F by sign flipping" %}
11379 ins_encode( NegXF_encoding(dst));
11380 ins_pipe( pipe_slow );
11381 %}
11382
11383 // Cisc-alternate to addF_reg
11384 // Spill to obtain 24-bit precision
11385 instruct addF24_reg_mem(stackSlotF dst, regF src1, memory src2) %{
11386 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11387 match(Set dst (AddF src1 (LoadF src2)));
11388
11389 format %{ "FLD $src2\n\t"
11390 "FADD ST,$src1\n\t"
11391 "FSTP_S $dst" %}
11392 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
11393 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
11394 OpcReg_F(src1),
11395 Pop_Mem_F(dst) );
11396 ins_pipe( fpu_mem_reg_mem );
11397 %}
11398 //
11399 // Cisc-alternate to addF_reg
11400 // This instruction does not round to 24-bits
11401 instruct addF_reg_mem(regF dst, memory src) %{
11402 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11403 match(Set dst (AddF dst (LoadF src)));
11404
11405 format %{ "FADD $dst,$src" %}
11406 opcode(0xDE, 0x0, 0xD9); /* DE C0+i or DE /0*/ /* LoadF D9 /0 */
11407 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
11408 OpcP, RegOpc(dst) );
11409 ins_pipe( fpu_reg_mem );
11410 %}
11411
11412 // // Following two instructions for _222_mpegaudio
11413 // Spill to obtain 24-bit precision
11414 instruct addF24_mem_reg(stackSlotF dst, regF src2, memory src1 ) %{
11415 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11416 match(Set dst (AddF src1 src2));
11417
11418 format %{ "FADD $dst,$src1,$src2" %}
11419 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
11420 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src1),
11421 OpcReg_F(src2),
11422 Pop_Mem_F(dst) );
11423 ins_pipe( fpu_mem_reg_mem );
11424 %}
11425
11426 // Cisc-spill variant
11427 // Spill to obtain 24-bit precision
11428 instruct addF24_mem_cisc(stackSlotF dst, memory src1, memory src2) %{
11429 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11430 match(Set dst (AddF src1 (LoadF src2)));
11431
11432 format %{ "FADD $dst,$src1,$src2 cisc" %}
11433 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
11434 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
11435 set_instruction_start,
11436 OpcP, RMopc_Mem(secondary,src1),
11437 Pop_Mem_F(dst) );
11438 ins_pipe( fpu_mem_mem_mem );
11439 %}
11440
11441 // Spill to obtain 24-bit precision
11442 instruct addF24_mem_mem(stackSlotF dst, memory src1, memory src2) %{
11443 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11444 match(Set dst (AddF src1 src2));
11445
11446 format %{ "FADD $dst,$src1,$src2" %}
11447 opcode(0xD8, 0x0, 0xD9); /* D8 /0 */ /* LoadF D9 /0 */
11448 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
11449 set_instruction_start,
11450 OpcP, RMopc_Mem(secondary,src1),
11451 Pop_Mem_F(dst) );
11452 ins_pipe( fpu_mem_mem_mem );
11453 %}
11454
11455
11456 // Spill to obtain 24-bit precision
11457 instruct addF24_reg_imm(stackSlotF dst, regF src1, immF src2) %{
11458 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11459 match(Set dst (AddF src1 src2));
11460 format %{ "FLD $src1\n\t"
11461 "FADD $src2\n\t"
11462 "FSTP_S $dst" %}
11463 opcode(0xD8, 0x00); /* D8 /0 */
11464 ins_encode( Push_Reg_F(src1),
11465 Opc_MemImm_F(src2),
11466 Pop_Mem_F(dst));
11467 ins_pipe( fpu_mem_reg_con );
11468 %}
11469 //
11470 // This instruction does not round to 24-bits
11471 instruct addF_reg_imm(regF dst, regF src1, immF src2) %{
11472 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11473 match(Set dst (AddF src1 src2));
11474 format %{ "FLD $src1\n\t"
11475 "FADD $src2\n\t"
11476 "FSTP_S $dst" %}
11477 opcode(0xD8, 0x00); /* D8 /0 */
11478 ins_encode( Push_Reg_F(src1),
11479 Opc_MemImm_F(src2),
11480 Pop_Reg_F(dst));
11481 ins_pipe( fpu_reg_reg_con );
11482 %}
11483
11484 // Spill to obtain 24-bit precision
11485 instruct mulF24_reg(stackSlotF dst, regF src1, regF src2) %{
11486 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11487 match(Set dst (MulF src1 src2));
11488
11489 format %{ "FLD $src1\n\t"
11490 "FMUL $src2\n\t"
11491 "FSTP_S $dst" %}
11492 opcode(0xD8, 0x1); /* D8 C8+i or D8 /1 ;; result in TOS */
11493 ins_encode( Push_Reg_F(src1),
11494 OpcReg_F(src2),
11495 Pop_Mem_F(dst) );
11496 ins_pipe( fpu_mem_reg_reg );
11497 %}
11498 //
11499 // This instruction does not round to 24-bits
11500 instruct mulF_reg(regF dst, regF src1, regF src2) %{
11501 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11502 match(Set dst (MulF src1 src2));
11503
11504 format %{ "FLD $src1\n\t"
11505 "FMUL $src2\n\t"
11506 "FSTP_S $dst" %}
11507 opcode(0xD8, 0x1); /* D8 C8+i */
11508 ins_encode( Push_Reg_F(src2),
11509 OpcReg_F(src1),
11510 Pop_Reg_F(dst) );
11511 ins_pipe( fpu_reg_reg_reg );
11512 %}
11513
11514
11515 // Spill to obtain 24-bit precision
11516 // Cisc-alternate to reg-reg multiply
11517 instruct mulF24_reg_mem(stackSlotF dst, regF src1, memory src2) %{
11518 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11519 match(Set dst (MulF src1 (LoadF src2)));
11520
11521 format %{ "FLD_S $src2\n\t"
11522 "FMUL $src1\n\t"
11523 "FSTP_S $dst" %}
11524 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or DE /1*/ /* LoadF D9 /0 */
11525 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
11526 OpcReg_F(src1),
11527 Pop_Mem_F(dst) );
11528 ins_pipe( fpu_mem_reg_mem );
11529 %}
11530 //
11531 // This instruction does not round to 24-bits
11532 // Cisc-alternate to reg-reg multiply
11533 instruct mulF_reg_mem(regF dst, regF src1, memory src2) %{
11534 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11535 match(Set dst (MulF src1 (LoadF src2)));
11536
11537 format %{ "FMUL $dst,$src1,$src2" %}
11538 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */ /* LoadF D9 /0 */
11539 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
11540 OpcReg_F(src1),
11541 Pop_Reg_F(dst) );
11542 ins_pipe( fpu_reg_reg_mem );
11543 %}
11544
11545 // Spill to obtain 24-bit precision
11546 instruct mulF24_mem_mem(stackSlotF dst, memory src1, memory src2) %{
11547 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11548 match(Set dst (MulF src1 src2));
11549
11550 format %{ "FMUL $dst,$src1,$src2" %}
11551 opcode(0xD8, 0x1, 0xD9); /* D8 /1 */ /* LoadF D9 /0 */
11552 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
11553 set_instruction_start,
11554 OpcP, RMopc_Mem(secondary,src1),
11555 Pop_Mem_F(dst) );
11556 ins_pipe( fpu_mem_mem_mem );
11557 %}
11558
11559 // Spill to obtain 24-bit precision
11560 instruct mulF24_reg_imm(stackSlotF dst, regF src1, immF src2) %{
11561 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11562 match(Set dst (MulF src1 src2));
11563
11564 format %{ "FMULc $dst,$src1,$src2" %}
11565 opcode(0xD8, 0x1); /* D8 /1*/
11566 ins_encode( Push_Reg_F(src1),
11567 Opc_MemImm_F(src2),
11568 Pop_Mem_F(dst));
11569 ins_pipe( fpu_mem_reg_con );
11570 %}
11571 //
11572 // This instruction does not round to 24-bits
11573 instruct mulF_reg_imm(regF dst, regF src1, immF src2) %{
11574 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11575 match(Set dst (MulF src1 src2));
11576
11577 format %{ "FMULc $dst. $src1, $src2" %}
11578 opcode(0xD8, 0x1); /* D8 /1*/
11579 ins_encode( Push_Reg_F(src1),
11580 Opc_MemImm_F(src2),
11581 Pop_Reg_F(dst));
11582 ins_pipe( fpu_reg_reg_con );
11583 %}
11584
11585
11586 //
11587 // MACRO1 -- subsume unshared load into mulF
11588 // This instruction does not round to 24-bits
11589 instruct mulF_reg_load1(regF dst, regF src, memory mem1 ) %{
11590 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11591 match(Set dst (MulF (LoadF mem1) src));
11592
11593 format %{ "FLD $mem1 ===MACRO1===\n\t"
11594 "FMUL ST,$src\n\t"
11595 "FSTP $dst" %}
11596 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or D8 /1 */ /* LoadF D9 /0 */
11597 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem1),
11598 OpcReg_F(src),
11599 Pop_Reg_F(dst) );
11600 ins_pipe( fpu_reg_reg_mem );
11601 %}
11602 //
11603 // MACRO2 -- addF a mulF which subsumed an unshared load
11604 // This instruction does not round to 24-bits
11605 instruct addF_mulF_reg_load1(regF dst, memory mem1, regF src1, regF src2) %{
11606 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11607 match(Set dst (AddF (MulF (LoadF mem1) src1) src2));
11608 ins_cost(95);
11609
11610 format %{ "FLD $mem1 ===MACRO2===\n\t"
11611 "FMUL ST,$src1 subsume mulF left load\n\t"
11612 "FADD ST,$src2\n\t"
11613 "FSTP $dst" %}
11614 opcode(0xD9); /* LoadF D9 /0 */
11615 ins_encode( OpcP, RMopc_Mem(0x00,mem1),
11616 FMul_ST_reg(src1),
11617 FAdd_ST_reg(src2),
11618 Pop_Reg_F(dst) );
11619 ins_pipe( fpu_reg_mem_reg_reg );
11620 %}
11621
11622 // MACRO3 -- addF a mulF
11623 // This instruction does not round to 24-bits. It is a '2-address'
11624 // instruction in that the result goes back to src2. This eliminates
11625 // a move from the macro; possibly the register allocator will have
11626 // to add it back (and maybe not).
11627 instruct addF_mulF_reg(regF src2, regF src1, regF src0) %{
11628 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11629 match(Set src2 (AddF (MulF src0 src1) src2));
11630
11631 format %{ "FLD $src0 ===MACRO3===\n\t"
11632 "FMUL ST,$src1\n\t"
11633 "FADDP $src2,ST" %}
11634 opcode(0xD9); /* LoadF D9 /0 */
11635 ins_encode( Push_Reg_F(src0),
11636 FMul_ST_reg(src1),
11637 FAddP_reg_ST(src2) );
11638 ins_pipe( fpu_reg_reg_reg );
11639 %}
11640
11641 // MACRO4 -- divF subF
11642 // This instruction does not round to 24-bits
11643 instruct subF_divF_reg(regF dst, regF src1, regF src2, regF src3) %{
11644 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11645 match(Set dst (DivF (SubF src2 src1) src3));
11646
11647 format %{ "FLD $src2 ===MACRO4===\n\t"
11648 "FSUB ST,$src1\n\t"
11649 "FDIV ST,$src3\n\t"
11650 "FSTP $dst" %}
11651 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
11652 ins_encode( Push_Reg_F(src2),
11653 subF_divF_encode(src1,src3),
11654 Pop_Reg_F(dst) );
11655 ins_pipe( fpu_reg_reg_reg_reg );
11656 %}
11657
11658 // Spill to obtain 24-bit precision
11659 instruct divF24_reg(stackSlotF dst, regF src1, regF src2) %{
11660 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11661 match(Set dst (DivF src1 src2));
11662
11663 format %{ "FDIV $dst,$src1,$src2" %}
11664 opcode(0xD8, 0x6); /* D8 F0+i or DE /6*/
11665 ins_encode( Push_Reg_F(src1),
11666 OpcReg_F(src2),
11667 Pop_Mem_F(dst) );
11668 ins_pipe( fpu_mem_reg_reg );
11669 %}
11670 //
11671 // This instruction does not round to 24-bits
11672 instruct divF_reg(regF dst, regF src) %{
11673 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11674 match(Set dst (DivF dst src));
11675
11676 format %{ "FDIV $dst,$src" %}
11677 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
11678 ins_encode( Push_Reg_F(src),
11679 OpcP, RegOpc(dst) );
11680 ins_pipe( fpu_reg_reg );
11681 %}
11682
11683
11684 // Spill to obtain 24-bit precision
11685 instruct modF24_reg(stackSlotF dst, regF src1, regF src2, eAXRegI rax, eFlagsReg cr) %{
11686 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
11687 match(Set dst (ModF src1 src2));
11688 effect(KILL rax, KILL cr); // emitModD() uses EAX and EFLAGS
11689
11690 format %{ "FMOD $dst,$src1,$src2" %}
11691 ins_encode( Push_Reg_Mod_D(src1, src2),
11692 emitModD(),
11693 Push_Result_Mod_D(src2),
11694 Pop_Mem_F(dst));
11695 ins_pipe( pipe_slow );
11696 %}
11697 //
11698 // This instruction does not round to 24-bits
11699 instruct modF_reg(regF dst, regF src, eAXRegI rax, eFlagsReg cr) %{
11700 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
11701 match(Set dst (ModF dst src));
11702 effect(KILL rax, KILL cr); // emitModD() uses EAX and EFLAGS
11703
11704 format %{ "FMOD $dst,$src" %}
11705 ins_encode(Push_Reg_Mod_D(dst, src),
11706 emitModD(),
11707 Push_Result_Mod_D(src),
11708 Pop_Reg_F(dst));
11709 ins_pipe( pipe_slow );
11710 %}
11711
11712 instruct modX_reg(regX dst, regX src0, regX src1, eAXRegI rax, eFlagsReg cr) %{
11713 predicate(UseSSE>=1);
11714 match(Set dst (ModF src0 src1));
11715 effect(KILL rax, KILL cr);
11716 format %{ "SUB ESP,4\t # FMOD\n"
11717 "\tMOVSS [ESP+0],$src1\n"
11718 "\tFLD_S [ESP+0]\n"
11719 "\tMOVSS [ESP+0],$src0\n"
11720 "\tFLD_S [ESP+0]\n"
11721 "loop:\tFPREM\n"
11722 "\tFWAIT\n"
11723 "\tFNSTSW AX\n"
11724 "\tSAHF\n"
11725 "\tJP loop\n"
11726 "\tFSTP_S [ESP+0]\n"
11727 "\tMOVSS $dst,[ESP+0]\n"
11728 "\tADD ESP,4\n"
11729 "\tFSTP ST0\t # Restore FPU Stack"
11730 %}
11731 ins_cost(250);
11732 ins_encode( Push_ModX_encoding(src0, src1), emitModD(), Push_ResultX(dst,0x4), PopFPU);
11733 ins_pipe( pipe_slow );
11734 %}
11735
11736
11737 //----------Arithmetic Conversion Instructions---------------------------------
11738 // The conversions operations are all Alpha sorted. Please keep it that way!
11739
11740 instruct roundFloat_mem_reg(stackSlotF dst, regF src) %{
11741 predicate(UseSSE==0);
11742 match(Set dst (RoundFloat src));
11743 ins_cost(125);
11744 format %{ "FST_S $dst,$src\t# F-round" %}
11745 ins_encode( Pop_Mem_Reg_F(dst, src) );
11746 ins_pipe( fpu_mem_reg );
11747 %}
11748
11749 instruct roundDouble_mem_reg(stackSlotD dst, regD src) %{
11750 predicate(UseSSE<=1);
11751 match(Set dst (RoundDouble src));
11752 ins_cost(125);
11753 format %{ "FST_D $dst,$src\t# D-round" %}
11754 ins_encode( Pop_Mem_Reg_D(dst, src) );
11755 ins_pipe( fpu_mem_reg );
11756 %}
11757
11758 // Force rounding to 24-bit precision and 6-bit exponent
11759 instruct convD2F_reg(stackSlotF dst, regD src) %{
11760 predicate(UseSSE==0);
11761 match(Set dst (ConvD2F src));
11762 format %{ "FST_S $dst,$src\t# F-round" %}
11763 expand %{
11764 roundFloat_mem_reg(dst,src);
11765 %}
11766 %}
11767
11768 // Force rounding to 24-bit precision and 6-bit exponent
11769 instruct convD2X_reg(regX dst, regD src, eFlagsReg cr) %{
11770 predicate(UseSSE==1);
11771 match(Set dst (ConvD2F src));
11772 effect( KILL cr );
11773 format %{ "SUB ESP,4\n\t"
11774 "FST_S [ESP],$src\t# F-round\n\t"
11775 "MOVSS $dst,[ESP]\n\t"
11776 "ADD ESP,4" %}
11777 ins_encode( D2X_encoding(dst, src) );
11778 ins_pipe( pipe_slow );
11779 %}
11780
11781 // Force rounding double precision to single precision
11782 instruct convXD2X_reg(regX dst, regXD src) %{
11783 predicate(UseSSE>=2);
11784 match(Set dst (ConvD2F src));
11785 format %{ "CVTSD2SS $dst,$src\t# F-round" %}
11786 opcode(0xF2, 0x0F, 0x5A);
11787 ins_encode( OpcP, OpcS, Opcode(tertiary), RegReg(dst, src));
11788 ins_pipe( pipe_slow );
11789 %}
11790
11791 instruct convF2D_reg_reg(regD dst, regF src) %{
11792 predicate(UseSSE==0);
11793 match(Set dst (ConvF2D src));
11794 format %{ "FST_S $dst,$src\t# D-round" %}
11795 ins_encode( Pop_Reg_Reg_D(dst, src));
11796 ins_pipe( fpu_reg_reg );
11797 %}
11798
11799 instruct convF2D_reg(stackSlotD dst, regF src) %{
11800 predicate(UseSSE==1);
11801 match(Set dst (ConvF2D src));
11802 format %{ "FST_D $dst,$src\t# D-round" %}
11803 expand %{
11804 roundDouble_mem_reg(dst,src);
11805 %}
11806 %}
11807
11808 instruct convX2D_reg(regD dst, regX src, eFlagsReg cr) %{
11809 predicate(UseSSE==1);
11810 match(Set dst (ConvF2D src));
11811 effect( KILL cr );
11812 format %{ "SUB ESP,4\n\t"
11813 "MOVSS [ESP] $src\n\t"
11814 "FLD_S [ESP]\n\t"
11815 "ADD ESP,4\n\t"
11816 "FSTP $dst\t# D-round" %}
11817 ins_encode( X2D_encoding(dst, src), Pop_Reg_D(dst));
11818 ins_pipe( pipe_slow );
11819 %}
11820
11821 instruct convX2XD_reg(regXD dst, regX src) %{
11822 predicate(UseSSE>=2);
11823 match(Set dst (ConvF2D src));
11824 format %{ "CVTSS2SD $dst,$src\t# D-round" %}
11825 opcode(0xF3, 0x0F, 0x5A);
11826 ins_encode( OpcP, OpcS, Opcode(tertiary), RegReg(dst, src));
11827 ins_pipe( pipe_slow );
11828 %}
11829
11830 // Convert a double to an int. If the double is a NAN, stuff a zero in instead.
11831 instruct convD2I_reg_reg( eAXRegI dst, eDXRegI tmp, regD src, eFlagsReg cr ) %{
11832 predicate(UseSSE<=1);
11833 match(Set dst (ConvD2I src));
11834 effect( KILL tmp, KILL cr );
11835 format %{ "FLD $src\t# Convert double to int \n\t"
11836 "FLDCW trunc mode\n\t"
11837 "SUB ESP,4\n\t"
11838 "FISTp [ESP + #0]\n\t"
11839 "FLDCW std/24-bit mode\n\t"
11840 "POP EAX\n\t"
11841 "CMP EAX,0x80000000\n\t"
11842 "JNE,s fast\n\t"
11843 "FLD_D $src\n\t"
11844 "CALL d2i_wrapper\n"
11845 "fast:" %}
11846 ins_encode( Push_Reg_D(src), D2I_encoding(src) );
11847 ins_pipe( pipe_slow );
11848 %}
11849
11850 // Convert a double to an int. If the double is a NAN, stuff a zero in instead.
11851 instruct convXD2I_reg_reg( eAXRegI dst, eDXRegI tmp, regXD src, eFlagsReg cr ) %{
11852 predicate(UseSSE>=2);
11853 match(Set dst (ConvD2I src));
11854 effect( KILL tmp, KILL cr );
11855 format %{ "CVTTSD2SI $dst, $src\n\t"
11856 "CMP $dst,0x80000000\n\t"
11857 "JNE,s fast\n\t"
11858 "SUB ESP, 8\n\t"
11859 "MOVSD [ESP], $src\n\t"
11860 "FLD_D [ESP]\n\t"
11861 "ADD ESP, 8\n\t"
11862 "CALL d2i_wrapper\n"
11863 "fast:" %}
11864 opcode(0x1); // double-precision conversion
11865 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x2C), FX2I_encoding(src,dst));
11866 ins_pipe( pipe_slow );
11867 %}
11868
11869 instruct convD2L_reg_reg( eADXRegL dst, regD src, eFlagsReg cr ) %{
11870 predicate(UseSSE<=1);
11871 match(Set dst (ConvD2L src));
11872 effect( KILL cr );
11873 format %{ "FLD $src\t# Convert double to long\n\t"
11874 "FLDCW trunc mode\n\t"
11875 "SUB ESP,8\n\t"
11876 "FISTp [ESP + #0]\n\t"
11877 "FLDCW std/24-bit mode\n\t"
11878 "POP EAX\n\t"
11879 "POP EDX\n\t"
11880 "CMP EDX,0x80000000\n\t"
11881 "JNE,s fast\n\t"
11882 "TEST EAX,EAX\n\t"
11883 "JNE,s fast\n\t"
11884 "FLD $src\n\t"
11885 "CALL d2l_wrapper\n"
11886 "fast:" %}
11887 ins_encode( Push_Reg_D(src), D2L_encoding(src) );
11888 ins_pipe( pipe_slow );
11889 %}
11890
11891 // XMM lacks a float/double->long conversion, so use the old FPU stack.
11892 instruct convXD2L_reg_reg( eADXRegL dst, regXD src, eFlagsReg cr ) %{
11893 predicate (UseSSE>=2);
11894 match(Set dst (ConvD2L src));
11895 effect( KILL cr );
11896 format %{ "SUB ESP,8\t# Convert double to long\n\t"
11897 "MOVSD [ESP],$src\n\t"
11898 "FLD_D [ESP]\n\t"
11899 "FLDCW trunc mode\n\t"
11900 "FISTp [ESP + #0]\n\t"
11901 "FLDCW std/24-bit mode\n\t"
11902 "POP EAX\n\t"
11903 "POP EDX\n\t"
11904 "CMP EDX,0x80000000\n\t"
11905 "JNE,s fast\n\t"
11906 "TEST EAX,EAX\n\t"
11907 "JNE,s fast\n\t"
11908 "SUB ESP,8\n\t"
11909 "MOVSD [ESP],$src\n\t"
11910 "FLD_D [ESP]\n\t"
11911 "CALL d2l_wrapper\n"
11912 "fast:" %}
11913 ins_encode( XD2L_encoding(src) );
11914 ins_pipe( pipe_slow );
11915 %}
11916
11917 // Convert a double to an int. Java semantics require we do complex
11918 // manglations in the corner cases. So we set the rounding mode to
11919 // 'zero', store the darned double down as an int, and reset the
11920 // rounding mode to 'nearest'. The hardware stores a flag value down
11921 // if we would overflow or converted a NAN; we check for this and
11922 // and go the slow path if needed.
11923 instruct convF2I_reg_reg(eAXRegI dst, eDXRegI tmp, regF src, eFlagsReg cr ) %{
11924 predicate(UseSSE==0);
11925 match(Set dst (ConvF2I src));
11926 effect( KILL tmp, KILL cr );
11927 format %{ "FLD $src\t# Convert float to int \n\t"
11928 "FLDCW trunc mode\n\t"
11929 "SUB ESP,4\n\t"
11930 "FISTp [ESP + #0]\n\t"
11931 "FLDCW std/24-bit mode\n\t"
11932 "POP EAX\n\t"
11933 "CMP EAX,0x80000000\n\t"
11934 "JNE,s fast\n\t"
11935 "FLD $src\n\t"
11936 "CALL d2i_wrapper\n"
11937 "fast:" %}
11938 // D2I_encoding works for F2I
11939 ins_encode( Push_Reg_F(src), D2I_encoding(src) );
11940 ins_pipe( pipe_slow );
11941 %}
11942
11943 // Convert a float in xmm to an int reg.
11944 instruct convX2I_reg(eAXRegI dst, eDXRegI tmp, regX src, eFlagsReg cr ) %{
11945 predicate(UseSSE>=1);
11946 match(Set dst (ConvF2I src));
11947 effect( KILL tmp, KILL cr );
11948 format %{ "CVTTSS2SI $dst, $src\n\t"
11949 "CMP $dst,0x80000000\n\t"
11950 "JNE,s fast\n\t"
11951 "SUB ESP, 4\n\t"
11952 "MOVSS [ESP], $src\n\t"
11953 "FLD [ESP]\n\t"
11954 "ADD ESP, 4\n\t"
11955 "CALL d2i_wrapper\n"
11956 "fast:" %}
11957 opcode(0x0); // single-precision conversion
11958 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x2C), FX2I_encoding(src,dst));
11959 ins_pipe( pipe_slow );
11960 %}
11961
11962 instruct convF2L_reg_reg( eADXRegL dst, regF src, eFlagsReg cr ) %{
11963 predicate(UseSSE==0);
11964 match(Set dst (ConvF2L src));
11965 effect( KILL cr );
11966 format %{ "FLD $src\t# Convert float to long\n\t"
11967 "FLDCW trunc mode\n\t"
11968 "SUB ESP,8\n\t"
11969 "FISTp [ESP + #0]\n\t"
11970 "FLDCW std/24-bit mode\n\t"
11971 "POP EAX\n\t"
11972 "POP EDX\n\t"
11973 "CMP EDX,0x80000000\n\t"
11974 "JNE,s fast\n\t"
11975 "TEST EAX,EAX\n\t"
11976 "JNE,s fast\n\t"
11977 "FLD $src\n\t"
11978 "CALL d2l_wrapper\n"
11979 "fast:" %}
11980 // D2L_encoding works for F2L
11981 ins_encode( Push_Reg_F(src), D2L_encoding(src) );
11982 ins_pipe( pipe_slow );
11983 %}
11984
11985 // XMM lacks a float/double->long conversion, so use the old FPU stack.
11986 instruct convX2L_reg_reg( eADXRegL dst, regX src, eFlagsReg cr ) %{
11987 predicate (UseSSE>=1);
11988 match(Set dst (ConvF2L src));
11989 effect( KILL cr );
11990 format %{ "SUB ESP,8\t# Convert float to long\n\t"
11991 "MOVSS [ESP],$src\n\t"
11992 "FLD_S [ESP]\n\t"
11993 "FLDCW trunc mode\n\t"
11994 "FISTp [ESP + #0]\n\t"
11995 "FLDCW std/24-bit mode\n\t"
11996 "POP EAX\n\t"
11997 "POP EDX\n\t"
11998 "CMP EDX,0x80000000\n\t"
11999 "JNE,s fast\n\t"
12000 "TEST EAX,EAX\n\t"
12001 "JNE,s fast\n\t"
12002 "SUB ESP,4\t# Convert float to long\n\t"
12003 "MOVSS [ESP],$src\n\t"
12004 "FLD_S [ESP]\n\t"
12005 "ADD ESP,4\n\t"
12006 "CALL d2l_wrapper\n"
12007 "fast:" %}
12008 ins_encode( X2L_encoding(src) );
12009 ins_pipe( pipe_slow );
12010 %}
12011
12012 instruct convI2D_reg(regD dst, stackSlotI src) %{
12013 predicate( UseSSE<=1 );
12014 match(Set dst (ConvI2D src));
12015 format %{ "FILD $src\n\t"
12016 "FSTP $dst" %}
12017 opcode(0xDB, 0x0); /* DB /0 */
12018 ins_encode(Push_Mem_I(src), Pop_Reg_D(dst));
12019 ins_pipe( fpu_reg_mem );
12020 %}
12021
12022 instruct convI2XD_reg(regXD dst, eRegI src) %{
12023 predicate( UseSSE>=2 && !UseXmmI2D );
12024 match(Set dst (ConvI2D src));
12025 format %{ "CVTSI2SD $dst,$src" %}
12026 opcode(0xF2, 0x0F, 0x2A);
12027 ins_encode( OpcP, OpcS, Opcode(tertiary), RegReg(dst, src));
12028 ins_pipe( pipe_slow );
12029 %}
12030
12031 instruct convI2XD_mem(regXD dst, memory mem) %{
12032 predicate( UseSSE>=2 );
12033 match(Set dst (ConvI2D (LoadI mem)));
12034 format %{ "CVTSI2SD $dst,$mem" %}
12035 opcode(0xF2, 0x0F, 0x2A);
12036 ins_encode( OpcP, OpcS, Opcode(tertiary), RegMem(dst, mem));
12037 ins_pipe( pipe_slow );
12038 %}
12039
12040 instruct convXI2XD_reg(regXD dst, eRegI src)
12041 %{
12042 predicate( UseSSE>=2 && UseXmmI2D );
12043 match(Set dst (ConvI2D src));
12044
12045 format %{ "MOVD $dst,$src\n\t"
12046 "CVTDQ2PD $dst,$dst\t# i2d" %}
12047 ins_encode %{
12048 __ movdl($dst$$XMMRegister, $src$$Register);
12049 __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister);
12050 %}
12051 ins_pipe(pipe_slow); // XXX
12052 %}
12053
12054 instruct convI2D_mem(regD dst, memory mem) %{
12055 predicate( UseSSE<=1 && !Compile::current()->select_24_bit_instr());
12056 match(Set dst (ConvI2D (LoadI mem)));
12057 format %{ "FILD $mem\n\t"
12058 "FSTP $dst" %}
12059 opcode(0xDB); /* DB /0 */
12060 ins_encode( OpcP, RMopc_Mem(0x00,mem),
12061 Pop_Reg_D(dst));
12062 ins_pipe( fpu_reg_mem );
12063 %}
12064
12065 // Convert a byte to a float; no rounding step needed.
12066 instruct conv24I2F_reg(regF dst, stackSlotI src) %{
12067 predicate( UseSSE==0 && n->in(1)->Opcode() == Op_AndI && n->in(1)->in(2)->is_Con() && n->in(1)->in(2)->get_int() == 255 );
12068 match(Set dst (ConvI2F src));
12069 format %{ "FILD $src\n\t"
12070 "FSTP $dst" %}
12071
12072 opcode(0xDB, 0x0); /* DB /0 */
12073 ins_encode(Push_Mem_I(src), Pop_Reg_F(dst));
12074 ins_pipe( fpu_reg_mem );
12075 %}
12076
12077 // In 24-bit mode, force exponent rounding by storing back out
12078 instruct convI2F_SSF(stackSlotF dst, stackSlotI src) %{
12079 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
12080 match(Set dst (ConvI2F src));
12081 ins_cost(200);
12082 format %{ "FILD $src\n\t"
12083 "FSTP_S $dst" %}
12084 opcode(0xDB, 0x0); /* DB /0 */
12085 ins_encode( Push_Mem_I(src),
12086 Pop_Mem_F(dst));
12087 ins_pipe( fpu_mem_mem );
12088 %}
12089
12090 // In 24-bit mode, force exponent rounding by storing back out
12091 instruct convI2F_SSF_mem(stackSlotF dst, memory mem) %{
12092 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
12093 match(Set dst (ConvI2F (LoadI mem)));
12094 ins_cost(200);
12095 format %{ "FILD $mem\n\t"
12096 "FSTP_S $dst" %}
12097 opcode(0xDB); /* DB /0 */
12098 ins_encode( OpcP, RMopc_Mem(0x00,mem),
12099 Pop_Mem_F(dst));
12100 ins_pipe( fpu_mem_mem );
12101 %}
12102
12103 // This instruction does not round to 24-bits
12104 instruct convI2F_reg(regF dst, stackSlotI src) %{
12105 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
12106 match(Set dst (ConvI2F src));
12107 format %{ "FILD $src\n\t"
12108 "FSTP $dst" %}
12109 opcode(0xDB, 0x0); /* DB /0 */
12110 ins_encode( Push_Mem_I(src),
12111 Pop_Reg_F(dst));
12112 ins_pipe( fpu_reg_mem );
12113 %}
12114
12115 // This instruction does not round to 24-bits
12116 instruct convI2F_mem(regF dst, memory mem) %{
12117 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
12118 match(Set dst (ConvI2F (LoadI mem)));
12119 format %{ "FILD $mem\n\t"
12120 "FSTP $dst" %}
12121 opcode(0xDB); /* DB /0 */
12122 ins_encode( OpcP, RMopc_Mem(0x00,mem),
12123 Pop_Reg_F(dst));
12124 ins_pipe( fpu_reg_mem );
12125 %}
12126
12127 // Convert an int to a float in xmm; no rounding step needed.
12128 instruct convI2X_reg(regX dst, eRegI src) %{
12129 predicate( UseSSE==1 || UseSSE>=2 && !UseXmmI2F );
12130 match(Set dst (ConvI2F src));
12131 format %{ "CVTSI2SS $dst, $src" %}
12132
12133 opcode(0xF3, 0x0F, 0x2A); /* F3 0F 2A /r */
12134 ins_encode( OpcP, OpcS, Opcode(tertiary), RegReg(dst, src));
12135 ins_pipe( pipe_slow );
12136 %}
12137
12138 instruct convXI2X_reg(regX dst, eRegI src)
12139 %{
12140 predicate( UseSSE>=2 && UseXmmI2F );
12141 match(Set dst (ConvI2F src));
12142
12143 format %{ "MOVD $dst,$src\n\t"
12144 "CVTDQ2PS $dst,$dst\t# i2f" %}
12145 ins_encode %{
12146 __ movdl($dst$$XMMRegister, $src$$Register);
12147 __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister);
12148 %}
12149 ins_pipe(pipe_slow); // XXX
12150 %}
12151
12152 instruct convI2L_reg( eRegL dst, eRegI src, eFlagsReg cr) %{
12153 match(Set dst (ConvI2L src));
12154 effect(KILL cr);
12155 ins_cost(375);
12156 format %{ "MOV $dst.lo,$src\n\t"
12157 "MOV $dst.hi,$src\n\t"
12158 "SAR $dst.hi,31" %}
12159 ins_encode(convert_int_long(dst,src));
12160 ins_pipe( ialu_reg_reg_long );
12161 %}
12162
12163 // Zero-extend convert int to long
12164 instruct convI2L_reg_zex(eRegL dst, eRegI src, immL_32bits mask, eFlagsReg flags ) %{
12165 match(Set dst (AndL (ConvI2L src) mask) );
12166 effect( KILL flags );
12167 ins_cost(250);
12168 format %{ "MOV $dst.lo,$src\n\t"
12169 "XOR $dst.hi,$dst.hi" %}
12170 opcode(0x33); // XOR
12171 ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) );
12172 ins_pipe( ialu_reg_reg_long );
12173 %}
12174
12175 // Zero-extend long
12176 instruct zerox_long(eRegL dst, eRegL src, immL_32bits mask, eFlagsReg flags ) %{
12177 match(Set dst (AndL src mask) );
12178 effect( KILL flags );
12179 ins_cost(250);
12180 format %{ "MOV $dst.lo,$src.lo\n\t"
12181 "XOR $dst.hi,$dst.hi\n\t" %}
12182 opcode(0x33); // XOR
12183 ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) );
12184 ins_pipe( ialu_reg_reg_long );
12185 %}
12186
12187 instruct convL2D_reg( stackSlotD dst, eRegL src, eFlagsReg cr) %{
12188 predicate (UseSSE<=1);
12189 match(Set dst (ConvL2D src));
12190 effect( KILL cr );
12191 format %{ "PUSH $src.hi\t# Convert long to double\n\t"
12192 "PUSH $src.lo\n\t"
12193 "FILD ST,[ESP + #0]\n\t"
12194 "ADD ESP,8\n\t"
12195 "FSTP_D $dst\t# D-round" %}
12196 opcode(0xDF, 0x5); /* DF /5 */
12197 ins_encode(convert_long_double(src), Pop_Mem_D(dst));
12198 ins_pipe( pipe_slow );
12199 %}
12200
12201 instruct convL2XD_reg( regXD dst, eRegL src, eFlagsReg cr) %{
12202 predicate (UseSSE>=2);
12203 match(Set dst (ConvL2D src));
12204 effect( KILL cr );
12205 format %{ "PUSH $src.hi\t# Convert long to double\n\t"
12206 "PUSH $src.lo\n\t"
12207 "FILD_D [ESP]\n\t"
12208 "FSTP_D [ESP]\n\t"
12209 "MOVSD $dst,[ESP]\n\t"
12210 "ADD ESP,8" %}
12211 opcode(0xDF, 0x5); /* DF /5 */
12212 ins_encode(convert_long_double2(src), Push_ResultXD(dst));
12213 ins_pipe( pipe_slow );
12214 %}
12215
12216 instruct convL2X_reg( regX dst, eRegL src, eFlagsReg cr) %{
12217 predicate (UseSSE>=1);
12218 match(Set dst (ConvL2F src));
12219 effect( KILL cr );
12220 format %{ "PUSH $src.hi\t# Convert long to single float\n\t"
12221 "PUSH $src.lo\n\t"
12222 "FILD_D [ESP]\n\t"
12223 "FSTP_S [ESP]\n\t"
12224 "MOVSS $dst,[ESP]\n\t"
12225 "ADD ESP,8" %}
12226 opcode(0xDF, 0x5); /* DF /5 */
12227 ins_encode(convert_long_double2(src), Push_ResultX(dst,0x8));
12228 ins_pipe( pipe_slow );
12229 %}
12230
12231 instruct convL2F_reg( stackSlotF dst, eRegL src, eFlagsReg cr) %{
12232 match(Set dst (ConvL2F src));
12233 effect( KILL cr );
12234 format %{ "PUSH $src.hi\t# Convert long to single float\n\t"
12235 "PUSH $src.lo\n\t"
12236 "FILD ST,[ESP + #0]\n\t"
12237 "ADD ESP,8\n\t"
12238 "FSTP_S $dst\t# F-round" %}
12239 opcode(0xDF, 0x5); /* DF /5 */
12240 ins_encode(convert_long_double(src), Pop_Mem_F(dst));
12241 ins_pipe( pipe_slow );
12242 %}
12243
12244 instruct convL2I_reg( eRegI dst, eRegL src ) %{
12245 match(Set dst (ConvL2I src));
12246 effect( DEF dst, USE src );
12247 format %{ "MOV $dst,$src.lo" %}
12248 ins_encode(enc_CopyL_Lo(dst,src));
12249 ins_pipe( ialu_reg_reg );
12250 %}
12251
12252
12253 instruct MoveF2I_stack_reg(eRegI dst, stackSlotF src) %{
12254 match(Set dst (MoveF2I src));
12255 effect( DEF dst, USE src );
12256 ins_cost(100);
12257 format %{ "MOV $dst,$src\t# MoveF2I_stack_reg" %}
12258 opcode(0x8B);
12259 ins_encode( OpcP, RegMem(dst,src));
12260 ins_pipe( ialu_reg_mem );
12261 %}
12262
12263 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{
12264 predicate(UseSSE==0);
12265 match(Set dst (MoveF2I src));
12266 effect( DEF dst, USE src );
12267
12268 ins_cost(125);
12269 format %{ "FST_S $dst,$src\t# MoveF2I_reg_stack" %}
12270 ins_encode( Pop_Mem_Reg_F(dst, src) );
12271 ins_pipe( fpu_mem_reg );
12272 %}
12273
12274 instruct MoveF2I_reg_stack_sse(stackSlotI dst, regX src) %{
12275 predicate(UseSSE>=1);
12276 match(Set dst (MoveF2I src));
12277 effect( DEF dst, USE src );
12278
12279 ins_cost(95);
12280 format %{ "MOVSS $dst,$src\t# MoveF2I_reg_stack_sse" %}
12281 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x11), RegMem(src, dst));
12282 ins_pipe( pipe_slow );
12283 %}
12284
12285 instruct MoveF2I_reg_reg_sse(eRegI dst, regX src) %{
12286 predicate(UseSSE>=2);
12287 match(Set dst (MoveF2I src));
12288 effect( DEF dst, USE src );
12289 ins_cost(85);
12290 format %{ "MOVD $dst,$src\t# MoveF2I_reg_reg_sse" %}
12291 ins_encode( MovX2I_reg(dst, src));
12292 ins_pipe( pipe_slow );
12293 %}
12294
12295 instruct MoveI2F_reg_stack(stackSlotF dst, eRegI src) %{
12296 match(Set dst (MoveI2F src));
12297 effect( DEF dst, USE src );
12298
12299 ins_cost(100);
12300 format %{ "MOV $dst,$src\t# MoveI2F_reg_stack" %}
12301 opcode(0x89);
12302 ins_encode( OpcPRegSS( dst, src ) );
12303 ins_pipe( ialu_mem_reg );
12304 %}
12305
12306
12307 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
12308 predicate(UseSSE==0);
12309 match(Set dst (MoveI2F src));
12310 effect(DEF dst, USE src);
12311
12312 ins_cost(125);
12313 format %{ "FLD_S $src\n\t"
12314 "FSTP $dst\t# MoveI2F_stack_reg" %}
12315 opcode(0xD9); /* D9 /0, FLD m32real */
12316 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
12317 Pop_Reg_F(dst) );
12318 ins_pipe( fpu_reg_mem );
12319 %}
12320
12321 instruct MoveI2F_stack_reg_sse(regX dst, stackSlotI src) %{
12322 predicate(UseSSE>=1);
12323 match(Set dst (MoveI2F src));
12324 effect( DEF dst, USE src );
12325
12326 ins_cost(95);
12327 format %{ "MOVSS $dst,$src\t# MoveI2F_stack_reg_sse" %}
12328 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x10), RegMem(dst,src));
12329 ins_pipe( pipe_slow );
12330 %}
12331
12332 instruct MoveI2F_reg_reg_sse(regX dst, eRegI src) %{
12333 predicate(UseSSE>=2);
12334 match(Set dst (MoveI2F src));
12335 effect( DEF dst, USE src );
12336
12337 ins_cost(85);
12338 format %{ "MOVD $dst,$src\t# MoveI2F_reg_reg_sse" %}
12339 ins_encode( MovI2X_reg(dst, src) );
12340 ins_pipe( pipe_slow );
12341 %}
12342
12343 instruct MoveD2L_stack_reg(eRegL dst, stackSlotD src) %{
12344 match(Set dst (MoveD2L src));
12345 effect(DEF dst, USE src);
12346
12347 ins_cost(250);
12348 format %{ "MOV $dst.lo,$src\n\t"
12349 "MOV $dst.hi,$src+4\t# MoveD2L_stack_reg" %}
12350 opcode(0x8B, 0x8B);
12351 ins_encode( OpcP, RegMem(dst,src), OpcS, RegMem_Hi(dst,src));
12352 ins_pipe( ialu_mem_long_reg );
12353 %}
12354
12355 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
12356 predicate(UseSSE<=1);
12357 match(Set dst (MoveD2L src));
12358 effect(DEF dst, USE src);
12359
12360 ins_cost(125);
12361 format %{ "FST_D $dst,$src\t# MoveD2L_reg_stack" %}
12362 ins_encode( Pop_Mem_Reg_D(dst, src) );
12363 ins_pipe( fpu_mem_reg );
12364 %}
12365
12366 instruct MoveD2L_reg_stack_sse(stackSlotL dst, regXD src) %{
12367 predicate(UseSSE>=2);
12368 match(Set dst (MoveD2L src));
12369 effect(DEF dst, USE src);
12370 ins_cost(95);
12371
12372 format %{ "MOVSD $dst,$src\t# MoveD2L_reg_stack_sse" %}
12373 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x11), RegMem(src,dst));
12374 ins_pipe( pipe_slow );
12375 %}
12376
12377 instruct MoveD2L_reg_reg_sse(eRegL dst, regXD src, regXD tmp) %{
12378 predicate(UseSSE>=2);
12379 match(Set dst (MoveD2L src));
12380 effect(DEF dst, USE src, TEMP tmp);
12381 ins_cost(85);
12382 format %{ "MOVD $dst.lo,$src\n\t"
12383 "PSHUFLW $tmp,$src,0x4E\n\t"
12384 "MOVD $dst.hi,$tmp\t# MoveD2L_reg_reg_sse" %}
12385 ins_encode( MovXD2L_reg(dst, src, tmp) );
12386 ins_pipe( pipe_slow );
12387 %}
12388
12389 instruct MoveL2D_reg_stack(stackSlotD dst, eRegL src) %{
12390 match(Set dst (MoveL2D src));
12391 effect(DEF dst, USE src);
12392
12393 ins_cost(200);
12394 format %{ "MOV $dst,$src.lo\n\t"
12395 "MOV $dst+4,$src.hi\t# MoveL2D_reg_stack" %}
12396 opcode(0x89, 0x89);
12397 ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) );
12398 ins_pipe( ialu_mem_long_reg );
12399 %}
12400
12401
12402 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
12403 predicate(UseSSE<=1);
12404 match(Set dst (MoveL2D src));
12405 effect(DEF dst, USE src);
12406 ins_cost(125);
12407
12408 format %{ "FLD_D $src\n\t"
12409 "FSTP $dst\t# MoveL2D_stack_reg" %}
12410 opcode(0xDD); /* DD /0, FLD m64real */
12411 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
12412 Pop_Reg_D(dst) );
12413 ins_pipe( fpu_reg_mem );
12414 %}
12415
12416
12417 instruct MoveL2D_stack_reg_sse(regXD dst, stackSlotL src) %{
12418 predicate(UseSSE>=2 && UseXmmLoadAndClearUpper);
12419 match(Set dst (MoveL2D src));
12420 effect(DEF dst, USE src);
12421
12422 ins_cost(95);
12423 format %{ "MOVSD $dst,$src\t# MoveL2D_stack_reg_sse" %}
12424 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x10), RegMem(dst,src));
12425 ins_pipe( pipe_slow );
12426 %}
12427
12428 instruct MoveL2D_stack_reg_sse_partial(regXD dst, stackSlotL src) %{
12429 predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper);
12430 match(Set dst (MoveL2D src));
12431 effect(DEF dst, USE src);
12432
12433 ins_cost(95);
12434 format %{ "MOVLPD $dst,$src\t# MoveL2D_stack_reg_sse" %}
12435 ins_encode( Opcode(0x66), Opcode(0x0F), Opcode(0x12), RegMem(dst,src));
12436 ins_pipe( pipe_slow );
12437 %}
12438
12439 instruct MoveL2D_reg_reg_sse(regXD dst, eRegL src, regXD tmp) %{
12440 predicate(UseSSE>=2);
12441 match(Set dst (MoveL2D src));
12442 effect(TEMP dst, USE src, TEMP tmp);
12443 ins_cost(85);
12444 format %{ "MOVD $dst,$src.lo\n\t"
12445 "MOVD $tmp,$src.hi\n\t"
12446 "PUNPCKLDQ $dst,$tmp\t# MoveL2D_reg_reg_sse" %}
12447 ins_encode( MovL2XD_reg(dst, src, tmp) );
12448 ins_pipe( pipe_slow );
12449 %}
12450
12451 // Replicate scalar to packed byte (1 byte) values in xmm
12452 instruct Repl8B_reg(regXD dst, regXD src) %{
12453 predicate(UseSSE>=2);
12454 match(Set dst (Replicate8B src));
12455 format %{ "MOVDQA $dst,$src\n\t"
12456 "PUNPCKLBW $dst,$dst\n\t"
12457 "PSHUFLW $dst,$dst,0x00\t! replicate8B" %}
12458 ins_encode( pshufd_8x8(dst, src));
12459 ins_pipe( pipe_slow );
12460 %}
12461
12462 // Replicate scalar to packed byte (1 byte) values in xmm
12463 instruct Repl8B_eRegI(regXD dst, eRegI src) %{
12464 predicate(UseSSE>=2);
12465 match(Set dst (Replicate8B src));
12466 format %{ "MOVD $dst,$src\n\t"
12467 "PUNPCKLBW $dst,$dst\n\t"
12468 "PSHUFLW $dst,$dst,0x00\t! replicate8B" %}
12469 ins_encode( mov_i2x(dst, src), pshufd_8x8(dst, dst));
12470 ins_pipe( pipe_slow );
12471 %}
12472
12473 // Replicate scalar zero to packed byte (1 byte) values in xmm
12474 instruct Repl8B_immI0(regXD dst, immI0 zero) %{
12475 predicate(UseSSE>=2);
12476 match(Set dst (Replicate8B zero));
12477 format %{ "PXOR $dst,$dst\t! replicate8B" %}
12478 ins_encode( pxor(dst, dst));
12479 ins_pipe( fpu_reg_reg );
12480 %}
12481
12482 // Replicate scalar to packed shore (2 byte) values in xmm
12483 instruct Repl4S_reg(regXD dst, regXD src) %{
12484 predicate(UseSSE>=2);
12485 match(Set dst (Replicate4S src));
12486 format %{ "PSHUFLW $dst,$src,0x00\t! replicate4S" %}
12487 ins_encode( pshufd_4x16(dst, src));
12488 ins_pipe( fpu_reg_reg );
12489 %}
12490
12491 // Replicate scalar to packed shore (2 byte) values in xmm
12492 instruct Repl4S_eRegI(regXD dst, eRegI src) %{
12493 predicate(UseSSE>=2);
12494 match(Set dst (Replicate4S src));
12495 format %{ "MOVD $dst,$src\n\t"
12496 "PSHUFLW $dst,$dst,0x00\t! replicate4S" %}
12497 ins_encode( mov_i2x(dst, src), pshufd_4x16(dst, dst));
12498 ins_pipe( fpu_reg_reg );
12499 %}
12500
12501 // Replicate scalar zero to packed short (2 byte) values in xmm
12502 instruct Repl4S_immI0(regXD dst, immI0 zero) %{
12503 predicate(UseSSE>=2);
12504 match(Set dst (Replicate4S zero));
12505 format %{ "PXOR $dst,$dst\t! replicate4S" %}
12506 ins_encode( pxor(dst, dst));
12507 ins_pipe( fpu_reg_reg );
12508 %}
12509
12510 // Replicate scalar to packed char (2 byte) values in xmm
12511 instruct Repl4C_reg(regXD dst, regXD src) %{
12512 predicate(UseSSE>=2);
12513 match(Set dst (Replicate4C src));
12514 format %{ "PSHUFLW $dst,$src,0x00\t! replicate4C" %}
12515 ins_encode( pshufd_4x16(dst, src));
12516 ins_pipe( fpu_reg_reg );
12517 %}
12518
12519 // Replicate scalar to packed char (2 byte) values in xmm
12520 instruct Repl4C_eRegI(regXD dst, eRegI src) %{
12521 predicate(UseSSE>=2);
12522 match(Set dst (Replicate4C src));
12523 format %{ "MOVD $dst,$src\n\t"
12524 "PSHUFLW $dst,$dst,0x00\t! replicate4C" %}
12525 ins_encode( mov_i2x(dst, src), pshufd_4x16(dst, dst));
12526 ins_pipe( fpu_reg_reg );
12527 %}
12528
12529 // Replicate scalar zero to packed char (2 byte) values in xmm
12530 instruct Repl4C_immI0(regXD dst, immI0 zero) %{
12531 predicate(UseSSE>=2);
12532 match(Set dst (Replicate4C zero));
12533 format %{ "PXOR $dst,$dst\t! replicate4C" %}
12534 ins_encode( pxor(dst, dst));
12535 ins_pipe( fpu_reg_reg );
12536 %}
12537
12538 // Replicate scalar to packed integer (4 byte) values in xmm
12539 instruct Repl2I_reg(regXD dst, regXD src) %{
12540 predicate(UseSSE>=2);
12541 match(Set dst (Replicate2I src));
12542 format %{ "PSHUFD $dst,$src,0x00\t! replicate2I" %}
12543 ins_encode( pshufd(dst, src, 0x00));
12544 ins_pipe( fpu_reg_reg );
12545 %}
12546
12547 // Replicate scalar to packed integer (4 byte) values in xmm
12548 instruct Repl2I_eRegI(regXD dst, eRegI src) %{
12549 predicate(UseSSE>=2);
12550 match(Set dst (Replicate2I src));
12551 format %{ "MOVD $dst,$src\n\t"
12552 "PSHUFD $dst,$dst,0x00\t! replicate2I" %}
12553 ins_encode( mov_i2x(dst, src), pshufd(dst, dst, 0x00));
12554 ins_pipe( fpu_reg_reg );
12555 %}
12556
12557 // Replicate scalar zero to packed integer (2 byte) values in xmm
12558 instruct Repl2I_immI0(regXD dst, immI0 zero) %{
12559 predicate(UseSSE>=2);
12560 match(Set dst (Replicate2I zero));
12561 format %{ "PXOR $dst,$dst\t! replicate2I" %}
12562 ins_encode( pxor(dst, dst));
12563 ins_pipe( fpu_reg_reg );
12564 %}
12565
12566 // Replicate scalar to packed single precision floating point values in xmm
12567 instruct Repl2F_reg(regXD dst, regXD src) %{
12568 predicate(UseSSE>=2);
12569 match(Set dst (Replicate2F src));
12570 format %{ "PSHUFD $dst,$src,0xe0\t! replicate2F" %}
12571 ins_encode( pshufd(dst, src, 0xe0));
12572 ins_pipe( fpu_reg_reg );
12573 %}
12574
12575 // Replicate scalar to packed single precision floating point values in xmm
12576 instruct Repl2F_regX(regXD dst, regX src) %{
12577 predicate(UseSSE>=2);
12578 match(Set dst (Replicate2F src));
12579 format %{ "PSHUFD $dst,$src,0xe0\t! replicate2F" %}
12580 ins_encode( pshufd(dst, src, 0xe0));
12581 ins_pipe( fpu_reg_reg );
12582 %}
12583
12584 // Replicate scalar to packed single precision floating point values in xmm
12585 instruct Repl2F_immXF0(regXD dst, immXF0 zero) %{
12586 predicate(UseSSE>=2);
12587 match(Set dst (Replicate2F zero));
12588 format %{ "PXOR $dst,$dst\t! replicate2F" %}
12589 ins_encode( pxor(dst, dst));
12590 ins_pipe( fpu_reg_reg );
12591 %}
12592
12593 // =======================================================================
12594 // fast clearing of an array
12595 instruct rep_stos(eCXRegI cnt, eDIRegP base, eAXRegI zero, Universe dummy, eFlagsReg cr) %{
12596 match(Set dummy (ClearArray cnt base));
12597 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr);
12598 format %{ "SHL ECX,1\t# Convert doublewords to words\n\t"
12599 "XOR EAX,EAX\n\t"
12600 "REP STOS\t# store EAX into [EDI++] while ECX--" %}
12601 opcode(0,0x4);
12602 ins_encode( Opcode(0xD1), RegOpc(ECX),
12603 OpcRegReg(0x33,EAX,EAX),
12604 Opcode(0xF3), Opcode(0xAB) );
12605 ins_pipe( pipe_slow );
12606 %}
12607
12608 instruct string_compare(eDIRegP str1, eSIRegP str2, regXD tmp1, regXD tmp2,
12609 eAXRegI tmp3, eBXRegI tmp4, eCXRegI result, eFlagsReg cr) %{
12610 match(Set result (StrComp str1 str2));
12611 effect(TEMP tmp1, TEMP tmp2, USE_KILL str1, USE_KILL str2, KILL tmp3, KILL tmp4, KILL cr);
12612 //ins_cost(300);
12613
12614 format %{ "String Compare $str1,$str2 -> $result // KILL EAX, EBX" %}
12615 ins_encode( enc_String_Compare(str1, str2, tmp1, tmp2, tmp3, tmp4, result) );
12616 ins_pipe( pipe_slow );
12617 %}
12618
12619 // fast string equals
12620 instruct string_equals(eDIRegP str1, eSIRegP str2, regXD tmp1, regXD tmp2,
12621 eBXRegI tmp3, eCXRegI tmp4, eAXRegI result, eFlagsReg cr) %{
12622 match(Set result (StrEquals str1 str2));
12623 effect(TEMP tmp1, TEMP tmp2, USE_KILL str1, USE_KILL str2, KILL tmp3, KILL tmp4, KILL cr);
12624
12625 format %{ "String Equals $str1,$str2 -> $result // KILL EBX, ECX" %}
12626 ins_encode( enc_String_Equals(tmp1, tmp2, str1, str2, tmp3, tmp4, result) );
12627 ins_pipe( pipe_slow );
12628 %}
12629
12630 instruct string_indexof(eSIRegP str1, eDIRegP str2, regXD tmp1, eAXRegI tmp2,
12631 eCXRegI tmp3, eDXRegI tmp4, eBXRegI result, eFlagsReg cr) %{
12632 predicate(UseSSE42Intrinsics);
12633 match(Set result (StrIndexOf str1 str2));
12634 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, KILL tmp2, KILL tmp3, KILL tmp4, KILL cr);
12635
12636 format %{ "String IndexOf $str1,$str2 -> $result // KILL EAX, ECX, EDX" %}
12637 ins_encode( enc_String_IndexOf(str1, str2, tmp1, tmp2, tmp3, tmp4, result) );
12638 ins_pipe( pipe_slow );
12639 %}
12640
12641 // fast array equals
12642 instruct array_equals(eDIRegP ary1, eSIRegP ary2, regXD tmp1, regXD tmp2, eBXRegI tmp3,
12643 eDXRegI tmp4, eAXRegI result, eFlagsReg cr) %{
12644 match(Set result (AryEq ary1 ary2));
12645 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
12646 //ins_cost(300);
12647
12648 format %{ "Array Equals $ary1,$ary2 -> $result // KILL EBX, EDX" %}
12649 ins_encode( enc_Array_Equals(ary1, ary2, tmp1, tmp2, tmp3, tmp4, result) );
12650 ins_pipe( pipe_slow );
12651 %}
12652
12653 //----------Control Flow Instructions------------------------------------------
12654 // Signed compare Instructions
12655 instruct compI_eReg(eFlagsReg cr, eRegI op1, eRegI op2) %{
12656 match(Set cr (CmpI op1 op2));
12657 effect( DEF cr, USE op1, USE op2 );
12658 format %{ "CMP $op1,$op2" %}
12659 opcode(0x3B); /* Opcode 3B /r */
12660 ins_encode( OpcP, RegReg( op1, op2) );
12661 ins_pipe( ialu_cr_reg_reg );
12662 %}
12663
12664 instruct compI_eReg_imm(eFlagsReg cr, eRegI op1, immI op2) %{
12665 match(Set cr (CmpI op1 op2));
12666 effect( DEF cr, USE op1 );
12667 format %{ "CMP $op1,$op2" %}
12668 opcode(0x81,0x07); /* Opcode 81 /7 */
12669 // ins_encode( RegImm( op1, op2) ); /* Was CmpImm */
12670 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
12671 ins_pipe( ialu_cr_reg_imm );
12672 %}
12673
12674 // Cisc-spilled version of cmpI_eReg
12675 instruct compI_eReg_mem(eFlagsReg cr, eRegI op1, memory op2) %{
12676 match(Set cr (CmpI op1 (LoadI op2)));
12677
12678 format %{ "CMP $op1,$op2" %}
12679 ins_cost(500);
12680 opcode(0x3B); /* Opcode 3B /r */
12681 ins_encode( OpcP, RegMem( op1, op2) );
12682 ins_pipe( ialu_cr_reg_mem );
12683 %}
12684
12685 instruct testI_reg( eFlagsReg cr, eRegI src, immI0 zero ) %{
12686 match(Set cr (CmpI src zero));
12687 effect( DEF cr, USE src );
12688
12689 format %{ "TEST $src,$src" %}
12690 opcode(0x85);
12691 ins_encode( OpcP, RegReg( src, src ) );
12692 ins_pipe( ialu_cr_reg_imm );
12693 %}
12694
12695 instruct testI_reg_imm( eFlagsReg cr, eRegI src, immI con, immI0 zero ) %{
12696 match(Set cr (CmpI (AndI src con) zero));
12697
12698 format %{ "TEST $src,$con" %}
12699 opcode(0xF7,0x00);
12700 ins_encode( OpcP, RegOpc(src), Con32(con) );
12701 ins_pipe( ialu_cr_reg_imm );
12702 %}
12703
12704 instruct testI_reg_mem( eFlagsReg cr, eRegI src, memory mem, immI0 zero ) %{
12705 match(Set cr (CmpI (AndI src mem) zero));
12706
12707 format %{ "TEST $src,$mem" %}
12708 opcode(0x85);
12709 ins_encode( OpcP, RegMem( src, mem ) );
12710 ins_pipe( ialu_cr_reg_mem );
12711 %}
12712
12713 // Unsigned compare Instructions; really, same as signed except they
12714 // produce an eFlagsRegU instead of eFlagsReg.
12715 instruct compU_eReg(eFlagsRegU cr, eRegI op1, eRegI op2) %{
12716 match(Set cr (CmpU op1 op2));
12717
12718 format %{ "CMPu $op1,$op2" %}
12719 opcode(0x3B); /* Opcode 3B /r */
12720 ins_encode( OpcP, RegReg( op1, op2) );
12721 ins_pipe( ialu_cr_reg_reg );
12722 %}
12723
12724 instruct compU_eReg_imm(eFlagsRegU cr, eRegI op1, immI op2) %{
12725 match(Set cr (CmpU op1 op2));
12726
12727 format %{ "CMPu $op1,$op2" %}
12728 opcode(0x81,0x07); /* Opcode 81 /7 */
12729 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
12730 ins_pipe( ialu_cr_reg_imm );
12731 %}
12732
12733 // // Cisc-spilled version of cmpU_eReg
12734 instruct compU_eReg_mem(eFlagsRegU cr, eRegI op1, memory op2) %{
12735 match(Set cr (CmpU op1 (LoadI op2)));
12736
12737 format %{ "CMPu $op1,$op2" %}
12738 ins_cost(500);
12739 opcode(0x3B); /* Opcode 3B /r */
12740 ins_encode( OpcP, RegMem( op1, op2) );
12741 ins_pipe( ialu_cr_reg_mem );
12742 %}
12743
12744 // // Cisc-spilled version of cmpU_eReg
12745 //instruct compU_mem_eReg(eFlagsRegU cr, memory op1, eRegI op2) %{
12746 // match(Set cr (CmpU (LoadI op1) op2));
12747 //
12748 // format %{ "CMPu $op1,$op2" %}
12749 // ins_cost(500);
12750 // opcode(0x39); /* Opcode 39 /r */
12751 // ins_encode( OpcP, RegMem( op1, op2) );
12752 //%}
12753
12754 instruct testU_reg( eFlagsRegU cr, eRegI src, immI0 zero ) %{
12755 match(Set cr (CmpU src zero));
12756
12757 format %{ "TESTu $src,$src" %}
12758 opcode(0x85);
12759 ins_encode( OpcP, RegReg( src, src ) );
12760 ins_pipe( ialu_cr_reg_imm );
12761 %}
12762
12763 // Unsigned pointer compare Instructions
12764 instruct compP_eReg(eFlagsRegU cr, eRegP op1, eRegP op2) %{
12765 match(Set cr (CmpP op1 op2));
12766
12767 format %{ "CMPu $op1,$op2" %}
12768 opcode(0x3B); /* Opcode 3B /r */
12769 ins_encode( OpcP, RegReg( op1, op2) );
12770 ins_pipe( ialu_cr_reg_reg );
12771 %}
12772
12773 instruct compP_eReg_imm(eFlagsRegU cr, eRegP op1, immP op2) %{
12774 match(Set cr (CmpP op1 op2));
12775
12776 format %{ "CMPu $op1,$op2" %}
12777 opcode(0x81,0x07); /* Opcode 81 /7 */
12778 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
12779 ins_pipe( ialu_cr_reg_imm );
12780 %}
12781
12782 // // Cisc-spilled version of cmpP_eReg
12783 instruct compP_eReg_mem(eFlagsRegU cr, eRegP op1, memory op2) %{
12784 match(Set cr (CmpP op1 (LoadP op2)));
12785
12786 format %{ "CMPu $op1,$op2" %}
12787 ins_cost(500);
12788 opcode(0x3B); /* Opcode 3B /r */
12789 ins_encode( OpcP, RegMem( op1, op2) );
12790 ins_pipe( ialu_cr_reg_mem );
12791 %}
12792
12793 // // Cisc-spilled version of cmpP_eReg
12794 //instruct compP_mem_eReg(eFlagsRegU cr, memory op1, eRegP op2) %{
12795 // match(Set cr (CmpP (LoadP op1) op2));
12796 //
12797 // format %{ "CMPu $op1,$op2" %}
12798 // ins_cost(500);
12799 // opcode(0x39); /* Opcode 39 /r */
12800 // ins_encode( OpcP, RegMem( op1, op2) );
12801 //%}
12802
12803 // Compare raw pointer (used in out-of-heap check).
12804 // Only works because non-oop pointers must be raw pointers
12805 // and raw pointers have no anti-dependencies.
12806 instruct compP_mem_eReg( eFlagsRegU cr, eRegP op1, memory op2 ) %{
12807 predicate( !n->in(2)->in(2)->bottom_type()->isa_oop_ptr() );
12808 match(Set cr (CmpP op1 (LoadP op2)));
12809
12810 format %{ "CMPu $op1,$op2" %}
12811 opcode(0x3B); /* Opcode 3B /r */
12812 ins_encode( OpcP, RegMem( op1, op2) );
12813 ins_pipe( ialu_cr_reg_mem );
12814 %}
12815
12816 //
12817 // This will generate a signed flags result. This should be ok
12818 // since any compare to a zero should be eq/neq.
12819 instruct testP_reg( eFlagsReg cr, eRegP src, immP0 zero ) %{
12820 match(Set cr (CmpP src zero));
12821
12822 format %{ "TEST $src,$src" %}
12823 opcode(0x85);
12824 ins_encode( OpcP, RegReg( src, src ) );
12825 ins_pipe( ialu_cr_reg_imm );
12826 %}
12827
12828 // Cisc-spilled version of testP_reg
12829 // This will generate a signed flags result. This should be ok
12830 // since any compare to a zero should be eq/neq.
12831 instruct testP_Reg_mem( eFlagsReg cr, memory op, immI0 zero ) %{
12832 match(Set cr (CmpP (LoadP op) zero));
12833
12834 format %{ "TEST $op,0xFFFFFFFF" %}
12835 ins_cost(500);
12836 opcode(0xF7); /* Opcode F7 /0 */
12837 ins_encode( OpcP, RMopc_Mem(0x00,op), Con_d32(0xFFFFFFFF) );
12838 ins_pipe( ialu_cr_reg_imm );
12839 %}
12840
12841 // Yanked all unsigned pointer compare operations.
12842 // Pointer compares are done with CmpP which is already unsigned.
12843
12844 //----------Max and Min--------------------------------------------------------
12845 // Min Instructions
12846 ////
12847 // *** Min and Max using the conditional move are slower than the
12848 // *** branch version on a Pentium III.
12849 // // Conditional move for min
12850 //instruct cmovI_reg_lt( eRegI op2, eRegI op1, eFlagsReg cr ) %{
12851 // effect( USE_DEF op2, USE op1, USE cr );
12852 // format %{ "CMOVlt $op2,$op1\t! min" %}
12853 // opcode(0x4C,0x0F);
12854 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) );
12855 // ins_pipe( pipe_cmov_reg );
12856 //%}
12857 //
12858 //// Min Register with Register (P6 version)
12859 //instruct minI_eReg_p6( eRegI op1, eRegI op2 ) %{
12860 // predicate(VM_Version::supports_cmov() );
12861 // match(Set op2 (MinI op1 op2));
12862 // ins_cost(200);
12863 // expand %{
12864 // eFlagsReg cr;
12865 // compI_eReg(cr,op1,op2);
12866 // cmovI_reg_lt(op2,op1,cr);
12867 // %}
12868 //%}
12869
12870 // Min Register with Register (generic version)
12871 instruct minI_eReg(eRegI dst, eRegI src, eFlagsReg flags) %{
12872 match(Set dst (MinI dst src));
12873 effect(KILL flags);
12874 ins_cost(300);
12875
12876 format %{ "MIN $dst,$src" %}
12877 opcode(0xCC);
12878 ins_encode( min_enc(dst,src) );
12879 ins_pipe( pipe_slow );
12880 %}
12881
12882 // Max Register with Register
12883 // *** Min and Max using the conditional move are slower than the
12884 // *** branch version on a Pentium III.
12885 // // Conditional move for max
12886 //instruct cmovI_reg_gt( eRegI op2, eRegI op1, eFlagsReg cr ) %{
12887 // effect( USE_DEF op2, USE op1, USE cr );
12888 // format %{ "CMOVgt $op2,$op1\t! max" %}
12889 // opcode(0x4F,0x0F);
12890 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) );
12891 // ins_pipe( pipe_cmov_reg );
12892 //%}
12893 //
12894 // // Max Register with Register (P6 version)
12895 //instruct maxI_eReg_p6( eRegI op1, eRegI op2 ) %{
12896 // predicate(VM_Version::supports_cmov() );
12897 // match(Set op2 (MaxI op1 op2));
12898 // ins_cost(200);
12899 // expand %{
12900 // eFlagsReg cr;
12901 // compI_eReg(cr,op1,op2);
12902 // cmovI_reg_gt(op2,op1,cr);
12903 // %}
12904 //%}
12905
12906 // Max Register with Register (generic version)
12907 instruct maxI_eReg(eRegI dst, eRegI src, eFlagsReg flags) %{
12908 match(Set dst (MaxI dst src));
12909 effect(KILL flags);
12910 ins_cost(300);
12911
12912 format %{ "MAX $dst,$src" %}
12913 opcode(0xCC);
12914 ins_encode( max_enc(dst,src) );
12915 ins_pipe( pipe_slow );
12916 %}
12917
12918 // ============================================================================
12919 // Branch Instructions
12920 // Jump Table
12921 instruct jumpXtnd(eRegI switch_val) %{
12922 match(Jump switch_val);
12923 ins_cost(350);
12924
12925 format %{ "JMP [table_base](,$switch_val,1)\n\t" %}
12926
12927 ins_encode %{
12928 address table_base = __ address_table_constant(_index2label);
12929
12930 // Jump to Address(table_base + switch_reg)
12931 InternalAddress table(table_base);
12932 Address index(noreg, $switch_val$$Register, Address::times_1);
12933 __ jump(ArrayAddress(table, index));
12934 %}
12935 ins_pc_relative(1);
12936 ins_pipe(pipe_jmp);
12937 %}
12938
12939 // Jump Direct - Label defines a relative address from JMP+1
12940 instruct jmpDir(label labl) %{
12941 match(Goto);
12942 effect(USE labl);
12943
12944 ins_cost(300);
12945 format %{ "JMP $labl" %}
12946 size(5);
12947 opcode(0xE9);
12948 ins_encode( OpcP, Lbl( labl ) );
12949 ins_pipe( pipe_jmp );
12950 ins_pc_relative(1);
12951 %}
12952
12953 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12954 instruct jmpCon(cmpOp cop, eFlagsReg cr, label labl) %{
12955 match(If cop cr);
12956 effect(USE labl);
12957
12958 ins_cost(300);
12959 format %{ "J$cop $labl" %}
12960 size(6);
12961 opcode(0x0F, 0x80);
12962 ins_encode( Jcc( cop, labl) );
12963 ins_pipe( pipe_jcc );
12964 ins_pc_relative(1);
12965 %}
12966
12967 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12968 instruct jmpLoopEnd(cmpOp cop, eFlagsReg cr, label labl) %{
12969 match(CountedLoopEnd cop cr);
12970 effect(USE labl);
12971
12972 ins_cost(300);
12973 format %{ "J$cop $labl\t# Loop end" %}
12974 size(6);
12975 opcode(0x0F, 0x80);
12976 ins_encode( Jcc( cop, labl) );
12977 ins_pipe( pipe_jcc );
12978 ins_pc_relative(1);
12979 %}
12980
12981 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12982 instruct jmpLoopEndU(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12983 match(CountedLoopEnd cop cmp);
12984 effect(USE labl);
12985
12986 ins_cost(300);
12987 format %{ "J$cop,u $labl\t# Loop end" %}
12988 size(6);
12989 opcode(0x0F, 0x80);
12990 ins_encode( Jcc( cop, labl) );
12991 ins_pipe( pipe_jcc );
12992 ins_pc_relative(1);
12993 %}
12994
12995 instruct jmpLoopEndUCF(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12996 match(CountedLoopEnd cop cmp);
12997 effect(USE labl);
12998
12999 ins_cost(200);
13000 format %{ "J$cop,u $labl\t# Loop end" %}
13001 size(6);
13002 opcode(0x0F, 0x80);
13003 ins_encode( Jcc( cop, labl) );
13004 ins_pipe( pipe_jcc );
13005 ins_pc_relative(1);
13006 %}
13007
13008 // Jump Direct Conditional - using unsigned comparison
13009 instruct jmpConU(cmpOpU cop, eFlagsRegU cmp, label labl) %{
13010 match(If cop cmp);
13011 effect(USE labl);
13012
13013 ins_cost(300);
13014 format %{ "J$cop,u $labl" %}
13015 size(6);
13016 opcode(0x0F, 0x80);
13017 ins_encode(Jcc(cop, labl));
13018 ins_pipe(pipe_jcc);
13019 ins_pc_relative(1);
13020 %}
13021
13022 instruct jmpConUCF(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
13023 match(If cop cmp);
13024 effect(USE labl);
13025
13026 ins_cost(200);
13027 format %{ "J$cop,u $labl" %}
13028 size(6);
13029 opcode(0x0F, 0x80);
13030 ins_encode(Jcc(cop, labl));
13031 ins_pipe(pipe_jcc);
13032 ins_pc_relative(1);
13033 %}
13034
13035 instruct jmpConUCF2(cmpOpUCF2 cop, eFlagsRegUCF cmp, label labl) %{
13036 match(If cop cmp);
13037 effect(USE labl);
13038
13039 ins_cost(200);
13040 format %{ $$template
13041 if ($cop$$cmpcode == Assembler::notEqual) {
13042 $$emit$$"JP,u $labl\n\t"
13043 $$emit$$"J$cop,u $labl"
13044 } else {
13045 $$emit$$"JP,u done\n\t"
13046 $$emit$$"J$cop,u $labl\n\t"
13047 $$emit$$"done:"
13048 }
13049 %}
13050 size(12);
13051 opcode(0x0F, 0x80);
13052 ins_encode %{
13053 Label* l = $labl$$label;
13054 $$$emit8$primary;
13055 emit_cc(cbuf, $secondary, Assembler::parity);
13056 int parity_disp = -1;
13057 bool ok = false;
13058 if ($cop$$cmpcode == Assembler::notEqual) {
13059 // the two jumps 6 bytes apart so the jump distances are too
13060 parity_disp = l ? (l->loc_pos() - (cbuf.code_size() + 4)) : 0;
13061 } else if ($cop$$cmpcode == Assembler::equal) {
13062 parity_disp = 6;
13063 ok = true;
13064 } else {
13065 ShouldNotReachHere();
13066 }
13067 emit_d32(cbuf, parity_disp);
13068 $$$emit8$primary;
13069 emit_cc(cbuf, $secondary, $cop$$cmpcode);
13070 int disp = l ? (l->loc_pos() - (cbuf.code_size() + 4)) : 0;
13071 emit_d32(cbuf, disp);
13072 %}
13073 ins_pipe(pipe_jcc);
13074 ins_pc_relative(1);
13075 %}
13076
13077 // ============================================================================
13078 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
13079 // array for an instance of the superklass. Set a hidden internal cache on a
13080 // hit (cache is checked with exposed code in gen_subtype_check()). Return
13081 // NZ for a miss or zero for a hit. The encoding ALSO sets flags.
13082 instruct partialSubtypeCheck( eDIRegP result, eSIRegP sub, eAXRegP super, eCXRegI rcx, eFlagsReg cr ) %{
13083 match(Set result (PartialSubtypeCheck sub super));
13084 effect( KILL rcx, KILL cr );
13085
13086 ins_cost(1100); // slightly larger than the next version
13087 format %{ "MOV EDI,[$sub+Klass::secondary_supers]\n\t"
13088 "MOV ECX,[EDI+arrayKlass::length]\t# length to scan\n\t"
13089 "ADD EDI,arrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t"
13090 "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t"
13091 "JNE,s miss\t\t# Missed: EDI not-zero\n\t"
13092 "MOV [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache\n\t"
13093 "XOR $result,$result\t\t Hit: EDI zero\n\t"
13094 "miss:\t" %}
13095
13096 opcode(0x1); // Force a XOR of EDI
13097 ins_encode( enc_PartialSubtypeCheck() );
13098 ins_pipe( pipe_slow );
13099 %}
13100
13101 instruct partialSubtypeCheck_vs_Zero( eFlagsReg cr, eSIRegP sub, eAXRegP super, eCXRegI rcx, eDIRegP result, immP0 zero ) %{
13102 match(Set cr (CmpP (PartialSubtypeCheck sub super) zero));
13103 effect( KILL rcx, KILL result );
13104
13105 ins_cost(1000);
13106 format %{ "MOV EDI,[$sub+Klass::secondary_supers]\n\t"
13107 "MOV ECX,[EDI+arrayKlass::length]\t# length to scan\n\t"
13108 "ADD EDI,arrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t"
13109 "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t"
13110 "JNE,s miss\t\t# Missed: flags NZ\n\t"
13111 "MOV [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache, flags Z\n\t"
13112 "miss:\t" %}
13113
13114 opcode(0x0); // No need to XOR EDI
13115 ins_encode( enc_PartialSubtypeCheck() );
13116 ins_pipe( pipe_slow );
13117 %}
13118
13119 // ============================================================================
13120 // Branch Instructions -- short offset versions
13121 //
13122 // These instructions are used to replace jumps of a long offset (the default
13123 // match) with jumps of a shorter offset. These instructions are all tagged
13124 // with the ins_short_branch attribute, which causes the ADLC to suppress the
13125 // match rules in general matching. Instead, the ADLC generates a conversion
13126 // method in the MachNode which can be used to do in-place replacement of the
13127 // long variant with the shorter variant. The compiler will determine if a
13128 // branch can be taken by the is_short_branch_offset() predicate in the machine
13129 // specific code section of the file.
13130
13131 // Jump Direct - Label defines a relative address from JMP+1
13132 instruct jmpDir_short(label labl) %{
13133 match(Goto);
13134 effect(USE labl);
13135
13136 ins_cost(300);
13137 format %{ "JMP,s $labl" %}
13138 size(2);
13139 opcode(0xEB);
13140 ins_encode( OpcP, LblShort( labl ) );
13141 ins_pipe( pipe_jmp );
13142 ins_pc_relative(1);
13143 ins_short_branch(1);
13144 %}
13145
13146 // Jump Direct Conditional - Label defines a relative address from Jcc+1
13147 instruct jmpCon_short(cmpOp cop, eFlagsReg cr, label labl) %{
13148 match(If cop cr);
13149 effect(USE labl);
13150
13151 ins_cost(300);
13152 format %{ "J$cop,s $labl" %}
13153 size(2);
13154 opcode(0x70);
13155 ins_encode( JccShort( cop, labl) );
13156 ins_pipe( pipe_jcc );
13157 ins_pc_relative(1);
13158 ins_short_branch(1);
13159 %}
13160
13161 // Jump Direct Conditional - Label defines a relative address from Jcc+1
13162 instruct jmpLoopEnd_short(cmpOp cop, eFlagsReg cr, label labl) %{
13163 match(CountedLoopEnd cop cr);
13164 effect(USE labl);
13165
13166 ins_cost(300);
13167 format %{ "J$cop,s $labl\t# Loop end" %}
13168 size(2);
13169 opcode(0x70);
13170 ins_encode( JccShort( cop, labl) );
13171 ins_pipe( pipe_jcc );
13172 ins_pc_relative(1);
13173 ins_short_branch(1);
13174 %}
13175
13176 // Jump Direct Conditional - Label defines a relative address from Jcc+1
13177 instruct jmpLoopEndU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{
13178 match(CountedLoopEnd cop cmp);
13179 effect(USE labl);
13180
13181 ins_cost(300);
13182 format %{ "J$cop,us $labl\t# Loop end" %}
13183 size(2);
13184 opcode(0x70);
13185 ins_encode( JccShort( cop, labl) );
13186 ins_pipe( pipe_jcc );
13187 ins_pc_relative(1);
13188 ins_short_branch(1);
13189 %}
13190
13191 instruct jmpLoopEndUCF_short(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
13192 match(CountedLoopEnd cop cmp);
13193 effect(USE labl);
13194
13195 ins_cost(300);
13196 format %{ "J$cop,us $labl\t# Loop end" %}
13197 size(2);
13198 opcode(0x70);
13199 ins_encode( JccShort( cop, labl) );
13200 ins_pipe( pipe_jcc );
13201 ins_pc_relative(1);
13202 ins_short_branch(1);
13203 %}
13204
13205 // Jump Direct Conditional - using unsigned comparison
13206 instruct jmpConU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{
13207 match(If cop cmp);
13208 effect(USE labl);
13209
13210 ins_cost(300);
13211 format %{ "J$cop,us $labl" %}
13212 size(2);
13213 opcode(0x70);
13214 ins_encode( JccShort( cop, labl) );
13215 ins_pipe( pipe_jcc );
13216 ins_pc_relative(1);
13217 ins_short_branch(1);
13218 %}
13219
13220 instruct jmpConUCF_short(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
13221 match(If cop cmp);
13222 effect(USE labl);
13223
13224 ins_cost(300);
13225 format %{ "J$cop,us $labl" %}
13226 size(2);
13227 opcode(0x70);
13228 ins_encode( JccShort( cop, labl) );
13229 ins_pipe( pipe_jcc );
13230 ins_pc_relative(1);
13231 ins_short_branch(1);
13232 %}
13233
13234 instruct jmpConUCF2_short(cmpOpUCF2 cop, eFlagsRegUCF cmp, label labl) %{
13235 match(If cop cmp);
13236 effect(USE labl);
13237
13238 ins_cost(300);
13239 format %{ $$template
13240 if ($cop$$cmpcode == Assembler::notEqual) {
13241 $$emit$$"JP,u,s $labl\n\t"
13242 $$emit$$"J$cop,u,s $labl"
13243 } else {
13244 $$emit$$"JP,u,s done\n\t"
13245 $$emit$$"J$cop,u,s $labl\n\t"
13246 $$emit$$"done:"
13247 }
13248 %}
13249 size(4);
13250 opcode(0x70);
13251 ins_encode %{
13252 Label* l = $labl$$label;
13253 emit_cc(cbuf, $primary, Assembler::parity);
13254 int parity_disp = -1;
13255 if ($cop$$cmpcode == Assembler::notEqual) {
13256 parity_disp = l ? (l->loc_pos() - (cbuf.code_size() + 1)) : 0;
13257 } else if ($cop$$cmpcode == Assembler::equal) {
13258 parity_disp = 2;
13259 } else {
13260 ShouldNotReachHere();
13261 }
13262 emit_d8(cbuf, parity_disp);
13263 emit_cc(cbuf, $primary, $cop$$cmpcode);
13264 int disp = l ? (l->loc_pos() - (cbuf.code_size() + 1)) : 0;
13265 emit_d8(cbuf, disp);
13266 assert(-128 <= disp && disp <= 127, "Displacement too large for short jmp");
13267 assert(-128 <= parity_disp && parity_disp <= 127, "Displacement too large for short jmp");
13268 %}
13269 ins_pipe(pipe_jcc);
13270 ins_pc_relative(1);
13271 ins_short_branch(1);
13272 %}
13273
13274 // ============================================================================
13275 // Long Compare
13276 //
13277 // Currently we hold longs in 2 registers. Comparing such values efficiently
13278 // is tricky. The flavor of compare used depends on whether we are testing
13279 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit.
13280 // The GE test is the negated LT test. The LE test can be had by commuting
13281 // the operands (yielding a GE test) and then negating; negate again for the
13282 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the
13283 // NE test is negated from that.
13284
13285 // Due to a shortcoming in the ADLC, it mixes up expressions like:
13286 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the
13287 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections
13288 // are collapsed internally in the ADLC's dfa-gen code. The match for
13289 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the
13290 // foo match ends up with the wrong leaf. One fix is to not match both
13291 // reg-reg and reg-zero forms of long-compare. This is unfortunate because
13292 // both forms beat the trinary form of long-compare and both are very useful
13293 // on Intel which has so few registers.
13294
13295 // Manifest a CmpL result in an integer register. Very painful.
13296 // This is the test to avoid.
13297 instruct cmpL3_reg_reg(eSIRegI dst, eRegL src1, eRegL src2, eFlagsReg flags ) %{
13298 match(Set dst (CmpL3 src1 src2));
13299 effect( KILL flags );
13300 ins_cost(1000);
13301 format %{ "XOR $dst,$dst\n\t"
13302 "CMP $src1.hi,$src2.hi\n\t"
13303 "JLT,s m_one\n\t"
13304 "JGT,s p_one\n\t"
13305 "CMP $src1.lo,$src2.lo\n\t"
13306 "JB,s m_one\n\t"
13307 "JEQ,s done\n"
13308 "p_one:\tINC $dst\n\t"
13309 "JMP,s done\n"
13310 "m_one:\tDEC $dst\n"
13311 "done:" %}
13312 ins_encode %{
13313 Label p_one, m_one, done;
13314 __ xorptr($dst$$Register, $dst$$Register);
13315 __ cmpl(HIGH_FROM_LOW($src1$$Register), HIGH_FROM_LOW($src2$$Register));
13316 __ jccb(Assembler::less, m_one);
13317 __ jccb(Assembler::greater, p_one);
13318 __ cmpl($src1$$Register, $src2$$Register);
13319 __ jccb(Assembler::below, m_one);
13320 __ jccb(Assembler::equal, done);
13321 __ bind(p_one);
13322 __ incrementl($dst$$Register);
13323 __ jmpb(done);
13324 __ bind(m_one);
13325 __ decrementl($dst$$Register);
13326 __ bind(done);
13327 %}
13328 ins_pipe( pipe_slow );
13329 %}
13330
13331 //======
13332 // Manifest a CmpL result in the normal flags. Only good for LT or GE
13333 // compares. Can be used for LE or GT compares by reversing arguments.
13334 // NOT GOOD FOR EQ/NE tests.
13335 instruct cmpL_zero_flags_LTGE( flagsReg_long_LTGE flags, eRegL src, immL0 zero ) %{
13336 match( Set flags (CmpL src zero ));
13337 ins_cost(100);
13338 format %{ "TEST $src.hi,$src.hi" %}
13339 opcode(0x85);
13340 ins_encode( OpcP, RegReg_Hi2( src, src ) );
13341 ins_pipe( ialu_cr_reg_reg );
13342 %}
13343
13344 // Manifest a CmpL result in the normal flags. Only good for LT or GE
13345 // compares. Can be used for LE or GT compares by reversing arguments.
13346 // NOT GOOD FOR EQ/NE tests.
13347 instruct cmpL_reg_flags_LTGE( flagsReg_long_LTGE flags, eRegL src1, eRegL src2, eRegI tmp ) %{
13348 match( Set flags (CmpL src1 src2 ));
13349 effect( TEMP tmp );
13350 ins_cost(300);
13351 format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t"
13352 "MOV $tmp,$src1.hi\n\t"
13353 "SBB $tmp,$src2.hi\t! Compute flags for long compare" %}
13354 ins_encode( long_cmp_flags2( src1, src2, tmp ) );
13355 ins_pipe( ialu_cr_reg_reg );
13356 %}
13357
13358 // Long compares reg < zero/req OR reg >= zero/req.
13359 // Just a wrapper for a normal branch, plus the predicate test.
13360 instruct cmpL_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, label labl) %{
13361 match(If cmp flags);
13362 effect(USE labl);
13363 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
13364 expand %{
13365 jmpCon(cmp,flags,labl); // JLT or JGE...
13366 %}
13367 %}
13368
13369 // Compare 2 longs and CMOVE longs.
13370 instruct cmovLL_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, eRegL src) %{
13371 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
13372 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
13373 ins_cost(400);
13374 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
13375 "CMOV$cmp $dst.hi,$src.hi" %}
13376 opcode(0x0F,0x40);
13377 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
13378 ins_pipe( pipe_cmov_reg_long );
13379 %}
13380
13381 instruct cmovLL_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, load_long_memory src) %{
13382 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
13383 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
13384 ins_cost(500);
13385 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
13386 "CMOV$cmp $dst.hi,$src.hi" %}
13387 opcode(0x0F,0x40);
13388 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
13389 ins_pipe( pipe_cmov_reg_long );
13390 %}
13391
13392 // Compare 2 longs and CMOVE ints.
13393 instruct cmovII_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegI dst, eRegI src) %{
13394 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
13395 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
13396 ins_cost(200);
13397 format %{ "CMOV$cmp $dst,$src" %}
13398 opcode(0x0F,0x40);
13399 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
13400 ins_pipe( pipe_cmov_reg );
13401 %}
13402
13403 instruct cmovII_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegI dst, memory src) %{
13404 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
13405 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
13406 ins_cost(250);
13407 format %{ "CMOV$cmp $dst,$src" %}
13408 opcode(0x0F,0x40);
13409 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
13410 ins_pipe( pipe_cmov_mem );
13411 %}
13412
13413 // Compare 2 longs and CMOVE ints.
13414 instruct cmovPP_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegP dst, eRegP src) %{
13415 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
13416 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
13417 ins_cost(200);
13418 format %{ "CMOV$cmp $dst,$src" %}
13419 opcode(0x0F,0x40);
13420 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
13421 ins_pipe( pipe_cmov_reg );
13422 %}
13423
13424 // Compare 2 longs and CMOVE doubles
13425 instruct cmovDD_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regD dst, regD src) %{
13426 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
13427 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
13428 ins_cost(200);
13429 expand %{
13430 fcmovD_regS(cmp,flags,dst,src);
13431 %}
13432 %}
13433
13434 // Compare 2 longs and CMOVE doubles
13435 instruct cmovXDD_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regXD dst, regXD src) %{
13436 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
13437 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
13438 ins_cost(200);
13439 expand %{
13440 fcmovXD_regS(cmp,flags,dst,src);
13441 %}
13442 %}
13443
13444 instruct cmovFF_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regF dst, regF src) %{
13445 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
13446 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
13447 ins_cost(200);
13448 expand %{
13449 fcmovF_regS(cmp,flags,dst,src);
13450 %}
13451 %}
13452
13453 instruct cmovXX_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regX dst, regX src) %{
13454 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
13455 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
13456 ins_cost(200);
13457 expand %{
13458 fcmovX_regS(cmp,flags,dst,src);
13459 %}
13460 %}
13461
13462 //======
13463 // Manifest a CmpL result in the normal flags. Only good for EQ/NE compares.
13464 instruct cmpL_zero_flags_EQNE( flagsReg_long_EQNE flags, eRegL src, immL0 zero, eRegI tmp ) %{
13465 match( Set flags (CmpL src zero ));
13466 effect(TEMP tmp);
13467 ins_cost(200);
13468 format %{ "MOV $tmp,$src.lo\n\t"
13469 "OR $tmp,$src.hi\t! Long is EQ/NE 0?" %}
13470 ins_encode( long_cmp_flags0( src, tmp ) );
13471 ins_pipe( ialu_reg_reg_long );
13472 %}
13473
13474 // Manifest a CmpL result in the normal flags. Only good for EQ/NE compares.
13475 instruct cmpL_reg_flags_EQNE( flagsReg_long_EQNE flags, eRegL src1, eRegL src2 ) %{
13476 match( Set flags (CmpL src1 src2 ));
13477 ins_cost(200+300);
13478 format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t"
13479 "JNE,s skip\n\t"
13480 "CMP $src1.hi,$src2.hi\n\t"
13481 "skip:\t" %}
13482 ins_encode( long_cmp_flags1( src1, src2 ) );
13483 ins_pipe( ialu_cr_reg_reg );
13484 %}
13485
13486 // Long compare reg == zero/reg OR reg != zero/reg
13487 // Just a wrapper for a normal branch, plus the predicate test.
13488 instruct cmpL_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, label labl) %{
13489 match(If cmp flags);
13490 effect(USE labl);
13491 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
13492 expand %{
13493 jmpCon(cmp,flags,labl); // JEQ or JNE...
13494 %}
13495 %}
13496
13497 // Compare 2 longs and CMOVE longs.
13498 instruct cmovLL_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, eRegL src) %{
13499 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
13500 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
13501 ins_cost(400);
13502 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
13503 "CMOV$cmp $dst.hi,$src.hi" %}
13504 opcode(0x0F,0x40);
13505 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
13506 ins_pipe( pipe_cmov_reg_long );
13507 %}
13508
13509 instruct cmovLL_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, load_long_memory src) %{
13510 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
13511 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
13512 ins_cost(500);
13513 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
13514 "CMOV$cmp $dst.hi,$src.hi" %}
13515 opcode(0x0F,0x40);
13516 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
13517 ins_pipe( pipe_cmov_reg_long );
13518 %}
13519
13520 // Compare 2 longs and CMOVE ints.
13521 instruct cmovII_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegI dst, eRegI src) %{
13522 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
13523 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
13524 ins_cost(200);
13525 format %{ "CMOV$cmp $dst,$src" %}
13526 opcode(0x0F,0x40);
13527 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
13528 ins_pipe( pipe_cmov_reg );
13529 %}
13530
13531 instruct cmovII_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegI dst, memory src) %{
13532 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
13533 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
13534 ins_cost(250);
13535 format %{ "CMOV$cmp $dst,$src" %}
13536 opcode(0x0F,0x40);
13537 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
13538 ins_pipe( pipe_cmov_mem );
13539 %}
13540
13541 // Compare 2 longs and CMOVE ints.
13542 instruct cmovPP_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegP dst, eRegP src) %{
13543 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
13544 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
13545 ins_cost(200);
13546 format %{ "CMOV$cmp $dst,$src" %}
13547 opcode(0x0F,0x40);
13548 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
13549 ins_pipe( pipe_cmov_reg );
13550 %}
13551
13552 // Compare 2 longs and CMOVE doubles
13553 instruct cmovDD_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regD dst, regD src) %{
13554 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
13555 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
13556 ins_cost(200);
13557 expand %{
13558 fcmovD_regS(cmp,flags,dst,src);
13559 %}
13560 %}
13561
13562 // Compare 2 longs and CMOVE doubles
13563 instruct cmovXDD_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regXD dst, regXD src) %{
13564 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
13565 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
13566 ins_cost(200);
13567 expand %{
13568 fcmovXD_regS(cmp,flags,dst,src);
13569 %}
13570 %}
13571
13572 instruct cmovFF_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regF dst, regF src) %{
13573 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
13574 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
13575 ins_cost(200);
13576 expand %{
13577 fcmovF_regS(cmp,flags,dst,src);
13578 %}
13579 %}
13580
13581 instruct cmovXX_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regX dst, regX src) %{
13582 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
13583 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
13584 ins_cost(200);
13585 expand %{
13586 fcmovX_regS(cmp,flags,dst,src);
13587 %}
13588 %}
13589
13590 //======
13591 // Manifest a CmpL result in the normal flags. Only good for LE or GT compares.
13592 // Same as cmpL_reg_flags_LEGT except must negate src
13593 instruct cmpL_zero_flags_LEGT( flagsReg_long_LEGT flags, eRegL src, immL0 zero, eRegI tmp ) %{
13594 match( Set flags (CmpL src zero ));
13595 effect( TEMP tmp );
13596 ins_cost(300);
13597 format %{ "XOR $tmp,$tmp\t# Long compare for -$src < 0, use commuted test\n\t"
13598 "CMP $tmp,$src.lo\n\t"
13599 "SBB $tmp,$src.hi\n\t" %}
13600 ins_encode( long_cmp_flags3(src, tmp) );
13601 ins_pipe( ialu_reg_reg_long );
13602 %}
13603
13604 // Manifest a CmpL result in the normal flags. Only good for LE or GT compares.
13605 // Same as cmpL_reg_flags_LTGE except operands swapped. Swapping operands
13606 // requires a commuted test to get the same result.
13607 instruct cmpL_reg_flags_LEGT( flagsReg_long_LEGT flags, eRegL src1, eRegL src2, eRegI tmp ) %{
13608 match( Set flags (CmpL src1 src2 ));
13609 effect( TEMP tmp );
13610 ins_cost(300);
13611 format %{ "CMP $src2.lo,$src1.lo\t! Long compare, swapped operands, use with commuted test\n\t"
13612 "MOV $tmp,$src2.hi\n\t"
13613 "SBB $tmp,$src1.hi\t! Compute flags for long compare" %}
13614 ins_encode( long_cmp_flags2( src2, src1, tmp ) );
13615 ins_pipe( ialu_cr_reg_reg );
13616 %}
13617
13618 // Long compares reg < zero/req OR reg >= zero/req.
13619 // Just a wrapper for a normal branch, plus the predicate test
13620 instruct cmpL_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, label labl) %{
13621 match(If cmp flags);
13622 effect(USE labl);
13623 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le );
13624 ins_cost(300);
13625 expand %{
13626 jmpCon(cmp,flags,labl); // JGT or JLE...
13627 %}
13628 %}
13629
13630 // Compare 2 longs and CMOVE longs.
13631 instruct cmovLL_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, eRegL src) %{
13632 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
13633 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
13634 ins_cost(400);
13635 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
13636 "CMOV$cmp $dst.hi,$src.hi" %}
13637 opcode(0x0F,0x40);
13638 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
13639 ins_pipe( pipe_cmov_reg_long );
13640 %}
13641
13642 instruct cmovLL_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, load_long_memory src) %{
13643 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
13644 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
13645 ins_cost(500);
13646 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
13647 "CMOV$cmp $dst.hi,$src.hi+4" %}
13648 opcode(0x0F,0x40);
13649 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
13650 ins_pipe( pipe_cmov_reg_long );
13651 %}
13652
13653 // Compare 2 longs and CMOVE ints.
13654 instruct cmovII_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegI dst, eRegI src) %{
13655 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
13656 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
13657 ins_cost(200);
13658 format %{ "CMOV$cmp $dst,$src" %}
13659 opcode(0x0F,0x40);
13660 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
13661 ins_pipe( pipe_cmov_reg );
13662 %}
13663
13664 instruct cmovII_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegI dst, memory src) %{
13665 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
13666 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
13667 ins_cost(250);
13668 format %{ "CMOV$cmp $dst,$src" %}
13669 opcode(0x0F,0x40);
13670 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
13671 ins_pipe( pipe_cmov_mem );
13672 %}
13673
13674 // Compare 2 longs and CMOVE ptrs.
13675 instruct cmovPP_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegP dst, eRegP src) %{
13676 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
13677 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
13678 ins_cost(200);
13679 format %{ "CMOV$cmp $dst,$src" %}
13680 opcode(0x0F,0x40);
13681 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
13682 ins_pipe( pipe_cmov_reg );
13683 %}
13684
13685 // Compare 2 longs and CMOVE doubles
13686 instruct cmovDD_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regD dst, regD src) %{
13687 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
13688 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
13689 ins_cost(200);
13690 expand %{
13691 fcmovD_regS(cmp,flags,dst,src);
13692 %}
13693 %}
13694
13695 // Compare 2 longs and CMOVE doubles
13696 instruct cmovXDD_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regXD dst, regXD src) %{
13697 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
13698 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
13699 ins_cost(200);
13700 expand %{
13701 fcmovXD_regS(cmp,flags,dst,src);
13702 %}
13703 %}
13704
13705 instruct cmovFF_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regF dst, regF src) %{
13706 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
13707 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
13708 ins_cost(200);
13709 expand %{
13710 fcmovF_regS(cmp,flags,dst,src);
13711 %}
13712 %}
13713
13714
13715 instruct cmovXX_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regX dst, regX src) %{
13716 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
13717 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
13718 ins_cost(200);
13719 expand %{
13720 fcmovX_regS(cmp,flags,dst,src);
13721 %}
13722 %}
13723
13724
13725 // ============================================================================
13726 // Procedure Call/Return Instructions
13727 // Call Java Static Instruction
13728 // Note: If this code changes, the corresponding ret_addr_offset() and
13729 // compute_padding() functions will have to be adjusted.
13730 instruct CallStaticJavaDirect(method meth) %{
13731 match(CallStaticJava);
13732 effect(USE meth);
13733
13734 ins_cost(300);
13735 format %{ "CALL,static " %}
13736 opcode(0xE8); /* E8 cd */
13737 ins_encode( pre_call_FPU,
13738 Java_Static_Call( meth ),
13739 call_epilog,
13740 post_call_FPU );
13741 ins_pipe( pipe_slow );
13742 ins_pc_relative(1);
13743 ins_alignment(4);
13744 %}
13745
13746 // Call Java Dynamic Instruction
13747 // Note: If this code changes, the corresponding ret_addr_offset() and
13748 // compute_padding() functions will have to be adjusted.
13749 instruct CallDynamicJavaDirect(method meth) %{
13750 match(CallDynamicJava);
13751 effect(USE meth);
13752
13753 ins_cost(300);
13754 format %{ "MOV EAX,(oop)-1\n\t"
13755 "CALL,dynamic" %}
13756 opcode(0xE8); /* E8 cd */
13757 ins_encode( pre_call_FPU,
13758 Java_Dynamic_Call( meth ),
13759 call_epilog,
13760 post_call_FPU );
13761 ins_pipe( pipe_slow );
13762 ins_pc_relative(1);
13763 ins_alignment(4);
13764 %}
13765
13766 // Call Runtime Instruction
13767 instruct CallRuntimeDirect(method meth) %{
13768 match(CallRuntime );
13769 effect(USE meth);
13770
13771 ins_cost(300);
13772 format %{ "CALL,runtime " %}
13773 opcode(0xE8); /* E8 cd */
13774 // Use FFREEs to clear entries in float stack
13775 ins_encode( pre_call_FPU,
13776 FFree_Float_Stack_All,
13777 Java_To_Runtime( meth ),
13778 post_call_FPU );
13779 ins_pipe( pipe_slow );
13780 ins_pc_relative(1);
13781 %}
13782
13783 // Call runtime without safepoint
13784 instruct CallLeafDirect(method meth) %{
13785 match(CallLeaf);
13786 effect(USE meth);
13787
13788 ins_cost(300);
13789 format %{ "CALL_LEAF,runtime " %}
13790 opcode(0xE8); /* E8 cd */
13791 ins_encode( pre_call_FPU,
13792 FFree_Float_Stack_All,
13793 Java_To_Runtime( meth ),
13794 Verify_FPU_For_Leaf, post_call_FPU );
13795 ins_pipe( pipe_slow );
13796 ins_pc_relative(1);
13797 %}
13798
13799 instruct CallLeafNoFPDirect(method meth) %{
13800 match(CallLeafNoFP);
13801 effect(USE meth);
13802
13803 ins_cost(300);
13804 format %{ "CALL_LEAF_NOFP,runtime " %}
13805 opcode(0xE8); /* E8 cd */
13806 ins_encode(Java_To_Runtime(meth));
13807 ins_pipe( pipe_slow );
13808 ins_pc_relative(1);
13809 %}
13810
13811
13812 // Return Instruction
13813 // Remove the return address & jump to it.
13814 instruct Ret() %{
13815 match(Return);
13816 format %{ "RET" %}
13817 opcode(0xC3);
13818 ins_encode(OpcP);
13819 ins_pipe( pipe_jmp );
13820 %}
13821
13822 // Tail Call; Jump from runtime stub to Java code.
13823 // Also known as an 'interprocedural jump'.
13824 // Target of jump will eventually return to caller.
13825 // TailJump below removes the return address.
13826 instruct TailCalljmpInd(eRegP_no_EBP jump_target, eBXRegP method_oop) %{
13827 match(TailCall jump_target method_oop );
13828 ins_cost(300);
13829 format %{ "JMP $jump_target \t# EBX holds method oop" %}
13830 opcode(0xFF, 0x4); /* Opcode FF /4 */
13831 ins_encode( OpcP, RegOpc(jump_target) );
13832 ins_pipe( pipe_jmp );
13833 %}
13834
13835
13836 // Tail Jump; remove the return address; jump to target.
13837 // TailCall above leaves the return address around.
13838 instruct tailjmpInd(eRegP_no_EBP jump_target, eAXRegP ex_oop) %{
13839 match( TailJump jump_target ex_oop );
13840 ins_cost(300);
13841 format %{ "POP EDX\t# pop return address into dummy\n\t"
13842 "JMP $jump_target " %}
13843 opcode(0xFF, 0x4); /* Opcode FF /4 */
13844 ins_encode( enc_pop_rdx,
13845 OpcP, RegOpc(jump_target) );
13846 ins_pipe( pipe_jmp );
13847 %}
13848
13849 // Create exception oop: created by stack-crawling runtime code.
13850 // Created exception is now available to this handler, and is setup
13851 // just prior to jumping to this handler. No code emitted.
13852 instruct CreateException( eAXRegP ex_oop )
13853 %{
13854 match(Set ex_oop (CreateEx));
13855
13856 size(0);
13857 // use the following format syntax
13858 format %{ "# exception oop is in EAX; no code emitted" %}
13859 ins_encode();
13860 ins_pipe( empty );
13861 %}
13862
13863
13864 // Rethrow exception:
13865 // The exception oop will come in the first argument position.
13866 // Then JUMP (not call) to the rethrow stub code.
13867 instruct RethrowException()
13868 %{
13869 match(Rethrow);
13870
13871 // use the following format syntax
13872 format %{ "JMP rethrow_stub" %}
13873 ins_encode(enc_rethrow);
13874 ins_pipe( pipe_jmp );
13875 %}
13876
13877 // inlined locking and unlocking
13878
13879
13880 instruct cmpFastLock( eFlagsReg cr, eRegP object, eRegP box, eAXRegI tmp, eRegP scr) %{
13881 match( Set cr (FastLock object box) );
13882 effect( TEMP tmp, TEMP scr );
13883 ins_cost(300);
13884 format %{ "FASTLOCK $object, $box KILLS $tmp,$scr" %}
13885 ins_encode( Fast_Lock(object,box,tmp,scr) );
13886 ins_pipe( pipe_slow );
13887 ins_pc_relative(1);
13888 %}
13889
13890 instruct cmpFastUnlock( eFlagsReg cr, eRegP object, eAXRegP box, eRegP tmp ) %{
13891 match( Set cr (FastUnlock object box) );
13892 effect( TEMP tmp );
13893 ins_cost(300);
13894 format %{ "FASTUNLOCK $object, $box, $tmp" %}
13895 ins_encode( Fast_Unlock(object,box,tmp) );
13896 ins_pipe( pipe_slow );
13897 ins_pc_relative(1);
13898 %}
13899
13900
13901
13902 // ============================================================================
13903 // Safepoint Instruction
13904 instruct safePoint_poll(eFlagsReg cr) %{
13905 match(SafePoint);
13906 effect(KILL cr);
13907
13908 // TODO-FIXME: we currently poll at offset 0 of the safepoint polling page.
13909 // On SPARC that might be acceptable as we can generate the address with
13910 // just a sethi, saving an or. By polling at offset 0 we can end up
13911 // putting additional pressure on the index-0 in the D$. Because of
13912 // alignment (just like the situation at hand) the lower indices tend
13913 // to see more traffic. It'd be better to change the polling address
13914 // to offset 0 of the last $line in the polling page.
13915
13916 format %{ "TSTL #polladdr,EAX\t! Safepoint: poll for GC" %}
13917 ins_cost(125);
13918 size(6) ;
13919 ins_encode( Safepoint_Poll() );
13920 ins_pipe( ialu_reg_mem );
13921 %}
13922
13923 //----------PEEPHOLE RULES-----------------------------------------------------
13924 // These must follow all instruction definitions as they use the names
13925 // defined in the instructions definitions.
13926 //
13927 // peepmatch ( root_instr_name [preceding_instruction]* );
13928 //
13929 // peepconstraint %{
13930 // (instruction_number.operand_name relational_op instruction_number.operand_name
13931 // [, ...] );
13932 // // instruction numbers are zero-based using left to right order in peepmatch
13933 //
13934 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
13935 // // provide an instruction_number.operand_name for each operand that appears
13936 // // in the replacement instruction's match rule
13937 //
13938 // ---------VM FLAGS---------------------------------------------------------
13939 //
13940 // All peephole optimizations can be turned off using -XX:-OptoPeephole
13941 //
13942 // Each peephole rule is given an identifying number starting with zero and
13943 // increasing by one in the order seen by the parser. An individual peephole
13944 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
13945 // on the command-line.
13946 //
13947 // ---------CURRENT LIMITATIONS----------------------------------------------
13948 //
13949 // Only match adjacent instructions in same basic block
13950 // Only equality constraints
13951 // Only constraints between operands, not (0.dest_reg == EAX_enc)
13952 // Only one replacement instruction
13953 //
13954 // ---------EXAMPLE----------------------------------------------------------
13955 //
13956 // // pertinent parts of existing instructions in architecture description
13957 // instruct movI(eRegI dst, eRegI src) %{
13958 // match(Set dst (CopyI src));
13959 // %}
13960 //
13961 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
13962 // match(Set dst (AddI dst src));
13963 // effect(KILL cr);
13964 // %}
13965 //
13966 // // Change (inc mov) to lea
13967 // peephole %{
13968 // // increment preceeded by register-register move
13969 // peepmatch ( incI_eReg movI );
13970 // // require that the destination register of the increment
13971 // // match the destination register of the move
13972 // peepconstraint ( 0.dst == 1.dst );
13973 // // construct a replacement instruction that sets
13974 // // the destination to ( move's source register + one )
13975 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13976 // %}
13977 //
13978 // Implementation no longer uses movX instructions since
13979 // machine-independent system no longer uses CopyX nodes.
13980 //
13981 // peephole %{
13982 // peepmatch ( incI_eReg movI );
13983 // peepconstraint ( 0.dst == 1.dst );
13984 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13985 // %}
13986 //
13987 // peephole %{
13988 // peepmatch ( decI_eReg movI );
13989 // peepconstraint ( 0.dst == 1.dst );
13990 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13991 // %}
13992 //
13993 // peephole %{
13994 // peepmatch ( addI_eReg_imm movI );
13995 // peepconstraint ( 0.dst == 1.dst );
13996 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13997 // %}
13998 //
13999 // peephole %{
14000 // peepmatch ( addP_eReg_imm movP );
14001 // peepconstraint ( 0.dst == 1.dst );
14002 // peepreplace ( leaP_eReg_immI( 0.dst 1.src 0.src ) );
14003 // %}
14004
14005 // // Change load of spilled value to only a spill
14006 // instruct storeI(memory mem, eRegI src) %{
14007 // match(Set mem (StoreI mem src));
14008 // %}
14009 //
14010 // instruct loadI(eRegI dst, memory mem) %{
14011 // match(Set dst (LoadI mem));
14012 // %}
14013 //
14014 peephole %{
14015 peepmatch ( loadI storeI );
14016 peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
14017 peepreplace ( storeI( 1.mem 1.mem 1.src ) );
14018 %}
14019
14020 //----------SMARTSPILL RULES---------------------------------------------------
14021 // These must follow all instruction definitions as they use the names
14022 // defined in the instructions definitions.