5223 interface(CONST_INTER);
5224 %}
5225
5226 operand immI_24() %{
5227 predicate( n->get_int() == 24 );
5228 match(ConI);
5229
5230 format %{ %}
5231 interface(CONST_INTER);
5232 %}
5233
5234 // Constant for byte-wide masking
5235 operand immI_255() %{
5236 predicate( n->get_int() == 255 );
5237 match(ConI);
5238
5239 format %{ %}
5240 interface(CONST_INTER);
5241 %}
5242
5243 // Register Operands
5244 // Integer Register
5245 operand eRegI() %{
5246 constraint(ALLOC_IN_RC(e_reg));
5247 match(RegI);
5248 match(xRegI);
5249 match(eAXRegI);
5250 match(eBXRegI);
5251 match(eCXRegI);
5252 match(eDXRegI);
5253 match(eDIRegI);
5254 match(eSIRegI);
5255
5256 format %{ %}
5257 interface(REG_INTER);
5258 %}
5259
5260 // Subset of Integer Register
5261 operand xRegI(eRegI reg) %{
5262 constraint(ALLOC_IN_RC(x_reg));
6921 __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register));
6922 %}
6923
6924 ins_pipe(ialu_reg_mem);
6925 %}
6926
6927 // Load Short (16bit signed)
6928 instruct loadS(eRegI dst, memory mem) %{
6929 match(Set dst (LoadS mem));
6930
6931 ins_cost(125);
6932 format %{ "MOVSX $dst,$mem\t# short" %}
6933
6934 ins_encode %{
6935 __ movswl($dst$$Register, $mem$$Address);
6936 %}
6937
6938 ins_pipe(ialu_reg_mem);
6939 %}
6940
6941 // Load Short (16bit signed) into Long Register
6942 instruct loadS2L(eRegL dst, memory mem) %{
6943 match(Set dst (ConvI2L (LoadS mem)));
6944
6945 ins_cost(375);
6946 format %{ "MOVSX $dst.lo,$mem\t# short -> long\n\t"
6947 "MOV $dst.hi,$dst.lo\n\t"
6948 "SAR $dst.hi,15" %}
6949
6950 ins_encode %{
6951 __ movswl($dst$$Register, $mem$$Address);
6952 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
6953 __ sarl(HIGH_FROM_LOW($dst$$Register), 15); // 16+1 MSB are already signed extended.
6954 %}
6955
6956 ins_pipe(ialu_reg_mem);
6957 %}
6958
6959 // Load Unsigned Short/Char (16bit unsigned)
6960 instruct loadUS(eRegI dst, memory mem) %{
6961 match(Set dst (LoadUS mem));
6962
6963 ins_cost(125);
6964 format %{ "MOVZX $dst,$mem\t# ushort/char -> int" %}
6965
6966 ins_encode %{
6967 __ movzwl($dst$$Register, $mem$$Address);
6968 %}
6969
6970 ins_pipe(ialu_reg_mem);
6971 %}
6972
6973 // Load Unsigned Short/Char (16 bit UNsigned) into Long Register
6974 instruct loadUS2L(eRegL dst, memory mem)
6975 %{
6976 match(Set dst (ConvI2L (LoadUS mem)));
6977
6978 ins_cost(250);
6979 format %{ "MOVZX $dst.lo,$mem\t# ushort/char -> long\n\t"
6980 "XOR $dst.hi,$dst.hi" %}
6981
6982 ins_encode %{
6983 __ movzwl($dst$$Register, $mem$$Address);
6984 __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register));
6985 %}
6986
6987 ins_pipe(ialu_reg_mem);
6988 %}
6989
6990 // Load Integer
6991 instruct loadI(eRegI dst, memory mem) %{
6992 match(Set dst (LoadI mem));
6993
6994 ins_cost(125);
6995 format %{ "MOV $dst,$mem\t# int" %}
6996
6997 ins_encode %{
6998 __ movl($dst$$Register, $mem$$Address);
6999 %}
7000
7001 ins_pipe(ialu_reg_mem);
7002 %}
7003
7004 // Load Integer into Long Register
7005 instruct loadI2L(eRegL dst, memory mem) %{
7006 match(Set dst (ConvI2L (LoadI mem)));
7007
7008 ins_cost(375);
7009 format %{ "MOV $dst.lo,$mem\t# int -> long\n\t"
7010 "MOV $dst.hi,$dst.lo\n\t"
7011 "SAR $dst.hi,31" %}
7012
7013 ins_encode %{
7014 __ movl($dst$$Register, $mem$$Address);
7015 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
7016 __ sarl(HIGH_FROM_LOW($dst$$Register), 31);
7017 %}
7018
7019 ins_pipe(ialu_reg_mem);
7020 %}
7021
7022 // Load Unsigned Integer into Long Register
7023 instruct loadUI2L(eRegL dst, memory mem) %{
9017 opcode(0xD1, 0x5); /* D1 /5 */
9018 ins_encode( OpcP, RegOpc( dst ) );
9019 ins_pipe( ialu_reg );
9020 %}
9021
9022 // Logical Shift Right by 8-bit immediate
9023 instruct shrI_eReg_imm(eRegI dst, immI8 shift, eFlagsReg cr) %{
9024 match(Set dst (URShiftI dst shift));
9025 effect(KILL cr);
9026
9027 size(3);
9028 format %{ "SHR $dst,$shift" %}
9029 opcode(0xC1, 0x5); /* C1 /5 ib */
9030 ins_encode( RegOpcImm( dst, shift) );
9031 ins_pipe( ialu_reg );
9032 %}
9033
9034
9035 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24.
9036 // This idiom is used by the compiler for the i2b bytecode.
9037 instruct i2b(eRegI dst, xRegI src, immI_24 twentyfour, eFlagsReg cr) %{
9038 match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour));
9039 effect(KILL cr);
9040
9041 size(3);
9042 format %{ "MOVSX $dst,$src :8" %}
9043 opcode(0xBE, 0x0F);
9044 ins_encode( OpcS, OpcP, RegReg( dst, src));
9045 ins_pipe( ialu_reg_reg );
9046 %}
9047
9048 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16.
9049 // This idiom is used by the compiler the i2s bytecode.
9050 instruct i2s(eRegI dst, xRegI src, immI_16 sixteen, eFlagsReg cr) %{
9051 match(Set dst (RShiftI (LShiftI src sixteen) sixteen));
9052 effect(KILL cr);
9053
9054 size(3);
9055 format %{ "MOVSX $dst,$src :16" %}
9056 opcode(0xBF, 0x0F);
9057 ins_encode( OpcS, OpcP, RegReg( dst, src));
9058 ins_pipe( ialu_reg_reg );
9059 %}
9060
9061
9062 // Logical Shift Right by variable
9063 instruct shrI_eReg_CL(eRegI dst, eCXRegI shift, eFlagsReg cr) %{
9064 match(Set dst (URShiftI dst shift));
9065 effect(KILL cr);
9066
9067 size(2);
9068 format %{ "SHR $dst,$shift" %}
9069 opcode(0xD3, 0x5); /* D3 /5 */
9070 ins_encode( OpcP, RegOpc( dst ) );
9071 ins_pipe( ialu_reg_reg );
9072 %}
9073
9074
9075 //----------Logical Instructions-----------------------------------------------
9076 //----------Integer Logical Instructions---------------------------------------
9077 // And Instructions
9078 // And Register with Register
|
5223 interface(CONST_INTER);
5224 %}
5225
5226 operand immI_24() %{
5227 predicate( n->get_int() == 24 );
5228 match(ConI);
5229
5230 format %{ %}
5231 interface(CONST_INTER);
5232 %}
5233
5234 // Constant for byte-wide masking
5235 operand immI_255() %{
5236 predicate( n->get_int() == 255 );
5237 match(ConI);
5238
5239 format %{ %}
5240 interface(CONST_INTER);
5241 %}
5242
5243 // Constant for short-wide masking
5244 operand immI_65535() %{
5245 predicate(n->get_int() == 65535);
5246 match(ConI);
5247
5248 format %{ %}
5249 interface(CONST_INTER);
5250 %}
5251
5252 // Register Operands
5253 // Integer Register
5254 operand eRegI() %{
5255 constraint(ALLOC_IN_RC(e_reg));
5256 match(RegI);
5257 match(xRegI);
5258 match(eAXRegI);
5259 match(eBXRegI);
5260 match(eCXRegI);
5261 match(eDXRegI);
5262 match(eDIRegI);
5263 match(eSIRegI);
5264
5265 format %{ %}
5266 interface(REG_INTER);
5267 %}
5268
5269 // Subset of Integer Register
5270 operand xRegI(eRegI reg) %{
5271 constraint(ALLOC_IN_RC(x_reg));
6930 __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register));
6931 %}
6932
6933 ins_pipe(ialu_reg_mem);
6934 %}
6935
6936 // Load Short (16bit signed)
6937 instruct loadS(eRegI dst, memory mem) %{
6938 match(Set dst (LoadS mem));
6939
6940 ins_cost(125);
6941 format %{ "MOVSX $dst,$mem\t# short" %}
6942
6943 ins_encode %{
6944 __ movswl($dst$$Register, $mem$$Address);
6945 %}
6946
6947 ins_pipe(ialu_reg_mem);
6948 %}
6949
6950 // Load Short (16 bit signed) to Byte (8 bit signed)
6951 instruct loadS2B(eRegI dst, memory mem, immI_24 twentyfour) %{
6952 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
6953
6954 ins_cost(125);
6955 format %{ "MOVSX $dst, $mem\t# short -> byte" %}
6956 ins_encode %{
6957 __ movsbl($dst$$Register, $mem$$Address);
6958 %}
6959 ins_pipe(ialu_reg_mem);
6960 %}
6961
6962 // Load Short (16bit signed) into Long Register
6963 instruct loadS2L(eRegL dst, memory mem) %{
6964 match(Set dst (ConvI2L (LoadS mem)));
6965
6966 ins_cost(375);
6967 format %{ "MOVSX $dst.lo,$mem\t# short -> long\n\t"
6968 "MOV $dst.hi,$dst.lo\n\t"
6969 "SAR $dst.hi,15" %}
6970
6971 ins_encode %{
6972 __ movswl($dst$$Register, $mem$$Address);
6973 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
6974 __ sarl(HIGH_FROM_LOW($dst$$Register), 15); // 16+1 MSB are already signed extended.
6975 %}
6976
6977 ins_pipe(ialu_reg_mem);
6978 %}
6979
6980 // Load Unsigned Short/Char (16bit unsigned)
6981 instruct loadUS(eRegI dst, memory mem) %{
6982 match(Set dst (LoadUS mem));
6983
6984 ins_cost(125);
6985 format %{ "MOVZX $dst,$mem\t# ushort/char -> int" %}
6986
6987 ins_encode %{
6988 __ movzwl($dst$$Register, $mem$$Address);
6989 %}
6990
6991 ins_pipe(ialu_reg_mem);
6992 %}
6993
6994 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
6995 instruct loadUS2B(eRegI dst, memory mem, immI_24 twentyfour) %{
6996 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
6997
6998 ins_cost(125);
6999 format %{ "MOVSX $dst, $mem\t# ushort -> byte" %}
7000 ins_encode %{
7001 __ movsbl($dst$$Register, $mem$$Address);
7002 %}
7003 ins_pipe(ialu_reg_mem);
7004 %}
7005
7006 // Load Unsigned Short/Char (16 bit UNsigned) into Long Register
7007 instruct loadUS2L(eRegL dst, memory mem) %{
7008 match(Set dst (ConvI2L (LoadUS mem)));
7009
7010 ins_cost(250);
7011 format %{ "MOVZX $dst.lo,$mem\t# ushort/char -> long\n\t"
7012 "XOR $dst.hi,$dst.hi" %}
7013
7014 ins_encode %{
7015 __ movzwl($dst$$Register, $mem$$Address);
7016 __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register));
7017 %}
7018
7019 ins_pipe(ialu_reg_mem);
7020 %}
7021
7022 // Load Integer
7023 instruct loadI(eRegI dst, memory mem) %{
7024 match(Set dst (LoadI mem));
7025
7026 ins_cost(125);
7027 format %{ "MOV $dst,$mem\t# int" %}
7028
7029 ins_encode %{
7030 __ movl($dst$$Register, $mem$$Address);
7031 %}
7032
7033 ins_pipe(ialu_reg_mem);
7034 %}
7035
7036 // Load Integer (32 bit signed) to Byte (8 bit signed)
7037 instruct loadI2B(eRegI dst, memory mem, immI_24 twentyfour) %{
7038 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
7039
7040 ins_cost(125);
7041 format %{ "MOVSX $dst, $mem\t# int -> byte" %}
7042 ins_encode %{
7043 __ movsbl($dst$$Register, $mem$$Address);
7044 %}
7045 ins_pipe(ialu_reg_mem);
7046 %}
7047
7048 // Load Integer (32 bit signed) to Unsigned Byte (8 bit UNsigned)
7049 instruct loadI2UB(eRegI dst, memory mem, immI_255 mask) %{
7050 match(Set dst (AndI (LoadI mem) mask));
7051
7052 ins_cost(125);
7053 format %{ "MOVZX $dst, $mem\t# int -> ubyte" %}
7054 ins_encode %{
7055 __ movzbl($dst$$Register, $mem$$Address);
7056 %}
7057 ins_pipe(ialu_reg_mem);
7058 %}
7059
7060 // Load Integer (32 bit signed) to Short (16 bit signed)
7061 instruct loadI2S(eRegI dst, memory mem, immI_16 sixteen) %{
7062 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
7063
7064 ins_cost(125);
7065 format %{ "MOVSX $dst, $mem\t# int -> short" %}
7066 ins_encode %{
7067 __ movswl($dst$$Register, $mem$$Address);
7068 %}
7069 ins_pipe(ialu_reg_mem);
7070 %}
7071
7072 // Load Integer (32 bit signed) to Unsigned Short/Char (16 bit UNsigned)
7073 instruct loadI2US(eRegI dst, memory mem, immI_65535 mask) %{
7074 match(Set dst (AndI (LoadI mem) mask));
7075
7076 ins_cost(125);
7077 format %{ "MOVZX $dst, $mem\t# int -> ushort/char" %}
7078 ins_encode %{
7079 __ movzwl($dst$$Register, $mem$$Address);
7080 %}
7081 ins_pipe(ialu_reg_mem);
7082 %}
7083
7084 // Load Integer into Long Register
7085 instruct loadI2L(eRegL dst, memory mem) %{
7086 match(Set dst (ConvI2L (LoadI mem)));
7087
7088 ins_cost(375);
7089 format %{ "MOV $dst.lo,$mem\t# int -> long\n\t"
7090 "MOV $dst.hi,$dst.lo\n\t"
7091 "SAR $dst.hi,31" %}
7092
7093 ins_encode %{
7094 __ movl($dst$$Register, $mem$$Address);
7095 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
7096 __ sarl(HIGH_FROM_LOW($dst$$Register), 31);
7097 %}
7098
7099 ins_pipe(ialu_reg_mem);
7100 %}
7101
7102 // Load Unsigned Integer into Long Register
7103 instruct loadUI2L(eRegL dst, memory mem) %{
9097 opcode(0xD1, 0x5); /* D1 /5 */
9098 ins_encode( OpcP, RegOpc( dst ) );
9099 ins_pipe( ialu_reg );
9100 %}
9101
9102 // Logical Shift Right by 8-bit immediate
9103 instruct shrI_eReg_imm(eRegI dst, immI8 shift, eFlagsReg cr) %{
9104 match(Set dst (URShiftI dst shift));
9105 effect(KILL cr);
9106
9107 size(3);
9108 format %{ "SHR $dst,$shift" %}
9109 opcode(0xC1, 0x5); /* C1 /5 ib */
9110 ins_encode( RegOpcImm( dst, shift) );
9111 ins_pipe( ialu_reg );
9112 %}
9113
9114
9115 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24.
9116 // This idiom is used by the compiler for the i2b bytecode.
9117 instruct i2b(eRegI dst, xRegI src, immI_24 twentyfour) %{
9118 match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour));
9119
9120 size(3);
9121 format %{ "MOVSX $dst,$src :8" %}
9122 ins_encode %{
9123 __ movsbl($dst$$Register, $src$$Register);
9124 %}
9125 ins_pipe(ialu_reg_reg);
9126 %}
9127
9128 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16.
9129 // This idiom is used by the compiler the i2s bytecode.
9130 instruct i2s(eRegI dst, xRegI src, immI_16 sixteen) %{
9131 match(Set dst (RShiftI (LShiftI src sixteen) sixteen));
9132
9133 size(3);
9134 format %{ "MOVSX $dst,$src :16" %}
9135 ins_encode %{
9136 __ movswl($dst$$Register, $src$$Register);
9137 %}
9138 ins_pipe(ialu_reg_reg);
9139 %}
9140
9141
9142 // Logical Shift Right by variable
9143 instruct shrI_eReg_CL(eRegI dst, eCXRegI shift, eFlagsReg cr) %{
9144 match(Set dst (URShiftI dst shift));
9145 effect(KILL cr);
9146
9147 size(2);
9148 format %{ "SHR $dst,$shift" %}
9149 opcode(0xD3, 0x5); /* D3 /5 */
9150 ins_encode( OpcP, RegOpc( dst ) );
9151 ins_pipe( ialu_reg_reg );
9152 %}
9153
9154
9155 //----------Logical Instructions-----------------------------------------------
9156 //----------Integer Logical Instructions---------------------------------------
9157 // And Instructions
9158 // And Register with Register
|