1 // 2 // Copyright 1998-2009 Sun Microsystems, Inc. All Rights Reserved. 3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 // 5 // This code is free software; you can redistribute it and/or modify it 6 // under the terms of the GNU General Public License version 2 only, as 7 // published by the Free Software Foundation. 8 // 9 // This code is distributed in the hope that it will be useful, but WITHOUT 10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 // version 2 for more details (a copy is included in the LICENSE file that 13 // accompanied this code). 14 // 15 // You should have received a copy of the GNU General Public License version 16 // 2 along with this work; if not, write to the Free Software Foundation, 17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 // 19 // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 20 // CA 95054 USA or visit www.sun.com if you need additional information or 21 // have any questions. 22 // 23 // 24 25 // SPARC Architecture Description File 26 27 //----------REGISTER DEFINITION BLOCK------------------------------------------ 28 // This information is used by the matcher and the register allocator to 29 // describe individual registers and classes of registers within the target 30 // archtecture. 31 register %{ 32 //----------Architecture Description Register Definitions---------------------- 33 // General Registers 34 // "reg_def" name ( register save type, C convention save type, 35 // ideal register type, encoding, vm name ); 36 // Register Save Types: 37 // 38 // NS = No-Save: The register allocator assumes that these registers 39 // can be used without saving upon entry to the method, & 40 // that they do not need to be saved at call sites. 41 // 42 // SOC = Save-On-Call: The register allocator assumes that these registers 43 // can be used without saving upon entry to the method, 44 // but that they must be saved at call sites. 45 // 46 // SOE = Save-On-Entry: The register allocator assumes that these registers 47 // must be saved before using them upon entry to the 48 // method, but they do not need to be saved at call 49 // sites. 50 // 51 // AS = Always-Save: The register allocator assumes that these registers 52 // must be saved before using them upon entry to the 53 // method, & that they must be saved at call sites. 54 // 55 // Ideal Register Type is used to determine how to save & restore a 56 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get 57 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI. 58 // 59 // The encoding number is the actual bit-pattern placed into the opcodes. 60 61 62 // ---------------------------- 63 // Integer/Long Registers 64 // ---------------------------- 65 66 // Need to expose the hi/lo aspect of 64-bit registers 67 // This register set is used for both the 64-bit build and 68 // the 32-bit build with 1-register longs. 69 70 // Global Registers 0-7 71 reg_def R_G0H( NS, NS, Op_RegI,128, G0->as_VMReg()->next()); 72 reg_def R_G0 ( NS, NS, Op_RegI, 0, G0->as_VMReg()); 73 reg_def R_G1H(SOC, SOC, Op_RegI,129, G1->as_VMReg()->next()); 74 reg_def R_G1 (SOC, SOC, Op_RegI, 1, G1->as_VMReg()); 75 reg_def R_G2H( NS, NS, Op_RegI,130, G2->as_VMReg()->next()); 76 reg_def R_G2 ( NS, NS, Op_RegI, 2, G2->as_VMReg()); 77 reg_def R_G3H(SOC, SOC, Op_RegI,131, G3->as_VMReg()->next()); 78 reg_def R_G3 (SOC, SOC, Op_RegI, 3, G3->as_VMReg()); 79 reg_def R_G4H(SOC, SOC, Op_RegI,132, G4->as_VMReg()->next()); 80 reg_def R_G4 (SOC, SOC, Op_RegI, 4, G4->as_VMReg()); 81 reg_def R_G5H(SOC, SOC, Op_RegI,133, G5->as_VMReg()->next()); 82 reg_def R_G5 (SOC, SOC, Op_RegI, 5, G5->as_VMReg()); 83 reg_def R_G6H( NS, NS, Op_RegI,134, G6->as_VMReg()->next()); 84 reg_def R_G6 ( NS, NS, Op_RegI, 6, G6->as_VMReg()); 85 reg_def R_G7H( NS, NS, Op_RegI,135, G7->as_VMReg()->next()); 86 reg_def R_G7 ( NS, NS, Op_RegI, 7, G7->as_VMReg()); 87 88 // Output Registers 0-7 89 reg_def R_O0H(SOC, SOC, Op_RegI,136, O0->as_VMReg()->next()); 90 reg_def R_O0 (SOC, SOC, Op_RegI, 8, O0->as_VMReg()); 91 reg_def R_O1H(SOC, SOC, Op_RegI,137, O1->as_VMReg()->next()); 92 reg_def R_O1 (SOC, SOC, Op_RegI, 9, O1->as_VMReg()); 93 reg_def R_O2H(SOC, SOC, Op_RegI,138, O2->as_VMReg()->next()); 94 reg_def R_O2 (SOC, SOC, Op_RegI, 10, O2->as_VMReg()); 95 reg_def R_O3H(SOC, SOC, Op_RegI,139, O3->as_VMReg()->next()); 96 reg_def R_O3 (SOC, SOC, Op_RegI, 11, O3->as_VMReg()); 97 reg_def R_O4H(SOC, SOC, Op_RegI,140, O4->as_VMReg()->next()); 98 reg_def R_O4 (SOC, SOC, Op_RegI, 12, O4->as_VMReg()); 99 reg_def R_O5H(SOC, SOC, Op_RegI,141, O5->as_VMReg()->next()); 100 reg_def R_O5 (SOC, SOC, Op_RegI, 13, O5->as_VMReg()); 101 reg_def R_SPH( NS, NS, Op_RegI,142, SP->as_VMReg()->next()); 102 reg_def R_SP ( NS, NS, Op_RegI, 14, SP->as_VMReg()); 103 reg_def R_O7H(SOC, SOC, Op_RegI,143, O7->as_VMReg()->next()); 104 reg_def R_O7 (SOC, SOC, Op_RegI, 15, O7->as_VMReg()); 105 106 // Local Registers 0-7 107 reg_def R_L0H( NS, NS, Op_RegI,144, L0->as_VMReg()->next()); 108 reg_def R_L0 ( NS, NS, Op_RegI, 16, L0->as_VMReg()); 109 reg_def R_L1H( NS, NS, Op_RegI,145, L1->as_VMReg()->next()); 110 reg_def R_L1 ( NS, NS, Op_RegI, 17, L1->as_VMReg()); 111 reg_def R_L2H( NS, NS, Op_RegI,146, L2->as_VMReg()->next()); 112 reg_def R_L2 ( NS, NS, Op_RegI, 18, L2->as_VMReg()); 113 reg_def R_L3H( NS, NS, Op_RegI,147, L3->as_VMReg()->next()); 114 reg_def R_L3 ( NS, NS, Op_RegI, 19, L3->as_VMReg()); 115 reg_def R_L4H( NS, NS, Op_RegI,148, L4->as_VMReg()->next()); 116 reg_def R_L4 ( NS, NS, Op_RegI, 20, L4->as_VMReg()); 117 reg_def R_L5H( NS, NS, Op_RegI,149, L5->as_VMReg()->next()); 118 reg_def R_L5 ( NS, NS, Op_RegI, 21, L5->as_VMReg()); 119 reg_def R_L6H( NS, NS, Op_RegI,150, L6->as_VMReg()->next()); 120 reg_def R_L6 ( NS, NS, Op_RegI, 22, L6->as_VMReg()); 121 reg_def R_L7H( NS, NS, Op_RegI,151, L7->as_VMReg()->next()); 122 reg_def R_L7 ( NS, NS, Op_RegI, 23, L7->as_VMReg()); 123 124 // Input Registers 0-7 125 reg_def R_I0H( NS, NS, Op_RegI,152, I0->as_VMReg()->next()); 126 reg_def R_I0 ( NS, NS, Op_RegI, 24, I0->as_VMReg()); 127 reg_def R_I1H( NS, NS, Op_RegI,153, I1->as_VMReg()->next()); 128 reg_def R_I1 ( NS, NS, Op_RegI, 25, I1->as_VMReg()); 129 reg_def R_I2H( NS, NS, Op_RegI,154, I2->as_VMReg()->next()); 130 reg_def R_I2 ( NS, NS, Op_RegI, 26, I2->as_VMReg()); 131 reg_def R_I3H( NS, NS, Op_RegI,155, I3->as_VMReg()->next()); 132 reg_def R_I3 ( NS, NS, Op_RegI, 27, I3->as_VMReg()); 133 reg_def R_I4H( NS, NS, Op_RegI,156, I4->as_VMReg()->next()); 134 reg_def R_I4 ( NS, NS, Op_RegI, 28, I4->as_VMReg()); 135 reg_def R_I5H( NS, NS, Op_RegI,157, I5->as_VMReg()->next()); 136 reg_def R_I5 ( NS, NS, Op_RegI, 29, I5->as_VMReg()); 137 reg_def R_FPH( NS, NS, Op_RegI,158, FP->as_VMReg()->next()); 138 reg_def R_FP ( NS, NS, Op_RegI, 30, FP->as_VMReg()); 139 reg_def R_I7H( NS, NS, Op_RegI,159, I7->as_VMReg()->next()); 140 reg_def R_I7 ( NS, NS, Op_RegI, 31, I7->as_VMReg()); 141 142 // ---------------------------- 143 // Float/Double Registers 144 // ---------------------------- 145 146 // Float Registers 147 reg_def R_F0 ( SOC, SOC, Op_RegF, 0, F0->as_VMReg()); 148 reg_def R_F1 ( SOC, SOC, Op_RegF, 1, F1->as_VMReg()); 149 reg_def R_F2 ( SOC, SOC, Op_RegF, 2, F2->as_VMReg()); 150 reg_def R_F3 ( SOC, SOC, Op_RegF, 3, F3->as_VMReg()); 151 reg_def R_F4 ( SOC, SOC, Op_RegF, 4, F4->as_VMReg()); 152 reg_def R_F5 ( SOC, SOC, Op_RegF, 5, F5->as_VMReg()); 153 reg_def R_F6 ( SOC, SOC, Op_RegF, 6, F6->as_VMReg()); 154 reg_def R_F7 ( SOC, SOC, Op_RegF, 7, F7->as_VMReg()); 155 reg_def R_F8 ( SOC, SOC, Op_RegF, 8, F8->as_VMReg()); 156 reg_def R_F9 ( SOC, SOC, Op_RegF, 9, F9->as_VMReg()); 157 reg_def R_F10( SOC, SOC, Op_RegF, 10, F10->as_VMReg()); 158 reg_def R_F11( SOC, SOC, Op_RegF, 11, F11->as_VMReg()); 159 reg_def R_F12( SOC, SOC, Op_RegF, 12, F12->as_VMReg()); 160 reg_def R_F13( SOC, SOC, Op_RegF, 13, F13->as_VMReg()); 161 reg_def R_F14( SOC, SOC, Op_RegF, 14, F14->as_VMReg()); 162 reg_def R_F15( SOC, SOC, Op_RegF, 15, F15->as_VMReg()); 163 reg_def R_F16( SOC, SOC, Op_RegF, 16, F16->as_VMReg()); 164 reg_def R_F17( SOC, SOC, Op_RegF, 17, F17->as_VMReg()); 165 reg_def R_F18( SOC, SOC, Op_RegF, 18, F18->as_VMReg()); 166 reg_def R_F19( SOC, SOC, Op_RegF, 19, F19->as_VMReg()); 167 reg_def R_F20( SOC, SOC, Op_RegF, 20, F20->as_VMReg()); 168 reg_def R_F21( SOC, SOC, Op_RegF, 21, F21->as_VMReg()); 169 reg_def R_F22( SOC, SOC, Op_RegF, 22, F22->as_VMReg()); 170 reg_def R_F23( SOC, SOC, Op_RegF, 23, F23->as_VMReg()); 171 reg_def R_F24( SOC, SOC, Op_RegF, 24, F24->as_VMReg()); 172 reg_def R_F25( SOC, SOC, Op_RegF, 25, F25->as_VMReg()); 173 reg_def R_F26( SOC, SOC, Op_RegF, 26, F26->as_VMReg()); 174 reg_def R_F27( SOC, SOC, Op_RegF, 27, F27->as_VMReg()); 175 reg_def R_F28( SOC, SOC, Op_RegF, 28, F28->as_VMReg()); 176 reg_def R_F29( SOC, SOC, Op_RegF, 29, F29->as_VMReg()); 177 reg_def R_F30( SOC, SOC, Op_RegF, 30, F30->as_VMReg()); 178 reg_def R_F31( SOC, SOC, Op_RegF, 31, F31->as_VMReg()); 179 180 // Double Registers 181 // The rules of ADL require that double registers be defined in pairs. 182 // Each pair must be two 32-bit values, but not necessarily a pair of 183 // single float registers. In each pair, ADLC-assigned register numbers 184 // must be adjacent, with the lower number even. Finally, when the 185 // CPU stores such a register pair to memory, the word associated with 186 // the lower ADLC-assigned number must be stored to the lower address. 187 188 // These definitions specify the actual bit encodings of the sparc 189 // double fp register numbers. FloatRegisterImpl in register_sparc.hpp 190 // wants 0-63, so we have to convert every time we want to use fp regs 191 // with the macroassembler, using reg_to_DoubleFloatRegister_object(). 192 // 255 is a flag meaning "don't go here". 193 // I believe we can't handle callee-save doubles D32 and up until 194 // the place in the sparc stack crawler that asserts on the 255 is 195 // fixed up. 196 reg_def R_D32x(SOC, SOC, Op_RegD,255, F32->as_VMReg()); 197 reg_def R_D32 (SOC, SOC, Op_RegD, 1, F32->as_VMReg()->next()); 198 reg_def R_D34x(SOC, SOC, Op_RegD,255, F34->as_VMReg()); 199 reg_def R_D34 (SOC, SOC, Op_RegD, 3, F34->as_VMReg()->next()); 200 reg_def R_D36x(SOC, SOC, Op_RegD,255, F36->as_VMReg()); 201 reg_def R_D36 (SOC, SOC, Op_RegD, 5, F36->as_VMReg()->next()); 202 reg_def R_D38x(SOC, SOC, Op_RegD,255, F38->as_VMReg()); 203 reg_def R_D38 (SOC, SOC, Op_RegD, 7, F38->as_VMReg()->next()); 204 reg_def R_D40x(SOC, SOC, Op_RegD,255, F40->as_VMReg()); 205 reg_def R_D40 (SOC, SOC, Op_RegD, 9, F40->as_VMReg()->next()); 206 reg_def R_D42x(SOC, SOC, Op_RegD,255, F42->as_VMReg()); 207 reg_def R_D42 (SOC, SOC, Op_RegD, 11, F42->as_VMReg()->next()); 208 reg_def R_D44x(SOC, SOC, Op_RegD,255, F44->as_VMReg()); 209 reg_def R_D44 (SOC, SOC, Op_RegD, 13, F44->as_VMReg()->next()); 210 reg_def R_D46x(SOC, SOC, Op_RegD,255, F46->as_VMReg()); 211 reg_def R_D46 (SOC, SOC, Op_RegD, 15, F46->as_VMReg()->next()); 212 reg_def R_D48x(SOC, SOC, Op_RegD,255, F48->as_VMReg()); 213 reg_def R_D48 (SOC, SOC, Op_RegD, 17, F48->as_VMReg()->next()); 214 reg_def R_D50x(SOC, SOC, Op_RegD,255, F50->as_VMReg()); 215 reg_def R_D50 (SOC, SOC, Op_RegD, 19, F50->as_VMReg()->next()); 216 reg_def R_D52x(SOC, SOC, Op_RegD,255, F52->as_VMReg()); 217 reg_def R_D52 (SOC, SOC, Op_RegD, 21, F52->as_VMReg()->next()); 218 reg_def R_D54x(SOC, SOC, Op_RegD,255, F54->as_VMReg()); 219 reg_def R_D54 (SOC, SOC, Op_RegD, 23, F54->as_VMReg()->next()); 220 reg_def R_D56x(SOC, SOC, Op_RegD,255, F56->as_VMReg()); 221 reg_def R_D56 (SOC, SOC, Op_RegD, 25, F56->as_VMReg()->next()); 222 reg_def R_D58x(SOC, SOC, Op_RegD,255, F58->as_VMReg()); 223 reg_def R_D58 (SOC, SOC, Op_RegD, 27, F58->as_VMReg()->next()); 224 reg_def R_D60x(SOC, SOC, Op_RegD,255, F60->as_VMReg()); 225 reg_def R_D60 (SOC, SOC, Op_RegD, 29, F60->as_VMReg()->next()); 226 reg_def R_D62x(SOC, SOC, Op_RegD,255, F62->as_VMReg()); 227 reg_def R_D62 (SOC, SOC, Op_RegD, 31, F62->as_VMReg()->next()); 228 229 230 // ---------------------------- 231 // Special Registers 232 // Condition Codes Flag Registers 233 // I tried to break out ICC and XCC but it's not very pretty. 234 // Every Sparc instruction which defs/kills one also kills the other. 235 // Hence every compare instruction which defs one kind of flags ends 236 // up needing a kill of the other. 237 reg_def CCR (SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad()); 238 239 reg_def FCC0(SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad()); 240 reg_def FCC1(SOC, SOC, Op_RegFlags, 1, VMRegImpl::Bad()); 241 reg_def FCC2(SOC, SOC, Op_RegFlags, 2, VMRegImpl::Bad()); 242 reg_def FCC3(SOC, SOC, Op_RegFlags, 3, VMRegImpl::Bad()); 243 244 // ---------------------------- 245 // Specify the enum values for the registers. These enums are only used by the 246 // OptoReg "class". We can convert these enum values at will to VMReg when needed 247 // for visibility to the rest of the vm. The order of this enum influences the 248 // register allocator so having the freedom to set this order and not be stuck 249 // with the order that is natural for the rest of the vm is worth it. 250 alloc_class chunk0( 251 R_L0,R_L0H, R_L1,R_L1H, R_L2,R_L2H, R_L3,R_L3H, R_L4,R_L4H, R_L5,R_L5H, R_L6,R_L6H, R_L7,R_L7H, 252 R_G0,R_G0H, R_G1,R_G1H, R_G2,R_G2H, R_G3,R_G3H, R_G4,R_G4H, R_G5,R_G5H, R_G6,R_G6H, R_G7,R_G7H, 253 R_O7,R_O7H, R_SP,R_SPH, R_O0,R_O0H, R_O1,R_O1H, R_O2,R_O2H, R_O3,R_O3H, R_O4,R_O4H, R_O5,R_O5H, 254 R_I0,R_I0H, R_I1,R_I1H, R_I2,R_I2H, R_I3,R_I3H, R_I4,R_I4H, R_I5,R_I5H, R_FP,R_FPH, R_I7,R_I7H); 255 256 // Note that a register is not allocatable unless it is also mentioned 257 // in a widely-used reg_class below. Thus, R_G7 and R_G0 are outside i_reg. 258 259 alloc_class chunk1( 260 // The first registers listed here are those most likely to be used 261 // as temporaries. We move F0..F7 away from the front of the list, 262 // to reduce the likelihood of interferences with parameters and 263 // return values. Likewise, we avoid using F0/F1 for parameters, 264 // since they are used for return values. 265 // This FPU fine-tuning is worth about 1% on the SPEC geomean. 266 R_F8 ,R_F9 ,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15, 267 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23, 268 R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,R_F30,R_F31, 269 R_F0 ,R_F1 ,R_F2 ,R_F3 ,R_F4 ,R_F5 ,R_F6 ,R_F7 , // used for arguments and return values 270 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x, 271 R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x, 272 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x, 273 R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x); 274 275 alloc_class chunk2(CCR, FCC0, FCC1, FCC2, FCC3); 276 277 //----------Architecture Description Register Classes-------------------------- 278 // Several register classes are automatically defined based upon information in 279 // this architecture description. 280 // 1) reg_class inline_cache_reg ( as defined in frame section ) 281 // 2) reg_class interpreter_method_oop_reg ( as defined in frame section ) 282 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ ) 283 // 284 285 // G0 is not included in integer class since it has special meaning. 286 reg_class g0_reg(R_G0); 287 288 // ---------------------------- 289 // Integer Register Classes 290 // ---------------------------- 291 // Exclusions from i_reg: 292 // R_G0: hardwired zero 293 // R_G2: reserved by HotSpot to the TLS register (invariant within Java) 294 // R_G6: reserved by Solaris ABI to tools 295 // R_G7: reserved by Solaris ABI to libthread 296 // R_O7: Used as a temp in many encodings 297 reg_class int_reg(R_G1,R_G3,R_G4,R_G5,R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); 298 299 // Class for all integer registers, except the G registers. This is used for 300 // encodings which use G registers as temps. The regular inputs to such 301 // instructions use a "notemp_" prefix, as a hack to ensure that the allocator 302 // will not put an input into a temp register. 303 reg_class notemp_int_reg(R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); 304 305 reg_class g1_regI(R_G1); 306 reg_class g3_regI(R_G3); 307 reg_class g4_regI(R_G4); 308 reg_class o0_regI(R_O0); 309 reg_class o7_regI(R_O7); 310 311 // ---------------------------- 312 // Pointer Register Classes 313 // ---------------------------- 314 #ifdef _LP64 315 // 64-bit build means 64-bit pointers means hi/lo pairs 316 reg_class ptr_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5, 317 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, 318 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7, 319 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 ); 320 // Lock encodings use G3 and G4 internally 321 reg_class lock_ptr_reg( R_G1H,R_G1, R_G5H,R_G5, 322 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, 323 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7, 324 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 ); 325 // Special class for storeP instructions, which can store SP or RPC to TLS. 326 // It is also used for memory addressing, allowing direct TLS addressing. 327 reg_class sp_ptr_reg( R_G1H,R_G1, R_G2H,R_G2, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5, 328 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, R_SPH,R_SP, 329 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7, 330 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5, R_FPH,R_FP ); 331 // R_L7 is the lowest-priority callee-save (i.e., NS) register 332 // We use it to save R_G2 across calls out of Java. 333 reg_class l7_regP(R_L7H,R_L7); 334 335 // Other special pointer regs 336 reg_class g1_regP(R_G1H,R_G1); 337 reg_class g2_regP(R_G2H,R_G2); 338 reg_class g3_regP(R_G3H,R_G3); 339 reg_class g4_regP(R_G4H,R_G4); 340 reg_class g5_regP(R_G5H,R_G5); 341 reg_class i0_regP(R_I0H,R_I0); 342 reg_class o0_regP(R_O0H,R_O0); 343 reg_class o1_regP(R_O1H,R_O1); 344 reg_class o2_regP(R_O2H,R_O2); 345 reg_class o7_regP(R_O7H,R_O7); 346 347 #else // _LP64 348 // 32-bit build means 32-bit pointers means 1 register. 349 reg_class ptr_reg( R_G1, R_G3,R_G4,R_G5, 350 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5, 351 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7, 352 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); 353 // Lock encodings use G3 and G4 internally 354 reg_class lock_ptr_reg(R_G1, R_G5, 355 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5, 356 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7, 357 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); 358 // Special class for storeP instructions, which can store SP or RPC to TLS. 359 // It is also used for memory addressing, allowing direct TLS addressing. 360 reg_class sp_ptr_reg( R_G1,R_G2,R_G3,R_G4,R_G5, 361 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_SP, 362 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7, 363 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5,R_FP); 364 // R_L7 is the lowest-priority callee-save (i.e., NS) register 365 // We use it to save R_G2 across calls out of Java. 366 reg_class l7_regP(R_L7); 367 368 // Other special pointer regs 369 reg_class g1_regP(R_G1); 370 reg_class g2_regP(R_G2); 371 reg_class g3_regP(R_G3); 372 reg_class g4_regP(R_G4); 373 reg_class g5_regP(R_G5); 374 reg_class i0_regP(R_I0); 375 reg_class o0_regP(R_O0); 376 reg_class o1_regP(R_O1); 377 reg_class o2_regP(R_O2); 378 reg_class o7_regP(R_O7); 379 #endif // _LP64 380 381 382 // ---------------------------- 383 // Long Register Classes 384 // ---------------------------- 385 // Longs in 1 register. Aligned adjacent hi/lo pairs. 386 // Note: O7 is never in this class; it is sometimes used as an encoding temp. 387 reg_class long_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5 388 ,R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5 389 #ifdef _LP64 390 // 64-bit, longs in 1 register: use all 64-bit integer registers 391 // 32-bit, longs in 1 register: cannot use I's and L's. Restrict to O's and G's. 392 ,R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7 393 ,R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 394 #endif // _LP64 395 ); 396 397 reg_class g1_regL(R_G1H,R_G1); 398 reg_class g3_regL(R_G3H,R_G3); 399 reg_class o2_regL(R_O2H,R_O2); 400 reg_class o7_regL(R_O7H,R_O7); 401 402 // ---------------------------- 403 // Special Class for Condition Code Flags Register 404 reg_class int_flags(CCR); 405 reg_class float_flags(FCC0,FCC1,FCC2,FCC3); 406 reg_class float_flag0(FCC0); 407 408 409 // ---------------------------- 410 // Float Point Register Classes 411 // ---------------------------- 412 // Skip F30/F31, they are reserved for mem-mem copies 413 reg_class sflt_reg(R_F0,R_F1,R_F2,R_F3,R_F4,R_F5,R_F6,R_F7,R_F8,R_F9,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29); 414 415 // Paired floating point registers--they show up in the same order as the floats, 416 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs. 417 reg_class dflt_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15, 418 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29, 419 /* Use extra V9 double registers; this AD file does not support V8 */ 420 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x, 421 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x 422 ); 423 424 // Paired floating point registers--they show up in the same order as the floats, 425 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs. 426 // This class is usable for mis-aligned loads as happen in I2C adapters. 427 reg_class dflt_low_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15, 428 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,R_F30,R_F31 ); 429 %} 430 431 //----------DEFINITION BLOCK--------------------------------------------------- 432 // Define name --> value mappings to inform the ADLC of an integer valued name 433 // Current support includes integer values in the range [0, 0x7FFFFFFF] 434 // Format: 435 // int_def <name> ( <int_value>, <expression>); 436 // Generated Code in ad_<arch>.hpp 437 // #define <name> (<expression>) 438 // // value == <int_value> 439 // Generated code in ad_<arch>.cpp adlc_verification() 440 // assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>"); 441 // 442 definitions %{ 443 // The default cost (of an ALU instruction). 444 int_def DEFAULT_COST ( 100, 100); 445 int_def HUGE_COST (1000000, 1000000); 446 447 // Memory refs are twice as expensive as run-of-the-mill. 448 int_def MEMORY_REF_COST ( 200, DEFAULT_COST * 2); 449 450 // Branches are even more expensive. 451 int_def BRANCH_COST ( 300, DEFAULT_COST * 3); 452 int_def CALL_COST ( 300, DEFAULT_COST * 3); 453 %} 454 455 456 //----------SOURCE BLOCK------------------------------------------------------- 457 // This is a block of C++ code which provides values, functions, and 458 // definitions necessary in the rest of the architecture description 459 source_hpp %{ 460 // Must be visible to the DFA in dfa_sparc.cpp 461 extern bool can_branch_register( Node *bol, Node *cmp ); 462 463 // Macros to extract hi & lo halves from a long pair. 464 // G0 is not part of any long pair, so assert on that. 465 // Prevents accidentally using G1 instead of G0. 466 #define LONG_HI_REG(x) (x) 467 #define LONG_LO_REG(x) (x) 468 469 %} 470 471 source %{ 472 #define __ _masm. 473 474 // tertiary op of a LoadP or StoreP encoding 475 #define REGP_OP true 476 477 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding); 478 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding); 479 static Register reg_to_register_object(int register_encoding); 480 481 // Used by the DFA in dfa_sparc.cpp. 482 // Check for being able to use a V9 branch-on-register. Requires a 483 // compare-vs-zero, equal/not-equal, of a value which was zero- or sign- 484 // extended. Doesn't work following an integer ADD, for example, because of 485 // overflow (-1 incremented yields 0 plus a carry in the high-order word). On 486 // 32-bit V9 systems, interrupts currently blow away the high-order 32 bits and 487 // replace them with zero, which could become sign-extension in a different OS 488 // release. There's no obvious reason why an interrupt will ever fill these 489 // bits with non-zero junk (the registers are reloaded with standard LD 490 // instructions which either zero-fill or sign-fill). 491 bool can_branch_register( Node *bol, Node *cmp ) { 492 if( !BranchOnRegister ) return false; 493 #ifdef _LP64 494 if( cmp->Opcode() == Op_CmpP ) 495 return true; // No problems with pointer compares 496 #endif 497 if( cmp->Opcode() == Op_CmpL ) 498 return true; // No problems with long compares 499 500 if( !SparcV9RegsHiBitsZero ) return false; 501 if( bol->as_Bool()->_test._test != BoolTest::ne && 502 bol->as_Bool()->_test._test != BoolTest::eq ) 503 return false; 504 505 // Check for comparing against a 'safe' value. Any operation which 506 // clears out the high word is safe. Thus, loads and certain shifts 507 // are safe, as are non-negative constants. Any operation which 508 // preserves zero bits in the high word is safe as long as each of its 509 // inputs are safe. Thus, phis and bitwise booleans are safe if their 510 // inputs are safe. At present, the only important case to recognize 511 // seems to be loads. Constants should fold away, and shifts & 512 // logicals can use the 'cc' forms. 513 Node *x = cmp->in(1); 514 if( x->is_Load() ) return true; 515 if( x->is_Phi() ) { 516 for( uint i = 1; i < x->req(); i++ ) 517 if( !x->in(i)->is_Load() ) 518 return false; 519 return true; 520 } 521 return false; 522 } 523 524 // **************************************************************************** 525 526 // REQUIRED FUNCTIONALITY 527 528 // !!!!! Special hack to get all type of calls to specify the byte offset 529 // from the start of the call to the point where the return address 530 // will point. 531 // The "return address" is the address of the call instruction, plus 8. 532 533 int MachCallStaticJavaNode::ret_addr_offset() { 534 return NativeCall::instruction_size; // call; delay slot 535 } 536 537 int MachCallDynamicJavaNode::ret_addr_offset() { 538 int vtable_index = this->_vtable_index; 539 if (vtable_index < 0) { 540 // must be invalid_vtable_index, not nonvirtual_vtable_index 541 assert(vtable_index == methodOopDesc::invalid_vtable_index, "correct sentinel value"); 542 return (NativeMovConstReg::instruction_size + 543 NativeCall::instruction_size); // sethi; setlo; call; delay slot 544 } else { 545 assert(!UseInlineCaches, "expect vtable calls only if not using ICs"); 546 int entry_offset = instanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size(); 547 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes(); 548 int klass_load_size; 549 if (UseCompressedOops) { 550 assert(Universe::heap() != NULL, "java heap should be initialized"); 551 if (Universe::narrow_oop_base() == NULL) 552 klass_load_size = 2*BytesPerInstWord; // see MacroAssembler::load_klass() 553 else 554 klass_load_size = 3*BytesPerInstWord; 555 } else { 556 klass_load_size = 1*BytesPerInstWord; 557 } 558 if( Assembler::is_simm13(v_off) ) { 559 return klass_load_size + 560 (2*BytesPerInstWord + // ld_ptr, ld_ptr 561 NativeCall::instruction_size); // call; delay slot 562 } else { 563 return klass_load_size + 564 (4*BytesPerInstWord + // set_hi, set, ld_ptr, ld_ptr 565 NativeCall::instruction_size); // call; delay slot 566 } 567 } 568 } 569 570 int MachCallRuntimeNode::ret_addr_offset() { 571 #ifdef _LP64 572 return NativeFarCall::instruction_size; // farcall; delay slot 573 #else 574 return NativeCall::instruction_size; // call; delay slot 575 #endif 576 } 577 578 // Indicate if the safepoint node needs the polling page as an input. 579 // Since Sparc does not have absolute addressing, it does. 580 bool SafePointNode::needs_polling_address_input() { 581 return true; 582 } 583 584 // emit an interrupt that is caught by the debugger (for debugging compiler) 585 void emit_break(CodeBuffer &cbuf) { 586 MacroAssembler _masm(&cbuf); 587 __ breakpoint_trap(); 588 } 589 590 #ifndef PRODUCT 591 void MachBreakpointNode::format( PhaseRegAlloc *, outputStream *st ) const { 592 st->print("TA"); 593 } 594 #endif 595 596 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 597 emit_break(cbuf); 598 } 599 600 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const { 601 return MachNode::size(ra_); 602 } 603 604 // Traceable jump 605 void emit_jmpl(CodeBuffer &cbuf, int jump_target) { 606 MacroAssembler _masm(&cbuf); 607 Register rdest = reg_to_register_object(jump_target); 608 __ JMP(rdest, 0); 609 __ delayed()->nop(); 610 } 611 612 // Traceable jump and set exception pc 613 void emit_jmpl_set_exception_pc(CodeBuffer &cbuf, int jump_target) { 614 MacroAssembler _masm(&cbuf); 615 Register rdest = reg_to_register_object(jump_target); 616 __ JMP(rdest, 0); 617 __ delayed()->add(O7, frame::pc_return_offset, Oissuing_pc ); 618 } 619 620 void emit_nop(CodeBuffer &cbuf) { 621 MacroAssembler _masm(&cbuf); 622 __ nop(); 623 } 624 625 void emit_illtrap(CodeBuffer &cbuf) { 626 MacroAssembler _masm(&cbuf); 627 __ illtrap(0); 628 } 629 630 631 intptr_t get_offset_from_base(const MachNode* n, const TypePtr* atype, int disp32) { 632 assert(n->rule() != loadUB_rule, ""); 633 634 intptr_t offset = 0; 635 const TypePtr *adr_type = TYPE_PTR_SENTINAL; // Check for base==RegI, disp==immP 636 const Node* addr = n->get_base_and_disp(offset, adr_type); 637 assert(adr_type == (const TypePtr*)-1, "VerifyOops: no support for sparc operands with base==RegI, disp==immP"); 638 assert(addr != NULL && addr != (Node*)-1, "invalid addr"); 639 assert(addr->bottom_type()->isa_oopptr() == atype, ""); 640 atype = atype->add_offset(offset); 641 assert(disp32 == offset, "wrong disp32"); 642 return atype->_offset; 643 } 644 645 646 intptr_t get_offset_from_base_2(const MachNode* n, const TypePtr* atype, int disp32) { 647 assert(n->rule() != loadUB_rule, ""); 648 649 intptr_t offset = 0; 650 Node* addr = n->in(2); 651 assert(addr->bottom_type()->isa_oopptr() == atype, ""); 652 if (addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP) { 653 Node* a = addr->in(2/*AddPNode::Address*/); 654 Node* o = addr->in(3/*AddPNode::Offset*/); 655 offset = o->is_Con() ? o->bottom_type()->is_intptr_t()->get_con() : Type::OffsetBot; 656 atype = a->bottom_type()->is_ptr()->add_offset(offset); 657 assert(atype->isa_oop_ptr(), "still an oop"); 658 } 659 offset = atype->is_ptr()->_offset; 660 if (offset != Type::OffsetBot) offset += disp32; 661 return offset; 662 } 663 664 // Standard Sparc opcode form2 field breakdown 665 static inline void emit2_19(CodeBuffer &cbuf, int f30, int f29, int f25, int f22, int f20, int f19, int f0 ) { 666 f0 &= (1<<19)-1; // Mask displacement to 19 bits 667 int op = (f30 << 30) | 668 (f29 << 29) | 669 (f25 << 25) | 670 (f22 << 22) | 671 (f20 << 20) | 672 (f19 << 19) | 673 (f0 << 0); 674 *((int*)(cbuf.code_end())) = op; 675 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); 676 } 677 678 // Standard Sparc opcode form2 field breakdown 679 static inline void emit2_22(CodeBuffer &cbuf, int f30, int f25, int f22, int f0 ) { 680 f0 >>= 10; // Drop 10 bits 681 f0 &= (1<<22)-1; // Mask displacement to 22 bits 682 int op = (f30 << 30) | 683 (f25 << 25) | 684 (f22 << 22) | 685 (f0 << 0); 686 *((int*)(cbuf.code_end())) = op; 687 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); 688 } 689 690 // Standard Sparc opcode form3 field breakdown 691 static inline void emit3(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int f5, int f0 ) { 692 int op = (f30 << 30) | 693 (f25 << 25) | 694 (f19 << 19) | 695 (f14 << 14) | 696 (f5 << 5) | 697 (f0 << 0); 698 *((int*)(cbuf.code_end())) = op; 699 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); 700 } 701 702 // Standard Sparc opcode form3 field breakdown 703 static inline void emit3_simm13(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm13 ) { 704 simm13 &= (1<<13)-1; // Mask to 13 bits 705 int op = (f30 << 30) | 706 (f25 << 25) | 707 (f19 << 19) | 708 (f14 << 14) | 709 (1 << 13) | // bit to indicate immediate-mode 710 (simm13<<0); 711 *((int*)(cbuf.code_end())) = op; 712 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); 713 } 714 715 static inline void emit3_simm10(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm10 ) { 716 simm10 &= (1<<10)-1; // Mask to 10 bits 717 emit3_simm13(cbuf,f30,f25,f19,f14,simm10); 718 } 719 720 #ifdef ASSERT 721 // Helper function for VerifyOops in emit_form3_mem_reg 722 void verify_oops_warning(const MachNode *n, int ideal_op, int mem_op) { 723 warning("VerifyOops encountered unexpected instruction:"); 724 n->dump(2); 725 warning("Instruction has ideal_Opcode==Op_%s and op_ld==Op_%s \n", NodeClassNames[ideal_op], NodeClassNames[mem_op]); 726 } 727 #endif 728 729 730 void emit_form3_mem_reg(CodeBuffer &cbuf, const MachNode* n, int primary, int tertiary, 731 int src1_enc, int disp32, int src2_enc, int dst_enc) { 732 733 #ifdef ASSERT 734 // The following code implements the +VerifyOops feature. 735 // It verifies oop values which are loaded into or stored out of 736 // the current method activation. +VerifyOops complements techniques 737 // like ScavengeALot, because it eagerly inspects oops in transit, 738 // as they enter or leave the stack, as opposed to ScavengeALot, 739 // which inspects oops "at rest", in the stack or heap, at safepoints. 740 // For this reason, +VerifyOops can sometimes detect bugs very close 741 // to their point of creation. It can also serve as a cross-check 742 // on the validity of oop maps, when used toegether with ScavengeALot. 743 744 // It would be good to verify oops at other points, especially 745 // when an oop is used as a base pointer for a load or store. 746 // This is presently difficult, because it is hard to know when 747 // a base address is biased or not. (If we had such information, 748 // it would be easy and useful to make a two-argument version of 749 // verify_oop which unbiases the base, and performs verification.) 750 751 assert((uint)tertiary == 0xFFFFFFFF || tertiary == REGP_OP, "valid tertiary"); 752 bool is_verified_oop_base = false; 753 bool is_verified_oop_load = false; 754 bool is_verified_oop_store = false; 755 int tmp_enc = -1; 756 if (VerifyOops && src1_enc != R_SP_enc) { 757 // classify the op, mainly for an assert check 758 int st_op = 0, ld_op = 0; 759 switch (primary) { 760 case Assembler::stb_op3: st_op = Op_StoreB; break; 761 case Assembler::sth_op3: st_op = Op_StoreC; break; 762 case Assembler::stx_op3: // may become StoreP or stay StoreI or StoreD0 763 case Assembler::stw_op3: st_op = Op_StoreI; break; 764 case Assembler::std_op3: st_op = Op_StoreL; break; 765 case Assembler::stf_op3: st_op = Op_StoreF; break; 766 case Assembler::stdf_op3: st_op = Op_StoreD; break; 767 768 case Assembler::ldsb_op3: ld_op = Op_LoadB; break; 769 case Assembler::lduh_op3: ld_op = Op_LoadUS; break; 770 case Assembler::ldsh_op3: ld_op = Op_LoadS; break; 771 case Assembler::ldx_op3: // may become LoadP or stay LoadI 772 case Assembler::ldsw_op3: // may become LoadP or stay LoadI 773 case Assembler::lduw_op3: ld_op = Op_LoadI; break; 774 case Assembler::ldd_op3: ld_op = Op_LoadL; break; 775 case Assembler::ldf_op3: ld_op = Op_LoadF; break; 776 case Assembler::lddf_op3: ld_op = Op_LoadD; break; 777 case Assembler::ldub_op3: ld_op = Op_LoadB; break; 778 case Assembler::prefetch_op3: ld_op = Op_LoadI; break; 779 780 default: ShouldNotReachHere(); 781 } 782 if (tertiary == REGP_OP) { 783 if (st_op == Op_StoreI) st_op = Op_StoreP; 784 else if (ld_op == Op_LoadI) ld_op = Op_LoadP; 785 else ShouldNotReachHere(); 786 if (st_op) { 787 // a store 788 // inputs are (0:control, 1:memory, 2:address, 3:value) 789 Node* n2 = n->in(3); 790 if (n2 != NULL) { 791 const Type* t = n2->bottom_type(); 792 is_verified_oop_store = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false; 793 } 794 } else { 795 // a load 796 const Type* t = n->bottom_type(); 797 is_verified_oop_load = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false; 798 } 799 } 800 801 if (ld_op) { 802 // a Load 803 // inputs are (0:control, 1:memory, 2:address) 804 if (!(n->ideal_Opcode()==ld_op) && // Following are special cases 805 !(n->ideal_Opcode()==Op_LoadLLocked && ld_op==Op_LoadI) && 806 !(n->ideal_Opcode()==Op_LoadPLocked && ld_op==Op_LoadP) && 807 !(n->ideal_Opcode()==Op_LoadI && ld_op==Op_LoadF) && 808 !(n->ideal_Opcode()==Op_LoadF && ld_op==Op_LoadI) && 809 !(n->ideal_Opcode()==Op_LoadRange && ld_op==Op_LoadI) && 810 !(n->ideal_Opcode()==Op_LoadKlass && ld_op==Op_LoadP) && 811 !(n->ideal_Opcode()==Op_LoadL && ld_op==Op_LoadI) && 812 !(n->ideal_Opcode()==Op_LoadL_unaligned && ld_op==Op_LoadI) && 813 !(n->ideal_Opcode()==Op_LoadD_unaligned && ld_op==Op_LoadF) && 814 !(n->ideal_Opcode()==Op_ConvI2F && ld_op==Op_LoadF) && 815 !(n->ideal_Opcode()==Op_ConvI2D && ld_op==Op_LoadF) && 816 !(n->ideal_Opcode()==Op_PrefetchRead && ld_op==Op_LoadI) && 817 !(n->ideal_Opcode()==Op_PrefetchWrite && ld_op==Op_LoadI) && 818 !(n->rule() == loadUB_rule)) { 819 verify_oops_warning(n, n->ideal_Opcode(), ld_op); 820 } 821 } else if (st_op) { 822 // a Store 823 // inputs are (0:control, 1:memory, 2:address, 3:value) 824 if (!(n->ideal_Opcode()==st_op) && // Following are special cases 825 !(n->ideal_Opcode()==Op_StoreCM && st_op==Op_StoreB) && 826 !(n->ideal_Opcode()==Op_StoreI && st_op==Op_StoreF) && 827 !(n->ideal_Opcode()==Op_StoreF && st_op==Op_StoreI) && 828 !(n->ideal_Opcode()==Op_StoreL && st_op==Op_StoreI) && 829 !(n->ideal_Opcode()==Op_StoreD && st_op==Op_StoreI && n->rule() == storeD0_rule)) { 830 verify_oops_warning(n, n->ideal_Opcode(), st_op); 831 } 832 } 833 834 if (src2_enc == R_G0_enc && n->rule() != loadUB_rule && n->ideal_Opcode() != Op_StoreCM ) { 835 Node* addr = n->in(2); 836 if (!(addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP)) { 837 const TypeOopPtr* atype = addr->bottom_type()->isa_instptr(); // %%% oopptr? 838 if (atype != NULL) { 839 intptr_t offset = get_offset_from_base(n, atype, disp32); 840 intptr_t offset_2 = get_offset_from_base_2(n, atype, disp32); 841 if (offset != offset_2) { 842 get_offset_from_base(n, atype, disp32); 843 get_offset_from_base_2(n, atype, disp32); 844 } 845 assert(offset == offset_2, "different offsets"); 846 if (offset == disp32) { 847 // we now know that src1 is a true oop pointer 848 is_verified_oop_base = true; 849 if (ld_op && src1_enc == dst_enc && ld_op != Op_LoadF && ld_op != Op_LoadD) { 850 if( primary == Assembler::ldd_op3 ) { 851 is_verified_oop_base = false; // Cannot 'ldd' into O7 852 } else { 853 tmp_enc = dst_enc; 854 dst_enc = R_O7_enc; // Load into O7; preserve source oop 855 assert(src1_enc != dst_enc, ""); 856 } 857 } 858 } 859 if (st_op && (( offset == oopDesc::klass_offset_in_bytes()) 860 || offset == oopDesc::mark_offset_in_bytes())) { 861 // loading the mark should not be allowed either, but 862 // we don't check this since it conflicts with InlineObjectHash 863 // usage of LoadINode to get the mark. We could keep the 864 // check if we create a new LoadMarkNode 865 // but do not verify the object before its header is initialized 866 ShouldNotReachHere(); 867 } 868 } 869 } 870 } 871 } 872 #endif 873 874 uint instr; 875 instr = (Assembler::ldst_op << 30) 876 | (dst_enc << 25) 877 | (primary << 19) 878 | (src1_enc << 14); 879 880 uint index = src2_enc; 881 int disp = disp32; 882 883 if (src1_enc == R_SP_enc || src1_enc == R_FP_enc) 884 disp += STACK_BIAS; 885 886 // We should have a compiler bailout here rather than a guarantee. 887 // Better yet would be some mechanism to handle variable-size matches correctly. 888 guarantee(Assembler::is_simm13(disp), "Do not match large constant offsets" ); 889 890 if( disp == 0 ) { 891 // use reg-reg form 892 // bit 13 is already zero 893 instr |= index; 894 } else { 895 // use reg-imm form 896 instr |= 0x00002000; // set bit 13 to one 897 instr |= disp & 0x1FFF; 898 } 899 900 uint *code = (uint*)cbuf.code_end(); 901 *code = instr; 902 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); 903 904 #ifdef ASSERT 905 { 906 MacroAssembler _masm(&cbuf); 907 if (is_verified_oop_base) { 908 __ verify_oop(reg_to_register_object(src1_enc)); 909 } 910 if (is_verified_oop_store) { 911 __ verify_oop(reg_to_register_object(dst_enc)); 912 } 913 if (tmp_enc != -1) { 914 __ mov(O7, reg_to_register_object(tmp_enc)); 915 } 916 if (is_verified_oop_load) { 917 __ verify_oop(reg_to_register_object(dst_enc)); 918 } 919 } 920 #endif 921 } 922 923 void emit_form3_mem_reg_asi(CodeBuffer &cbuf, const MachNode* n, int primary, int tertiary, 924 int src1_enc, int disp32, int src2_enc, int dst_enc, int asi) { 925 926 uint instr; 927 instr = (Assembler::ldst_op << 30) 928 | (dst_enc << 25) 929 | (primary << 19) 930 | (src1_enc << 14); 931 932 int disp = disp32; 933 int index = src2_enc; 934 935 if (src1_enc == R_SP_enc || src1_enc == R_FP_enc) 936 disp += STACK_BIAS; 937 938 // We should have a compiler bailout here rather than a guarantee. 939 // Better yet would be some mechanism to handle variable-size matches correctly. 940 guarantee(Assembler::is_simm13(disp), "Do not match large constant offsets" ); 941 942 if( disp != 0 ) { 943 // use reg-reg form 944 // set src2=R_O7 contains offset 945 index = R_O7_enc; 946 emit3_simm13( cbuf, Assembler::arith_op, index, Assembler::or_op3, 0, disp); 947 } 948 instr |= (asi << 5); 949 instr |= index; 950 uint *code = (uint*)cbuf.code_end(); 951 *code = instr; 952 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); 953 } 954 955 void emit_call_reloc(CodeBuffer &cbuf, intptr_t entry_point, relocInfo::relocType rtype, bool preserve_g2 = false, bool force_far_call = false) { 956 // The method which records debug information at every safepoint 957 // expects the call to be the first instruction in the snippet as 958 // it creates a PcDesc structure which tracks the offset of a call 959 // from the start of the codeBlob. This offset is computed as 960 // code_end() - code_begin() of the code which has been emitted 961 // so far. 962 // In this particular case we have skirted around the problem by 963 // putting the "mov" instruction in the delay slot but the problem 964 // may bite us again at some other point and a cleaner/generic 965 // solution using relocations would be needed. 966 MacroAssembler _masm(&cbuf); 967 __ set_inst_mark(); 968 969 // We flush the current window just so that there is a valid stack copy 970 // the fact that the current window becomes active again instantly is 971 // not a problem there is nothing live in it. 972 973 #ifdef ASSERT 974 int startpos = __ offset(); 975 #endif /* ASSERT */ 976 977 #ifdef _LP64 978 // Calls to the runtime or native may not be reachable from compiled code, 979 // so we generate the far call sequence on 64 bit sparc. 980 // This code sequence is relocatable to any address, even on LP64. 981 if ( force_far_call ) { 982 __ relocate(rtype); 983 AddressLiteral dest(entry_point); 984 __ jumpl_to(dest, O7, O7); 985 } 986 else 987 #endif 988 { 989 __ call((address)entry_point, rtype); 990 } 991 992 if (preserve_g2) __ delayed()->mov(G2, L7); 993 else __ delayed()->nop(); 994 995 if (preserve_g2) __ mov(L7, G2); 996 997 #ifdef ASSERT 998 if (preserve_g2 && (VerifyCompiledCode || VerifyOops)) { 999 #ifdef _LP64 1000 // Trash argument dump slots. 1001 __ set(0xb0b8ac0db0b8ac0d, G1); 1002 __ mov(G1, G5); 1003 __ stx(G1, SP, STACK_BIAS + 0x80); 1004 __ stx(G1, SP, STACK_BIAS + 0x88); 1005 __ stx(G1, SP, STACK_BIAS + 0x90); 1006 __ stx(G1, SP, STACK_BIAS + 0x98); 1007 __ stx(G1, SP, STACK_BIAS + 0xA0); 1008 __ stx(G1, SP, STACK_BIAS + 0xA8); 1009 #else // _LP64 1010 // this is also a native call, so smash the first 7 stack locations, 1011 // and the various registers 1012 1013 // Note: [SP+0x40] is sp[callee_aggregate_return_pointer_sp_offset], 1014 // while [SP+0x44..0x58] are the argument dump slots. 1015 __ set((intptr_t)0xbaadf00d, G1); 1016 __ mov(G1, G5); 1017 __ sllx(G1, 32, G1); 1018 __ or3(G1, G5, G1); 1019 __ mov(G1, G5); 1020 __ stx(G1, SP, 0x40); 1021 __ stx(G1, SP, 0x48); 1022 __ stx(G1, SP, 0x50); 1023 __ stw(G1, SP, 0x58); // Do not trash [SP+0x5C] which is a usable spill slot 1024 #endif // _LP64 1025 } 1026 #endif /*ASSERT*/ 1027 } 1028 1029 //============================================================================= 1030 // REQUIRED FUNCTIONALITY for encoding 1031 void emit_lo(CodeBuffer &cbuf, int val) { } 1032 void emit_hi(CodeBuffer &cbuf, int val) { } 1033 1034 1035 //============================================================================= 1036 1037 #ifndef PRODUCT 1038 void MachPrologNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { 1039 Compile* C = ra_->C; 1040 1041 for (int i = 0; i < OptoPrologueNops; i++) { 1042 st->print_cr("NOP"); st->print("\t"); 1043 } 1044 1045 if( VerifyThread ) { 1046 st->print_cr("Verify_Thread"); st->print("\t"); 1047 } 1048 1049 size_t framesize = C->frame_slots() << LogBytesPerInt; 1050 1051 // Calls to C2R adapters often do not accept exceptional returns. 1052 // We require that their callers must bang for them. But be careful, because 1053 // some VM calls (such as call site linkage) can use several kilobytes of 1054 // stack. But the stack safety zone should account for that. 1055 // See bugs 4446381, 4468289, 4497237. 1056 if (C->need_stack_bang(framesize)) { 1057 st->print_cr("! stack bang"); st->print("\t"); 1058 } 1059 1060 if (Assembler::is_simm13(-framesize)) { 1061 st->print ("SAVE R_SP,-%d,R_SP",framesize); 1062 } else { 1063 st->print_cr("SETHI R_SP,hi%%(-%d),R_G3",framesize); st->print("\t"); 1064 st->print_cr("ADD R_G3,lo%%(-%d),R_G3",framesize); st->print("\t"); 1065 st->print ("SAVE R_SP,R_G3,R_SP"); 1066 } 1067 1068 } 1069 #endif 1070 1071 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1072 Compile* C = ra_->C; 1073 MacroAssembler _masm(&cbuf); 1074 1075 for (int i = 0; i < OptoPrologueNops; i++) { 1076 __ nop(); 1077 } 1078 1079 __ verify_thread(); 1080 1081 size_t framesize = C->frame_slots() << LogBytesPerInt; 1082 assert(framesize >= 16*wordSize, "must have room for reg. save area"); 1083 assert(framesize%(2*wordSize) == 0, "must preserve 2*wordSize alignment"); 1084 1085 // Calls to C2R adapters often do not accept exceptional returns. 1086 // We require that their callers must bang for them. But be careful, because 1087 // some VM calls (such as call site linkage) can use several kilobytes of 1088 // stack. But the stack safety zone should account for that. 1089 // See bugs 4446381, 4468289, 4497237. 1090 if (C->need_stack_bang(framesize)) { 1091 __ generate_stack_overflow_check(framesize); 1092 } 1093 1094 if (Assembler::is_simm13(-framesize)) { 1095 __ save(SP, -framesize, SP); 1096 } else { 1097 __ sethi(-framesize & ~0x3ff, G3); 1098 __ add(G3, -framesize & 0x3ff, G3); 1099 __ save(SP, G3, SP); 1100 } 1101 C->set_frame_complete( __ offset() ); 1102 } 1103 1104 uint MachPrologNode::size(PhaseRegAlloc *ra_) const { 1105 return MachNode::size(ra_); 1106 } 1107 1108 int MachPrologNode::reloc() const { 1109 return 10; // a large enough number 1110 } 1111 1112 //============================================================================= 1113 #ifndef PRODUCT 1114 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { 1115 Compile* C = ra_->C; 1116 1117 if( do_polling() && ra_->C->is_method_compilation() ) { 1118 st->print("SETHI #PollAddr,L0\t! Load Polling address\n\t"); 1119 #ifdef _LP64 1120 st->print("LDX [L0],G0\t!Poll for Safepointing\n\t"); 1121 #else 1122 st->print("LDUW [L0],G0\t!Poll for Safepointing\n\t"); 1123 #endif 1124 } 1125 1126 if( do_polling() ) 1127 st->print("RET\n\t"); 1128 1129 st->print("RESTORE"); 1130 } 1131 #endif 1132 1133 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1134 MacroAssembler _masm(&cbuf); 1135 Compile* C = ra_->C; 1136 1137 __ verify_thread(); 1138 1139 // If this does safepoint polling, then do it here 1140 if( do_polling() && ra_->C->is_method_compilation() ) { 1141 AddressLiteral polling_page(os::get_polling_page()); 1142 __ sethi(polling_page, L0); 1143 __ relocate(relocInfo::poll_return_type); 1144 __ ld_ptr( L0, 0, G0 ); 1145 } 1146 1147 // If this is a return, then stuff the restore in the delay slot 1148 if( do_polling() ) { 1149 __ ret(); 1150 __ delayed()->restore(); 1151 } else { 1152 __ restore(); 1153 } 1154 } 1155 1156 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const { 1157 return MachNode::size(ra_); 1158 } 1159 1160 int MachEpilogNode::reloc() const { 1161 return 16; // a large enough number 1162 } 1163 1164 const Pipeline * MachEpilogNode::pipeline() const { 1165 return MachNode::pipeline_class(); 1166 } 1167 1168 int MachEpilogNode::safepoint_offset() const { 1169 assert( do_polling(), "no return for this epilog node"); 1170 return MacroAssembler::size_of_sethi(os::get_polling_page()); 1171 } 1172 1173 //============================================================================= 1174 1175 // Figure out which register class each belongs in: rc_int, rc_float, rc_stack 1176 enum RC { rc_bad, rc_int, rc_float, rc_stack }; 1177 static enum RC rc_class( OptoReg::Name reg ) { 1178 if( !OptoReg::is_valid(reg) ) return rc_bad; 1179 if (OptoReg::is_stack(reg)) return rc_stack; 1180 VMReg r = OptoReg::as_VMReg(reg); 1181 if (r->is_Register()) return rc_int; 1182 assert(r->is_FloatRegister(), "must be"); 1183 return rc_float; 1184 } 1185 1186 static int impl_helper( const MachNode *mach, CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, bool is_load, int offset, int reg, int opcode, const char *op_str, int size, outputStream* st ) { 1187 if( cbuf ) { 1188 // Better yet would be some mechanism to handle variable-size matches correctly 1189 if (!Assembler::is_simm13(offset + STACK_BIAS)) { 1190 ra_->C->record_method_not_compilable("unable to handle large constant offsets"); 1191 } else { 1192 emit_form3_mem_reg(*cbuf, mach, opcode, -1, R_SP_enc, offset, 0, Matcher::_regEncode[reg]); 1193 } 1194 } 1195 #ifndef PRODUCT 1196 else if( !do_size ) { 1197 if( size != 0 ) st->print("\n\t"); 1198 if( is_load ) st->print("%s [R_SP + #%d],R_%s\t! spill",op_str,offset,OptoReg::regname(reg)); 1199 else st->print("%s R_%s,[R_SP + #%d]\t! spill",op_str,OptoReg::regname(reg),offset); 1200 } 1201 #endif 1202 return size+4; 1203 } 1204 1205 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int op1, int op2, const char *op_str, int size, outputStream* st ) { 1206 if( cbuf ) emit3( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst], op1, 0, op2, Matcher::_regEncode[src] ); 1207 #ifndef PRODUCT 1208 else if( !do_size ) { 1209 if( size != 0 ) st->print("\n\t"); 1210 st->print("%s R_%s,R_%s\t! spill",op_str,OptoReg::regname(src),OptoReg::regname(dst)); 1211 } 1212 #endif 1213 return size+4; 1214 } 1215 1216 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf, 1217 PhaseRegAlloc *ra_, 1218 bool do_size, 1219 outputStream* st ) const { 1220 // Get registers to move 1221 OptoReg::Name src_second = ra_->get_reg_second(in(1)); 1222 OptoReg::Name src_first = ra_->get_reg_first(in(1)); 1223 OptoReg::Name dst_second = ra_->get_reg_second(this ); 1224 OptoReg::Name dst_first = ra_->get_reg_first(this ); 1225 1226 enum RC src_second_rc = rc_class(src_second); 1227 enum RC src_first_rc = rc_class(src_first); 1228 enum RC dst_second_rc = rc_class(dst_second); 1229 enum RC dst_first_rc = rc_class(dst_first); 1230 1231 assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" ); 1232 1233 // Generate spill code! 1234 int size = 0; 1235 1236 if( src_first == dst_first && src_second == dst_second ) 1237 return size; // Self copy, no move 1238 1239 // -------------------------------------- 1240 // Check for mem-mem move. Load into unused float registers and fall into 1241 // the float-store case. 1242 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) { 1243 int offset = ra_->reg2offset(src_first); 1244 // Further check for aligned-adjacent pair, so we can use a double load 1245 if( (src_first&1)==0 && src_first+1 == src_second ) { 1246 src_second = OptoReg::Name(R_F31_num); 1247 src_second_rc = rc_float; 1248 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::lddf_op3,"LDDF",size, st); 1249 } else { 1250 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::ldf_op3 ,"LDF ",size, st); 1251 } 1252 src_first = OptoReg::Name(R_F30_num); 1253 src_first_rc = rc_float; 1254 } 1255 1256 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) { 1257 int offset = ra_->reg2offset(src_second); 1258 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F31_num,Assembler::ldf_op3,"LDF ",size, st); 1259 src_second = OptoReg::Name(R_F31_num); 1260 src_second_rc = rc_float; 1261 } 1262 1263 // -------------------------------------- 1264 // Check for float->int copy; requires a trip through memory 1265 if( src_first_rc == rc_float && dst_first_rc == rc_int ) { 1266 int offset = frame::register_save_words*wordSize; 1267 if( cbuf ) { 1268 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::sub_op3, R_SP_enc, 16 ); 1269 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st); 1270 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st); 1271 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::add_op3, R_SP_enc, 16 ); 1272 } 1273 #ifndef PRODUCT 1274 else if( !do_size ) { 1275 if( size != 0 ) st->print("\n\t"); 1276 st->print( "SUB R_SP,16,R_SP\n"); 1277 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st); 1278 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st); 1279 st->print("\tADD R_SP,16,R_SP\n"); 1280 } 1281 #endif 1282 size += 16; 1283 } 1284 1285 // -------------------------------------- 1286 // In the 32-bit 1-reg-longs build ONLY, I see mis-aligned long destinations. 1287 // In such cases, I have to do the big-endian swap. For aligned targets, the 1288 // hardware does the flop for me. Doubles are always aligned, so no problem 1289 // there. Misaligned sources only come from native-long-returns (handled 1290 // special below). 1291 #ifndef _LP64 1292 if( src_first_rc == rc_int && // source is already big-endian 1293 src_second_rc != rc_bad && // 64-bit move 1294 ((dst_first&1)!=0 || dst_second != dst_first+1) ) { // misaligned dst 1295 assert( (src_first&1)==0 && src_second == src_first+1, "source must be aligned" ); 1296 // Do the big-endian flop. 1297 OptoReg::Name tmp = dst_first ; dst_first = dst_second ; dst_second = tmp ; 1298 enum RC tmp_rc = dst_first_rc; dst_first_rc = dst_second_rc; dst_second_rc = tmp_rc; 1299 } 1300 #endif 1301 1302 // -------------------------------------- 1303 // Check for integer reg-reg copy 1304 if( src_first_rc == rc_int && dst_first_rc == rc_int ) { 1305 #ifndef _LP64 1306 if( src_first == R_O0_num && src_second == R_O1_num ) { // Check for the evil O0/O1 native long-return case 1307 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value 1308 // as stored in memory. On a big-endian machine like SPARC, this means that the _second 1309 // operand contains the least significant word of the 64-bit value and vice versa. 1310 OptoReg::Name tmp = OptoReg::Name(R_O7_num); 1311 assert( (dst_first&1)==0 && dst_second == dst_first+1, "return a native O0/O1 long to an aligned-adjacent 64-bit reg" ); 1312 // Shift O0 left in-place, zero-extend O1, then OR them into the dst 1313 if( cbuf ) { 1314 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tmp], Assembler::sllx_op3, Matcher::_regEncode[src_first], 0x1020 ); 1315 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[src_second], Assembler::srl_op3, Matcher::_regEncode[src_second], 0x0000 ); 1316 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler:: or_op3, Matcher::_regEncode[tmp], 0, Matcher::_regEncode[src_second] ); 1317 #ifndef PRODUCT 1318 } else if( !do_size ) { 1319 if( size != 0 ) st->print("\n\t"); 1320 st->print("SLLX R_%s,32,R_%s\t! Move O0-first to O7-high\n\t", OptoReg::regname(src_first), OptoReg::regname(tmp)); 1321 st->print("SRL R_%s, 0,R_%s\t! Zero-extend O1\n\t", OptoReg::regname(src_second), OptoReg::regname(src_second)); 1322 st->print("OR R_%s,R_%s,R_%s\t! spill",OptoReg::regname(tmp), OptoReg::regname(src_second), OptoReg::regname(dst_first)); 1323 #endif 1324 } 1325 return size+12; 1326 } 1327 else if( dst_first == R_I0_num && dst_second == R_I1_num ) { 1328 // returning a long value in I0/I1 1329 // a SpillCopy must be able to target a return instruction's reg_class 1330 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value 1331 // as stored in memory. On a big-endian machine like SPARC, this means that the _second 1332 // operand contains the least significant word of the 64-bit value and vice versa. 1333 OptoReg::Name tdest = dst_first; 1334 1335 if (src_first == dst_first) { 1336 tdest = OptoReg::Name(R_O7_num); 1337 size += 4; 1338 } 1339 1340 if( cbuf ) { 1341 assert( (src_first&1) == 0 && (src_first+1) == src_second, "return value was in an aligned-adjacent 64-bit reg"); 1342 // Shift value in upper 32-bits of src to lower 32-bits of I0; move lower 32-bits to I1 1343 // ShrL_reg_imm6 1344 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tdest], Assembler::srlx_op3, Matcher::_regEncode[src_second], 32 | 0x1000 ); 1345 // ShrR_reg_imm6 src, 0, dst 1346 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srl_op3, Matcher::_regEncode[src_first], 0x0000 ); 1347 if (tdest != dst_first) { 1348 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler::or_op3, 0/*G0*/, 0/*op2*/, Matcher::_regEncode[tdest] ); 1349 } 1350 } 1351 #ifndef PRODUCT 1352 else if( !do_size ) { 1353 if( size != 0 ) st->print("\n\t"); // %%%%% !!!!! 1354 st->print("SRLX R_%s,32,R_%s\t! Extract MSW\n\t",OptoReg::regname(src_second),OptoReg::regname(tdest)); 1355 st->print("SRL R_%s, 0,R_%s\t! Extract LSW\n\t",OptoReg::regname(src_first),OptoReg::regname(dst_second)); 1356 if (tdest != dst_first) { 1357 st->print("MOV R_%s,R_%s\t! spill\n\t", OptoReg::regname(tdest), OptoReg::regname(dst_first)); 1358 } 1359 } 1360 #endif // PRODUCT 1361 return size+8; 1362 } 1363 #endif // !_LP64 1364 // Else normal reg-reg copy 1365 assert( src_second != dst_first, "smashed second before evacuating it" ); 1366 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::or_op3,0,"MOV ",size, st); 1367 assert( (src_first&1) == 0 && (dst_first&1) == 0, "never move second-halves of int registers" ); 1368 // This moves an aligned adjacent pair. 1369 // See if we are done. 1370 if( src_first+1 == src_second && dst_first+1 == dst_second ) 1371 return size; 1372 } 1373 1374 // Check for integer store 1375 if( src_first_rc == rc_int && dst_first_rc == rc_stack ) { 1376 int offset = ra_->reg2offset(dst_first); 1377 // Further check for aligned-adjacent pair, so we can use a double store 1378 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) 1379 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stx_op3,"STX ",size, st); 1380 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stw_op3,"STW ",size, st); 1381 } 1382 1383 // Check for integer load 1384 if( dst_first_rc == rc_int && src_first_rc == rc_stack ) { 1385 int offset = ra_->reg2offset(src_first); 1386 // Further check for aligned-adjacent pair, so we can use a double load 1387 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) 1388 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldx_op3 ,"LDX ",size, st); 1389 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st); 1390 } 1391 1392 // Check for float reg-reg copy 1393 if( src_first_rc == rc_float && dst_first_rc == rc_float ) { 1394 // Further check for aligned-adjacent pair, so we can use a double move 1395 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) 1396 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovd_opf,"FMOVD",size, st); 1397 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovs_opf,"FMOVS",size, st); 1398 } 1399 1400 // Check for float store 1401 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) { 1402 int offset = ra_->reg2offset(dst_first); 1403 // Further check for aligned-adjacent pair, so we can use a double store 1404 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) 1405 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stdf_op3,"STDF",size, st); 1406 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st); 1407 } 1408 1409 // Check for float load 1410 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) { 1411 int offset = ra_->reg2offset(src_first); 1412 // Further check for aligned-adjacent pair, so we can use a double load 1413 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) 1414 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lddf_op3,"LDDF",size, st); 1415 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldf_op3 ,"LDF ",size, st); 1416 } 1417 1418 // -------------------------------------------------------------------- 1419 // Check for hi bits still needing moving. Only happens for misaligned 1420 // arguments to native calls. 1421 if( src_second == dst_second ) 1422 return size; // Self copy; no move 1423 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" ); 1424 1425 #ifndef _LP64 1426 // In the LP64 build, all registers can be moved as aligned/adjacent 1427 // pairs, so there's never any need to move the high bits separately. 1428 // The 32-bit builds have to deal with the 32-bit ABI which can force 1429 // all sorts of silly alignment problems. 1430 1431 // Check for integer reg-reg copy. Hi bits are stuck up in the top 1432 // 32-bits of a 64-bit register, but are needed in low bits of another 1433 // register (else it's a hi-bits-to-hi-bits copy which should have 1434 // happened already as part of a 64-bit move) 1435 if( src_second_rc == rc_int && dst_second_rc == rc_int ) { 1436 assert( (src_second&1)==1, "its the evil O0/O1 native return case" ); 1437 assert( (dst_second&1)==0, "should have moved with 1 64-bit move" ); 1438 // Shift src_second down to dst_second's low bits. 1439 if( cbuf ) { 1440 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 ); 1441 #ifndef PRODUCT 1442 } else if( !do_size ) { 1443 if( size != 0 ) st->print("\n\t"); 1444 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(dst_second)); 1445 #endif 1446 } 1447 return size+4; 1448 } 1449 1450 // Check for high word integer store. Must down-shift the hi bits 1451 // into a temp register, then fall into the case of storing int bits. 1452 if( src_second_rc == rc_int && dst_second_rc == rc_stack && (src_second&1)==1 ) { 1453 // Shift src_second down to dst_second's low bits. 1454 if( cbuf ) { 1455 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[R_O7_num], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 ); 1456 #ifndef PRODUCT 1457 } else if( !do_size ) { 1458 if( size != 0 ) st->print("\n\t"); 1459 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(R_O7_num)); 1460 #endif 1461 } 1462 size+=4; 1463 src_second = OptoReg::Name(R_O7_num); // Not R_O7H_num! 1464 } 1465 1466 // Check for high word integer load 1467 if( dst_second_rc == rc_int && src_second_rc == rc_stack ) 1468 return impl_helper(this,cbuf,ra_,do_size,true ,ra_->reg2offset(src_second),dst_second,Assembler::lduw_op3,"LDUW",size, st); 1469 1470 // Check for high word integer store 1471 if( src_second_rc == rc_int && dst_second_rc == rc_stack ) 1472 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stw_op3 ,"STW ",size, st); 1473 1474 // Check for high word float store 1475 if( src_second_rc == rc_float && dst_second_rc == rc_stack ) 1476 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stf_op3 ,"STF ",size, st); 1477 1478 #endif // !_LP64 1479 1480 Unimplemented(); 1481 } 1482 1483 #ifndef PRODUCT 1484 void MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { 1485 implementation( NULL, ra_, false, st ); 1486 } 1487 #endif 1488 1489 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1490 implementation( &cbuf, ra_, false, NULL ); 1491 } 1492 1493 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const { 1494 return implementation( NULL, ra_, true, NULL ); 1495 } 1496 1497 //============================================================================= 1498 #ifndef PRODUCT 1499 void MachNopNode::format( PhaseRegAlloc *, outputStream *st ) const { 1500 st->print("NOP \t# %d bytes pad for loops and calls", 4 * _count); 1501 } 1502 #endif 1503 1504 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc * ) const { 1505 MacroAssembler _masm(&cbuf); 1506 for(int i = 0; i < _count; i += 1) { 1507 __ nop(); 1508 } 1509 } 1510 1511 uint MachNopNode::size(PhaseRegAlloc *ra_) const { 1512 return 4 * _count; 1513 } 1514 1515 1516 //============================================================================= 1517 #ifndef PRODUCT 1518 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { 1519 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); 1520 int reg = ra_->get_reg_first(this); 1521 st->print("LEA [R_SP+#%d+BIAS],%s",offset,Matcher::regName[reg]); 1522 } 1523 #endif 1524 1525 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1526 MacroAssembler _masm(&cbuf); 1527 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()) + STACK_BIAS; 1528 int reg = ra_->get_encode(this); 1529 1530 if (Assembler::is_simm13(offset)) { 1531 __ add(SP, offset, reg_to_register_object(reg)); 1532 } else { 1533 __ set(offset, O7); 1534 __ add(SP, O7, reg_to_register_object(reg)); 1535 } 1536 } 1537 1538 uint BoxLockNode::size(PhaseRegAlloc *ra_) const { 1539 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_) 1540 assert(ra_ == ra_->C->regalloc(), "sanity"); 1541 return ra_->C->scratch_emit_size(this); 1542 } 1543 1544 //============================================================================= 1545 1546 // emit call stub, compiled java to interpretor 1547 void emit_java_to_interp(CodeBuffer &cbuf ) { 1548 1549 // Stub is fixed up when the corresponding call is converted from calling 1550 // compiled code to calling interpreted code. 1551 // set (empty), G5 1552 // jmp -1 1553 1554 address mark = cbuf.inst_mark(); // get mark within main instrs section 1555 1556 MacroAssembler _masm(&cbuf); 1557 1558 address base = 1559 __ start_a_stub(Compile::MAX_stubs_size); 1560 if (base == NULL) return; // CodeBuffer::expand failed 1561 1562 // static stub relocation stores the instruction address of the call 1563 __ relocate(static_stub_Relocation::spec(mark)); 1564 1565 __ set_oop(NULL, reg_to_register_object(Matcher::inline_cache_reg_encode())); 1566 1567 __ set_inst_mark(); 1568 AddressLiteral addrlit(-1); 1569 __ JUMP(addrlit, G3, 0); 1570 1571 __ delayed()->nop(); 1572 1573 // Update current stubs pointer and restore code_end. 1574 __ end_a_stub(); 1575 } 1576 1577 // size of call stub, compiled java to interpretor 1578 uint size_java_to_interp() { 1579 // This doesn't need to be accurate but it must be larger or equal to 1580 // the real size of the stub. 1581 return (NativeMovConstReg::instruction_size + // sethi/setlo; 1582 NativeJump::instruction_size + // sethi; jmp; nop 1583 (TraceJumps ? 20 * BytesPerInstWord : 0) ); 1584 } 1585 // relocation entries for call stub, compiled java to interpretor 1586 uint reloc_java_to_interp() { 1587 return 10; // 4 in emit_java_to_interp + 1 in Java_Static_Call 1588 } 1589 1590 1591 //============================================================================= 1592 #ifndef PRODUCT 1593 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { 1594 st->print_cr("\nUEP:"); 1595 #ifdef _LP64 1596 if (UseCompressedOops) { 1597 assert(Universe::heap() != NULL, "java heap should be initialized"); 1598 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check - compressed klass"); 1599 st->print_cr("\tSLL R_G5,3,R_G5"); 1600 if (Universe::narrow_oop_base() != NULL) 1601 st->print_cr("\tADD R_G5,R_G6_heap_base,R_G5"); 1602 } else { 1603 st->print_cr("\tLDX [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check"); 1604 } 1605 st->print_cr("\tCMP R_G5,R_G3" ); 1606 st->print ("\tTne xcc,R_G0+ST_RESERVED_FOR_USER_0+2"); 1607 #else // _LP64 1608 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check"); 1609 st->print_cr("\tCMP R_G5,R_G3" ); 1610 st->print ("\tTne icc,R_G0+ST_RESERVED_FOR_USER_0+2"); 1611 #endif // _LP64 1612 } 1613 #endif 1614 1615 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1616 MacroAssembler _masm(&cbuf); 1617 Label L; 1618 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode()); 1619 Register temp_reg = G3; 1620 assert( G5_ic_reg != temp_reg, "conflicting registers" ); 1621 1622 // Load klass from receiver 1623 __ load_klass(O0, temp_reg); 1624 // Compare against expected klass 1625 __ cmp(temp_reg, G5_ic_reg); 1626 // Branch to miss code, checks xcc or icc depending 1627 __ trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2); 1628 } 1629 1630 uint MachUEPNode::size(PhaseRegAlloc *ra_) const { 1631 return MachNode::size(ra_); 1632 } 1633 1634 1635 //============================================================================= 1636 1637 uint size_exception_handler() { 1638 if (TraceJumps) { 1639 return (400); // just a guess 1640 } 1641 return ( NativeJump::instruction_size ); // sethi;jmp;nop 1642 } 1643 1644 uint size_deopt_handler() { 1645 if (TraceJumps) { 1646 return (400); // just a guess 1647 } 1648 return ( 4+ NativeJump::instruction_size ); // save;sethi;jmp;restore 1649 } 1650 1651 // Emit exception handler code. 1652 int emit_exception_handler(CodeBuffer& cbuf) { 1653 Register temp_reg = G3; 1654 AddressLiteral exception_blob(OptoRuntime::exception_blob()->instructions_begin()); 1655 MacroAssembler _masm(&cbuf); 1656 1657 address base = 1658 __ start_a_stub(size_exception_handler()); 1659 if (base == NULL) return 0; // CodeBuffer::expand failed 1660 1661 int offset = __ offset(); 1662 1663 __ JUMP(exception_blob, temp_reg, 0); // sethi;jmp 1664 __ delayed()->nop(); 1665 1666 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow"); 1667 1668 __ end_a_stub(); 1669 1670 return offset; 1671 } 1672 1673 int emit_deopt_handler(CodeBuffer& cbuf) { 1674 // Can't use any of the current frame's registers as we may have deopted 1675 // at a poll and everything (including G3) can be live. 1676 Register temp_reg = L0; 1677 AddressLiteral deopt_blob(SharedRuntime::deopt_blob()->unpack()); 1678 MacroAssembler _masm(&cbuf); 1679 1680 address base = 1681 __ start_a_stub(size_deopt_handler()); 1682 if (base == NULL) return 0; // CodeBuffer::expand failed 1683 1684 int offset = __ offset(); 1685 __ save_frame(0); 1686 __ JUMP(deopt_blob, temp_reg, 0); // sethi;jmp 1687 __ delayed()->restore(); 1688 1689 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow"); 1690 1691 __ end_a_stub(); 1692 return offset; 1693 1694 } 1695 1696 // Given a register encoding, produce a Integer Register object 1697 static Register reg_to_register_object(int register_encoding) { 1698 assert(L5->encoding() == R_L5_enc && G1->encoding() == R_G1_enc, "right coding"); 1699 return as_Register(register_encoding); 1700 } 1701 1702 // Given a register encoding, produce a single-precision Float Register object 1703 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding) { 1704 assert(F5->encoding(FloatRegisterImpl::S) == R_F5_enc && F12->encoding(FloatRegisterImpl::S) == R_F12_enc, "right coding"); 1705 return as_SingleFloatRegister(register_encoding); 1706 } 1707 1708 // Given a register encoding, produce a double-precision Float Register object 1709 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding) { 1710 assert(F4->encoding(FloatRegisterImpl::D) == R_F4_enc, "right coding"); 1711 assert(F32->encoding(FloatRegisterImpl::D) == R_D32_enc, "right coding"); 1712 return as_DoubleFloatRegister(register_encoding); 1713 } 1714 1715 int Matcher::regnum_to_fpu_offset(int regnum) { 1716 return regnum - 32; // The FP registers are in the second chunk 1717 } 1718 1719 #ifdef ASSERT 1720 address last_rethrow = NULL; // debugging aid for Rethrow encoding 1721 #endif 1722 1723 // Vector width in bytes 1724 const uint Matcher::vector_width_in_bytes(void) { 1725 return 8; 1726 } 1727 1728 // Vector ideal reg 1729 const uint Matcher::vector_ideal_reg(void) { 1730 return Op_RegD; 1731 } 1732 1733 // USII supports fxtof through the whole range of number, USIII doesn't 1734 const bool Matcher::convL2FSupported(void) { 1735 return VM_Version::has_fast_fxtof(); 1736 } 1737 1738 // Is this branch offset short enough that a short branch can be used? 1739 // 1740 // NOTE: If the platform does not provide any short branch variants, then 1741 // this method should return false for offset 0. 1742 bool Matcher::is_short_branch_offset(int rule, int offset) { 1743 return false; 1744 } 1745 1746 const bool Matcher::isSimpleConstant64(jlong value) { 1747 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?. 1748 // Depends on optimizations in MacroAssembler::setx. 1749 int hi = (int)(value >> 32); 1750 int lo = (int)(value & ~0); 1751 return (hi == 0) || (hi == -1) || (lo == 0); 1752 } 1753 1754 // No scaling for the parameter the ClearArray node. 1755 const bool Matcher::init_array_count_is_in_bytes = true; 1756 1757 // Threshold size for cleararray. 1758 const int Matcher::init_array_short_size = 8 * BytesPerLong; 1759 1760 // Should the Matcher clone shifts on addressing modes, expecting them to 1761 // be subsumed into complex addressing expressions or compute them into 1762 // registers? True for Intel but false for most RISCs 1763 const bool Matcher::clone_shift_expressions = false; 1764 1765 // Is it better to copy float constants, or load them directly from memory? 1766 // Intel can load a float constant from a direct address, requiring no 1767 // extra registers. Most RISCs will have to materialize an address into a 1768 // register first, so they would do better to copy the constant from stack. 1769 const bool Matcher::rematerialize_float_constants = false; 1770 1771 // If CPU can load and store mis-aligned doubles directly then no fixup is 1772 // needed. Else we split the double into 2 integer pieces and move it 1773 // piece-by-piece. Only happens when passing doubles into C code as the 1774 // Java calling convention forces doubles to be aligned. 1775 #ifdef _LP64 1776 const bool Matcher::misaligned_doubles_ok = true; 1777 #else 1778 const bool Matcher::misaligned_doubles_ok = false; 1779 #endif 1780 1781 // No-op on SPARC. 1782 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) { 1783 } 1784 1785 // Advertise here if the CPU requires explicit rounding operations 1786 // to implement the UseStrictFP mode. 1787 const bool Matcher::strict_fp_requires_explicit_rounding = false; 1788 1789 // Do floats take an entire double register or just half? 1790 const bool Matcher::float_in_double = false; 1791 1792 // Do ints take an entire long register or just half? 1793 // Note that we if-def off of _LP64. 1794 // The relevant question is how the int is callee-saved. In _LP64 1795 // the whole long is written but de-opt'ing will have to extract 1796 // the relevant 32 bits, in not-_LP64 only the low 32 bits is written. 1797 #ifdef _LP64 1798 const bool Matcher::int_in_long = true; 1799 #else 1800 const bool Matcher::int_in_long = false; 1801 #endif 1802 1803 // Return whether or not this register is ever used as an argument. This 1804 // function is used on startup to build the trampoline stubs in generateOptoStub. 1805 // Registers not mentioned will be killed by the VM call in the trampoline, and 1806 // arguments in those registers not be available to the callee. 1807 bool Matcher::can_be_java_arg( int reg ) { 1808 // Standard sparc 6 args in registers 1809 if( reg == R_I0_num || 1810 reg == R_I1_num || 1811 reg == R_I2_num || 1812 reg == R_I3_num || 1813 reg == R_I4_num || 1814 reg == R_I5_num ) return true; 1815 #ifdef _LP64 1816 // 64-bit builds can pass 64-bit pointers and longs in 1817 // the high I registers 1818 if( reg == R_I0H_num || 1819 reg == R_I1H_num || 1820 reg == R_I2H_num || 1821 reg == R_I3H_num || 1822 reg == R_I4H_num || 1823 reg == R_I5H_num ) return true; 1824 1825 if ((UseCompressedOops) && (reg == R_G6_num || reg == R_G6H_num)) { 1826 return true; 1827 } 1828 1829 #else 1830 // 32-bit builds with longs-in-one-entry pass longs in G1 & G4. 1831 // Longs cannot be passed in O regs, because O regs become I regs 1832 // after a 'save' and I regs get their high bits chopped off on 1833 // interrupt. 1834 if( reg == R_G1H_num || reg == R_G1_num ) return true; 1835 if( reg == R_G4H_num || reg == R_G4_num ) return true; 1836 #endif 1837 // A few float args in registers 1838 if( reg >= R_F0_num && reg <= R_F7_num ) return true; 1839 1840 return false; 1841 } 1842 1843 bool Matcher::is_spillable_arg( int reg ) { 1844 return can_be_java_arg(reg); 1845 } 1846 1847 // Register for DIVI projection of divmodI 1848 RegMask Matcher::divI_proj_mask() { 1849 ShouldNotReachHere(); 1850 return RegMask(); 1851 } 1852 1853 // Register for MODI projection of divmodI 1854 RegMask Matcher::modI_proj_mask() { 1855 ShouldNotReachHere(); 1856 return RegMask(); 1857 } 1858 1859 // Register for DIVL projection of divmodL 1860 RegMask Matcher::divL_proj_mask() { 1861 ShouldNotReachHere(); 1862 return RegMask(); 1863 } 1864 1865 // Register for MODL projection of divmodL 1866 RegMask Matcher::modL_proj_mask() { 1867 ShouldNotReachHere(); 1868 return RegMask(); 1869 } 1870 1871 %} 1872 1873 1874 // The intptr_t operand types, defined by textual substitution. 1875 // (Cf. opto/type.hpp. This lets us avoid many, many other ifdefs.) 1876 #ifdef _LP64 1877 #define immX immL 1878 #define immX13 immL13 1879 #define iRegX iRegL 1880 #define g1RegX g1RegL 1881 #else 1882 #define immX immI 1883 #define immX13 immI13 1884 #define iRegX iRegI 1885 #define g1RegX g1RegI 1886 #endif 1887 1888 //----------ENCODING BLOCK----------------------------------------------------- 1889 // This block specifies the encoding classes used by the compiler to output 1890 // byte streams. Encoding classes are parameterized macros used by 1891 // Machine Instruction Nodes in order to generate the bit encoding of the 1892 // instruction. Operands specify their base encoding interface with the 1893 // interface keyword. There are currently supported four interfaces, 1894 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an 1895 // operand to generate a function which returns its register number when 1896 // queried. CONST_INTER causes an operand to generate a function which 1897 // returns the value of the constant when queried. MEMORY_INTER causes an 1898 // operand to generate four functions which return the Base Register, the 1899 // Index Register, the Scale Value, and the Offset Value of the operand when 1900 // queried. COND_INTER causes an operand to generate six functions which 1901 // return the encoding code (ie - encoding bits for the instruction) 1902 // associated with each basic boolean condition for a conditional instruction. 1903 // 1904 // Instructions specify two basic values for encoding. Again, a function 1905 // is available to check if the constant displacement is an oop. They use the 1906 // ins_encode keyword to specify their encoding classes (which must be 1907 // a sequence of enc_class names, and their parameters, specified in 1908 // the encoding block), and they use the 1909 // opcode keyword to specify, in order, their primary, secondary, and 1910 // tertiary opcode. Only the opcode sections which a particular instruction 1911 // needs for encoding need to be specified. 1912 encode %{ 1913 enc_class enc_untested %{ 1914 #ifdef ASSERT 1915 MacroAssembler _masm(&cbuf); 1916 __ untested("encoding"); 1917 #endif 1918 %} 1919 1920 enc_class form3_mem_reg( memory mem, iRegI dst ) %{ 1921 emit_form3_mem_reg(cbuf, this, $primary, $tertiary, 1922 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg); 1923 %} 1924 1925 enc_class simple_form3_mem_reg( memory mem, iRegI dst ) %{ 1926 emit_form3_mem_reg(cbuf, this, $primary, -1, 1927 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg); 1928 %} 1929 1930 enc_class form3_mem_reg_little( memory mem, iRegI dst) %{ 1931 emit_form3_mem_reg_asi(cbuf, this, $primary, -1, 1932 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg, Assembler::ASI_PRIMARY_LITTLE); 1933 %} 1934 1935 enc_class form3_mem_prefetch_read( memory mem ) %{ 1936 emit_form3_mem_reg(cbuf, this, $primary, -1, 1937 $mem$$base, $mem$$disp, $mem$$index, 0/*prefetch function many-reads*/); 1938 %} 1939 1940 enc_class form3_mem_prefetch_write( memory mem ) %{ 1941 emit_form3_mem_reg(cbuf, this, $primary, -1, 1942 $mem$$base, $mem$$disp, $mem$$index, 2/*prefetch function many-writes*/); 1943 %} 1944 1945 enc_class form3_mem_reg_long_unaligned_marshal( memory mem, iRegL reg ) %{ 1946 assert( Assembler::is_simm13($mem$$disp ), "need disp and disp+4" ); 1947 assert( Assembler::is_simm13($mem$$disp+4), "need disp and disp+4" ); 1948 guarantee($mem$$index == R_G0_enc, "double index?"); 1949 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, R_O7_enc ); 1950 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg ); 1951 emit3_simm13( cbuf, Assembler::arith_op, $reg$$reg, Assembler::sllx_op3, $reg$$reg, 0x1020 ); 1952 emit3( cbuf, Assembler::arith_op, $reg$$reg, Assembler::or_op3, $reg$$reg, 0, R_O7_enc ); 1953 %} 1954 1955 enc_class form3_mem_reg_double_unaligned( memory mem, RegD_low reg ) %{ 1956 assert( Assembler::is_simm13($mem$$disp ), "need disp and disp+4" ); 1957 assert( Assembler::is_simm13($mem$$disp+4), "need disp and disp+4" ); 1958 guarantee($mem$$index == R_G0_enc, "double index?"); 1959 // Load long with 2 instructions 1960 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg+0 ); 1961 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, $reg$$reg+1 ); 1962 %} 1963 1964 //%%% form3_mem_plus_4_reg is a hack--get rid of it 1965 enc_class form3_mem_plus_4_reg( memory mem, iRegI dst ) %{ 1966 guarantee($mem$$disp, "cannot offset a reg-reg operand by 4"); 1967 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp + 4, $mem$$index, $dst$$reg); 1968 %} 1969 1970 enc_class form3_g0_rs2_rd_move( iRegI rs2, iRegI rd ) %{ 1971 // Encode a reg-reg copy. If it is useless, then empty encoding. 1972 if( $rs2$$reg != $rd$$reg ) 1973 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, $rs2$$reg ); 1974 %} 1975 1976 // Target lo half of long 1977 enc_class form3_g0_rs2_rd_move_lo( iRegI rs2, iRegL rd ) %{ 1978 // Encode a reg-reg copy. If it is useless, then empty encoding. 1979 if( $rs2$$reg != LONG_LO_REG($rd$$reg) ) 1980 emit3( cbuf, Assembler::arith_op, LONG_LO_REG($rd$$reg), Assembler::or_op3, 0, 0, $rs2$$reg ); 1981 %} 1982 1983 // Source lo half of long 1984 enc_class form3_g0_rs2_rd_move_lo2( iRegL rs2, iRegI rd ) %{ 1985 // Encode a reg-reg copy. If it is useless, then empty encoding. 1986 if( LONG_LO_REG($rs2$$reg) != $rd$$reg ) 1987 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_LO_REG($rs2$$reg) ); 1988 %} 1989 1990 // Target hi half of long 1991 enc_class form3_rs1_rd_copysign_hi( iRegI rs1, iRegL rd ) %{ 1992 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 31 ); 1993 %} 1994 1995 // Source lo half of long, and leave it sign extended. 1996 enc_class form3_rs1_rd_signextend_lo1( iRegL rs1, iRegI rd ) %{ 1997 // Sign extend low half 1998 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 0, 0 ); 1999 %} 2000 2001 // Source hi half of long, and leave it sign extended. 2002 enc_class form3_rs1_rd_copy_hi1( iRegL rs1, iRegI rd ) %{ 2003 // Shift high half to low half 2004 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::srlx_op3, $rs1$$reg, 32 ); 2005 %} 2006 2007 // Source hi half of long 2008 enc_class form3_g0_rs2_rd_move_hi2( iRegL rs2, iRegI rd ) %{ 2009 // Encode a reg-reg copy. If it is useless, then empty encoding. 2010 if( LONG_HI_REG($rs2$$reg) != $rd$$reg ) 2011 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_HI_REG($rs2$$reg) ); 2012 %} 2013 2014 enc_class form3_rs1_rs2_rd( iRegI rs1, iRegI rs2, iRegI rd ) %{ 2015 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0, $rs2$$reg ); 2016 %} 2017 2018 enc_class enc_to_bool( iRegI src, iRegI dst ) %{ 2019 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, 0, 0, $src$$reg ); 2020 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::addc_op3 , 0, 0 ); 2021 %} 2022 2023 enc_class enc_ltmask( iRegI p, iRegI q, iRegI dst ) %{ 2024 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $p$$reg, 0, $q$$reg ); 2025 // clear if nothing else is happening 2026 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 0 ); 2027 // blt,a,pn done 2028 emit2_19 ( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less, Assembler::bp_op2, Assembler::icc, 0/*predict not taken*/, 2 ); 2029 // mov dst,-1 in delay slot 2030 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 ); 2031 %} 2032 2033 enc_class form3_rs1_imm5_rd( iRegI rs1, immU5 imm5, iRegI rd ) %{ 2034 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $imm5$$constant & 0x1F ); 2035 %} 2036 2037 enc_class form3_sd_rs1_imm6_rd( iRegL rs1, immU6 imm6, iRegL rd ) %{ 2038 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, ($imm6$$constant & 0x3F) | 0x1000 ); 2039 %} 2040 2041 enc_class form3_sd_rs1_rs2_rd( iRegL rs1, iRegI rs2, iRegL rd ) %{ 2042 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0x80, $rs2$$reg ); 2043 %} 2044 2045 enc_class form3_rs1_simm13_rd( iRegI rs1, immI13 simm13, iRegI rd ) %{ 2046 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $simm13$$constant ); 2047 %} 2048 2049 enc_class move_return_pc_to_o1() %{ 2050 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::add_op3, R_O7_enc, frame::pc_return_offset ); 2051 %} 2052 2053 #ifdef _LP64 2054 /* %%% merge with enc_to_bool */ 2055 enc_class enc_convP2B( iRegI dst, iRegP src ) %{ 2056 MacroAssembler _masm(&cbuf); 2057 2058 Register src_reg = reg_to_register_object($src$$reg); 2059 Register dst_reg = reg_to_register_object($dst$$reg); 2060 __ movr(Assembler::rc_nz, src_reg, 1, dst_reg); 2061 %} 2062 #endif 2063 2064 enc_class enc_cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp ) %{ 2065 // (Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q))) 2066 MacroAssembler _masm(&cbuf); 2067 2068 Register p_reg = reg_to_register_object($p$$reg); 2069 Register q_reg = reg_to_register_object($q$$reg); 2070 Register y_reg = reg_to_register_object($y$$reg); 2071 Register tmp_reg = reg_to_register_object($tmp$$reg); 2072 2073 __ subcc( p_reg, q_reg, p_reg ); 2074 __ add ( p_reg, y_reg, tmp_reg ); 2075 __ movcc( Assembler::less, false, Assembler::icc, tmp_reg, p_reg ); 2076 %} 2077 2078 enc_class form_d2i_helper(regD src, regF dst) %{ 2079 // fcmp %fcc0,$src,$src 2080 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg ); 2081 // branch %fcc0 not-nan, predict taken 2082 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); 2083 // fdtoi $src,$dst 2084 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtoi_opf, $src$$reg ); 2085 // fitos $dst,$dst (if nan) 2086 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg ); 2087 // clear $dst (if nan) 2088 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg ); 2089 // carry on here... 2090 %} 2091 2092 enc_class form_d2l_helper(regD src, regD dst) %{ 2093 // fcmp %fcc0,$src,$src check for NAN 2094 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg ); 2095 // branch %fcc0 not-nan, predict taken 2096 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); 2097 // fdtox $src,$dst convert in delay slot 2098 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtox_opf, $src$$reg ); 2099 // fxtod $dst,$dst (if nan) 2100 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg ); 2101 // clear $dst (if nan) 2102 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg ); 2103 // carry on here... 2104 %} 2105 2106 enc_class form_f2i_helper(regF src, regF dst) %{ 2107 // fcmps %fcc0,$src,$src 2108 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg ); 2109 // branch %fcc0 not-nan, predict taken 2110 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); 2111 // fstoi $src,$dst 2112 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstoi_opf, $src$$reg ); 2113 // fitos $dst,$dst (if nan) 2114 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg ); 2115 // clear $dst (if nan) 2116 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg ); 2117 // carry on here... 2118 %} 2119 2120 enc_class form_f2l_helper(regF src, regD dst) %{ 2121 // fcmps %fcc0,$src,$src 2122 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg ); 2123 // branch %fcc0 not-nan, predict taken 2124 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); 2125 // fstox $src,$dst 2126 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstox_opf, $src$$reg ); 2127 // fxtod $dst,$dst (if nan) 2128 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg ); 2129 // clear $dst (if nan) 2130 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg ); 2131 // carry on here... 2132 %} 2133 2134 enc_class form3_opf_rs2F_rdF(regF rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} 2135 enc_class form3_opf_rs2F_rdD(regF rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} 2136 enc_class form3_opf_rs2D_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} 2137 enc_class form3_opf_rs2D_rdD(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} 2138 2139 enc_class form3_opf_rs2D_lo_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg+1); %} 2140 2141 enc_class form3_opf_rs2D_hi_rdD_hi(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} 2142 enc_class form3_opf_rs2D_lo_rdD_lo(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg+1,$primary,0,$tertiary,$rs2$$reg+1); %} 2143 2144 enc_class form3_opf_rs1F_rs2F_rdF( regF rs1, regF rs2, regF rd ) %{ 2145 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); 2146 %} 2147 2148 enc_class form3_opf_rs1D_rs2D_rdD( regD rs1, regD rs2, regD rd ) %{ 2149 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); 2150 %} 2151 2152 enc_class form3_opf_rs1F_rs2F_fcc( regF rs1, regF rs2, flagsRegF fcc ) %{ 2153 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); 2154 %} 2155 2156 enc_class form3_opf_rs1D_rs2D_fcc( regD rs1, regD rs2, flagsRegF fcc ) %{ 2157 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); 2158 %} 2159 2160 enc_class form3_convI2F(regF rs2, regF rd) %{ 2161 emit3(cbuf,Assembler::arith_op,$rd$$reg,Assembler::fpop1_op3,0,$secondary,$rs2$$reg); 2162 %} 2163 2164 // Encloding class for traceable jumps 2165 enc_class form_jmpl(g3RegP dest) %{ 2166 emit_jmpl(cbuf, $dest$$reg); 2167 %} 2168 2169 enc_class form_jmpl_set_exception_pc(g1RegP dest) %{ 2170 emit_jmpl_set_exception_pc(cbuf, $dest$$reg); 2171 %} 2172 2173 enc_class form2_nop() %{ 2174 emit_nop(cbuf); 2175 %} 2176 2177 enc_class form2_illtrap() %{ 2178 emit_illtrap(cbuf); 2179 %} 2180 2181 2182 // Compare longs and convert into -1, 0, 1. 2183 enc_class cmpl_flag( iRegL src1, iRegL src2, iRegI dst ) %{ 2184 // CMP $src1,$src2 2185 emit3( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $src1$$reg, 0, $src2$$reg ); 2186 // blt,a,pn done 2187 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less , Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 5 ); 2188 // mov dst,-1 in delay slot 2189 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 ); 2190 // bgt,a,pn done 2191 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::greater, Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 3 ); 2192 // mov dst,1 in delay slot 2193 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 1 ); 2194 // CLR $dst 2195 emit3( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3 , 0, 0, 0 ); 2196 %} 2197 2198 enc_class enc_PartialSubtypeCheck() %{ 2199 MacroAssembler _masm(&cbuf); 2200 __ call(StubRoutines::Sparc::partial_subtype_check(), relocInfo::runtime_call_type); 2201 __ delayed()->nop(); 2202 %} 2203 2204 enc_class enc_bp( Label labl, cmpOp cmp, flagsReg cc ) %{ 2205 MacroAssembler _masm(&cbuf); 2206 Label &L = *($labl$$label); 2207 Assembler::Predict predict_taken = 2208 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn; 2209 2210 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, L); 2211 __ delayed()->nop(); 2212 %} 2213 2214 enc_class enc_bpl( Label labl, cmpOp cmp, flagsRegL cc ) %{ 2215 MacroAssembler _masm(&cbuf); 2216 Label &L = *($labl$$label); 2217 Assembler::Predict predict_taken = 2218 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn; 2219 2220 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, L); 2221 __ delayed()->nop(); 2222 %} 2223 2224 enc_class enc_bpx( Label labl, cmpOp cmp, flagsRegP cc ) %{ 2225 MacroAssembler _masm(&cbuf); 2226 Label &L = *($labl$$label); 2227 Assembler::Predict predict_taken = 2228 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn; 2229 2230 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, L); 2231 __ delayed()->nop(); 2232 %} 2233 2234 enc_class enc_fbp( Label labl, cmpOpF cmp, flagsRegF cc ) %{ 2235 MacroAssembler _masm(&cbuf); 2236 Label &L = *($labl$$label); 2237 Assembler::Predict predict_taken = 2238 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn; 2239 2240 __ fbp( (Assembler::Condition)($cmp$$cmpcode), false, (Assembler::CC)($cc$$reg), predict_taken, L); 2241 __ delayed()->nop(); 2242 %} 2243 2244 enc_class jump_enc( iRegX switch_val, o7RegI table) %{ 2245 MacroAssembler _masm(&cbuf); 2246 2247 Register switch_reg = as_Register($switch_val$$reg); 2248 Register table_reg = O7; 2249 2250 address table_base = __ address_table_constant(_index2label); 2251 RelocationHolder rspec = internal_word_Relocation::spec(table_base); 2252 2253 // Move table address into a register. 2254 __ set(table_base, table_reg, rspec); 2255 2256 // Jump to base address + switch value 2257 __ ld_ptr(table_reg, switch_reg, table_reg); 2258 __ jmp(table_reg, G0); 2259 __ delayed()->nop(); 2260 2261 %} 2262 2263 enc_class enc_ba( Label labl ) %{ 2264 MacroAssembler _masm(&cbuf); 2265 Label &L = *($labl$$label); 2266 __ ba(false, L); 2267 __ delayed()->nop(); 2268 %} 2269 2270 enc_class enc_bpr( Label labl, cmpOp_reg cmp, iRegI op1 ) %{ 2271 MacroAssembler _masm(&cbuf); 2272 Label &L = *$labl$$label; 2273 Assembler::Predict predict_taken = 2274 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn; 2275 2276 __ bpr( (Assembler::RCondition)($cmp$$cmpcode), false, predict_taken, as_Register($op1$$reg), L); 2277 __ delayed()->nop(); 2278 %} 2279 2280 enc_class enc_cmov_reg( cmpOp cmp, iRegI dst, iRegI src, immI pcc) %{ 2281 int op = (Assembler::arith_op << 30) | 2282 ($dst$$reg << 25) | 2283 (Assembler::movcc_op3 << 19) | 2284 (1 << 18) | // cc2 bit for 'icc' 2285 ($cmp$$cmpcode << 14) | 2286 (0 << 13) | // select register move 2287 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc' or 'xcc' 2288 ($src$$reg << 0); 2289 *((int*)(cbuf.code_end())) = op; 2290 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); 2291 %} 2292 2293 enc_class enc_cmov_imm( cmpOp cmp, iRegI dst, immI11 src, immI pcc ) %{ 2294 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits 2295 int op = (Assembler::arith_op << 30) | 2296 ($dst$$reg << 25) | 2297 (Assembler::movcc_op3 << 19) | 2298 (1 << 18) | // cc2 bit for 'icc' 2299 ($cmp$$cmpcode << 14) | 2300 (1 << 13) | // select immediate move 2301 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc' 2302 (simm11 << 0); 2303 *((int*)(cbuf.code_end())) = op; 2304 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); 2305 %} 2306 2307 enc_class enc_cmov_reg_f( cmpOpF cmp, iRegI dst, iRegI src, flagsRegF fcc ) %{ 2308 int op = (Assembler::arith_op << 30) | 2309 ($dst$$reg << 25) | 2310 (Assembler::movcc_op3 << 19) | 2311 (0 << 18) | // cc2 bit for 'fccX' 2312 ($cmp$$cmpcode << 14) | 2313 (0 << 13) | // select register move 2314 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3 2315 ($src$$reg << 0); 2316 *((int*)(cbuf.code_end())) = op; 2317 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); 2318 %} 2319 2320 enc_class enc_cmov_imm_f( cmpOp cmp, iRegI dst, immI11 src, flagsRegF fcc ) %{ 2321 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits 2322 int op = (Assembler::arith_op << 30) | 2323 ($dst$$reg << 25) | 2324 (Assembler::movcc_op3 << 19) | 2325 (0 << 18) | // cc2 bit for 'fccX' 2326 ($cmp$$cmpcode << 14) | 2327 (1 << 13) | // select immediate move 2328 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3 2329 (simm11 << 0); 2330 *((int*)(cbuf.code_end())) = op; 2331 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); 2332 %} 2333 2334 enc_class enc_cmovf_reg( cmpOp cmp, regD dst, regD src, immI pcc ) %{ 2335 int op = (Assembler::arith_op << 30) | 2336 ($dst$$reg << 25) | 2337 (Assembler::fpop2_op3 << 19) | 2338 (0 << 18) | 2339 ($cmp$$cmpcode << 14) | 2340 (1 << 13) | // select register move 2341 ($pcc$$constant << 11) | // cc1-cc0 bits for 'icc' or 'xcc' 2342 ($primary << 5) | // select single, double or quad 2343 ($src$$reg << 0); 2344 *((int*)(cbuf.code_end())) = op; 2345 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); 2346 %} 2347 2348 enc_class enc_cmovff_reg( cmpOpF cmp, flagsRegF fcc, regD dst, regD src ) %{ 2349 int op = (Assembler::arith_op << 30) | 2350 ($dst$$reg << 25) | 2351 (Assembler::fpop2_op3 << 19) | 2352 (0 << 18) | 2353 ($cmp$$cmpcode << 14) | 2354 ($fcc$$reg << 11) | // cc2-cc0 bits for 'fccX' 2355 ($primary << 5) | // select single, double or quad 2356 ($src$$reg << 0); 2357 *((int*)(cbuf.code_end())) = op; 2358 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); 2359 %} 2360 2361 // Used by the MIN/MAX encodings. Same as a CMOV, but 2362 // the condition comes from opcode-field instead of an argument. 2363 enc_class enc_cmov_reg_minmax( iRegI dst, iRegI src ) %{ 2364 int op = (Assembler::arith_op << 30) | 2365 ($dst$$reg << 25) | 2366 (Assembler::movcc_op3 << 19) | 2367 (1 << 18) | // cc2 bit for 'icc' 2368 ($primary << 14) | 2369 (0 << 13) | // select register move 2370 (0 << 11) | // cc1, cc0 bits for 'icc' 2371 ($src$$reg << 0); 2372 *((int*)(cbuf.code_end())) = op; 2373 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); 2374 %} 2375 2376 enc_class enc_cmov_reg_minmax_long( iRegL dst, iRegL src ) %{ 2377 int op = (Assembler::arith_op << 30) | 2378 ($dst$$reg << 25) | 2379 (Assembler::movcc_op3 << 19) | 2380 (6 << 16) | // cc2 bit for 'xcc' 2381 ($primary << 14) | 2382 (0 << 13) | // select register move 2383 (0 << 11) | // cc1, cc0 bits for 'icc' 2384 ($src$$reg << 0); 2385 *((int*)(cbuf.code_end())) = op; 2386 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); 2387 %} 2388 2389 // Utility encoding for loading a 64 bit Pointer into a register 2390 // The 64 bit pointer is stored in the generated code stream 2391 enc_class SetPtr( immP src, iRegP rd ) %{ 2392 Register dest = reg_to_register_object($rd$$reg); 2393 MacroAssembler _masm(&cbuf); 2394 // [RGV] This next line should be generated from ADLC 2395 if ( _opnds[1]->constant_is_oop() ) { 2396 intptr_t val = $src$$constant; 2397 __ set_oop_constant((jobject)val, dest); 2398 } else { // non-oop pointers, e.g. card mark base, heap top 2399 __ set($src$$constant, dest); 2400 } 2401 %} 2402 2403 enc_class Set13( immI13 src, iRegI rd ) %{ 2404 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, $src$$constant ); 2405 %} 2406 2407 enc_class SetHi22( immI src, iRegI rd ) %{ 2408 emit2_22( cbuf, Assembler::branch_op, $rd$$reg, Assembler::sethi_op2, $src$$constant ); 2409 %} 2410 2411 enc_class Set32( immI src, iRegI rd ) %{ 2412 MacroAssembler _masm(&cbuf); 2413 __ set($src$$constant, reg_to_register_object($rd$$reg)); 2414 %} 2415 2416 enc_class SetNull( iRegI rd ) %{ 2417 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0 ); 2418 %} 2419 2420 enc_class call_epilog %{ 2421 if( VerifyStackAtCalls ) { 2422 MacroAssembler _masm(&cbuf); 2423 int framesize = ra_->C->frame_slots() << LogBytesPerInt; 2424 Register temp_reg = G3; 2425 __ add(SP, framesize, temp_reg); 2426 __ cmp(temp_reg, FP); 2427 __ breakpoint_trap(Assembler::notEqual, Assembler::ptr_cc); 2428 } 2429 %} 2430 2431 // Long values come back from native calls in O0:O1 in the 32-bit VM, copy the value 2432 // to G1 so the register allocator will not have to deal with the misaligned register 2433 // pair. 2434 enc_class adjust_long_from_native_call %{ 2435 #ifndef _LP64 2436 if (returns_long()) { 2437 // sllx O0,32,O0 2438 emit3_simm13( cbuf, Assembler::arith_op, R_O0_enc, Assembler::sllx_op3, R_O0_enc, 0x1020 ); 2439 // srl O1,0,O1 2440 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::srl_op3, R_O1_enc, 0x0000 ); 2441 // or O0,O1,G1 2442 emit3 ( cbuf, Assembler::arith_op, R_G1_enc, Assembler:: or_op3, R_O0_enc, 0, R_O1_enc ); 2443 } 2444 #endif 2445 %} 2446 2447 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime 2448 // CALL directly to the runtime 2449 // The user of this is responsible for ensuring that R_L7 is empty (killed). 2450 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type, 2451 /*preserve_g2=*/true, /*force far call*/true); 2452 %} 2453 2454 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL 2455 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine 2456 // who we intended to call. 2457 if ( !_method ) { 2458 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type); 2459 } else if (_optimized_virtual) { 2460 emit_call_reloc(cbuf, $meth$$method, relocInfo::opt_virtual_call_type); 2461 } else { 2462 emit_call_reloc(cbuf, $meth$$method, relocInfo::static_call_type); 2463 } 2464 if( _method ) { // Emit stub for static call 2465 emit_java_to_interp(cbuf); 2466 } 2467 %} 2468 2469 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL 2470 MacroAssembler _masm(&cbuf); 2471 __ set_inst_mark(); 2472 int vtable_index = this->_vtable_index; 2473 // MachCallDynamicJavaNode::ret_addr_offset uses this same test 2474 if (vtable_index < 0) { 2475 // must be invalid_vtable_index, not nonvirtual_vtable_index 2476 assert(vtable_index == methodOopDesc::invalid_vtable_index, "correct sentinel value"); 2477 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode()); 2478 assert(G5_ic_reg == G5_inline_cache_reg, "G5_inline_cache_reg used in assemble_ic_buffer_code()"); 2479 assert(G5_ic_reg == G5_megamorphic_method, "G5_megamorphic_method used in megamorphic call stub"); 2480 // !!!!! 2481 // Generate "set 0x01, R_G5", placeholder instruction to load oop-info 2482 // emit_call_dynamic_prologue( cbuf ); 2483 __ set_oop((jobject)Universe::non_oop_word(), G5_ic_reg); 2484 2485 address virtual_call_oop_addr = __ inst_mark(); 2486 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine 2487 // who we intended to call. 2488 __ relocate(virtual_call_Relocation::spec(virtual_call_oop_addr)); 2489 emit_call_reloc(cbuf, $meth$$method, relocInfo::none); 2490 } else { 2491 assert(!UseInlineCaches, "expect vtable calls only if not using ICs"); 2492 // Just go thru the vtable 2493 // get receiver klass (receiver already checked for non-null) 2494 // If we end up going thru a c2i adapter interpreter expects method in G5 2495 int off = __ offset(); 2496 __ load_klass(O0, G3_scratch); 2497 int klass_load_size; 2498 if (UseCompressedOops) { 2499 assert(Universe::heap() != NULL, "java heap should be initialized"); 2500 if (Universe::narrow_oop_base() == NULL) 2501 klass_load_size = 2*BytesPerInstWord; 2502 else 2503 klass_load_size = 3*BytesPerInstWord; 2504 } else { 2505 klass_load_size = 1*BytesPerInstWord; 2506 } 2507 int entry_offset = instanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size(); 2508 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes(); 2509 if( __ is_simm13(v_off) ) { 2510 __ ld_ptr(G3, v_off, G5_method); 2511 } else { 2512 // Generate 2 instructions 2513 __ Assembler::sethi(v_off & ~0x3ff, G5_method); 2514 __ or3(G5_method, v_off & 0x3ff, G5_method); 2515 // ld_ptr, set_hi, set 2516 assert(__ offset() - off == klass_load_size + 2*BytesPerInstWord, 2517 "Unexpected instruction size(s)"); 2518 __ ld_ptr(G3, G5_method, G5_method); 2519 } 2520 // NOTE: for vtable dispatches, the vtable entry will never be null. 2521 // However it may very well end up in handle_wrong_method if the 2522 // method is abstract for the particular class. 2523 __ ld_ptr(G5_method, in_bytes(methodOopDesc::from_compiled_offset()), G3_scratch); 2524 // jump to target (either compiled code or c2iadapter) 2525 __ jmpl(G3_scratch, G0, O7); 2526 __ delayed()->nop(); 2527 } 2528 %} 2529 2530 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL 2531 MacroAssembler _masm(&cbuf); 2532 2533 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode()); 2534 Register temp_reg = G3; // caller must kill G3! We cannot reuse G5_ic_reg here because 2535 // we might be calling a C2I adapter which needs it. 2536 2537 assert(temp_reg != G5_ic_reg, "conflicting registers"); 2538 // Load nmethod 2539 __ ld_ptr(G5_ic_reg, in_bytes(methodOopDesc::from_compiled_offset()), temp_reg); 2540 2541 // CALL to compiled java, indirect the contents of G3 2542 __ set_inst_mark(); 2543 __ callr(temp_reg, G0); 2544 __ delayed()->nop(); 2545 %} 2546 2547 enc_class idiv_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst) %{ 2548 MacroAssembler _masm(&cbuf); 2549 Register Rdividend = reg_to_register_object($src1$$reg); 2550 Register Rdivisor = reg_to_register_object($src2$$reg); 2551 Register Rresult = reg_to_register_object($dst$$reg); 2552 2553 __ sra(Rdivisor, 0, Rdivisor); 2554 __ sra(Rdividend, 0, Rdividend); 2555 __ sdivx(Rdividend, Rdivisor, Rresult); 2556 %} 2557 2558 enc_class idiv_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst) %{ 2559 MacroAssembler _masm(&cbuf); 2560 2561 Register Rdividend = reg_to_register_object($src1$$reg); 2562 int divisor = $imm$$constant; 2563 Register Rresult = reg_to_register_object($dst$$reg); 2564 2565 __ sra(Rdividend, 0, Rdividend); 2566 __ sdivx(Rdividend, divisor, Rresult); 2567 %} 2568 2569 enc_class enc_mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2) %{ 2570 MacroAssembler _masm(&cbuf); 2571 Register Rsrc1 = reg_to_register_object($src1$$reg); 2572 Register Rsrc2 = reg_to_register_object($src2$$reg); 2573 Register Rdst = reg_to_register_object($dst$$reg); 2574 2575 __ sra( Rsrc1, 0, Rsrc1 ); 2576 __ sra( Rsrc2, 0, Rsrc2 ); 2577 __ mulx( Rsrc1, Rsrc2, Rdst ); 2578 __ srlx( Rdst, 32, Rdst ); 2579 %} 2580 2581 enc_class irem_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst, o7RegL scratch) %{ 2582 MacroAssembler _masm(&cbuf); 2583 Register Rdividend = reg_to_register_object($src1$$reg); 2584 Register Rdivisor = reg_to_register_object($src2$$reg); 2585 Register Rresult = reg_to_register_object($dst$$reg); 2586 Register Rscratch = reg_to_register_object($scratch$$reg); 2587 2588 assert(Rdividend != Rscratch, ""); 2589 assert(Rdivisor != Rscratch, ""); 2590 2591 __ sra(Rdividend, 0, Rdividend); 2592 __ sra(Rdivisor, 0, Rdivisor); 2593 __ sdivx(Rdividend, Rdivisor, Rscratch); 2594 __ mulx(Rscratch, Rdivisor, Rscratch); 2595 __ sub(Rdividend, Rscratch, Rresult); 2596 %} 2597 2598 enc_class irem_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst, o7RegL scratch) %{ 2599 MacroAssembler _masm(&cbuf); 2600 2601 Register Rdividend = reg_to_register_object($src1$$reg); 2602 int divisor = $imm$$constant; 2603 Register Rresult = reg_to_register_object($dst$$reg); 2604 Register Rscratch = reg_to_register_object($scratch$$reg); 2605 2606 assert(Rdividend != Rscratch, ""); 2607 2608 __ sra(Rdividend, 0, Rdividend); 2609 __ sdivx(Rdividend, divisor, Rscratch); 2610 __ mulx(Rscratch, divisor, Rscratch); 2611 __ sub(Rdividend, Rscratch, Rresult); 2612 %} 2613 2614 enc_class fabss (sflt_reg dst, sflt_reg src) %{ 2615 MacroAssembler _masm(&cbuf); 2616 2617 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg); 2618 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg); 2619 2620 __ fabs(FloatRegisterImpl::S, Fsrc, Fdst); 2621 %} 2622 2623 enc_class fabsd (dflt_reg dst, dflt_reg src) %{ 2624 MacroAssembler _masm(&cbuf); 2625 2626 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); 2627 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); 2628 2629 __ fabs(FloatRegisterImpl::D, Fsrc, Fdst); 2630 %} 2631 2632 enc_class fnegd (dflt_reg dst, dflt_reg src) %{ 2633 MacroAssembler _masm(&cbuf); 2634 2635 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); 2636 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); 2637 2638 __ fneg(FloatRegisterImpl::D, Fsrc, Fdst); 2639 %} 2640 2641 enc_class fsqrts (sflt_reg dst, sflt_reg src) %{ 2642 MacroAssembler _masm(&cbuf); 2643 2644 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg); 2645 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg); 2646 2647 __ fsqrt(FloatRegisterImpl::S, Fsrc, Fdst); 2648 %} 2649 2650 enc_class fsqrtd (dflt_reg dst, dflt_reg src) %{ 2651 MacroAssembler _masm(&cbuf); 2652 2653 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); 2654 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); 2655 2656 __ fsqrt(FloatRegisterImpl::D, Fsrc, Fdst); 2657 %} 2658 2659 enc_class fmovs (dflt_reg dst, dflt_reg src) %{ 2660 MacroAssembler _masm(&cbuf); 2661 2662 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg); 2663 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg); 2664 2665 __ fmov(FloatRegisterImpl::S, Fsrc, Fdst); 2666 %} 2667 2668 enc_class fmovd (dflt_reg dst, dflt_reg src) %{ 2669 MacroAssembler _masm(&cbuf); 2670 2671 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); 2672 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); 2673 2674 __ fmov(FloatRegisterImpl::D, Fsrc, Fdst); 2675 %} 2676 2677 enc_class Fast_Lock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{ 2678 MacroAssembler _masm(&cbuf); 2679 2680 Register Roop = reg_to_register_object($oop$$reg); 2681 Register Rbox = reg_to_register_object($box$$reg); 2682 Register Rscratch = reg_to_register_object($scratch$$reg); 2683 Register Rmark = reg_to_register_object($scratch2$$reg); 2684 2685 assert(Roop != Rscratch, ""); 2686 assert(Roop != Rmark, ""); 2687 assert(Rbox != Rscratch, ""); 2688 assert(Rbox != Rmark, ""); 2689 2690 __ compiler_lock_object(Roop, Rmark, Rbox, Rscratch, _counters, UseBiasedLocking && !UseOptoBiasInlining); 2691 %} 2692 2693 enc_class Fast_Unlock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{ 2694 MacroAssembler _masm(&cbuf); 2695 2696 Register Roop = reg_to_register_object($oop$$reg); 2697 Register Rbox = reg_to_register_object($box$$reg); 2698 Register Rscratch = reg_to_register_object($scratch$$reg); 2699 Register Rmark = reg_to_register_object($scratch2$$reg); 2700 2701 assert(Roop != Rscratch, ""); 2702 assert(Roop != Rmark, ""); 2703 assert(Rbox != Rscratch, ""); 2704 assert(Rbox != Rmark, ""); 2705 2706 __ compiler_unlock_object(Roop, Rmark, Rbox, Rscratch, UseBiasedLocking && !UseOptoBiasInlining); 2707 %} 2708 2709 enc_class enc_cas( iRegP mem, iRegP old, iRegP new ) %{ 2710 MacroAssembler _masm(&cbuf); 2711 Register Rmem = reg_to_register_object($mem$$reg); 2712 Register Rold = reg_to_register_object($old$$reg); 2713 Register Rnew = reg_to_register_object($new$$reg); 2714 2715 // casx_under_lock picks 1 of 3 encodings: 2716 // For 32-bit pointers you get a 32-bit CAS 2717 // For 64-bit pointers you get a 64-bit CASX 2718 __ casn(Rmem, Rold, Rnew); // Swap(*Rmem,Rnew) if *Rmem == Rold 2719 __ cmp( Rold, Rnew ); 2720 %} 2721 2722 enc_class enc_casx( iRegP mem, iRegL old, iRegL new) %{ 2723 Register Rmem = reg_to_register_object($mem$$reg); 2724 Register Rold = reg_to_register_object($old$$reg); 2725 Register Rnew = reg_to_register_object($new$$reg); 2726 2727 MacroAssembler _masm(&cbuf); 2728 __ mov(Rnew, O7); 2729 __ casx(Rmem, Rold, O7); 2730 __ cmp( Rold, O7 ); 2731 %} 2732 2733 // raw int cas, used for compareAndSwap 2734 enc_class enc_casi( iRegP mem, iRegL old, iRegL new) %{ 2735 Register Rmem = reg_to_register_object($mem$$reg); 2736 Register Rold = reg_to_register_object($old$$reg); 2737 Register Rnew = reg_to_register_object($new$$reg); 2738 2739 MacroAssembler _masm(&cbuf); 2740 __ mov(Rnew, O7); 2741 __ cas(Rmem, Rold, O7); 2742 __ cmp( Rold, O7 ); 2743 %} 2744 2745 enc_class enc_lflags_ne_to_boolean( iRegI res ) %{ 2746 Register Rres = reg_to_register_object($res$$reg); 2747 2748 MacroAssembler _masm(&cbuf); 2749 __ mov(1, Rres); 2750 __ movcc( Assembler::notEqual, false, Assembler::xcc, G0, Rres ); 2751 %} 2752 2753 enc_class enc_iflags_ne_to_boolean( iRegI res ) %{ 2754 Register Rres = reg_to_register_object($res$$reg); 2755 2756 MacroAssembler _masm(&cbuf); 2757 __ mov(1, Rres); 2758 __ movcc( Assembler::notEqual, false, Assembler::icc, G0, Rres ); 2759 %} 2760 2761 enc_class floating_cmp ( iRegP dst, regF src1, regF src2 ) %{ 2762 MacroAssembler _masm(&cbuf); 2763 Register Rdst = reg_to_register_object($dst$$reg); 2764 FloatRegister Fsrc1 = $primary ? reg_to_SingleFloatRegister_object($src1$$reg) 2765 : reg_to_DoubleFloatRegister_object($src1$$reg); 2766 FloatRegister Fsrc2 = $primary ? reg_to_SingleFloatRegister_object($src2$$reg) 2767 : reg_to_DoubleFloatRegister_object($src2$$reg); 2768 2769 // Convert condition code fcc0 into -1,0,1; unordered reports less-than (-1) 2770 __ float_cmp( $primary, -1, Fsrc1, Fsrc2, Rdst); 2771 %} 2772 2773 enc_class LdImmL (immL src, iRegL dst, o7RegL tmp) %{ // Load Immediate 2774 MacroAssembler _masm(&cbuf); 2775 Register dest = reg_to_register_object($dst$$reg); 2776 Register temp = reg_to_register_object($tmp$$reg); 2777 __ set64( $src$$constant, dest, temp ); 2778 %} 2779 2780 enc_class LdReplImmI(immI src, regD dst, o7RegP tmp, int count, int width) %{ 2781 // Load a constant replicated "count" times with width "width" 2782 int bit_width = $width$$constant * 8; 2783 jlong elt_val = $src$$constant; 2784 elt_val &= (((jlong)1) << bit_width) - 1; // mask off sign bits 2785 jlong val = elt_val; 2786 for (int i = 0; i < $count$$constant - 1; i++) { 2787 val <<= bit_width; 2788 val |= elt_val; 2789 } 2790 jdouble dval = *(jdouble*)&val; // coerce to double type 2791 MacroAssembler _masm(&cbuf); 2792 address double_address = __ double_constant(dval); 2793 RelocationHolder rspec = internal_word_Relocation::spec(double_address); 2794 AddressLiteral addrlit(double_address, rspec); 2795 2796 __ sethi(addrlit, $tmp$$Register); 2797 __ ldf(FloatRegisterImpl::D, $tmp$$Register, addrlit.low10(), $dst$$FloatRegister, rspec); 2798 %} 2799 2800 // Compiler ensures base is doubleword aligned and cnt is count of doublewords 2801 enc_class enc_Clear_Array(iRegX cnt, iRegP base, iRegX temp) %{ 2802 MacroAssembler _masm(&cbuf); 2803 Register nof_bytes_arg = reg_to_register_object($cnt$$reg); 2804 Register nof_bytes_tmp = reg_to_register_object($temp$$reg); 2805 Register base_pointer_arg = reg_to_register_object($base$$reg); 2806 2807 Label loop; 2808 __ mov(nof_bytes_arg, nof_bytes_tmp); 2809 2810 // Loop and clear, walking backwards through the array. 2811 // nof_bytes_tmp (if >0) is always the number of bytes to zero 2812 __ bind(loop); 2813 __ deccc(nof_bytes_tmp, 8); 2814 __ br(Assembler::greaterEqual, true, Assembler::pt, loop); 2815 __ delayed()-> stx(G0, base_pointer_arg, nof_bytes_tmp); 2816 // %%%% this mini-loop must not cross a cache boundary! 2817 %} 2818 2819 2820 enc_class enc_String_Compare(o0RegP str1, o1RegP str2, g3RegP tmp1, g4RegP tmp2, notemp_iRegI result) %{ 2821 Label Ldone, Lloop; 2822 MacroAssembler _masm(&cbuf); 2823 2824 Register str1_reg = reg_to_register_object($str1$$reg); 2825 Register str2_reg = reg_to_register_object($str2$$reg); 2826 Register tmp1_reg = reg_to_register_object($tmp1$$reg); 2827 Register tmp2_reg = reg_to_register_object($tmp2$$reg); 2828 Register result_reg = reg_to_register_object($result$$reg); 2829 2830 // Get the first character position in both strings 2831 // [8] char array, [12] offset, [16] count 2832 int value_offset = java_lang_String:: value_offset_in_bytes(); 2833 int offset_offset = java_lang_String::offset_offset_in_bytes(); 2834 int count_offset = java_lang_String:: count_offset_in_bytes(); 2835 2836 // load str1 (jchar*) base address into tmp1_reg 2837 __ load_heap_oop(str1_reg, value_offset, tmp1_reg); 2838 __ ld(str1_reg, offset_offset, result_reg); 2839 __ add(tmp1_reg, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp1_reg); 2840 __ ld(str1_reg, count_offset, str1_reg); // hoisted 2841 __ sll(result_reg, exact_log2(sizeof(jchar)), result_reg); 2842 __ load_heap_oop(str2_reg, value_offset, tmp2_reg); // hoisted 2843 __ add(result_reg, tmp1_reg, tmp1_reg); 2844 2845 // load str2 (jchar*) base address into tmp2_reg 2846 // __ ld_ptr(str2_reg, value_offset, tmp2_reg); // hoisted 2847 __ ld(str2_reg, offset_offset, result_reg); 2848 __ add(tmp2_reg, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp2_reg); 2849 __ ld(str2_reg, count_offset, str2_reg); // hoisted 2850 __ sll(result_reg, exact_log2(sizeof(jchar)), result_reg); 2851 __ subcc(str1_reg, str2_reg, O7); // hoisted 2852 __ add(result_reg, tmp2_reg, tmp2_reg); 2853 2854 // Compute the minimum of the string lengths(str1_reg) and the 2855 // difference of the string lengths (stack) 2856 2857 // discard string base pointers, after loading up the lengths 2858 // __ ld(str1_reg, count_offset, str1_reg); // hoisted 2859 // __ ld(str2_reg, count_offset, str2_reg); // hoisted 2860 2861 // See if the lengths are different, and calculate min in str1_reg. 2862 // Stash diff in O7 in case we need it for a tie-breaker. 2863 Label Lskip; 2864 // __ subcc(str1_reg, str2_reg, O7); // hoisted 2865 __ sll(str1_reg, exact_log2(sizeof(jchar)), str1_reg); // scale the limit 2866 __ br(Assembler::greater, true, Assembler::pt, Lskip); 2867 // str2 is shorter, so use its count: 2868 __ delayed()->sll(str2_reg, exact_log2(sizeof(jchar)), str1_reg); // scale the limit 2869 __ bind(Lskip); 2870 2871 // reallocate str1_reg, str2_reg, result_reg 2872 // Note: limit_reg holds the string length pre-scaled by 2 2873 Register limit_reg = str1_reg; 2874 Register chr2_reg = str2_reg; 2875 Register chr1_reg = result_reg; 2876 // tmp{12} are the base pointers 2877 2878 // Is the minimum length zero? 2879 __ cmp(limit_reg, (int)(0 * sizeof(jchar))); // use cast to resolve overloading ambiguity 2880 __ br(Assembler::equal, true, Assembler::pn, Ldone); 2881 __ delayed()->mov(O7, result_reg); // result is difference in lengths 2882 2883 // Load first characters 2884 __ lduh(tmp1_reg, 0, chr1_reg); 2885 __ lduh(tmp2_reg, 0, chr2_reg); 2886 2887 // Compare first characters 2888 __ subcc(chr1_reg, chr2_reg, chr1_reg); 2889 __ br(Assembler::notZero, false, Assembler::pt, Ldone); 2890 assert(chr1_reg == result_reg, "result must be pre-placed"); 2891 __ delayed()->nop(); 2892 2893 { 2894 // Check after comparing first character to see if strings are equivalent 2895 Label LSkip2; 2896 // Check if the strings start at same location 2897 __ cmp(tmp1_reg, tmp2_reg); 2898 __ brx(Assembler::notEqual, true, Assembler::pt, LSkip2); 2899 __ delayed()->nop(); 2900 2901 // Check if the length difference is zero (in O7) 2902 __ cmp(G0, O7); 2903 __ br(Assembler::equal, true, Assembler::pn, Ldone); 2904 __ delayed()->mov(G0, result_reg); // result is zero 2905 2906 // Strings might not be equal 2907 __ bind(LSkip2); 2908 } 2909 2910 __ subcc(limit_reg, 1 * sizeof(jchar), chr1_reg); 2911 __ br(Assembler::equal, true, Assembler::pn, Ldone); 2912 __ delayed()->mov(O7, result_reg); // result is difference in lengths 2913 2914 // Shift tmp1_reg and tmp2_reg to the end of the arrays, negate limit 2915 __ add(tmp1_reg, limit_reg, tmp1_reg); 2916 __ add(tmp2_reg, limit_reg, tmp2_reg); 2917 __ neg(chr1_reg, limit_reg); // limit = -(limit-2) 2918 2919 // Compare the rest of the characters 2920 __ lduh(tmp1_reg, limit_reg, chr1_reg); 2921 __ bind(Lloop); 2922 // __ lduh(tmp1_reg, limit_reg, chr1_reg); // hoisted 2923 __ lduh(tmp2_reg, limit_reg, chr2_reg); 2924 __ subcc(chr1_reg, chr2_reg, chr1_reg); 2925 __ br(Assembler::notZero, false, Assembler::pt, Ldone); 2926 assert(chr1_reg == result_reg, "result must be pre-placed"); 2927 __ delayed()->inccc(limit_reg, sizeof(jchar)); 2928 // annul LDUH if branch is not taken to prevent access past end of string 2929 __ br(Assembler::notZero, true, Assembler::pt, Lloop); 2930 __ delayed()->lduh(tmp1_reg, limit_reg, chr1_reg); // hoisted 2931 2932 // If strings are equal up to min length, return the length difference. 2933 __ mov(O7, result_reg); 2934 2935 // Otherwise, return the difference between the first mismatched chars. 2936 __ bind(Ldone); 2937 %} 2938 2939 enc_class enc_String_Equals(o0RegP str1, o1RegP str2, g3RegP tmp1, g4RegP tmp2, notemp_iRegI result) %{ 2940 Label Lword, Lword_loop, Lpost_word, Lchar, Lchar_loop, Ldone; 2941 MacroAssembler _masm(&cbuf); 2942 2943 Register str1_reg = reg_to_register_object($str1$$reg); 2944 Register str2_reg = reg_to_register_object($str2$$reg); 2945 Register tmp1_reg = reg_to_register_object($tmp1$$reg); 2946 Register tmp2_reg = reg_to_register_object($tmp2$$reg); 2947 Register result_reg = reg_to_register_object($result$$reg); 2948 2949 // Get the first character position in both strings 2950 // [8] char array, [12] offset, [16] count 2951 int value_offset = java_lang_String:: value_offset_in_bytes(); 2952 int offset_offset = java_lang_String::offset_offset_in_bytes(); 2953 int count_offset = java_lang_String:: count_offset_in_bytes(); 2954 2955 // load str1 (jchar*) base address into tmp1_reg 2956 __ load_heap_oop(Address(str1_reg, value_offset), tmp1_reg); 2957 __ ld(Address(str1_reg, offset_offset), result_reg); 2958 __ add(tmp1_reg, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp1_reg); 2959 __ ld(Address(str1_reg, count_offset), str1_reg); // hoisted 2960 __ sll(result_reg, exact_log2(sizeof(jchar)), result_reg); 2961 __ load_heap_oop(Address(str2_reg, value_offset), tmp2_reg); // hoisted 2962 __ add(result_reg, tmp1_reg, tmp1_reg); 2963 2964 // load str2 (jchar*) base address into tmp2_reg 2965 // __ ld_ptr(Address(str2_reg, value_offset), tmp2_reg); // hoisted 2966 __ ld(Address(str2_reg, offset_offset), result_reg); 2967 __ add(tmp2_reg, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp2_reg); 2968 __ ld(Address(str2_reg, count_offset), str2_reg); // hoisted 2969 __ sll(result_reg, exact_log2(sizeof(jchar)), result_reg); 2970 __ cmp(str1_reg, str2_reg); // hoisted 2971 __ add(result_reg, tmp2_reg, tmp2_reg); 2972 2973 __ sll(str1_reg, exact_log2(sizeof(jchar)), str1_reg); 2974 __ br(Assembler::notEqual, true, Assembler::pt, Ldone); 2975 __ delayed()->mov(G0, result_reg); // not equal 2976 2977 __ br_zero(Assembler::equal, true, Assembler::pn, str1_reg, Ldone); 2978 __ delayed()->add(G0, 1, result_reg); //equals 2979 2980 __ cmp(tmp1_reg, tmp2_reg); //same string ? 2981 __ brx(Assembler::equal, true, Assembler::pn, Ldone); 2982 __ delayed()->add(G0, 1, result_reg); 2983 2984 //rename registers 2985 Register limit_reg = str1_reg; 2986 Register chr2_reg = str2_reg; 2987 Register chr1_reg = result_reg; 2988 // tmp{12} are the base pointers 2989 2990 //check for alignment and position the pointers to the ends 2991 __ or3(tmp1_reg, tmp2_reg, chr1_reg); 2992 __ andcc(chr1_reg, 0x3, chr1_reg); // notZero means at least one not 4-byte aligned 2993 __ br(Assembler::notZero, false, Assembler::pn, Lchar); 2994 __ delayed()->nop(); 2995 2996 __ bind(Lword); 2997 __ and3(limit_reg, 0x2, O7); //remember the remainder (either 0 or 2) 2998 __ andn(limit_reg, 0x3, limit_reg); 2999 __ br_zero(Assembler::zero, false, Assembler::pn, limit_reg, Lpost_word); 3000 __ delayed()->nop(); 3001 3002 __ add(tmp1_reg, limit_reg, tmp1_reg); 3003 __ add(tmp2_reg, limit_reg, tmp2_reg); 3004 __ neg(limit_reg); 3005 3006 __ lduw(tmp1_reg, limit_reg, chr1_reg); 3007 __ bind(Lword_loop); 3008 __ lduw(tmp2_reg, limit_reg, chr2_reg); 3009 __ cmp(chr1_reg, chr2_reg); 3010 __ br(Assembler::notEqual, true, Assembler::pt, Ldone); 3011 __ delayed()->mov(G0, result_reg); 3012 __ inccc(limit_reg, 2*sizeof(jchar)); 3013 // annul LDUW if branch i s not taken to prevent access past end of string 3014 __ br(Assembler::notZero, true, Assembler::pt, Lword_loop); //annul on taken 3015 __ delayed()->lduw(tmp1_reg, limit_reg, chr1_reg); // hoisted 3016 3017 __ bind(Lpost_word); 3018 __ br_zero(Assembler::zero, true, Assembler::pt, O7, Ldone); 3019 __ delayed()->add(G0, 1, result_reg); 3020 3021 __ lduh(tmp1_reg, 0, chr1_reg); 3022 __ lduh(tmp2_reg, 0, chr2_reg); 3023 __ cmp (chr1_reg, chr2_reg); 3024 __ br(Assembler::notEqual, true, Assembler::pt, Ldone); 3025 __ delayed()->mov(G0, result_reg); 3026 __ ba(false,Ldone); 3027 __ delayed()->add(G0, 1, result_reg); 3028 3029 __ bind(Lchar); 3030 __ add(tmp1_reg, limit_reg, tmp1_reg); 3031 __ add(tmp2_reg, limit_reg, tmp2_reg); 3032 __ neg(limit_reg); //negate count 3033 3034 __ lduh(tmp1_reg, limit_reg, chr1_reg); 3035 __ bind(Lchar_loop); 3036 __ lduh(tmp2_reg, limit_reg, chr2_reg); 3037 __ cmp(chr1_reg, chr2_reg); 3038 __ br(Assembler::notEqual, true, Assembler::pt, Ldone); 3039 __ delayed()->mov(G0, result_reg); //not equal 3040 __ inccc(limit_reg, sizeof(jchar)); 3041 // annul LDUH if branch is not taken to prevent access past end of string 3042 __ br(Assembler::notZero, true, Assembler::pt, Lchar_loop); //annul on taken 3043 __ delayed()->lduh(tmp1_reg, limit_reg, chr1_reg); // hoisted 3044 3045 __ add(G0, 1, result_reg); //equal 3046 3047 __ bind(Ldone); 3048 %} 3049 3050 enc_class enc_Array_Equals(o0RegP ary1, o1RegP ary2, g3RegP tmp1, g4RegP tmp2, notemp_iRegI result) %{ 3051 Label Lvector, Ldone, Lloop; 3052 MacroAssembler _masm(&cbuf); 3053 3054 Register ary1_reg = reg_to_register_object($ary1$$reg); 3055 Register ary2_reg = reg_to_register_object($ary2$$reg); 3056 Register tmp1_reg = reg_to_register_object($tmp1$$reg); 3057 Register tmp2_reg = reg_to_register_object($tmp2$$reg); 3058 Register result_reg = reg_to_register_object($result$$reg); 3059 3060 int length_offset = arrayOopDesc::length_offset_in_bytes(); 3061 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR); 3062 3063 // return true if the same array 3064 __ cmp(ary1_reg, ary2_reg); 3065 __ br(Assembler::equal, true, Assembler::pn, Ldone); 3066 __ delayed()->add(G0, 1, result_reg); // equal 3067 3068 __ br_null(ary1_reg, true, Assembler::pn, Ldone); 3069 __ delayed()->mov(G0, result_reg); // not equal 3070 3071 __ br_null(ary2_reg, true, Assembler::pn, Ldone); 3072 __ delayed()->mov(G0, result_reg); // not equal 3073 3074 //load the lengths of arrays 3075 __ ld(Address(ary1_reg, length_offset), tmp1_reg); 3076 __ ld(Address(ary2_reg, length_offset), tmp2_reg); 3077 3078 // return false if the two arrays are not equal length 3079 __ cmp(tmp1_reg, tmp2_reg); 3080 __ br(Assembler::notEqual, true, Assembler::pn, Ldone); 3081 __ delayed()->mov(G0, result_reg); // not equal 3082 3083 __ br_zero(Assembler::zero, true, Assembler::pn, tmp1_reg, Ldone); 3084 __ delayed()->add(G0, 1, result_reg); // zero-length arrays are equal 3085 3086 // load array addresses 3087 __ add(ary1_reg, base_offset, ary1_reg); 3088 __ add(ary2_reg, base_offset, ary2_reg); 3089 3090 // renaming registers 3091 Register chr1_reg = tmp2_reg; // for characters in ary1 3092 Register chr2_reg = result_reg; // for characters in ary2 3093 Register limit_reg = tmp1_reg; // length 3094 3095 // set byte count 3096 __ sll(limit_reg, exact_log2(sizeof(jchar)), limit_reg); 3097 __ andcc(limit_reg, 0x2, chr1_reg); //trailing character ? 3098 __ br(Assembler::zero, false, Assembler::pt, Lvector); 3099 __ delayed()->nop(); 3100 3101 //compare the trailing char 3102 __ sub(limit_reg, sizeof(jchar), limit_reg); 3103 __ lduh(ary1_reg, limit_reg, chr1_reg); 3104 __ lduh(ary2_reg, limit_reg, chr2_reg); 3105 __ cmp(chr1_reg, chr2_reg); 3106 __ br(Assembler::notEqual, true, Assembler::pt, Ldone); 3107 __ delayed()->mov(G0, result_reg); // not equal 3108 3109 // only one char ? 3110 __ br_zero(Assembler::zero, true, Assembler::pn, limit_reg, Ldone); 3111 __ delayed()->add(G0, 1, result_reg); // zero-length arrays are equal 3112 3113 __ bind(Lvector); 3114 // Shift ary1_reg and ary2_reg to the end of the arrays, negate limit 3115 __ add(ary1_reg, limit_reg, ary1_reg); 3116 __ add(ary2_reg, limit_reg, ary2_reg); 3117 __ neg(limit_reg, limit_reg); 3118 3119 __ lduw(ary1_reg, limit_reg, chr1_reg); 3120 __ bind(Lloop); 3121 __ lduw(ary2_reg, limit_reg, chr2_reg); 3122 __ cmp(chr1_reg, chr2_reg); 3123 __ br(Assembler::notEqual, false, Assembler::pt, Ldone); 3124 __ delayed()->mov(G0, result_reg); // not equal 3125 __ inccc(limit_reg, 2*sizeof(jchar)); 3126 // annul LDUW if branch is not taken to prevent access past end of string 3127 __ br(Assembler::notZero, true, Assembler::pt, Lloop); //annul on taken 3128 __ delayed()->lduw(ary1_reg, limit_reg, chr1_reg); // hoisted 3129 3130 __ add(G0, 1, result_reg); // equals 3131 3132 __ bind(Ldone); 3133 %} 3134 3135 enc_class enc_rethrow() %{ 3136 cbuf.set_inst_mark(); 3137 Register temp_reg = G3; 3138 AddressLiteral rethrow_stub(OptoRuntime::rethrow_stub()); 3139 assert(temp_reg != reg_to_register_object(R_I0_num), "temp must not break oop_reg"); 3140 MacroAssembler _masm(&cbuf); 3141 #ifdef ASSERT 3142 __ save_frame(0); 3143 AddressLiteral last_rethrow_addrlit(&last_rethrow); 3144 __ sethi(last_rethrow_addrlit, L1); 3145 Address addr(L1, last_rethrow_addrlit.low10()); 3146 __ get_pc(L2); 3147 __ inc(L2, 3 * BytesPerInstWord); // skip this & 2 more insns to point at jump_to 3148 __ st_ptr(L2, addr); 3149 __ restore(); 3150 #endif 3151 __ JUMP(rethrow_stub, temp_reg, 0); // sethi;jmp 3152 __ delayed()->nop(); 3153 %} 3154 3155 enc_class emit_mem_nop() %{ 3156 // Generates the instruction LDUXA [o6,g0],#0x82,g0 3157 unsigned int *code = (unsigned int*)cbuf.code_end(); 3158 *code = (unsigned int)0xc0839040; 3159 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); 3160 %} 3161 3162 enc_class emit_fadd_nop() %{ 3163 // Generates the instruction FMOVS f31,f31 3164 unsigned int *code = (unsigned int*)cbuf.code_end(); 3165 *code = (unsigned int)0xbfa0003f; 3166 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); 3167 %} 3168 3169 enc_class emit_br_nop() %{ 3170 // Generates the instruction BPN,PN . 3171 unsigned int *code = (unsigned int*)cbuf.code_end(); 3172 *code = (unsigned int)0x00400000; 3173 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); 3174 %} 3175 3176 enc_class enc_membar_acquire %{ 3177 MacroAssembler _masm(&cbuf); 3178 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::LoadLoad) ); 3179 %} 3180 3181 enc_class enc_membar_release %{ 3182 MacroAssembler _masm(&cbuf); 3183 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::StoreStore) ); 3184 %} 3185 3186 enc_class enc_membar_volatile %{ 3187 MacroAssembler _masm(&cbuf); 3188 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad) ); 3189 %} 3190 3191 enc_class enc_repl8b( iRegI src, iRegL dst ) %{ 3192 MacroAssembler _masm(&cbuf); 3193 Register src_reg = reg_to_register_object($src$$reg); 3194 Register dst_reg = reg_to_register_object($dst$$reg); 3195 __ sllx(src_reg, 56, dst_reg); 3196 __ srlx(dst_reg, 8, O7); 3197 __ or3 (dst_reg, O7, dst_reg); 3198 __ srlx(dst_reg, 16, O7); 3199 __ or3 (dst_reg, O7, dst_reg); 3200 __ srlx(dst_reg, 32, O7); 3201 __ or3 (dst_reg, O7, dst_reg); 3202 %} 3203 3204 enc_class enc_repl4b( iRegI src, iRegL dst ) %{ 3205 MacroAssembler _masm(&cbuf); 3206 Register src_reg = reg_to_register_object($src$$reg); 3207 Register dst_reg = reg_to_register_object($dst$$reg); 3208 __ sll(src_reg, 24, dst_reg); 3209 __ srl(dst_reg, 8, O7); 3210 __ or3(dst_reg, O7, dst_reg); 3211 __ srl(dst_reg, 16, O7); 3212 __ or3(dst_reg, O7, dst_reg); 3213 %} 3214 3215 enc_class enc_repl4s( iRegI src, iRegL dst ) %{ 3216 MacroAssembler _masm(&cbuf); 3217 Register src_reg = reg_to_register_object($src$$reg); 3218 Register dst_reg = reg_to_register_object($dst$$reg); 3219 __ sllx(src_reg, 48, dst_reg); 3220 __ srlx(dst_reg, 16, O7); 3221 __ or3 (dst_reg, O7, dst_reg); 3222 __ srlx(dst_reg, 32, O7); 3223 __ or3 (dst_reg, O7, dst_reg); 3224 %} 3225 3226 enc_class enc_repl2i( iRegI src, iRegL dst ) %{ 3227 MacroAssembler _masm(&cbuf); 3228 Register src_reg = reg_to_register_object($src$$reg); 3229 Register dst_reg = reg_to_register_object($dst$$reg); 3230 __ sllx(src_reg, 32, dst_reg); 3231 __ srlx(dst_reg, 32, O7); 3232 __ or3 (dst_reg, O7, dst_reg); 3233 %} 3234 3235 %} 3236 3237 //----------FRAME-------------------------------------------------------------- 3238 // Definition of frame structure and management information. 3239 // 3240 // S T A C K L A Y O U T Allocators stack-slot number 3241 // | (to get allocators register number 3242 // G Owned by | | v add VMRegImpl::stack0) 3243 // r CALLER | | 3244 // o | +--------+ pad to even-align allocators stack-slot 3245 // w V | pad0 | numbers; owned by CALLER 3246 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned 3247 // h ^ | in | 5 3248 // | | args | 4 Holes in incoming args owned by SELF 3249 // | | | | 3 3250 // | | +--------+ 3251 // V | | old out| Empty on Intel, window on Sparc 3252 // | old |preserve| Must be even aligned. 3253 // | SP-+--------+----> Matcher::_old_SP, 8 (or 16 in LP64)-byte aligned 3254 // | | in | 3 area for Intel ret address 3255 // Owned by |preserve| Empty on Sparc. 3256 // SELF +--------+ 3257 // | | pad2 | 2 pad to align old SP 3258 // | +--------+ 1 3259 // | | locks | 0 3260 // | +--------+----> VMRegImpl::stack0, 8 (or 16 in LP64)-byte aligned 3261 // | | pad1 | 11 pad to align new SP 3262 // | +--------+ 3263 // | | | 10 3264 // | | spills | 9 spills 3265 // V | | 8 (pad0 slot for callee) 3266 // -----------+--------+----> Matcher::_out_arg_limit, unaligned 3267 // ^ | out | 7 3268 // | | args | 6 Holes in outgoing args owned by CALLEE 3269 // Owned by +--------+ 3270 // CALLEE | new out| 6 Empty on Intel, window on Sparc 3271 // | new |preserve| Must be even-aligned. 3272 // | SP-+--------+----> Matcher::_new_SP, even aligned 3273 // | | | 3274 // 3275 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is 3276 // known from SELF's arguments and the Java calling convention. 3277 // Region 6-7 is determined per call site. 3278 // Note 2: If the calling convention leaves holes in the incoming argument 3279 // area, those holes are owned by SELF. Holes in the outgoing area 3280 // are owned by the CALLEE. Holes should not be nessecary in the 3281 // incoming area, as the Java calling convention is completely under 3282 // the control of the AD file. Doubles can be sorted and packed to 3283 // avoid holes. Holes in the outgoing arguments may be nessecary for 3284 // varargs C calling conventions. 3285 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is 3286 // even aligned with pad0 as needed. 3287 // Region 6 is even aligned. Region 6-7 is NOT even aligned; 3288 // region 6-11 is even aligned; it may be padded out more so that 3289 // the region from SP to FP meets the minimum stack alignment. 3290 3291 frame %{ 3292 // What direction does stack grow in (assumed to be same for native & Java) 3293 stack_direction(TOWARDS_LOW); 3294 3295 // These two registers define part of the calling convention 3296 // between compiled code and the interpreter. 3297 inline_cache_reg(R_G5); // Inline Cache Register or methodOop for I2C 3298 interpreter_method_oop_reg(R_G5); // Method Oop Register when calling interpreter 3299 3300 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset] 3301 cisc_spilling_operand_name(indOffset); 3302 3303 // Number of stack slots consumed by a Monitor enter 3304 #ifdef _LP64 3305 sync_stack_slots(2); 3306 #else 3307 sync_stack_slots(1); 3308 #endif 3309 3310 // Compiled code's Frame Pointer 3311 frame_pointer(R_SP); 3312 3313 // Stack alignment requirement 3314 stack_alignment(StackAlignmentInBytes); 3315 // LP64: Alignment size in bytes (128-bit -> 16 bytes) 3316 // !LP64: Alignment size in bytes (64-bit -> 8 bytes) 3317 3318 // Number of stack slots between incoming argument block and the start of 3319 // a new frame. The PROLOG must add this many slots to the stack. The 3320 // EPILOG must remove this many slots. 3321 in_preserve_stack_slots(0); 3322 3323 // Number of outgoing stack slots killed above the out_preserve_stack_slots 3324 // for calls to C. Supports the var-args backing area for register parms. 3325 // ADLC doesn't support parsing expressions, so I folded the math by hand. 3326 #ifdef _LP64 3327 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (0)) * 2-stack-slots-per-word 3328 varargs_C_out_slots_killed(12); 3329 #else 3330 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (1)) * 1-stack-slots-per-word 3331 varargs_C_out_slots_killed( 7); 3332 #endif 3333 3334 // The after-PROLOG location of the return address. Location of 3335 // return address specifies a type (REG or STACK) and a number 3336 // representing the register number (i.e. - use a register name) or 3337 // stack slot. 3338 return_addr(REG R_I7); // Ret Addr is in register I7 3339 3340 // Body of function which returns an OptoRegs array locating 3341 // arguments either in registers or in stack slots for calling 3342 // java 3343 calling_convention %{ 3344 (void) SharedRuntime::java_calling_convention(sig_bt, regs, length, is_outgoing); 3345 3346 %} 3347 3348 // Body of function which returns an OptoRegs array locating 3349 // arguments either in registers or in stack slots for callin 3350 // C. 3351 c_calling_convention %{ 3352 // This is obviously always outgoing 3353 (void) SharedRuntime::c_calling_convention(sig_bt, regs, length); 3354 %} 3355 3356 // Location of native (C/C++) and interpreter return values. This is specified to 3357 // be the same as Java. In the 32-bit VM, long values are actually returned from 3358 // native calls in O0:O1 and returned to the interpreter in I0:I1. The copying 3359 // to and from the register pairs is done by the appropriate call and epilog 3360 // opcodes. This simplifies the register allocator. 3361 c_return_value %{ 3362 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" ); 3363 #ifdef _LP64 3364 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num }; 3365 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num}; 3366 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num }; 3367 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num}; 3368 #else // !_LP64 3369 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num }; 3370 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num }; 3371 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num }; 3372 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num }; 3373 #endif 3374 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg], 3375 (is_outgoing?lo_out:lo_in)[ideal_reg] ); 3376 %} 3377 3378 // Location of compiled Java return values. Same as C 3379 return_value %{ 3380 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" ); 3381 #ifdef _LP64 3382 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num }; 3383 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num}; 3384 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num }; 3385 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num}; 3386 #else // !_LP64 3387 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num }; 3388 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num}; 3389 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num }; 3390 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num}; 3391 #endif 3392 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg], 3393 (is_outgoing?lo_out:lo_in)[ideal_reg] ); 3394 %} 3395 3396 %} 3397 3398 3399 //----------ATTRIBUTES--------------------------------------------------------- 3400 //----------Operand Attributes------------------------------------------------- 3401 op_attrib op_cost(1); // Required cost attribute 3402 3403 //----------Instruction Attributes--------------------------------------------- 3404 ins_attrib ins_cost(DEFAULT_COST); // Required cost attribute 3405 ins_attrib ins_size(32); // Required size attribute (in bits) 3406 ins_attrib ins_pc_relative(0); // Required PC Relative flag 3407 ins_attrib ins_short_branch(0); // Required flag: is this instruction a 3408 // non-matching short branch variant of some 3409 // long branch? 3410 3411 //----------OPERANDS----------------------------------------------------------- 3412 // Operand definitions must precede instruction definitions for correct parsing 3413 // in the ADLC because operands constitute user defined types which are used in 3414 // instruction definitions. 3415 3416 //----------Simple Operands---------------------------------------------------- 3417 // Immediate Operands 3418 // Integer Immediate: 32-bit 3419 operand immI() %{ 3420 match(ConI); 3421 3422 op_cost(0); 3423 // formats are generated automatically for constants and base registers 3424 format %{ %} 3425 interface(CONST_INTER); 3426 %} 3427 3428 // Integer Immediate: 13-bit 3429 operand immI13() %{ 3430 predicate(Assembler::is_simm13(n->get_int())); 3431 match(ConI); 3432 op_cost(0); 3433 3434 format %{ %} 3435 interface(CONST_INTER); 3436 %} 3437 3438 // Unsigned (positive) Integer Immediate: 13-bit 3439 operand immU13() %{ 3440 predicate((0 <= n->get_int()) && Assembler::is_simm13(n->get_int())); 3441 match(ConI); 3442 op_cost(0); 3443 3444 format %{ %} 3445 interface(CONST_INTER); 3446 %} 3447 3448 // Integer Immediate: 6-bit 3449 operand immU6() %{ 3450 predicate(n->get_int() >= 0 && n->get_int() <= 63); 3451 match(ConI); 3452 op_cost(0); 3453 format %{ %} 3454 interface(CONST_INTER); 3455 %} 3456 3457 // Integer Immediate: 11-bit 3458 operand immI11() %{ 3459 predicate(Assembler::is_simm(n->get_int(),11)); 3460 match(ConI); 3461 op_cost(0); 3462 format %{ %} 3463 interface(CONST_INTER); 3464 %} 3465 3466 // Integer Immediate: 0-bit 3467 operand immI0() %{ 3468 predicate(n->get_int() == 0); 3469 match(ConI); 3470 op_cost(0); 3471 3472 format %{ %} 3473 interface(CONST_INTER); 3474 %} 3475 3476 // Integer Immediate: the value 10 3477 operand immI10() %{ 3478 predicate(n->get_int() == 10); 3479 match(ConI); 3480 op_cost(0); 3481 3482 format %{ %} 3483 interface(CONST_INTER); 3484 %} 3485 3486 // Integer Immediate: the values 0-31 3487 operand immU5() %{ 3488 predicate(n->get_int() >= 0 && n->get_int() <= 31); 3489 match(ConI); 3490 op_cost(0); 3491 3492 format %{ %} 3493 interface(CONST_INTER); 3494 %} 3495 3496 // Integer Immediate: the values 1-31 3497 operand immI_1_31() %{ 3498 predicate(n->get_int() >= 1 && n->get_int() <= 31); 3499 match(ConI); 3500 op_cost(0); 3501 3502 format %{ %} 3503 interface(CONST_INTER); 3504 %} 3505 3506 // Integer Immediate: the values 32-63 3507 operand immI_32_63() %{ 3508 predicate(n->get_int() >= 32 && n->get_int() <= 63); 3509 match(ConI); 3510 op_cost(0); 3511 3512 format %{ %} 3513 interface(CONST_INTER); 3514 %} 3515 3516 // Integer Immediate: the value 255 3517 operand immI_255() %{ 3518 predicate( n->get_int() == 255 ); 3519 match(ConI); 3520 op_cost(0); 3521 3522 format %{ %} 3523 interface(CONST_INTER); 3524 %} 3525 3526 // Long Immediate: the value FF 3527 operand immL_FF() %{ 3528 predicate( n->get_long() == 0xFFL ); 3529 match(ConL); 3530 op_cost(0); 3531 3532 format %{ %} 3533 interface(CONST_INTER); 3534 %} 3535 3536 // Long Immediate: the value FFFF 3537 operand immL_FFFF() %{ 3538 predicate( n->get_long() == 0xFFFFL ); 3539 match(ConL); 3540 op_cost(0); 3541 3542 format %{ %} 3543 interface(CONST_INTER); 3544 %} 3545 3546 // Pointer Immediate: 32 or 64-bit 3547 operand immP() %{ 3548 match(ConP); 3549 3550 op_cost(5); 3551 // formats are generated automatically for constants and base registers 3552 format %{ %} 3553 interface(CONST_INTER); 3554 %} 3555 3556 operand immP13() %{ 3557 predicate((-4096 < n->get_ptr()) && (n->get_ptr() <= 4095)); 3558 match(ConP); 3559 op_cost(0); 3560 3561 format %{ %} 3562 interface(CONST_INTER); 3563 %} 3564 3565 operand immP0() %{ 3566 predicate(n->get_ptr() == 0); 3567 match(ConP); 3568 op_cost(0); 3569 3570 format %{ %} 3571 interface(CONST_INTER); 3572 %} 3573 3574 operand immP_poll() %{ 3575 predicate(n->get_ptr() != 0 && n->get_ptr() == (intptr_t)os::get_polling_page()); 3576 match(ConP); 3577 3578 // formats are generated automatically for constants and base registers 3579 format %{ %} 3580 interface(CONST_INTER); 3581 %} 3582 3583 // Pointer Immediate 3584 operand immN() 3585 %{ 3586 match(ConN); 3587 3588 op_cost(10); 3589 format %{ %} 3590 interface(CONST_INTER); 3591 %} 3592 3593 // NULL Pointer Immediate 3594 operand immN0() 3595 %{ 3596 predicate(n->get_narrowcon() == 0); 3597 match(ConN); 3598 3599 op_cost(0); 3600 format %{ %} 3601 interface(CONST_INTER); 3602 %} 3603 3604 operand immL() %{ 3605 match(ConL); 3606 op_cost(40); 3607 // formats are generated automatically for constants and base registers 3608 format %{ %} 3609 interface(CONST_INTER); 3610 %} 3611 3612 operand immL0() %{ 3613 predicate(n->get_long() == 0L); 3614 match(ConL); 3615 op_cost(0); 3616 // formats are generated automatically for constants and base registers 3617 format %{ %} 3618 interface(CONST_INTER); 3619 %} 3620 3621 // Long Immediate: 13-bit 3622 operand immL13() %{ 3623 predicate((-4096L < n->get_long()) && (n->get_long() <= 4095L)); 3624 match(ConL); 3625 op_cost(0); 3626 3627 format %{ %} 3628 interface(CONST_INTER); 3629 %} 3630 3631 // Long Immediate: low 32-bit mask 3632 operand immL_32bits() %{ 3633 predicate(n->get_long() == 0xFFFFFFFFL); 3634 match(ConL); 3635 op_cost(0); 3636 3637 format %{ %} 3638 interface(CONST_INTER); 3639 %} 3640 3641 // Double Immediate 3642 operand immD() %{ 3643 match(ConD); 3644 3645 op_cost(40); 3646 format %{ %} 3647 interface(CONST_INTER); 3648 %} 3649 3650 operand immD0() %{ 3651 #ifdef _LP64 3652 // on 64-bit architectures this comparision is faster 3653 predicate(jlong_cast(n->getd()) == 0); 3654 #else 3655 predicate((n->getd() == 0) && (fpclass(n->getd()) == FP_PZERO)); 3656 #endif 3657 match(ConD); 3658 3659 op_cost(0); 3660 format %{ %} 3661 interface(CONST_INTER); 3662 %} 3663 3664 // Float Immediate 3665 operand immF() %{ 3666 match(ConF); 3667 3668 op_cost(20); 3669 format %{ %} 3670 interface(CONST_INTER); 3671 %} 3672 3673 // Float Immediate: 0 3674 operand immF0() %{ 3675 predicate((n->getf() == 0) && (fpclass(n->getf()) == FP_PZERO)); 3676 match(ConF); 3677 3678 op_cost(0); 3679 format %{ %} 3680 interface(CONST_INTER); 3681 %} 3682 3683 // Integer Register Operands 3684 // Integer Register 3685 operand iRegI() %{ 3686 constraint(ALLOC_IN_RC(int_reg)); 3687 match(RegI); 3688 3689 match(notemp_iRegI); 3690 match(g1RegI); 3691 match(o0RegI); 3692 match(iRegIsafe); 3693 3694 format %{ %} 3695 interface(REG_INTER); 3696 %} 3697 3698 operand notemp_iRegI() %{ 3699 constraint(ALLOC_IN_RC(notemp_int_reg)); 3700 match(RegI); 3701 3702 match(o0RegI); 3703 3704 format %{ %} 3705 interface(REG_INTER); 3706 %} 3707 3708 operand o0RegI() %{ 3709 constraint(ALLOC_IN_RC(o0_regI)); 3710 match(iRegI); 3711 3712 format %{ %} 3713 interface(REG_INTER); 3714 %} 3715 3716 // Pointer Register 3717 operand iRegP() %{ 3718 constraint(ALLOC_IN_RC(ptr_reg)); 3719 match(RegP); 3720 3721 match(lock_ptr_RegP); 3722 match(g1RegP); 3723 match(g2RegP); 3724 match(g3RegP); 3725 match(g4RegP); 3726 match(i0RegP); 3727 match(o0RegP); 3728 match(o1RegP); 3729 match(l7RegP); 3730 3731 format %{ %} 3732 interface(REG_INTER); 3733 %} 3734 3735 operand sp_ptr_RegP() %{ 3736 constraint(ALLOC_IN_RC(sp_ptr_reg)); 3737 match(RegP); 3738 match(iRegP); 3739 3740 format %{ %} 3741 interface(REG_INTER); 3742 %} 3743 3744 operand lock_ptr_RegP() %{ 3745 constraint(ALLOC_IN_RC(lock_ptr_reg)); 3746 match(RegP); 3747 match(i0RegP); 3748 match(o0RegP); 3749 match(o1RegP); 3750 match(l7RegP); 3751 3752 format %{ %} 3753 interface(REG_INTER); 3754 %} 3755 3756 operand g1RegP() %{ 3757 constraint(ALLOC_IN_RC(g1_regP)); 3758 match(iRegP); 3759 3760 format %{ %} 3761 interface(REG_INTER); 3762 %} 3763 3764 operand g2RegP() %{ 3765 constraint(ALLOC_IN_RC(g2_regP)); 3766 match(iRegP); 3767 3768 format %{ %} 3769 interface(REG_INTER); 3770 %} 3771 3772 operand g3RegP() %{ 3773 constraint(ALLOC_IN_RC(g3_regP)); 3774 match(iRegP); 3775 3776 format %{ %} 3777 interface(REG_INTER); 3778 %} 3779 3780 operand g1RegI() %{ 3781 constraint(ALLOC_IN_RC(g1_regI)); 3782 match(iRegI); 3783 3784 format %{ %} 3785 interface(REG_INTER); 3786 %} 3787 3788 operand g3RegI() %{ 3789 constraint(ALLOC_IN_RC(g3_regI)); 3790 match(iRegI); 3791 3792 format %{ %} 3793 interface(REG_INTER); 3794 %} 3795 3796 operand g4RegI() %{ 3797 constraint(ALLOC_IN_RC(g4_regI)); 3798 match(iRegI); 3799 3800 format %{ %} 3801 interface(REG_INTER); 3802 %} 3803 3804 operand g4RegP() %{ 3805 constraint(ALLOC_IN_RC(g4_regP)); 3806 match(iRegP); 3807 3808 format %{ %} 3809 interface(REG_INTER); 3810 %} 3811 3812 operand i0RegP() %{ 3813 constraint(ALLOC_IN_RC(i0_regP)); 3814 match(iRegP); 3815 3816 format %{ %} 3817 interface(REG_INTER); 3818 %} 3819 3820 operand o0RegP() %{ 3821 constraint(ALLOC_IN_RC(o0_regP)); 3822 match(iRegP); 3823 3824 format %{ %} 3825 interface(REG_INTER); 3826 %} 3827 3828 operand o1RegP() %{ 3829 constraint(ALLOC_IN_RC(o1_regP)); 3830 match(iRegP); 3831 3832 format %{ %} 3833 interface(REG_INTER); 3834 %} 3835 3836 operand o2RegP() %{ 3837 constraint(ALLOC_IN_RC(o2_regP)); 3838 match(iRegP); 3839 3840 format %{ %} 3841 interface(REG_INTER); 3842 %} 3843 3844 operand o7RegP() %{ 3845 constraint(ALLOC_IN_RC(o7_regP)); 3846 match(iRegP); 3847 3848 format %{ %} 3849 interface(REG_INTER); 3850 %} 3851 3852 operand l7RegP() %{ 3853 constraint(ALLOC_IN_RC(l7_regP)); 3854 match(iRegP); 3855 3856 format %{ %} 3857 interface(REG_INTER); 3858 %} 3859 3860 operand o7RegI() %{ 3861 constraint(ALLOC_IN_RC(o7_regI)); 3862 match(iRegI); 3863 3864 format %{ %} 3865 interface(REG_INTER); 3866 %} 3867 3868 operand iRegN() %{ 3869 constraint(ALLOC_IN_RC(int_reg)); 3870 match(RegN); 3871 3872 format %{ %} 3873 interface(REG_INTER); 3874 %} 3875 3876 // Long Register 3877 operand iRegL() %{ 3878 constraint(ALLOC_IN_RC(long_reg)); 3879 match(RegL); 3880 3881 format %{ %} 3882 interface(REG_INTER); 3883 %} 3884 3885 operand o2RegL() %{ 3886 constraint(ALLOC_IN_RC(o2_regL)); 3887 match(iRegL); 3888 3889 format %{ %} 3890 interface(REG_INTER); 3891 %} 3892 3893 operand o7RegL() %{ 3894 constraint(ALLOC_IN_RC(o7_regL)); 3895 match(iRegL); 3896 3897 format %{ %} 3898 interface(REG_INTER); 3899 %} 3900 3901 operand g1RegL() %{ 3902 constraint(ALLOC_IN_RC(g1_regL)); 3903 match(iRegL); 3904 3905 format %{ %} 3906 interface(REG_INTER); 3907 %} 3908 3909 operand g3RegL() %{ 3910 constraint(ALLOC_IN_RC(g3_regL)); 3911 match(iRegL); 3912 3913 format %{ %} 3914 interface(REG_INTER); 3915 %} 3916 3917 // Int Register safe 3918 // This is 64bit safe 3919 operand iRegIsafe() %{ 3920 constraint(ALLOC_IN_RC(long_reg)); 3921 3922 match(iRegI); 3923 3924 format %{ %} 3925 interface(REG_INTER); 3926 %} 3927 3928 // Condition Code Flag Register 3929 operand flagsReg() %{ 3930 constraint(ALLOC_IN_RC(int_flags)); 3931 match(RegFlags); 3932 3933 format %{ "ccr" %} // both ICC and XCC 3934 interface(REG_INTER); 3935 %} 3936 3937 // Condition Code Register, unsigned comparisons. 3938 operand flagsRegU() %{ 3939 constraint(ALLOC_IN_RC(int_flags)); 3940 match(RegFlags); 3941 3942 format %{ "icc_U" %} 3943 interface(REG_INTER); 3944 %} 3945 3946 // Condition Code Register, pointer comparisons. 3947 operand flagsRegP() %{ 3948 constraint(ALLOC_IN_RC(int_flags)); 3949 match(RegFlags); 3950 3951 #ifdef _LP64 3952 format %{ "xcc_P" %} 3953 #else 3954 format %{ "icc_P" %} 3955 #endif 3956 interface(REG_INTER); 3957 %} 3958 3959 // Condition Code Register, long comparisons. 3960 operand flagsRegL() %{ 3961 constraint(ALLOC_IN_RC(int_flags)); 3962 match(RegFlags); 3963 3964 format %{ "xcc_L" %} 3965 interface(REG_INTER); 3966 %} 3967 3968 // Condition Code Register, floating comparisons, unordered same as "less". 3969 operand flagsRegF() %{ 3970 constraint(ALLOC_IN_RC(float_flags)); 3971 match(RegFlags); 3972 match(flagsRegF0); 3973 3974 format %{ %} 3975 interface(REG_INTER); 3976 %} 3977 3978 operand flagsRegF0() %{ 3979 constraint(ALLOC_IN_RC(float_flag0)); 3980 match(RegFlags); 3981 3982 format %{ %} 3983 interface(REG_INTER); 3984 %} 3985 3986 3987 // Condition Code Flag Register used by long compare 3988 operand flagsReg_long_LTGE() %{ 3989 constraint(ALLOC_IN_RC(int_flags)); 3990 match(RegFlags); 3991 format %{ "icc_LTGE" %} 3992 interface(REG_INTER); 3993 %} 3994 operand flagsReg_long_EQNE() %{ 3995 constraint(ALLOC_IN_RC(int_flags)); 3996 match(RegFlags); 3997 format %{ "icc_EQNE" %} 3998 interface(REG_INTER); 3999 %} 4000 operand flagsReg_long_LEGT() %{ 4001 constraint(ALLOC_IN_RC(int_flags)); 4002 match(RegFlags); 4003 format %{ "icc_LEGT" %} 4004 interface(REG_INTER); 4005 %} 4006 4007 4008 operand regD() %{ 4009 constraint(ALLOC_IN_RC(dflt_reg)); 4010 match(RegD); 4011 4012 match(regD_low); 4013 4014 format %{ %} 4015 interface(REG_INTER); 4016 %} 4017 4018 operand regF() %{ 4019 constraint(ALLOC_IN_RC(sflt_reg)); 4020 match(RegF); 4021 4022 format %{ %} 4023 interface(REG_INTER); 4024 %} 4025 4026 operand regD_low() %{ 4027 constraint(ALLOC_IN_RC(dflt_low_reg)); 4028 match(regD); 4029 4030 format %{ %} 4031 interface(REG_INTER); 4032 %} 4033 4034 // Special Registers 4035 4036 // Method Register 4037 operand inline_cache_regP(iRegP reg) %{ 4038 constraint(ALLOC_IN_RC(g5_regP)); // G5=inline_cache_reg but uses 2 bits instead of 1 4039 match(reg); 4040 format %{ %} 4041 interface(REG_INTER); 4042 %} 4043 4044 operand interpreter_method_oop_regP(iRegP reg) %{ 4045 constraint(ALLOC_IN_RC(g5_regP)); // G5=interpreter_method_oop_reg but uses 2 bits instead of 1 4046 match(reg); 4047 format %{ %} 4048 interface(REG_INTER); 4049 %} 4050 4051 4052 //----------Complex Operands--------------------------------------------------- 4053 // Indirect Memory Reference 4054 operand indirect(sp_ptr_RegP reg) %{ 4055 constraint(ALLOC_IN_RC(sp_ptr_reg)); 4056 match(reg); 4057 4058 op_cost(100); 4059 format %{ "[$reg]" %} 4060 interface(MEMORY_INTER) %{ 4061 base($reg); 4062 index(0x0); 4063 scale(0x0); 4064 disp(0x0); 4065 %} 4066 %} 4067 4068 // Indirect with Offset 4069 operand indOffset13(sp_ptr_RegP reg, immX13 offset) %{ 4070 constraint(ALLOC_IN_RC(sp_ptr_reg)); 4071 match(AddP reg offset); 4072 4073 op_cost(100); 4074 format %{ "[$reg + $offset]" %} 4075 interface(MEMORY_INTER) %{ 4076 base($reg); 4077 index(0x0); 4078 scale(0x0); 4079 disp($offset); 4080 %} 4081 %} 4082 4083 // Note: Intel has a swapped version also, like this: 4084 //operand indOffsetX(iRegI reg, immP offset) %{ 4085 // constraint(ALLOC_IN_RC(int_reg)); 4086 // match(AddP offset reg); 4087 // 4088 // op_cost(100); 4089 // format %{ "[$reg + $offset]" %} 4090 // interface(MEMORY_INTER) %{ 4091 // base($reg); 4092 // index(0x0); 4093 // scale(0x0); 4094 // disp($offset); 4095 // %} 4096 //%} 4097 //// However, it doesn't make sense for SPARC, since 4098 // we have no particularly good way to embed oops in 4099 // single instructions. 4100 4101 // Indirect with Register Index 4102 operand indIndex(iRegP addr, iRegX index) %{ 4103 constraint(ALLOC_IN_RC(ptr_reg)); 4104 match(AddP addr index); 4105 4106 op_cost(100); 4107 format %{ "[$addr + $index]" %} 4108 interface(MEMORY_INTER) %{ 4109 base($addr); 4110 index($index); 4111 scale(0x0); 4112 disp(0x0); 4113 %} 4114 %} 4115 4116 //----------Special Memory Operands-------------------------------------------- 4117 // Stack Slot Operand - This operand is used for loading and storing temporary 4118 // values on the stack where a match requires a value to 4119 // flow through memory. 4120 operand stackSlotI(sRegI reg) %{ 4121 constraint(ALLOC_IN_RC(stack_slots)); 4122 op_cost(100); 4123 //match(RegI); 4124 format %{ "[$reg]" %} 4125 interface(MEMORY_INTER) %{ 4126 base(0xE); // R_SP 4127 index(0x0); 4128 scale(0x0); 4129 disp($reg); // Stack Offset 4130 %} 4131 %} 4132 4133 operand stackSlotP(sRegP reg) %{ 4134 constraint(ALLOC_IN_RC(stack_slots)); 4135 op_cost(100); 4136 //match(RegP); 4137 format %{ "[$reg]" %} 4138 interface(MEMORY_INTER) %{ 4139 base(0xE); // R_SP 4140 index(0x0); 4141 scale(0x0); 4142 disp($reg); // Stack Offset 4143 %} 4144 %} 4145 4146 operand stackSlotF(sRegF reg) %{ 4147 constraint(ALLOC_IN_RC(stack_slots)); 4148 op_cost(100); 4149 //match(RegF); 4150 format %{ "[$reg]" %} 4151 interface(MEMORY_INTER) %{ 4152 base(0xE); // R_SP 4153 index(0x0); 4154 scale(0x0); 4155 disp($reg); // Stack Offset 4156 %} 4157 %} 4158 operand stackSlotD(sRegD reg) %{ 4159 constraint(ALLOC_IN_RC(stack_slots)); 4160 op_cost(100); 4161 //match(RegD); 4162 format %{ "[$reg]" %} 4163 interface(MEMORY_INTER) %{ 4164 base(0xE); // R_SP 4165 index(0x0); 4166 scale(0x0); 4167 disp($reg); // Stack Offset 4168 %} 4169 %} 4170 operand stackSlotL(sRegL reg) %{ 4171 constraint(ALLOC_IN_RC(stack_slots)); 4172 op_cost(100); 4173 //match(RegL); 4174 format %{ "[$reg]" %} 4175 interface(MEMORY_INTER) %{ 4176 base(0xE); // R_SP 4177 index(0x0); 4178 scale(0x0); 4179 disp($reg); // Stack Offset 4180 %} 4181 %} 4182 4183 // Operands for expressing Control Flow 4184 // NOTE: Label is a predefined operand which should not be redefined in 4185 // the AD file. It is generically handled within the ADLC. 4186 4187 //----------Conditional Branch Operands---------------------------------------- 4188 // Comparison Op - This is the operation of the comparison, and is limited to 4189 // the following set of codes: 4190 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=) 4191 // 4192 // Other attributes of the comparison, such as unsignedness, are specified 4193 // by the comparison instruction that sets a condition code flags register. 4194 // That result is represented by a flags operand whose subtype is appropriate 4195 // to the unsignedness (etc.) of the comparison. 4196 // 4197 // Later, the instruction which matches both the Comparison Op (a Bool) and 4198 // the flags (produced by the Cmp) specifies the coding of the comparison op 4199 // by matching a specific subtype of Bool operand below, such as cmpOpU. 4200 4201 operand cmpOp() %{ 4202 match(Bool); 4203 4204 format %{ "" %} 4205 interface(COND_INTER) %{ 4206 equal(0x1); 4207 not_equal(0x9); 4208 less(0x3); 4209 greater_equal(0xB); 4210 less_equal(0x2); 4211 greater(0xA); 4212 %} 4213 %} 4214 4215 // Comparison Op, unsigned 4216 operand cmpOpU() %{ 4217 match(Bool); 4218 4219 format %{ "u" %} 4220 interface(COND_INTER) %{ 4221 equal(0x1); 4222 not_equal(0x9); 4223 less(0x5); 4224 greater_equal(0xD); 4225 less_equal(0x4); 4226 greater(0xC); 4227 %} 4228 %} 4229 4230 // Comparison Op, pointer (same as unsigned) 4231 operand cmpOpP() %{ 4232 match(Bool); 4233 4234 format %{ "p" %} 4235 interface(COND_INTER) %{ 4236 equal(0x1); 4237 not_equal(0x9); 4238 less(0x5); 4239 greater_equal(0xD); 4240 less_equal(0x4); 4241 greater(0xC); 4242 %} 4243 %} 4244 4245 // Comparison Op, branch-register encoding 4246 operand cmpOp_reg() %{ 4247 match(Bool); 4248 4249 format %{ "" %} 4250 interface(COND_INTER) %{ 4251 equal (0x1); 4252 not_equal (0x5); 4253 less (0x3); 4254 greater_equal(0x7); 4255 less_equal (0x2); 4256 greater (0x6); 4257 %} 4258 %} 4259 4260 // Comparison Code, floating, unordered same as less 4261 operand cmpOpF() %{ 4262 match(Bool); 4263 4264 format %{ "fl" %} 4265 interface(COND_INTER) %{ 4266 equal(0x9); 4267 not_equal(0x1); 4268 less(0x3); 4269 greater_equal(0xB); 4270 less_equal(0xE); 4271 greater(0x6); 4272 %} 4273 %} 4274 4275 // Used by long compare 4276 operand cmpOp_commute() %{ 4277 match(Bool); 4278 4279 format %{ "" %} 4280 interface(COND_INTER) %{ 4281 equal(0x1); 4282 not_equal(0x9); 4283 less(0xA); 4284 greater_equal(0x2); 4285 less_equal(0xB); 4286 greater(0x3); 4287 %} 4288 %} 4289 4290 //----------OPERAND CLASSES---------------------------------------------------- 4291 // Operand Classes are groups of operands that are used to simplify 4292 // instruction definitions by not requiring the AD writer to specify separate 4293 // instructions for every form of operand when the instruction accepts 4294 // multiple operand types with the same basic encoding and format. The classic 4295 // case of this is memory operands. 4296 // Indirect is not included since its use is limited to Compare & Swap 4297 opclass memory( indirect, indOffset13, indIndex ); 4298 4299 //----------PIPELINE----------------------------------------------------------- 4300 pipeline %{ 4301 4302 //----------ATTRIBUTES--------------------------------------------------------- 4303 attributes %{ 4304 fixed_size_instructions; // Fixed size instructions 4305 branch_has_delay_slot; // Branch has delay slot following 4306 max_instructions_per_bundle = 4; // Up to 4 instructions per bundle 4307 instruction_unit_size = 4; // An instruction is 4 bytes long 4308 instruction_fetch_unit_size = 16; // The processor fetches one line 4309 instruction_fetch_units = 1; // of 16 bytes 4310 4311 // List of nop instructions 4312 nops( Nop_A0, Nop_A1, Nop_MS, Nop_FA, Nop_BR ); 4313 %} 4314 4315 //----------RESOURCES---------------------------------------------------------- 4316 // Resources are the functional units available to the machine 4317 resources(A0, A1, MS, BR, FA, FM, IDIV, FDIV, IALU = A0 | A1); 4318 4319 //----------PIPELINE DESCRIPTION----------------------------------------------- 4320 // Pipeline Description specifies the stages in the machine's pipeline 4321 4322 pipe_desc(A, P, F, B, I, J, S, R, E, C, M, W, X, T, D); 4323 4324 //----------PIPELINE CLASSES--------------------------------------------------- 4325 // Pipeline Classes describe the stages in which input and output are 4326 // referenced by the hardware pipeline. 4327 4328 // Integer ALU reg-reg operation 4329 pipe_class ialu_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 4330 single_instruction; 4331 dst : E(write); 4332 src1 : R(read); 4333 src2 : R(read); 4334 IALU : R; 4335 %} 4336 4337 // Integer ALU reg-reg long operation 4338 pipe_class ialu_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{ 4339 instruction_count(2); 4340 dst : E(write); 4341 src1 : R(read); 4342 src2 : R(read); 4343 IALU : R; 4344 IALU : R; 4345 %} 4346 4347 // Integer ALU reg-reg long dependent operation 4348 pipe_class ialu_reg_reg_2_dep(iRegL dst, iRegL src1, iRegL src2, flagsReg cr) %{ 4349 instruction_count(1); multiple_bundles; 4350 dst : E(write); 4351 src1 : R(read); 4352 src2 : R(read); 4353 cr : E(write); 4354 IALU : R(2); 4355 %} 4356 4357 // Integer ALU reg-imm operaion 4358 pipe_class ialu_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{ 4359 single_instruction; 4360 dst : E(write); 4361 src1 : R(read); 4362 IALU : R; 4363 %} 4364 4365 // Integer ALU reg-reg operation with condition code 4366 pipe_class ialu_cc_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{ 4367 single_instruction; 4368 dst : E(write); 4369 cr : E(write); 4370 src1 : R(read); 4371 src2 : R(read); 4372 IALU : R; 4373 %} 4374 4375 // Integer ALU reg-imm operation with condition code 4376 pipe_class ialu_cc_reg_imm(iRegI dst, iRegI src1, immI13 src2, flagsReg cr) %{ 4377 single_instruction; 4378 dst : E(write); 4379 cr : E(write); 4380 src1 : R(read); 4381 IALU : R; 4382 %} 4383 4384 // Integer ALU zero-reg operation 4385 pipe_class ialu_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{ 4386 single_instruction; 4387 dst : E(write); 4388 src2 : R(read); 4389 IALU : R; 4390 %} 4391 4392 // Integer ALU zero-reg operation with condition code only 4393 pipe_class ialu_cconly_zero_reg(flagsReg cr, iRegI src) %{ 4394 single_instruction; 4395 cr : E(write); 4396 src : R(read); 4397 IALU : R; 4398 %} 4399 4400 // Integer ALU reg-reg operation with condition code only 4401 pipe_class ialu_cconly_reg_reg(flagsReg cr, iRegI src1, iRegI src2) %{ 4402 single_instruction; 4403 cr : E(write); 4404 src1 : R(read); 4405 src2 : R(read); 4406 IALU : R; 4407 %} 4408 4409 // Integer ALU reg-imm operation with condition code only 4410 pipe_class ialu_cconly_reg_imm(flagsReg cr, iRegI src1, immI13 src2) %{ 4411 single_instruction; 4412 cr : E(write); 4413 src1 : R(read); 4414 IALU : R; 4415 %} 4416 4417 // Integer ALU reg-reg-zero operation with condition code only 4418 pipe_class ialu_cconly_reg_reg_zero(flagsReg cr, iRegI src1, iRegI src2, immI0 zero) %{ 4419 single_instruction; 4420 cr : E(write); 4421 src1 : R(read); 4422 src2 : R(read); 4423 IALU : R; 4424 %} 4425 4426 // Integer ALU reg-imm-zero operation with condition code only 4427 pipe_class ialu_cconly_reg_imm_zero(flagsReg cr, iRegI src1, immI13 src2, immI0 zero) %{ 4428 single_instruction; 4429 cr : E(write); 4430 src1 : R(read); 4431 IALU : R; 4432 %} 4433 4434 // Integer ALU reg-reg operation with condition code, src1 modified 4435 pipe_class ialu_cc_rwreg_reg(flagsReg cr, iRegI src1, iRegI src2) %{ 4436 single_instruction; 4437 cr : E(write); 4438 src1 : E(write); 4439 src1 : R(read); 4440 src2 : R(read); 4441 IALU : R; 4442 %} 4443 4444 // Integer ALU reg-imm operation with condition code, src1 modified 4445 pipe_class ialu_cc_rwreg_imm(flagsReg cr, iRegI src1, immI13 src2) %{ 4446 single_instruction; 4447 cr : E(write); 4448 src1 : E(write); 4449 src1 : R(read); 4450 IALU : R; 4451 %} 4452 4453 pipe_class cmpL_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg cr ) %{ 4454 multiple_bundles; 4455 dst : E(write)+4; 4456 cr : E(write); 4457 src1 : R(read); 4458 src2 : R(read); 4459 IALU : R(3); 4460 BR : R(2); 4461 %} 4462 4463 // Integer ALU operation 4464 pipe_class ialu_none(iRegI dst) %{ 4465 single_instruction; 4466 dst : E(write); 4467 IALU : R; 4468 %} 4469 4470 // Integer ALU reg operation 4471 pipe_class ialu_reg(iRegI dst, iRegI src) %{ 4472 single_instruction; may_have_no_code; 4473 dst : E(write); 4474 src : R(read); 4475 IALU : R; 4476 %} 4477 4478 // Integer ALU reg conditional operation 4479 // This instruction has a 1 cycle stall, and cannot execute 4480 // in the same cycle as the instruction setting the condition 4481 // code. We kludge this by pretending to read the condition code 4482 // 1 cycle earlier, and by marking the functional units as busy 4483 // for 2 cycles with the result available 1 cycle later than 4484 // is really the case. 4485 pipe_class ialu_reg_flags( iRegI op2_out, iRegI op2_in, iRegI op1, flagsReg cr ) %{ 4486 single_instruction; 4487 op2_out : C(write); 4488 op1 : R(read); 4489 cr : R(read); // This is really E, with a 1 cycle stall 4490 BR : R(2); 4491 MS : R(2); 4492 %} 4493 4494 #ifdef _LP64 4495 pipe_class ialu_clr_and_mover( iRegI dst, iRegP src ) %{ 4496 instruction_count(1); multiple_bundles; 4497 dst : C(write)+1; 4498 src : R(read)+1; 4499 IALU : R(1); 4500 BR : E(2); 4501 MS : E(2); 4502 %} 4503 #endif 4504 4505 // Integer ALU reg operation 4506 pipe_class ialu_move_reg_L_to_I(iRegI dst, iRegL src) %{ 4507 single_instruction; may_have_no_code; 4508 dst : E(write); 4509 src : R(read); 4510 IALU : R; 4511 %} 4512 pipe_class ialu_move_reg_I_to_L(iRegL dst, iRegI src) %{ 4513 single_instruction; may_have_no_code; 4514 dst : E(write); 4515 src : R(read); 4516 IALU : R; 4517 %} 4518 4519 // Two integer ALU reg operations 4520 pipe_class ialu_reg_2(iRegL dst, iRegL src) %{ 4521 instruction_count(2); 4522 dst : E(write); 4523 src : R(read); 4524 A0 : R; 4525 A1 : R; 4526 %} 4527 4528 // Two integer ALU reg operations 4529 pipe_class ialu_move_reg_L_to_L(iRegL dst, iRegL src) %{ 4530 instruction_count(2); may_have_no_code; 4531 dst : E(write); 4532 src : R(read); 4533 A0 : R; 4534 A1 : R; 4535 %} 4536 4537 // Integer ALU imm operation 4538 pipe_class ialu_imm(iRegI dst, immI13 src) %{ 4539 single_instruction; 4540 dst : E(write); 4541 IALU : R; 4542 %} 4543 4544 // Integer ALU reg-reg with carry operation 4545 pipe_class ialu_reg_reg_cy(iRegI dst, iRegI src1, iRegI src2, iRegI cy) %{ 4546 single_instruction; 4547 dst : E(write); 4548 src1 : R(read); 4549 src2 : R(read); 4550 IALU : R; 4551 %} 4552 4553 // Integer ALU cc operation 4554 pipe_class ialu_cc(iRegI dst, flagsReg cc) %{ 4555 single_instruction; 4556 dst : E(write); 4557 cc : R(read); 4558 IALU : R; 4559 %} 4560 4561 // Integer ALU cc / second IALU operation 4562 pipe_class ialu_reg_ialu( iRegI dst, iRegI src ) %{ 4563 instruction_count(1); multiple_bundles; 4564 dst : E(write)+1; 4565 src : R(read); 4566 IALU : R; 4567 %} 4568 4569 // Integer ALU cc / second IALU operation 4570 pipe_class ialu_reg_reg_ialu( iRegI dst, iRegI p, iRegI q ) %{ 4571 instruction_count(1); multiple_bundles; 4572 dst : E(write)+1; 4573 p : R(read); 4574 q : R(read); 4575 IALU : R; 4576 %} 4577 4578 // Integer ALU hi-lo-reg operation 4579 pipe_class ialu_hi_lo_reg(iRegI dst, immI src) %{ 4580 instruction_count(1); multiple_bundles; 4581 dst : E(write)+1; 4582 IALU : R(2); 4583 %} 4584 4585 // Float ALU hi-lo-reg operation (with temp) 4586 pipe_class ialu_hi_lo_reg_temp(regF dst, immF src, g3RegP tmp) %{ 4587 instruction_count(1); multiple_bundles; 4588 dst : E(write)+1; 4589 IALU : R(2); 4590 %} 4591 4592 // Long Constant 4593 pipe_class loadConL( iRegL dst, immL src ) %{ 4594 instruction_count(2); multiple_bundles; 4595 dst : E(write)+1; 4596 IALU : R(2); 4597 IALU : R(2); 4598 %} 4599 4600 // Pointer Constant 4601 pipe_class loadConP( iRegP dst, immP src ) %{ 4602 instruction_count(0); multiple_bundles; 4603 fixed_latency(6); 4604 %} 4605 4606 // Polling Address 4607 pipe_class loadConP_poll( iRegP dst, immP_poll src ) %{ 4608 #ifdef _LP64 4609 instruction_count(0); multiple_bundles; 4610 fixed_latency(6); 4611 #else 4612 dst : E(write); 4613 IALU : R; 4614 #endif 4615 %} 4616 4617 // Long Constant small 4618 pipe_class loadConLlo( iRegL dst, immL src ) %{ 4619 instruction_count(2); 4620 dst : E(write); 4621 IALU : R; 4622 IALU : R; 4623 %} 4624 4625 // [PHH] This is wrong for 64-bit. See LdImmF/D. 4626 pipe_class loadConFD(regF dst, immF src, g3RegP tmp) %{ 4627 instruction_count(1); multiple_bundles; 4628 src : R(read); 4629 dst : M(write)+1; 4630 IALU : R; 4631 MS : E; 4632 %} 4633 4634 // Integer ALU nop operation 4635 pipe_class ialu_nop() %{ 4636 single_instruction; 4637 IALU : R; 4638 %} 4639 4640 // Integer ALU nop operation 4641 pipe_class ialu_nop_A0() %{ 4642 single_instruction; 4643 A0 : R; 4644 %} 4645 4646 // Integer ALU nop operation 4647 pipe_class ialu_nop_A1() %{ 4648 single_instruction; 4649 A1 : R; 4650 %} 4651 4652 // Integer Multiply reg-reg operation 4653 pipe_class imul_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 4654 single_instruction; 4655 dst : E(write); 4656 src1 : R(read); 4657 src2 : R(read); 4658 MS : R(5); 4659 %} 4660 4661 // Integer Multiply reg-imm operation 4662 pipe_class imul_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{ 4663 single_instruction; 4664 dst : E(write); 4665 src1 : R(read); 4666 MS : R(5); 4667 %} 4668 4669 pipe_class mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 4670 single_instruction; 4671 dst : E(write)+4; 4672 src1 : R(read); 4673 src2 : R(read); 4674 MS : R(6); 4675 %} 4676 4677 pipe_class mulL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{ 4678 single_instruction; 4679 dst : E(write)+4; 4680 src1 : R(read); 4681 MS : R(6); 4682 %} 4683 4684 // Integer Divide reg-reg 4685 pipe_class sdiv_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI temp, flagsReg cr) %{ 4686 instruction_count(1); multiple_bundles; 4687 dst : E(write); 4688 temp : E(write); 4689 src1 : R(read); 4690 src2 : R(read); 4691 temp : R(read); 4692 MS : R(38); 4693 %} 4694 4695 // Integer Divide reg-imm 4696 pipe_class sdiv_reg_imm(iRegI dst, iRegI src1, immI13 src2, iRegI temp, flagsReg cr) %{ 4697 instruction_count(1); multiple_bundles; 4698 dst : E(write); 4699 temp : E(write); 4700 src1 : R(read); 4701 temp : R(read); 4702 MS : R(38); 4703 %} 4704 4705 // Long Divide 4706 pipe_class divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 4707 dst : E(write)+71; 4708 src1 : R(read); 4709 src2 : R(read)+1; 4710 MS : R(70); 4711 %} 4712 4713 pipe_class divL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{ 4714 dst : E(write)+71; 4715 src1 : R(read); 4716 MS : R(70); 4717 %} 4718 4719 // Floating Point Add Float 4720 pipe_class faddF_reg_reg(regF dst, regF src1, regF src2) %{ 4721 single_instruction; 4722 dst : X(write); 4723 src1 : E(read); 4724 src2 : E(read); 4725 FA : R; 4726 %} 4727 4728 // Floating Point Add Double 4729 pipe_class faddD_reg_reg(regD dst, regD src1, regD src2) %{ 4730 single_instruction; 4731 dst : X(write); 4732 src1 : E(read); 4733 src2 : E(read); 4734 FA : R; 4735 %} 4736 4737 // Floating Point Conditional Move based on integer flags 4738 pipe_class int_conditional_float_move (cmpOp cmp, flagsReg cr, regF dst, regF src) %{ 4739 single_instruction; 4740 dst : X(write); 4741 src : E(read); 4742 cr : R(read); 4743 FA : R(2); 4744 BR : R(2); 4745 %} 4746 4747 // Floating Point Conditional Move based on integer flags 4748 pipe_class int_conditional_double_move (cmpOp cmp, flagsReg cr, regD dst, regD src) %{ 4749 single_instruction; 4750 dst : X(write); 4751 src : E(read); 4752 cr : R(read); 4753 FA : R(2); 4754 BR : R(2); 4755 %} 4756 4757 // Floating Point Multiply Float 4758 pipe_class fmulF_reg_reg(regF dst, regF src1, regF src2) %{ 4759 single_instruction; 4760 dst : X(write); 4761 src1 : E(read); 4762 src2 : E(read); 4763 FM : R; 4764 %} 4765 4766 // Floating Point Multiply Double 4767 pipe_class fmulD_reg_reg(regD dst, regD src1, regD src2) %{ 4768 single_instruction; 4769 dst : X(write); 4770 src1 : E(read); 4771 src2 : E(read); 4772 FM : R; 4773 %} 4774 4775 // Floating Point Divide Float 4776 pipe_class fdivF_reg_reg(regF dst, regF src1, regF src2) %{ 4777 single_instruction; 4778 dst : X(write); 4779 src1 : E(read); 4780 src2 : E(read); 4781 FM : R; 4782 FDIV : C(14); 4783 %} 4784 4785 // Floating Point Divide Double 4786 pipe_class fdivD_reg_reg(regD dst, regD src1, regD src2) %{ 4787 single_instruction; 4788 dst : X(write); 4789 src1 : E(read); 4790 src2 : E(read); 4791 FM : R; 4792 FDIV : C(17); 4793 %} 4794 4795 // Floating Point Move/Negate/Abs Float 4796 pipe_class faddF_reg(regF dst, regF src) %{ 4797 single_instruction; 4798 dst : W(write); 4799 src : E(read); 4800 FA : R(1); 4801 %} 4802 4803 // Floating Point Move/Negate/Abs Double 4804 pipe_class faddD_reg(regD dst, regD src) %{ 4805 single_instruction; 4806 dst : W(write); 4807 src : E(read); 4808 FA : R; 4809 %} 4810 4811 // Floating Point Convert F->D 4812 pipe_class fcvtF2D(regD dst, regF src) %{ 4813 single_instruction; 4814 dst : X(write); 4815 src : E(read); 4816 FA : R; 4817 %} 4818 4819 // Floating Point Convert I->D 4820 pipe_class fcvtI2D(regD dst, regF src) %{ 4821 single_instruction; 4822 dst : X(write); 4823 src : E(read); 4824 FA : R; 4825 %} 4826 4827 // Floating Point Convert LHi->D 4828 pipe_class fcvtLHi2D(regD dst, regD src) %{ 4829 single_instruction; 4830 dst : X(write); 4831 src : E(read); 4832 FA : R; 4833 %} 4834 4835 // Floating Point Convert L->D 4836 pipe_class fcvtL2D(regD dst, regF src) %{ 4837 single_instruction; 4838 dst : X(write); 4839 src : E(read); 4840 FA : R; 4841 %} 4842 4843 // Floating Point Convert L->F 4844 pipe_class fcvtL2F(regD dst, regF src) %{ 4845 single_instruction; 4846 dst : X(write); 4847 src : E(read); 4848 FA : R; 4849 %} 4850 4851 // Floating Point Convert D->F 4852 pipe_class fcvtD2F(regD dst, regF src) %{ 4853 single_instruction; 4854 dst : X(write); 4855 src : E(read); 4856 FA : R; 4857 %} 4858 4859 // Floating Point Convert I->L 4860 pipe_class fcvtI2L(regD dst, regF src) %{ 4861 single_instruction; 4862 dst : X(write); 4863 src : E(read); 4864 FA : R; 4865 %} 4866 4867 // Floating Point Convert D->F 4868 pipe_class fcvtD2I(regF dst, regD src, flagsReg cr) %{ 4869 instruction_count(1); multiple_bundles; 4870 dst : X(write)+6; 4871 src : E(read); 4872 FA : R; 4873 %} 4874 4875 // Floating Point Convert D->L 4876 pipe_class fcvtD2L(regD dst, regD src, flagsReg cr) %{ 4877 instruction_count(1); multiple_bundles; 4878 dst : X(write)+6; 4879 src : E(read); 4880 FA : R; 4881 %} 4882 4883 // Floating Point Convert F->I 4884 pipe_class fcvtF2I(regF dst, regF src, flagsReg cr) %{ 4885 instruction_count(1); multiple_bundles; 4886 dst : X(write)+6; 4887 src : E(read); 4888 FA : R; 4889 %} 4890 4891 // Floating Point Convert F->L 4892 pipe_class fcvtF2L(regD dst, regF src, flagsReg cr) %{ 4893 instruction_count(1); multiple_bundles; 4894 dst : X(write)+6; 4895 src : E(read); 4896 FA : R; 4897 %} 4898 4899 // Floating Point Convert I->F 4900 pipe_class fcvtI2F(regF dst, regF src) %{ 4901 single_instruction; 4902 dst : X(write); 4903 src : E(read); 4904 FA : R; 4905 %} 4906 4907 // Floating Point Compare 4908 pipe_class faddF_fcc_reg_reg_zero(flagsRegF cr, regF src1, regF src2, immI0 zero) %{ 4909 single_instruction; 4910 cr : X(write); 4911 src1 : E(read); 4912 src2 : E(read); 4913 FA : R; 4914 %} 4915 4916 // Floating Point Compare 4917 pipe_class faddD_fcc_reg_reg_zero(flagsRegF cr, regD src1, regD src2, immI0 zero) %{ 4918 single_instruction; 4919 cr : X(write); 4920 src1 : E(read); 4921 src2 : E(read); 4922 FA : R; 4923 %} 4924 4925 // Floating Add Nop 4926 pipe_class fadd_nop() %{ 4927 single_instruction; 4928 FA : R; 4929 %} 4930 4931 // Integer Store to Memory 4932 pipe_class istore_mem_reg(memory mem, iRegI src) %{ 4933 single_instruction; 4934 mem : R(read); 4935 src : C(read); 4936 MS : R; 4937 %} 4938 4939 // Integer Store to Memory 4940 pipe_class istore_mem_spORreg(memory mem, sp_ptr_RegP src) %{ 4941 single_instruction; 4942 mem : R(read); 4943 src : C(read); 4944 MS : R; 4945 %} 4946 4947 // Integer Store Zero to Memory 4948 pipe_class istore_mem_zero(memory mem, immI0 src) %{ 4949 single_instruction; 4950 mem : R(read); 4951 MS : R; 4952 %} 4953 4954 // Special Stack Slot Store 4955 pipe_class istore_stk_reg(stackSlotI stkSlot, iRegI src) %{ 4956 single_instruction; 4957 stkSlot : R(read); 4958 src : C(read); 4959 MS : R; 4960 %} 4961 4962 // Special Stack Slot Store 4963 pipe_class lstoreI_stk_reg(stackSlotL stkSlot, iRegI src) %{ 4964 instruction_count(2); multiple_bundles; 4965 stkSlot : R(read); 4966 src : C(read); 4967 MS : R(2); 4968 %} 4969 4970 // Float Store 4971 pipe_class fstoreF_mem_reg(memory mem, RegF src) %{ 4972 single_instruction; 4973 mem : R(read); 4974 src : C(read); 4975 MS : R; 4976 %} 4977 4978 // Float Store 4979 pipe_class fstoreF_mem_zero(memory mem, immF0 src) %{ 4980 single_instruction; 4981 mem : R(read); 4982 MS : R; 4983 %} 4984 4985 // Double Store 4986 pipe_class fstoreD_mem_reg(memory mem, RegD src) %{ 4987 instruction_count(1); 4988 mem : R(read); 4989 src : C(read); 4990 MS : R; 4991 %} 4992 4993 // Double Store 4994 pipe_class fstoreD_mem_zero(memory mem, immD0 src) %{ 4995 single_instruction; 4996 mem : R(read); 4997 MS : R; 4998 %} 4999 5000 // Special Stack Slot Float Store 5001 pipe_class fstoreF_stk_reg(stackSlotI stkSlot, RegF src) %{ 5002 single_instruction; 5003 stkSlot : R(read); 5004 src : C(read); 5005 MS : R; 5006 %} 5007 5008 // Special Stack Slot Double Store 5009 pipe_class fstoreD_stk_reg(stackSlotI stkSlot, RegD src) %{ 5010 single_instruction; 5011 stkSlot : R(read); 5012 src : C(read); 5013 MS : R; 5014 %} 5015 5016 // Integer Load (when sign bit propagation not needed) 5017 pipe_class iload_mem(iRegI dst, memory mem) %{ 5018 single_instruction; 5019 mem : R(read); 5020 dst : C(write); 5021 MS : R; 5022 %} 5023 5024 // Integer Load from stack operand 5025 pipe_class iload_stkD(iRegI dst, stackSlotD mem ) %{ 5026 single_instruction; 5027 mem : R(read); 5028 dst : C(write); 5029 MS : R; 5030 %} 5031 5032 // Integer Load (when sign bit propagation or masking is needed) 5033 pipe_class iload_mask_mem(iRegI dst, memory mem) %{ 5034 single_instruction; 5035 mem : R(read); 5036 dst : M(write); 5037 MS : R; 5038 %} 5039 5040 // Float Load 5041 pipe_class floadF_mem(regF dst, memory mem) %{ 5042 single_instruction; 5043 mem : R(read); 5044 dst : M(write); 5045 MS : R; 5046 %} 5047 5048 // Float Load 5049 pipe_class floadD_mem(regD dst, memory mem) %{ 5050 instruction_count(1); multiple_bundles; // Again, unaligned argument is only multiple case 5051 mem : R(read); 5052 dst : M(write); 5053 MS : R; 5054 %} 5055 5056 // Float Load 5057 pipe_class floadF_stk(regF dst, stackSlotI stkSlot) %{ 5058 single_instruction; 5059 stkSlot : R(read); 5060 dst : M(write); 5061 MS : R; 5062 %} 5063 5064 // Float Load 5065 pipe_class floadD_stk(regD dst, stackSlotI stkSlot) %{ 5066 single_instruction; 5067 stkSlot : R(read); 5068 dst : M(write); 5069 MS : R; 5070 %} 5071 5072 // Memory Nop 5073 pipe_class mem_nop() %{ 5074 single_instruction; 5075 MS : R; 5076 %} 5077 5078 pipe_class sethi(iRegP dst, immI src) %{ 5079 single_instruction; 5080 dst : E(write); 5081 IALU : R; 5082 %} 5083 5084 pipe_class loadPollP(iRegP poll) %{ 5085 single_instruction; 5086 poll : R(read); 5087 MS : R; 5088 %} 5089 5090 pipe_class br(Universe br, label labl) %{ 5091 single_instruction_with_delay_slot; 5092 BR : R; 5093 %} 5094 5095 pipe_class br_cc(Universe br, cmpOp cmp, flagsReg cr, label labl) %{ 5096 single_instruction_with_delay_slot; 5097 cr : E(read); 5098 BR : R; 5099 %} 5100 5101 pipe_class br_reg(Universe br, cmpOp cmp, iRegI op1, label labl) %{ 5102 single_instruction_with_delay_slot; 5103 op1 : E(read); 5104 BR : R; 5105 MS : R; 5106 %} 5107 5108 pipe_class br_fcc(Universe br, cmpOpF cc, flagsReg cr, label labl) %{ 5109 single_instruction_with_delay_slot; 5110 cr : E(read); 5111 BR : R; 5112 %} 5113 5114 pipe_class br_nop() %{ 5115 single_instruction; 5116 BR : R; 5117 %} 5118 5119 pipe_class simple_call(method meth) %{ 5120 instruction_count(2); multiple_bundles; force_serialization; 5121 fixed_latency(100); 5122 BR : R(1); 5123 MS : R(1); 5124 A0 : R(1); 5125 %} 5126 5127 pipe_class compiled_call(method meth) %{ 5128 instruction_count(1); multiple_bundles; force_serialization; 5129 fixed_latency(100); 5130 MS : R(1); 5131 %} 5132 5133 pipe_class call(method meth) %{ 5134 instruction_count(0); multiple_bundles; force_serialization; 5135 fixed_latency(100); 5136 %} 5137 5138 pipe_class tail_call(Universe ignore, label labl) %{ 5139 single_instruction; has_delay_slot; 5140 fixed_latency(100); 5141 BR : R(1); 5142 MS : R(1); 5143 %} 5144 5145 pipe_class ret(Universe ignore) %{ 5146 single_instruction; has_delay_slot; 5147 BR : R(1); 5148 MS : R(1); 5149 %} 5150 5151 pipe_class ret_poll(g3RegP poll) %{ 5152 instruction_count(3); has_delay_slot; 5153 poll : E(read); 5154 MS : R; 5155 %} 5156 5157 // The real do-nothing guy 5158 pipe_class empty( ) %{ 5159 instruction_count(0); 5160 %} 5161 5162 pipe_class long_memory_op() %{ 5163 instruction_count(0); multiple_bundles; force_serialization; 5164 fixed_latency(25); 5165 MS : R(1); 5166 %} 5167 5168 // Check-cast 5169 pipe_class partial_subtype_check_pipe(Universe ignore, iRegP array, iRegP match ) %{ 5170 array : R(read); 5171 match : R(read); 5172 IALU : R(2); 5173 BR : R(2); 5174 MS : R; 5175 %} 5176 5177 // Convert FPU flags into +1,0,-1 5178 pipe_class floating_cmp( iRegI dst, regF src1, regF src2 ) %{ 5179 src1 : E(read); 5180 src2 : E(read); 5181 dst : E(write); 5182 FA : R; 5183 MS : R(2); 5184 BR : R(2); 5185 %} 5186 5187 // Compare for p < q, and conditionally add y 5188 pipe_class cadd_cmpltmask( iRegI p, iRegI q, iRegI y ) %{ 5189 p : E(read); 5190 q : E(read); 5191 y : E(read); 5192 IALU : R(3) 5193 %} 5194 5195 // Perform a compare, then move conditionally in a branch delay slot. 5196 pipe_class min_max( iRegI src2, iRegI srcdst ) %{ 5197 src2 : E(read); 5198 srcdst : E(read); 5199 IALU : R; 5200 BR : R; 5201 %} 5202 5203 // Define the class for the Nop node 5204 define %{ 5205 MachNop = ialu_nop; 5206 %} 5207 5208 %} 5209 5210 //----------INSTRUCTIONS------------------------------------------------------- 5211 5212 //------------Special Stack Slot instructions - no match rules----------------- 5213 instruct stkI_to_regF(regF dst, stackSlotI src) %{ 5214 // No match rule to avoid chain rule match. 5215 effect(DEF dst, USE src); 5216 ins_cost(MEMORY_REF_COST); 5217 size(4); 5218 format %{ "LDF $src,$dst\t! stkI to regF" %} 5219 opcode(Assembler::ldf_op3); 5220 ins_encode(simple_form3_mem_reg(src, dst)); 5221 ins_pipe(floadF_stk); 5222 %} 5223 5224 instruct stkL_to_regD(regD dst, stackSlotL src) %{ 5225 // No match rule to avoid chain rule match. 5226 effect(DEF dst, USE src); 5227 ins_cost(MEMORY_REF_COST); 5228 size(4); 5229 format %{ "LDDF $src,$dst\t! stkL to regD" %} 5230 opcode(Assembler::lddf_op3); 5231 ins_encode(simple_form3_mem_reg(src, dst)); 5232 ins_pipe(floadD_stk); 5233 %} 5234 5235 instruct regF_to_stkI(stackSlotI dst, regF src) %{ 5236 // No match rule to avoid chain rule match. 5237 effect(DEF dst, USE src); 5238 ins_cost(MEMORY_REF_COST); 5239 size(4); 5240 format %{ "STF $src,$dst\t! regF to stkI" %} 5241 opcode(Assembler::stf_op3); 5242 ins_encode(simple_form3_mem_reg(dst, src)); 5243 ins_pipe(fstoreF_stk_reg); 5244 %} 5245 5246 instruct regD_to_stkL(stackSlotL dst, regD src) %{ 5247 // No match rule to avoid chain rule match. 5248 effect(DEF dst, USE src); 5249 ins_cost(MEMORY_REF_COST); 5250 size(4); 5251 format %{ "STDF $src,$dst\t! regD to stkL" %} 5252 opcode(Assembler::stdf_op3); 5253 ins_encode(simple_form3_mem_reg(dst, src)); 5254 ins_pipe(fstoreD_stk_reg); 5255 %} 5256 5257 instruct regI_to_stkLHi(stackSlotL dst, iRegI src) %{ 5258 effect(DEF dst, USE src); 5259 ins_cost(MEMORY_REF_COST*2); 5260 size(8); 5261 format %{ "STW $src,$dst.hi\t! long\n\t" 5262 "STW R_G0,$dst.lo" %} 5263 opcode(Assembler::stw_op3); 5264 ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, R_G0)); 5265 ins_pipe(lstoreI_stk_reg); 5266 %} 5267 5268 instruct regL_to_stkD(stackSlotD dst, iRegL src) %{ 5269 // No match rule to avoid chain rule match. 5270 effect(DEF dst, USE src); 5271 ins_cost(MEMORY_REF_COST); 5272 size(4); 5273 format %{ "STX $src,$dst\t! regL to stkD" %} 5274 opcode(Assembler::stx_op3); 5275 ins_encode(simple_form3_mem_reg( dst, src ) ); 5276 ins_pipe(istore_stk_reg); 5277 %} 5278 5279 //---------- Chain stack slots between similar types -------- 5280 5281 // Load integer from stack slot 5282 instruct stkI_to_regI( iRegI dst, stackSlotI src ) %{ 5283 match(Set dst src); 5284 ins_cost(MEMORY_REF_COST); 5285 5286 size(4); 5287 format %{ "LDUW $src,$dst\t!stk" %} 5288 opcode(Assembler::lduw_op3); 5289 ins_encode(simple_form3_mem_reg( src, dst ) ); 5290 ins_pipe(iload_mem); 5291 %} 5292 5293 // Store integer to stack slot 5294 instruct regI_to_stkI( stackSlotI dst, iRegI src ) %{ 5295 match(Set dst src); 5296 ins_cost(MEMORY_REF_COST); 5297 5298 size(4); 5299 format %{ "STW $src,$dst\t!stk" %} 5300 opcode(Assembler::stw_op3); 5301 ins_encode(simple_form3_mem_reg( dst, src ) ); 5302 ins_pipe(istore_mem_reg); 5303 %} 5304 5305 // Load long from stack slot 5306 instruct stkL_to_regL( iRegL dst, stackSlotL src ) %{ 5307 match(Set dst src); 5308 5309 ins_cost(MEMORY_REF_COST); 5310 size(4); 5311 format %{ "LDX $src,$dst\t! long" %} 5312 opcode(Assembler::ldx_op3); 5313 ins_encode(simple_form3_mem_reg( src, dst ) ); 5314 ins_pipe(iload_mem); 5315 %} 5316 5317 // Store long to stack slot 5318 instruct regL_to_stkL(stackSlotL dst, iRegL src) %{ 5319 match(Set dst src); 5320 5321 ins_cost(MEMORY_REF_COST); 5322 size(4); 5323 format %{ "STX $src,$dst\t! long" %} 5324 opcode(Assembler::stx_op3); 5325 ins_encode(simple_form3_mem_reg( dst, src ) ); 5326 ins_pipe(istore_mem_reg); 5327 %} 5328 5329 #ifdef _LP64 5330 // Load pointer from stack slot, 64-bit encoding 5331 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{ 5332 match(Set dst src); 5333 ins_cost(MEMORY_REF_COST); 5334 size(4); 5335 format %{ "LDX $src,$dst\t!ptr" %} 5336 opcode(Assembler::ldx_op3); 5337 ins_encode(simple_form3_mem_reg( src, dst ) ); 5338 ins_pipe(iload_mem); 5339 %} 5340 5341 // Store pointer to stack slot 5342 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{ 5343 match(Set dst src); 5344 ins_cost(MEMORY_REF_COST); 5345 size(4); 5346 format %{ "STX $src,$dst\t!ptr" %} 5347 opcode(Assembler::stx_op3); 5348 ins_encode(simple_form3_mem_reg( dst, src ) ); 5349 ins_pipe(istore_mem_reg); 5350 %} 5351 #else // _LP64 5352 // Load pointer from stack slot, 32-bit encoding 5353 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{ 5354 match(Set dst src); 5355 ins_cost(MEMORY_REF_COST); 5356 format %{ "LDUW $src,$dst\t!ptr" %} 5357 opcode(Assembler::lduw_op3, Assembler::ldst_op); 5358 ins_encode(simple_form3_mem_reg( src, dst ) ); 5359 ins_pipe(iload_mem); 5360 %} 5361 5362 // Store pointer to stack slot 5363 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{ 5364 match(Set dst src); 5365 ins_cost(MEMORY_REF_COST); 5366 format %{ "STW $src,$dst\t!ptr" %} 5367 opcode(Assembler::stw_op3, Assembler::ldst_op); 5368 ins_encode(simple_form3_mem_reg( dst, src ) ); 5369 ins_pipe(istore_mem_reg); 5370 %} 5371 #endif // _LP64 5372 5373 //------------Special Nop instructions for bundling - no match rules----------- 5374 // Nop using the A0 functional unit 5375 instruct Nop_A0() %{ 5376 ins_cost(0); 5377 5378 format %{ "NOP ! Alu Pipeline" %} 5379 opcode(Assembler::or_op3, Assembler::arith_op); 5380 ins_encode( form2_nop() ); 5381 ins_pipe(ialu_nop_A0); 5382 %} 5383 5384 // Nop using the A1 functional unit 5385 instruct Nop_A1( ) %{ 5386 ins_cost(0); 5387 5388 format %{ "NOP ! Alu Pipeline" %} 5389 opcode(Assembler::or_op3, Assembler::arith_op); 5390 ins_encode( form2_nop() ); 5391 ins_pipe(ialu_nop_A1); 5392 %} 5393 5394 // Nop using the memory functional unit 5395 instruct Nop_MS( ) %{ 5396 ins_cost(0); 5397 5398 format %{ "NOP ! Memory Pipeline" %} 5399 ins_encode( emit_mem_nop ); 5400 ins_pipe(mem_nop); 5401 %} 5402 5403 // Nop using the floating add functional unit 5404 instruct Nop_FA( ) %{ 5405 ins_cost(0); 5406 5407 format %{ "NOP ! Floating Add Pipeline" %} 5408 ins_encode( emit_fadd_nop ); 5409 ins_pipe(fadd_nop); 5410 %} 5411 5412 // Nop using the branch functional unit 5413 instruct Nop_BR( ) %{ 5414 ins_cost(0); 5415 5416 format %{ "NOP ! Branch Pipeline" %} 5417 ins_encode( emit_br_nop ); 5418 ins_pipe(br_nop); 5419 %} 5420 5421 //----------Load/Store/Move Instructions--------------------------------------- 5422 //----------Load Instructions-------------------------------------------------- 5423 // Load Byte (8bit signed) 5424 instruct loadB(iRegI dst, memory mem) %{ 5425 match(Set dst (LoadB mem)); 5426 ins_cost(MEMORY_REF_COST); 5427 5428 size(4); 5429 format %{ "LDSB $mem,$dst\t! byte" %} 5430 ins_encode %{ 5431 __ ldsb($mem$$Address, $dst$$Register); 5432 %} 5433 ins_pipe(iload_mask_mem); 5434 %} 5435 5436 // Load Byte (8bit signed) into a Long Register 5437 instruct loadB2L(iRegL dst, memory mem) %{ 5438 match(Set dst (ConvI2L (LoadB mem))); 5439 ins_cost(MEMORY_REF_COST); 5440 5441 size(4); 5442 format %{ "LDSB $mem,$dst\t! byte -> long" %} 5443 ins_encode %{ 5444 __ ldsb($mem$$Address, $dst$$Register); 5445 %} 5446 ins_pipe(iload_mask_mem); 5447 %} 5448 5449 // Load Unsigned Byte (8bit UNsigned) into an int reg 5450 instruct loadUB(iRegI dst, memory mem) %{ 5451 match(Set dst (LoadUB mem)); 5452 ins_cost(MEMORY_REF_COST); 5453 5454 size(4); 5455 format %{ "LDUB $mem,$dst\t! ubyte" %} 5456 ins_encode %{ 5457 __ ldub($mem$$Address, $dst$$Register); 5458 %} 5459 ins_pipe(iload_mask_mem); 5460 %} 5461 5462 // Load Unsigned Byte (8bit UNsigned) into a Long Register 5463 instruct loadUB2L(iRegL dst, memory mem) %{ 5464 match(Set dst (ConvI2L (LoadUB mem))); 5465 ins_cost(MEMORY_REF_COST); 5466 5467 size(4); 5468 format %{ "LDUB $mem,$dst\t! ubyte -> long" %} 5469 ins_encode %{ 5470 __ ldub($mem$$Address, $dst$$Register); 5471 %} 5472 ins_pipe(iload_mask_mem); 5473 %} 5474 5475 // Load Short (16bit signed) 5476 instruct loadS(iRegI dst, memory mem) %{ 5477 match(Set dst (LoadS mem)); 5478 ins_cost(MEMORY_REF_COST); 5479 5480 size(4); 5481 format %{ "LDSH $mem,$dst\t! short" %} 5482 ins_encode %{ 5483 __ ldsh($mem$$Address, $dst$$Register); 5484 %} 5485 ins_pipe(iload_mask_mem); 5486 %} 5487 5488 // Load Short (16bit signed) into a Long Register 5489 instruct loadS2L(iRegL dst, memory mem) %{ 5490 match(Set dst (ConvI2L (LoadS mem))); 5491 ins_cost(MEMORY_REF_COST); 5492 5493 size(4); 5494 format %{ "LDSH $mem,$dst\t! short -> long" %} 5495 ins_encode %{ 5496 __ ldsh($mem$$Address, $dst$$Register); 5497 %} 5498 ins_pipe(iload_mask_mem); 5499 %} 5500 5501 // Load Unsigned Short/Char (16bit UNsigned) 5502 instruct loadUS(iRegI dst, memory mem) %{ 5503 match(Set dst (LoadUS mem)); 5504 ins_cost(MEMORY_REF_COST); 5505 5506 size(4); 5507 format %{ "LDUH $mem,$dst\t! ushort/char" %} 5508 ins_encode %{ 5509 __ lduh($mem$$Address, $dst$$Register); 5510 %} 5511 ins_pipe(iload_mask_mem); 5512 %} 5513 5514 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register 5515 instruct loadUS2L(iRegL dst, memory mem) %{ 5516 match(Set dst (ConvI2L (LoadUS mem))); 5517 ins_cost(MEMORY_REF_COST); 5518 5519 size(4); 5520 format %{ "LDUH $mem,$dst\t! ushort/char -> long" %} 5521 ins_encode %{ 5522 __ lduh($mem$$Address, $dst$$Register); 5523 %} 5524 ins_pipe(iload_mask_mem); 5525 %} 5526 5527 // Load Integer 5528 instruct loadI(iRegI dst, memory mem) %{ 5529 match(Set dst (LoadI mem)); 5530 ins_cost(MEMORY_REF_COST); 5531 5532 size(4); 5533 format %{ "LDUW $mem,$dst\t! int" %} 5534 ins_encode %{ 5535 __ lduw($mem$$Address, $dst$$Register); 5536 %} 5537 ins_pipe(iload_mem); 5538 %} 5539 5540 // Load Integer into a Long Register 5541 instruct loadI2L(iRegL dst, memory mem) %{ 5542 match(Set dst (ConvI2L (LoadI mem))); 5543 ins_cost(MEMORY_REF_COST); 5544 5545 size(4); 5546 format %{ "LDSW $mem,$dst\t! int -> long" %} 5547 ins_encode %{ 5548 __ ldsw($mem$$Address, $dst$$Register); 5549 %} 5550 ins_pipe(iload_mem); 5551 %} 5552 5553 // Load Unsigned Integer into a Long Register 5554 instruct loadUI2L(iRegL dst, memory mem) %{ 5555 match(Set dst (LoadUI2L mem)); 5556 ins_cost(MEMORY_REF_COST); 5557 5558 size(4); 5559 format %{ "LDUW $mem,$dst\t! uint -> long" %} 5560 ins_encode %{ 5561 __ lduw($mem$$Address, $dst$$Register); 5562 %} 5563 ins_pipe(iload_mem); 5564 %} 5565 5566 // Load Long - aligned 5567 instruct loadL(iRegL dst, memory mem ) %{ 5568 match(Set dst (LoadL mem)); 5569 ins_cost(MEMORY_REF_COST); 5570 5571 size(4); 5572 format %{ "LDX $mem,$dst\t! long" %} 5573 ins_encode %{ 5574 __ ldx($mem$$Address, $dst$$Register); 5575 %} 5576 ins_pipe(iload_mem); 5577 %} 5578 5579 // Load Long - UNaligned 5580 instruct loadL_unaligned(iRegL dst, memory mem, o7RegI tmp) %{ 5581 match(Set dst (LoadL_unaligned mem)); 5582 effect(KILL tmp); 5583 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST); 5584 size(16); 5585 format %{ "LDUW $mem+4,R_O7\t! misaligned long\n" 5586 "\tLDUW $mem ,$dst\n" 5587 "\tSLLX #32, $dst, $dst\n" 5588 "\tOR $dst, R_O7, $dst" %} 5589 opcode(Assembler::lduw_op3); 5590 ins_encode(form3_mem_reg_long_unaligned_marshal( mem, dst )); 5591 ins_pipe(iload_mem); 5592 %} 5593 5594 // Load Aligned Packed Byte into a Double Register 5595 instruct loadA8B(regD dst, memory mem) %{ 5596 match(Set dst (Load8B mem)); 5597 ins_cost(MEMORY_REF_COST); 5598 size(4); 5599 format %{ "LDDF $mem,$dst\t! packed8B" %} 5600 opcode(Assembler::lddf_op3); 5601 ins_encode(simple_form3_mem_reg( mem, dst ) ); 5602 ins_pipe(floadD_mem); 5603 %} 5604 5605 // Load Aligned Packed Char into a Double Register 5606 instruct loadA4C(regD dst, memory mem) %{ 5607 match(Set dst (Load4C mem)); 5608 ins_cost(MEMORY_REF_COST); 5609 size(4); 5610 format %{ "LDDF $mem,$dst\t! packed4C" %} 5611 opcode(Assembler::lddf_op3); 5612 ins_encode(simple_form3_mem_reg( mem, dst ) ); 5613 ins_pipe(floadD_mem); 5614 %} 5615 5616 // Load Aligned Packed Short into a Double Register 5617 instruct loadA4S(regD dst, memory mem) %{ 5618 match(Set dst (Load4S mem)); 5619 ins_cost(MEMORY_REF_COST); 5620 size(4); 5621 format %{ "LDDF $mem,$dst\t! packed4S" %} 5622 opcode(Assembler::lddf_op3); 5623 ins_encode(simple_form3_mem_reg( mem, dst ) ); 5624 ins_pipe(floadD_mem); 5625 %} 5626 5627 // Load Aligned Packed Int into a Double Register 5628 instruct loadA2I(regD dst, memory mem) %{ 5629 match(Set dst (Load2I mem)); 5630 ins_cost(MEMORY_REF_COST); 5631 size(4); 5632 format %{ "LDDF $mem,$dst\t! packed2I" %} 5633 opcode(Assembler::lddf_op3); 5634 ins_encode(simple_form3_mem_reg( mem, dst ) ); 5635 ins_pipe(floadD_mem); 5636 %} 5637 5638 // Load Range 5639 instruct loadRange(iRegI dst, memory mem) %{ 5640 match(Set dst (LoadRange mem)); 5641 ins_cost(MEMORY_REF_COST); 5642 5643 size(4); 5644 format %{ "LDUW $mem,$dst\t! range" %} 5645 opcode(Assembler::lduw_op3); 5646 ins_encode(simple_form3_mem_reg( mem, dst ) ); 5647 ins_pipe(iload_mem); 5648 %} 5649 5650 // Load Integer into %f register (for fitos/fitod) 5651 instruct loadI_freg(regF dst, memory mem) %{ 5652 match(Set dst (LoadI mem)); 5653 ins_cost(MEMORY_REF_COST); 5654 size(4); 5655 5656 format %{ "LDF $mem,$dst\t! for fitos/fitod" %} 5657 opcode(Assembler::ldf_op3); 5658 ins_encode(simple_form3_mem_reg( mem, dst ) ); 5659 ins_pipe(floadF_mem); 5660 %} 5661 5662 // Load Pointer 5663 instruct loadP(iRegP dst, memory mem) %{ 5664 match(Set dst (LoadP mem)); 5665 ins_cost(MEMORY_REF_COST); 5666 size(4); 5667 5668 #ifndef _LP64 5669 format %{ "LDUW $mem,$dst\t! ptr" %} 5670 ins_encode %{ 5671 __ lduw($mem$$Address, $dst$$Register); 5672 %} 5673 #else 5674 format %{ "LDX $mem,$dst\t! ptr" %} 5675 ins_encode %{ 5676 __ ldx($mem$$Address, $dst$$Register); 5677 %} 5678 #endif 5679 ins_pipe(iload_mem); 5680 %} 5681 5682 // Load Compressed Pointer 5683 instruct loadN(iRegN dst, memory mem) %{ 5684 match(Set dst (LoadN mem)); 5685 ins_cost(MEMORY_REF_COST); 5686 size(4); 5687 5688 format %{ "LDUW $mem,$dst\t! compressed ptr" %} 5689 ins_encode %{ 5690 __ lduw($mem$$Address, $dst$$Register); 5691 %} 5692 ins_pipe(iload_mem); 5693 %} 5694 5695 // Load Klass Pointer 5696 instruct loadKlass(iRegP dst, memory mem) %{ 5697 match(Set dst (LoadKlass mem)); 5698 ins_cost(MEMORY_REF_COST); 5699 size(4); 5700 5701 #ifndef _LP64 5702 format %{ "LDUW $mem,$dst\t! klass ptr" %} 5703 ins_encode %{ 5704 __ lduw($mem$$Address, $dst$$Register); 5705 %} 5706 #else 5707 format %{ "LDX $mem,$dst\t! klass ptr" %} 5708 ins_encode %{ 5709 __ ldx($mem$$Address, $dst$$Register); 5710 %} 5711 #endif 5712 ins_pipe(iload_mem); 5713 %} 5714 5715 // Load narrow Klass Pointer 5716 instruct loadNKlass(iRegN dst, memory mem) %{ 5717 match(Set dst (LoadNKlass mem)); 5718 ins_cost(MEMORY_REF_COST); 5719 size(4); 5720 5721 format %{ "LDUW $mem,$dst\t! compressed klass ptr" %} 5722 ins_encode %{ 5723 __ lduw($mem$$Address, $dst$$Register); 5724 %} 5725 ins_pipe(iload_mem); 5726 %} 5727 5728 // Load Double 5729 instruct loadD(regD dst, memory mem) %{ 5730 match(Set dst (LoadD mem)); 5731 ins_cost(MEMORY_REF_COST); 5732 5733 size(4); 5734 format %{ "LDDF $mem,$dst" %} 5735 opcode(Assembler::lddf_op3); 5736 ins_encode(simple_form3_mem_reg( mem, dst ) ); 5737 ins_pipe(floadD_mem); 5738 %} 5739 5740 // Load Double - UNaligned 5741 instruct loadD_unaligned(regD_low dst, memory mem ) %{ 5742 match(Set dst (LoadD_unaligned mem)); 5743 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST); 5744 size(8); 5745 format %{ "LDF $mem ,$dst.hi\t! misaligned double\n" 5746 "\tLDF $mem+4,$dst.lo\t!" %} 5747 opcode(Assembler::ldf_op3); 5748 ins_encode( form3_mem_reg_double_unaligned( mem, dst )); 5749 ins_pipe(iload_mem); 5750 %} 5751 5752 // Load Float 5753 instruct loadF(regF dst, memory mem) %{ 5754 match(Set dst (LoadF mem)); 5755 ins_cost(MEMORY_REF_COST); 5756 5757 size(4); 5758 format %{ "LDF $mem,$dst" %} 5759 opcode(Assembler::ldf_op3); 5760 ins_encode(simple_form3_mem_reg( mem, dst ) ); 5761 ins_pipe(floadF_mem); 5762 %} 5763 5764 // Load Constant 5765 instruct loadConI( iRegI dst, immI src ) %{ 5766 match(Set dst src); 5767 ins_cost(DEFAULT_COST * 3/2); 5768 format %{ "SET $src,$dst" %} 5769 ins_encode( Set32(src, dst) ); 5770 ins_pipe(ialu_hi_lo_reg); 5771 %} 5772 5773 instruct loadConI13( iRegI dst, immI13 src ) %{ 5774 match(Set dst src); 5775 5776 size(4); 5777 format %{ "MOV $src,$dst" %} 5778 ins_encode( Set13( src, dst ) ); 5779 ins_pipe(ialu_imm); 5780 %} 5781 5782 instruct loadConP(iRegP dst, immP src) %{ 5783 match(Set dst src); 5784 ins_cost(DEFAULT_COST * 3/2); 5785 format %{ "SET $src,$dst\t!ptr" %} 5786 // This rule does not use "expand" unlike loadConI because then 5787 // the result type is not known to be an Oop. An ADLC 5788 // enhancement will be needed to make that work - not worth it! 5789 5790 ins_encode( SetPtr( src, dst ) ); 5791 ins_pipe(loadConP); 5792 5793 %} 5794 5795 instruct loadConP0(iRegP dst, immP0 src) %{ 5796 match(Set dst src); 5797 5798 size(4); 5799 format %{ "CLR $dst\t!ptr" %} 5800 ins_encode( SetNull( dst ) ); 5801 ins_pipe(ialu_imm); 5802 %} 5803 5804 instruct loadConP_poll(iRegP dst, immP_poll src) %{ 5805 match(Set dst src); 5806 ins_cost(DEFAULT_COST); 5807 format %{ "SET $src,$dst\t!ptr" %} 5808 ins_encode %{ 5809 AddressLiteral polling_page(os::get_polling_page()); 5810 __ sethi(polling_page, reg_to_register_object($dst$$reg)); 5811 %} 5812 ins_pipe(loadConP_poll); 5813 %} 5814 5815 instruct loadConN0(iRegN dst, immN0 src) %{ 5816 match(Set dst src); 5817 5818 size(4); 5819 format %{ "CLR $dst\t! compressed NULL ptr" %} 5820 ins_encode( SetNull( dst ) ); 5821 ins_pipe(ialu_imm); 5822 %} 5823 5824 instruct loadConN(iRegN dst, immN src) %{ 5825 match(Set dst src); 5826 ins_cost(DEFAULT_COST * 3/2); 5827 format %{ "SET $src,$dst\t! compressed ptr" %} 5828 ins_encode %{ 5829 Register dst = $dst$$Register; 5830 __ set_narrow_oop((jobject)$src$$constant, dst); 5831 %} 5832 ins_pipe(ialu_hi_lo_reg); 5833 %} 5834 5835 instruct loadConL(iRegL dst, immL src, o7RegL tmp) %{ 5836 // %%% maybe this should work like loadConD 5837 match(Set dst src); 5838 effect(KILL tmp); 5839 ins_cost(DEFAULT_COST * 4); 5840 format %{ "SET64 $src,$dst KILL $tmp\t! long" %} 5841 ins_encode( LdImmL(src, dst, tmp) ); 5842 ins_pipe(loadConL); 5843 %} 5844 5845 instruct loadConL0( iRegL dst, immL0 src ) %{ 5846 match(Set dst src); 5847 ins_cost(DEFAULT_COST); 5848 size(4); 5849 format %{ "CLR $dst\t! long" %} 5850 ins_encode( Set13( src, dst ) ); 5851 ins_pipe(ialu_imm); 5852 %} 5853 5854 instruct loadConL13( iRegL dst, immL13 src ) %{ 5855 match(Set dst src); 5856 ins_cost(DEFAULT_COST * 2); 5857 5858 size(4); 5859 format %{ "MOV $src,$dst\t! long" %} 5860 ins_encode( Set13( src, dst ) ); 5861 ins_pipe(ialu_imm); 5862 %} 5863 5864 instruct loadConF(regF dst, immF src, o7RegP tmp) %{ 5865 match(Set dst src); 5866 effect(KILL tmp); 5867 5868 #ifdef _LP64 5869 size(8*4); 5870 #else 5871 size(2*4); 5872 #endif 5873 5874 format %{ "SETHI hi(&$src),$tmp\t!get float $src from table\n\t" 5875 "LDF [$tmp+lo(&$src)],$dst" %} 5876 ins_encode %{ 5877 address float_address = __ float_constant($src$$constant); 5878 RelocationHolder rspec = internal_word_Relocation::spec(float_address); 5879 AddressLiteral addrlit(float_address, rspec); 5880 5881 __ sethi(addrlit, $tmp$$Register); 5882 __ ldf(FloatRegisterImpl::S, $tmp$$Register, addrlit.low10(), $dst$$FloatRegister, rspec); 5883 %} 5884 ins_pipe(loadConFD); 5885 %} 5886 5887 instruct loadConD(regD dst, immD src, o7RegP tmp) %{ 5888 match(Set dst src); 5889 effect(KILL tmp); 5890 5891 #ifdef _LP64 5892 size(8*4); 5893 #else 5894 size(2*4); 5895 #endif 5896 5897 format %{ "SETHI hi(&$src),$tmp\t!get double $src from table\n\t" 5898 "LDDF [$tmp+lo(&$src)],$dst" %} 5899 ins_encode %{ 5900 address double_address = __ double_constant($src$$constant); 5901 RelocationHolder rspec = internal_word_Relocation::spec(double_address); 5902 AddressLiteral addrlit(double_address, rspec); 5903 5904 __ sethi(addrlit, $tmp$$Register); 5905 __ ldf(FloatRegisterImpl::D, $tmp$$Register, addrlit.low10(), $dst$$FloatRegister, rspec); 5906 %} 5907 ins_pipe(loadConFD); 5908 %} 5909 5910 // Prefetch instructions. 5911 // Must be safe to execute with invalid address (cannot fault). 5912 5913 instruct prefetchr( memory mem ) %{ 5914 match( PrefetchRead mem ); 5915 ins_cost(MEMORY_REF_COST); 5916 5917 format %{ "PREFETCH $mem,0\t! Prefetch read-many" %} 5918 opcode(Assembler::prefetch_op3); 5919 ins_encode( form3_mem_prefetch_read( mem ) ); 5920 ins_pipe(iload_mem); 5921 %} 5922 5923 instruct prefetchw( memory mem ) %{ 5924 match( PrefetchWrite mem ); 5925 ins_cost(MEMORY_REF_COST); 5926 5927 format %{ "PREFETCH $mem,2\t! Prefetch write-many (and read)" %} 5928 opcode(Assembler::prefetch_op3); 5929 ins_encode( form3_mem_prefetch_write( mem ) ); 5930 ins_pipe(iload_mem); 5931 %} 5932 5933 5934 //----------Store Instructions------------------------------------------------- 5935 // Store Byte 5936 instruct storeB(memory mem, iRegI src) %{ 5937 match(Set mem (StoreB mem src)); 5938 ins_cost(MEMORY_REF_COST); 5939 5940 size(4); 5941 format %{ "STB $src,$mem\t! byte" %} 5942 opcode(Assembler::stb_op3); 5943 ins_encode(simple_form3_mem_reg( mem, src ) ); 5944 ins_pipe(istore_mem_reg); 5945 %} 5946 5947 instruct storeB0(memory mem, immI0 src) %{ 5948 match(Set mem (StoreB mem src)); 5949 ins_cost(MEMORY_REF_COST); 5950 5951 size(4); 5952 format %{ "STB $src,$mem\t! byte" %} 5953 opcode(Assembler::stb_op3); 5954 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); 5955 ins_pipe(istore_mem_zero); 5956 %} 5957 5958 instruct storeCM0(memory mem, immI0 src) %{ 5959 match(Set mem (StoreCM mem src)); 5960 ins_cost(MEMORY_REF_COST); 5961 5962 size(4); 5963 format %{ "STB $src,$mem\t! CMS card-mark byte 0" %} 5964 opcode(Assembler::stb_op3); 5965 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); 5966 ins_pipe(istore_mem_zero); 5967 %} 5968 5969 // Store Char/Short 5970 instruct storeC(memory mem, iRegI src) %{ 5971 match(Set mem (StoreC mem src)); 5972 ins_cost(MEMORY_REF_COST); 5973 5974 size(4); 5975 format %{ "STH $src,$mem\t! short" %} 5976 opcode(Assembler::sth_op3); 5977 ins_encode(simple_form3_mem_reg( mem, src ) ); 5978 ins_pipe(istore_mem_reg); 5979 %} 5980 5981 instruct storeC0(memory mem, immI0 src) %{ 5982 match(Set mem (StoreC mem src)); 5983 ins_cost(MEMORY_REF_COST); 5984 5985 size(4); 5986 format %{ "STH $src,$mem\t! short" %} 5987 opcode(Assembler::sth_op3); 5988 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); 5989 ins_pipe(istore_mem_zero); 5990 %} 5991 5992 // Store Integer 5993 instruct storeI(memory mem, iRegI src) %{ 5994 match(Set mem (StoreI mem src)); 5995 ins_cost(MEMORY_REF_COST); 5996 5997 size(4); 5998 format %{ "STW $src,$mem" %} 5999 opcode(Assembler::stw_op3); 6000 ins_encode(simple_form3_mem_reg( mem, src ) ); 6001 ins_pipe(istore_mem_reg); 6002 %} 6003 6004 // Store Long 6005 instruct storeL(memory mem, iRegL src) %{ 6006 match(Set mem (StoreL mem src)); 6007 ins_cost(MEMORY_REF_COST); 6008 size(4); 6009 format %{ "STX $src,$mem\t! long" %} 6010 opcode(Assembler::stx_op3); 6011 ins_encode(simple_form3_mem_reg( mem, src ) ); 6012 ins_pipe(istore_mem_reg); 6013 %} 6014 6015 instruct storeI0(memory mem, immI0 src) %{ 6016 match(Set mem (StoreI mem src)); 6017 ins_cost(MEMORY_REF_COST); 6018 6019 size(4); 6020 format %{ "STW $src,$mem" %} 6021 opcode(Assembler::stw_op3); 6022 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); 6023 ins_pipe(istore_mem_zero); 6024 %} 6025 6026 instruct storeL0(memory mem, immL0 src) %{ 6027 match(Set mem (StoreL mem src)); 6028 ins_cost(MEMORY_REF_COST); 6029 6030 size(4); 6031 format %{ "STX $src,$mem" %} 6032 opcode(Assembler::stx_op3); 6033 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); 6034 ins_pipe(istore_mem_zero); 6035 %} 6036 6037 // Store Integer from float register (used after fstoi) 6038 instruct storeI_Freg(memory mem, regF src) %{ 6039 match(Set mem (StoreI mem src)); 6040 ins_cost(MEMORY_REF_COST); 6041 6042 size(4); 6043 format %{ "STF $src,$mem\t! after fstoi/fdtoi" %} 6044 opcode(Assembler::stf_op3); 6045 ins_encode(simple_form3_mem_reg( mem, src ) ); 6046 ins_pipe(fstoreF_mem_reg); 6047 %} 6048 6049 // Store Pointer 6050 instruct storeP(memory dst, sp_ptr_RegP src) %{ 6051 match(Set dst (StoreP dst src)); 6052 ins_cost(MEMORY_REF_COST); 6053 size(4); 6054 6055 #ifndef _LP64 6056 format %{ "STW $src,$dst\t! ptr" %} 6057 opcode(Assembler::stw_op3, 0, REGP_OP); 6058 #else 6059 format %{ "STX $src,$dst\t! ptr" %} 6060 opcode(Assembler::stx_op3, 0, REGP_OP); 6061 #endif 6062 ins_encode( form3_mem_reg( dst, src ) ); 6063 ins_pipe(istore_mem_spORreg); 6064 %} 6065 6066 instruct storeP0(memory dst, immP0 src) %{ 6067 match(Set dst (StoreP dst src)); 6068 ins_cost(MEMORY_REF_COST); 6069 size(4); 6070 6071 #ifndef _LP64 6072 format %{ "STW $src,$dst\t! ptr" %} 6073 opcode(Assembler::stw_op3, 0, REGP_OP); 6074 #else 6075 format %{ "STX $src,$dst\t! ptr" %} 6076 opcode(Assembler::stx_op3, 0, REGP_OP); 6077 #endif 6078 ins_encode( form3_mem_reg( dst, R_G0 ) ); 6079 ins_pipe(istore_mem_zero); 6080 %} 6081 6082 // Store Compressed Pointer 6083 instruct storeN(memory dst, iRegN src) %{ 6084 match(Set dst (StoreN dst src)); 6085 ins_cost(MEMORY_REF_COST); 6086 size(4); 6087 6088 format %{ "STW $src,$dst\t! compressed ptr" %} 6089 ins_encode %{ 6090 Register base = as_Register($dst$$base); 6091 Register index = as_Register($dst$$index); 6092 Register src = $src$$Register; 6093 if (index != G0) { 6094 __ stw(src, base, index); 6095 } else { 6096 __ stw(src, base, $dst$$disp); 6097 } 6098 %} 6099 ins_pipe(istore_mem_spORreg); 6100 %} 6101 6102 instruct storeN0(memory dst, immN0 src) %{ 6103 match(Set dst (StoreN dst src)); 6104 ins_cost(MEMORY_REF_COST); 6105 size(4); 6106 6107 format %{ "STW $src,$dst\t! compressed ptr" %} 6108 ins_encode %{ 6109 Register base = as_Register($dst$$base); 6110 Register index = as_Register($dst$$index); 6111 if (index != G0) { 6112 __ stw(0, base, index); 6113 } else { 6114 __ stw(0, base, $dst$$disp); 6115 } 6116 %} 6117 ins_pipe(istore_mem_zero); 6118 %} 6119 6120 // Store Double 6121 instruct storeD( memory mem, regD src) %{ 6122 match(Set mem (StoreD mem src)); 6123 ins_cost(MEMORY_REF_COST); 6124 6125 size(4); 6126 format %{ "STDF $src,$mem" %} 6127 opcode(Assembler::stdf_op3); 6128 ins_encode(simple_form3_mem_reg( mem, src ) ); 6129 ins_pipe(fstoreD_mem_reg); 6130 %} 6131 6132 instruct storeD0( memory mem, immD0 src) %{ 6133 match(Set mem (StoreD mem src)); 6134 ins_cost(MEMORY_REF_COST); 6135 6136 size(4); 6137 format %{ "STX $src,$mem" %} 6138 opcode(Assembler::stx_op3); 6139 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); 6140 ins_pipe(fstoreD_mem_zero); 6141 %} 6142 6143 // Store Float 6144 instruct storeF( memory mem, regF src) %{ 6145 match(Set mem (StoreF mem src)); 6146 ins_cost(MEMORY_REF_COST); 6147 6148 size(4); 6149 format %{ "STF $src,$mem" %} 6150 opcode(Assembler::stf_op3); 6151 ins_encode(simple_form3_mem_reg( mem, src ) ); 6152 ins_pipe(fstoreF_mem_reg); 6153 %} 6154 6155 instruct storeF0( memory mem, immF0 src) %{ 6156 match(Set mem (StoreF mem src)); 6157 ins_cost(MEMORY_REF_COST); 6158 6159 size(4); 6160 format %{ "STW $src,$mem\t! storeF0" %} 6161 opcode(Assembler::stw_op3); 6162 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); 6163 ins_pipe(fstoreF_mem_zero); 6164 %} 6165 6166 // Store Aligned Packed Bytes in Double register to memory 6167 instruct storeA8B(memory mem, regD src) %{ 6168 match(Set mem (Store8B mem src)); 6169 ins_cost(MEMORY_REF_COST); 6170 size(4); 6171 format %{ "STDF $src,$mem\t! packed8B" %} 6172 opcode(Assembler::stdf_op3); 6173 ins_encode(simple_form3_mem_reg( mem, src ) ); 6174 ins_pipe(fstoreD_mem_reg); 6175 %} 6176 6177 // Convert oop pointer into compressed form 6178 instruct encodeHeapOop(iRegN dst, iRegP src) %{ 6179 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull); 6180 match(Set dst (EncodeP src)); 6181 format %{ "encode_heap_oop $src, $dst" %} 6182 ins_encode %{ 6183 __ encode_heap_oop($src$$Register, $dst$$Register); 6184 %} 6185 ins_pipe(ialu_reg); 6186 %} 6187 6188 instruct encodeHeapOop_not_null(iRegN dst, iRegP src) %{ 6189 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull); 6190 match(Set dst (EncodeP src)); 6191 format %{ "encode_heap_oop_not_null $src, $dst" %} 6192 ins_encode %{ 6193 __ encode_heap_oop_not_null($src$$Register, $dst$$Register); 6194 %} 6195 ins_pipe(ialu_reg); 6196 %} 6197 6198 instruct decodeHeapOop(iRegP dst, iRegN src) %{ 6199 predicate(n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull && 6200 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant); 6201 match(Set dst (DecodeN src)); 6202 format %{ "decode_heap_oop $src, $dst" %} 6203 ins_encode %{ 6204 __ decode_heap_oop($src$$Register, $dst$$Register); 6205 %} 6206 ins_pipe(ialu_reg); 6207 %} 6208 6209 instruct decodeHeapOop_not_null(iRegP dst, iRegN src) %{ 6210 predicate(n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull || 6211 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant); 6212 match(Set dst (DecodeN src)); 6213 format %{ "decode_heap_oop_not_null $src, $dst" %} 6214 ins_encode %{ 6215 __ decode_heap_oop_not_null($src$$Register, $dst$$Register); 6216 %} 6217 ins_pipe(ialu_reg); 6218 %} 6219 6220 6221 // Store Zero into Aligned Packed Bytes 6222 instruct storeA8B0(memory mem, immI0 zero) %{ 6223 match(Set mem (Store8B mem zero)); 6224 ins_cost(MEMORY_REF_COST); 6225 size(4); 6226 format %{ "STX $zero,$mem\t! packed8B" %} 6227 opcode(Assembler::stx_op3); 6228 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); 6229 ins_pipe(fstoreD_mem_zero); 6230 %} 6231 6232 // Store Aligned Packed Chars/Shorts in Double register to memory 6233 instruct storeA4C(memory mem, regD src) %{ 6234 match(Set mem (Store4C mem src)); 6235 ins_cost(MEMORY_REF_COST); 6236 size(4); 6237 format %{ "STDF $src,$mem\t! packed4C" %} 6238 opcode(Assembler::stdf_op3); 6239 ins_encode(simple_form3_mem_reg( mem, src ) ); 6240 ins_pipe(fstoreD_mem_reg); 6241 %} 6242 6243 // Store Zero into Aligned Packed Chars/Shorts 6244 instruct storeA4C0(memory mem, immI0 zero) %{ 6245 match(Set mem (Store4C mem (Replicate4C zero))); 6246 ins_cost(MEMORY_REF_COST); 6247 size(4); 6248 format %{ "STX $zero,$mem\t! packed4C" %} 6249 opcode(Assembler::stx_op3); 6250 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); 6251 ins_pipe(fstoreD_mem_zero); 6252 %} 6253 6254 // Store Aligned Packed Ints in Double register to memory 6255 instruct storeA2I(memory mem, regD src) %{ 6256 match(Set mem (Store2I mem src)); 6257 ins_cost(MEMORY_REF_COST); 6258 size(4); 6259 format %{ "STDF $src,$mem\t! packed2I" %} 6260 opcode(Assembler::stdf_op3); 6261 ins_encode(simple_form3_mem_reg( mem, src ) ); 6262 ins_pipe(fstoreD_mem_reg); 6263 %} 6264 6265 // Store Zero into Aligned Packed Ints 6266 instruct storeA2I0(memory mem, immI0 zero) %{ 6267 match(Set mem (Store2I mem zero)); 6268 ins_cost(MEMORY_REF_COST); 6269 size(4); 6270 format %{ "STX $zero,$mem\t! packed2I" %} 6271 opcode(Assembler::stx_op3); 6272 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); 6273 ins_pipe(fstoreD_mem_zero); 6274 %} 6275 6276 6277 //----------MemBar Instructions----------------------------------------------- 6278 // Memory barrier flavors 6279 6280 instruct membar_acquire() %{ 6281 match(MemBarAcquire); 6282 ins_cost(4*MEMORY_REF_COST); 6283 6284 size(0); 6285 format %{ "MEMBAR-acquire" %} 6286 ins_encode( enc_membar_acquire ); 6287 ins_pipe(long_memory_op); 6288 %} 6289 6290 instruct membar_acquire_lock() %{ 6291 match(MemBarAcquire); 6292 predicate(Matcher::prior_fast_lock(n)); 6293 ins_cost(0); 6294 6295 size(0); 6296 format %{ "!MEMBAR-acquire (CAS in prior FastLock so empty encoding)" %} 6297 ins_encode( ); 6298 ins_pipe(empty); 6299 %} 6300 6301 instruct membar_release() %{ 6302 match(MemBarRelease); 6303 ins_cost(4*MEMORY_REF_COST); 6304 6305 size(0); 6306 format %{ "MEMBAR-release" %} 6307 ins_encode( enc_membar_release ); 6308 ins_pipe(long_memory_op); 6309 %} 6310 6311 instruct membar_release_lock() %{ 6312 match(MemBarRelease); 6313 predicate(Matcher::post_fast_unlock(n)); 6314 ins_cost(0); 6315 6316 size(0); 6317 format %{ "!MEMBAR-release (CAS in succeeding FastUnlock so empty encoding)" %} 6318 ins_encode( ); 6319 ins_pipe(empty); 6320 %} 6321 6322 instruct membar_volatile() %{ 6323 match(MemBarVolatile); 6324 ins_cost(4*MEMORY_REF_COST); 6325 6326 size(4); 6327 format %{ "MEMBAR-volatile" %} 6328 ins_encode( enc_membar_volatile ); 6329 ins_pipe(long_memory_op); 6330 %} 6331 6332 instruct unnecessary_membar_volatile() %{ 6333 match(MemBarVolatile); 6334 predicate(Matcher::post_store_load_barrier(n)); 6335 ins_cost(0); 6336 6337 size(0); 6338 format %{ "!MEMBAR-volatile (unnecessary so empty encoding)" %} 6339 ins_encode( ); 6340 ins_pipe(empty); 6341 %} 6342 6343 //----------Register Move Instructions----------------------------------------- 6344 instruct roundDouble_nop(regD dst) %{ 6345 match(Set dst (RoundDouble dst)); 6346 ins_cost(0); 6347 // SPARC results are already "rounded" (i.e., normal-format IEEE) 6348 ins_encode( ); 6349 ins_pipe(empty); 6350 %} 6351 6352 6353 instruct roundFloat_nop(regF dst) %{ 6354 match(Set dst (RoundFloat dst)); 6355 ins_cost(0); 6356 // SPARC results are already "rounded" (i.e., normal-format IEEE) 6357 ins_encode( ); 6358 ins_pipe(empty); 6359 %} 6360 6361 6362 // Cast Index to Pointer for unsafe natives 6363 instruct castX2P(iRegX src, iRegP dst) %{ 6364 match(Set dst (CastX2P src)); 6365 6366 format %{ "MOV $src,$dst\t! IntX->Ptr" %} 6367 ins_encode( form3_g0_rs2_rd_move( src, dst ) ); 6368 ins_pipe(ialu_reg); 6369 %} 6370 6371 // Cast Pointer to Index for unsafe natives 6372 instruct castP2X(iRegP src, iRegX dst) %{ 6373 match(Set dst (CastP2X src)); 6374 6375 format %{ "MOV $src,$dst\t! Ptr->IntX" %} 6376 ins_encode( form3_g0_rs2_rd_move( src, dst ) ); 6377 ins_pipe(ialu_reg); 6378 %} 6379 6380 instruct stfSSD(stackSlotD stkSlot, regD src) %{ 6381 // %%%% TO DO: Tell the coalescer that this kind of node is a copy! 6382 match(Set stkSlot src); // chain rule 6383 ins_cost(MEMORY_REF_COST); 6384 format %{ "STDF $src,$stkSlot\t!stk" %} 6385 opcode(Assembler::stdf_op3); 6386 ins_encode(simple_form3_mem_reg(stkSlot, src)); 6387 ins_pipe(fstoreD_stk_reg); 6388 %} 6389 6390 instruct ldfSSD(regD dst, stackSlotD stkSlot) %{ 6391 // %%%% TO DO: Tell the coalescer that this kind of node is a copy! 6392 match(Set dst stkSlot); // chain rule 6393 ins_cost(MEMORY_REF_COST); 6394 format %{ "LDDF $stkSlot,$dst\t!stk" %} 6395 opcode(Assembler::lddf_op3); 6396 ins_encode(simple_form3_mem_reg(stkSlot, dst)); 6397 ins_pipe(floadD_stk); 6398 %} 6399 6400 instruct stfSSF(stackSlotF stkSlot, regF src) %{ 6401 // %%%% TO DO: Tell the coalescer that this kind of node is a copy! 6402 match(Set stkSlot src); // chain rule 6403 ins_cost(MEMORY_REF_COST); 6404 format %{ "STF $src,$stkSlot\t!stk" %} 6405 opcode(Assembler::stf_op3); 6406 ins_encode(simple_form3_mem_reg(stkSlot, src)); 6407 ins_pipe(fstoreF_stk_reg); 6408 %} 6409 6410 //----------Conditional Move--------------------------------------------------- 6411 // Conditional move 6412 instruct cmovIP_reg(cmpOpP cmp, flagsRegP pcc, iRegI dst, iRegI src) %{ 6413 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src))); 6414 ins_cost(150); 6415 format %{ "MOV$cmp $pcc,$src,$dst" %} 6416 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); 6417 ins_pipe(ialu_reg); 6418 %} 6419 6420 instruct cmovIP_imm(cmpOpP cmp, flagsRegP pcc, iRegI dst, immI11 src) %{ 6421 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src))); 6422 ins_cost(140); 6423 format %{ "MOV$cmp $pcc,$src,$dst" %} 6424 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) ); 6425 ins_pipe(ialu_imm); 6426 %} 6427 6428 instruct cmovII_reg(cmpOp cmp, flagsReg icc, iRegI dst, iRegI src) %{ 6429 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); 6430 ins_cost(150); 6431 size(4); 6432 format %{ "MOV$cmp $icc,$src,$dst" %} 6433 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); 6434 ins_pipe(ialu_reg); 6435 %} 6436 6437 instruct cmovII_imm(cmpOp cmp, flagsReg icc, iRegI dst, immI11 src) %{ 6438 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); 6439 ins_cost(140); 6440 size(4); 6441 format %{ "MOV$cmp $icc,$src,$dst" %} 6442 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); 6443 ins_pipe(ialu_imm); 6444 %} 6445 6446 instruct cmovII_U_reg(cmpOpU cmp, flagsRegU icc, iRegI dst, iRegI src) %{ 6447 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); 6448 ins_cost(150); 6449 size(4); 6450 format %{ "MOV$cmp $icc,$src,$dst" %} 6451 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); 6452 ins_pipe(ialu_reg); 6453 %} 6454 6455 instruct cmovII_U_imm(cmpOpU cmp, flagsRegU icc, iRegI dst, immI11 src) %{ 6456 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); 6457 ins_cost(140); 6458 size(4); 6459 format %{ "MOV$cmp $icc,$src,$dst" %} 6460 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); 6461 ins_pipe(ialu_imm); 6462 %} 6463 6464 instruct cmovIF_reg(cmpOpF cmp, flagsRegF fcc, iRegI dst, iRegI src) %{ 6465 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src))); 6466 ins_cost(150); 6467 size(4); 6468 format %{ "MOV$cmp $fcc,$src,$dst" %} 6469 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); 6470 ins_pipe(ialu_reg); 6471 %} 6472 6473 instruct cmovIF_imm(cmpOpF cmp, flagsRegF fcc, iRegI dst, immI11 src) %{ 6474 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src))); 6475 ins_cost(140); 6476 size(4); 6477 format %{ "MOV$cmp $fcc,$src,$dst" %} 6478 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) ); 6479 ins_pipe(ialu_imm); 6480 %} 6481 6482 // Conditional move for RegN. Only cmov(reg,reg). 6483 instruct cmovNP_reg(cmpOpP cmp, flagsRegP pcc, iRegN dst, iRegN src) %{ 6484 match(Set dst (CMoveN (Binary cmp pcc) (Binary dst src))); 6485 ins_cost(150); 6486 format %{ "MOV$cmp $pcc,$src,$dst" %} 6487 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); 6488 ins_pipe(ialu_reg); 6489 %} 6490 6491 // This instruction also works with CmpN so we don't need cmovNN_reg. 6492 instruct cmovNI_reg(cmpOp cmp, flagsReg icc, iRegN dst, iRegN src) %{ 6493 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src))); 6494 ins_cost(150); 6495 size(4); 6496 format %{ "MOV$cmp $icc,$src,$dst" %} 6497 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); 6498 ins_pipe(ialu_reg); 6499 %} 6500 6501 instruct cmovNF_reg(cmpOpF cmp, flagsRegF fcc, iRegN dst, iRegN src) %{ 6502 match(Set dst (CMoveN (Binary cmp fcc) (Binary dst src))); 6503 ins_cost(150); 6504 size(4); 6505 format %{ "MOV$cmp $fcc,$src,$dst" %} 6506 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); 6507 ins_pipe(ialu_reg); 6508 %} 6509 6510 // Conditional move 6511 instruct cmovPP_reg(cmpOpP cmp, flagsRegP pcc, iRegP dst, iRegP src) %{ 6512 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src))); 6513 ins_cost(150); 6514 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %} 6515 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); 6516 ins_pipe(ialu_reg); 6517 %} 6518 6519 instruct cmovPP_imm(cmpOpP cmp, flagsRegP pcc, iRegP dst, immP0 src) %{ 6520 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src))); 6521 ins_cost(140); 6522 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %} 6523 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) ); 6524 ins_pipe(ialu_imm); 6525 %} 6526 6527 // This instruction also works with CmpN so we don't need cmovPN_reg. 6528 instruct cmovPI_reg(cmpOp cmp, flagsReg icc, iRegP dst, iRegP src) %{ 6529 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); 6530 ins_cost(150); 6531 6532 size(4); 6533 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %} 6534 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); 6535 ins_pipe(ialu_reg); 6536 %} 6537 6538 instruct cmovPI_imm(cmpOp cmp, flagsReg icc, iRegP dst, immP0 src) %{ 6539 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); 6540 ins_cost(140); 6541 6542 size(4); 6543 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %} 6544 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); 6545 ins_pipe(ialu_imm); 6546 %} 6547 6548 instruct cmovPF_reg(cmpOpF cmp, flagsRegF fcc, iRegP dst, iRegP src) %{ 6549 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src))); 6550 ins_cost(150); 6551 size(4); 6552 format %{ "MOV$cmp $fcc,$src,$dst" %} 6553 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); 6554 ins_pipe(ialu_imm); 6555 %} 6556 6557 instruct cmovPF_imm(cmpOpF cmp, flagsRegF fcc, iRegP dst, immP0 src) %{ 6558 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src))); 6559 ins_cost(140); 6560 size(4); 6561 format %{ "MOV$cmp $fcc,$src,$dst" %} 6562 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) ); 6563 ins_pipe(ialu_imm); 6564 %} 6565 6566 // Conditional move 6567 instruct cmovFP_reg(cmpOpP cmp, flagsRegP pcc, regF dst, regF src) %{ 6568 match(Set dst (CMoveF (Binary cmp pcc) (Binary dst src))); 6569 ins_cost(150); 6570 opcode(0x101); 6571 format %{ "FMOVD$cmp $pcc,$src,$dst" %} 6572 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) ); 6573 ins_pipe(int_conditional_float_move); 6574 %} 6575 6576 instruct cmovFI_reg(cmpOp cmp, flagsReg icc, regF dst, regF src) %{ 6577 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src))); 6578 ins_cost(150); 6579 6580 size(4); 6581 format %{ "FMOVS$cmp $icc,$src,$dst" %} 6582 opcode(0x101); 6583 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) ); 6584 ins_pipe(int_conditional_float_move); 6585 %} 6586 6587 // Conditional move, 6588 instruct cmovFF_reg(cmpOpF cmp, flagsRegF fcc, regF dst, regF src) %{ 6589 match(Set dst (CMoveF (Binary cmp fcc) (Binary dst src))); 6590 ins_cost(150); 6591 size(4); 6592 format %{ "FMOVF$cmp $fcc,$src,$dst" %} 6593 opcode(0x1); 6594 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) ); 6595 ins_pipe(int_conditional_double_move); 6596 %} 6597 6598 // Conditional move 6599 instruct cmovDP_reg(cmpOpP cmp, flagsRegP pcc, regD dst, regD src) %{ 6600 match(Set dst (CMoveD (Binary cmp pcc) (Binary dst src))); 6601 ins_cost(150); 6602 size(4); 6603 opcode(0x102); 6604 format %{ "FMOVD$cmp $pcc,$src,$dst" %} 6605 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) ); 6606 ins_pipe(int_conditional_double_move); 6607 %} 6608 6609 instruct cmovDI_reg(cmpOp cmp, flagsReg icc, regD dst, regD src) %{ 6610 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src))); 6611 ins_cost(150); 6612 6613 size(4); 6614 format %{ "FMOVD$cmp $icc,$src,$dst" %} 6615 opcode(0x102); 6616 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) ); 6617 ins_pipe(int_conditional_double_move); 6618 %} 6619 6620 // Conditional move, 6621 instruct cmovDF_reg(cmpOpF cmp, flagsRegF fcc, regD dst, regD src) %{ 6622 match(Set dst (CMoveD (Binary cmp fcc) (Binary dst src))); 6623 ins_cost(150); 6624 size(4); 6625 format %{ "FMOVD$cmp $fcc,$src,$dst" %} 6626 opcode(0x2); 6627 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) ); 6628 ins_pipe(int_conditional_double_move); 6629 %} 6630 6631 // Conditional move 6632 instruct cmovLP_reg(cmpOpP cmp, flagsRegP pcc, iRegL dst, iRegL src) %{ 6633 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src))); 6634 ins_cost(150); 6635 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %} 6636 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); 6637 ins_pipe(ialu_reg); 6638 %} 6639 6640 instruct cmovLP_imm(cmpOpP cmp, flagsRegP pcc, iRegL dst, immI11 src) %{ 6641 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src))); 6642 ins_cost(140); 6643 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %} 6644 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) ); 6645 ins_pipe(ialu_imm); 6646 %} 6647 6648 instruct cmovLI_reg(cmpOp cmp, flagsReg icc, iRegL dst, iRegL src) %{ 6649 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src))); 6650 ins_cost(150); 6651 6652 size(4); 6653 format %{ "MOV$cmp $icc,$src,$dst\t! long" %} 6654 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); 6655 ins_pipe(ialu_reg); 6656 %} 6657 6658 6659 instruct cmovLF_reg(cmpOpF cmp, flagsRegF fcc, iRegL dst, iRegL src) %{ 6660 match(Set dst (CMoveL (Binary cmp fcc) (Binary dst src))); 6661 ins_cost(150); 6662 6663 size(4); 6664 format %{ "MOV$cmp $fcc,$src,$dst\t! long" %} 6665 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); 6666 ins_pipe(ialu_reg); 6667 %} 6668 6669 6670 6671 //----------OS and Locking Instructions---------------------------------------- 6672 6673 // This name is KNOWN by the ADLC and cannot be changed. 6674 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type 6675 // for this guy. 6676 instruct tlsLoadP(g2RegP dst) %{ 6677 match(Set dst (ThreadLocal)); 6678 6679 size(0); 6680 ins_cost(0); 6681 format %{ "# TLS is in G2" %} 6682 ins_encode( /*empty encoding*/ ); 6683 ins_pipe(ialu_none); 6684 %} 6685 6686 instruct checkCastPP( iRegP dst ) %{ 6687 match(Set dst (CheckCastPP dst)); 6688 6689 size(0); 6690 format %{ "# checkcastPP of $dst" %} 6691 ins_encode( /*empty encoding*/ ); 6692 ins_pipe(empty); 6693 %} 6694 6695 6696 instruct castPP( iRegP dst ) %{ 6697 match(Set dst (CastPP dst)); 6698 format %{ "# castPP of $dst" %} 6699 ins_encode( /*empty encoding*/ ); 6700 ins_pipe(empty); 6701 %} 6702 6703 instruct castII( iRegI dst ) %{ 6704 match(Set dst (CastII dst)); 6705 format %{ "# castII of $dst" %} 6706 ins_encode( /*empty encoding*/ ); 6707 ins_cost(0); 6708 ins_pipe(empty); 6709 %} 6710 6711 //----------Arithmetic Instructions-------------------------------------------- 6712 // Addition Instructions 6713 // Register Addition 6714 instruct addI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 6715 match(Set dst (AddI src1 src2)); 6716 6717 size(4); 6718 format %{ "ADD $src1,$src2,$dst" %} 6719 ins_encode %{ 6720 __ add($src1$$Register, $src2$$Register, $dst$$Register); 6721 %} 6722 ins_pipe(ialu_reg_reg); 6723 %} 6724 6725 // Immediate Addition 6726 instruct addI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ 6727 match(Set dst (AddI src1 src2)); 6728 6729 size(4); 6730 format %{ "ADD $src1,$src2,$dst" %} 6731 opcode(Assembler::add_op3, Assembler::arith_op); 6732 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 6733 ins_pipe(ialu_reg_imm); 6734 %} 6735 6736 // Pointer Register Addition 6737 instruct addP_reg_reg(iRegP dst, iRegP src1, iRegX src2) %{ 6738 match(Set dst (AddP src1 src2)); 6739 6740 size(4); 6741 format %{ "ADD $src1,$src2,$dst" %} 6742 opcode(Assembler::add_op3, Assembler::arith_op); 6743 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 6744 ins_pipe(ialu_reg_reg); 6745 %} 6746 6747 // Pointer Immediate Addition 6748 instruct addP_reg_imm13(iRegP dst, iRegP src1, immX13 src2) %{ 6749 match(Set dst (AddP src1 src2)); 6750 6751 size(4); 6752 format %{ "ADD $src1,$src2,$dst" %} 6753 opcode(Assembler::add_op3, Assembler::arith_op); 6754 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 6755 ins_pipe(ialu_reg_imm); 6756 %} 6757 6758 // Long Addition 6759 instruct addL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 6760 match(Set dst (AddL src1 src2)); 6761 6762 size(4); 6763 format %{ "ADD $src1,$src2,$dst\t! long" %} 6764 opcode(Assembler::add_op3, Assembler::arith_op); 6765 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 6766 ins_pipe(ialu_reg_reg); 6767 %} 6768 6769 instruct addL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ 6770 match(Set dst (AddL src1 con)); 6771 6772 size(4); 6773 format %{ "ADD $src1,$con,$dst" %} 6774 opcode(Assembler::add_op3, Assembler::arith_op); 6775 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); 6776 ins_pipe(ialu_reg_imm); 6777 %} 6778 6779 //----------Conditional_store-------------------------------------------------- 6780 // Conditional-store of the updated heap-top. 6781 // Used during allocation of the shared heap. 6782 // Sets flags (EQ) on success. Implemented with a CASA on Sparc. 6783 6784 // LoadP-locked. Same as a regular pointer load when used with a compare-swap 6785 instruct loadPLocked(iRegP dst, memory mem) %{ 6786 match(Set dst (LoadPLocked mem)); 6787 ins_cost(MEMORY_REF_COST); 6788 6789 #ifndef _LP64 6790 size(4); 6791 format %{ "LDUW $mem,$dst\t! ptr" %} 6792 opcode(Assembler::lduw_op3, 0, REGP_OP); 6793 #else 6794 format %{ "LDX $mem,$dst\t! ptr" %} 6795 opcode(Assembler::ldx_op3, 0, REGP_OP); 6796 #endif 6797 ins_encode( form3_mem_reg( mem, dst ) ); 6798 ins_pipe(iload_mem); 6799 %} 6800 6801 // LoadL-locked. Same as a regular long load when used with a compare-swap 6802 instruct loadLLocked(iRegL dst, memory mem) %{ 6803 match(Set dst (LoadLLocked mem)); 6804 ins_cost(MEMORY_REF_COST); 6805 size(4); 6806 format %{ "LDX $mem,$dst\t! long" %} 6807 opcode(Assembler::ldx_op3); 6808 ins_encode(simple_form3_mem_reg( mem, dst ) ); 6809 ins_pipe(iload_mem); 6810 %} 6811 6812 instruct storePConditional( iRegP heap_top_ptr, iRegP oldval, g3RegP newval, flagsRegP pcc ) %{ 6813 match(Set pcc (StorePConditional heap_top_ptr (Binary oldval newval))); 6814 effect( KILL newval ); 6815 format %{ "CASA [$heap_top_ptr],$oldval,R_G3\t! If $oldval==[$heap_top_ptr] Then store R_G3 into [$heap_top_ptr], set R_G3=[$heap_top_ptr] in any case\n\t" 6816 "CMP R_G3,$oldval\t\t! See if we made progress" %} 6817 ins_encode( enc_cas(heap_top_ptr,oldval,newval) ); 6818 ins_pipe( long_memory_op ); 6819 %} 6820 6821 // Conditional-store of an int value. 6822 instruct storeIConditional( iRegP mem_ptr, iRegI oldval, g3RegI newval, flagsReg icc ) %{ 6823 match(Set icc (StoreIConditional mem_ptr (Binary oldval newval))); 6824 effect( KILL newval ); 6825 format %{ "CASA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t" 6826 "CMP $oldval,$newval\t\t! See if we made progress" %} 6827 ins_encode( enc_cas(mem_ptr,oldval,newval) ); 6828 ins_pipe( long_memory_op ); 6829 %} 6830 6831 // Conditional-store of a long value. 6832 instruct storeLConditional( iRegP mem_ptr, iRegL oldval, g3RegL newval, flagsRegL xcc ) %{ 6833 match(Set xcc (StoreLConditional mem_ptr (Binary oldval newval))); 6834 effect( KILL newval ); 6835 format %{ "CASXA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t" 6836 "CMP $oldval,$newval\t\t! See if we made progress" %} 6837 ins_encode( enc_cas(mem_ptr,oldval,newval) ); 6838 ins_pipe( long_memory_op ); 6839 %} 6840 6841 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them 6842 6843 instruct compareAndSwapL_bool(iRegP mem_ptr, iRegL oldval, iRegL newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ 6844 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval))); 6845 effect( USE mem_ptr, KILL ccr, KILL tmp1); 6846 format %{ 6847 "MOV $newval,O7\n\t" 6848 "CASXA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" 6849 "CMP $oldval,O7\t\t! See if we made progress\n\t" 6850 "MOV 1,$res\n\t" 6851 "MOVne xcc,R_G0,$res" 6852 %} 6853 ins_encode( enc_casx(mem_ptr, oldval, newval), 6854 enc_lflags_ne_to_boolean(res) ); 6855 ins_pipe( long_memory_op ); 6856 %} 6857 6858 6859 instruct compareAndSwapI_bool(iRegP mem_ptr, iRegI oldval, iRegI newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ 6860 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval))); 6861 effect( USE mem_ptr, KILL ccr, KILL tmp1); 6862 format %{ 6863 "MOV $newval,O7\n\t" 6864 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" 6865 "CMP $oldval,O7\t\t! See if we made progress\n\t" 6866 "MOV 1,$res\n\t" 6867 "MOVne icc,R_G0,$res" 6868 %} 6869 ins_encode( enc_casi(mem_ptr, oldval, newval), 6870 enc_iflags_ne_to_boolean(res) ); 6871 ins_pipe( long_memory_op ); 6872 %} 6873 6874 instruct compareAndSwapP_bool(iRegP mem_ptr, iRegP oldval, iRegP newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ 6875 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval))); 6876 effect( USE mem_ptr, KILL ccr, KILL tmp1); 6877 format %{ 6878 "MOV $newval,O7\n\t" 6879 "CASA_PTR [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" 6880 "CMP $oldval,O7\t\t! See if we made progress\n\t" 6881 "MOV 1,$res\n\t" 6882 "MOVne xcc,R_G0,$res" 6883 %} 6884 #ifdef _LP64 6885 ins_encode( enc_casx(mem_ptr, oldval, newval), 6886 enc_lflags_ne_to_boolean(res) ); 6887 #else 6888 ins_encode( enc_casi(mem_ptr, oldval, newval), 6889 enc_iflags_ne_to_boolean(res) ); 6890 #endif 6891 ins_pipe( long_memory_op ); 6892 %} 6893 6894 instruct compareAndSwapN_bool(iRegP mem_ptr, iRegN oldval, iRegN newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ 6895 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval))); 6896 effect( USE mem_ptr, KILL ccr, KILL tmp1); 6897 format %{ 6898 "MOV $newval,O7\n\t" 6899 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" 6900 "CMP $oldval,O7\t\t! See if we made progress\n\t" 6901 "MOV 1,$res\n\t" 6902 "MOVne icc,R_G0,$res" 6903 %} 6904 ins_encode( enc_casi(mem_ptr, oldval, newval), 6905 enc_iflags_ne_to_boolean(res) ); 6906 ins_pipe( long_memory_op ); 6907 %} 6908 6909 //--------------------- 6910 // Subtraction Instructions 6911 // Register Subtraction 6912 instruct subI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 6913 match(Set dst (SubI src1 src2)); 6914 6915 size(4); 6916 format %{ "SUB $src1,$src2,$dst" %} 6917 opcode(Assembler::sub_op3, Assembler::arith_op); 6918 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 6919 ins_pipe(ialu_reg_reg); 6920 %} 6921 6922 // Immediate Subtraction 6923 instruct subI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ 6924 match(Set dst (SubI src1 src2)); 6925 6926 size(4); 6927 format %{ "SUB $src1,$src2,$dst" %} 6928 opcode(Assembler::sub_op3, Assembler::arith_op); 6929 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 6930 ins_pipe(ialu_reg_imm); 6931 %} 6932 6933 instruct subI_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{ 6934 match(Set dst (SubI zero src2)); 6935 6936 size(4); 6937 format %{ "NEG $src2,$dst" %} 6938 opcode(Assembler::sub_op3, Assembler::arith_op); 6939 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) ); 6940 ins_pipe(ialu_zero_reg); 6941 %} 6942 6943 // Long subtraction 6944 instruct subL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 6945 match(Set dst (SubL src1 src2)); 6946 6947 size(4); 6948 format %{ "SUB $src1,$src2,$dst\t! long" %} 6949 opcode(Assembler::sub_op3, Assembler::arith_op); 6950 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 6951 ins_pipe(ialu_reg_reg); 6952 %} 6953 6954 // Immediate Subtraction 6955 instruct subL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ 6956 match(Set dst (SubL src1 con)); 6957 6958 size(4); 6959 format %{ "SUB $src1,$con,$dst\t! long" %} 6960 opcode(Assembler::sub_op3, Assembler::arith_op); 6961 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); 6962 ins_pipe(ialu_reg_imm); 6963 %} 6964 6965 // Long negation 6966 instruct negL_reg_reg(iRegL dst, immL0 zero, iRegL src2) %{ 6967 match(Set dst (SubL zero src2)); 6968 6969 size(4); 6970 format %{ "NEG $src2,$dst\t! long" %} 6971 opcode(Assembler::sub_op3, Assembler::arith_op); 6972 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) ); 6973 ins_pipe(ialu_zero_reg); 6974 %} 6975 6976 // Multiplication Instructions 6977 // Integer Multiplication 6978 // Register Multiplication 6979 instruct mulI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 6980 match(Set dst (MulI src1 src2)); 6981 6982 size(4); 6983 format %{ "MULX $src1,$src2,$dst" %} 6984 opcode(Assembler::mulx_op3, Assembler::arith_op); 6985 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 6986 ins_pipe(imul_reg_reg); 6987 %} 6988 6989 // Immediate Multiplication 6990 instruct mulI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ 6991 match(Set dst (MulI src1 src2)); 6992 6993 size(4); 6994 format %{ "MULX $src1,$src2,$dst" %} 6995 opcode(Assembler::mulx_op3, Assembler::arith_op); 6996 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 6997 ins_pipe(imul_reg_imm); 6998 %} 6999 7000 instruct mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 7001 match(Set dst (MulL src1 src2)); 7002 ins_cost(DEFAULT_COST * 5); 7003 size(4); 7004 format %{ "MULX $src1,$src2,$dst\t! long" %} 7005 opcode(Assembler::mulx_op3, Assembler::arith_op); 7006 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7007 ins_pipe(mulL_reg_reg); 7008 %} 7009 7010 // Immediate Multiplication 7011 instruct mulL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{ 7012 match(Set dst (MulL src1 src2)); 7013 ins_cost(DEFAULT_COST * 5); 7014 size(4); 7015 format %{ "MULX $src1,$src2,$dst" %} 7016 opcode(Assembler::mulx_op3, Assembler::arith_op); 7017 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7018 ins_pipe(mulL_reg_imm); 7019 %} 7020 7021 // Integer Division 7022 // Register Division 7023 instruct divI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2) %{ 7024 match(Set dst (DivI src1 src2)); 7025 ins_cost((2+71)*DEFAULT_COST); 7026 7027 format %{ "SRA $src2,0,$src2\n\t" 7028 "SRA $src1,0,$src1\n\t" 7029 "SDIVX $src1,$src2,$dst" %} 7030 ins_encode( idiv_reg( src1, src2, dst ) ); 7031 ins_pipe(sdiv_reg_reg); 7032 %} 7033 7034 // Immediate Division 7035 instruct divI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2) %{ 7036 match(Set dst (DivI src1 src2)); 7037 ins_cost((2+71)*DEFAULT_COST); 7038 7039 format %{ "SRA $src1,0,$src1\n\t" 7040 "SDIVX $src1,$src2,$dst" %} 7041 ins_encode( idiv_imm( src1, src2, dst ) ); 7042 ins_pipe(sdiv_reg_imm); 7043 %} 7044 7045 //----------Div-By-10-Expansion------------------------------------------------ 7046 // Extract hi bits of a 32x32->64 bit multiply. 7047 // Expand rule only, not matched 7048 instruct mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2 ) %{ 7049 effect( DEF dst, USE src1, USE src2 ); 7050 format %{ "MULX $src1,$src2,$dst\t! Used in div-by-10\n\t" 7051 "SRLX $dst,#32,$dst\t\t! Extract only hi word of result" %} 7052 ins_encode( enc_mul_hi(dst,src1,src2)); 7053 ins_pipe(sdiv_reg_reg); 7054 %} 7055 7056 // Magic constant, reciprocal of 10 7057 instruct loadConI_x66666667(iRegIsafe dst) %{ 7058 effect( DEF dst ); 7059 7060 size(8); 7061 format %{ "SET 0x66666667,$dst\t! Used in div-by-10" %} 7062 ins_encode( Set32(0x66666667, dst) ); 7063 ins_pipe(ialu_hi_lo_reg); 7064 %} 7065 7066 // Register Shift Right Arithmetic Long by 32-63 7067 instruct sra_31( iRegI dst, iRegI src ) %{ 7068 effect( DEF dst, USE src ); 7069 format %{ "SRA $src,31,$dst\t! Used in div-by-10" %} 7070 ins_encode( form3_rs1_rd_copysign_hi(src,dst) ); 7071 ins_pipe(ialu_reg_reg); 7072 %} 7073 7074 // Arithmetic Shift Right by 8-bit immediate 7075 instruct sra_reg_2( iRegI dst, iRegI src ) %{ 7076 effect( DEF dst, USE src ); 7077 format %{ "SRA $src,2,$dst\t! Used in div-by-10" %} 7078 opcode(Assembler::sra_op3, Assembler::arith_op); 7079 ins_encode( form3_rs1_simm13_rd( src, 0x2, dst ) ); 7080 ins_pipe(ialu_reg_imm); 7081 %} 7082 7083 // Integer DIV with 10 7084 instruct divI_10( iRegI dst, iRegIsafe src, immI10 div ) %{ 7085 match(Set dst (DivI src div)); 7086 ins_cost((6+6)*DEFAULT_COST); 7087 expand %{ 7088 iRegIsafe tmp1; // Killed temps; 7089 iRegIsafe tmp2; // Killed temps; 7090 iRegI tmp3; // Killed temps; 7091 iRegI tmp4; // Killed temps; 7092 loadConI_x66666667( tmp1 ); // SET 0x66666667 -> tmp1 7093 mul_hi( tmp2, src, tmp1 ); // MUL hibits(src * tmp1) -> tmp2 7094 sra_31( tmp3, src ); // SRA src,31 -> tmp3 7095 sra_reg_2( tmp4, tmp2 ); // SRA tmp2,2 -> tmp4 7096 subI_reg_reg( dst,tmp4,tmp3); // SUB tmp4 - tmp3 -> dst 7097 %} 7098 %} 7099 7100 // Register Long Division 7101 instruct divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 7102 match(Set dst (DivL src1 src2)); 7103 ins_cost(DEFAULT_COST*71); 7104 size(4); 7105 format %{ "SDIVX $src1,$src2,$dst\t! long" %} 7106 opcode(Assembler::sdivx_op3, Assembler::arith_op); 7107 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7108 ins_pipe(divL_reg_reg); 7109 %} 7110 7111 // Register Long Division 7112 instruct divL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{ 7113 match(Set dst (DivL src1 src2)); 7114 ins_cost(DEFAULT_COST*71); 7115 size(4); 7116 format %{ "SDIVX $src1,$src2,$dst\t! long" %} 7117 opcode(Assembler::sdivx_op3, Assembler::arith_op); 7118 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7119 ins_pipe(divL_reg_imm); 7120 %} 7121 7122 // Integer Remainder 7123 // Register Remainder 7124 instruct modI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2, o7RegP temp, flagsReg ccr ) %{ 7125 match(Set dst (ModI src1 src2)); 7126 effect( KILL ccr, KILL temp); 7127 7128 format %{ "SREM $src1,$src2,$dst" %} 7129 ins_encode( irem_reg(src1, src2, dst, temp) ); 7130 ins_pipe(sdiv_reg_reg); 7131 %} 7132 7133 // Immediate Remainder 7134 instruct modI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2, o7RegP temp, flagsReg ccr ) %{ 7135 match(Set dst (ModI src1 src2)); 7136 effect( KILL ccr, KILL temp); 7137 7138 format %{ "SREM $src1,$src2,$dst" %} 7139 ins_encode( irem_imm(src1, src2, dst, temp) ); 7140 ins_pipe(sdiv_reg_imm); 7141 %} 7142 7143 // Register Long Remainder 7144 instruct divL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{ 7145 effect(DEF dst, USE src1, USE src2); 7146 size(4); 7147 format %{ "SDIVX $src1,$src2,$dst\t! long" %} 7148 opcode(Assembler::sdivx_op3, Assembler::arith_op); 7149 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7150 ins_pipe(divL_reg_reg); 7151 %} 7152 7153 // Register Long Division 7154 instruct divL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{ 7155 effect(DEF dst, USE src1, USE src2); 7156 size(4); 7157 format %{ "SDIVX $src1,$src2,$dst\t! long" %} 7158 opcode(Assembler::sdivx_op3, Assembler::arith_op); 7159 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7160 ins_pipe(divL_reg_imm); 7161 %} 7162 7163 instruct mulL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{ 7164 effect(DEF dst, USE src1, USE src2); 7165 size(4); 7166 format %{ "MULX $src1,$src2,$dst\t! long" %} 7167 opcode(Assembler::mulx_op3, Assembler::arith_op); 7168 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7169 ins_pipe(mulL_reg_reg); 7170 %} 7171 7172 // Immediate Multiplication 7173 instruct mulL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{ 7174 effect(DEF dst, USE src1, USE src2); 7175 size(4); 7176 format %{ "MULX $src1,$src2,$dst" %} 7177 opcode(Assembler::mulx_op3, Assembler::arith_op); 7178 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7179 ins_pipe(mulL_reg_imm); 7180 %} 7181 7182 instruct subL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{ 7183 effect(DEF dst, USE src1, USE src2); 7184 size(4); 7185 format %{ "SUB $src1,$src2,$dst\t! long" %} 7186 opcode(Assembler::sub_op3, Assembler::arith_op); 7187 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7188 ins_pipe(ialu_reg_reg); 7189 %} 7190 7191 instruct subL_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{ 7192 effect(DEF dst, USE src1, USE src2); 7193 size(4); 7194 format %{ "SUB $src1,$src2,$dst\t! long" %} 7195 opcode(Assembler::sub_op3, Assembler::arith_op); 7196 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7197 ins_pipe(ialu_reg_reg); 7198 %} 7199 7200 // Register Long Remainder 7201 instruct modL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 7202 match(Set dst (ModL src1 src2)); 7203 ins_cost(DEFAULT_COST*(71 + 6 + 1)); 7204 expand %{ 7205 iRegL tmp1; 7206 iRegL tmp2; 7207 divL_reg_reg_1(tmp1, src1, src2); 7208 mulL_reg_reg_1(tmp2, tmp1, src2); 7209 subL_reg_reg_1(dst, src1, tmp2); 7210 %} 7211 %} 7212 7213 // Register Long Remainder 7214 instruct modL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{ 7215 match(Set dst (ModL src1 src2)); 7216 ins_cost(DEFAULT_COST*(71 + 6 + 1)); 7217 expand %{ 7218 iRegL tmp1; 7219 iRegL tmp2; 7220 divL_reg_imm13_1(tmp1, src1, src2); 7221 mulL_reg_imm13_1(tmp2, tmp1, src2); 7222 subL_reg_reg_2 (dst, src1, tmp2); 7223 %} 7224 %} 7225 7226 // Integer Shift Instructions 7227 // Register Shift Left 7228 instruct shlI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 7229 match(Set dst (LShiftI src1 src2)); 7230 7231 size(4); 7232 format %{ "SLL $src1,$src2,$dst" %} 7233 opcode(Assembler::sll_op3, Assembler::arith_op); 7234 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7235 ins_pipe(ialu_reg_reg); 7236 %} 7237 7238 // Register Shift Left Immediate 7239 instruct shlI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{ 7240 match(Set dst (LShiftI src1 src2)); 7241 7242 size(4); 7243 format %{ "SLL $src1,$src2,$dst" %} 7244 opcode(Assembler::sll_op3, Assembler::arith_op); 7245 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); 7246 ins_pipe(ialu_reg_imm); 7247 %} 7248 7249 // Register Shift Left 7250 instruct shlL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{ 7251 match(Set dst (LShiftL src1 src2)); 7252 7253 size(4); 7254 format %{ "SLLX $src1,$src2,$dst" %} 7255 opcode(Assembler::sllx_op3, Assembler::arith_op); 7256 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) ); 7257 ins_pipe(ialu_reg_reg); 7258 %} 7259 7260 // Register Shift Left Immediate 7261 instruct shlL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{ 7262 match(Set dst (LShiftL src1 src2)); 7263 7264 size(4); 7265 format %{ "SLLX $src1,$src2,$dst" %} 7266 opcode(Assembler::sllx_op3, Assembler::arith_op); 7267 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); 7268 ins_pipe(ialu_reg_imm); 7269 %} 7270 7271 // Register Arithmetic Shift Right 7272 instruct sarI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 7273 match(Set dst (RShiftI src1 src2)); 7274 size(4); 7275 format %{ "SRA $src1,$src2,$dst" %} 7276 opcode(Assembler::sra_op3, Assembler::arith_op); 7277 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7278 ins_pipe(ialu_reg_reg); 7279 %} 7280 7281 // Register Arithmetic Shift Right Immediate 7282 instruct sarI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{ 7283 match(Set dst (RShiftI src1 src2)); 7284 7285 size(4); 7286 format %{ "SRA $src1,$src2,$dst" %} 7287 opcode(Assembler::sra_op3, Assembler::arith_op); 7288 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); 7289 ins_pipe(ialu_reg_imm); 7290 %} 7291 7292 // Register Shift Right Arithmatic Long 7293 instruct sarL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{ 7294 match(Set dst (RShiftL src1 src2)); 7295 7296 size(4); 7297 format %{ "SRAX $src1,$src2,$dst" %} 7298 opcode(Assembler::srax_op3, Assembler::arith_op); 7299 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) ); 7300 ins_pipe(ialu_reg_reg); 7301 %} 7302 7303 // Register Shift Left Immediate 7304 instruct sarL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{ 7305 match(Set dst (RShiftL src1 src2)); 7306 7307 size(4); 7308 format %{ "SRAX $src1,$src2,$dst" %} 7309 opcode(Assembler::srax_op3, Assembler::arith_op); 7310 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); 7311 ins_pipe(ialu_reg_imm); 7312 %} 7313 7314 // Register Shift Right 7315 instruct shrI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 7316 match(Set dst (URShiftI src1 src2)); 7317 7318 size(4); 7319 format %{ "SRL $src1,$src2,$dst" %} 7320 opcode(Assembler::srl_op3, Assembler::arith_op); 7321 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7322 ins_pipe(ialu_reg_reg); 7323 %} 7324 7325 // Register Shift Right Immediate 7326 instruct shrI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{ 7327 match(Set dst (URShiftI src1 src2)); 7328 7329 size(4); 7330 format %{ "SRL $src1,$src2,$dst" %} 7331 opcode(Assembler::srl_op3, Assembler::arith_op); 7332 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); 7333 ins_pipe(ialu_reg_imm); 7334 %} 7335 7336 // Register Shift Right 7337 instruct shrL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{ 7338 match(Set dst (URShiftL src1 src2)); 7339 7340 size(4); 7341 format %{ "SRLX $src1,$src2,$dst" %} 7342 opcode(Assembler::srlx_op3, Assembler::arith_op); 7343 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) ); 7344 ins_pipe(ialu_reg_reg); 7345 %} 7346 7347 // Register Shift Right Immediate 7348 instruct shrL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{ 7349 match(Set dst (URShiftL src1 src2)); 7350 7351 size(4); 7352 format %{ "SRLX $src1,$src2,$dst" %} 7353 opcode(Assembler::srlx_op3, Assembler::arith_op); 7354 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); 7355 ins_pipe(ialu_reg_imm); 7356 %} 7357 7358 // Register Shift Right Immediate with a CastP2X 7359 #ifdef _LP64 7360 instruct shrP_reg_imm6(iRegL dst, iRegP src1, immU6 src2) %{ 7361 match(Set dst (URShiftL (CastP2X src1) src2)); 7362 size(4); 7363 format %{ "SRLX $src1,$src2,$dst\t! Cast ptr $src1 to long and shift" %} 7364 opcode(Assembler::srlx_op3, Assembler::arith_op); 7365 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); 7366 ins_pipe(ialu_reg_imm); 7367 %} 7368 #else 7369 instruct shrP_reg_imm5(iRegI dst, iRegP src1, immU5 src2) %{ 7370 match(Set dst (URShiftI (CastP2X src1) src2)); 7371 size(4); 7372 format %{ "SRL $src1,$src2,$dst\t! Cast ptr $src1 to int and shift" %} 7373 opcode(Assembler::srl_op3, Assembler::arith_op); 7374 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); 7375 ins_pipe(ialu_reg_imm); 7376 %} 7377 #endif 7378 7379 7380 //----------Floating Point Arithmetic Instructions----------------------------- 7381 7382 // Add float single precision 7383 instruct addF_reg_reg(regF dst, regF src1, regF src2) %{ 7384 match(Set dst (AddF src1 src2)); 7385 7386 size(4); 7387 format %{ "FADDS $src1,$src2,$dst" %} 7388 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fadds_opf); 7389 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); 7390 ins_pipe(faddF_reg_reg); 7391 %} 7392 7393 // Add float double precision 7394 instruct addD_reg_reg(regD dst, regD src1, regD src2) %{ 7395 match(Set dst (AddD src1 src2)); 7396 7397 size(4); 7398 format %{ "FADDD $src1,$src2,$dst" %} 7399 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf); 7400 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); 7401 ins_pipe(faddD_reg_reg); 7402 %} 7403 7404 // Sub float single precision 7405 instruct subF_reg_reg(regF dst, regF src1, regF src2) %{ 7406 match(Set dst (SubF src1 src2)); 7407 7408 size(4); 7409 format %{ "FSUBS $src1,$src2,$dst" %} 7410 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubs_opf); 7411 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); 7412 ins_pipe(faddF_reg_reg); 7413 %} 7414 7415 // Sub float double precision 7416 instruct subD_reg_reg(regD dst, regD src1, regD src2) %{ 7417 match(Set dst (SubD src1 src2)); 7418 7419 size(4); 7420 format %{ "FSUBD $src1,$src2,$dst" %} 7421 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf); 7422 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); 7423 ins_pipe(faddD_reg_reg); 7424 %} 7425 7426 // Mul float single precision 7427 instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{ 7428 match(Set dst (MulF src1 src2)); 7429 7430 size(4); 7431 format %{ "FMULS $src1,$src2,$dst" %} 7432 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuls_opf); 7433 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); 7434 ins_pipe(fmulF_reg_reg); 7435 %} 7436 7437 // Mul float double precision 7438 instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{ 7439 match(Set dst (MulD src1 src2)); 7440 7441 size(4); 7442 format %{ "FMULD $src1,$src2,$dst" %} 7443 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf); 7444 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); 7445 ins_pipe(fmulD_reg_reg); 7446 %} 7447 7448 // Div float single precision 7449 instruct divF_reg_reg(regF dst, regF src1, regF src2) %{ 7450 match(Set dst (DivF src1 src2)); 7451 7452 size(4); 7453 format %{ "FDIVS $src1,$src2,$dst" %} 7454 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivs_opf); 7455 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); 7456 ins_pipe(fdivF_reg_reg); 7457 %} 7458 7459 // Div float double precision 7460 instruct divD_reg_reg(regD dst, regD src1, regD src2) %{ 7461 match(Set dst (DivD src1 src2)); 7462 7463 size(4); 7464 format %{ "FDIVD $src1,$src2,$dst" %} 7465 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivd_opf); 7466 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); 7467 ins_pipe(fdivD_reg_reg); 7468 %} 7469 7470 // Absolute float double precision 7471 instruct absD_reg(regD dst, regD src) %{ 7472 match(Set dst (AbsD src)); 7473 7474 format %{ "FABSd $src,$dst" %} 7475 ins_encode(fabsd(dst, src)); 7476 ins_pipe(faddD_reg); 7477 %} 7478 7479 // Absolute float single precision 7480 instruct absF_reg(regF dst, regF src) %{ 7481 match(Set dst (AbsF src)); 7482 7483 format %{ "FABSs $src,$dst" %} 7484 ins_encode(fabss(dst, src)); 7485 ins_pipe(faddF_reg); 7486 %} 7487 7488 instruct negF_reg(regF dst, regF src) %{ 7489 match(Set dst (NegF src)); 7490 7491 size(4); 7492 format %{ "FNEGs $src,$dst" %} 7493 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fnegs_opf); 7494 ins_encode(form3_opf_rs2F_rdF(src, dst)); 7495 ins_pipe(faddF_reg); 7496 %} 7497 7498 instruct negD_reg(regD dst, regD src) %{ 7499 match(Set dst (NegD src)); 7500 7501 format %{ "FNEGd $src,$dst" %} 7502 ins_encode(fnegd(dst, src)); 7503 ins_pipe(faddD_reg); 7504 %} 7505 7506 // Sqrt float double precision 7507 instruct sqrtF_reg_reg(regF dst, regF src) %{ 7508 match(Set dst (ConvD2F (SqrtD (ConvF2D src)))); 7509 7510 size(4); 7511 format %{ "FSQRTS $src,$dst" %} 7512 ins_encode(fsqrts(dst, src)); 7513 ins_pipe(fdivF_reg_reg); 7514 %} 7515 7516 // Sqrt float double precision 7517 instruct sqrtD_reg_reg(regD dst, regD src) %{ 7518 match(Set dst (SqrtD src)); 7519 7520 size(4); 7521 format %{ "FSQRTD $src,$dst" %} 7522 ins_encode(fsqrtd(dst, src)); 7523 ins_pipe(fdivD_reg_reg); 7524 %} 7525 7526 //----------Logical Instructions----------------------------------------------- 7527 // And Instructions 7528 // Register And 7529 instruct andI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 7530 match(Set dst (AndI src1 src2)); 7531 7532 size(4); 7533 format %{ "AND $src1,$src2,$dst" %} 7534 opcode(Assembler::and_op3, Assembler::arith_op); 7535 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7536 ins_pipe(ialu_reg_reg); 7537 %} 7538 7539 // Immediate And 7540 instruct andI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ 7541 match(Set dst (AndI src1 src2)); 7542 7543 size(4); 7544 format %{ "AND $src1,$src2,$dst" %} 7545 opcode(Assembler::and_op3, Assembler::arith_op); 7546 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7547 ins_pipe(ialu_reg_imm); 7548 %} 7549 7550 // Register And Long 7551 instruct andL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 7552 match(Set dst (AndL src1 src2)); 7553 7554 ins_cost(DEFAULT_COST); 7555 size(4); 7556 format %{ "AND $src1,$src2,$dst\t! long" %} 7557 opcode(Assembler::and_op3, Assembler::arith_op); 7558 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7559 ins_pipe(ialu_reg_reg); 7560 %} 7561 7562 instruct andL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ 7563 match(Set dst (AndL src1 con)); 7564 7565 ins_cost(DEFAULT_COST); 7566 size(4); 7567 format %{ "AND $src1,$con,$dst\t! long" %} 7568 opcode(Assembler::and_op3, Assembler::arith_op); 7569 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); 7570 ins_pipe(ialu_reg_imm); 7571 %} 7572 7573 // Or Instructions 7574 // Register Or 7575 instruct orI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 7576 match(Set dst (OrI src1 src2)); 7577 7578 size(4); 7579 format %{ "OR $src1,$src2,$dst" %} 7580 opcode(Assembler::or_op3, Assembler::arith_op); 7581 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7582 ins_pipe(ialu_reg_reg); 7583 %} 7584 7585 // Immediate Or 7586 instruct orI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ 7587 match(Set dst (OrI src1 src2)); 7588 7589 size(4); 7590 format %{ "OR $src1,$src2,$dst" %} 7591 opcode(Assembler::or_op3, Assembler::arith_op); 7592 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7593 ins_pipe(ialu_reg_imm); 7594 %} 7595 7596 // Register Or Long 7597 instruct orL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 7598 match(Set dst (OrL src1 src2)); 7599 7600 ins_cost(DEFAULT_COST); 7601 size(4); 7602 format %{ "OR $src1,$src2,$dst\t! long" %} 7603 opcode(Assembler::or_op3, Assembler::arith_op); 7604 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7605 ins_pipe(ialu_reg_reg); 7606 %} 7607 7608 instruct orL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ 7609 match(Set dst (OrL src1 con)); 7610 ins_cost(DEFAULT_COST*2); 7611 7612 ins_cost(DEFAULT_COST); 7613 size(4); 7614 format %{ "OR $src1,$con,$dst\t! long" %} 7615 opcode(Assembler::or_op3, Assembler::arith_op); 7616 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); 7617 ins_pipe(ialu_reg_imm); 7618 %} 7619 7620 #ifndef _LP64 7621 7622 // Use sp_ptr_RegP to match G2 (TLS register) without spilling. 7623 instruct orI_reg_castP2X(iRegI dst, iRegI src1, sp_ptr_RegP src2) %{ 7624 match(Set dst (OrI src1 (CastP2X src2))); 7625 7626 size(4); 7627 format %{ "OR $src1,$src2,$dst" %} 7628 opcode(Assembler::or_op3, Assembler::arith_op); 7629 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7630 ins_pipe(ialu_reg_reg); 7631 %} 7632 7633 #else 7634 7635 instruct orL_reg_castP2X(iRegL dst, iRegL src1, sp_ptr_RegP src2) %{ 7636 match(Set dst (OrL src1 (CastP2X src2))); 7637 7638 ins_cost(DEFAULT_COST); 7639 size(4); 7640 format %{ "OR $src1,$src2,$dst\t! long" %} 7641 opcode(Assembler::or_op3, Assembler::arith_op); 7642 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7643 ins_pipe(ialu_reg_reg); 7644 %} 7645 7646 #endif 7647 7648 // Xor Instructions 7649 // Register Xor 7650 instruct xorI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 7651 match(Set dst (XorI src1 src2)); 7652 7653 size(4); 7654 format %{ "XOR $src1,$src2,$dst" %} 7655 opcode(Assembler::xor_op3, Assembler::arith_op); 7656 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7657 ins_pipe(ialu_reg_reg); 7658 %} 7659 7660 // Immediate Xor 7661 instruct xorI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ 7662 match(Set dst (XorI src1 src2)); 7663 7664 size(4); 7665 format %{ "XOR $src1,$src2,$dst" %} 7666 opcode(Assembler::xor_op3, Assembler::arith_op); 7667 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7668 ins_pipe(ialu_reg_imm); 7669 %} 7670 7671 // Register Xor Long 7672 instruct xorL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 7673 match(Set dst (XorL src1 src2)); 7674 7675 ins_cost(DEFAULT_COST); 7676 size(4); 7677 format %{ "XOR $src1,$src2,$dst\t! long" %} 7678 opcode(Assembler::xor_op3, Assembler::arith_op); 7679 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7680 ins_pipe(ialu_reg_reg); 7681 %} 7682 7683 instruct xorL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ 7684 match(Set dst (XorL src1 con)); 7685 7686 ins_cost(DEFAULT_COST); 7687 size(4); 7688 format %{ "XOR $src1,$con,$dst\t! long" %} 7689 opcode(Assembler::xor_op3, Assembler::arith_op); 7690 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); 7691 ins_pipe(ialu_reg_imm); 7692 %} 7693 7694 //----------Convert to Boolean------------------------------------------------- 7695 // Nice hack for 32-bit tests but doesn't work for 7696 // 64-bit pointers. 7697 instruct convI2B( iRegI dst, iRegI src, flagsReg ccr ) %{ 7698 match(Set dst (Conv2B src)); 7699 effect( KILL ccr ); 7700 ins_cost(DEFAULT_COST*2); 7701 format %{ "CMP R_G0,$src\n\t" 7702 "ADDX R_G0,0,$dst" %} 7703 ins_encode( enc_to_bool( src, dst ) ); 7704 ins_pipe(ialu_reg_ialu); 7705 %} 7706 7707 #ifndef _LP64 7708 instruct convP2B( iRegI dst, iRegP src, flagsReg ccr ) %{ 7709 match(Set dst (Conv2B src)); 7710 effect( KILL ccr ); 7711 ins_cost(DEFAULT_COST*2); 7712 format %{ "CMP R_G0,$src\n\t" 7713 "ADDX R_G0,0,$dst" %} 7714 ins_encode( enc_to_bool( src, dst ) ); 7715 ins_pipe(ialu_reg_ialu); 7716 %} 7717 #else 7718 instruct convP2B( iRegI dst, iRegP src ) %{ 7719 match(Set dst (Conv2B src)); 7720 ins_cost(DEFAULT_COST*2); 7721 format %{ "MOV $src,$dst\n\t" 7722 "MOVRNZ $src,1,$dst" %} 7723 ins_encode( form3_g0_rs2_rd_move( src, dst ), enc_convP2B( dst, src ) ); 7724 ins_pipe(ialu_clr_and_mover); 7725 %} 7726 #endif 7727 7728 instruct cmpLTMask_reg_reg( iRegI dst, iRegI p, iRegI q, flagsReg ccr ) %{ 7729 match(Set dst (CmpLTMask p q)); 7730 effect( KILL ccr ); 7731 ins_cost(DEFAULT_COST*4); 7732 format %{ "CMP $p,$q\n\t" 7733 "MOV #0,$dst\n\t" 7734 "BLT,a .+8\n\t" 7735 "MOV #-1,$dst" %} 7736 ins_encode( enc_ltmask(p,q,dst) ); 7737 ins_pipe(ialu_reg_reg_ialu); 7738 %} 7739 7740 instruct cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp, flagsReg ccr ) %{ 7741 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q))); 7742 effect(KILL ccr, TEMP tmp); 7743 ins_cost(DEFAULT_COST*3); 7744 7745 format %{ "SUBcc $p,$q,$p\t! p' = p-q\n\t" 7746 "ADD $p,$y,$tmp\t! g3=p-q+y\n\t" 7747 "MOVl $tmp,$p\t! p' < 0 ? p'+y : p'" %} 7748 ins_encode( enc_cadd_cmpLTMask(p, q, y, tmp) ); 7749 ins_pipe( cadd_cmpltmask ); 7750 %} 7751 7752 instruct cadd_cmpLTMask2( iRegI p, iRegI q, iRegI y, iRegI tmp, flagsReg ccr ) %{ 7753 match(Set p (AddI (SubI p q) (AndI (CmpLTMask p q) y))); 7754 effect( KILL ccr, TEMP tmp); 7755 ins_cost(DEFAULT_COST*3); 7756 7757 format %{ "SUBcc $p,$q,$p\t! p' = p-q\n\t" 7758 "ADD $p,$y,$tmp\t! g3=p-q+y\n\t" 7759 "MOVl $tmp,$p\t! p' < 0 ? p'+y : p'" %} 7760 ins_encode( enc_cadd_cmpLTMask(p, q, y, tmp) ); 7761 ins_pipe( cadd_cmpltmask ); 7762 %} 7763 7764 //----------Arithmetic Conversion Instructions--------------------------------- 7765 // The conversions operations are all Alpha sorted. Please keep it that way! 7766 7767 instruct convD2F_reg(regF dst, regD src) %{ 7768 match(Set dst (ConvD2F src)); 7769 size(4); 7770 format %{ "FDTOS $src,$dst" %} 7771 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdtos_opf); 7772 ins_encode(form3_opf_rs2D_rdF(src, dst)); 7773 ins_pipe(fcvtD2F); 7774 %} 7775 7776 7777 // Convert a double to an int in a float register. 7778 // If the double is a NAN, stuff a zero in instead. 7779 instruct convD2I_helper(regF dst, regD src, flagsRegF0 fcc0) %{ 7780 effect(DEF dst, USE src, KILL fcc0); 7781 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t" 7782 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" 7783 "FDTOI $src,$dst\t! convert in delay slot\n\t" 7784 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t" 7785 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n" 7786 "skip:" %} 7787 ins_encode(form_d2i_helper(src,dst)); 7788 ins_pipe(fcvtD2I); 7789 %} 7790 7791 instruct convD2I_reg(stackSlotI dst, regD src) %{ 7792 match(Set dst (ConvD2I src)); 7793 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); 7794 expand %{ 7795 regF tmp; 7796 convD2I_helper(tmp, src); 7797 regF_to_stkI(dst, tmp); 7798 %} 7799 %} 7800 7801 // Convert a double to a long in a double register. 7802 // If the double is a NAN, stuff a zero in instead. 7803 instruct convD2L_helper(regD dst, regD src, flagsRegF0 fcc0) %{ 7804 effect(DEF dst, USE src, KILL fcc0); 7805 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t" 7806 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" 7807 "FDTOX $src,$dst\t! convert in delay slot\n\t" 7808 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t" 7809 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n" 7810 "skip:" %} 7811 ins_encode(form_d2l_helper(src,dst)); 7812 ins_pipe(fcvtD2L); 7813 %} 7814 7815 7816 // Double to Long conversion 7817 instruct convD2L_reg(stackSlotL dst, regD src) %{ 7818 match(Set dst (ConvD2L src)); 7819 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); 7820 expand %{ 7821 regD tmp; 7822 convD2L_helper(tmp, src); 7823 regD_to_stkL(dst, tmp); 7824 %} 7825 %} 7826 7827 7828 instruct convF2D_reg(regD dst, regF src) %{ 7829 match(Set dst (ConvF2D src)); 7830 format %{ "FSTOD $src,$dst" %} 7831 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fstod_opf); 7832 ins_encode(form3_opf_rs2F_rdD(src, dst)); 7833 ins_pipe(fcvtF2D); 7834 %} 7835 7836 7837 instruct convF2I_helper(regF dst, regF src, flagsRegF0 fcc0) %{ 7838 effect(DEF dst, USE src, KILL fcc0); 7839 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t" 7840 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" 7841 "FSTOI $src,$dst\t! convert in delay slot\n\t" 7842 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t" 7843 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n" 7844 "skip:" %} 7845 ins_encode(form_f2i_helper(src,dst)); 7846 ins_pipe(fcvtF2I); 7847 %} 7848 7849 instruct convF2I_reg(stackSlotI dst, regF src) %{ 7850 match(Set dst (ConvF2I src)); 7851 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); 7852 expand %{ 7853 regF tmp; 7854 convF2I_helper(tmp, src); 7855 regF_to_stkI(dst, tmp); 7856 %} 7857 %} 7858 7859 7860 instruct convF2L_helper(regD dst, regF src, flagsRegF0 fcc0) %{ 7861 effect(DEF dst, USE src, KILL fcc0); 7862 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t" 7863 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" 7864 "FSTOX $src,$dst\t! convert in delay slot\n\t" 7865 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t" 7866 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n" 7867 "skip:" %} 7868 ins_encode(form_f2l_helper(src,dst)); 7869 ins_pipe(fcvtF2L); 7870 %} 7871 7872 // Float to Long conversion 7873 instruct convF2L_reg(stackSlotL dst, regF src) %{ 7874 match(Set dst (ConvF2L src)); 7875 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); 7876 expand %{ 7877 regD tmp; 7878 convF2L_helper(tmp, src); 7879 regD_to_stkL(dst, tmp); 7880 %} 7881 %} 7882 7883 7884 instruct convI2D_helper(regD dst, regF tmp) %{ 7885 effect(USE tmp, DEF dst); 7886 format %{ "FITOD $tmp,$dst" %} 7887 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf); 7888 ins_encode(form3_opf_rs2F_rdD(tmp, dst)); 7889 ins_pipe(fcvtI2D); 7890 %} 7891 7892 instruct convI2D_reg(stackSlotI src, regD dst) %{ 7893 match(Set dst (ConvI2D src)); 7894 ins_cost(DEFAULT_COST + MEMORY_REF_COST); 7895 expand %{ 7896 regF tmp; 7897 stkI_to_regF( tmp, src); 7898 convI2D_helper( dst, tmp); 7899 %} 7900 %} 7901 7902 instruct convI2D_mem( regD_low dst, memory mem ) %{ 7903 match(Set dst (ConvI2D (LoadI mem))); 7904 ins_cost(DEFAULT_COST + MEMORY_REF_COST); 7905 size(8); 7906 format %{ "LDF $mem,$dst\n\t" 7907 "FITOD $dst,$dst" %} 7908 opcode(Assembler::ldf_op3, Assembler::fitod_opf); 7909 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst)); 7910 ins_pipe(floadF_mem); 7911 %} 7912 7913 7914 instruct convI2F_helper(regF dst, regF tmp) %{ 7915 effect(DEF dst, USE tmp); 7916 format %{ "FITOS $tmp,$dst" %} 7917 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitos_opf); 7918 ins_encode(form3_opf_rs2F_rdF(tmp, dst)); 7919 ins_pipe(fcvtI2F); 7920 %} 7921 7922 instruct convI2F_reg( regF dst, stackSlotI src ) %{ 7923 match(Set dst (ConvI2F src)); 7924 ins_cost(DEFAULT_COST + MEMORY_REF_COST); 7925 expand %{ 7926 regF tmp; 7927 stkI_to_regF(tmp,src); 7928 convI2F_helper(dst, tmp); 7929 %} 7930 %} 7931 7932 instruct convI2F_mem( regF dst, memory mem ) %{ 7933 match(Set dst (ConvI2F (LoadI mem))); 7934 ins_cost(DEFAULT_COST + MEMORY_REF_COST); 7935 size(8); 7936 format %{ "LDF $mem,$dst\n\t" 7937 "FITOS $dst,$dst" %} 7938 opcode(Assembler::ldf_op3, Assembler::fitos_opf); 7939 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst)); 7940 ins_pipe(floadF_mem); 7941 %} 7942 7943 7944 instruct convI2L_reg(iRegL dst, iRegI src) %{ 7945 match(Set dst (ConvI2L src)); 7946 size(4); 7947 format %{ "SRA $src,0,$dst\t! int->long" %} 7948 opcode(Assembler::sra_op3, Assembler::arith_op); 7949 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) ); 7950 ins_pipe(ialu_reg_reg); 7951 %} 7952 7953 // Zero-extend convert int to long 7954 instruct convI2L_reg_zex(iRegL dst, iRegI src, immL_32bits mask ) %{ 7955 match(Set dst (AndL (ConvI2L src) mask) ); 7956 size(4); 7957 format %{ "SRL $src,0,$dst\t! zero-extend int to long" %} 7958 opcode(Assembler::srl_op3, Assembler::arith_op); 7959 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) ); 7960 ins_pipe(ialu_reg_reg); 7961 %} 7962 7963 // Zero-extend long 7964 instruct zerox_long(iRegL dst, iRegL src, immL_32bits mask ) %{ 7965 match(Set dst (AndL src mask) ); 7966 size(4); 7967 format %{ "SRL $src,0,$dst\t! zero-extend long" %} 7968 opcode(Assembler::srl_op3, Assembler::arith_op); 7969 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) ); 7970 ins_pipe(ialu_reg_reg); 7971 %} 7972 7973 instruct MoveF2I_stack_reg(iRegI dst, stackSlotF src) %{ 7974 match(Set dst (MoveF2I src)); 7975 effect(DEF dst, USE src); 7976 ins_cost(MEMORY_REF_COST); 7977 7978 size(4); 7979 format %{ "LDUW $src,$dst\t! MoveF2I" %} 7980 opcode(Assembler::lduw_op3); 7981 ins_encode(simple_form3_mem_reg( src, dst ) ); 7982 ins_pipe(iload_mem); 7983 %} 7984 7985 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{ 7986 match(Set dst (MoveI2F src)); 7987 effect(DEF dst, USE src); 7988 ins_cost(MEMORY_REF_COST); 7989 7990 size(4); 7991 format %{ "LDF $src,$dst\t! MoveI2F" %} 7992 opcode(Assembler::ldf_op3); 7993 ins_encode(simple_form3_mem_reg(src, dst)); 7994 ins_pipe(floadF_stk); 7995 %} 7996 7997 instruct MoveD2L_stack_reg(iRegL dst, stackSlotD src) %{ 7998 match(Set dst (MoveD2L src)); 7999 effect(DEF dst, USE src); 8000 ins_cost(MEMORY_REF_COST); 8001 8002 size(4); 8003 format %{ "LDX $src,$dst\t! MoveD2L" %} 8004 opcode(Assembler::ldx_op3); 8005 ins_encode(simple_form3_mem_reg( src, dst ) ); 8006 ins_pipe(iload_mem); 8007 %} 8008 8009 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{ 8010 match(Set dst (MoveL2D src)); 8011 effect(DEF dst, USE src); 8012 ins_cost(MEMORY_REF_COST); 8013 8014 size(4); 8015 format %{ "LDDF $src,$dst\t! MoveL2D" %} 8016 opcode(Assembler::lddf_op3); 8017 ins_encode(simple_form3_mem_reg(src, dst)); 8018 ins_pipe(floadD_stk); 8019 %} 8020 8021 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{ 8022 match(Set dst (MoveF2I src)); 8023 effect(DEF dst, USE src); 8024 ins_cost(MEMORY_REF_COST); 8025 8026 size(4); 8027 format %{ "STF $src,$dst\t!MoveF2I" %} 8028 opcode(Assembler::stf_op3); 8029 ins_encode(simple_form3_mem_reg(dst, src)); 8030 ins_pipe(fstoreF_stk_reg); 8031 %} 8032 8033 instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{ 8034 match(Set dst (MoveI2F src)); 8035 effect(DEF dst, USE src); 8036 ins_cost(MEMORY_REF_COST); 8037 8038 size(4); 8039 format %{ "STW $src,$dst\t!MoveI2F" %} 8040 opcode(Assembler::stw_op3); 8041 ins_encode(simple_form3_mem_reg( dst, src ) ); 8042 ins_pipe(istore_mem_reg); 8043 %} 8044 8045 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{ 8046 match(Set dst (MoveD2L src)); 8047 effect(DEF dst, USE src); 8048 ins_cost(MEMORY_REF_COST); 8049 8050 size(4); 8051 format %{ "STDF $src,$dst\t!MoveD2L" %} 8052 opcode(Assembler::stdf_op3); 8053 ins_encode(simple_form3_mem_reg(dst, src)); 8054 ins_pipe(fstoreD_stk_reg); 8055 %} 8056 8057 instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{ 8058 match(Set dst (MoveL2D src)); 8059 effect(DEF dst, USE src); 8060 ins_cost(MEMORY_REF_COST); 8061 8062 size(4); 8063 format %{ "STX $src,$dst\t!MoveL2D" %} 8064 opcode(Assembler::stx_op3); 8065 ins_encode(simple_form3_mem_reg( dst, src ) ); 8066 ins_pipe(istore_mem_reg); 8067 %} 8068 8069 8070 //----------- 8071 // Long to Double conversion using V8 opcodes. 8072 // Still useful because cheetah traps and becomes 8073 // amazingly slow for some common numbers. 8074 8075 // Magic constant, 0x43300000 8076 instruct loadConI_x43300000(iRegI dst) %{ 8077 effect(DEF dst); 8078 size(4); 8079 format %{ "SETHI HI(0x43300000),$dst\t! 2^52" %} 8080 ins_encode(SetHi22(0x43300000, dst)); 8081 ins_pipe(ialu_none); 8082 %} 8083 8084 // Magic constant, 0x41f00000 8085 instruct loadConI_x41f00000(iRegI dst) %{ 8086 effect(DEF dst); 8087 size(4); 8088 format %{ "SETHI HI(0x41f00000),$dst\t! 2^32" %} 8089 ins_encode(SetHi22(0x41f00000, dst)); 8090 ins_pipe(ialu_none); 8091 %} 8092 8093 // Construct a double from two float halves 8094 instruct regDHi_regDLo_to_regD(regD_low dst, regD_low src1, regD_low src2) %{ 8095 effect(DEF dst, USE src1, USE src2); 8096 size(8); 8097 format %{ "FMOVS $src1.hi,$dst.hi\n\t" 8098 "FMOVS $src2.lo,$dst.lo" %} 8099 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmovs_opf); 8100 ins_encode(form3_opf_rs2D_hi_rdD_hi(src1, dst), form3_opf_rs2D_lo_rdD_lo(src2, dst)); 8101 ins_pipe(faddD_reg_reg); 8102 %} 8103 8104 // Convert integer in high half of a double register (in the lower half of 8105 // the double register file) to double 8106 instruct convI2D_regDHi_regD(regD dst, regD_low src) %{ 8107 effect(DEF dst, USE src); 8108 size(4); 8109 format %{ "FITOD $src,$dst" %} 8110 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf); 8111 ins_encode(form3_opf_rs2D_rdD(src, dst)); 8112 ins_pipe(fcvtLHi2D); 8113 %} 8114 8115 // Add float double precision 8116 instruct addD_regD_regD(regD dst, regD src1, regD src2) %{ 8117 effect(DEF dst, USE src1, USE src2); 8118 size(4); 8119 format %{ "FADDD $src1,$src2,$dst" %} 8120 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf); 8121 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); 8122 ins_pipe(faddD_reg_reg); 8123 %} 8124 8125 // Sub float double precision 8126 instruct subD_regD_regD(regD dst, regD src1, regD src2) %{ 8127 effect(DEF dst, USE src1, USE src2); 8128 size(4); 8129 format %{ "FSUBD $src1,$src2,$dst" %} 8130 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf); 8131 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); 8132 ins_pipe(faddD_reg_reg); 8133 %} 8134 8135 // Mul float double precision 8136 instruct mulD_regD_regD(regD dst, regD src1, regD src2) %{ 8137 effect(DEF dst, USE src1, USE src2); 8138 size(4); 8139 format %{ "FMULD $src1,$src2,$dst" %} 8140 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf); 8141 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); 8142 ins_pipe(fmulD_reg_reg); 8143 %} 8144 8145 instruct convL2D_reg_slow_fxtof(regD dst, stackSlotL src) %{ 8146 match(Set dst (ConvL2D src)); 8147 ins_cost(DEFAULT_COST*8 + MEMORY_REF_COST*6); 8148 8149 expand %{ 8150 regD_low tmpsrc; 8151 iRegI ix43300000; 8152 iRegI ix41f00000; 8153 stackSlotL lx43300000; 8154 stackSlotL lx41f00000; 8155 regD_low dx43300000; 8156 regD dx41f00000; 8157 regD tmp1; 8158 regD_low tmp2; 8159 regD tmp3; 8160 regD tmp4; 8161 8162 stkL_to_regD(tmpsrc, src); 8163 8164 loadConI_x43300000(ix43300000); 8165 loadConI_x41f00000(ix41f00000); 8166 regI_to_stkLHi(lx43300000, ix43300000); 8167 regI_to_stkLHi(lx41f00000, ix41f00000); 8168 stkL_to_regD(dx43300000, lx43300000); 8169 stkL_to_regD(dx41f00000, lx41f00000); 8170 8171 convI2D_regDHi_regD(tmp1, tmpsrc); 8172 regDHi_regDLo_to_regD(tmp2, dx43300000, tmpsrc); 8173 subD_regD_regD(tmp3, tmp2, dx43300000); 8174 mulD_regD_regD(tmp4, tmp1, dx41f00000); 8175 addD_regD_regD(dst, tmp3, tmp4); 8176 %} 8177 %} 8178 8179 // Long to Double conversion using fast fxtof 8180 instruct convL2D_helper(regD dst, regD tmp) %{ 8181 effect(DEF dst, USE tmp); 8182 size(4); 8183 format %{ "FXTOD $tmp,$dst" %} 8184 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtod_opf); 8185 ins_encode(form3_opf_rs2D_rdD(tmp, dst)); 8186 ins_pipe(fcvtL2D); 8187 %} 8188 8189 instruct convL2D_reg_fast_fxtof(regD dst, stackSlotL src) %{ 8190 predicate(VM_Version::has_fast_fxtof()); 8191 match(Set dst (ConvL2D src)); 8192 ins_cost(DEFAULT_COST + 3 * MEMORY_REF_COST); 8193 expand %{ 8194 regD tmp; 8195 stkL_to_regD(tmp, src); 8196 convL2D_helper(dst, tmp); 8197 %} 8198 %} 8199 8200 //----------- 8201 // Long to Float conversion using V8 opcodes. 8202 // Still useful because cheetah traps and becomes 8203 // amazingly slow for some common numbers. 8204 8205 // Long to Float conversion using fast fxtof 8206 instruct convL2F_helper(regF dst, regD tmp) %{ 8207 effect(DEF dst, USE tmp); 8208 size(4); 8209 format %{ "FXTOS $tmp,$dst" %} 8210 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtos_opf); 8211 ins_encode(form3_opf_rs2D_rdF(tmp, dst)); 8212 ins_pipe(fcvtL2F); 8213 %} 8214 8215 instruct convL2F_reg_fast_fxtof(regF dst, stackSlotL src) %{ 8216 match(Set dst (ConvL2F src)); 8217 ins_cost(DEFAULT_COST + MEMORY_REF_COST); 8218 expand %{ 8219 regD tmp; 8220 stkL_to_regD(tmp, src); 8221 convL2F_helper(dst, tmp); 8222 %} 8223 %} 8224 //----------- 8225 8226 instruct convL2I_reg(iRegI dst, iRegL src) %{ 8227 match(Set dst (ConvL2I src)); 8228 #ifndef _LP64 8229 format %{ "MOV $src.lo,$dst\t! long->int" %} 8230 ins_encode( form3_g0_rs2_rd_move_lo2( src, dst ) ); 8231 ins_pipe(ialu_move_reg_I_to_L); 8232 #else 8233 size(4); 8234 format %{ "SRA $src,R_G0,$dst\t! long->int" %} 8235 ins_encode( form3_rs1_rd_signextend_lo1( src, dst ) ); 8236 ins_pipe(ialu_reg); 8237 #endif 8238 %} 8239 8240 // Register Shift Right Immediate 8241 instruct shrL_reg_imm6_L2I(iRegI dst, iRegL src, immI_32_63 cnt) %{ 8242 match(Set dst (ConvL2I (RShiftL src cnt))); 8243 8244 size(4); 8245 format %{ "SRAX $src,$cnt,$dst" %} 8246 opcode(Assembler::srax_op3, Assembler::arith_op); 8247 ins_encode( form3_sd_rs1_imm6_rd( src, cnt, dst ) ); 8248 ins_pipe(ialu_reg_imm); 8249 %} 8250 8251 // Replicate scalar to packed byte values in Double register 8252 instruct Repl8B_reg_helper(iRegL dst, iRegI src) %{ 8253 effect(DEF dst, USE src); 8254 format %{ "SLLX $src,56,$dst\n\t" 8255 "SRLX $dst, 8,O7\n\t" 8256 "OR $dst,O7,$dst\n\t" 8257 "SRLX $dst,16,O7\n\t" 8258 "OR $dst,O7,$dst\n\t" 8259 "SRLX $dst,32,O7\n\t" 8260 "OR $dst,O7,$dst\t! replicate8B" %} 8261 ins_encode( enc_repl8b(src, dst)); 8262 ins_pipe(ialu_reg); 8263 %} 8264 8265 // Replicate scalar to packed byte values in Double register 8266 instruct Repl8B_reg(stackSlotD dst, iRegI src) %{ 8267 match(Set dst (Replicate8B src)); 8268 expand %{ 8269 iRegL tmp; 8270 Repl8B_reg_helper(tmp, src); 8271 regL_to_stkD(dst, tmp); 8272 %} 8273 %} 8274 8275 // Replicate scalar constant to packed byte values in Double register 8276 instruct Repl8B_immI(regD dst, immI13 src, o7RegP tmp) %{ 8277 match(Set dst (Replicate8B src)); 8278 #ifdef _LP64 8279 size(36); 8280 #else 8281 size(8); 8282 #endif 8283 format %{ "SETHI hi(&Repl8($src)),$tmp\t!get Repl8B($src) from table\n\t" 8284 "LDDF [$tmp+lo(&Repl8($src))],$dst" %} 8285 ins_encode( LdReplImmI(src, dst, tmp, (8), (1)) ); 8286 ins_pipe(loadConFD); 8287 %} 8288 8289 // Replicate scalar to packed char values into stack slot 8290 instruct Repl4C_reg_helper(iRegL dst, iRegI src) %{ 8291 effect(DEF dst, USE src); 8292 format %{ "SLLX $src,48,$dst\n\t" 8293 "SRLX $dst,16,O7\n\t" 8294 "OR $dst,O7,$dst\n\t" 8295 "SRLX $dst,32,O7\n\t" 8296 "OR $dst,O7,$dst\t! replicate4C" %} 8297 ins_encode( enc_repl4s(src, dst) ); 8298 ins_pipe(ialu_reg); 8299 %} 8300 8301 // Replicate scalar to packed char values into stack slot 8302 instruct Repl4C_reg(stackSlotD dst, iRegI src) %{ 8303 match(Set dst (Replicate4C src)); 8304 expand %{ 8305 iRegL tmp; 8306 Repl4C_reg_helper(tmp, src); 8307 regL_to_stkD(dst, tmp); 8308 %} 8309 %} 8310 8311 // Replicate scalar constant to packed char values in Double register 8312 instruct Repl4C_immI(regD dst, immI src, o7RegP tmp) %{ 8313 match(Set dst (Replicate4C src)); 8314 #ifdef _LP64 8315 size(36); 8316 #else 8317 size(8); 8318 #endif 8319 format %{ "SETHI hi(&Repl4($src)),$tmp\t!get Repl4C($src) from table\n\t" 8320 "LDDF [$tmp+lo(&Repl4($src))],$dst" %} 8321 ins_encode( LdReplImmI(src, dst, tmp, (4), (2)) ); 8322 ins_pipe(loadConFD); 8323 %} 8324 8325 // Replicate scalar to packed short values into stack slot 8326 instruct Repl4S_reg_helper(iRegL dst, iRegI src) %{ 8327 effect(DEF dst, USE src); 8328 format %{ "SLLX $src,48,$dst\n\t" 8329 "SRLX $dst,16,O7\n\t" 8330 "OR $dst,O7,$dst\n\t" 8331 "SRLX $dst,32,O7\n\t" 8332 "OR $dst,O7,$dst\t! replicate4S" %} 8333 ins_encode( enc_repl4s(src, dst) ); 8334 ins_pipe(ialu_reg); 8335 %} 8336 8337 // Replicate scalar to packed short values into stack slot 8338 instruct Repl4S_reg(stackSlotD dst, iRegI src) %{ 8339 match(Set dst (Replicate4S src)); 8340 expand %{ 8341 iRegL tmp; 8342 Repl4S_reg_helper(tmp, src); 8343 regL_to_stkD(dst, tmp); 8344 %} 8345 %} 8346 8347 // Replicate scalar constant to packed short values in Double register 8348 instruct Repl4S_immI(regD dst, immI src, o7RegP tmp) %{ 8349 match(Set dst (Replicate4S src)); 8350 #ifdef _LP64 8351 size(36); 8352 #else 8353 size(8); 8354 #endif 8355 format %{ "SETHI hi(&Repl4($src)),$tmp\t!get Repl4S($src) from table\n\t" 8356 "LDDF [$tmp+lo(&Repl4($src))],$dst" %} 8357 ins_encode( LdReplImmI(src, dst, tmp, (4), (2)) ); 8358 ins_pipe(loadConFD); 8359 %} 8360 8361 // Replicate scalar to packed int values in Double register 8362 instruct Repl2I_reg_helper(iRegL dst, iRegI src) %{ 8363 effect(DEF dst, USE src); 8364 format %{ "SLLX $src,32,$dst\n\t" 8365 "SRLX $dst,32,O7\n\t" 8366 "OR $dst,O7,$dst\t! replicate2I" %} 8367 ins_encode( enc_repl2i(src, dst)); 8368 ins_pipe(ialu_reg); 8369 %} 8370 8371 // Replicate scalar to packed int values in Double register 8372 instruct Repl2I_reg(stackSlotD dst, iRegI src) %{ 8373 match(Set dst (Replicate2I src)); 8374 expand %{ 8375 iRegL tmp; 8376 Repl2I_reg_helper(tmp, src); 8377 regL_to_stkD(dst, tmp); 8378 %} 8379 %} 8380 8381 // Replicate scalar zero constant to packed int values in Double register 8382 instruct Repl2I_immI(regD dst, immI src, o7RegP tmp) %{ 8383 match(Set dst (Replicate2I src)); 8384 #ifdef _LP64 8385 size(36); 8386 #else 8387 size(8); 8388 #endif 8389 format %{ "SETHI hi(&Repl2($src)),$tmp\t!get Repl2I($src) from table\n\t" 8390 "LDDF [$tmp+lo(&Repl2($src))],$dst" %} 8391 ins_encode( LdReplImmI(src, dst, tmp, (2), (4)) ); 8392 ins_pipe(loadConFD); 8393 %} 8394 8395 //----------Control Flow Instructions------------------------------------------ 8396 // Compare Instructions 8397 // Compare Integers 8398 instruct compI_iReg(flagsReg icc, iRegI op1, iRegI op2) %{ 8399 match(Set icc (CmpI op1 op2)); 8400 effect( DEF icc, USE op1, USE op2 ); 8401 8402 size(4); 8403 format %{ "CMP $op1,$op2" %} 8404 opcode(Assembler::subcc_op3, Assembler::arith_op); 8405 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); 8406 ins_pipe(ialu_cconly_reg_reg); 8407 %} 8408 8409 instruct compU_iReg(flagsRegU icc, iRegI op1, iRegI op2) %{ 8410 match(Set icc (CmpU op1 op2)); 8411 8412 size(4); 8413 format %{ "CMP $op1,$op2\t! unsigned" %} 8414 opcode(Assembler::subcc_op3, Assembler::arith_op); 8415 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); 8416 ins_pipe(ialu_cconly_reg_reg); 8417 %} 8418 8419 instruct compI_iReg_imm13(flagsReg icc, iRegI op1, immI13 op2) %{ 8420 match(Set icc (CmpI op1 op2)); 8421 effect( DEF icc, USE op1 ); 8422 8423 size(4); 8424 format %{ "CMP $op1,$op2" %} 8425 opcode(Assembler::subcc_op3, Assembler::arith_op); 8426 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); 8427 ins_pipe(ialu_cconly_reg_imm); 8428 %} 8429 8430 instruct testI_reg_reg( flagsReg icc, iRegI op1, iRegI op2, immI0 zero ) %{ 8431 match(Set icc (CmpI (AndI op1 op2) zero)); 8432 8433 size(4); 8434 format %{ "BTST $op2,$op1" %} 8435 opcode(Assembler::andcc_op3, Assembler::arith_op); 8436 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); 8437 ins_pipe(ialu_cconly_reg_reg_zero); 8438 %} 8439 8440 instruct testI_reg_imm( flagsReg icc, iRegI op1, immI13 op2, immI0 zero ) %{ 8441 match(Set icc (CmpI (AndI op1 op2) zero)); 8442 8443 size(4); 8444 format %{ "BTST $op2,$op1" %} 8445 opcode(Assembler::andcc_op3, Assembler::arith_op); 8446 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); 8447 ins_pipe(ialu_cconly_reg_imm_zero); 8448 %} 8449 8450 instruct compL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2 ) %{ 8451 match(Set xcc (CmpL op1 op2)); 8452 effect( DEF xcc, USE op1, USE op2 ); 8453 8454 size(4); 8455 format %{ "CMP $op1,$op2\t\t! long" %} 8456 opcode(Assembler::subcc_op3, Assembler::arith_op); 8457 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); 8458 ins_pipe(ialu_cconly_reg_reg); 8459 %} 8460 8461 instruct compL_reg_con(flagsRegL xcc, iRegL op1, immL13 con) %{ 8462 match(Set xcc (CmpL op1 con)); 8463 effect( DEF xcc, USE op1, USE con ); 8464 8465 size(4); 8466 format %{ "CMP $op1,$con\t\t! long" %} 8467 opcode(Assembler::subcc_op3, Assembler::arith_op); 8468 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) ); 8469 ins_pipe(ialu_cconly_reg_reg); 8470 %} 8471 8472 instruct testL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2, immL0 zero) %{ 8473 match(Set xcc (CmpL (AndL op1 op2) zero)); 8474 effect( DEF xcc, USE op1, USE op2 ); 8475 8476 size(4); 8477 format %{ "BTST $op1,$op2\t\t! long" %} 8478 opcode(Assembler::andcc_op3, Assembler::arith_op); 8479 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); 8480 ins_pipe(ialu_cconly_reg_reg); 8481 %} 8482 8483 // useful for checking the alignment of a pointer: 8484 instruct testL_reg_con(flagsRegL xcc, iRegL op1, immL13 con, immL0 zero) %{ 8485 match(Set xcc (CmpL (AndL op1 con) zero)); 8486 effect( DEF xcc, USE op1, USE con ); 8487 8488 size(4); 8489 format %{ "BTST $op1,$con\t\t! long" %} 8490 opcode(Assembler::andcc_op3, Assembler::arith_op); 8491 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) ); 8492 ins_pipe(ialu_cconly_reg_reg); 8493 %} 8494 8495 instruct compU_iReg_imm13(flagsRegU icc, iRegI op1, immU13 op2 ) %{ 8496 match(Set icc (CmpU op1 op2)); 8497 8498 size(4); 8499 format %{ "CMP $op1,$op2\t! unsigned" %} 8500 opcode(Assembler::subcc_op3, Assembler::arith_op); 8501 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); 8502 ins_pipe(ialu_cconly_reg_imm); 8503 %} 8504 8505 // Compare Pointers 8506 instruct compP_iRegP(flagsRegP pcc, iRegP op1, iRegP op2 ) %{ 8507 match(Set pcc (CmpP op1 op2)); 8508 8509 size(4); 8510 format %{ "CMP $op1,$op2\t! ptr" %} 8511 opcode(Assembler::subcc_op3, Assembler::arith_op); 8512 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); 8513 ins_pipe(ialu_cconly_reg_reg); 8514 %} 8515 8516 instruct compP_iRegP_imm13(flagsRegP pcc, iRegP op1, immP13 op2 ) %{ 8517 match(Set pcc (CmpP op1 op2)); 8518 8519 size(4); 8520 format %{ "CMP $op1,$op2\t! ptr" %} 8521 opcode(Assembler::subcc_op3, Assembler::arith_op); 8522 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); 8523 ins_pipe(ialu_cconly_reg_imm); 8524 %} 8525 8526 // Compare Narrow oops 8527 instruct compN_iRegN(flagsReg icc, iRegN op1, iRegN op2 ) %{ 8528 match(Set icc (CmpN op1 op2)); 8529 8530 size(4); 8531 format %{ "CMP $op1,$op2\t! compressed ptr" %} 8532 opcode(Assembler::subcc_op3, Assembler::arith_op); 8533 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); 8534 ins_pipe(ialu_cconly_reg_reg); 8535 %} 8536 8537 instruct compN_iRegN_immN0(flagsReg icc, iRegN op1, immN0 op2 ) %{ 8538 match(Set icc (CmpN op1 op2)); 8539 8540 size(4); 8541 format %{ "CMP $op1,$op2\t! compressed ptr" %} 8542 opcode(Assembler::subcc_op3, Assembler::arith_op); 8543 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); 8544 ins_pipe(ialu_cconly_reg_imm); 8545 %} 8546 8547 //----------Max and Min-------------------------------------------------------- 8548 // Min Instructions 8549 // Conditional move for min 8550 instruct cmovI_reg_lt( iRegI op2, iRegI op1, flagsReg icc ) %{ 8551 effect( USE_DEF op2, USE op1, USE icc ); 8552 8553 size(4); 8554 format %{ "MOVlt icc,$op1,$op2\t! min" %} 8555 opcode(Assembler::less); 8556 ins_encode( enc_cmov_reg_minmax(op2,op1) ); 8557 ins_pipe(ialu_reg_flags); 8558 %} 8559 8560 // Min Register with Register. 8561 instruct minI_eReg(iRegI op1, iRegI op2) %{ 8562 match(Set op2 (MinI op1 op2)); 8563 ins_cost(DEFAULT_COST*2); 8564 expand %{ 8565 flagsReg icc; 8566 compI_iReg(icc,op1,op2); 8567 cmovI_reg_lt(op2,op1,icc); 8568 %} 8569 %} 8570 8571 // Max Instructions 8572 // Conditional move for max 8573 instruct cmovI_reg_gt( iRegI op2, iRegI op1, flagsReg icc ) %{ 8574 effect( USE_DEF op2, USE op1, USE icc ); 8575 format %{ "MOVgt icc,$op1,$op2\t! max" %} 8576 opcode(Assembler::greater); 8577 ins_encode( enc_cmov_reg_minmax(op2,op1) ); 8578 ins_pipe(ialu_reg_flags); 8579 %} 8580 8581 // Max Register with Register 8582 instruct maxI_eReg(iRegI op1, iRegI op2) %{ 8583 match(Set op2 (MaxI op1 op2)); 8584 ins_cost(DEFAULT_COST*2); 8585 expand %{ 8586 flagsReg icc; 8587 compI_iReg(icc,op1,op2); 8588 cmovI_reg_gt(op2,op1,icc); 8589 %} 8590 %} 8591 8592 8593 //----------Float Compares---------------------------------------------------- 8594 // Compare floating, generate condition code 8595 instruct cmpF_cc(flagsRegF fcc, regF src1, regF src2) %{ 8596 match(Set fcc (CmpF src1 src2)); 8597 8598 size(4); 8599 format %{ "FCMPs $fcc,$src1,$src2" %} 8600 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmps_opf); 8601 ins_encode( form3_opf_rs1F_rs2F_fcc( src1, src2, fcc ) ); 8602 ins_pipe(faddF_fcc_reg_reg_zero); 8603 %} 8604 8605 instruct cmpD_cc(flagsRegF fcc, regD src1, regD src2) %{ 8606 match(Set fcc (CmpD src1 src2)); 8607 8608 size(4); 8609 format %{ "FCMPd $fcc,$src1,$src2" %} 8610 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmpd_opf); 8611 ins_encode( form3_opf_rs1D_rs2D_fcc( src1, src2, fcc ) ); 8612 ins_pipe(faddD_fcc_reg_reg_zero); 8613 %} 8614 8615 8616 // Compare floating, generate -1,0,1 8617 instruct cmpF_reg(iRegI dst, regF src1, regF src2, flagsRegF0 fcc0) %{ 8618 match(Set dst (CmpF3 src1 src2)); 8619 effect(KILL fcc0); 8620 ins_cost(DEFAULT_COST*3+BRANCH_COST*3); 8621 format %{ "fcmpl $dst,$src1,$src2" %} 8622 // Primary = float 8623 opcode( true ); 8624 ins_encode( floating_cmp( dst, src1, src2 ) ); 8625 ins_pipe( floating_cmp ); 8626 %} 8627 8628 instruct cmpD_reg(iRegI dst, regD src1, regD src2, flagsRegF0 fcc0) %{ 8629 match(Set dst (CmpD3 src1 src2)); 8630 effect(KILL fcc0); 8631 ins_cost(DEFAULT_COST*3+BRANCH_COST*3); 8632 format %{ "dcmpl $dst,$src1,$src2" %} 8633 // Primary = double (not float) 8634 opcode( false ); 8635 ins_encode( floating_cmp( dst, src1, src2 ) ); 8636 ins_pipe( floating_cmp ); 8637 %} 8638 8639 //----------Branches--------------------------------------------------------- 8640 // Jump 8641 // (compare 'operand indIndex' and 'instruct addP_reg_reg' above) 8642 instruct jumpXtnd(iRegX switch_val, o7RegI table) %{ 8643 match(Jump switch_val); 8644 8645 ins_cost(350); 8646 8647 format %{ "SETHI [hi(table_base)],O7\n\t" 8648 "ADD O7, lo(table_base), O7\n\t" 8649 "LD [O7+$switch_val], O7\n\t" 8650 "JUMP O7" 8651 %} 8652 ins_encode( jump_enc( switch_val, table) ); 8653 ins_pc_relative(1); 8654 ins_pipe(ialu_reg_reg); 8655 %} 8656 8657 // Direct Branch. Use V8 version with longer range. 8658 instruct branch(label labl) %{ 8659 match(Goto); 8660 effect(USE labl); 8661 8662 size(8); 8663 ins_cost(BRANCH_COST); 8664 format %{ "BA $labl" %} 8665 // Prim = bits 24-22, Secnd = bits 31-30, Tert = cond 8666 opcode(Assembler::br_op2, Assembler::branch_op, Assembler::always); 8667 ins_encode( enc_ba( labl ) ); 8668 ins_pc_relative(1); 8669 ins_pipe(br); 8670 %} 8671 8672 // Conditional Direct Branch 8673 instruct branchCon(cmpOp cmp, flagsReg icc, label labl) %{ 8674 match(If cmp icc); 8675 effect(USE labl); 8676 8677 size(8); 8678 ins_cost(BRANCH_COST); 8679 format %{ "BP$cmp $icc,$labl" %} 8680 // Prim = bits 24-22, Secnd = bits 31-30 8681 ins_encode( enc_bp( labl, cmp, icc ) ); 8682 ins_pc_relative(1); 8683 ins_pipe(br_cc); 8684 %} 8685 8686 // Branch-on-register tests all 64 bits. We assume that values 8687 // in 64-bit registers always remains zero or sign extended 8688 // unless our code munges the high bits. Interrupts can chop 8689 // the high order bits to zero or sign at any time. 8690 instruct branchCon_regI(cmpOp_reg cmp, iRegI op1, immI0 zero, label labl) %{ 8691 match(If cmp (CmpI op1 zero)); 8692 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf)); 8693 effect(USE labl); 8694 8695 size(8); 8696 ins_cost(BRANCH_COST); 8697 format %{ "BR$cmp $op1,$labl" %} 8698 ins_encode( enc_bpr( labl, cmp, op1 ) ); 8699 ins_pc_relative(1); 8700 ins_pipe(br_reg); 8701 %} 8702 8703 instruct branchCon_regP(cmpOp_reg cmp, iRegP op1, immP0 null, label labl) %{ 8704 match(If cmp (CmpP op1 null)); 8705 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf)); 8706 effect(USE labl); 8707 8708 size(8); 8709 ins_cost(BRANCH_COST); 8710 format %{ "BR$cmp $op1,$labl" %} 8711 ins_encode( enc_bpr( labl, cmp, op1 ) ); 8712 ins_pc_relative(1); 8713 ins_pipe(br_reg); 8714 %} 8715 8716 instruct branchCon_regL(cmpOp_reg cmp, iRegL op1, immL0 zero, label labl) %{ 8717 match(If cmp (CmpL op1 zero)); 8718 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf)); 8719 effect(USE labl); 8720 8721 size(8); 8722 ins_cost(BRANCH_COST); 8723 format %{ "BR$cmp $op1,$labl" %} 8724 ins_encode( enc_bpr( labl, cmp, op1 ) ); 8725 ins_pc_relative(1); 8726 ins_pipe(br_reg); 8727 %} 8728 8729 instruct branchConU(cmpOpU cmp, flagsRegU icc, label labl) %{ 8730 match(If cmp icc); 8731 effect(USE labl); 8732 8733 format %{ "BP$cmp $icc,$labl" %} 8734 // Prim = bits 24-22, Secnd = bits 31-30 8735 ins_encode( enc_bp( labl, cmp, icc ) ); 8736 ins_pc_relative(1); 8737 ins_pipe(br_cc); 8738 %} 8739 8740 instruct branchConP(cmpOpP cmp, flagsRegP pcc, label labl) %{ 8741 match(If cmp pcc); 8742 effect(USE labl); 8743 8744 size(8); 8745 ins_cost(BRANCH_COST); 8746 format %{ "BP$cmp $pcc,$labl" %} 8747 // Prim = bits 24-22, Secnd = bits 31-30 8748 ins_encode( enc_bpx( labl, cmp, pcc ) ); 8749 ins_pc_relative(1); 8750 ins_pipe(br_cc); 8751 %} 8752 8753 instruct branchConF(cmpOpF cmp, flagsRegF fcc, label labl) %{ 8754 match(If cmp fcc); 8755 effect(USE labl); 8756 8757 size(8); 8758 ins_cost(BRANCH_COST); 8759 format %{ "FBP$cmp $fcc,$labl" %} 8760 // Prim = bits 24-22, Secnd = bits 31-30 8761 ins_encode( enc_fbp( labl, cmp, fcc ) ); 8762 ins_pc_relative(1); 8763 ins_pipe(br_fcc); 8764 %} 8765 8766 instruct branchLoopEnd(cmpOp cmp, flagsReg icc, label labl) %{ 8767 match(CountedLoopEnd cmp icc); 8768 effect(USE labl); 8769 8770 size(8); 8771 ins_cost(BRANCH_COST); 8772 format %{ "BP$cmp $icc,$labl\t! Loop end" %} 8773 // Prim = bits 24-22, Secnd = bits 31-30 8774 ins_encode( enc_bp( labl, cmp, icc ) ); 8775 ins_pc_relative(1); 8776 ins_pipe(br_cc); 8777 %} 8778 8779 instruct branchLoopEndU(cmpOpU cmp, flagsRegU icc, label labl) %{ 8780 match(CountedLoopEnd cmp icc); 8781 effect(USE labl); 8782 8783 size(8); 8784 ins_cost(BRANCH_COST); 8785 format %{ "BP$cmp $icc,$labl\t! Loop end" %} 8786 // Prim = bits 24-22, Secnd = bits 31-30 8787 ins_encode( enc_bp( labl, cmp, icc ) ); 8788 ins_pc_relative(1); 8789 ins_pipe(br_cc); 8790 %} 8791 8792 // ============================================================================ 8793 // Long Compare 8794 // 8795 // Currently we hold longs in 2 registers. Comparing such values efficiently 8796 // is tricky. The flavor of compare used depends on whether we are testing 8797 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit. 8798 // The GE test is the negated LT test. The LE test can be had by commuting 8799 // the operands (yielding a GE test) and then negating; negate again for the 8800 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the 8801 // NE test is negated from that. 8802 8803 // Due to a shortcoming in the ADLC, it mixes up expressions like: 8804 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the 8805 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections 8806 // are collapsed internally in the ADLC's dfa-gen code. The match for 8807 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the 8808 // foo match ends up with the wrong leaf. One fix is to not match both 8809 // reg-reg and reg-zero forms of long-compare. This is unfortunate because 8810 // both forms beat the trinary form of long-compare and both are very useful 8811 // on Intel which has so few registers. 8812 8813 instruct branchCon_long(cmpOp cmp, flagsRegL xcc, label labl) %{ 8814 match(If cmp xcc); 8815 effect(USE labl); 8816 8817 size(8); 8818 ins_cost(BRANCH_COST); 8819 format %{ "BP$cmp $xcc,$labl" %} 8820 // Prim = bits 24-22, Secnd = bits 31-30 8821 ins_encode( enc_bpl( labl, cmp, xcc ) ); 8822 ins_pc_relative(1); 8823 ins_pipe(br_cc); 8824 %} 8825 8826 // Manifest a CmpL3 result in an integer register. Very painful. 8827 // This is the test to avoid. 8828 instruct cmpL3_reg_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg ccr ) %{ 8829 match(Set dst (CmpL3 src1 src2) ); 8830 effect( KILL ccr ); 8831 ins_cost(6*DEFAULT_COST); 8832 size(24); 8833 format %{ "CMP $src1,$src2\t\t! long\n" 8834 "\tBLT,a,pn done\n" 8835 "\tMOV -1,$dst\t! delay slot\n" 8836 "\tBGT,a,pn done\n" 8837 "\tMOV 1,$dst\t! delay slot\n" 8838 "\tCLR $dst\n" 8839 "done:" %} 8840 ins_encode( cmpl_flag(src1,src2,dst) ); 8841 ins_pipe(cmpL_reg); 8842 %} 8843 8844 // Conditional move 8845 instruct cmovLL_reg(cmpOp cmp, flagsRegL xcc, iRegL dst, iRegL src) %{ 8846 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src))); 8847 ins_cost(150); 8848 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %} 8849 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); 8850 ins_pipe(ialu_reg); 8851 %} 8852 8853 instruct cmovLL_imm(cmpOp cmp, flagsRegL xcc, iRegL dst, immL0 src) %{ 8854 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src))); 8855 ins_cost(140); 8856 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %} 8857 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) ); 8858 ins_pipe(ialu_imm); 8859 %} 8860 8861 instruct cmovIL_reg(cmpOp cmp, flagsRegL xcc, iRegI dst, iRegI src) %{ 8862 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src))); 8863 ins_cost(150); 8864 format %{ "MOV$cmp $xcc,$src,$dst" %} 8865 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); 8866 ins_pipe(ialu_reg); 8867 %} 8868 8869 instruct cmovIL_imm(cmpOp cmp, flagsRegL xcc, iRegI dst, immI11 src) %{ 8870 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src))); 8871 ins_cost(140); 8872 format %{ "MOV$cmp $xcc,$src,$dst" %} 8873 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) ); 8874 ins_pipe(ialu_imm); 8875 %} 8876 8877 instruct cmovNL_reg(cmpOp cmp, flagsRegL xcc, iRegN dst, iRegN src) %{ 8878 match(Set dst (CMoveN (Binary cmp xcc) (Binary dst src))); 8879 ins_cost(150); 8880 format %{ "MOV$cmp $xcc,$src,$dst" %} 8881 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); 8882 ins_pipe(ialu_reg); 8883 %} 8884 8885 instruct cmovPL_reg(cmpOp cmp, flagsRegL xcc, iRegP dst, iRegP src) %{ 8886 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src))); 8887 ins_cost(150); 8888 format %{ "MOV$cmp $xcc,$src,$dst" %} 8889 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); 8890 ins_pipe(ialu_reg); 8891 %} 8892 8893 instruct cmovPL_imm(cmpOp cmp, flagsRegL xcc, iRegP dst, immP0 src) %{ 8894 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src))); 8895 ins_cost(140); 8896 format %{ "MOV$cmp $xcc,$src,$dst" %} 8897 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) ); 8898 ins_pipe(ialu_imm); 8899 %} 8900 8901 instruct cmovFL_reg(cmpOp cmp, flagsRegL xcc, regF dst, regF src) %{ 8902 match(Set dst (CMoveF (Binary cmp xcc) (Binary dst src))); 8903 ins_cost(150); 8904 opcode(0x101); 8905 format %{ "FMOVS$cmp $xcc,$src,$dst" %} 8906 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) ); 8907 ins_pipe(int_conditional_float_move); 8908 %} 8909 8910 instruct cmovDL_reg(cmpOp cmp, flagsRegL xcc, regD dst, regD src) %{ 8911 match(Set dst (CMoveD (Binary cmp xcc) (Binary dst src))); 8912 ins_cost(150); 8913 opcode(0x102); 8914 format %{ "FMOVD$cmp $xcc,$src,$dst" %} 8915 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) ); 8916 ins_pipe(int_conditional_float_move); 8917 %} 8918 8919 // ============================================================================ 8920 // Safepoint Instruction 8921 instruct safePoint_poll(iRegP poll) %{ 8922 match(SafePoint poll); 8923 effect(USE poll); 8924 8925 size(4); 8926 #ifdef _LP64 8927 format %{ "LDX [$poll],R_G0\t! Safepoint: poll for GC" %} 8928 #else 8929 format %{ "LDUW [$poll],R_G0\t! Safepoint: poll for GC" %} 8930 #endif 8931 ins_encode %{ 8932 __ relocate(relocInfo::poll_type); 8933 __ ld_ptr($poll$$Register, 0, G0); 8934 %} 8935 ins_pipe(loadPollP); 8936 %} 8937 8938 // ============================================================================ 8939 // Call Instructions 8940 // Call Java Static Instruction 8941 instruct CallStaticJavaDirect( method meth ) %{ 8942 match(CallStaticJava); 8943 effect(USE meth); 8944 8945 size(8); 8946 ins_cost(CALL_COST); 8947 format %{ "CALL,static ; NOP ==> " %} 8948 ins_encode( Java_Static_Call( meth ), call_epilog ); 8949 ins_pc_relative(1); 8950 ins_pipe(simple_call); 8951 %} 8952 8953 // Call Java Dynamic Instruction 8954 instruct CallDynamicJavaDirect( method meth ) %{ 8955 match(CallDynamicJava); 8956 effect(USE meth); 8957 8958 ins_cost(CALL_COST); 8959 format %{ "SET (empty),R_G5\n\t" 8960 "CALL,dynamic ; NOP ==> " %} 8961 ins_encode( Java_Dynamic_Call( meth ), call_epilog ); 8962 ins_pc_relative(1); 8963 ins_pipe(call); 8964 %} 8965 8966 // Call Runtime Instruction 8967 instruct CallRuntimeDirect(method meth, l7RegP l7) %{ 8968 match(CallRuntime); 8969 effect(USE meth, KILL l7); 8970 ins_cost(CALL_COST); 8971 format %{ "CALL,runtime" %} 8972 ins_encode( Java_To_Runtime( meth ), 8973 call_epilog, adjust_long_from_native_call ); 8974 ins_pc_relative(1); 8975 ins_pipe(simple_call); 8976 %} 8977 8978 // Call runtime without safepoint - same as CallRuntime 8979 instruct CallLeafDirect(method meth, l7RegP l7) %{ 8980 match(CallLeaf); 8981 effect(USE meth, KILL l7); 8982 ins_cost(CALL_COST); 8983 format %{ "CALL,runtime leaf" %} 8984 ins_encode( Java_To_Runtime( meth ), 8985 call_epilog, 8986 adjust_long_from_native_call ); 8987 ins_pc_relative(1); 8988 ins_pipe(simple_call); 8989 %} 8990 8991 // Call runtime without safepoint - same as CallLeaf 8992 instruct CallLeafNoFPDirect(method meth, l7RegP l7) %{ 8993 match(CallLeafNoFP); 8994 effect(USE meth, KILL l7); 8995 ins_cost(CALL_COST); 8996 format %{ "CALL,runtime leaf nofp" %} 8997 ins_encode( Java_To_Runtime( meth ), 8998 call_epilog, 8999 adjust_long_from_native_call ); 9000 ins_pc_relative(1); 9001 ins_pipe(simple_call); 9002 %} 9003 9004 // Tail Call; Jump from runtime stub to Java code. 9005 // Also known as an 'interprocedural jump'. 9006 // Target of jump will eventually return to caller. 9007 // TailJump below removes the return address. 9008 instruct TailCalljmpInd(g3RegP jump_target, inline_cache_regP method_oop) %{ 9009 match(TailCall jump_target method_oop ); 9010 9011 ins_cost(CALL_COST); 9012 format %{ "Jmp $jump_target ; NOP \t! $method_oop holds method oop" %} 9013 ins_encode(form_jmpl(jump_target)); 9014 ins_pipe(tail_call); 9015 %} 9016 9017 9018 // Return Instruction 9019 instruct Ret() %{ 9020 match(Return); 9021 9022 // The epilogue node did the ret already. 9023 size(0); 9024 format %{ "! return" %} 9025 ins_encode(); 9026 ins_pipe(empty); 9027 %} 9028 9029 9030 // Tail Jump; remove the return address; jump to target. 9031 // TailCall above leaves the return address around. 9032 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2). 9033 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a 9034 // "restore" before this instruction (in Epilogue), we need to materialize it 9035 // in %i0. 9036 instruct tailjmpInd(g1RegP jump_target, i0RegP ex_oop) %{ 9037 match( TailJump jump_target ex_oop ); 9038 ins_cost(CALL_COST); 9039 format %{ "! discard R_O7\n\t" 9040 "Jmp $jump_target ; ADD O7,8,O1 \t! $ex_oop holds exc. oop" %} 9041 ins_encode(form_jmpl_set_exception_pc(jump_target)); 9042 // opcode(Assembler::jmpl_op3, Assembler::arith_op); 9043 // The hack duplicates the exception oop into G3, so that CreateEx can use it there. 9044 // ins_encode( form3_rs1_simm13_rd( jump_target, 0x00, R_G0 ), move_return_pc_to_o1() ); 9045 ins_pipe(tail_call); 9046 %} 9047 9048 // Create exception oop: created by stack-crawling runtime code. 9049 // Created exception is now available to this handler, and is setup 9050 // just prior to jumping to this handler. No code emitted. 9051 instruct CreateException( o0RegP ex_oop ) 9052 %{ 9053 match(Set ex_oop (CreateEx)); 9054 ins_cost(0); 9055 9056 size(0); 9057 // use the following format syntax 9058 format %{ "! exception oop is in R_O0; no code emitted" %} 9059 ins_encode(); 9060 ins_pipe(empty); 9061 %} 9062 9063 9064 // Rethrow exception: 9065 // The exception oop will come in the first argument position. 9066 // Then JUMP (not call) to the rethrow stub code. 9067 instruct RethrowException() 9068 %{ 9069 match(Rethrow); 9070 ins_cost(CALL_COST); 9071 9072 // use the following format syntax 9073 format %{ "Jmp rethrow_stub" %} 9074 ins_encode(enc_rethrow); 9075 ins_pipe(tail_call); 9076 %} 9077 9078 9079 // Die now 9080 instruct ShouldNotReachHere( ) 9081 %{ 9082 match(Halt); 9083 ins_cost(CALL_COST); 9084 9085 size(4); 9086 // Use the following format syntax 9087 format %{ "ILLTRAP ; ShouldNotReachHere" %} 9088 ins_encode( form2_illtrap() ); 9089 ins_pipe(tail_call); 9090 %} 9091 9092 // ============================================================================ 9093 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass 9094 // array for an instance of the superklass. Set a hidden internal cache on a 9095 // hit (cache is checked with exposed code in gen_subtype_check()). Return 9096 // not zero for a miss or zero for a hit. The encoding ALSO sets flags. 9097 instruct partialSubtypeCheck( o0RegP index, o1RegP sub, o2RegP super, flagsRegP pcc, o7RegP o7 ) %{ 9098 match(Set index (PartialSubtypeCheck sub super)); 9099 effect( KILL pcc, KILL o7 ); 9100 ins_cost(DEFAULT_COST*10); 9101 format %{ "CALL PartialSubtypeCheck\n\tNOP" %} 9102 ins_encode( enc_PartialSubtypeCheck() ); 9103 ins_pipe(partial_subtype_check_pipe); 9104 %} 9105 9106 instruct partialSubtypeCheck_vs_zero( flagsRegP pcc, o1RegP sub, o2RegP super, immP0 zero, o0RegP idx, o7RegP o7 ) %{ 9107 match(Set pcc (CmpP (PartialSubtypeCheck sub super) zero)); 9108 effect( KILL idx, KILL o7 ); 9109 ins_cost(DEFAULT_COST*10); 9110 format %{ "CALL PartialSubtypeCheck\n\tNOP\t# (sets condition codes)" %} 9111 ins_encode( enc_PartialSubtypeCheck() ); 9112 ins_pipe(partial_subtype_check_pipe); 9113 %} 9114 9115 9116 // ============================================================================ 9117 // inlined locking and unlocking 9118 9119 instruct cmpFastLock(flagsRegP pcc, iRegP object, iRegP box, iRegP scratch2, o7RegP scratch ) %{ 9120 match(Set pcc (FastLock object box)); 9121 9122 effect(KILL scratch, TEMP scratch2); 9123 ins_cost(100); 9124 9125 size(4*112); // conservative overestimation ... 9126 format %{ "FASTLOCK $object, $box; KILL $scratch, $scratch2, $box" %} 9127 ins_encode( Fast_Lock(object, box, scratch, scratch2) ); 9128 ins_pipe(long_memory_op); 9129 %} 9130 9131 9132 instruct cmpFastUnlock(flagsRegP pcc, iRegP object, iRegP box, iRegP scratch2, o7RegP scratch ) %{ 9133 match(Set pcc (FastUnlock object box)); 9134 effect(KILL scratch, TEMP scratch2); 9135 ins_cost(100); 9136 9137 size(4*120); // conservative overestimation ... 9138 format %{ "FASTUNLOCK $object, $box; KILL $scratch, $scratch2, $box" %} 9139 ins_encode( Fast_Unlock(object, box, scratch, scratch2) ); 9140 ins_pipe(long_memory_op); 9141 %} 9142 9143 // Count and Base registers are fixed because the allocator cannot 9144 // kill unknown registers. The encodings are generic. 9145 instruct clear_array(iRegX cnt, iRegP base, iRegX temp, Universe dummy, flagsReg ccr) %{ 9146 match(Set dummy (ClearArray cnt base)); 9147 effect(TEMP temp, KILL ccr); 9148 ins_cost(300); 9149 format %{ "MOV $cnt,$temp\n" 9150 "loop: SUBcc $temp,8,$temp\t! Count down a dword of bytes\n" 9151 " BRge loop\t\t! Clearing loop\n" 9152 " STX G0,[$base+$temp]\t! delay slot" %} 9153 ins_encode( enc_Clear_Array(cnt, base, temp) ); 9154 ins_pipe(long_memory_op); 9155 %} 9156 9157 instruct string_compare(o0RegP str1, o1RegP str2, g3RegP tmp1, g4RegP tmp2, notemp_iRegI result, 9158 o7RegI tmp3, flagsReg ccr) %{ 9159 match(Set result (StrComp str1 str2)); 9160 effect(USE_KILL str1, USE_KILL str2, KILL tmp1, KILL tmp2, KILL ccr, KILL tmp3); 9161 ins_cost(300); 9162 format %{ "String Compare $str1,$str2 -> $result" %} 9163 ins_encode( enc_String_Compare(str1, str2, tmp1, tmp2, result) ); 9164 ins_pipe(long_memory_op); 9165 %} 9166 9167 instruct string_equals(o0RegP str1, o1RegP str2, g3RegP tmp1, g4RegP tmp2, notemp_iRegI result, 9168 o7RegI tmp3, flagsReg ccr) %{ 9169 match(Set result (StrEquals str1 str2)); 9170 effect(USE_KILL str1, USE_KILL str2, KILL tmp1, KILL tmp2, KILL ccr, KILL tmp3); 9171 ins_cost(300); 9172 format %{ "String Equals $str1,$str2 -> $result" %} 9173 ins_encode( enc_String_Equals(str1, str2, tmp1, tmp2, result) ); 9174 ins_pipe(long_memory_op); 9175 %} 9176 9177 instruct array_equals(o0RegP ary1, o1RegP ary2, g3RegP tmp1, g4RegP tmp2, notemp_iRegI result, 9178 flagsReg ccr) %{ 9179 match(Set result (AryEq ary1 ary2)); 9180 effect(USE_KILL ary1, USE_KILL ary2, KILL tmp1, KILL tmp2, KILL ccr); 9181 ins_cost(300); 9182 format %{ "Array Equals $ary1,$ary2 -> $result" %} 9183 ins_encode( enc_Array_Equals(ary1, ary2, tmp1, tmp2, result)); 9184 ins_pipe(long_memory_op); 9185 %} 9186 9187 //---------- Population Count Instructions ------------------------------------- 9188 9189 instruct popCountI(iRegI dst, iRegI src) %{ 9190 predicate(UsePopCountInstruction); 9191 match(Set dst (PopCountI src)); 9192 9193 format %{ "POPC $src, $dst" %} 9194 ins_encode %{ 9195 __ popc($src$$Register, $dst$$Register); 9196 %} 9197 ins_pipe(ialu_reg); 9198 %} 9199 9200 // Note: Long.bitCount(long) returns an int. 9201 instruct popCountL(iRegI dst, iRegL src) %{ 9202 predicate(UsePopCountInstruction); 9203 match(Set dst (PopCountL src)); 9204 9205 format %{ "POPC $src, $dst" %} 9206 ins_encode %{ 9207 __ popc($src$$Register, $dst$$Register); 9208 %} 9209 ins_pipe(ialu_reg); 9210 %} 9211 9212 9213 // ============================================================================ 9214 //------------Bytes reverse-------------------------------------------------- 9215 9216 instruct bytes_reverse_int(iRegI dst, stackSlotI src) %{ 9217 match(Set dst (ReverseBytesI src)); 9218 effect(DEF dst, USE src); 9219 9220 // Op cost is artificially doubled to make sure that load or store 9221 // instructions are preferred over this one which requires a spill 9222 // onto a stack slot. 9223 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST); 9224 size(8); 9225 format %{ "LDUWA $src, $dst\t!asi=primary_little" %} 9226 opcode(Assembler::lduwa_op3); 9227 ins_encode( form3_mem_reg_little(src, dst) ); 9228 ins_pipe( iload_mem ); 9229 %} 9230 9231 instruct bytes_reverse_long(iRegL dst, stackSlotL src) %{ 9232 match(Set dst (ReverseBytesL src)); 9233 effect(DEF dst, USE src); 9234 9235 // Op cost is artificially doubled to make sure that load or store 9236 // instructions are preferred over this one which requires a spill 9237 // onto a stack slot. 9238 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST); 9239 size(8); 9240 format %{ "LDXA $src, $dst\t!asi=primary_little" %} 9241 9242 opcode(Assembler::ldxa_op3); 9243 ins_encode( form3_mem_reg_little(src, dst) ); 9244 ins_pipe( iload_mem ); 9245 %} 9246 9247 // Load Integer reversed byte order 9248 instruct loadI_reversed(iRegI dst, memory src) %{ 9249 match(Set dst (ReverseBytesI (LoadI src))); 9250 9251 ins_cost(DEFAULT_COST + MEMORY_REF_COST); 9252 size(8); 9253 format %{ "LDUWA $src, $dst\t!asi=primary_little" %} 9254 9255 opcode(Assembler::lduwa_op3); 9256 ins_encode( form3_mem_reg_little( src, dst) ); 9257 ins_pipe(iload_mem); 9258 %} 9259 9260 // Load Long - aligned and reversed 9261 instruct loadL_reversed(iRegL dst, memory src) %{ 9262 match(Set dst (ReverseBytesL (LoadL src))); 9263 9264 ins_cost(DEFAULT_COST + MEMORY_REF_COST); 9265 size(8); 9266 format %{ "LDXA $src, $dst\t!asi=primary_little" %} 9267 9268 opcode(Assembler::ldxa_op3); 9269 ins_encode( form3_mem_reg_little( src, dst ) ); 9270 ins_pipe(iload_mem); 9271 %} 9272 9273 // Store Integer reversed byte order 9274 instruct storeI_reversed(memory dst, iRegI src) %{ 9275 match(Set dst (StoreI dst (ReverseBytesI src))); 9276 9277 ins_cost(MEMORY_REF_COST); 9278 size(8); 9279 format %{ "STWA $src, $dst\t!asi=primary_little" %} 9280 9281 opcode(Assembler::stwa_op3); 9282 ins_encode( form3_mem_reg_little( dst, src) ); 9283 ins_pipe(istore_mem_reg); 9284 %} 9285 9286 // Store Long reversed byte order 9287 instruct storeL_reversed(memory dst, iRegL src) %{ 9288 match(Set dst (StoreL dst (ReverseBytesL src))); 9289 9290 ins_cost(MEMORY_REF_COST); 9291 size(8); 9292 format %{ "STXA $src, $dst\t!asi=primary_little" %} 9293 9294 opcode(Assembler::stxa_op3); 9295 ins_encode( form3_mem_reg_little( dst, src) ); 9296 ins_pipe(istore_mem_reg); 9297 %} 9298 9299 //----------PEEPHOLE RULES----------------------------------------------------- 9300 // These must follow all instruction definitions as they use the names 9301 // defined in the instructions definitions. 9302 // 9303 // peepmatch ( root_instr_name [preceding_instruction]* ); 9304 // 9305 // peepconstraint %{ 9306 // (instruction_number.operand_name relational_op instruction_number.operand_name 9307 // [, ...] ); 9308 // // instruction numbers are zero-based using left to right order in peepmatch 9309 // 9310 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) ); 9311 // // provide an instruction_number.operand_name for each operand that appears 9312 // // in the replacement instruction's match rule 9313 // 9314 // ---------VM FLAGS--------------------------------------------------------- 9315 // 9316 // All peephole optimizations can be turned off using -XX:-OptoPeephole 9317 // 9318 // Each peephole rule is given an identifying number starting with zero and 9319 // increasing by one in the order seen by the parser. An individual peephole 9320 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=# 9321 // on the command-line. 9322 // 9323 // ---------CURRENT LIMITATIONS---------------------------------------------- 9324 // 9325 // Only match adjacent instructions in same basic block 9326 // Only equality constraints 9327 // Only constraints between operands, not (0.dest_reg == EAX_enc) 9328 // Only one replacement instruction 9329 // 9330 // ---------EXAMPLE---------------------------------------------------------- 9331 // 9332 // // pertinent parts of existing instructions in architecture description 9333 // instruct movI(eRegI dst, eRegI src) %{ 9334 // match(Set dst (CopyI src)); 9335 // %} 9336 // 9337 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{ 9338 // match(Set dst (AddI dst src)); 9339 // effect(KILL cr); 9340 // %} 9341 // 9342 // // Change (inc mov) to lea 9343 // peephole %{ 9344 // // increment preceeded by register-register move 9345 // peepmatch ( incI_eReg movI ); 9346 // // require that the destination register of the increment 9347 // // match the destination register of the move 9348 // peepconstraint ( 0.dst == 1.dst ); 9349 // // construct a replacement instruction that sets 9350 // // the destination to ( move's source register + one ) 9351 // peepreplace ( incI_eReg_immI1( 0.dst 1.src 0.src ) ); 9352 // %} 9353 // 9354 9355 // // Change load of spilled value to only a spill 9356 // instruct storeI(memory mem, eRegI src) %{ 9357 // match(Set mem (StoreI mem src)); 9358 // %} 9359 // 9360 // instruct loadI(eRegI dst, memory mem) %{ 9361 // match(Set dst (LoadI mem)); 9362 // %} 9363 // 9364 // peephole %{ 9365 // peepmatch ( loadI storeI ); 9366 // peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem ); 9367 // peepreplace ( storeI( 1.mem 1.mem 1.src ) ); 9368 // %} 9369 9370 //----------SMARTSPILL RULES--------------------------------------------------- 9371 // These must follow all instruction definitions as they use the names 9372 // defined in the instructions definitions. 9373 // 9374 // SPARC will probably not have any of these rules due to RISC instruction set. 9375 9376 //----------PIPELINE----------------------------------------------------------- 9377 // Rules which define the behavior of the target architectures pipeline.