1 //
2 // Copyright 1998-2009 Sun Microsystems, Inc. All Rights Reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
9 // This code is distributed in the hope that it will be useful, but WITHOUT
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
15 // You should have received a copy of the GNU General Public License version
16 // 2 along with this work; if not, write to the Free Software Foundation,
17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 //
19 // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
20 // CA 95054 USA or visit www.sun.com if you need additional information or
21 // have any questions.
22 //
23 //
24
25 // SPARC Architecture Description File
26
27 //----------REGISTER DEFINITION BLOCK------------------------------------------
28 // This information is used by the matcher and the register allocator to
29 // describe individual registers and classes of registers within the target
30 // archtecture.
31 register %{
32 //----------Architecture Description Register Definitions----------------------
33 // General Registers
34 // "reg_def" name ( register save type, C convention save type,
35 // ideal register type, encoding, vm name );
36 // Register Save Types:
37 //
38 // NS = No-Save: The register allocator assumes that these registers
39 // can be used without saving upon entry to the method, &
40 // that they do not need to be saved at call sites.
41 //
42 // SOC = Save-On-Call: The register allocator assumes that these registers
43 // can be used without saving upon entry to the method,
44 // but that they must be saved at call sites.
45 //
46 // SOE = Save-On-Entry: The register allocator assumes that these registers
47 // must be saved before using them upon entry to the
48 // method, but they do not need to be saved at call
49 // sites.
50 //
51 // AS = Always-Save: The register allocator assumes that these registers
52 // must be saved before using them upon entry to the
53 // method, & that they must be saved at call sites.
54 //
55 // Ideal Register Type is used to determine how to save & restore a
56 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
57 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
58 //
59 // The encoding number is the actual bit-pattern placed into the opcodes.
60
61
62 // ----------------------------
63 // Integer/Long Registers
64 // ----------------------------
65
66 // Need to expose the hi/lo aspect of 64-bit registers
67 // This register set is used for both the 64-bit build and
68 // the 32-bit build with 1-register longs.
69
70 // Global Registers 0-7
71 reg_def R_G0H( NS, NS, Op_RegI,128, G0->as_VMReg()->next());
72 reg_def R_G0 ( NS, NS, Op_RegI, 0, G0->as_VMReg());
73 reg_def R_G1H(SOC, SOC, Op_RegI,129, G1->as_VMReg()->next());
74 reg_def R_G1 (SOC, SOC, Op_RegI, 1, G1->as_VMReg());
75 reg_def R_G2H( NS, NS, Op_RegI,130, G2->as_VMReg()->next());
76 reg_def R_G2 ( NS, NS, Op_RegI, 2, G2->as_VMReg());
77 reg_def R_G3H(SOC, SOC, Op_RegI,131, G3->as_VMReg()->next());
78 reg_def R_G3 (SOC, SOC, Op_RegI, 3, G3->as_VMReg());
79 reg_def R_G4H(SOC, SOC, Op_RegI,132, G4->as_VMReg()->next());
80 reg_def R_G4 (SOC, SOC, Op_RegI, 4, G4->as_VMReg());
81 reg_def R_G5H(SOC, SOC, Op_RegI,133, G5->as_VMReg()->next());
82 reg_def R_G5 (SOC, SOC, Op_RegI, 5, G5->as_VMReg());
83 reg_def R_G6H( NS, NS, Op_RegI,134, G6->as_VMReg()->next());
84 reg_def R_G6 ( NS, NS, Op_RegI, 6, G6->as_VMReg());
85 reg_def R_G7H( NS, NS, Op_RegI,135, G7->as_VMReg()->next());
86 reg_def R_G7 ( NS, NS, Op_RegI, 7, G7->as_VMReg());
87
88 // Output Registers 0-7
89 reg_def R_O0H(SOC, SOC, Op_RegI,136, O0->as_VMReg()->next());
90 reg_def R_O0 (SOC, SOC, Op_RegI, 8, O0->as_VMReg());
91 reg_def R_O1H(SOC, SOC, Op_RegI,137, O1->as_VMReg()->next());
92 reg_def R_O1 (SOC, SOC, Op_RegI, 9, O1->as_VMReg());
93 reg_def R_O2H(SOC, SOC, Op_RegI,138, O2->as_VMReg()->next());
94 reg_def R_O2 (SOC, SOC, Op_RegI, 10, O2->as_VMReg());
95 reg_def R_O3H(SOC, SOC, Op_RegI,139, O3->as_VMReg()->next());
96 reg_def R_O3 (SOC, SOC, Op_RegI, 11, O3->as_VMReg());
97 reg_def R_O4H(SOC, SOC, Op_RegI,140, O4->as_VMReg()->next());
98 reg_def R_O4 (SOC, SOC, Op_RegI, 12, O4->as_VMReg());
99 reg_def R_O5H(SOC, SOC, Op_RegI,141, O5->as_VMReg()->next());
100 reg_def R_O5 (SOC, SOC, Op_RegI, 13, O5->as_VMReg());
101 reg_def R_SPH( NS, NS, Op_RegI,142, SP->as_VMReg()->next());
102 reg_def R_SP ( NS, NS, Op_RegI, 14, SP->as_VMReg());
103 reg_def R_O7H(SOC, SOC, Op_RegI,143, O7->as_VMReg()->next());
104 reg_def R_O7 (SOC, SOC, Op_RegI, 15, O7->as_VMReg());
105
106 // Local Registers 0-7
107 reg_def R_L0H( NS, NS, Op_RegI,144, L0->as_VMReg()->next());
108 reg_def R_L0 ( NS, NS, Op_RegI, 16, L0->as_VMReg());
109 reg_def R_L1H( NS, NS, Op_RegI,145, L1->as_VMReg()->next());
110 reg_def R_L1 ( NS, NS, Op_RegI, 17, L1->as_VMReg());
111 reg_def R_L2H( NS, NS, Op_RegI,146, L2->as_VMReg()->next());
112 reg_def R_L2 ( NS, NS, Op_RegI, 18, L2->as_VMReg());
113 reg_def R_L3H( NS, NS, Op_RegI,147, L3->as_VMReg()->next());
114 reg_def R_L3 ( NS, NS, Op_RegI, 19, L3->as_VMReg());
115 reg_def R_L4H( NS, NS, Op_RegI,148, L4->as_VMReg()->next());
116 reg_def R_L4 ( NS, NS, Op_RegI, 20, L4->as_VMReg());
117 reg_def R_L5H( NS, NS, Op_RegI,149, L5->as_VMReg()->next());
118 reg_def R_L5 ( NS, NS, Op_RegI, 21, L5->as_VMReg());
119 reg_def R_L6H( NS, NS, Op_RegI,150, L6->as_VMReg()->next());
120 reg_def R_L6 ( NS, NS, Op_RegI, 22, L6->as_VMReg());
121 reg_def R_L7H( NS, NS, Op_RegI,151, L7->as_VMReg()->next());
122 reg_def R_L7 ( NS, NS, Op_RegI, 23, L7->as_VMReg());
123
124 // Input Registers 0-7
125 reg_def R_I0H( NS, NS, Op_RegI,152, I0->as_VMReg()->next());
126 reg_def R_I0 ( NS, NS, Op_RegI, 24, I0->as_VMReg());
127 reg_def R_I1H( NS, NS, Op_RegI,153, I1->as_VMReg()->next());
128 reg_def R_I1 ( NS, NS, Op_RegI, 25, I1->as_VMReg());
129 reg_def R_I2H( NS, NS, Op_RegI,154, I2->as_VMReg()->next());
130 reg_def R_I2 ( NS, NS, Op_RegI, 26, I2->as_VMReg());
131 reg_def R_I3H( NS, NS, Op_RegI,155, I3->as_VMReg()->next());
132 reg_def R_I3 ( NS, NS, Op_RegI, 27, I3->as_VMReg());
133 reg_def R_I4H( NS, NS, Op_RegI,156, I4->as_VMReg()->next());
134 reg_def R_I4 ( NS, NS, Op_RegI, 28, I4->as_VMReg());
135 reg_def R_I5H( NS, NS, Op_RegI,157, I5->as_VMReg()->next());
136 reg_def R_I5 ( NS, NS, Op_RegI, 29, I5->as_VMReg());
137 reg_def R_FPH( NS, NS, Op_RegI,158, FP->as_VMReg()->next());
138 reg_def R_FP ( NS, NS, Op_RegI, 30, FP->as_VMReg());
139 reg_def R_I7H( NS, NS, Op_RegI,159, I7->as_VMReg()->next());
140 reg_def R_I7 ( NS, NS, Op_RegI, 31, I7->as_VMReg());
141
142 // ----------------------------
143 // Float/Double Registers
144 // ----------------------------
145
146 // Float Registers
147 reg_def R_F0 ( SOC, SOC, Op_RegF, 0, F0->as_VMReg());
148 reg_def R_F1 ( SOC, SOC, Op_RegF, 1, F1->as_VMReg());
149 reg_def R_F2 ( SOC, SOC, Op_RegF, 2, F2->as_VMReg());
150 reg_def R_F3 ( SOC, SOC, Op_RegF, 3, F3->as_VMReg());
151 reg_def R_F4 ( SOC, SOC, Op_RegF, 4, F4->as_VMReg());
152 reg_def R_F5 ( SOC, SOC, Op_RegF, 5, F5->as_VMReg());
153 reg_def R_F6 ( SOC, SOC, Op_RegF, 6, F6->as_VMReg());
154 reg_def R_F7 ( SOC, SOC, Op_RegF, 7, F7->as_VMReg());
155 reg_def R_F8 ( SOC, SOC, Op_RegF, 8, F8->as_VMReg());
156 reg_def R_F9 ( SOC, SOC, Op_RegF, 9, F9->as_VMReg());
157 reg_def R_F10( SOC, SOC, Op_RegF, 10, F10->as_VMReg());
158 reg_def R_F11( SOC, SOC, Op_RegF, 11, F11->as_VMReg());
159 reg_def R_F12( SOC, SOC, Op_RegF, 12, F12->as_VMReg());
160 reg_def R_F13( SOC, SOC, Op_RegF, 13, F13->as_VMReg());
161 reg_def R_F14( SOC, SOC, Op_RegF, 14, F14->as_VMReg());
162 reg_def R_F15( SOC, SOC, Op_RegF, 15, F15->as_VMReg());
163 reg_def R_F16( SOC, SOC, Op_RegF, 16, F16->as_VMReg());
164 reg_def R_F17( SOC, SOC, Op_RegF, 17, F17->as_VMReg());
165 reg_def R_F18( SOC, SOC, Op_RegF, 18, F18->as_VMReg());
166 reg_def R_F19( SOC, SOC, Op_RegF, 19, F19->as_VMReg());
167 reg_def R_F20( SOC, SOC, Op_RegF, 20, F20->as_VMReg());
168 reg_def R_F21( SOC, SOC, Op_RegF, 21, F21->as_VMReg());
169 reg_def R_F22( SOC, SOC, Op_RegF, 22, F22->as_VMReg());
170 reg_def R_F23( SOC, SOC, Op_RegF, 23, F23->as_VMReg());
171 reg_def R_F24( SOC, SOC, Op_RegF, 24, F24->as_VMReg());
172 reg_def R_F25( SOC, SOC, Op_RegF, 25, F25->as_VMReg());
173 reg_def R_F26( SOC, SOC, Op_RegF, 26, F26->as_VMReg());
174 reg_def R_F27( SOC, SOC, Op_RegF, 27, F27->as_VMReg());
175 reg_def R_F28( SOC, SOC, Op_RegF, 28, F28->as_VMReg());
176 reg_def R_F29( SOC, SOC, Op_RegF, 29, F29->as_VMReg());
177 reg_def R_F30( SOC, SOC, Op_RegF, 30, F30->as_VMReg());
178 reg_def R_F31( SOC, SOC, Op_RegF, 31, F31->as_VMReg());
179
180 // Double Registers
181 // The rules of ADL require that double registers be defined in pairs.
182 // Each pair must be two 32-bit values, but not necessarily a pair of
183 // single float registers. In each pair, ADLC-assigned register numbers
184 // must be adjacent, with the lower number even. Finally, when the
185 // CPU stores such a register pair to memory, the word associated with
186 // the lower ADLC-assigned number must be stored to the lower address.
187
188 // These definitions specify the actual bit encodings of the sparc
189 // double fp register numbers. FloatRegisterImpl in register_sparc.hpp
190 // wants 0-63, so we have to convert every time we want to use fp regs
191 // with the macroassembler, using reg_to_DoubleFloatRegister_object().
192 // 255 is a flag meaning "don't go here".
193 // I believe we can't handle callee-save doubles D32 and up until
194 // the place in the sparc stack crawler that asserts on the 255 is
195 // fixed up.
196 reg_def R_D32x(SOC, SOC, Op_RegD,255, F32->as_VMReg());
197 reg_def R_D32 (SOC, SOC, Op_RegD, 1, F32->as_VMReg()->next());
198 reg_def R_D34x(SOC, SOC, Op_RegD,255, F34->as_VMReg());
199 reg_def R_D34 (SOC, SOC, Op_RegD, 3, F34->as_VMReg()->next());
200 reg_def R_D36x(SOC, SOC, Op_RegD,255, F36->as_VMReg());
201 reg_def R_D36 (SOC, SOC, Op_RegD, 5, F36->as_VMReg()->next());
202 reg_def R_D38x(SOC, SOC, Op_RegD,255, F38->as_VMReg());
203 reg_def R_D38 (SOC, SOC, Op_RegD, 7, F38->as_VMReg()->next());
204 reg_def R_D40x(SOC, SOC, Op_RegD,255, F40->as_VMReg());
205 reg_def R_D40 (SOC, SOC, Op_RegD, 9, F40->as_VMReg()->next());
206 reg_def R_D42x(SOC, SOC, Op_RegD,255, F42->as_VMReg());
207 reg_def R_D42 (SOC, SOC, Op_RegD, 11, F42->as_VMReg()->next());
208 reg_def R_D44x(SOC, SOC, Op_RegD,255, F44->as_VMReg());
209 reg_def R_D44 (SOC, SOC, Op_RegD, 13, F44->as_VMReg()->next());
210 reg_def R_D46x(SOC, SOC, Op_RegD,255, F46->as_VMReg());
211 reg_def R_D46 (SOC, SOC, Op_RegD, 15, F46->as_VMReg()->next());
212 reg_def R_D48x(SOC, SOC, Op_RegD,255, F48->as_VMReg());
213 reg_def R_D48 (SOC, SOC, Op_RegD, 17, F48->as_VMReg()->next());
214 reg_def R_D50x(SOC, SOC, Op_RegD,255, F50->as_VMReg());
215 reg_def R_D50 (SOC, SOC, Op_RegD, 19, F50->as_VMReg()->next());
216 reg_def R_D52x(SOC, SOC, Op_RegD,255, F52->as_VMReg());
217 reg_def R_D52 (SOC, SOC, Op_RegD, 21, F52->as_VMReg()->next());
218 reg_def R_D54x(SOC, SOC, Op_RegD,255, F54->as_VMReg());
219 reg_def R_D54 (SOC, SOC, Op_RegD, 23, F54->as_VMReg()->next());
220 reg_def R_D56x(SOC, SOC, Op_RegD,255, F56->as_VMReg());
221 reg_def R_D56 (SOC, SOC, Op_RegD, 25, F56->as_VMReg()->next());
222 reg_def R_D58x(SOC, SOC, Op_RegD,255, F58->as_VMReg());
223 reg_def R_D58 (SOC, SOC, Op_RegD, 27, F58->as_VMReg()->next());
224 reg_def R_D60x(SOC, SOC, Op_RegD,255, F60->as_VMReg());
225 reg_def R_D60 (SOC, SOC, Op_RegD, 29, F60->as_VMReg()->next());
226 reg_def R_D62x(SOC, SOC, Op_RegD,255, F62->as_VMReg());
227 reg_def R_D62 (SOC, SOC, Op_RegD, 31, F62->as_VMReg()->next());
228
229
230 // ----------------------------
231 // Special Registers
232 // Condition Codes Flag Registers
233 // I tried to break out ICC and XCC but it's not very pretty.
234 // Every Sparc instruction which defs/kills one also kills the other.
235 // Hence every compare instruction which defs one kind of flags ends
236 // up needing a kill of the other.
237 reg_def CCR (SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad());
238
239 reg_def FCC0(SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad());
240 reg_def FCC1(SOC, SOC, Op_RegFlags, 1, VMRegImpl::Bad());
241 reg_def FCC2(SOC, SOC, Op_RegFlags, 2, VMRegImpl::Bad());
242 reg_def FCC3(SOC, SOC, Op_RegFlags, 3, VMRegImpl::Bad());
243
244 // ----------------------------
245 // Specify the enum values for the registers. These enums are only used by the
246 // OptoReg "class". We can convert these enum values at will to VMReg when needed
247 // for visibility to the rest of the vm. The order of this enum influences the
248 // register allocator so having the freedom to set this order and not be stuck
249 // with the order that is natural for the rest of the vm is worth it.
250 alloc_class chunk0(
251 R_L0,R_L0H, R_L1,R_L1H, R_L2,R_L2H, R_L3,R_L3H, R_L4,R_L4H, R_L5,R_L5H, R_L6,R_L6H, R_L7,R_L7H,
252 R_G0,R_G0H, R_G1,R_G1H, R_G2,R_G2H, R_G3,R_G3H, R_G4,R_G4H, R_G5,R_G5H, R_G6,R_G6H, R_G7,R_G7H,
253 R_O7,R_O7H, R_SP,R_SPH, R_O0,R_O0H, R_O1,R_O1H, R_O2,R_O2H, R_O3,R_O3H, R_O4,R_O4H, R_O5,R_O5H,
254 R_I0,R_I0H, R_I1,R_I1H, R_I2,R_I2H, R_I3,R_I3H, R_I4,R_I4H, R_I5,R_I5H, R_FP,R_FPH, R_I7,R_I7H);
255
256 // Note that a register is not allocatable unless it is also mentioned
257 // in a widely-used reg_class below. Thus, R_G7 and R_G0 are outside i_reg.
258
259 alloc_class chunk1(
260 // The first registers listed here are those most likely to be used
261 // as temporaries. We move F0..F7 away from the front of the list,
262 // to reduce the likelihood of interferences with parameters and
263 // return values. Likewise, we avoid using F0/F1 for parameters,
264 // since they are used for return values.
265 // This FPU fine-tuning is worth about 1% on the SPEC geomean.
266 R_F8 ,R_F9 ,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
267 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,
268 R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,R_F30,R_F31,
269 R_F0 ,R_F1 ,R_F2 ,R_F3 ,R_F4 ,R_F5 ,R_F6 ,R_F7 , // used for arguments and return values
270 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,
271 R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x,
272 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,
273 R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x);
274
275 alloc_class chunk2(CCR, FCC0, FCC1, FCC2, FCC3);
276
277 //----------Architecture Description Register Classes--------------------------
278 // Several register classes are automatically defined based upon information in
279 // this architecture description.
280 // 1) reg_class inline_cache_reg ( as defined in frame section )
281 // 2) reg_class interpreter_method_oop_reg ( as defined in frame section )
282 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
283 //
284
285 // G0 is not included in integer class since it has special meaning.
286 reg_class g0_reg(R_G0);
287
288 // ----------------------------
289 // Integer Register Classes
290 // ----------------------------
291 // Exclusions from i_reg:
292 // R_G0: hardwired zero
293 // R_G2: reserved by HotSpot to the TLS register (invariant within Java)
294 // R_G6: reserved by Solaris ABI to tools
295 // R_G7: reserved by Solaris ABI to libthread
296 // R_O7: Used as a temp in many encodings
297 reg_class int_reg(R_G1,R_G3,R_G4,R_G5,R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
298
299 // Class for all integer registers, except the G registers. This is used for
300 // encodings which use G registers as temps. The regular inputs to such
301 // instructions use a "notemp_" prefix, as a hack to ensure that the allocator
302 // will not put an input into a temp register.
303 reg_class notemp_int_reg(R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
304
305 reg_class g1_regI(R_G1);
306 reg_class g3_regI(R_G3);
307 reg_class g4_regI(R_G4);
308 reg_class o0_regI(R_O0);
309 reg_class o7_regI(R_O7);
310
311 // ----------------------------
312 // Pointer Register Classes
313 // ----------------------------
314 #ifdef _LP64
315 // 64-bit build means 64-bit pointers means hi/lo pairs
316 reg_class ptr_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5,
317 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5,
318 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
319 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 );
320 // Lock encodings use G3 and G4 internally
321 reg_class lock_ptr_reg( R_G1H,R_G1, R_G5H,R_G5,
322 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5,
323 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
324 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 );
325 // Special class for storeP instructions, which can store SP or RPC to TLS.
326 // It is also used for memory addressing, allowing direct TLS addressing.
327 reg_class sp_ptr_reg( R_G1H,R_G1, R_G2H,R_G2, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5,
328 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, R_SPH,R_SP,
329 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
330 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5, R_FPH,R_FP );
331 // R_L7 is the lowest-priority callee-save (i.e., NS) register
332 // We use it to save R_G2 across calls out of Java.
333 reg_class l7_regP(R_L7H,R_L7);
334
335 // Other special pointer regs
336 reg_class g1_regP(R_G1H,R_G1);
337 reg_class g2_regP(R_G2H,R_G2);
338 reg_class g3_regP(R_G3H,R_G3);
339 reg_class g4_regP(R_G4H,R_G4);
340 reg_class g5_regP(R_G5H,R_G5);
341 reg_class i0_regP(R_I0H,R_I0);
342 reg_class o0_regP(R_O0H,R_O0);
343 reg_class o1_regP(R_O1H,R_O1);
344 reg_class o2_regP(R_O2H,R_O2);
345 reg_class o7_regP(R_O7H,R_O7);
346
347 #else // _LP64
348 // 32-bit build means 32-bit pointers means 1 register.
349 reg_class ptr_reg( R_G1, R_G3,R_G4,R_G5,
350 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,
351 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
352 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
353 // Lock encodings use G3 and G4 internally
354 reg_class lock_ptr_reg(R_G1, R_G5,
355 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,
356 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
357 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
358 // Special class for storeP instructions, which can store SP or RPC to TLS.
359 // It is also used for memory addressing, allowing direct TLS addressing.
360 reg_class sp_ptr_reg( R_G1,R_G2,R_G3,R_G4,R_G5,
361 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_SP,
362 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
363 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5,R_FP);
364 // R_L7 is the lowest-priority callee-save (i.e., NS) register
365 // We use it to save R_G2 across calls out of Java.
366 reg_class l7_regP(R_L7);
367
368 // Other special pointer regs
369 reg_class g1_regP(R_G1);
370 reg_class g2_regP(R_G2);
371 reg_class g3_regP(R_G3);
372 reg_class g4_regP(R_G4);
373 reg_class g5_regP(R_G5);
374 reg_class i0_regP(R_I0);
375 reg_class o0_regP(R_O0);
376 reg_class o1_regP(R_O1);
377 reg_class o2_regP(R_O2);
378 reg_class o7_regP(R_O7);
379 #endif // _LP64
380
381
382 // ----------------------------
383 // Long Register Classes
384 // ----------------------------
385 // Longs in 1 register. Aligned adjacent hi/lo pairs.
386 // Note: O7 is never in this class; it is sometimes used as an encoding temp.
387 reg_class long_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5
388 ,R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5
389 #ifdef _LP64
390 // 64-bit, longs in 1 register: use all 64-bit integer registers
391 // 32-bit, longs in 1 register: cannot use I's and L's. Restrict to O's and G's.
392 ,R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7
393 ,R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5
394 #endif // _LP64
395 );
396
397 reg_class g1_regL(R_G1H,R_G1);
398 reg_class g3_regL(R_G3H,R_G3);
399 reg_class o2_regL(R_O2H,R_O2);
400 reg_class o7_regL(R_O7H,R_O7);
401
402 // ----------------------------
403 // Special Class for Condition Code Flags Register
404 reg_class int_flags(CCR);
405 reg_class float_flags(FCC0,FCC1,FCC2,FCC3);
406 reg_class float_flag0(FCC0);
407
408
409 // ----------------------------
410 // Float Point Register Classes
411 // ----------------------------
412 // Skip F30/F31, they are reserved for mem-mem copies
413 reg_class sflt_reg(R_F0,R_F1,R_F2,R_F3,R_F4,R_F5,R_F6,R_F7,R_F8,R_F9,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29);
414
415 // Paired floating point registers--they show up in the same order as the floats,
416 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs.
417 reg_class dflt_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
418 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,
419 /* Use extra V9 double registers; this AD file does not support V8 */
420 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x,
421 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x
422 );
423
424 // Paired floating point registers--they show up in the same order as the floats,
425 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs.
426 // This class is usable for mis-aligned loads as happen in I2C adapters.
427 reg_class dflt_low_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
428 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,R_F30,R_F31 );
429 %}
430
431 //----------DEFINITION BLOCK---------------------------------------------------
432 // Define name --> value mappings to inform the ADLC of an integer valued name
433 // Current support includes integer values in the range [0, 0x7FFFFFFF]
434 // Format:
435 // int_def <name> ( <int_value>, <expression>);
436 // Generated Code in ad_<arch>.hpp
437 // #define <name> (<expression>)
438 // // value == <int_value>
439 // Generated code in ad_<arch>.cpp adlc_verification()
440 // assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>");
441 //
442 definitions %{
443 // The default cost (of an ALU instruction).
444 int_def DEFAULT_COST ( 100, 100);
445 int_def HUGE_COST (1000000, 1000000);
446
447 // Memory refs are twice as expensive as run-of-the-mill.
448 int_def MEMORY_REF_COST ( 200, DEFAULT_COST * 2);
449
450 // Branches are even more expensive.
451 int_def BRANCH_COST ( 300, DEFAULT_COST * 3);
452 int_def CALL_COST ( 300, DEFAULT_COST * 3);
453 %}
454
455
456 //----------SOURCE BLOCK-------------------------------------------------------
457 // This is a block of C++ code which provides values, functions, and
458 // definitions necessary in the rest of the architecture description
459 source_hpp %{
460 // Must be visible to the DFA in dfa_sparc.cpp
461 extern bool can_branch_register( Node *bol, Node *cmp );
462
463 // Macros to extract hi & lo halves from a long pair.
464 // G0 is not part of any long pair, so assert on that.
465 // Prevents accidentally using G1 instead of G0.
466 #define LONG_HI_REG(x) (x)
467 #define LONG_LO_REG(x) (x)
468
469 %}
470
471 source %{
472 #define __ _masm.
473
474 // tertiary op of a LoadP or StoreP encoding
475 #define REGP_OP true
476
477 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding);
478 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding);
479 static Register reg_to_register_object(int register_encoding);
480
481 // Used by the DFA in dfa_sparc.cpp.
482 // Check for being able to use a V9 branch-on-register. Requires a
483 // compare-vs-zero, equal/not-equal, of a value which was zero- or sign-
484 // extended. Doesn't work following an integer ADD, for example, because of
485 // overflow (-1 incremented yields 0 plus a carry in the high-order word). On
486 // 32-bit V9 systems, interrupts currently blow away the high-order 32 bits and
487 // replace them with zero, which could become sign-extension in a different OS
488 // release. There's no obvious reason why an interrupt will ever fill these
489 // bits with non-zero junk (the registers are reloaded with standard LD
490 // instructions which either zero-fill or sign-fill).
491 bool can_branch_register( Node *bol, Node *cmp ) {
492 if( !BranchOnRegister ) return false;
493 #ifdef _LP64
494 if( cmp->Opcode() == Op_CmpP )
495 return true; // No problems with pointer compares
496 #endif
497 if( cmp->Opcode() == Op_CmpL )
498 return true; // No problems with long compares
499
500 if( !SparcV9RegsHiBitsZero ) return false;
501 if( bol->as_Bool()->_test._test != BoolTest::ne &&
502 bol->as_Bool()->_test._test != BoolTest::eq )
503 return false;
504
505 // Check for comparing against a 'safe' value. Any operation which
506 // clears out the high word is safe. Thus, loads and certain shifts
507 // are safe, as are non-negative constants. Any operation which
508 // preserves zero bits in the high word is safe as long as each of its
509 // inputs are safe. Thus, phis and bitwise booleans are safe if their
510 // inputs are safe. At present, the only important case to recognize
511 // seems to be loads. Constants should fold away, and shifts &
512 // logicals can use the 'cc' forms.
513 Node *x = cmp->in(1);
514 if( x->is_Load() ) return true;
515 if( x->is_Phi() ) {
516 for( uint i = 1; i < x->req(); i++ )
517 if( !x->in(i)->is_Load() )
518 return false;
519 return true;
520 }
521 return false;
522 }
523
524 // ****************************************************************************
525
526 // REQUIRED FUNCTIONALITY
527
528 // !!!!! Special hack to get all type of calls to specify the byte offset
529 // from the start of the call to the point where the return address
530 // will point.
531 // The "return address" is the address of the call instruction, plus 8.
532
533 int MachCallStaticJavaNode::ret_addr_offset() {
534 return NativeCall::instruction_size; // call; delay slot
535 }
536
537 int MachCallDynamicJavaNode::ret_addr_offset() {
538 int vtable_index = this->_vtable_index;
539 if (vtable_index < 0) {
540 // must be invalid_vtable_index, not nonvirtual_vtable_index
541 assert(vtable_index == methodOopDesc::invalid_vtable_index, "correct sentinel value");
542 return (NativeMovConstReg::instruction_size +
543 NativeCall::instruction_size); // sethi; setlo; call; delay slot
544 } else {
545 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
546 int entry_offset = instanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size();
547 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes();
548 int klass_load_size;
549 if (UseCompressedOops) {
550 assert(Universe::heap() != NULL, "java heap should be initialized");
551 if (Universe::narrow_oop_base() == NULL)
552 klass_load_size = 2*BytesPerInstWord; // see MacroAssembler::load_klass()
553 else
554 klass_load_size = 3*BytesPerInstWord;
555 } else {
556 klass_load_size = 1*BytesPerInstWord;
557 }
558 if( Assembler::is_simm13(v_off) ) {
559 return klass_load_size +
560 (2*BytesPerInstWord + // ld_ptr, ld_ptr
561 NativeCall::instruction_size); // call; delay slot
562 } else {
563 return klass_load_size +
564 (4*BytesPerInstWord + // set_hi, set, ld_ptr, ld_ptr
565 NativeCall::instruction_size); // call; delay slot
566 }
567 }
568 }
569
570 int MachCallRuntimeNode::ret_addr_offset() {
571 #ifdef _LP64
572 return NativeFarCall::instruction_size; // farcall; delay slot
573 #else
574 return NativeCall::instruction_size; // call; delay slot
575 #endif
576 }
577
578 // Indicate if the safepoint node needs the polling page as an input.
579 // Since Sparc does not have absolute addressing, it does.
580 bool SafePointNode::needs_polling_address_input() {
581 return true;
582 }
583
584 // emit an interrupt that is caught by the debugger (for debugging compiler)
585 void emit_break(CodeBuffer &cbuf) {
586 MacroAssembler _masm(&cbuf);
587 __ breakpoint_trap();
588 }
589
590 #ifndef PRODUCT
591 void MachBreakpointNode::format( PhaseRegAlloc *, outputStream *st ) const {
592 st->print("TA");
593 }
594 #endif
595
596 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
597 emit_break(cbuf);
598 }
599
600 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {
601 return MachNode::size(ra_);
602 }
603
604 // Traceable jump
605 void emit_jmpl(CodeBuffer &cbuf, int jump_target) {
606 MacroAssembler _masm(&cbuf);
607 Register rdest = reg_to_register_object(jump_target);
608 __ JMP(rdest, 0);
609 __ delayed()->nop();
610 }
611
612 // Traceable jump and set exception pc
613 void emit_jmpl_set_exception_pc(CodeBuffer &cbuf, int jump_target) {
614 MacroAssembler _masm(&cbuf);
615 Register rdest = reg_to_register_object(jump_target);
616 __ JMP(rdest, 0);
617 __ delayed()->add(O7, frame::pc_return_offset, Oissuing_pc );
618 }
619
620 void emit_nop(CodeBuffer &cbuf) {
621 MacroAssembler _masm(&cbuf);
622 __ nop();
623 }
624
625 void emit_illtrap(CodeBuffer &cbuf) {
626 MacroAssembler _masm(&cbuf);
627 __ illtrap(0);
628 }
629
630
631 intptr_t get_offset_from_base(const MachNode* n, const TypePtr* atype, int disp32) {
632 assert(n->rule() != loadUB_rule, "");
633
634 intptr_t offset = 0;
635 const TypePtr *adr_type = TYPE_PTR_SENTINAL; // Check for base==RegI, disp==immP
636 const Node* addr = n->get_base_and_disp(offset, adr_type);
637 assert(adr_type == (const TypePtr*)-1, "VerifyOops: no support for sparc operands with base==RegI, disp==immP");
638 assert(addr != NULL && addr != (Node*)-1, "invalid addr");
639 assert(addr->bottom_type()->isa_oopptr() == atype, "");
640 atype = atype->add_offset(offset);
641 assert(disp32 == offset, "wrong disp32");
642 return atype->_offset;
643 }
644
645
646 intptr_t get_offset_from_base_2(const MachNode* n, const TypePtr* atype, int disp32) {
647 assert(n->rule() != loadUB_rule, "");
648
649 intptr_t offset = 0;
650 Node* addr = n->in(2);
651 assert(addr->bottom_type()->isa_oopptr() == atype, "");
652 if (addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP) {
653 Node* a = addr->in(2/*AddPNode::Address*/);
654 Node* o = addr->in(3/*AddPNode::Offset*/);
655 offset = o->is_Con() ? o->bottom_type()->is_intptr_t()->get_con() : Type::OffsetBot;
656 atype = a->bottom_type()->is_ptr()->add_offset(offset);
657 assert(atype->isa_oop_ptr(), "still an oop");
658 }
659 offset = atype->is_ptr()->_offset;
660 if (offset != Type::OffsetBot) offset += disp32;
661 return offset;
662 }
663
664 // Standard Sparc opcode form2 field breakdown
665 static inline void emit2_19(CodeBuffer &cbuf, int f30, int f29, int f25, int f22, int f20, int f19, int f0 ) {
666 f0 &= (1<<19)-1; // Mask displacement to 19 bits
667 int op = (f30 << 30) |
668 (f29 << 29) |
669 (f25 << 25) |
670 (f22 << 22) |
671 (f20 << 20) |
672 (f19 << 19) |
673 (f0 << 0);
674 *((int*)(cbuf.code_end())) = op;
675 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
676 }
677
678 // Standard Sparc opcode form2 field breakdown
679 static inline void emit2_22(CodeBuffer &cbuf, int f30, int f25, int f22, int f0 ) {
680 f0 >>= 10; // Drop 10 bits
681 f0 &= (1<<22)-1; // Mask displacement to 22 bits
682 int op = (f30 << 30) |
683 (f25 << 25) |
684 (f22 << 22) |
685 (f0 << 0);
686 *((int*)(cbuf.code_end())) = op;
687 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
688 }
689
690 // Standard Sparc opcode form3 field breakdown
691 static inline void emit3(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int f5, int f0 ) {
692 int op = (f30 << 30) |
693 (f25 << 25) |
694 (f19 << 19) |
695 (f14 << 14) |
696 (f5 << 5) |
697 (f0 << 0);
698 *((int*)(cbuf.code_end())) = op;
699 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
700 }
701
702 // Standard Sparc opcode form3 field breakdown
703 static inline void emit3_simm13(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm13 ) {
704 simm13 &= (1<<13)-1; // Mask to 13 bits
705 int op = (f30 << 30) |
706 (f25 << 25) |
707 (f19 << 19) |
708 (f14 << 14) |
709 (1 << 13) | // bit to indicate immediate-mode
710 (simm13<<0);
711 *((int*)(cbuf.code_end())) = op;
712 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
713 }
714
715 static inline void emit3_simm10(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm10 ) {
716 simm10 &= (1<<10)-1; // Mask to 10 bits
717 emit3_simm13(cbuf,f30,f25,f19,f14,simm10);
718 }
719
720 #ifdef ASSERT
721 // Helper function for VerifyOops in emit_form3_mem_reg
722 void verify_oops_warning(const MachNode *n, int ideal_op, int mem_op) {
723 warning("VerifyOops encountered unexpected instruction:");
724 n->dump(2);
725 warning("Instruction has ideal_Opcode==Op_%s and op_ld==Op_%s \n", NodeClassNames[ideal_op], NodeClassNames[mem_op]);
726 }
727 #endif
728
729
730 void emit_form3_mem_reg(CodeBuffer &cbuf, const MachNode* n, int primary, int tertiary,
731 int src1_enc, int disp32, int src2_enc, int dst_enc) {
732
733 #ifdef ASSERT
734 // The following code implements the +VerifyOops feature.
735 // It verifies oop values which are loaded into or stored out of
736 // the current method activation. +VerifyOops complements techniques
737 // like ScavengeALot, because it eagerly inspects oops in transit,
738 // as they enter or leave the stack, as opposed to ScavengeALot,
739 // which inspects oops "at rest", in the stack or heap, at safepoints.
740 // For this reason, +VerifyOops can sometimes detect bugs very close
741 // to their point of creation. It can also serve as a cross-check
742 // on the validity of oop maps, when used toegether with ScavengeALot.
743
744 // It would be good to verify oops at other points, especially
745 // when an oop is used as a base pointer for a load or store.
746 // This is presently difficult, because it is hard to know when
747 // a base address is biased or not. (If we had such information,
748 // it would be easy and useful to make a two-argument version of
749 // verify_oop which unbiases the base, and performs verification.)
750
751 assert((uint)tertiary == 0xFFFFFFFF || tertiary == REGP_OP, "valid tertiary");
752 bool is_verified_oop_base = false;
753 bool is_verified_oop_load = false;
754 bool is_verified_oop_store = false;
755 int tmp_enc = -1;
756 if (VerifyOops && src1_enc != R_SP_enc) {
757 // classify the op, mainly for an assert check
758 int st_op = 0, ld_op = 0;
759 switch (primary) {
760 case Assembler::stb_op3: st_op = Op_StoreB; break;
761 case Assembler::sth_op3: st_op = Op_StoreC; break;
762 case Assembler::stx_op3: // may become StoreP or stay StoreI or StoreD0
763 case Assembler::stw_op3: st_op = Op_StoreI; break;
764 case Assembler::std_op3: st_op = Op_StoreL; break;
765 case Assembler::stf_op3: st_op = Op_StoreF; break;
766 case Assembler::stdf_op3: st_op = Op_StoreD; break;
767
768 case Assembler::ldsb_op3: ld_op = Op_LoadB; break;
769 case Assembler::lduh_op3: ld_op = Op_LoadUS; break;
770 case Assembler::ldsh_op3: ld_op = Op_LoadS; break;
771 case Assembler::ldx_op3: // may become LoadP or stay LoadI
772 case Assembler::ldsw_op3: // may become LoadP or stay LoadI
773 case Assembler::lduw_op3: ld_op = Op_LoadI; break;
774 case Assembler::ldd_op3: ld_op = Op_LoadL; break;
775 case Assembler::ldf_op3: ld_op = Op_LoadF; break;
776 case Assembler::lddf_op3: ld_op = Op_LoadD; break;
777 case Assembler::ldub_op3: ld_op = Op_LoadB; break;
778 case Assembler::prefetch_op3: ld_op = Op_LoadI; break;
779
780 default: ShouldNotReachHere();
781 }
782 if (tertiary == REGP_OP) {
783 if (st_op == Op_StoreI) st_op = Op_StoreP;
784 else if (ld_op == Op_LoadI) ld_op = Op_LoadP;
785 else ShouldNotReachHere();
786 if (st_op) {
787 // a store
788 // inputs are (0:control, 1:memory, 2:address, 3:value)
789 Node* n2 = n->in(3);
790 if (n2 != NULL) {
791 const Type* t = n2->bottom_type();
792 is_verified_oop_store = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false;
793 }
794 } else {
795 // a load
796 const Type* t = n->bottom_type();
797 is_verified_oop_load = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false;
798 }
799 }
800
801 if (ld_op) {
802 // a Load
803 // inputs are (0:control, 1:memory, 2:address)
804 if (!(n->ideal_Opcode()==ld_op) && // Following are special cases
805 !(n->ideal_Opcode()==Op_LoadLLocked && ld_op==Op_LoadI) &&
806 !(n->ideal_Opcode()==Op_LoadPLocked && ld_op==Op_LoadP) &&
807 !(n->ideal_Opcode()==Op_LoadI && ld_op==Op_LoadF) &&
808 !(n->ideal_Opcode()==Op_LoadF && ld_op==Op_LoadI) &&
809 !(n->ideal_Opcode()==Op_LoadRange && ld_op==Op_LoadI) &&
810 !(n->ideal_Opcode()==Op_LoadKlass && ld_op==Op_LoadP) &&
811 !(n->ideal_Opcode()==Op_LoadL && ld_op==Op_LoadI) &&
812 !(n->ideal_Opcode()==Op_LoadL_unaligned && ld_op==Op_LoadI) &&
813 !(n->ideal_Opcode()==Op_LoadD_unaligned && ld_op==Op_LoadF) &&
814 !(n->ideal_Opcode()==Op_ConvI2F && ld_op==Op_LoadF) &&
815 !(n->ideal_Opcode()==Op_ConvI2D && ld_op==Op_LoadF) &&
816 !(n->ideal_Opcode()==Op_PrefetchRead && ld_op==Op_LoadI) &&
817 !(n->ideal_Opcode()==Op_PrefetchWrite && ld_op==Op_LoadI) &&
818 !(n->rule() == loadUB_rule)) {
819 verify_oops_warning(n, n->ideal_Opcode(), ld_op);
820 }
821 } else if (st_op) {
822 // a Store
823 // inputs are (0:control, 1:memory, 2:address, 3:value)
824 if (!(n->ideal_Opcode()==st_op) && // Following are special cases
825 !(n->ideal_Opcode()==Op_StoreCM && st_op==Op_StoreB) &&
826 !(n->ideal_Opcode()==Op_StoreI && st_op==Op_StoreF) &&
827 !(n->ideal_Opcode()==Op_StoreF && st_op==Op_StoreI) &&
828 !(n->ideal_Opcode()==Op_StoreL && st_op==Op_StoreI) &&
829 !(n->ideal_Opcode()==Op_StoreD && st_op==Op_StoreI && n->rule() == storeD0_rule)) {
830 verify_oops_warning(n, n->ideal_Opcode(), st_op);
831 }
832 }
833
834 if (src2_enc == R_G0_enc && n->rule() != loadUB_rule && n->ideal_Opcode() != Op_StoreCM ) {
835 Node* addr = n->in(2);
836 if (!(addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP)) {
837 const TypeOopPtr* atype = addr->bottom_type()->isa_instptr(); // %%% oopptr?
838 if (atype != NULL) {
839 intptr_t offset = get_offset_from_base(n, atype, disp32);
840 intptr_t offset_2 = get_offset_from_base_2(n, atype, disp32);
841 if (offset != offset_2) {
842 get_offset_from_base(n, atype, disp32);
843 get_offset_from_base_2(n, atype, disp32);
844 }
845 assert(offset == offset_2, "different offsets");
846 if (offset == disp32) {
847 // we now know that src1 is a true oop pointer
848 is_verified_oop_base = true;
849 if (ld_op && src1_enc == dst_enc && ld_op != Op_LoadF && ld_op != Op_LoadD) {
850 if( primary == Assembler::ldd_op3 ) {
851 is_verified_oop_base = false; // Cannot 'ldd' into O7
852 } else {
853 tmp_enc = dst_enc;
854 dst_enc = R_O7_enc; // Load into O7; preserve source oop
855 assert(src1_enc != dst_enc, "");
856 }
857 }
858 }
859 if (st_op && (( offset == oopDesc::klass_offset_in_bytes())
860 || offset == oopDesc::mark_offset_in_bytes())) {
861 // loading the mark should not be allowed either, but
862 // we don't check this since it conflicts with InlineObjectHash
863 // usage of LoadINode to get the mark. We could keep the
864 // check if we create a new LoadMarkNode
865 // but do not verify the object before its header is initialized
866 ShouldNotReachHere();
867 }
868 }
869 }
870 }
871 }
872 #endif
873
874 uint instr;
875 instr = (Assembler::ldst_op << 30)
876 | (dst_enc << 25)
877 | (primary << 19)
878 | (src1_enc << 14);
879
880 uint index = src2_enc;
881 int disp = disp32;
882
883 if (src1_enc == R_SP_enc || src1_enc == R_FP_enc)
884 disp += STACK_BIAS;
885
886 // We should have a compiler bailout here rather than a guarantee.
887 // Better yet would be some mechanism to handle variable-size matches correctly.
888 guarantee(Assembler::is_simm13(disp), "Do not match large constant offsets" );
889
890 if( disp == 0 ) {
891 // use reg-reg form
892 // bit 13 is already zero
893 instr |= index;
894 } else {
895 // use reg-imm form
896 instr |= 0x00002000; // set bit 13 to one
897 instr |= disp & 0x1FFF;
898 }
899
900 uint *code = (uint*)cbuf.code_end();
901 *code = instr;
902 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
903
904 #ifdef ASSERT
905 {
906 MacroAssembler _masm(&cbuf);
907 if (is_verified_oop_base) {
908 __ verify_oop(reg_to_register_object(src1_enc));
909 }
910 if (is_verified_oop_store) {
911 __ verify_oop(reg_to_register_object(dst_enc));
912 }
913 if (tmp_enc != -1) {
914 __ mov(O7, reg_to_register_object(tmp_enc));
915 }
916 if (is_verified_oop_load) {
917 __ verify_oop(reg_to_register_object(dst_enc));
918 }
919 }
920 #endif
921 }
922
923 void emit_form3_mem_reg_asi(CodeBuffer &cbuf, const MachNode* n, int primary, int tertiary,
924 int src1_enc, int disp32, int src2_enc, int dst_enc, int asi) {
925
926 uint instr;
927 instr = (Assembler::ldst_op << 30)
928 | (dst_enc << 25)
929 | (primary << 19)
930 | (src1_enc << 14);
931
932 int disp = disp32;
933 int index = src2_enc;
934
935 if (src1_enc == R_SP_enc || src1_enc == R_FP_enc)
936 disp += STACK_BIAS;
937
938 // We should have a compiler bailout here rather than a guarantee.
939 // Better yet would be some mechanism to handle variable-size matches correctly.
940 guarantee(Assembler::is_simm13(disp), "Do not match large constant offsets" );
941
942 if( disp != 0 ) {
943 // use reg-reg form
944 // set src2=R_O7 contains offset
945 index = R_O7_enc;
946 emit3_simm13( cbuf, Assembler::arith_op, index, Assembler::or_op3, 0, disp);
947 }
948 instr |= (asi << 5);
949 instr |= index;
950 uint *code = (uint*)cbuf.code_end();
951 *code = instr;
952 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
953 }
954
955 void emit_call_reloc(CodeBuffer &cbuf, intptr_t entry_point, relocInfo::relocType rtype, bool preserve_g2 = false, bool force_far_call = false) {
956 // The method which records debug information at every safepoint
957 // expects the call to be the first instruction in the snippet as
958 // it creates a PcDesc structure which tracks the offset of a call
959 // from the start of the codeBlob. This offset is computed as
960 // code_end() - code_begin() of the code which has been emitted
961 // so far.
962 // In this particular case we have skirted around the problem by
963 // putting the "mov" instruction in the delay slot but the problem
964 // may bite us again at some other point and a cleaner/generic
965 // solution using relocations would be needed.
966 MacroAssembler _masm(&cbuf);
967 __ set_inst_mark();
968
969 // We flush the current window just so that there is a valid stack copy
970 // the fact that the current window becomes active again instantly is
971 // not a problem there is nothing live in it.
972
973 #ifdef ASSERT
974 int startpos = __ offset();
975 #endif /* ASSERT */
976
977 #ifdef _LP64
978 // Calls to the runtime or native may not be reachable from compiled code,
979 // so we generate the far call sequence on 64 bit sparc.
980 // This code sequence is relocatable to any address, even on LP64.
981 if ( force_far_call ) {
982 __ relocate(rtype);
983 AddressLiteral dest(entry_point);
984 __ jumpl_to(dest, O7, O7);
985 }
986 else
987 #endif
988 {
989 __ call((address)entry_point, rtype);
990 }
991
992 if (preserve_g2) __ delayed()->mov(G2, L7);
993 else __ delayed()->nop();
994
995 if (preserve_g2) __ mov(L7, G2);
996
997 #ifdef ASSERT
998 if (preserve_g2 && (VerifyCompiledCode || VerifyOops)) {
999 #ifdef _LP64
1000 // Trash argument dump slots.
1001 __ set(0xb0b8ac0db0b8ac0d, G1);
1002 __ mov(G1, G5);
1003 __ stx(G1, SP, STACK_BIAS + 0x80);
1004 __ stx(G1, SP, STACK_BIAS + 0x88);
1005 __ stx(G1, SP, STACK_BIAS + 0x90);
1006 __ stx(G1, SP, STACK_BIAS + 0x98);
1007 __ stx(G1, SP, STACK_BIAS + 0xA0);
1008 __ stx(G1, SP, STACK_BIAS + 0xA8);
1009 #else // _LP64
1010 // this is also a native call, so smash the first 7 stack locations,
1011 // and the various registers
1012
1013 // Note: [SP+0x40] is sp[callee_aggregate_return_pointer_sp_offset],
1014 // while [SP+0x44..0x58] are the argument dump slots.
1015 __ set((intptr_t)0xbaadf00d, G1);
1016 __ mov(G1, G5);
1017 __ sllx(G1, 32, G1);
1018 __ or3(G1, G5, G1);
1019 __ mov(G1, G5);
1020 __ stx(G1, SP, 0x40);
1021 __ stx(G1, SP, 0x48);
1022 __ stx(G1, SP, 0x50);
1023 __ stw(G1, SP, 0x58); // Do not trash [SP+0x5C] which is a usable spill slot
1024 #endif // _LP64
1025 }
1026 #endif /*ASSERT*/
1027 }
1028
1029 //=============================================================================
1030 // REQUIRED FUNCTIONALITY for encoding
1031 void emit_lo(CodeBuffer &cbuf, int val) { }
1032 void emit_hi(CodeBuffer &cbuf, int val) { }
1033
1034
1035 //=============================================================================
1036
1037 #ifndef PRODUCT
1038 void MachPrologNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1039 Compile* C = ra_->C;
1040
1041 for (int i = 0; i < OptoPrologueNops; i++) {
1042 st->print_cr("NOP"); st->print("\t");
1043 }
1044
1045 if( VerifyThread ) {
1046 st->print_cr("Verify_Thread"); st->print("\t");
1047 }
1048
1049 size_t framesize = C->frame_slots() << LogBytesPerInt;
1050
1051 // Calls to C2R adapters often do not accept exceptional returns.
1052 // We require that their callers must bang for them. But be careful, because
1053 // some VM calls (such as call site linkage) can use several kilobytes of
1054 // stack. But the stack safety zone should account for that.
1055 // See bugs 4446381, 4468289, 4497237.
1056 if (C->need_stack_bang(framesize)) {
1057 st->print_cr("! stack bang"); st->print("\t");
1058 }
1059
1060 if (Assembler::is_simm13(-framesize)) {
1061 st->print ("SAVE R_SP,-%d,R_SP",framesize);
1062 } else {
1063 st->print_cr("SETHI R_SP,hi%%(-%d),R_G3",framesize); st->print("\t");
1064 st->print_cr("ADD R_G3,lo%%(-%d),R_G3",framesize); st->print("\t");
1065 st->print ("SAVE R_SP,R_G3,R_SP");
1066 }
1067
1068 }
1069 #endif
1070
1071 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1072 Compile* C = ra_->C;
1073 MacroAssembler _masm(&cbuf);
1074
1075 for (int i = 0; i < OptoPrologueNops; i++) {
1076 __ nop();
1077 }
1078
1079 __ verify_thread();
1080
1081 size_t framesize = C->frame_slots() << LogBytesPerInt;
1082 assert(framesize >= 16*wordSize, "must have room for reg. save area");
1083 assert(framesize%(2*wordSize) == 0, "must preserve 2*wordSize alignment");
1084
1085 // Calls to C2R adapters often do not accept exceptional returns.
1086 // We require that their callers must bang for them. But be careful, because
1087 // some VM calls (such as call site linkage) can use several kilobytes of
1088 // stack. But the stack safety zone should account for that.
1089 // See bugs 4446381, 4468289, 4497237.
1090 if (C->need_stack_bang(framesize)) {
1091 __ generate_stack_overflow_check(framesize);
1092 }
1093
1094 if (Assembler::is_simm13(-framesize)) {
1095 __ save(SP, -framesize, SP);
1096 } else {
1097 __ sethi(-framesize & ~0x3ff, G3);
1098 __ add(G3, -framesize & 0x3ff, G3);
1099 __ save(SP, G3, SP);
1100 }
1101 C->set_frame_complete( __ offset() );
1102 }
1103
1104 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
1105 return MachNode::size(ra_);
1106 }
1107
1108 int MachPrologNode::reloc() const {
1109 return 10; // a large enough number
1110 }
1111
1112 //=============================================================================
1113 #ifndef PRODUCT
1114 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1115 Compile* C = ra_->C;
1116
1117 if( do_polling() && ra_->C->is_method_compilation() ) {
1118 st->print("SETHI #PollAddr,L0\t! Load Polling address\n\t");
1119 #ifdef _LP64
1120 st->print("LDX [L0],G0\t!Poll for Safepointing\n\t");
1121 #else
1122 st->print("LDUW [L0],G0\t!Poll for Safepointing\n\t");
1123 #endif
1124 }
1125
1126 if( do_polling() )
1127 st->print("RET\n\t");
1128
1129 st->print("RESTORE");
1130 }
1131 #endif
1132
1133 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1134 MacroAssembler _masm(&cbuf);
1135 Compile* C = ra_->C;
1136
1137 __ verify_thread();
1138
1139 // If this does safepoint polling, then do it here
1140 if( do_polling() && ra_->C->is_method_compilation() ) {
1141 AddressLiteral polling_page(os::get_polling_page());
1142 __ sethi(polling_page, L0);
1143 __ relocate(relocInfo::poll_return_type);
1144 __ ld_ptr( L0, 0, G0 );
1145 }
1146
1147 // If this is a return, then stuff the restore in the delay slot
1148 if( do_polling() ) {
1149 __ ret();
1150 __ delayed()->restore();
1151 } else {
1152 __ restore();
1153 }
1154 }
1155
1156 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
1157 return MachNode::size(ra_);
1158 }
1159
1160 int MachEpilogNode::reloc() const {
1161 return 16; // a large enough number
1162 }
1163
1164 const Pipeline * MachEpilogNode::pipeline() const {
1165 return MachNode::pipeline_class();
1166 }
1167
1168 int MachEpilogNode::safepoint_offset() const {
1169 assert( do_polling(), "no return for this epilog node");
1170 return MacroAssembler::size_of_sethi(os::get_polling_page());
1171 }
1172
1173 //=============================================================================
1174
1175 // Figure out which register class each belongs in: rc_int, rc_float, rc_stack
1176 enum RC { rc_bad, rc_int, rc_float, rc_stack };
1177 static enum RC rc_class( OptoReg::Name reg ) {
1178 if( !OptoReg::is_valid(reg) ) return rc_bad;
1179 if (OptoReg::is_stack(reg)) return rc_stack;
1180 VMReg r = OptoReg::as_VMReg(reg);
1181 if (r->is_Register()) return rc_int;
1182 assert(r->is_FloatRegister(), "must be");
1183 return rc_float;
1184 }
1185
1186 static int impl_helper( const MachNode *mach, CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, bool is_load, int offset, int reg, int opcode, const char *op_str, int size, outputStream* st ) {
1187 if( cbuf ) {
1188 // Better yet would be some mechanism to handle variable-size matches correctly
1189 if (!Assembler::is_simm13(offset + STACK_BIAS)) {
1190 ra_->C->record_method_not_compilable("unable to handle large constant offsets");
1191 } else {
1192 emit_form3_mem_reg(*cbuf, mach, opcode, -1, R_SP_enc, offset, 0, Matcher::_regEncode[reg]);
1193 }
1194 }
1195 #ifndef PRODUCT
1196 else if( !do_size ) {
1197 if( size != 0 ) st->print("\n\t");
1198 if( is_load ) st->print("%s [R_SP + #%d],R_%s\t! spill",op_str,offset,OptoReg::regname(reg));
1199 else st->print("%s R_%s,[R_SP + #%d]\t! spill",op_str,OptoReg::regname(reg),offset);
1200 }
1201 #endif
1202 return size+4;
1203 }
1204
1205 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int op1, int op2, const char *op_str, int size, outputStream* st ) {
1206 if( cbuf ) emit3( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst], op1, 0, op2, Matcher::_regEncode[src] );
1207 #ifndef PRODUCT
1208 else if( !do_size ) {
1209 if( size != 0 ) st->print("\n\t");
1210 st->print("%s R_%s,R_%s\t! spill",op_str,OptoReg::regname(src),OptoReg::regname(dst));
1211 }
1212 #endif
1213 return size+4;
1214 }
1215
1216 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf,
1217 PhaseRegAlloc *ra_,
1218 bool do_size,
1219 outputStream* st ) const {
1220 // Get registers to move
1221 OptoReg::Name src_second = ra_->get_reg_second(in(1));
1222 OptoReg::Name src_first = ra_->get_reg_first(in(1));
1223 OptoReg::Name dst_second = ra_->get_reg_second(this );
1224 OptoReg::Name dst_first = ra_->get_reg_first(this );
1225
1226 enum RC src_second_rc = rc_class(src_second);
1227 enum RC src_first_rc = rc_class(src_first);
1228 enum RC dst_second_rc = rc_class(dst_second);
1229 enum RC dst_first_rc = rc_class(dst_first);
1230
1231 assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" );
1232
1233 // Generate spill code!
1234 int size = 0;
1235
1236 if( src_first == dst_first && src_second == dst_second )
1237 return size; // Self copy, no move
1238
1239 // --------------------------------------
1240 // Check for mem-mem move. Load into unused float registers and fall into
1241 // the float-store case.
1242 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
1243 int offset = ra_->reg2offset(src_first);
1244 // Further check for aligned-adjacent pair, so we can use a double load
1245 if( (src_first&1)==0 && src_first+1 == src_second ) {
1246 src_second = OptoReg::Name(R_F31_num);
1247 src_second_rc = rc_float;
1248 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::lddf_op3,"LDDF",size, st);
1249 } else {
1250 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::ldf_op3 ,"LDF ",size, st);
1251 }
1252 src_first = OptoReg::Name(R_F30_num);
1253 src_first_rc = rc_float;
1254 }
1255
1256 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) {
1257 int offset = ra_->reg2offset(src_second);
1258 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F31_num,Assembler::ldf_op3,"LDF ",size, st);
1259 src_second = OptoReg::Name(R_F31_num);
1260 src_second_rc = rc_float;
1261 }
1262
1263 // --------------------------------------
1264 // Check for float->int copy; requires a trip through memory
1265 if( src_first_rc == rc_float && dst_first_rc == rc_int ) {
1266 int offset = frame::register_save_words*wordSize;
1267 if( cbuf ) {
1268 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::sub_op3, R_SP_enc, 16 );
1269 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
1270 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
1271 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::add_op3, R_SP_enc, 16 );
1272 }
1273 #ifndef PRODUCT
1274 else if( !do_size ) {
1275 if( size != 0 ) st->print("\n\t");
1276 st->print( "SUB R_SP,16,R_SP\n");
1277 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
1278 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
1279 st->print("\tADD R_SP,16,R_SP\n");
1280 }
1281 #endif
1282 size += 16;
1283 }
1284
1285 // --------------------------------------
1286 // In the 32-bit 1-reg-longs build ONLY, I see mis-aligned long destinations.
1287 // In such cases, I have to do the big-endian swap. For aligned targets, the
1288 // hardware does the flop for me. Doubles are always aligned, so no problem
1289 // there. Misaligned sources only come from native-long-returns (handled
1290 // special below).
1291 #ifndef _LP64
1292 if( src_first_rc == rc_int && // source is already big-endian
1293 src_second_rc != rc_bad && // 64-bit move
1294 ((dst_first&1)!=0 || dst_second != dst_first+1) ) { // misaligned dst
1295 assert( (src_first&1)==0 && src_second == src_first+1, "source must be aligned" );
1296 // Do the big-endian flop.
1297 OptoReg::Name tmp = dst_first ; dst_first = dst_second ; dst_second = tmp ;
1298 enum RC tmp_rc = dst_first_rc; dst_first_rc = dst_second_rc; dst_second_rc = tmp_rc;
1299 }
1300 #endif
1301
1302 // --------------------------------------
1303 // Check for integer reg-reg copy
1304 if( src_first_rc == rc_int && dst_first_rc == rc_int ) {
1305 #ifndef _LP64
1306 if( src_first == R_O0_num && src_second == R_O1_num ) { // Check for the evil O0/O1 native long-return case
1307 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value
1308 // as stored in memory. On a big-endian machine like SPARC, this means that the _second
1309 // operand contains the least significant word of the 64-bit value and vice versa.
1310 OptoReg::Name tmp = OptoReg::Name(R_O7_num);
1311 assert( (dst_first&1)==0 && dst_second == dst_first+1, "return a native O0/O1 long to an aligned-adjacent 64-bit reg" );
1312 // Shift O0 left in-place, zero-extend O1, then OR them into the dst
1313 if( cbuf ) {
1314 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tmp], Assembler::sllx_op3, Matcher::_regEncode[src_first], 0x1020 );
1315 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[src_second], Assembler::srl_op3, Matcher::_regEncode[src_second], 0x0000 );
1316 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler:: or_op3, Matcher::_regEncode[tmp], 0, Matcher::_regEncode[src_second] );
1317 #ifndef PRODUCT
1318 } else if( !do_size ) {
1319 if( size != 0 ) st->print("\n\t");
1320 st->print("SLLX R_%s,32,R_%s\t! Move O0-first to O7-high\n\t", OptoReg::regname(src_first), OptoReg::regname(tmp));
1321 st->print("SRL R_%s, 0,R_%s\t! Zero-extend O1\n\t", OptoReg::regname(src_second), OptoReg::regname(src_second));
1322 st->print("OR R_%s,R_%s,R_%s\t! spill",OptoReg::regname(tmp), OptoReg::regname(src_second), OptoReg::regname(dst_first));
1323 #endif
1324 }
1325 return size+12;
1326 }
1327 else if( dst_first == R_I0_num && dst_second == R_I1_num ) {
1328 // returning a long value in I0/I1
1329 // a SpillCopy must be able to target a return instruction's reg_class
1330 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value
1331 // as stored in memory. On a big-endian machine like SPARC, this means that the _second
1332 // operand contains the least significant word of the 64-bit value and vice versa.
1333 OptoReg::Name tdest = dst_first;
1334
1335 if (src_first == dst_first) {
1336 tdest = OptoReg::Name(R_O7_num);
1337 size += 4;
1338 }
1339
1340 if( cbuf ) {
1341 assert( (src_first&1) == 0 && (src_first+1) == src_second, "return value was in an aligned-adjacent 64-bit reg");
1342 // Shift value in upper 32-bits of src to lower 32-bits of I0; move lower 32-bits to I1
1343 // ShrL_reg_imm6
1344 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tdest], Assembler::srlx_op3, Matcher::_regEncode[src_second], 32 | 0x1000 );
1345 // ShrR_reg_imm6 src, 0, dst
1346 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srl_op3, Matcher::_regEncode[src_first], 0x0000 );
1347 if (tdest != dst_first) {
1348 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler::or_op3, 0/*G0*/, 0/*op2*/, Matcher::_regEncode[tdest] );
1349 }
1350 }
1351 #ifndef PRODUCT
1352 else if( !do_size ) {
1353 if( size != 0 ) st->print("\n\t"); // %%%%% !!!!!
1354 st->print("SRLX R_%s,32,R_%s\t! Extract MSW\n\t",OptoReg::regname(src_second),OptoReg::regname(tdest));
1355 st->print("SRL R_%s, 0,R_%s\t! Extract LSW\n\t",OptoReg::regname(src_first),OptoReg::regname(dst_second));
1356 if (tdest != dst_first) {
1357 st->print("MOV R_%s,R_%s\t! spill\n\t", OptoReg::regname(tdest), OptoReg::regname(dst_first));
1358 }
1359 }
1360 #endif // PRODUCT
1361 return size+8;
1362 }
1363 #endif // !_LP64
1364 // Else normal reg-reg copy
1365 assert( src_second != dst_first, "smashed second before evacuating it" );
1366 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::or_op3,0,"MOV ",size, st);
1367 assert( (src_first&1) == 0 && (dst_first&1) == 0, "never move second-halves of int registers" );
1368 // This moves an aligned adjacent pair.
1369 // See if we are done.
1370 if( src_first+1 == src_second && dst_first+1 == dst_second )
1371 return size;
1372 }
1373
1374 // Check for integer store
1375 if( src_first_rc == rc_int && dst_first_rc == rc_stack ) {
1376 int offset = ra_->reg2offset(dst_first);
1377 // Further check for aligned-adjacent pair, so we can use a double store
1378 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1379 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stx_op3,"STX ",size, st);
1380 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stw_op3,"STW ",size, st);
1381 }
1382
1383 // Check for integer load
1384 if( dst_first_rc == rc_int && src_first_rc == rc_stack ) {
1385 int offset = ra_->reg2offset(src_first);
1386 // Further check for aligned-adjacent pair, so we can use a double load
1387 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1388 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldx_op3 ,"LDX ",size, st);
1389 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
1390 }
1391
1392 // Check for float reg-reg copy
1393 if( src_first_rc == rc_float && dst_first_rc == rc_float ) {
1394 // Further check for aligned-adjacent pair, so we can use a double move
1395 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1396 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovd_opf,"FMOVD",size, st);
1397 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovs_opf,"FMOVS",size, st);
1398 }
1399
1400 // Check for float store
1401 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) {
1402 int offset = ra_->reg2offset(dst_first);
1403 // Further check for aligned-adjacent pair, so we can use a double store
1404 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1405 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stdf_op3,"STDF",size, st);
1406 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
1407 }
1408
1409 // Check for float load
1410 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) {
1411 int offset = ra_->reg2offset(src_first);
1412 // Further check for aligned-adjacent pair, so we can use a double load
1413 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1414 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lddf_op3,"LDDF",size, st);
1415 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldf_op3 ,"LDF ",size, st);
1416 }
1417
1418 // --------------------------------------------------------------------
1419 // Check for hi bits still needing moving. Only happens for misaligned
1420 // arguments to native calls.
1421 if( src_second == dst_second )
1422 return size; // Self copy; no move
1423 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" );
1424
1425 #ifndef _LP64
1426 // In the LP64 build, all registers can be moved as aligned/adjacent
1427 // pairs, so there's never any need to move the high bits separately.
1428 // The 32-bit builds have to deal with the 32-bit ABI which can force
1429 // all sorts of silly alignment problems.
1430
1431 // Check for integer reg-reg copy. Hi bits are stuck up in the top
1432 // 32-bits of a 64-bit register, but are needed in low bits of another
1433 // register (else it's a hi-bits-to-hi-bits copy which should have
1434 // happened already as part of a 64-bit move)
1435 if( src_second_rc == rc_int && dst_second_rc == rc_int ) {
1436 assert( (src_second&1)==1, "its the evil O0/O1 native return case" );
1437 assert( (dst_second&1)==0, "should have moved with 1 64-bit move" );
1438 // Shift src_second down to dst_second's low bits.
1439 if( cbuf ) {
1440 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 );
1441 #ifndef PRODUCT
1442 } else if( !do_size ) {
1443 if( size != 0 ) st->print("\n\t");
1444 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(dst_second));
1445 #endif
1446 }
1447 return size+4;
1448 }
1449
1450 // Check for high word integer store. Must down-shift the hi bits
1451 // into a temp register, then fall into the case of storing int bits.
1452 if( src_second_rc == rc_int && dst_second_rc == rc_stack && (src_second&1)==1 ) {
1453 // Shift src_second down to dst_second's low bits.
1454 if( cbuf ) {
1455 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[R_O7_num], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 );
1456 #ifndef PRODUCT
1457 } else if( !do_size ) {
1458 if( size != 0 ) st->print("\n\t");
1459 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(R_O7_num));
1460 #endif
1461 }
1462 size+=4;
1463 src_second = OptoReg::Name(R_O7_num); // Not R_O7H_num!
1464 }
1465
1466 // Check for high word integer load
1467 if( dst_second_rc == rc_int && src_second_rc == rc_stack )
1468 return impl_helper(this,cbuf,ra_,do_size,true ,ra_->reg2offset(src_second),dst_second,Assembler::lduw_op3,"LDUW",size, st);
1469
1470 // Check for high word integer store
1471 if( src_second_rc == rc_int && dst_second_rc == rc_stack )
1472 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stw_op3 ,"STW ",size, st);
1473
1474 // Check for high word float store
1475 if( src_second_rc == rc_float && dst_second_rc == rc_stack )
1476 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stf_op3 ,"STF ",size, st);
1477
1478 #endif // !_LP64
1479
1480 Unimplemented();
1481 }
1482
1483 #ifndef PRODUCT
1484 void MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1485 implementation( NULL, ra_, false, st );
1486 }
1487 #endif
1488
1489 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1490 implementation( &cbuf, ra_, false, NULL );
1491 }
1492
1493 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1494 return implementation( NULL, ra_, true, NULL );
1495 }
1496
1497 //=============================================================================
1498 #ifndef PRODUCT
1499 void MachNopNode::format( PhaseRegAlloc *, outputStream *st ) const {
1500 st->print("NOP \t# %d bytes pad for loops and calls", 4 * _count);
1501 }
1502 #endif
1503
1504 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc * ) const {
1505 MacroAssembler _masm(&cbuf);
1506 for(int i = 0; i < _count; i += 1) {
1507 __ nop();
1508 }
1509 }
1510
1511 uint MachNopNode::size(PhaseRegAlloc *ra_) const {
1512 return 4 * _count;
1513 }
1514
1515
1516 //=============================================================================
1517 #ifndef PRODUCT
1518 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1519 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1520 int reg = ra_->get_reg_first(this);
1521 st->print("LEA [R_SP+#%d+BIAS],%s",offset,Matcher::regName[reg]);
1522 }
1523 #endif
1524
1525 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1526 MacroAssembler _masm(&cbuf);
1527 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()) + STACK_BIAS;
1528 int reg = ra_->get_encode(this);
1529
1530 if (Assembler::is_simm13(offset)) {
1531 __ add(SP, offset, reg_to_register_object(reg));
1532 } else {
1533 __ set(offset, O7);
1534 __ add(SP, O7, reg_to_register_object(reg));
1535 }
1536 }
1537
1538 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1539 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_)
1540 assert(ra_ == ra_->C->regalloc(), "sanity");
1541 return ra_->C->scratch_emit_size(this);
1542 }
1543
1544 //=============================================================================
1545
1546 // emit call stub, compiled java to interpretor
1547 void emit_java_to_interp(CodeBuffer &cbuf ) {
1548
1549 // Stub is fixed up when the corresponding call is converted from calling
1550 // compiled code to calling interpreted code.
1551 // set (empty), G5
1552 // jmp -1
1553
1554 address mark = cbuf.inst_mark(); // get mark within main instrs section
1555
1556 MacroAssembler _masm(&cbuf);
1557
1558 address base =
1559 __ start_a_stub(Compile::MAX_stubs_size);
1560 if (base == NULL) return; // CodeBuffer::expand failed
1561
1562 // static stub relocation stores the instruction address of the call
1563 __ relocate(static_stub_Relocation::spec(mark));
1564
1565 __ set_oop(NULL, reg_to_register_object(Matcher::inline_cache_reg_encode()));
1566
1567 __ set_inst_mark();
1568 AddressLiteral addrlit(-1);
1569 __ JUMP(addrlit, G3, 0);
1570
1571 __ delayed()->nop();
1572
1573 // Update current stubs pointer and restore code_end.
1574 __ end_a_stub();
1575 }
1576
1577 // size of call stub, compiled java to interpretor
1578 uint size_java_to_interp() {
1579 // This doesn't need to be accurate but it must be larger or equal to
1580 // the real size of the stub.
1581 return (NativeMovConstReg::instruction_size + // sethi/setlo;
1582 NativeJump::instruction_size + // sethi; jmp; nop
1583 (TraceJumps ? 20 * BytesPerInstWord : 0) );
1584 }
1585 // relocation entries for call stub, compiled java to interpretor
1586 uint reloc_java_to_interp() {
1587 return 10; // 4 in emit_java_to_interp + 1 in Java_Static_Call
1588 }
1589
1590
1591 //=============================================================================
1592 #ifndef PRODUCT
1593 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1594 st->print_cr("\nUEP:");
1595 #ifdef _LP64
1596 if (UseCompressedOops) {
1597 assert(Universe::heap() != NULL, "java heap should be initialized");
1598 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check - compressed klass");
1599 st->print_cr("\tSLL R_G5,3,R_G5");
1600 if (Universe::narrow_oop_base() != NULL)
1601 st->print_cr("\tADD R_G5,R_G6_heap_base,R_G5");
1602 } else {
1603 st->print_cr("\tLDX [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check");
1604 }
1605 st->print_cr("\tCMP R_G5,R_G3" );
1606 st->print ("\tTne xcc,R_G0+ST_RESERVED_FOR_USER_0+2");
1607 #else // _LP64
1608 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check");
1609 st->print_cr("\tCMP R_G5,R_G3" );
1610 st->print ("\tTne icc,R_G0+ST_RESERVED_FOR_USER_0+2");
1611 #endif // _LP64
1612 }
1613 #endif
1614
1615 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1616 MacroAssembler _masm(&cbuf);
1617 Label L;
1618 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
1619 Register temp_reg = G3;
1620 assert( G5_ic_reg != temp_reg, "conflicting registers" );
1621
1622 // Load klass from receiver
1623 __ load_klass(O0, temp_reg);
1624 // Compare against expected klass
1625 __ cmp(temp_reg, G5_ic_reg);
1626 // Branch to miss code, checks xcc or icc depending
1627 __ trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2);
1628 }
1629
1630 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
1631 return MachNode::size(ra_);
1632 }
1633
1634
1635 //=============================================================================
1636
1637 uint size_exception_handler() {
1638 if (TraceJumps) {
1639 return (400); // just a guess
1640 }
1641 return ( NativeJump::instruction_size ); // sethi;jmp;nop
1642 }
1643
1644 uint size_deopt_handler() {
1645 if (TraceJumps) {
1646 return (400); // just a guess
1647 }
1648 return ( 4+ NativeJump::instruction_size ); // save;sethi;jmp;restore
1649 }
1650
1651 // Emit exception handler code.
1652 int emit_exception_handler(CodeBuffer& cbuf) {
1653 Register temp_reg = G3;
1654 AddressLiteral exception_blob(OptoRuntime::exception_blob()->instructions_begin());
1655 MacroAssembler _masm(&cbuf);
1656
1657 address base =
1658 __ start_a_stub(size_exception_handler());
1659 if (base == NULL) return 0; // CodeBuffer::expand failed
1660
1661 int offset = __ offset();
1662
1663 __ JUMP(exception_blob, temp_reg, 0); // sethi;jmp
1664 __ delayed()->nop();
1665
1666 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
1667
1668 __ end_a_stub();
1669
1670 return offset;
1671 }
1672
1673 int emit_deopt_handler(CodeBuffer& cbuf) {
1674 // Can't use any of the current frame's registers as we may have deopted
1675 // at a poll and everything (including G3) can be live.
1676 Register temp_reg = L0;
1677 AddressLiteral deopt_blob(SharedRuntime::deopt_blob()->unpack());
1678 MacroAssembler _masm(&cbuf);
1679
1680 address base =
1681 __ start_a_stub(size_deopt_handler());
1682 if (base == NULL) return 0; // CodeBuffer::expand failed
1683
1684 int offset = __ offset();
1685 __ save_frame(0);
1686 __ JUMP(deopt_blob, temp_reg, 0); // sethi;jmp
1687 __ delayed()->restore();
1688
1689 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
1690
1691 __ end_a_stub();
1692 return offset;
1693
1694 }
1695
1696 // Given a register encoding, produce a Integer Register object
1697 static Register reg_to_register_object(int register_encoding) {
1698 assert(L5->encoding() == R_L5_enc && G1->encoding() == R_G1_enc, "right coding");
1699 return as_Register(register_encoding);
1700 }
1701
1702 // Given a register encoding, produce a single-precision Float Register object
1703 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding) {
1704 assert(F5->encoding(FloatRegisterImpl::S) == R_F5_enc && F12->encoding(FloatRegisterImpl::S) == R_F12_enc, "right coding");
1705 return as_SingleFloatRegister(register_encoding);
1706 }
1707
1708 // Given a register encoding, produce a double-precision Float Register object
1709 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding) {
1710 assert(F4->encoding(FloatRegisterImpl::D) == R_F4_enc, "right coding");
1711 assert(F32->encoding(FloatRegisterImpl::D) == R_D32_enc, "right coding");
1712 return as_DoubleFloatRegister(register_encoding);
1713 }
1714
1715 const bool Matcher::match_rule_supported(int opcode) {
1716 if (!has_match_rule(opcode))
1717 return false;
1718
1719 switch (opcode) {
1720 case Op_CountLeadingZerosI:
1721 case Op_CountLeadingZerosL:
1722 case Op_CountTrailingZerosI:
1723 case Op_CountTrailingZerosL:
1724 if (!UsePopCountInstruction)
1725 return false;
1726 break;
1727 }
1728
1729 return true; // Per default match rules are supported.
1730 }
1731
1732 int Matcher::regnum_to_fpu_offset(int regnum) {
1733 return regnum - 32; // The FP registers are in the second chunk
1734 }
1735
1736 #ifdef ASSERT
1737 address last_rethrow = NULL; // debugging aid for Rethrow encoding
1738 #endif
1739
1740 // Vector width in bytes
1741 const uint Matcher::vector_width_in_bytes(void) {
1742 return 8;
1743 }
1744
1745 // Vector ideal reg
1746 const uint Matcher::vector_ideal_reg(void) {
1747 return Op_RegD;
1748 }
1749
1750 // USII supports fxtof through the whole range of number, USIII doesn't
1751 const bool Matcher::convL2FSupported(void) {
1752 return VM_Version::has_fast_fxtof();
1753 }
1754
1755 // Is this branch offset short enough that a short branch can be used?
1756 //
1757 // NOTE: If the platform does not provide any short branch variants, then
1758 // this method should return false for offset 0.
1759 bool Matcher::is_short_branch_offset(int rule, int offset) {
1760 return false;
1761 }
1762
1763 const bool Matcher::isSimpleConstant64(jlong value) {
1764 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1765 // Depends on optimizations in MacroAssembler::setx.
1766 int hi = (int)(value >> 32);
1767 int lo = (int)(value & ~0);
1768 return (hi == 0) || (hi == -1) || (lo == 0);
1769 }
1770
1771 // No scaling for the parameter the ClearArray node.
1772 const bool Matcher::init_array_count_is_in_bytes = true;
1773
1774 // Threshold size for cleararray.
1775 const int Matcher::init_array_short_size = 8 * BytesPerLong;
1776
1777 // Should the Matcher clone shifts on addressing modes, expecting them to
1778 // be subsumed into complex addressing expressions or compute them into
1779 // registers? True for Intel but false for most RISCs
1780 const bool Matcher::clone_shift_expressions = false;
1781
1782 // Is it better to copy float constants, or load them directly from memory?
1783 // Intel can load a float constant from a direct address, requiring no
1784 // extra registers. Most RISCs will have to materialize an address into a
1785 // register first, so they would do better to copy the constant from stack.
1786 const bool Matcher::rematerialize_float_constants = false;
1787
1788 // If CPU can load and store mis-aligned doubles directly then no fixup is
1789 // needed. Else we split the double into 2 integer pieces and move it
1790 // piece-by-piece. Only happens when passing doubles into C code as the
1791 // Java calling convention forces doubles to be aligned.
1792 #ifdef _LP64
1793 const bool Matcher::misaligned_doubles_ok = true;
1794 #else
1795 const bool Matcher::misaligned_doubles_ok = false;
1796 #endif
1797
1798 // No-op on SPARC.
1799 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
1800 }
1801
1802 // Advertise here if the CPU requires explicit rounding operations
1803 // to implement the UseStrictFP mode.
1804 const bool Matcher::strict_fp_requires_explicit_rounding = false;
1805
1806 // Do floats take an entire double register or just half?
1807 const bool Matcher::float_in_double = false;
1808
1809 // Do ints take an entire long register or just half?
1810 // Note that we if-def off of _LP64.
1811 // The relevant question is how the int is callee-saved. In _LP64
1812 // the whole long is written but de-opt'ing will have to extract
1813 // the relevant 32 bits, in not-_LP64 only the low 32 bits is written.
1814 #ifdef _LP64
1815 const bool Matcher::int_in_long = true;
1816 #else
1817 const bool Matcher::int_in_long = false;
1818 #endif
1819
1820 // Return whether or not this register is ever used as an argument. This
1821 // function is used on startup to build the trampoline stubs in generateOptoStub.
1822 // Registers not mentioned will be killed by the VM call in the trampoline, and
1823 // arguments in those registers not be available to the callee.
1824 bool Matcher::can_be_java_arg( int reg ) {
1825 // Standard sparc 6 args in registers
1826 if( reg == R_I0_num ||
1827 reg == R_I1_num ||
1828 reg == R_I2_num ||
1829 reg == R_I3_num ||
1830 reg == R_I4_num ||
1831 reg == R_I5_num ) return true;
1832 #ifdef _LP64
1833 // 64-bit builds can pass 64-bit pointers and longs in
1834 // the high I registers
1835 if( reg == R_I0H_num ||
1836 reg == R_I1H_num ||
1837 reg == R_I2H_num ||
1838 reg == R_I3H_num ||
1839 reg == R_I4H_num ||
1840 reg == R_I5H_num ) return true;
1841
1842 if ((UseCompressedOops) && (reg == R_G6_num || reg == R_G6H_num)) {
1843 return true;
1844 }
1845
1846 #else
1847 // 32-bit builds with longs-in-one-entry pass longs in G1 & G4.
1848 // Longs cannot be passed in O regs, because O regs become I regs
1849 // after a 'save' and I regs get their high bits chopped off on
1850 // interrupt.
1851 if( reg == R_G1H_num || reg == R_G1_num ) return true;
1852 if( reg == R_G4H_num || reg == R_G4_num ) return true;
1853 #endif
1854 // A few float args in registers
1855 if( reg >= R_F0_num && reg <= R_F7_num ) return true;
1856
1857 return false;
1858 }
1859
1860 bool Matcher::is_spillable_arg( int reg ) {
1861 return can_be_java_arg(reg);
1862 }
1863
1864 // Register for DIVI projection of divmodI
1865 RegMask Matcher::divI_proj_mask() {
1866 ShouldNotReachHere();
1867 return RegMask();
1868 }
1869
1870 // Register for MODI projection of divmodI
1871 RegMask Matcher::modI_proj_mask() {
1872 ShouldNotReachHere();
1873 return RegMask();
1874 }
1875
1876 // Register for DIVL projection of divmodL
1877 RegMask Matcher::divL_proj_mask() {
1878 ShouldNotReachHere();
1879 return RegMask();
1880 }
1881
1882 // Register for MODL projection of divmodL
1883 RegMask Matcher::modL_proj_mask() {
1884 ShouldNotReachHere();
1885 return RegMask();
1886 }
1887
1888 %}
1889
1890
1891 // The intptr_t operand types, defined by textual substitution.
1892 // (Cf. opto/type.hpp. This lets us avoid many, many other ifdefs.)
1893 #ifdef _LP64
1894 #define immX immL
1895 #define immX13 immL13
1896 #define iRegX iRegL
1897 #define g1RegX g1RegL
1898 #else
1899 #define immX immI
1900 #define immX13 immI13
1901 #define iRegX iRegI
1902 #define g1RegX g1RegI
1903 #endif
1904
1905 //----------ENCODING BLOCK-----------------------------------------------------
1906 // This block specifies the encoding classes used by the compiler to output
1907 // byte streams. Encoding classes are parameterized macros used by
1908 // Machine Instruction Nodes in order to generate the bit encoding of the
1909 // instruction. Operands specify their base encoding interface with the
1910 // interface keyword. There are currently supported four interfaces,
1911 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
1912 // operand to generate a function which returns its register number when
1913 // queried. CONST_INTER causes an operand to generate a function which
1914 // returns the value of the constant when queried. MEMORY_INTER causes an
1915 // operand to generate four functions which return the Base Register, the
1916 // Index Register, the Scale Value, and the Offset Value of the operand when
1917 // queried. COND_INTER causes an operand to generate six functions which
1918 // return the encoding code (ie - encoding bits for the instruction)
1919 // associated with each basic boolean condition for a conditional instruction.
1920 //
1921 // Instructions specify two basic values for encoding. Again, a function
1922 // is available to check if the constant displacement is an oop. They use the
1923 // ins_encode keyword to specify their encoding classes (which must be
1924 // a sequence of enc_class names, and their parameters, specified in
1925 // the encoding block), and they use the
1926 // opcode keyword to specify, in order, their primary, secondary, and
1927 // tertiary opcode. Only the opcode sections which a particular instruction
1928 // needs for encoding need to be specified.
1929 encode %{
1930 enc_class enc_untested %{
1931 #ifdef ASSERT
1932 MacroAssembler _masm(&cbuf);
1933 __ untested("encoding");
1934 #endif
1935 %}
1936
1937 enc_class form3_mem_reg( memory mem, iRegI dst ) %{
1938 emit_form3_mem_reg(cbuf, this, $primary, $tertiary,
1939 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg);
1940 %}
1941
1942 enc_class simple_form3_mem_reg( memory mem, iRegI dst ) %{
1943 emit_form3_mem_reg(cbuf, this, $primary, -1,
1944 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg);
1945 %}
1946
1947 enc_class form3_mem_reg_little( memory mem, iRegI dst) %{
1948 emit_form3_mem_reg_asi(cbuf, this, $primary, -1,
1949 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg, Assembler::ASI_PRIMARY_LITTLE);
1950 %}
1951
1952 enc_class form3_mem_prefetch_read( memory mem ) %{
1953 emit_form3_mem_reg(cbuf, this, $primary, -1,
1954 $mem$$base, $mem$$disp, $mem$$index, 0/*prefetch function many-reads*/);
1955 %}
1956
1957 enc_class form3_mem_prefetch_write( memory mem ) %{
1958 emit_form3_mem_reg(cbuf, this, $primary, -1,
1959 $mem$$base, $mem$$disp, $mem$$index, 2/*prefetch function many-writes*/);
1960 %}
1961
1962 enc_class form3_mem_reg_long_unaligned_marshal( memory mem, iRegL reg ) %{
1963 assert( Assembler::is_simm13($mem$$disp ), "need disp and disp+4" );
1964 assert( Assembler::is_simm13($mem$$disp+4), "need disp and disp+4" );
1965 guarantee($mem$$index == R_G0_enc, "double index?");
1966 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, R_O7_enc );
1967 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg );
1968 emit3_simm13( cbuf, Assembler::arith_op, $reg$$reg, Assembler::sllx_op3, $reg$$reg, 0x1020 );
1969 emit3( cbuf, Assembler::arith_op, $reg$$reg, Assembler::or_op3, $reg$$reg, 0, R_O7_enc );
1970 %}
1971
1972 enc_class form3_mem_reg_double_unaligned( memory mem, RegD_low reg ) %{
1973 assert( Assembler::is_simm13($mem$$disp ), "need disp and disp+4" );
1974 assert( Assembler::is_simm13($mem$$disp+4), "need disp and disp+4" );
1975 guarantee($mem$$index == R_G0_enc, "double index?");
1976 // Load long with 2 instructions
1977 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg+0 );
1978 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, $reg$$reg+1 );
1979 %}
1980
1981 //%%% form3_mem_plus_4_reg is a hack--get rid of it
1982 enc_class form3_mem_plus_4_reg( memory mem, iRegI dst ) %{
1983 guarantee($mem$$disp, "cannot offset a reg-reg operand by 4");
1984 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp + 4, $mem$$index, $dst$$reg);
1985 %}
1986
1987 enc_class form3_g0_rs2_rd_move( iRegI rs2, iRegI rd ) %{
1988 // Encode a reg-reg copy. If it is useless, then empty encoding.
1989 if( $rs2$$reg != $rd$$reg )
1990 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, $rs2$$reg );
1991 %}
1992
1993 // Target lo half of long
1994 enc_class form3_g0_rs2_rd_move_lo( iRegI rs2, iRegL rd ) %{
1995 // Encode a reg-reg copy. If it is useless, then empty encoding.
1996 if( $rs2$$reg != LONG_LO_REG($rd$$reg) )
1997 emit3( cbuf, Assembler::arith_op, LONG_LO_REG($rd$$reg), Assembler::or_op3, 0, 0, $rs2$$reg );
1998 %}
1999
2000 // Source lo half of long
2001 enc_class form3_g0_rs2_rd_move_lo2( iRegL rs2, iRegI rd ) %{
2002 // Encode a reg-reg copy. If it is useless, then empty encoding.
2003 if( LONG_LO_REG($rs2$$reg) != $rd$$reg )
2004 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_LO_REG($rs2$$reg) );
2005 %}
2006
2007 // Target hi half of long
2008 enc_class form3_rs1_rd_copysign_hi( iRegI rs1, iRegL rd ) %{
2009 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 31 );
2010 %}
2011
2012 // Source lo half of long, and leave it sign extended.
2013 enc_class form3_rs1_rd_signextend_lo1( iRegL rs1, iRegI rd ) %{
2014 // Sign extend low half
2015 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 0, 0 );
2016 %}
2017
2018 // Source hi half of long, and leave it sign extended.
2019 enc_class form3_rs1_rd_copy_hi1( iRegL rs1, iRegI rd ) %{
2020 // Shift high half to low half
2021 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::srlx_op3, $rs1$$reg, 32 );
2022 %}
2023
2024 // Source hi half of long
2025 enc_class form3_g0_rs2_rd_move_hi2( iRegL rs2, iRegI rd ) %{
2026 // Encode a reg-reg copy. If it is useless, then empty encoding.
2027 if( LONG_HI_REG($rs2$$reg) != $rd$$reg )
2028 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_HI_REG($rs2$$reg) );
2029 %}
2030
2031 enc_class form3_rs1_rs2_rd( iRegI rs1, iRegI rs2, iRegI rd ) %{
2032 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0, $rs2$$reg );
2033 %}
2034
2035 enc_class enc_to_bool( iRegI src, iRegI dst ) %{
2036 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, 0, 0, $src$$reg );
2037 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::addc_op3 , 0, 0 );
2038 %}
2039
2040 enc_class enc_ltmask( iRegI p, iRegI q, iRegI dst ) %{
2041 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $p$$reg, 0, $q$$reg );
2042 // clear if nothing else is happening
2043 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 0 );
2044 // blt,a,pn done
2045 emit2_19 ( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less, Assembler::bp_op2, Assembler::icc, 0/*predict not taken*/, 2 );
2046 // mov dst,-1 in delay slot
2047 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 );
2048 %}
2049
2050 enc_class form3_rs1_imm5_rd( iRegI rs1, immU5 imm5, iRegI rd ) %{
2051 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $imm5$$constant & 0x1F );
2052 %}
2053
2054 enc_class form3_sd_rs1_imm6_rd( iRegL rs1, immU6 imm6, iRegL rd ) %{
2055 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, ($imm6$$constant & 0x3F) | 0x1000 );
2056 %}
2057
2058 enc_class form3_sd_rs1_rs2_rd( iRegL rs1, iRegI rs2, iRegL rd ) %{
2059 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0x80, $rs2$$reg );
2060 %}
2061
2062 enc_class form3_rs1_simm13_rd( iRegI rs1, immI13 simm13, iRegI rd ) %{
2063 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $simm13$$constant );
2064 %}
2065
2066 enc_class move_return_pc_to_o1() %{
2067 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::add_op3, R_O7_enc, frame::pc_return_offset );
2068 %}
2069
2070 #ifdef _LP64
2071 /* %%% merge with enc_to_bool */
2072 enc_class enc_convP2B( iRegI dst, iRegP src ) %{
2073 MacroAssembler _masm(&cbuf);
2074
2075 Register src_reg = reg_to_register_object($src$$reg);
2076 Register dst_reg = reg_to_register_object($dst$$reg);
2077 __ movr(Assembler::rc_nz, src_reg, 1, dst_reg);
2078 %}
2079 #endif
2080
2081 enc_class enc_cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp ) %{
2082 // (Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)))
2083 MacroAssembler _masm(&cbuf);
2084
2085 Register p_reg = reg_to_register_object($p$$reg);
2086 Register q_reg = reg_to_register_object($q$$reg);
2087 Register y_reg = reg_to_register_object($y$$reg);
2088 Register tmp_reg = reg_to_register_object($tmp$$reg);
2089
2090 __ subcc( p_reg, q_reg, p_reg );
2091 __ add ( p_reg, y_reg, tmp_reg );
2092 __ movcc( Assembler::less, false, Assembler::icc, tmp_reg, p_reg );
2093 %}
2094
2095 enc_class form_d2i_helper(regD src, regF dst) %{
2096 // fcmp %fcc0,$src,$src
2097 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg );
2098 // branch %fcc0 not-nan, predict taken
2099 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2100 // fdtoi $src,$dst
2101 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtoi_opf, $src$$reg );
2102 // fitos $dst,$dst (if nan)
2103 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg );
2104 // clear $dst (if nan)
2105 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg );
2106 // carry on here...
2107 %}
2108
2109 enc_class form_d2l_helper(regD src, regD dst) %{
2110 // fcmp %fcc0,$src,$src check for NAN
2111 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg );
2112 // branch %fcc0 not-nan, predict taken
2113 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2114 // fdtox $src,$dst convert in delay slot
2115 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtox_opf, $src$$reg );
2116 // fxtod $dst,$dst (if nan)
2117 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg );
2118 // clear $dst (if nan)
2119 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg );
2120 // carry on here...
2121 %}
2122
2123 enc_class form_f2i_helper(regF src, regF dst) %{
2124 // fcmps %fcc0,$src,$src
2125 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg );
2126 // branch %fcc0 not-nan, predict taken
2127 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2128 // fstoi $src,$dst
2129 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstoi_opf, $src$$reg );
2130 // fitos $dst,$dst (if nan)
2131 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg );
2132 // clear $dst (if nan)
2133 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg );
2134 // carry on here...
2135 %}
2136
2137 enc_class form_f2l_helper(regF src, regD dst) %{
2138 // fcmps %fcc0,$src,$src
2139 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg );
2140 // branch %fcc0 not-nan, predict taken
2141 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2142 // fstox $src,$dst
2143 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstox_opf, $src$$reg );
2144 // fxtod $dst,$dst (if nan)
2145 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg );
2146 // clear $dst (if nan)
2147 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg );
2148 // carry on here...
2149 %}
2150
2151 enc_class form3_opf_rs2F_rdF(regF rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2152 enc_class form3_opf_rs2F_rdD(regF rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2153 enc_class form3_opf_rs2D_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2154 enc_class form3_opf_rs2D_rdD(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2155
2156 enc_class form3_opf_rs2D_lo_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg+1); %}
2157
2158 enc_class form3_opf_rs2D_hi_rdD_hi(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2159 enc_class form3_opf_rs2D_lo_rdD_lo(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg+1,$primary,0,$tertiary,$rs2$$reg+1); %}
2160
2161 enc_class form3_opf_rs1F_rs2F_rdF( regF rs1, regF rs2, regF rd ) %{
2162 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2163 %}
2164
2165 enc_class form3_opf_rs1D_rs2D_rdD( regD rs1, regD rs2, regD rd ) %{
2166 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2167 %}
2168
2169 enc_class form3_opf_rs1F_rs2F_fcc( regF rs1, regF rs2, flagsRegF fcc ) %{
2170 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2171 %}
2172
2173 enc_class form3_opf_rs1D_rs2D_fcc( regD rs1, regD rs2, flagsRegF fcc ) %{
2174 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2175 %}
2176
2177 enc_class form3_convI2F(regF rs2, regF rd) %{
2178 emit3(cbuf,Assembler::arith_op,$rd$$reg,Assembler::fpop1_op3,0,$secondary,$rs2$$reg);
2179 %}
2180
2181 // Encloding class for traceable jumps
2182 enc_class form_jmpl(g3RegP dest) %{
2183 emit_jmpl(cbuf, $dest$$reg);
2184 %}
2185
2186 enc_class form_jmpl_set_exception_pc(g1RegP dest) %{
2187 emit_jmpl_set_exception_pc(cbuf, $dest$$reg);
2188 %}
2189
2190 enc_class form2_nop() %{
2191 emit_nop(cbuf);
2192 %}
2193
2194 enc_class form2_illtrap() %{
2195 emit_illtrap(cbuf);
2196 %}
2197
2198
2199 // Compare longs and convert into -1, 0, 1.
2200 enc_class cmpl_flag( iRegL src1, iRegL src2, iRegI dst ) %{
2201 // CMP $src1,$src2
2202 emit3( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $src1$$reg, 0, $src2$$reg );
2203 // blt,a,pn done
2204 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less , Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 5 );
2205 // mov dst,-1 in delay slot
2206 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 );
2207 // bgt,a,pn done
2208 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::greater, Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 3 );
2209 // mov dst,1 in delay slot
2210 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 1 );
2211 // CLR $dst
2212 emit3( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3 , 0, 0, 0 );
2213 %}
2214
2215 enc_class enc_PartialSubtypeCheck() %{
2216 MacroAssembler _masm(&cbuf);
2217 __ call(StubRoutines::Sparc::partial_subtype_check(), relocInfo::runtime_call_type);
2218 __ delayed()->nop();
2219 %}
2220
2221 enc_class enc_bp( Label labl, cmpOp cmp, flagsReg cc ) %{
2222 MacroAssembler _masm(&cbuf);
2223 Label &L = *($labl$$label);
2224 Assembler::Predict predict_taken =
2225 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn;
2226
2227 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, L);
2228 __ delayed()->nop();
2229 %}
2230
2231 enc_class enc_bpl( Label labl, cmpOp cmp, flagsRegL cc ) %{
2232 MacroAssembler _masm(&cbuf);
2233 Label &L = *($labl$$label);
2234 Assembler::Predict predict_taken =
2235 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn;
2236
2237 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, L);
2238 __ delayed()->nop();
2239 %}
2240
2241 enc_class enc_bpx( Label labl, cmpOp cmp, flagsRegP cc ) %{
2242 MacroAssembler _masm(&cbuf);
2243 Label &L = *($labl$$label);
2244 Assembler::Predict predict_taken =
2245 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn;
2246
2247 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, L);
2248 __ delayed()->nop();
2249 %}
2250
2251 enc_class enc_fbp( Label labl, cmpOpF cmp, flagsRegF cc ) %{
2252 MacroAssembler _masm(&cbuf);
2253 Label &L = *($labl$$label);
2254 Assembler::Predict predict_taken =
2255 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn;
2256
2257 __ fbp( (Assembler::Condition)($cmp$$cmpcode), false, (Assembler::CC)($cc$$reg), predict_taken, L);
2258 __ delayed()->nop();
2259 %}
2260
2261 enc_class jump_enc( iRegX switch_val, o7RegI table) %{
2262 MacroAssembler _masm(&cbuf);
2263
2264 Register switch_reg = as_Register($switch_val$$reg);
2265 Register table_reg = O7;
2266
2267 address table_base = __ address_table_constant(_index2label);
2268 RelocationHolder rspec = internal_word_Relocation::spec(table_base);
2269
2270 // Move table address into a register.
2271 __ set(table_base, table_reg, rspec);
2272
2273 // Jump to base address + switch value
2274 __ ld_ptr(table_reg, switch_reg, table_reg);
2275 __ jmp(table_reg, G0);
2276 __ delayed()->nop();
2277
2278 %}
2279
2280 enc_class enc_ba( Label labl ) %{
2281 MacroAssembler _masm(&cbuf);
2282 Label &L = *($labl$$label);
2283 __ ba(false, L);
2284 __ delayed()->nop();
2285 %}
2286
2287 enc_class enc_bpr( Label labl, cmpOp_reg cmp, iRegI op1 ) %{
2288 MacroAssembler _masm(&cbuf);
2289 Label &L = *$labl$$label;
2290 Assembler::Predict predict_taken =
2291 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn;
2292
2293 __ bpr( (Assembler::RCondition)($cmp$$cmpcode), false, predict_taken, as_Register($op1$$reg), L);
2294 __ delayed()->nop();
2295 %}
2296
2297 enc_class enc_cmov_reg( cmpOp cmp, iRegI dst, iRegI src, immI pcc) %{
2298 int op = (Assembler::arith_op << 30) |
2299 ($dst$$reg << 25) |
2300 (Assembler::movcc_op3 << 19) |
2301 (1 << 18) | // cc2 bit for 'icc'
2302 ($cmp$$cmpcode << 14) |
2303 (0 << 13) | // select register move
2304 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc' or 'xcc'
2305 ($src$$reg << 0);
2306 *((int*)(cbuf.code_end())) = op;
2307 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
2308 %}
2309
2310 enc_class enc_cmov_imm( cmpOp cmp, iRegI dst, immI11 src, immI pcc ) %{
2311 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits
2312 int op = (Assembler::arith_op << 30) |
2313 ($dst$$reg << 25) |
2314 (Assembler::movcc_op3 << 19) |
2315 (1 << 18) | // cc2 bit for 'icc'
2316 ($cmp$$cmpcode << 14) |
2317 (1 << 13) | // select immediate move
2318 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc'
2319 (simm11 << 0);
2320 *((int*)(cbuf.code_end())) = op;
2321 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
2322 %}
2323
2324 enc_class enc_cmov_reg_f( cmpOpF cmp, iRegI dst, iRegI src, flagsRegF fcc ) %{
2325 int op = (Assembler::arith_op << 30) |
2326 ($dst$$reg << 25) |
2327 (Assembler::movcc_op3 << 19) |
2328 (0 << 18) | // cc2 bit for 'fccX'
2329 ($cmp$$cmpcode << 14) |
2330 (0 << 13) | // select register move
2331 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3
2332 ($src$$reg << 0);
2333 *((int*)(cbuf.code_end())) = op;
2334 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
2335 %}
2336
2337 enc_class enc_cmov_imm_f( cmpOp cmp, iRegI dst, immI11 src, flagsRegF fcc ) %{
2338 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits
2339 int op = (Assembler::arith_op << 30) |
2340 ($dst$$reg << 25) |
2341 (Assembler::movcc_op3 << 19) |
2342 (0 << 18) | // cc2 bit for 'fccX'
2343 ($cmp$$cmpcode << 14) |
2344 (1 << 13) | // select immediate move
2345 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3
2346 (simm11 << 0);
2347 *((int*)(cbuf.code_end())) = op;
2348 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
2349 %}
2350
2351 enc_class enc_cmovf_reg( cmpOp cmp, regD dst, regD src, immI pcc ) %{
2352 int op = (Assembler::arith_op << 30) |
2353 ($dst$$reg << 25) |
2354 (Assembler::fpop2_op3 << 19) |
2355 (0 << 18) |
2356 ($cmp$$cmpcode << 14) |
2357 (1 << 13) | // select register move
2358 ($pcc$$constant << 11) | // cc1-cc0 bits for 'icc' or 'xcc'
2359 ($primary << 5) | // select single, double or quad
2360 ($src$$reg << 0);
2361 *((int*)(cbuf.code_end())) = op;
2362 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
2363 %}
2364
2365 enc_class enc_cmovff_reg( cmpOpF cmp, flagsRegF fcc, regD dst, regD src ) %{
2366 int op = (Assembler::arith_op << 30) |
2367 ($dst$$reg << 25) |
2368 (Assembler::fpop2_op3 << 19) |
2369 (0 << 18) |
2370 ($cmp$$cmpcode << 14) |
2371 ($fcc$$reg << 11) | // cc2-cc0 bits for 'fccX'
2372 ($primary << 5) | // select single, double or quad
2373 ($src$$reg << 0);
2374 *((int*)(cbuf.code_end())) = op;
2375 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
2376 %}
2377
2378 // Used by the MIN/MAX encodings. Same as a CMOV, but
2379 // the condition comes from opcode-field instead of an argument.
2380 enc_class enc_cmov_reg_minmax( iRegI dst, iRegI src ) %{
2381 int op = (Assembler::arith_op << 30) |
2382 ($dst$$reg << 25) |
2383 (Assembler::movcc_op3 << 19) |
2384 (1 << 18) | // cc2 bit for 'icc'
2385 ($primary << 14) |
2386 (0 << 13) | // select register move
2387 (0 << 11) | // cc1, cc0 bits for 'icc'
2388 ($src$$reg << 0);
2389 *((int*)(cbuf.code_end())) = op;
2390 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
2391 %}
2392
2393 enc_class enc_cmov_reg_minmax_long( iRegL dst, iRegL src ) %{
2394 int op = (Assembler::arith_op << 30) |
2395 ($dst$$reg << 25) |
2396 (Assembler::movcc_op3 << 19) |
2397 (6 << 16) | // cc2 bit for 'xcc'
2398 ($primary << 14) |
2399 (0 << 13) | // select register move
2400 (0 << 11) | // cc1, cc0 bits for 'icc'
2401 ($src$$reg << 0);
2402 *((int*)(cbuf.code_end())) = op;
2403 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
2404 %}
2405
2406 // Utility encoding for loading a 64 bit Pointer into a register
2407 // The 64 bit pointer is stored in the generated code stream
2408 enc_class SetPtr( immP src, iRegP rd ) %{
2409 Register dest = reg_to_register_object($rd$$reg);
2410 MacroAssembler _masm(&cbuf);
2411 // [RGV] This next line should be generated from ADLC
2412 if ( _opnds[1]->constant_is_oop() ) {
2413 intptr_t val = $src$$constant;
2414 __ set_oop_constant((jobject)val, dest);
2415 } else { // non-oop pointers, e.g. card mark base, heap top
2416 __ set($src$$constant, dest);
2417 }
2418 %}
2419
2420 enc_class Set13( immI13 src, iRegI rd ) %{
2421 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, $src$$constant );
2422 %}
2423
2424 enc_class SetHi22( immI src, iRegI rd ) %{
2425 emit2_22( cbuf, Assembler::branch_op, $rd$$reg, Assembler::sethi_op2, $src$$constant );
2426 %}
2427
2428 enc_class Set32( immI src, iRegI rd ) %{
2429 MacroAssembler _masm(&cbuf);
2430 __ set($src$$constant, reg_to_register_object($rd$$reg));
2431 %}
2432
2433 enc_class SetNull( iRegI rd ) %{
2434 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0 );
2435 %}
2436
2437 enc_class call_epilog %{
2438 if( VerifyStackAtCalls ) {
2439 MacroAssembler _masm(&cbuf);
2440 int framesize = ra_->C->frame_slots() << LogBytesPerInt;
2441 Register temp_reg = G3;
2442 __ add(SP, framesize, temp_reg);
2443 __ cmp(temp_reg, FP);
2444 __ breakpoint_trap(Assembler::notEqual, Assembler::ptr_cc);
2445 }
2446 %}
2447
2448 // Long values come back from native calls in O0:O1 in the 32-bit VM, copy the value
2449 // to G1 so the register allocator will not have to deal with the misaligned register
2450 // pair.
2451 enc_class adjust_long_from_native_call %{
2452 #ifndef _LP64
2453 if (returns_long()) {
2454 // sllx O0,32,O0
2455 emit3_simm13( cbuf, Assembler::arith_op, R_O0_enc, Assembler::sllx_op3, R_O0_enc, 0x1020 );
2456 // srl O1,0,O1
2457 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::srl_op3, R_O1_enc, 0x0000 );
2458 // or O0,O1,G1
2459 emit3 ( cbuf, Assembler::arith_op, R_G1_enc, Assembler:: or_op3, R_O0_enc, 0, R_O1_enc );
2460 }
2461 #endif
2462 %}
2463
2464 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime
2465 // CALL directly to the runtime
2466 // The user of this is responsible for ensuring that R_L7 is empty (killed).
2467 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type,
2468 /*preserve_g2=*/true, /*force far call*/true);
2469 %}
2470
2471 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL
2472 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
2473 // who we intended to call.
2474 if ( !_method ) {
2475 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type);
2476 } else if (_optimized_virtual) {
2477 emit_call_reloc(cbuf, $meth$$method, relocInfo::opt_virtual_call_type);
2478 } else {
2479 emit_call_reloc(cbuf, $meth$$method, relocInfo::static_call_type);
2480 }
2481 if( _method ) { // Emit stub for static call
2482 emit_java_to_interp(cbuf);
2483 }
2484 %}
2485
2486 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL
2487 MacroAssembler _masm(&cbuf);
2488 __ set_inst_mark();
2489 int vtable_index = this->_vtable_index;
2490 // MachCallDynamicJavaNode::ret_addr_offset uses this same test
2491 if (vtable_index < 0) {
2492 // must be invalid_vtable_index, not nonvirtual_vtable_index
2493 assert(vtable_index == methodOopDesc::invalid_vtable_index, "correct sentinel value");
2494 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
2495 assert(G5_ic_reg == G5_inline_cache_reg, "G5_inline_cache_reg used in assemble_ic_buffer_code()");
2496 assert(G5_ic_reg == G5_megamorphic_method, "G5_megamorphic_method used in megamorphic call stub");
2497 // !!!!!
2498 // Generate "set 0x01, R_G5", placeholder instruction to load oop-info
2499 // emit_call_dynamic_prologue( cbuf );
2500 __ set_oop((jobject)Universe::non_oop_word(), G5_ic_reg);
2501
2502 address virtual_call_oop_addr = __ inst_mark();
2503 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
2504 // who we intended to call.
2505 __ relocate(virtual_call_Relocation::spec(virtual_call_oop_addr));
2506 emit_call_reloc(cbuf, $meth$$method, relocInfo::none);
2507 } else {
2508 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
2509 // Just go thru the vtable
2510 // get receiver klass (receiver already checked for non-null)
2511 // If we end up going thru a c2i adapter interpreter expects method in G5
2512 int off = __ offset();
2513 __ load_klass(O0, G3_scratch);
2514 int klass_load_size;
2515 if (UseCompressedOops) {
2516 assert(Universe::heap() != NULL, "java heap should be initialized");
2517 if (Universe::narrow_oop_base() == NULL)
2518 klass_load_size = 2*BytesPerInstWord;
2519 else
2520 klass_load_size = 3*BytesPerInstWord;
2521 } else {
2522 klass_load_size = 1*BytesPerInstWord;
2523 }
2524 int entry_offset = instanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size();
2525 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes();
2526 if( __ is_simm13(v_off) ) {
2527 __ ld_ptr(G3, v_off, G5_method);
2528 } else {
2529 // Generate 2 instructions
2530 __ Assembler::sethi(v_off & ~0x3ff, G5_method);
2531 __ or3(G5_method, v_off & 0x3ff, G5_method);
2532 // ld_ptr, set_hi, set
2533 assert(__ offset() - off == klass_load_size + 2*BytesPerInstWord,
2534 "Unexpected instruction size(s)");
2535 __ ld_ptr(G3, G5_method, G5_method);
2536 }
2537 // NOTE: for vtable dispatches, the vtable entry will never be null.
2538 // However it may very well end up in handle_wrong_method if the
2539 // method is abstract for the particular class.
2540 __ ld_ptr(G5_method, in_bytes(methodOopDesc::from_compiled_offset()), G3_scratch);
2541 // jump to target (either compiled code or c2iadapter)
2542 __ jmpl(G3_scratch, G0, O7);
2543 __ delayed()->nop();
2544 }
2545 %}
2546
2547 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL
2548 MacroAssembler _masm(&cbuf);
2549
2550 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
2551 Register temp_reg = G3; // caller must kill G3! We cannot reuse G5_ic_reg here because
2552 // we might be calling a C2I adapter which needs it.
2553
2554 assert(temp_reg != G5_ic_reg, "conflicting registers");
2555 // Load nmethod
2556 __ ld_ptr(G5_ic_reg, in_bytes(methodOopDesc::from_compiled_offset()), temp_reg);
2557
2558 // CALL to compiled java, indirect the contents of G3
2559 __ set_inst_mark();
2560 __ callr(temp_reg, G0);
2561 __ delayed()->nop();
2562 %}
2563
2564 enc_class idiv_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst) %{
2565 MacroAssembler _masm(&cbuf);
2566 Register Rdividend = reg_to_register_object($src1$$reg);
2567 Register Rdivisor = reg_to_register_object($src2$$reg);
2568 Register Rresult = reg_to_register_object($dst$$reg);
2569
2570 __ sra(Rdivisor, 0, Rdivisor);
2571 __ sra(Rdividend, 0, Rdividend);
2572 __ sdivx(Rdividend, Rdivisor, Rresult);
2573 %}
2574
2575 enc_class idiv_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst) %{
2576 MacroAssembler _masm(&cbuf);
2577
2578 Register Rdividend = reg_to_register_object($src1$$reg);
2579 int divisor = $imm$$constant;
2580 Register Rresult = reg_to_register_object($dst$$reg);
2581
2582 __ sra(Rdividend, 0, Rdividend);
2583 __ sdivx(Rdividend, divisor, Rresult);
2584 %}
2585
2586 enc_class enc_mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2) %{
2587 MacroAssembler _masm(&cbuf);
2588 Register Rsrc1 = reg_to_register_object($src1$$reg);
2589 Register Rsrc2 = reg_to_register_object($src2$$reg);
2590 Register Rdst = reg_to_register_object($dst$$reg);
2591
2592 __ sra( Rsrc1, 0, Rsrc1 );
2593 __ sra( Rsrc2, 0, Rsrc2 );
2594 __ mulx( Rsrc1, Rsrc2, Rdst );
2595 __ srlx( Rdst, 32, Rdst );
2596 %}
2597
2598 enc_class irem_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst, o7RegL scratch) %{
2599 MacroAssembler _masm(&cbuf);
2600 Register Rdividend = reg_to_register_object($src1$$reg);
2601 Register Rdivisor = reg_to_register_object($src2$$reg);
2602 Register Rresult = reg_to_register_object($dst$$reg);
2603 Register Rscratch = reg_to_register_object($scratch$$reg);
2604
2605 assert(Rdividend != Rscratch, "");
2606 assert(Rdivisor != Rscratch, "");
2607
2608 __ sra(Rdividend, 0, Rdividend);
2609 __ sra(Rdivisor, 0, Rdivisor);
2610 __ sdivx(Rdividend, Rdivisor, Rscratch);
2611 __ mulx(Rscratch, Rdivisor, Rscratch);
2612 __ sub(Rdividend, Rscratch, Rresult);
2613 %}
2614
2615 enc_class irem_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst, o7RegL scratch) %{
2616 MacroAssembler _masm(&cbuf);
2617
2618 Register Rdividend = reg_to_register_object($src1$$reg);
2619 int divisor = $imm$$constant;
2620 Register Rresult = reg_to_register_object($dst$$reg);
2621 Register Rscratch = reg_to_register_object($scratch$$reg);
2622
2623 assert(Rdividend != Rscratch, "");
2624
2625 __ sra(Rdividend, 0, Rdividend);
2626 __ sdivx(Rdividend, divisor, Rscratch);
2627 __ mulx(Rscratch, divisor, Rscratch);
2628 __ sub(Rdividend, Rscratch, Rresult);
2629 %}
2630
2631 enc_class fabss (sflt_reg dst, sflt_reg src) %{
2632 MacroAssembler _masm(&cbuf);
2633
2634 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2635 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2636
2637 __ fabs(FloatRegisterImpl::S, Fsrc, Fdst);
2638 %}
2639
2640 enc_class fabsd (dflt_reg dst, dflt_reg src) %{
2641 MacroAssembler _masm(&cbuf);
2642
2643 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2644 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2645
2646 __ fabs(FloatRegisterImpl::D, Fsrc, Fdst);
2647 %}
2648
2649 enc_class fnegd (dflt_reg dst, dflt_reg src) %{
2650 MacroAssembler _masm(&cbuf);
2651
2652 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2653 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2654
2655 __ fneg(FloatRegisterImpl::D, Fsrc, Fdst);
2656 %}
2657
2658 enc_class fsqrts (sflt_reg dst, sflt_reg src) %{
2659 MacroAssembler _masm(&cbuf);
2660
2661 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2662 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2663
2664 __ fsqrt(FloatRegisterImpl::S, Fsrc, Fdst);
2665 %}
2666
2667 enc_class fsqrtd (dflt_reg dst, dflt_reg src) %{
2668 MacroAssembler _masm(&cbuf);
2669
2670 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2671 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2672
2673 __ fsqrt(FloatRegisterImpl::D, Fsrc, Fdst);
2674 %}
2675
2676 enc_class fmovs (dflt_reg dst, dflt_reg src) %{
2677 MacroAssembler _masm(&cbuf);
2678
2679 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2680 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2681
2682 __ fmov(FloatRegisterImpl::S, Fsrc, Fdst);
2683 %}
2684
2685 enc_class fmovd (dflt_reg dst, dflt_reg src) %{
2686 MacroAssembler _masm(&cbuf);
2687
2688 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2689 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2690
2691 __ fmov(FloatRegisterImpl::D, Fsrc, Fdst);
2692 %}
2693
2694 enc_class Fast_Lock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{
2695 MacroAssembler _masm(&cbuf);
2696
2697 Register Roop = reg_to_register_object($oop$$reg);
2698 Register Rbox = reg_to_register_object($box$$reg);
2699 Register Rscratch = reg_to_register_object($scratch$$reg);
2700 Register Rmark = reg_to_register_object($scratch2$$reg);
2701
2702 assert(Roop != Rscratch, "");
2703 assert(Roop != Rmark, "");
2704 assert(Rbox != Rscratch, "");
2705 assert(Rbox != Rmark, "");
2706
2707 __ compiler_lock_object(Roop, Rmark, Rbox, Rscratch, _counters, UseBiasedLocking && !UseOptoBiasInlining);
2708 %}
2709
2710 enc_class Fast_Unlock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{
2711 MacroAssembler _masm(&cbuf);
2712
2713 Register Roop = reg_to_register_object($oop$$reg);
2714 Register Rbox = reg_to_register_object($box$$reg);
2715 Register Rscratch = reg_to_register_object($scratch$$reg);
2716 Register Rmark = reg_to_register_object($scratch2$$reg);
2717
2718 assert(Roop != Rscratch, "");
2719 assert(Roop != Rmark, "");
2720 assert(Rbox != Rscratch, "");
2721 assert(Rbox != Rmark, "");
2722
2723 __ compiler_unlock_object(Roop, Rmark, Rbox, Rscratch, UseBiasedLocking && !UseOptoBiasInlining);
2724 %}
2725
2726 enc_class enc_cas( iRegP mem, iRegP old, iRegP new ) %{
2727 MacroAssembler _masm(&cbuf);
2728 Register Rmem = reg_to_register_object($mem$$reg);
2729 Register Rold = reg_to_register_object($old$$reg);
2730 Register Rnew = reg_to_register_object($new$$reg);
2731
2732 // casx_under_lock picks 1 of 3 encodings:
2733 // For 32-bit pointers you get a 32-bit CAS
2734 // For 64-bit pointers you get a 64-bit CASX
2735 __ casn(Rmem, Rold, Rnew); // Swap(*Rmem,Rnew) if *Rmem == Rold
2736 __ cmp( Rold, Rnew );
2737 %}
2738
2739 enc_class enc_casx( iRegP mem, iRegL old, iRegL new) %{
2740 Register Rmem = reg_to_register_object($mem$$reg);
2741 Register Rold = reg_to_register_object($old$$reg);
2742 Register Rnew = reg_to_register_object($new$$reg);
2743
2744 MacroAssembler _masm(&cbuf);
2745 __ mov(Rnew, O7);
2746 __ casx(Rmem, Rold, O7);
2747 __ cmp( Rold, O7 );
2748 %}
2749
2750 // raw int cas, used for compareAndSwap
2751 enc_class enc_casi( iRegP mem, iRegL old, iRegL new) %{
2752 Register Rmem = reg_to_register_object($mem$$reg);
2753 Register Rold = reg_to_register_object($old$$reg);
2754 Register Rnew = reg_to_register_object($new$$reg);
2755
2756 MacroAssembler _masm(&cbuf);
2757 __ mov(Rnew, O7);
2758 __ cas(Rmem, Rold, O7);
2759 __ cmp( Rold, O7 );
2760 %}
2761
2762 enc_class enc_lflags_ne_to_boolean( iRegI res ) %{
2763 Register Rres = reg_to_register_object($res$$reg);
2764
2765 MacroAssembler _masm(&cbuf);
2766 __ mov(1, Rres);
2767 __ movcc( Assembler::notEqual, false, Assembler::xcc, G0, Rres );
2768 %}
2769
2770 enc_class enc_iflags_ne_to_boolean( iRegI res ) %{
2771 Register Rres = reg_to_register_object($res$$reg);
2772
2773 MacroAssembler _masm(&cbuf);
2774 __ mov(1, Rres);
2775 __ movcc( Assembler::notEqual, false, Assembler::icc, G0, Rres );
2776 %}
2777
2778 enc_class floating_cmp ( iRegP dst, regF src1, regF src2 ) %{
2779 MacroAssembler _masm(&cbuf);
2780 Register Rdst = reg_to_register_object($dst$$reg);
2781 FloatRegister Fsrc1 = $primary ? reg_to_SingleFloatRegister_object($src1$$reg)
2782 : reg_to_DoubleFloatRegister_object($src1$$reg);
2783 FloatRegister Fsrc2 = $primary ? reg_to_SingleFloatRegister_object($src2$$reg)
2784 : reg_to_DoubleFloatRegister_object($src2$$reg);
2785
2786 // Convert condition code fcc0 into -1,0,1; unordered reports less-than (-1)
2787 __ float_cmp( $primary, -1, Fsrc1, Fsrc2, Rdst);
2788 %}
2789
2790 enc_class LdImmL (immL src, iRegL dst, o7RegL tmp) %{ // Load Immediate
2791 MacroAssembler _masm(&cbuf);
2792 Register dest = reg_to_register_object($dst$$reg);
2793 Register temp = reg_to_register_object($tmp$$reg);
2794 __ set64( $src$$constant, dest, temp );
2795 %}
2796
2797 enc_class LdReplImmI(immI src, regD dst, o7RegP tmp, int count, int width) %{
2798 // Load a constant replicated "count" times with width "width"
2799 int bit_width = $width$$constant * 8;
2800 jlong elt_val = $src$$constant;
2801 elt_val &= (((jlong)1) << bit_width) - 1; // mask off sign bits
2802 jlong val = elt_val;
2803 for (int i = 0; i < $count$$constant - 1; i++) {
2804 val <<= bit_width;
2805 val |= elt_val;
2806 }
2807 jdouble dval = *(jdouble*)&val; // coerce to double type
2808 MacroAssembler _masm(&cbuf);
2809 address double_address = __ double_constant(dval);
2810 RelocationHolder rspec = internal_word_Relocation::spec(double_address);
2811 AddressLiteral addrlit(double_address, rspec);
2812
2813 __ sethi(addrlit, $tmp$$Register);
2814 __ ldf(FloatRegisterImpl::D, $tmp$$Register, addrlit.low10(), $dst$$FloatRegister, rspec);
2815 %}
2816
2817 // Compiler ensures base is doubleword aligned and cnt is count of doublewords
2818 enc_class enc_Clear_Array(iRegX cnt, iRegP base, iRegX temp) %{
2819 MacroAssembler _masm(&cbuf);
2820 Register nof_bytes_arg = reg_to_register_object($cnt$$reg);
2821 Register nof_bytes_tmp = reg_to_register_object($temp$$reg);
2822 Register base_pointer_arg = reg_to_register_object($base$$reg);
2823
2824 Label loop;
2825 __ mov(nof_bytes_arg, nof_bytes_tmp);
2826
2827 // Loop and clear, walking backwards through the array.
2828 // nof_bytes_tmp (if >0) is always the number of bytes to zero
2829 __ bind(loop);
2830 __ deccc(nof_bytes_tmp, 8);
2831 __ br(Assembler::greaterEqual, true, Assembler::pt, loop);
2832 __ delayed()-> stx(G0, base_pointer_arg, nof_bytes_tmp);
2833 // %%%% this mini-loop must not cross a cache boundary!
2834 %}
2835
2836
2837 enc_class enc_String_Compare(o0RegP str1, o1RegP str2, g3RegP tmp1, g4RegP tmp2, notemp_iRegI result) %{
2838 Label Ldone, Lloop;
2839 MacroAssembler _masm(&cbuf);
2840
2841 Register str1_reg = reg_to_register_object($str1$$reg);
2842 Register str2_reg = reg_to_register_object($str2$$reg);
2843 Register tmp1_reg = reg_to_register_object($tmp1$$reg);
2844 Register tmp2_reg = reg_to_register_object($tmp2$$reg);
2845 Register result_reg = reg_to_register_object($result$$reg);
2846
2847 // Get the first character position in both strings
2848 // [8] char array, [12] offset, [16] count
2849 int value_offset = java_lang_String:: value_offset_in_bytes();
2850 int offset_offset = java_lang_String::offset_offset_in_bytes();
2851 int count_offset = java_lang_String:: count_offset_in_bytes();
2852
2853 // load str1 (jchar*) base address into tmp1_reg
2854 __ load_heap_oop(str1_reg, value_offset, tmp1_reg);
2855 __ ld(str1_reg, offset_offset, result_reg);
2856 __ add(tmp1_reg, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp1_reg);
2857 __ ld(str1_reg, count_offset, str1_reg); // hoisted
2858 __ sll(result_reg, exact_log2(sizeof(jchar)), result_reg);
2859 __ load_heap_oop(str2_reg, value_offset, tmp2_reg); // hoisted
2860 __ add(result_reg, tmp1_reg, tmp1_reg);
2861
2862 // load str2 (jchar*) base address into tmp2_reg
2863 // __ ld_ptr(str2_reg, value_offset, tmp2_reg); // hoisted
2864 __ ld(str2_reg, offset_offset, result_reg);
2865 __ add(tmp2_reg, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp2_reg);
2866 __ ld(str2_reg, count_offset, str2_reg); // hoisted
2867 __ sll(result_reg, exact_log2(sizeof(jchar)), result_reg);
2868 __ subcc(str1_reg, str2_reg, O7); // hoisted
2869 __ add(result_reg, tmp2_reg, tmp2_reg);
2870
2871 // Compute the minimum of the string lengths(str1_reg) and the
2872 // difference of the string lengths (stack)
2873
2874 // discard string base pointers, after loading up the lengths
2875 // __ ld(str1_reg, count_offset, str1_reg); // hoisted
2876 // __ ld(str2_reg, count_offset, str2_reg); // hoisted
2877
2878 // See if the lengths are different, and calculate min in str1_reg.
2879 // Stash diff in O7 in case we need it for a tie-breaker.
2880 Label Lskip;
2881 // __ subcc(str1_reg, str2_reg, O7); // hoisted
2882 __ sll(str1_reg, exact_log2(sizeof(jchar)), str1_reg); // scale the limit
2883 __ br(Assembler::greater, true, Assembler::pt, Lskip);
2884 // str2 is shorter, so use its count:
2885 __ delayed()->sll(str2_reg, exact_log2(sizeof(jchar)), str1_reg); // scale the limit
2886 __ bind(Lskip);
2887
2888 // reallocate str1_reg, str2_reg, result_reg
2889 // Note: limit_reg holds the string length pre-scaled by 2
2890 Register limit_reg = str1_reg;
2891 Register chr2_reg = str2_reg;
2892 Register chr1_reg = result_reg;
2893 // tmp{12} are the base pointers
2894
2895 // Is the minimum length zero?
2896 __ cmp(limit_reg, (int)(0 * sizeof(jchar))); // use cast to resolve overloading ambiguity
2897 __ br(Assembler::equal, true, Assembler::pn, Ldone);
2898 __ delayed()->mov(O7, result_reg); // result is difference in lengths
2899
2900 // Load first characters
2901 __ lduh(tmp1_reg, 0, chr1_reg);
2902 __ lduh(tmp2_reg, 0, chr2_reg);
2903
2904 // Compare first characters
2905 __ subcc(chr1_reg, chr2_reg, chr1_reg);
2906 __ br(Assembler::notZero, false, Assembler::pt, Ldone);
2907 assert(chr1_reg == result_reg, "result must be pre-placed");
2908 __ delayed()->nop();
2909
2910 {
2911 // Check after comparing first character to see if strings are equivalent
2912 Label LSkip2;
2913 // Check if the strings start at same location
2914 __ cmp(tmp1_reg, tmp2_reg);
2915 __ brx(Assembler::notEqual, true, Assembler::pt, LSkip2);
2916 __ delayed()->nop();
2917
2918 // Check if the length difference is zero (in O7)
2919 __ cmp(G0, O7);
2920 __ br(Assembler::equal, true, Assembler::pn, Ldone);
2921 __ delayed()->mov(G0, result_reg); // result is zero
2922
2923 // Strings might not be equal
2924 __ bind(LSkip2);
2925 }
2926
2927 __ subcc(limit_reg, 1 * sizeof(jchar), chr1_reg);
2928 __ br(Assembler::equal, true, Assembler::pn, Ldone);
2929 __ delayed()->mov(O7, result_reg); // result is difference in lengths
2930
2931 // Shift tmp1_reg and tmp2_reg to the end of the arrays, negate limit
2932 __ add(tmp1_reg, limit_reg, tmp1_reg);
2933 __ add(tmp2_reg, limit_reg, tmp2_reg);
2934 __ neg(chr1_reg, limit_reg); // limit = -(limit-2)
2935
2936 // Compare the rest of the characters
2937 __ lduh(tmp1_reg, limit_reg, chr1_reg);
2938 __ bind(Lloop);
2939 // __ lduh(tmp1_reg, limit_reg, chr1_reg); // hoisted
2940 __ lduh(tmp2_reg, limit_reg, chr2_reg);
2941 __ subcc(chr1_reg, chr2_reg, chr1_reg);
2942 __ br(Assembler::notZero, false, Assembler::pt, Ldone);
2943 assert(chr1_reg == result_reg, "result must be pre-placed");
2944 __ delayed()->inccc(limit_reg, sizeof(jchar));
2945 // annul LDUH if branch is not taken to prevent access past end of string
2946 __ br(Assembler::notZero, true, Assembler::pt, Lloop);
2947 __ delayed()->lduh(tmp1_reg, limit_reg, chr1_reg); // hoisted
2948
2949 // If strings are equal up to min length, return the length difference.
2950 __ mov(O7, result_reg);
2951
2952 // Otherwise, return the difference between the first mismatched chars.
2953 __ bind(Ldone);
2954 %}
2955
2956 enc_class enc_String_Equals(o0RegP str1, o1RegP str2, g3RegP tmp1, g4RegP tmp2, notemp_iRegI result) %{
2957 Label Lword, Lword_loop, Lpost_word, Lchar, Lchar_loop, Ldone;
2958 MacroAssembler _masm(&cbuf);
2959
2960 Register str1_reg = reg_to_register_object($str1$$reg);
2961 Register str2_reg = reg_to_register_object($str2$$reg);
2962 Register tmp1_reg = reg_to_register_object($tmp1$$reg);
2963 Register tmp2_reg = reg_to_register_object($tmp2$$reg);
2964 Register result_reg = reg_to_register_object($result$$reg);
2965
2966 // Get the first character position in both strings
2967 // [8] char array, [12] offset, [16] count
2968 int value_offset = java_lang_String:: value_offset_in_bytes();
2969 int offset_offset = java_lang_String::offset_offset_in_bytes();
2970 int count_offset = java_lang_String:: count_offset_in_bytes();
2971
2972 // load str1 (jchar*) base address into tmp1_reg
2973 __ load_heap_oop(Address(str1_reg, value_offset), tmp1_reg);
2974 __ ld(Address(str1_reg, offset_offset), result_reg);
2975 __ add(tmp1_reg, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp1_reg);
2976 __ ld(Address(str1_reg, count_offset), str1_reg); // hoisted
2977 __ sll(result_reg, exact_log2(sizeof(jchar)), result_reg);
2978 __ load_heap_oop(Address(str2_reg, value_offset), tmp2_reg); // hoisted
2979 __ add(result_reg, tmp1_reg, tmp1_reg);
2980
2981 // load str2 (jchar*) base address into tmp2_reg
2982 // __ ld_ptr(Address(str2_reg, value_offset), tmp2_reg); // hoisted
2983 __ ld(Address(str2_reg, offset_offset), result_reg);
2984 __ add(tmp2_reg, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp2_reg);
2985 __ ld(Address(str2_reg, count_offset), str2_reg); // hoisted
2986 __ sll(result_reg, exact_log2(sizeof(jchar)), result_reg);
2987 __ cmp(str1_reg, str2_reg); // hoisted
2988 __ add(result_reg, tmp2_reg, tmp2_reg);
2989
2990 __ sll(str1_reg, exact_log2(sizeof(jchar)), str1_reg);
2991 __ br(Assembler::notEqual, true, Assembler::pt, Ldone);
2992 __ delayed()->mov(G0, result_reg); // not equal
2993
2994 __ br_zero(Assembler::equal, true, Assembler::pn, str1_reg, Ldone);
2995 __ delayed()->add(G0, 1, result_reg); //equals
2996
2997 __ cmp(tmp1_reg, tmp2_reg); //same string ?
2998 __ brx(Assembler::equal, true, Assembler::pn, Ldone);
2999 __ delayed()->add(G0, 1, result_reg);
3000
3001 //rename registers
3002 Register limit_reg = str1_reg;
3003 Register chr2_reg = str2_reg;
3004 Register chr1_reg = result_reg;
3005 // tmp{12} are the base pointers
3006
3007 //check for alignment and position the pointers to the ends
3008 __ or3(tmp1_reg, tmp2_reg, chr1_reg);
3009 __ andcc(chr1_reg, 0x3, chr1_reg); // notZero means at least one not 4-byte aligned
3010 __ br(Assembler::notZero, false, Assembler::pn, Lchar);
3011 __ delayed()->nop();
3012
3013 __ bind(Lword);
3014 __ and3(limit_reg, 0x2, O7); //remember the remainder (either 0 or 2)
3015 __ andn(limit_reg, 0x3, limit_reg);
3016 __ br_zero(Assembler::zero, false, Assembler::pn, limit_reg, Lpost_word);
3017 __ delayed()->nop();
3018
3019 __ add(tmp1_reg, limit_reg, tmp1_reg);
3020 __ add(tmp2_reg, limit_reg, tmp2_reg);
3021 __ neg(limit_reg);
3022
3023 __ lduw(tmp1_reg, limit_reg, chr1_reg);
3024 __ bind(Lword_loop);
3025 __ lduw(tmp2_reg, limit_reg, chr2_reg);
3026 __ cmp(chr1_reg, chr2_reg);
3027 __ br(Assembler::notEqual, true, Assembler::pt, Ldone);
3028 __ delayed()->mov(G0, result_reg);
3029 __ inccc(limit_reg, 2*sizeof(jchar));
3030 // annul LDUW if branch i s not taken to prevent access past end of string
3031 __ br(Assembler::notZero, true, Assembler::pt, Lword_loop); //annul on taken
3032 __ delayed()->lduw(tmp1_reg, limit_reg, chr1_reg); // hoisted
3033
3034 __ bind(Lpost_word);
3035 __ br_zero(Assembler::zero, true, Assembler::pt, O7, Ldone);
3036 __ delayed()->add(G0, 1, result_reg);
3037
3038 __ lduh(tmp1_reg, 0, chr1_reg);
3039 __ lduh(tmp2_reg, 0, chr2_reg);
3040 __ cmp (chr1_reg, chr2_reg);
3041 __ br(Assembler::notEqual, true, Assembler::pt, Ldone);
3042 __ delayed()->mov(G0, result_reg);
3043 __ ba(false,Ldone);
3044 __ delayed()->add(G0, 1, result_reg);
3045
3046 __ bind(Lchar);
3047 __ add(tmp1_reg, limit_reg, tmp1_reg);
3048 __ add(tmp2_reg, limit_reg, tmp2_reg);
3049 __ neg(limit_reg); //negate count
3050
3051 __ lduh(tmp1_reg, limit_reg, chr1_reg);
3052 __ bind(Lchar_loop);
3053 __ lduh(tmp2_reg, limit_reg, chr2_reg);
3054 __ cmp(chr1_reg, chr2_reg);
3055 __ br(Assembler::notEqual, true, Assembler::pt, Ldone);
3056 __ delayed()->mov(G0, result_reg); //not equal
3057 __ inccc(limit_reg, sizeof(jchar));
3058 // annul LDUH if branch is not taken to prevent access past end of string
3059 __ br(Assembler::notZero, true, Assembler::pt, Lchar_loop); //annul on taken
3060 __ delayed()->lduh(tmp1_reg, limit_reg, chr1_reg); // hoisted
3061
3062 __ add(G0, 1, result_reg); //equal
3063
3064 __ bind(Ldone);
3065 %}
3066
3067 enc_class enc_Array_Equals(o0RegP ary1, o1RegP ary2, g3RegP tmp1, g4RegP tmp2, notemp_iRegI result) %{
3068 Label Lvector, Ldone, Lloop;
3069 MacroAssembler _masm(&cbuf);
3070
3071 Register ary1_reg = reg_to_register_object($ary1$$reg);
3072 Register ary2_reg = reg_to_register_object($ary2$$reg);
3073 Register tmp1_reg = reg_to_register_object($tmp1$$reg);
3074 Register tmp2_reg = reg_to_register_object($tmp2$$reg);
3075 Register result_reg = reg_to_register_object($result$$reg);
3076
3077 int length_offset = arrayOopDesc::length_offset_in_bytes();
3078 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR);
3079
3080 // return true if the same array
3081 __ cmp(ary1_reg, ary2_reg);
3082 __ br(Assembler::equal, true, Assembler::pn, Ldone);
3083 __ delayed()->add(G0, 1, result_reg); // equal
3084
3085 __ br_null(ary1_reg, true, Assembler::pn, Ldone);
3086 __ delayed()->mov(G0, result_reg); // not equal
3087
3088 __ br_null(ary2_reg, true, Assembler::pn, Ldone);
3089 __ delayed()->mov(G0, result_reg); // not equal
3090
3091 //load the lengths of arrays
3092 __ ld(Address(ary1_reg, length_offset), tmp1_reg);
3093 __ ld(Address(ary2_reg, length_offset), tmp2_reg);
3094
3095 // return false if the two arrays are not equal length
3096 __ cmp(tmp1_reg, tmp2_reg);
3097 __ br(Assembler::notEqual, true, Assembler::pn, Ldone);
3098 __ delayed()->mov(G0, result_reg); // not equal
3099
3100 __ br_zero(Assembler::zero, true, Assembler::pn, tmp1_reg, Ldone);
3101 __ delayed()->add(G0, 1, result_reg); // zero-length arrays are equal
3102
3103 // load array addresses
3104 __ add(ary1_reg, base_offset, ary1_reg);
3105 __ add(ary2_reg, base_offset, ary2_reg);
3106
3107 // renaming registers
3108 Register chr1_reg = tmp2_reg; // for characters in ary1
3109 Register chr2_reg = result_reg; // for characters in ary2
3110 Register limit_reg = tmp1_reg; // length
3111
3112 // set byte count
3113 __ sll(limit_reg, exact_log2(sizeof(jchar)), limit_reg);
3114 __ andcc(limit_reg, 0x2, chr1_reg); //trailing character ?
3115 __ br(Assembler::zero, false, Assembler::pt, Lvector);
3116 __ delayed()->nop();
3117
3118 //compare the trailing char
3119 __ sub(limit_reg, sizeof(jchar), limit_reg);
3120 __ lduh(ary1_reg, limit_reg, chr1_reg);
3121 __ lduh(ary2_reg, limit_reg, chr2_reg);
3122 __ cmp(chr1_reg, chr2_reg);
3123 __ br(Assembler::notEqual, true, Assembler::pt, Ldone);
3124 __ delayed()->mov(G0, result_reg); // not equal
3125
3126 // only one char ?
3127 __ br_zero(Assembler::zero, true, Assembler::pn, limit_reg, Ldone);
3128 __ delayed()->add(G0, 1, result_reg); // zero-length arrays are equal
3129
3130 __ bind(Lvector);
3131 // Shift ary1_reg and ary2_reg to the end of the arrays, negate limit
3132 __ add(ary1_reg, limit_reg, ary1_reg);
3133 __ add(ary2_reg, limit_reg, ary2_reg);
3134 __ neg(limit_reg, limit_reg);
3135
3136 __ lduw(ary1_reg, limit_reg, chr1_reg);
3137 __ bind(Lloop);
3138 __ lduw(ary2_reg, limit_reg, chr2_reg);
3139 __ cmp(chr1_reg, chr2_reg);
3140 __ br(Assembler::notEqual, false, Assembler::pt, Ldone);
3141 __ delayed()->mov(G0, result_reg); // not equal
3142 __ inccc(limit_reg, 2*sizeof(jchar));
3143 // annul LDUW if branch is not taken to prevent access past end of string
3144 __ br(Assembler::notZero, true, Assembler::pt, Lloop); //annul on taken
3145 __ delayed()->lduw(ary1_reg, limit_reg, chr1_reg); // hoisted
3146
3147 __ add(G0, 1, result_reg); // equals
3148
3149 __ bind(Ldone);
3150 %}
3151
3152 enc_class enc_rethrow() %{
3153 cbuf.set_inst_mark();
3154 Register temp_reg = G3;
3155 AddressLiteral rethrow_stub(OptoRuntime::rethrow_stub());
3156 assert(temp_reg != reg_to_register_object(R_I0_num), "temp must not break oop_reg");
3157 MacroAssembler _masm(&cbuf);
3158 #ifdef ASSERT
3159 __ save_frame(0);
3160 AddressLiteral last_rethrow_addrlit(&last_rethrow);
3161 __ sethi(last_rethrow_addrlit, L1);
3162 Address addr(L1, last_rethrow_addrlit.low10());
3163 __ get_pc(L2);
3164 __ inc(L2, 3 * BytesPerInstWord); // skip this & 2 more insns to point at jump_to
3165 __ st_ptr(L2, addr);
3166 __ restore();
3167 #endif
3168 __ JUMP(rethrow_stub, temp_reg, 0); // sethi;jmp
3169 __ delayed()->nop();
3170 %}
3171
3172 enc_class emit_mem_nop() %{
3173 // Generates the instruction LDUXA [o6,g0],#0x82,g0
3174 unsigned int *code = (unsigned int*)cbuf.code_end();
3175 *code = (unsigned int)0xc0839040;
3176 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
3177 %}
3178
3179 enc_class emit_fadd_nop() %{
3180 // Generates the instruction FMOVS f31,f31
3181 unsigned int *code = (unsigned int*)cbuf.code_end();
3182 *code = (unsigned int)0xbfa0003f;
3183 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
3184 %}
3185
3186 enc_class emit_br_nop() %{
3187 // Generates the instruction BPN,PN .
3188 unsigned int *code = (unsigned int*)cbuf.code_end();
3189 *code = (unsigned int)0x00400000;
3190 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
3191 %}
3192
3193 enc_class enc_membar_acquire %{
3194 MacroAssembler _masm(&cbuf);
3195 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::LoadLoad) );
3196 %}
3197
3198 enc_class enc_membar_release %{
3199 MacroAssembler _masm(&cbuf);
3200 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::StoreStore) );
3201 %}
3202
3203 enc_class enc_membar_volatile %{
3204 MacroAssembler _masm(&cbuf);
3205 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad) );
3206 %}
3207
3208 enc_class enc_repl8b( iRegI src, iRegL dst ) %{
3209 MacroAssembler _masm(&cbuf);
3210 Register src_reg = reg_to_register_object($src$$reg);
3211 Register dst_reg = reg_to_register_object($dst$$reg);
3212 __ sllx(src_reg, 56, dst_reg);
3213 __ srlx(dst_reg, 8, O7);
3214 __ or3 (dst_reg, O7, dst_reg);
3215 __ srlx(dst_reg, 16, O7);
3216 __ or3 (dst_reg, O7, dst_reg);
3217 __ srlx(dst_reg, 32, O7);
3218 __ or3 (dst_reg, O7, dst_reg);
3219 %}
3220
3221 enc_class enc_repl4b( iRegI src, iRegL dst ) %{
3222 MacroAssembler _masm(&cbuf);
3223 Register src_reg = reg_to_register_object($src$$reg);
3224 Register dst_reg = reg_to_register_object($dst$$reg);
3225 __ sll(src_reg, 24, dst_reg);
3226 __ srl(dst_reg, 8, O7);
3227 __ or3(dst_reg, O7, dst_reg);
3228 __ srl(dst_reg, 16, O7);
3229 __ or3(dst_reg, O7, dst_reg);
3230 %}
3231
3232 enc_class enc_repl4s( iRegI src, iRegL dst ) %{
3233 MacroAssembler _masm(&cbuf);
3234 Register src_reg = reg_to_register_object($src$$reg);
3235 Register dst_reg = reg_to_register_object($dst$$reg);
3236 __ sllx(src_reg, 48, dst_reg);
3237 __ srlx(dst_reg, 16, O7);
3238 __ or3 (dst_reg, O7, dst_reg);
3239 __ srlx(dst_reg, 32, O7);
3240 __ or3 (dst_reg, O7, dst_reg);
3241 %}
3242
3243 enc_class enc_repl2i( iRegI src, iRegL dst ) %{
3244 MacroAssembler _masm(&cbuf);
3245 Register src_reg = reg_to_register_object($src$$reg);
3246 Register dst_reg = reg_to_register_object($dst$$reg);
3247 __ sllx(src_reg, 32, dst_reg);
3248 __ srlx(dst_reg, 32, O7);
3249 __ or3 (dst_reg, O7, dst_reg);
3250 %}
3251
3252 %}
3253
3254 //----------FRAME--------------------------------------------------------------
3255 // Definition of frame structure and management information.
3256 //
3257 // S T A C K L A Y O U T Allocators stack-slot number
3258 // | (to get allocators register number
3259 // G Owned by | | v add VMRegImpl::stack0)
3260 // r CALLER | |
3261 // o | +--------+ pad to even-align allocators stack-slot
3262 // w V | pad0 | numbers; owned by CALLER
3263 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
3264 // h ^ | in | 5
3265 // | | args | 4 Holes in incoming args owned by SELF
3266 // | | | | 3
3267 // | | +--------+
3268 // V | | old out| Empty on Intel, window on Sparc
3269 // | old |preserve| Must be even aligned.
3270 // | SP-+--------+----> Matcher::_old_SP, 8 (or 16 in LP64)-byte aligned
3271 // | | in | 3 area for Intel ret address
3272 // Owned by |preserve| Empty on Sparc.
3273 // SELF +--------+
3274 // | | pad2 | 2 pad to align old SP
3275 // | +--------+ 1
3276 // | | locks | 0
3277 // | +--------+----> VMRegImpl::stack0, 8 (or 16 in LP64)-byte aligned
3278 // | | pad1 | 11 pad to align new SP
3279 // | +--------+
3280 // | | | 10
3281 // | | spills | 9 spills
3282 // V | | 8 (pad0 slot for callee)
3283 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
3284 // ^ | out | 7
3285 // | | args | 6 Holes in outgoing args owned by CALLEE
3286 // Owned by +--------+
3287 // CALLEE | new out| 6 Empty on Intel, window on Sparc
3288 // | new |preserve| Must be even-aligned.
3289 // | SP-+--------+----> Matcher::_new_SP, even aligned
3290 // | | |
3291 //
3292 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
3293 // known from SELF's arguments and the Java calling convention.
3294 // Region 6-7 is determined per call site.
3295 // Note 2: If the calling convention leaves holes in the incoming argument
3296 // area, those holes are owned by SELF. Holes in the outgoing area
3297 // are owned by the CALLEE. Holes should not be nessecary in the
3298 // incoming area, as the Java calling convention is completely under
3299 // the control of the AD file. Doubles can be sorted and packed to
3300 // avoid holes. Holes in the outgoing arguments may be nessecary for
3301 // varargs C calling conventions.
3302 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
3303 // even aligned with pad0 as needed.
3304 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
3305 // region 6-11 is even aligned; it may be padded out more so that
3306 // the region from SP to FP meets the minimum stack alignment.
3307
3308 frame %{
3309 // What direction does stack grow in (assumed to be same for native & Java)
3310 stack_direction(TOWARDS_LOW);
3311
3312 // These two registers define part of the calling convention
3313 // between compiled code and the interpreter.
3314 inline_cache_reg(R_G5); // Inline Cache Register or methodOop for I2C
3315 interpreter_method_oop_reg(R_G5); // Method Oop Register when calling interpreter
3316
3317 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
3318 cisc_spilling_operand_name(indOffset);
3319
3320 // Number of stack slots consumed by a Monitor enter
3321 #ifdef _LP64
3322 sync_stack_slots(2);
3323 #else
3324 sync_stack_slots(1);
3325 #endif
3326
3327 // Compiled code's Frame Pointer
3328 frame_pointer(R_SP);
3329
3330 // Stack alignment requirement
3331 stack_alignment(StackAlignmentInBytes);
3332 // LP64: Alignment size in bytes (128-bit -> 16 bytes)
3333 // !LP64: Alignment size in bytes (64-bit -> 8 bytes)
3334
3335 // Number of stack slots between incoming argument block and the start of
3336 // a new frame. The PROLOG must add this many slots to the stack. The
3337 // EPILOG must remove this many slots.
3338 in_preserve_stack_slots(0);
3339
3340 // Number of outgoing stack slots killed above the out_preserve_stack_slots
3341 // for calls to C. Supports the var-args backing area for register parms.
3342 // ADLC doesn't support parsing expressions, so I folded the math by hand.
3343 #ifdef _LP64
3344 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (0)) * 2-stack-slots-per-word
3345 varargs_C_out_slots_killed(12);
3346 #else
3347 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (1)) * 1-stack-slots-per-word
3348 varargs_C_out_slots_killed( 7);
3349 #endif
3350
3351 // The after-PROLOG location of the return address. Location of
3352 // return address specifies a type (REG or STACK) and a number
3353 // representing the register number (i.e. - use a register name) or
3354 // stack slot.
3355 return_addr(REG R_I7); // Ret Addr is in register I7
3356
3357 // Body of function which returns an OptoRegs array locating
3358 // arguments either in registers or in stack slots for calling
3359 // java
3360 calling_convention %{
3361 (void) SharedRuntime::java_calling_convention(sig_bt, regs, length, is_outgoing);
3362
3363 %}
3364
3365 // Body of function which returns an OptoRegs array locating
3366 // arguments either in registers or in stack slots for callin
3367 // C.
3368 c_calling_convention %{
3369 // This is obviously always outgoing
3370 (void) SharedRuntime::c_calling_convention(sig_bt, regs, length);
3371 %}
3372
3373 // Location of native (C/C++) and interpreter return values. This is specified to
3374 // be the same as Java. In the 32-bit VM, long values are actually returned from
3375 // native calls in O0:O1 and returned to the interpreter in I0:I1. The copying
3376 // to and from the register pairs is done by the appropriate call and epilog
3377 // opcodes. This simplifies the register allocator.
3378 c_return_value %{
3379 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3380 #ifdef _LP64
3381 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num };
3382 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num};
3383 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num };
3384 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num};
3385 #else // !_LP64
3386 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num };
3387 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num };
3388 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num };
3389 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num };
3390 #endif
3391 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg],
3392 (is_outgoing?lo_out:lo_in)[ideal_reg] );
3393 %}
3394
3395 // Location of compiled Java return values. Same as C
3396 return_value %{
3397 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3398 #ifdef _LP64
3399 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num };
3400 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num};
3401 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num };
3402 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num};
3403 #else // !_LP64
3404 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num };
3405 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num};
3406 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num };
3407 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num};
3408 #endif
3409 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg],
3410 (is_outgoing?lo_out:lo_in)[ideal_reg] );
3411 %}
3412
3413 %}
3414
3415
3416 //----------ATTRIBUTES---------------------------------------------------------
3417 //----------Operand Attributes-------------------------------------------------
3418 op_attrib op_cost(1); // Required cost attribute
3419
3420 //----------Instruction Attributes---------------------------------------------
3421 ins_attrib ins_cost(DEFAULT_COST); // Required cost attribute
3422 ins_attrib ins_size(32); // Required size attribute (in bits)
3423 ins_attrib ins_pc_relative(0); // Required PC Relative flag
3424 ins_attrib ins_short_branch(0); // Required flag: is this instruction a
3425 // non-matching short branch variant of some
3426 // long branch?
3427
3428 //----------OPERANDS-----------------------------------------------------------
3429 // Operand definitions must precede instruction definitions for correct parsing
3430 // in the ADLC because operands constitute user defined types which are used in
3431 // instruction definitions.
3432
3433 //----------Simple Operands----------------------------------------------------
3434 // Immediate Operands
3435 // Integer Immediate: 32-bit
3436 operand immI() %{
3437 match(ConI);
3438
3439 op_cost(0);
3440 // formats are generated automatically for constants and base registers
3441 format %{ %}
3442 interface(CONST_INTER);
3443 %}
3444
3445 // Integer Immediate: 13-bit
3446 operand immI13() %{
3447 predicate(Assembler::is_simm13(n->get_int()));
3448 match(ConI);
3449 op_cost(0);
3450
3451 format %{ %}
3452 interface(CONST_INTER);
3453 %}
3454
3455 // Unsigned (positive) Integer Immediate: 13-bit
3456 operand immU13() %{
3457 predicate((0 <= n->get_int()) && Assembler::is_simm13(n->get_int()));
3458 match(ConI);
3459 op_cost(0);
3460
3461 format %{ %}
3462 interface(CONST_INTER);
3463 %}
3464
3465 // Integer Immediate: 6-bit
3466 operand immU6() %{
3467 predicate(n->get_int() >= 0 && n->get_int() <= 63);
3468 match(ConI);
3469 op_cost(0);
3470 format %{ %}
3471 interface(CONST_INTER);
3472 %}
3473
3474 // Integer Immediate: 11-bit
3475 operand immI11() %{
3476 predicate(Assembler::is_simm(n->get_int(),11));
3477 match(ConI);
3478 op_cost(0);
3479 format %{ %}
3480 interface(CONST_INTER);
3481 %}
3482
3483 // Integer Immediate: 0-bit
3484 operand immI0() %{
3485 predicate(n->get_int() == 0);
3486 match(ConI);
3487 op_cost(0);
3488
3489 format %{ %}
3490 interface(CONST_INTER);
3491 %}
3492
3493 // Integer Immediate: the value 10
3494 operand immI10() %{
3495 predicate(n->get_int() == 10);
3496 match(ConI);
3497 op_cost(0);
3498
3499 format %{ %}
3500 interface(CONST_INTER);
3501 %}
3502
3503 // Integer Immediate: the values 0-31
3504 operand immU5() %{
3505 predicate(n->get_int() >= 0 && n->get_int() <= 31);
3506 match(ConI);
3507 op_cost(0);
3508
3509 format %{ %}
3510 interface(CONST_INTER);
3511 %}
3512
3513 // Integer Immediate: the values 1-31
3514 operand immI_1_31() %{
3515 predicate(n->get_int() >= 1 && n->get_int() <= 31);
3516 match(ConI);
3517 op_cost(0);
3518
3519 format %{ %}
3520 interface(CONST_INTER);
3521 %}
3522
3523 // Integer Immediate: the values 32-63
3524 operand immI_32_63() %{
3525 predicate(n->get_int() >= 32 && n->get_int() <= 63);
3526 match(ConI);
3527 op_cost(0);
3528
3529 format %{ %}
3530 interface(CONST_INTER);
3531 %}
3532
3533 // Integer Immediate: the value 255
3534 operand immI_255() %{
3535 predicate( n->get_int() == 255 );
3536 match(ConI);
3537 op_cost(0);
3538
3539 format %{ %}
3540 interface(CONST_INTER);
3541 %}
3542
3543 // Long Immediate: the value FF
3544 operand immL_FF() %{
3545 predicate( n->get_long() == 0xFFL );
3546 match(ConL);
3547 op_cost(0);
3548
3549 format %{ %}
3550 interface(CONST_INTER);
3551 %}
3552
3553 // Long Immediate: the value FFFF
3554 operand immL_FFFF() %{
3555 predicate( n->get_long() == 0xFFFFL );
3556 match(ConL);
3557 op_cost(0);
3558
3559 format %{ %}
3560 interface(CONST_INTER);
3561 %}
3562
3563 // Pointer Immediate: 32 or 64-bit
3564 operand immP() %{
3565 match(ConP);
3566
3567 op_cost(5);
3568 // formats are generated automatically for constants and base registers
3569 format %{ %}
3570 interface(CONST_INTER);
3571 %}
3572
3573 operand immP13() %{
3574 predicate((-4096 < n->get_ptr()) && (n->get_ptr() <= 4095));
3575 match(ConP);
3576 op_cost(0);
3577
3578 format %{ %}
3579 interface(CONST_INTER);
3580 %}
3581
3582 operand immP0() %{
3583 predicate(n->get_ptr() == 0);
3584 match(ConP);
3585 op_cost(0);
3586
3587 format %{ %}
3588 interface(CONST_INTER);
3589 %}
3590
3591 operand immP_poll() %{
3592 predicate(n->get_ptr() != 0 && n->get_ptr() == (intptr_t)os::get_polling_page());
3593 match(ConP);
3594
3595 // formats are generated automatically for constants and base registers
3596 format %{ %}
3597 interface(CONST_INTER);
3598 %}
3599
3600 // Pointer Immediate
3601 operand immN()
3602 %{
3603 match(ConN);
3604
3605 op_cost(10);
3606 format %{ %}
3607 interface(CONST_INTER);
3608 %}
3609
3610 // NULL Pointer Immediate
3611 operand immN0()
3612 %{
3613 predicate(n->get_narrowcon() == 0);
3614 match(ConN);
3615
3616 op_cost(0);
3617 format %{ %}
3618 interface(CONST_INTER);
3619 %}
3620
3621 operand immL() %{
3622 match(ConL);
3623 op_cost(40);
3624 // formats are generated automatically for constants and base registers
3625 format %{ %}
3626 interface(CONST_INTER);
3627 %}
3628
3629 operand immL0() %{
3630 predicate(n->get_long() == 0L);
3631 match(ConL);
3632 op_cost(0);
3633 // formats are generated automatically for constants and base registers
3634 format %{ %}
3635 interface(CONST_INTER);
3636 %}
3637
3638 // Long Immediate: 13-bit
3639 operand immL13() %{
3640 predicate((-4096L < n->get_long()) && (n->get_long() <= 4095L));
3641 match(ConL);
3642 op_cost(0);
3643
3644 format %{ %}
3645 interface(CONST_INTER);
3646 %}
3647
3648 // Long Immediate: low 32-bit mask
3649 operand immL_32bits() %{
3650 predicate(n->get_long() == 0xFFFFFFFFL);
3651 match(ConL);
3652 op_cost(0);
3653
3654 format %{ %}
3655 interface(CONST_INTER);
3656 %}
3657
3658 // Double Immediate
3659 operand immD() %{
3660 match(ConD);
3661
3662 op_cost(40);
3663 format %{ %}
3664 interface(CONST_INTER);
3665 %}
3666
3667 operand immD0() %{
3668 #ifdef _LP64
3669 // on 64-bit architectures this comparision is faster
3670 predicate(jlong_cast(n->getd()) == 0);
3671 #else
3672 predicate((n->getd() == 0) && (fpclass(n->getd()) == FP_PZERO));
3673 #endif
3674 match(ConD);
3675
3676 op_cost(0);
3677 format %{ %}
3678 interface(CONST_INTER);
3679 %}
3680
3681 // Float Immediate
3682 operand immF() %{
3683 match(ConF);
3684
3685 op_cost(20);
3686 format %{ %}
3687 interface(CONST_INTER);
3688 %}
3689
3690 // Float Immediate: 0
3691 operand immF0() %{
3692 predicate((n->getf() == 0) && (fpclass(n->getf()) == FP_PZERO));
3693 match(ConF);
3694
3695 op_cost(0);
3696 format %{ %}
3697 interface(CONST_INTER);
3698 %}
3699
3700 // Integer Register Operands
3701 // Integer Register
3702 operand iRegI() %{
3703 constraint(ALLOC_IN_RC(int_reg));
3704 match(RegI);
3705
3706 match(notemp_iRegI);
3707 match(g1RegI);
3708 match(o0RegI);
3709 match(iRegIsafe);
3710
3711 format %{ %}
3712 interface(REG_INTER);
3713 %}
3714
3715 operand notemp_iRegI() %{
3716 constraint(ALLOC_IN_RC(notemp_int_reg));
3717 match(RegI);
3718
3719 match(o0RegI);
3720
3721 format %{ %}
3722 interface(REG_INTER);
3723 %}
3724
3725 operand o0RegI() %{
3726 constraint(ALLOC_IN_RC(o0_regI));
3727 match(iRegI);
3728
3729 format %{ %}
3730 interface(REG_INTER);
3731 %}
3732
3733 // Pointer Register
3734 operand iRegP() %{
3735 constraint(ALLOC_IN_RC(ptr_reg));
3736 match(RegP);
3737
3738 match(lock_ptr_RegP);
3739 match(g1RegP);
3740 match(g2RegP);
3741 match(g3RegP);
3742 match(g4RegP);
3743 match(i0RegP);
3744 match(o0RegP);
3745 match(o1RegP);
3746 match(l7RegP);
3747
3748 format %{ %}
3749 interface(REG_INTER);
3750 %}
3751
3752 operand sp_ptr_RegP() %{
3753 constraint(ALLOC_IN_RC(sp_ptr_reg));
3754 match(RegP);
3755 match(iRegP);
3756
3757 format %{ %}
3758 interface(REG_INTER);
3759 %}
3760
3761 operand lock_ptr_RegP() %{
3762 constraint(ALLOC_IN_RC(lock_ptr_reg));
3763 match(RegP);
3764 match(i0RegP);
3765 match(o0RegP);
3766 match(o1RegP);
3767 match(l7RegP);
3768
3769 format %{ %}
3770 interface(REG_INTER);
3771 %}
3772
3773 operand g1RegP() %{
3774 constraint(ALLOC_IN_RC(g1_regP));
3775 match(iRegP);
3776
3777 format %{ %}
3778 interface(REG_INTER);
3779 %}
3780
3781 operand g2RegP() %{
3782 constraint(ALLOC_IN_RC(g2_regP));
3783 match(iRegP);
3784
3785 format %{ %}
3786 interface(REG_INTER);
3787 %}
3788
3789 operand g3RegP() %{
3790 constraint(ALLOC_IN_RC(g3_regP));
3791 match(iRegP);
3792
3793 format %{ %}
3794 interface(REG_INTER);
3795 %}
3796
3797 operand g1RegI() %{
3798 constraint(ALLOC_IN_RC(g1_regI));
3799 match(iRegI);
3800
3801 format %{ %}
3802 interface(REG_INTER);
3803 %}
3804
3805 operand g3RegI() %{
3806 constraint(ALLOC_IN_RC(g3_regI));
3807 match(iRegI);
3808
3809 format %{ %}
3810 interface(REG_INTER);
3811 %}
3812
3813 operand g4RegI() %{
3814 constraint(ALLOC_IN_RC(g4_regI));
3815 match(iRegI);
3816
3817 format %{ %}
3818 interface(REG_INTER);
3819 %}
3820
3821 operand g4RegP() %{
3822 constraint(ALLOC_IN_RC(g4_regP));
3823 match(iRegP);
3824
3825 format %{ %}
3826 interface(REG_INTER);
3827 %}
3828
3829 operand i0RegP() %{
3830 constraint(ALLOC_IN_RC(i0_regP));
3831 match(iRegP);
3832
3833 format %{ %}
3834 interface(REG_INTER);
3835 %}
3836
3837 operand o0RegP() %{
3838 constraint(ALLOC_IN_RC(o0_regP));
3839 match(iRegP);
3840
3841 format %{ %}
3842 interface(REG_INTER);
3843 %}
3844
3845 operand o1RegP() %{
3846 constraint(ALLOC_IN_RC(o1_regP));
3847 match(iRegP);
3848
3849 format %{ %}
3850 interface(REG_INTER);
3851 %}
3852
3853 operand o2RegP() %{
3854 constraint(ALLOC_IN_RC(o2_regP));
3855 match(iRegP);
3856
3857 format %{ %}
3858 interface(REG_INTER);
3859 %}
3860
3861 operand o7RegP() %{
3862 constraint(ALLOC_IN_RC(o7_regP));
3863 match(iRegP);
3864
3865 format %{ %}
3866 interface(REG_INTER);
3867 %}
3868
3869 operand l7RegP() %{
3870 constraint(ALLOC_IN_RC(l7_regP));
3871 match(iRegP);
3872
3873 format %{ %}
3874 interface(REG_INTER);
3875 %}
3876
3877 operand o7RegI() %{
3878 constraint(ALLOC_IN_RC(o7_regI));
3879 match(iRegI);
3880
3881 format %{ %}
3882 interface(REG_INTER);
3883 %}
3884
3885 operand iRegN() %{
3886 constraint(ALLOC_IN_RC(int_reg));
3887 match(RegN);
3888
3889 format %{ %}
3890 interface(REG_INTER);
3891 %}
3892
3893 // Long Register
3894 operand iRegL() %{
3895 constraint(ALLOC_IN_RC(long_reg));
3896 match(RegL);
3897
3898 format %{ %}
3899 interface(REG_INTER);
3900 %}
3901
3902 operand o2RegL() %{
3903 constraint(ALLOC_IN_RC(o2_regL));
3904 match(iRegL);
3905
3906 format %{ %}
3907 interface(REG_INTER);
3908 %}
3909
3910 operand o7RegL() %{
3911 constraint(ALLOC_IN_RC(o7_regL));
3912 match(iRegL);
3913
3914 format %{ %}
3915 interface(REG_INTER);
3916 %}
3917
3918 operand g1RegL() %{
3919 constraint(ALLOC_IN_RC(g1_regL));
3920 match(iRegL);
3921
3922 format %{ %}
3923 interface(REG_INTER);
3924 %}
3925
3926 operand g3RegL() %{
3927 constraint(ALLOC_IN_RC(g3_regL));
3928 match(iRegL);
3929
3930 format %{ %}
3931 interface(REG_INTER);
3932 %}
3933
3934 // Int Register safe
3935 // This is 64bit safe
3936 operand iRegIsafe() %{
3937 constraint(ALLOC_IN_RC(long_reg));
3938
3939 match(iRegI);
3940
3941 format %{ %}
3942 interface(REG_INTER);
3943 %}
3944
3945 // Condition Code Flag Register
3946 operand flagsReg() %{
3947 constraint(ALLOC_IN_RC(int_flags));
3948 match(RegFlags);
3949
3950 format %{ "ccr" %} // both ICC and XCC
3951 interface(REG_INTER);
3952 %}
3953
3954 // Condition Code Register, unsigned comparisons.
3955 operand flagsRegU() %{
3956 constraint(ALLOC_IN_RC(int_flags));
3957 match(RegFlags);
3958
3959 format %{ "icc_U" %}
3960 interface(REG_INTER);
3961 %}
3962
3963 // Condition Code Register, pointer comparisons.
3964 operand flagsRegP() %{
3965 constraint(ALLOC_IN_RC(int_flags));
3966 match(RegFlags);
3967
3968 #ifdef _LP64
3969 format %{ "xcc_P" %}
3970 #else
3971 format %{ "icc_P" %}
3972 #endif
3973 interface(REG_INTER);
3974 %}
3975
3976 // Condition Code Register, long comparisons.
3977 operand flagsRegL() %{
3978 constraint(ALLOC_IN_RC(int_flags));
3979 match(RegFlags);
3980
3981 format %{ "xcc_L" %}
3982 interface(REG_INTER);
3983 %}
3984
3985 // Condition Code Register, floating comparisons, unordered same as "less".
3986 operand flagsRegF() %{
3987 constraint(ALLOC_IN_RC(float_flags));
3988 match(RegFlags);
3989 match(flagsRegF0);
3990
3991 format %{ %}
3992 interface(REG_INTER);
3993 %}
3994
3995 operand flagsRegF0() %{
3996 constraint(ALLOC_IN_RC(float_flag0));
3997 match(RegFlags);
3998
3999 format %{ %}
4000 interface(REG_INTER);
4001 %}
4002
4003
4004 // Condition Code Flag Register used by long compare
4005 operand flagsReg_long_LTGE() %{
4006 constraint(ALLOC_IN_RC(int_flags));
4007 match(RegFlags);
4008 format %{ "icc_LTGE" %}
4009 interface(REG_INTER);
4010 %}
4011 operand flagsReg_long_EQNE() %{
4012 constraint(ALLOC_IN_RC(int_flags));
4013 match(RegFlags);
4014 format %{ "icc_EQNE" %}
4015 interface(REG_INTER);
4016 %}
4017 operand flagsReg_long_LEGT() %{
4018 constraint(ALLOC_IN_RC(int_flags));
4019 match(RegFlags);
4020 format %{ "icc_LEGT" %}
4021 interface(REG_INTER);
4022 %}
4023
4024
4025 operand regD() %{
4026 constraint(ALLOC_IN_RC(dflt_reg));
4027 match(RegD);
4028
4029 match(regD_low);
4030
4031 format %{ %}
4032 interface(REG_INTER);
4033 %}
4034
4035 operand regF() %{
4036 constraint(ALLOC_IN_RC(sflt_reg));
4037 match(RegF);
4038
4039 format %{ %}
4040 interface(REG_INTER);
4041 %}
4042
4043 operand regD_low() %{
4044 constraint(ALLOC_IN_RC(dflt_low_reg));
4045 match(regD);
4046
4047 format %{ %}
4048 interface(REG_INTER);
4049 %}
4050
4051 // Special Registers
4052
4053 // Method Register
4054 operand inline_cache_regP(iRegP reg) %{
4055 constraint(ALLOC_IN_RC(g5_regP)); // G5=inline_cache_reg but uses 2 bits instead of 1
4056 match(reg);
4057 format %{ %}
4058 interface(REG_INTER);
4059 %}
4060
4061 operand interpreter_method_oop_regP(iRegP reg) %{
4062 constraint(ALLOC_IN_RC(g5_regP)); // G5=interpreter_method_oop_reg but uses 2 bits instead of 1
4063 match(reg);
4064 format %{ %}
4065 interface(REG_INTER);
4066 %}
4067
4068
4069 //----------Complex Operands---------------------------------------------------
4070 // Indirect Memory Reference
4071 operand indirect(sp_ptr_RegP reg) %{
4072 constraint(ALLOC_IN_RC(sp_ptr_reg));
4073 match(reg);
4074
4075 op_cost(100);
4076 format %{ "[$reg]" %}
4077 interface(MEMORY_INTER) %{
4078 base($reg);
4079 index(0x0);
4080 scale(0x0);
4081 disp(0x0);
4082 %}
4083 %}
4084
4085 // Indirect with Offset
4086 operand indOffset13(sp_ptr_RegP reg, immX13 offset) %{
4087 constraint(ALLOC_IN_RC(sp_ptr_reg));
4088 match(AddP reg offset);
4089
4090 op_cost(100);
4091 format %{ "[$reg + $offset]" %}
4092 interface(MEMORY_INTER) %{
4093 base($reg);
4094 index(0x0);
4095 scale(0x0);
4096 disp($offset);
4097 %}
4098 %}
4099
4100 // Note: Intel has a swapped version also, like this:
4101 //operand indOffsetX(iRegI reg, immP offset) %{
4102 // constraint(ALLOC_IN_RC(int_reg));
4103 // match(AddP offset reg);
4104 //
4105 // op_cost(100);
4106 // format %{ "[$reg + $offset]" %}
4107 // interface(MEMORY_INTER) %{
4108 // base($reg);
4109 // index(0x0);
4110 // scale(0x0);
4111 // disp($offset);
4112 // %}
4113 //%}
4114 //// However, it doesn't make sense for SPARC, since
4115 // we have no particularly good way to embed oops in
4116 // single instructions.
4117
4118 // Indirect with Register Index
4119 operand indIndex(iRegP addr, iRegX index) %{
4120 constraint(ALLOC_IN_RC(ptr_reg));
4121 match(AddP addr index);
4122
4123 op_cost(100);
4124 format %{ "[$addr + $index]" %}
4125 interface(MEMORY_INTER) %{
4126 base($addr);
4127 index($index);
4128 scale(0x0);
4129 disp(0x0);
4130 %}
4131 %}
4132
4133 //----------Special Memory Operands--------------------------------------------
4134 // Stack Slot Operand - This operand is used for loading and storing temporary
4135 // values on the stack where a match requires a value to
4136 // flow through memory.
4137 operand stackSlotI(sRegI reg) %{
4138 constraint(ALLOC_IN_RC(stack_slots));
4139 op_cost(100);
4140 //match(RegI);
4141 format %{ "[$reg]" %}
4142 interface(MEMORY_INTER) %{
4143 base(0xE); // R_SP
4144 index(0x0);
4145 scale(0x0);
4146 disp($reg); // Stack Offset
4147 %}
4148 %}
4149
4150 operand stackSlotP(sRegP reg) %{
4151 constraint(ALLOC_IN_RC(stack_slots));
4152 op_cost(100);
4153 //match(RegP);
4154 format %{ "[$reg]" %}
4155 interface(MEMORY_INTER) %{
4156 base(0xE); // R_SP
4157 index(0x0);
4158 scale(0x0);
4159 disp($reg); // Stack Offset
4160 %}
4161 %}
4162
4163 operand stackSlotF(sRegF reg) %{
4164 constraint(ALLOC_IN_RC(stack_slots));
4165 op_cost(100);
4166 //match(RegF);
4167 format %{ "[$reg]" %}
4168 interface(MEMORY_INTER) %{
4169 base(0xE); // R_SP
4170 index(0x0);
4171 scale(0x0);
4172 disp($reg); // Stack Offset
4173 %}
4174 %}
4175 operand stackSlotD(sRegD reg) %{
4176 constraint(ALLOC_IN_RC(stack_slots));
4177 op_cost(100);
4178 //match(RegD);
4179 format %{ "[$reg]" %}
4180 interface(MEMORY_INTER) %{
4181 base(0xE); // R_SP
4182 index(0x0);
4183 scale(0x0);
4184 disp($reg); // Stack Offset
4185 %}
4186 %}
4187 operand stackSlotL(sRegL reg) %{
4188 constraint(ALLOC_IN_RC(stack_slots));
4189 op_cost(100);
4190 //match(RegL);
4191 format %{ "[$reg]" %}
4192 interface(MEMORY_INTER) %{
4193 base(0xE); // R_SP
4194 index(0x0);
4195 scale(0x0);
4196 disp($reg); // Stack Offset
4197 %}
4198 %}
4199
4200 // Operands for expressing Control Flow
4201 // NOTE: Label is a predefined operand which should not be redefined in
4202 // the AD file. It is generically handled within the ADLC.
4203
4204 //----------Conditional Branch Operands----------------------------------------
4205 // Comparison Op - This is the operation of the comparison, and is limited to
4206 // the following set of codes:
4207 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
4208 //
4209 // Other attributes of the comparison, such as unsignedness, are specified
4210 // by the comparison instruction that sets a condition code flags register.
4211 // That result is represented by a flags operand whose subtype is appropriate
4212 // to the unsignedness (etc.) of the comparison.
4213 //
4214 // Later, the instruction which matches both the Comparison Op (a Bool) and
4215 // the flags (produced by the Cmp) specifies the coding of the comparison op
4216 // by matching a specific subtype of Bool operand below, such as cmpOpU.
4217
4218 operand cmpOp() %{
4219 match(Bool);
4220
4221 format %{ "" %}
4222 interface(COND_INTER) %{
4223 equal(0x1);
4224 not_equal(0x9);
4225 less(0x3);
4226 greater_equal(0xB);
4227 less_equal(0x2);
4228 greater(0xA);
4229 %}
4230 %}
4231
4232 // Comparison Op, unsigned
4233 operand cmpOpU() %{
4234 match(Bool);
4235
4236 format %{ "u" %}
4237 interface(COND_INTER) %{
4238 equal(0x1);
4239 not_equal(0x9);
4240 less(0x5);
4241 greater_equal(0xD);
4242 less_equal(0x4);
4243 greater(0xC);
4244 %}
4245 %}
4246
4247 // Comparison Op, pointer (same as unsigned)
4248 operand cmpOpP() %{
4249 match(Bool);
4250
4251 format %{ "p" %}
4252 interface(COND_INTER) %{
4253 equal(0x1);
4254 not_equal(0x9);
4255 less(0x5);
4256 greater_equal(0xD);
4257 less_equal(0x4);
4258 greater(0xC);
4259 %}
4260 %}
4261
4262 // Comparison Op, branch-register encoding
4263 operand cmpOp_reg() %{
4264 match(Bool);
4265
4266 format %{ "" %}
4267 interface(COND_INTER) %{
4268 equal (0x1);
4269 not_equal (0x5);
4270 less (0x3);
4271 greater_equal(0x7);
4272 less_equal (0x2);
4273 greater (0x6);
4274 %}
4275 %}
4276
4277 // Comparison Code, floating, unordered same as less
4278 operand cmpOpF() %{
4279 match(Bool);
4280
4281 format %{ "fl" %}
4282 interface(COND_INTER) %{
4283 equal(0x9);
4284 not_equal(0x1);
4285 less(0x3);
4286 greater_equal(0xB);
4287 less_equal(0xE);
4288 greater(0x6);
4289 %}
4290 %}
4291
4292 // Used by long compare
4293 operand cmpOp_commute() %{
4294 match(Bool);
4295
4296 format %{ "" %}
4297 interface(COND_INTER) %{
4298 equal(0x1);
4299 not_equal(0x9);
4300 less(0xA);
4301 greater_equal(0x2);
4302 less_equal(0xB);
4303 greater(0x3);
4304 %}
4305 %}
4306
4307 //----------OPERAND CLASSES----------------------------------------------------
4308 // Operand Classes are groups of operands that are used to simplify
4309 // instruction definitions by not requiring the AD writer to specify separate
4310 // instructions for every form of operand when the instruction accepts
4311 // multiple operand types with the same basic encoding and format. The classic
4312 // case of this is memory operands.
4313 // Indirect is not included since its use is limited to Compare & Swap
4314 opclass memory( indirect, indOffset13, indIndex );
4315
4316 //----------PIPELINE-----------------------------------------------------------
4317 pipeline %{
4318
4319 //----------ATTRIBUTES---------------------------------------------------------
4320 attributes %{
4321 fixed_size_instructions; // Fixed size instructions
4322 branch_has_delay_slot; // Branch has delay slot following
4323 max_instructions_per_bundle = 4; // Up to 4 instructions per bundle
4324 instruction_unit_size = 4; // An instruction is 4 bytes long
4325 instruction_fetch_unit_size = 16; // The processor fetches one line
4326 instruction_fetch_units = 1; // of 16 bytes
4327
4328 // List of nop instructions
4329 nops( Nop_A0, Nop_A1, Nop_MS, Nop_FA, Nop_BR );
4330 %}
4331
4332 //----------RESOURCES----------------------------------------------------------
4333 // Resources are the functional units available to the machine
4334 resources(A0, A1, MS, BR, FA, FM, IDIV, FDIV, IALU = A0 | A1);
4335
4336 //----------PIPELINE DESCRIPTION-----------------------------------------------
4337 // Pipeline Description specifies the stages in the machine's pipeline
4338
4339 pipe_desc(A, P, F, B, I, J, S, R, E, C, M, W, X, T, D);
4340
4341 //----------PIPELINE CLASSES---------------------------------------------------
4342 // Pipeline Classes describe the stages in which input and output are
4343 // referenced by the hardware pipeline.
4344
4345 // Integer ALU reg-reg operation
4346 pipe_class ialu_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
4347 single_instruction;
4348 dst : E(write);
4349 src1 : R(read);
4350 src2 : R(read);
4351 IALU : R;
4352 %}
4353
4354 // Integer ALU reg-reg long operation
4355 pipe_class ialu_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{
4356 instruction_count(2);
4357 dst : E(write);
4358 src1 : R(read);
4359 src2 : R(read);
4360 IALU : R;
4361 IALU : R;
4362 %}
4363
4364 // Integer ALU reg-reg long dependent operation
4365 pipe_class ialu_reg_reg_2_dep(iRegL dst, iRegL src1, iRegL src2, flagsReg cr) %{
4366 instruction_count(1); multiple_bundles;
4367 dst : E(write);
4368 src1 : R(read);
4369 src2 : R(read);
4370 cr : E(write);
4371 IALU : R(2);
4372 %}
4373
4374 // Integer ALU reg-imm operaion
4375 pipe_class ialu_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{
4376 single_instruction;
4377 dst : E(write);
4378 src1 : R(read);
4379 IALU : R;
4380 %}
4381
4382 // Integer ALU reg-reg operation with condition code
4383 pipe_class ialu_cc_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
4384 single_instruction;
4385 dst : E(write);
4386 cr : E(write);
4387 src1 : R(read);
4388 src2 : R(read);
4389 IALU : R;
4390 %}
4391
4392 // Integer ALU reg-imm operation with condition code
4393 pipe_class ialu_cc_reg_imm(iRegI dst, iRegI src1, immI13 src2, flagsReg cr) %{
4394 single_instruction;
4395 dst : E(write);
4396 cr : E(write);
4397 src1 : R(read);
4398 IALU : R;
4399 %}
4400
4401 // Integer ALU zero-reg operation
4402 pipe_class ialu_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{
4403 single_instruction;
4404 dst : E(write);
4405 src2 : R(read);
4406 IALU : R;
4407 %}
4408
4409 // Integer ALU zero-reg operation with condition code only
4410 pipe_class ialu_cconly_zero_reg(flagsReg cr, iRegI src) %{
4411 single_instruction;
4412 cr : E(write);
4413 src : R(read);
4414 IALU : R;
4415 %}
4416
4417 // Integer ALU reg-reg operation with condition code only
4418 pipe_class ialu_cconly_reg_reg(flagsReg cr, iRegI src1, iRegI src2) %{
4419 single_instruction;
4420 cr : E(write);
4421 src1 : R(read);
4422 src2 : R(read);
4423 IALU : R;
4424 %}
4425
4426 // Integer ALU reg-imm operation with condition code only
4427 pipe_class ialu_cconly_reg_imm(flagsReg cr, iRegI src1, immI13 src2) %{
4428 single_instruction;
4429 cr : E(write);
4430 src1 : R(read);
4431 IALU : R;
4432 %}
4433
4434 // Integer ALU reg-reg-zero operation with condition code only
4435 pipe_class ialu_cconly_reg_reg_zero(flagsReg cr, iRegI src1, iRegI src2, immI0 zero) %{
4436 single_instruction;
4437 cr : E(write);
4438 src1 : R(read);
4439 src2 : R(read);
4440 IALU : R;
4441 %}
4442
4443 // Integer ALU reg-imm-zero operation with condition code only
4444 pipe_class ialu_cconly_reg_imm_zero(flagsReg cr, iRegI src1, immI13 src2, immI0 zero) %{
4445 single_instruction;
4446 cr : E(write);
4447 src1 : R(read);
4448 IALU : R;
4449 %}
4450
4451 // Integer ALU reg-reg operation with condition code, src1 modified
4452 pipe_class ialu_cc_rwreg_reg(flagsReg cr, iRegI src1, iRegI src2) %{
4453 single_instruction;
4454 cr : E(write);
4455 src1 : E(write);
4456 src1 : R(read);
4457 src2 : R(read);
4458 IALU : R;
4459 %}
4460
4461 // Integer ALU reg-imm operation with condition code, src1 modified
4462 pipe_class ialu_cc_rwreg_imm(flagsReg cr, iRegI src1, immI13 src2) %{
4463 single_instruction;
4464 cr : E(write);
4465 src1 : E(write);
4466 src1 : R(read);
4467 IALU : R;
4468 %}
4469
4470 pipe_class cmpL_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg cr ) %{
4471 multiple_bundles;
4472 dst : E(write)+4;
4473 cr : E(write);
4474 src1 : R(read);
4475 src2 : R(read);
4476 IALU : R(3);
4477 BR : R(2);
4478 %}
4479
4480 // Integer ALU operation
4481 pipe_class ialu_none(iRegI dst) %{
4482 single_instruction;
4483 dst : E(write);
4484 IALU : R;
4485 %}
4486
4487 // Integer ALU reg operation
4488 pipe_class ialu_reg(iRegI dst, iRegI src) %{
4489 single_instruction; may_have_no_code;
4490 dst : E(write);
4491 src : R(read);
4492 IALU : R;
4493 %}
4494
4495 // Integer ALU reg conditional operation
4496 // This instruction has a 1 cycle stall, and cannot execute
4497 // in the same cycle as the instruction setting the condition
4498 // code. We kludge this by pretending to read the condition code
4499 // 1 cycle earlier, and by marking the functional units as busy
4500 // for 2 cycles with the result available 1 cycle later than
4501 // is really the case.
4502 pipe_class ialu_reg_flags( iRegI op2_out, iRegI op2_in, iRegI op1, flagsReg cr ) %{
4503 single_instruction;
4504 op2_out : C(write);
4505 op1 : R(read);
4506 cr : R(read); // This is really E, with a 1 cycle stall
4507 BR : R(2);
4508 MS : R(2);
4509 %}
4510
4511 #ifdef _LP64
4512 pipe_class ialu_clr_and_mover( iRegI dst, iRegP src ) %{
4513 instruction_count(1); multiple_bundles;
4514 dst : C(write)+1;
4515 src : R(read)+1;
4516 IALU : R(1);
4517 BR : E(2);
4518 MS : E(2);
4519 %}
4520 #endif
4521
4522 // Integer ALU reg operation
4523 pipe_class ialu_move_reg_L_to_I(iRegI dst, iRegL src) %{
4524 single_instruction; may_have_no_code;
4525 dst : E(write);
4526 src : R(read);
4527 IALU : R;
4528 %}
4529 pipe_class ialu_move_reg_I_to_L(iRegL dst, iRegI src) %{
4530 single_instruction; may_have_no_code;
4531 dst : E(write);
4532 src : R(read);
4533 IALU : R;
4534 %}
4535
4536 // Two integer ALU reg operations
4537 pipe_class ialu_reg_2(iRegL dst, iRegL src) %{
4538 instruction_count(2);
4539 dst : E(write);
4540 src : R(read);
4541 A0 : R;
4542 A1 : R;
4543 %}
4544
4545 // Two integer ALU reg operations
4546 pipe_class ialu_move_reg_L_to_L(iRegL dst, iRegL src) %{
4547 instruction_count(2); may_have_no_code;
4548 dst : E(write);
4549 src : R(read);
4550 A0 : R;
4551 A1 : R;
4552 %}
4553
4554 // Integer ALU imm operation
4555 pipe_class ialu_imm(iRegI dst, immI13 src) %{
4556 single_instruction;
4557 dst : E(write);
4558 IALU : R;
4559 %}
4560
4561 // Integer ALU reg-reg with carry operation
4562 pipe_class ialu_reg_reg_cy(iRegI dst, iRegI src1, iRegI src2, iRegI cy) %{
4563 single_instruction;
4564 dst : E(write);
4565 src1 : R(read);
4566 src2 : R(read);
4567 IALU : R;
4568 %}
4569
4570 // Integer ALU cc operation
4571 pipe_class ialu_cc(iRegI dst, flagsReg cc) %{
4572 single_instruction;
4573 dst : E(write);
4574 cc : R(read);
4575 IALU : R;
4576 %}
4577
4578 // Integer ALU cc / second IALU operation
4579 pipe_class ialu_reg_ialu( iRegI dst, iRegI src ) %{
4580 instruction_count(1); multiple_bundles;
4581 dst : E(write)+1;
4582 src : R(read);
4583 IALU : R;
4584 %}
4585
4586 // Integer ALU cc / second IALU operation
4587 pipe_class ialu_reg_reg_ialu( iRegI dst, iRegI p, iRegI q ) %{
4588 instruction_count(1); multiple_bundles;
4589 dst : E(write)+1;
4590 p : R(read);
4591 q : R(read);
4592 IALU : R;
4593 %}
4594
4595 // Integer ALU hi-lo-reg operation
4596 pipe_class ialu_hi_lo_reg(iRegI dst, immI src) %{
4597 instruction_count(1); multiple_bundles;
4598 dst : E(write)+1;
4599 IALU : R(2);
4600 %}
4601
4602 // Float ALU hi-lo-reg operation (with temp)
4603 pipe_class ialu_hi_lo_reg_temp(regF dst, immF src, g3RegP tmp) %{
4604 instruction_count(1); multiple_bundles;
4605 dst : E(write)+1;
4606 IALU : R(2);
4607 %}
4608
4609 // Long Constant
4610 pipe_class loadConL( iRegL dst, immL src ) %{
4611 instruction_count(2); multiple_bundles;
4612 dst : E(write)+1;
4613 IALU : R(2);
4614 IALU : R(2);
4615 %}
4616
4617 // Pointer Constant
4618 pipe_class loadConP( iRegP dst, immP src ) %{
4619 instruction_count(0); multiple_bundles;
4620 fixed_latency(6);
4621 %}
4622
4623 // Polling Address
4624 pipe_class loadConP_poll( iRegP dst, immP_poll src ) %{
4625 #ifdef _LP64
4626 instruction_count(0); multiple_bundles;
4627 fixed_latency(6);
4628 #else
4629 dst : E(write);
4630 IALU : R;
4631 #endif
4632 %}
4633
4634 // Long Constant small
4635 pipe_class loadConLlo( iRegL dst, immL src ) %{
4636 instruction_count(2);
4637 dst : E(write);
4638 IALU : R;
4639 IALU : R;
4640 %}
4641
4642 // [PHH] This is wrong for 64-bit. See LdImmF/D.
4643 pipe_class loadConFD(regF dst, immF src, g3RegP tmp) %{
4644 instruction_count(1); multiple_bundles;
4645 src : R(read);
4646 dst : M(write)+1;
4647 IALU : R;
4648 MS : E;
4649 %}
4650
4651 // Integer ALU nop operation
4652 pipe_class ialu_nop() %{
4653 single_instruction;
4654 IALU : R;
4655 %}
4656
4657 // Integer ALU nop operation
4658 pipe_class ialu_nop_A0() %{
4659 single_instruction;
4660 A0 : R;
4661 %}
4662
4663 // Integer ALU nop operation
4664 pipe_class ialu_nop_A1() %{
4665 single_instruction;
4666 A1 : R;
4667 %}
4668
4669 // Integer Multiply reg-reg operation
4670 pipe_class imul_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
4671 single_instruction;
4672 dst : E(write);
4673 src1 : R(read);
4674 src2 : R(read);
4675 MS : R(5);
4676 %}
4677
4678 // Integer Multiply reg-imm operation
4679 pipe_class imul_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{
4680 single_instruction;
4681 dst : E(write);
4682 src1 : R(read);
4683 MS : R(5);
4684 %}
4685
4686 pipe_class mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
4687 single_instruction;
4688 dst : E(write)+4;
4689 src1 : R(read);
4690 src2 : R(read);
4691 MS : R(6);
4692 %}
4693
4694 pipe_class mulL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{
4695 single_instruction;
4696 dst : E(write)+4;
4697 src1 : R(read);
4698 MS : R(6);
4699 %}
4700
4701 // Integer Divide reg-reg
4702 pipe_class sdiv_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI temp, flagsReg cr) %{
4703 instruction_count(1); multiple_bundles;
4704 dst : E(write);
4705 temp : E(write);
4706 src1 : R(read);
4707 src2 : R(read);
4708 temp : R(read);
4709 MS : R(38);
4710 %}
4711
4712 // Integer Divide reg-imm
4713 pipe_class sdiv_reg_imm(iRegI dst, iRegI src1, immI13 src2, iRegI temp, flagsReg cr) %{
4714 instruction_count(1); multiple_bundles;
4715 dst : E(write);
4716 temp : E(write);
4717 src1 : R(read);
4718 temp : R(read);
4719 MS : R(38);
4720 %}
4721
4722 // Long Divide
4723 pipe_class divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
4724 dst : E(write)+71;
4725 src1 : R(read);
4726 src2 : R(read)+1;
4727 MS : R(70);
4728 %}
4729
4730 pipe_class divL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{
4731 dst : E(write)+71;
4732 src1 : R(read);
4733 MS : R(70);
4734 %}
4735
4736 // Floating Point Add Float
4737 pipe_class faddF_reg_reg(regF dst, regF src1, regF src2) %{
4738 single_instruction;
4739 dst : X(write);
4740 src1 : E(read);
4741 src2 : E(read);
4742 FA : R;
4743 %}
4744
4745 // Floating Point Add Double
4746 pipe_class faddD_reg_reg(regD dst, regD src1, regD src2) %{
4747 single_instruction;
4748 dst : X(write);
4749 src1 : E(read);
4750 src2 : E(read);
4751 FA : R;
4752 %}
4753
4754 // Floating Point Conditional Move based on integer flags
4755 pipe_class int_conditional_float_move (cmpOp cmp, flagsReg cr, regF dst, regF src) %{
4756 single_instruction;
4757 dst : X(write);
4758 src : E(read);
4759 cr : R(read);
4760 FA : R(2);
4761 BR : R(2);
4762 %}
4763
4764 // Floating Point Conditional Move based on integer flags
4765 pipe_class int_conditional_double_move (cmpOp cmp, flagsReg cr, regD dst, regD src) %{
4766 single_instruction;
4767 dst : X(write);
4768 src : E(read);
4769 cr : R(read);
4770 FA : R(2);
4771 BR : R(2);
4772 %}
4773
4774 // Floating Point Multiply Float
4775 pipe_class fmulF_reg_reg(regF dst, regF src1, regF src2) %{
4776 single_instruction;
4777 dst : X(write);
4778 src1 : E(read);
4779 src2 : E(read);
4780 FM : R;
4781 %}
4782
4783 // Floating Point Multiply Double
4784 pipe_class fmulD_reg_reg(regD dst, regD src1, regD src2) %{
4785 single_instruction;
4786 dst : X(write);
4787 src1 : E(read);
4788 src2 : E(read);
4789 FM : R;
4790 %}
4791
4792 // Floating Point Divide Float
4793 pipe_class fdivF_reg_reg(regF dst, regF src1, regF src2) %{
4794 single_instruction;
4795 dst : X(write);
4796 src1 : E(read);
4797 src2 : E(read);
4798 FM : R;
4799 FDIV : C(14);
4800 %}
4801
4802 // Floating Point Divide Double
4803 pipe_class fdivD_reg_reg(regD dst, regD src1, regD src2) %{
4804 single_instruction;
4805 dst : X(write);
4806 src1 : E(read);
4807 src2 : E(read);
4808 FM : R;
4809 FDIV : C(17);
4810 %}
4811
4812 // Floating Point Move/Negate/Abs Float
4813 pipe_class faddF_reg(regF dst, regF src) %{
4814 single_instruction;
4815 dst : W(write);
4816 src : E(read);
4817 FA : R(1);
4818 %}
4819
4820 // Floating Point Move/Negate/Abs Double
4821 pipe_class faddD_reg(regD dst, regD src) %{
4822 single_instruction;
4823 dst : W(write);
4824 src : E(read);
4825 FA : R;
4826 %}
4827
4828 // Floating Point Convert F->D
4829 pipe_class fcvtF2D(regD dst, regF src) %{
4830 single_instruction;
4831 dst : X(write);
4832 src : E(read);
4833 FA : R;
4834 %}
4835
4836 // Floating Point Convert I->D
4837 pipe_class fcvtI2D(regD dst, regF src) %{
4838 single_instruction;
4839 dst : X(write);
4840 src : E(read);
4841 FA : R;
4842 %}
4843
4844 // Floating Point Convert LHi->D
4845 pipe_class fcvtLHi2D(regD dst, regD src) %{
4846 single_instruction;
4847 dst : X(write);
4848 src : E(read);
4849 FA : R;
4850 %}
4851
4852 // Floating Point Convert L->D
4853 pipe_class fcvtL2D(regD dst, regF src) %{
4854 single_instruction;
4855 dst : X(write);
4856 src : E(read);
4857 FA : R;
4858 %}
4859
4860 // Floating Point Convert L->F
4861 pipe_class fcvtL2F(regD dst, regF src) %{
4862 single_instruction;
4863 dst : X(write);
4864 src : E(read);
4865 FA : R;
4866 %}
4867
4868 // Floating Point Convert D->F
4869 pipe_class fcvtD2F(regD dst, regF src) %{
4870 single_instruction;
4871 dst : X(write);
4872 src : E(read);
4873 FA : R;
4874 %}
4875
4876 // Floating Point Convert I->L
4877 pipe_class fcvtI2L(regD dst, regF src) %{
4878 single_instruction;
4879 dst : X(write);
4880 src : E(read);
4881 FA : R;
4882 %}
4883
4884 // Floating Point Convert D->F
4885 pipe_class fcvtD2I(regF dst, regD src, flagsReg cr) %{
4886 instruction_count(1); multiple_bundles;
4887 dst : X(write)+6;
4888 src : E(read);
4889 FA : R;
4890 %}
4891
4892 // Floating Point Convert D->L
4893 pipe_class fcvtD2L(regD dst, regD src, flagsReg cr) %{
4894 instruction_count(1); multiple_bundles;
4895 dst : X(write)+6;
4896 src : E(read);
4897 FA : R;
4898 %}
4899
4900 // Floating Point Convert F->I
4901 pipe_class fcvtF2I(regF dst, regF src, flagsReg cr) %{
4902 instruction_count(1); multiple_bundles;
4903 dst : X(write)+6;
4904 src : E(read);
4905 FA : R;
4906 %}
4907
4908 // Floating Point Convert F->L
4909 pipe_class fcvtF2L(regD dst, regF src, flagsReg cr) %{
4910 instruction_count(1); multiple_bundles;
4911 dst : X(write)+6;
4912 src : E(read);
4913 FA : R;
4914 %}
4915
4916 // Floating Point Convert I->F
4917 pipe_class fcvtI2F(regF dst, regF src) %{
4918 single_instruction;
4919 dst : X(write);
4920 src : E(read);
4921 FA : R;
4922 %}
4923
4924 // Floating Point Compare
4925 pipe_class faddF_fcc_reg_reg_zero(flagsRegF cr, regF src1, regF src2, immI0 zero) %{
4926 single_instruction;
4927 cr : X(write);
4928 src1 : E(read);
4929 src2 : E(read);
4930 FA : R;
4931 %}
4932
4933 // Floating Point Compare
4934 pipe_class faddD_fcc_reg_reg_zero(flagsRegF cr, regD src1, regD src2, immI0 zero) %{
4935 single_instruction;
4936 cr : X(write);
4937 src1 : E(read);
4938 src2 : E(read);
4939 FA : R;
4940 %}
4941
4942 // Floating Add Nop
4943 pipe_class fadd_nop() %{
4944 single_instruction;
4945 FA : R;
4946 %}
4947
4948 // Integer Store to Memory
4949 pipe_class istore_mem_reg(memory mem, iRegI src) %{
4950 single_instruction;
4951 mem : R(read);
4952 src : C(read);
4953 MS : R;
4954 %}
4955
4956 // Integer Store to Memory
4957 pipe_class istore_mem_spORreg(memory mem, sp_ptr_RegP src) %{
4958 single_instruction;
4959 mem : R(read);
4960 src : C(read);
4961 MS : R;
4962 %}
4963
4964 // Integer Store Zero to Memory
4965 pipe_class istore_mem_zero(memory mem, immI0 src) %{
4966 single_instruction;
4967 mem : R(read);
4968 MS : R;
4969 %}
4970
4971 // Special Stack Slot Store
4972 pipe_class istore_stk_reg(stackSlotI stkSlot, iRegI src) %{
4973 single_instruction;
4974 stkSlot : R(read);
4975 src : C(read);
4976 MS : R;
4977 %}
4978
4979 // Special Stack Slot Store
4980 pipe_class lstoreI_stk_reg(stackSlotL stkSlot, iRegI src) %{
4981 instruction_count(2); multiple_bundles;
4982 stkSlot : R(read);
4983 src : C(read);
4984 MS : R(2);
4985 %}
4986
4987 // Float Store
4988 pipe_class fstoreF_mem_reg(memory mem, RegF src) %{
4989 single_instruction;
4990 mem : R(read);
4991 src : C(read);
4992 MS : R;
4993 %}
4994
4995 // Float Store
4996 pipe_class fstoreF_mem_zero(memory mem, immF0 src) %{
4997 single_instruction;
4998 mem : R(read);
4999 MS : R;
5000 %}
5001
5002 // Double Store
5003 pipe_class fstoreD_mem_reg(memory mem, RegD src) %{
5004 instruction_count(1);
5005 mem : R(read);
5006 src : C(read);
5007 MS : R;
5008 %}
5009
5010 // Double Store
5011 pipe_class fstoreD_mem_zero(memory mem, immD0 src) %{
5012 single_instruction;
5013 mem : R(read);
5014 MS : R;
5015 %}
5016
5017 // Special Stack Slot Float Store
5018 pipe_class fstoreF_stk_reg(stackSlotI stkSlot, RegF src) %{
5019 single_instruction;
5020 stkSlot : R(read);
5021 src : C(read);
5022 MS : R;
5023 %}
5024
5025 // Special Stack Slot Double Store
5026 pipe_class fstoreD_stk_reg(stackSlotI stkSlot, RegD src) %{
5027 single_instruction;
5028 stkSlot : R(read);
5029 src : C(read);
5030 MS : R;
5031 %}
5032
5033 // Integer Load (when sign bit propagation not needed)
5034 pipe_class iload_mem(iRegI dst, memory mem) %{
5035 single_instruction;
5036 mem : R(read);
5037 dst : C(write);
5038 MS : R;
5039 %}
5040
5041 // Integer Load from stack operand
5042 pipe_class iload_stkD(iRegI dst, stackSlotD mem ) %{
5043 single_instruction;
5044 mem : R(read);
5045 dst : C(write);
5046 MS : R;
5047 %}
5048
5049 // Integer Load (when sign bit propagation or masking is needed)
5050 pipe_class iload_mask_mem(iRegI dst, memory mem) %{
5051 single_instruction;
5052 mem : R(read);
5053 dst : M(write);
5054 MS : R;
5055 %}
5056
5057 // Float Load
5058 pipe_class floadF_mem(regF dst, memory mem) %{
5059 single_instruction;
5060 mem : R(read);
5061 dst : M(write);
5062 MS : R;
5063 %}
5064
5065 // Float Load
5066 pipe_class floadD_mem(regD dst, memory mem) %{
5067 instruction_count(1); multiple_bundles; // Again, unaligned argument is only multiple case
5068 mem : R(read);
5069 dst : M(write);
5070 MS : R;
5071 %}
5072
5073 // Float Load
5074 pipe_class floadF_stk(regF dst, stackSlotI stkSlot) %{
5075 single_instruction;
5076 stkSlot : R(read);
5077 dst : M(write);
5078 MS : R;
5079 %}
5080
5081 // Float Load
5082 pipe_class floadD_stk(regD dst, stackSlotI stkSlot) %{
5083 single_instruction;
5084 stkSlot : R(read);
5085 dst : M(write);
5086 MS : R;
5087 %}
5088
5089 // Memory Nop
5090 pipe_class mem_nop() %{
5091 single_instruction;
5092 MS : R;
5093 %}
5094
5095 pipe_class sethi(iRegP dst, immI src) %{
5096 single_instruction;
5097 dst : E(write);
5098 IALU : R;
5099 %}
5100
5101 pipe_class loadPollP(iRegP poll) %{
5102 single_instruction;
5103 poll : R(read);
5104 MS : R;
5105 %}
5106
5107 pipe_class br(Universe br, label labl) %{
5108 single_instruction_with_delay_slot;
5109 BR : R;
5110 %}
5111
5112 pipe_class br_cc(Universe br, cmpOp cmp, flagsReg cr, label labl) %{
5113 single_instruction_with_delay_slot;
5114 cr : E(read);
5115 BR : R;
5116 %}
5117
5118 pipe_class br_reg(Universe br, cmpOp cmp, iRegI op1, label labl) %{
5119 single_instruction_with_delay_slot;
5120 op1 : E(read);
5121 BR : R;
5122 MS : R;
5123 %}
5124
5125 pipe_class br_fcc(Universe br, cmpOpF cc, flagsReg cr, label labl) %{
5126 single_instruction_with_delay_slot;
5127 cr : E(read);
5128 BR : R;
5129 %}
5130
5131 pipe_class br_nop() %{
5132 single_instruction;
5133 BR : R;
5134 %}
5135
5136 pipe_class simple_call(method meth) %{
5137 instruction_count(2); multiple_bundles; force_serialization;
5138 fixed_latency(100);
5139 BR : R(1);
5140 MS : R(1);
5141 A0 : R(1);
5142 %}
5143
5144 pipe_class compiled_call(method meth) %{
5145 instruction_count(1); multiple_bundles; force_serialization;
5146 fixed_latency(100);
5147 MS : R(1);
5148 %}
5149
5150 pipe_class call(method meth) %{
5151 instruction_count(0); multiple_bundles; force_serialization;
5152 fixed_latency(100);
5153 %}
5154
5155 pipe_class tail_call(Universe ignore, label labl) %{
5156 single_instruction; has_delay_slot;
5157 fixed_latency(100);
5158 BR : R(1);
5159 MS : R(1);
5160 %}
5161
5162 pipe_class ret(Universe ignore) %{
5163 single_instruction; has_delay_slot;
5164 BR : R(1);
5165 MS : R(1);
5166 %}
5167
5168 pipe_class ret_poll(g3RegP poll) %{
5169 instruction_count(3); has_delay_slot;
5170 poll : E(read);
5171 MS : R;
5172 %}
5173
5174 // The real do-nothing guy
5175 pipe_class empty( ) %{
5176 instruction_count(0);
5177 %}
5178
5179 pipe_class long_memory_op() %{
5180 instruction_count(0); multiple_bundles; force_serialization;
5181 fixed_latency(25);
5182 MS : R(1);
5183 %}
5184
5185 // Check-cast
5186 pipe_class partial_subtype_check_pipe(Universe ignore, iRegP array, iRegP match ) %{
5187 array : R(read);
5188 match : R(read);
5189 IALU : R(2);
5190 BR : R(2);
5191 MS : R;
5192 %}
5193
5194 // Convert FPU flags into +1,0,-1
5195 pipe_class floating_cmp( iRegI dst, regF src1, regF src2 ) %{
5196 src1 : E(read);
5197 src2 : E(read);
5198 dst : E(write);
5199 FA : R;
5200 MS : R(2);
5201 BR : R(2);
5202 %}
5203
5204 // Compare for p < q, and conditionally add y
5205 pipe_class cadd_cmpltmask( iRegI p, iRegI q, iRegI y ) %{
5206 p : E(read);
5207 q : E(read);
5208 y : E(read);
5209 IALU : R(3)
5210 %}
5211
5212 // Perform a compare, then move conditionally in a branch delay slot.
5213 pipe_class min_max( iRegI src2, iRegI srcdst ) %{
5214 src2 : E(read);
5215 srcdst : E(read);
5216 IALU : R;
5217 BR : R;
5218 %}
5219
5220 // Define the class for the Nop node
5221 define %{
5222 MachNop = ialu_nop;
5223 %}
5224
5225 %}
5226
5227 //----------INSTRUCTIONS-------------------------------------------------------
5228
5229 //------------Special Stack Slot instructions - no match rules-----------------
5230 instruct stkI_to_regF(regF dst, stackSlotI src) %{
5231 // No match rule to avoid chain rule match.
5232 effect(DEF dst, USE src);
5233 ins_cost(MEMORY_REF_COST);
5234 size(4);
5235 format %{ "LDF $src,$dst\t! stkI to regF" %}
5236 opcode(Assembler::ldf_op3);
5237 ins_encode(simple_form3_mem_reg(src, dst));
5238 ins_pipe(floadF_stk);
5239 %}
5240
5241 instruct stkL_to_regD(regD dst, stackSlotL src) %{
5242 // No match rule to avoid chain rule match.
5243 effect(DEF dst, USE src);
5244 ins_cost(MEMORY_REF_COST);
5245 size(4);
5246 format %{ "LDDF $src,$dst\t! stkL to regD" %}
5247 opcode(Assembler::lddf_op3);
5248 ins_encode(simple_form3_mem_reg(src, dst));
5249 ins_pipe(floadD_stk);
5250 %}
5251
5252 instruct regF_to_stkI(stackSlotI dst, regF src) %{
5253 // No match rule to avoid chain rule match.
5254 effect(DEF dst, USE src);
5255 ins_cost(MEMORY_REF_COST);
5256 size(4);
5257 format %{ "STF $src,$dst\t! regF to stkI" %}
5258 opcode(Assembler::stf_op3);
5259 ins_encode(simple_form3_mem_reg(dst, src));
5260 ins_pipe(fstoreF_stk_reg);
5261 %}
5262
5263 instruct regD_to_stkL(stackSlotL dst, regD src) %{
5264 // No match rule to avoid chain rule match.
5265 effect(DEF dst, USE src);
5266 ins_cost(MEMORY_REF_COST);
5267 size(4);
5268 format %{ "STDF $src,$dst\t! regD to stkL" %}
5269 opcode(Assembler::stdf_op3);
5270 ins_encode(simple_form3_mem_reg(dst, src));
5271 ins_pipe(fstoreD_stk_reg);
5272 %}
5273
5274 instruct regI_to_stkLHi(stackSlotL dst, iRegI src) %{
5275 effect(DEF dst, USE src);
5276 ins_cost(MEMORY_REF_COST*2);
5277 size(8);
5278 format %{ "STW $src,$dst.hi\t! long\n\t"
5279 "STW R_G0,$dst.lo" %}
5280 opcode(Assembler::stw_op3);
5281 ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, R_G0));
5282 ins_pipe(lstoreI_stk_reg);
5283 %}
5284
5285 instruct regL_to_stkD(stackSlotD dst, iRegL src) %{
5286 // No match rule to avoid chain rule match.
5287 effect(DEF dst, USE src);
5288 ins_cost(MEMORY_REF_COST);
5289 size(4);
5290 format %{ "STX $src,$dst\t! regL to stkD" %}
5291 opcode(Assembler::stx_op3);
5292 ins_encode(simple_form3_mem_reg( dst, src ) );
5293 ins_pipe(istore_stk_reg);
5294 %}
5295
5296 //---------- Chain stack slots between similar types --------
5297
5298 // Load integer from stack slot
5299 instruct stkI_to_regI( iRegI dst, stackSlotI src ) %{
5300 match(Set dst src);
5301 ins_cost(MEMORY_REF_COST);
5302
5303 size(4);
5304 format %{ "LDUW $src,$dst\t!stk" %}
5305 opcode(Assembler::lduw_op3);
5306 ins_encode(simple_form3_mem_reg( src, dst ) );
5307 ins_pipe(iload_mem);
5308 %}
5309
5310 // Store integer to stack slot
5311 instruct regI_to_stkI( stackSlotI dst, iRegI src ) %{
5312 match(Set dst src);
5313 ins_cost(MEMORY_REF_COST);
5314
5315 size(4);
5316 format %{ "STW $src,$dst\t!stk" %}
5317 opcode(Assembler::stw_op3);
5318 ins_encode(simple_form3_mem_reg( dst, src ) );
5319 ins_pipe(istore_mem_reg);
5320 %}
5321
5322 // Load long from stack slot
5323 instruct stkL_to_regL( iRegL dst, stackSlotL src ) %{
5324 match(Set dst src);
5325
5326 ins_cost(MEMORY_REF_COST);
5327 size(4);
5328 format %{ "LDX $src,$dst\t! long" %}
5329 opcode(Assembler::ldx_op3);
5330 ins_encode(simple_form3_mem_reg( src, dst ) );
5331 ins_pipe(iload_mem);
5332 %}
5333
5334 // Store long to stack slot
5335 instruct regL_to_stkL(stackSlotL dst, iRegL src) %{
5336 match(Set dst src);
5337
5338 ins_cost(MEMORY_REF_COST);
5339 size(4);
5340 format %{ "STX $src,$dst\t! long" %}
5341 opcode(Assembler::stx_op3);
5342 ins_encode(simple_form3_mem_reg( dst, src ) );
5343 ins_pipe(istore_mem_reg);
5344 %}
5345
5346 #ifdef _LP64
5347 // Load pointer from stack slot, 64-bit encoding
5348 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{
5349 match(Set dst src);
5350 ins_cost(MEMORY_REF_COST);
5351 size(4);
5352 format %{ "LDX $src,$dst\t!ptr" %}
5353 opcode(Assembler::ldx_op3);
5354 ins_encode(simple_form3_mem_reg( src, dst ) );
5355 ins_pipe(iload_mem);
5356 %}
5357
5358 // Store pointer to stack slot
5359 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{
5360 match(Set dst src);
5361 ins_cost(MEMORY_REF_COST);
5362 size(4);
5363 format %{ "STX $src,$dst\t!ptr" %}
5364 opcode(Assembler::stx_op3);
5365 ins_encode(simple_form3_mem_reg( dst, src ) );
5366 ins_pipe(istore_mem_reg);
5367 %}
5368 #else // _LP64
5369 // Load pointer from stack slot, 32-bit encoding
5370 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{
5371 match(Set dst src);
5372 ins_cost(MEMORY_REF_COST);
5373 format %{ "LDUW $src,$dst\t!ptr" %}
5374 opcode(Assembler::lduw_op3, Assembler::ldst_op);
5375 ins_encode(simple_form3_mem_reg( src, dst ) );
5376 ins_pipe(iload_mem);
5377 %}
5378
5379 // Store pointer to stack slot
5380 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{
5381 match(Set dst src);
5382 ins_cost(MEMORY_REF_COST);
5383 format %{ "STW $src,$dst\t!ptr" %}
5384 opcode(Assembler::stw_op3, Assembler::ldst_op);
5385 ins_encode(simple_form3_mem_reg( dst, src ) );
5386 ins_pipe(istore_mem_reg);
5387 %}
5388 #endif // _LP64
5389
5390 //------------Special Nop instructions for bundling - no match rules-----------
5391 // Nop using the A0 functional unit
5392 instruct Nop_A0() %{
5393 ins_cost(0);
5394
5395 format %{ "NOP ! Alu Pipeline" %}
5396 opcode(Assembler::or_op3, Assembler::arith_op);
5397 ins_encode( form2_nop() );
5398 ins_pipe(ialu_nop_A0);
5399 %}
5400
5401 // Nop using the A1 functional unit
5402 instruct Nop_A1( ) %{
5403 ins_cost(0);
5404
5405 format %{ "NOP ! Alu Pipeline" %}
5406 opcode(Assembler::or_op3, Assembler::arith_op);
5407 ins_encode( form2_nop() );
5408 ins_pipe(ialu_nop_A1);
5409 %}
5410
5411 // Nop using the memory functional unit
5412 instruct Nop_MS( ) %{
5413 ins_cost(0);
5414
5415 format %{ "NOP ! Memory Pipeline" %}
5416 ins_encode( emit_mem_nop );
5417 ins_pipe(mem_nop);
5418 %}
5419
5420 // Nop using the floating add functional unit
5421 instruct Nop_FA( ) %{
5422 ins_cost(0);
5423
5424 format %{ "NOP ! Floating Add Pipeline" %}
5425 ins_encode( emit_fadd_nop );
5426 ins_pipe(fadd_nop);
5427 %}
5428
5429 // Nop using the branch functional unit
5430 instruct Nop_BR( ) %{
5431 ins_cost(0);
5432
5433 format %{ "NOP ! Branch Pipeline" %}
5434 ins_encode( emit_br_nop );
5435 ins_pipe(br_nop);
5436 %}
5437
5438 //----------Load/Store/Move Instructions---------------------------------------
5439 //----------Load Instructions--------------------------------------------------
5440 // Load Byte (8bit signed)
5441 instruct loadB(iRegI dst, memory mem) %{
5442 match(Set dst (LoadB mem));
5443 ins_cost(MEMORY_REF_COST);
5444
5445 size(4);
5446 format %{ "LDSB $mem,$dst\t! byte" %}
5447 ins_encode %{
5448 __ ldsb($mem$$Address, $dst$$Register);
5449 %}
5450 ins_pipe(iload_mask_mem);
5451 %}
5452
5453 // Load Byte (8bit signed) into a Long Register
5454 instruct loadB2L(iRegL dst, memory mem) %{
5455 match(Set dst (ConvI2L (LoadB mem)));
5456 ins_cost(MEMORY_REF_COST);
5457
5458 size(4);
5459 format %{ "LDSB $mem,$dst\t! byte -> long" %}
5460 ins_encode %{
5461 __ ldsb($mem$$Address, $dst$$Register);
5462 %}
5463 ins_pipe(iload_mask_mem);
5464 %}
5465
5466 // Load Unsigned Byte (8bit UNsigned) into an int reg
5467 instruct loadUB(iRegI dst, memory mem) %{
5468 match(Set dst (LoadUB mem));
5469 ins_cost(MEMORY_REF_COST);
5470
5471 size(4);
5472 format %{ "LDUB $mem,$dst\t! ubyte" %}
5473 ins_encode %{
5474 __ ldub($mem$$Address, $dst$$Register);
5475 %}
5476 ins_pipe(iload_mask_mem);
5477 %}
5478
5479 // Load Unsigned Byte (8bit UNsigned) into a Long Register
5480 instruct loadUB2L(iRegL dst, memory mem) %{
5481 match(Set dst (ConvI2L (LoadUB mem)));
5482 ins_cost(MEMORY_REF_COST);
5483
5484 size(4);
5485 format %{ "LDUB $mem,$dst\t! ubyte -> long" %}
5486 ins_encode %{
5487 __ ldub($mem$$Address, $dst$$Register);
5488 %}
5489 ins_pipe(iload_mask_mem);
5490 %}
5491
5492 // Load Short (16bit signed)
5493 instruct loadS(iRegI dst, memory mem) %{
5494 match(Set dst (LoadS mem));
5495 ins_cost(MEMORY_REF_COST);
5496
5497 size(4);
5498 format %{ "LDSH $mem,$dst\t! short" %}
5499 ins_encode %{
5500 __ ldsh($mem$$Address, $dst$$Register);
5501 %}
5502 ins_pipe(iload_mask_mem);
5503 %}
5504
5505 // Load Short (16bit signed) into a Long Register
5506 instruct loadS2L(iRegL dst, memory mem) %{
5507 match(Set dst (ConvI2L (LoadS mem)));
5508 ins_cost(MEMORY_REF_COST);
5509
5510 size(4);
5511 format %{ "LDSH $mem,$dst\t! short -> long" %}
5512 ins_encode %{
5513 __ ldsh($mem$$Address, $dst$$Register);
5514 %}
5515 ins_pipe(iload_mask_mem);
5516 %}
5517
5518 // Load Unsigned Short/Char (16bit UNsigned)
5519 instruct loadUS(iRegI dst, memory mem) %{
5520 match(Set dst (LoadUS mem));
5521 ins_cost(MEMORY_REF_COST);
5522
5523 size(4);
5524 format %{ "LDUH $mem,$dst\t! ushort/char" %}
5525 ins_encode %{
5526 __ lduh($mem$$Address, $dst$$Register);
5527 %}
5528 ins_pipe(iload_mask_mem);
5529 %}
5530
5531 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register
5532 instruct loadUS2L(iRegL dst, memory mem) %{
5533 match(Set dst (ConvI2L (LoadUS mem)));
5534 ins_cost(MEMORY_REF_COST);
5535
5536 size(4);
5537 format %{ "LDUH $mem,$dst\t! ushort/char -> long" %}
5538 ins_encode %{
5539 __ lduh($mem$$Address, $dst$$Register);
5540 %}
5541 ins_pipe(iload_mask_mem);
5542 %}
5543
5544 // Load Integer
5545 instruct loadI(iRegI dst, memory mem) %{
5546 match(Set dst (LoadI mem));
5547 ins_cost(MEMORY_REF_COST);
5548
5549 size(4);
5550 format %{ "LDUW $mem,$dst\t! int" %}
5551 ins_encode %{
5552 __ lduw($mem$$Address, $dst$$Register);
5553 %}
5554 ins_pipe(iload_mem);
5555 %}
5556
5557 // Load Integer into a Long Register
5558 instruct loadI2L(iRegL dst, memory mem) %{
5559 match(Set dst (ConvI2L (LoadI mem)));
5560 ins_cost(MEMORY_REF_COST);
5561
5562 size(4);
5563 format %{ "LDSW $mem,$dst\t! int -> long" %}
5564 ins_encode %{
5565 __ ldsw($mem$$Address, $dst$$Register);
5566 %}
5567 ins_pipe(iload_mem);
5568 %}
5569
5570 // Load Unsigned Integer into a Long Register
5571 instruct loadUI2L(iRegL dst, memory mem) %{
5572 match(Set dst (LoadUI2L mem));
5573 ins_cost(MEMORY_REF_COST);
5574
5575 size(4);
5576 format %{ "LDUW $mem,$dst\t! uint -> long" %}
5577 ins_encode %{
5578 __ lduw($mem$$Address, $dst$$Register);
5579 %}
5580 ins_pipe(iload_mem);
5581 %}
5582
5583 // Load Long - aligned
5584 instruct loadL(iRegL dst, memory mem ) %{
5585 match(Set dst (LoadL mem));
5586 ins_cost(MEMORY_REF_COST);
5587
5588 size(4);
5589 format %{ "LDX $mem,$dst\t! long" %}
5590 ins_encode %{
5591 __ ldx($mem$$Address, $dst$$Register);
5592 %}
5593 ins_pipe(iload_mem);
5594 %}
5595
5596 // Load Long - UNaligned
5597 instruct loadL_unaligned(iRegL dst, memory mem, o7RegI tmp) %{
5598 match(Set dst (LoadL_unaligned mem));
5599 effect(KILL tmp);
5600 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST);
5601 size(16);
5602 format %{ "LDUW $mem+4,R_O7\t! misaligned long\n"
5603 "\tLDUW $mem ,$dst\n"
5604 "\tSLLX #32, $dst, $dst\n"
5605 "\tOR $dst, R_O7, $dst" %}
5606 opcode(Assembler::lduw_op3);
5607 ins_encode(form3_mem_reg_long_unaligned_marshal( mem, dst ));
5608 ins_pipe(iload_mem);
5609 %}
5610
5611 // Load Aligned Packed Byte into a Double Register
5612 instruct loadA8B(regD dst, memory mem) %{
5613 match(Set dst (Load8B mem));
5614 ins_cost(MEMORY_REF_COST);
5615 size(4);
5616 format %{ "LDDF $mem,$dst\t! packed8B" %}
5617 opcode(Assembler::lddf_op3);
5618 ins_encode(simple_form3_mem_reg( mem, dst ) );
5619 ins_pipe(floadD_mem);
5620 %}
5621
5622 // Load Aligned Packed Char into a Double Register
5623 instruct loadA4C(regD dst, memory mem) %{
5624 match(Set dst (Load4C mem));
5625 ins_cost(MEMORY_REF_COST);
5626 size(4);
5627 format %{ "LDDF $mem,$dst\t! packed4C" %}
5628 opcode(Assembler::lddf_op3);
5629 ins_encode(simple_form3_mem_reg( mem, dst ) );
5630 ins_pipe(floadD_mem);
5631 %}
5632
5633 // Load Aligned Packed Short into a Double Register
5634 instruct loadA4S(regD dst, memory mem) %{
5635 match(Set dst (Load4S mem));
5636 ins_cost(MEMORY_REF_COST);
5637 size(4);
5638 format %{ "LDDF $mem,$dst\t! packed4S" %}
5639 opcode(Assembler::lddf_op3);
5640 ins_encode(simple_form3_mem_reg( mem, dst ) );
5641 ins_pipe(floadD_mem);
5642 %}
5643
5644 // Load Aligned Packed Int into a Double Register
5645 instruct loadA2I(regD dst, memory mem) %{
5646 match(Set dst (Load2I mem));
5647 ins_cost(MEMORY_REF_COST);
5648 size(4);
5649 format %{ "LDDF $mem,$dst\t! packed2I" %}
5650 opcode(Assembler::lddf_op3);
5651 ins_encode(simple_form3_mem_reg( mem, dst ) );
5652 ins_pipe(floadD_mem);
5653 %}
5654
5655 // Load Range
5656 instruct loadRange(iRegI dst, memory mem) %{
5657 match(Set dst (LoadRange mem));
5658 ins_cost(MEMORY_REF_COST);
5659
5660 size(4);
5661 format %{ "LDUW $mem,$dst\t! range" %}
5662 opcode(Assembler::lduw_op3);
5663 ins_encode(simple_form3_mem_reg( mem, dst ) );
5664 ins_pipe(iload_mem);
5665 %}
5666
5667 // Load Integer into %f register (for fitos/fitod)
5668 instruct loadI_freg(regF dst, memory mem) %{
5669 match(Set dst (LoadI mem));
5670 ins_cost(MEMORY_REF_COST);
5671 size(4);
5672
5673 format %{ "LDF $mem,$dst\t! for fitos/fitod" %}
5674 opcode(Assembler::ldf_op3);
5675 ins_encode(simple_form3_mem_reg( mem, dst ) );
5676 ins_pipe(floadF_mem);
5677 %}
5678
5679 // Load Pointer
5680 instruct loadP(iRegP dst, memory mem) %{
5681 match(Set dst (LoadP mem));
5682 ins_cost(MEMORY_REF_COST);
5683 size(4);
5684
5685 #ifndef _LP64
5686 format %{ "LDUW $mem,$dst\t! ptr" %}
5687 ins_encode %{
5688 __ lduw($mem$$Address, $dst$$Register);
5689 %}
5690 #else
5691 format %{ "LDX $mem,$dst\t! ptr" %}
5692 ins_encode %{
5693 __ ldx($mem$$Address, $dst$$Register);
5694 %}
5695 #endif
5696 ins_pipe(iload_mem);
5697 %}
5698
5699 // Load Compressed Pointer
5700 instruct loadN(iRegN dst, memory mem) %{
5701 match(Set dst (LoadN mem));
5702 ins_cost(MEMORY_REF_COST);
5703 size(4);
5704
5705 format %{ "LDUW $mem,$dst\t! compressed ptr" %}
5706 ins_encode %{
5707 __ lduw($mem$$Address, $dst$$Register);
5708 %}
5709 ins_pipe(iload_mem);
5710 %}
5711
5712 // Load Klass Pointer
5713 instruct loadKlass(iRegP dst, memory mem) %{
5714 match(Set dst (LoadKlass mem));
5715 ins_cost(MEMORY_REF_COST);
5716 size(4);
5717
5718 #ifndef _LP64
5719 format %{ "LDUW $mem,$dst\t! klass ptr" %}
5720 ins_encode %{
5721 __ lduw($mem$$Address, $dst$$Register);
5722 %}
5723 #else
5724 format %{ "LDX $mem,$dst\t! klass ptr" %}
5725 ins_encode %{
5726 __ ldx($mem$$Address, $dst$$Register);
5727 %}
5728 #endif
5729 ins_pipe(iload_mem);
5730 %}
5731
5732 // Load narrow Klass Pointer
5733 instruct loadNKlass(iRegN dst, memory mem) %{
5734 match(Set dst (LoadNKlass mem));
5735 ins_cost(MEMORY_REF_COST);
5736 size(4);
5737
5738 format %{ "LDUW $mem,$dst\t! compressed klass ptr" %}
5739 ins_encode %{
5740 __ lduw($mem$$Address, $dst$$Register);
5741 %}
5742 ins_pipe(iload_mem);
5743 %}
5744
5745 // Load Double
5746 instruct loadD(regD dst, memory mem) %{
5747 match(Set dst (LoadD mem));
5748 ins_cost(MEMORY_REF_COST);
5749
5750 size(4);
5751 format %{ "LDDF $mem,$dst" %}
5752 opcode(Assembler::lddf_op3);
5753 ins_encode(simple_form3_mem_reg( mem, dst ) );
5754 ins_pipe(floadD_mem);
5755 %}
5756
5757 // Load Double - UNaligned
5758 instruct loadD_unaligned(regD_low dst, memory mem ) %{
5759 match(Set dst (LoadD_unaligned mem));
5760 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST);
5761 size(8);
5762 format %{ "LDF $mem ,$dst.hi\t! misaligned double\n"
5763 "\tLDF $mem+4,$dst.lo\t!" %}
5764 opcode(Assembler::ldf_op3);
5765 ins_encode( form3_mem_reg_double_unaligned( mem, dst ));
5766 ins_pipe(iload_mem);
5767 %}
5768
5769 // Load Float
5770 instruct loadF(regF dst, memory mem) %{
5771 match(Set dst (LoadF mem));
5772 ins_cost(MEMORY_REF_COST);
5773
5774 size(4);
5775 format %{ "LDF $mem,$dst" %}
5776 opcode(Assembler::ldf_op3);
5777 ins_encode(simple_form3_mem_reg( mem, dst ) );
5778 ins_pipe(floadF_mem);
5779 %}
5780
5781 // Load Constant
5782 instruct loadConI( iRegI dst, immI src ) %{
5783 match(Set dst src);
5784 ins_cost(DEFAULT_COST * 3/2);
5785 format %{ "SET $src,$dst" %}
5786 ins_encode( Set32(src, dst) );
5787 ins_pipe(ialu_hi_lo_reg);
5788 %}
5789
5790 instruct loadConI13( iRegI dst, immI13 src ) %{
5791 match(Set dst src);
5792
5793 size(4);
5794 format %{ "MOV $src,$dst" %}
5795 ins_encode( Set13( src, dst ) );
5796 ins_pipe(ialu_imm);
5797 %}
5798
5799 instruct loadConP(iRegP dst, immP src) %{
5800 match(Set dst src);
5801 ins_cost(DEFAULT_COST * 3/2);
5802 format %{ "SET $src,$dst\t!ptr" %}
5803 // This rule does not use "expand" unlike loadConI because then
5804 // the result type is not known to be an Oop. An ADLC
5805 // enhancement will be needed to make that work - not worth it!
5806
5807 ins_encode( SetPtr( src, dst ) );
5808 ins_pipe(loadConP);
5809
5810 %}
5811
5812 instruct loadConP0(iRegP dst, immP0 src) %{
5813 match(Set dst src);
5814
5815 size(4);
5816 format %{ "CLR $dst\t!ptr" %}
5817 ins_encode( SetNull( dst ) );
5818 ins_pipe(ialu_imm);
5819 %}
5820
5821 instruct loadConP_poll(iRegP dst, immP_poll src) %{
5822 match(Set dst src);
5823 ins_cost(DEFAULT_COST);
5824 format %{ "SET $src,$dst\t!ptr" %}
5825 ins_encode %{
5826 AddressLiteral polling_page(os::get_polling_page());
5827 __ sethi(polling_page, reg_to_register_object($dst$$reg));
5828 %}
5829 ins_pipe(loadConP_poll);
5830 %}
5831
5832 instruct loadConN0(iRegN dst, immN0 src) %{
5833 match(Set dst src);
5834
5835 size(4);
5836 format %{ "CLR $dst\t! compressed NULL ptr" %}
5837 ins_encode( SetNull( dst ) );
5838 ins_pipe(ialu_imm);
5839 %}
5840
5841 instruct loadConN(iRegN dst, immN src) %{
5842 match(Set dst src);
5843 ins_cost(DEFAULT_COST * 3/2);
5844 format %{ "SET $src,$dst\t! compressed ptr" %}
5845 ins_encode %{
5846 Register dst = $dst$$Register;
5847 __ set_narrow_oop((jobject)$src$$constant, dst);
5848 %}
5849 ins_pipe(ialu_hi_lo_reg);
5850 %}
5851
5852 instruct loadConL(iRegL dst, immL src, o7RegL tmp) %{
5853 // %%% maybe this should work like loadConD
5854 match(Set dst src);
5855 effect(KILL tmp);
5856 ins_cost(DEFAULT_COST * 4);
5857 format %{ "SET64 $src,$dst KILL $tmp\t! long" %}
5858 ins_encode( LdImmL(src, dst, tmp) );
5859 ins_pipe(loadConL);
5860 %}
5861
5862 instruct loadConL0( iRegL dst, immL0 src ) %{
5863 match(Set dst src);
5864 ins_cost(DEFAULT_COST);
5865 size(4);
5866 format %{ "CLR $dst\t! long" %}
5867 ins_encode( Set13( src, dst ) );
5868 ins_pipe(ialu_imm);
5869 %}
5870
5871 instruct loadConL13( iRegL dst, immL13 src ) %{
5872 match(Set dst src);
5873 ins_cost(DEFAULT_COST * 2);
5874
5875 size(4);
5876 format %{ "MOV $src,$dst\t! long" %}
5877 ins_encode( Set13( src, dst ) );
5878 ins_pipe(ialu_imm);
5879 %}
5880
5881 instruct loadConF(regF dst, immF src, o7RegP tmp) %{
5882 match(Set dst src);
5883 effect(KILL tmp);
5884
5885 #ifdef _LP64
5886 size(8*4);
5887 #else
5888 size(2*4);
5889 #endif
5890
5891 format %{ "SETHI hi(&$src),$tmp\t!get float $src from table\n\t"
5892 "LDF [$tmp+lo(&$src)],$dst" %}
5893 ins_encode %{
5894 address float_address = __ float_constant($src$$constant);
5895 RelocationHolder rspec = internal_word_Relocation::spec(float_address);
5896 AddressLiteral addrlit(float_address, rspec);
5897
5898 __ sethi(addrlit, $tmp$$Register);
5899 __ ldf(FloatRegisterImpl::S, $tmp$$Register, addrlit.low10(), $dst$$FloatRegister, rspec);
5900 %}
5901 ins_pipe(loadConFD);
5902 %}
5903
5904 instruct loadConD(regD dst, immD src, o7RegP tmp) %{
5905 match(Set dst src);
5906 effect(KILL tmp);
5907
5908 #ifdef _LP64
5909 size(8*4);
5910 #else
5911 size(2*4);
5912 #endif
5913
5914 format %{ "SETHI hi(&$src),$tmp\t!get double $src from table\n\t"
5915 "LDDF [$tmp+lo(&$src)],$dst" %}
5916 ins_encode %{
5917 address double_address = __ double_constant($src$$constant);
5918 RelocationHolder rspec = internal_word_Relocation::spec(double_address);
5919 AddressLiteral addrlit(double_address, rspec);
5920
5921 __ sethi(addrlit, $tmp$$Register);
5922 __ ldf(FloatRegisterImpl::D, $tmp$$Register, addrlit.low10(), $dst$$FloatRegister, rspec);
5923 %}
5924 ins_pipe(loadConFD);
5925 %}
5926
5927 // Prefetch instructions.
5928 // Must be safe to execute with invalid address (cannot fault).
5929
5930 instruct prefetchr( memory mem ) %{
5931 match( PrefetchRead mem );
5932 ins_cost(MEMORY_REF_COST);
5933
5934 format %{ "PREFETCH $mem,0\t! Prefetch read-many" %}
5935 opcode(Assembler::prefetch_op3);
5936 ins_encode( form3_mem_prefetch_read( mem ) );
5937 ins_pipe(iload_mem);
5938 %}
5939
5940 instruct prefetchw( memory mem ) %{
5941 match( PrefetchWrite mem );
5942 ins_cost(MEMORY_REF_COST);
5943
5944 format %{ "PREFETCH $mem,2\t! Prefetch write-many (and read)" %}
5945 opcode(Assembler::prefetch_op3);
5946 ins_encode( form3_mem_prefetch_write( mem ) );
5947 ins_pipe(iload_mem);
5948 %}
5949
5950
5951 //----------Store Instructions-------------------------------------------------
5952 // Store Byte
5953 instruct storeB(memory mem, iRegI src) %{
5954 match(Set mem (StoreB mem src));
5955 ins_cost(MEMORY_REF_COST);
5956
5957 size(4);
5958 format %{ "STB $src,$mem\t! byte" %}
5959 opcode(Assembler::stb_op3);
5960 ins_encode(simple_form3_mem_reg( mem, src ) );
5961 ins_pipe(istore_mem_reg);
5962 %}
5963
5964 instruct storeB0(memory mem, immI0 src) %{
5965 match(Set mem (StoreB mem src));
5966 ins_cost(MEMORY_REF_COST);
5967
5968 size(4);
5969 format %{ "STB $src,$mem\t! byte" %}
5970 opcode(Assembler::stb_op3);
5971 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
5972 ins_pipe(istore_mem_zero);
5973 %}
5974
5975 instruct storeCM0(memory mem, immI0 src) %{
5976 match(Set mem (StoreCM mem src));
5977 ins_cost(MEMORY_REF_COST);
5978
5979 size(4);
5980 format %{ "STB $src,$mem\t! CMS card-mark byte 0" %}
5981 opcode(Assembler::stb_op3);
5982 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
5983 ins_pipe(istore_mem_zero);
5984 %}
5985
5986 // Store Char/Short
5987 instruct storeC(memory mem, iRegI src) %{
5988 match(Set mem (StoreC mem src));
5989 ins_cost(MEMORY_REF_COST);
5990
5991 size(4);
5992 format %{ "STH $src,$mem\t! short" %}
5993 opcode(Assembler::sth_op3);
5994 ins_encode(simple_form3_mem_reg( mem, src ) );
5995 ins_pipe(istore_mem_reg);
5996 %}
5997
5998 instruct storeC0(memory mem, immI0 src) %{
5999 match(Set mem (StoreC mem src));
6000 ins_cost(MEMORY_REF_COST);
6001
6002 size(4);
6003 format %{ "STH $src,$mem\t! short" %}
6004 opcode(Assembler::sth_op3);
6005 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6006 ins_pipe(istore_mem_zero);
6007 %}
6008
6009 // Store Integer
6010 instruct storeI(memory mem, iRegI src) %{
6011 match(Set mem (StoreI mem src));
6012 ins_cost(MEMORY_REF_COST);
6013
6014 size(4);
6015 format %{ "STW $src,$mem" %}
6016 opcode(Assembler::stw_op3);
6017 ins_encode(simple_form3_mem_reg( mem, src ) );
6018 ins_pipe(istore_mem_reg);
6019 %}
6020
6021 // Store Long
6022 instruct storeL(memory mem, iRegL src) %{
6023 match(Set mem (StoreL mem src));
6024 ins_cost(MEMORY_REF_COST);
6025 size(4);
6026 format %{ "STX $src,$mem\t! long" %}
6027 opcode(Assembler::stx_op3);
6028 ins_encode(simple_form3_mem_reg( mem, src ) );
6029 ins_pipe(istore_mem_reg);
6030 %}
6031
6032 instruct storeI0(memory mem, immI0 src) %{
6033 match(Set mem (StoreI mem src));
6034 ins_cost(MEMORY_REF_COST);
6035
6036 size(4);
6037 format %{ "STW $src,$mem" %}
6038 opcode(Assembler::stw_op3);
6039 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6040 ins_pipe(istore_mem_zero);
6041 %}
6042
6043 instruct storeL0(memory mem, immL0 src) %{
6044 match(Set mem (StoreL mem src));
6045 ins_cost(MEMORY_REF_COST);
6046
6047 size(4);
6048 format %{ "STX $src,$mem" %}
6049 opcode(Assembler::stx_op3);
6050 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6051 ins_pipe(istore_mem_zero);
6052 %}
6053
6054 // Store Integer from float register (used after fstoi)
6055 instruct storeI_Freg(memory mem, regF src) %{
6056 match(Set mem (StoreI mem src));
6057 ins_cost(MEMORY_REF_COST);
6058
6059 size(4);
6060 format %{ "STF $src,$mem\t! after fstoi/fdtoi" %}
6061 opcode(Assembler::stf_op3);
6062 ins_encode(simple_form3_mem_reg( mem, src ) );
6063 ins_pipe(fstoreF_mem_reg);
6064 %}
6065
6066 // Store Pointer
6067 instruct storeP(memory dst, sp_ptr_RegP src) %{
6068 match(Set dst (StoreP dst src));
6069 ins_cost(MEMORY_REF_COST);
6070 size(4);
6071
6072 #ifndef _LP64
6073 format %{ "STW $src,$dst\t! ptr" %}
6074 opcode(Assembler::stw_op3, 0, REGP_OP);
6075 #else
6076 format %{ "STX $src,$dst\t! ptr" %}
6077 opcode(Assembler::stx_op3, 0, REGP_OP);
6078 #endif
6079 ins_encode( form3_mem_reg( dst, src ) );
6080 ins_pipe(istore_mem_spORreg);
6081 %}
6082
6083 instruct storeP0(memory dst, immP0 src) %{
6084 match(Set dst (StoreP dst src));
6085 ins_cost(MEMORY_REF_COST);
6086 size(4);
6087
6088 #ifndef _LP64
6089 format %{ "STW $src,$dst\t! ptr" %}
6090 opcode(Assembler::stw_op3, 0, REGP_OP);
6091 #else
6092 format %{ "STX $src,$dst\t! ptr" %}
6093 opcode(Assembler::stx_op3, 0, REGP_OP);
6094 #endif
6095 ins_encode( form3_mem_reg( dst, R_G0 ) );
6096 ins_pipe(istore_mem_zero);
6097 %}
6098
6099 // Store Compressed Pointer
6100 instruct storeN(memory dst, iRegN src) %{
6101 match(Set dst (StoreN dst src));
6102 ins_cost(MEMORY_REF_COST);
6103 size(4);
6104
6105 format %{ "STW $src,$dst\t! compressed ptr" %}
6106 ins_encode %{
6107 Register base = as_Register($dst$$base);
6108 Register index = as_Register($dst$$index);
6109 Register src = $src$$Register;
6110 if (index != G0) {
6111 __ stw(src, base, index);
6112 } else {
6113 __ stw(src, base, $dst$$disp);
6114 }
6115 %}
6116 ins_pipe(istore_mem_spORreg);
6117 %}
6118
6119 instruct storeN0(memory dst, immN0 src) %{
6120 match(Set dst (StoreN dst src));
6121 ins_cost(MEMORY_REF_COST);
6122 size(4);
6123
6124 format %{ "STW $src,$dst\t! compressed ptr" %}
6125 ins_encode %{
6126 Register base = as_Register($dst$$base);
6127 Register index = as_Register($dst$$index);
6128 if (index != G0) {
6129 __ stw(0, base, index);
6130 } else {
6131 __ stw(0, base, $dst$$disp);
6132 }
6133 %}
6134 ins_pipe(istore_mem_zero);
6135 %}
6136
6137 // Store Double
6138 instruct storeD( memory mem, regD src) %{
6139 match(Set mem (StoreD mem src));
6140 ins_cost(MEMORY_REF_COST);
6141
6142 size(4);
6143 format %{ "STDF $src,$mem" %}
6144 opcode(Assembler::stdf_op3);
6145 ins_encode(simple_form3_mem_reg( mem, src ) );
6146 ins_pipe(fstoreD_mem_reg);
6147 %}
6148
6149 instruct storeD0( memory mem, immD0 src) %{
6150 match(Set mem (StoreD mem src));
6151 ins_cost(MEMORY_REF_COST);
6152
6153 size(4);
6154 format %{ "STX $src,$mem" %}
6155 opcode(Assembler::stx_op3);
6156 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6157 ins_pipe(fstoreD_mem_zero);
6158 %}
6159
6160 // Store Float
6161 instruct storeF( memory mem, regF src) %{
6162 match(Set mem (StoreF mem src));
6163 ins_cost(MEMORY_REF_COST);
6164
6165 size(4);
6166 format %{ "STF $src,$mem" %}
6167 opcode(Assembler::stf_op3);
6168 ins_encode(simple_form3_mem_reg( mem, src ) );
6169 ins_pipe(fstoreF_mem_reg);
6170 %}
6171
6172 instruct storeF0( memory mem, immF0 src) %{
6173 match(Set mem (StoreF mem src));
6174 ins_cost(MEMORY_REF_COST);
6175
6176 size(4);
6177 format %{ "STW $src,$mem\t! storeF0" %}
6178 opcode(Assembler::stw_op3);
6179 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6180 ins_pipe(fstoreF_mem_zero);
6181 %}
6182
6183 // Store Aligned Packed Bytes in Double register to memory
6184 instruct storeA8B(memory mem, regD src) %{
6185 match(Set mem (Store8B mem src));
6186 ins_cost(MEMORY_REF_COST);
6187 size(4);
6188 format %{ "STDF $src,$mem\t! packed8B" %}
6189 opcode(Assembler::stdf_op3);
6190 ins_encode(simple_form3_mem_reg( mem, src ) );
6191 ins_pipe(fstoreD_mem_reg);
6192 %}
6193
6194 // Convert oop pointer into compressed form
6195 instruct encodeHeapOop(iRegN dst, iRegP src) %{
6196 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
6197 match(Set dst (EncodeP src));
6198 format %{ "encode_heap_oop $src, $dst" %}
6199 ins_encode %{
6200 __ encode_heap_oop($src$$Register, $dst$$Register);
6201 %}
6202 ins_pipe(ialu_reg);
6203 %}
6204
6205 instruct encodeHeapOop_not_null(iRegN dst, iRegP src) %{
6206 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
6207 match(Set dst (EncodeP src));
6208 format %{ "encode_heap_oop_not_null $src, $dst" %}
6209 ins_encode %{
6210 __ encode_heap_oop_not_null($src$$Register, $dst$$Register);
6211 %}
6212 ins_pipe(ialu_reg);
6213 %}
6214
6215 instruct decodeHeapOop(iRegP dst, iRegN src) %{
6216 predicate(n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull &&
6217 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant);
6218 match(Set dst (DecodeN src));
6219 format %{ "decode_heap_oop $src, $dst" %}
6220 ins_encode %{
6221 __ decode_heap_oop($src$$Register, $dst$$Register);
6222 %}
6223 ins_pipe(ialu_reg);
6224 %}
6225
6226 instruct decodeHeapOop_not_null(iRegP dst, iRegN src) %{
6227 predicate(n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull ||
6228 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant);
6229 match(Set dst (DecodeN src));
6230 format %{ "decode_heap_oop_not_null $src, $dst" %}
6231 ins_encode %{
6232 __ decode_heap_oop_not_null($src$$Register, $dst$$Register);
6233 %}
6234 ins_pipe(ialu_reg);
6235 %}
6236
6237
6238 // Store Zero into Aligned Packed Bytes
6239 instruct storeA8B0(memory mem, immI0 zero) %{
6240 match(Set mem (Store8B mem zero));
6241 ins_cost(MEMORY_REF_COST);
6242 size(4);
6243 format %{ "STX $zero,$mem\t! packed8B" %}
6244 opcode(Assembler::stx_op3);
6245 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6246 ins_pipe(fstoreD_mem_zero);
6247 %}
6248
6249 // Store Aligned Packed Chars/Shorts in Double register to memory
6250 instruct storeA4C(memory mem, regD src) %{
6251 match(Set mem (Store4C mem src));
6252 ins_cost(MEMORY_REF_COST);
6253 size(4);
6254 format %{ "STDF $src,$mem\t! packed4C" %}
6255 opcode(Assembler::stdf_op3);
6256 ins_encode(simple_form3_mem_reg( mem, src ) );
6257 ins_pipe(fstoreD_mem_reg);
6258 %}
6259
6260 // Store Zero into Aligned Packed Chars/Shorts
6261 instruct storeA4C0(memory mem, immI0 zero) %{
6262 match(Set mem (Store4C mem (Replicate4C zero)));
6263 ins_cost(MEMORY_REF_COST);
6264 size(4);
6265 format %{ "STX $zero,$mem\t! packed4C" %}
6266 opcode(Assembler::stx_op3);
6267 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6268 ins_pipe(fstoreD_mem_zero);
6269 %}
6270
6271 // Store Aligned Packed Ints in Double register to memory
6272 instruct storeA2I(memory mem, regD src) %{
6273 match(Set mem (Store2I mem src));
6274 ins_cost(MEMORY_REF_COST);
6275 size(4);
6276 format %{ "STDF $src,$mem\t! packed2I" %}
6277 opcode(Assembler::stdf_op3);
6278 ins_encode(simple_form3_mem_reg( mem, src ) );
6279 ins_pipe(fstoreD_mem_reg);
6280 %}
6281
6282 // Store Zero into Aligned Packed Ints
6283 instruct storeA2I0(memory mem, immI0 zero) %{
6284 match(Set mem (Store2I mem zero));
6285 ins_cost(MEMORY_REF_COST);
6286 size(4);
6287 format %{ "STX $zero,$mem\t! packed2I" %}
6288 opcode(Assembler::stx_op3);
6289 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6290 ins_pipe(fstoreD_mem_zero);
6291 %}
6292
6293
6294 //----------MemBar Instructions-----------------------------------------------
6295 // Memory barrier flavors
6296
6297 instruct membar_acquire() %{
6298 match(MemBarAcquire);
6299 ins_cost(4*MEMORY_REF_COST);
6300
6301 size(0);
6302 format %{ "MEMBAR-acquire" %}
6303 ins_encode( enc_membar_acquire );
6304 ins_pipe(long_memory_op);
6305 %}
6306
6307 instruct membar_acquire_lock() %{
6308 match(MemBarAcquire);
6309 predicate(Matcher::prior_fast_lock(n));
6310 ins_cost(0);
6311
6312 size(0);
6313 format %{ "!MEMBAR-acquire (CAS in prior FastLock so empty encoding)" %}
6314 ins_encode( );
6315 ins_pipe(empty);
6316 %}
6317
6318 instruct membar_release() %{
6319 match(MemBarRelease);
6320 ins_cost(4*MEMORY_REF_COST);
6321
6322 size(0);
6323 format %{ "MEMBAR-release" %}
6324 ins_encode( enc_membar_release );
6325 ins_pipe(long_memory_op);
6326 %}
6327
6328 instruct membar_release_lock() %{
6329 match(MemBarRelease);
6330 predicate(Matcher::post_fast_unlock(n));
6331 ins_cost(0);
6332
6333 size(0);
6334 format %{ "!MEMBAR-release (CAS in succeeding FastUnlock so empty encoding)" %}
6335 ins_encode( );
6336 ins_pipe(empty);
6337 %}
6338
6339 instruct membar_volatile() %{
6340 match(MemBarVolatile);
6341 ins_cost(4*MEMORY_REF_COST);
6342
6343 size(4);
6344 format %{ "MEMBAR-volatile" %}
6345 ins_encode( enc_membar_volatile );
6346 ins_pipe(long_memory_op);
6347 %}
6348
6349 instruct unnecessary_membar_volatile() %{
6350 match(MemBarVolatile);
6351 predicate(Matcher::post_store_load_barrier(n));
6352 ins_cost(0);
6353
6354 size(0);
6355 format %{ "!MEMBAR-volatile (unnecessary so empty encoding)" %}
6356 ins_encode( );
6357 ins_pipe(empty);
6358 %}
6359
6360 //----------Register Move Instructions-----------------------------------------
6361 instruct roundDouble_nop(regD dst) %{
6362 match(Set dst (RoundDouble dst));
6363 ins_cost(0);
6364 // SPARC results are already "rounded" (i.e., normal-format IEEE)
6365 ins_encode( );
6366 ins_pipe(empty);
6367 %}
6368
6369
6370 instruct roundFloat_nop(regF dst) %{
6371 match(Set dst (RoundFloat dst));
6372 ins_cost(0);
6373 // SPARC results are already "rounded" (i.e., normal-format IEEE)
6374 ins_encode( );
6375 ins_pipe(empty);
6376 %}
6377
6378
6379 // Cast Index to Pointer for unsafe natives
6380 instruct castX2P(iRegX src, iRegP dst) %{
6381 match(Set dst (CastX2P src));
6382
6383 format %{ "MOV $src,$dst\t! IntX->Ptr" %}
6384 ins_encode( form3_g0_rs2_rd_move( src, dst ) );
6385 ins_pipe(ialu_reg);
6386 %}
6387
6388 // Cast Pointer to Index for unsafe natives
6389 instruct castP2X(iRegP src, iRegX dst) %{
6390 match(Set dst (CastP2X src));
6391
6392 format %{ "MOV $src,$dst\t! Ptr->IntX" %}
6393 ins_encode( form3_g0_rs2_rd_move( src, dst ) );
6394 ins_pipe(ialu_reg);
6395 %}
6396
6397 instruct stfSSD(stackSlotD stkSlot, regD src) %{
6398 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6399 match(Set stkSlot src); // chain rule
6400 ins_cost(MEMORY_REF_COST);
6401 format %{ "STDF $src,$stkSlot\t!stk" %}
6402 opcode(Assembler::stdf_op3);
6403 ins_encode(simple_form3_mem_reg(stkSlot, src));
6404 ins_pipe(fstoreD_stk_reg);
6405 %}
6406
6407 instruct ldfSSD(regD dst, stackSlotD stkSlot) %{
6408 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6409 match(Set dst stkSlot); // chain rule
6410 ins_cost(MEMORY_REF_COST);
6411 format %{ "LDDF $stkSlot,$dst\t!stk" %}
6412 opcode(Assembler::lddf_op3);
6413 ins_encode(simple_form3_mem_reg(stkSlot, dst));
6414 ins_pipe(floadD_stk);
6415 %}
6416
6417 instruct stfSSF(stackSlotF stkSlot, regF src) %{
6418 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6419 match(Set stkSlot src); // chain rule
6420 ins_cost(MEMORY_REF_COST);
6421 format %{ "STF $src,$stkSlot\t!stk" %}
6422 opcode(Assembler::stf_op3);
6423 ins_encode(simple_form3_mem_reg(stkSlot, src));
6424 ins_pipe(fstoreF_stk_reg);
6425 %}
6426
6427 //----------Conditional Move---------------------------------------------------
6428 // Conditional move
6429 instruct cmovIP_reg(cmpOpP cmp, flagsRegP pcc, iRegI dst, iRegI src) %{
6430 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src)));
6431 ins_cost(150);
6432 format %{ "MOV$cmp $pcc,$src,$dst" %}
6433 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6434 ins_pipe(ialu_reg);
6435 %}
6436
6437 instruct cmovIP_imm(cmpOpP cmp, flagsRegP pcc, iRegI dst, immI11 src) %{
6438 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src)));
6439 ins_cost(140);
6440 format %{ "MOV$cmp $pcc,$src,$dst" %}
6441 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
6442 ins_pipe(ialu_imm);
6443 %}
6444
6445 instruct cmovII_reg(cmpOp cmp, flagsReg icc, iRegI dst, iRegI src) %{
6446 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6447 ins_cost(150);
6448 size(4);
6449 format %{ "MOV$cmp $icc,$src,$dst" %}
6450 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6451 ins_pipe(ialu_reg);
6452 %}
6453
6454 instruct cmovII_imm(cmpOp cmp, flagsReg icc, iRegI dst, immI11 src) %{
6455 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6456 ins_cost(140);
6457 size(4);
6458 format %{ "MOV$cmp $icc,$src,$dst" %}
6459 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6460 ins_pipe(ialu_imm);
6461 %}
6462
6463 instruct cmovII_U_reg(cmpOpU cmp, flagsRegU icc, iRegI dst, iRegI src) %{
6464 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6465 ins_cost(150);
6466 size(4);
6467 format %{ "MOV$cmp $icc,$src,$dst" %}
6468 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6469 ins_pipe(ialu_reg);
6470 %}
6471
6472 instruct cmovII_U_imm(cmpOpU cmp, flagsRegU icc, iRegI dst, immI11 src) %{
6473 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6474 ins_cost(140);
6475 size(4);
6476 format %{ "MOV$cmp $icc,$src,$dst" %}
6477 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6478 ins_pipe(ialu_imm);
6479 %}
6480
6481 instruct cmovIF_reg(cmpOpF cmp, flagsRegF fcc, iRegI dst, iRegI src) %{
6482 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src)));
6483 ins_cost(150);
6484 size(4);
6485 format %{ "MOV$cmp $fcc,$src,$dst" %}
6486 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6487 ins_pipe(ialu_reg);
6488 %}
6489
6490 instruct cmovIF_imm(cmpOpF cmp, flagsRegF fcc, iRegI dst, immI11 src) %{
6491 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src)));
6492 ins_cost(140);
6493 size(4);
6494 format %{ "MOV$cmp $fcc,$src,$dst" %}
6495 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) );
6496 ins_pipe(ialu_imm);
6497 %}
6498
6499 // Conditional move for RegN. Only cmov(reg,reg).
6500 instruct cmovNP_reg(cmpOpP cmp, flagsRegP pcc, iRegN dst, iRegN src) %{
6501 match(Set dst (CMoveN (Binary cmp pcc) (Binary dst src)));
6502 ins_cost(150);
6503 format %{ "MOV$cmp $pcc,$src,$dst" %}
6504 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6505 ins_pipe(ialu_reg);
6506 %}
6507
6508 // This instruction also works with CmpN so we don't need cmovNN_reg.
6509 instruct cmovNI_reg(cmpOp cmp, flagsReg icc, iRegN dst, iRegN src) %{
6510 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src)));
6511 ins_cost(150);
6512 size(4);
6513 format %{ "MOV$cmp $icc,$src,$dst" %}
6514 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6515 ins_pipe(ialu_reg);
6516 %}
6517
6518 instruct cmovNF_reg(cmpOpF cmp, flagsRegF fcc, iRegN dst, iRegN src) %{
6519 match(Set dst (CMoveN (Binary cmp fcc) (Binary dst src)));
6520 ins_cost(150);
6521 size(4);
6522 format %{ "MOV$cmp $fcc,$src,$dst" %}
6523 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6524 ins_pipe(ialu_reg);
6525 %}
6526
6527 // Conditional move
6528 instruct cmovPP_reg(cmpOpP cmp, flagsRegP pcc, iRegP dst, iRegP src) %{
6529 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src)));
6530 ins_cost(150);
6531 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %}
6532 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6533 ins_pipe(ialu_reg);
6534 %}
6535
6536 instruct cmovPP_imm(cmpOpP cmp, flagsRegP pcc, iRegP dst, immP0 src) %{
6537 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src)));
6538 ins_cost(140);
6539 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %}
6540 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
6541 ins_pipe(ialu_imm);
6542 %}
6543
6544 // This instruction also works with CmpN so we don't need cmovPN_reg.
6545 instruct cmovPI_reg(cmpOp cmp, flagsReg icc, iRegP dst, iRegP src) %{
6546 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6547 ins_cost(150);
6548
6549 size(4);
6550 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6551 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6552 ins_pipe(ialu_reg);
6553 %}
6554
6555 instruct cmovPI_imm(cmpOp cmp, flagsReg icc, iRegP dst, immP0 src) %{
6556 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6557 ins_cost(140);
6558
6559 size(4);
6560 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6561 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6562 ins_pipe(ialu_imm);
6563 %}
6564
6565 instruct cmovPF_reg(cmpOpF cmp, flagsRegF fcc, iRegP dst, iRegP src) %{
6566 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src)));
6567 ins_cost(150);
6568 size(4);
6569 format %{ "MOV$cmp $fcc,$src,$dst" %}
6570 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6571 ins_pipe(ialu_imm);
6572 %}
6573
6574 instruct cmovPF_imm(cmpOpF cmp, flagsRegF fcc, iRegP dst, immP0 src) %{
6575 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src)));
6576 ins_cost(140);
6577 size(4);
6578 format %{ "MOV$cmp $fcc,$src,$dst" %}
6579 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) );
6580 ins_pipe(ialu_imm);
6581 %}
6582
6583 // Conditional move
6584 instruct cmovFP_reg(cmpOpP cmp, flagsRegP pcc, regF dst, regF src) %{
6585 match(Set dst (CMoveF (Binary cmp pcc) (Binary dst src)));
6586 ins_cost(150);
6587 opcode(0x101);
6588 format %{ "FMOVD$cmp $pcc,$src,$dst" %}
6589 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6590 ins_pipe(int_conditional_float_move);
6591 %}
6592
6593 instruct cmovFI_reg(cmpOp cmp, flagsReg icc, regF dst, regF src) %{
6594 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src)));
6595 ins_cost(150);
6596
6597 size(4);
6598 format %{ "FMOVS$cmp $icc,$src,$dst" %}
6599 opcode(0x101);
6600 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6601 ins_pipe(int_conditional_float_move);
6602 %}
6603
6604 // Conditional move,
6605 instruct cmovFF_reg(cmpOpF cmp, flagsRegF fcc, regF dst, regF src) %{
6606 match(Set dst (CMoveF (Binary cmp fcc) (Binary dst src)));
6607 ins_cost(150);
6608 size(4);
6609 format %{ "FMOVF$cmp $fcc,$src,$dst" %}
6610 opcode(0x1);
6611 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) );
6612 ins_pipe(int_conditional_double_move);
6613 %}
6614
6615 // Conditional move
6616 instruct cmovDP_reg(cmpOpP cmp, flagsRegP pcc, regD dst, regD src) %{
6617 match(Set dst (CMoveD (Binary cmp pcc) (Binary dst src)));
6618 ins_cost(150);
6619 size(4);
6620 opcode(0x102);
6621 format %{ "FMOVD$cmp $pcc,$src,$dst" %}
6622 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6623 ins_pipe(int_conditional_double_move);
6624 %}
6625
6626 instruct cmovDI_reg(cmpOp cmp, flagsReg icc, regD dst, regD src) %{
6627 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src)));
6628 ins_cost(150);
6629
6630 size(4);
6631 format %{ "FMOVD$cmp $icc,$src,$dst" %}
6632 opcode(0x102);
6633 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6634 ins_pipe(int_conditional_double_move);
6635 %}
6636
6637 // Conditional move,
6638 instruct cmovDF_reg(cmpOpF cmp, flagsRegF fcc, regD dst, regD src) %{
6639 match(Set dst (CMoveD (Binary cmp fcc) (Binary dst src)));
6640 ins_cost(150);
6641 size(4);
6642 format %{ "FMOVD$cmp $fcc,$src,$dst" %}
6643 opcode(0x2);
6644 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) );
6645 ins_pipe(int_conditional_double_move);
6646 %}
6647
6648 // Conditional move
6649 instruct cmovLP_reg(cmpOpP cmp, flagsRegP pcc, iRegL dst, iRegL src) %{
6650 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src)));
6651 ins_cost(150);
6652 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %}
6653 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6654 ins_pipe(ialu_reg);
6655 %}
6656
6657 instruct cmovLP_imm(cmpOpP cmp, flagsRegP pcc, iRegL dst, immI11 src) %{
6658 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src)));
6659 ins_cost(140);
6660 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %}
6661 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
6662 ins_pipe(ialu_imm);
6663 %}
6664
6665 instruct cmovLI_reg(cmpOp cmp, flagsReg icc, iRegL dst, iRegL src) %{
6666 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src)));
6667 ins_cost(150);
6668
6669 size(4);
6670 format %{ "MOV$cmp $icc,$src,$dst\t! long" %}
6671 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6672 ins_pipe(ialu_reg);
6673 %}
6674
6675
6676 instruct cmovLF_reg(cmpOpF cmp, flagsRegF fcc, iRegL dst, iRegL src) %{
6677 match(Set dst (CMoveL (Binary cmp fcc) (Binary dst src)));
6678 ins_cost(150);
6679
6680 size(4);
6681 format %{ "MOV$cmp $fcc,$src,$dst\t! long" %}
6682 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6683 ins_pipe(ialu_reg);
6684 %}
6685
6686
6687
6688 //----------OS and Locking Instructions----------------------------------------
6689
6690 // This name is KNOWN by the ADLC and cannot be changed.
6691 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
6692 // for this guy.
6693 instruct tlsLoadP(g2RegP dst) %{
6694 match(Set dst (ThreadLocal));
6695
6696 size(0);
6697 ins_cost(0);
6698 format %{ "# TLS is in G2" %}
6699 ins_encode( /*empty encoding*/ );
6700 ins_pipe(ialu_none);
6701 %}
6702
6703 instruct checkCastPP( iRegP dst ) %{
6704 match(Set dst (CheckCastPP dst));
6705
6706 size(0);
6707 format %{ "# checkcastPP of $dst" %}
6708 ins_encode( /*empty encoding*/ );
6709 ins_pipe(empty);
6710 %}
6711
6712
6713 instruct castPP( iRegP dst ) %{
6714 match(Set dst (CastPP dst));
6715 format %{ "# castPP of $dst" %}
6716 ins_encode( /*empty encoding*/ );
6717 ins_pipe(empty);
6718 %}
6719
6720 instruct castII( iRegI dst ) %{
6721 match(Set dst (CastII dst));
6722 format %{ "# castII of $dst" %}
6723 ins_encode( /*empty encoding*/ );
6724 ins_cost(0);
6725 ins_pipe(empty);
6726 %}
6727
6728 //----------Arithmetic Instructions--------------------------------------------
6729 // Addition Instructions
6730 // Register Addition
6731 instruct addI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
6732 match(Set dst (AddI src1 src2));
6733
6734 size(4);
6735 format %{ "ADD $src1,$src2,$dst" %}
6736 ins_encode %{
6737 __ add($src1$$Register, $src2$$Register, $dst$$Register);
6738 %}
6739 ins_pipe(ialu_reg_reg);
6740 %}
6741
6742 // Immediate Addition
6743 instruct addI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
6744 match(Set dst (AddI src1 src2));
6745
6746 size(4);
6747 format %{ "ADD $src1,$src2,$dst" %}
6748 opcode(Assembler::add_op3, Assembler::arith_op);
6749 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
6750 ins_pipe(ialu_reg_imm);
6751 %}
6752
6753 // Pointer Register Addition
6754 instruct addP_reg_reg(iRegP dst, iRegP src1, iRegX src2) %{
6755 match(Set dst (AddP src1 src2));
6756
6757 size(4);
6758 format %{ "ADD $src1,$src2,$dst" %}
6759 opcode(Assembler::add_op3, Assembler::arith_op);
6760 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
6761 ins_pipe(ialu_reg_reg);
6762 %}
6763
6764 // Pointer Immediate Addition
6765 instruct addP_reg_imm13(iRegP dst, iRegP src1, immX13 src2) %{
6766 match(Set dst (AddP src1 src2));
6767
6768 size(4);
6769 format %{ "ADD $src1,$src2,$dst" %}
6770 opcode(Assembler::add_op3, Assembler::arith_op);
6771 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
6772 ins_pipe(ialu_reg_imm);
6773 %}
6774
6775 // Long Addition
6776 instruct addL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
6777 match(Set dst (AddL src1 src2));
6778
6779 size(4);
6780 format %{ "ADD $src1,$src2,$dst\t! long" %}
6781 opcode(Assembler::add_op3, Assembler::arith_op);
6782 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
6783 ins_pipe(ialu_reg_reg);
6784 %}
6785
6786 instruct addL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
6787 match(Set dst (AddL src1 con));
6788
6789 size(4);
6790 format %{ "ADD $src1,$con,$dst" %}
6791 opcode(Assembler::add_op3, Assembler::arith_op);
6792 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
6793 ins_pipe(ialu_reg_imm);
6794 %}
6795
6796 //----------Conditional_store--------------------------------------------------
6797 // Conditional-store of the updated heap-top.
6798 // Used during allocation of the shared heap.
6799 // Sets flags (EQ) on success. Implemented with a CASA on Sparc.
6800
6801 // LoadP-locked. Same as a regular pointer load when used with a compare-swap
6802 instruct loadPLocked(iRegP dst, memory mem) %{
6803 match(Set dst (LoadPLocked mem));
6804 ins_cost(MEMORY_REF_COST);
6805
6806 #ifndef _LP64
6807 size(4);
6808 format %{ "LDUW $mem,$dst\t! ptr" %}
6809 opcode(Assembler::lduw_op3, 0, REGP_OP);
6810 #else
6811 format %{ "LDX $mem,$dst\t! ptr" %}
6812 opcode(Assembler::ldx_op3, 0, REGP_OP);
6813 #endif
6814 ins_encode( form3_mem_reg( mem, dst ) );
6815 ins_pipe(iload_mem);
6816 %}
6817
6818 // LoadL-locked. Same as a regular long load when used with a compare-swap
6819 instruct loadLLocked(iRegL dst, memory mem) %{
6820 match(Set dst (LoadLLocked mem));
6821 ins_cost(MEMORY_REF_COST);
6822 size(4);
6823 format %{ "LDX $mem,$dst\t! long" %}
6824 opcode(Assembler::ldx_op3);
6825 ins_encode(simple_form3_mem_reg( mem, dst ) );
6826 ins_pipe(iload_mem);
6827 %}
6828
6829 instruct storePConditional( iRegP heap_top_ptr, iRegP oldval, g3RegP newval, flagsRegP pcc ) %{
6830 match(Set pcc (StorePConditional heap_top_ptr (Binary oldval newval)));
6831 effect( KILL newval );
6832 format %{ "CASA [$heap_top_ptr],$oldval,R_G3\t! If $oldval==[$heap_top_ptr] Then store R_G3 into [$heap_top_ptr], set R_G3=[$heap_top_ptr] in any case\n\t"
6833 "CMP R_G3,$oldval\t\t! See if we made progress" %}
6834 ins_encode( enc_cas(heap_top_ptr,oldval,newval) );
6835 ins_pipe( long_memory_op );
6836 %}
6837
6838 // Conditional-store of an int value.
6839 instruct storeIConditional( iRegP mem_ptr, iRegI oldval, g3RegI newval, flagsReg icc ) %{
6840 match(Set icc (StoreIConditional mem_ptr (Binary oldval newval)));
6841 effect( KILL newval );
6842 format %{ "CASA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t"
6843 "CMP $oldval,$newval\t\t! See if we made progress" %}
6844 ins_encode( enc_cas(mem_ptr,oldval,newval) );
6845 ins_pipe( long_memory_op );
6846 %}
6847
6848 // Conditional-store of a long value.
6849 instruct storeLConditional( iRegP mem_ptr, iRegL oldval, g3RegL newval, flagsRegL xcc ) %{
6850 match(Set xcc (StoreLConditional mem_ptr (Binary oldval newval)));
6851 effect( KILL newval );
6852 format %{ "CASXA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t"
6853 "CMP $oldval,$newval\t\t! See if we made progress" %}
6854 ins_encode( enc_cas(mem_ptr,oldval,newval) );
6855 ins_pipe( long_memory_op );
6856 %}
6857
6858 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
6859
6860 instruct compareAndSwapL_bool(iRegP mem_ptr, iRegL oldval, iRegL newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
6861 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
6862 effect( USE mem_ptr, KILL ccr, KILL tmp1);
6863 format %{
6864 "MOV $newval,O7\n\t"
6865 "CASXA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
6866 "CMP $oldval,O7\t\t! See if we made progress\n\t"
6867 "MOV 1,$res\n\t"
6868 "MOVne xcc,R_G0,$res"
6869 %}
6870 ins_encode( enc_casx(mem_ptr, oldval, newval),
6871 enc_lflags_ne_to_boolean(res) );
6872 ins_pipe( long_memory_op );
6873 %}
6874
6875
6876 instruct compareAndSwapI_bool(iRegP mem_ptr, iRegI oldval, iRegI newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
6877 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
6878 effect( USE mem_ptr, KILL ccr, KILL tmp1);
6879 format %{
6880 "MOV $newval,O7\n\t"
6881 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
6882 "CMP $oldval,O7\t\t! See if we made progress\n\t"
6883 "MOV 1,$res\n\t"
6884 "MOVne icc,R_G0,$res"
6885 %}
6886 ins_encode( enc_casi(mem_ptr, oldval, newval),
6887 enc_iflags_ne_to_boolean(res) );
6888 ins_pipe( long_memory_op );
6889 %}
6890
6891 instruct compareAndSwapP_bool(iRegP mem_ptr, iRegP oldval, iRegP newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
6892 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
6893 effect( USE mem_ptr, KILL ccr, KILL tmp1);
6894 format %{
6895 "MOV $newval,O7\n\t"
6896 "CASA_PTR [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
6897 "CMP $oldval,O7\t\t! See if we made progress\n\t"
6898 "MOV 1,$res\n\t"
6899 "MOVne xcc,R_G0,$res"
6900 %}
6901 #ifdef _LP64
6902 ins_encode( enc_casx(mem_ptr, oldval, newval),
6903 enc_lflags_ne_to_boolean(res) );
6904 #else
6905 ins_encode( enc_casi(mem_ptr, oldval, newval),
6906 enc_iflags_ne_to_boolean(res) );
6907 #endif
6908 ins_pipe( long_memory_op );
6909 %}
6910
6911 instruct compareAndSwapN_bool(iRegP mem_ptr, iRegN oldval, iRegN newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
6912 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval)));
6913 effect( USE mem_ptr, KILL ccr, KILL tmp1);
6914 format %{
6915 "MOV $newval,O7\n\t"
6916 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
6917 "CMP $oldval,O7\t\t! See if we made progress\n\t"
6918 "MOV 1,$res\n\t"
6919 "MOVne icc,R_G0,$res"
6920 %}
6921 ins_encode( enc_casi(mem_ptr, oldval, newval),
6922 enc_iflags_ne_to_boolean(res) );
6923 ins_pipe( long_memory_op );
6924 %}
6925
6926 //---------------------
6927 // Subtraction Instructions
6928 // Register Subtraction
6929 instruct subI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
6930 match(Set dst (SubI src1 src2));
6931
6932 size(4);
6933 format %{ "SUB $src1,$src2,$dst" %}
6934 opcode(Assembler::sub_op3, Assembler::arith_op);
6935 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
6936 ins_pipe(ialu_reg_reg);
6937 %}
6938
6939 // Immediate Subtraction
6940 instruct subI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
6941 match(Set dst (SubI src1 src2));
6942
6943 size(4);
6944 format %{ "SUB $src1,$src2,$dst" %}
6945 opcode(Assembler::sub_op3, Assembler::arith_op);
6946 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
6947 ins_pipe(ialu_reg_imm);
6948 %}
6949
6950 instruct subI_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{
6951 match(Set dst (SubI zero src2));
6952
6953 size(4);
6954 format %{ "NEG $src2,$dst" %}
6955 opcode(Assembler::sub_op3, Assembler::arith_op);
6956 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) );
6957 ins_pipe(ialu_zero_reg);
6958 %}
6959
6960 // Long subtraction
6961 instruct subL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
6962 match(Set dst (SubL src1 src2));
6963
6964 size(4);
6965 format %{ "SUB $src1,$src2,$dst\t! long" %}
6966 opcode(Assembler::sub_op3, Assembler::arith_op);
6967 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
6968 ins_pipe(ialu_reg_reg);
6969 %}
6970
6971 // Immediate Subtraction
6972 instruct subL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
6973 match(Set dst (SubL src1 con));
6974
6975 size(4);
6976 format %{ "SUB $src1,$con,$dst\t! long" %}
6977 opcode(Assembler::sub_op3, Assembler::arith_op);
6978 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
6979 ins_pipe(ialu_reg_imm);
6980 %}
6981
6982 // Long negation
6983 instruct negL_reg_reg(iRegL dst, immL0 zero, iRegL src2) %{
6984 match(Set dst (SubL zero src2));
6985
6986 size(4);
6987 format %{ "NEG $src2,$dst\t! long" %}
6988 opcode(Assembler::sub_op3, Assembler::arith_op);
6989 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) );
6990 ins_pipe(ialu_zero_reg);
6991 %}
6992
6993 // Multiplication Instructions
6994 // Integer Multiplication
6995 // Register Multiplication
6996 instruct mulI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
6997 match(Set dst (MulI src1 src2));
6998
6999 size(4);
7000 format %{ "MULX $src1,$src2,$dst" %}
7001 opcode(Assembler::mulx_op3, Assembler::arith_op);
7002 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7003 ins_pipe(imul_reg_reg);
7004 %}
7005
7006 // Immediate Multiplication
7007 instruct mulI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7008 match(Set dst (MulI src1 src2));
7009
7010 size(4);
7011 format %{ "MULX $src1,$src2,$dst" %}
7012 opcode(Assembler::mulx_op3, Assembler::arith_op);
7013 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7014 ins_pipe(imul_reg_imm);
7015 %}
7016
7017 instruct mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7018 match(Set dst (MulL src1 src2));
7019 ins_cost(DEFAULT_COST * 5);
7020 size(4);
7021 format %{ "MULX $src1,$src2,$dst\t! long" %}
7022 opcode(Assembler::mulx_op3, Assembler::arith_op);
7023 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7024 ins_pipe(mulL_reg_reg);
7025 %}
7026
7027 // Immediate Multiplication
7028 instruct mulL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7029 match(Set dst (MulL src1 src2));
7030 ins_cost(DEFAULT_COST * 5);
7031 size(4);
7032 format %{ "MULX $src1,$src2,$dst" %}
7033 opcode(Assembler::mulx_op3, Assembler::arith_op);
7034 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7035 ins_pipe(mulL_reg_imm);
7036 %}
7037
7038 // Integer Division
7039 // Register Division
7040 instruct divI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2) %{
7041 match(Set dst (DivI src1 src2));
7042 ins_cost((2+71)*DEFAULT_COST);
7043
7044 format %{ "SRA $src2,0,$src2\n\t"
7045 "SRA $src1,0,$src1\n\t"
7046 "SDIVX $src1,$src2,$dst" %}
7047 ins_encode( idiv_reg( src1, src2, dst ) );
7048 ins_pipe(sdiv_reg_reg);
7049 %}
7050
7051 // Immediate Division
7052 instruct divI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2) %{
7053 match(Set dst (DivI src1 src2));
7054 ins_cost((2+71)*DEFAULT_COST);
7055
7056 format %{ "SRA $src1,0,$src1\n\t"
7057 "SDIVX $src1,$src2,$dst" %}
7058 ins_encode( idiv_imm( src1, src2, dst ) );
7059 ins_pipe(sdiv_reg_imm);
7060 %}
7061
7062 //----------Div-By-10-Expansion------------------------------------------------
7063 // Extract hi bits of a 32x32->64 bit multiply.
7064 // Expand rule only, not matched
7065 instruct mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2 ) %{
7066 effect( DEF dst, USE src1, USE src2 );
7067 format %{ "MULX $src1,$src2,$dst\t! Used in div-by-10\n\t"
7068 "SRLX $dst,#32,$dst\t\t! Extract only hi word of result" %}
7069 ins_encode( enc_mul_hi(dst,src1,src2));
7070 ins_pipe(sdiv_reg_reg);
7071 %}
7072
7073 // Magic constant, reciprocal of 10
7074 instruct loadConI_x66666667(iRegIsafe dst) %{
7075 effect( DEF dst );
7076
7077 size(8);
7078 format %{ "SET 0x66666667,$dst\t! Used in div-by-10" %}
7079 ins_encode( Set32(0x66666667, dst) );
7080 ins_pipe(ialu_hi_lo_reg);
7081 %}
7082
7083 // Register Shift Right Arithmetic Long by 32-63
7084 instruct sra_31( iRegI dst, iRegI src ) %{
7085 effect( DEF dst, USE src );
7086 format %{ "SRA $src,31,$dst\t! Used in div-by-10" %}
7087 ins_encode( form3_rs1_rd_copysign_hi(src,dst) );
7088 ins_pipe(ialu_reg_reg);
7089 %}
7090
7091 // Arithmetic Shift Right by 8-bit immediate
7092 instruct sra_reg_2( iRegI dst, iRegI src ) %{
7093 effect( DEF dst, USE src );
7094 format %{ "SRA $src,2,$dst\t! Used in div-by-10" %}
7095 opcode(Assembler::sra_op3, Assembler::arith_op);
7096 ins_encode( form3_rs1_simm13_rd( src, 0x2, dst ) );
7097 ins_pipe(ialu_reg_imm);
7098 %}
7099
7100 // Integer DIV with 10
7101 instruct divI_10( iRegI dst, iRegIsafe src, immI10 div ) %{
7102 match(Set dst (DivI src div));
7103 ins_cost((6+6)*DEFAULT_COST);
7104 expand %{
7105 iRegIsafe tmp1; // Killed temps;
7106 iRegIsafe tmp2; // Killed temps;
7107 iRegI tmp3; // Killed temps;
7108 iRegI tmp4; // Killed temps;
7109 loadConI_x66666667( tmp1 ); // SET 0x66666667 -> tmp1
7110 mul_hi( tmp2, src, tmp1 ); // MUL hibits(src * tmp1) -> tmp2
7111 sra_31( tmp3, src ); // SRA src,31 -> tmp3
7112 sra_reg_2( tmp4, tmp2 ); // SRA tmp2,2 -> tmp4
7113 subI_reg_reg( dst,tmp4,tmp3); // SUB tmp4 - tmp3 -> dst
7114 %}
7115 %}
7116
7117 // Register Long Division
7118 instruct divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7119 match(Set dst (DivL src1 src2));
7120 ins_cost(DEFAULT_COST*71);
7121 size(4);
7122 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7123 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7124 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7125 ins_pipe(divL_reg_reg);
7126 %}
7127
7128 // Register Long Division
7129 instruct divL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7130 match(Set dst (DivL src1 src2));
7131 ins_cost(DEFAULT_COST*71);
7132 size(4);
7133 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7134 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7135 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7136 ins_pipe(divL_reg_imm);
7137 %}
7138
7139 // Integer Remainder
7140 // Register Remainder
7141 instruct modI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2, o7RegP temp, flagsReg ccr ) %{
7142 match(Set dst (ModI src1 src2));
7143 effect( KILL ccr, KILL temp);
7144
7145 format %{ "SREM $src1,$src2,$dst" %}
7146 ins_encode( irem_reg(src1, src2, dst, temp) );
7147 ins_pipe(sdiv_reg_reg);
7148 %}
7149
7150 // Immediate Remainder
7151 instruct modI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2, o7RegP temp, flagsReg ccr ) %{
7152 match(Set dst (ModI src1 src2));
7153 effect( KILL ccr, KILL temp);
7154
7155 format %{ "SREM $src1,$src2,$dst" %}
7156 ins_encode( irem_imm(src1, src2, dst, temp) );
7157 ins_pipe(sdiv_reg_imm);
7158 %}
7159
7160 // Register Long Remainder
7161 instruct divL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7162 effect(DEF dst, USE src1, USE src2);
7163 size(4);
7164 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7165 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7166 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7167 ins_pipe(divL_reg_reg);
7168 %}
7169
7170 // Register Long Division
7171 instruct divL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{
7172 effect(DEF dst, USE src1, USE src2);
7173 size(4);
7174 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7175 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7176 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7177 ins_pipe(divL_reg_imm);
7178 %}
7179
7180 instruct mulL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7181 effect(DEF dst, USE src1, USE src2);
7182 size(4);
7183 format %{ "MULX $src1,$src2,$dst\t! long" %}
7184 opcode(Assembler::mulx_op3, Assembler::arith_op);
7185 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7186 ins_pipe(mulL_reg_reg);
7187 %}
7188
7189 // Immediate Multiplication
7190 instruct mulL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{
7191 effect(DEF dst, USE src1, USE src2);
7192 size(4);
7193 format %{ "MULX $src1,$src2,$dst" %}
7194 opcode(Assembler::mulx_op3, Assembler::arith_op);
7195 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7196 ins_pipe(mulL_reg_imm);
7197 %}
7198
7199 instruct subL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7200 effect(DEF dst, USE src1, USE src2);
7201 size(4);
7202 format %{ "SUB $src1,$src2,$dst\t! long" %}
7203 opcode(Assembler::sub_op3, Assembler::arith_op);
7204 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7205 ins_pipe(ialu_reg_reg);
7206 %}
7207
7208 instruct subL_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{
7209 effect(DEF dst, USE src1, USE src2);
7210 size(4);
7211 format %{ "SUB $src1,$src2,$dst\t! long" %}
7212 opcode(Assembler::sub_op3, Assembler::arith_op);
7213 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7214 ins_pipe(ialu_reg_reg);
7215 %}
7216
7217 // Register Long Remainder
7218 instruct modL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7219 match(Set dst (ModL src1 src2));
7220 ins_cost(DEFAULT_COST*(71 + 6 + 1));
7221 expand %{
7222 iRegL tmp1;
7223 iRegL tmp2;
7224 divL_reg_reg_1(tmp1, src1, src2);
7225 mulL_reg_reg_1(tmp2, tmp1, src2);
7226 subL_reg_reg_1(dst, src1, tmp2);
7227 %}
7228 %}
7229
7230 // Register Long Remainder
7231 instruct modL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7232 match(Set dst (ModL src1 src2));
7233 ins_cost(DEFAULT_COST*(71 + 6 + 1));
7234 expand %{
7235 iRegL tmp1;
7236 iRegL tmp2;
7237 divL_reg_imm13_1(tmp1, src1, src2);
7238 mulL_reg_imm13_1(tmp2, tmp1, src2);
7239 subL_reg_reg_2 (dst, src1, tmp2);
7240 %}
7241 %}
7242
7243 // Integer Shift Instructions
7244 // Register Shift Left
7245 instruct shlI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7246 match(Set dst (LShiftI src1 src2));
7247
7248 size(4);
7249 format %{ "SLL $src1,$src2,$dst" %}
7250 opcode(Assembler::sll_op3, Assembler::arith_op);
7251 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7252 ins_pipe(ialu_reg_reg);
7253 %}
7254
7255 // Register Shift Left Immediate
7256 instruct shlI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7257 match(Set dst (LShiftI src1 src2));
7258
7259 size(4);
7260 format %{ "SLL $src1,$src2,$dst" %}
7261 opcode(Assembler::sll_op3, Assembler::arith_op);
7262 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7263 ins_pipe(ialu_reg_imm);
7264 %}
7265
7266 // Register Shift Left
7267 instruct shlL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7268 match(Set dst (LShiftL src1 src2));
7269
7270 size(4);
7271 format %{ "SLLX $src1,$src2,$dst" %}
7272 opcode(Assembler::sllx_op3, Assembler::arith_op);
7273 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7274 ins_pipe(ialu_reg_reg);
7275 %}
7276
7277 // Register Shift Left Immediate
7278 instruct shlL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7279 match(Set dst (LShiftL src1 src2));
7280
7281 size(4);
7282 format %{ "SLLX $src1,$src2,$dst" %}
7283 opcode(Assembler::sllx_op3, Assembler::arith_op);
7284 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7285 ins_pipe(ialu_reg_imm);
7286 %}
7287
7288 // Register Arithmetic Shift Right
7289 instruct sarI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7290 match(Set dst (RShiftI src1 src2));
7291 size(4);
7292 format %{ "SRA $src1,$src2,$dst" %}
7293 opcode(Assembler::sra_op3, Assembler::arith_op);
7294 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7295 ins_pipe(ialu_reg_reg);
7296 %}
7297
7298 // Register Arithmetic Shift Right Immediate
7299 instruct sarI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7300 match(Set dst (RShiftI src1 src2));
7301
7302 size(4);
7303 format %{ "SRA $src1,$src2,$dst" %}
7304 opcode(Assembler::sra_op3, Assembler::arith_op);
7305 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7306 ins_pipe(ialu_reg_imm);
7307 %}
7308
7309 // Register Shift Right Arithmatic Long
7310 instruct sarL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7311 match(Set dst (RShiftL src1 src2));
7312
7313 size(4);
7314 format %{ "SRAX $src1,$src2,$dst" %}
7315 opcode(Assembler::srax_op3, Assembler::arith_op);
7316 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7317 ins_pipe(ialu_reg_reg);
7318 %}
7319
7320 // Register Shift Left Immediate
7321 instruct sarL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7322 match(Set dst (RShiftL src1 src2));
7323
7324 size(4);
7325 format %{ "SRAX $src1,$src2,$dst" %}
7326 opcode(Assembler::srax_op3, Assembler::arith_op);
7327 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7328 ins_pipe(ialu_reg_imm);
7329 %}
7330
7331 // Register Shift Right
7332 instruct shrI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7333 match(Set dst (URShiftI src1 src2));
7334
7335 size(4);
7336 format %{ "SRL $src1,$src2,$dst" %}
7337 opcode(Assembler::srl_op3, Assembler::arith_op);
7338 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7339 ins_pipe(ialu_reg_reg);
7340 %}
7341
7342 // Register Shift Right Immediate
7343 instruct shrI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7344 match(Set dst (URShiftI src1 src2));
7345
7346 size(4);
7347 format %{ "SRL $src1,$src2,$dst" %}
7348 opcode(Assembler::srl_op3, Assembler::arith_op);
7349 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7350 ins_pipe(ialu_reg_imm);
7351 %}
7352
7353 // Register Shift Right
7354 instruct shrL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7355 match(Set dst (URShiftL src1 src2));
7356
7357 size(4);
7358 format %{ "SRLX $src1,$src2,$dst" %}
7359 opcode(Assembler::srlx_op3, Assembler::arith_op);
7360 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7361 ins_pipe(ialu_reg_reg);
7362 %}
7363
7364 // Register Shift Right Immediate
7365 instruct shrL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7366 match(Set dst (URShiftL src1 src2));
7367
7368 size(4);
7369 format %{ "SRLX $src1,$src2,$dst" %}
7370 opcode(Assembler::srlx_op3, Assembler::arith_op);
7371 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7372 ins_pipe(ialu_reg_imm);
7373 %}
7374
7375 // Register Shift Right Immediate with a CastP2X
7376 #ifdef _LP64
7377 instruct shrP_reg_imm6(iRegL dst, iRegP src1, immU6 src2) %{
7378 match(Set dst (URShiftL (CastP2X src1) src2));
7379 size(4);
7380 format %{ "SRLX $src1,$src2,$dst\t! Cast ptr $src1 to long and shift" %}
7381 opcode(Assembler::srlx_op3, Assembler::arith_op);
7382 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7383 ins_pipe(ialu_reg_imm);
7384 %}
7385 #else
7386 instruct shrP_reg_imm5(iRegI dst, iRegP src1, immU5 src2) %{
7387 match(Set dst (URShiftI (CastP2X src1) src2));
7388 size(4);
7389 format %{ "SRL $src1,$src2,$dst\t! Cast ptr $src1 to int and shift" %}
7390 opcode(Assembler::srl_op3, Assembler::arith_op);
7391 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7392 ins_pipe(ialu_reg_imm);
7393 %}
7394 #endif
7395
7396
7397 //----------Floating Point Arithmetic Instructions-----------------------------
7398
7399 // Add float single precision
7400 instruct addF_reg_reg(regF dst, regF src1, regF src2) %{
7401 match(Set dst (AddF src1 src2));
7402
7403 size(4);
7404 format %{ "FADDS $src1,$src2,$dst" %}
7405 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fadds_opf);
7406 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7407 ins_pipe(faddF_reg_reg);
7408 %}
7409
7410 // Add float double precision
7411 instruct addD_reg_reg(regD dst, regD src1, regD src2) %{
7412 match(Set dst (AddD src1 src2));
7413
7414 size(4);
7415 format %{ "FADDD $src1,$src2,$dst" %}
7416 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf);
7417 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7418 ins_pipe(faddD_reg_reg);
7419 %}
7420
7421 // Sub float single precision
7422 instruct subF_reg_reg(regF dst, regF src1, regF src2) %{
7423 match(Set dst (SubF src1 src2));
7424
7425 size(4);
7426 format %{ "FSUBS $src1,$src2,$dst" %}
7427 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubs_opf);
7428 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7429 ins_pipe(faddF_reg_reg);
7430 %}
7431
7432 // Sub float double precision
7433 instruct subD_reg_reg(regD dst, regD src1, regD src2) %{
7434 match(Set dst (SubD src1 src2));
7435
7436 size(4);
7437 format %{ "FSUBD $src1,$src2,$dst" %}
7438 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf);
7439 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7440 ins_pipe(faddD_reg_reg);
7441 %}
7442
7443 // Mul float single precision
7444 instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{
7445 match(Set dst (MulF src1 src2));
7446
7447 size(4);
7448 format %{ "FMULS $src1,$src2,$dst" %}
7449 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuls_opf);
7450 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7451 ins_pipe(fmulF_reg_reg);
7452 %}
7453
7454 // Mul float double precision
7455 instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{
7456 match(Set dst (MulD src1 src2));
7457
7458 size(4);
7459 format %{ "FMULD $src1,$src2,$dst" %}
7460 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf);
7461 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7462 ins_pipe(fmulD_reg_reg);
7463 %}
7464
7465 // Div float single precision
7466 instruct divF_reg_reg(regF dst, regF src1, regF src2) %{
7467 match(Set dst (DivF src1 src2));
7468
7469 size(4);
7470 format %{ "FDIVS $src1,$src2,$dst" %}
7471 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivs_opf);
7472 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7473 ins_pipe(fdivF_reg_reg);
7474 %}
7475
7476 // Div float double precision
7477 instruct divD_reg_reg(regD dst, regD src1, regD src2) %{
7478 match(Set dst (DivD src1 src2));
7479
7480 size(4);
7481 format %{ "FDIVD $src1,$src2,$dst" %}
7482 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivd_opf);
7483 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7484 ins_pipe(fdivD_reg_reg);
7485 %}
7486
7487 // Absolute float double precision
7488 instruct absD_reg(regD dst, regD src) %{
7489 match(Set dst (AbsD src));
7490
7491 format %{ "FABSd $src,$dst" %}
7492 ins_encode(fabsd(dst, src));
7493 ins_pipe(faddD_reg);
7494 %}
7495
7496 // Absolute float single precision
7497 instruct absF_reg(regF dst, regF src) %{
7498 match(Set dst (AbsF src));
7499
7500 format %{ "FABSs $src,$dst" %}
7501 ins_encode(fabss(dst, src));
7502 ins_pipe(faddF_reg);
7503 %}
7504
7505 instruct negF_reg(regF dst, regF src) %{
7506 match(Set dst (NegF src));
7507
7508 size(4);
7509 format %{ "FNEGs $src,$dst" %}
7510 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fnegs_opf);
7511 ins_encode(form3_opf_rs2F_rdF(src, dst));
7512 ins_pipe(faddF_reg);
7513 %}
7514
7515 instruct negD_reg(regD dst, regD src) %{
7516 match(Set dst (NegD src));
7517
7518 format %{ "FNEGd $src,$dst" %}
7519 ins_encode(fnegd(dst, src));
7520 ins_pipe(faddD_reg);
7521 %}
7522
7523 // Sqrt float double precision
7524 instruct sqrtF_reg_reg(regF dst, regF src) %{
7525 match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
7526
7527 size(4);
7528 format %{ "FSQRTS $src,$dst" %}
7529 ins_encode(fsqrts(dst, src));
7530 ins_pipe(fdivF_reg_reg);
7531 %}
7532
7533 // Sqrt float double precision
7534 instruct sqrtD_reg_reg(regD dst, regD src) %{
7535 match(Set dst (SqrtD src));
7536
7537 size(4);
7538 format %{ "FSQRTD $src,$dst" %}
7539 ins_encode(fsqrtd(dst, src));
7540 ins_pipe(fdivD_reg_reg);
7541 %}
7542
7543 //----------Logical Instructions-----------------------------------------------
7544 // And Instructions
7545 // Register And
7546 instruct andI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7547 match(Set dst (AndI src1 src2));
7548
7549 size(4);
7550 format %{ "AND $src1,$src2,$dst" %}
7551 opcode(Assembler::and_op3, Assembler::arith_op);
7552 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7553 ins_pipe(ialu_reg_reg);
7554 %}
7555
7556 // Immediate And
7557 instruct andI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7558 match(Set dst (AndI src1 src2));
7559
7560 size(4);
7561 format %{ "AND $src1,$src2,$dst" %}
7562 opcode(Assembler::and_op3, Assembler::arith_op);
7563 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7564 ins_pipe(ialu_reg_imm);
7565 %}
7566
7567 // Register And Long
7568 instruct andL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7569 match(Set dst (AndL src1 src2));
7570
7571 ins_cost(DEFAULT_COST);
7572 size(4);
7573 format %{ "AND $src1,$src2,$dst\t! long" %}
7574 opcode(Assembler::and_op3, Assembler::arith_op);
7575 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7576 ins_pipe(ialu_reg_reg);
7577 %}
7578
7579 instruct andL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7580 match(Set dst (AndL src1 con));
7581
7582 ins_cost(DEFAULT_COST);
7583 size(4);
7584 format %{ "AND $src1,$con,$dst\t! long" %}
7585 opcode(Assembler::and_op3, Assembler::arith_op);
7586 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7587 ins_pipe(ialu_reg_imm);
7588 %}
7589
7590 // Or Instructions
7591 // Register Or
7592 instruct orI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7593 match(Set dst (OrI src1 src2));
7594
7595 size(4);
7596 format %{ "OR $src1,$src2,$dst" %}
7597 opcode(Assembler::or_op3, Assembler::arith_op);
7598 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7599 ins_pipe(ialu_reg_reg);
7600 %}
7601
7602 // Immediate Or
7603 instruct orI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7604 match(Set dst (OrI src1 src2));
7605
7606 size(4);
7607 format %{ "OR $src1,$src2,$dst" %}
7608 opcode(Assembler::or_op3, Assembler::arith_op);
7609 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7610 ins_pipe(ialu_reg_imm);
7611 %}
7612
7613 // Register Or Long
7614 instruct orL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7615 match(Set dst (OrL src1 src2));
7616
7617 ins_cost(DEFAULT_COST);
7618 size(4);
7619 format %{ "OR $src1,$src2,$dst\t! long" %}
7620 opcode(Assembler::or_op3, Assembler::arith_op);
7621 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7622 ins_pipe(ialu_reg_reg);
7623 %}
7624
7625 instruct orL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7626 match(Set dst (OrL src1 con));
7627 ins_cost(DEFAULT_COST*2);
7628
7629 ins_cost(DEFAULT_COST);
7630 size(4);
7631 format %{ "OR $src1,$con,$dst\t! long" %}
7632 opcode(Assembler::or_op3, Assembler::arith_op);
7633 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7634 ins_pipe(ialu_reg_imm);
7635 %}
7636
7637 #ifndef _LP64
7638
7639 // Use sp_ptr_RegP to match G2 (TLS register) without spilling.
7640 instruct orI_reg_castP2X(iRegI dst, iRegI src1, sp_ptr_RegP src2) %{
7641 match(Set dst (OrI src1 (CastP2X src2)));
7642
7643 size(4);
7644 format %{ "OR $src1,$src2,$dst" %}
7645 opcode(Assembler::or_op3, Assembler::arith_op);
7646 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7647 ins_pipe(ialu_reg_reg);
7648 %}
7649
7650 #else
7651
7652 instruct orL_reg_castP2X(iRegL dst, iRegL src1, sp_ptr_RegP src2) %{
7653 match(Set dst (OrL src1 (CastP2X src2)));
7654
7655 ins_cost(DEFAULT_COST);
7656 size(4);
7657 format %{ "OR $src1,$src2,$dst\t! long" %}
7658 opcode(Assembler::or_op3, Assembler::arith_op);
7659 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7660 ins_pipe(ialu_reg_reg);
7661 %}
7662
7663 #endif
7664
7665 // Xor Instructions
7666 // Register Xor
7667 instruct xorI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7668 match(Set dst (XorI src1 src2));
7669
7670 size(4);
7671 format %{ "XOR $src1,$src2,$dst" %}
7672 opcode(Assembler::xor_op3, Assembler::arith_op);
7673 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7674 ins_pipe(ialu_reg_reg);
7675 %}
7676
7677 // Immediate Xor
7678 instruct xorI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7679 match(Set dst (XorI src1 src2));
7680
7681 size(4);
7682 format %{ "XOR $src1,$src2,$dst" %}
7683 opcode(Assembler::xor_op3, Assembler::arith_op);
7684 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7685 ins_pipe(ialu_reg_imm);
7686 %}
7687
7688 // Register Xor Long
7689 instruct xorL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7690 match(Set dst (XorL src1 src2));
7691
7692 ins_cost(DEFAULT_COST);
7693 size(4);
7694 format %{ "XOR $src1,$src2,$dst\t! long" %}
7695 opcode(Assembler::xor_op3, Assembler::arith_op);
7696 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7697 ins_pipe(ialu_reg_reg);
7698 %}
7699
7700 instruct xorL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7701 match(Set dst (XorL src1 con));
7702
7703 ins_cost(DEFAULT_COST);
7704 size(4);
7705 format %{ "XOR $src1,$con,$dst\t! long" %}
7706 opcode(Assembler::xor_op3, Assembler::arith_op);
7707 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7708 ins_pipe(ialu_reg_imm);
7709 %}
7710
7711 //----------Convert to Boolean-------------------------------------------------
7712 // Nice hack for 32-bit tests but doesn't work for
7713 // 64-bit pointers.
7714 instruct convI2B( iRegI dst, iRegI src, flagsReg ccr ) %{
7715 match(Set dst (Conv2B src));
7716 effect( KILL ccr );
7717 ins_cost(DEFAULT_COST*2);
7718 format %{ "CMP R_G0,$src\n\t"
7719 "ADDX R_G0,0,$dst" %}
7720 ins_encode( enc_to_bool( src, dst ) );
7721 ins_pipe(ialu_reg_ialu);
7722 %}
7723
7724 #ifndef _LP64
7725 instruct convP2B( iRegI dst, iRegP src, flagsReg ccr ) %{
7726 match(Set dst (Conv2B src));
7727 effect( KILL ccr );
7728 ins_cost(DEFAULT_COST*2);
7729 format %{ "CMP R_G0,$src\n\t"
7730 "ADDX R_G0,0,$dst" %}
7731 ins_encode( enc_to_bool( src, dst ) );
7732 ins_pipe(ialu_reg_ialu);
7733 %}
7734 #else
7735 instruct convP2B( iRegI dst, iRegP src ) %{
7736 match(Set dst (Conv2B src));
7737 ins_cost(DEFAULT_COST*2);
7738 format %{ "MOV $src,$dst\n\t"
7739 "MOVRNZ $src,1,$dst" %}
7740 ins_encode( form3_g0_rs2_rd_move( src, dst ), enc_convP2B( dst, src ) );
7741 ins_pipe(ialu_clr_and_mover);
7742 %}
7743 #endif
7744
7745 instruct cmpLTMask_reg_reg( iRegI dst, iRegI p, iRegI q, flagsReg ccr ) %{
7746 match(Set dst (CmpLTMask p q));
7747 effect( KILL ccr );
7748 ins_cost(DEFAULT_COST*4);
7749 format %{ "CMP $p,$q\n\t"
7750 "MOV #0,$dst\n\t"
7751 "BLT,a .+8\n\t"
7752 "MOV #-1,$dst" %}
7753 ins_encode( enc_ltmask(p,q,dst) );
7754 ins_pipe(ialu_reg_reg_ialu);
7755 %}
7756
7757 instruct cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp, flagsReg ccr ) %{
7758 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
7759 effect(KILL ccr, TEMP tmp);
7760 ins_cost(DEFAULT_COST*3);
7761
7762 format %{ "SUBcc $p,$q,$p\t! p' = p-q\n\t"
7763 "ADD $p,$y,$tmp\t! g3=p-q+y\n\t"
7764 "MOVl $tmp,$p\t! p' < 0 ? p'+y : p'" %}
7765 ins_encode( enc_cadd_cmpLTMask(p, q, y, tmp) );
7766 ins_pipe( cadd_cmpltmask );
7767 %}
7768
7769 instruct cadd_cmpLTMask2( iRegI p, iRegI q, iRegI y, iRegI tmp, flagsReg ccr ) %{
7770 match(Set p (AddI (SubI p q) (AndI (CmpLTMask p q) y)));
7771 effect( KILL ccr, TEMP tmp);
7772 ins_cost(DEFAULT_COST*3);
7773
7774 format %{ "SUBcc $p,$q,$p\t! p' = p-q\n\t"
7775 "ADD $p,$y,$tmp\t! g3=p-q+y\n\t"
7776 "MOVl $tmp,$p\t! p' < 0 ? p'+y : p'" %}
7777 ins_encode( enc_cadd_cmpLTMask(p, q, y, tmp) );
7778 ins_pipe( cadd_cmpltmask );
7779 %}
7780
7781 //----------Arithmetic Conversion Instructions---------------------------------
7782 // The conversions operations are all Alpha sorted. Please keep it that way!
7783
7784 instruct convD2F_reg(regF dst, regD src) %{
7785 match(Set dst (ConvD2F src));
7786 size(4);
7787 format %{ "FDTOS $src,$dst" %}
7788 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdtos_opf);
7789 ins_encode(form3_opf_rs2D_rdF(src, dst));
7790 ins_pipe(fcvtD2F);
7791 %}
7792
7793
7794 // Convert a double to an int in a float register.
7795 // If the double is a NAN, stuff a zero in instead.
7796 instruct convD2I_helper(regF dst, regD src, flagsRegF0 fcc0) %{
7797 effect(DEF dst, USE src, KILL fcc0);
7798 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t"
7799 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
7800 "FDTOI $src,$dst\t! convert in delay slot\n\t"
7801 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t"
7802 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n"
7803 "skip:" %}
7804 ins_encode(form_d2i_helper(src,dst));
7805 ins_pipe(fcvtD2I);
7806 %}
7807
7808 instruct convD2I_reg(stackSlotI dst, regD src) %{
7809 match(Set dst (ConvD2I src));
7810 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
7811 expand %{
7812 regF tmp;
7813 convD2I_helper(tmp, src);
7814 regF_to_stkI(dst, tmp);
7815 %}
7816 %}
7817
7818 // Convert a double to a long in a double register.
7819 // If the double is a NAN, stuff a zero in instead.
7820 instruct convD2L_helper(regD dst, regD src, flagsRegF0 fcc0) %{
7821 effect(DEF dst, USE src, KILL fcc0);
7822 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t"
7823 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
7824 "FDTOX $src,$dst\t! convert in delay slot\n\t"
7825 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t"
7826 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n"
7827 "skip:" %}
7828 ins_encode(form_d2l_helper(src,dst));
7829 ins_pipe(fcvtD2L);
7830 %}
7831
7832
7833 // Double to Long conversion
7834 instruct convD2L_reg(stackSlotL dst, regD src) %{
7835 match(Set dst (ConvD2L src));
7836 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
7837 expand %{
7838 regD tmp;
7839 convD2L_helper(tmp, src);
7840 regD_to_stkL(dst, tmp);
7841 %}
7842 %}
7843
7844
7845 instruct convF2D_reg(regD dst, regF src) %{
7846 match(Set dst (ConvF2D src));
7847 format %{ "FSTOD $src,$dst" %}
7848 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fstod_opf);
7849 ins_encode(form3_opf_rs2F_rdD(src, dst));
7850 ins_pipe(fcvtF2D);
7851 %}
7852
7853
7854 instruct convF2I_helper(regF dst, regF src, flagsRegF0 fcc0) %{
7855 effect(DEF dst, USE src, KILL fcc0);
7856 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t"
7857 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
7858 "FSTOI $src,$dst\t! convert in delay slot\n\t"
7859 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t"
7860 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n"
7861 "skip:" %}
7862 ins_encode(form_f2i_helper(src,dst));
7863 ins_pipe(fcvtF2I);
7864 %}
7865
7866 instruct convF2I_reg(stackSlotI dst, regF src) %{
7867 match(Set dst (ConvF2I src));
7868 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
7869 expand %{
7870 regF tmp;
7871 convF2I_helper(tmp, src);
7872 regF_to_stkI(dst, tmp);
7873 %}
7874 %}
7875
7876
7877 instruct convF2L_helper(regD dst, regF src, flagsRegF0 fcc0) %{
7878 effect(DEF dst, USE src, KILL fcc0);
7879 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t"
7880 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
7881 "FSTOX $src,$dst\t! convert in delay slot\n\t"
7882 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t"
7883 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n"
7884 "skip:" %}
7885 ins_encode(form_f2l_helper(src,dst));
7886 ins_pipe(fcvtF2L);
7887 %}
7888
7889 // Float to Long conversion
7890 instruct convF2L_reg(stackSlotL dst, regF src) %{
7891 match(Set dst (ConvF2L src));
7892 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
7893 expand %{
7894 regD tmp;
7895 convF2L_helper(tmp, src);
7896 regD_to_stkL(dst, tmp);
7897 %}
7898 %}
7899
7900
7901 instruct convI2D_helper(regD dst, regF tmp) %{
7902 effect(USE tmp, DEF dst);
7903 format %{ "FITOD $tmp,$dst" %}
7904 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf);
7905 ins_encode(form3_opf_rs2F_rdD(tmp, dst));
7906 ins_pipe(fcvtI2D);
7907 %}
7908
7909 instruct convI2D_reg(stackSlotI src, regD dst) %{
7910 match(Set dst (ConvI2D src));
7911 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
7912 expand %{
7913 regF tmp;
7914 stkI_to_regF( tmp, src);
7915 convI2D_helper( dst, tmp);
7916 %}
7917 %}
7918
7919 instruct convI2D_mem( regD_low dst, memory mem ) %{
7920 match(Set dst (ConvI2D (LoadI mem)));
7921 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
7922 size(8);
7923 format %{ "LDF $mem,$dst\n\t"
7924 "FITOD $dst,$dst" %}
7925 opcode(Assembler::ldf_op3, Assembler::fitod_opf);
7926 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst));
7927 ins_pipe(floadF_mem);
7928 %}
7929
7930
7931 instruct convI2F_helper(regF dst, regF tmp) %{
7932 effect(DEF dst, USE tmp);
7933 format %{ "FITOS $tmp,$dst" %}
7934 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitos_opf);
7935 ins_encode(form3_opf_rs2F_rdF(tmp, dst));
7936 ins_pipe(fcvtI2F);
7937 %}
7938
7939 instruct convI2F_reg( regF dst, stackSlotI src ) %{
7940 match(Set dst (ConvI2F src));
7941 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
7942 expand %{
7943 regF tmp;
7944 stkI_to_regF(tmp,src);
7945 convI2F_helper(dst, tmp);
7946 %}
7947 %}
7948
7949 instruct convI2F_mem( regF dst, memory mem ) %{
7950 match(Set dst (ConvI2F (LoadI mem)));
7951 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
7952 size(8);
7953 format %{ "LDF $mem,$dst\n\t"
7954 "FITOS $dst,$dst" %}
7955 opcode(Assembler::ldf_op3, Assembler::fitos_opf);
7956 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst));
7957 ins_pipe(floadF_mem);
7958 %}
7959
7960
7961 instruct convI2L_reg(iRegL dst, iRegI src) %{
7962 match(Set dst (ConvI2L src));
7963 size(4);
7964 format %{ "SRA $src,0,$dst\t! int->long" %}
7965 opcode(Assembler::sra_op3, Assembler::arith_op);
7966 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
7967 ins_pipe(ialu_reg_reg);
7968 %}
7969
7970 // Zero-extend convert int to long
7971 instruct convI2L_reg_zex(iRegL dst, iRegI src, immL_32bits mask ) %{
7972 match(Set dst (AndL (ConvI2L src) mask) );
7973 size(4);
7974 format %{ "SRL $src,0,$dst\t! zero-extend int to long" %}
7975 opcode(Assembler::srl_op3, Assembler::arith_op);
7976 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
7977 ins_pipe(ialu_reg_reg);
7978 %}
7979
7980 // Zero-extend long
7981 instruct zerox_long(iRegL dst, iRegL src, immL_32bits mask ) %{
7982 match(Set dst (AndL src mask) );
7983 size(4);
7984 format %{ "SRL $src,0,$dst\t! zero-extend long" %}
7985 opcode(Assembler::srl_op3, Assembler::arith_op);
7986 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
7987 ins_pipe(ialu_reg_reg);
7988 %}
7989
7990 instruct MoveF2I_stack_reg(iRegI dst, stackSlotF src) %{
7991 match(Set dst (MoveF2I src));
7992 effect(DEF dst, USE src);
7993 ins_cost(MEMORY_REF_COST);
7994
7995 size(4);
7996 format %{ "LDUW $src,$dst\t! MoveF2I" %}
7997 opcode(Assembler::lduw_op3);
7998 ins_encode(simple_form3_mem_reg( src, dst ) );
7999 ins_pipe(iload_mem);
8000 %}
8001
8002 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
8003 match(Set dst (MoveI2F src));
8004 effect(DEF dst, USE src);
8005 ins_cost(MEMORY_REF_COST);
8006
8007 size(4);
8008 format %{ "LDF $src,$dst\t! MoveI2F" %}
8009 opcode(Assembler::ldf_op3);
8010 ins_encode(simple_form3_mem_reg(src, dst));
8011 ins_pipe(floadF_stk);
8012 %}
8013
8014 instruct MoveD2L_stack_reg(iRegL dst, stackSlotD src) %{
8015 match(Set dst (MoveD2L src));
8016 effect(DEF dst, USE src);
8017 ins_cost(MEMORY_REF_COST);
8018
8019 size(4);
8020 format %{ "LDX $src,$dst\t! MoveD2L" %}
8021 opcode(Assembler::ldx_op3);
8022 ins_encode(simple_form3_mem_reg( src, dst ) );
8023 ins_pipe(iload_mem);
8024 %}
8025
8026 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
8027 match(Set dst (MoveL2D src));
8028 effect(DEF dst, USE src);
8029 ins_cost(MEMORY_REF_COST);
8030
8031 size(4);
8032 format %{ "LDDF $src,$dst\t! MoveL2D" %}
8033 opcode(Assembler::lddf_op3);
8034 ins_encode(simple_form3_mem_reg(src, dst));
8035 ins_pipe(floadD_stk);
8036 %}
8037
8038 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{
8039 match(Set dst (MoveF2I src));
8040 effect(DEF dst, USE src);
8041 ins_cost(MEMORY_REF_COST);
8042
8043 size(4);
8044 format %{ "STF $src,$dst\t!MoveF2I" %}
8045 opcode(Assembler::stf_op3);
8046 ins_encode(simple_form3_mem_reg(dst, src));
8047 ins_pipe(fstoreF_stk_reg);
8048 %}
8049
8050 instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{
8051 match(Set dst (MoveI2F src));
8052 effect(DEF dst, USE src);
8053 ins_cost(MEMORY_REF_COST);
8054
8055 size(4);
8056 format %{ "STW $src,$dst\t!MoveI2F" %}
8057 opcode(Assembler::stw_op3);
8058 ins_encode(simple_form3_mem_reg( dst, src ) );
8059 ins_pipe(istore_mem_reg);
8060 %}
8061
8062 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
8063 match(Set dst (MoveD2L src));
8064 effect(DEF dst, USE src);
8065 ins_cost(MEMORY_REF_COST);
8066
8067 size(4);
8068 format %{ "STDF $src,$dst\t!MoveD2L" %}
8069 opcode(Assembler::stdf_op3);
8070 ins_encode(simple_form3_mem_reg(dst, src));
8071 ins_pipe(fstoreD_stk_reg);
8072 %}
8073
8074 instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{
8075 match(Set dst (MoveL2D src));
8076 effect(DEF dst, USE src);
8077 ins_cost(MEMORY_REF_COST);
8078
8079 size(4);
8080 format %{ "STX $src,$dst\t!MoveL2D" %}
8081 opcode(Assembler::stx_op3);
8082 ins_encode(simple_form3_mem_reg( dst, src ) );
8083 ins_pipe(istore_mem_reg);
8084 %}
8085
8086
8087 //-----------
8088 // Long to Double conversion using V8 opcodes.
8089 // Still useful because cheetah traps and becomes
8090 // amazingly slow for some common numbers.
8091
8092 // Magic constant, 0x43300000
8093 instruct loadConI_x43300000(iRegI dst) %{
8094 effect(DEF dst);
8095 size(4);
8096 format %{ "SETHI HI(0x43300000),$dst\t! 2^52" %}
8097 ins_encode(SetHi22(0x43300000, dst));
8098 ins_pipe(ialu_none);
8099 %}
8100
8101 // Magic constant, 0x41f00000
8102 instruct loadConI_x41f00000(iRegI dst) %{
8103 effect(DEF dst);
8104 size(4);
8105 format %{ "SETHI HI(0x41f00000),$dst\t! 2^32" %}
8106 ins_encode(SetHi22(0x41f00000, dst));
8107 ins_pipe(ialu_none);
8108 %}
8109
8110 // Construct a double from two float halves
8111 instruct regDHi_regDLo_to_regD(regD_low dst, regD_low src1, regD_low src2) %{
8112 effect(DEF dst, USE src1, USE src2);
8113 size(8);
8114 format %{ "FMOVS $src1.hi,$dst.hi\n\t"
8115 "FMOVS $src2.lo,$dst.lo" %}
8116 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmovs_opf);
8117 ins_encode(form3_opf_rs2D_hi_rdD_hi(src1, dst), form3_opf_rs2D_lo_rdD_lo(src2, dst));
8118 ins_pipe(faddD_reg_reg);
8119 %}
8120
8121 // Convert integer in high half of a double register (in the lower half of
8122 // the double register file) to double
8123 instruct convI2D_regDHi_regD(regD dst, regD_low src) %{
8124 effect(DEF dst, USE src);
8125 size(4);
8126 format %{ "FITOD $src,$dst" %}
8127 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf);
8128 ins_encode(form3_opf_rs2D_rdD(src, dst));
8129 ins_pipe(fcvtLHi2D);
8130 %}
8131
8132 // Add float double precision
8133 instruct addD_regD_regD(regD dst, regD src1, regD src2) %{
8134 effect(DEF dst, USE src1, USE src2);
8135 size(4);
8136 format %{ "FADDD $src1,$src2,$dst" %}
8137 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf);
8138 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8139 ins_pipe(faddD_reg_reg);
8140 %}
8141
8142 // Sub float double precision
8143 instruct subD_regD_regD(regD dst, regD src1, regD src2) %{
8144 effect(DEF dst, USE src1, USE src2);
8145 size(4);
8146 format %{ "FSUBD $src1,$src2,$dst" %}
8147 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf);
8148 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8149 ins_pipe(faddD_reg_reg);
8150 %}
8151
8152 // Mul float double precision
8153 instruct mulD_regD_regD(regD dst, regD src1, regD src2) %{
8154 effect(DEF dst, USE src1, USE src2);
8155 size(4);
8156 format %{ "FMULD $src1,$src2,$dst" %}
8157 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf);
8158 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8159 ins_pipe(fmulD_reg_reg);
8160 %}
8161
8162 instruct convL2D_reg_slow_fxtof(regD dst, stackSlotL src) %{
8163 match(Set dst (ConvL2D src));
8164 ins_cost(DEFAULT_COST*8 + MEMORY_REF_COST*6);
8165
8166 expand %{
8167 regD_low tmpsrc;
8168 iRegI ix43300000;
8169 iRegI ix41f00000;
8170 stackSlotL lx43300000;
8171 stackSlotL lx41f00000;
8172 regD_low dx43300000;
8173 regD dx41f00000;
8174 regD tmp1;
8175 regD_low tmp2;
8176 regD tmp3;
8177 regD tmp4;
8178
8179 stkL_to_regD(tmpsrc, src);
8180
8181 loadConI_x43300000(ix43300000);
8182 loadConI_x41f00000(ix41f00000);
8183 regI_to_stkLHi(lx43300000, ix43300000);
8184 regI_to_stkLHi(lx41f00000, ix41f00000);
8185 stkL_to_regD(dx43300000, lx43300000);
8186 stkL_to_regD(dx41f00000, lx41f00000);
8187
8188 convI2D_regDHi_regD(tmp1, tmpsrc);
8189 regDHi_regDLo_to_regD(tmp2, dx43300000, tmpsrc);
8190 subD_regD_regD(tmp3, tmp2, dx43300000);
8191 mulD_regD_regD(tmp4, tmp1, dx41f00000);
8192 addD_regD_regD(dst, tmp3, tmp4);
8193 %}
8194 %}
8195
8196 // Long to Double conversion using fast fxtof
8197 instruct convL2D_helper(regD dst, regD tmp) %{
8198 effect(DEF dst, USE tmp);
8199 size(4);
8200 format %{ "FXTOD $tmp,$dst" %}
8201 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtod_opf);
8202 ins_encode(form3_opf_rs2D_rdD(tmp, dst));
8203 ins_pipe(fcvtL2D);
8204 %}
8205
8206 instruct convL2D_reg_fast_fxtof(regD dst, stackSlotL src) %{
8207 predicate(VM_Version::has_fast_fxtof());
8208 match(Set dst (ConvL2D src));
8209 ins_cost(DEFAULT_COST + 3 * MEMORY_REF_COST);
8210 expand %{
8211 regD tmp;
8212 stkL_to_regD(tmp, src);
8213 convL2D_helper(dst, tmp);
8214 %}
8215 %}
8216
8217 //-----------
8218 // Long to Float conversion using V8 opcodes.
8219 // Still useful because cheetah traps and becomes
8220 // amazingly slow for some common numbers.
8221
8222 // Long to Float conversion using fast fxtof
8223 instruct convL2F_helper(regF dst, regD tmp) %{
8224 effect(DEF dst, USE tmp);
8225 size(4);
8226 format %{ "FXTOS $tmp,$dst" %}
8227 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtos_opf);
8228 ins_encode(form3_opf_rs2D_rdF(tmp, dst));
8229 ins_pipe(fcvtL2F);
8230 %}
8231
8232 instruct convL2F_reg_fast_fxtof(regF dst, stackSlotL src) %{
8233 match(Set dst (ConvL2F src));
8234 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8235 expand %{
8236 regD tmp;
8237 stkL_to_regD(tmp, src);
8238 convL2F_helper(dst, tmp);
8239 %}
8240 %}
8241 //-----------
8242
8243 instruct convL2I_reg(iRegI dst, iRegL src) %{
8244 match(Set dst (ConvL2I src));
8245 #ifndef _LP64
8246 format %{ "MOV $src.lo,$dst\t! long->int" %}
8247 ins_encode( form3_g0_rs2_rd_move_lo2( src, dst ) );
8248 ins_pipe(ialu_move_reg_I_to_L);
8249 #else
8250 size(4);
8251 format %{ "SRA $src,R_G0,$dst\t! long->int" %}
8252 ins_encode( form3_rs1_rd_signextend_lo1( src, dst ) );
8253 ins_pipe(ialu_reg);
8254 #endif
8255 %}
8256
8257 // Register Shift Right Immediate
8258 instruct shrL_reg_imm6_L2I(iRegI dst, iRegL src, immI_32_63 cnt) %{
8259 match(Set dst (ConvL2I (RShiftL src cnt)));
8260
8261 size(4);
8262 format %{ "SRAX $src,$cnt,$dst" %}
8263 opcode(Assembler::srax_op3, Assembler::arith_op);
8264 ins_encode( form3_sd_rs1_imm6_rd( src, cnt, dst ) );
8265 ins_pipe(ialu_reg_imm);
8266 %}
8267
8268 // Replicate scalar to packed byte values in Double register
8269 instruct Repl8B_reg_helper(iRegL dst, iRegI src) %{
8270 effect(DEF dst, USE src);
8271 format %{ "SLLX $src,56,$dst\n\t"
8272 "SRLX $dst, 8,O7\n\t"
8273 "OR $dst,O7,$dst\n\t"
8274 "SRLX $dst,16,O7\n\t"
8275 "OR $dst,O7,$dst\n\t"
8276 "SRLX $dst,32,O7\n\t"
8277 "OR $dst,O7,$dst\t! replicate8B" %}
8278 ins_encode( enc_repl8b(src, dst));
8279 ins_pipe(ialu_reg);
8280 %}
8281
8282 // Replicate scalar to packed byte values in Double register
8283 instruct Repl8B_reg(stackSlotD dst, iRegI src) %{
8284 match(Set dst (Replicate8B src));
8285 expand %{
8286 iRegL tmp;
8287 Repl8B_reg_helper(tmp, src);
8288 regL_to_stkD(dst, tmp);
8289 %}
8290 %}
8291
8292 // Replicate scalar constant to packed byte values in Double register
8293 instruct Repl8B_immI(regD dst, immI13 src, o7RegP tmp) %{
8294 match(Set dst (Replicate8B src));
8295 #ifdef _LP64
8296 size(36);
8297 #else
8298 size(8);
8299 #endif
8300 format %{ "SETHI hi(&Repl8($src)),$tmp\t!get Repl8B($src) from table\n\t"
8301 "LDDF [$tmp+lo(&Repl8($src))],$dst" %}
8302 ins_encode( LdReplImmI(src, dst, tmp, (8), (1)) );
8303 ins_pipe(loadConFD);
8304 %}
8305
8306 // Replicate scalar to packed char values into stack slot
8307 instruct Repl4C_reg_helper(iRegL dst, iRegI src) %{
8308 effect(DEF dst, USE src);
8309 format %{ "SLLX $src,48,$dst\n\t"
8310 "SRLX $dst,16,O7\n\t"
8311 "OR $dst,O7,$dst\n\t"
8312 "SRLX $dst,32,O7\n\t"
8313 "OR $dst,O7,$dst\t! replicate4C" %}
8314 ins_encode( enc_repl4s(src, dst) );
8315 ins_pipe(ialu_reg);
8316 %}
8317
8318 // Replicate scalar to packed char values into stack slot
8319 instruct Repl4C_reg(stackSlotD dst, iRegI src) %{
8320 match(Set dst (Replicate4C src));
8321 expand %{
8322 iRegL tmp;
8323 Repl4C_reg_helper(tmp, src);
8324 regL_to_stkD(dst, tmp);
8325 %}
8326 %}
8327
8328 // Replicate scalar constant to packed char values in Double register
8329 instruct Repl4C_immI(regD dst, immI src, o7RegP tmp) %{
8330 match(Set dst (Replicate4C src));
8331 #ifdef _LP64
8332 size(36);
8333 #else
8334 size(8);
8335 #endif
8336 format %{ "SETHI hi(&Repl4($src)),$tmp\t!get Repl4C($src) from table\n\t"
8337 "LDDF [$tmp+lo(&Repl4($src))],$dst" %}
8338 ins_encode( LdReplImmI(src, dst, tmp, (4), (2)) );
8339 ins_pipe(loadConFD);
8340 %}
8341
8342 // Replicate scalar to packed short values into stack slot
8343 instruct Repl4S_reg_helper(iRegL dst, iRegI src) %{
8344 effect(DEF dst, USE src);
8345 format %{ "SLLX $src,48,$dst\n\t"
8346 "SRLX $dst,16,O7\n\t"
8347 "OR $dst,O7,$dst\n\t"
8348 "SRLX $dst,32,O7\n\t"
8349 "OR $dst,O7,$dst\t! replicate4S" %}
8350 ins_encode( enc_repl4s(src, dst) );
8351 ins_pipe(ialu_reg);
8352 %}
8353
8354 // Replicate scalar to packed short values into stack slot
8355 instruct Repl4S_reg(stackSlotD dst, iRegI src) %{
8356 match(Set dst (Replicate4S src));
8357 expand %{
8358 iRegL tmp;
8359 Repl4S_reg_helper(tmp, src);
8360 regL_to_stkD(dst, tmp);
8361 %}
8362 %}
8363
8364 // Replicate scalar constant to packed short values in Double register
8365 instruct Repl4S_immI(regD dst, immI src, o7RegP tmp) %{
8366 match(Set dst (Replicate4S src));
8367 #ifdef _LP64
8368 size(36);
8369 #else
8370 size(8);
8371 #endif
8372 format %{ "SETHI hi(&Repl4($src)),$tmp\t!get Repl4S($src) from table\n\t"
8373 "LDDF [$tmp+lo(&Repl4($src))],$dst" %}
8374 ins_encode( LdReplImmI(src, dst, tmp, (4), (2)) );
8375 ins_pipe(loadConFD);
8376 %}
8377
8378 // Replicate scalar to packed int values in Double register
8379 instruct Repl2I_reg_helper(iRegL dst, iRegI src) %{
8380 effect(DEF dst, USE src);
8381 format %{ "SLLX $src,32,$dst\n\t"
8382 "SRLX $dst,32,O7\n\t"
8383 "OR $dst,O7,$dst\t! replicate2I" %}
8384 ins_encode( enc_repl2i(src, dst));
8385 ins_pipe(ialu_reg);
8386 %}
8387
8388 // Replicate scalar to packed int values in Double register
8389 instruct Repl2I_reg(stackSlotD dst, iRegI src) %{
8390 match(Set dst (Replicate2I src));
8391 expand %{
8392 iRegL tmp;
8393 Repl2I_reg_helper(tmp, src);
8394 regL_to_stkD(dst, tmp);
8395 %}
8396 %}
8397
8398 // Replicate scalar zero constant to packed int values in Double register
8399 instruct Repl2I_immI(regD dst, immI src, o7RegP tmp) %{
8400 match(Set dst (Replicate2I src));
8401 #ifdef _LP64
8402 size(36);
8403 #else
8404 size(8);
8405 #endif
8406 format %{ "SETHI hi(&Repl2($src)),$tmp\t!get Repl2I($src) from table\n\t"
8407 "LDDF [$tmp+lo(&Repl2($src))],$dst" %}
8408 ins_encode( LdReplImmI(src, dst, tmp, (2), (4)) );
8409 ins_pipe(loadConFD);
8410 %}
8411
8412 //----------Control Flow Instructions------------------------------------------
8413 // Compare Instructions
8414 // Compare Integers
8415 instruct compI_iReg(flagsReg icc, iRegI op1, iRegI op2) %{
8416 match(Set icc (CmpI op1 op2));
8417 effect( DEF icc, USE op1, USE op2 );
8418
8419 size(4);
8420 format %{ "CMP $op1,$op2" %}
8421 opcode(Assembler::subcc_op3, Assembler::arith_op);
8422 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8423 ins_pipe(ialu_cconly_reg_reg);
8424 %}
8425
8426 instruct compU_iReg(flagsRegU icc, iRegI op1, iRegI op2) %{
8427 match(Set icc (CmpU op1 op2));
8428
8429 size(4);
8430 format %{ "CMP $op1,$op2\t! unsigned" %}
8431 opcode(Assembler::subcc_op3, Assembler::arith_op);
8432 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8433 ins_pipe(ialu_cconly_reg_reg);
8434 %}
8435
8436 instruct compI_iReg_imm13(flagsReg icc, iRegI op1, immI13 op2) %{
8437 match(Set icc (CmpI op1 op2));
8438 effect( DEF icc, USE op1 );
8439
8440 size(4);
8441 format %{ "CMP $op1,$op2" %}
8442 opcode(Assembler::subcc_op3, Assembler::arith_op);
8443 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8444 ins_pipe(ialu_cconly_reg_imm);
8445 %}
8446
8447 instruct testI_reg_reg( flagsReg icc, iRegI op1, iRegI op2, immI0 zero ) %{
8448 match(Set icc (CmpI (AndI op1 op2) zero));
8449
8450 size(4);
8451 format %{ "BTST $op2,$op1" %}
8452 opcode(Assembler::andcc_op3, Assembler::arith_op);
8453 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8454 ins_pipe(ialu_cconly_reg_reg_zero);
8455 %}
8456
8457 instruct testI_reg_imm( flagsReg icc, iRegI op1, immI13 op2, immI0 zero ) %{
8458 match(Set icc (CmpI (AndI op1 op2) zero));
8459
8460 size(4);
8461 format %{ "BTST $op2,$op1" %}
8462 opcode(Assembler::andcc_op3, Assembler::arith_op);
8463 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8464 ins_pipe(ialu_cconly_reg_imm_zero);
8465 %}
8466
8467 instruct compL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2 ) %{
8468 match(Set xcc (CmpL op1 op2));
8469 effect( DEF xcc, USE op1, USE op2 );
8470
8471 size(4);
8472 format %{ "CMP $op1,$op2\t\t! long" %}
8473 opcode(Assembler::subcc_op3, Assembler::arith_op);
8474 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8475 ins_pipe(ialu_cconly_reg_reg);
8476 %}
8477
8478 instruct compL_reg_con(flagsRegL xcc, iRegL op1, immL13 con) %{
8479 match(Set xcc (CmpL op1 con));
8480 effect( DEF xcc, USE op1, USE con );
8481
8482 size(4);
8483 format %{ "CMP $op1,$con\t\t! long" %}
8484 opcode(Assembler::subcc_op3, Assembler::arith_op);
8485 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) );
8486 ins_pipe(ialu_cconly_reg_reg);
8487 %}
8488
8489 instruct testL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2, immL0 zero) %{
8490 match(Set xcc (CmpL (AndL op1 op2) zero));
8491 effect( DEF xcc, USE op1, USE op2 );
8492
8493 size(4);
8494 format %{ "BTST $op1,$op2\t\t! long" %}
8495 opcode(Assembler::andcc_op3, Assembler::arith_op);
8496 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8497 ins_pipe(ialu_cconly_reg_reg);
8498 %}
8499
8500 // useful for checking the alignment of a pointer:
8501 instruct testL_reg_con(flagsRegL xcc, iRegL op1, immL13 con, immL0 zero) %{
8502 match(Set xcc (CmpL (AndL op1 con) zero));
8503 effect( DEF xcc, USE op1, USE con );
8504
8505 size(4);
8506 format %{ "BTST $op1,$con\t\t! long" %}
8507 opcode(Assembler::andcc_op3, Assembler::arith_op);
8508 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) );
8509 ins_pipe(ialu_cconly_reg_reg);
8510 %}
8511
8512 instruct compU_iReg_imm13(flagsRegU icc, iRegI op1, immU13 op2 ) %{
8513 match(Set icc (CmpU op1 op2));
8514
8515 size(4);
8516 format %{ "CMP $op1,$op2\t! unsigned" %}
8517 opcode(Assembler::subcc_op3, Assembler::arith_op);
8518 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8519 ins_pipe(ialu_cconly_reg_imm);
8520 %}
8521
8522 // Compare Pointers
8523 instruct compP_iRegP(flagsRegP pcc, iRegP op1, iRegP op2 ) %{
8524 match(Set pcc (CmpP op1 op2));
8525
8526 size(4);
8527 format %{ "CMP $op1,$op2\t! ptr" %}
8528 opcode(Assembler::subcc_op3, Assembler::arith_op);
8529 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8530 ins_pipe(ialu_cconly_reg_reg);
8531 %}
8532
8533 instruct compP_iRegP_imm13(flagsRegP pcc, iRegP op1, immP13 op2 ) %{
8534 match(Set pcc (CmpP op1 op2));
8535
8536 size(4);
8537 format %{ "CMP $op1,$op2\t! ptr" %}
8538 opcode(Assembler::subcc_op3, Assembler::arith_op);
8539 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8540 ins_pipe(ialu_cconly_reg_imm);
8541 %}
8542
8543 // Compare Narrow oops
8544 instruct compN_iRegN(flagsReg icc, iRegN op1, iRegN op2 ) %{
8545 match(Set icc (CmpN op1 op2));
8546
8547 size(4);
8548 format %{ "CMP $op1,$op2\t! compressed ptr" %}
8549 opcode(Assembler::subcc_op3, Assembler::arith_op);
8550 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8551 ins_pipe(ialu_cconly_reg_reg);
8552 %}
8553
8554 instruct compN_iRegN_immN0(flagsReg icc, iRegN op1, immN0 op2 ) %{
8555 match(Set icc (CmpN op1 op2));
8556
8557 size(4);
8558 format %{ "CMP $op1,$op2\t! compressed ptr" %}
8559 opcode(Assembler::subcc_op3, Assembler::arith_op);
8560 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8561 ins_pipe(ialu_cconly_reg_imm);
8562 %}
8563
8564 //----------Max and Min--------------------------------------------------------
8565 // Min Instructions
8566 // Conditional move for min
8567 instruct cmovI_reg_lt( iRegI op2, iRegI op1, flagsReg icc ) %{
8568 effect( USE_DEF op2, USE op1, USE icc );
8569
8570 size(4);
8571 format %{ "MOVlt icc,$op1,$op2\t! min" %}
8572 opcode(Assembler::less);
8573 ins_encode( enc_cmov_reg_minmax(op2,op1) );
8574 ins_pipe(ialu_reg_flags);
8575 %}
8576
8577 // Min Register with Register.
8578 instruct minI_eReg(iRegI op1, iRegI op2) %{
8579 match(Set op2 (MinI op1 op2));
8580 ins_cost(DEFAULT_COST*2);
8581 expand %{
8582 flagsReg icc;
8583 compI_iReg(icc,op1,op2);
8584 cmovI_reg_lt(op2,op1,icc);
8585 %}
8586 %}
8587
8588 // Max Instructions
8589 // Conditional move for max
8590 instruct cmovI_reg_gt( iRegI op2, iRegI op1, flagsReg icc ) %{
8591 effect( USE_DEF op2, USE op1, USE icc );
8592 format %{ "MOVgt icc,$op1,$op2\t! max" %}
8593 opcode(Assembler::greater);
8594 ins_encode( enc_cmov_reg_minmax(op2,op1) );
8595 ins_pipe(ialu_reg_flags);
8596 %}
8597
8598 // Max Register with Register
8599 instruct maxI_eReg(iRegI op1, iRegI op2) %{
8600 match(Set op2 (MaxI op1 op2));
8601 ins_cost(DEFAULT_COST*2);
8602 expand %{
8603 flagsReg icc;
8604 compI_iReg(icc,op1,op2);
8605 cmovI_reg_gt(op2,op1,icc);
8606 %}
8607 %}
8608
8609
8610 //----------Float Compares----------------------------------------------------
8611 // Compare floating, generate condition code
8612 instruct cmpF_cc(flagsRegF fcc, regF src1, regF src2) %{
8613 match(Set fcc (CmpF src1 src2));
8614
8615 size(4);
8616 format %{ "FCMPs $fcc,$src1,$src2" %}
8617 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmps_opf);
8618 ins_encode( form3_opf_rs1F_rs2F_fcc( src1, src2, fcc ) );
8619 ins_pipe(faddF_fcc_reg_reg_zero);
8620 %}
8621
8622 instruct cmpD_cc(flagsRegF fcc, regD src1, regD src2) %{
8623 match(Set fcc (CmpD src1 src2));
8624
8625 size(4);
8626 format %{ "FCMPd $fcc,$src1,$src2" %}
8627 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmpd_opf);
8628 ins_encode( form3_opf_rs1D_rs2D_fcc( src1, src2, fcc ) );
8629 ins_pipe(faddD_fcc_reg_reg_zero);
8630 %}
8631
8632
8633 // Compare floating, generate -1,0,1
8634 instruct cmpF_reg(iRegI dst, regF src1, regF src2, flagsRegF0 fcc0) %{
8635 match(Set dst (CmpF3 src1 src2));
8636 effect(KILL fcc0);
8637 ins_cost(DEFAULT_COST*3+BRANCH_COST*3);
8638 format %{ "fcmpl $dst,$src1,$src2" %}
8639 // Primary = float
8640 opcode( true );
8641 ins_encode( floating_cmp( dst, src1, src2 ) );
8642 ins_pipe( floating_cmp );
8643 %}
8644
8645 instruct cmpD_reg(iRegI dst, regD src1, regD src2, flagsRegF0 fcc0) %{
8646 match(Set dst (CmpD3 src1 src2));
8647 effect(KILL fcc0);
8648 ins_cost(DEFAULT_COST*3+BRANCH_COST*3);
8649 format %{ "dcmpl $dst,$src1,$src2" %}
8650 // Primary = double (not float)
8651 opcode( false );
8652 ins_encode( floating_cmp( dst, src1, src2 ) );
8653 ins_pipe( floating_cmp );
8654 %}
8655
8656 //----------Branches---------------------------------------------------------
8657 // Jump
8658 // (compare 'operand indIndex' and 'instruct addP_reg_reg' above)
8659 instruct jumpXtnd(iRegX switch_val, o7RegI table) %{
8660 match(Jump switch_val);
8661
8662 ins_cost(350);
8663
8664 format %{ "SETHI [hi(table_base)],O7\n\t"
8665 "ADD O7, lo(table_base), O7\n\t"
8666 "LD [O7+$switch_val], O7\n\t"
8667 "JUMP O7"
8668 %}
8669 ins_encode( jump_enc( switch_val, table) );
8670 ins_pc_relative(1);
8671 ins_pipe(ialu_reg_reg);
8672 %}
8673
8674 // Direct Branch. Use V8 version with longer range.
8675 instruct branch(label labl) %{
8676 match(Goto);
8677 effect(USE labl);
8678
8679 size(8);
8680 ins_cost(BRANCH_COST);
8681 format %{ "BA $labl" %}
8682 // Prim = bits 24-22, Secnd = bits 31-30, Tert = cond
8683 opcode(Assembler::br_op2, Assembler::branch_op, Assembler::always);
8684 ins_encode( enc_ba( labl ) );
8685 ins_pc_relative(1);
8686 ins_pipe(br);
8687 %}
8688
8689 // Conditional Direct Branch
8690 instruct branchCon(cmpOp cmp, flagsReg icc, label labl) %{
8691 match(If cmp icc);
8692 effect(USE labl);
8693
8694 size(8);
8695 ins_cost(BRANCH_COST);
8696 format %{ "BP$cmp $icc,$labl" %}
8697 // Prim = bits 24-22, Secnd = bits 31-30
8698 ins_encode( enc_bp( labl, cmp, icc ) );
8699 ins_pc_relative(1);
8700 ins_pipe(br_cc);
8701 %}
8702
8703 // Branch-on-register tests all 64 bits. We assume that values
8704 // in 64-bit registers always remains zero or sign extended
8705 // unless our code munges the high bits. Interrupts can chop
8706 // the high order bits to zero or sign at any time.
8707 instruct branchCon_regI(cmpOp_reg cmp, iRegI op1, immI0 zero, label labl) %{
8708 match(If cmp (CmpI op1 zero));
8709 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
8710 effect(USE labl);
8711
8712 size(8);
8713 ins_cost(BRANCH_COST);
8714 format %{ "BR$cmp $op1,$labl" %}
8715 ins_encode( enc_bpr( labl, cmp, op1 ) );
8716 ins_pc_relative(1);
8717 ins_pipe(br_reg);
8718 %}
8719
8720 instruct branchCon_regP(cmpOp_reg cmp, iRegP op1, immP0 null, label labl) %{
8721 match(If cmp (CmpP op1 null));
8722 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
8723 effect(USE labl);
8724
8725 size(8);
8726 ins_cost(BRANCH_COST);
8727 format %{ "BR$cmp $op1,$labl" %}
8728 ins_encode( enc_bpr( labl, cmp, op1 ) );
8729 ins_pc_relative(1);
8730 ins_pipe(br_reg);
8731 %}
8732
8733 instruct branchCon_regL(cmpOp_reg cmp, iRegL op1, immL0 zero, label labl) %{
8734 match(If cmp (CmpL op1 zero));
8735 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
8736 effect(USE labl);
8737
8738 size(8);
8739 ins_cost(BRANCH_COST);
8740 format %{ "BR$cmp $op1,$labl" %}
8741 ins_encode( enc_bpr( labl, cmp, op1 ) );
8742 ins_pc_relative(1);
8743 ins_pipe(br_reg);
8744 %}
8745
8746 instruct branchConU(cmpOpU cmp, flagsRegU icc, label labl) %{
8747 match(If cmp icc);
8748 effect(USE labl);
8749
8750 format %{ "BP$cmp $icc,$labl" %}
8751 // Prim = bits 24-22, Secnd = bits 31-30
8752 ins_encode( enc_bp( labl, cmp, icc ) );
8753 ins_pc_relative(1);
8754 ins_pipe(br_cc);
8755 %}
8756
8757 instruct branchConP(cmpOpP cmp, flagsRegP pcc, label labl) %{
8758 match(If cmp pcc);
8759 effect(USE labl);
8760
8761 size(8);
8762 ins_cost(BRANCH_COST);
8763 format %{ "BP$cmp $pcc,$labl" %}
8764 // Prim = bits 24-22, Secnd = bits 31-30
8765 ins_encode( enc_bpx( labl, cmp, pcc ) );
8766 ins_pc_relative(1);
8767 ins_pipe(br_cc);
8768 %}
8769
8770 instruct branchConF(cmpOpF cmp, flagsRegF fcc, label labl) %{
8771 match(If cmp fcc);
8772 effect(USE labl);
8773
8774 size(8);
8775 ins_cost(BRANCH_COST);
8776 format %{ "FBP$cmp $fcc,$labl" %}
8777 // Prim = bits 24-22, Secnd = bits 31-30
8778 ins_encode( enc_fbp( labl, cmp, fcc ) );
8779 ins_pc_relative(1);
8780 ins_pipe(br_fcc);
8781 %}
8782
8783 instruct branchLoopEnd(cmpOp cmp, flagsReg icc, label labl) %{
8784 match(CountedLoopEnd cmp icc);
8785 effect(USE labl);
8786
8787 size(8);
8788 ins_cost(BRANCH_COST);
8789 format %{ "BP$cmp $icc,$labl\t! Loop end" %}
8790 // Prim = bits 24-22, Secnd = bits 31-30
8791 ins_encode( enc_bp( labl, cmp, icc ) );
8792 ins_pc_relative(1);
8793 ins_pipe(br_cc);
8794 %}
8795
8796 instruct branchLoopEndU(cmpOpU cmp, flagsRegU icc, label labl) %{
8797 match(CountedLoopEnd cmp icc);
8798 effect(USE labl);
8799
8800 size(8);
8801 ins_cost(BRANCH_COST);
8802 format %{ "BP$cmp $icc,$labl\t! Loop end" %}
8803 // Prim = bits 24-22, Secnd = bits 31-30
8804 ins_encode( enc_bp( labl, cmp, icc ) );
8805 ins_pc_relative(1);
8806 ins_pipe(br_cc);
8807 %}
8808
8809 // ============================================================================
8810 // Long Compare
8811 //
8812 // Currently we hold longs in 2 registers. Comparing such values efficiently
8813 // is tricky. The flavor of compare used depends on whether we are testing
8814 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit.
8815 // The GE test is the negated LT test. The LE test can be had by commuting
8816 // the operands (yielding a GE test) and then negating; negate again for the
8817 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the
8818 // NE test is negated from that.
8819
8820 // Due to a shortcoming in the ADLC, it mixes up expressions like:
8821 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the
8822 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections
8823 // are collapsed internally in the ADLC's dfa-gen code. The match for
8824 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the
8825 // foo match ends up with the wrong leaf. One fix is to not match both
8826 // reg-reg and reg-zero forms of long-compare. This is unfortunate because
8827 // both forms beat the trinary form of long-compare and both are very useful
8828 // on Intel which has so few registers.
8829
8830 instruct branchCon_long(cmpOp cmp, flagsRegL xcc, label labl) %{
8831 match(If cmp xcc);
8832 effect(USE labl);
8833
8834 size(8);
8835 ins_cost(BRANCH_COST);
8836 format %{ "BP$cmp $xcc,$labl" %}
8837 // Prim = bits 24-22, Secnd = bits 31-30
8838 ins_encode( enc_bpl( labl, cmp, xcc ) );
8839 ins_pc_relative(1);
8840 ins_pipe(br_cc);
8841 %}
8842
8843 // Manifest a CmpL3 result in an integer register. Very painful.
8844 // This is the test to avoid.
8845 instruct cmpL3_reg_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg ccr ) %{
8846 match(Set dst (CmpL3 src1 src2) );
8847 effect( KILL ccr );
8848 ins_cost(6*DEFAULT_COST);
8849 size(24);
8850 format %{ "CMP $src1,$src2\t\t! long\n"
8851 "\tBLT,a,pn done\n"
8852 "\tMOV -1,$dst\t! delay slot\n"
8853 "\tBGT,a,pn done\n"
8854 "\tMOV 1,$dst\t! delay slot\n"
8855 "\tCLR $dst\n"
8856 "done:" %}
8857 ins_encode( cmpl_flag(src1,src2,dst) );
8858 ins_pipe(cmpL_reg);
8859 %}
8860
8861 // Conditional move
8862 instruct cmovLL_reg(cmpOp cmp, flagsRegL xcc, iRegL dst, iRegL src) %{
8863 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src)));
8864 ins_cost(150);
8865 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %}
8866 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
8867 ins_pipe(ialu_reg);
8868 %}
8869
8870 instruct cmovLL_imm(cmpOp cmp, flagsRegL xcc, iRegL dst, immL0 src) %{
8871 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src)));
8872 ins_cost(140);
8873 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %}
8874 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
8875 ins_pipe(ialu_imm);
8876 %}
8877
8878 instruct cmovIL_reg(cmpOp cmp, flagsRegL xcc, iRegI dst, iRegI src) %{
8879 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src)));
8880 ins_cost(150);
8881 format %{ "MOV$cmp $xcc,$src,$dst" %}
8882 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
8883 ins_pipe(ialu_reg);
8884 %}
8885
8886 instruct cmovIL_imm(cmpOp cmp, flagsRegL xcc, iRegI dst, immI11 src) %{
8887 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src)));
8888 ins_cost(140);
8889 format %{ "MOV$cmp $xcc,$src,$dst" %}
8890 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
8891 ins_pipe(ialu_imm);
8892 %}
8893
8894 instruct cmovNL_reg(cmpOp cmp, flagsRegL xcc, iRegN dst, iRegN src) %{
8895 match(Set dst (CMoveN (Binary cmp xcc) (Binary dst src)));
8896 ins_cost(150);
8897 format %{ "MOV$cmp $xcc,$src,$dst" %}
8898 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
8899 ins_pipe(ialu_reg);
8900 %}
8901
8902 instruct cmovPL_reg(cmpOp cmp, flagsRegL xcc, iRegP dst, iRegP src) %{
8903 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src)));
8904 ins_cost(150);
8905 format %{ "MOV$cmp $xcc,$src,$dst" %}
8906 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
8907 ins_pipe(ialu_reg);
8908 %}
8909
8910 instruct cmovPL_imm(cmpOp cmp, flagsRegL xcc, iRegP dst, immP0 src) %{
8911 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src)));
8912 ins_cost(140);
8913 format %{ "MOV$cmp $xcc,$src,$dst" %}
8914 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
8915 ins_pipe(ialu_imm);
8916 %}
8917
8918 instruct cmovFL_reg(cmpOp cmp, flagsRegL xcc, regF dst, regF src) %{
8919 match(Set dst (CMoveF (Binary cmp xcc) (Binary dst src)));
8920 ins_cost(150);
8921 opcode(0x101);
8922 format %{ "FMOVS$cmp $xcc,$src,$dst" %}
8923 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) );
8924 ins_pipe(int_conditional_float_move);
8925 %}
8926
8927 instruct cmovDL_reg(cmpOp cmp, flagsRegL xcc, regD dst, regD src) %{
8928 match(Set dst (CMoveD (Binary cmp xcc) (Binary dst src)));
8929 ins_cost(150);
8930 opcode(0x102);
8931 format %{ "FMOVD$cmp $xcc,$src,$dst" %}
8932 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) );
8933 ins_pipe(int_conditional_float_move);
8934 %}
8935
8936 // ============================================================================
8937 // Safepoint Instruction
8938 instruct safePoint_poll(iRegP poll) %{
8939 match(SafePoint poll);
8940 effect(USE poll);
8941
8942 size(4);
8943 #ifdef _LP64
8944 format %{ "LDX [$poll],R_G0\t! Safepoint: poll for GC" %}
8945 #else
8946 format %{ "LDUW [$poll],R_G0\t! Safepoint: poll for GC" %}
8947 #endif
8948 ins_encode %{
8949 __ relocate(relocInfo::poll_type);
8950 __ ld_ptr($poll$$Register, 0, G0);
8951 %}
8952 ins_pipe(loadPollP);
8953 %}
8954
8955 // ============================================================================
8956 // Call Instructions
8957 // Call Java Static Instruction
8958 instruct CallStaticJavaDirect( method meth ) %{
8959 match(CallStaticJava);
8960 effect(USE meth);
8961
8962 size(8);
8963 ins_cost(CALL_COST);
8964 format %{ "CALL,static ; NOP ==> " %}
8965 ins_encode( Java_Static_Call( meth ), call_epilog );
8966 ins_pc_relative(1);
8967 ins_pipe(simple_call);
8968 %}
8969
8970 // Call Java Dynamic Instruction
8971 instruct CallDynamicJavaDirect( method meth ) %{
8972 match(CallDynamicJava);
8973 effect(USE meth);
8974
8975 ins_cost(CALL_COST);
8976 format %{ "SET (empty),R_G5\n\t"
8977 "CALL,dynamic ; NOP ==> " %}
8978 ins_encode( Java_Dynamic_Call( meth ), call_epilog );
8979 ins_pc_relative(1);
8980 ins_pipe(call);
8981 %}
8982
8983 // Call Runtime Instruction
8984 instruct CallRuntimeDirect(method meth, l7RegP l7) %{
8985 match(CallRuntime);
8986 effect(USE meth, KILL l7);
8987 ins_cost(CALL_COST);
8988 format %{ "CALL,runtime" %}
8989 ins_encode( Java_To_Runtime( meth ),
8990 call_epilog, adjust_long_from_native_call );
8991 ins_pc_relative(1);
8992 ins_pipe(simple_call);
8993 %}
8994
8995 // Call runtime without safepoint - same as CallRuntime
8996 instruct CallLeafDirect(method meth, l7RegP l7) %{
8997 match(CallLeaf);
8998 effect(USE meth, KILL l7);
8999 ins_cost(CALL_COST);
9000 format %{ "CALL,runtime leaf" %}
9001 ins_encode( Java_To_Runtime( meth ),
9002 call_epilog,
9003 adjust_long_from_native_call );
9004 ins_pc_relative(1);
9005 ins_pipe(simple_call);
9006 %}
9007
9008 // Call runtime without safepoint - same as CallLeaf
9009 instruct CallLeafNoFPDirect(method meth, l7RegP l7) %{
9010 match(CallLeafNoFP);
9011 effect(USE meth, KILL l7);
9012 ins_cost(CALL_COST);
9013 format %{ "CALL,runtime leaf nofp" %}
9014 ins_encode( Java_To_Runtime( meth ),
9015 call_epilog,
9016 adjust_long_from_native_call );
9017 ins_pc_relative(1);
9018 ins_pipe(simple_call);
9019 %}
9020
9021 // Tail Call; Jump from runtime stub to Java code.
9022 // Also known as an 'interprocedural jump'.
9023 // Target of jump will eventually return to caller.
9024 // TailJump below removes the return address.
9025 instruct TailCalljmpInd(g3RegP jump_target, inline_cache_regP method_oop) %{
9026 match(TailCall jump_target method_oop );
9027
9028 ins_cost(CALL_COST);
9029 format %{ "Jmp $jump_target ; NOP \t! $method_oop holds method oop" %}
9030 ins_encode(form_jmpl(jump_target));
9031 ins_pipe(tail_call);
9032 %}
9033
9034
9035 // Return Instruction
9036 instruct Ret() %{
9037 match(Return);
9038
9039 // The epilogue node did the ret already.
9040 size(0);
9041 format %{ "! return" %}
9042 ins_encode();
9043 ins_pipe(empty);
9044 %}
9045
9046
9047 // Tail Jump; remove the return address; jump to target.
9048 // TailCall above leaves the return address around.
9049 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2).
9050 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a
9051 // "restore" before this instruction (in Epilogue), we need to materialize it
9052 // in %i0.
9053 instruct tailjmpInd(g1RegP jump_target, i0RegP ex_oop) %{
9054 match( TailJump jump_target ex_oop );
9055 ins_cost(CALL_COST);
9056 format %{ "! discard R_O7\n\t"
9057 "Jmp $jump_target ; ADD O7,8,O1 \t! $ex_oop holds exc. oop" %}
9058 ins_encode(form_jmpl_set_exception_pc(jump_target));
9059 // opcode(Assembler::jmpl_op3, Assembler::arith_op);
9060 // The hack duplicates the exception oop into G3, so that CreateEx can use it there.
9061 // ins_encode( form3_rs1_simm13_rd( jump_target, 0x00, R_G0 ), move_return_pc_to_o1() );
9062 ins_pipe(tail_call);
9063 %}
9064
9065 // Create exception oop: created by stack-crawling runtime code.
9066 // Created exception is now available to this handler, and is setup
9067 // just prior to jumping to this handler. No code emitted.
9068 instruct CreateException( o0RegP ex_oop )
9069 %{
9070 match(Set ex_oop (CreateEx));
9071 ins_cost(0);
9072
9073 size(0);
9074 // use the following format syntax
9075 format %{ "! exception oop is in R_O0; no code emitted" %}
9076 ins_encode();
9077 ins_pipe(empty);
9078 %}
9079
9080
9081 // Rethrow exception:
9082 // The exception oop will come in the first argument position.
9083 // Then JUMP (not call) to the rethrow stub code.
9084 instruct RethrowException()
9085 %{
9086 match(Rethrow);
9087 ins_cost(CALL_COST);
9088
9089 // use the following format syntax
9090 format %{ "Jmp rethrow_stub" %}
9091 ins_encode(enc_rethrow);
9092 ins_pipe(tail_call);
9093 %}
9094
9095
9096 // Die now
9097 instruct ShouldNotReachHere( )
9098 %{
9099 match(Halt);
9100 ins_cost(CALL_COST);
9101
9102 size(4);
9103 // Use the following format syntax
9104 format %{ "ILLTRAP ; ShouldNotReachHere" %}
9105 ins_encode( form2_illtrap() );
9106 ins_pipe(tail_call);
9107 %}
9108
9109 // ============================================================================
9110 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
9111 // array for an instance of the superklass. Set a hidden internal cache on a
9112 // hit (cache is checked with exposed code in gen_subtype_check()). Return
9113 // not zero for a miss or zero for a hit. The encoding ALSO sets flags.
9114 instruct partialSubtypeCheck( o0RegP index, o1RegP sub, o2RegP super, flagsRegP pcc, o7RegP o7 ) %{
9115 match(Set index (PartialSubtypeCheck sub super));
9116 effect( KILL pcc, KILL o7 );
9117 ins_cost(DEFAULT_COST*10);
9118 format %{ "CALL PartialSubtypeCheck\n\tNOP" %}
9119 ins_encode( enc_PartialSubtypeCheck() );
9120 ins_pipe(partial_subtype_check_pipe);
9121 %}
9122
9123 instruct partialSubtypeCheck_vs_zero( flagsRegP pcc, o1RegP sub, o2RegP super, immP0 zero, o0RegP idx, o7RegP o7 ) %{
9124 match(Set pcc (CmpP (PartialSubtypeCheck sub super) zero));
9125 effect( KILL idx, KILL o7 );
9126 ins_cost(DEFAULT_COST*10);
9127 format %{ "CALL PartialSubtypeCheck\n\tNOP\t# (sets condition codes)" %}
9128 ins_encode( enc_PartialSubtypeCheck() );
9129 ins_pipe(partial_subtype_check_pipe);
9130 %}
9131
9132
9133 // ============================================================================
9134 // inlined locking and unlocking
9135
9136 instruct cmpFastLock(flagsRegP pcc, iRegP object, iRegP box, iRegP scratch2, o7RegP scratch ) %{
9137 match(Set pcc (FastLock object box));
9138
9139 effect(KILL scratch, TEMP scratch2);
9140 ins_cost(100);
9141
9142 size(4*112); // conservative overestimation ...
9143 format %{ "FASTLOCK $object, $box; KILL $scratch, $scratch2, $box" %}
9144 ins_encode( Fast_Lock(object, box, scratch, scratch2) );
9145 ins_pipe(long_memory_op);
9146 %}
9147
9148
9149 instruct cmpFastUnlock(flagsRegP pcc, iRegP object, iRegP box, iRegP scratch2, o7RegP scratch ) %{
9150 match(Set pcc (FastUnlock object box));
9151 effect(KILL scratch, TEMP scratch2);
9152 ins_cost(100);
9153
9154 size(4*120); // conservative overestimation ...
9155 format %{ "FASTUNLOCK $object, $box; KILL $scratch, $scratch2, $box" %}
9156 ins_encode( Fast_Unlock(object, box, scratch, scratch2) );
9157 ins_pipe(long_memory_op);
9158 %}
9159
9160 // Count and Base registers are fixed because the allocator cannot
9161 // kill unknown registers. The encodings are generic.
9162 instruct clear_array(iRegX cnt, iRegP base, iRegX temp, Universe dummy, flagsReg ccr) %{
9163 match(Set dummy (ClearArray cnt base));
9164 effect(TEMP temp, KILL ccr);
9165 ins_cost(300);
9166 format %{ "MOV $cnt,$temp\n"
9167 "loop: SUBcc $temp,8,$temp\t! Count down a dword of bytes\n"
9168 " BRge loop\t\t! Clearing loop\n"
9169 " STX G0,[$base+$temp]\t! delay slot" %}
9170 ins_encode( enc_Clear_Array(cnt, base, temp) );
9171 ins_pipe(long_memory_op);
9172 %}
9173
9174 instruct string_compare(o0RegP str1, o1RegP str2, g3RegP tmp1, g4RegP tmp2, notemp_iRegI result,
9175 o7RegI tmp3, flagsReg ccr) %{
9176 match(Set result (StrComp str1 str2));
9177 effect(USE_KILL str1, USE_KILL str2, KILL tmp1, KILL tmp2, KILL ccr, KILL tmp3);
9178 ins_cost(300);
9179 format %{ "String Compare $str1,$str2 -> $result" %}
9180 ins_encode( enc_String_Compare(str1, str2, tmp1, tmp2, result) );
9181 ins_pipe(long_memory_op);
9182 %}
9183
9184 instruct string_equals(o0RegP str1, o1RegP str2, g3RegP tmp1, g4RegP tmp2, notemp_iRegI result,
9185 o7RegI tmp3, flagsReg ccr) %{
9186 match(Set result (StrEquals str1 str2));
9187 effect(USE_KILL str1, USE_KILL str2, KILL tmp1, KILL tmp2, KILL ccr, KILL tmp3);
9188 ins_cost(300);
9189 format %{ "String Equals $str1,$str2 -> $result" %}
9190 ins_encode( enc_String_Equals(str1, str2, tmp1, tmp2, result) );
9191 ins_pipe(long_memory_op);
9192 %}
9193
9194 instruct array_equals(o0RegP ary1, o1RegP ary2, g3RegP tmp1, g4RegP tmp2, notemp_iRegI result,
9195 flagsReg ccr) %{
9196 match(Set result (AryEq ary1 ary2));
9197 effect(USE_KILL ary1, USE_KILL ary2, KILL tmp1, KILL tmp2, KILL ccr);
9198 ins_cost(300);
9199 format %{ "Array Equals $ary1,$ary2 -> $result" %}
9200 ins_encode( enc_Array_Equals(ary1, ary2, tmp1, tmp2, result));
9201 ins_pipe(long_memory_op);
9202 %}
9203
9204
9205 //---------- Zeros Count Instructions ------------------------------------------
9206
9207 instruct countLeadingZerosI(iRegI dst, iRegI src, iRegI tmp, flagsReg cr) %{
9208 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
9209 match(Set dst (CountLeadingZerosI src));
9210 effect(TEMP dst, TEMP tmp, KILL cr);
9211
9212 // x |= (x >> 1);
9213 // x |= (x >> 2);
9214 // x |= (x >> 4);
9215 // x |= (x >> 8);
9216 // x |= (x >> 16);
9217 // return (WORDBITS - popc(x));
9218 format %{ "SRL $src,1,$dst\t! count leading zeros (int)\n\t"
9219 "OR $src,$tmp,$dst\n\t"
9220 "SRL $dst,2,$tmp\n\t"
9221 "OR $dst,$tmp,$dst\n\t"
9222 "SRL $dst,4,$tmp\n\t"
9223 "OR $dst,$tmp,$dst\n\t"
9224 "SRL $dst,8,$tmp\n\t"
9225 "OR $dst,$tmp,$dst\n\t"
9226 "SRL $dst,16,$tmp\n\t"
9227 "OR $dst,$tmp,$dst\n\t"
9228 "POPC $dst,$dst\n\t"
9229 "MOV 32,$tmp\n\t"
9230 "SUB $tmp,$dst,$dst" %}
9231 ins_encode %{
9232 Register Rdst = $dst$$Register;
9233 Register Rsrc = $src$$Register;
9234 Register Rtmp = $tmp$$Register;
9235 __ srl(Rsrc, 1, Rtmp);
9236 __ or3(Rsrc, Rtmp, Rdst);
9237 __ srl(Rdst, 2, Rtmp);
9238 __ or3(Rdst, Rtmp, Rdst);
9239 __ srl(Rdst, 4, Rtmp);
9240 __ or3(Rdst, Rtmp, Rdst);
9241 __ srl(Rdst, 8, Rtmp);
9242 __ or3(Rdst, Rtmp, Rdst);
9243 __ srl(Rdst, 16, Rtmp);
9244 __ or3(Rdst, Rtmp, Rdst);
9245 __ popc(Rdst, Rdst);
9246 __ mov(BitsPerInt, Rtmp);
9247 __ sub(Rtmp, Rdst, Rdst);
9248 %}
9249 ins_pipe(ialu_reg);
9250 %}
9251
9252 instruct countLeadingZerosL(iRegI dst, iRegL src, iRegL tmp, iRegL tmp2, flagsReg cr) %{
9253 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
9254 match(Set dst (CountLeadingZerosL src));
9255 effect(TEMP tmp, TEMP tmp2, KILL cr);
9256
9257 // x |= (x >> 1);
9258 // x |= (x >> 2);
9259 // x |= (x >> 4);
9260 // x |= (x >> 8);
9261 // x |= (x >> 16);
9262 // x |= (x >> 32);
9263 // return (WORDBITS - popc(x));
9264 format %{ "SRLX $src,1,$tmp2\t! count leading zeros (long)\n\t"
9265 "OR $src,$tmp2,$tmp\n\t"
9266 "SRLX $tmp,2,$tmp2\n\t"
9267 "OR $tmp,$tmp2,$tmp\n\t"
9268 "SRLX $tmp,4,$tmp2\n\t"
9269 "OR $tmp,$tmp2,$tmp\n\t"
9270 "SRLX $tmp,8,$tmp2\n\t"
9271 "OR $tmp,$tmp2,$tmp\n\t"
9272 "SRLX $tmp,16,$tmp2\n\t"
9273 "OR $tmp,$tmp2,$tmp\n\t"
9274 "SRLX $tmp,32,$tmp2\n\t"
9275 "OR $tmp,$tmp2,$tmp\n\t"
9276 "POPC $tmp,$dst\n\t"
9277 "MOV 64,$tmp2\n\t"
9278 "SUB $tmp2,$dst,$dst" %}
9279 ins_encode %{
9280 Register Rdst = $dst$$Register;
9281 Register Rsrc = $src$$Register;
9282 Register Rtmp = $tmp$$Register;
9283 Register Rtmp2 = $tmp2$$Register;
9284 __ srlx(Rsrc, 1, Rtmp2);
9285 __ or3(Rsrc, Rtmp2, Rtmp);
9286 __ srlx(Rtmp, 2, Rtmp2);
9287 __ or3(Rtmp, Rtmp2, Rtmp);
9288 __ srlx(Rtmp, 4, Rtmp2);
9289 __ or3(Rtmp, Rtmp2, Rtmp);
9290 __ srlx(Rtmp, 8, Rtmp2);
9291 __ or3(Rtmp, Rtmp2, Rtmp);
9292 __ srlx(Rtmp, 16, Rtmp2);
9293 __ or3(Rtmp, Rtmp2, Rtmp);
9294 __ srlx(Rtmp, 32, Rtmp2);
9295 __ or3(Rtmp, Rtmp2, Rtmp);
9296 __ popc(Rtmp, Rdst);
9297 __ mov(BitsPerLong, Rtmp2);
9298 __ sub(Rtmp2, Rdst, Rdst);
9299 %}
9300 ins_pipe(ialu_reg);
9301 %}
9302
9303 instruct countTrailingZerosI(iRegI dst, iRegI src, iRegI tmp, flagsReg cr) %{
9304 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
9305 match(Set dst (CountTrailingZerosI src));
9306 effect(TEMP tmp, KILL cr);
9307
9308 // return popc(~x & (x - 1));
9309 format %{ "SUB $src, 1, $tmp\t! count trailing zeros (int)\n\t"
9310 "ANDN $tmp, $src, $tmp\n\t"
9311 "SRL $tmp, R_G0, Rtmp\n\t"
9312 "POPC $tmp, $dst" %}
9313 ins_encode %{
9314 Register Rdst = $dst$$Register;
9315 Register Rsrc = $src$$Register;
9316 Register Rtmp = $tmp$$Register;
9317 __ sub(Rsrc, 1, Rtmp);
9318 __ andn(Rtmp, Rsrc, Rtmp);
9319 __ srl(Rtmp, G0, Rtmp);
9320 __ popc(Rtmp, Rdst);
9321 %}
9322 ins_pipe(ialu_reg);
9323 %}
9324
9325 instruct countTrailingZerosL(iRegI dst, iRegL src, iRegL tmp, flagsReg cr) %{
9326 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
9327 match(Set dst (CountTrailingZerosL src));
9328 effect(TEMP tmp, KILL cr);
9329
9330 // return popc(~x & (x - 1));
9331 format %{ "SUB $src, 1, $tmp\t! count trailing zeros (long)\n\t"
9332 "ANDN $tmp, $src, $tmp\n\t"
9333 "POPC $tmp, $dst" %}
9334 ins_encode %{
9335 Register Rdst = $dst$$Register;
9336 Register Rsrc = $src$$Register;
9337 Register Rtmp = $tmp$$Register;
9338 __ sub(Rsrc, 1, Rtmp);
9339 __ andn(Rtmp, Rsrc, Rtmp);
9340 __ popc(Rtmp, Rdst);
9341 %}
9342 ins_pipe(ialu_reg);
9343 %}
9344
9345
9346 //---------- Population Count Instructions -------------------------------------
9347
9348 instruct popCountI(iRegI dst, iRegI src) %{
9349 predicate(UsePopCountInstruction);
9350 match(Set dst (PopCountI src));
9351
9352 format %{ "POPC $src, $dst" %}
9353 ins_encode %{
9354 __ popc($src$$Register, $dst$$Register);
9355 %}
9356 ins_pipe(ialu_reg);
9357 %}
9358
9359 // Note: Long.bitCount(long) returns an int.
9360 instruct popCountL(iRegI dst, iRegL src) %{
9361 predicate(UsePopCountInstruction);
9362 match(Set dst (PopCountL src));
9363
9364 format %{ "POPC $src, $dst" %}
9365 ins_encode %{
9366 __ popc($src$$Register, $dst$$Register);
9367 %}
9368 ins_pipe(ialu_reg);
9369 %}
9370
9371
9372 // ============================================================================
9373 //------------Bytes reverse--------------------------------------------------
9374
9375 instruct bytes_reverse_int(iRegI dst, stackSlotI src) %{
9376 match(Set dst (ReverseBytesI src));
9377 effect(DEF dst, USE src);
9378
9379 // Op cost is artificially doubled to make sure that load or store
9380 // instructions are preferred over this one which requires a spill
9381 // onto a stack slot.
9382 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
9383 size(8);
9384 format %{ "LDUWA $src, $dst\t!asi=primary_little" %}
9385 opcode(Assembler::lduwa_op3);
9386 ins_encode( form3_mem_reg_little(src, dst) );
9387 ins_pipe( iload_mem );
9388 %}
9389
9390 instruct bytes_reverse_long(iRegL dst, stackSlotL src) %{
9391 match(Set dst (ReverseBytesL src));
9392 effect(DEF dst, USE src);
9393
9394 // Op cost is artificially doubled to make sure that load or store
9395 // instructions are preferred over this one which requires a spill
9396 // onto a stack slot.
9397 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
9398 size(8);
9399 format %{ "LDXA $src, $dst\t!asi=primary_little" %}
9400
9401 opcode(Assembler::ldxa_op3);
9402 ins_encode( form3_mem_reg_little(src, dst) );
9403 ins_pipe( iload_mem );
9404 %}
9405
9406 // Load Integer reversed byte order
9407 instruct loadI_reversed(iRegI dst, memory src) %{
9408 match(Set dst (ReverseBytesI (LoadI src)));
9409
9410 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
9411 size(8);
9412 format %{ "LDUWA $src, $dst\t!asi=primary_little" %}
9413
9414 opcode(Assembler::lduwa_op3);
9415 ins_encode( form3_mem_reg_little( src, dst) );
9416 ins_pipe(iload_mem);
9417 %}
9418
9419 // Load Long - aligned and reversed
9420 instruct loadL_reversed(iRegL dst, memory src) %{
9421 match(Set dst (ReverseBytesL (LoadL src)));
9422
9423 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
9424 size(8);
9425 format %{ "LDXA $src, $dst\t!asi=primary_little" %}
9426
9427 opcode(Assembler::ldxa_op3);
9428 ins_encode( form3_mem_reg_little( src, dst ) );
9429 ins_pipe(iload_mem);
9430 %}
9431
9432 // Store Integer reversed byte order
9433 instruct storeI_reversed(memory dst, iRegI src) %{
9434 match(Set dst (StoreI dst (ReverseBytesI src)));
9435
9436 ins_cost(MEMORY_REF_COST);
9437 size(8);
9438 format %{ "STWA $src, $dst\t!asi=primary_little" %}
9439
9440 opcode(Assembler::stwa_op3);
9441 ins_encode( form3_mem_reg_little( dst, src) );
9442 ins_pipe(istore_mem_reg);
9443 %}
9444
9445 // Store Long reversed byte order
9446 instruct storeL_reversed(memory dst, iRegL src) %{
9447 match(Set dst (StoreL dst (ReverseBytesL src)));
9448
9449 ins_cost(MEMORY_REF_COST);
9450 size(8);
9451 format %{ "STXA $src, $dst\t!asi=primary_little" %}
9452
9453 opcode(Assembler::stxa_op3);
9454 ins_encode( form3_mem_reg_little( dst, src) );
9455 ins_pipe(istore_mem_reg);
9456 %}
9457
9458 //----------PEEPHOLE RULES-----------------------------------------------------
9459 // These must follow all instruction definitions as they use the names
9460 // defined in the instructions definitions.
9461 //
9462 // peepmatch ( root_instr_name [preceding_instruction]* );
9463 //
9464 // peepconstraint %{
9465 // (instruction_number.operand_name relational_op instruction_number.operand_name
9466 // [, ...] );
9467 // // instruction numbers are zero-based using left to right order in peepmatch
9468 //
9469 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
9470 // // provide an instruction_number.operand_name for each operand that appears
9471 // // in the replacement instruction's match rule
9472 //
9473 // ---------VM FLAGS---------------------------------------------------------
9474 //
9475 // All peephole optimizations can be turned off using -XX:-OptoPeephole
9476 //
9477 // Each peephole rule is given an identifying number starting with zero and
9478 // increasing by one in the order seen by the parser. An individual peephole
9479 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
9480 // on the command-line.
9481 //
9482 // ---------CURRENT LIMITATIONS----------------------------------------------
9483 //
9484 // Only match adjacent instructions in same basic block
9485 // Only equality constraints
9486 // Only constraints between operands, not (0.dest_reg == EAX_enc)
9487 // Only one replacement instruction
9488 //
9489 // ---------EXAMPLE----------------------------------------------------------
9490 //
9491 // // pertinent parts of existing instructions in architecture description
9492 // instruct movI(eRegI dst, eRegI src) %{
9493 // match(Set dst (CopyI src));
9494 // %}
9495 //
9496 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
9497 // match(Set dst (AddI dst src));
9498 // effect(KILL cr);
9499 // %}
9500 //
9501 // // Change (inc mov) to lea
9502 // peephole %{
9503 // // increment preceeded by register-register move
9504 // peepmatch ( incI_eReg movI );
9505 // // require that the destination register of the increment
9506 // // match the destination register of the move
9507 // peepconstraint ( 0.dst == 1.dst );
9508 // // construct a replacement instruction that sets
9509 // // the destination to ( move's source register + one )
9510 // peepreplace ( incI_eReg_immI1( 0.dst 1.src 0.src ) );
9511 // %}
9512 //
9513
9514 // // Change load of spilled value to only a spill
9515 // instruct storeI(memory mem, eRegI src) %{
9516 // match(Set mem (StoreI mem src));
9517 // %}
9518 //
9519 // instruct loadI(eRegI dst, memory mem) %{
9520 // match(Set dst (LoadI mem));
9521 // %}
9522 //
9523 // peephole %{
9524 // peepmatch ( loadI storeI );
9525 // peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
9526 // peepreplace ( storeI( 1.mem 1.mem 1.src ) );
9527 // %}
9528
9529 //----------SMARTSPILL RULES---------------------------------------------------
9530 // These must follow all instruction definitions as they use the names
9531 // defined in the instructions definitions.
9532 //
9533 // SPARC will probably not have any of these rules due to RISC instruction set.
9534
9535 //----------PIPELINE-----------------------------------------------------------
9536 // Rules which define the behavior of the target architectures pipeline.