1695
1696 // Given a register encoding, produce a Integer Register object
1697 static Register reg_to_register_object(int register_encoding) {
1698 assert(L5->encoding() == R_L5_enc && G1->encoding() == R_G1_enc, "right coding");
1699 return as_Register(register_encoding);
1700 }
1701
1702 // Given a register encoding, produce a single-precision Float Register object
1703 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding) {
1704 assert(F5->encoding(FloatRegisterImpl::S) == R_F5_enc && F12->encoding(FloatRegisterImpl::S) == R_F12_enc, "right coding");
1705 return as_SingleFloatRegister(register_encoding);
1706 }
1707
1708 // Given a register encoding, produce a double-precision Float Register object
1709 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding) {
1710 assert(F4->encoding(FloatRegisterImpl::D) == R_F4_enc, "right coding");
1711 assert(F32->encoding(FloatRegisterImpl::D) == R_D32_enc, "right coding");
1712 return as_DoubleFloatRegister(register_encoding);
1713 }
1714
1715 int Matcher::regnum_to_fpu_offset(int regnum) {
1716 return regnum - 32; // The FP registers are in the second chunk
1717 }
1718
1719 #ifdef ASSERT
1720 address last_rethrow = NULL; // debugging aid for Rethrow encoding
1721 #endif
1722
1723 // Vector width in bytes
1724 const uint Matcher::vector_width_in_bytes(void) {
1725 return 8;
1726 }
1727
1728 // Vector ideal reg
1729 const uint Matcher::vector_ideal_reg(void) {
1730 return Op_RegD;
1731 }
1732
1733 // USII supports fxtof through the whole range of number, USIII doesn't
1734 const bool Matcher::convL2FSupported(void) {
9167 instruct string_equals(o0RegP str1, o1RegP str2, g3RegP tmp1, g4RegP tmp2, notemp_iRegI result,
9168 o7RegI tmp3, flagsReg ccr) %{
9169 match(Set result (StrEquals str1 str2));
9170 effect(USE_KILL str1, USE_KILL str2, KILL tmp1, KILL tmp2, KILL ccr, KILL tmp3);
9171 ins_cost(300);
9172 format %{ "String Equals $str1,$str2 -> $result" %}
9173 ins_encode( enc_String_Equals(str1, str2, tmp1, tmp2, result) );
9174 ins_pipe(long_memory_op);
9175 %}
9176
9177 instruct array_equals(o0RegP ary1, o1RegP ary2, g3RegP tmp1, g4RegP tmp2, notemp_iRegI result,
9178 flagsReg ccr) %{
9179 match(Set result (AryEq ary1 ary2));
9180 effect(USE_KILL ary1, USE_KILL ary2, KILL tmp1, KILL tmp2, KILL ccr);
9181 ins_cost(300);
9182 format %{ "Array Equals $ary1,$ary2 -> $result" %}
9183 ins_encode( enc_Array_Equals(ary1, ary2, tmp1, tmp2, result));
9184 ins_pipe(long_memory_op);
9185 %}
9186
9187 //---------- Population Count Instructions -------------------------------------
9188
9189 instruct popCountI(iRegI dst, iRegI src) %{
9190 predicate(UsePopCountInstruction);
9191 match(Set dst (PopCountI src));
9192
9193 format %{ "POPC $src, $dst" %}
9194 ins_encode %{
9195 __ popc($src$$Register, $dst$$Register);
9196 %}
9197 ins_pipe(ialu_reg);
9198 %}
9199
9200 // Note: Long.bitCount(long) returns an int.
9201 instruct popCountL(iRegI dst, iRegL src) %{
9202 predicate(UsePopCountInstruction);
9203 match(Set dst (PopCountL src));
9204
9205 format %{ "POPC $src, $dst" %}
9206 ins_encode %{
|
1695
1696 // Given a register encoding, produce a Integer Register object
1697 static Register reg_to_register_object(int register_encoding) {
1698 assert(L5->encoding() == R_L5_enc && G1->encoding() == R_G1_enc, "right coding");
1699 return as_Register(register_encoding);
1700 }
1701
1702 // Given a register encoding, produce a single-precision Float Register object
1703 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding) {
1704 assert(F5->encoding(FloatRegisterImpl::S) == R_F5_enc && F12->encoding(FloatRegisterImpl::S) == R_F12_enc, "right coding");
1705 return as_SingleFloatRegister(register_encoding);
1706 }
1707
1708 // Given a register encoding, produce a double-precision Float Register object
1709 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding) {
1710 assert(F4->encoding(FloatRegisterImpl::D) == R_F4_enc, "right coding");
1711 assert(F32->encoding(FloatRegisterImpl::D) == R_D32_enc, "right coding");
1712 return as_DoubleFloatRegister(register_encoding);
1713 }
1714
1715 const bool Matcher::match_rule_supported(int opcode) {
1716 if (!has_match_rule(opcode))
1717 return false;
1718
1719 switch (opcode) {
1720 case Op_CountLeadingZerosI:
1721 case Op_CountLeadingZerosL:
1722 case Op_CountTrailingZerosI:
1723 case Op_CountTrailingZerosL:
1724 if (!UsePopCountInstruction)
1725 return false;
1726 break;
1727 }
1728
1729 return true; // Per default match rules are supported.
1730 }
1731
1732 int Matcher::regnum_to_fpu_offset(int regnum) {
1733 return regnum - 32; // The FP registers are in the second chunk
1734 }
1735
1736 #ifdef ASSERT
1737 address last_rethrow = NULL; // debugging aid for Rethrow encoding
1738 #endif
1739
1740 // Vector width in bytes
1741 const uint Matcher::vector_width_in_bytes(void) {
1742 return 8;
1743 }
1744
1745 // Vector ideal reg
1746 const uint Matcher::vector_ideal_reg(void) {
1747 return Op_RegD;
1748 }
1749
1750 // USII supports fxtof through the whole range of number, USIII doesn't
1751 const bool Matcher::convL2FSupported(void) {
9184 instruct string_equals(o0RegP str1, o1RegP str2, g3RegP tmp1, g4RegP tmp2, notemp_iRegI result,
9185 o7RegI tmp3, flagsReg ccr) %{
9186 match(Set result (StrEquals str1 str2));
9187 effect(USE_KILL str1, USE_KILL str2, KILL tmp1, KILL tmp2, KILL ccr, KILL tmp3);
9188 ins_cost(300);
9189 format %{ "String Equals $str1,$str2 -> $result" %}
9190 ins_encode( enc_String_Equals(str1, str2, tmp1, tmp2, result) );
9191 ins_pipe(long_memory_op);
9192 %}
9193
9194 instruct array_equals(o0RegP ary1, o1RegP ary2, g3RegP tmp1, g4RegP tmp2, notemp_iRegI result,
9195 flagsReg ccr) %{
9196 match(Set result (AryEq ary1 ary2));
9197 effect(USE_KILL ary1, USE_KILL ary2, KILL tmp1, KILL tmp2, KILL ccr);
9198 ins_cost(300);
9199 format %{ "Array Equals $ary1,$ary2 -> $result" %}
9200 ins_encode( enc_Array_Equals(ary1, ary2, tmp1, tmp2, result));
9201 ins_pipe(long_memory_op);
9202 %}
9203
9204
9205 //---------- Zeros Count Instructions ------------------------------------------
9206
9207 instruct countLeadingZerosI(iRegI dst, iRegI src, iRegI tmp, flagsReg cr) %{
9208 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
9209 match(Set dst (CountLeadingZerosI src));
9210 effect(TEMP dst, TEMP tmp, KILL cr);
9211
9212 // x |= (x >> 1);
9213 // x |= (x >> 2);
9214 // x |= (x >> 4);
9215 // x |= (x >> 8);
9216 // x |= (x >> 16);
9217 // return (WORDBITS - popc(x));
9218 format %{ "SRL $src,1,$dst\t! count leading zeros (int)\n\t"
9219 "OR $src,$tmp,$dst\n\t"
9220 "SRL $dst,2,$tmp\n\t"
9221 "OR $dst,$tmp,$dst\n\t"
9222 "SRL $dst,4,$tmp\n\t"
9223 "OR $dst,$tmp,$dst\n\t"
9224 "SRL $dst,8,$tmp\n\t"
9225 "OR $dst,$tmp,$dst\n\t"
9226 "SRL $dst,16,$tmp\n\t"
9227 "OR $dst,$tmp,$dst\n\t"
9228 "POPC $dst,$dst\n\t"
9229 "MOV 32,$tmp\n\t"
9230 "SUB $tmp,$dst,$dst" %}
9231 ins_encode %{
9232 Register Rdst = $dst$$Register;
9233 Register Rsrc = $src$$Register;
9234 Register Rtmp = $tmp$$Register;
9235 __ srl(Rsrc, 1, Rtmp);
9236 __ or3(Rsrc, Rtmp, Rdst);
9237 __ srl(Rdst, 2, Rtmp);
9238 __ or3(Rdst, Rtmp, Rdst);
9239 __ srl(Rdst, 4, Rtmp);
9240 __ or3(Rdst, Rtmp, Rdst);
9241 __ srl(Rdst, 8, Rtmp);
9242 __ or3(Rdst, Rtmp, Rdst);
9243 __ srl(Rdst, 16, Rtmp);
9244 __ or3(Rdst, Rtmp, Rdst);
9245 __ popc(Rdst, Rdst);
9246 __ mov(BitsPerInt, Rtmp);
9247 __ sub(Rtmp, Rdst, Rdst);
9248 %}
9249 ins_pipe(ialu_reg);
9250 %}
9251
9252 instruct countLeadingZerosL(iRegI dst, iRegL src, iRegL tmp, iRegL tmp2, flagsReg cr) %{
9253 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
9254 match(Set dst (CountLeadingZerosL src));
9255 effect(TEMP tmp, TEMP tmp2, KILL cr);
9256
9257 // x |= (x >> 1);
9258 // x |= (x >> 2);
9259 // x |= (x >> 4);
9260 // x |= (x >> 8);
9261 // x |= (x >> 16);
9262 // x |= (x >> 32);
9263 // return (WORDBITS - popc(x));
9264 format %{ "SRLX $src,1,$tmp2\t! count leading zeros (long)\n\t"
9265 "OR $src,$tmp2,$tmp\n\t"
9266 "SRLX $tmp,2,$tmp2\n\t"
9267 "OR $tmp,$tmp2,$tmp\n\t"
9268 "SRLX $tmp,4,$tmp2\n\t"
9269 "OR $tmp,$tmp2,$tmp\n\t"
9270 "SRLX $tmp,8,$tmp2\n\t"
9271 "OR $tmp,$tmp2,$tmp\n\t"
9272 "SRLX $tmp,16,$tmp2\n\t"
9273 "OR $tmp,$tmp2,$tmp\n\t"
9274 "SRLX $tmp,32,$tmp2\n\t"
9275 "OR $tmp,$tmp2,$tmp\n\t"
9276 "POPC $tmp,$dst\n\t"
9277 "MOV 64,$tmp2\n\t"
9278 "SUB $tmp2,$dst,$dst" %}
9279 ins_encode %{
9280 Register Rdst = $dst$$Register;
9281 Register Rsrc = $src$$Register;
9282 Register Rtmp = $tmp$$Register;
9283 Register Rtmp2 = $tmp2$$Register;
9284 __ srlx(Rsrc, 1, Rtmp2);
9285 __ or3(Rsrc, Rtmp2, Rtmp);
9286 __ srlx(Rtmp, 2, Rtmp2);
9287 __ or3(Rtmp, Rtmp2, Rtmp);
9288 __ srlx(Rtmp, 4, Rtmp2);
9289 __ or3(Rtmp, Rtmp2, Rtmp);
9290 __ srlx(Rtmp, 8, Rtmp2);
9291 __ or3(Rtmp, Rtmp2, Rtmp);
9292 __ srlx(Rtmp, 16, Rtmp2);
9293 __ or3(Rtmp, Rtmp2, Rtmp);
9294 __ srlx(Rtmp, 32, Rtmp2);
9295 __ or3(Rtmp, Rtmp2, Rtmp);
9296 __ popc(Rtmp, Rdst);
9297 __ mov(BitsPerLong, Rtmp2);
9298 __ sub(Rtmp2, Rdst, Rdst);
9299 %}
9300 ins_pipe(ialu_reg);
9301 %}
9302
9303 instruct countTrailingZerosI(iRegI dst, iRegI src, iRegI tmp, flagsReg cr) %{
9304 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
9305 match(Set dst (CountTrailingZerosI src));
9306 effect(TEMP tmp, KILL cr);
9307
9308 // return popc(~x & (x - 1));
9309 format %{ "SUB $src, 1, $tmp\t! count trailing zeros (int)\n\t"
9310 "ANDN $tmp, $src, $tmp\n\t"
9311 "SRL $tmp, R_G0, Rtmp\n\t"
9312 "POPC $tmp, $dst" %}
9313 ins_encode %{
9314 Register Rdst = $dst$$Register;
9315 Register Rsrc = $src$$Register;
9316 Register Rtmp = $tmp$$Register;
9317 __ sub(Rsrc, 1, Rtmp);
9318 __ andn(Rtmp, Rsrc, Rtmp);
9319 __ srl(Rtmp, G0, Rtmp);
9320 __ popc(Rtmp, Rdst);
9321 %}
9322 ins_pipe(ialu_reg);
9323 %}
9324
9325 instruct countTrailingZerosL(iRegI dst, iRegL src, iRegL tmp, flagsReg cr) %{
9326 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
9327 match(Set dst (CountTrailingZerosL src));
9328 effect(TEMP tmp, KILL cr);
9329
9330 // return popc(~x & (x - 1));
9331 format %{ "SUB $src, 1, $tmp\t! count trailing zeros (long)\n\t"
9332 "ANDN $tmp, $src, $tmp\n\t"
9333 "POPC $tmp, $dst" %}
9334 ins_encode %{
9335 Register Rdst = $dst$$Register;
9336 Register Rsrc = $src$$Register;
9337 Register Rtmp = $tmp$$Register;
9338 __ sub(Rsrc, 1, Rtmp);
9339 __ andn(Rtmp, Rsrc, Rtmp);
9340 __ popc(Rtmp, Rdst);
9341 %}
9342 ins_pipe(ialu_reg);
9343 %}
9344
9345
9346 //---------- Population Count Instructions -------------------------------------
9347
9348 instruct popCountI(iRegI dst, iRegI src) %{
9349 predicate(UsePopCountInstruction);
9350 match(Set dst (PopCountI src));
9351
9352 format %{ "POPC $src, $dst" %}
9353 ins_encode %{
9354 __ popc($src$$Register, $dst$$Register);
9355 %}
9356 ins_pipe(ialu_reg);
9357 %}
9358
9359 // Note: Long.bitCount(long) returns an int.
9360 instruct popCountL(iRegI dst, iRegL src) %{
9361 predicate(UsePopCountInstruction);
9362 match(Set dst (PopCountL src));
9363
9364 format %{ "POPC $src, $dst" %}
9365 ins_encode %{
|