935   prefix(src, dst);
 936   emit_byte(0x23);
 937   emit_operand(dst, src);
 938 }
 939 
 940 void Assembler::andl(Register dst, Register src) {
 941   (void) prefix_and_encode(dst->encoding(), src->encoding());
 942   emit_arith(0x23, 0xC0, dst, src);
 943 }
 944 
 945 void Assembler::andpd(XMMRegister dst, Address src) {
 946   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
 947   InstructionMark im(this);
 948   emit_byte(0x66);
 949   prefix(src, dst);
 950   emit_byte(0x0F);
 951   emit_byte(0x54);
 952   emit_operand(dst, src);
 953 }
 954 















 955 void Assembler::bswapl(Register reg) { // bswap
 956   int encode = prefix_and_encode(reg->encoding());
 957   emit_byte(0x0F);
 958   emit_byte(0xC8 | encode);
 959 }
 960 
 961 void Assembler::call(Label& L, relocInfo::relocType rtype) {
 962   // suspect disp32 is always good
 963   int operand = LP64_ONLY(disp32_operand) NOT_LP64(imm_operand);
 964 
 965   if (L.is_bound()) {
 966     const int long_size = 5;
 967     int offs = (int)( target(L) - pc() );
 968     assert(offs <= 0, "assembler error");
 969     InstructionMark im(this);
 970     // 1110 1000 #32-bit disp
 971     emit_byte(0xE8);
 972     emit_data(offs - long_size, rtype, operand);
 973   } else {
 974     InstructionMark im(this);

1421 
1422 void Assembler::leal(Register dst, Address src) {
1423   InstructionMark im(this);
1424 #ifdef _LP64
1425   emit_byte(0x67); // addr32
1426   prefix(src, dst);
1427 #endif // LP64
1428   emit_byte(0x8D);
1429   emit_operand(dst, src);
1430 }
1431 
1432 void Assembler::lock() {
1433   if (Atomics & 1) {
1434      // Emit either nothing, a NOP, or a NOP: prefix
1435      emit_byte(0x90) ;
1436   } else {
1437      emit_byte(0xF0);
1438   }
1439 }
1440 









1441 // Emit mfence instruction
1442 void Assembler::mfence() {
1443   NOT_LP64(assert(VM_Version::supports_sse2(), "unsupported");)
1444   emit_byte( 0x0F );
1445   emit_byte( 0xAE );
1446   emit_byte( 0xF0 );
1447 }
1448 
1449 void Assembler::mov(Register dst, Register src) {
1450   LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
1451 }
1452 
1453 void Assembler::movapd(XMMRegister dst, XMMRegister src) {
1454   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1455   int dstenc = dst->encoding();
1456   int srcenc = src->encoding();
1457   emit_byte(0x66);
1458   if (dstenc < 8) {
1459     if (srcenc >= 8) {
1460       prefix(REX_B);

3671   emit_arith(0x03, 0xC0, dst, src);
3672 }
3673 
3674 void Assembler::andq(Register dst, int32_t imm32) {
3675   (void) prefixq_and_encode(dst->encoding());
3676   emit_arith(0x81, 0xE0, dst, imm32);
3677 }
3678 
3679 void Assembler::andq(Register dst, Address src) {
3680   InstructionMark im(this);
3681   prefixq(src, dst);
3682   emit_byte(0x23);
3683   emit_operand(dst, src);
3684 }
3685 
3686 void Assembler::andq(Register dst, Register src) {
3687   (int) prefixq_and_encode(dst->encoding(), src->encoding());
3688   emit_arith(0x23, 0xC0, dst, src);
3689 }
3690 















3691 void Assembler::bswapq(Register reg) {
3692   int encode = prefixq_and_encode(reg->encoding());
3693   emit_byte(0x0F);
3694   emit_byte(0xC8 | encode);
3695 }
3696 
3697 void Assembler::cdqq() {
3698   prefix(REX_W);
3699   emit_byte(0x99);
3700 }
3701 
3702 void Assembler::clflush(Address adr) {
3703   prefix(adr);
3704   emit_byte(0x0F);
3705   emit_byte(0xAE);
3706   emit_operand(rdi, adr);
3707 }
3708 
3709 void Assembler::cmovq(Condition cc, Register dst, Register src) {
3710   int encode = prefixq_and_encode(dst->encoding(), src->encoding());

3924   emit_operand(rax, dst, 4);
3925   emit_data((int)imm32, rspec, narrow_oop_operand);
3926 }
3927 
3928 void Assembler::cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec) {
3929   InstructionMark im(this);
3930   int encode = prefix_and_encode(src1->encoding());
3931   emit_byte(0x81);
3932   emit_byte(0xF8 | encode);
3933   emit_data((int)imm32, rspec, narrow_oop_operand);
3934 }
3935 
3936 void Assembler::cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec) {
3937   InstructionMark im(this);
3938   prefix(src1);
3939   emit_byte(0x81);
3940   emit_operand(rax, src1, 4);
3941   emit_data((int)imm32, rspec, narrow_oop_operand);
3942 }
3943 









3944 void Assembler::movdq(XMMRegister dst, Register src) {
3945   // table D-1 says MMX/SSE2
3946   NOT_LP64(assert(VM_Version::supports_sse2() || VM_Version::supports_mmx(), ""));
3947   emit_byte(0x66);
3948   int encode = prefixq_and_encode(dst->encoding(), src->encoding());
3949   emit_byte(0x0F);
3950   emit_byte(0x6E);
3951   emit_byte(0xC0 | encode);
3952 }
3953 
3954 void Assembler::movdq(Register dst, XMMRegister src) {
3955   // table D-1 says MMX/SSE2
3956   NOT_LP64(assert(VM_Version::supports_sse2() || VM_Version::supports_mmx(), ""));
3957   emit_byte(0x66);
3958   // swap src/dst to get correct prefix
3959   int encode = prefixq_and_encode(src->encoding(), dst->encoding());
3960   emit_byte(0x0F);
3961   emit_byte(0x7E);
3962   emit_byte(0xC0 | encode);
3963 }

 935   prefix(src, dst);
 936   emit_byte(0x23);
 937   emit_operand(dst, src);
 938 }
 939 
 940 void Assembler::andl(Register dst, Register src) {
 941   (void) prefix_and_encode(dst->encoding(), src->encoding());
 942   emit_arith(0x23, 0xC0, dst, src);
 943 }
 944 
 945 void Assembler::andpd(XMMRegister dst, Address src) {
 946   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
 947   InstructionMark im(this);
 948   emit_byte(0x66);
 949   prefix(src, dst);
 950   emit_byte(0x0F);
 951   emit_byte(0x54);
 952   emit_operand(dst, src);
 953 }
 954 
 955 void Assembler::bsfl(Register dst, Register src) {
 956   int encode = prefix_and_encode(dst->encoding(), src->encoding());
 957   emit_byte(0x0F);
 958   emit_byte(0xBC);
 959   emit_byte(0xC0 | encode);
 960 }
 961 
 962 void Assembler::bsrl(Register dst, Register src) {
 963   assert(UseCountLeadingZerosInstruction == false, "encoding is treated as LZCNT");
 964   int encode = prefix_and_encode(dst->encoding(), src->encoding());
 965   emit_byte(0x0F);
 966   emit_byte(0xBD);
 967   emit_byte(0xC0 | encode);
 968 }
 969 
 970 void Assembler::bswapl(Register reg) { // bswap
 971   int encode = prefix_and_encode(reg->encoding());
 972   emit_byte(0x0F);
 973   emit_byte(0xC8 | encode);
 974 }
 975 
 976 void Assembler::call(Label& L, relocInfo::relocType rtype) {
 977   // suspect disp32 is always good
 978   int operand = LP64_ONLY(disp32_operand) NOT_LP64(imm_operand);
 979 
 980   if (L.is_bound()) {
 981     const int long_size = 5;
 982     int offs = (int)( target(L) - pc() );
 983     assert(offs <= 0, "assembler error");
 984     InstructionMark im(this);
 985     // 1110 1000 #32-bit disp
 986     emit_byte(0xE8);
 987     emit_data(offs - long_size, rtype, operand);
 988   } else {
 989     InstructionMark im(this);

1436 
1437 void Assembler::leal(Register dst, Address src) {
1438   InstructionMark im(this);
1439 #ifdef _LP64
1440   emit_byte(0x67); // addr32
1441   prefix(src, dst);
1442 #endif // LP64
1443   emit_byte(0x8D);
1444   emit_operand(dst, src);
1445 }
1446 
1447 void Assembler::lock() {
1448   if (Atomics & 1) {
1449      // Emit either nothing, a NOP, or a NOP: prefix
1450      emit_byte(0x90) ;
1451   } else {
1452      emit_byte(0xF0);
1453   }
1454 }
1455 
1456 void Assembler::lzcntl(Register dst, Register src) {
1457   assert(UseCountLeadingZerosInstruction, "encoding is treated as BSR");
1458   emit_byte(0xF3);
1459   int encode = prefix_and_encode(dst->encoding(), src->encoding());
1460   emit_byte(0x0F);
1461   emit_byte(0xBD);
1462   emit_byte(0xC0 | encode);
1463 }
1464 
1465 // Emit mfence instruction
1466 void Assembler::mfence() {
1467   NOT_LP64(assert(VM_Version::supports_sse2(), "unsupported");)
1468   emit_byte( 0x0F );
1469   emit_byte( 0xAE );
1470   emit_byte( 0xF0 );
1471 }
1472 
1473 void Assembler::mov(Register dst, Register src) {
1474   LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
1475 }
1476 
1477 void Assembler::movapd(XMMRegister dst, XMMRegister src) {
1478   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1479   int dstenc = dst->encoding();
1480   int srcenc = src->encoding();
1481   emit_byte(0x66);
1482   if (dstenc < 8) {
1483     if (srcenc >= 8) {
1484       prefix(REX_B);

3695   emit_arith(0x03, 0xC0, dst, src);
3696 }
3697 
3698 void Assembler::andq(Register dst, int32_t imm32) {
3699   (void) prefixq_and_encode(dst->encoding());
3700   emit_arith(0x81, 0xE0, dst, imm32);
3701 }
3702 
3703 void Assembler::andq(Register dst, Address src) {
3704   InstructionMark im(this);
3705   prefixq(src, dst);
3706   emit_byte(0x23);
3707   emit_operand(dst, src);
3708 }
3709 
3710 void Assembler::andq(Register dst, Register src) {
3711   (int) prefixq_and_encode(dst->encoding(), src->encoding());
3712   emit_arith(0x23, 0xC0, dst, src);
3713 }
3714 
3715 void Assembler::bsfq(Register dst, Register src) {
3716   int encode = prefixq_and_encode(dst->encoding(), src->encoding());
3717   emit_byte(0x0F);
3718   emit_byte(0xBC);
3719   emit_byte(0xC0 | encode);
3720 }
3721 
3722 void Assembler::bsrq(Register dst, Register src) {
3723   assert(UseCountLeadingZerosInstruction == false, "encoding is treated as LZCNT");
3724   int encode = prefixq_and_encode(dst->encoding(), src->encoding());
3725   emit_byte(0x0F);
3726   emit_byte(0xBD);
3727   emit_byte(0xC0 | encode);
3728 }
3729 
3730 void Assembler::bswapq(Register reg) {
3731   int encode = prefixq_and_encode(reg->encoding());
3732   emit_byte(0x0F);
3733   emit_byte(0xC8 | encode);
3734 }
3735 
3736 void Assembler::cdqq() {
3737   prefix(REX_W);
3738   emit_byte(0x99);
3739 }
3740 
3741 void Assembler::clflush(Address adr) {
3742   prefix(adr);
3743   emit_byte(0x0F);
3744   emit_byte(0xAE);
3745   emit_operand(rdi, adr);
3746 }
3747 
3748 void Assembler::cmovq(Condition cc, Register dst, Register src) {
3749   int encode = prefixq_and_encode(dst->encoding(), src->encoding());

3963   emit_operand(rax, dst, 4);
3964   emit_data((int)imm32, rspec, narrow_oop_operand);
3965 }
3966 
3967 void Assembler::cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec) {
3968   InstructionMark im(this);
3969   int encode = prefix_and_encode(src1->encoding());
3970   emit_byte(0x81);
3971   emit_byte(0xF8 | encode);
3972   emit_data((int)imm32, rspec, narrow_oop_operand);
3973 }
3974 
3975 void Assembler::cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec) {
3976   InstructionMark im(this);
3977   prefix(src1);
3978   emit_byte(0x81);
3979   emit_operand(rax, src1, 4);
3980   emit_data((int)imm32, rspec, narrow_oop_operand);
3981 }
3982 
3983 void Assembler::lzcntq(Register dst, Register src) {
3984   assert(UseCountLeadingZerosInstruction, "encoding is treated as BSR");
3985   emit_byte(0xF3);
3986   int encode = prefixq_and_encode(dst->encoding(), src->encoding());
3987   emit_byte(0x0F);
3988   emit_byte(0xBD);
3989   emit_byte(0xC0 | encode);
3990 }
3991 
3992 void Assembler::movdq(XMMRegister dst, Register src) {
3993   // table D-1 says MMX/SSE2
3994   NOT_LP64(assert(VM_Version::supports_sse2() || VM_Version::supports_mmx(), ""));
3995   emit_byte(0x66);
3996   int encode = prefixq_and_encode(dst->encoding(), src->encoding());
3997   emit_byte(0x0F);
3998   emit_byte(0x6E);
3999   emit_byte(0xC0 | encode);
4000 }
4001 
4002 void Assembler::movdq(Register dst, XMMRegister src) {
4003   // table D-1 says MMX/SSE2
4004   NOT_LP64(assert(VM_Version::supports_sse2() || VM_Version::supports_mmx(), ""));
4005   emit_byte(0x66);
4006   // swap src/dst to get correct prefix
4007   int encode = prefixq_and_encode(src->encoding(), dst->encoding());
4008   emit_byte(0x0F);
4009   emit_byte(0x7E);
4010   emit_byte(0xC0 | encode);
4011 }