740 void addsd(XMMRegister dst, Address src);
741 void addsd(XMMRegister dst, XMMRegister src);
742
743 // Add Scalar Single-Precision Floating-Point Values
744 void addss(XMMRegister dst, Address src);
745 void addss(XMMRegister dst, XMMRegister src);
746
747 void andl(Register dst, int32_t imm32);
748 void andl(Register dst, Address src);
749 void andl(Register dst, Register src);
750
751 void andq(Register dst, int32_t imm32);
752 void andq(Register dst, Address src);
753 void andq(Register dst, Register src);
754
755
756 // Bitwise Logical AND of Packed Double-Precision Floating-Point Values
757 void andpd(XMMRegister dst, Address src);
758 void andpd(XMMRegister dst, XMMRegister src);
759
760 void bswapl(Register reg);
761
762 void bswapq(Register reg);
763
764 void call(Label& L, relocInfo::relocType rtype);
765 void call(Register reg); // push pc; pc <- reg
766 void call(Address adr); // push pc; pc <- adr
767
768 void cdql();
769
770 void cdqq();
771
772 void cld() { emit_byte(0xfc); }
773
774 void clflush(Address adr);
775
776 void cmovl(Condition cc, Register dst, Register src);
777 void cmovl(Condition cc, Register dst, Address src);
778
779 void cmovq(Condition cc, Register dst, Register src);
1044 // Unconditional 8-bit offset jump to L.
1045 // WARNING: be very careful using this for forward jumps. If the label is
1046 // not bound within an 8-bit offset of this instruction, a run-time error
1047 // will occur.
1048 void jmpb(Label& L);
1049
1050 void ldmxcsr( Address src );
1051
1052 void leal(Register dst, Address src);
1053
1054 void leaq(Register dst, Address src);
1055
1056 void lfence() {
1057 emit_byte(0x0F);
1058 emit_byte(0xAE);
1059 emit_byte(0xE8);
1060 }
1061
1062 void lock();
1063
1064 enum Membar_mask_bits {
1065 StoreStore = 1 << 3,
1066 LoadStore = 1 << 2,
1067 StoreLoad = 1 << 1,
1068 LoadLoad = 1 << 0
1069 };
1070
1071 // Serializes memory and blows flags
1072 void membar(Membar_mask_bits order_constraint) {
1073 if (os::is_MP()) {
1074 // We only have to handle StoreLoad
1075 if (order_constraint & StoreLoad) {
1076 // All usable chips support "locked" instructions which suffice
1077 // as barriers, and are much faster than the alternative of
1078 // using cpuid instruction. We use here a locked add [esp],0.
1079 // This is conveniently otherwise a no-op except for blowing
1080 // flags.
1081 // Any change to this code may need to revisit other places in
1082 // the code where this idiom is used, in particular the
1083 // orderAccess code.
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740 void addsd(XMMRegister dst, Address src);
741 void addsd(XMMRegister dst, XMMRegister src);
742
743 // Add Scalar Single-Precision Floating-Point Values
744 void addss(XMMRegister dst, Address src);
745 void addss(XMMRegister dst, XMMRegister src);
746
747 void andl(Register dst, int32_t imm32);
748 void andl(Register dst, Address src);
749 void andl(Register dst, Register src);
750
751 void andq(Register dst, int32_t imm32);
752 void andq(Register dst, Address src);
753 void andq(Register dst, Register src);
754
755
756 // Bitwise Logical AND of Packed Double-Precision Floating-Point Values
757 void andpd(XMMRegister dst, Address src);
758 void andpd(XMMRegister dst, XMMRegister src);
759
760 void bsfl(Register dst, Register src);
761
762 #ifdef _LP64
763 void bsfq(Register dst, Register src);
764 #endif
765
766 void bsrl(Register dst, Register src);
767
768 #ifdef _LP64
769 void bsrq(Register dst, Register src);
770 #endif
771
772 void bswapl(Register reg);
773
774 void bswapq(Register reg);
775
776 void call(Label& L, relocInfo::relocType rtype);
777 void call(Register reg); // push pc; pc <- reg
778 void call(Address adr); // push pc; pc <- adr
779
780 void cdql();
781
782 void cdqq();
783
784 void cld() { emit_byte(0xfc); }
785
786 void clflush(Address adr);
787
788 void cmovl(Condition cc, Register dst, Register src);
789 void cmovl(Condition cc, Register dst, Address src);
790
791 void cmovq(Condition cc, Register dst, Register src);
1056 // Unconditional 8-bit offset jump to L.
1057 // WARNING: be very careful using this for forward jumps. If the label is
1058 // not bound within an 8-bit offset of this instruction, a run-time error
1059 // will occur.
1060 void jmpb(Label& L);
1061
1062 void ldmxcsr( Address src );
1063
1064 void leal(Register dst, Address src);
1065
1066 void leaq(Register dst, Address src);
1067
1068 void lfence() {
1069 emit_byte(0x0F);
1070 emit_byte(0xAE);
1071 emit_byte(0xE8);
1072 }
1073
1074 void lock();
1075
1076 void lzcntl(Register dst, Register src);
1077
1078 #ifdef _LP64
1079 void lzcntq(Register dst, Register src);
1080 #endif
1081
1082 enum Membar_mask_bits {
1083 StoreStore = 1 << 3,
1084 LoadStore = 1 << 2,
1085 StoreLoad = 1 << 1,
1086 LoadLoad = 1 << 0
1087 };
1088
1089 // Serializes memory and blows flags
1090 void membar(Membar_mask_bits order_constraint) {
1091 if (os::is_MP()) {
1092 // We only have to handle StoreLoad
1093 if (order_constraint & StoreLoad) {
1094 // All usable chips support "locked" instructions which suffice
1095 // as barriers, and are much faster than the alternative of
1096 // using cpuid instruction. We use here a locked add [esp],0.
1097 // This is conveniently otherwise a no-op except for blowing
1098 // flags.
1099 // Any change to this code may need to revisit other places in
1100 // the code where this idiom is used, in particular the
1101 // orderAccess code.
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