267 }
268
269 if (UseSSE < 3) {
270 _cpuFeatures &= ~CPU_SSE3;
271 _cpuFeatures &= ~CPU_SSSE3;
272 _cpuFeatures &= ~CPU_SSE4A;
273 }
274
275 if (UseSSE < 2)
276 _cpuFeatures &= ~CPU_SSE2;
277
278 if (UseSSE < 1)
279 _cpuFeatures &= ~CPU_SSE;
280
281 if (logical_processors_per_package() == 1) {
282 // HT processor could be installed on a system which doesn't support HT.
283 _cpuFeatures &= ~CPU_HT;
284 }
285
286 char buf[256];
287 jio_snprintf(buf, sizeof(buf), "(%u cores per cpu, %u threads per core) family %d model %d stepping %d%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
288 cores_per_cpu(), threads_per_core(),
289 cpu_family(), _model, _stepping,
290 (supports_cmov() ? ", cmov" : ""),
291 (supports_cmpxchg8() ? ", cx8" : ""),
292 (supports_fxsr() ? ", fxsr" : ""),
293 (supports_mmx() ? ", mmx" : ""),
294 (supports_sse() ? ", sse" : ""),
295 (supports_sse2() ? ", sse2" : ""),
296 (supports_sse3() ? ", sse3" : ""),
297 (supports_ssse3()? ", ssse3": ""),
298 (supports_sse4_1() ? ", sse4.1" : ""),
299 (supports_sse4_2() ? ", sse4.2" : ""),
300 (supports_popcnt() ? ", popcnt" : ""),
301 (supports_mmx_ext() ? ", mmxext" : ""),
302 (supports_3dnow() ? ", 3dnow" : ""),
303 (supports_3dnow2() ? ", 3dnowext" : ""),
304 (supports_sse4a() ? ", sse4a": ""),
305 (supports_ht() ? ", ht": ""));
306 _features_str = strdup(buf);
307
308 // UseSSE is set to the smaller of what hardware supports and what
309 // the command line requires. I.e., you cannot set UseSSE to 2 on
310 // older Pentiums which do not support it.
311 if( UseSSE > 4 ) UseSSE=4;
312 if( UseSSE < 0 ) UseSSE=0;
313 if( !supports_sse4_1() ) // Drop to 3 if no SSE4 support
314 UseSSE = MIN2((intx)3,UseSSE);
315 if( !supports_sse3() ) // Drop to 2 if no SSE3 support
316 UseSSE = MIN2((intx)2,UseSSE);
317 if( !supports_sse2() ) // Drop to 1 if no SSE2 support
318 UseSSE = MIN2((intx)1,UseSSE);
319 if( !supports_sse () ) // Drop to 0 if no SSE support
320 UseSSE = 0;
321
322 // On new cpus instructions which update whole XMM register should be used
323 // to prevent partial register stall due to dependencies on high half.
347 if( supports_sse4a() ) {
348 UseXmmRegToRegMoveAll = true; // use movaps, movapd only on '10h'
349 } else {
350 UseXmmRegToRegMoveAll = false;
351 }
352 }
353 if( FLAG_IS_DEFAULT(UseXmmI2F) ) {
354 if( supports_sse4a() ) {
355 UseXmmI2F = true;
356 } else {
357 UseXmmI2F = false;
358 }
359 }
360 if( FLAG_IS_DEFAULT(UseXmmI2D) ) {
361 if( supports_sse4a() ) {
362 UseXmmI2D = true;
363 } else {
364 UseXmmI2D = false;
365 }
366 }
367 }
368
369 if( is_intel() ) { // Intel cpus specific settings
370 if( FLAG_IS_DEFAULT(UseStoreImmI16) ) {
371 UseStoreImmI16 = false; // don't use it on Intel cpus
372 }
373 if( cpu_family() == 6 || cpu_family() == 15 ) {
374 if( FLAG_IS_DEFAULT(UseAddressNop) ) {
375 // Use it on all Intel cpus starting from PentiumPro
376 UseAddressNop = true;
377 }
378 }
379 if( FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper) ) {
380 UseXmmLoadAndClearUpper = true; // use movsd on all Intel cpus
381 }
382 if( FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll) ) {
383 if( supports_sse3() ) {
384 UseXmmRegToRegMoveAll = true; // use movaps, movapd on new Intel cpus
385 } else {
386 UseXmmRegToRegMoveAll = false;
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267 }
268
269 if (UseSSE < 3) {
270 _cpuFeatures &= ~CPU_SSE3;
271 _cpuFeatures &= ~CPU_SSSE3;
272 _cpuFeatures &= ~CPU_SSE4A;
273 }
274
275 if (UseSSE < 2)
276 _cpuFeatures &= ~CPU_SSE2;
277
278 if (UseSSE < 1)
279 _cpuFeatures &= ~CPU_SSE;
280
281 if (logical_processors_per_package() == 1) {
282 // HT processor could be installed on a system which doesn't support HT.
283 _cpuFeatures &= ~CPU_HT;
284 }
285
286 char buf[256];
287 jio_snprintf(buf, sizeof(buf), "(%u cores per cpu, %u threads per core) family %d model %d stepping %d%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
288 cores_per_cpu(), threads_per_core(),
289 cpu_family(), _model, _stepping,
290 (supports_cmov() ? ", cmov" : ""),
291 (supports_cmpxchg8() ? ", cx8" : ""),
292 (supports_fxsr() ? ", fxsr" : ""),
293 (supports_mmx() ? ", mmx" : ""),
294 (supports_sse() ? ", sse" : ""),
295 (supports_sse2() ? ", sse2" : ""),
296 (supports_sse3() ? ", sse3" : ""),
297 (supports_ssse3()? ", ssse3": ""),
298 (supports_sse4_1() ? ", sse4.1" : ""),
299 (supports_sse4_2() ? ", sse4.2" : ""),
300 (supports_popcnt() ? ", popcnt" : ""),
301 (supports_mmx_ext() ? ", mmxext" : ""),
302 (supports_3dnow() ? ", 3dnow" : ""),
303 (supports_3dnow2() ? ", 3dnowext" : ""),
304 (supports_lzcnt() ? ", lzcnt": ""),
305 (supports_sse4a() ? ", sse4a": ""),
306 (supports_ht() ? ", ht": ""));
307 _features_str = strdup(buf);
308
309 // UseSSE is set to the smaller of what hardware supports and what
310 // the command line requires. I.e., you cannot set UseSSE to 2 on
311 // older Pentiums which do not support it.
312 if( UseSSE > 4 ) UseSSE=4;
313 if( UseSSE < 0 ) UseSSE=0;
314 if( !supports_sse4_1() ) // Drop to 3 if no SSE4 support
315 UseSSE = MIN2((intx)3,UseSSE);
316 if( !supports_sse3() ) // Drop to 2 if no SSE3 support
317 UseSSE = MIN2((intx)2,UseSSE);
318 if( !supports_sse2() ) // Drop to 1 if no SSE2 support
319 UseSSE = MIN2((intx)1,UseSSE);
320 if( !supports_sse () ) // Drop to 0 if no SSE support
321 UseSSE = 0;
322
323 // On new cpus instructions which update whole XMM register should be used
324 // to prevent partial register stall due to dependencies on high half.
348 if( supports_sse4a() ) {
349 UseXmmRegToRegMoveAll = true; // use movaps, movapd only on '10h'
350 } else {
351 UseXmmRegToRegMoveAll = false;
352 }
353 }
354 if( FLAG_IS_DEFAULT(UseXmmI2F) ) {
355 if( supports_sse4a() ) {
356 UseXmmI2F = true;
357 } else {
358 UseXmmI2F = false;
359 }
360 }
361 if( FLAG_IS_DEFAULT(UseXmmI2D) ) {
362 if( supports_sse4a() ) {
363 UseXmmI2D = true;
364 } else {
365 UseXmmI2D = false;
366 }
367 }
368
369 // Use count leading zeros count instruction if available.
370 if (supports_lzcnt()) {
371 if (FLAG_IS_DEFAULT(UseCountLeadingZerosInstruction)) {
372 UseCountLeadingZerosInstruction = true;
373 }
374 }
375 }
376
377 if( is_intel() ) { // Intel cpus specific settings
378 if( FLAG_IS_DEFAULT(UseStoreImmI16) ) {
379 UseStoreImmI16 = false; // don't use it on Intel cpus
380 }
381 if( cpu_family() == 6 || cpu_family() == 15 ) {
382 if( FLAG_IS_DEFAULT(UseAddressNop) ) {
383 // Use it on all Intel cpus starting from PentiumPro
384 UseAddressNop = true;
385 }
386 }
387 if( FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper) ) {
388 UseXmmLoadAndClearUpper = true; // use movsd on all Intel cpus
389 }
390 if( FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll) ) {
391 if( supports_sse3() ) {
392 UseXmmRegToRegMoveAll = true; // use movaps, movapd on new Intel cpus
393 } else {
394 UseXmmRegToRegMoveAll = false;
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