1 //
2 // Copyright 1997-2009 Sun Microsystems, Inc. All Rights Reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
9 // This code is distributed in the hope that it will be useful, but WITHOUT
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
15 // You should have received a copy of the GNU General Public License version
16 // 2 along with this work; if not, write to the Free Software Foundation,
17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 //
19 // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
20 // CA 95054 USA or visit www.sun.com if you need additional information or
21 // have any questions.
22 //
23 //
24
25 // X86 Architecture Description File
26
27 //----------REGISTER DEFINITION BLOCK------------------------------------------
28 // This information is used by the matcher and the register allocator to
29 // describe individual registers and classes of registers within the target
30 // archtecture.
31
32 register %{
33 //----------Architecture Description Register Definitions----------------------
34 // General Registers
35 // "reg_def" name ( register save type, C convention save type,
36 // ideal register type, encoding );
37 // Register Save Types:
38 //
39 // NS = No-Save: The register allocator assumes that these registers
40 // can be used without saving upon entry to the method, &
41 // that they do not need to be saved at call sites.
42 //
43 // SOC = Save-On-Call: The register allocator assumes that these registers
44 // can be used without saving upon entry to the method,
45 // but that they must be saved at call sites.
46 //
47 // SOE = Save-On-Entry: The register allocator assumes that these registers
48 // must be saved before using them upon entry to the
49 // method, but they do not need to be saved at call
50 // sites.
51 //
52 // AS = Always-Save: The register allocator assumes that these registers
53 // must be saved before using them upon entry to the
54 // method, & that they must be saved at call sites.
55 //
56 // Ideal Register Type is used to determine how to save & restore a
57 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
58 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
59 //
60 // The encoding number is the actual bit-pattern placed into the opcodes.
61
62 // General Registers
63 // Previously set EBX, ESI, and EDI as save-on-entry for java code
64 // Turn off SOE in java-code due to frequent use of uncommon-traps.
65 // Now that allocator is better, turn on ESI and EDI as SOE registers.
66
67 reg_def EBX(SOC, SOE, Op_RegI, 3, rbx->as_VMReg());
68 reg_def ECX(SOC, SOC, Op_RegI, 1, rcx->as_VMReg());
69 reg_def ESI(SOC, SOE, Op_RegI, 6, rsi->as_VMReg());
70 reg_def EDI(SOC, SOE, Op_RegI, 7, rdi->as_VMReg());
71 // now that adapter frames are gone EBP is always saved and restored by the prolog/epilog code
72 reg_def EBP(NS, SOE, Op_RegI, 5, rbp->as_VMReg());
73 reg_def EDX(SOC, SOC, Op_RegI, 2, rdx->as_VMReg());
74 reg_def EAX(SOC, SOC, Op_RegI, 0, rax->as_VMReg());
75 reg_def ESP( NS, NS, Op_RegI, 4, rsp->as_VMReg());
76
77 // Special Registers
78 reg_def EFLAGS(SOC, SOC, 0, 8, VMRegImpl::Bad());
79
80 // Float registers. We treat TOS/FPR0 special. It is invisible to the
81 // allocator, and only shows up in the encodings.
82 reg_def FPR0L( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad());
83 reg_def FPR0H( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad());
84 // Ok so here's the trick FPR1 is really st(0) except in the midst
85 // of emission of assembly for a machnode. During the emission the fpu stack
86 // is pushed making FPR1 == st(1) temporarily. However at any safepoint
87 // the stack will not have this element so FPR1 == st(0) from the
88 // oopMap viewpoint. This same weirdness with numbering causes
89 // instruction encoding to have to play games with the register
90 // encode to correct for this 0/1 issue. See MachSpillCopyNode::implementation
91 // where it does flt->flt moves to see an example
92 //
93 reg_def FPR1L( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg());
94 reg_def FPR1H( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg()->next());
95 reg_def FPR2L( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg());
96 reg_def FPR2H( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg()->next());
97 reg_def FPR3L( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg());
98 reg_def FPR3H( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg()->next());
99 reg_def FPR4L( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg());
100 reg_def FPR4H( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg()->next());
101 reg_def FPR5L( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg());
102 reg_def FPR5H( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg()->next());
103 reg_def FPR6L( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg());
104 reg_def FPR6H( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg()->next());
105 reg_def FPR7L( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg());
106 reg_def FPR7H( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg()->next());
107
108 // XMM registers. 128-bit registers or 4 words each, labeled a-d.
109 // Word a in each register holds a Float, words ab hold a Double.
110 // We currently do not use the SIMD capabilities, so registers cd
111 // are unused at the moment.
112 reg_def XMM0a( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg());
113 reg_def XMM0b( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()->next());
114 reg_def XMM1a( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg());
115 reg_def XMM1b( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()->next());
116 reg_def XMM2a( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg());
117 reg_def XMM2b( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()->next());
118 reg_def XMM3a( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg());
119 reg_def XMM3b( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()->next());
120 reg_def XMM4a( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg());
121 reg_def XMM4b( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()->next());
122 reg_def XMM5a( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg());
123 reg_def XMM5b( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()->next());
124 reg_def XMM6a( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg());
125 reg_def XMM6b( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()->next());
126 reg_def XMM7a( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg());
127 reg_def XMM7b( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()->next());
128
129 // Specify priority of register selection within phases of register
130 // allocation. Highest priority is first. A useful heuristic is to
131 // give registers a low priority when they are required by machine
132 // instructions, like EAX and EDX. Registers which are used as
133 // pairs must fall on an even boundary (witness the FPR#L's in this list).
134 // For the Intel integer registers, the equivalent Long pairs are
135 // EDX:EAX, EBX:ECX, and EDI:EBP.
136 alloc_class chunk0( ECX, EBX, EBP, EDI, EAX, EDX, ESI, ESP,
137 FPR0L, FPR0H, FPR1L, FPR1H, FPR2L, FPR2H,
138 FPR3L, FPR3H, FPR4L, FPR4H, FPR5L, FPR5H,
139 FPR6L, FPR6H, FPR7L, FPR7H );
140
141 alloc_class chunk1( XMM0a, XMM0b,
142 XMM1a, XMM1b,
143 XMM2a, XMM2b,
144 XMM3a, XMM3b,
145 XMM4a, XMM4b,
146 XMM5a, XMM5b,
147 XMM6a, XMM6b,
148 XMM7a, XMM7b, EFLAGS);
149
150
151 //----------Architecture Description Register Classes--------------------------
152 // Several register classes are automatically defined based upon information in
153 // this architecture description.
154 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ )
155 // 2) reg_class compiler_method_oop_reg ( /* as def'd in frame section */ )
156 // 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ )
157 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
158 //
159 // Class for all registers
160 reg_class any_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX, ESP);
161 // Class for general registers
162 reg_class e_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX);
163 // Class for general registers which may be used for implicit null checks on win95
164 // Also safe for use by tailjump. We don't want to allocate in rbp,
165 reg_class e_reg_no_rbp(EAX, EDX, EDI, ESI, ECX, EBX);
166 // Class of "X" registers
167 reg_class x_reg(EBX, ECX, EDX, EAX);
168 // Class of registers that can appear in an address with no offset.
169 // EBP and ESP require an extra instruction byte for zero offset.
170 // Used in fast-unlock
171 reg_class p_reg(EDX, EDI, ESI, EBX);
172 // Class for general registers not including ECX
173 reg_class ncx_reg(EAX, EDX, EBP, EDI, ESI, EBX);
174 // Class for general registers not including EAX
175 reg_class nax_reg(EDX, EDI, ESI, ECX, EBX);
176 // Class for general registers not including EAX or EBX.
177 reg_class nabx_reg(EDX, EDI, ESI, ECX, EBP);
178 // Class of EAX (for multiply and divide operations)
179 reg_class eax_reg(EAX);
180 // Class of EBX (for atomic add)
181 reg_class ebx_reg(EBX);
182 // Class of ECX (for shift and JCXZ operations and cmpLTMask)
183 reg_class ecx_reg(ECX);
184 // Class of EDX (for multiply and divide operations)
185 reg_class edx_reg(EDX);
186 // Class of EDI (for synchronization)
187 reg_class edi_reg(EDI);
188 // Class of ESI (for synchronization)
189 reg_class esi_reg(ESI);
190 // Singleton class for interpreter's stack pointer
191 reg_class ebp_reg(EBP);
192 // Singleton class for stack pointer
193 reg_class sp_reg(ESP);
194 // Singleton class for instruction pointer
195 // reg_class ip_reg(EIP);
196 // Singleton class for condition codes
197 reg_class int_flags(EFLAGS);
198 // Class of integer register pairs
199 reg_class long_reg( EAX,EDX, ECX,EBX, EBP,EDI );
200 // Class of integer register pairs that aligns with calling convention
201 reg_class eadx_reg( EAX,EDX );
202 reg_class ebcx_reg( ECX,EBX );
203 // Not AX or DX, used in divides
204 reg_class nadx_reg( EBX,ECX,ESI,EDI,EBP );
205
206 // Floating point registers. Notice FPR0 is not a choice.
207 // FPR0 is not ever allocated; we use clever encodings to fake
208 // a 2-address instructions out of Intels FP stack.
209 reg_class flt_reg( FPR1L,FPR2L,FPR3L,FPR4L,FPR5L,FPR6L,FPR7L );
210
211 // make a register class for SSE registers
212 reg_class xmm_reg(XMM0a, XMM1a, XMM2a, XMM3a, XMM4a, XMM5a, XMM6a, XMM7a);
213
214 // make a double register class for SSE2 registers
215 reg_class xdb_reg(XMM0a,XMM0b, XMM1a,XMM1b, XMM2a,XMM2b, XMM3a,XMM3b,
216 XMM4a,XMM4b, XMM5a,XMM5b, XMM6a,XMM6b, XMM7a,XMM7b );
217
218 reg_class dbl_reg( FPR1L,FPR1H, FPR2L,FPR2H, FPR3L,FPR3H,
219 FPR4L,FPR4H, FPR5L,FPR5H, FPR6L,FPR6H,
220 FPR7L,FPR7H );
221
222 reg_class flt_reg0( FPR1L );
223 reg_class dbl_reg0( FPR1L,FPR1H );
224 reg_class dbl_reg1( FPR2L,FPR2H );
225 reg_class dbl_notreg0( FPR2L,FPR2H, FPR3L,FPR3H, FPR4L,FPR4H,
226 FPR5L,FPR5H, FPR6L,FPR6H, FPR7L,FPR7H );
227
228 // XMM6 and XMM7 could be used as temporary registers for long, float and
229 // double values for SSE2.
230 reg_class xdb_reg6( XMM6a,XMM6b );
231 reg_class xdb_reg7( XMM7a,XMM7b );
232 %}
233
234
235 //----------SOURCE BLOCK-------------------------------------------------------
236 // This is a block of C++ code which provides values, functions, and
237 // definitions necessary in the rest of the architecture description
238 source %{
239 #define RELOC_IMM32 Assembler::imm_operand
240 #define RELOC_DISP32 Assembler::disp32_operand
241
242 #define __ _masm.
243
244 // How to find the high register of a Long pair, given the low register
245 #define HIGH_FROM_LOW(x) ((x)+2)
246
247 // These masks are used to provide 128-bit aligned bitmasks to the XMM
248 // instructions, to allow sign-masking or sign-bit flipping. They allow
249 // fast versions of NegF/NegD and AbsF/AbsD.
250
251 // Note: 'double' and 'long long' have 32-bits alignment on x86.
252 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) {
253 // Use the expression (adr)&(~0xF) to provide 128-bits aligned address
254 // of 128-bits operands for SSE instructions.
255 jlong *operand = (jlong*)(((uintptr_t)adr)&((uintptr_t)(~0xF)));
256 // Store the value to a 128-bits operand.
257 operand[0] = lo;
258 operand[1] = hi;
259 return operand;
260 }
261
262 // Buffer for 128-bits masks used by SSE instructions.
263 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment)
264
265 // Static initialization during VM startup.
266 static jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF));
267 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF));
268 static jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], CONST64(0x8000000080000000), CONST64(0x8000000080000000));
269 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], CONST64(0x8000000000000000), CONST64(0x8000000000000000));
270
271 // !!!!! Special hack to get all type of calls to specify the byte offset
272 // from the start of the call to the point where the return address
273 // will point.
274 int MachCallStaticJavaNode::ret_addr_offset() {
275 return 5 + (Compile::current()->in_24_bit_fp_mode() ? 6 : 0); // 5 bytes from start of call to where return address points
276 }
277
278 int MachCallDynamicJavaNode::ret_addr_offset() {
279 return 10 + (Compile::current()->in_24_bit_fp_mode() ? 6 : 0); // 10 bytes from start of call to where return address points
280 }
281
282 static int sizeof_FFree_Float_Stack_All = -1;
283
284 int MachCallRuntimeNode::ret_addr_offset() {
285 assert(sizeof_FFree_Float_Stack_All != -1, "must have been emitted already");
286 return sizeof_FFree_Float_Stack_All + 5 + (Compile::current()->in_24_bit_fp_mode() ? 6 : 0);
287 }
288
289 // Indicate if the safepoint node needs the polling page as an input.
290 // Since x86 does have absolute addressing, it doesn't.
291 bool SafePointNode::needs_polling_address_input() {
292 return false;
293 }
294
295 //
296 // Compute padding required for nodes which need alignment
297 //
298
299 // The address of the call instruction needs to be 4-byte aligned to
300 // ensure that it does not span a cache line so that it can be patched.
301 int CallStaticJavaDirectNode::compute_padding(int current_offset) const {
302 if (Compile::current()->in_24_bit_fp_mode())
303 current_offset += 6; // skip fldcw in pre_call_FPU, if any
304 current_offset += 1; // skip call opcode byte
305 return round_to(current_offset, alignment_required()) - current_offset;
306 }
307
308 // The address of the call instruction needs to be 4-byte aligned to
309 // ensure that it does not span a cache line so that it can be patched.
310 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const {
311 if (Compile::current()->in_24_bit_fp_mode())
312 current_offset += 6; // skip fldcw in pre_call_FPU, if any
313 current_offset += 5; // skip MOV instruction
314 current_offset += 1; // skip call opcode byte
315 return round_to(current_offset, alignment_required()) - current_offset;
316 }
317
318 #ifndef PRODUCT
319 void MachBreakpointNode::format( PhaseRegAlloc *, outputStream* st ) const {
320 st->print("INT3");
321 }
322 #endif
323
324 // EMIT_RM()
325 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) {
326 unsigned char c = (unsigned char)((f1 << 6) | (f2 << 3) | f3);
327 *(cbuf.code_end()) = c;
328 cbuf.set_code_end(cbuf.code_end() + 1);
329 }
330
331 // EMIT_CC()
332 void emit_cc(CodeBuffer &cbuf, int f1, int f2) {
333 unsigned char c = (unsigned char)( f1 | f2 );
334 *(cbuf.code_end()) = c;
335 cbuf.set_code_end(cbuf.code_end() + 1);
336 }
337
338 // EMIT_OPCODE()
339 void emit_opcode(CodeBuffer &cbuf, int code) {
340 *(cbuf.code_end()) = (unsigned char)code;
341 cbuf.set_code_end(cbuf.code_end() + 1);
342 }
343
344 // EMIT_OPCODE() w/ relocation information
345 void emit_opcode(CodeBuffer &cbuf, int code, relocInfo::relocType reloc, int offset = 0) {
346 cbuf.relocate(cbuf.inst_mark() + offset, reloc);
347 emit_opcode(cbuf, code);
348 }
349
350 // EMIT_D8()
351 void emit_d8(CodeBuffer &cbuf, int d8) {
352 *(cbuf.code_end()) = (unsigned char)d8;
353 cbuf.set_code_end(cbuf.code_end() + 1);
354 }
355
356 // EMIT_D16()
357 void emit_d16(CodeBuffer &cbuf, int d16) {
358 *((short *)(cbuf.code_end())) = d16;
359 cbuf.set_code_end(cbuf.code_end() + 2);
360 }
361
362 // EMIT_D32()
363 void emit_d32(CodeBuffer &cbuf, int d32) {
364 *((int *)(cbuf.code_end())) = d32;
365 cbuf.set_code_end(cbuf.code_end() + 4);
366 }
367
368 // emit 32 bit value and construct relocation entry from relocInfo::relocType
369 void emit_d32_reloc(CodeBuffer &cbuf, int d32, relocInfo::relocType reloc,
370 int format) {
371 cbuf.relocate(cbuf.inst_mark(), reloc, format);
372
373 *((int *)(cbuf.code_end())) = d32;
374 cbuf.set_code_end(cbuf.code_end() + 4);
375 }
376
377 // emit 32 bit value and construct relocation entry from RelocationHolder
378 void emit_d32_reloc(CodeBuffer &cbuf, int d32, RelocationHolder const& rspec,
379 int format) {
380 #ifdef ASSERT
381 if (rspec.reloc()->type() == relocInfo::oop_type && d32 != 0 && d32 != (int)Universe::non_oop_word()) {
382 assert(oop(d32)->is_oop() && oop(d32)->is_perm(), "cannot embed non-perm oops in code");
383 }
384 #endif
385 cbuf.relocate(cbuf.inst_mark(), rspec, format);
386
387 *((int *)(cbuf.code_end())) = d32;
388 cbuf.set_code_end(cbuf.code_end() + 4);
389 }
390
391 // Access stack slot for load or store
392 void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp) {
393 emit_opcode( cbuf, opcode ); // (e.g., FILD [ESP+src])
394 if( -128 <= disp && disp <= 127 ) {
395 emit_rm( cbuf, 0x01, rm_field, ESP_enc ); // R/M byte
396 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
397 emit_d8 (cbuf, disp); // Displacement // R/M byte
398 } else {
399 emit_rm( cbuf, 0x02, rm_field, ESP_enc ); // R/M byte
400 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
401 emit_d32(cbuf, disp); // Displacement // R/M byte
402 }
403 }
404
405 // eRegI ereg, memory mem) %{ // emit_reg_mem
406 void encode_RegMem( CodeBuffer &cbuf, int reg_encoding, int base, int index, int scale, int displace, bool displace_is_oop ) {
407 // There is no index & no scale, use form without SIB byte
408 if ((index == 0x4) &&
409 (scale == 0) && (base != ESP_enc)) {
410 // If no displacement, mode is 0x0; unless base is [EBP]
411 if ( (displace == 0) && (base != EBP_enc) ) {
412 emit_rm(cbuf, 0x0, reg_encoding, base);
413 }
414 else { // If 8-bit displacement, mode 0x1
415 if ((displace >= -128) && (displace <= 127)
416 && !(displace_is_oop) ) {
417 emit_rm(cbuf, 0x1, reg_encoding, base);
418 emit_d8(cbuf, displace);
419 }
420 else { // If 32-bit displacement
421 if (base == -1) { // Special flag for absolute address
422 emit_rm(cbuf, 0x0, reg_encoding, 0x5);
423 // (manual lies; no SIB needed here)
424 if ( displace_is_oop ) {
425 emit_d32_reloc(cbuf, displace, relocInfo::oop_type, 1);
426 } else {
427 emit_d32 (cbuf, displace);
428 }
429 }
430 else { // Normal base + offset
431 emit_rm(cbuf, 0x2, reg_encoding, base);
432 if ( displace_is_oop ) {
433 emit_d32_reloc(cbuf, displace, relocInfo::oop_type, 1);
434 } else {
435 emit_d32 (cbuf, displace);
436 }
437 }
438 }
439 }
440 }
441 else { // Else, encode with the SIB byte
442 // If no displacement, mode is 0x0; unless base is [EBP]
443 if (displace == 0 && (base != EBP_enc)) { // If no displacement
444 emit_rm(cbuf, 0x0, reg_encoding, 0x4);
445 emit_rm(cbuf, scale, index, base);
446 }
447 else { // If 8-bit displacement, mode 0x1
448 if ((displace >= -128) && (displace <= 127)
449 && !(displace_is_oop) ) {
450 emit_rm(cbuf, 0x1, reg_encoding, 0x4);
451 emit_rm(cbuf, scale, index, base);
452 emit_d8(cbuf, displace);
453 }
454 else { // If 32-bit displacement
455 if (base == 0x04 ) {
456 emit_rm(cbuf, 0x2, reg_encoding, 0x4);
457 emit_rm(cbuf, scale, index, 0x04);
458 } else {
459 emit_rm(cbuf, 0x2, reg_encoding, 0x4);
460 emit_rm(cbuf, scale, index, base);
461 }
462 if ( displace_is_oop ) {
463 emit_d32_reloc(cbuf, displace, relocInfo::oop_type, 1);
464 } else {
465 emit_d32 (cbuf, displace);
466 }
467 }
468 }
469 }
470 }
471
472
473 void encode_Copy( CodeBuffer &cbuf, int dst_encoding, int src_encoding ) {
474 if( dst_encoding == src_encoding ) {
475 // reg-reg copy, use an empty encoding
476 } else {
477 emit_opcode( cbuf, 0x8B );
478 emit_rm(cbuf, 0x3, dst_encoding, src_encoding );
479 }
480 }
481
482 void encode_CopyXD( CodeBuffer &cbuf, int dst_encoding, int src_encoding ) {
483 if( dst_encoding == src_encoding ) {
484 // reg-reg copy, use an empty encoding
485 } else {
486 MacroAssembler _masm(&cbuf);
487
488 __ movdqa(as_XMMRegister(dst_encoding), as_XMMRegister(src_encoding));
489 }
490 }
491
492
493 //=============================================================================
494 #ifndef PRODUCT
495 void MachPrologNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
496 Compile* C = ra_->C;
497 if( C->in_24_bit_fp_mode() ) {
498 st->print("FLDCW 24 bit fpu control word");
499 st->print_cr(""); st->print("\t");
500 }
501
502 int framesize = C->frame_slots() << LogBytesPerInt;
503 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
504 // Remove two words for return addr and rbp,
505 framesize -= 2*wordSize;
506
507 // Calls to C2R adapters often do not accept exceptional returns.
508 // We require that their callers must bang for them. But be careful, because
509 // some VM calls (such as call site linkage) can use several kilobytes of
510 // stack. But the stack safety zone should account for that.
511 // See bugs 4446381, 4468289, 4497237.
512 if (C->need_stack_bang(framesize)) {
513 st->print_cr("# stack bang"); st->print("\t");
514 }
515 st->print_cr("PUSHL EBP"); st->print("\t");
516
517 if( VerifyStackAtCalls ) { // Majik cookie to verify stack depth
518 st->print("PUSH 0xBADB100D\t# Majik cookie for stack depth check");
519 st->print_cr(""); st->print("\t");
520 framesize -= wordSize;
521 }
522
523 if ((C->in_24_bit_fp_mode() || VerifyStackAtCalls ) && framesize < 128 ) {
524 if (framesize) {
525 st->print("SUB ESP,%d\t# Create frame",framesize);
526 }
527 } else {
528 st->print("SUB ESP,%d\t# Create frame",framesize);
529 }
530 }
531 #endif
532
533
534 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
535 Compile* C = ra_->C;
536
537 if (UseSSE >= 2 && VerifyFPU) {
538 MacroAssembler masm(&cbuf);
539 masm.verify_FPU(0, "FPU stack must be clean on entry");
540 }
541
542 // WARNING: Initial instruction MUST be 5 bytes or longer so that
543 // NativeJump::patch_verified_entry will be able to patch out the entry
544 // code safely. The fldcw is ok at 6 bytes, the push to verify stack
545 // depth is ok at 5 bytes, the frame allocation can be either 3 or
546 // 6 bytes. So if we don't do the fldcw or the push then we must
547 // use the 6 byte frame allocation even if we have no frame. :-(
548 // If method sets FPU control word do it now
549 if( C->in_24_bit_fp_mode() ) {
550 MacroAssembler masm(&cbuf);
551 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
552 }
553
554 int framesize = C->frame_slots() << LogBytesPerInt;
555 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
556 // Remove two words for return addr and rbp,
557 framesize -= 2*wordSize;
558
559 // Calls to C2R adapters often do not accept exceptional returns.
560 // We require that their callers must bang for them. But be careful, because
561 // some VM calls (such as call site linkage) can use several kilobytes of
562 // stack. But the stack safety zone should account for that.
563 // See bugs 4446381, 4468289, 4497237.
564 if (C->need_stack_bang(framesize)) {
565 MacroAssembler masm(&cbuf);
566 masm.generate_stack_overflow_check(framesize);
567 }
568
569 // We always push rbp, so that on return to interpreter rbp, will be
570 // restored correctly and we can correct the stack.
571 emit_opcode(cbuf, 0x50 | EBP_enc);
572
573 if( VerifyStackAtCalls ) { // Majik cookie to verify stack depth
574 emit_opcode(cbuf, 0x68); // push 0xbadb100d
575 emit_d32(cbuf, 0xbadb100d);
576 framesize -= wordSize;
577 }
578
579 if ((C->in_24_bit_fp_mode() || VerifyStackAtCalls ) && framesize < 128 ) {
580 if (framesize) {
581 emit_opcode(cbuf, 0x83); // sub SP,#framesize
582 emit_rm(cbuf, 0x3, 0x05, ESP_enc);
583 emit_d8(cbuf, framesize);
584 }
585 } else {
586 emit_opcode(cbuf, 0x81); // sub SP,#framesize
587 emit_rm(cbuf, 0x3, 0x05, ESP_enc);
588 emit_d32(cbuf, framesize);
589 }
590 C->set_frame_complete(cbuf.code_end() - cbuf.code_begin());
591
592 #ifdef ASSERT
593 if (VerifyStackAtCalls) {
594 Label L;
595 MacroAssembler masm(&cbuf);
596 masm.push(rax);
597 masm.mov(rax, rsp);
598 masm.andptr(rax, StackAlignmentInBytes-1);
599 masm.cmpptr(rax, StackAlignmentInBytes-wordSize);
600 masm.pop(rax);
601 masm.jcc(Assembler::equal, L);
602 masm.stop("Stack is not properly aligned!");
603 masm.bind(L);
604 }
605 #endif
606
607 }
608
609 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
610 return MachNode::size(ra_); // too many variables; just compute it the hard way
611 }
612
613 int MachPrologNode::reloc() const {
614 return 0; // a large enough number
615 }
616
617 //=============================================================================
618 #ifndef PRODUCT
619 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
620 Compile *C = ra_->C;
621 int framesize = C->frame_slots() << LogBytesPerInt;
622 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
623 // Remove two words for return addr and rbp,
624 framesize -= 2*wordSize;
625
626 if( C->in_24_bit_fp_mode() ) {
627 st->print("FLDCW standard control word");
628 st->cr(); st->print("\t");
629 }
630 if( framesize ) {
631 st->print("ADD ESP,%d\t# Destroy frame",framesize);
632 st->cr(); st->print("\t");
633 }
634 st->print_cr("POPL EBP"); st->print("\t");
635 if( do_polling() && C->is_method_compilation() ) {
636 st->print("TEST PollPage,EAX\t! Poll Safepoint");
637 st->cr(); st->print("\t");
638 }
639 }
640 #endif
641
642 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
643 Compile *C = ra_->C;
644
645 // If method set FPU control word, restore to standard control word
646 if( C->in_24_bit_fp_mode() ) {
647 MacroAssembler masm(&cbuf);
648 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
649 }
650
651 int framesize = C->frame_slots() << LogBytesPerInt;
652 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
653 // Remove two words for return addr and rbp,
654 framesize -= 2*wordSize;
655
656 // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here
657
658 if( framesize >= 128 ) {
659 emit_opcode(cbuf, 0x81); // add SP, #framesize
660 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
661 emit_d32(cbuf, framesize);
662 }
663 else if( framesize ) {
664 emit_opcode(cbuf, 0x83); // add SP, #framesize
665 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
666 emit_d8(cbuf, framesize);
667 }
668
669 emit_opcode(cbuf, 0x58 | EBP_enc);
670
671 if( do_polling() && C->is_method_compilation() ) {
672 cbuf.relocate(cbuf.code_end(), relocInfo::poll_return_type, 0);
673 emit_opcode(cbuf,0x85);
674 emit_rm(cbuf, 0x0, EAX_enc, 0x5); // EAX
675 emit_d32(cbuf, (intptr_t)os::get_polling_page());
676 }
677 }
678
679 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
680 Compile *C = ra_->C;
681 // If method set FPU control word, restore to standard control word
682 int size = C->in_24_bit_fp_mode() ? 6 : 0;
683 if( do_polling() && C->is_method_compilation() ) size += 6;
684
685 int framesize = C->frame_slots() << LogBytesPerInt;
686 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
687 // Remove two words for return addr and rbp,
688 framesize -= 2*wordSize;
689
690 size++; // popl rbp,
691
692 if( framesize >= 128 ) {
693 size += 6;
694 } else {
695 size += framesize ? 3 : 0;
696 }
697 return size;
698 }
699
700 int MachEpilogNode::reloc() const {
701 return 0; // a large enough number
702 }
703
704 const Pipeline * MachEpilogNode::pipeline() const {
705 return MachNode::pipeline_class();
706 }
707
708 int MachEpilogNode::safepoint_offset() const { return 0; }
709
710 //=============================================================================
711
712 enum RC { rc_bad, rc_int, rc_float, rc_xmm, rc_stack };
713 static enum RC rc_class( OptoReg::Name reg ) {
714
715 if( !OptoReg::is_valid(reg) ) return rc_bad;
716 if (OptoReg::is_stack(reg)) return rc_stack;
717
718 VMReg r = OptoReg::as_VMReg(reg);
719 if (r->is_Register()) return rc_int;
720 if (r->is_FloatRegister()) {
721 assert(UseSSE < 2, "shouldn't be used in SSE2+ mode");
722 return rc_float;
723 }
724 assert(r->is_XMMRegister(), "must be");
725 return rc_xmm;
726 }
727
728 static int impl_helper( CodeBuffer *cbuf, bool do_size, bool is_load, int offset, int reg,
729 int opcode, const char *op_str, int size, outputStream* st ) {
730 if( cbuf ) {
731 emit_opcode (*cbuf, opcode );
732 encode_RegMem(*cbuf, Matcher::_regEncode[reg], ESP_enc, 0x4, 0, offset, false);
733 #ifndef PRODUCT
734 } else if( !do_size ) {
735 if( size != 0 ) st->print("\n\t");
736 if( opcode == 0x8B || opcode == 0x89 ) { // MOV
737 if( is_load ) st->print("%s %s,[ESP + #%d]",op_str,Matcher::regName[reg],offset);
738 else st->print("%s [ESP + #%d],%s",op_str,offset,Matcher::regName[reg]);
739 } else { // FLD, FST, PUSH, POP
740 st->print("%s [ESP + #%d]",op_str,offset);
741 }
742 #endif
743 }
744 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
745 return size+3+offset_size;
746 }
747
748 // Helper for XMM registers. Extra opcode bits, limited syntax.
749 static int impl_x_helper( CodeBuffer *cbuf, bool do_size, bool is_load,
750 int offset, int reg_lo, int reg_hi, int size, outputStream* st ) {
751 if( cbuf ) {
752 if( reg_lo+1 == reg_hi ) { // double move?
753 if( is_load && !UseXmmLoadAndClearUpper )
754 emit_opcode(*cbuf, 0x66 ); // use 'movlpd' for load
755 else
756 emit_opcode(*cbuf, 0xF2 ); // use 'movsd' otherwise
757 } else {
758 emit_opcode(*cbuf, 0xF3 );
759 }
760 emit_opcode(*cbuf, 0x0F );
761 if( reg_lo+1 == reg_hi && is_load && !UseXmmLoadAndClearUpper )
762 emit_opcode(*cbuf, 0x12 ); // use 'movlpd' for load
763 else
764 emit_opcode(*cbuf, is_load ? 0x10 : 0x11 );
765 encode_RegMem(*cbuf, Matcher::_regEncode[reg_lo], ESP_enc, 0x4, 0, offset, false);
766 #ifndef PRODUCT
767 } else if( !do_size ) {
768 if( size != 0 ) st->print("\n\t");
769 if( reg_lo+1 == reg_hi ) { // double move?
770 if( is_load ) st->print("%s %s,[ESP + #%d]",
771 UseXmmLoadAndClearUpper ? "MOVSD " : "MOVLPD",
772 Matcher::regName[reg_lo], offset);
773 else st->print("MOVSD [ESP + #%d],%s",
774 offset, Matcher::regName[reg_lo]);
775 } else {
776 if( is_load ) st->print("MOVSS %s,[ESP + #%d]",
777 Matcher::regName[reg_lo], offset);
778 else st->print("MOVSS [ESP + #%d],%s",
779 offset, Matcher::regName[reg_lo]);
780 }
781 #endif
782 }
783 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
784 return size+5+offset_size;
785 }
786
787
788 static int impl_movx_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
789 int src_hi, int dst_hi, int size, outputStream* st ) {
790 if( UseXmmRegToRegMoveAll ) {//Use movaps,movapd to move between xmm registers
791 if( cbuf ) {
792 if( (src_lo+1 == src_hi && dst_lo+1 == dst_hi) ) {
793 emit_opcode(*cbuf, 0x66 );
794 }
795 emit_opcode(*cbuf, 0x0F );
796 emit_opcode(*cbuf, 0x28 );
797 emit_rm (*cbuf, 0x3, Matcher::_regEncode[dst_lo], Matcher::_regEncode[src_lo] );
798 #ifndef PRODUCT
799 } else if( !do_size ) {
800 if( size != 0 ) st->print("\n\t");
801 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double move?
802 st->print("MOVAPD %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
803 } else {
804 st->print("MOVAPS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
805 }
806 #endif
807 }
808 return size + ((src_lo+1 == src_hi && dst_lo+1 == dst_hi) ? 4 : 3);
809 } else {
810 if( cbuf ) {
811 emit_opcode(*cbuf, (src_lo+1 == src_hi && dst_lo+1 == dst_hi) ? 0xF2 : 0xF3 );
812 emit_opcode(*cbuf, 0x0F );
813 emit_opcode(*cbuf, 0x10 );
814 emit_rm (*cbuf, 0x3, Matcher::_regEncode[dst_lo], Matcher::_regEncode[src_lo] );
815 #ifndef PRODUCT
816 } else if( !do_size ) {
817 if( size != 0 ) st->print("\n\t");
818 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double move?
819 st->print("MOVSD %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
820 } else {
821 st->print("MOVSS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
822 }
823 #endif
824 }
825 return size+4;
826 }
827 }
828
829 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int size, outputStream* st ) {
830 if( cbuf ) {
831 emit_opcode(*cbuf, 0x8B );
832 emit_rm (*cbuf, 0x3, Matcher::_regEncode[dst], Matcher::_regEncode[src] );
833 #ifndef PRODUCT
834 } else if( !do_size ) {
835 if( size != 0 ) st->print("\n\t");
836 st->print("MOV %s,%s",Matcher::regName[dst],Matcher::regName[src]);
837 #endif
838 }
839 return size+2;
840 }
841
842 static int impl_fp_store_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int src_hi, int dst_lo, int dst_hi,
843 int offset, int size, outputStream* st ) {
844 if( src_lo != FPR1L_num ) { // Move value to top of FP stack, if not already there
845 if( cbuf ) {
846 emit_opcode( *cbuf, 0xD9 ); // FLD (i.e., push it)
847 emit_d8( *cbuf, 0xC0-1+Matcher::_regEncode[src_lo] );
848 #ifndef PRODUCT
849 } else if( !do_size ) {
850 if( size != 0 ) st->print("\n\t");
851 st->print("FLD %s",Matcher::regName[src_lo]);
852 #endif
853 }
854 size += 2;
855 }
856
857 int st_op = (src_lo != FPR1L_num) ? EBX_num /*store & pop*/ : EDX_num /*store no pop*/;
858 const char *op_str;
859 int op;
860 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double store?
861 op_str = (src_lo != FPR1L_num) ? "FSTP_D" : "FST_D ";
862 op = 0xDD;
863 } else { // 32-bit store
864 op_str = (src_lo != FPR1L_num) ? "FSTP_S" : "FST_S ";
865 op = 0xD9;
866 assert( !OptoReg::is_valid(src_hi) && !OptoReg::is_valid(dst_hi), "no non-adjacent float-stores" );
867 }
868
869 return impl_helper(cbuf,do_size,false,offset,st_op,op,op_str,size, st);
870 }
871
872 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream* st ) const {
873 // Get registers to move
874 OptoReg::Name src_second = ra_->get_reg_second(in(1));
875 OptoReg::Name src_first = ra_->get_reg_first(in(1));
876 OptoReg::Name dst_second = ra_->get_reg_second(this );
877 OptoReg::Name dst_first = ra_->get_reg_first(this );
878
879 enum RC src_second_rc = rc_class(src_second);
880 enum RC src_first_rc = rc_class(src_first);
881 enum RC dst_second_rc = rc_class(dst_second);
882 enum RC dst_first_rc = rc_class(dst_first);
883
884 assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" );
885
886 // Generate spill code!
887 int size = 0;
888
889 if( src_first == dst_first && src_second == dst_second )
890 return size; // Self copy, no move
891
892 // --------------------------------------
893 // Check for mem-mem move. push/pop to move.
894 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
895 if( src_second == dst_first ) { // overlapping stack copy ranges
896 assert( src_second_rc == rc_stack && dst_second_rc == rc_stack, "we only expect a stk-stk copy here" );
897 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH ",size, st);
898 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP ",size, st);
899 src_second_rc = dst_second_rc = rc_bad; // flag as already moved the second bits
900 }
901 // move low bits
902 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),ESI_num,0xFF,"PUSH ",size, st);
903 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),EAX_num,0x8F,"POP ",size, st);
904 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) { // mov second bits
905 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH ",size, st);
906 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP ",size, st);
907 }
908 return size;
909 }
910
911 // --------------------------------------
912 // Check for integer reg-reg copy
913 if( src_first_rc == rc_int && dst_first_rc == rc_int )
914 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,size, st);
915
916 // Check for integer store
917 if( src_first_rc == rc_int && dst_first_rc == rc_stack )
918 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first,0x89,"MOV ",size, st);
919
920 // Check for integer load
921 if( dst_first_rc == rc_int && src_first_rc == rc_stack )
922 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first,0x8B,"MOV ",size, st);
923
924 // --------------------------------------
925 // Check for float reg-reg copy
926 if( src_first_rc == rc_float && dst_first_rc == rc_float ) {
927 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) ||
928 (src_first+1 == src_second && dst_first+1 == dst_second), "no non-adjacent float-moves" );
929 if( cbuf ) {
930
931 // Note the mucking with the register encode to compensate for the 0/1
932 // indexing issue mentioned in a comment in the reg_def sections
933 // for FPR registers many lines above here.
934
935 if( src_first != FPR1L_num ) {
936 emit_opcode (*cbuf, 0xD9 ); // FLD ST(i)
937 emit_d8 (*cbuf, 0xC0+Matcher::_regEncode[src_first]-1 );
938 emit_opcode (*cbuf, 0xDD ); // FSTP ST(i)
939 emit_d8 (*cbuf, 0xD8+Matcher::_regEncode[dst_first] );
940 } else {
941 emit_opcode (*cbuf, 0xDD ); // FST ST(i)
942 emit_d8 (*cbuf, 0xD0+Matcher::_regEncode[dst_first]-1 );
943 }
944 #ifndef PRODUCT
945 } else if( !do_size ) {
946 if( size != 0 ) st->print("\n\t");
947 if( src_first != FPR1L_num ) st->print("FLD %s\n\tFSTP %s",Matcher::regName[src_first],Matcher::regName[dst_first]);
948 else st->print( "FST %s", Matcher::regName[dst_first]);
949 #endif
950 }
951 return size + ((src_first != FPR1L_num) ? 2+2 : 2);
952 }
953
954 // Check for float store
955 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) {
956 return impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,ra_->reg2offset(dst_first),size, st);
957 }
958
959 // Check for float load
960 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) {
961 int offset = ra_->reg2offset(src_first);
962 const char *op_str;
963 int op;
964 if( src_first+1 == src_second && dst_first+1 == dst_second ) { // double load?
965 op_str = "FLD_D";
966 op = 0xDD;
967 } else { // 32-bit load
968 op_str = "FLD_S";
969 op = 0xD9;
970 assert( src_second_rc == rc_bad && dst_second_rc == rc_bad, "no non-adjacent float-loads" );
971 }
972 if( cbuf ) {
973 emit_opcode (*cbuf, op );
974 encode_RegMem(*cbuf, 0x0, ESP_enc, 0x4, 0, offset, false);
975 emit_opcode (*cbuf, 0xDD ); // FSTP ST(i)
976 emit_d8 (*cbuf, 0xD8+Matcher::_regEncode[dst_first] );
977 #ifndef PRODUCT
978 } else if( !do_size ) {
979 if( size != 0 ) st->print("\n\t");
980 st->print("%s ST,[ESP + #%d]\n\tFSTP %s",op_str, offset,Matcher::regName[dst_first]);
981 #endif
982 }
983 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
984 return size + 3+offset_size+2;
985 }
986
987 // Check for xmm reg-reg copy
988 if( src_first_rc == rc_xmm && dst_first_rc == rc_xmm ) {
989 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) ||
990 (src_first+1 == src_second && dst_first+1 == dst_second),
991 "no non-adjacent float-moves" );
992 return impl_movx_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st);
993 }
994
995 // Check for xmm store
996 if( src_first_rc == rc_xmm && dst_first_rc == rc_stack ) {
997 return impl_x_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first, src_second, size, st);
998 }
999
1000 // Check for float xmm load
1001 if( dst_first_rc == rc_xmm && src_first_rc == rc_stack ) {
1002 return impl_x_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first, dst_second, size, st);
1003 }
1004
1005 // Copy from float reg to xmm reg
1006 if( dst_first_rc == rc_xmm && src_first_rc == rc_float ) {
1007 // copy to the top of stack from floating point reg
1008 // and use LEA to preserve flags
1009 if( cbuf ) {
1010 emit_opcode(*cbuf,0x8D); // LEA ESP,[ESP-8]
1011 emit_rm(*cbuf, 0x1, ESP_enc, 0x04);
1012 emit_rm(*cbuf, 0x0, 0x04, ESP_enc);
1013 emit_d8(*cbuf,0xF8);
1014 #ifndef PRODUCT
1015 } else if( !do_size ) {
1016 if( size != 0 ) st->print("\n\t");
1017 st->print("LEA ESP,[ESP-8]");
1018 #endif
1019 }
1020 size += 4;
1021
1022 size = impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,0,size, st);
1023
1024 // Copy from the temp memory to the xmm reg.
1025 size = impl_x_helper(cbuf,do_size,true ,0,dst_first, dst_second, size, st);
1026
1027 if( cbuf ) {
1028 emit_opcode(*cbuf,0x8D); // LEA ESP,[ESP+8]
1029 emit_rm(*cbuf, 0x1, ESP_enc, 0x04);
1030 emit_rm(*cbuf, 0x0, 0x04, ESP_enc);
1031 emit_d8(*cbuf,0x08);
1032 #ifndef PRODUCT
1033 } else if( !do_size ) {
1034 if( size != 0 ) st->print("\n\t");
1035 st->print("LEA ESP,[ESP+8]");
1036 #endif
1037 }
1038 size += 4;
1039 return size;
1040 }
1041
1042 assert( size > 0, "missed a case" );
1043
1044 // --------------------------------------------------------------------
1045 // Check for second bits still needing moving.
1046 if( src_second == dst_second )
1047 return size; // Self copy; no move
1048 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" );
1049
1050 // Check for second word int-int move
1051 if( src_second_rc == rc_int && dst_second_rc == rc_int )
1052 return impl_mov_helper(cbuf,do_size,src_second,dst_second,size, st);
1053
1054 // Check for second word integer store
1055 if( src_second_rc == rc_int && dst_second_rc == rc_stack )
1056 return impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),src_second,0x89,"MOV ",size, st);
1057
1058 // Check for second word integer load
1059 if( dst_second_rc == rc_int && src_second_rc == rc_stack )
1060 return impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),dst_second,0x8B,"MOV ",size, st);
1061
1062
1063 Unimplemented();
1064 }
1065
1066 #ifndef PRODUCT
1067 void MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1068 implementation( NULL, ra_, false, st );
1069 }
1070 #endif
1071
1072 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1073 implementation( &cbuf, ra_, false, NULL );
1074 }
1075
1076 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1077 return implementation( NULL, ra_, true, NULL );
1078 }
1079
1080 //=============================================================================
1081 #ifndef PRODUCT
1082 void MachNopNode::format( PhaseRegAlloc *, outputStream* st ) const {
1083 st->print("NOP \t# %d bytes pad for loops and calls", _count);
1084 }
1085 #endif
1086
1087 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc * ) const {
1088 MacroAssembler _masm(&cbuf);
1089 __ nop(_count);
1090 }
1091
1092 uint MachNopNode::size(PhaseRegAlloc *) const {
1093 return _count;
1094 }
1095
1096
1097 //=============================================================================
1098 #ifndef PRODUCT
1099 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1100 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1101 int reg = ra_->get_reg_first(this);
1102 st->print("LEA %s,[ESP + #%d]",Matcher::regName[reg],offset);
1103 }
1104 #endif
1105
1106 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1107 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1108 int reg = ra_->get_encode(this);
1109 if( offset >= 128 ) {
1110 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1111 emit_rm(cbuf, 0x2, reg, 0x04);
1112 emit_rm(cbuf, 0x0, 0x04, ESP_enc);
1113 emit_d32(cbuf, offset);
1114 }
1115 else {
1116 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1117 emit_rm(cbuf, 0x1, reg, 0x04);
1118 emit_rm(cbuf, 0x0, 0x04, ESP_enc);
1119 emit_d8(cbuf, offset);
1120 }
1121 }
1122
1123 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1124 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1125 if( offset >= 128 ) {
1126 return 7;
1127 }
1128 else {
1129 return 4;
1130 }
1131 }
1132
1133 //=============================================================================
1134
1135 // emit call stub, compiled java to interpreter
1136 void emit_java_to_interp(CodeBuffer &cbuf ) {
1137 // Stub is fixed up when the corresponding call is converted from calling
1138 // compiled code to calling interpreted code.
1139 // mov rbx,0
1140 // jmp -1
1141
1142 address mark = cbuf.inst_mark(); // get mark within main instrs section
1143
1144 // Note that the code buffer's inst_mark is always relative to insts.
1145 // That's why we must use the macroassembler to generate a stub.
1146 MacroAssembler _masm(&cbuf);
1147
1148 address base =
1149 __ start_a_stub(Compile::MAX_stubs_size);
1150 if (base == NULL) return; // CodeBuffer::expand failed
1151 // static stub relocation stores the instruction address of the call
1152 __ relocate(static_stub_Relocation::spec(mark), RELOC_IMM32);
1153 // static stub relocation also tags the methodOop in the code-stream.
1154 __ movoop(rbx, (jobject)NULL); // method is zapped till fixup time
1155 // This is recognized as unresolved by relocs/nativeInst/ic code
1156 __ jump(RuntimeAddress(__ pc()));
1157
1158 __ end_a_stub();
1159 // Update current stubs pointer and restore code_end.
1160 }
1161 // size of call stub, compiled java to interpretor
1162 uint size_java_to_interp() {
1163 return 10; // movl; jmp
1164 }
1165 // relocation entries for call stub, compiled java to interpretor
1166 uint reloc_java_to_interp() {
1167 return 4; // 3 in emit_java_to_interp + 1 in Java_Static_Call
1168 }
1169
1170 //=============================================================================
1171 #ifndef PRODUCT
1172 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1173 st->print_cr( "CMP EAX,[ECX+4]\t# Inline cache check");
1174 st->print_cr("\tJNE SharedRuntime::handle_ic_miss_stub");
1175 st->print_cr("\tNOP");
1176 st->print_cr("\tNOP");
1177 if( !OptoBreakpoint )
1178 st->print_cr("\tNOP");
1179 }
1180 #endif
1181
1182 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1183 MacroAssembler masm(&cbuf);
1184 #ifdef ASSERT
1185 uint code_size = cbuf.code_size();
1186 #endif
1187 masm.cmpptr(rax, Address(rcx, oopDesc::klass_offset_in_bytes()));
1188 masm.jump_cc(Assembler::notEqual,
1189 RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1190 /* WARNING these NOPs are critical so that verified entry point is properly
1191 aligned for patching by NativeJump::patch_verified_entry() */
1192 int nops_cnt = 2;
1193 if( !OptoBreakpoint ) // Leave space for int3
1194 nops_cnt += 1;
1195 masm.nop(nops_cnt);
1196
1197 assert(cbuf.code_size() - code_size == size(ra_), "checking code size of inline cache node");
1198 }
1199
1200 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
1201 return OptoBreakpoint ? 11 : 12;
1202 }
1203
1204
1205 //=============================================================================
1206 uint size_exception_handler() {
1207 // NativeCall instruction size is the same as NativeJump.
1208 // exception handler starts out as jump and can be patched to
1209 // a call be deoptimization. (4932387)
1210 // Note that this value is also credited (in output.cpp) to
1211 // the size of the code section.
1212 return NativeJump::instruction_size;
1213 }
1214
1215 // Emit exception handler code. Stuff framesize into a register
1216 // and call a VM stub routine.
1217 int emit_exception_handler(CodeBuffer& cbuf) {
1218
1219 // Note that the code buffer's inst_mark is always relative to insts.
1220 // That's why we must use the macroassembler to generate a handler.
1221 MacroAssembler _masm(&cbuf);
1222 address base =
1223 __ start_a_stub(size_exception_handler());
1224 if (base == NULL) return 0; // CodeBuffer::expand failed
1225 int offset = __ offset();
1226 __ jump(RuntimeAddress(OptoRuntime::exception_blob()->instructions_begin()));
1227 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
1228 __ end_a_stub();
1229 return offset;
1230 }
1231
1232 uint size_deopt_handler() {
1233 // NativeCall instruction size is the same as NativeJump.
1234 // exception handler starts out as jump and can be patched to
1235 // a call be deoptimization. (4932387)
1236 // Note that this value is also credited (in output.cpp) to
1237 // the size of the code section.
1238 return 5 + NativeJump::instruction_size; // pushl(); jmp;
1239 }
1240
1241 // Emit deopt handler code.
1242 int emit_deopt_handler(CodeBuffer& cbuf) {
1243
1244 // Note that the code buffer's inst_mark is always relative to insts.
1245 // That's why we must use the macroassembler to generate a handler.
1246 MacroAssembler _masm(&cbuf);
1247 address base =
1248 __ start_a_stub(size_exception_handler());
1249 if (base == NULL) return 0; // CodeBuffer::expand failed
1250 int offset = __ offset();
1251 InternalAddress here(__ pc());
1252 __ pushptr(here.addr());
1253
1254 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
1255 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
1256 __ end_a_stub();
1257 return offset;
1258 }
1259
1260
1261 static void emit_double_constant(CodeBuffer& cbuf, double x) {
1262 int mark = cbuf.insts()->mark_off();
1263 MacroAssembler _masm(&cbuf);
1264 address double_address = __ double_constant(x);
1265 cbuf.insts()->set_mark_off(mark); // preserve mark across masm shift
1266 emit_d32_reloc(cbuf,
1267 (int)double_address,
1268 internal_word_Relocation::spec(double_address),
1269 RELOC_DISP32);
1270 }
1271
1272 static void emit_float_constant(CodeBuffer& cbuf, float x) {
1273 int mark = cbuf.insts()->mark_off();
1274 MacroAssembler _masm(&cbuf);
1275 address float_address = __ float_constant(x);
1276 cbuf.insts()->set_mark_off(mark); // preserve mark across masm shift
1277 emit_d32_reloc(cbuf,
1278 (int)float_address,
1279 internal_word_Relocation::spec(float_address),
1280 RELOC_DISP32);
1281 }
1282
1283
1284 int Matcher::regnum_to_fpu_offset(int regnum) {
1285 return regnum - 32; // The FP registers are in the second chunk
1286 }
1287
1288 bool is_positive_zero_float(jfloat f) {
1289 return jint_cast(f) == jint_cast(0.0F);
1290 }
1291
1292 bool is_positive_one_float(jfloat f) {
1293 return jint_cast(f) == jint_cast(1.0F);
1294 }
1295
1296 bool is_positive_zero_double(jdouble d) {
1297 return jlong_cast(d) == jlong_cast(0.0);
1298 }
1299
1300 bool is_positive_one_double(jdouble d) {
1301 return jlong_cast(d) == jlong_cast(1.0);
1302 }
1303
1304 // This is UltraSparc specific, true just means we have fast l2f conversion
1305 const bool Matcher::convL2FSupported(void) {
1306 return true;
1307 }
1308
1309 // Vector width in bytes
1310 const uint Matcher::vector_width_in_bytes(void) {
1311 return UseSSE >= 2 ? 8 : 0;
1312 }
1313
1314 // Vector ideal reg
1315 const uint Matcher::vector_ideal_reg(void) {
1316 return Op_RegD;
1317 }
1318
1319 // Is this branch offset short enough that a short branch can be used?
1320 //
1321 // NOTE: If the platform does not provide any short branch variants, then
1322 // this method should return false for offset 0.
1323 bool Matcher::is_short_branch_offset(int rule, int offset) {
1324 // the short version of jmpConUCF2 contains multiple branches,
1325 // making the reach slightly less
1326 if (rule == jmpConUCF2_rule)
1327 return (-126 <= offset && offset <= 125);
1328 return (-128 <= offset && offset <= 127);
1329 }
1330
1331 const bool Matcher::isSimpleConstant64(jlong value) {
1332 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1333 return false;
1334 }
1335
1336 // The ecx parameter to rep stos for the ClearArray node is in dwords.
1337 const bool Matcher::init_array_count_is_in_bytes = false;
1338
1339 // Threshold size for cleararray.
1340 const int Matcher::init_array_short_size = 8 * BytesPerLong;
1341
1342 // Should the Matcher clone shifts on addressing modes, expecting them to
1343 // be subsumed into complex addressing expressions or compute them into
1344 // registers? True for Intel but false for most RISCs
1345 const bool Matcher::clone_shift_expressions = true;
1346
1347 // Is it better to copy float constants, or load them directly from memory?
1348 // Intel can load a float constant from a direct address, requiring no
1349 // extra registers. Most RISCs will have to materialize an address into a
1350 // register first, so they would do better to copy the constant from stack.
1351 const bool Matcher::rematerialize_float_constants = true;
1352
1353 // If CPU can load and store mis-aligned doubles directly then no fixup is
1354 // needed. Else we split the double into 2 integer pieces and move it
1355 // piece-by-piece. Only happens when passing doubles into C code as the
1356 // Java calling convention forces doubles to be aligned.
1357 const bool Matcher::misaligned_doubles_ok = true;
1358
1359
1360 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
1361 // Get the memory operand from the node
1362 uint numopnds = node->num_opnds(); // Virtual call for number of operands
1363 uint skipped = node->oper_input_base(); // Sum of leaves skipped so far
1364 assert( idx >= skipped, "idx too low in pd_implicit_null_fixup" );
1365 uint opcnt = 1; // First operand
1366 uint num_edges = node->_opnds[1]->num_edges(); // leaves for first operand
1367 while( idx >= skipped+num_edges ) {
1368 skipped += num_edges;
1369 opcnt++; // Bump operand count
1370 assert( opcnt < numopnds, "Accessing non-existent operand" );
1371 num_edges = node->_opnds[opcnt]->num_edges(); // leaves for next operand
1372 }
1373
1374 MachOper *memory = node->_opnds[opcnt];
1375 MachOper *new_memory = NULL;
1376 switch (memory->opcode()) {
1377 case DIRECT:
1378 case INDOFFSET32X:
1379 // No transformation necessary.
1380 return;
1381 case INDIRECT:
1382 new_memory = new (C) indirect_win95_safeOper( );
1383 break;
1384 case INDOFFSET8:
1385 new_memory = new (C) indOffset8_win95_safeOper(memory->disp(NULL, NULL, 0));
1386 break;
1387 case INDOFFSET32:
1388 new_memory = new (C) indOffset32_win95_safeOper(memory->disp(NULL, NULL, 0));
1389 break;
1390 case INDINDEXOFFSET:
1391 new_memory = new (C) indIndexOffset_win95_safeOper(memory->disp(NULL, NULL, 0));
1392 break;
1393 case INDINDEXSCALE:
1394 new_memory = new (C) indIndexScale_win95_safeOper(memory->scale());
1395 break;
1396 case INDINDEXSCALEOFFSET:
1397 new_memory = new (C) indIndexScaleOffset_win95_safeOper(memory->scale(), memory->disp(NULL, NULL, 0));
1398 break;
1399 case LOAD_LONG_INDIRECT:
1400 case LOAD_LONG_INDOFFSET32:
1401 // Does not use EBP as address register, use { EDX, EBX, EDI, ESI}
1402 return;
1403 default:
1404 assert(false, "unexpected memory operand in pd_implicit_null_fixup()");
1405 return;
1406 }
1407 node->_opnds[opcnt] = new_memory;
1408 }
1409
1410 // Advertise here if the CPU requires explicit rounding operations
1411 // to implement the UseStrictFP mode.
1412 const bool Matcher::strict_fp_requires_explicit_rounding = true;
1413
1414 // Do floats take an entire double register or just half?
1415 const bool Matcher::float_in_double = true;
1416 // Do ints take an entire long register or just half?
1417 const bool Matcher::int_in_long = false;
1418
1419 // Return whether or not this register is ever used as an argument. This
1420 // function is used on startup to build the trampoline stubs in generateOptoStub.
1421 // Registers not mentioned will be killed by the VM call in the trampoline, and
1422 // arguments in those registers not be available to the callee.
1423 bool Matcher::can_be_java_arg( int reg ) {
1424 if( reg == ECX_num || reg == EDX_num ) return true;
1425 if( (reg == XMM0a_num || reg == XMM1a_num) && UseSSE>=1 ) return true;
1426 if( (reg == XMM0b_num || reg == XMM1b_num) && UseSSE>=2 ) return true;
1427 return false;
1428 }
1429
1430 bool Matcher::is_spillable_arg( int reg ) {
1431 return can_be_java_arg(reg);
1432 }
1433
1434 // Register for DIVI projection of divmodI
1435 RegMask Matcher::divI_proj_mask() {
1436 return EAX_REG_mask;
1437 }
1438
1439 // Register for MODI projection of divmodI
1440 RegMask Matcher::modI_proj_mask() {
1441 return EDX_REG_mask;
1442 }
1443
1444 // Register for DIVL projection of divmodL
1445 RegMask Matcher::divL_proj_mask() {
1446 ShouldNotReachHere();
1447 return RegMask();
1448 }
1449
1450 // Register for MODL projection of divmodL
1451 RegMask Matcher::modL_proj_mask() {
1452 ShouldNotReachHere();
1453 return RegMask();
1454 }
1455
1456 %}
1457
1458 //----------ENCODING BLOCK-----------------------------------------------------
1459 // This block specifies the encoding classes used by the compiler to output
1460 // byte streams. Encoding classes generate functions which are called by
1461 // Machine Instruction Nodes in order to generate the bit encoding of the
1462 // instruction. Operands specify their base encoding interface with the
1463 // interface keyword. There are currently supported four interfaces,
1464 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
1465 // operand to generate a function which returns its register number when
1466 // queried. CONST_INTER causes an operand to generate a function which
1467 // returns the value of the constant when queried. MEMORY_INTER causes an
1468 // operand to generate four functions which return the Base Register, the
1469 // Index Register, the Scale Value, and the Offset Value of the operand when
1470 // queried. COND_INTER causes an operand to generate six functions which
1471 // return the encoding code (ie - encoding bits for the instruction)
1472 // associated with each basic boolean condition for a conditional instruction.
1473 // Instructions specify two basic values for encoding. They use the
1474 // ins_encode keyword to specify their encoding class (which must be one of
1475 // the class names specified in the encoding block), and they use the
1476 // opcode keyword to specify, in order, their primary, secondary, and
1477 // tertiary opcode. Only the opcode sections which a particular instruction
1478 // needs for encoding need to be specified.
1479 encode %{
1480 // Build emit functions for each basic byte or larger field in the intel
1481 // encoding scheme (opcode, rm, sib, immediate), and call them from C++
1482 // code in the enc_class source block. Emit functions will live in the
1483 // main source block for now. In future, we can generalize this by
1484 // adding a syntax that specifies the sizes of fields in an order,
1485 // so that the adlc can build the emit functions automagically
1486
1487 // Emit primary opcode
1488 enc_class OpcP %{
1489 emit_opcode(cbuf, $primary);
1490 %}
1491
1492 // Emit secondary opcode
1493 enc_class OpcS %{
1494 emit_opcode(cbuf, $secondary);
1495 %}
1496
1497 // Emit opcode directly
1498 enc_class Opcode(immI d8) %{
1499 emit_opcode(cbuf, $d8$$constant);
1500 %}
1501
1502 enc_class SizePrefix %{
1503 emit_opcode(cbuf,0x66);
1504 %}
1505
1506 enc_class RegReg (eRegI dst, eRegI src) %{ // RegReg(Many)
1507 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1508 %}
1509
1510 enc_class OpcRegReg (immI opcode, eRegI dst, eRegI src) %{ // OpcRegReg(Many)
1511 emit_opcode(cbuf,$opcode$$constant);
1512 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1513 %}
1514
1515 enc_class mov_r32_imm0( eRegI dst ) %{
1516 emit_opcode( cbuf, 0xB8 + $dst$$reg ); // 0xB8+ rd -- MOV r32 ,imm32
1517 emit_d32 ( cbuf, 0x0 ); // imm32==0x0
1518 %}
1519
1520 enc_class cdq_enc %{
1521 // Full implementation of Java idiv and irem; checks for
1522 // special case as described in JVM spec., p.243 & p.271.
1523 //
1524 // normal case special case
1525 //
1526 // input : rax,: dividend min_int
1527 // reg: divisor -1
1528 //
1529 // output: rax,: quotient (= rax, idiv reg) min_int
1530 // rdx: remainder (= rax, irem reg) 0
1531 //
1532 // Code sequnce:
1533 //
1534 // 81 F8 00 00 00 80 cmp rax,80000000h
1535 // 0F 85 0B 00 00 00 jne normal_case
1536 // 33 D2 xor rdx,edx
1537 // 83 F9 FF cmp rcx,0FFh
1538 // 0F 84 03 00 00 00 je done
1539 // normal_case:
1540 // 99 cdq
1541 // F7 F9 idiv rax,ecx
1542 // done:
1543 //
1544 emit_opcode(cbuf,0x81); emit_d8(cbuf,0xF8);
1545 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00);
1546 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x80); // cmp rax,80000000h
1547 emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x85);
1548 emit_opcode(cbuf,0x0B); emit_d8(cbuf,0x00);
1549 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); // jne normal_case
1550 emit_opcode(cbuf,0x33); emit_d8(cbuf,0xD2); // xor rdx,edx
1551 emit_opcode(cbuf,0x83); emit_d8(cbuf,0xF9); emit_d8(cbuf,0xFF); // cmp rcx,0FFh
1552 emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x84);
1553 emit_opcode(cbuf,0x03); emit_d8(cbuf,0x00);
1554 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); // je done
1555 // normal_case:
1556 emit_opcode(cbuf,0x99); // cdq
1557 // idiv (note: must be emitted by the user of this rule)
1558 // normal:
1559 %}
1560
1561 // Dense encoding for older common ops
1562 enc_class Opc_plus(immI opcode, eRegI reg) %{
1563 emit_opcode(cbuf, $opcode$$constant + $reg$$reg);
1564 %}
1565
1566
1567 // Opcde enc_class for 8/32 bit immediate instructions with sign-extension
1568 enc_class OpcSE (immI imm) %{ // Emit primary opcode and set sign-extend bit
1569 // Check for 8-bit immediate, and set sign extend bit in opcode
1570 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1571 emit_opcode(cbuf, $primary | 0x02);
1572 }
1573 else { // If 32-bit immediate
1574 emit_opcode(cbuf, $primary);
1575 }
1576 %}
1577
1578 enc_class OpcSErm (eRegI dst, immI imm) %{ // OpcSEr/m
1579 // Emit primary opcode and set sign-extend bit
1580 // Check for 8-bit immediate, and set sign extend bit in opcode
1581 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1582 emit_opcode(cbuf, $primary | 0x02); }
1583 else { // If 32-bit immediate
1584 emit_opcode(cbuf, $primary);
1585 }
1586 // Emit r/m byte with secondary opcode, after primary opcode.
1587 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1588 %}
1589
1590 enc_class Con8or32 (immI imm) %{ // Con8or32(storeImmI), 8 or 32 bits
1591 // Check for 8-bit immediate, and set sign extend bit in opcode
1592 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1593 $$$emit8$imm$$constant;
1594 }
1595 else { // If 32-bit immediate
1596 // Output immediate
1597 $$$emit32$imm$$constant;
1598 }
1599 %}
1600
1601 enc_class Long_OpcSErm_Lo(eRegL dst, immL imm) %{
1602 // Emit primary opcode and set sign-extend bit
1603 // Check for 8-bit immediate, and set sign extend bit in opcode
1604 int con = (int)$imm$$constant; // Throw away top bits
1605 emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary);
1606 // Emit r/m byte with secondary opcode, after primary opcode.
1607 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1608 if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con);
1609 else emit_d32(cbuf,con);
1610 %}
1611
1612 enc_class Long_OpcSErm_Hi(eRegL dst, immL imm) %{
1613 // Emit primary opcode and set sign-extend bit
1614 // Check for 8-bit immediate, and set sign extend bit in opcode
1615 int con = (int)($imm$$constant >> 32); // Throw away bottom bits
1616 emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary);
1617 // Emit r/m byte with tertiary opcode, after primary opcode.
1618 emit_rm(cbuf, 0x3, $tertiary, HIGH_FROM_LOW($dst$$reg));
1619 if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con);
1620 else emit_d32(cbuf,con);
1621 %}
1622
1623 enc_class Lbl (label labl) %{ // JMP, CALL
1624 Label *l = $labl$$label;
1625 emit_d32(cbuf, l ? (l->loc_pos() - (cbuf.code_size()+4)) : 0);
1626 %}
1627
1628 enc_class LblShort (label labl) %{ // JMP, CALL
1629 Label *l = $labl$$label;
1630 int disp = l ? (l->loc_pos() - (cbuf.code_size()+1)) : 0;
1631 assert(-128 <= disp && disp <= 127, "Displacement too large for short jmp");
1632 emit_d8(cbuf, disp);
1633 %}
1634
1635 enc_class OpcSReg (eRegI dst) %{ // BSWAP
1636 emit_cc(cbuf, $secondary, $dst$$reg );
1637 %}
1638
1639 enc_class bswap_long_bytes(eRegL dst) %{ // BSWAP
1640 int destlo = $dst$$reg;
1641 int desthi = HIGH_FROM_LOW(destlo);
1642 // bswap lo
1643 emit_opcode(cbuf, 0x0F);
1644 emit_cc(cbuf, 0xC8, destlo);
1645 // bswap hi
1646 emit_opcode(cbuf, 0x0F);
1647 emit_cc(cbuf, 0xC8, desthi);
1648 // xchg lo and hi
1649 emit_opcode(cbuf, 0x87);
1650 emit_rm(cbuf, 0x3, destlo, desthi);
1651 %}
1652
1653 enc_class RegOpc (eRegI div) %{ // IDIV, IMOD, JMP indirect, ...
1654 emit_rm(cbuf, 0x3, $secondary, $div$$reg );
1655 %}
1656
1657 enc_class Jcc (cmpOp cop, label labl) %{ // JCC
1658 Label *l = $labl$$label;
1659 $$$emit8$primary;
1660 emit_cc(cbuf, $secondary, $cop$$cmpcode);
1661 emit_d32(cbuf, l ? (l->loc_pos() - (cbuf.code_size()+4)) : 0);
1662 %}
1663
1664 enc_class JccShort (cmpOp cop, label labl) %{ // JCC
1665 Label *l = $labl$$label;
1666 emit_cc(cbuf, $primary, $cop$$cmpcode);
1667 int disp = l ? (l->loc_pos() - (cbuf.code_size()+1)) : 0;
1668 assert(-128 <= disp && disp <= 127, "Displacement too large for short jmp");
1669 emit_d8(cbuf, disp);
1670 %}
1671
1672 enc_class enc_cmov(cmpOp cop ) %{ // CMOV
1673 $$$emit8$primary;
1674 emit_cc(cbuf, $secondary, $cop$$cmpcode);
1675 %}
1676
1677 enc_class enc_cmov_d(cmpOp cop, regD src ) %{ // CMOV
1678 int op = 0xDA00 + $cop$$cmpcode + ($src$$reg-1);
1679 emit_d8(cbuf, op >> 8 );
1680 emit_d8(cbuf, op & 255);
1681 %}
1682
1683 // emulate a CMOV with a conditional branch around a MOV
1684 enc_class enc_cmov_branch( cmpOp cop, immI brOffs ) %{ // CMOV
1685 // Invert sense of branch from sense of CMOV
1686 emit_cc( cbuf, 0x70, ($cop$$cmpcode^1) );
1687 emit_d8( cbuf, $brOffs$$constant );
1688 %}
1689
1690 enc_class enc_PartialSubtypeCheck( ) %{
1691 Register Redi = as_Register(EDI_enc); // result register
1692 Register Reax = as_Register(EAX_enc); // super class
1693 Register Recx = as_Register(ECX_enc); // killed
1694 Register Resi = as_Register(ESI_enc); // sub class
1695 Label miss;
1696
1697 MacroAssembler _masm(&cbuf);
1698 __ check_klass_subtype_slow_path(Resi, Reax, Recx, Redi,
1699 NULL, &miss,
1700 /*set_cond_codes:*/ true);
1701 if ($primary) {
1702 __ xorptr(Redi, Redi);
1703 }
1704 __ bind(miss);
1705 %}
1706
1707 enc_class FFree_Float_Stack_All %{ // Free_Float_Stack_All
1708 MacroAssembler masm(&cbuf);
1709 int start = masm.offset();
1710 if (UseSSE >= 2) {
1711 if (VerifyFPU) {
1712 masm.verify_FPU(0, "must be empty in SSE2+ mode");
1713 }
1714 } else {
1715 // External c_calling_convention expects the FPU stack to be 'clean'.
1716 // Compiled code leaves it dirty. Do cleanup now.
1717 masm.empty_FPU_stack();
1718 }
1719 if (sizeof_FFree_Float_Stack_All == -1) {
1720 sizeof_FFree_Float_Stack_All = masm.offset() - start;
1721 } else {
1722 assert(masm.offset() - start == sizeof_FFree_Float_Stack_All, "wrong size");
1723 }
1724 %}
1725
1726 enc_class Verify_FPU_For_Leaf %{
1727 if( VerifyFPU ) {
1728 MacroAssembler masm(&cbuf);
1729 masm.verify_FPU( -3, "Returning from Runtime Leaf call");
1730 }
1731 %}
1732
1733 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime, Java_To_Runtime_Leaf
1734 // This is the instruction starting address for relocation info.
1735 cbuf.set_inst_mark();
1736 $$$emit8$primary;
1737 // CALL directly to the runtime
1738 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.code_end()) - 4),
1739 runtime_call_Relocation::spec(), RELOC_IMM32 );
1740
1741 if (UseSSE >= 2) {
1742 MacroAssembler _masm(&cbuf);
1743 BasicType rt = tf()->return_type();
1744
1745 if ((rt == T_FLOAT || rt == T_DOUBLE) && !return_value_is_used()) {
1746 // A C runtime call where the return value is unused. In SSE2+
1747 // mode the result needs to be removed from the FPU stack. It's
1748 // likely that this function call could be removed by the
1749 // optimizer if the C function is a pure function.
1750 __ ffree(0);
1751 } else if (rt == T_FLOAT) {
1752 __ lea(rsp, Address(rsp, -4));
1753 __ fstp_s(Address(rsp, 0));
1754 __ movflt(xmm0, Address(rsp, 0));
1755 __ lea(rsp, Address(rsp, 4));
1756 } else if (rt == T_DOUBLE) {
1757 __ lea(rsp, Address(rsp, -8));
1758 __ fstp_d(Address(rsp, 0));
1759 __ movdbl(xmm0, Address(rsp, 0));
1760 __ lea(rsp, Address(rsp, 8));
1761 }
1762 }
1763 %}
1764
1765
1766 enc_class pre_call_FPU %{
1767 // If method sets FPU control word restore it here
1768 if( Compile::current()->in_24_bit_fp_mode() ) {
1769 MacroAssembler masm(&cbuf);
1770 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
1771 }
1772 %}
1773
1774 enc_class post_call_FPU %{
1775 // If method sets FPU control word do it here also
1776 if( Compile::current()->in_24_bit_fp_mode() ) {
1777 MacroAssembler masm(&cbuf);
1778 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
1779 }
1780 %}
1781
1782 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL
1783 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
1784 // who we intended to call.
1785 cbuf.set_inst_mark();
1786 $$$emit8$primary;
1787 if ( !_method ) {
1788 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.code_end()) - 4),
1789 runtime_call_Relocation::spec(), RELOC_IMM32 );
1790 } else if(_optimized_virtual) {
1791 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.code_end()) - 4),
1792 opt_virtual_call_Relocation::spec(), RELOC_IMM32 );
1793 } else {
1794 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.code_end()) - 4),
1795 static_call_Relocation::spec(), RELOC_IMM32 );
1796 }
1797 if( _method ) { // Emit stub for static call
1798 emit_java_to_interp(cbuf);
1799 }
1800 %}
1801
1802 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL
1803 // !!!!!
1804 // Generate "Mov EAX,0x00", placeholder instruction to load oop-info
1805 // emit_call_dynamic_prologue( cbuf );
1806 cbuf.set_inst_mark();
1807 emit_opcode(cbuf, 0xB8 + EAX_enc); // mov EAX,-1
1808 emit_d32_reloc(cbuf, (int)Universe::non_oop_word(), oop_Relocation::spec_for_immediate(), RELOC_IMM32);
1809 address virtual_call_oop_addr = cbuf.inst_mark();
1810 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
1811 // who we intended to call.
1812 cbuf.set_inst_mark();
1813 $$$emit8$primary;
1814 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.code_end()) - 4),
1815 virtual_call_Relocation::spec(virtual_call_oop_addr), RELOC_IMM32 );
1816 %}
1817
1818 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL
1819 int disp = in_bytes(methodOopDesc::from_compiled_offset());
1820 assert( -128 <= disp && disp <= 127, "compiled_code_offset isn't small");
1821
1822 // CALL *[EAX+in_bytes(methodOopDesc::from_compiled_code_entry_point_offset())]
1823 cbuf.set_inst_mark();
1824 $$$emit8$primary;
1825 emit_rm(cbuf, 0x01, $secondary, EAX_enc ); // R/M byte
1826 emit_d8(cbuf, disp); // Displacement
1827
1828 %}
1829
1830 enc_class Xor_Reg (eRegI dst) %{
1831 emit_opcode(cbuf, 0x33);
1832 emit_rm(cbuf, 0x3, $dst$$reg, $dst$$reg);
1833 %}
1834
1835 // Following encoding is no longer used, but may be restored if calling
1836 // convention changes significantly.
1837 // Became: Xor_Reg(EBP), Java_To_Runtime( labl )
1838 //
1839 // enc_class Java_Interpreter_Call (label labl) %{ // JAVA INTERPRETER CALL
1840 // // int ic_reg = Matcher::inline_cache_reg();
1841 // // int ic_encode = Matcher::_regEncode[ic_reg];
1842 // // int imo_reg = Matcher::interpreter_method_oop_reg();
1843 // // int imo_encode = Matcher::_regEncode[imo_reg];
1844 //
1845 // // // Interpreter expects method_oop in EBX, currently a callee-saved register,
1846 // // // so we load it immediately before the call
1847 // // emit_opcode(cbuf, 0x8B); // MOV imo_reg,ic_reg # method_oop
1848 // // emit_rm(cbuf, 0x03, imo_encode, ic_encode ); // R/M byte
1849 //
1850 // // xor rbp,ebp
1851 // emit_opcode(cbuf, 0x33);
1852 // emit_rm(cbuf, 0x3, EBP_enc, EBP_enc);
1853 //
1854 // // CALL to interpreter.
1855 // cbuf.set_inst_mark();
1856 // $$$emit8$primary;
1857 // emit_d32_reloc(cbuf, ($labl$$label - (int)(cbuf.code_end()) - 4),
1858 // runtime_call_Relocation::spec(), RELOC_IMM32 );
1859 // %}
1860
1861 enc_class RegOpcImm (eRegI dst, immI8 shift) %{ // SHL, SAR, SHR
1862 $$$emit8$primary;
1863 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1864 $$$emit8$shift$$constant;
1865 %}
1866
1867 enc_class LdImmI (eRegI dst, immI src) %{ // Load Immediate
1868 // Load immediate does not have a zero or sign extended version
1869 // for 8-bit immediates
1870 emit_opcode(cbuf, 0xB8 + $dst$$reg);
1871 $$$emit32$src$$constant;
1872 %}
1873
1874 enc_class LdImmP (eRegI dst, immI src) %{ // Load Immediate
1875 // Load immediate does not have a zero or sign extended version
1876 // for 8-bit immediates
1877 emit_opcode(cbuf, $primary + $dst$$reg);
1878 $$$emit32$src$$constant;
1879 %}
1880
1881 enc_class LdImmL_Lo( eRegL dst, immL src) %{ // Load Immediate
1882 // Load immediate does not have a zero or sign extended version
1883 // for 8-bit immediates
1884 int dst_enc = $dst$$reg;
1885 int src_con = $src$$constant & 0x0FFFFFFFFL;
1886 if (src_con == 0) {
1887 // xor dst, dst
1888 emit_opcode(cbuf, 0x33);
1889 emit_rm(cbuf, 0x3, dst_enc, dst_enc);
1890 } else {
1891 emit_opcode(cbuf, $primary + dst_enc);
1892 emit_d32(cbuf, src_con);
1893 }
1894 %}
1895
1896 enc_class LdImmL_Hi( eRegL dst, immL src) %{ // Load Immediate
1897 // Load immediate does not have a zero or sign extended version
1898 // for 8-bit immediates
1899 int dst_enc = $dst$$reg + 2;
1900 int src_con = ((julong)($src$$constant)) >> 32;
1901 if (src_con == 0) {
1902 // xor dst, dst
1903 emit_opcode(cbuf, 0x33);
1904 emit_rm(cbuf, 0x3, dst_enc, dst_enc);
1905 } else {
1906 emit_opcode(cbuf, $primary + dst_enc);
1907 emit_d32(cbuf, src_con);
1908 }
1909 %}
1910
1911
1912 enc_class LdImmD (immD src) %{ // Load Immediate
1913 if( is_positive_zero_double($src$$constant)) {
1914 // FLDZ
1915 emit_opcode(cbuf,0xD9);
1916 emit_opcode(cbuf,0xEE);
1917 } else if( is_positive_one_double($src$$constant)) {
1918 // FLD1
1919 emit_opcode(cbuf,0xD9);
1920 emit_opcode(cbuf,0xE8);
1921 } else {
1922 emit_opcode(cbuf,0xDD);
1923 emit_rm(cbuf, 0x0, 0x0, 0x5);
1924 emit_double_constant(cbuf, $src$$constant);
1925 }
1926 %}
1927
1928
1929 enc_class LdImmF (immF src) %{ // Load Immediate
1930 if( is_positive_zero_float($src$$constant)) {
1931 emit_opcode(cbuf,0xD9);
1932 emit_opcode(cbuf,0xEE);
1933 } else if( is_positive_one_float($src$$constant)) {
1934 emit_opcode(cbuf,0xD9);
1935 emit_opcode(cbuf,0xE8);
1936 } else {
1937 $$$emit8$primary;
1938 // Load immediate does not have a zero or sign extended version
1939 // for 8-bit immediates
1940 // First load to TOS, then move to dst
1941 emit_rm(cbuf, 0x0, 0x0, 0x5);
1942 emit_float_constant(cbuf, $src$$constant);
1943 }
1944 %}
1945
1946 enc_class LdImmX (regX dst, immXF con) %{ // Load Immediate
1947 emit_rm(cbuf, 0x0, $dst$$reg, 0x5);
1948 emit_float_constant(cbuf, $con$$constant);
1949 %}
1950
1951 enc_class LdImmXD (regXD dst, immXD con) %{ // Load Immediate
1952 emit_rm(cbuf, 0x0, $dst$$reg, 0x5);
1953 emit_double_constant(cbuf, $con$$constant);
1954 %}
1955
1956 enc_class load_conXD (regXD dst, immXD con) %{ // Load double constant
1957 // UseXmmLoadAndClearUpper ? movsd(dst, con) : movlpd(dst, con)
1958 emit_opcode(cbuf, UseXmmLoadAndClearUpper ? 0xF2 : 0x66);
1959 emit_opcode(cbuf, 0x0F);
1960 emit_opcode(cbuf, UseXmmLoadAndClearUpper ? 0x10 : 0x12);
1961 emit_rm(cbuf, 0x0, $dst$$reg, 0x5);
1962 emit_double_constant(cbuf, $con$$constant);
1963 %}
1964
1965 enc_class Opc_MemImm_F(immF src) %{
1966 cbuf.set_inst_mark();
1967 $$$emit8$primary;
1968 emit_rm(cbuf, 0x0, $secondary, 0x5);
1969 emit_float_constant(cbuf, $src$$constant);
1970 %}
1971
1972
1973 enc_class MovI2X_reg(regX dst, eRegI src) %{
1974 emit_opcode(cbuf, 0x66 ); // MOVD dst,src
1975 emit_opcode(cbuf, 0x0F );
1976 emit_opcode(cbuf, 0x6E );
1977 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1978 %}
1979
1980 enc_class MovX2I_reg(eRegI dst, regX src) %{
1981 emit_opcode(cbuf, 0x66 ); // MOVD dst,src
1982 emit_opcode(cbuf, 0x0F );
1983 emit_opcode(cbuf, 0x7E );
1984 emit_rm(cbuf, 0x3, $src$$reg, $dst$$reg);
1985 %}
1986
1987 enc_class MovL2XD_reg(regXD dst, eRegL src, regXD tmp) %{
1988 { // MOVD $dst,$src.lo
1989 emit_opcode(cbuf,0x66);
1990 emit_opcode(cbuf,0x0F);
1991 emit_opcode(cbuf,0x6E);
1992 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1993 }
1994 { // MOVD $tmp,$src.hi
1995 emit_opcode(cbuf,0x66);
1996 emit_opcode(cbuf,0x0F);
1997 emit_opcode(cbuf,0x6E);
1998 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg));
1999 }
2000 { // PUNPCKLDQ $dst,$tmp
2001 emit_opcode(cbuf,0x66);
2002 emit_opcode(cbuf,0x0F);
2003 emit_opcode(cbuf,0x62);
2004 emit_rm(cbuf, 0x3, $dst$$reg, $tmp$$reg);
2005 }
2006 %}
2007
2008 enc_class MovXD2L_reg(eRegL dst, regXD src, regXD tmp) %{
2009 { // MOVD $dst.lo,$src
2010 emit_opcode(cbuf,0x66);
2011 emit_opcode(cbuf,0x0F);
2012 emit_opcode(cbuf,0x7E);
2013 emit_rm(cbuf, 0x3, $src$$reg, $dst$$reg);
2014 }
2015 { // PSHUFLW $tmp,$src,0x4E (01001110b)
2016 emit_opcode(cbuf,0xF2);
2017 emit_opcode(cbuf,0x0F);
2018 emit_opcode(cbuf,0x70);
2019 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg);
2020 emit_d8(cbuf, 0x4E);
2021 }
2022 { // MOVD $dst.hi,$tmp
2023 emit_opcode(cbuf,0x66);
2024 emit_opcode(cbuf,0x0F);
2025 emit_opcode(cbuf,0x7E);
2026 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg));
2027 }
2028 %}
2029
2030
2031 // Encode a reg-reg copy. If it is useless, then empty encoding.
2032 enc_class enc_Copy( eRegI dst, eRegI src ) %{
2033 encode_Copy( cbuf, $dst$$reg, $src$$reg );
2034 %}
2035
2036 enc_class enc_CopyL_Lo( eRegI dst, eRegL src ) %{
2037 encode_Copy( cbuf, $dst$$reg, $src$$reg );
2038 %}
2039
2040 // Encode xmm reg-reg copy. If it is useless, then empty encoding.
2041 enc_class enc_CopyXD( RegXD dst, RegXD src ) %{
2042 encode_CopyXD( cbuf, $dst$$reg, $src$$reg );
2043 %}
2044
2045 enc_class RegReg (eRegI dst, eRegI src) %{ // RegReg(Many)
2046 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2047 %}
2048
2049 enc_class RegReg_Lo(eRegL dst, eRegL src) %{ // RegReg(Many)
2050 $$$emit8$primary;
2051 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2052 %}
2053
2054 enc_class RegReg_Hi(eRegL dst, eRegL src) %{ // RegReg(Many)
2055 $$$emit8$secondary;
2056 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg));
2057 %}
2058
2059 enc_class RegReg_Lo2(eRegL dst, eRegL src) %{ // RegReg(Many)
2060 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2061 %}
2062
2063 enc_class RegReg_Hi2(eRegL dst, eRegL src) %{ // RegReg(Many)
2064 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg));
2065 %}
2066
2067 enc_class RegReg_HiLo( eRegL src, eRegI dst ) %{
2068 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($src$$reg));
2069 %}
2070
2071 enc_class Con32 (immI src) %{ // Con32(storeImmI)
2072 // Output immediate
2073 $$$emit32$src$$constant;
2074 %}
2075
2076 enc_class Con32F_as_bits(immF src) %{ // storeF_imm
2077 // Output Float immediate bits
2078 jfloat jf = $src$$constant;
2079 int jf_as_bits = jint_cast( jf );
2080 emit_d32(cbuf, jf_as_bits);
2081 %}
2082
2083 enc_class Con32XF_as_bits(immXF src) %{ // storeX_imm
2084 // Output Float immediate bits
2085 jfloat jf = $src$$constant;
2086 int jf_as_bits = jint_cast( jf );
2087 emit_d32(cbuf, jf_as_bits);
2088 %}
2089
2090 enc_class Con16 (immI src) %{ // Con16(storeImmI)
2091 // Output immediate
2092 $$$emit16$src$$constant;
2093 %}
2094
2095 enc_class Con_d32(immI src) %{
2096 emit_d32(cbuf,$src$$constant);
2097 %}
2098
2099 enc_class conmemref (eRegP t1) %{ // Con32(storeImmI)
2100 // Output immediate memory reference
2101 emit_rm(cbuf, 0x00, $t1$$reg, 0x05 );
2102 emit_d32(cbuf, 0x00);
2103 %}
2104
2105 enc_class lock_prefix( ) %{
2106 if( os::is_MP() )
2107 emit_opcode(cbuf,0xF0); // [Lock]
2108 %}
2109
2110 // Cmp-xchg long value.
2111 // Note: we need to swap rbx, and rcx before and after the
2112 // cmpxchg8 instruction because the instruction uses
2113 // rcx as the high order word of the new value to store but
2114 // our register encoding uses rbx,.
2115 enc_class enc_cmpxchg8(eSIRegP mem_ptr) %{
2116
2117 // XCHG rbx,ecx
2118 emit_opcode(cbuf,0x87);
2119 emit_opcode(cbuf,0xD9);
2120 // [Lock]
2121 if( os::is_MP() )
2122 emit_opcode(cbuf,0xF0);
2123 // CMPXCHG8 [Eptr]
2124 emit_opcode(cbuf,0x0F);
2125 emit_opcode(cbuf,0xC7);
2126 emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg );
2127 // XCHG rbx,ecx
2128 emit_opcode(cbuf,0x87);
2129 emit_opcode(cbuf,0xD9);
2130 %}
2131
2132 enc_class enc_cmpxchg(eSIRegP mem_ptr) %{
2133 // [Lock]
2134 if( os::is_MP() )
2135 emit_opcode(cbuf,0xF0);
2136
2137 // CMPXCHG [Eptr]
2138 emit_opcode(cbuf,0x0F);
2139 emit_opcode(cbuf,0xB1);
2140 emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg );
2141 %}
2142
2143 enc_class enc_flags_ne_to_boolean( iRegI res ) %{
2144 int res_encoding = $res$$reg;
2145
2146 // MOV res,0
2147 emit_opcode( cbuf, 0xB8 + res_encoding);
2148 emit_d32( cbuf, 0 );
2149 // JNE,s fail
2150 emit_opcode(cbuf,0x75);
2151 emit_d8(cbuf, 5 );
2152 // MOV res,1
2153 emit_opcode( cbuf, 0xB8 + res_encoding);
2154 emit_d32( cbuf, 1 );
2155 // fail:
2156 %}
2157
2158 enc_class set_instruction_start( ) %{
2159 cbuf.set_inst_mark(); // Mark start of opcode for reloc info in mem operand
2160 %}
2161
2162 enc_class RegMem (eRegI ereg, memory mem) %{ // emit_reg_mem
2163 int reg_encoding = $ereg$$reg;
2164 int base = $mem$$base;
2165 int index = $mem$$index;
2166 int scale = $mem$$scale;
2167 int displace = $mem$$disp;
2168 bool disp_is_oop = $mem->disp_is_oop();
2169 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2170 %}
2171
2172 enc_class RegMem_Hi(eRegL ereg, memory mem) %{ // emit_reg_mem
2173 int reg_encoding = HIGH_FROM_LOW($ereg$$reg); // Hi register of pair, computed from lo
2174 int base = $mem$$base;
2175 int index = $mem$$index;
2176 int scale = $mem$$scale;
2177 int displace = $mem$$disp + 4; // Offset is 4 further in memory
2178 assert( !$mem->disp_is_oop(), "Cannot add 4 to oop" );
2179 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, false/*disp_is_oop*/);
2180 %}
2181
2182 enc_class move_long_small_shift( eRegL dst, immI_1_31 cnt ) %{
2183 int r1, r2;
2184 if( $tertiary == 0xA4 ) { r1 = $dst$$reg; r2 = HIGH_FROM_LOW($dst$$reg); }
2185 else { r2 = $dst$$reg; r1 = HIGH_FROM_LOW($dst$$reg); }
2186 emit_opcode(cbuf,0x0F);
2187 emit_opcode(cbuf,$tertiary);
2188 emit_rm(cbuf, 0x3, r1, r2);
2189 emit_d8(cbuf,$cnt$$constant);
2190 emit_d8(cbuf,$primary);
2191 emit_rm(cbuf, 0x3, $secondary, r1);
2192 emit_d8(cbuf,$cnt$$constant);
2193 %}
2194
2195 enc_class move_long_big_shift_sign( eRegL dst, immI_32_63 cnt ) %{
2196 emit_opcode( cbuf, 0x8B ); // Move
2197 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg));
2198 emit_d8(cbuf,$primary);
2199 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
2200 emit_d8(cbuf,$cnt$$constant-32);
2201 emit_d8(cbuf,$primary);
2202 emit_rm(cbuf, 0x3, $secondary, HIGH_FROM_LOW($dst$$reg));
2203 emit_d8(cbuf,31);
2204 %}
2205
2206 enc_class move_long_big_shift_clr( eRegL dst, immI_32_63 cnt ) %{
2207 int r1, r2;
2208 if( $secondary == 0x5 ) { r1 = $dst$$reg; r2 = HIGH_FROM_LOW($dst$$reg); }
2209 else { r2 = $dst$$reg; r1 = HIGH_FROM_LOW($dst$$reg); }
2210
2211 emit_opcode( cbuf, 0x8B ); // Move r1,r2
2212 emit_rm(cbuf, 0x3, r1, r2);
2213 if( $cnt$$constant > 32 ) { // Shift, if not by zero
2214 emit_opcode(cbuf,$primary);
2215 emit_rm(cbuf, 0x3, $secondary, r1);
2216 emit_d8(cbuf,$cnt$$constant-32);
2217 }
2218 emit_opcode(cbuf,0x33); // XOR r2,r2
2219 emit_rm(cbuf, 0x3, r2, r2);
2220 %}
2221
2222 // Clone of RegMem but accepts an extra parameter to access each
2223 // half of a double in memory; it never needs relocation info.
2224 enc_class Mov_MemD_half_to_Reg (immI opcode, memory mem, immI disp_for_half, eRegI rm_reg) %{
2225 emit_opcode(cbuf,$opcode$$constant);
2226 int reg_encoding = $rm_reg$$reg;
2227 int base = $mem$$base;
2228 int index = $mem$$index;
2229 int scale = $mem$$scale;
2230 int displace = $mem$$disp + $disp_for_half$$constant;
2231 bool disp_is_oop = false;
2232 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2233 %}
2234
2235 // !!!!! Special Custom Code used by MemMove, and stack access instructions !!!!!
2236 //
2237 // Clone of RegMem except the RM-byte's reg/opcode field is an ADLC-time constant
2238 // and it never needs relocation information.
2239 // Frequently used to move data between FPU's Stack Top and memory.
2240 enc_class RMopc_Mem_no_oop (immI rm_opcode, memory mem) %{
2241 int rm_byte_opcode = $rm_opcode$$constant;
2242 int base = $mem$$base;
2243 int index = $mem$$index;
2244 int scale = $mem$$scale;
2245 int displace = $mem$$disp;
2246 assert( !$mem->disp_is_oop(), "No oops here because no relo info allowed" );
2247 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, false);
2248 %}
2249
2250 enc_class RMopc_Mem (immI rm_opcode, memory mem) %{
2251 int rm_byte_opcode = $rm_opcode$$constant;
2252 int base = $mem$$base;
2253 int index = $mem$$index;
2254 int scale = $mem$$scale;
2255 int displace = $mem$$disp;
2256 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
2257 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_is_oop);
2258 %}
2259
2260 enc_class RegLea (eRegI dst, eRegI src0, immI src1 ) %{ // emit_reg_lea
2261 int reg_encoding = $dst$$reg;
2262 int base = $src0$$reg; // 0xFFFFFFFF indicates no base
2263 int index = 0x04; // 0x04 indicates no index
2264 int scale = 0x00; // 0x00 indicates no scale
2265 int displace = $src1$$constant; // 0x00 indicates no displacement
2266 bool disp_is_oop = false;
2267 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2268 %}
2269
2270 enc_class min_enc (eRegI dst, eRegI src) %{ // MIN
2271 // Compare dst,src
2272 emit_opcode(cbuf,0x3B);
2273 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2274 // jmp dst < src around move
2275 emit_opcode(cbuf,0x7C);
2276 emit_d8(cbuf,2);
2277 // move dst,src
2278 emit_opcode(cbuf,0x8B);
2279 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2280 %}
2281
2282 enc_class max_enc (eRegI dst, eRegI src) %{ // MAX
2283 // Compare dst,src
2284 emit_opcode(cbuf,0x3B);
2285 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2286 // jmp dst > src around move
2287 emit_opcode(cbuf,0x7F);
2288 emit_d8(cbuf,2);
2289 // move dst,src
2290 emit_opcode(cbuf,0x8B);
2291 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2292 %}
2293
2294 enc_class enc_FP_store(memory mem, regD src) %{
2295 // If src is FPR1, we can just FST to store it.
2296 // Else we need to FLD it to FPR1, then FSTP to store/pop it.
2297 int reg_encoding = 0x2; // Just store
2298 int base = $mem$$base;
2299 int index = $mem$$index;
2300 int scale = $mem$$scale;
2301 int displace = $mem$$disp;
2302 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
2303 if( $src$$reg != FPR1L_enc ) {
2304 reg_encoding = 0x3; // Store & pop
2305 emit_opcode( cbuf, 0xD9 ); // FLD (i.e., push it)
2306 emit_d8( cbuf, 0xC0-1+$src$$reg );
2307 }
2308 cbuf.set_inst_mark(); // Mark start of opcode for reloc info in mem operand
2309 emit_opcode(cbuf,$primary);
2310 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2311 %}
2312
2313 enc_class neg_reg(eRegI dst) %{
2314 // NEG $dst
2315 emit_opcode(cbuf,0xF7);
2316 emit_rm(cbuf, 0x3, 0x03, $dst$$reg );
2317 %}
2318
2319 enc_class setLT_reg(eCXRegI dst) %{
2320 // SETLT $dst
2321 emit_opcode(cbuf,0x0F);
2322 emit_opcode(cbuf,0x9C);
2323 emit_rm( cbuf, 0x3, 0x4, $dst$$reg );
2324 %}
2325
2326 enc_class enc_cmpLTP(ncxRegI p, ncxRegI q, ncxRegI y, eCXRegI tmp) %{ // cadd_cmpLT
2327 int tmpReg = $tmp$$reg;
2328
2329 // SUB $p,$q
2330 emit_opcode(cbuf,0x2B);
2331 emit_rm(cbuf, 0x3, $p$$reg, $q$$reg);
2332 // SBB $tmp,$tmp
2333 emit_opcode(cbuf,0x1B);
2334 emit_rm(cbuf, 0x3, tmpReg, tmpReg);
2335 // AND $tmp,$y
2336 emit_opcode(cbuf,0x23);
2337 emit_rm(cbuf, 0x3, tmpReg, $y$$reg);
2338 // ADD $p,$tmp
2339 emit_opcode(cbuf,0x03);
2340 emit_rm(cbuf, 0x3, $p$$reg, tmpReg);
2341 %}
2342
2343 enc_class enc_cmpLTP_mem(eRegI p, eRegI q, memory mem, eCXRegI tmp) %{ // cadd_cmpLT
2344 int tmpReg = $tmp$$reg;
2345
2346 // SUB $p,$q
2347 emit_opcode(cbuf,0x2B);
2348 emit_rm(cbuf, 0x3, $p$$reg, $q$$reg);
2349 // SBB $tmp,$tmp
2350 emit_opcode(cbuf,0x1B);
2351 emit_rm(cbuf, 0x3, tmpReg, tmpReg);
2352 // AND $tmp,$y
2353 cbuf.set_inst_mark(); // Mark start of opcode for reloc info in mem operand
2354 emit_opcode(cbuf,0x23);
2355 int reg_encoding = tmpReg;
2356 int base = $mem$$base;
2357 int index = $mem$$index;
2358 int scale = $mem$$scale;
2359 int displace = $mem$$disp;
2360 bool disp_is_oop = $mem->disp_is_oop();
2361 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2362 // ADD $p,$tmp
2363 emit_opcode(cbuf,0x03);
2364 emit_rm(cbuf, 0x3, $p$$reg, tmpReg);
2365 %}
2366
2367 enc_class shift_left_long( eRegL dst, eCXRegI shift ) %{
2368 // TEST shift,32
2369 emit_opcode(cbuf,0xF7);
2370 emit_rm(cbuf, 0x3, 0, ECX_enc);
2371 emit_d32(cbuf,0x20);
2372 // JEQ,s small
2373 emit_opcode(cbuf, 0x74);
2374 emit_d8(cbuf, 0x04);
2375 // MOV $dst.hi,$dst.lo
2376 emit_opcode( cbuf, 0x8B );
2377 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg );
2378 // CLR $dst.lo
2379 emit_opcode(cbuf, 0x33);
2380 emit_rm(cbuf, 0x3, $dst$$reg, $dst$$reg);
2381 // small:
2382 // SHLD $dst.hi,$dst.lo,$shift
2383 emit_opcode(cbuf,0x0F);
2384 emit_opcode(cbuf,0xA5);
2385 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg));
2386 // SHL $dst.lo,$shift"
2387 emit_opcode(cbuf,0xD3);
2388 emit_rm(cbuf, 0x3, 0x4, $dst$$reg );
2389 %}
2390
2391 enc_class shift_right_long( eRegL dst, eCXRegI shift ) %{
2392 // TEST shift,32
2393 emit_opcode(cbuf,0xF7);
2394 emit_rm(cbuf, 0x3, 0, ECX_enc);
2395 emit_d32(cbuf,0x20);
2396 // JEQ,s small
2397 emit_opcode(cbuf, 0x74);
2398 emit_d8(cbuf, 0x04);
2399 // MOV $dst.lo,$dst.hi
2400 emit_opcode( cbuf, 0x8B );
2401 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) );
2402 // CLR $dst.hi
2403 emit_opcode(cbuf, 0x33);
2404 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($dst$$reg));
2405 // small:
2406 // SHRD $dst.lo,$dst.hi,$shift
2407 emit_opcode(cbuf,0x0F);
2408 emit_opcode(cbuf,0xAD);
2409 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg);
2410 // SHR $dst.hi,$shift"
2411 emit_opcode(cbuf,0xD3);
2412 emit_rm(cbuf, 0x3, 0x5, HIGH_FROM_LOW($dst$$reg) );
2413 %}
2414
2415 enc_class shift_right_arith_long( eRegL dst, eCXRegI shift ) %{
2416 // TEST shift,32
2417 emit_opcode(cbuf,0xF7);
2418 emit_rm(cbuf, 0x3, 0, ECX_enc);
2419 emit_d32(cbuf,0x20);
2420 // JEQ,s small
2421 emit_opcode(cbuf, 0x74);
2422 emit_d8(cbuf, 0x05);
2423 // MOV $dst.lo,$dst.hi
2424 emit_opcode( cbuf, 0x8B );
2425 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) );
2426 // SAR $dst.hi,31
2427 emit_opcode(cbuf, 0xC1);
2428 emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW($dst$$reg) );
2429 emit_d8(cbuf, 0x1F );
2430 // small:
2431 // SHRD $dst.lo,$dst.hi,$shift
2432 emit_opcode(cbuf,0x0F);
2433 emit_opcode(cbuf,0xAD);
2434 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg);
2435 // SAR $dst.hi,$shift"
2436 emit_opcode(cbuf,0xD3);
2437 emit_rm(cbuf, 0x3, 0x7, HIGH_FROM_LOW($dst$$reg) );
2438 %}
2439
2440
2441 // ----------------- Encodings for floating point unit -----------------
2442 // May leave result in FPU-TOS or FPU reg depending on opcodes
2443 enc_class OpcReg_F (regF src) %{ // FMUL, FDIV
2444 $$$emit8$primary;
2445 emit_rm(cbuf, 0x3, $secondary, $src$$reg );
2446 %}
2447
2448 // Pop argument in FPR0 with FSTP ST(0)
2449 enc_class PopFPU() %{
2450 emit_opcode( cbuf, 0xDD );
2451 emit_d8( cbuf, 0xD8 );
2452 %}
2453
2454 // !!!!! equivalent to Pop_Reg_F
2455 enc_class Pop_Reg_D( regD dst ) %{
2456 emit_opcode( cbuf, 0xDD ); // FSTP ST(i)
2457 emit_d8( cbuf, 0xD8+$dst$$reg );
2458 %}
2459
2460 enc_class Push_Reg_D( regD dst ) %{
2461 emit_opcode( cbuf, 0xD9 );
2462 emit_d8( cbuf, 0xC0-1+$dst$$reg ); // FLD ST(i-1)
2463 %}
2464
2465 enc_class strictfp_bias1( regD dst ) %{
2466 emit_opcode( cbuf, 0xDB ); // FLD m80real
2467 emit_opcode( cbuf, 0x2D );
2468 emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias1() );
2469 emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0
2470 emit_opcode( cbuf, 0xC8+$dst$$reg );
2471 %}
2472
2473 enc_class strictfp_bias2( regD dst ) %{
2474 emit_opcode( cbuf, 0xDB ); // FLD m80real
2475 emit_opcode( cbuf, 0x2D );
2476 emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias2() );
2477 emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0
2478 emit_opcode( cbuf, 0xC8+$dst$$reg );
2479 %}
2480
2481 // Special case for moving an integer register to a stack slot.
2482 enc_class OpcPRegSS( stackSlotI dst, eRegI src ) %{ // RegSS
2483 store_to_stackslot( cbuf, $primary, $src$$reg, $dst$$disp );
2484 %}
2485
2486 // Special case for moving a register to a stack slot.
2487 enc_class RegSS( stackSlotI dst, eRegI src ) %{ // RegSS
2488 // Opcode already emitted
2489 emit_rm( cbuf, 0x02, $src$$reg, ESP_enc ); // R/M byte
2490 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
2491 emit_d32(cbuf, $dst$$disp); // Displacement
2492 %}
2493
2494 // Push the integer in stackSlot 'src' onto FP-stack
2495 enc_class Push_Mem_I( memory src ) %{ // FILD [ESP+src]
2496 store_to_stackslot( cbuf, $primary, $secondary, $src$$disp );
2497 %}
2498
2499 // Push the float in stackSlot 'src' onto FP-stack
2500 enc_class Push_Mem_F( memory src ) %{ // FLD_S [ESP+src]
2501 store_to_stackslot( cbuf, 0xD9, 0x00, $src$$disp );
2502 %}
2503
2504 // Push the double in stackSlot 'src' onto FP-stack
2505 enc_class Push_Mem_D( memory src ) %{ // FLD_D [ESP+src]
2506 store_to_stackslot( cbuf, 0xDD, 0x00, $src$$disp );
2507 %}
2508
2509 // Push FPU's TOS float to a stack-slot, and pop FPU-stack
2510 enc_class Pop_Mem_F( stackSlotF dst ) %{ // FSTP_S [ESP+dst]
2511 store_to_stackslot( cbuf, 0xD9, 0x03, $dst$$disp );
2512 %}
2513
2514 // Same as Pop_Mem_F except for opcode
2515 // Push FPU's TOS double to a stack-slot, and pop FPU-stack
2516 enc_class Pop_Mem_D( stackSlotD dst ) %{ // FSTP_D [ESP+dst]
2517 store_to_stackslot( cbuf, 0xDD, 0x03, $dst$$disp );
2518 %}
2519
2520 enc_class Pop_Reg_F( regF dst ) %{
2521 emit_opcode( cbuf, 0xDD ); // FSTP ST(i)
2522 emit_d8( cbuf, 0xD8+$dst$$reg );
2523 %}
2524
2525 enc_class Push_Reg_F( regF dst ) %{
2526 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2527 emit_d8( cbuf, 0xC0-1+$dst$$reg );
2528 %}
2529
2530 // Push FPU's float to a stack-slot, and pop FPU-stack
2531 enc_class Pop_Mem_Reg_F( stackSlotF dst, regF src ) %{
2532 int pop = 0x02;
2533 if ($src$$reg != FPR1L_enc) {
2534 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2535 emit_d8( cbuf, 0xC0-1+$src$$reg );
2536 pop = 0x03;
2537 }
2538 store_to_stackslot( cbuf, 0xD9, pop, $dst$$disp ); // FST<P>_S [ESP+dst]
2539 %}
2540
2541 // Push FPU's double to a stack-slot, and pop FPU-stack
2542 enc_class Pop_Mem_Reg_D( stackSlotD dst, regD src ) %{
2543 int pop = 0x02;
2544 if ($src$$reg != FPR1L_enc) {
2545 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2546 emit_d8( cbuf, 0xC0-1+$src$$reg );
2547 pop = 0x03;
2548 }
2549 store_to_stackslot( cbuf, 0xDD, pop, $dst$$disp ); // FST<P>_D [ESP+dst]
2550 %}
2551
2552 // Push FPU's double to a FPU-stack-slot, and pop FPU-stack
2553 enc_class Pop_Reg_Reg_D( regD dst, regF src ) %{
2554 int pop = 0xD0 - 1; // -1 since we skip FLD
2555 if ($src$$reg != FPR1L_enc) {
2556 emit_opcode( cbuf, 0xD9 ); // FLD ST(src-1)
2557 emit_d8( cbuf, 0xC0-1+$src$$reg );
2558 pop = 0xD8;
2559 }
2560 emit_opcode( cbuf, 0xDD );
2561 emit_d8( cbuf, pop+$dst$$reg ); // FST<P> ST(i)
2562 %}
2563
2564
2565 enc_class Mul_Add_F( regF dst, regF src, regF src1, regF src2 ) %{
2566 MacroAssembler masm(&cbuf);
2567 masm.fld_s( $src1$$reg-1); // nothing at TOS, load TOS from src1.reg
2568 masm.fmul( $src2$$reg+0); // value at TOS
2569 masm.fadd( $src$$reg+0); // value at TOS
2570 masm.fstp_d( $dst$$reg+0); // value at TOS, popped off after store
2571 %}
2572
2573
2574 enc_class Push_Reg_Mod_D( regD dst, regD src) %{
2575 // load dst in FPR0
2576 emit_opcode( cbuf, 0xD9 );
2577 emit_d8( cbuf, 0xC0-1+$dst$$reg );
2578 if ($src$$reg != FPR1L_enc) {
2579 // fincstp
2580 emit_opcode (cbuf, 0xD9);
2581 emit_opcode (cbuf, 0xF7);
2582 // swap src with FPR1:
2583 // FXCH FPR1 with src
2584 emit_opcode(cbuf, 0xD9);
2585 emit_d8(cbuf, 0xC8-1+$src$$reg );
2586 // fdecstp
2587 emit_opcode (cbuf, 0xD9);
2588 emit_opcode (cbuf, 0xF6);
2589 }
2590 %}
2591
2592 enc_class Push_ModD_encoding( regXD src0, regXD src1) %{
2593 // Allocate a word
2594 emit_opcode(cbuf,0x83); // SUB ESP,8
2595 emit_opcode(cbuf,0xEC);
2596 emit_d8(cbuf,0x08);
2597
2598 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], src1
2599 emit_opcode (cbuf, 0x0F );
2600 emit_opcode (cbuf, 0x11 );
2601 encode_RegMem(cbuf, $src1$$reg, ESP_enc, 0x4, 0, 0, false);
2602
2603 emit_opcode(cbuf,0xDD ); // FLD_D [ESP]
2604 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
2605
2606 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], src0
2607 emit_opcode (cbuf, 0x0F );
2608 emit_opcode (cbuf, 0x11 );
2609 encode_RegMem(cbuf, $src0$$reg, ESP_enc, 0x4, 0, 0, false);
2610
2611 emit_opcode(cbuf,0xDD ); // FLD_D [ESP]
2612 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
2613
2614 %}
2615
2616 enc_class Push_ModX_encoding( regX src0, regX src1) %{
2617 // Allocate a word
2618 emit_opcode(cbuf,0x83); // SUB ESP,4
2619 emit_opcode(cbuf,0xEC);
2620 emit_d8(cbuf,0x04);
2621
2622 emit_opcode (cbuf, 0xF3 ); // MOVSS [ESP], src1
2623 emit_opcode (cbuf, 0x0F );
2624 emit_opcode (cbuf, 0x11 );
2625 encode_RegMem(cbuf, $src1$$reg, ESP_enc, 0x4, 0, 0, false);
2626
2627 emit_opcode(cbuf,0xD9 ); // FLD [ESP]
2628 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
2629
2630 emit_opcode (cbuf, 0xF3 ); // MOVSS [ESP], src0
2631 emit_opcode (cbuf, 0x0F );
2632 emit_opcode (cbuf, 0x11 );
2633 encode_RegMem(cbuf, $src0$$reg, ESP_enc, 0x4, 0, 0, false);
2634
2635 emit_opcode(cbuf,0xD9 ); // FLD [ESP]
2636 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
2637
2638 %}
2639
2640 enc_class Push_ResultXD(regXD dst) %{
2641 store_to_stackslot( cbuf, 0xDD, 0x03, 0 ); //FSTP [ESP]
2642
2643 // UseXmmLoadAndClearUpper ? movsd dst,[esp] : movlpd dst,[esp]
2644 emit_opcode (cbuf, UseXmmLoadAndClearUpper ? 0xF2 : 0x66);
2645 emit_opcode (cbuf, 0x0F );
2646 emit_opcode (cbuf, UseXmmLoadAndClearUpper ? 0x10 : 0x12);
2647 encode_RegMem(cbuf, $dst$$reg, ESP_enc, 0x4, 0, 0, false);
2648
2649 emit_opcode(cbuf,0x83); // ADD ESP,8
2650 emit_opcode(cbuf,0xC4);
2651 emit_d8(cbuf,0x08);
2652 %}
2653
2654 enc_class Push_ResultX(regX dst, immI d8) %{
2655 store_to_stackslot( cbuf, 0xD9, 0x03, 0 ); //FSTP_S [ESP]
2656
2657 emit_opcode (cbuf, 0xF3 ); // MOVSS dst(xmm), [ESP]
2658 emit_opcode (cbuf, 0x0F );
2659 emit_opcode (cbuf, 0x10 );
2660 encode_RegMem(cbuf, $dst$$reg, ESP_enc, 0x4, 0, 0, false);
2661
2662 emit_opcode(cbuf,0x83); // ADD ESP,d8 (4 or 8)
2663 emit_opcode(cbuf,0xC4);
2664 emit_d8(cbuf,$d8$$constant);
2665 %}
2666
2667 enc_class Push_SrcXD(regXD src) %{
2668 // Allocate a word
2669 emit_opcode(cbuf,0x83); // SUB ESP,8
2670 emit_opcode(cbuf,0xEC);
2671 emit_d8(cbuf,0x08);
2672
2673 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], src
2674 emit_opcode (cbuf, 0x0F );
2675 emit_opcode (cbuf, 0x11 );
2676 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false);
2677
2678 emit_opcode(cbuf,0xDD ); // FLD_D [ESP]
2679 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
2680 %}
2681
2682 enc_class push_stack_temp_qword() %{
2683 emit_opcode(cbuf,0x83); // SUB ESP,8
2684 emit_opcode(cbuf,0xEC);
2685 emit_d8 (cbuf,0x08);
2686 %}
2687
2688 enc_class pop_stack_temp_qword() %{
2689 emit_opcode(cbuf,0x83); // ADD ESP,8
2690 emit_opcode(cbuf,0xC4);
2691 emit_d8 (cbuf,0x08);
2692 %}
2693
2694 enc_class push_xmm_to_fpr1( regXD xmm_src ) %{
2695 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], xmm_src
2696 emit_opcode (cbuf, 0x0F );
2697 emit_opcode (cbuf, 0x11 );
2698 encode_RegMem(cbuf, $xmm_src$$reg, ESP_enc, 0x4, 0, 0, false);
2699
2700 emit_opcode(cbuf,0xDD ); // FLD_D [ESP]
2701 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
2702 %}
2703
2704 // Compute X^Y using Intel's fast hardware instructions, if possible.
2705 // Otherwise return a NaN.
2706 enc_class pow_exp_core_encoding %{
2707 // FPR1 holds Y*ln2(X). Compute FPR1 = 2^(Y*ln2(X))
2708 emit_opcode(cbuf,0xD9); emit_opcode(cbuf,0xC0); // fdup = fld st(0) Q Q
2709 emit_opcode(cbuf,0xD9); emit_opcode(cbuf,0xFC); // frndint int(Q) Q
2710 emit_opcode(cbuf,0xDC); emit_opcode(cbuf,0xE9); // fsub st(1) -= st(0); int(Q) frac(Q)
2711 emit_opcode(cbuf,0xDB); // FISTP [ESP] frac(Q)
2712 emit_opcode(cbuf,0x1C);
2713 emit_d8(cbuf,0x24);
2714 emit_opcode(cbuf,0xD9); emit_opcode(cbuf,0xF0); // f2xm1 2^frac(Q)-1
2715 emit_opcode(cbuf,0xD9); emit_opcode(cbuf,0xE8); // fld1 1 2^frac(Q)-1
2716 emit_opcode(cbuf,0xDE); emit_opcode(cbuf,0xC1); // faddp 2^frac(Q)
2717 emit_opcode(cbuf,0x8B); // mov rax,[esp+0]=int(Q)
2718 encode_RegMem(cbuf, EAX_enc, ESP_enc, 0x4, 0, 0, false);
2719 emit_opcode(cbuf,0xC7); // mov rcx,0xFFFFF800 - overflow mask
2720 emit_rm(cbuf, 0x3, 0x0, ECX_enc);
2721 emit_d32(cbuf,0xFFFFF800);
2722 emit_opcode(cbuf,0x81); // add rax,1023 - the double exponent bias
2723 emit_rm(cbuf, 0x3, 0x0, EAX_enc);
2724 emit_d32(cbuf,1023);
2725 emit_opcode(cbuf,0x8B); // mov rbx,eax
2726 emit_rm(cbuf, 0x3, EBX_enc, EAX_enc);
2727 emit_opcode(cbuf,0xC1); // shl rax,20 - Slide to exponent position
2728 emit_rm(cbuf,0x3,0x4,EAX_enc);
2729 emit_d8(cbuf,20);
2730 emit_opcode(cbuf,0x85); // test rbx,ecx - check for overflow
2731 emit_rm(cbuf, 0x3, EBX_enc, ECX_enc);
2732 emit_opcode(cbuf,0x0F); emit_opcode(cbuf,0x45); // CMOVne rax,ecx - overflow; stuff NAN into EAX
2733 emit_rm(cbuf, 0x3, EAX_enc, ECX_enc);
2734 emit_opcode(cbuf,0x89); // mov [esp+4],eax - Store as part of double word
2735 encode_RegMem(cbuf, EAX_enc, ESP_enc, 0x4, 0, 4, false);
2736 emit_opcode(cbuf,0xC7); // mov [esp+0],0 - [ESP] = (double)(1<<int(Q)) = 2^int(Q)
2737 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
2738 emit_d32(cbuf,0);
2739 emit_opcode(cbuf,0xDC); // fmul dword st(0),[esp+0]; FPR1 = 2^int(Q)*2^frac(Q) = 2^Q
2740 encode_RegMem(cbuf, 0x1, ESP_enc, 0x4, 0, 0, false);
2741 %}
2742
2743 // enc_class Pop_Reg_Mod_D( regD dst, regD src)
2744 // was replaced by Push_Result_Mod_D followed by Pop_Reg_X() or Pop_Mem_X()
2745
2746 enc_class Push_Result_Mod_D( regD src) %{
2747 if ($src$$reg != FPR1L_enc) {
2748 // fincstp
2749 emit_opcode (cbuf, 0xD9);
2750 emit_opcode (cbuf, 0xF7);
2751 // FXCH FPR1 with src
2752 emit_opcode(cbuf, 0xD9);
2753 emit_d8(cbuf, 0xC8-1+$src$$reg );
2754 // fdecstp
2755 emit_opcode (cbuf, 0xD9);
2756 emit_opcode (cbuf, 0xF6);
2757 }
2758 // // following asm replaced with Pop_Reg_F or Pop_Mem_F
2759 // // FSTP FPR$dst$$reg
2760 // emit_opcode( cbuf, 0xDD );
2761 // emit_d8( cbuf, 0xD8+$dst$$reg );
2762 %}
2763
2764 enc_class fnstsw_sahf_skip_parity() %{
2765 // fnstsw ax
2766 emit_opcode( cbuf, 0xDF );
2767 emit_opcode( cbuf, 0xE0 );
2768 // sahf
2769 emit_opcode( cbuf, 0x9E );
2770 // jnp ::skip
2771 emit_opcode( cbuf, 0x7B );
2772 emit_opcode( cbuf, 0x05 );
2773 %}
2774
2775 enc_class emitModD() %{
2776 // fprem must be iterative
2777 // :: loop
2778 // fprem
2779 emit_opcode( cbuf, 0xD9 );
2780 emit_opcode( cbuf, 0xF8 );
2781 // wait
2782 emit_opcode( cbuf, 0x9b );
2783 // fnstsw ax
2784 emit_opcode( cbuf, 0xDF );
2785 emit_opcode( cbuf, 0xE0 );
2786 // sahf
2787 emit_opcode( cbuf, 0x9E );
2788 // jp ::loop
2789 emit_opcode( cbuf, 0x0F );
2790 emit_opcode( cbuf, 0x8A );
2791 emit_opcode( cbuf, 0xF4 );
2792 emit_opcode( cbuf, 0xFF );
2793 emit_opcode( cbuf, 0xFF );
2794 emit_opcode( cbuf, 0xFF );
2795 %}
2796
2797 enc_class fpu_flags() %{
2798 // fnstsw_ax
2799 emit_opcode( cbuf, 0xDF);
2800 emit_opcode( cbuf, 0xE0);
2801 // test ax,0x0400
2802 emit_opcode( cbuf, 0x66 ); // operand-size prefix for 16-bit immediate
2803 emit_opcode( cbuf, 0xA9 );
2804 emit_d16 ( cbuf, 0x0400 );
2805 // // // This sequence works, but stalls for 12-16 cycles on PPro
2806 // // test rax,0x0400
2807 // emit_opcode( cbuf, 0xA9 );
2808 // emit_d32 ( cbuf, 0x00000400 );
2809 //
2810 // jz exit (no unordered comparison)
2811 emit_opcode( cbuf, 0x74 );
2812 emit_d8 ( cbuf, 0x02 );
2813 // mov ah,1 - treat as LT case (set carry flag)
2814 emit_opcode( cbuf, 0xB4 );
2815 emit_d8 ( cbuf, 0x01 );
2816 // sahf
2817 emit_opcode( cbuf, 0x9E);
2818 %}
2819
2820 enc_class cmpF_P6_fixup() %{
2821 // Fixup the integer flags in case comparison involved a NaN
2822 //
2823 // JNP exit (no unordered comparison, P-flag is set by NaN)
2824 emit_opcode( cbuf, 0x7B );
2825 emit_d8 ( cbuf, 0x03 );
2826 // MOV AH,1 - treat as LT case (set carry flag)
2827 emit_opcode( cbuf, 0xB4 );
2828 emit_d8 ( cbuf, 0x01 );
2829 // SAHF
2830 emit_opcode( cbuf, 0x9E);
2831 // NOP // target for branch to avoid branch to branch
2832 emit_opcode( cbuf, 0x90);
2833 %}
2834
2835 // fnstsw_ax();
2836 // sahf();
2837 // movl(dst, nan_result);
2838 // jcc(Assembler::parity, exit);
2839 // movl(dst, less_result);
2840 // jcc(Assembler::below, exit);
2841 // movl(dst, equal_result);
2842 // jcc(Assembler::equal, exit);
2843 // movl(dst, greater_result);
2844
2845 // less_result = 1;
2846 // greater_result = -1;
2847 // equal_result = 0;
2848 // nan_result = -1;
2849
2850 enc_class CmpF_Result(eRegI dst) %{
2851 // fnstsw_ax();
2852 emit_opcode( cbuf, 0xDF);
2853 emit_opcode( cbuf, 0xE0);
2854 // sahf
2855 emit_opcode( cbuf, 0x9E);
2856 // movl(dst, nan_result);
2857 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2858 emit_d32( cbuf, -1 );
2859 // jcc(Assembler::parity, exit);
2860 emit_opcode( cbuf, 0x7A );
2861 emit_d8 ( cbuf, 0x13 );
2862 // movl(dst, less_result);
2863 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2864 emit_d32( cbuf, -1 );
2865 // jcc(Assembler::below, exit);
2866 emit_opcode( cbuf, 0x72 );
2867 emit_d8 ( cbuf, 0x0C );
2868 // movl(dst, equal_result);
2869 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2870 emit_d32( cbuf, 0 );
2871 // jcc(Assembler::equal, exit);
2872 emit_opcode( cbuf, 0x74 );
2873 emit_d8 ( cbuf, 0x05 );
2874 // movl(dst, greater_result);
2875 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2876 emit_d32( cbuf, 1 );
2877 %}
2878
2879
2880 // XMM version of CmpF_Result. Because the XMM compare
2881 // instructions set the EFLAGS directly. It becomes simpler than
2882 // the float version above.
2883 enc_class CmpX_Result(eRegI dst) %{
2884 MacroAssembler _masm(&cbuf);
2885 Label nan, inc, done;
2886
2887 __ jccb(Assembler::parity, nan);
2888 __ jccb(Assembler::equal, done);
2889 __ jccb(Assembler::above, inc);
2890 __ bind(nan);
2891 __ decrement(as_Register($dst$$reg)); // NO L qqq
2892 __ jmpb(done);
2893 __ bind(inc);
2894 __ increment(as_Register($dst$$reg)); // NO L qqq
2895 __ bind(done);
2896 %}
2897
2898 // Compare the longs and set flags
2899 // BROKEN! Do Not use as-is
2900 enc_class cmpl_test( eRegL src1, eRegL src2 ) %{
2901 // CMP $src1.hi,$src2.hi
2902 emit_opcode( cbuf, 0x3B );
2903 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) );
2904 // JNE,s done
2905 emit_opcode(cbuf,0x75);
2906 emit_d8(cbuf, 2 );
2907 // CMP $src1.lo,$src2.lo
2908 emit_opcode( cbuf, 0x3B );
2909 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
2910 // done:
2911 %}
2912
2913 enc_class convert_int_long( regL dst, eRegI src ) %{
2914 // mov $dst.lo,$src
2915 int dst_encoding = $dst$$reg;
2916 int src_encoding = $src$$reg;
2917 encode_Copy( cbuf, dst_encoding , src_encoding );
2918 // mov $dst.hi,$src
2919 encode_Copy( cbuf, HIGH_FROM_LOW(dst_encoding), src_encoding );
2920 // sar $dst.hi,31
2921 emit_opcode( cbuf, 0xC1 );
2922 emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW(dst_encoding) );
2923 emit_d8(cbuf, 0x1F );
2924 %}
2925
2926 enc_class convert_long_double( eRegL src ) %{
2927 // push $src.hi
2928 emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg));
2929 // push $src.lo
2930 emit_opcode(cbuf, 0x50+$src$$reg );
2931 // fild 64-bits at [SP]
2932 emit_opcode(cbuf,0xdf);
2933 emit_d8(cbuf, 0x6C);
2934 emit_d8(cbuf, 0x24);
2935 emit_d8(cbuf, 0x00);
2936 // pop stack
2937 emit_opcode(cbuf, 0x83); // add SP, #8
2938 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
2939 emit_d8(cbuf, 0x8);
2940 %}
2941
2942 enc_class multiply_con_and_shift_high( eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr ) %{
2943 // IMUL EDX:EAX,$src1
2944 emit_opcode( cbuf, 0xF7 );
2945 emit_rm( cbuf, 0x3, 0x5, $src1$$reg );
2946 // SAR EDX,$cnt-32
2947 int shift_count = ((int)$cnt$$constant) - 32;
2948 if (shift_count > 0) {
2949 emit_opcode(cbuf, 0xC1);
2950 emit_rm(cbuf, 0x3, 7, $dst$$reg );
2951 emit_d8(cbuf, shift_count);
2952 }
2953 %}
2954
2955 // this version doesn't have add sp, 8
2956 enc_class convert_long_double2( eRegL src ) %{
2957 // push $src.hi
2958 emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg));
2959 // push $src.lo
2960 emit_opcode(cbuf, 0x50+$src$$reg );
2961 // fild 64-bits at [SP]
2962 emit_opcode(cbuf,0xdf);
2963 emit_d8(cbuf, 0x6C);
2964 emit_d8(cbuf, 0x24);
2965 emit_d8(cbuf, 0x00);
2966 %}
2967
2968 enc_class long_int_multiply( eADXRegL dst, nadxRegI src) %{
2969 // Basic idea: long = (long)int * (long)int
2970 // IMUL EDX:EAX, src
2971 emit_opcode( cbuf, 0xF7 );
2972 emit_rm( cbuf, 0x3, 0x5, $src$$reg);
2973 %}
2974
2975 enc_class long_uint_multiply( eADXRegL dst, nadxRegI src) %{
2976 // Basic Idea: long = (int & 0xffffffffL) * (int & 0xffffffffL)
2977 // MUL EDX:EAX, src
2978 emit_opcode( cbuf, 0xF7 );
2979 emit_rm( cbuf, 0x3, 0x4, $src$$reg);
2980 %}
2981
2982 enc_class long_multiply( eADXRegL dst, eRegL src, eRegI tmp ) %{
2983 // Basic idea: lo(result) = lo(x_lo * y_lo)
2984 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
2985 // MOV $tmp,$src.lo
2986 encode_Copy( cbuf, $tmp$$reg, $src$$reg );
2987 // IMUL $tmp,EDX
2988 emit_opcode( cbuf, 0x0F );
2989 emit_opcode( cbuf, 0xAF );
2990 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
2991 // MOV EDX,$src.hi
2992 encode_Copy( cbuf, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg) );
2993 // IMUL EDX,EAX
2994 emit_opcode( cbuf, 0x0F );
2995 emit_opcode( cbuf, 0xAF );
2996 emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg );
2997 // ADD $tmp,EDX
2998 emit_opcode( cbuf, 0x03 );
2999 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
3000 // MUL EDX:EAX,$src.lo
3001 emit_opcode( cbuf, 0xF7 );
3002 emit_rm( cbuf, 0x3, 0x4, $src$$reg );
3003 // ADD EDX,ESI
3004 emit_opcode( cbuf, 0x03 );
3005 emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $tmp$$reg );
3006 %}
3007
3008 enc_class long_multiply_con( eADXRegL dst, immL_127 src, eRegI tmp ) %{
3009 // Basic idea: lo(result) = lo(src * y_lo)
3010 // hi(result) = hi(src * y_lo) + lo(src * y_hi)
3011 // IMUL $tmp,EDX,$src
3012 emit_opcode( cbuf, 0x6B );
3013 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
3014 emit_d8( cbuf, (int)$src$$constant );
3015 // MOV EDX,$src
3016 emit_opcode(cbuf, 0xB8 + EDX_enc);
3017 emit_d32( cbuf, (int)$src$$constant );
3018 // MUL EDX:EAX,EDX
3019 emit_opcode( cbuf, 0xF7 );
3020 emit_rm( cbuf, 0x3, 0x4, EDX_enc );
3021 // ADD EDX,ESI
3022 emit_opcode( cbuf, 0x03 );
3023 emit_rm( cbuf, 0x3, EDX_enc, $tmp$$reg );
3024 %}
3025
3026 enc_class long_div( eRegL src1, eRegL src2 ) %{
3027 // PUSH src1.hi
3028 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) );
3029 // PUSH src1.lo
3030 emit_opcode(cbuf, 0x50+$src1$$reg );
3031 // PUSH src2.hi
3032 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) );
3033 // PUSH src2.lo
3034 emit_opcode(cbuf, 0x50+$src2$$reg );
3035 // CALL directly to the runtime
3036 cbuf.set_inst_mark();
3037 emit_opcode(cbuf,0xE8); // Call into runtime
3038 emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::ldiv) - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
3039 // Restore stack
3040 emit_opcode(cbuf, 0x83); // add SP, #framesize
3041 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
3042 emit_d8(cbuf, 4*4);
3043 %}
3044
3045 enc_class long_mod( eRegL src1, eRegL src2 ) %{
3046 // PUSH src1.hi
3047 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) );
3048 // PUSH src1.lo
3049 emit_opcode(cbuf, 0x50+$src1$$reg );
3050 // PUSH src2.hi
3051 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) );
3052 // PUSH src2.lo
3053 emit_opcode(cbuf, 0x50+$src2$$reg );
3054 // CALL directly to the runtime
3055 cbuf.set_inst_mark();
3056 emit_opcode(cbuf,0xE8); // Call into runtime
3057 emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::lrem ) - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
3058 // Restore stack
3059 emit_opcode(cbuf, 0x83); // add SP, #framesize
3060 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
3061 emit_d8(cbuf, 4*4);
3062 %}
3063
3064 enc_class long_cmp_flags0( eRegL src, eRegI tmp ) %{
3065 // MOV $tmp,$src.lo
3066 emit_opcode(cbuf, 0x8B);
3067 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg);
3068 // OR $tmp,$src.hi
3069 emit_opcode(cbuf, 0x0B);
3070 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg));
3071 %}
3072
3073 enc_class long_cmp_flags1( eRegL src1, eRegL src2 ) %{
3074 // CMP $src1.lo,$src2.lo
3075 emit_opcode( cbuf, 0x3B );
3076 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
3077 // JNE,s skip
3078 emit_cc(cbuf, 0x70, 0x5);
3079 emit_d8(cbuf,2);
3080 // CMP $src1.hi,$src2.hi
3081 emit_opcode( cbuf, 0x3B );
3082 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) );
3083 %}
3084
3085 enc_class long_cmp_flags2( eRegL src1, eRegL src2, eRegI tmp ) %{
3086 // CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits
3087 emit_opcode( cbuf, 0x3B );
3088 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
3089 // MOV $tmp,$src1.hi
3090 emit_opcode( cbuf, 0x8B );
3091 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src1$$reg) );
3092 // SBB $tmp,$src2.hi\t! Compute flags for long compare
3093 emit_opcode( cbuf, 0x1B );
3094 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src2$$reg) );
3095 %}
3096
3097 enc_class long_cmp_flags3( eRegL src, eRegI tmp ) %{
3098 // XOR $tmp,$tmp
3099 emit_opcode(cbuf,0x33); // XOR
3100 emit_rm(cbuf,0x3, $tmp$$reg, $tmp$$reg);
3101 // CMP $tmp,$src.lo
3102 emit_opcode( cbuf, 0x3B );
3103 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg );
3104 // SBB $tmp,$src.hi
3105 emit_opcode( cbuf, 0x1B );
3106 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg) );
3107 %}
3108
3109 // Sniff, sniff... smells like Gnu Superoptimizer
3110 enc_class neg_long( eRegL dst ) %{
3111 emit_opcode(cbuf,0xF7); // NEG hi
3112 emit_rm (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg));
3113 emit_opcode(cbuf,0xF7); // NEG lo
3114 emit_rm (cbuf,0x3, 0x3, $dst$$reg );
3115 emit_opcode(cbuf,0x83); // SBB hi,0
3116 emit_rm (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg));
3117 emit_d8 (cbuf,0 );
3118 %}
3119
3120 enc_class movq_ld(regXD dst, memory mem) %{
3121 MacroAssembler _masm(&cbuf);
3122 __ movq($dst$$XMMRegister, $mem$$Address);
3123 %}
3124
3125 enc_class movq_st(memory mem, regXD src) %{
3126 MacroAssembler _masm(&cbuf);
3127 __ movq($mem$$Address, $src$$XMMRegister);
3128 %}
3129
3130 enc_class pshufd_8x8(regX dst, regX src) %{
3131 MacroAssembler _masm(&cbuf);
3132
3133 encode_CopyXD(cbuf, $dst$$reg, $src$$reg);
3134 __ punpcklbw(as_XMMRegister($dst$$reg), as_XMMRegister($dst$$reg));
3135 __ pshuflw(as_XMMRegister($dst$$reg), as_XMMRegister($dst$$reg), 0x00);
3136 %}
3137
3138 enc_class pshufd_4x16(regX dst, regX src) %{
3139 MacroAssembler _masm(&cbuf);
3140
3141 __ pshuflw(as_XMMRegister($dst$$reg), as_XMMRegister($src$$reg), 0x00);
3142 %}
3143
3144 enc_class pshufd(regXD dst, regXD src, int mode) %{
3145 MacroAssembler _masm(&cbuf);
3146
3147 __ pshufd(as_XMMRegister($dst$$reg), as_XMMRegister($src$$reg), $mode);
3148 %}
3149
3150 enc_class pxor(regXD dst, regXD src) %{
3151 MacroAssembler _masm(&cbuf);
3152
3153 __ pxor(as_XMMRegister($dst$$reg), as_XMMRegister($src$$reg));
3154 %}
3155
3156 enc_class mov_i2x(regXD dst, eRegI src) %{
3157 MacroAssembler _masm(&cbuf);
3158
3159 __ movdl(as_XMMRegister($dst$$reg), as_Register($src$$reg));
3160 %}
3161
3162
3163 // Because the transitions from emitted code to the runtime
3164 // monitorenter/exit helper stubs are so slow it's critical that
3165 // we inline both the stack-locking fast-path and the inflated fast path.
3166 //
3167 // See also: cmpFastLock and cmpFastUnlock.
3168 //
3169 // What follows is a specialized inline transliteration of the code
3170 // in slow_enter() and slow_exit(). If we're concerned about I$ bloat
3171 // another option would be to emit TrySlowEnter and TrySlowExit methods
3172 // at startup-time. These methods would accept arguments as
3173 // (rax,=Obj, rbx=Self, rcx=box, rdx=Scratch) and return success-failure
3174 // indications in the icc.ZFlag. Fast_Lock and Fast_Unlock would simply
3175 // marshal the arguments and emit calls to TrySlowEnter and TrySlowExit.
3176 // In practice, however, the # of lock sites is bounded and is usually small.
3177 // Besides the call overhead, TrySlowEnter and TrySlowExit might suffer
3178 // if the processor uses simple bimodal branch predictors keyed by EIP
3179 // Since the helper routines would be called from multiple synchronization
3180 // sites.
3181 //
3182 // An even better approach would be write "MonitorEnter()" and "MonitorExit()"
3183 // in java - using j.u.c and unsafe - and just bind the lock and unlock sites
3184 // to those specialized methods. That'd give us a mostly platform-independent
3185 // implementation that the JITs could optimize and inline at their pleasure.
3186 // Done correctly, the only time we'd need to cross to native could would be
3187 // to park() or unpark() threads. We'd also need a few more unsafe operators
3188 // to (a) prevent compiler-JIT reordering of non-volatile accesses, and
3189 // (b) explicit barriers or fence operations.
3190 //
3191 // TODO:
3192 //
3193 // * Arrange for C2 to pass "Self" into Fast_Lock and Fast_Unlock in one of the registers (scr).
3194 // This avoids manifesting the Self pointer in the Fast_Lock and Fast_Unlock terminals.
3195 // Given TLAB allocation, Self is usually manifested in a register, so passing it into
3196 // the lock operators would typically be faster than reifying Self.
3197 //
3198 // * Ideally I'd define the primitives as:
3199 // fast_lock (nax Obj, nax box, EAX tmp, nax scr) where box, tmp and scr are KILLED.
3200 // fast_unlock (nax Obj, EAX box, nax tmp) where box and tmp are KILLED
3201 // Unfortunately ADLC bugs prevent us from expressing the ideal form.
3202 // Instead, we're stuck with a rather awkward and brittle register assignments below.
3203 // Furthermore the register assignments are overconstrained, possibly resulting in
3204 // sub-optimal code near the synchronization site.
3205 //
3206 // * Eliminate the sp-proximity tests and just use "== Self" tests instead.
3207 // Alternately, use a better sp-proximity test.
3208 //
3209 // * Currently ObjectMonitor._Owner can hold either an sp value or a (THREAD *) value.
3210 // Either one is sufficient to uniquely identify a thread.
3211 // TODO: eliminate use of sp in _owner and use get_thread(tr) instead.
3212 //
3213 // * Intrinsify notify() and notifyAll() for the common cases where the
3214 // object is locked by the calling thread but the waitlist is empty.
3215 // avoid the expensive JNI call to JVM_Notify() and JVM_NotifyAll().
3216 //
3217 // * use jccb and jmpb instead of jcc and jmp to improve code density.
3218 // But beware of excessive branch density on AMD Opterons.
3219 //
3220 // * Both Fast_Lock and Fast_Unlock set the ICC.ZF to indicate success
3221 // or failure of the fast-path. If the fast-path fails then we pass
3222 // control to the slow-path, typically in C. In Fast_Lock and
3223 // Fast_Unlock we often branch to DONE_LABEL, just to find that C2
3224 // will emit a conditional branch immediately after the node.
3225 // So we have branches to branches and lots of ICC.ZF games.
3226 // Instead, it might be better to have C2 pass a "FailureLabel"
3227 // into Fast_Lock and Fast_Unlock. In the case of success, control
3228 // will drop through the node. ICC.ZF is undefined at exit.
3229 // In the case of failure, the node will branch directly to the
3230 // FailureLabel
3231
3232
3233 // obj: object to lock
3234 // box: on-stack box address (displaced header location) - KILLED
3235 // rax,: tmp -- KILLED
3236 // scr: tmp -- KILLED
3237 enc_class Fast_Lock( eRegP obj, eRegP box, eAXRegI tmp, eRegP scr ) %{
3238
3239 Register objReg = as_Register($obj$$reg);
3240 Register boxReg = as_Register($box$$reg);
3241 Register tmpReg = as_Register($tmp$$reg);
3242 Register scrReg = as_Register($scr$$reg);
3243
3244 // Ensure the register assignents are disjoint
3245 guarantee (objReg != boxReg, "") ;
3246 guarantee (objReg != tmpReg, "") ;
3247 guarantee (objReg != scrReg, "") ;
3248 guarantee (boxReg != tmpReg, "") ;
3249 guarantee (boxReg != scrReg, "") ;
3250 guarantee (tmpReg == as_Register(EAX_enc), "") ;
3251
3252 MacroAssembler masm(&cbuf);
3253
3254 if (_counters != NULL) {
3255 masm.atomic_incl(ExternalAddress((address) _counters->total_entry_count_addr()));
3256 }
3257 if (EmitSync & 1) {
3258 // set box->dhw = unused_mark (3)
3259 // Force all sync thru slow-path: slow_enter() and slow_exit()
3260 masm.movptr (Address(boxReg, 0), int32_t(markOopDesc::unused_mark())) ;
3261 masm.cmpptr (rsp, (int32_t)0) ;
3262 } else
3263 if (EmitSync & 2) {
3264 Label DONE_LABEL ;
3265 if (UseBiasedLocking) {
3266 // Note: tmpReg maps to the swap_reg argument and scrReg to the tmp_reg argument.
3267 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters);
3268 }
3269
3270 masm.movptr(tmpReg, Address(objReg, 0)) ; // fetch markword
3271 masm.orptr (tmpReg, 0x1);
3272 masm.movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS
3273 if (os::is_MP()) { masm.lock(); }
3274 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
3275 masm.jcc(Assembler::equal, DONE_LABEL);
3276 // Recursive locking
3277 masm.subptr(tmpReg, rsp);
3278 masm.andptr(tmpReg, (int32_t) 0xFFFFF003 );
3279 masm.movptr(Address(boxReg, 0), tmpReg);
3280 masm.bind(DONE_LABEL) ;
3281 } else {
3282 // Possible cases that we'll encounter in fast_lock
3283 // ------------------------------------------------
3284 // * Inflated
3285 // -- unlocked
3286 // -- Locked
3287 // = by self
3288 // = by other
3289 // * biased
3290 // -- by Self
3291 // -- by other
3292 // * neutral
3293 // * stack-locked
3294 // -- by self
3295 // = sp-proximity test hits
3296 // = sp-proximity test generates false-negative
3297 // -- by other
3298 //
3299
3300 Label IsInflated, DONE_LABEL, PopDone ;
3301
3302 // TODO: optimize away redundant LDs of obj->mark and improve the markword triage
3303 // order to reduce the number of conditional branches in the most common cases.
3304 // Beware -- there's a subtle invariant that fetch of the markword
3305 // at [FETCH], below, will never observe a biased encoding (*101b).
3306 // If this invariant is not held we risk exclusion (safety) failure.
3307 if (UseBiasedLocking && !UseOptoBiasInlining) {
3308 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters);
3309 }
3310
3311 masm.movptr(tmpReg, Address(objReg, 0)) ; // [FETCH]
3312 masm.testptr(tmpReg, 0x02) ; // Inflated v (Stack-locked or neutral)
3313 masm.jccb (Assembler::notZero, IsInflated) ;
3314
3315 // Attempt stack-locking ...
3316 masm.orptr (tmpReg, 0x1);
3317 masm.movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS
3318 if (os::is_MP()) { masm.lock(); }
3319 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
3320 if (_counters != NULL) {
3321 masm.cond_inc32(Assembler::equal,
3322 ExternalAddress((address)_counters->fast_path_entry_count_addr()));
3323 }
3324 masm.jccb (Assembler::equal, DONE_LABEL);
3325
3326 // Recursive locking
3327 masm.subptr(tmpReg, rsp);
3328 masm.andptr(tmpReg, 0xFFFFF003 );
3329 masm.movptr(Address(boxReg, 0), tmpReg);
3330 if (_counters != NULL) {
3331 masm.cond_inc32(Assembler::equal,
3332 ExternalAddress((address)_counters->fast_path_entry_count_addr()));
3333 }
3334 masm.jmp (DONE_LABEL) ;
3335
3336 masm.bind (IsInflated) ;
3337
3338 // The object is inflated.
3339 //
3340 // TODO-FIXME: eliminate the ugly use of manifest constants:
3341 // Use markOopDesc::monitor_value instead of "2".
3342 // use markOop::unused_mark() instead of "3".
3343 // The tmpReg value is an objectMonitor reference ORed with
3344 // markOopDesc::monitor_value (2). We can either convert tmpReg to an
3345 // objectmonitor pointer by masking off the "2" bit or we can just
3346 // use tmpReg as an objectmonitor pointer but bias the objectmonitor
3347 // field offsets with "-2" to compensate for and annul the low-order tag bit.
3348 //
3349 // I use the latter as it avoids AGI stalls.
3350 // As such, we write "mov r, [tmpReg+OFFSETOF(Owner)-2]"
3351 // instead of "mov r, [tmpReg+OFFSETOF(Owner)]".
3352 //
3353 #define OFFSET_SKEWED(f) ((ObjectMonitor::f ## _offset_in_bytes())-2)
3354
3355 // boxReg refers to the on-stack BasicLock in the current frame.
3356 // We'd like to write:
3357 // set box->_displaced_header = markOop::unused_mark(). Any non-0 value suffices.
3358 // This is convenient but results a ST-before-CAS penalty. The following CAS suffers
3359 // additional latency as we have another ST in the store buffer that must drain.
3360
3361 if (EmitSync & 8192) {
3362 masm.movptr(Address(boxReg, 0), 3) ; // results in ST-before-CAS penalty
3363 masm.get_thread (scrReg) ;
3364 masm.movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
3365 masm.movptr(tmpReg, NULL_WORD); // consider: xor vs mov
3366 if (os::is_MP()) { masm.lock(); }
3367 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3368 } else
3369 if ((EmitSync & 128) == 0) { // avoid ST-before-CAS
3370 masm.movptr(scrReg, boxReg) ;
3371 masm.movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
3372
3373 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
3374 if ((EmitSync & 2048) && VM_Version::supports_3dnow() && os::is_MP()) {
3375 // prefetchw [eax + Offset(_owner)-2]
3376 masm.prefetchw(Address(rax, ObjectMonitor::owner_offset_in_bytes()-2));
3377 }
3378
3379 if ((EmitSync & 64) == 0) {
3380 // Optimistic form: consider XORL tmpReg,tmpReg
3381 masm.movptr(tmpReg, NULL_WORD) ;
3382 } else {
3383 // Can suffer RTS->RTO upgrades on shared or cold $ lines
3384 // Test-And-CAS instead of CAS
3385 masm.movptr(tmpReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; // rax, = m->_owner
3386 masm.testptr(tmpReg, tmpReg) ; // Locked ?
3387 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3388 }
3389
3390 // Appears unlocked - try to swing _owner from null to non-null.
3391 // Ideally, I'd manifest "Self" with get_thread and then attempt
3392 // to CAS the register containing Self into m->Owner.
3393 // But we don't have enough registers, so instead we can either try to CAS
3394 // rsp or the address of the box (in scr) into &m->owner. If the CAS succeeds
3395 // we later store "Self" into m->Owner. Transiently storing a stack address
3396 // (rsp or the address of the box) into m->owner is harmless.
3397 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
3398 if (os::is_MP()) { masm.lock(); }
3399 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3400 masm.movptr(Address(scrReg, 0), 3) ; // box->_displaced_header = 3
3401 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3402 masm.get_thread (scrReg) ; // beware: clobbers ICCs
3403 masm.movptr(Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2), scrReg) ;
3404 masm.xorptr(boxReg, boxReg) ; // set icc.ZFlag = 1 to indicate success
3405
3406 // If the CAS fails we can either retry or pass control to the slow-path.
3407 // We use the latter tactic.
3408 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
3409 // If the CAS was successful ...
3410 // Self has acquired the lock
3411 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
3412 // Intentional fall-through into DONE_LABEL ...
3413 } else {
3414 masm.movptr(Address(boxReg, 0), 3) ; // results in ST-before-CAS penalty
3415 masm.movptr(boxReg, tmpReg) ;
3416
3417 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
3418 if ((EmitSync & 2048) && VM_Version::supports_3dnow() && os::is_MP()) {
3419 // prefetchw [eax + Offset(_owner)-2]
3420 masm.prefetchw(Address(rax, ObjectMonitor::owner_offset_in_bytes()-2));
3421 }
3422
3423 if ((EmitSync & 64) == 0) {
3424 // Optimistic form
3425 masm.xorptr (tmpReg, tmpReg) ;
3426 } else {
3427 // Can suffer RTS->RTO upgrades on shared or cold $ lines
3428 masm.movptr(tmpReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; // rax, = m->_owner
3429 masm.testptr(tmpReg, tmpReg) ; // Locked ?
3430 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3431 }
3432
3433 // Appears unlocked - try to swing _owner from null to non-null.
3434 // Use either "Self" (in scr) or rsp as thread identity in _owner.
3435 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
3436 masm.get_thread (scrReg) ;
3437 if (os::is_MP()) { masm.lock(); }
3438 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3439
3440 // If the CAS fails we can either retry or pass control to the slow-path.
3441 // We use the latter tactic.
3442 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
3443 // If the CAS was successful ...
3444 // Self has acquired the lock
3445 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
3446 // Intentional fall-through into DONE_LABEL ...
3447 }
3448
3449 // DONE_LABEL is a hot target - we'd really like to place it at the
3450 // start of cache line by padding with NOPs.
3451 // See the AMD and Intel software optimization manuals for the
3452 // most efficient "long" NOP encodings.
3453 // Unfortunately none of our alignment mechanisms suffice.
3454 masm.bind(DONE_LABEL);
3455
3456 // Avoid branch-to-branch on AMD processors
3457 // This appears to be superstition.
3458 if (EmitSync & 32) masm.nop() ;
3459
3460
3461 // At DONE_LABEL the icc ZFlag is set as follows ...
3462 // Fast_Unlock uses the same protocol.
3463 // ZFlag == 1 -> Success
3464 // ZFlag == 0 -> Failure - force control through the slow-path
3465 }
3466 %}
3467
3468 // obj: object to unlock
3469 // box: box address (displaced header location), killed. Must be EAX.
3470 // rbx,: killed tmp; cannot be obj nor box.
3471 //
3472 // Some commentary on balanced locking:
3473 //
3474 // Fast_Lock and Fast_Unlock are emitted only for provably balanced lock sites.
3475 // Methods that don't have provably balanced locking are forced to run in the
3476 // interpreter - such methods won't be compiled to use fast_lock and fast_unlock.
3477 // The interpreter provides two properties:
3478 // I1: At return-time the interpreter automatically and quietly unlocks any
3479 // objects acquired the current activation (frame). Recall that the
3480 // interpreter maintains an on-stack list of locks currently held by
3481 // a frame.
3482 // I2: If a method attempts to unlock an object that is not held by the
3483 // the frame the interpreter throws IMSX.
3484 //
3485 // Lets say A(), which has provably balanced locking, acquires O and then calls B().
3486 // B() doesn't have provably balanced locking so it runs in the interpreter.
3487 // Control returns to A() and A() unlocks O. By I1 and I2, above, we know that O
3488 // is still locked by A().
3489 //
3490 // The only other source of unbalanced locking would be JNI. The "Java Native Interface:
3491 // Programmer's Guide and Specification" claims that an object locked by jni_monitorenter
3492 // should not be unlocked by "normal" java-level locking and vice-versa. The specification
3493 // doesn't specify what will occur if a program engages in such mixed-mode locking, however.
3494
3495 enc_class Fast_Unlock( nabxRegP obj, eAXRegP box, eRegP tmp) %{
3496
3497 Register objReg = as_Register($obj$$reg);
3498 Register boxReg = as_Register($box$$reg);
3499 Register tmpReg = as_Register($tmp$$reg);
3500
3501 guarantee (objReg != boxReg, "") ;
3502 guarantee (objReg != tmpReg, "") ;
3503 guarantee (boxReg != tmpReg, "") ;
3504 guarantee (boxReg == as_Register(EAX_enc), "") ;
3505 MacroAssembler masm(&cbuf);
3506
3507 if (EmitSync & 4) {
3508 // Disable - inhibit all inlining. Force control through the slow-path
3509 masm.cmpptr (rsp, 0) ;
3510 } else
3511 if (EmitSync & 8) {
3512 Label DONE_LABEL ;
3513 if (UseBiasedLocking) {
3514 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL);
3515 }
3516 // classic stack-locking code ...
3517 masm.movptr(tmpReg, Address(boxReg, 0)) ;
3518 masm.testptr(tmpReg, tmpReg) ;
3519 masm.jcc (Assembler::zero, DONE_LABEL) ;
3520 if (os::is_MP()) { masm.lock(); }
3521 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses EAX which is box
3522 masm.bind(DONE_LABEL);
3523 } else {
3524 Label DONE_LABEL, Stacked, CheckSucc, Inflated ;
3525
3526 // Critically, the biased locking test must have precedence over
3527 // and appear before the (box->dhw == 0) recursive stack-lock test.
3528 if (UseBiasedLocking && !UseOptoBiasInlining) {
3529 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL);
3530 }
3531
3532 masm.cmpptr(Address(boxReg, 0), 0) ; // Examine the displaced header
3533 masm.movptr(tmpReg, Address(objReg, 0)) ; // Examine the object's markword
3534 masm.jccb (Assembler::zero, DONE_LABEL) ; // 0 indicates recursive stack-lock
3535
3536 masm.testptr(tmpReg, 0x02) ; // Inflated?
3537 masm.jccb (Assembler::zero, Stacked) ;
3538
3539 masm.bind (Inflated) ;
3540 // It's inflated.
3541 // Despite our balanced locking property we still check that m->_owner == Self
3542 // as java routines or native JNI code called by this thread might
3543 // have released the lock.
3544 // Refer to the comments in synchronizer.cpp for how we might encode extra
3545 // state in _succ so we can avoid fetching EntryList|cxq.
3546 //
3547 // I'd like to add more cases in fast_lock() and fast_unlock() --
3548 // such as recursive enter and exit -- but we have to be wary of
3549 // I$ bloat, T$ effects and BP$ effects.
3550 //
3551 // If there's no contention try a 1-0 exit. That is, exit without
3552 // a costly MEMBAR or CAS. See synchronizer.cpp for details on how
3553 // we detect and recover from the race that the 1-0 exit admits.
3554 //
3555 // Conceptually Fast_Unlock() must execute a STST|LDST "release" barrier
3556 // before it STs null into _owner, releasing the lock. Updates
3557 // to data protected by the critical section must be visible before
3558 // we drop the lock (and thus before any other thread could acquire
3559 // the lock and observe the fields protected by the lock).
3560 // IA32's memory-model is SPO, so STs are ordered with respect to
3561 // each other and there's no need for an explicit barrier (fence).
3562 // See also http://gee.cs.oswego.edu/dl/jmm/cookbook.html.
3563
3564 masm.get_thread (boxReg) ;
3565 if ((EmitSync & 4096) && VM_Version::supports_3dnow() && os::is_MP()) {
3566 // prefetchw [ebx + Offset(_owner)-2]
3567 masm.prefetchw(Address(rbx, ObjectMonitor::owner_offset_in_bytes()-2));
3568 }
3569
3570 // Note that we could employ various encoding schemes to reduce
3571 // the number of loads below (currently 4) to just 2 or 3.
3572 // Refer to the comments in synchronizer.cpp.
3573 // In practice the chain of fetches doesn't seem to impact performance, however.
3574 if ((EmitSync & 65536) == 0 && (EmitSync & 256)) {
3575 // Attempt to reduce branch density - AMD's branch predictor.
3576 masm.xorptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3577 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ;
3578 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ;
3579 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ;
3580 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3581 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ;
3582 masm.jmpb (DONE_LABEL) ;
3583 } else {
3584 masm.xorptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3585 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ;
3586 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3587 masm.movptr(boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ;
3588 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ;
3589 masm.jccb (Assembler::notZero, CheckSucc) ;
3590 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ;
3591 masm.jmpb (DONE_LABEL) ;
3592 }
3593
3594 // The Following code fragment (EmitSync & 65536) improves the performance of
3595 // contended applications and contended synchronization microbenchmarks.
3596 // Unfortunately the emission of the code - even though not executed - causes regressions
3597 // in scimark and jetstream, evidently because of $ effects. Replacing the code
3598 // with an equal number of never-executed NOPs results in the same regression.
3599 // We leave it off by default.
3600
3601 if ((EmitSync & 65536) != 0) {
3602 Label LSuccess, LGoSlowPath ;
3603
3604 masm.bind (CheckSucc) ;
3605
3606 // Optional pre-test ... it's safe to elide this
3607 if ((EmitSync & 16) == 0) {
3608 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), 0) ;
3609 masm.jccb (Assembler::zero, LGoSlowPath) ;
3610 }
3611
3612 // We have a classic Dekker-style idiom:
3613 // ST m->_owner = 0 ; MEMBAR; LD m->_succ
3614 // There are a number of ways to implement the barrier:
3615 // (1) lock:andl &m->_owner, 0
3616 // is fast, but mask doesn't currently support the "ANDL M,IMM32" form.
3617 // LOCK: ANDL [ebx+Offset(_Owner)-2], 0
3618 // Encodes as 81 31 OFF32 IMM32 or 83 63 OFF8 IMM8
3619 // (2) If supported, an explicit MFENCE is appealing.
3620 // In older IA32 processors MFENCE is slower than lock:add or xchg
3621 // particularly if the write-buffer is full as might be the case if
3622 // if stores closely precede the fence or fence-equivalent instruction.
3623 // In more modern implementations MFENCE appears faster, however.
3624 // (3) In lieu of an explicit fence, use lock:addl to the top-of-stack
3625 // The $lines underlying the top-of-stack should be in M-state.
3626 // The locked add instruction is serializing, of course.
3627 // (4) Use xchg, which is serializing
3628 // mov boxReg, 0; xchgl boxReg, [tmpReg + Offset(_owner)-2] also works
3629 // (5) ST m->_owner = 0 and then execute lock:orl &m->_succ, 0.
3630 // The integer condition codes will tell us if succ was 0.
3631 // Since _succ and _owner should reside in the same $line and
3632 // we just stored into _owner, it's likely that the $line
3633 // remains in M-state for the lock:orl.
3634 //
3635 // We currently use (3), although it's likely that switching to (2)
3636 // is correct for the future.
3637
3638 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ;
3639 if (os::is_MP()) {
3640 if (VM_Version::supports_sse2() && 1 == FenceInstruction) {
3641 masm.mfence();
3642 } else {
3643 masm.lock () ; masm.addptr(Address(rsp, 0), 0) ;
3644 }
3645 }
3646 // Ratify _succ remains non-null
3647 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), 0) ;
3648 masm.jccb (Assembler::notZero, LSuccess) ;
3649
3650 masm.xorptr(boxReg, boxReg) ; // box is really EAX
3651 if (os::is_MP()) { masm.lock(); }
3652 masm.cmpxchgptr(rsp, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2));
3653 masm.jccb (Assembler::notEqual, LSuccess) ;
3654 // Since we're low on registers we installed rsp as a placeholding in _owner.
3655 // Now install Self over rsp. This is safe as we're transitioning from
3656 // non-null to non=null
3657 masm.get_thread (boxReg) ;
3658 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), boxReg) ;
3659 // Intentional fall-through into LGoSlowPath ...
3660
3661 masm.bind (LGoSlowPath) ;
3662 masm.orptr(boxReg, 1) ; // set ICC.ZF=0 to indicate failure
3663 masm.jmpb (DONE_LABEL) ;
3664
3665 masm.bind (LSuccess) ;
3666 masm.xorptr(boxReg, boxReg) ; // set ICC.ZF=1 to indicate success
3667 masm.jmpb (DONE_LABEL) ;
3668 }
3669
3670 masm.bind (Stacked) ;
3671 // It's not inflated and it's not recursively stack-locked and it's not biased.
3672 // It must be stack-locked.
3673 // Try to reset the header to displaced header.
3674 // The "box" value on the stack is stable, so we can reload
3675 // and be assured we observe the same value as above.
3676 masm.movptr(tmpReg, Address(boxReg, 0)) ;
3677 if (os::is_MP()) { masm.lock(); }
3678 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses EAX which is box
3679 // Intention fall-thru into DONE_LABEL
3680
3681
3682 // DONE_LABEL is a hot target - we'd really like to place it at the
3683 // start of cache line by padding with NOPs.
3684 // See the AMD and Intel software optimization manuals for the
3685 // most efficient "long" NOP encodings.
3686 // Unfortunately none of our alignment mechanisms suffice.
3687 if ((EmitSync & 65536) == 0) {
3688 masm.bind (CheckSucc) ;
3689 }
3690 masm.bind(DONE_LABEL);
3691
3692 // Avoid branch to branch on AMD processors
3693 if (EmitSync & 32768) { masm.nop() ; }
3694 }
3695 %}
3696
3697 enc_class enc_String_Compare(eDIRegP str1, eSIRegP str2, regXD tmp1, regXD tmp2,
3698 eAXRegI tmp3, eBXRegI tmp4, eCXRegI result) %{
3699 Label ECX_GOOD_LABEL, LENGTH_DIFF_LABEL,
3700 POP_LABEL, DONE_LABEL, CONT_LABEL,
3701 WHILE_HEAD_LABEL;
3702 MacroAssembler masm(&cbuf);
3703
3704 XMMRegister tmp1Reg = as_XMMRegister($tmp1$$reg);
3705 XMMRegister tmp2Reg = as_XMMRegister($tmp2$$reg);
3706
3707 // Get the first character position in both strings
3708 // [8] char array, [12] offset, [16] count
3709 int value_offset = java_lang_String::value_offset_in_bytes();
3710 int offset_offset = java_lang_String::offset_offset_in_bytes();
3711 int count_offset = java_lang_String::count_offset_in_bytes();
3712 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR);
3713
3714 masm.movptr(rax, Address(rsi, value_offset));
3715 masm.movl(rcx, Address(rsi, offset_offset));
3716 masm.lea(rax, Address(rax, rcx, Address::times_2, base_offset));
3717 masm.movptr(rbx, Address(rdi, value_offset));
3718 masm.movl(rcx, Address(rdi, offset_offset));
3719 masm.lea(rbx, Address(rbx, rcx, Address::times_2, base_offset));
3720
3721 // Compute the minimum of the string lengths(rsi) and the
3722 // difference of the string lengths (stack)
3723
3724 if (VM_Version::supports_cmov()) {
3725 masm.movl(rdi, Address(rdi, count_offset));
3726 masm.movl(rsi, Address(rsi, count_offset));
3727 masm.movl(rcx, rdi);
3728 masm.subl(rdi, rsi);
3729 masm.push(rdi);
3730 masm.cmovl(Assembler::lessEqual, rsi, rcx);
3731 } else {
3732 masm.movl(rdi, Address(rdi, count_offset));
3733 masm.movl(rcx, Address(rsi, count_offset));
3734 masm.movl(rsi, rdi);
3735 masm.subl(rdi, rcx);
3736 masm.push(rdi);
3737 masm.jccb(Assembler::lessEqual, ECX_GOOD_LABEL);
3738 masm.movl(rsi, rcx);
3739 // rsi holds min, rcx is unused
3740 }
3741
3742 // Is the minimum length zero?
3743 masm.bind(ECX_GOOD_LABEL);
3744 masm.testl(rsi, rsi);
3745 masm.jcc(Assembler::zero, LENGTH_DIFF_LABEL);
3746
3747 // Load first characters
3748 masm.load_unsigned_short(rcx, Address(rbx, 0));
3749 masm.load_unsigned_short(rdi, Address(rax, 0));
3750
3751 // Compare first characters
3752 masm.subl(rcx, rdi);
3753 masm.jcc(Assembler::notZero, POP_LABEL);
3754 masm.decrementl(rsi);
3755 masm.jcc(Assembler::zero, LENGTH_DIFF_LABEL);
3756
3757 {
3758 // Check after comparing first character to see if strings are equivalent
3759 Label LSkip2;
3760 // Check if the strings start at same location
3761 masm.cmpptr(rbx,rax);
3762 masm.jccb(Assembler::notEqual, LSkip2);
3763
3764 // Check if the length difference is zero (from stack)
3765 masm.cmpl(Address(rsp, 0), 0x0);
3766 masm.jcc(Assembler::equal, LENGTH_DIFF_LABEL);
3767
3768 // Strings might not be equivalent
3769 masm.bind(LSkip2);
3770 }
3771
3772 // Advance to next character
3773 masm.addptr(rax, 2);
3774 masm.addptr(rbx, 2);
3775
3776 if (UseSSE42Intrinsics) {
3777 // With SSE4.2, use double quad vector compare
3778 Label COMPARE_VECTORS, VECTOR_NOT_EQUAL, COMPARE_TAIL;
3779 // Setup to compare 16-byte vectors
3780 masm.movl(rdi, rsi);
3781 masm.andl(rsi, 0xfffffff8); // rsi holds the vector count
3782 masm.andl(rdi, 0x00000007); // rdi holds the tail count
3783 masm.testl(rsi, rsi);
3784 masm.jccb(Assembler::zero, COMPARE_TAIL);
3785
3786 masm.lea(rax, Address(rax, rsi, Address::times_2));
3787 masm.lea(rbx, Address(rbx, rsi, Address::times_2));
3788 masm.negl(rsi);
3789
3790 masm.bind(COMPARE_VECTORS);
3791 masm.movdqu(tmp1Reg, Address(rax, rsi, Address::times_2));
3792 masm.movdqu(tmp2Reg, Address(rbx, rsi, Address::times_2));
3793 masm.pxor(tmp1Reg, tmp2Reg);
3794 masm.ptest(tmp1Reg, tmp1Reg);
3795 masm.jccb(Assembler::notZero, VECTOR_NOT_EQUAL);
3796 masm.addl(rsi, 8);
3797 masm.jcc(Assembler::notZero, COMPARE_VECTORS);
3798 masm.jmpb(COMPARE_TAIL);
3799
3800 // Mismatched characters in the vectors
3801 masm.bind(VECTOR_NOT_EQUAL);
3802 masm.lea(rax, Address(rax, rsi, Address::times_2));
3803 masm.lea(rbx, Address(rbx, rsi, Address::times_2));
3804 masm.movl(rdi, 8);
3805
3806 // Compare tail (< 8 chars), or rescan last vectors to
3807 // find 1st mismatched characters
3808 masm.bind(COMPARE_TAIL);
3809 masm.testl(rdi, rdi);
3810 masm.jccb(Assembler::zero, LENGTH_DIFF_LABEL);
3811 masm.movl(rsi, rdi);
3812 // Fallthru to tail compare
3813 }
3814
3815 //Shift rax, and rbx, to the end of the arrays, negate min
3816 masm.lea(rax, Address(rax, rsi, Address::times_2, 0));
3817 masm.lea(rbx, Address(rbx, rsi, Address::times_2, 0));
3818 masm.negl(rsi);
3819
3820 // Compare the rest of the characters
3821 masm.bind(WHILE_HEAD_LABEL);
3822 masm.load_unsigned_short(rcx, Address(rbx, rsi, Address::times_2, 0));
3823 masm.load_unsigned_short(rdi, Address(rax, rsi, Address::times_2, 0));
3824 masm.subl(rcx, rdi);
3825 masm.jccb(Assembler::notZero, POP_LABEL);
3826 masm.incrementl(rsi);
3827 masm.jcc(Assembler::notZero, WHILE_HEAD_LABEL);
3828
3829 // Strings are equal up to min length. Return the length difference.
3830 masm.bind(LENGTH_DIFF_LABEL);
3831 masm.pop(rcx);
3832 masm.jmpb(DONE_LABEL);
3833
3834 // Discard the stored length difference
3835 masm.bind(POP_LABEL);
3836 masm.addptr(rsp, 4);
3837
3838 // That's it
3839 masm.bind(DONE_LABEL);
3840 %}
3841
3842 enc_class enc_String_Equals(eDIRegP str1, eSIRegP str2, regXD tmp1, regXD tmp2,
3843 eBXRegI tmp3, eCXRegI tmp4, eAXRegI result) %{
3844 Label RET_TRUE, RET_FALSE, DONE, COMPARE_VECTORS, COMPARE_CHAR;
3845 MacroAssembler masm(&cbuf);
3846
3847 XMMRegister tmp1Reg = as_XMMRegister($tmp1$$reg);
3848 XMMRegister tmp2Reg = as_XMMRegister($tmp2$$reg);
3849
3850 int value_offset = java_lang_String::value_offset_in_bytes();
3851 int offset_offset = java_lang_String::offset_offset_in_bytes();
3852 int count_offset = java_lang_String::count_offset_in_bytes();
3853 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR);
3854
3855 // does source == target string?
3856 masm.cmpptr(rdi, rsi);
3857 masm.jcc(Assembler::equal, RET_TRUE);
3858
3859 // get and compare counts
3860 masm.movl(rcx, Address(rdi, count_offset));
3861 masm.movl(rax, Address(rsi, count_offset));
3862 masm.cmpl(rcx, rax);
3863 masm.jcc(Assembler::notEqual, RET_FALSE);
3864 masm.testl(rax, rax);
3865 masm.jcc(Assembler::zero, RET_TRUE);
3866
3867 // get source string offset and value
3868 masm.movptr(rbx, Address(rsi, value_offset));
3869 masm.movl(rax, Address(rsi, offset_offset));
3870 masm.leal(rsi, Address(rbx, rax, Address::times_2, base_offset));
3871
3872 // get compare string offset and value
3873 masm.movptr(rbx, Address(rdi, value_offset));
3874 masm.movl(rax, Address(rdi, offset_offset));
3875 masm.leal(rdi, Address(rbx, rax, Address::times_2, base_offset));
3876
3877 // Set byte count
3878 masm.shll(rcx, 1);
3879 masm.movl(rax, rcx);
3880
3881 if (UseSSE42Intrinsics) {
3882 // With SSE4.2, use double quad vector compare
3883 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
3884 // Compare 16-byte vectors
3885 masm.andl(rcx, 0xfffffff0); // vector count (in bytes)
3886 masm.andl(rax, 0x0000000e); // tail count (in bytes)
3887 masm.testl(rcx, rcx);
3888 masm.jccb(Assembler::zero, COMPARE_TAIL);
3889 masm.lea(rdi, Address(rdi, rcx, Address::times_1));
3890 masm.lea(rsi, Address(rsi, rcx, Address::times_1));
3891 masm.negl(rcx);
3892
3893 masm.bind(COMPARE_WIDE_VECTORS);
3894 masm.movdqu(tmp1Reg, Address(rdi, rcx, Address::times_1));
3895 masm.movdqu(tmp2Reg, Address(rsi, rcx, Address::times_1));
3896 masm.pxor(tmp1Reg, tmp2Reg);
3897 masm.ptest(tmp1Reg, tmp1Reg);
3898 masm.jccb(Assembler::notZero, RET_FALSE);
3899 masm.addl(rcx, 16);
3900 masm.jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
3901 masm.bind(COMPARE_TAIL);
3902 masm.movl(rcx, rax);
3903 // Fallthru to tail compare
3904 }
3905
3906 // Compare 4-byte vectors
3907 masm.andl(rcx, 0xfffffffc); // vector count (in bytes)
3908 masm.andl(rax, 0x00000002); // tail char (in bytes)
3909 masm.testl(rcx, rcx);
3910 masm.jccb(Assembler::zero, COMPARE_CHAR);
3911 masm.lea(rdi, Address(rdi, rcx, Address::times_1));
3912 masm.lea(rsi, Address(rsi, rcx, Address::times_1));
3913 masm.negl(rcx);
3914
3915 masm.bind(COMPARE_VECTORS);
3916 masm.movl(rbx, Address(rdi, rcx, Address::times_1));
3917 masm.cmpl(rbx, Address(rsi, rcx, Address::times_1));
3918 masm.jccb(Assembler::notEqual, RET_FALSE);
3919 masm.addl(rcx, 4);
3920 masm.jcc(Assembler::notZero, COMPARE_VECTORS);
3921
3922 // Compare trailing char (final 2 bytes), if any
3923 masm.bind(COMPARE_CHAR);
3924 masm.testl(rax, rax);
3925 masm.jccb(Assembler::zero, RET_TRUE);
3926 masm.load_unsigned_short(rbx, Address(rdi, 0));
3927 masm.load_unsigned_short(rcx, Address(rsi, 0));
3928 masm.cmpl(rbx, rcx);
3929 masm.jccb(Assembler::notEqual, RET_FALSE);
3930
3931 masm.bind(RET_TRUE);
3932 masm.movl(rax, 1); // return true
3933 masm.jmpb(DONE);
3934
3935 masm.bind(RET_FALSE);
3936 masm.xorl(rax, rax); // return false
3937
3938 masm.bind(DONE);
3939 %}
3940
3941 enc_class enc_String_IndexOf(eSIRegP str1, eDIRegP str2, regXD tmp1, eAXRegI tmp2,
3942 eCXRegI tmp3, eDXRegI tmp4, eBXRegI result) %{
3943 // SSE4.2 version
3944 Label LOAD_SUBSTR, PREP_FOR_SCAN, SCAN_TO_SUBSTR,
3945 SCAN_SUBSTR, RET_NEG_ONE, RET_NOT_FOUND, CLEANUP, DONE;
3946 MacroAssembler masm(&cbuf);
3947
3948 XMMRegister tmp1Reg = as_XMMRegister($tmp1$$reg);
3949
3950 // Get the first character position in both strings
3951 // [8] char array, [12] offset, [16] count
3952 int value_offset = java_lang_String::value_offset_in_bytes();
3953 int offset_offset = java_lang_String::offset_offset_in_bytes();
3954 int count_offset = java_lang_String::count_offset_in_bytes();
3955 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR);
3956
3957 // Get counts for string and substr
3958 masm.movl(rdx, Address(rsi, count_offset));
3959 masm.movl(rax, Address(rdi, count_offset));
3960 // Check for substr count > string count
3961 masm.cmpl(rax, rdx);
3962 masm.jcc(Assembler::greater, RET_NEG_ONE);
3963
3964 // Start the indexOf operation
3965 // Get start addr of string
3966 masm.movptr(rbx, Address(rsi, value_offset));
3967 masm.movl(rcx, Address(rsi, offset_offset));
3968 masm.lea(rsi, Address(rbx, rcx, Address::times_2, base_offset));
3969 masm.push(rsi);
3970
3971 // Get start addr of substr
3972 masm.movptr(rbx, Address(rdi, value_offset));
3973 masm.movl(rcx, Address(rdi, offset_offset));
3974 masm.lea(rdi, Address(rbx, rcx, Address::times_2, base_offset));
3975 masm.push(rdi);
3976 masm.push(rax);
3977 masm.jmpb(PREP_FOR_SCAN);
3978
3979 // Substr count saved at sp
3980 // Substr saved at sp+4
3981 // String saved at sp+8
3982
3983 // Prep to load substr for scan
3984 masm.bind(LOAD_SUBSTR);
3985 masm.movptr(rdi, Address(rsp, 4));
3986 masm.movl(rax, Address(rsp, 0));
3987
3988 // Load substr
3989 masm.bind(PREP_FOR_SCAN);
3990 masm.movdqu(tmp1Reg, Address(rdi, 0));
3991 masm.addl(rdx, 8); // prime the loop
3992 masm.subptr(rsi, 16);
3993
3994 // Scan string for substr in 16-byte vectors
3995 masm.bind(SCAN_TO_SUBSTR);
3996 masm.subl(rdx, 8);
3997 masm.addptr(rsi, 16);
3998 masm.pcmpestri(tmp1Reg, Address(rsi, 0), 0x0d);
3999 masm.jcc(Assembler::above, SCAN_TO_SUBSTR); // CF == 0 && ZF == 0
4000 masm.jccb(Assembler::aboveEqual, RET_NOT_FOUND); // CF == 0
4001
4002 // Fallthru: found a potential substr
4003
4004 // Make sure string is still long enough
4005 masm.subl(rdx, rcx);
4006 masm.cmpl(rdx, rax);
4007 masm.jccb(Assembler::negative, RET_NOT_FOUND);
4008 // Compute start addr of substr
4009 masm.lea(rsi, Address(rsi, rcx, Address::times_2));
4010 masm.movptr(rbx, rsi);
4011
4012 // Compare potential substr
4013 masm.addl(rdx, 8); // prime the loop
4014 masm.addl(rax, 8);
4015 masm.subptr(rsi, 16);
4016 masm.subptr(rdi, 16);
4017
4018 // Scan 16-byte vectors of string and substr
4019 masm.bind(SCAN_SUBSTR);
4020 masm.subl(rax, 8);
4021 masm.subl(rdx, 8);
4022 masm.addptr(rsi, 16);
4023 masm.addptr(rdi, 16);
4024 masm.movdqu(tmp1Reg, Address(rdi, 0));
4025 masm.pcmpestri(tmp1Reg, Address(rsi, 0), 0x0d);
4026 masm.jcc(Assembler::noOverflow, LOAD_SUBSTR); // OF == 0
4027 masm.jcc(Assembler::positive, SCAN_SUBSTR); // SF == 0
4028
4029 // Compute substr offset
4030 masm.movptr(rsi, Address(rsp, 8));
4031 masm.subptr(rbx, rsi);
4032 masm.shrl(rbx, 1);
4033 masm.jmpb(CLEANUP);
4034
4035 masm.bind(RET_NEG_ONE);
4036 masm.movl(rbx, -1);
4037 masm.jmpb(DONE);
4038
4039 masm.bind(RET_NOT_FOUND);
4040 masm.movl(rbx, -1);
4041
4042 masm.bind(CLEANUP);
4043 masm.addptr(rsp, 12);
4044
4045 masm.bind(DONE);
4046 %}
4047
4048 enc_class enc_Array_Equals(eDIRegP ary1, eSIRegP ary2, regXD tmp1, regXD tmp2,
4049 eBXRegI tmp3, eDXRegI tmp4, eAXRegI result) %{
4050 Label TRUE_LABEL, FALSE_LABEL, DONE, COMPARE_VECTORS, COMPARE_CHAR;
4051 MacroAssembler masm(&cbuf);
4052
4053 XMMRegister tmp1Reg = as_XMMRegister($tmp1$$reg);
4054 XMMRegister tmp2Reg = as_XMMRegister($tmp2$$reg);
4055 Register ary1Reg = as_Register($ary1$$reg);
4056 Register ary2Reg = as_Register($ary2$$reg);
4057 Register tmp3Reg = as_Register($tmp3$$reg);
4058 Register tmp4Reg = as_Register($tmp4$$reg);
4059 Register resultReg = as_Register($result$$reg);
4060
4061 int length_offset = arrayOopDesc::length_offset_in_bytes();
4062 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR);
4063
4064 // Check the input args
4065 masm.cmpptr(ary1Reg, ary2Reg);
4066 masm.jcc(Assembler::equal, TRUE_LABEL);
4067 masm.testptr(ary1Reg, ary1Reg);
4068 masm.jcc(Assembler::zero, FALSE_LABEL);
4069 masm.testptr(ary2Reg, ary2Reg);
4070 masm.jcc(Assembler::zero, FALSE_LABEL);
4071
4072 // Check the lengths
4073 masm.movl(tmp4Reg, Address(ary1Reg, length_offset));
4074 masm.movl(resultReg, Address(ary2Reg, length_offset));
4075 masm.cmpl(tmp4Reg, resultReg);
4076 masm.jcc(Assembler::notEqual, FALSE_LABEL);
4077 masm.testl(resultReg, resultReg);
4078 masm.jcc(Assembler::zero, TRUE_LABEL);
4079
4080 // Load array addrs
4081 masm.lea(ary1Reg, Address(ary1Reg, base_offset));
4082 masm.lea(ary2Reg, Address(ary2Reg, base_offset));
4083
4084 // Set byte count
4085 masm.shll(tmp4Reg, 1);
4086 masm.movl(resultReg, tmp4Reg);
4087
4088 if (UseSSE42Intrinsics) {
4089 // With SSE4.2, use double quad vector compare
4090 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
4091 // Compare 16-byte vectors
4092 masm.andl(tmp4Reg, 0xfffffff0); // vector count (in bytes)
4093 masm.andl(resultReg, 0x0000000e); // tail count (in bytes)
4094 masm.testl(tmp4Reg, tmp4Reg);
4095 masm.jccb(Assembler::zero, COMPARE_TAIL);
4096 masm.lea(ary1Reg, Address(ary1Reg, tmp4Reg, Address::times_1));
4097 masm.lea(ary2Reg, Address(ary2Reg, tmp4Reg, Address::times_1));
4098 masm.negl(tmp4Reg);
4099
4100 masm.bind(COMPARE_WIDE_VECTORS);
4101 masm.movdqu(tmp1Reg, Address(ary1Reg, tmp4Reg, Address::times_1));
4102 masm.movdqu(tmp2Reg, Address(ary2Reg, tmp4Reg, Address::times_1));
4103 masm.pxor(tmp1Reg, tmp2Reg);
4104 masm.ptest(tmp1Reg, tmp1Reg);
4105
4106 masm.jccb(Assembler::notZero, FALSE_LABEL);
4107 masm.addl(tmp4Reg, 16);
4108 masm.jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
4109 masm.bind(COMPARE_TAIL);
4110 masm.movl(tmp4Reg, resultReg);
4111 // Fallthru to tail compare
4112 }
4113
4114 // Compare 4-byte vectors
4115 masm.andl(tmp4Reg, 0xfffffffc); // vector count (in bytes)
4116 masm.andl(resultReg, 0x00000002); // tail char (in bytes)
4117 masm.testl(tmp4Reg, tmp4Reg);
4118 masm.jccb(Assembler::zero, COMPARE_CHAR);
4119 masm.lea(ary1Reg, Address(ary1Reg, tmp4Reg, Address::times_1));
4120 masm.lea(ary2Reg, Address(ary2Reg, tmp4Reg, Address::times_1));
4121 masm.negl(tmp4Reg);
4122
4123 masm.bind(COMPARE_VECTORS);
4124 masm.movl(tmp3Reg, Address(ary1Reg, tmp4Reg, Address::times_1));
4125 masm.cmpl(tmp3Reg, Address(ary2Reg, tmp4Reg, Address::times_1));
4126 masm.jccb(Assembler::notEqual, FALSE_LABEL);
4127 masm.addl(tmp4Reg, 4);
4128 masm.jcc(Assembler::notZero, COMPARE_VECTORS);
4129
4130 // Compare trailing char (final 2 bytes), if any
4131 masm.bind(COMPARE_CHAR);
4132 masm.testl(resultReg, resultReg);
4133 masm.jccb(Assembler::zero, TRUE_LABEL);
4134 masm.load_unsigned_short(tmp3Reg, Address(ary1Reg, 0));
4135 masm.load_unsigned_short(tmp4Reg, Address(ary2Reg, 0));
4136 masm.cmpl(tmp3Reg, tmp4Reg);
4137 masm.jccb(Assembler::notEqual, FALSE_LABEL);
4138
4139 masm.bind(TRUE_LABEL);
4140 masm.movl(resultReg, 1); // return true
4141 masm.jmpb(DONE);
4142
4143 masm.bind(FALSE_LABEL);
4144 masm.xorl(resultReg, resultReg); // return false
4145
4146 // That's it
4147 masm.bind(DONE);
4148 %}
4149
4150 enc_class enc_pop_rdx() %{
4151 emit_opcode(cbuf,0x5A);
4152 %}
4153
4154 enc_class enc_rethrow() %{
4155 cbuf.set_inst_mark();
4156 emit_opcode(cbuf, 0xE9); // jmp entry
4157 emit_d32_reloc(cbuf, (int)OptoRuntime::rethrow_stub() - ((int)cbuf.code_end())-4,
4158 runtime_call_Relocation::spec(), RELOC_IMM32 );
4159 %}
4160
4161
4162 // Convert a double to an int. Java semantics require we do complex
4163 // manglelations in the corner cases. So we set the rounding mode to
4164 // 'zero', store the darned double down as an int, and reset the
4165 // rounding mode to 'nearest'. The hardware throws an exception which
4166 // patches up the correct value directly to the stack.
4167 enc_class D2I_encoding( regD src ) %{
4168 // Flip to round-to-zero mode. We attempted to allow invalid-op
4169 // exceptions here, so that a NAN or other corner-case value will
4170 // thrown an exception (but normal values get converted at full speed).
4171 // However, I2C adapters and other float-stack manglers leave pending
4172 // invalid-op exceptions hanging. We would have to clear them before
4173 // enabling them and that is more expensive than just testing for the
4174 // invalid value Intel stores down in the corner cases.
4175 emit_opcode(cbuf,0xD9); // FLDCW trunc
4176 emit_opcode(cbuf,0x2D);
4177 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
4178 // Allocate a word
4179 emit_opcode(cbuf,0x83); // SUB ESP,4
4180 emit_opcode(cbuf,0xEC);
4181 emit_d8(cbuf,0x04);
4182 // Encoding assumes a double has been pushed into FPR0.
4183 // Store down the double as an int, popping the FPU stack
4184 emit_opcode(cbuf,0xDB); // FISTP [ESP]
4185 emit_opcode(cbuf,0x1C);
4186 emit_d8(cbuf,0x24);
4187 // Restore the rounding mode; mask the exception
4188 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode
4189 emit_opcode(cbuf,0x2D);
4190 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
4191 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
4192 : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
4193
4194 // Load the converted int; adjust CPU stack
4195 emit_opcode(cbuf,0x58); // POP EAX
4196 emit_opcode(cbuf,0x3D); // CMP EAX,imm
4197 emit_d32 (cbuf,0x80000000); // 0x80000000
4198 emit_opcode(cbuf,0x75); // JNE around_slow_call
4199 emit_d8 (cbuf,0x07); // Size of slow_call
4200 // Push src onto stack slow-path
4201 emit_opcode(cbuf,0xD9 ); // FLD ST(i)
4202 emit_d8 (cbuf,0xC0-1+$src$$reg );
4203 // CALL directly to the runtime
4204 cbuf.set_inst_mark();
4205 emit_opcode(cbuf,0xE8); // Call into runtime
4206 emit_d32_reloc(cbuf, (StubRoutines::d2i_wrapper() - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
4207 // Carry on here...
4208 %}
4209
4210 enc_class D2L_encoding( regD src ) %{
4211 emit_opcode(cbuf,0xD9); // FLDCW trunc
4212 emit_opcode(cbuf,0x2D);
4213 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
4214 // Allocate a word
4215 emit_opcode(cbuf,0x83); // SUB ESP,8
4216 emit_opcode(cbuf,0xEC);
4217 emit_d8(cbuf,0x08);
4218 // Encoding assumes a double has been pushed into FPR0.
4219 // Store down the double as a long, popping the FPU stack
4220 emit_opcode(cbuf,0xDF); // FISTP [ESP]
4221 emit_opcode(cbuf,0x3C);
4222 emit_d8(cbuf,0x24);
4223 // Restore the rounding mode; mask the exception
4224 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode
4225 emit_opcode(cbuf,0x2D);
4226 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
4227 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
4228 : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
4229
4230 // Load the converted int; adjust CPU stack
4231 emit_opcode(cbuf,0x58); // POP EAX
4232 emit_opcode(cbuf,0x5A); // POP EDX
4233 emit_opcode(cbuf,0x81); // CMP EDX,imm
4234 emit_d8 (cbuf,0xFA); // rdx
4235 emit_d32 (cbuf,0x80000000); // 0x80000000
4236 emit_opcode(cbuf,0x75); // JNE around_slow_call
4237 emit_d8 (cbuf,0x07+4); // Size of slow_call
4238 emit_opcode(cbuf,0x85); // TEST EAX,EAX
4239 emit_opcode(cbuf,0xC0); // 2/rax,/rax,
4240 emit_opcode(cbuf,0x75); // JNE around_slow_call
4241 emit_d8 (cbuf,0x07); // Size of slow_call
4242 // Push src onto stack slow-path
4243 emit_opcode(cbuf,0xD9 ); // FLD ST(i)
4244 emit_d8 (cbuf,0xC0-1+$src$$reg );
4245 // CALL directly to the runtime
4246 cbuf.set_inst_mark();
4247 emit_opcode(cbuf,0xE8); // Call into runtime
4248 emit_d32_reloc(cbuf, (StubRoutines::d2l_wrapper() - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
4249 // Carry on here...
4250 %}
4251
4252 enc_class X2L_encoding( regX src ) %{
4253 // Allocate a word
4254 emit_opcode(cbuf,0x83); // SUB ESP,8
4255 emit_opcode(cbuf,0xEC);
4256 emit_d8(cbuf,0x08);
4257
4258 emit_opcode (cbuf, 0xF3 ); // MOVSS [ESP], src
4259 emit_opcode (cbuf, 0x0F );
4260 emit_opcode (cbuf, 0x11 );
4261 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false);
4262
4263 emit_opcode(cbuf,0xD9 ); // FLD_S [ESP]
4264 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
4265
4266 emit_opcode(cbuf,0xD9); // FLDCW trunc
4267 emit_opcode(cbuf,0x2D);
4268 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
4269
4270 // Encoding assumes a double has been pushed into FPR0.
4271 // Store down the double as a long, popping the FPU stack
4272 emit_opcode(cbuf,0xDF); // FISTP [ESP]
4273 emit_opcode(cbuf,0x3C);
4274 emit_d8(cbuf,0x24);
4275
4276 // Restore the rounding mode; mask the exception
4277 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode
4278 emit_opcode(cbuf,0x2D);
4279 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
4280 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
4281 : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
4282
4283 // Load the converted int; adjust CPU stack
4284 emit_opcode(cbuf,0x58); // POP EAX
4285
4286 emit_opcode(cbuf,0x5A); // POP EDX
4287
4288 emit_opcode(cbuf,0x81); // CMP EDX,imm
4289 emit_d8 (cbuf,0xFA); // rdx
4290 emit_d32 (cbuf,0x80000000);// 0x80000000
4291
4292 emit_opcode(cbuf,0x75); // JNE around_slow_call
4293 emit_d8 (cbuf,0x13+4); // Size of slow_call
4294
4295 emit_opcode(cbuf,0x85); // TEST EAX,EAX
4296 emit_opcode(cbuf,0xC0); // 2/rax,/rax,
4297
4298 emit_opcode(cbuf,0x75); // JNE around_slow_call
4299 emit_d8 (cbuf,0x13); // Size of slow_call
4300
4301 // Allocate a word
4302 emit_opcode(cbuf,0x83); // SUB ESP,4
4303 emit_opcode(cbuf,0xEC);
4304 emit_d8(cbuf,0x04);
4305
4306 emit_opcode (cbuf, 0xF3 ); // MOVSS [ESP], src
4307 emit_opcode (cbuf, 0x0F );
4308 emit_opcode (cbuf, 0x11 );
4309 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false);
4310
4311 emit_opcode(cbuf,0xD9 ); // FLD_S [ESP]
4312 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
4313
4314 emit_opcode(cbuf,0x83); // ADD ESP,4
4315 emit_opcode(cbuf,0xC4);
4316 emit_d8(cbuf,0x04);
4317
4318 // CALL directly to the runtime
4319 cbuf.set_inst_mark();
4320 emit_opcode(cbuf,0xE8); // Call into runtime
4321 emit_d32_reloc(cbuf, (StubRoutines::d2l_wrapper() - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
4322 // Carry on here...
4323 %}
4324
4325 enc_class XD2L_encoding( regXD src ) %{
4326 // Allocate a word
4327 emit_opcode(cbuf,0x83); // SUB ESP,8
4328 emit_opcode(cbuf,0xEC);
4329 emit_d8(cbuf,0x08);
4330
4331 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], src
4332 emit_opcode (cbuf, 0x0F );
4333 emit_opcode (cbuf, 0x11 );
4334 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false);
4335
4336 emit_opcode(cbuf,0xDD ); // FLD_D [ESP]
4337 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
4338
4339 emit_opcode(cbuf,0xD9); // FLDCW trunc
4340 emit_opcode(cbuf,0x2D);
4341 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
4342
4343 // Encoding assumes a double has been pushed into FPR0.
4344 // Store down the double as a long, popping the FPU stack
4345 emit_opcode(cbuf,0xDF); // FISTP [ESP]
4346 emit_opcode(cbuf,0x3C);
4347 emit_d8(cbuf,0x24);
4348
4349 // Restore the rounding mode; mask the exception
4350 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode
4351 emit_opcode(cbuf,0x2D);
4352 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
4353 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
4354 : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
4355
4356 // Load the converted int; adjust CPU stack
4357 emit_opcode(cbuf,0x58); // POP EAX
4358
4359 emit_opcode(cbuf,0x5A); // POP EDX
4360
4361 emit_opcode(cbuf,0x81); // CMP EDX,imm
4362 emit_d8 (cbuf,0xFA); // rdx
4363 emit_d32 (cbuf,0x80000000); // 0x80000000
4364
4365 emit_opcode(cbuf,0x75); // JNE around_slow_call
4366 emit_d8 (cbuf,0x13+4); // Size of slow_call
4367
4368 emit_opcode(cbuf,0x85); // TEST EAX,EAX
4369 emit_opcode(cbuf,0xC0); // 2/rax,/rax,
4370
4371 emit_opcode(cbuf,0x75); // JNE around_slow_call
4372 emit_d8 (cbuf,0x13); // Size of slow_call
4373
4374 // Push src onto stack slow-path
4375 // Allocate a word
4376 emit_opcode(cbuf,0x83); // SUB ESP,8
4377 emit_opcode(cbuf,0xEC);
4378 emit_d8(cbuf,0x08);
4379
4380 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], src
4381 emit_opcode (cbuf, 0x0F );
4382 emit_opcode (cbuf, 0x11 );
4383 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false);
4384
4385 emit_opcode(cbuf,0xDD ); // FLD_D [ESP]
4386 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
4387
4388 emit_opcode(cbuf,0x83); // ADD ESP,8
4389 emit_opcode(cbuf,0xC4);
4390 emit_d8(cbuf,0x08);
4391
4392 // CALL directly to the runtime
4393 cbuf.set_inst_mark();
4394 emit_opcode(cbuf,0xE8); // Call into runtime
4395 emit_d32_reloc(cbuf, (StubRoutines::d2l_wrapper() - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
4396 // Carry on here...
4397 %}
4398
4399 enc_class D2X_encoding( regX dst, regD src ) %{
4400 // Allocate a word
4401 emit_opcode(cbuf,0x83); // SUB ESP,4
4402 emit_opcode(cbuf,0xEC);
4403 emit_d8(cbuf,0x04);
4404 int pop = 0x02;
4405 if ($src$$reg != FPR1L_enc) {
4406 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
4407 emit_d8( cbuf, 0xC0-1+$src$$reg );
4408 pop = 0x03;
4409 }
4410 store_to_stackslot( cbuf, 0xD9, pop, 0 ); // FST<P>_S [ESP]
4411
4412 emit_opcode (cbuf, 0xF3 ); // MOVSS dst(xmm), [ESP]
4413 emit_opcode (cbuf, 0x0F );
4414 emit_opcode (cbuf, 0x10 );
4415 encode_RegMem(cbuf, $dst$$reg, ESP_enc, 0x4, 0, 0, false);
4416
4417 emit_opcode(cbuf,0x83); // ADD ESP,4
4418 emit_opcode(cbuf,0xC4);
4419 emit_d8(cbuf,0x04);
4420 // Carry on here...
4421 %}
4422
4423 enc_class FX2I_encoding( regX src, eRegI dst ) %{
4424 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
4425
4426 // Compare the result to see if we need to go to the slow path
4427 emit_opcode(cbuf,0x81); // CMP dst,imm
4428 emit_rm (cbuf,0x3,0x7,$dst$$reg);
4429 emit_d32 (cbuf,0x80000000); // 0x80000000
4430
4431 emit_opcode(cbuf,0x75); // JNE around_slow_call
4432 emit_d8 (cbuf,0x13); // Size of slow_call
4433 // Store xmm to a temp memory
4434 // location and push it onto stack.
4435
4436 emit_opcode(cbuf,0x83); // SUB ESP,4
4437 emit_opcode(cbuf,0xEC);
4438 emit_d8(cbuf, $primary ? 0x8 : 0x4);
4439
4440 emit_opcode (cbuf, $primary ? 0xF2 : 0xF3 ); // MOVSS [ESP], xmm
4441 emit_opcode (cbuf, 0x0F );
4442 emit_opcode (cbuf, 0x11 );
4443 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false);
4444
4445 emit_opcode(cbuf, $primary ? 0xDD : 0xD9 ); // FLD [ESP]
4446 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
4447
4448 emit_opcode(cbuf,0x83); // ADD ESP,4
4449 emit_opcode(cbuf,0xC4);
4450 emit_d8(cbuf, $primary ? 0x8 : 0x4);
4451
4452 // CALL directly to the runtime
4453 cbuf.set_inst_mark();
4454 emit_opcode(cbuf,0xE8); // Call into runtime
4455 emit_d32_reloc(cbuf, (StubRoutines::d2i_wrapper() - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
4456
4457 // Carry on here...
4458 %}
4459
4460 enc_class X2D_encoding( regD dst, regX src ) %{
4461 // Allocate a word
4462 emit_opcode(cbuf,0x83); // SUB ESP,4
4463 emit_opcode(cbuf,0xEC);
4464 emit_d8(cbuf,0x04);
4465
4466 emit_opcode (cbuf, 0xF3 ); // MOVSS [ESP], xmm
4467 emit_opcode (cbuf, 0x0F );
4468 emit_opcode (cbuf, 0x11 );
4469 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false);
4470
4471 emit_opcode(cbuf,0xD9 ); // FLD_S [ESP]
4472 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
4473
4474 emit_opcode(cbuf,0x83); // ADD ESP,4
4475 emit_opcode(cbuf,0xC4);
4476 emit_d8(cbuf,0x04);
4477
4478 // Carry on here...
4479 %}
4480
4481 enc_class AbsXF_encoding(regX dst) %{
4482 address signmask_address=(address)float_signmask_pool;
4483 // andpd:\tANDPS $dst,[signconst]
4484 emit_opcode(cbuf, 0x0F);
4485 emit_opcode(cbuf, 0x54);
4486 emit_rm(cbuf, 0x0, $dst$$reg, 0x5);
4487 emit_d32(cbuf, (int)signmask_address);
4488 %}
4489
4490 enc_class AbsXD_encoding(regXD dst) %{
4491 address signmask_address=(address)double_signmask_pool;
4492 // andpd:\tANDPD $dst,[signconst]
4493 emit_opcode(cbuf, 0x66);
4494 emit_opcode(cbuf, 0x0F);
4495 emit_opcode(cbuf, 0x54);
4496 emit_rm(cbuf, 0x0, $dst$$reg, 0x5);
4497 emit_d32(cbuf, (int)signmask_address);
4498 %}
4499
4500 enc_class NegXF_encoding(regX dst) %{
4501 address signmask_address=(address)float_signflip_pool;
4502 // andpd:\tXORPS $dst,[signconst]
4503 emit_opcode(cbuf, 0x0F);
4504 emit_opcode(cbuf, 0x57);
4505 emit_rm(cbuf, 0x0, $dst$$reg, 0x5);
4506 emit_d32(cbuf, (int)signmask_address);
4507 %}
4508
4509 enc_class NegXD_encoding(regXD dst) %{
4510 address signmask_address=(address)double_signflip_pool;
4511 // andpd:\tXORPD $dst,[signconst]
4512 emit_opcode(cbuf, 0x66);
4513 emit_opcode(cbuf, 0x0F);
4514 emit_opcode(cbuf, 0x57);
4515 emit_rm(cbuf, 0x0, $dst$$reg, 0x5);
4516 emit_d32(cbuf, (int)signmask_address);
4517 %}
4518
4519 enc_class FMul_ST_reg( eRegF src1 ) %{
4520 // Operand was loaded from memory into fp ST (stack top)
4521 // FMUL ST,$src /* D8 C8+i */
4522 emit_opcode(cbuf, 0xD8);
4523 emit_opcode(cbuf, 0xC8 + $src1$$reg);
4524 %}
4525
4526 enc_class FAdd_ST_reg( eRegF src2 ) %{
4527 // FADDP ST,src2 /* D8 C0+i */
4528 emit_opcode(cbuf, 0xD8);
4529 emit_opcode(cbuf, 0xC0 + $src2$$reg);
4530 //could use FADDP src2,fpST /* DE C0+i */
4531 %}
4532
4533 enc_class FAddP_reg_ST( eRegF src2 ) %{
4534 // FADDP src2,ST /* DE C0+i */
4535 emit_opcode(cbuf, 0xDE);
4536 emit_opcode(cbuf, 0xC0 + $src2$$reg);
4537 %}
4538
4539 enc_class subF_divF_encode( eRegF src1, eRegF src2) %{
4540 // Operand has been loaded into fp ST (stack top)
4541 // FSUB ST,$src1
4542 emit_opcode(cbuf, 0xD8);
4543 emit_opcode(cbuf, 0xE0 + $src1$$reg);
4544
4545 // FDIV
4546 emit_opcode(cbuf, 0xD8);
4547 emit_opcode(cbuf, 0xF0 + $src2$$reg);
4548 %}
4549
4550 enc_class MulFAddF (eRegF src1, eRegF src2) %{
4551 // Operand was loaded from memory into fp ST (stack top)
4552 // FADD ST,$src /* D8 C0+i */
4553 emit_opcode(cbuf, 0xD8);
4554 emit_opcode(cbuf, 0xC0 + $src1$$reg);
4555
4556 // FMUL ST,src2 /* D8 C*+i */
4557 emit_opcode(cbuf, 0xD8);
4558 emit_opcode(cbuf, 0xC8 + $src2$$reg);
4559 %}
4560
4561
4562 enc_class MulFAddFreverse (eRegF src1, eRegF src2) %{
4563 // Operand was loaded from memory into fp ST (stack top)
4564 // FADD ST,$src /* D8 C0+i */
4565 emit_opcode(cbuf, 0xD8);
4566 emit_opcode(cbuf, 0xC0 + $src1$$reg);
4567
4568 // FMULP src2,ST /* DE C8+i */
4569 emit_opcode(cbuf, 0xDE);
4570 emit_opcode(cbuf, 0xC8 + $src2$$reg);
4571 %}
4572
4573 // Atomically load the volatile long
4574 enc_class enc_loadL_volatile( memory mem, stackSlotL dst ) %{
4575 emit_opcode(cbuf,0xDF);
4576 int rm_byte_opcode = 0x05;
4577 int base = $mem$$base;
4578 int index = $mem$$index;
4579 int scale = $mem$$scale;
4580 int displace = $mem$$disp;
4581 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
4582 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_is_oop);
4583 store_to_stackslot( cbuf, 0x0DF, 0x07, $dst$$disp );
4584 %}
4585
4586 enc_class enc_loadLX_volatile( memory mem, stackSlotL dst, regXD tmp ) %{
4587 { // Atomic long load
4588 // UseXmmLoadAndClearUpper ? movsd $tmp,$mem : movlpd $tmp,$mem
4589 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0xF2 : 0x66);
4590 emit_opcode(cbuf,0x0F);
4591 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0x10 : 0x12);
4592 int base = $mem$$base;
4593 int index = $mem$$index;
4594 int scale = $mem$$scale;
4595 int displace = $mem$$disp;
4596 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
4597 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop);
4598 }
4599 { // MOVSD $dst,$tmp ! atomic long store
4600 emit_opcode(cbuf,0xF2);
4601 emit_opcode(cbuf,0x0F);
4602 emit_opcode(cbuf,0x11);
4603 int base = $dst$$base;
4604 int index = $dst$$index;
4605 int scale = $dst$$scale;
4606 int displace = $dst$$disp;
4607 bool disp_is_oop = $dst->disp_is_oop(); // disp-as-oop when working with static globals
4608 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop);
4609 }
4610 %}
4611
4612 enc_class enc_loadLX_reg_volatile( memory mem, eRegL dst, regXD tmp ) %{
4613 { // Atomic long load
4614 // UseXmmLoadAndClearUpper ? movsd $tmp,$mem : movlpd $tmp,$mem
4615 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0xF2 : 0x66);
4616 emit_opcode(cbuf,0x0F);
4617 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0x10 : 0x12);
4618 int base = $mem$$base;
4619 int index = $mem$$index;
4620 int scale = $mem$$scale;
4621 int displace = $mem$$disp;
4622 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
4623 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop);
4624 }
4625 { // MOVD $dst.lo,$tmp
4626 emit_opcode(cbuf,0x66);
4627 emit_opcode(cbuf,0x0F);
4628 emit_opcode(cbuf,0x7E);
4629 emit_rm(cbuf, 0x3, $tmp$$reg, $dst$$reg);
4630 }
4631 { // PSRLQ $tmp,32
4632 emit_opcode(cbuf,0x66);
4633 emit_opcode(cbuf,0x0F);
4634 emit_opcode(cbuf,0x73);
4635 emit_rm(cbuf, 0x3, 0x02, $tmp$$reg);
4636 emit_d8(cbuf, 0x20);
4637 }
4638 { // MOVD $dst.hi,$tmp
4639 emit_opcode(cbuf,0x66);
4640 emit_opcode(cbuf,0x0F);
4641 emit_opcode(cbuf,0x7E);
4642 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg));
4643 }
4644 %}
4645
4646 // Volatile Store Long. Must be atomic, so move it into
4647 // the FP TOS and then do a 64-bit FIST. Has to probe the
4648 // target address before the store (for null-ptr checks)
4649 // so the memory operand is used twice in the encoding.
4650 enc_class enc_storeL_volatile( memory mem, stackSlotL src ) %{
4651 store_to_stackslot( cbuf, 0x0DF, 0x05, $src$$disp );
4652 cbuf.set_inst_mark(); // Mark start of FIST in case $mem has an oop
4653 emit_opcode(cbuf,0xDF);
4654 int rm_byte_opcode = 0x07;
4655 int base = $mem$$base;
4656 int index = $mem$$index;
4657 int scale = $mem$$scale;
4658 int displace = $mem$$disp;
4659 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
4660 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_is_oop);
4661 %}
4662
4663 enc_class enc_storeLX_volatile( memory mem, stackSlotL src, regXD tmp) %{
4664 { // Atomic long load
4665 // UseXmmLoadAndClearUpper ? movsd $tmp,[$src] : movlpd $tmp,[$src]
4666 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0xF2 : 0x66);
4667 emit_opcode(cbuf,0x0F);
4668 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0x10 : 0x12);
4669 int base = $src$$base;
4670 int index = $src$$index;
4671 int scale = $src$$scale;
4672 int displace = $src$$disp;
4673 bool disp_is_oop = $src->disp_is_oop(); // disp-as-oop when working with static globals
4674 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop);
4675 }
4676 cbuf.set_inst_mark(); // Mark start of MOVSD in case $mem has an oop
4677 { // MOVSD $mem,$tmp ! atomic long store
4678 emit_opcode(cbuf,0xF2);
4679 emit_opcode(cbuf,0x0F);
4680 emit_opcode(cbuf,0x11);
4681 int base = $mem$$base;
4682 int index = $mem$$index;
4683 int scale = $mem$$scale;
4684 int displace = $mem$$disp;
4685 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
4686 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop);
4687 }
4688 %}
4689
4690 enc_class enc_storeLX_reg_volatile( memory mem, eRegL src, regXD tmp, regXD tmp2) %{
4691 { // MOVD $tmp,$src.lo
4692 emit_opcode(cbuf,0x66);
4693 emit_opcode(cbuf,0x0F);
4694 emit_opcode(cbuf,0x6E);
4695 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg);
4696 }
4697 { // MOVD $tmp2,$src.hi
4698 emit_opcode(cbuf,0x66);
4699 emit_opcode(cbuf,0x0F);
4700 emit_opcode(cbuf,0x6E);
4701 emit_rm(cbuf, 0x3, $tmp2$$reg, HIGH_FROM_LOW($src$$reg));
4702 }
4703 { // PUNPCKLDQ $tmp,$tmp2
4704 emit_opcode(cbuf,0x66);
4705 emit_opcode(cbuf,0x0F);
4706 emit_opcode(cbuf,0x62);
4707 emit_rm(cbuf, 0x3, $tmp$$reg, $tmp2$$reg);
4708 }
4709 cbuf.set_inst_mark(); // Mark start of MOVSD in case $mem has an oop
4710 { // MOVSD $mem,$tmp ! atomic long store
4711 emit_opcode(cbuf,0xF2);
4712 emit_opcode(cbuf,0x0F);
4713 emit_opcode(cbuf,0x11);
4714 int base = $mem$$base;
4715 int index = $mem$$index;
4716 int scale = $mem$$scale;
4717 int displace = $mem$$disp;
4718 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
4719 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop);
4720 }
4721 %}
4722
4723 // Safepoint Poll. This polls the safepoint page, and causes an
4724 // exception if it is not readable. Unfortunately, it kills the condition code
4725 // in the process
4726 // We current use TESTL [spp],EDI
4727 // A better choice might be TESTB [spp + pagesize() - CacheLineSize()],0
4728
4729 enc_class Safepoint_Poll() %{
4730 cbuf.relocate(cbuf.inst_mark(), relocInfo::poll_type, 0);
4731 emit_opcode(cbuf,0x85);
4732 emit_rm (cbuf, 0x0, 0x7, 0x5);
4733 emit_d32(cbuf, (intptr_t)os::get_polling_page());
4734 %}
4735 %}
4736
4737
4738 //----------FRAME--------------------------------------------------------------
4739 // Definition of frame structure and management information.
4740 //
4741 // S T A C K L A Y O U T Allocators stack-slot number
4742 // | (to get allocators register number
4743 // G Owned by | | v add OptoReg::stack0())
4744 // r CALLER | |
4745 // o | +--------+ pad to even-align allocators stack-slot
4746 // w V | pad0 | numbers; owned by CALLER
4747 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
4748 // h ^ | in | 5
4749 // | | args | 4 Holes in incoming args owned by SELF
4750 // | | | | 3
4751 // | | +--------+
4752 // V | | old out| Empty on Intel, window on Sparc
4753 // | old |preserve| Must be even aligned.
4754 // | SP-+--------+----> Matcher::_old_SP, even aligned
4755 // | | in | 3 area for Intel ret address
4756 // Owned by |preserve| Empty on Sparc.
4757 // SELF +--------+
4758 // | | pad2 | 2 pad to align old SP
4759 // | +--------+ 1
4760 // | | locks | 0
4761 // | +--------+----> OptoReg::stack0(), even aligned
4762 // | | pad1 | 11 pad to align new SP
4763 // | +--------+
4764 // | | | 10
4765 // | | spills | 9 spills
4766 // V | | 8 (pad0 slot for callee)
4767 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
4768 // ^ | out | 7
4769 // | | args | 6 Holes in outgoing args owned by CALLEE
4770 // Owned by +--------+
4771 // CALLEE | new out| 6 Empty on Intel, window on Sparc
4772 // | new |preserve| Must be even-aligned.
4773 // | SP-+--------+----> Matcher::_new_SP, even aligned
4774 // | | |
4775 //
4776 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
4777 // known from SELF's arguments and the Java calling convention.
4778 // Region 6-7 is determined per call site.
4779 // Note 2: If the calling convention leaves holes in the incoming argument
4780 // area, those holes are owned by SELF. Holes in the outgoing area
4781 // are owned by the CALLEE. Holes should not be nessecary in the
4782 // incoming area, as the Java calling convention is completely under
4783 // the control of the AD file. Doubles can be sorted and packed to
4784 // avoid holes. Holes in the outgoing arguments may be nessecary for
4785 // varargs C calling conventions.
4786 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
4787 // even aligned with pad0 as needed.
4788 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
4789 // region 6-11 is even aligned; it may be padded out more so that
4790 // the region from SP to FP meets the minimum stack alignment.
4791
4792 frame %{
4793 // What direction does stack grow in (assumed to be same for C & Java)
4794 stack_direction(TOWARDS_LOW);
4795
4796 // These three registers define part of the calling convention
4797 // between compiled code and the interpreter.
4798 inline_cache_reg(EAX); // Inline Cache Register
4799 interpreter_method_oop_reg(EBX); // Method Oop Register when calling interpreter
4800
4801 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
4802 cisc_spilling_operand_name(indOffset32);
4803
4804 // Number of stack slots consumed by locking an object
4805 sync_stack_slots(1);
4806
4807 // Compiled code's Frame Pointer
4808 frame_pointer(ESP);
4809 // Interpreter stores its frame pointer in a register which is
4810 // stored to the stack by I2CAdaptors.
4811 // I2CAdaptors convert from interpreted java to compiled java.
4812 interpreter_frame_pointer(EBP);
4813
4814 // Stack alignment requirement
4815 // Alignment size in bytes (128-bit -> 16 bytes)
4816 stack_alignment(StackAlignmentInBytes);
4817
4818 // Number of stack slots between incoming argument block and the start of
4819 // a new frame. The PROLOG must add this many slots to the stack. The
4820 // EPILOG must remove this many slots. Intel needs one slot for
4821 // return address and one for rbp, (must save rbp)
4822 in_preserve_stack_slots(2+VerifyStackAtCalls);
4823
4824 // Number of outgoing stack slots killed above the out_preserve_stack_slots
4825 // for calls to C. Supports the var-args backing area for register parms.
4826 varargs_C_out_slots_killed(0);
4827
4828 // The after-PROLOG location of the return address. Location of
4829 // return address specifies a type (REG or STACK) and a number
4830 // representing the register number (i.e. - use a register name) or
4831 // stack slot.
4832 // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
4833 // Otherwise, it is above the locks and verification slot and alignment word
4834 return_addr(STACK - 1 +
4835 round_to(1+VerifyStackAtCalls+
4836 Compile::current()->fixed_slots(),
4837 (StackAlignmentInBytes/wordSize)));
4838
4839 // Body of function which returns an integer array locating
4840 // arguments either in registers or in stack slots. Passed an array
4841 // of ideal registers called "sig" and a "length" count. Stack-slot
4842 // offsets are based on outgoing arguments, i.e. a CALLER setting up
4843 // arguments for a CALLEE. Incoming stack arguments are
4844 // automatically biased by the preserve_stack_slots field above.
4845 calling_convention %{
4846 // No difference between ingoing/outgoing just pass false
4847 SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
4848 %}
4849
4850
4851 // Body of function which returns an integer array locating
4852 // arguments either in registers or in stack slots. Passed an array
4853 // of ideal registers called "sig" and a "length" count. Stack-slot
4854 // offsets are based on outgoing arguments, i.e. a CALLER setting up
4855 // arguments for a CALLEE. Incoming stack arguments are
4856 // automatically biased by the preserve_stack_slots field above.
4857 c_calling_convention %{
4858 // This is obviously always outgoing
4859 (void) SharedRuntime::c_calling_convention(sig_bt, regs, length);
4860 %}
4861
4862 // Location of C & interpreter return values
4863 c_return_value %{
4864 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
4865 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num };
4866 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num };
4867
4868 // in SSE2+ mode we want to keep the FPU stack clean so pretend
4869 // that C functions return float and double results in XMM0.
4870 if( ideal_reg == Op_RegD && UseSSE>=2 )
4871 return OptoRegPair(XMM0b_num,XMM0a_num);
4872 if( ideal_reg == Op_RegF && UseSSE>=2 )
4873 return OptoRegPair(OptoReg::Bad,XMM0a_num);
4874
4875 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]);
4876 %}
4877
4878 // Location of return values
4879 return_value %{
4880 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
4881 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num };
4882 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num };
4883 if( ideal_reg == Op_RegD && UseSSE>=2 )
4884 return OptoRegPair(XMM0b_num,XMM0a_num);
4885 if( ideal_reg == Op_RegF && UseSSE>=1 )
4886 return OptoRegPair(OptoReg::Bad,XMM0a_num);
4887 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]);
4888 %}
4889
4890 %}
4891
4892 //----------ATTRIBUTES---------------------------------------------------------
4893 //----------Operand Attributes-------------------------------------------------
4894 op_attrib op_cost(0); // Required cost attribute
4895
4896 //----------Instruction Attributes---------------------------------------------
4897 ins_attrib ins_cost(100); // Required cost attribute
4898 ins_attrib ins_size(8); // Required size attribute (in bits)
4899 ins_attrib ins_pc_relative(0); // Required PC Relative flag
4900 ins_attrib ins_short_branch(0); // Required flag: is this instruction a
4901 // non-matching short branch variant of some
4902 // long branch?
4903 ins_attrib ins_alignment(1); // Required alignment attribute (must be a power of 2)
4904 // specifies the alignment that some part of the instruction (not
4905 // necessarily the start) requires. If > 1, a compute_padding()
4906 // function must be provided for the instruction
4907
4908 //----------OPERANDS-----------------------------------------------------------
4909 // Operand definitions must precede instruction definitions for correct parsing
4910 // in the ADLC because operands constitute user defined types which are used in
4911 // instruction definitions.
4912
4913 //----------Simple Operands----------------------------------------------------
4914 // Immediate Operands
4915 // Integer Immediate
4916 operand immI() %{
4917 match(ConI);
4918
4919 op_cost(10);
4920 format %{ %}
4921 interface(CONST_INTER);
4922 %}
4923
4924 // Constant for test vs zero
4925 operand immI0() %{
4926 predicate(n->get_int() == 0);
4927 match(ConI);
4928
4929 op_cost(0);
4930 format %{ %}
4931 interface(CONST_INTER);
4932 %}
4933
4934 // Constant for increment
4935 operand immI1() %{
4936 predicate(n->get_int() == 1);
4937 match(ConI);
4938
4939 op_cost(0);
4940 format %{ %}
4941 interface(CONST_INTER);
4942 %}
4943
4944 // Constant for decrement
4945 operand immI_M1() %{
4946 predicate(n->get_int() == -1);
4947 match(ConI);
4948
4949 op_cost(0);
4950 format %{ %}
4951 interface(CONST_INTER);
4952 %}
4953
4954 // Valid scale values for addressing modes
4955 operand immI2() %{
4956 predicate(0 <= n->get_int() && (n->get_int() <= 3));
4957 match(ConI);
4958
4959 format %{ %}
4960 interface(CONST_INTER);
4961 %}
4962
4963 operand immI8() %{
4964 predicate((-128 <= n->get_int()) && (n->get_int() <= 127));
4965 match(ConI);
4966
4967 op_cost(5);
4968 format %{ %}
4969 interface(CONST_INTER);
4970 %}
4971
4972 operand immI16() %{
4973 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767));
4974 match(ConI);
4975
4976 op_cost(10);
4977 format %{ %}
4978 interface(CONST_INTER);
4979 %}
4980
4981 // Constant for long shifts
4982 operand immI_32() %{
4983 predicate( n->get_int() == 32 );
4984 match(ConI);
4985
4986 op_cost(0);
4987 format %{ %}
4988 interface(CONST_INTER);
4989 %}
4990
4991 operand immI_1_31() %{
4992 predicate( n->get_int() >= 1 && n->get_int() <= 31 );
4993 match(ConI);
4994
4995 op_cost(0);
4996 format %{ %}
4997 interface(CONST_INTER);
4998 %}
4999
5000 operand immI_32_63() %{
5001 predicate( n->get_int() >= 32 && n->get_int() <= 63 );
5002 match(ConI);
5003 op_cost(0);
5004
5005 format %{ %}
5006 interface(CONST_INTER);
5007 %}
5008
5009 operand immI_1() %{
5010 predicate( n->get_int() == 1 );
5011 match(ConI);
5012
5013 op_cost(0);
5014 format %{ %}
5015 interface(CONST_INTER);
5016 %}
5017
5018 operand immI_2() %{
5019 predicate( n->get_int() == 2 );
5020 match(ConI);
5021
5022 op_cost(0);
5023 format %{ %}
5024 interface(CONST_INTER);
5025 %}
5026
5027 operand immI_3() %{
5028 predicate( n->get_int() == 3 );
5029 match(ConI);
5030
5031 op_cost(0);
5032 format %{ %}
5033 interface(CONST_INTER);
5034 %}
5035
5036 // Pointer Immediate
5037 operand immP() %{
5038 match(ConP);
5039
5040 op_cost(10);
5041 format %{ %}
5042 interface(CONST_INTER);
5043 %}
5044
5045 // NULL Pointer Immediate
5046 operand immP0() %{
5047 predicate( n->get_ptr() == 0 );
5048 match(ConP);
5049 op_cost(0);
5050
5051 format %{ %}
5052 interface(CONST_INTER);
5053 %}
5054
5055 // Long Immediate
5056 operand immL() %{
5057 match(ConL);
5058
5059 op_cost(20);
5060 format %{ %}
5061 interface(CONST_INTER);
5062 %}
5063
5064 // Long Immediate zero
5065 operand immL0() %{
5066 predicate( n->get_long() == 0L );
5067 match(ConL);
5068 op_cost(0);
5069
5070 format %{ %}
5071 interface(CONST_INTER);
5072 %}
5073
5074 // Long Immediate zero
5075 operand immL_M1() %{
5076 predicate( n->get_long() == -1L );
5077 match(ConL);
5078 op_cost(0);
5079
5080 format %{ %}
5081 interface(CONST_INTER);
5082 %}
5083
5084 // Long immediate from 0 to 127.
5085 // Used for a shorter form of long mul by 10.
5086 operand immL_127() %{
5087 predicate((0 <= n->get_long()) && (n->get_long() <= 127));
5088 match(ConL);
5089 op_cost(0);
5090
5091 format %{ %}
5092 interface(CONST_INTER);
5093 %}
5094
5095 // Long Immediate: low 32-bit mask
5096 operand immL_32bits() %{
5097 predicate(n->get_long() == 0xFFFFFFFFL);
5098 match(ConL);
5099 op_cost(0);
5100
5101 format %{ %}
5102 interface(CONST_INTER);
5103 %}
5104
5105 // Long Immediate: low 32-bit mask
5106 operand immL32() %{
5107 predicate(n->get_long() == (int)(n->get_long()));
5108 match(ConL);
5109 op_cost(20);
5110
5111 format %{ %}
5112 interface(CONST_INTER);
5113 %}
5114
5115 //Double Immediate zero
5116 operand immD0() %{
5117 // Do additional (and counter-intuitive) test against NaN to work around VC++
5118 // bug that generates code such that NaNs compare equal to 0.0
5119 predicate( UseSSE<=1 && n->getd() == 0.0 && !g_isnan(n->getd()) );
5120 match(ConD);
5121
5122 op_cost(5);
5123 format %{ %}
5124 interface(CONST_INTER);
5125 %}
5126
5127 // Double Immediate
5128 operand immD1() %{
5129 predicate( UseSSE<=1 && n->getd() == 1.0 );
5130 match(ConD);
5131
5132 op_cost(5);
5133 format %{ %}
5134 interface(CONST_INTER);
5135 %}
5136
5137 // Double Immediate
5138 operand immD() %{
5139 predicate(UseSSE<=1);
5140 match(ConD);
5141
5142 op_cost(5);
5143 format %{ %}
5144 interface(CONST_INTER);
5145 %}
5146
5147 operand immXD() %{
5148 predicate(UseSSE>=2);
5149 match(ConD);
5150
5151 op_cost(5);
5152 format %{ %}
5153 interface(CONST_INTER);
5154 %}
5155
5156 // Double Immediate zero
5157 operand immXD0() %{
5158 // Do additional (and counter-intuitive) test against NaN to work around VC++
5159 // bug that generates code such that NaNs compare equal to 0.0 AND do not
5160 // compare equal to -0.0.
5161 predicate( UseSSE>=2 && jlong_cast(n->getd()) == 0 );
5162 match(ConD);
5163
5164 format %{ %}
5165 interface(CONST_INTER);
5166 %}
5167
5168 // Float Immediate zero
5169 operand immF0() %{
5170 predicate( UseSSE == 0 && n->getf() == 0.0 );
5171 match(ConF);
5172
5173 op_cost(5);
5174 format %{ %}
5175 interface(CONST_INTER);
5176 %}
5177
5178 // Float Immediate
5179 operand immF() %{
5180 predicate( UseSSE == 0 );
5181 match(ConF);
5182
5183 op_cost(5);
5184 format %{ %}
5185 interface(CONST_INTER);
5186 %}
5187
5188 // Float Immediate
5189 operand immXF() %{
5190 predicate(UseSSE >= 1);
5191 match(ConF);
5192
5193 op_cost(5);
5194 format %{ %}
5195 interface(CONST_INTER);
5196 %}
5197
5198 // Float Immediate zero. Zero and not -0.0
5199 operand immXF0() %{
5200 predicate( UseSSE >= 1 && jint_cast(n->getf()) == 0 );
5201 match(ConF);
5202
5203 op_cost(5);
5204 format %{ %}
5205 interface(CONST_INTER);
5206 %}
5207
5208 // Immediates for special shifts (sign extend)
5209
5210 // Constants for increment
5211 operand immI_16() %{
5212 predicate( n->get_int() == 16 );
5213 match(ConI);
5214
5215 format %{ %}
5216 interface(CONST_INTER);
5217 %}
5218
5219 operand immI_24() %{
5220 predicate( n->get_int() == 24 );
5221 match(ConI);
5222
5223 format %{ %}
5224 interface(CONST_INTER);
5225 %}
5226
5227 // Constant for byte-wide masking
5228 operand immI_255() %{
5229 predicate( n->get_int() == 255 );
5230 match(ConI);
5231
5232 format %{ %}
5233 interface(CONST_INTER);
5234 %}
5235
5236 // Register Operands
5237 // Integer Register
5238 operand eRegI() %{
5239 constraint(ALLOC_IN_RC(e_reg));
5240 match(RegI);
5241 match(xRegI);
5242 match(eAXRegI);
5243 match(eBXRegI);
5244 match(eCXRegI);
5245 match(eDXRegI);
5246 match(eDIRegI);
5247 match(eSIRegI);
5248
5249 format %{ %}
5250 interface(REG_INTER);
5251 %}
5252
5253 // Subset of Integer Register
5254 operand xRegI(eRegI reg) %{
5255 constraint(ALLOC_IN_RC(x_reg));
5256 match(reg);
5257 match(eAXRegI);
5258 match(eBXRegI);
5259 match(eCXRegI);
5260 match(eDXRegI);
5261
5262 format %{ %}
5263 interface(REG_INTER);
5264 %}
5265
5266 // Special Registers
5267 operand eAXRegI(xRegI reg) %{
5268 constraint(ALLOC_IN_RC(eax_reg));
5269 match(reg);
5270 match(eRegI);
5271
5272 format %{ "EAX" %}
5273 interface(REG_INTER);
5274 %}
5275
5276 // Special Registers
5277 operand eBXRegI(xRegI reg) %{
5278 constraint(ALLOC_IN_RC(ebx_reg));
5279 match(reg);
5280 match(eRegI);
5281
5282 format %{ "EBX" %}
5283 interface(REG_INTER);
5284 %}
5285
5286 operand eCXRegI(xRegI reg) %{
5287 constraint(ALLOC_IN_RC(ecx_reg));
5288 match(reg);
5289 match(eRegI);
5290
5291 format %{ "ECX" %}
5292 interface(REG_INTER);
5293 %}
5294
5295 operand eDXRegI(xRegI reg) %{
5296 constraint(ALLOC_IN_RC(edx_reg));
5297 match(reg);
5298 match(eRegI);
5299
5300 format %{ "EDX" %}
5301 interface(REG_INTER);
5302 %}
5303
5304 operand eDIRegI(xRegI reg) %{
5305 constraint(ALLOC_IN_RC(edi_reg));
5306 match(reg);
5307 match(eRegI);
5308
5309 format %{ "EDI" %}
5310 interface(REG_INTER);
5311 %}
5312
5313 operand naxRegI() %{
5314 constraint(ALLOC_IN_RC(nax_reg));
5315 match(RegI);
5316 match(eCXRegI);
5317 match(eDXRegI);
5318 match(eSIRegI);
5319 match(eDIRegI);
5320
5321 format %{ %}
5322 interface(REG_INTER);
5323 %}
5324
5325 operand nadxRegI() %{
5326 constraint(ALLOC_IN_RC(nadx_reg));
5327 match(RegI);
5328 match(eBXRegI);
5329 match(eCXRegI);
5330 match(eSIRegI);
5331 match(eDIRegI);
5332
5333 format %{ %}
5334 interface(REG_INTER);
5335 %}
5336
5337 operand ncxRegI() %{
5338 constraint(ALLOC_IN_RC(ncx_reg));
5339 match(RegI);
5340 match(eAXRegI);
5341 match(eDXRegI);
5342 match(eSIRegI);
5343 match(eDIRegI);
5344
5345 format %{ %}
5346 interface(REG_INTER);
5347 %}
5348
5349 // // This operand was used by cmpFastUnlock, but conflicted with 'object' reg
5350 // //
5351 operand eSIRegI(xRegI reg) %{
5352 constraint(ALLOC_IN_RC(esi_reg));
5353 match(reg);
5354 match(eRegI);
5355
5356 format %{ "ESI" %}
5357 interface(REG_INTER);
5358 %}
5359
5360 // Pointer Register
5361 operand anyRegP() %{
5362 constraint(ALLOC_IN_RC(any_reg));
5363 match(RegP);
5364 match(eAXRegP);
5365 match(eBXRegP);
5366 match(eCXRegP);
5367 match(eDIRegP);
5368 match(eRegP);
5369
5370 format %{ %}
5371 interface(REG_INTER);
5372 %}
5373
5374 operand eRegP() %{
5375 constraint(ALLOC_IN_RC(e_reg));
5376 match(RegP);
5377 match(eAXRegP);
5378 match(eBXRegP);
5379 match(eCXRegP);
5380 match(eDIRegP);
5381
5382 format %{ %}
5383 interface(REG_INTER);
5384 %}
5385
5386 // On windows95, EBP is not safe to use for implicit null tests.
5387 operand eRegP_no_EBP() %{
5388 constraint(ALLOC_IN_RC(e_reg_no_rbp));
5389 match(RegP);
5390 match(eAXRegP);
5391 match(eBXRegP);
5392 match(eCXRegP);
5393 match(eDIRegP);
5394
5395 op_cost(100);
5396 format %{ %}
5397 interface(REG_INTER);
5398 %}
5399
5400 operand naxRegP() %{
5401 constraint(ALLOC_IN_RC(nax_reg));
5402 match(RegP);
5403 match(eBXRegP);
5404 match(eDXRegP);
5405 match(eCXRegP);
5406 match(eSIRegP);
5407 match(eDIRegP);
5408
5409 format %{ %}
5410 interface(REG_INTER);
5411 %}
5412
5413 operand nabxRegP() %{
5414 constraint(ALLOC_IN_RC(nabx_reg));
5415 match(RegP);
5416 match(eCXRegP);
5417 match(eDXRegP);
5418 match(eSIRegP);
5419 match(eDIRegP);
5420
5421 format %{ %}
5422 interface(REG_INTER);
5423 %}
5424
5425 operand pRegP() %{
5426 constraint(ALLOC_IN_RC(p_reg));
5427 match(RegP);
5428 match(eBXRegP);
5429 match(eDXRegP);
5430 match(eSIRegP);
5431 match(eDIRegP);
5432
5433 format %{ %}
5434 interface(REG_INTER);
5435 %}
5436
5437 // Special Registers
5438 // Return a pointer value
5439 operand eAXRegP(eRegP reg) %{
5440 constraint(ALLOC_IN_RC(eax_reg));
5441 match(reg);
5442 format %{ "EAX" %}
5443 interface(REG_INTER);
5444 %}
5445
5446 // Used in AtomicAdd
5447 operand eBXRegP(eRegP reg) %{
5448 constraint(ALLOC_IN_RC(ebx_reg));
5449 match(reg);
5450 format %{ "EBX" %}
5451 interface(REG_INTER);
5452 %}
5453
5454 // Tail-call (interprocedural jump) to interpreter
5455 operand eCXRegP(eRegP reg) %{
5456 constraint(ALLOC_IN_RC(ecx_reg));
5457 match(reg);
5458 format %{ "ECX" %}
5459 interface(REG_INTER);
5460 %}
5461
5462 operand eSIRegP(eRegP reg) %{
5463 constraint(ALLOC_IN_RC(esi_reg));
5464 match(reg);
5465 format %{ "ESI" %}
5466 interface(REG_INTER);
5467 %}
5468
5469 // Used in rep stosw
5470 operand eDIRegP(eRegP reg) %{
5471 constraint(ALLOC_IN_RC(edi_reg));
5472 match(reg);
5473 format %{ "EDI" %}
5474 interface(REG_INTER);
5475 %}
5476
5477 operand eBPRegP() %{
5478 constraint(ALLOC_IN_RC(ebp_reg));
5479 match(RegP);
5480 format %{ "EBP" %}
5481 interface(REG_INTER);
5482 %}
5483
5484 operand eRegL() %{
5485 constraint(ALLOC_IN_RC(long_reg));
5486 match(RegL);
5487 match(eADXRegL);
5488
5489 format %{ %}
5490 interface(REG_INTER);
5491 %}
5492
5493 operand eADXRegL( eRegL reg ) %{
5494 constraint(ALLOC_IN_RC(eadx_reg));
5495 match(reg);
5496
5497 format %{ "EDX:EAX" %}
5498 interface(REG_INTER);
5499 %}
5500
5501 operand eBCXRegL( eRegL reg ) %{
5502 constraint(ALLOC_IN_RC(ebcx_reg));
5503 match(reg);
5504
5505 format %{ "EBX:ECX" %}
5506 interface(REG_INTER);
5507 %}
5508
5509 // Special case for integer high multiply
5510 operand eADXRegL_low_only() %{
5511 constraint(ALLOC_IN_RC(eadx_reg));
5512 match(RegL);
5513
5514 format %{ "EAX" %}
5515 interface(REG_INTER);
5516 %}
5517
5518 // Flags register, used as output of compare instructions
5519 operand eFlagsReg() %{
5520 constraint(ALLOC_IN_RC(int_flags));
5521 match(RegFlags);
5522
5523 format %{ "EFLAGS" %}
5524 interface(REG_INTER);
5525 %}
5526
5527 // Flags register, used as output of FLOATING POINT compare instructions
5528 operand eFlagsRegU() %{
5529 constraint(ALLOC_IN_RC(int_flags));
5530 match(RegFlags);
5531
5532 format %{ "EFLAGS_U" %}
5533 interface(REG_INTER);
5534 %}
5535
5536 operand eFlagsRegUCF() %{
5537 constraint(ALLOC_IN_RC(int_flags));
5538 match(RegFlags);
5539 predicate(false);
5540
5541 format %{ "EFLAGS_U_CF" %}
5542 interface(REG_INTER);
5543 %}
5544
5545 // Condition Code Register used by long compare
5546 operand flagsReg_long_LTGE() %{
5547 constraint(ALLOC_IN_RC(int_flags));
5548 match(RegFlags);
5549 format %{ "FLAGS_LTGE" %}
5550 interface(REG_INTER);
5551 %}
5552 operand flagsReg_long_EQNE() %{
5553 constraint(ALLOC_IN_RC(int_flags));
5554 match(RegFlags);
5555 format %{ "FLAGS_EQNE" %}
5556 interface(REG_INTER);
5557 %}
5558 operand flagsReg_long_LEGT() %{
5559 constraint(ALLOC_IN_RC(int_flags));
5560 match(RegFlags);
5561 format %{ "FLAGS_LEGT" %}
5562 interface(REG_INTER);
5563 %}
5564
5565 // Float register operands
5566 operand regD() %{
5567 predicate( UseSSE < 2 );
5568 constraint(ALLOC_IN_RC(dbl_reg));
5569 match(RegD);
5570 match(regDPR1);
5571 match(regDPR2);
5572 format %{ %}
5573 interface(REG_INTER);
5574 %}
5575
5576 operand regDPR1(regD reg) %{
5577 predicate( UseSSE < 2 );
5578 constraint(ALLOC_IN_RC(dbl_reg0));
5579 match(reg);
5580 format %{ "FPR1" %}
5581 interface(REG_INTER);
5582 %}
5583
5584 operand regDPR2(regD reg) %{
5585 predicate( UseSSE < 2 );
5586 constraint(ALLOC_IN_RC(dbl_reg1));
5587 match(reg);
5588 format %{ "FPR2" %}
5589 interface(REG_INTER);
5590 %}
5591
5592 operand regnotDPR1(regD reg) %{
5593 predicate( UseSSE < 2 );
5594 constraint(ALLOC_IN_RC(dbl_notreg0));
5595 match(reg);
5596 format %{ %}
5597 interface(REG_INTER);
5598 %}
5599
5600 // XMM Double register operands
5601 operand regXD() %{
5602 predicate( UseSSE>=2 );
5603 constraint(ALLOC_IN_RC(xdb_reg));
5604 match(RegD);
5605 match(regXD6);
5606 match(regXD7);
5607 format %{ %}
5608 interface(REG_INTER);
5609 %}
5610
5611 // XMM6 double register operands
5612 operand regXD6(regXD reg) %{
5613 predicate( UseSSE>=2 );
5614 constraint(ALLOC_IN_RC(xdb_reg6));
5615 match(reg);
5616 format %{ "XMM6" %}
5617 interface(REG_INTER);
5618 %}
5619
5620 // XMM7 double register operands
5621 operand regXD7(regXD reg) %{
5622 predicate( UseSSE>=2 );
5623 constraint(ALLOC_IN_RC(xdb_reg7));
5624 match(reg);
5625 format %{ "XMM7" %}
5626 interface(REG_INTER);
5627 %}
5628
5629 // Float register operands
5630 operand regF() %{
5631 predicate( UseSSE < 2 );
5632 constraint(ALLOC_IN_RC(flt_reg));
5633 match(RegF);
5634 match(regFPR1);
5635 format %{ %}
5636 interface(REG_INTER);
5637 %}
5638
5639 // Float register operands
5640 operand regFPR1(regF reg) %{
5641 predicate( UseSSE < 2 );
5642 constraint(ALLOC_IN_RC(flt_reg0));
5643 match(reg);
5644 format %{ "FPR1" %}
5645 interface(REG_INTER);
5646 %}
5647
5648 // XMM register operands
5649 operand regX() %{
5650 predicate( UseSSE>=1 );
5651 constraint(ALLOC_IN_RC(xmm_reg));
5652 match(RegF);
5653 format %{ %}
5654 interface(REG_INTER);
5655 %}
5656
5657
5658 //----------Memory Operands----------------------------------------------------
5659 // Direct Memory Operand
5660 operand direct(immP addr) %{
5661 match(addr);
5662
5663 format %{ "[$addr]" %}
5664 interface(MEMORY_INTER) %{
5665 base(0xFFFFFFFF);
5666 index(0x4);
5667 scale(0x0);
5668 disp($addr);
5669 %}
5670 %}
5671
5672 // Indirect Memory Operand
5673 operand indirect(eRegP reg) %{
5674 constraint(ALLOC_IN_RC(e_reg));
5675 match(reg);
5676
5677 format %{ "[$reg]" %}
5678 interface(MEMORY_INTER) %{
5679 base($reg);
5680 index(0x4);
5681 scale(0x0);
5682 disp(0x0);
5683 %}
5684 %}
5685
5686 // Indirect Memory Plus Short Offset Operand
5687 operand indOffset8(eRegP reg, immI8 off) %{
5688 match(AddP reg off);
5689
5690 format %{ "[$reg + $off]" %}
5691 interface(MEMORY_INTER) %{
5692 base($reg);
5693 index(0x4);
5694 scale(0x0);
5695 disp($off);
5696 %}
5697 %}
5698
5699 // Indirect Memory Plus Long Offset Operand
5700 operand indOffset32(eRegP reg, immI off) %{
5701 match(AddP reg off);
5702
5703 format %{ "[$reg + $off]" %}
5704 interface(MEMORY_INTER) %{
5705 base($reg);
5706 index(0x4);
5707 scale(0x0);
5708 disp($off);
5709 %}
5710 %}
5711
5712 // Indirect Memory Plus Long Offset Operand
5713 operand indOffset32X(eRegI reg, immP off) %{
5714 match(AddP off reg);
5715
5716 format %{ "[$reg + $off]" %}
5717 interface(MEMORY_INTER) %{
5718 base($reg);
5719 index(0x4);
5720 scale(0x0);
5721 disp($off);
5722 %}
5723 %}
5724
5725 // Indirect Memory Plus Index Register Plus Offset Operand
5726 operand indIndexOffset(eRegP reg, eRegI ireg, immI off) %{
5727 match(AddP (AddP reg ireg) off);
5728
5729 op_cost(10);
5730 format %{"[$reg + $off + $ireg]" %}
5731 interface(MEMORY_INTER) %{
5732 base($reg);
5733 index($ireg);
5734 scale(0x0);
5735 disp($off);
5736 %}
5737 %}
5738
5739 // Indirect Memory Plus Index Register Plus Offset Operand
5740 operand indIndex(eRegP reg, eRegI ireg) %{
5741 match(AddP reg ireg);
5742
5743 op_cost(10);
5744 format %{"[$reg + $ireg]" %}
5745 interface(MEMORY_INTER) %{
5746 base($reg);
5747 index($ireg);
5748 scale(0x0);
5749 disp(0x0);
5750 %}
5751 %}
5752
5753 // // -------------------------------------------------------------------------
5754 // // 486 architecture doesn't support "scale * index + offset" with out a base
5755 // // -------------------------------------------------------------------------
5756 // // Scaled Memory Operands
5757 // // Indirect Memory Times Scale Plus Offset Operand
5758 // operand indScaleOffset(immP off, eRegI ireg, immI2 scale) %{
5759 // match(AddP off (LShiftI ireg scale));
5760 //
5761 // op_cost(10);
5762 // format %{"[$off + $ireg << $scale]" %}
5763 // interface(MEMORY_INTER) %{
5764 // base(0x4);
5765 // index($ireg);
5766 // scale($scale);
5767 // disp($off);
5768 // %}
5769 // %}
5770
5771 // Indirect Memory Times Scale Plus Index Register
5772 operand indIndexScale(eRegP reg, eRegI ireg, immI2 scale) %{
5773 match(AddP reg (LShiftI ireg scale));
5774
5775 op_cost(10);
5776 format %{"[$reg + $ireg << $scale]" %}
5777 interface(MEMORY_INTER) %{
5778 base($reg);
5779 index($ireg);
5780 scale($scale);
5781 disp(0x0);
5782 %}
5783 %}
5784
5785 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
5786 operand indIndexScaleOffset(eRegP reg, immI off, eRegI ireg, immI2 scale) %{
5787 match(AddP (AddP reg (LShiftI ireg scale)) off);
5788
5789 op_cost(10);
5790 format %{"[$reg + $off + $ireg << $scale]" %}
5791 interface(MEMORY_INTER) %{
5792 base($reg);
5793 index($ireg);
5794 scale($scale);
5795 disp($off);
5796 %}
5797 %}
5798
5799 //----------Load Long Memory Operands------------------------------------------
5800 // The load-long idiom will use it's address expression again after loading
5801 // the first word of the long. If the load-long destination overlaps with
5802 // registers used in the addressing expression, the 2nd half will be loaded
5803 // from a clobbered address. Fix this by requiring that load-long use
5804 // address registers that do not overlap with the load-long target.
5805
5806 // load-long support
5807 operand load_long_RegP() %{
5808 constraint(ALLOC_IN_RC(esi_reg));
5809 match(RegP);
5810 match(eSIRegP);
5811 op_cost(100);
5812 format %{ %}
5813 interface(REG_INTER);
5814 %}
5815
5816 // Indirect Memory Operand Long
5817 operand load_long_indirect(load_long_RegP reg) %{
5818 constraint(ALLOC_IN_RC(esi_reg));
5819 match(reg);
5820
5821 format %{ "[$reg]" %}
5822 interface(MEMORY_INTER) %{
5823 base($reg);
5824 index(0x4);
5825 scale(0x0);
5826 disp(0x0);
5827 %}
5828 %}
5829
5830 // Indirect Memory Plus Long Offset Operand
5831 operand load_long_indOffset32(load_long_RegP reg, immI off) %{
5832 match(AddP reg off);
5833
5834 format %{ "[$reg + $off]" %}
5835 interface(MEMORY_INTER) %{
5836 base($reg);
5837 index(0x4);
5838 scale(0x0);
5839 disp($off);
5840 %}
5841 %}
5842
5843 opclass load_long_memory(load_long_indirect, load_long_indOffset32);
5844
5845
5846 //----------Special Memory Operands--------------------------------------------
5847 // Stack Slot Operand - This operand is used for loading and storing temporary
5848 // values on the stack where a match requires a value to
5849 // flow through memory.
5850 operand stackSlotP(sRegP reg) %{
5851 constraint(ALLOC_IN_RC(stack_slots));
5852 // No match rule because this operand is only generated in matching
5853 format %{ "[$reg]" %}
5854 interface(MEMORY_INTER) %{
5855 base(0x4); // ESP
5856 index(0x4); // No Index
5857 scale(0x0); // No Scale
5858 disp($reg); // Stack Offset
5859 %}
5860 %}
5861
5862 operand stackSlotI(sRegI reg) %{
5863 constraint(ALLOC_IN_RC(stack_slots));
5864 // No match rule because this operand is only generated in matching
5865 format %{ "[$reg]" %}
5866 interface(MEMORY_INTER) %{
5867 base(0x4); // ESP
5868 index(0x4); // No Index
5869 scale(0x0); // No Scale
5870 disp($reg); // Stack Offset
5871 %}
5872 %}
5873
5874 operand stackSlotF(sRegF reg) %{
5875 constraint(ALLOC_IN_RC(stack_slots));
5876 // No match rule because this operand is only generated in matching
5877 format %{ "[$reg]" %}
5878 interface(MEMORY_INTER) %{
5879 base(0x4); // ESP
5880 index(0x4); // No Index
5881 scale(0x0); // No Scale
5882 disp($reg); // Stack Offset
5883 %}
5884 %}
5885
5886 operand stackSlotD(sRegD reg) %{
5887 constraint(ALLOC_IN_RC(stack_slots));
5888 // No match rule because this operand is only generated in matching
5889 format %{ "[$reg]" %}
5890 interface(MEMORY_INTER) %{
5891 base(0x4); // ESP
5892 index(0x4); // No Index
5893 scale(0x0); // No Scale
5894 disp($reg); // Stack Offset
5895 %}
5896 %}
5897
5898 operand stackSlotL(sRegL reg) %{
5899 constraint(ALLOC_IN_RC(stack_slots));
5900 // No match rule because this operand is only generated in matching
5901 format %{ "[$reg]" %}
5902 interface(MEMORY_INTER) %{
5903 base(0x4); // ESP
5904 index(0x4); // No Index
5905 scale(0x0); // No Scale
5906 disp($reg); // Stack Offset
5907 %}
5908 %}
5909
5910 //----------Memory Operands - Win95 Implicit Null Variants----------------
5911 // Indirect Memory Operand
5912 operand indirect_win95_safe(eRegP_no_EBP reg)
5913 %{
5914 constraint(ALLOC_IN_RC(e_reg));
5915 match(reg);
5916
5917 op_cost(100);
5918 format %{ "[$reg]" %}
5919 interface(MEMORY_INTER) %{
5920 base($reg);
5921 index(0x4);
5922 scale(0x0);
5923 disp(0x0);
5924 %}
5925 %}
5926
5927 // Indirect Memory Plus Short Offset Operand
5928 operand indOffset8_win95_safe(eRegP_no_EBP reg, immI8 off)
5929 %{
5930 match(AddP reg off);
5931
5932 op_cost(100);
5933 format %{ "[$reg + $off]" %}
5934 interface(MEMORY_INTER) %{
5935 base($reg);
5936 index(0x4);
5937 scale(0x0);
5938 disp($off);
5939 %}
5940 %}
5941
5942 // Indirect Memory Plus Long Offset Operand
5943 operand indOffset32_win95_safe(eRegP_no_EBP reg, immI off)
5944 %{
5945 match(AddP reg off);
5946
5947 op_cost(100);
5948 format %{ "[$reg + $off]" %}
5949 interface(MEMORY_INTER) %{
5950 base($reg);
5951 index(0x4);
5952 scale(0x0);
5953 disp($off);
5954 %}
5955 %}
5956
5957 // Indirect Memory Plus Index Register Plus Offset Operand
5958 operand indIndexOffset_win95_safe(eRegP_no_EBP reg, eRegI ireg, immI off)
5959 %{
5960 match(AddP (AddP reg ireg) off);
5961
5962 op_cost(100);
5963 format %{"[$reg + $off + $ireg]" %}
5964 interface(MEMORY_INTER) %{
5965 base($reg);
5966 index($ireg);
5967 scale(0x0);
5968 disp($off);
5969 %}
5970 %}
5971
5972 // Indirect Memory Times Scale Plus Index Register
5973 operand indIndexScale_win95_safe(eRegP_no_EBP reg, eRegI ireg, immI2 scale)
5974 %{
5975 match(AddP reg (LShiftI ireg scale));
5976
5977 op_cost(100);
5978 format %{"[$reg + $ireg << $scale]" %}
5979 interface(MEMORY_INTER) %{
5980 base($reg);
5981 index($ireg);
5982 scale($scale);
5983 disp(0x0);
5984 %}
5985 %}
5986
5987 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
5988 operand indIndexScaleOffset_win95_safe(eRegP_no_EBP reg, immI off, eRegI ireg, immI2 scale)
5989 %{
5990 match(AddP (AddP reg (LShiftI ireg scale)) off);
5991
5992 op_cost(100);
5993 format %{"[$reg + $off + $ireg << $scale]" %}
5994 interface(MEMORY_INTER) %{
5995 base($reg);
5996 index($ireg);
5997 scale($scale);
5998 disp($off);
5999 %}
6000 %}
6001
6002 //----------Conditional Branch Operands----------------------------------------
6003 // Comparison Op - This is the operation of the comparison, and is limited to
6004 // the following set of codes:
6005 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
6006 //
6007 // Other attributes of the comparison, such as unsignedness, are specified
6008 // by the comparison instruction that sets a condition code flags register.
6009 // That result is represented by a flags operand whose subtype is appropriate
6010 // to the unsignedness (etc.) of the comparison.
6011 //
6012 // Later, the instruction which matches both the Comparison Op (a Bool) and
6013 // the flags (produced by the Cmp) specifies the coding of the comparison op
6014 // by matching a specific subtype of Bool operand below, such as cmpOpU.
6015
6016 // Comparision Code
6017 operand cmpOp() %{
6018 match(Bool);
6019
6020 format %{ "" %}
6021 interface(COND_INTER) %{
6022 equal(0x4, "e");
6023 not_equal(0x5, "ne");
6024 less(0xC, "l");
6025 greater_equal(0xD, "ge");
6026 less_equal(0xE, "le");
6027 greater(0xF, "g");
6028 %}
6029 %}
6030
6031 // Comparison Code, unsigned compare. Used by FP also, with
6032 // C2 (unordered) turned into GT or LT already. The other bits
6033 // C0 and C3 are turned into Carry & Zero flags.
6034 operand cmpOpU() %{
6035 match(Bool);
6036
6037 format %{ "" %}
6038 interface(COND_INTER) %{
6039 equal(0x4, "e");
6040 not_equal(0x5, "ne");
6041 less(0x2, "b");
6042 greater_equal(0x3, "nb");
6043 less_equal(0x6, "be");
6044 greater(0x7, "nbe");
6045 %}
6046 %}
6047
6048 // Floating comparisons that don't require any fixup for the unordered case
6049 operand cmpOpUCF() %{
6050 match(Bool);
6051 predicate(n->as_Bool()->_test._test == BoolTest::lt ||
6052 n->as_Bool()->_test._test == BoolTest::ge ||
6053 n->as_Bool()->_test._test == BoolTest::le ||
6054 n->as_Bool()->_test._test == BoolTest::gt);
6055 format %{ "" %}
6056 interface(COND_INTER) %{
6057 equal(0x4, "e");
6058 not_equal(0x5, "ne");
6059 less(0x2, "b");
6060 greater_equal(0x3, "nb");
6061 less_equal(0x6, "be");
6062 greater(0x7, "nbe");
6063 %}
6064 %}
6065
6066
6067 // Floating comparisons that can be fixed up with extra conditional jumps
6068 operand cmpOpUCF2() %{
6069 match(Bool);
6070 predicate(n->as_Bool()->_test._test == BoolTest::ne ||
6071 n->as_Bool()->_test._test == BoolTest::eq);
6072 format %{ "" %}
6073 interface(COND_INTER) %{
6074 equal(0x4, "e");
6075 not_equal(0x5, "ne");
6076 less(0x2, "b");
6077 greater_equal(0x3, "nb");
6078 less_equal(0x6, "be");
6079 greater(0x7, "nbe");
6080 %}
6081 %}
6082
6083 // Comparison Code for FP conditional move
6084 operand cmpOp_fcmov() %{
6085 match(Bool);
6086
6087 format %{ "" %}
6088 interface(COND_INTER) %{
6089 equal (0x0C8);
6090 not_equal (0x1C8);
6091 less (0x0C0);
6092 greater_equal(0x1C0);
6093 less_equal (0x0D0);
6094 greater (0x1D0);
6095 %}
6096 %}
6097
6098 // Comparision Code used in long compares
6099 operand cmpOp_commute() %{
6100 match(Bool);
6101
6102 format %{ "" %}
6103 interface(COND_INTER) %{
6104 equal(0x4, "e");
6105 not_equal(0x5, "ne");
6106 less(0xF, "g");
6107 greater_equal(0xE, "le");
6108 less_equal(0xD, "ge");
6109 greater(0xC, "l");
6110 %}
6111 %}
6112
6113 //----------OPERAND CLASSES----------------------------------------------------
6114 // Operand Classes are groups of operands that are used as to simplify
6115 // instruction definitions by not requiring the AD writer to specify separate
6116 // instructions for every form of operand when the instruction accepts
6117 // multiple operand types with the same basic encoding and format. The classic
6118 // case of this is memory operands.
6119
6120 opclass memory(direct, indirect, indOffset8, indOffset32, indOffset32X, indIndexOffset,
6121 indIndex, indIndexScale, indIndexScaleOffset);
6122
6123 // Long memory operations are encoded in 2 instructions and a +4 offset.
6124 // This means some kind of offset is always required and you cannot use
6125 // an oop as the offset (done when working on static globals).
6126 opclass long_memory(direct, indirect, indOffset8, indOffset32, indIndexOffset,
6127 indIndex, indIndexScale, indIndexScaleOffset);
6128
6129
6130 //----------PIPELINE-----------------------------------------------------------
6131 // Rules which define the behavior of the target architectures pipeline.
6132 pipeline %{
6133
6134 //----------ATTRIBUTES---------------------------------------------------------
6135 attributes %{
6136 variable_size_instructions; // Fixed size instructions
6137 max_instructions_per_bundle = 3; // Up to 3 instructions per bundle
6138 instruction_unit_size = 1; // An instruction is 1 bytes long
6139 instruction_fetch_unit_size = 16; // The processor fetches one line
6140 instruction_fetch_units = 1; // of 16 bytes
6141
6142 // List of nop instructions
6143 nops( MachNop );
6144 %}
6145
6146 //----------RESOURCES----------------------------------------------------------
6147 // Resources are the functional units available to the machine
6148
6149 // Generic P2/P3 pipeline
6150 // 3 decoders, only D0 handles big operands; a "bundle" is the limit of
6151 // 3 instructions decoded per cycle.
6152 // 2 load/store ops per cycle, 1 branch, 1 FPU,
6153 // 2 ALU op, only ALU0 handles mul/div instructions.
6154 resources( D0, D1, D2, DECODE = D0 | D1 | D2,
6155 MS0, MS1, MEM = MS0 | MS1,
6156 BR, FPU,
6157 ALU0, ALU1, ALU = ALU0 | ALU1 );
6158
6159 //----------PIPELINE DESCRIPTION-----------------------------------------------
6160 // Pipeline Description specifies the stages in the machine's pipeline
6161
6162 // Generic P2/P3 pipeline
6163 pipe_desc(S0, S1, S2, S3, S4, S5);
6164
6165 //----------PIPELINE CLASSES---------------------------------------------------
6166 // Pipeline Classes describe the stages in which input and output are
6167 // referenced by the hardware pipeline.
6168
6169 // Naming convention: ialu or fpu
6170 // Then: _reg
6171 // Then: _reg if there is a 2nd register
6172 // Then: _long if it's a pair of instructions implementing a long
6173 // Then: _fat if it requires the big decoder
6174 // Or: _mem if it requires the big decoder and a memory unit.
6175
6176 // Integer ALU reg operation
6177 pipe_class ialu_reg(eRegI dst) %{
6178 single_instruction;
6179 dst : S4(write);
6180 dst : S3(read);
6181 DECODE : S0; // any decoder
6182 ALU : S3; // any alu
6183 %}
6184
6185 // Long ALU reg operation
6186 pipe_class ialu_reg_long(eRegL dst) %{
6187 instruction_count(2);
6188 dst : S4(write);
6189 dst : S3(read);
6190 DECODE : S0(2); // any 2 decoders
6191 ALU : S3(2); // both alus
6192 %}
6193
6194 // Integer ALU reg operation using big decoder
6195 pipe_class ialu_reg_fat(eRegI dst) %{
6196 single_instruction;
6197 dst : S4(write);
6198 dst : S3(read);
6199 D0 : S0; // big decoder only
6200 ALU : S3; // any alu
6201 %}
6202
6203 // Long ALU reg operation using big decoder
6204 pipe_class ialu_reg_long_fat(eRegL dst) %{
6205 instruction_count(2);
6206 dst : S4(write);
6207 dst : S3(read);
6208 D0 : S0(2); // big decoder only; twice
6209 ALU : S3(2); // any 2 alus
6210 %}
6211
6212 // Integer ALU reg-reg operation
6213 pipe_class ialu_reg_reg(eRegI dst, eRegI src) %{
6214 single_instruction;
6215 dst : S4(write);
6216 src : S3(read);
6217 DECODE : S0; // any decoder
6218 ALU : S3; // any alu
6219 %}
6220
6221 // Long ALU reg-reg operation
6222 pipe_class ialu_reg_reg_long(eRegL dst, eRegL src) %{
6223 instruction_count(2);
6224 dst : S4(write);
6225 src : S3(read);
6226 DECODE : S0(2); // any 2 decoders
6227 ALU : S3(2); // both alus
6228 %}
6229
6230 // Integer ALU reg-reg operation
6231 pipe_class ialu_reg_reg_fat(eRegI dst, memory src) %{
6232 single_instruction;
6233 dst : S4(write);
6234 src : S3(read);
6235 D0 : S0; // big decoder only
6236 ALU : S3; // any alu
6237 %}
6238
6239 // Long ALU reg-reg operation
6240 pipe_class ialu_reg_reg_long_fat(eRegL dst, eRegL src) %{
6241 instruction_count(2);
6242 dst : S4(write);
6243 src : S3(read);
6244 D0 : S0(2); // big decoder only; twice
6245 ALU : S3(2); // both alus
6246 %}
6247
6248 // Integer ALU reg-mem operation
6249 pipe_class ialu_reg_mem(eRegI dst, memory mem) %{
6250 single_instruction;
6251 dst : S5(write);
6252 mem : S3(read);
6253 D0 : S0; // big decoder only
6254 ALU : S4; // any alu
6255 MEM : S3; // any mem
6256 %}
6257
6258 // Long ALU reg-mem operation
6259 pipe_class ialu_reg_long_mem(eRegL dst, load_long_memory mem) %{
6260 instruction_count(2);
6261 dst : S5(write);
6262 mem : S3(read);
6263 D0 : S0(2); // big decoder only; twice
6264 ALU : S4(2); // any 2 alus
6265 MEM : S3(2); // both mems
6266 %}
6267
6268 // Integer mem operation (prefetch)
6269 pipe_class ialu_mem(memory mem)
6270 %{
6271 single_instruction;
6272 mem : S3(read);
6273 D0 : S0; // big decoder only
6274 MEM : S3; // any mem
6275 %}
6276
6277 // Integer Store to Memory
6278 pipe_class ialu_mem_reg(memory mem, eRegI src) %{
6279 single_instruction;
6280 mem : S3(read);
6281 src : S5(read);
6282 D0 : S0; // big decoder only
6283 ALU : S4; // any alu
6284 MEM : S3;
6285 %}
6286
6287 // Long Store to Memory
6288 pipe_class ialu_mem_long_reg(memory mem, eRegL src) %{
6289 instruction_count(2);
6290 mem : S3(read);
6291 src : S5(read);
6292 D0 : S0(2); // big decoder only; twice
6293 ALU : S4(2); // any 2 alus
6294 MEM : S3(2); // Both mems
6295 %}
6296
6297 // Integer Store to Memory
6298 pipe_class ialu_mem_imm(memory mem) %{
6299 single_instruction;
6300 mem : S3(read);
6301 D0 : S0; // big decoder only
6302 ALU : S4; // any alu
6303 MEM : S3;
6304 %}
6305
6306 // Integer ALU0 reg-reg operation
6307 pipe_class ialu_reg_reg_alu0(eRegI dst, eRegI src) %{
6308 single_instruction;
6309 dst : S4(write);
6310 src : S3(read);
6311 D0 : S0; // Big decoder only
6312 ALU0 : S3; // only alu0
6313 %}
6314
6315 // Integer ALU0 reg-mem operation
6316 pipe_class ialu_reg_mem_alu0(eRegI dst, memory mem) %{
6317 single_instruction;
6318 dst : S5(write);
6319 mem : S3(read);
6320 D0 : S0; // big decoder only
6321 ALU0 : S4; // ALU0 only
6322 MEM : S3; // any mem
6323 %}
6324
6325 // Integer ALU reg-reg operation
6326 pipe_class ialu_cr_reg_reg(eFlagsReg cr, eRegI src1, eRegI src2) %{
6327 single_instruction;
6328 cr : S4(write);
6329 src1 : S3(read);
6330 src2 : S3(read);
6331 DECODE : S0; // any decoder
6332 ALU : S3; // any alu
6333 %}
6334
6335 // Integer ALU reg-imm operation
6336 pipe_class ialu_cr_reg_imm(eFlagsReg cr, eRegI src1) %{
6337 single_instruction;
6338 cr : S4(write);
6339 src1 : S3(read);
6340 DECODE : S0; // any decoder
6341 ALU : S3; // any alu
6342 %}
6343
6344 // Integer ALU reg-mem operation
6345 pipe_class ialu_cr_reg_mem(eFlagsReg cr, eRegI src1, memory src2) %{
6346 single_instruction;
6347 cr : S4(write);
6348 src1 : S3(read);
6349 src2 : S3(read);
6350 D0 : S0; // big decoder only
6351 ALU : S4; // any alu
6352 MEM : S3;
6353 %}
6354
6355 // Conditional move reg-reg
6356 pipe_class pipe_cmplt( eRegI p, eRegI q, eRegI y ) %{
6357 instruction_count(4);
6358 y : S4(read);
6359 q : S3(read);
6360 p : S3(read);
6361 DECODE : S0(4); // any decoder
6362 %}
6363
6364 // Conditional move reg-reg
6365 pipe_class pipe_cmov_reg( eRegI dst, eRegI src, eFlagsReg cr ) %{
6366 single_instruction;
6367 dst : S4(write);
6368 src : S3(read);
6369 cr : S3(read);
6370 DECODE : S0; // any decoder
6371 %}
6372
6373 // Conditional move reg-mem
6374 pipe_class pipe_cmov_mem( eFlagsReg cr, eRegI dst, memory src) %{
6375 single_instruction;
6376 dst : S4(write);
6377 src : S3(read);
6378 cr : S3(read);
6379 DECODE : S0; // any decoder
6380 MEM : S3;
6381 %}
6382
6383 // Conditional move reg-reg long
6384 pipe_class pipe_cmov_reg_long( eFlagsReg cr, eRegL dst, eRegL src) %{
6385 single_instruction;
6386 dst : S4(write);
6387 src : S3(read);
6388 cr : S3(read);
6389 DECODE : S0(2); // any 2 decoders
6390 %}
6391
6392 // Conditional move double reg-reg
6393 pipe_class pipe_cmovD_reg( eFlagsReg cr, regDPR1 dst, regD src) %{
6394 single_instruction;
6395 dst : S4(write);
6396 src : S3(read);
6397 cr : S3(read);
6398 DECODE : S0; // any decoder
6399 %}
6400
6401 // Float reg-reg operation
6402 pipe_class fpu_reg(regD dst) %{
6403 instruction_count(2);
6404 dst : S3(read);
6405 DECODE : S0(2); // any 2 decoders
6406 FPU : S3;
6407 %}
6408
6409 // Float reg-reg operation
6410 pipe_class fpu_reg_reg(regD dst, regD src) %{
6411 instruction_count(2);
6412 dst : S4(write);
6413 src : S3(read);
6414 DECODE : S0(2); // any 2 decoders
6415 FPU : S3;
6416 %}
6417
6418 // Float reg-reg operation
6419 pipe_class fpu_reg_reg_reg(regD dst, regD src1, regD src2) %{
6420 instruction_count(3);
6421 dst : S4(write);
6422 src1 : S3(read);
6423 src2 : S3(read);
6424 DECODE : S0(3); // any 3 decoders
6425 FPU : S3(2);
6426 %}
6427
6428 // Float reg-reg operation
6429 pipe_class fpu_reg_reg_reg_reg(regD dst, regD src1, regD src2, regD src3) %{
6430 instruction_count(4);
6431 dst : S4(write);
6432 src1 : S3(read);
6433 src2 : S3(read);
6434 src3 : S3(read);
6435 DECODE : S0(4); // any 3 decoders
6436 FPU : S3(2);
6437 %}
6438
6439 // Float reg-reg operation
6440 pipe_class fpu_reg_mem_reg_reg(regD dst, memory src1, regD src2, regD src3) %{
6441 instruction_count(4);
6442 dst : S4(write);
6443 src1 : S3(read);
6444 src2 : S3(read);
6445 src3 : S3(read);
6446 DECODE : S1(3); // any 3 decoders
6447 D0 : S0; // Big decoder only
6448 FPU : S3(2);
6449 MEM : S3;
6450 %}
6451
6452 // Float reg-mem operation
6453 pipe_class fpu_reg_mem(regD dst, memory mem) %{
6454 instruction_count(2);
6455 dst : S5(write);
6456 mem : S3(read);
6457 D0 : S0; // big decoder only
6458 DECODE : S1; // any decoder for FPU POP
6459 FPU : S4;
6460 MEM : S3; // any mem
6461 %}
6462
6463 // Float reg-mem operation
6464 pipe_class fpu_reg_reg_mem(regD dst, regD src1, memory mem) %{
6465 instruction_count(3);
6466 dst : S5(write);
6467 src1 : S3(read);
6468 mem : S3(read);
6469 D0 : S0; // big decoder only
6470 DECODE : S1(2); // any decoder for FPU POP
6471 FPU : S4;
6472 MEM : S3; // any mem
6473 %}
6474
6475 // Float mem-reg operation
6476 pipe_class fpu_mem_reg(memory mem, regD src) %{
6477 instruction_count(2);
6478 src : S5(read);
6479 mem : S3(read);
6480 DECODE : S0; // any decoder for FPU PUSH
6481 D0 : S1; // big decoder only
6482 FPU : S4;
6483 MEM : S3; // any mem
6484 %}
6485
6486 pipe_class fpu_mem_reg_reg(memory mem, regD src1, regD src2) %{
6487 instruction_count(3);
6488 src1 : S3(read);
6489 src2 : S3(read);
6490 mem : S3(read);
6491 DECODE : S0(2); // any decoder for FPU PUSH
6492 D0 : S1; // big decoder only
6493 FPU : S4;
6494 MEM : S3; // any mem
6495 %}
6496
6497 pipe_class fpu_mem_reg_mem(memory mem, regD src1, memory src2) %{
6498 instruction_count(3);
6499 src1 : S3(read);
6500 src2 : S3(read);
6501 mem : S4(read);
6502 DECODE : S0; // any decoder for FPU PUSH
6503 D0 : S0(2); // big decoder only
6504 FPU : S4;
6505 MEM : S3(2); // any mem
6506 %}
6507
6508 pipe_class fpu_mem_mem(memory dst, memory src1) %{
6509 instruction_count(2);
6510 src1 : S3(read);
6511 dst : S4(read);
6512 D0 : S0(2); // big decoder only
6513 MEM : S3(2); // any mem
6514 %}
6515
6516 pipe_class fpu_mem_mem_mem(memory dst, memory src1, memory src2) %{
6517 instruction_count(3);
6518 src1 : S3(read);
6519 src2 : S3(read);
6520 dst : S4(read);
6521 D0 : S0(3); // big decoder only
6522 FPU : S4;
6523 MEM : S3(3); // any mem
6524 %}
6525
6526 pipe_class fpu_mem_reg_con(memory mem, regD src1) %{
6527 instruction_count(3);
6528 src1 : S4(read);
6529 mem : S4(read);
6530 DECODE : S0; // any decoder for FPU PUSH
6531 D0 : S0(2); // big decoder only
6532 FPU : S4;
6533 MEM : S3(2); // any mem
6534 %}
6535
6536 // Float load constant
6537 pipe_class fpu_reg_con(regD dst) %{
6538 instruction_count(2);
6539 dst : S5(write);
6540 D0 : S0; // big decoder only for the load
6541 DECODE : S1; // any decoder for FPU POP
6542 FPU : S4;
6543 MEM : S3; // any mem
6544 %}
6545
6546 // Float load constant
6547 pipe_class fpu_reg_reg_con(regD dst, regD src) %{
6548 instruction_count(3);
6549 dst : S5(write);
6550 src : S3(read);
6551 D0 : S0; // big decoder only for the load
6552 DECODE : S1(2); // any decoder for FPU POP
6553 FPU : S4;
6554 MEM : S3; // any mem
6555 %}
6556
6557 // UnConditional branch
6558 pipe_class pipe_jmp( label labl ) %{
6559 single_instruction;
6560 BR : S3;
6561 %}
6562
6563 // Conditional branch
6564 pipe_class pipe_jcc( cmpOp cmp, eFlagsReg cr, label labl ) %{
6565 single_instruction;
6566 cr : S1(read);
6567 BR : S3;
6568 %}
6569
6570 // Allocation idiom
6571 pipe_class pipe_cmpxchg( eRegP dst, eRegP heap_ptr ) %{
6572 instruction_count(1); force_serialization;
6573 fixed_latency(6);
6574 heap_ptr : S3(read);
6575 DECODE : S0(3);
6576 D0 : S2;
6577 MEM : S3;
6578 ALU : S3(2);
6579 dst : S5(write);
6580 BR : S5;
6581 %}
6582
6583 // Generic big/slow expanded idiom
6584 pipe_class pipe_slow( ) %{
6585 instruction_count(10); multiple_bundles; force_serialization;
6586 fixed_latency(100);
6587 D0 : S0(2);
6588 MEM : S3(2);
6589 %}
6590
6591 // The real do-nothing guy
6592 pipe_class empty( ) %{
6593 instruction_count(0);
6594 %}
6595
6596 // Define the class for the Nop node
6597 define %{
6598 MachNop = empty;
6599 %}
6600
6601 %}
6602
6603 //----------INSTRUCTIONS-------------------------------------------------------
6604 //
6605 // match -- States which machine-independent subtree may be replaced
6606 // by this instruction.
6607 // ins_cost -- The estimated cost of this instruction is used by instruction
6608 // selection to identify a minimum cost tree of machine
6609 // instructions that matches a tree of machine-independent
6610 // instructions.
6611 // format -- A string providing the disassembly for this instruction.
6612 // The value of an instruction's operand may be inserted
6613 // by referring to it with a '$' prefix.
6614 // opcode -- Three instruction opcodes may be provided. These are referred
6615 // to within an encode class as $primary, $secondary, and $tertiary
6616 // respectively. The primary opcode is commonly used to
6617 // indicate the type of machine instruction, while secondary
6618 // and tertiary are often used for prefix options or addressing
6619 // modes.
6620 // ins_encode -- A list of encode classes with parameters. The encode class
6621 // name must have been defined in an 'enc_class' specification
6622 // in the encode section of the architecture description.
6623
6624 //----------BSWAP-Instruction--------------------------------------------------
6625 instruct bytes_reverse_int(eRegI dst) %{
6626 match(Set dst (ReverseBytesI dst));
6627
6628 format %{ "BSWAP $dst" %}
6629 opcode(0x0F, 0xC8);
6630 ins_encode( OpcP, OpcSReg(dst) );
6631 ins_pipe( ialu_reg );
6632 %}
6633
6634 instruct bytes_reverse_long(eRegL dst) %{
6635 match(Set dst (ReverseBytesL dst));
6636
6637 format %{ "BSWAP $dst.lo\n\t"
6638 "BSWAP $dst.hi\n\t"
6639 "XCHG $dst.lo $dst.hi" %}
6640
6641 ins_cost(125);
6642 ins_encode( bswap_long_bytes(dst) );
6643 ins_pipe( ialu_reg_reg);
6644 %}
6645
6646
6647 //---------- Population Count Instructions -------------------------------------
6648
6649 instruct popCountI(eRegI dst, eRegI src) %{
6650 predicate(UsePopCountInstruction);
6651 match(Set dst (PopCountI src));
6652
6653 format %{ "POPCNT $dst, $src" %}
6654 ins_encode %{
6655 __ popcntl($dst$$Register, $src$$Register);
6656 %}
6657 ins_pipe(ialu_reg);
6658 %}
6659
6660 instruct popCountI_mem(eRegI dst, memory mem) %{
6661 predicate(UsePopCountInstruction);
6662 match(Set dst (PopCountI (LoadI mem)));
6663
6664 format %{ "POPCNT $dst, $mem" %}
6665 ins_encode %{
6666 __ popcntl($dst$$Register, $mem$$Address);
6667 %}
6668 ins_pipe(ialu_reg);
6669 %}
6670
6671 // Note: Long.bitCount(long) returns an int.
6672 instruct popCountL(eRegI dst, eRegL src, eRegI tmp, eFlagsReg cr) %{
6673 predicate(UsePopCountInstruction);
6674 match(Set dst (PopCountL src));
6675 effect(KILL cr, TEMP tmp, TEMP dst);
6676
6677 format %{ "POPCNT $dst, $src.lo\n\t"
6678 "POPCNT $tmp, $src.hi\n\t"
6679 "ADD $dst, $tmp" %}
6680 ins_encode %{
6681 __ popcntl($dst$$Register, $src$$Register);
6682 __ popcntl($tmp$$Register, HIGH_FROM_LOW($src$$Register));
6683 __ addl($dst$$Register, $tmp$$Register);
6684 %}
6685 ins_pipe(ialu_reg);
6686 %}
6687
6688 // Note: Long.bitCount(long) returns an int.
6689 instruct popCountL_mem(eRegI dst, memory mem, eRegI tmp, eFlagsReg cr) %{
6690 predicate(UsePopCountInstruction);
6691 match(Set dst (PopCountL (LoadL mem)));
6692 effect(KILL cr, TEMP tmp, TEMP dst);
6693
6694 format %{ "POPCNT $dst, $mem\n\t"
6695 "POPCNT $tmp, $mem+4\n\t"
6696 "ADD $dst, $tmp" %}
6697 ins_encode %{
6698 //__ popcntl($dst$$Register, $mem$$Address$$first);
6699 //__ popcntl($tmp$$Register, $mem$$Address$$second);
6700 __ popcntl($dst$$Register, Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp, false));
6701 __ popcntl($tmp$$Register, Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp + 4, false));
6702 __ addl($dst$$Register, $tmp$$Register);
6703 %}
6704 ins_pipe(ialu_reg);
6705 %}
6706
6707
6708 //----------Load/Store/Move Instructions---------------------------------------
6709 //----------Load Instructions--------------------------------------------------
6710 // Load Byte (8bit signed)
6711 instruct loadB(xRegI dst, memory mem) %{
6712 match(Set dst (LoadB mem));
6713
6714 ins_cost(125);
6715 format %{ "MOVSX8 $dst,$mem\t# byte" %}
6716
6717 ins_encode %{
6718 __ movsbl($dst$$Register, $mem$$Address);
6719 %}
6720
6721 ins_pipe(ialu_reg_mem);
6722 %}
6723
6724 // Load Byte (8bit signed) into Long Register
6725 instruct loadB2L(eRegL dst, memory mem) %{
6726 match(Set dst (ConvI2L (LoadB mem)));
6727
6728 ins_cost(375);
6729 format %{ "MOVSX8 $dst.lo,$mem\t# byte -> long\n\t"
6730 "MOV $dst.hi,$dst.lo\n\t"
6731 "SAR $dst.hi,7" %}
6732
6733 ins_encode %{
6734 __ movsbl($dst$$Register, $mem$$Address);
6735 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
6736 __ sarl(HIGH_FROM_LOW($dst$$Register), 7); // 24+1 MSB are already signed extended.
6737 %}
6738
6739 ins_pipe(ialu_reg_mem);
6740 %}
6741
6742 // Load Unsigned Byte (8bit UNsigned)
6743 instruct loadUB(xRegI dst, memory mem) %{
6744 match(Set dst (LoadUB mem));
6745
6746 ins_cost(125);
6747 format %{ "MOVZX8 $dst,$mem\t# ubyte -> int" %}
6748
6749 ins_encode %{
6750 __ movzbl($dst$$Register, $mem$$Address);
6751 %}
6752
6753 ins_pipe(ialu_reg_mem);
6754 %}
6755
6756 // Load Unsigned Byte (8 bit UNsigned) into Long Register
6757 instruct loadUB2L(eRegL dst, memory mem)
6758 %{
6759 match(Set dst (ConvI2L (LoadUB mem)));
6760
6761 ins_cost(250);
6762 format %{ "MOVZX8 $dst.lo,$mem\t# ubyte -> long\n\t"
6763 "XOR $dst.hi,$dst.hi" %}
6764
6765 ins_encode %{
6766 __ movzbl($dst$$Register, $mem$$Address);
6767 __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register));
6768 %}
6769
6770 ins_pipe(ialu_reg_mem);
6771 %}
6772
6773 // Load Short (16bit signed)
6774 instruct loadS(eRegI dst, memory mem) %{
6775 match(Set dst (LoadS mem));
6776
6777 ins_cost(125);
6778 format %{ "MOVSX $dst,$mem\t# short" %}
6779
6780 ins_encode %{
6781 __ movswl($dst$$Register, $mem$$Address);
6782 %}
6783
6784 ins_pipe(ialu_reg_mem);
6785 %}
6786
6787 // Load Short (16bit signed) into Long Register
6788 instruct loadS2L(eRegL dst, memory mem) %{
6789 match(Set dst (ConvI2L (LoadS mem)));
6790
6791 ins_cost(375);
6792 format %{ "MOVSX $dst.lo,$mem\t# short -> long\n\t"
6793 "MOV $dst.hi,$dst.lo\n\t"
6794 "SAR $dst.hi,15" %}
6795
6796 ins_encode %{
6797 __ movswl($dst$$Register, $mem$$Address);
6798 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
6799 __ sarl(HIGH_FROM_LOW($dst$$Register), 15); // 16+1 MSB are already signed extended.
6800 %}
6801
6802 ins_pipe(ialu_reg_mem);
6803 %}
6804
6805 // Load Unsigned Short/Char (16bit unsigned)
6806 instruct loadUS(eRegI dst, memory mem) %{
6807 match(Set dst (LoadUS mem));
6808
6809 ins_cost(125);
6810 format %{ "MOVZX $dst,$mem\t# ushort/char -> int" %}
6811
6812 ins_encode %{
6813 __ movzwl($dst$$Register, $mem$$Address);
6814 %}
6815
6816 ins_pipe(ialu_reg_mem);
6817 %}
6818
6819 // Load Unsigned Short/Char (16 bit UNsigned) into Long Register
6820 instruct loadUS2L(eRegL dst, memory mem)
6821 %{
6822 match(Set dst (ConvI2L (LoadUS mem)));
6823
6824 ins_cost(250);
6825 format %{ "MOVZX $dst.lo,$mem\t# ushort/char -> long\n\t"
6826 "XOR $dst.hi,$dst.hi" %}
6827
6828 ins_encode %{
6829 __ movzwl($dst$$Register, $mem$$Address);
6830 __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register));
6831 %}
6832
6833 ins_pipe(ialu_reg_mem);
6834 %}
6835
6836 // Load Integer
6837 instruct loadI(eRegI dst, memory mem) %{
6838 match(Set dst (LoadI mem));
6839
6840 ins_cost(125);
6841 format %{ "MOV $dst,$mem\t# int" %}
6842
6843 ins_encode %{
6844 __ movl($dst$$Register, $mem$$Address);
6845 %}
6846
6847 ins_pipe(ialu_reg_mem);
6848 %}
6849
6850 // Load Integer into Long Register
6851 instruct loadI2L(eRegL dst, memory mem) %{
6852 match(Set dst (ConvI2L (LoadI mem)));
6853
6854 ins_cost(375);
6855 format %{ "MOV $dst.lo,$mem\t# int -> long\n\t"
6856 "MOV $dst.hi,$dst.lo\n\t"
6857 "SAR $dst.hi,31" %}
6858
6859 ins_encode %{
6860 __ movl($dst$$Register, $mem$$Address);
6861 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
6862 __ sarl(HIGH_FROM_LOW($dst$$Register), 31);
6863 %}
6864
6865 ins_pipe(ialu_reg_mem);
6866 %}
6867
6868 // Load Unsigned Integer into Long Register
6869 instruct loadUI2L(eRegL dst, memory mem) %{
6870 match(Set dst (LoadUI2L mem));
6871
6872 ins_cost(250);
6873 format %{ "MOV $dst.lo,$mem\t# uint -> long\n\t"
6874 "XOR $dst.hi,$dst.hi" %}
6875
6876 ins_encode %{
6877 __ movl($dst$$Register, $mem$$Address);
6878 __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register));
6879 %}
6880
6881 ins_pipe(ialu_reg_mem);
6882 %}
6883
6884 // Load Long. Cannot clobber address while loading, so restrict address
6885 // register to ESI
6886 instruct loadL(eRegL dst, load_long_memory mem) %{
6887 predicate(!((LoadLNode*)n)->require_atomic_access());
6888 match(Set dst (LoadL mem));
6889
6890 ins_cost(250);
6891 format %{ "MOV $dst.lo,$mem\t# long\n\t"
6892 "MOV $dst.hi,$mem+4" %}
6893
6894 ins_encode %{
6895 Address Amemlo = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp, false);
6896 Address Amemhi = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp + 4, false);
6897 __ movl($dst$$Register, Amemlo);
6898 __ movl(HIGH_FROM_LOW($dst$$Register), Amemhi);
6899 %}
6900
6901 ins_pipe(ialu_reg_long_mem);
6902 %}
6903
6904 // Volatile Load Long. Must be atomic, so do 64-bit FILD
6905 // then store it down to the stack and reload on the int
6906 // side.
6907 instruct loadL_volatile(stackSlotL dst, memory mem) %{
6908 predicate(UseSSE<=1 && ((LoadLNode*)n)->require_atomic_access());
6909 match(Set dst (LoadL mem));
6910
6911 ins_cost(200);
6912 format %{ "FILD $mem\t# Atomic volatile long load\n\t"
6913 "FISTp $dst" %}
6914 ins_encode(enc_loadL_volatile(mem,dst));
6915 ins_pipe( fpu_reg_mem );
6916 %}
6917
6918 instruct loadLX_volatile(stackSlotL dst, memory mem, regXD tmp) %{
6919 predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access());
6920 match(Set dst (LoadL mem));
6921 effect(TEMP tmp);
6922 ins_cost(180);
6923 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
6924 "MOVSD $dst,$tmp" %}
6925 ins_encode(enc_loadLX_volatile(mem, dst, tmp));
6926 ins_pipe( pipe_slow );
6927 %}
6928
6929 instruct loadLX_reg_volatile(eRegL dst, memory mem, regXD tmp) %{
6930 predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access());
6931 match(Set dst (LoadL mem));
6932 effect(TEMP tmp);
6933 ins_cost(160);
6934 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
6935 "MOVD $dst.lo,$tmp\n\t"
6936 "PSRLQ $tmp,32\n\t"
6937 "MOVD $dst.hi,$tmp" %}
6938 ins_encode(enc_loadLX_reg_volatile(mem, dst, tmp));
6939 ins_pipe( pipe_slow );
6940 %}
6941
6942 // Load Range
6943 instruct loadRange(eRegI dst, memory mem) %{
6944 match(Set dst (LoadRange mem));
6945
6946 ins_cost(125);
6947 format %{ "MOV $dst,$mem" %}
6948 opcode(0x8B);
6949 ins_encode( OpcP, RegMem(dst,mem));
6950 ins_pipe( ialu_reg_mem );
6951 %}
6952
6953
6954 // Load Pointer
6955 instruct loadP(eRegP dst, memory mem) %{
6956 match(Set dst (LoadP mem));
6957
6958 ins_cost(125);
6959 format %{ "MOV $dst,$mem" %}
6960 opcode(0x8B);
6961 ins_encode( OpcP, RegMem(dst,mem));
6962 ins_pipe( ialu_reg_mem );
6963 %}
6964
6965 // Load Klass Pointer
6966 instruct loadKlass(eRegP dst, memory mem) %{
6967 match(Set dst (LoadKlass mem));
6968
6969 ins_cost(125);
6970 format %{ "MOV $dst,$mem" %}
6971 opcode(0x8B);
6972 ins_encode( OpcP, RegMem(dst,mem));
6973 ins_pipe( ialu_reg_mem );
6974 %}
6975
6976 // Load Double
6977 instruct loadD(regD dst, memory mem) %{
6978 predicate(UseSSE<=1);
6979 match(Set dst (LoadD mem));
6980
6981 ins_cost(150);
6982 format %{ "FLD_D ST,$mem\n\t"
6983 "FSTP $dst" %}
6984 opcode(0xDD); /* DD /0 */
6985 ins_encode( OpcP, RMopc_Mem(0x00,mem),
6986 Pop_Reg_D(dst) );
6987 ins_pipe( fpu_reg_mem );
6988 %}
6989
6990 // Load Double to XMM
6991 instruct loadXD(regXD dst, memory mem) %{
6992 predicate(UseSSE>=2 && UseXmmLoadAndClearUpper);
6993 match(Set dst (LoadD mem));
6994 ins_cost(145);
6995 format %{ "MOVSD $dst,$mem" %}
6996 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x10), RegMem(dst,mem));
6997 ins_pipe( pipe_slow );
6998 %}
6999
7000 instruct loadXD_partial(regXD dst, memory mem) %{
7001 predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper);
7002 match(Set dst (LoadD mem));
7003 ins_cost(145);
7004 format %{ "MOVLPD $dst,$mem" %}
7005 ins_encode( Opcode(0x66), Opcode(0x0F), Opcode(0x12), RegMem(dst,mem));
7006 ins_pipe( pipe_slow );
7007 %}
7008
7009 // Load to XMM register (single-precision floating point)
7010 // MOVSS instruction
7011 instruct loadX(regX dst, memory mem) %{
7012 predicate(UseSSE>=1);
7013 match(Set dst (LoadF mem));
7014 ins_cost(145);
7015 format %{ "MOVSS $dst,$mem" %}
7016 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x10), RegMem(dst,mem));
7017 ins_pipe( pipe_slow );
7018 %}
7019
7020 // Load Float
7021 instruct loadF(regF dst, memory mem) %{
7022 predicate(UseSSE==0);
7023 match(Set dst (LoadF mem));
7024
7025 ins_cost(150);
7026 format %{ "FLD_S ST,$mem\n\t"
7027 "FSTP $dst" %}
7028 opcode(0xD9); /* D9 /0 */
7029 ins_encode( OpcP, RMopc_Mem(0x00,mem),
7030 Pop_Reg_F(dst) );
7031 ins_pipe( fpu_reg_mem );
7032 %}
7033
7034 // Load Aligned Packed Byte to XMM register
7035 instruct loadA8B(regXD dst, memory mem) %{
7036 predicate(UseSSE>=1);
7037 match(Set dst (Load8B mem));
7038 ins_cost(125);
7039 format %{ "MOVQ $dst,$mem\t! packed8B" %}
7040 ins_encode( movq_ld(dst, mem));
7041 ins_pipe( pipe_slow );
7042 %}
7043
7044 // Load Aligned Packed Short to XMM register
7045 instruct loadA4S(regXD dst, memory mem) %{
7046 predicate(UseSSE>=1);
7047 match(Set dst (Load4S mem));
7048 ins_cost(125);
7049 format %{ "MOVQ $dst,$mem\t! packed4S" %}
7050 ins_encode( movq_ld(dst, mem));
7051 ins_pipe( pipe_slow );
7052 %}
7053
7054 // Load Aligned Packed Char to XMM register
7055 instruct loadA4C(regXD dst, memory mem) %{
7056 predicate(UseSSE>=1);
7057 match(Set dst (Load4C mem));
7058 ins_cost(125);
7059 format %{ "MOVQ $dst,$mem\t! packed4C" %}
7060 ins_encode( movq_ld(dst, mem));
7061 ins_pipe( pipe_slow );
7062 %}
7063
7064 // Load Aligned Packed Integer to XMM register
7065 instruct load2IU(regXD dst, memory mem) %{
7066 predicate(UseSSE>=1);
7067 match(Set dst (Load2I mem));
7068 ins_cost(125);
7069 format %{ "MOVQ $dst,$mem\t! packed2I" %}
7070 ins_encode( movq_ld(dst, mem));
7071 ins_pipe( pipe_slow );
7072 %}
7073
7074 // Load Aligned Packed Single to XMM
7075 instruct loadA2F(regXD dst, memory mem) %{
7076 predicate(UseSSE>=1);
7077 match(Set dst (Load2F mem));
7078 ins_cost(145);
7079 format %{ "MOVQ $dst,$mem\t! packed2F" %}
7080 ins_encode( movq_ld(dst, mem));
7081 ins_pipe( pipe_slow );
7082 %}
7083
7084 // Load Effective Address
7085 instruct leaP8(eRegP dst, indOffset8 mem) %{
7086 match(Set dst mem);
7087
7088 ins_cost(110);
7089 format %{ "LEA $dst,$mem" %}
7090 opcode(0x8D);
7091 ins_encode( OpcP, RegMem(dst,mem));
7092 ins_pipe( ialu_reg_reg_fat );
7093 %}
7094
7095 instruct leaP32(eRegP dst, indOffset32 mem) %{
7096 match(Set dst mem);
7097
7098 ins_cost(110);
7099 format %{ "LEA $dst,$mem" %}
7100 opcode(0x8D);
7101 ins_encode( OpcP, RegMem(dst,mem));
7102 ins_pipe( ialu_reg_reg_fat );
7103 %}
7104
7105 instruct leaPIdxOff(eRegP dst, indIndexOffset mem) %{
7106 match(Set dst mem);
7107
7108 ins_cost(110);
7109 format %{ "LEA $dst,$mem" %}
7110 opcode(0x8D);
7111 ins_encode( OpcP, RegMem(dst,mem));
7112 ins_pipe( ialu_reg_reg_fat );
7113 %}
7114
7115 instruct leaPIdxScale(eRegP dst, indIndexScale mem) %{
7116 match(Set dst mem);
7117
7118 ins_cost(110);
7119 format %{ "LEA $dst,$mem" %}
7120 opcode(0x8D);
7121 ins_encode( OpcP, RegMem(dst,mem));
7122 ins_pipe( ialu_reg_reg_fat );
7123 %}
7124
7125 instruct leaPIdxScaleOff(eRegP dst, indIndexScaleOffset mem) %{
7126 match(Set dst mem);
7127
7128 ins_cost(110);
7129 format %{ "LEA $dst,$mem" %}
7130 opcode(0x8D);
7131 ins_encode( OpcP, RegMem(dst,mem));
7132 ins_pipe( ialu_reg_reg_fat );
7133 %}
7134
7135 // Load Constant
7136 instruct loadConI(eRegI dst, immI src) %{
7137 match(Set dst src);
7138
7139 format %{ "MOV $dst,$src" %}
7140 ins_encode( LdImmI(dst, src) );
7141 ins_pipe( ialu_reg_fat );
7142 %}
7143
7144 // Load Constant zero
7145 instruct loadConI0(eRegI dst, immI0 src, eFlagsReg cr) %{
7146 match(Set dst src);
7147 effect(KILL cr);
7148
7149 ins_cost(50);
7150 format %{ "XOR $dst,$dst" %}
7151 opcode(0x33); /* + rd */
7152 ins_encode( OpcP, RegReg( dst, dst ) );
7153 ins_pipe( ialu_reg );
7154 %}
7155
7156 instruct loadConP(eRegP dst, immP src) %{
7157 match(Set dst src);
7158
7159 format %{ "MOV $dst,$src" %}
7160 opcode(0xB8); /* + rd */
7161 ins_encode( LdImmP(dst, src) );
7162 ins_pipe( ialu_reg_fat );
7163 %}
7164
7165 instruct loadConL(eRegL dst, immL src, eFlagsReg cr) %{
7166 match(Set dst src);
7167 effect(KILL cr);
7168 ins_cost(200);
7169 format %{ "MOV $dst.lo,$src.lo\n\t"
7170 "MOV $dst.hi,$src.hi" %}
7171 opcode(0xB8);
7172 ins_encode( LdImmL_Lo(dst, src), LdImmL_Hi(dst, src) );
7173 ins_pipe( ialu_reg_long_fat );
7174 %}
7175
7176 instruct loadConL0(eRegL dst, immL0 src, eFlagsReg cr) %{
7177 match(Set dst src);
7178 effect(KILL cr);
7179 ins_cost(150);
7180 format %{ "XOR $dst.lo,$dst.lo\n\t"
7181 "XOR $dst.hi,$dst.hi" %}
7182 opcode(0x33,0x33);
7183 ins_encode( RegReg_Lo(dst,dst), RegReg_Hi(dst, dst) );
7184 ins_pipe( ialu_reg_long );
7185 %}
7186
7187 // The instruction usage is guarded by predicate in operand immF().
7188 instruct loadConF(regF dst, immF src) %{
7189 match(Set dst src);
7190 ins_cost(125);
7191
7192 format %{ "FLD_S ST,$src\n\t"
7193 "FSTP $dst" %}
7194 opcode(0xD9, 0x00); /* D9 /0 */
7195 ins_encode(LdImmF(src), Pop_Reg_F(dst) );
7196 ins_pipe( fpu_reg_con );
7197 %}
7198
7199 // The instruction usage is guarded by predicate in operand immXF().
7200 instruct loadConX(regX dst, immXF con) %{
7201 match(Set dst con);
7202 ins_cost(125);
7203 format %{ "MOVSS $dst,[$con]" %}
7204 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x10), LdImmX(dst, con));
7205 ins_pipe( pipe_slow );
7206 %}
7207
7208 // The instruction usage is guarded by predicate in operand immXF0().
7209 instruct loadConX0(regX dst, immXF0 src) %{
7210 match(Set dst src);
7211 ins_cost(100);
7212 format %{ "XORPS $dst,$dst\t# float 0.0" %}
7213 ins_encode( Opcode(0x0F), Opcode(0x57), RegReg(dst,dst));
7214 ins_pipe( pipe_slow );
7215 %}
7216
7217 // The instruction usage is guarded by predicate in operand immD().
7218 instruct loadConD(regD dst, immD src) %{
7219 match(Set dst src);
7220 ins_cost(125);
7221
7222 format %{ "FLD_D ST,$src\n\t"
7223 "FSTP $dst" %}
7224 ins_encode(LdImmD(src), Pop_Reg_D(dst) );
7225 ins_pipe( fpu_reg_con );
7226 %}
7227
7228 // The instruction usage is guarded by predicate in operand immXD().
7229 instruct loadConXD(regXD dst, immXD con) %{
7230 match(Set dst con);
7231 ins_cost(125);
7232 format %{ "MOVSD $dst,[$con]" %}
7233 ins_encode(load_conXD(dst, con));
7234 ins_pipe( pipe_slow );
7235 %}
7236
7237 // The instruction usage is guarded by predicate in operand immXD0().
7238 instruct loadConXD0(regXD dst, immXD0 src) %{
7239 match(Set dst src);
7240 ins_cost(100);
7241 format %{ "XORPD $dst,$dst\t# double 0.0" %}
7242 ins_encode( Opcode(0x66), Opcode(0x0F), Opcode(0x57), RegReg(dst,dst));
7243 ins_pipe( pipe_slow );
7244 %}
7245
7246 // Load Stack Slot
7247 instruct loadSSI(eRegI dst, stackSlotI src) %{
7248 match(Set dst src);
7249 ins_cost(125);
7250
7251 format %{ "MOV $dst,$src" %}
7252 opcode(0x8B);
7253 ins_encode( OpcP, RegMem(dst,src));
7254 ins_pipe( ialu_reg_mem );
7255 %}
7256
7257 instruct loadSSL(eRegL dst, stackSlotL src) %{
7258 match(Set dst src);
7259
7260 ins_cost(200);
7261 format %{ "MOV $dst,$src.lo\n\t"
7262 "MOV $dst+4,$src.hi" %}
7263 opcode(0x8B, 0x8B);
7264 ins_encode( OpcP, RegMem( dst, src ), OpcS, RegMem_Hi( dst, src ) );
7265 ins_pipe( ialu_mem_long_reg );
7266 %}
7267
7268 // Load Stack Slot
7269 instruct loadSSP(eRegP dst, stackSlotP src) %{
7270 match(Set dst src);
7271 ins_cost(125);
7272
7273 format %{ "MOV $dst,$src" %}
7274 opcode(0x8B);
7275 ins_encode( OpcP, RegMem(dst,src));
7276 ins_pipe( ialu_reg_mem );
7277 %}
7278
7279 // Load Stack Slot
7280 instruct loadSSF(regF dst, stackSlotF src) %{
7281 match(Set dst src);
7282 ins_cost(125);
7283
7284 format %{ "FLD_S $src\n\t"
7285 "FSTP $dst" %}
7286 opcode(0xD9); /* D9 /0, FLD m32real */
7287 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
7288 Pop_Reg_F(dst) );
7289 ins_pipe( fpu_reg_mem );
7290 %}
7291
7292 // Load Stack Slot
7293 instruct loadSSD(regD dst, stackSlotD src) %{
7294 match(Set dst src);
7295 ins_cost(125);
7296
7297 format %{ "FLD_D $src\n\t"
7298 "FSTP $dst" %}
7299 opcode(0xDD); /* DD /0, FLD m64real */
7300 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
7301 Pop_Reg_D(dst) );
7302 ins_pipe( fpu_reg_mem );
7303 %}
7304
7305 // Prefetch instructions.
7306 // Must be safe to execute with invalid address (cannot fault).
7307
7308 instruct prefetchr0( memory mem ) %{
7309 predicate(UseSSE==0 && !VM_Version::supports_3dnow());
7310 match(PrefetchRead mem);
7311 ins_cost(0);
7312 size(0);
7313 format %{ "PREFETCHR (non-SSE is empty encoding)" %}
7314 ins_encode();
7315 ins_pipe(empty);
7316 %}
7317
7318 instruct prefetchr( memory mem ) %{
7319 predicate(UseSSE==0 && VM_Version::supports_3dnow() || ReadPrefetchInstr==3);
7320 match(PrefetchRead mem);
7321 ins_cost(100);
7322
7323 format %{ "PREFETCHR $mem\t! Prefetch into level 1 cache for read" %}
7324 opcode(0x0F, 0x0d); /* Opcode 0F 0d /0 */
7325 ins_encode(OpcP, OpcS, RMopc_Mem(0x00,mem));
7326 ins_pipe(ialu_mem);
7327 %}
7328
7329 instruct prefetchrNTA( memory mem ) %{
7330 predicate(UseSSE>=1 && ReadPrefetchInstr==0);
7331 match(PrefetchRead mem);
7332 ins_cost(100);
7333
7334 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for read" %}
7335 opcode(0x0F, 0x18); /* Opcode 0F 18 /0 */
7336 ins_encode(OpcP, OpcS, RMopc_Mem(0x00,mem));
7337 ins_pipe(ialu_mem);
7338 %}
7339
7340 instruct prefetchrT0( memory mem ) %{
7341 predicate(UseSSE>=1 && ReadPrefetchInstr==1);
7342 match(PrefetchRead mem);
7343 ins_cost(100);
7344
7345 format %{ "PREFETCHT0 $mem\t! Prefetch into L1 and L2 caches for read" %}
7346 opcode(0x0F, 0x18); /* Opcode 0F 18 /1 */
7347 ins_encode(OpcP, OpcS, RMopc_Mem(0x01,mem));
7348 ins_pipe(ialu_mem);
7349 %}
7350
7351 instruct prefetchrT2( memory mem ) %{
7352 predicate(UseSSE>=1 && ReadPrefetchInstr==2);
7353 match(PrefetchRead mem);
7354 ins_cost(100);
7355
7356 format %{ "PREFETCHT2 $mem\t! Prefetch into L2 cache for read" %}
7357 opcode(0x0F, 0x18); /* Opcode 0F 18 /3 */
7358 ins_encode(OpcP, OpcS, RMopc_Mem(0x03,mem));
7359 ins_pipe(ialu_mem);
7360 %}
7361
7362 instruct prefetchw0( memory mem ) %{
7363 predicate(UseSSE==0 && !VM_Version::supports_3dnow());
7364 match(PrefetchWrite mem);
7365 ins_cost(0);
7366 size(0);
7367 format %{ "Prefetch (non-SSE is empty encoding)" %}
7368 ins_encode();
7369 ins_pipe(empty);
7370 %}
7371
7372 instruct prefetchw( memory mem ) %{
7373 predicate(UseSSE==0 && VM_Version::supports_3dnow() || AllocatePrefetchInstr==3);
7374 match( PrefetchWrite mem );
7375 ins_cost(100);
7376
7377 format %{ "PREFETCHW $mem\t! Prefetch into L1 cache and mark modified" %}
7378 opcode(0x0F, 0x0D); /* Opcode 0F 0D /1 */
7379 ins_encode(OpcP, OpcS, RMopc_Mem(0x01,mem));
7380 ins_pipe(ialu_mem);
7381 %}
7382
7383 instruct prefetchwNTA( memory mem ) %{
7384 predicate(UseSSE>=1 && AllocatePrefetchInstr==0);
7385 match(PrefetchWrite mem);
7386 ins_cost(100);
7387
7388 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for write" %}
7389 opcode(0x0F, 0x18); /* Opcode 0F 18 /0 */
7390 ins_encode(OpcP, OpcS, RMopc_Mem(0x00,mem));
7391 ins_pipe(ialu_mem);
7392 %}
7393
7394 instruct prefetchwT0( memory mem ) %{
7395 predicate(UseSSE>=1 && AllocatePrefetchInstr==1);
7396 match(PrefetchWrite mem);
7397 ins_cost(100);
7398
7399 format %{ "PREFETCHT0 $mem\t! Prefetch into L1 and L2 caches for write" %}
7400 opcode(0x0F, 0x18); /* Opcode 0F 18 /1 */
7401 ins_encode(OpcP, OpcS, RMopc_Mem(0x01,mem));
7402 ins_pipe(ialu_mem);
7403 %}
7404
7405 instruct prefetchwT2( memory mem ) %{
7406 predicate(UseSSE>=1 && AllocatePrefetchInstr==2);
7407 match(PrefetchWrite mem);
7408 ins_cost(100);
7409
7410 format %{ "PREFETCHT2 $mem\t! Prefetch into L2 cache for write" %}
7411 opcode(0x0F, 0x18); /* Opcode 0F 18 /3 */
7412 ins_encode(OpcP, OpcS, RMopc_Mem(0x03,mem));
7413 ins_pipe(ialu_mem);
7414 %}
7415
7416 //----------Store Instructions-------------------------------------------------
7417
7418 // Store Byte
7419 instruct storeB(memory mem, xRegI src) %{
7420 match(Set mem (StoreB mem src));
7421
7422 ins_cost(125);
7423 format %{ "MOV8 $mem,$src" %}
7424 opcode(0x88);
7425 ins_encode( OpcP, RegMem( src, mem ) );
7426 ins_pipe( ialu_mem_reg );
7427 %}
7428
7429 // Store Char/Short
7430 instruct storeC(memory mem, eRegI src) %{
7431 match(Set mem (StoreC mem src));
7432
7433 ins_cost(125);
7434 format %{ "MOV16 $mem,$src" %}
7435 opcode(0x89, 0x66);
7436 ins_encode( OpcS, OpcP, RegMem( src, mem ) );
7437 ins_pipe( ialu_mem_reg );
7438 %}
7439
7440 // Store Integer
7441 instruct storeI(memory mem, eRegI src) %{
7442 match(Set mem (StoreI mem src));
7443
7444 ins_cost(125);
7445 format %{ "MOV $mem,$src" %}
7446 opcode(0x89);
7447 ins_encode( OpcP, RegMem( src, mem ) );
7448 ins_pipe( ialu_mem_reg );
7449 %}
7450
7451 // Store Long
7452 instruct storeL(long_memory mem, eRegL src) %{
7453 predicate(!((StoreLNode*)n)->require_atomic_access());
7454 match(Set mem (StoreL mem src));
7455
7456 ins_cost(200);
7457 format %{ "MOV $mem,$src.lo\n\t"
7458 "MOV $mem+4,$src.hi" %}
7459 opcode(0x89, 0x89);
7460 ins_encode( OpcP, RegMem( src, mem ), OpcS, RegMem_Hi( src, mem ) );
7461 ins_pipe( ialu_mem_long_reg );
7462 %}
7463
7464 // Volatile Store Long. Must be atomic, so move it into
7465 // the FP TOS and then do a 64-bit FIST. Has to probe the
7466 // target address before the store (for null-ptr checks)
7467 // so the memory operand is used twice in the encoding.
7468 instruct storeL_volatile(memory mem, stackSlotL src, eFlagsReg cr ) %{
7469 predicate(UseSSE<=1 && ((StoreLNode*)n)->require_atomic_access());
7470 match(Set mem (StoreL mem src));
7471 effect( KILL cr );
7472 ins_cost(400);
7473 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
7474 "FILD $src\n\t"
7475 "FISTp $mem\t # 64-bit atomic volatile long store" %}
7476 opcode(0x3B);
7477 ins_encode( OpcP, RegMem( EAX, mem ), enc_storeL_volatile(mem,src));
7478 ins_pipe( fpu_reg_mem );
7479 %}
7480
7481 instruct storeLX_volatile(memory mem, stackSlotL src, regXD tmp, eFlagsReg cr) %{
7482 predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access());
7483 match(Set mem (StoreL mem src));
7484 effect( TEMP tmp, KILL cr );
7485 ins_cost(380);
7486 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
7487 "MOVSD $tmp,$src\n\t"
7488 "MOVSD $mem,$tmp\t # 64-bit atomic volatile long store" %}
7489 opcode(0x3B);
7490 ins_encode( OpcP, RegMem( EAX, mem ), enc_storeLX_volatile(mem, src, tmp));
7491 ins_pipe( pipe_slow );
7492 %}
7493
7494 instruct storeLX_reg_volatile(memory mem, eRegL src, regXD tmp2, regXD tmp, eFlagsReg cr) %{
7495 predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access());
7496 match(Set mem (StoreL mem src));
7497 effect( TEMP tmp2 , TEMP tmp, KILL cr );
7498 ins_cost(360);
7499 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
7500 "MOVD $tmp,$src.lo\n\t"
7501 "MOVD $tmp2,$src.hi\n\t"
7502 "PUNPCKLDQ $tmp,$tmp2\n\t"
7503 "MOVSD $mem,$tmp\t # 64-bit atomic volatile long store" %}
7504 opcode(0x3B);
7505 ins_encode( OpcP, RegMem( EAX, mem ), enc_storeLX_reg_volatile(mem, src, tmp, tmp2));
7506 ins_pipe( pipe_slow );
7507 %}
7508
7509 // Store Pointer; for storing unknown oops and raw pointers
7510 instruct storeP(memory mem, anyRegP src) %{
7511 match(Set mem (StoreP mem src));
7512
7513 ins_cost(125);
7514 format %{ "MOV $mem,$src" %}
7515 opcode(0x89);
7516 ins_encode( OpcP, RegMem( src, mem ) );
7517 ins_pipe( ialu_mem_reg );
7518 %}
7519
7520 // Store Integer Immediate
7521 instruct storeImmI(memory mem, immI src) %{
7522 match(Set mem (StoreI mem src));
7523
7524 ins_cost(150);
7525 format %{ "MOV $mem,$src" %}
7526 opcode(0xC7); /* C7 /0 */
7527 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32( src ));
7528 ins_pipe( ialu_mem_imm );
7529 %}
7530
7531 // Store Short/Char Immediate
7532 instruct storeImmI16(memory mem, immI16 src) %{
7533 predicate(UseStoreImmI16);
7534 match(Set mem (StoreC mem src));
7535
7536 ins_cost(150);
7537 format %{ "MOV16 $mem,$src" %}
7538 opcode(0xC7); /* C7 /0 Same as 32 store immediate with prefix */
7539 ins_encode( SizePrefix, OpcP, RMopc_Mem(0x00,mem), Con16( src ));
7540 ins_pipe( ialu_mem_imm );
7541 %}
7542
7543 // Store Pointer Immediate; null pointers or constant oops that do not
7544 // need card-mark barriers.
7545 instruct storeImmP(memory mem, immP src) %{
7546 match(Set mem (StoreP mem src));
7547
7548 ins_cost(150);
7549 format %{ "MOV $mem,$src" %}
7550 opcode(0xC7); /* C7 /0 */
7551 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32( src ));
7552 ins_pipe( ialu_mem_imm );
7553 %}
7554
7555 // Store Byte Immediate
7556 instruct storeImmB(memory mem, immI8 src) %{
7557 match(Set mem (StoreB mem src));
7558
7559 ins_cost(150);
7560 format %{ "MOV8 $mem,$src" %}
7561 opcode(0xC6); /* C6 /0 */
7562 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con8or32( src ));
7563 ins_pipe( ialu_mem_imm );
7564 %}
7565
7566 // Store Aligned Packed Byte XMM register to memory
7567 instruct storeA8B(memory mem, regXD src) %{
7568 predicate(UseSSE>=1);
7569 match(Set mem (Store8B mem src));
7570 ins_cost(145);
7571 format %{ "MOVQ $mem,$src\t! packed8B" %}
7572 ins_encode( movq_st(mem, src));
7573 ins_pipe( pipe_slow );
7574 %}
7575
7576 // Store Aligned Packed Char/Short XMM register to memory
7577 instruct storeA4C(memory mem, regXD src) %{
7578 predicate(UseSSE>=1);
7579 match(Set mem (Store4C mem src));
7580 ins_cost(145);
7581 format %{ "MOVQ $mem,$src\t! packed4C" %}
7582 ins_encode( movq_st(mem, src));
7583 ins_pipe( pipe_slow );
7584 %}
7585
7586 // Store Aligned Packed Integer XMM register to memory
7587 instruct storeA2I(memory mem, regXD src) %{
7588 predicate(UseSSE>=1);
7589 match(Set mem (Store2I mem src));
7590 ins_cost(145);
7591 format %{ "MOVQ $mem,$src\t! packed2I" %}
7592 ins_encode( movq_st(mem, src));
7593 ins_pipe( pipe_slow );
7594 %}
7595
7596 // Store CMS card-mark Immediate
7597 instruct storeImmCM(memory mem, immI8 src) %{
7598 match(Set mem (StoreCM mem src));
7599
7600 ins_cost(150);
7601 format %{ "MOV8 $mem,$src\t! CMS card-mark imm0" %}
7602 opcode(0xC6); /* C6 /0 */
7603 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con8or32( src ));
7604 ins_pipe( ialu_mem_imm );
7605 %}
7606
7607 // Store Double
7608 instruct storeD( memory mem, regDPR1 src) %{
7609 predicate(UseSSE<=1);
7610 match(Set mem (StoreD mem src));
7611
7612 ins_cost(100);
7613 format %{ "FST_D $mem,$src" %}
7614 opcode(0xDD); /* DD /2 */
7615 ins_encode( enc_FP_store(mem,src) );
7616 ins_pipe( fpu_mem_reg );
7617 %}
7618
7619 // Store double does rounding on x86
7620 instruct storeD_rounded( memory mem, regDPR1 src) %{
7621 predicate(UseSSE<=1);
7622 match(Set mem (StoreD mem (RoundDouble src)));
7623
7624 ins_cost(100);
7625 format %{ "FST_D $mem,$src\t# round" %}
7626 opcode(0xDD); /* DD /2 */
7627 ins_encode( enc_FP_store(mem,src) );
7628 ins_pipe( fpu_mem_reg );
7629 %}
7630
7631 // Store XMM register to memory (double-precision floating points)
7632 // MOVSD instruction
7633 instruct storeXD(memory mem, regXD src) %{
7634 predicate(UseSSE>=2);
7635 match(Set mem (StoreD mem src));
7636 ins_cost(95);
7637 format %{ "MOVSD $mem,$src" %}
7638 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x11), RegMem(src, mem));
7639 ins_pipe( pipe_slow );
7640 %}
7641
7642 // Store XMM register to memory (single-precision floating point)
7643 // MOVSS instruction
7644 instruct storeX(memory mem, regX src) %{
7645 predicate(UseSSE>=1);
7646 match(Set mem (StoreF mem src));
7647 ins_cost(95);
7648 format %{ "MOVSS $mem,$src" %}
7649 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x11), RegMem(src, mem));
7650 ins_pipe( pipe_slow );
7651 %}
7652
7653 // Store Aligned Packed Single Float XMM register to memory
7654 instruct storeA2F(memory mem, regXD src) %{
7655 predicate(UseSSE>=1);
7656 match(Set mem (Store2F mem src));
7657 ins_cost(145);
7658 format %{ "MOVQ $mem,$src\t! packed2F" %}
7659 ins_encode( movq_st(mem, src));
7660 ins_pipe( pipe_slow );
7661 %}
7662
7663 // Store Float
7664 instruct storeF( memory mem, regFPR1 src) %{
7665 predicate(UseSSE==0);
7666 match(Set mem (StoreF mem src));
7667
7668 ins_cost(100);
7669 format %{ "FST_S $mem,$src" %}
7670 opcode(0xD9); /* D9 /2 */
7671 ins_encode( enc_FP_store(mem,src) );
7672 ins_pipe( fpu_mem_reg );
7673 %}
7674
7675 // Store Float does rounding on x86
7676 instruct storeF_rounded( memory mem, regFPR1 src) %{
7677 predicate(UseSSE==0);
7678 match(Set mem (StoreF mem (RoundFloat src)));
7679
7680 ins_cost(100);
7681 format %{ "FST_S $mem,$src\t# round" %}
7682 opcode(0xD9); /* D9 /2 */
7683 ins_encode( enc_FP_store(mem,src) );
7684 ins_pipe( fpu_mem_reg );
7685 %}
7686
7687 // Store Float does rounding on x86
7688 instruct storeF_Drounded( memory mem, regDPR1 src) %{
7689 predicate(UseSSE<=1);
7690 match(Set mem (StoreF mem (ConvD2F src)));
7691
7692 ins_cost(100);
7693 format %{ "FST_S $mem,$src\t# D-round" %}
7694 opcode(0xD9); /* D9 /2 */
7695 ins_encode( enc_FP_store(mem,src) );
7696 ins_pipe( fpu_mem_reg );
7697 %}
7698
7699 // Store immediate Float value (it is faster than store from FPU register)
7700 // The instruction usage is guarded by predicate in operand immF().
7701 instruct storeF_imm( memory mem, immF src) %{
7702 match(Set mem (StoreF mem src));
7703
7704 ins_cost(50);
7705 format %{ "MOV $mem,$src\t# store float" %}
7706 opcode(0xC7); /* C7 /0 */
7707 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32F_as_bits( src ));
7708 ins_pipe( ialu_mem_imm );
7709 %}
7710
7711 // Store immediate Float value (it is faster than store from XMM register)
7712 // The instruction usage is guarded by predicate in operand immXF().
7713 instruct storeX_imm( memory mem, immXF src) %{
7714 match(Set mem (StoreF mem src));
7715
7716 ins_cost(50);
7717 format %{ "MOV $mem,$src\t# store float" %}
7718 opcode(0xC7); /* C7 /0 */
7719 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32XF_as_bits( src ));
7720 ins_pipe( ialu_mem_imm );
7721 %}
7722
7723 // Store Integer to stack slot
7724 instruct storeSSI(stackSlotI dst, eRegI src) %{
7725 match(Set dst src);
7726
7727 ins_cost(100);
7728 format %{ "MOV $dst,$src" %}
7729 opcode(0x89);
7730 ins_encode( OpcPRegSS( dst, src ) );
7731 ins_pipe( ialu_mem_reg );
7732 %}
7733
7734 // Store Integer to stack slot
7735 instruct storeSSP(stackSlotP dst, eRegP src) %{
7736 match(Set dst src);
7737
7738 ins_cost(100);
7739 format %{ "MOV $dst,$src" %}
7740 opcode(0x89);
7741 ins_encode( OpcPRegSS( dst, src ) );
7742 ins_pipe( ialu_mem_reg );
7743 %}
7744
7745 // Store Long to stack slot
7746 instruct storeSSL(stackSlotL dst, eRegL src) %{
7747 match(Set dst src);
7748
7749 ins_cost(200);
7750 format %{ "MOV $dst,$src.lo\n\t"
7751 "MOV $dst+4,$src.hi" %}
7752 opcode(0x89, 0x89);
7753 ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) );
7754 ins_pipe( ialu_mem_long_reg );
7755 %}
7756
7757 //----------MemBar Instructions-----------------------------------------------
7758 // Memory barrier flavors
7759
7760 instruct membar_acquire() %{
7761 match(MemBarAcquire);
7762 ins_cost(400);
7763
7764 size(0);
7765 format %{ "MEMBAR-acquire ! (empty encoding)" %}
7766 ins_encode();
7767 ins_pipe(empty);
7768 %}
7769
7770 instruct membar_acquire_lock() %{
7771 match(MemBarAcquire);
7772 predicate(Matcher::prior_fast_lock(n));
7773 ins_cost(0);
7774
7775 size(0);
7776 format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)" %}
7777 ins_encode( );
7778 ins_pipe(empty);
7779 %}
7780
7781 instruct membar_release() %{
7782 match(MemBarRelease);
7783 ins_cost(400);
7784
7785 size(0);
7786 format %{ "MEMBAR-release ! (empty encoding)" %}
7787 ins_encode( );
7788 ins_pipe(empty);
7789 %}
7790
7791 instruct membar_release_lock() %{
7792 match(MemBarRelease);
7793 predicate(Matcher::post_fast_unlock(n));
7794 ins_cost(0);
7795
7796 size(0);
7797 format %{ "MEMBAR-release (a FastUnlock follows so empty encoding)" %}
7798 ins_encode( );
7799 ins_pipe(empty);
7800 %}
7801
7802 instruct membar_volatile(eFlagsReg cr) %{
7803 match(MemBarVolatile);
7804 effect(KILL cr);
7805 ins_cost(400);
7806
7807 format %{
7808 $$template
7809 if (os::is_MP()) {
7810 $$emit$$"LOCK ADDL [ESP + #0], 0\t! membar_volatile"
7811 } else {
7812 $$emit$$"MEMBAR-volatile ! (empty encoding)"
7813 }
7814 %}
7815 ins_encode %{
7816 __ membar(Assembler::StoreLoad);
7817 %}
7818 ins_pipe(pipe_slow);
7819 %}
7820
7821 instruct unnecessary_membar_volatile() %{
7822 match(MemBarVolatile);
7823 predicate(Matcher::post_store_load_barrier(n));
7824 ins_cost(0);
7825
7826 size(0);
7827 format %{ "MEMBAR-volatile (unnecessary so empty encoding)" %}
7828 ins_encode( );
7829 ins_pipe(empty);
7830 %}
7831
7832 //----------Move Instructions--------------------------------------------------
7833 instruct castX2P(eAXRegP dst, eAXRegI src) %{
7834 match(Set dst (CastX2P src));
7835 format %{ "# X2P $dst, $src" %}
7836 ins_encode( /*empty encoding*/ );
7837 ins_cost(0);
7838 ins_pipe(empty);
7839 %}
7840
7841 instruct castP2X(eRegI dst, eRegP src ) %{
7842 match(Set dst (CastP2X src));
7843 ins_cost(50);
7844 format %{ "MOV $dst, $src\t# CastP2X" %}
7845 ins_encode( enc_Copy( dst, src) );
7846 ins_pipe( ialu_reg_reg );
7847 %}
7848
7849 //----------Conditional Move---------------------------------------------------
7850 // Conditional move
7851 instruct cmovI_reg(eRegI dst, eRegI src, eFlagsReg cr, cmpOp cop ) %{
7852 predicate(VM_Version::supports_cmov() );
7853 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7854 ins_cost(200);
7855 format %{ "CMOV$cop $dst,$src" %}
7856 opcode(0x0F,0x40);
7857 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7858 ins_pipe( pipe_cmov_reg );
7859 %}
7860
7861 instruct cmovI_regU( cmpOpU cop, eFlagsRegU cr, eRegI dst, eRegI src ) %{
7862 predicate(VM_Version::supports_cmov() );
7863 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7864 ins_cost(200);
7865 format %{ "CMOV$cop $dst,$src" %}
7866 opcode(0x0F,0x40);
7867 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7868 ins_pipe( pipe_cmov_reg );
7869 %}
7870
7871 instruct cmovI_regUCF( cmpOpUCF cop, eFlagsRegUCF cr, eRegI dst, eRegI src ) %{
7872 predicate(VM_Version::supports_cmov() );
7873 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7874 ins_cost(200);
7875 expand %{
7876 cmovI_regU(cop, cr, dst, src);
7877 %}
7878 %}
7879
7880 // Conditional move
7881 instruct cmovI_mem(cmpOp cop, eFlagsReg cr, eRegI dst, memory src) %{
7882 predicate(VM_Version::supports_cmov() );
7883 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7884 ins_cost(250);
7885 format %{ "CMOV$cop $dst,$src" %}
7886 opcode(0x0F,0x40);
7887 ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7888 ins_pipe( pipe_cmov_mem );
7889 %}
7890
7891 // Conditional move
7892 instruct cmovI_memU(cmpOpU cop, eFlagsRegU cr, eRegI dst, memory src) %{
7893 predicate(VM_Version::supports_cmov() );
7894 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7895 ins_cost(250);
7896 format %{ "CMOV$cop $dst,$src" %}
7897 opcode(0x0F,0x40);
7898 ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7899 ins_pipe( pipe_cmov_mem );
7900 %}
7901
7902 instruct cmovI_memUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegI dst, memory src) %{
7903 predicate(VM_Version::supports_cmov() );
7904 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7905 ins_cost(250);
7906 expand %{
7907 cmovI_memU(cop, cr, dst, src);
7908 %}
7909 %}
7910
7911 // Conditional move
7912 instruct cmovP_reg(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{
7913 predicate(VM_Version::supports_cmov() );
7914 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7915 ins_cost(200);
7916 format %{ "CMOV$cop $dst,$src\t# ptr" %}
7917 opcode(0x0F,0x40);
7918 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7919 ins_pipe( pipe_cmov_reg );
7920 %}
7921
7922 // Conditional move (non-P6 version)
7923 // Note: a CMoveP is generated for stubs and native wrappers
7924 // regardless of whether we are on a P6, so we
7925 // emulate a cmov here
7926 instruct cmovP_reg_nonP6(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{
7927 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7928 ins_cost(300);
7929 format %{ "Jn$cop skip\n\t"
7930 "MOV $dst,$src\t# pointer\n"
7931 "skip:" %}
7932 opcode(0x8b);
7933 ins_encode( enc_cmov_branch(cop, 0x2), OpcP, RegReg(dst, src));
7934 ins_pipe( pipe_cmov_reg );
7935 %}
7936
7937 // Conditional move
7938 instruct cmovP_regU(cmpOpU cop, eFlagsRegU cr, eRegP dst, eRegP src ) %{
7939 predicate(VM_Version::supports_cmov() );
7940 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7941 ins_cost(200);
7942 format %{ "CMOV$cop $dst,$src\t# ptr" %}
7943 opcode(0x0F,0x40);
7944 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7945 ins_pipe( pipe_cmov_reg );
7946 %}
7947
7948 instruct cmovP_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegP dst, eRegP src ) %{
7949 predicate(VM_Version::supports_cmov() );
7950 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7951 ins_cost(200);
7952 expand %{
7953 cmovP_regU(cop, cr, dst, src);
7954 %}
7955 %}
7956
7957 // DISABLED: Requires the ADLC to emit a bottom_type call that
7958 // correctly meets the two pointer arguments; one is an incoming
7959 // register but the other is a memory operand. ALSO appears to
7960 // be buggy with implicit null checks.
7961 //
7962 //// Conditional move
7963 //instruct cmovP_mem(cmpOp cop, eFlagsReg cr, eRegP dst, memory src) %{
7964 // predicate(VM_Version::supports_cmov() );
7965 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
7966 // ins_cost(250);
7967 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
7968 // opcode(0x0F,0x40);
7969 // ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7970 // ins_pipe( pipe_cmov_mem );
7971 //%}
7972 //
7973 //// Conditional move
7974 //instruct cmovP_memU(cmpOpU cop, eFlagsRegU cr, eRegP dst, memory src) %{
7975 // predicate(VM_Version::supports_cmov() );
7976 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
7977 // ins_cost(250);
7978 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
7979 // opcode(0x0F,0x40);
7980 // ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7981 // ins_pipe( pipe_cmov_mem );
7982 //%}
7983
7984 // Conditional move
7985 instruct fcmovD_regU(cmpOp_fcmov cop, eFlagsRegU cr, regDPR1 dst, regD src) %{
7986 predicate(UseSSE<=1);
7987 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7988 ins_cost(200);
7989 format %{ "FCMOV$cop $dst,$src\t# double" %}
7990 opcode(0xDA);
7991 ins_encode( enc_cmov_d(cop,src) );
7992 ins_pipe( pipe_cmovD_reg );
7993 %}
7994
7995 // Conditional move
7996 instruct fcmovF_regU(cmpOp_fcmov cop, eFlagsRegU cr, regFPR1 dst, regF src) %{
7997 predicate(UseSSE==0);
7998 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7999 ins_cost(200);
8000 format %{ "FCMOV$cop $dst,$src\t# float" %}
8001 opcode(0xDA);
8002 ins_encode( enc_cmov_d(cop,src) );
8003 ins_pipe( pipe_cmovD_reg );
8004 %}
8005
8006 // Float CMOV on Intel doesn't handle *signed* compares, only unsigned.
8007 instruct fcmovD_regS(cmpOp cop, eFlagsReg cr, regD dst, regD src) %{
8008 predicate(UseSSE<=1);
8009 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
8010 ins_cost(200);
8011 format %{ "Jn$cop skip\n\t"
8012 "MOV $dst,$src\t# double\n"
8013 "skip:" %}
8014 opcode (0xdd, 0x3); /* DD D8+i or DD /3 */
8015 ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_D(src), OpcP, RegOpc(dst) );
8016 ins_pipe( pipe_cmovD_reg );
8017 %}
8018
8019 // Float CMOV on Intel doesn't handle *signed* compares, only unsigned.
8020 instruct fcmovF_regS(cmpOp cop, eFlagsReg cr, regF dst, regF src) %{
8021 predicate(UseSSE==0);
8022 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
8023 ins_cost(200);
8024 format %{ "Jn$cop skip\n\t"
8025 "MOV $dst,$src\t# float\n"
8026 "skip:" %}
8027 opcode (0xdd, 0x3); /* DD D8+i or DD /3 */
8028 ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_F(src), OpcP, RegOpc(dst) );
8029 ins_pipe( pipe_cmovD_reg );
8030 %}
8031
8032 // No CMOVE with SSE/SSE2
8033 instruct fcmovX_regS(cmpOp cop, eFlagsReg cr, regX dst, regX src) %{
8034 predicate (UseSSE>=1);
8035 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
8036 ins_cost(200);
8037 format %{ "Jn$cop skip\n\t"
8038 "MOVSS $dst,$src\t# float\n"
8039 "skip:" %}
8040 ins_encode %{
8041 Label skip;
8042 // Invert sense of branch from sense of CMOV
8043 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
8044 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
8045 __ bind(skip);
8046 %}
8047 ins_pipe( pipe_slow );
8048 %}
8049
8050 // No CMOVE with SSE/SSE2
8051 instruct fcmovXD_regS(cmpOp cop, eFlagsReg cr, regXD dst, regXD src) %{
8052 predicate (UseSSE>=2);
8053 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
8054 ins_cost(200);
8055 format %{ "Jn$cop skip\n\t"
8056 "MOVSD $dst,$src\t# float\n"
8057 "skip:" %}
8058 ins_encode %{
8059 Label skip;
8060 // Invert sense of branch from sense of CMOV
8061 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
8062 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
8063 __ bind(skip);
8064 %}
8065 ins_pipe( pipe_slow );
8066 %}
8067
8068 // unsigned version
8069 instruct fcmovX_regU(cmpOpU cop, eFlagsRegU cr, regX dst, regX src) %{
8070 predicate (UseSSE>=1);
8071 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
8072 ins_cost(200);
8073 format %{ "Jn$cop skip\n\t"
8074 "MOVSS $dst,$src\t# float\n"
8075 "skip:" %}
8076 ins_encode %{
8077 Label skip;
8078 // Invert sense of branch from sense of CMOV
8079 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
8080 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
8081 __ bind(skip);
8082 %}
8083 ins_pipe( pipe_slow );
8084 %}
8085
8086 instruct fcmovX_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, regX dst, regX src) %{
8087 predicate (UseSSE>=1);
8088 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
8089 ins_cost(200);
8090 expand %{
8091 fcmovX_regU(cop, cr, dst, src);
8092 %}
8093 %}
8094
8095 // unsigned version
8096 instruct fcmovXD_regU(cmpOpU cop, eFlagsRegU cr, regXD dst, regXD src) %{
8097 predicate (UseSSE>=2);
8098 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
8099 ins_cost(200);
8100 format %{ "Jn$cop skip\n\t"
8101 "MOVSD $dst,$src\t# float\n"
8102 "skip:" %}
8103 ins_encode %{
8104 Label skip;
8105 // Invert sense of branch from sense of CMOV
8106 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
8107 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
8108 __ bind(skip);
8109 %}
8110 ins_pipe( pipe_slow );
8111 %}
8112
8113 instruct fcmovXD_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, regXD dst, regXD src) %{
8114 predicate (UseSSE>=2);
8115 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
8116 ins_cost(200);
8117 expand %{
8118 fcmovXD_regU(cop, cr, dst, src);
8119 %}
8120 %}
8121
8122 instruct cmovL_reg(cmpOp cop, eFlagsReg cr, eRegL dst, eRegL src) %{
8123 predicate(VM_Version::supports_cmov() );
8124 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
8125 ins_cost(200);
8126 format %{ "CMOV$cop $dst.lo,$src.lo\n\t"
8127 "CMOV$cop $dst.hi,$src.hi" %}
8128 opcode(0x0F,0x40);
8129 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) );
8130 ins_pipe( pipe_cmov_reg_long );
8131 %}
8132
8133 instruct cmovL_regU(cmpOpU cop, eFlagsRegU cr, eRegL dst, eRegL src) %{
8134 predicate(VM_Version::supports_cmov() );
8135 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
8136 ins_cost(200);
8137 format %{ "CMOV$cop $dst.lo,$src.lo\n\t"
8138 "CMOV$cop $dst.hi,$src.hi" %}
8139 opcode(0x0F,0x40);
8140 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) );
8141 ins_pipe( pipe_cmov_reg_long );
8142 %}
8143
8144 instruct cmovL_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegL dst, eRegL src) %{
8145 predicate(VM_Version::supports_cmov() );
8146 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
8147 ins_cost(200);
8148 expand %{
8149 cmovL_regU(cop, cr, dst, src);
8150 %}
8151 %}
8152
8153 //----------Arithmetic Instructions--------------------------------------------
8154 //----------Addition Instructions----------------------------------------------
8155 // Integer Addition Instructions
8156 instruct addI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
8157 match(Set dst (AddI dst src));
8158 effect(KILL cr);
8159
8160 size(2);
8161 format %{ "ADD $dst,$src" %}
8162 opcode(0x03);
8163 ins_encode( OpcP, RegReg( dst, src) );
8164 ins_pipe( ialu_reg_reg );
8165 %}
8166
8167 instruct addI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{
8168 match(Set dst (AddI dst src));
8169 effect(KILL cr);
8170
8171 format %{ "ADD $dst,$src" %}
8172 opcode(0x81, 0x00); /* /0 id */
8173 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8174 ins_pipe( ialu_reg );
8175 %}
8176
8177 instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
8178 predicate(UseIncDec);
8179 match(Set dst (AddI dst src));
8180 effect(KILL cr);
8181
8182 size(1);
8183 format %{ "INC $dst" %}
8184 opcode(0x40); /* */
8185 ins_encode( Opc_plus( primary, dst ) );
8186 ins_pipe( ialu_reg );
8187 %}
8188
8189 instruct leaI_eReg_immI(eRegI dst, eRegI src0, immI src1) %{
8190 match(Set dst (AddI src0 src1));
8191 ins_cost(110);
8192
8193 format %{ "LEA $dst,[$src0 + $src1]" %}
8194 opcode(0x8D); /* 0x8D /r */
8195 ins_encode( OpcP, RegLea( dst, src0, src1 ) );
8196 ins_pipe( ialu_reg_reg );
8197 %}
8198
8199 instruct leaP_eReg_immI(eRegP dst, eRegP src0, immI src1) %{
8200 match(Set dst (AddP src0 src1));
8201 ins_cost(110);
8202
8203 format %{ "LEA $dst,[$src0 + $src1]\t# ptr" %}
8204 opcode(0x8D); /* 0x8D /r */
8205 ins_encode( OpcP, RegLea( dst, src0, src1 ) );
8206 ins_pipe( ialu_reg_reg );
8207 %}
8208
8209 instruct decI_eReg(eRegI dst, immI_M1 src, eFlagsReg cr) %{
8210 predicate(UseIncDec);
8211 match(Set dst (AddI dst src));
8212 effect(KILL cr);
8213
8214 size(1);
8215 format %{ "DEC $dst" %}
8216 opcode(0x48); /* */
8217 ins_encode( Opc_plus( primary, dst ) );
8218 ins_pipe( ialu_reg );
8219 %}
8220
8221 instruct addP_eReg(eRegP dst, eRegI src, eFlagsReg cr) %{
8222 match(Set dst (AddP dst src));
8223 effect(KILL cr);
8224
8225 size(2);
8226 format %{ "ADD $dst,$src" %}
8227 opcode(0x03);
8228 ins_encode( OpcP, RegReg( dst, src) );
8229 ins_pipe( ialu_reg_reg );
8230 %}
8231
8232 instruct addP_eReg_imm(eRegP dst, immI src, eFlagsReg cr) %{
8233 match(Set dst (AddP dst src));
8234 effect(KILL cr);
8235
8236 format %{ "ADD $dst,$src" %}
8237 opcode(0x81,0x00); /* Opcode 81 /0 id */
8238 // ins_encode( RegImm( dst, src) );
8239 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8240 ins_pipe( ialu_reg );
8241 %}
8242
8243 instruct addI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{
8244 match(Set dst (AddI dst (LoadI src)));
8245 effect(KILL cr);
8246
8247 ins_cost(125);
8248 format %{ "ADD $dst,$src" %}
8249 opcode(0x03);
8250 ins_encode( OpcP, RegMem( dst, src) );
8251 ins_pipe( ialu_reg_mem );
8252 %}
8253
8254 instruct addI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{
8255 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
8256 effect(KILL cr);
8257
8258 ins_cost(150);
8259 format %{ "ADD $dst,$src" %}
8260 opcode(0x01); /* Opcode 01 /r */
8261 ins_encode( OpcP, RegMem( src, dst ) );
8262 ins_pipe( ialu_mem_reg );
8263 %}
8264
8265 // Add Memory with Immediate
8266 instruct addI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
8267 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
8268 effect(KILL cr);
8269
8270 ins_cost(125);
8271 format %{ "ADD $dst,$src" %}
8272 opcode(0x81); /* Opcode 81 /0 id */
8273 ins_encode( OpcSE( src ), RMopc_Mem(0x00,dst), Con8or32( src ) );
8274 ins_pipe( ialu_mem_imm );
8275 %}
8276
8277 instruct incI_mem(memory dst, immI1 src, eFlagsReg cr) %{
8278 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
8279 effect(KILL cr);
8280
8281 ins_cost(125);
8282 format %{ "INC $dst" %}
8283 opcode(0xFF); /* Opcode FF /0 */
8284 ins_encode( OpcP, RMopc_Mem(0x00,dst));
8285 ins_pipe( ialu_mem_imm );
8286 %}
8287
8288 instruct decI_mem(memory dst, immI_M1 src, eFlagsReg cr) %{
8289 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
8290 effect(KILL cr);
8291
8292 ins_cost(125);
8293 format %{ "DEC $dst" %}
8294 opcode(0xFF); /* Opcode FF /1 */
8295 ins_encode( OpcP, RMopc_Mem(0x01,dst));
8296 ins_pipe( ialu_mem_imm );
8297 %}
8298
8299
8300 instruct checkCastPP( eRegP dst ) %{
8301 match(Set dst (CheckCastPP dst));
8302
8303 size(0);
8304 format %{ "#checkcastPP of $dst" %}
8305 ins_encode( /*empty encoding*/ );
8306 ins_pipe( empty );
8307 %}
8308
8309 instruct castPP( eRegP dst ) %{
8310 match(Set dst (CastPP dst));
8311 format %{ "#castPP of $dst" %}
8312 ins_encode( /*empty encoding*/ );
8313 ins_pipe( empty );
8314 %}
8315
8316 instruct castII( eRegI dst ) %{
8317 match(Set dst (CastII dst));
8318 format %{ "#castII of $dst" %}
8319 ins_encode( /*empty encoding*/ );
8320 ins_cost(0);
8321 ins_pipe( empty );
8322 %}
8323
8324
8325 // Load-locked - same as a regular pointer load when used with compare-swap
8326 instruct loadPLocked(eRegP dst, memory mem) %{
8327 match(Set dst (LoadPLocked mem));
8328
8329 ins_cost(125);
8330 format %{ "MOV $dst,$mem\t# Load ptr. locked" %}
8331 opcode(0x8B);
8332 ins_encode( OpcP, RegMem(dst,mem));
8333 ins_pipe( ialu_reg_mem );
8334 %}
8335
8336 // LoadLong-locked - same as a volatile long load when used with compare-swap
8337 instruct loadLLocked(stackSlotL dst, load_long_memory mem) %{
8338 predicate(UseSSE<=1);
8339 match(Set dst (LoadLLocked mem));
8340
8341 ins_cost(200);
8342 format %{ "FILD $mem\t# Atomic volatile long load\n\t"
8343 "FISTp $dst" %}
8344 ins_encode(enc_loadL_volatile(mem,dst));
8345 ins_pipe( fpu_reg_mem );
8346 %}
8347
8348 instruct loadLX_Locked(stackSlotL dst, load_long_memory mem, regXD tmp) %{
8349 predicate(UseSSE>=2);
8350 match(Set dst (LoadLLocked mem));
8351 effect(TEMP tmp);
8352 ins_cost(180);
8353 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
8354 "MOVSD $dst,$tmp" %}
8355 ins_encode(enc_loadLX_volatile(mem, dst, tmp));
8356 ins_pipe( pipe_slow );
8357 %}
8358
8359 instruct loadLX_reg_Locked(eRegL dst, load_long_memory mem, regXD tmp) %{
8360 predicate(UseSSE>=2);
8361 match(Set dst (LoadLLocked mem));
8362 effect(TEMP tmp);
8363 ins_cost(160);
8364 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
8365 "MOVD $dst.lo,$tmp\n\t"
8366 "PSRLQ $tmp,32\n\t"
8367 "MOVD $dst.hi,$tmp" %}
8368 ins_encode(enc_loadLX_reg_volatile(mem, dst, tmp));
8369 ins_pipe( pipe_slow );
8370 %}
8371
8372 // Conditional-store of the updated heap-top.
8373 // Used during allocation of the shared heap.
8374 // Sets flags (EQ) on success. Implemented with a CMPXCHG on Intel.
8375 instruct storePConditional( memory heap_top_ptr, eAXRegP oldval, eRegP newval, eFlagsReg cr ) %{
8376 match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval)));
8377 // EAX is killed if there is contention, but then it's also unused.
8378 // In the common case of no contention, EAX holds the new oop address.
8379 format %{ "CMPXCHG $heap_top_ptr,$newval\t# If EAX==$heap_top_ptr Then store $newval into $heap_top_ptr" %}
8380 ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval,heap_top_ptr) );
8381 ins_pipe( pipe_cmpxchg );
8382 %}
8383
8384 // Conditional-store of an int value.
8385 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG on Intel.
8386 instruct storeIConditional( memory mem, eAXRegI oldval, eRegI newval, eFlagsReg cr ) %{
8387 match(Set cr (StoreIConditional mem (Binary oldval newval)));
8388 effect(KILL oldval);
8389 format %{ "CMPXCHG $mem,$newval\t# If EAX==$mem Then store $newval into $mem" %}
8390 ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval, mem) );
8391 ins_pipe( pipe_cmpxchg );
8392 %}
8393
8394 // Conditional-store of a long value.
8395 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG8 on Intel.
8396 instruct storeLConditional( memory mem, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{
8397 match(Set cr (StoreLConditional mem (Binary oldval newval)));
8398 effect(KILL oldval);
8399 format %{ "XCHG EBX,ECX\t# correct order for CMPXCHG8 instruction\n\t"
8400 "CMPXCHG8 $mem,ECX:EBX\t# If EDX:EAX==$mem Then store ECX:EBX into $mem\n\t"
8401 "XCHG EBX,ECX"
8402 %}
8403 ins_encode %{
8404 // Note: we need to swap rbx, and rcx before and after the
8405 // cmpxchg8 instruction because the instruction uses
8406 // rcx as the high order word of the new value to store but
8407 // our register encoding uses rbx.
8408 __ xchgl(as_Register(EBX_enc), as_Register(ECX_enc));
8409 if( os::is_MP() )
8410 __ lock();
8411 __ cmpxchg8($mem$$Address);
8412 __ xchgl(as_Register(EBX_enc), as_Register(ECX_enc));
8413 %}
8414 ins_pipe( pipe_cmpxchg );
8415 %}
8416
8417 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
8418
8419 instruct compareAndSwapL( eRegI res, eSIRegP mem_ptr, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{
8420 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
8421 effect(KILL cr, KILL oldval);
8422 format %{ "CMPXCHG8 [$mem_ptr],$newval\t# If EDX:EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
8423 "MOV $res,0\n\t"
8424 "JNE,s fail\n\t"
8425 "MOV $res,1\n"
8426 "fail:" %}
8427 ins_encode( enc_cmpxchg8(mem_ptr),
8428 enc_flags_ne_to_boolean(res) );
8429 ins_pipe( pipe_cmpxchg );
8430 %}
8431
8432 instruct compareAndSwapP( eRegI res, pRegP mem_ptr, eAXRegP oldval, eCXRegP newval, eFlagsReg cr) %{
8433 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
8434 effect(KILL cr, KILL oldval);
8435 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
8436 "MOV $res,0\n\t"
8437 "JNE,s fail\n\t"
8438 "MOV $res,1\n"
8439 "fail:" %}
8440 ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) );
8441 ins_pipe( pipe_cmpxchg );
8442 %}
8443
8444 instruct compareAndSwapI( eRegI res, pRegP mem_ptr, eAXRegI oldval, eCXRegI newval, eFlagsReg cr) %{
8445 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
8446 effect(KILL cr, KILL oldval);
8447 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
8448 "MOV $res,0\n\t"
8449 "JNE,s fail\n\t"
8450 "MOV $res,1\n"
8451 "fail:" %}
8452 ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) );
8453 ins_pipe( pipe_cmpxchg );
8454 %}
8455
8456 //----------Subtraction Instructions-------------------------------------------
8457 // Integer Subtraction Instructions
8458 instruct subI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
8459 match(Set dst (SubI dst src));
8460 effect(KILL cr);
8461
8462 size(2);
8463 format %{ "SUB $dst,$src" %}
8464 opcode(0x2B);
8465 ins_encode( OpcP, RegReg( dst, src) );
8466 ins_pipe( ialu_reg_reg );
8467 %}
8468
8469 instruct subI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{
8470 match(Set dst (SubI dst src));
8471 effect(KILL cr);
8472
8473 format %{ "SUB $dst,$src" %}
8474 opcode(0x81,0x05); /* Opcode 81 /5 */
8475 // ins_encode( RegImm( dst, src) );
8476 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8477 ins_pipe( ialu_reg );
8478 %}
8479
8480 instruct subI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{
8481 match(Set dst (SubI dst (LoadI src)));
8482 effect(KILL cr);
8483
8484 ins_cost(125);
8485 format %{ "SUB $dst,$src" %}
8486 opcode(0x2B);
8487 ins_encode( OpcP, RegMem( dst, src) );
8488 ins_pipe( ialu_reg_mem );
8489 %}
8490
8491 instruct subI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{
8492 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
8493 effect(KILL cr);
8494
8495 ins_cost(150);
8496 format %{ "SUB $dst,$src" %}
8497 opcode(0x29); /* Opcode 29 /r */
8498 ins_encode( OpcP, RegMem( src, dst ) );
8499 ins_pipe( ialu_mem_reg );
8500 %}
8501
8502 // Subtract from a pointer
8503 instruct subP_eReg(eRegP dst, eRegI src, immI0 zero, eFlagsReg cr) %{
8504 match(Set dst (AddP dst (SubI zero src)));
8505 effect(KILL cr);
8506
8507 size(2);
8508 format %{ "SUB $dst,$src" %}
8509 opcode(0x2B);
8510 ins_encode( OpcP, RegReg( dst, src) );
8511 ins_pipe( ialu_reg_reg );
8512 %}
8513
8514 instruct negI_eReg(eRegI dst, immI0 zero, eFlagsReg cr) %{
8515 match(Set dst (SubI zero dst));
8516 effect(KILL cr);
8517
8518 size(2);
8519 format %{ "NEG $dst" %}
8520 opcode(0xF7,0x03); // Opcode F7 /3
8521 ins_encode( OpcP, RegOpc( dst ) );
8522 ins_pipe( ialu_reg );
8523 %}
8524
8525
8526 //----------Multiplication/Division Instructions-------------------------------
8527 // Integer Multiplication Instructions
8528 // Multiply Register
8529 instruct mulI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
8530 match(Set dst (MulI dst src));
8531 effect(KILL cr);
8532
8533 size(3);
8534 ins_cost(300);
8535 format %{ "IMUL $dst,$src" %}
8536 opcode(0xAF, 0x0F);
8537 ins_encode( OpcS, OpcP, RegReg( dst, src) );
8538 ins_pipe( ialu_reg_reg_alu0 );
8539 %}
8540
8541 // Multiply 32-bit Immediate
8542 instruct mulI_eReg_imm(eRegI dst, eRegI src, immI imm, eFlagsReg cr) %{
8543 match(Set dst (MulI src imm));
8544 effect(KILL cr);
8545
8546 ins_cost(300);
8547 format %{ "IMUL $dst,$src,$imm" %}
8548 opcode(0x69); /* 69 /r id */
8549 ins_encode( OpcSE(imm), RegReg( dst, src ), Con8or32( imm ) );
8550 ins_pipe( ialu_reg_reg_alu0 );
8551 %}
8552
8553 instruct loadConL_low_only(eADXRegL_low_only dst, immL32 src, eFlagsReg cr) %{
8554 match(Set dst src);
8555 effect(KILL cr);
8556
8557 // Note that this is artificially increased to make it more expensive than loadConL
8558 ins_cost(250);
8559 format %{ "MOV EAX,$src\t// low word only" %}
8560 opcode(0xB8);
8561 ins_encode( LdImmL_Lo(dst, src) );
8562 ins_pipe( ialu_reg_fat );
8563 %}
8564
8565 // Multiply by 32-bit Immediate, taking the shifted high order results
8566 // (special case for shift by 32)
8567 instruct mulI_imm_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32 cnt, eFlagsReg cr) %{
8568 match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt)));
8569 predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL &&
8570 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint &&
8571 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint );
8572 effect(USE src1, KILL cr);
8573
8574 // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only
8575 ins_cost(0*100 + 1*400 - 150);
8576 format %{ "IMUL EDX:EAX,$src1" %}
8577 ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) );
8578 ins_pipe( pipe_slow );
8579 %}
8580
8581 // Multiply by 32-bit Immediate, taking the shifted high order results
8582 instruct mulI_imm_RShift_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr) %{
8583 match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt)));
8584 predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL &&
8585 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint &&
8586 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint );
8587 effect(USE src1, KILL cr);
8588
8589 // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only
8590 ins_cost(1*100 + 1*400 - 150);
8591 format %{ "IMUL EDX:EAX,$src1\n\t"
8592 "SAR EDX,$cnt-32" %}
8593 ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) );
8594 ins_pipe( pipe_slow );
8595 %}
8596
8597 // Multiply Memory 32-bit Immediate
8598 instruct mulI_mem_imm(eRegI dst, memory src, immI imm, eFlagsReg cr) %{
8599 match(Set dst (MulI (LoadI src) imm));
8600 effect(KILL cr);
8601
8602 ins_cost(300);
8603 format %{ "IMUL $dst,$src,$imm" %}
8604 opcode(0x69); /* 69 /r id */
8605 ins_encode( OpcSE(imm), RegMem( dst, src ), Con8or32( imm ) );
8606 ins_pipe( ialu_reg_mem_alu0 );
8607 %}
8608
8609 // Multiply Memory
8610 instruct mulI(eRegI dst, memory src, eFlagsReg cr) %{
8611 match(Set dst (MulI dst (LoadI src)));
8612 effect(KILL cr);
8613
8614 ins_cost(350);
8615 format %{ "IMUL $dst,$src" %}
8616 opcode(0xAF, 0x0F);
8617 ins_encode( OpcS, OpcP, RegMem( dst, src) );
8618 ins_pipe( ialu_reg_mem_alu0 );
8619 %}
8620
8621 // Multiply Register Int to Long
8622 instruct mulI2L(eADXRegL dst, eAXRegI src, nadxRegI src1, eFlagsReg flags) %{
8623 // Basic Idea: long = (long)int * (long)int
8624 match(Set dst (MulL (ConvI2L src) (ConvI2L src1)));
8625 effect(DEF dst, USE src, USE src1, KILL flags);
8626
8627 ins_cost(300);
8628 format %{ "IMUL $dst,$src1" %}
8629
8630 ins_encode( long_int_multiply( dst, src1 ) );
8631 ins_pipe( ialu_reg_reg_alu0 );
8632 %}
8633
8634 instruct mulIS_eReg(eADXRegL dst, immL_32bits mask, eFlagsReg flags, eAXRegI src, nadxRegI src1) %{
8635 // Basic Idea: long = (int & 0xffffffffL) * (int & 0xffffffffL)
8636 match(Set dst (MulL (AndL (ConvI2L src) mask) (AndL (ConvI2L src1) mask)));
8637 effect(KILL flags);
8638
8639 ins_cost(300);
8640 format %{ "MUL $dst,$src1" %}
8641
8642 ins_encode( long_uint_multiply(dst, src1) );
8643 ins_pipe( ialu_reg_reg_alu0 );
8644 %}
8645
8646 // Multiply Register Long
8647 instruct mulL_eReg(eADXRegL dst, eRegL src, eRegI tmp, eFlagsReg cr) %{
8648 match(Set dst (MulL dst src));
8649 effect(KILL cr, TEMP tmp);
8650 ins_cost(4*100+3*400);
8651 // Basic idea: lo(result) = lo(x_lo * y_lo)
8652 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
8653 format %{ "MOV $tmp,$src.lo\n\t"
8654 "IMUL $tmp,EDX\n\t"
8655 "MOV EDX,$src.hi\n\t"
8656 "IMUL EDX,EAX\n\t"
8657 "ADD $tmp,EDX\n\t"
8658 "MUL EDX:EAX,$src.lo\n\t"
8659 "ADD EDX,$tmp" %}
8660 ins_encode( long_multiply( dst, src, tmp ) );
8661 ins_pipe( pipe_slow );
8662 %}
8663
8664 // Multiply Register Long by small constant
8665 instruct mulL_eReg_con(eADXRegL dst, immL_127 src, eRegI tmp, eFlagsReg cr) %{
8666 match(Set dst (MulL dst src));
8667 effect(KILL cr, TEMP tmp);
8668 ins_cost(2*100+2*400);
8669 size(12);
8670 // Basic idea: lo(result) = lo(src * EAX)
8671 // hi(result) = hi(src * EAX) + lo(src * EDX)
8672 format %{ "IMUL $tmp,EDX,$src\n\t"
8673 "MOV EDX,$src\n\t"
8674 "MUL EDX\t# EDX*EAX -> EDX:EAX\n\t"
8675 "ADD EDX,$tmp" %}
8676 ins_encode( long_multiply_con( dst, src, tmp ) );
8677 ins_pipe( pipe_slow );
8678 %}
8679
8680 // Integer DIV with Register
8681 instruct divI_eReg(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{
8682 match(Set rax (DivI rax div));
8683 effect(KILL rdx, KILL cr);
8684 size(26);
8685 ins_cost(30*100+10*100);
8686 format %{ "CMP EAX,0x80000000\n\t"
8687 "JNE,s normal\n\t"
8688 "XOR EDX,EDX\n\t"
8689 "CMP ECX,-1\n\t"
8690 "JE,s done\n"
8691 "normal: CDQ\n\t"
8692 "IDIV $div\n\t"
8693 "done:" %}
8694 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8695 ins_encode( cdq_enc, OpcP, RegOpc(div) );
8696 ins_pipe( ialu_reg_reg_alu0 );
8697 %}
8698
8699 // Divide Register Long
8700 instruct divL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{
8701 match(Set dst (DivL src1 src2));
8702 effect( KILL cr, KILL cx, KILL bx );
8703 ins_cost(10000);
8704 format %{ "PUSH $src1.hi\n\t"
8705 "PUSH $src1.lo\n\t"
8706 "PUSH $src2.hi\n\t"
8707 "PUSH $src2.lo\n\t"
8708 "CALL SharedRuntime::ldiv\n\t"
8709 "ADD ESP,16" %}
8710 ins_encode( long_div(src1,src2) );
8711 ins_pipe( pipe_slow );
8712 %}
8713
8714 // Integer DIVMOD with Register, both quotient and mod results
8715 instruct divModI_eReg_divmod(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{
8716 match(DivModI rax div);
8717 effect(KILL cr);
8718 size(26);
8719 ins_cost(30*100+10*100);
8720 format %{ "CMP EAX,0x80000000\n\t"
8721 "JNE,s normal\n\t"
8722 "XOR EDX,EDX\n\t"
8723 "CMP ECX,-1\n\t"
8724 "JE,s done\n"
8725 "normal: CDQ\n\t"
8726 "IDIV $div\n\t"
8727 "done:" %}
8728 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8729 ins_encode( cdq_enc, OpcP, RegOpc(div) );
8730 ins_pipe( pipe_slow );
8731 %}
8732
8733 // Integer MOD with Register
8734 instruct modI_eReg(eDXRegI rdx, eAXRegI rax, eCXRegI div, eFlagsReg cr) %{
8735 match(Set rdx (ModI rax div));
8736 effect(KILL rax, KILL cr);
8737
8738 size(26);
8739 ins_cost(300);
8740 format %{ "CDQ\n\t"
8741 "IDIV $div" %}
8742 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8743 ins_encode( cdq_enc, OpcP, RegOpc(div) );
8744 ins_pipe( ialu_reg_reg_alu0 );
8745 %}
8746
8747 // Remainder Register Long
8748 instruct modL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{
8749 match(Set dst (ModL src1 src2));
8750 effect( KILL cr, KILL cx, KILL bx );
8751 ins_cost(10000);
8752 format %{ "PUSH $src1.hi\n\t"
8753 "PUSH $src1.lo\n\t"
8754 "PUSH $src2.hi\n\t"
8755 "PUSH $src2.lo\n\t"
8756 "CALL SharedRuntime::lrem\n\t"
8757 "ADD ESP,16" %}
8758 ins_encode( long_mod(src1,src2) );
8759 ins_pipe( pipe_slow );
8760 %}
8761
8762 // Integer Shift Instructions
8763 // Shift Left by one
8764 instruct shlI_eReg_1(eRegI dst, immI1 shift, eFlagsReg cr) %{
8765 match(Set dst (LShiftI dst shift));
8766 effect(KILL cr);
8767
8768 size(2);
8769 format %{ "SHL $dst,$shift" %}
8770 opcode(0xD1, 0x4); /* D1 /4 */
8771 ins_encode( OpcP, RegOpc( dst ) );
8772 ins_pipe( ialu_reg );
8773 %}
8774
8775 // Shift Left by 8-bit immediate
8776 instruct salI_eReg_imm(eRegI dst, immI8 shift, eFlagsReg cr) %{
8777 match(Set dst (LShiftI dst shift));
8778 effect(KILL cr);
8779
8780 size(3);
8781 format %{ "SHL $dst,$shift" %}
8782 opcode(0xC1, 0x4); /* C1 /4 ib */
8783 ins_encode( RegOpcImm( dst, shift) );
8784 ins_pipe( ialu_reg );
8785 %}
8786
8787 // Shift Left by variable
8788 instruct salI_eReg_CL(eRegI dst, eCXRegI shift, eFlagsReg cr) %{
8789 match(Set dst (LShiftI dst shift));
8790 effect(KILL cr);
8791
8792 size(2);
8793 format %{ "SHL $dst,$shift" %}
8794 opcode(0xD3, 0x4); /* D3 /4 */
8795 ins_encode( OpcP, RegOpc( dst ) );
8796 ins_pipe( ialu_reg_reg );
8797 %}
8798
8799 // Arithmetic shift right by one
8800 instruct sarI_eReg_1(eRegI dst, immI1 shift, eFlagsReg cr) %{
8801 match(Set dst (RShiftI dst shift));
8802 effect(KILL cr);
8803
8804 size(2);
8805 format %{ "SAR $dst,$shift" %}
8806 opcode(0xD1, 0x7); /* D1 /7 */
8807 ins_encode( OpcP, RegOpc( dst ) );
8808 ins_pipe( ialu_reg );
8809 %}
8810
8811 // Arithmetic shift right by one
8812 instruct sarI_mem_1(memory dst, immI1 shift, eFlagsReg cr) %{
8813 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8814 effect(KILL cr);
8815 format %{ "SAR $dst,$shift" %}
8816 opcode(0xD1, 0x7); /* D1 /7 */
8817 ins_encode( OpcP, RMopc_Mem(secondary,dst) );
8818 ins_pipe( ialu_mem_imm );
8819 %}
8820
8821 // Arithmetic Shift Right by 8-bit immediate
8822 instruct sarI_eReg_imm(eRegI dst, immI8 shift, eFlagsReg cr) %{
8823 match(Set dst (RShiftI dst shift));
8824 effect(KILL cr);
8825
8826 size(3);
8827 format %{ "SAR $dst,$shift" %}
8828 opcode(0xC1, 0x7); /* C1 /7 ib */
8829 ins_encode( RegOpcImm( dst, shift ) );
8830 ins_pipe( ialu_mem_imm );
8831 %}
8832
8833 // Arithmetic Shift Right by 8-bit immediate
8834 instruct sarI_mem_imm(memory dst, immI8 shift, eFlagsReg cr) %{
8835 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8836 effect(KILL cr);
8837
8838 format %{ "SAR $dst,$shift" %}
8839 opcode(0xC1, 0x7); /* C1 /7 ib */
8840 ins_encode( OpcP, RMopc_Mem(secondary, dst ), Con8or32( shift ) );
8841 ins_pipe( ialu_mem_imm );
8842 %}
8843
8844 // Arithmetic Shift Right by variable
8845 instruct sarI_eReg_CL(eRegI dst, eCXRegI shift, eFlagsReg cr) %{
8846 match(Set dst (RShiftI dst shift));
8847 effect(KILL cr);
8848
8849 size(2);
8850 format %{ "SAR $dst,$shift" %}
8851 opcode(0xD3, 0x7); /* D3 /7 */
8852 ins_encode( OpcP, RegOpc( dst ) );
8853 ins_pipe( ialu_reg_reg );
8854 %}
8855
8856 // Logical shift right by one
8857 instruct shrI_eReg_1(eRegI dst, immI1 shift, eFlagsReg cr) %{
8858 match(Set dst (URShiftI dst shift));
8859 effect(KILL cr);
8860
8861 size(2);
8862 format %{ "SHR $dst,$shift" %}
8863 opcode(0xD1, 0x5); /* D1 /5 */
8864 ins_encode( OpcP, RegOpc( dst ) );
8865 ins_pipe( ialu_reg );
8866 %}
8867
8868 // Logical Shift Right by 8-bit immediate
8869 instruct shrI_eReg_imm(eRegI dst, immI8 shift, eFlagsReg cr) %{
8870 match(Set dst (URShiftI dst shift));
8871 effect(KILL cr);
8872
8873 size(3);
8874 format %{ "SHR $dst,$shift" %}
8875 opcode(0xC1, 0x5); /* C1 /5 ib */
8876 ins_encode( RegOpcImm( dst, shift) );
8877 ins_pipe( ialu_reg );
8878 %}
8879
8880
8881 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24.
8882 // This idiom is used by the compiler for the i2b bytecode.
8883 instruct i2b(eRegI dst, xRegI src, immI_24 twentyfour, eFlagsReg cr) %{
8884 match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour));
8885 effect(KILL cr);
8886
8887 size(3);
8888 format %{ "MOVSX $dst,$src :8" %}
8889 opcode(0xBE, 0x0F);
8890 ins_encode( OpcS, OpcP, RegReg( dst, src));
8891 ins_pipe( ialu_reg_reg );
8892 %}
8893
8894 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16.
8895 // This idiom is used by the compiler the i2s bytecode.
8896 instruct i2s(eRegI dst, xRegI src, immI_16 sixteen, eFlagsReg cr) %{
8897 match(Set dst (RShiftI (LShiftI src sixteen) sixteen));
8898 effect(KILL cr);
8899
8900 size(3);
8901 format %{ "MOVSX $dst,$src :16" %}
8902 opcode(0xBF, 0x0F);
8903 ins_encode( OpcS, OpcP, RegReg( dst, src));
8904 ins_pipe( ialu_reg_reg );
8905 %}
8906
8907
8908 // Logical Shift Right by variable
8909 instruct shrI_eReg_CL(eRegI dst, eCXRegI shift, eFlagsReg cr) %{
8910 match(Set dst (URShiftI dst shift));
8911 effect(KILL cr);
8912
8913 size(2);
8914 format %{ "SHR $dst,$shift" %}
8915 opcode(0xD3, 0x5); /* D3 /5 */
8916 ins_encode( OpcP, RegOpc( dst ) );
8917 ins_pipe( ialu_reg_reg );
8918 %}
8919
8920
8921 //----------Logical Instructions-----------------------------------------------
8922 //----------Integer Logical Instructions---------------------------------------
8923 // And Instructions
8924 // And Register with Register
8925 instruct andI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
8926 match(Set dst (AndI dst src));
8927 effect(KILL cr);
8928
8929 size(2);
8930 format %{ "AND $dst,$src" %}
8931 opcode(0x23);
8932 ins_encode( OpcP, RegReg( dst, src) );
8933 ins_pipe( ialu_reg_reg );
8934 %}
8935
8936 // And Register with Immediate
8937 instruct andI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{
8938 match(Set dst (AndI dst src));
8939 effect(KILL cr);
8940
8941 format %{ "AND $dst,$src" %}
8942 opcode(0x81,0x04); /* Opcode 81 /4 */
8943 // ins_encode( RegImm( dst, src) );
8944 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8945 ins_pipe( ialu_reg );
8946 %}
8947
8948 // And Register with Memory
8949 instruct andI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{
8950 match(Set dst (AndI dst (LoadI src)));
8951 effect(KILL cr);
8952
8953 ins_cost(125);
8954 format %{ "AND $dst,$src" %}
8955 opcode(0x23);
8956 ins_encode( OpcP, RegMem( dst, src) );
8957 ins_pipe( ialu_reg_mem );
8958 %}
8959
8960 // And Memory with Register
8961 instruct andI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{
8962 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
8963 effect(KILL cr);
8964
8965 ins_cost(150);
8966 format %{ "AND $dst,$src" %}
8967 opcode(0x21); /* Opcode 21 /r */
8968 ins_encode( OpcP, RegMem( src, dst ) );
8969 ins_pipe( ialu_mem_reg );
8970 %}
8971
8972 // And Memory with Immediate
8973 instruct andI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
8974 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
8975 effect(KILL cr);
8976
8977 ins_cost(125);
8978 format %{ "AND $dst,$src" %}
8979 opcode(0x81, 0x4); /* Opcode 81 /4 id */
8980 // ins_encode( MemImm( dst, src) );
8981 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
8982 ins_pipe( ialu_mem_imm );
8983 %}
8984
8985 // Or Instructions
8986 // Or Register with Register
8987 instruct orI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
8988 match(Set dst (OrI dst src));
8989 effect(KILL cr);
8990
8991 size(2);
8992 format %{ "OR $dst,$src" %}
8993 opcode(0x0B);
8994 ins_encode( OpcP, RegReg( dst, src) );
8995 ins_pipe( ialu_reg_reg );
8996 %}
8997
8998 instruct orI_eReg_castP2X(eRegI dst, eRegP src, eFlagsReg cr) %{
8999 match(Set dst (OrI dst (CastP2X src)));
9000 effect(KILL cr);
9001
9002 size(2);
9003 format %{ "OR $dst,$src" %}
9004 opcode(0x0B);
9005 ins_encode( OpcP, RegReg( dst, src) );
9006 ins_pipe( ialu_reg_reg );
9007 %}
9008
9009
9010 // Or Register with Immediate
9011 instruct orI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{
9012 match(Set dst (OrI dst src));
9013 effect(KILL cr);
9014
9015 format %{ "OR $dst,$src" %}
9016 opcode(0x81,0x01); /* Opcode 81 /1 id */
9017 // ins_encode( RegImm( dst, src) );
9018 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
9019 ins_pipe( ialu_reg );
9020 %}
9021
9022 // Or Register with Memory
9023 instruct orI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{
9024 match(Set dst (OrI dst (LoadI src)));
9025 effect(KILL cr);
9026
9027 ins_cost(125);
9028 format %{ "OR $dst,$src" %}
9029 opcode(0x0B);
9030 ins_encode( OpcP, RegMem( dst, src) );
9031 ins_pipe( ialu_reg_mem );
9032 %}
9033
9034 // Or Memory with Register
9035 instruct orI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{
9036 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
9037 effect(KILL cr);
9038
9039 ins_cost(150);
9040 format %{ "OR $dst,$src" %}
9041 opcode(0x09); /* Opcode 09 /r */
9042 ins_encode( OpcP, RegMem( src, dst ) );
9043 ins_pipe( ialu_mem_reg );
9044 %}
9045
9046 // Or Memory with Immediate
9047 instruct orI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
9048 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
9049 effect(KILL cr);
9050
9051 ins_cost(125);
9052 format %{ "OR $dst,$src" %}
9053 opcode(0x81,0x1); /* Opcode 81 /1 id */
9054 // ins_encode( MemImm( dst, src) );
9055 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
9056 ins_pipe( ialu_mem_imm );
9057 %}
9058
9059 // ROL/ROR
9060 // ROL expand
9061 instruct rolI_eReg_imm1(eRegI dst, immI1 shift, eFlagsReg cr) %{
9062 effect(USE_DEF dst, USE shift, KILL cr);
9063
9064 format %{ "ROL $dst, $shift" %}
9065 opcode(0xD1, 0x0); /* Opcode D1 /0 */
9066 ins_encode( OpcP, RegOpc( dst ));
9067 ins_pipe( ialu_reg );
9068 %}
9069
9070 instruct rolI_eReg_imm8(eRegI dst, immI8 shift, eFlagsReg cr) %{
9071 effect(USE_DEF dst, USE shift, KILL cr);
9072
9073 format %{ "ROL $dst, $shift" %}
9074 opcode(0xC1, 0x0); /*Opcode /C1 /0 */
9075 ins_encode( RegOpcImm(dst, shift) );
9076 ins_pipe(ialu_reg);
9077 %}
9078
9079 instruct rolI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr) %{
9080 effect(USE_DEF dst, USE shift, KILL cr);
9081
9082 format %{ "ROL $dst, $shift" %}
9083 opcode(0xD3, 0x0); /* Opcode D3 /0 */
9084 ins_encode(OpcP, RegOpc(dst));
9085 ins_pipe( ialu_reg_reg );
9086 %}
9087 // end of ROL expand
9088
9089 // ROL 32bit by one once
9090 instruct rolI_eReg_i1(eRegI dst, immI1 lshift, immI_M1 rshift, eFlagsReg cr) %{
9091 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift)));
9092
9093 expand %{
9094 rolI_eReg_imm1(dst, lshift, cr);
9095 %}
9096 %}
9097
9098 // ROL 32bit var by imm8 once
9099 instruct rolI_eReg_i8(eRegI dst, immI8 lshift, immI8 rshift, eFlagsReg cr) %{
9100 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
9101 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift)));
9102
9103 expand %{
9104 rolI_eReg_imm8(dst, lshift, cr);
9105 %}
9106 %}
9107
9108 // ROL 32bit var by var once
9109 instruct rolI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{
9110 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI zero shift))));
9111
9112 expand %{
9113 rolI_eReg_CL(dst, shift, cr);
9114 %}
9115 %}
9116
9117 // ROL 32bit var by var once
9118 instruct rolI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{
9119 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI c32 shift))));
9120
9121 expand %{
9122 rolI_eReg_CL(dst, shift, cr);
9123 %}
9124 %}
9125
9126 // ROR expand
9127 instruct rorI_eReg_imm1(eRegI dst, immI1 shift, eFlagsReg cr) %{
9128 effect(USE_DEF dst, USE shift, KILL cr);
9129
9130 format %{ "ROR $dst, $shift" %}
9131 opcode(0xD1,0x1); /* Opcode D1 /1 */
9132 ins_encode( OpcP, RegOpc( dst ) );
9133 ins_pipe( ialu_reg );
9134 %}
9135
9136 instruct rorI_eReg_imm8(eRegI dst, immI8 shift, eFlagsReg cr) %{
9137 effect (USE_DEF dst, USE shift, KILL cr);
9138
9139 format %{ "ROR $dst, $shift" %}
9140 opcode(0xC1, 0x1); /* Opcode /C1 /1 ib */
9141 ins_encode( RegOpcImm(dst, shift) );
9142 ins_pipe( ialu_reg );
9143 %}
9144
9145 instruct rorI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr)%{
9146 effect(USE_DEF dst, USE shift, KILL cr);
9147
9148 format %{ "ROR $dst, $shift" %}
9149 opcode(0xD3, 0x1); /* Opcode D3 /1 */
9150 ins_encode(OpcP, RegOpc(dst));
9151 ins_pipe( ialu_reg_reg );
9152 %}
9153 // end of ROR expand
9154
9155 // ROR right once
9156 instruct rorI_eReg_i1(eRegI dst, immI1 rshift, immI_M1 lshift, eFlagsReg cr) %{
9157 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift)));
9158
9159 expand %{
9160 rorI_eReg_imm1(dst, rshift, cr);
9161 %}
9162 %}
9163
9164 // ROR 32bit by immI8 once
9165 instruct rorI_eReg_i8(eRegI dst, immI8 rshift, immI8 lshift, eFlagsReg cr) %{
9166 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
9167 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift)));
9168
9169 expand %{
9170 rorI_eReg_imm8(dst, rshift, cr);
9171 %}
9172 %}
9173
9174 // ROR 32bit var by var once
9175 instruct rorI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{
9176 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI zero shift))));
9177
9178 expand %{
9179 rorI_eReg_CL(dst, shift, cr);
9180 %}
9181 %}
9182
9183 // ROR 32bit var by var once
9184 instruct rorI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{
9185 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI c32 shift))));
9186
9187 expand %{
9188 rorI_eReg_CL(dst, shift, cr);
9189 %}
9190 %}
9191
9192 // Xor Instructions
9193 // Xor Register with Register
9194 instruct xorI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
9195 match(Set dst (XorI dst src));
9196 effect(KILL cr);
9197
9198 size(2);
9199 format %{ "XOR $dst,$src" %}
9200 opcode(0x33);
9201 ins_encode( OpcP, RegReg( dst, src) );
9202 ins_pipe( ialu_reg_reg );
9203 %}
9204
9205 // Xor Register with Immediate -1
9206 instruct xorI_eReg_im1(eRegI dst, immI_M1 imm) %{
9207 match(Set dst (XorI dst imm));
9208
9209 size(2);
9210 format %{ "NOT $dst" %}
9211 ins_encode %{
9212 __ notl($dst$$Register);
9213 %}
9214 ins_pipe( ialu_reg );
9215 %}
9216
9217 // Xor Register with Immediate
9218 instruct xorI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{
9219 match(Set dst (XorI dst src));
9220 effect(KILL cr);
9221
9222 format %{ "XOR $dst,$src" %}
9223 opcode(0x81,0x06); /* Opcode 81 /6 id */
9224 // ins_encode( RegImm( dst, src) );
9225 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
9226 ins_pipe( ialu_reg );
9227 %}
9228
9229 // Xor Register with Memory
9230 instruct xorI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{
9231 match(Set dst (XorI dst (LoadI src)));
9232 effect(KILL cr);
9233
9234 ins_cost(125);
9235 format %{ "XOR $dst,$src" %}
9236 opcode(0x33);
9237 ins_encode( OpcP, RegMem(dst, src) );
9238 ins_pipe( ialu_reg_mem );
9239 %}
9240
9241 // Xor Memory with Register
9242 instruct xorI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{
9243 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
9244 effect(KILL cr);
9245
9246 ins_cost(150);
9247 format %{ "XOR $dst,$src" %}
9248 opcode(0x31); /* Opcode 31 /r */
9249 ins_encode( OpcP, RegMem( src, dst ) );
9250 ins_pipe( ialu_mem_reg );
9251 %}
9252
9253 // Xor Memory with Immediate
9254 instruct xorI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
9255 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
9256 effect(KILL cr);
9257
9258 ins_cost(125);
9259 format %{ "XOR $dst,$src" %}
9260 opcode(0x81,0x6); /* Opcode 81 /6 id */
9261 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
9262 ins_pipe( ialu_mem_imm );
9263 %}
9264
9265 //----------Convert Int to Boolean---------------------------------------------
9266
9267 instruct movI_nocopy(eRegI dst, eRegI src) %{
9268 effect( DEF dst, USE src );
9269 format %{ "MOV $dst,$src" %}
9270 ins_encode( enc_Copy( dst, src) );
9271 ins_pipe( ialu_reg_reg );
9272 %}
9273
9274 instruct ci2b( eRegI dst, eRegI src, eFlagsReg cr ) %{
9275 effect( USE_DEF dst, USE src, KILL cr );
9276
9277 size(4);
9278 format %{ "NEG $dst\n\t"
9279 "ADC $dst,$src" %}
9280 ins_encode( neg_reg(dst),
9281 OpcRegReg(0x13,dst,src) );
9282 ins_pipe( ialu_reg_reg_long );
9283 %}
9284
9285 instruct convI2B( eRegI dst, eRegI src, eFlagsReg cr ) %{
9286 match(Set dst (Conv2B src));
9287
9288 expand %{
9289 movI_nocopy(dst,src);
9290 ci2b(dst,src,cr);
9291 %}
9292 %}
9293
9294 instruct movP_nocopy(eRegI dst, eRegP src) %{
9295 effect( DEF dst, USE src );
9296 format %{ "MOV $dst,$src" %}
9297 ins_encode( enc_Copy( dst, src) );
9298 ins_pipe( ialu_reg_reg );
9299 %}
9300
9301 instruct cp2b( eRegI dst, eRegP src, eFlagsReg cr ) %{
9302 effect( USE_DEF dst, USE src, KILL cr );
9303 format %{ "NEG $dst\n\t"
9304 "ADC $dst,$src" %}
9305 ins_encode( neg_reg(dst),
9306 OpcRegReg(0x13,dst,src) );
9307 ins_pipe( ialu_reg_reg_long );
9308 %}
9309
9310 instruct convP2B( eRegI dst, eRegP src, eFlagsReg cr ) %{
9311 match(Set dst (Conv2B src));
9312
9313 expand %{
9314 movP_nocopy(dst,src);
9315 cp2b(dst,src,cr);
9316 %}
9317 %}
9318
9319 instruct cmpLTMask( eCXRegI dst, ncxRegI p, ncxRegI q, eFlagsReg cr ) %{
9320 match(Set dst (CmpLTMask p q));
9321 effect( KILL cr );
9322 ins_cost(400);
9323
9324 // SETlt can only use low byte of EAX,EBX, ECX, or EDX as destination
9325 format %{ "XOR $dst,$dst\n\t"
9326 "CMP $p,$q\n\t"
9327 "SETlt $dst\n\t"
9328 "NEG $dst" %}
9329 ins_encode( OpcRegReg(0x33,dst,dst),
9330 OpcRegReg(0x3B,p,q),
9331 setLT_reg(dst), neg_reg(dst) );
9332 ins_pipe( pipe_slow );
9333 %}
9334
9335 instruct cmpLTMask0( eRegI dst, immI0 zero, eFlagsReg cr ) %{
9336 match(Set dst (CmpLTMask dst zero));
9337 effect( DEF dst, KILL cr );
9338 ins_cost(100);
9339
9340 format %{ "SAR $dst,31" %}
9341 opcode(0xC1, 0x7); /* C1 /7 ib */
9342 ins_encode( RegOpcImm( dst, 0x1F ) );
9343 ins_pipe( ialu_reg );
9344 %}
9345
9346
9347 instruct cadd_cmpLTMask( ncxRegI p, ncxRegI q, ncxRegI y, eCXRegI tmp, eFlagsReg cr ) %{
9348 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
9349 effect( KILL tmp, KILL cr );
9350 ins_cost(400);
9351 // annoyingly, $tmp has no edges so you cant ask for it in
9352 // any format or encoding
9353 format %{ "SUB $p,$q\n\t"
9354 "SBB ECX,ECX\n\t"
9355 "AND ECX,$y\n\t"
9356 "ADD $p,ECX" %}
9357 ins_encode( enc_cmpLTP(p,q,y,tmp) );
9358 ins_pipe( pipe_cmplt );
9359 %}
9360
9361 /* If I enable this, I encourage spilling in the inner loop of compress.
9362 instruct cadd_cmpLTMask_mem( ncxRegI p, ncxRegI q, memory y, eCXRegI tmp, eFlagsReg cr ) %{
9363 match(Set p (AddI (AndI (CmpLTMask p q) (LoadI y)) (SubI p q)));
9364 effect( USE_KILL tmp, KILL cr );
9365 ins_cost(400);
9366
9367 format %{ "SUB $p,$q\n\t"
9368 "SBB ECX,ECX\n\t"
9369 "AND ECX,$y\n\t"
9370 "ADD $p,ECX" %}
9371 ins_encode( enc_cmpLTP_mem(p,q,y,tmp) );
9372 %}
9373 */
9374
9375 //----------Long Instructions------------------------------------------------
9376 // Add Long Register with Register
9377 instruct addL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9378 match(Set dst (AddL dst src));
9379 effect(KILL cr);
9380 ins_cost(200);
9381 format %{ "ADD $dst.lo,$src.lo\n\t"
9382 "ADC $dst.hi,$src.hi" %}
9383 opcode(0x03, 0x13);
9384 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) );
9385 ins_pipe( ialu_reg_reg_long );
9386 %}
9387
9388 // Add Long Register with Immediate
9389 instruct addL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9390 match(Set dst (AddL dst src));
9391 effect(KILL cr);
9392 format %{ "ADD $dst.lo,$src.lo\n\t"
9393 "ADC $dst.hi,$src.hi" %}
9394 opcode(0x81,0x00,0x02); /* Opcode 81 /0, 81 /2 */
9395 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9396 ins_pipe( ialu_reg_long );
9397 %}
9398
9399 // Add Long Register with Memory
9400 instruct addL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9401 match(Set dst (AddL dst (LoadL mem)));
9402 effect(KILL cr);
9403 ins_cost(125);
9404 format %{ "ADD $dst.lo,$mem\n\t"
9405 "ADC $dst.hi,$mem+4" %}
9406 opcode(0x03, 0x13);
9407 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9408 ins_pipe( ialu_reg_long_mem );
9409 %}
9410
9411 // Subtract Long Register with Register.
9412 instruct subL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9413 match(Set dst (SubL dst src));
9414 effect(KILL cr);
9415 ins_cost(200);
9416 format %{ "SUB $dst.lo,$src.lo\n\t"
9417 "SBB $dst.hi,$src.hi" %}
9418 opcode(0x2B, 0x1B);
9419 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) );
9420 ins_pipe( ialu_reg_reg_long );
9421 %}
9422
9423 // Subtract Long Register with Immediate
9424 instruct subL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9425 match(Set dst (SubL dst src));
9426 effect(KILL cr);
9427 format %{ "SUB $dst.lo,$src.lo\n\t"
9428 "SBB $dst.hi,$src.hi" %}
9429 opcode(0x81,0x05,0x03); /* Opcode 81 /5, 81 /3 */
9430 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9431 ins_pipe( ialu_reg_long );
9432 %}
9433
9434 // Subtract Long Register with Memory
9435 instruct subL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9436 match(Set dst (SubL dst (LoadL mem)));
9437 effect(KILL cr);
9438 ins_cost(125);
9439 format %{ "SUB $dst.lo,$mem\n\t"
9440 "SBB $dst.hi,$mem+4" %}
9441 opcode(0x2B, 0x1B);
9442 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9443 ins_pipe( ialu_reg_long_mem );
9444 %}
9445
9446 instruct negL_eReg(eRegL dst, immL0 zero, eFlagsReg cr) %{
9447 match(Set dst (SubL zero dst));
9448 effect(KILL cr);
9449 ins_cost(300);
9450 format %{ "NEG $dst.hi\n\tNEG $dst.lo\n\tSBB $dst.hi,0" %}
9451 ins_encode( neg_long(dst) );
9452 ins_pipe( ialu_reg_reg_long );
9453 %}
9454
9455 // And Long Register with Register
9456 instruct andL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9457 match(Set dst (AndL dst src));
9458 effect(KILL cr);
9459 format %{ "AND $dst.lo,$src.lo\n\t"
9460 "AND $dst.hi,$src.hi" %}
9461 opcode(0x23,0x23);
9462 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
9463 ins_pipe( ialu_reg_reg_long );
9464 %}
9465
9466 // And Long Register with Immediate
9467 instruct andL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9468 match(Set dst (AndL dst src));
9469 effect(KILL cr);
9470 format %{ "AND $dst.lo,$src.lo\n\t"
9471 "AND $dst.hi,$src.hi" %}
9472 opcode(0x81,0x04,0x04); /* Opcode 81 /4, 81 /4 */
9473 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9474 ins_pipe( ialu_reg_long );
9475 %}
9476
9477 // And Long Register with Memory
9478 instruct andL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9479 match(Set dst (AndL dst (LoadL mem)));
9480 effect(KILL cr);
9481 ins_cost(125);
9482 format %{ "AND $dst.lo,$mem\n\t"
9483 "AND $dst.hi,$mem+4" %}
9484 opcode(0x23, 0x23);
9485 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9486 ins_pipe( ialu_reg_long_mem );
9487 %}
9488
9489 // Or Long Register with Register
9490 instruct orl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9491 match(Set dst (OrL dst src));
9492 effect(KILL cr);
9493 format %{ "OR $dst.lo,$src.lo\n\t"
9494 "OR $dst.hi,$src.hi" %}
9495 opcode(0x0B,0x0B);
9496 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
9497 ins_pipe( ialu_reg_reg_long );
9498 %}
9499
9500 // Or Long Register with Immediate
9501 instruct orl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9502 match(Set dst (OrL dst src));
9503 effect(KILL cr);
9504 format %{ "OR $dst.lo,$src.lo\n\t"
9505 "OR $dst.hi,$src.hi" %}
9506 opcode(0x81,0x01,0x01); /* Opcode 81 /1, 81 /1 */
9507 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9508 ins_pipe( ialu_reg_long );
9509 %}
9510
9511 // Or Long Register with Memory
9512 instruct orl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9513 match(Set dst (OrL dst (LoadL mem)));
9514 effect(KILL cr);
9515 ins_cost(125);
9516 format %{ "OR $dst.lo,$mem\n\t"
9517 "OR $dst.hi,$mem+4" %}
9518 opcode(0x0B,0x0B);
9519 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9520 ins_pipe( ialu_reg_long_mem );
9521 %}
9522
9523 // Xor Long Register with Register
9524 instruct xorl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9525 match(Set dst (XorL dst src));
9526 effect(KILL cr);
9527 format %{ "XOR $dst.lo,$src.lo\n\t"
9528 "XOR $dst.hi,$src.hi" %}
9529 opcode(0x33,0x33);
9530 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
9531 ins_pipe( ialu_reg_reg_long );
9532 %}
9533
9534 // Xor Long Register with Immediate -1
9535 instruct xorl_eReg_im1(eRegL dst, immL_M1 imm) %{
9536 match(Set dst (XorL dst imm));
9537 format %{ "NOT $dst.lo\n\t"
9538 "NOT $dst.hi" %}
9539 ins_encode %{
9540 __ notl($dst$$Register);
9541 __ notl(HIGH_FROM_LOW($dst$$Register));
9542 %}
9543 ins_pipe( ialu_reg_long );
9544 %}
9545
9546 // Xor Long Register with Immediate
9547 instruct xorl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9548 match(Set dst (XorL dst src));
9549 effect(KILL cr);
9550 format %{ "XOR $dst.lo,$src.lo\n\t"
9551 "XOR $dst.hi,$src.hi" %}
9552 opcode(0x81,0x06,0x06); /* Opcode 81 /6, 81 /6 */
9553 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9554 ins_pipe( ialu_reg_long );
9555 %}
9556
9557 // Xor Long Register with Memory
9558 instruct xorl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9559 match(Set dst (XorL dst (LoadL mem)));
9560 effect(KILL cr);
9561 ins_cost(125);
9562 format %{ "XOR $dst.lo,$mem\n\t"
9563 "XOR $dst.hi,$mem+4" %}
9564 opcode(0x33,0x33);
9565 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9566 ins_pipe( ialu_reg_long_mem );
9567 %}
9568
9569 // Shift Left Long by 1
9570 instruct shlL_eReg_1(eRegL dst, immI_1 cnt, eFlagsReg cr) %{
9571 predicate(UseNewLongLShift);
9572 match(Set dst (LShiftL dst cnt));
9573 effect(KILL cr);
9574 ins_cost(100);
9575 format %{ "ADD $dst.lo,$dst.lo\n\t"
9576 "ADC $dst.hi,$dst.hi" %}
9577 ins_encode %{
9578 __ addl($dst$$Register,$dst$$Register);
9579 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9580 %}
9581 ins_pipe( ialu_reg_long );
9582 %}
9583
9584 // Shift Left Long by 2
9585 instruct shlL_eReg_2(eRegL dst, immI_2 cnt, eFlagsReg cr) %{
9586 predicate(UseNewLongLShift);
9587 match(Set dst (LShiftL dst cnt));
9588 effect(KILL cr);
9589 ins_cost(100);
9590 format %{ "ADD $dst.lo,$dst.lo\n\t"
9591 "ADC $dst.hi,$dst.hi\n\t"
9592 "ADD $dst.lo,$dst.lo\n\t"
9593 "ADC $dst.hi,$dst.hi" %}
9594 ins_encode %{
9595 __ addl($dst$$Register,$dst$$Register);
9596 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9597 __ addl($dst$$Register,$dst$$Register);
9598 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9599 %}
9600 ins_pipe( ialu_reg_long );
9601 %}
9602
9603 // Shift Left Long by 3
9604 instruct shlL_eReg_3(eRegL dst, immI_3 cnt, eFlagsReg cr) %{
9605 predicate(UseNewLongLShift);
9606 match(Set dst (LShiftL dst cnt));
9607 effect(KILL cr);
9608 ins_cost(100);
9609 format %{ "ADD $dst.lo,$dst.lo\n\t"
9610 "ADC $dst.hi,$dst.hi\n\t"
9611 "ADD $dst.lo,$dst.lo\n\t"
9612 "ADC $dst.hi,$dst.hi\n\t"
9613 "ADD $dst.lo,$dst.lo\n\t"
9614 "ADC $dst.hi,$dst.hi" %}
9615 ins_encode %{
9616 __ addl($dst$$Register,$dst$$Register);
9617 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9618 __ addl($dst$$Register,$dst$$Register);
9619 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9620 __ addl($dst$$Register,$dst$$Register);
9621 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9622 %}
9623 ins_pipe( ialu_reg_long );
9624 %}
9625
9626 // Shift Left Long by 1-31
9627 instruct shlL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9628 match(Set dst (LShiftL dst cnt));
9629 effect(KILL cr);
9630 ins_cost(200);
9631 format %{ "SHLD $dst.hi,$dst.lo,$cnt\n\t"
9632 "SHL $dst.lo,$cnt" %}
9633 opcode(0xC1, 0x4, 0xA4); /* 0F/A4, then C1 /4 ib */
9634 ins_encode( move_long_small_shift(dst,cnt) );
9635 ins_pipe( ialu_reg_long );
9636 %}
9637
9638 // Shift Left Long by 32-63
9639 instruct shlL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9640 match(Set dst (LShiftL dst cnt));
9641 effect(KILL cr);
9642 ins_cost(300);
9643 format %{ "MOV $dst.hi,$dst.lo\n"
9644 "\tSHL $dst.hi,$cnt-32\n"
9645 "\tXOR $dst.lo,$dst.lo" %}
9646 opcode(0xC1, 0x4); /* C1 /4 ib */
9647 ins_encode( move_long_big_shift_clr(dst,cnt) );
9648 ins_pipe( ialu_reg_long );
9649 %}
9650
9651 // Shift Left Long by variable
9652 instruct salL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9653 match(Set dst (LShiftL dst shift));
9654 effect(KILL cr);
9655 ins_cost(500+200);
9656 size(17);
9657 format %{ "TEST $shift,32\n\t"
9658 "JEQ,s small\n\t"
9659 "MOV $dst.hi,$dst.lo\n\t"
9660 "XOR $dst.lo,$dst.lo\n"
9661 "small:\tSHLD $dst.hi,$dst.lo,$shift\n\t"
9662 "SHL $dst.lo,$shift" %}
9663 ins_encode( shift_left_long( dst, shift ) );
9664 ins_pipe( pipe_slow );
9665 %}
9666
9667 // Shift Right Long by 1-31
9668 instruct shrL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9669 match(Set dst (URShiftL dst cnt));
9670 effect(KILL cr);
9671 ins_cost(200);
9672 format %{ "SHRD $dst.lo,$dst.hi,$cnt\n\t"
9673 "SHR $dst.hi,$cnt" %}
9674 opcode(0xC1, 0x5, 0xAC); /* 0F/AC, then C1 /5 ib */
9675 ins_encode( move_long_small_shift(dst,cnt) );
9676 ins_pipe( ialu_reg_long );
9677 %}
9678
9679 // Shift Right Long by 32-63
9680 instruct shrL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9681 match(Set dst (URShiftL dst cnt));
9682 effect(KILL cr);
9683 ins_cost(300);
9684 format %{ "MOV $dst.lo,$dst.hi\n"
9685 "\tSHR $dst.lo,$cnt-32\n"
9686 "\tXOR $dst.hi,$dst.hi" %}
9687 opcode(0xC1, 0x5); /* C1 /5 ib */
9688 ins_encode( move_long_big_shift_clr(dst,cnt) );
9689 ins_pipe( ialu_reg_long );
9690 %}
9691
9692 // Shift Right Long by variable
9693 instruct shrL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9694 match(Set dst (URShiftL dst shift));
9695 effect(KILL cr);
9696 ins_cost(600);
9697 size(17);
9698 format %{ "TEST $shift,32\n\t"
9699 "JEQ,s small\n\t"
9700 "MOV $dst.lo,$dst.hi\n\t"
9701 "XOR $dst.hi,$dst.hi\n"
9702 "small:\tSHRD $dst.lo,$dst.hi,$shift\n\t"
9703 "SHR $dst.hi,$shift" %}
9704 ins_encode( shift_right_long( dst, shift ) );
9705 ins_pipe( pipe_slow );
9706 %}
9707
9708 // Shift Right Long by 1-31
9709 instruct sarL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9710 match(Set dst (RShiftL dst cnt));
9711 effect(KILL cr);
9712 ins_cost(200);
9713 format %{ "SHRD $dst.lo,$dst.hi,$cnt\n\t"
9714 "SAR $dst.hi,$cnt" %}
9715 opcode(0xC1, 0x7, 0xAC); /* 0F/AC, then C1 /7 ib */
9716 ins_encode( move_long_small_shift(dst,cnt) );
9717 ins_pipe( ialu_reg_long );
9718 %}
9719
9720 // Shift Right Long by 32-63
9721 instruct sarL_eReg_32_63( eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9722 match(Set dst (RShiftL dst cnt));
9723 effect(KILL cr);
9724 ins_cost(300);
9725 format %{ "MOV $dst.lo,$dst.hi\n"
9726 "\tSAR $dst.lo,$cnt-32\n"
9727 "\tSAR $dst.hi,31" %}
9728 opcode(0xC1, 0x7); /* C1 /7 ib */
9729 ins_encode( move_long_big_shift_sign(dst,cnt) );
9730 ins_pipe( ialu_reg_long );
9731 %}
9732
9733 // Shift Right arithmetic Long by variable
9734 instruct sarL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9735 match(Set dst (RShiftL dst shift));
9736 effect(KILL cr);
9737 ins_cost(600);
9738 size(18);
9739 format %{ "TEST $shift,32\n\t"
9740 "JEQ,s small\n\t"
9741 "MOV $dst.lo,$dst.hi\n\t"
9742 "SAR $dst.hi,31\n"
9743 "small:\tSHRD $dst.lo,$dst.hi,$shift\n\t"
9744 "SAR $dst.hi,$shift" %}
9745 ins_encode( shift_right_arith_long( dst, shift ) );
9746 ins_pipe( pipe_slow );
9747 %}
9748
9749
9750 //----------Double Instructions------------------------------------------------
9751 // Double Math
9752
9753 // Compare & branch
9754
9755 // P6 version of float compare, sets condition codes in EFLAGS
9756 instruct cmpD_cc_P6(eFlagsRegU cr, regD src1, regD src2, eAXRegI rax) %{
9757 predicate(VM_Version::supports_cmov() && UseSSE <=1);
9758 match(Set cr (CmpD src1 src2));
9759 effect(KILL rax);
9760 ins_cost(150);
9761 format %{ "FLD $src1\n\t"
9762 "FUCOMIP ST,$src2 // P6 instruction\n\t"
9763 "JNP exit\n\t"
9764 "MOV ah,1 // saw a NaN, set CF\n\t"
9765 "SAHF\n"
9766 "exit:\tNOP // avoid branch to branch" %}
9767 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
9768 ins_encode( Push_Reg_D(src1),
9769 OpcP, RegOpc(src2),
9770 cmpF_P6_fixup );
9771 ins_pipe( pipe_slow );
9772 %}
9773
9774 instruct cmpD_cc_P6CF(eFlagsRegUCF cr, regD src1, regD src2) %{
9775 predicate(VM_Version::supports_cmov() && UseSSE <=1);
9776 match(Set cr (CmpD src1 src2));
9777 ins_cost(150);
9778 format %{ "FLD $src1\n\t"
9779 "FUCOMIP ST,$src2 // P6 instruction" %}
9780 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
9781 ins_encode( Push_Reg_D(src1),
9782 OpcP, RegOpc(src2));
9783 ins_pipe( pipe_slow );
9784 %}
9785
9786 // Compare & branch
9787 instruct cmpD_cc(eFlagsRegU cr, regD src1, regD src2, eAXRegI rax) %{
9788 predicate(UseSSE<=1);
9789 match(Set cr (CmpD src1 src2));
9790 effect(KILL rax);
9791 ins_cost(200);
9792 format %{ "FLD $src1\n\t"
9793 "FCOMp $src2\n\t"
9794 "FNSTSW AX\n\t"
9795 "TEST AX,0x400\n\t"
9796 "JZ,s flags\n\t"
9797 "MOV AH,1\t# unordered treat as LT\n"
9798 "flags:\tSAHF" %}
9799 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
9800 ins_encode( Push_Reg_D(src1),
9801 OpcP, RegOpc(src2),
9802 fpu_flags);
9803 ins_pipe( pipe_slow );
9804 %}
9805
9806 // Compare vs zero into -1,0,1
9807 instruct cmpD_0(eRegI dst, regD src1, immD0 zero, eAXRegI rax, eFlagsReg cr) %{
9808 predicate(UseSSE<=1);
9809 match(Set dst (CmpD3 src1 zero));
9810 effect(KILL cr, KILL rax);
9811 ins_cost(280);
9812 format %{ "FTSTD $dst,$src1" %}
9813 opcode(0xE4, 0xD9);
9814 ins_encode( Push_Reg_D(src1),
9815 OpcS, OpcP, PopFPU,
9816 CmpF_Result(dst));
9817 ins_pipe( pipe_slow );
9818 %}
9819
9820 // Compare into -1,0,1
9821 instruct cmpD_reg(eRegI dst, regD src1, regD src2, eAXRegI rax, eFlagsReg cr) %{
9822 predicate(UseSSE<=1);
9823 match(Set dst (CmpD3 src1 src2));
9824 effect(KILL cr, KILL rax);
9825 ins_cost(300);
9826 format %{ "FCMPD $dst,$src1,$src2" %}
9827 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
9828 ins_encode( Push_Reg_D(src1),
9829 OpcP, RegOpc(src2),
9830 CmpF_Result(dst));
9831 ins_pipe( pipe_slow );
9832 %}
9833
9834 // float compare and set condition codes in EFLAGS by XMM regs
9835 instruct cmpXD_cc(eFlagsRegU cr, regXD dst, regXD src, eAXRegI rax) %{
9836 predicate(UseSSE>=2);
9837 match(Set cr (CmpD dst src));
9838 effect(KILL rax);
9839 ins_cost(125);
9840 format %{ "COMISD $dst,$src\n"
9841 "\tJNP exit\n"
9842 "\tMOV ah,1 // saw a NaN, set CF\n"
9843 "\tSAHF\n"
9844 "exit:\tNOP // avoid branch to branch" %}
9845 opcode(0x66, 0x0F, 0x2F);
9846 ins_encode(OpcP, OpcS, Opcode(tertiary), RegReg(dst, src), cmpF_P6_fixup);
9847 ins_pipe( pipe_slow );
9848 %}
9849
9850 instruct cmpXD_ccCF(eFlagsRegUCF cr, regXD dst, regXD src) %{
9851 predicate(UseSSE>=2);
9852 match(Set cr (CmpD dst src));
9853 ins_cost(100);
9854 format %{ "COMISD $dst,$src" %}
9855 opcode(0x66, 0x0F, 0x2F);
9856 ins_encode(OpcP, OpcS, Opcode(tertiary), RegReg(dst, src));
9857 ins_pipe( pipe_slow );
9858 %}
9859
9860 // float compare and set condition codes in EFLAGS by XMM regs
9861 instruct cmpXD_ccmem(eFlagsRegU cr, regXD dst, memory src, eAXRegI rax) %{
9862 predicate(UseSSE>=2);
9863 match(Set cr (CmpD dst (LoadD src)));
9864 effect(KILL rax);
9865 ins_cost(145);
9866 format %{ "COMISD $dst,$src\n"
9867 "\tJNP exit\n"
9868 "\tMOV ah,1 // saw a NaN, set CF\n"
9869 "\tSAHF\n"
9870 "exit:\tNOP // avoid branch to branch" %}
9871 opcode(0x66, 0x0F, 0x2F);
9872 ins_encode(OpcP, OpcS, Opcode(tertiary), RegMem(dst, src), cmpF_P6_fixup);
9873 ins_pipe( pipe_slow );
9874 %}
9875
9876 instruct cmpXD_ccmemCF(eFlagsRegUCF cr, regXD dst, memory src) %{
9877 predicate(UseSSE>=2);
9878 match(Set cr (CmpD dst (LoadD src)));
9879 ins_cost(100);
9880 format %{ "COMISD $dst,$src" %}
9881 opcode(0x66, 0x0F, 0x2F);
9882 ins_encode(OpcP, OpcS, Opcode(tertiary), RegMem(dst, src));
9883 ins_pipe( pipe_slow );
9884 %}
9885
9886 // Compare into -1,0,1 in XMM
9887 instruct cmpXD_reg(eRegI dst, regXD src1, regXD src2, eFlagsReg cr) %{
9888 predicate(UseSSE>=2);
9889 match(Set dst (CmpD3 src1 src2));
9890 effect(KILL cr);
9891 ins_cost(255);
9892 format %{ "XOR $dst,$dst\n"
9893 "\tCOMISD $src1,$src2\n"
9894 "\tJP,s nan\n"
9895 "\tJEQ,s exit\n"
9896 "\tJA,s inc\n"
9897 "nan:\tDEC $dst\n"
9898 "\tJMP,s exit\n"
9899 "inc:\tINC $dst\n"
9900 "exit:"
9901 %}
9902 opcode(0x66, 0x0F, 0x2F);
9903 ins_encode(Xor_Reg(dst), OpcP, OpcS, Opcode(tertiary), RegReg(src1, src2),
9904 CmpX_Result(dst));
9905 ins_pipe( pipe_slow );
9906 %}
9907
9908 // Compare into -1,0,1 in XMM and memory
9909 instruct cmpXD_regmem(eRegI dst, regXD src1, memory mem, eFlagsReg cr) %{
9910 predicate(UseSSE>=2);
9911 match(Set dst (CmpD3 src1 (LoadD mem)));
9912 effect(KILL cr);
9913 ins_cost(275);
9914 format %{ "COMISD $src1,$mem\n"
9915 "\tMOV $dst,0\t\t# do not blow flags\n"
9916 "\tJP,s nan\n"
9917 "\tJEQ,s exit\n"
9918 "\tJA,s inc\n"
9919 "nan:\tDEC $dst\n"
9920 "\tJMP,s exit\n"
9921 "inc:\tINC $dst\n"
9922 "exit:"
9923 %}
9924 opcode(0x66, 0x0F, 0x2F);
9925 ins_encode(OpcP, OpcS, Opcode(tertiary), RegMem(src1, mem),
9926 LdImmI(dst,0x0), CmpX_Result(dst));
9927 ins_pipe( pipe_slow );
9928 %}
9929
9930
9931 instruct subD_reg(regD dst, regD src) %{
9932 predicate (UseSSE <=1);
9933 match(Set dst (SubD dst src));
9934
9935 format %{ "FLD $src\n\t"
9936 "DSUBp $dst,ST" %}
9937 opcode(0xDE, 0x5); /* DE E8+i or DE /5 */
9938 ins_cost(150);
9939 ins_encode( Push_Reg_D(src),
9940 OpcP, RegOpc(dst) );
9941 ins_pipe( fpu_reg_reg );
9942 %}
9943
9944 instruct subD_reg_round(stackSlotD dst, regD src1, regD src2) %{
9945 predicate (UseSSE <=1);
9946 match(Set dst (RoundDouble (SubD src1 src2)));
9947 ins_cost(250);
9948
9949 format %{ "FLD $src2\n\t"
9950 "DSUB ST,$src1\n\t"
9951 "FSTP_D $dst\t# D-round" %}
9952 opcode(0xD8, 0x5);
9953 ins_encode( Push_Reg_D(src2),
9954 OpcP, RegOpc(src1), Pop_Mem_D(dst) );
9955 ins_pipe( fpu_mem_reg_reg );
9956 %}
9957
9958
9959 instruct subD_reg_mem(regD dst, memory src) %{
9960 predicate (UseSSE <=1);
9961 match(Set dst (SubD dst (LoadD src)));
9962 ins_cost(150);
9963
9964 format %{ "FLD $src\n\t"
9965 "DSUBp $dst,ST" %}
9966 opcode(0xDE, 0x5, 0xDD); /* DE C0+i */ /* LoadD DD /0 */
9967 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
9968 OpcP, RegOpc(dst) );
9969 ins_pipe( fpu_reg_mem );
9970 %}
9971
9972 instruct absD_reg(regDPR1 dst, regDPR1 src) %{
9973 predicate (UseSSE<=1);
9974 match(Set dst (AbsD src));
9975 ins_cost(100);
9976 format %{ "FABS" %}
9977 opcode(0xE1, 0xD9);
9978 ins_encode( OpcS, OpcP );
9979 ins_pipe( fpu_reg_reg );
9980 %}
9981
9982 instruct absXD_reg( regXD dst ) %{
9983 predicate(UseSSE>=2);
9984 match(Set dst (AbsD dst));
9985 format %{ "ANDPD $dst,[0x7FFFFFFFFFFFFFFF]\t# ABS D by sign masking" %}
9986 ins_encode( AbsXD_encoding(dst));
9987 ins_pipe( pipe_slow );
9988 %}
9989
9990 instruct negD_reg(regDPR1 dst, regDPR1 src) %{
9991 predicate(UseSSE<=1);
9992 match(Set dst (NegD src));
9993 ins_cost(100);
9994 format %{ "FCHS" %}
9995 opcode(0xE0, 0xD9);
9996 ins_encode( OpcS, OpcP );
9997 ins_pipe( fpu_reg_reg );
9998 %}
9999
10000 instruct negXD_reg( regXD dst ) %{
10001 predicate(UseSSE>=2);
10002 match(Set dst (NegD dst));
10003 format %{ "XORPD $dst,[0x8000000000000000]\t# CHS D by sign flipping" %}
10004 ins_encode %{
10005 __ xorpd($dst$$XMMRegister,
10006 ExternalAddress((address)double_signflip_pool));
10007 %}
10008 ins_pipe( pipe_slow );
10009 %}
10010
10011 instruct addD_reg(regD dst, regD src) %{
10012 predicate(UseSSE<=1);
10013 match(Set dst (AddD dst src));
10014 format %{ "FLD $src\n\t"
10015 "DADD $dst,ST" %}
10016 size(4);
10017 ins_cost(150);
10018 opcode(0xDE, 0x0); /* DE C0+i or DE /0*/
10019 ins_encode( Push_Reg_D(src),
10020 OpcP, RegOpc(dst) );
10021 ins_pipe( fpu_reg_reg );
10022 %}
10023
10024
10025 instruct addD_reg_round(stackSlotD dst, regD src1, regD src2) %{
10026 predicate(UseSSE<=1);
10027 match(Set dst (RoundDouble (AddD src1 src2)));
10028 ins_cost(250);
10029
10030 format %{ "FLD $src2\n\t"
10031 "DADD ST,$src1\n\t"
10032 "FSTP_D $dst\t# D-round" %}
10033 opcode(0xD8, 0x0); /* D8 C0+i or D8 /0*/
10034 ins_encode( Push_Reg_D(src2),
10035 OpcP, RegOpc(src1), Pop_Mem_D(dst) );
10036 ins_pipe( fpu_mem_reg_reg );
10037 %}
10038
10039
10040 instruct addD_reg_mem(regD dst, memory src) %{
10041 predicate(UseSSE<=1);
10042 match(Set dst (AddD dst (LoadD src)));
10043 ins_cost(150);
10044
10045 format %{ "FLD $src\n\t"
10046 "DADDp $dst,ST" %}
10047 opcode(0xDE, 0x0, 0xDD); /* DE C0+i */ /* LoadD DD /0 */
10048 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
10049 OpcP, RegOpc(dst) );
10050 ins_pipe( fpu_reg_mem );
10051 %}
10052
10053 // add-to-memory
10054 instruct addD_mem_reg(memory dst, regD src) %{
10055 predicate(UseSSE<=1);
10056 match(Set dst (StoreD dst (RoundDouble (AddD (LoadD dst) src))));
10057 ins_cost(150);
10058
10059 format %{ "FLD_D $dst\n\t"
10060 "DADD ST,$src\n\t"
10061 "FST_D $dst" %}
10062 opcode(0xDD, 0x0);
10063 ins_encode( Opcode(0xDD), RMopc_Mem(0x00,dst),
10064 Opcode(0xD8), RegOpc(src),
10065 set_instruction_start,
10066 Opcode(0xDD), RMopc_Mem(0x03,dst) );
10067 ins_pipe( fpu_reg_mem );
10068 %}
10069
10070 instruct addD_reg_imm1(regD dst, immD1 src) %{
10071 predicate(UseSSE<=1);
10072 match(Set dst (AddD dst src));
10073 ins_cost(125);
10074 format %{ "FLD1\n\t"
10075 "DADDp $dst,ST" %}
10076 opcode(0xDE, 0x00);
10077 ins_encode( LdImmD(src),
10078 OpcP, RegOpc(dst) );
10079 ins_pipe( fpu_reg );
10080 %}
10081
10082 instruct addD_reg_imm(regD dst, immD src) %{
10083 predicate(UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 );
10084 match(Set dst (AddD dst src));
10085 ins_cost(200);
10086 format %{ "FLD_D [$src]\n\t"
10087 "DADDp $dst,ST" %}
10088 opcode(0xDE, 0x00); /* DE /0 */
10089 ins_encode( LdImmD(src),
10090 OpcP, RegOpc(dst));
10091 ins_pipe( fpu_reg_mem );
10092 %}
10093
10094 instruct addD_reg_imm_round(stackSlotD dst, regD src, immD con) %{
10095 predicate(UseSSE<=1 && _kids[0]->_kids[1]->_leaf->getd() != 0.0 && _kids[0]->_kids[1]->_leaf->getd() != 1.0 );
10096 match(Set dst (RoundDouble (AddD src con)));
10097 ins_cost(200);
10098 format %{ "FLD_D [$con]\n\t"
10099 "DADD ST,$src\n\t"
10100 "FSTP_D $dst\t# D-round" %}
10101 opcode(0xD8, 0x00); /* D8 /0 */
10102 ins_encode( LdImmD(con),
10103 OpcP, RegOpc(src), Pop_Mem_D(dst));
10104 ins_pipe( fpu_mem_reg_con );
10105 %}
10106
10107 // Add two double precision floating point values in xmm
10108 instruct addXD_reg(regXD dst, regXD src) %{
10109 predicate(UseSSE>=2);
10110 match(Set dst (AddD dst src));
10111 format %{ "ADDSD $dst,$src" %}
10112 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x58), RegReg(dst, src));
10113 ins_pipe( pipe_slow );
10114 %}
10115
10116 instruct addXD_imm(regXD dst, immXD con) %{
10117 predicate(UseSSE>=2);
10118 match(Set dst (AddD dst con));
10119 format %{ "ADDSD $dst,[$con]" %}
10120 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x58), LdImmXD(dst, con) );
10121 ins_pipe( pipe_slow );
10122 %}
10123
10124 instruct addXD_mem(regXD dst, memory mem) %{
10125 predicate(UseSSE>=2);
10126 match(Set dst (AddD dst (LoadD mem)));
10127 format %{ "ADDSD $dst,$mem" %}
10128 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x58), RegMem(dst,mem));
10129 ins_pipe( pipe_slow );
10130 %}
10131
10132 // Sub two double precision floating point values in xmm
10133 instruct subXD_reg(regXD dst, regXD src) %{
10134 predicate(UseSSE>=2);
10135 match(Set dst (SubD dst src));
10136 format %{ "SUBSD $dst,$src" %}
10137 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5C), RegReg(dst, src));
10138 ins_pipe( pipe_slow );
10139 %}
10140
10141 instruct subXD_imm(regXD dst, immXD con) %{
10142 predicate(UseSSE>=2);
10143 match(Set dst (SubD dst con));
10144 format %{ "SUBSD $dst,[$con]" %}
10145 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5C), LdImmXD(dst, con) );
10146 ins_pipe( pipe_slow );
10147 %}
10148
10149 instruct subXD_mem(regXD dst, memory mem) %{
10150 predicate(UseSSE>=2);
10151 match(Set dst (SubD dst (LoadD mem)));
10152 format %{ "SUBSD $dst,$mem" %}
10153 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5C), RegMem(dst,mem));
10154 ins_pipe( pipe_slow );
10155 %}
10156
10157 // Mul two double precision floating point values in xmm
10158 instruct mulXD_reg(regXD dst, regXD src) %{
10159 predicate(UseSSE>=2);
10160 match(Set dst (MulD dst src));
10161 format %{ "MULSD $dst,$src" %}
10162 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x59), RegReg(dst, src));
10163 ins_pipe( pipe_slow );
10164 %}
10165
10166 instruct mulXD_imm(regXD dst, immXD con) %{
10167 predicate(UseSSE>=2);
10168 match(Set dst (MulD dst con));
10169 format %{ "MULSD $dst,[$con]" %}
10170 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x59), LdImmXD(dst, con) );
10171 ins_pipe( pipe_slow );
10172 %}
10173
10174 instruct mulXD_mem(regXD dst, memory mem) %{
10175 predicate(UseSSE>=2);
10176 match(Set dst (MulD dst (LoadD mem)));
10177 format %{ "MULSD $dst,$mem" %}
10178 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x59), RegMem(dst,mem));
10179 ins_pipe( pipe_slow );
10180 %}
10181
10182 // Div two double precision floating point values in xmm
10183 instruct divXD_reg(regXD dst, regXD src) %{
10184 predicate(UseSSE>=2);
10185 match(Set dst (DivD dst src));
10186 format %{ "DIVSD $dst,$src" %}
10187 opcode(0xF2, 0x0F, 0x5E);
10188 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5E), RegReg(dst, src));
10189 ins_pipe( pipe_slow );
10190 %}
10191
10192 instruct divXD_imm(regXD dst, immXD con) %{
10193 predicate(UseSSE>=2);
10194 match(Set dst (DivD dst con));
10195 format %{ "DIVSD $dst,[$con]" %}
10196 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5E), LdImmXD(dst, con));
10197 ins_pipe( pipe_slow );
10198 %}
10199
10200 instruct divXD_mem(regXD dst, memory mem) %{
10201 predicate(UseSSE>=2);
10202 match(Set dst (DivD dst (LoadD mem)));
10203 format %{ "DIVSD $dst,$mem" %}
10204 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5E), RegMem(dst,mem));
10205 ins_pipe( pipe_slow );
10206 %}
10207
10208
10209 instruct mulD_reg(regD dst, regD src) %{
10210 predicate(UseSSE<=1);
10211 match(Set dst (MulD dst src));
10212 format %{ "FLD $src\n\t"
10213 "DMULp $dst,ST" %}
10214 opcode(0xDE, 0x1); /* DE C8+i or DE /1*/
10215 ins_cost(150);
10216 ins_encode( Push_Reg_D(src),
10217 OpcP, RegOpc(dst) );
10218 ins_pipe( fpu_reg_reg );
10219 %}
10220
10221 // Strict FP instruction biases argument before multiply then
10222 // biases result to avoid double rounding of subnormals.
10223 //
10224 // scale arg1 by multiplying arg1 by 2^(-15360)
10225 // load arg2
10226 // multiply scaled arg1 by arg2
10227 // rescale product by 2^(15360)
10228 //
10229 instruct strictfp_mulD_reg(regDPR1 dst, regnotDPR1 src) %{
10230 predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() );
10231 match(Set dst (MulD dst src));
10232 ins_cost(1); // Select this instruction for all strict FP double multiplies
10233
10234 format %{ "FLD StubRoutines::_fpu_subnormal_bias1\n\t"
10235 "DMULp $dst,ST\n\t"
10236 "FLD $src\n\t"
10237 "DMULp $dst,ST\n\t"
10238 "FLD StubRoutines::_fpu_subnormal_bias2\n\t"
10239 "DMULp $dst,ST\n\t" %}
10240 opcode(0xDE, 0x1); /* DE C8+i or DE /1*/
10241 ins_encode( strictfp_bias1(dst),
10242 Push_Reg_D(src),
10243 OpcP, RegOpc(dst),
10244 strictfp_bias2(dst) );
10245 ins_pipe( fpu_reg_reg );
10246 %}
10247
10248 instruct mulD_reg_imm(regD dst, immD src) %{
10249 predicate( UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 );
10250 match(Set dst (MulD dst src));
10251 ins_cost(200);
10252 format %{ "FLD_D [$src]\n\t"
10253 "DMULp $dst,ST" %}
10254 opcode(0xDE, 0x1); /* DE /1 */
10255 ins_encode( LdImmD(src),
10256 OpcP, RegOpc(dst) );
10257 ins_pipe( fpu_reg_mem );
10258 %}
10259
10260
10261 instruct mulD_reg_mem(regD dst, memory src) %{
10262 predicate( UseSSE<=1 );
10263 match(Set dst (MulD dst (LoadD src)));
10264 ins_cost(200);
10265 format %{ "FLD_D $src\n\t"
10266 "DMULp $dst,ST" %}
10267 opcode(0xDE, 0x1, 0xDD); /* DE C8+i or DE /1*/ /* LoadD DD /0 */
10268 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
10269 OpcP, RegOpc(dst) );
10270 ins_pipe( fpu_reg_mem );
10271 %}
10272
10273 //
10274 // Cisc-alternate to reg-reg multiply
10275 instruct mulD_reg_mem_cisc(regD dst, regD src, memory mem) %{
10276 predicate( UseSSE<=1 );
10277 match(Set dst (MulD src (LoadD mem)));
10278 ins_cost(250);
10279 format %{ "FLD_D $mem\n\t"
10280 "DMUL ST,$src\n\t"
10281 "FSTP_D $dst" %}
10282 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */ /* LoadD D9 /0 */
10283 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem),
10284 OpcReg_F(src),
10285 Pop_Reg_D(dst) );
10286 ins_pipe( fpu_reg_reg_mem );
10287 %}
10288
10289
10290 // MACRO3 -- addD a mulD
10291 // This instruction is a '2-address' instruction in that the result goes
10292 // back to src2. This eliminates a move from the macro; possibly the
10293 // register allocator will have to add it back (and maybe not).
10294 instruct addD_mulD_reg(regD src2, regD src1, regD src0) %{
10295 predicate( UseSSE<=1 );
10296 match(Set src2 (AddD (MulD src0 src1) src2));
10297 format %{ "FLD $src0\t# ===MACRO3d===\n\t"
10298 "DMUL ST,$src1\n\t"
10299 "DADDp $src2,ST" %}
10300 ins_cost(250);
10301 opcode(0xDD); /* LoadD DD /0 */
10302 ins_encode( Push_Reg_F(src0),
10303 FMul_ST_reg(src1),
10304 FAddP_reg_ST(src2) );
10305 ins_pipe( fpu_reg_reg_reg );
10306 %}
10307
10308
10309 // MACRO3 -- subD a mulD
10310 instruct subD_mulD_reg(regD src2, regD src1, regD src0) %{
10311 predicate( UseSSE<=1 );
10312 match(Set src2 (SubD (MulD src0 src1) src2));
10313 format %{ "FLD $src0\t# ===MACRO3d===\n\t"
10314 "DMUL ST,$src1\n\t"
10315 "DSUBRp $src2,ST" %}
10316 ins_cost(250);
10317 ins_encode( Push_Reg_F(src0),
10318 FMul_ST_reg(src1),
10319 Opcode(0xDE), Opc_plus(0xE0,src2));
10320 ins_pipe( fpu_reg_reg_reg );
10321 %}
10322
10323
10324 instruct divD_reg(regD dst, regD src) %{
10325 predicate( UseSSE<=1 );
10326 match(Set dst (DivD dst src));
10327
10328 format %{ "FLD $src\n\t"
10329 "FDIVp $dst,ST" %}
10330 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
10331 ins_cost(150);
10332 ins_encode( Push_Reg_D(src),
10333 OpcP, RegOpc(dst) );
10334 ins_pipe( fpu_reg_reg );
10335 %}
10336
10337 // Strict FP instruction biases argument before division then
10338 // biases result, to avoid double rounding of subnormals.
10339 //
10340 // scale dividend by multiplying dividend by 2^(-15360)
10341 // load divisor
10342 // divide scaled dividend by divisor
10343 // rescale quotient by 2^(15360)
10344 //
10345 instruct strictfp_divD_reg(regDPR1 dst, regnotDPR1 src) %{
10346 predicate (UseSSE<=1);
10347 match(Set dst (DivD dst src));
10348 predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() );
10349 ins_cost(01);
10350
10351 format %{ "FLD StubRoutines::_fpu_subnormal_bias1\n\t"
10352 "DMULp $dst,ST\n\t"
10353 "FLD $src\n\t"
10354 "FDIVp $dst,ST\n\t"
10355 "FLD StubRoutines::_fpu_subnormal_bias2\n\t"
10356 "DMULp $dst,ST\n\t" %}
10357 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
10358 ins_encode( strictfp_bias1(dst),
10359 Push_Reg_D(src),
10360 OpcP, RegOpc(dst),
10361 strictfp_bias2(dst) );
10362 ins_pipe( fpu_reg_reg );
10363 %}
10364
10365 instruct divD_reg_round(stackSlotD dst, regD src1, regD src2) %{
10366 predicate( UseSSE<=1 && !(Compile::current()->has_method() && Compile::current()->method()->is_strict()) );
10367 match(Set dst (RoundDouble (DivD src1 src2)));
10368
10369 format %{ "FLD $src1\n\t"
10370 "FDIV ST,$src2\n\t"
10371 "FSTP_D $dst\t# D-round" %}
10372 opcode(0xD8, 0x6); /* D8 F0+i or D8 /6 */
10373 ins_encode( Push_Reg_D(src1),
10374 OpcP, RegOpc(src2), Pop_Mem_D(dst) );
10375 ins_pipe( fpu_mem_reg_reg );
10376 %}
10377
10378
10379 instruct modD_reg(regD dst, regD src, eAXRegI rax, eFlagsReg cr) %{
10380 predicate(UseSSE<=1);
10381 match(Set dst (ModD dst src));
10382 effect(KILL rax, KILL cr); // emitModD() uses EAX and EFLAGS
10383
10384 format %{ "DMOD $dst,$src" %}
10385 ins_cost(250);
10386 ins_encode(Push_Reg_Mod_D(dst, src),
10387 emitModD(),
10388 Push_Result_Mod_D(src),
10389 Pop_Reg_D(dst));
10390 ins_pipe( pipe_slow );
10391 %}
10392
10393 instruct modXD_reg(regXD dst, regXD src0, regXD src1, eAXRegI rax, eFlagsReg cr) %{
10394 predicate(UseSSE>=2);
10395 match(Set dst (ModD src0 src1));
10396 effect(KILL rax, KILL cr);
10397
10398 format %{ "SUB ESP,8\t # DMOD\n"
10399 "\tMOVSD [ESP+0],$src1\n"
10400 "\tFLD_D [ESP+0]\n"
10401 "\tMOVSD [ESP+0],$src0\n"
10402 "\tFLD_D [ESP+0]\n"
10403 "loop:\tFPREM\n"
10404 "\tFWAIT\n"
10405 "\tFNSTSW AX\n"
10406 "\tSAHF\n"
10407 "\tJP loop\n"
10408 "\tFSTP_D [ESP+0]\n"
10409 "\tMOVSD $dst,[ESP+0]\n"
10410 "\tADD ESP,8\n"
10411 "\tFSTP ST0\t # Restore FPU Stack"
10412 %}
10413 ins_cost(250);
10414 ins_encode( Push_ModD_encoding(src0, src1), emitModD(), Push_ResultXD(dst), PopFPU);
10415 ins_pipe( pipe_slow );
10416 %}
10417
10418 instruct sinD_reg(regDPR1 dst, regDPR1 src) %{
10419 predicate (UseSSE<=1);
10420 match(Set dst (SinD src));
10421 ins_cost(1800);
10422 format %{ "DSIN $dst" %}
10423 opcode(0xD9, 0xFE);
10424 ins_encode( OpcP, OpcS );
10425 ins_pipe( pipe_slow );
10426 %}
10427
10428 instruct sinXD_reg(regXD dst, eFlagsReg cr) %{
10429 predicate (UseSSE>=2);
10430 match(Set dst (SinD dst));
10431 effect(KILL cr); // Push_{Src|Result}XD() uses "{SUB|ADD} ESP,8"
10432 ins_cost(1800);
10433 format %{ "DSIN $dst" %}
10434 opcode(0xD9, 0xFE);
10435 ins_encode( Push_SrcXD(dst), OpcP, OpcS, Push_ResultXD(dst) );
10436 ins_pipe( pipe_slow );
10437 %}
10438
10439 instruct cosD_reg(regDPR1 dst, regDPR1 src) %{
10440 predicate (UseSSE<=1);
10441 match(Set dst (CosD src));
10442 ins_cost(1800);
10443 format %{ "DCOS $dst" %}
10444 opcode(0xD9, 0xFF);
10445 ins_encode( OpcP, OpcS );
10446 ins_pipe( pipe_slow );
10447 %}
10448
10449 instruct cosXD_reg(regXD dst, eFlagsReg cr) %{
10450 predicate (UseSSE>=2);
10451 match(Set dst (CosD dst));
10452 effect(KILL cr); // Push_{Src|Result}XD() uses "{SUB|ADD} ESP,8"
10453 ins_cost(1800);
10454 format %{ "DCOS $dst" %}
10455 opcode(0xD9, 0xFF);
10456 ins_encode( Push_SrcXD(dst), OpcP, OpcS, Push_ResultXD(dst) );
10457 ins_pipe( pipe_slow );
10458 %}
10459
10460 instruct tanD_reg(regDPR1 dst, regDPR1 src) %{
10461 predicate (UseSSE<=1);
10462 match(Set dst(TanD src));
10463 format %{ "DTAN $dst" %}
10464 ins_encode( Opcode(0xD9), Opcode(0xF2), // fptan
10465 Opcode(0xDD), Opcode(0xD8)); // fstp st
10466 ins_pipe( pipe_slow );
10467 %}
10468
10469 instruct tanXD_reg(regXD dst, eFlagsReg cr) %{
10470 predicate (UseSSE>=2);
10471 match(Set dst(TanD dst));
10472 effect(KILL cr); // Push_{Src|Result}XD() uses "{SUB|ADD} ESP,8"
10473 format %{ "DTAN $dst" %}
10474 ins_encode( Push_SrcXD(dst),
10475 Opcode(0xD9), Opcode(0xF2), // fptan
10476 Opcode(0xDD), Opcode(0xD8), // fstp st
10477 Push_ResultXD(dst) );
10478 ins_pipe( pipe_slow );
10479 %}
10480
10481 instruct atanD_reg(regD dst, regD src) %{
10482 predicate (UseSSE<=1);
10483 match(Set dst(AtanD dst src));
10484 format %{ "DATA $dst,$src" %}
10485 opcode(0xD9, 0xF3);
10486 ins_encode( Push_Reg_D(src),
10487 OpcP, OpcS, RegOpc(dst) );
10488 ins_pipe( pipe_slow );
10489 %}
10490
10491 instruct atanXD_reg(regXD dst, regXD src, eFlagsReg cr) %{
10492 predicate (UseSSE>=2);
10493 match(Set dst(AtanD dst src));
10494 effect(KILL cr); // Push_{Src|Result}XD() uses "{SUB|ADD} ESP,8"
10495 format %{ "DATA $dst,$src" %}
10496 opcode(0xD9, 0xF3);
10497 ins_encode( Push_SrcXD(src),
10498 OpcP, OpcS, Push_ResultXD(dst) );
10499 ins_pipe( pipe_slow );
10500 %}
10501
10502 instruct sqrtD_reg(regD dst, regD src) %{
10503 predicate (UseSSE<=1);
10504 match(Set dst (SqrtD src));
10505 format %{ "DSQRT $dst,$src" %}
10506 opcode(0xFA, 0xD9);
10507 ins_encode( Push_Reg_D(src),
10508 OpcS, OpcP, Pop_Reg_D(dst) );
10509 ins_pipe( pipe_slow );
10510 %}
10511
10512 instruct powD_reg(regD X, regDPR1 Y, eAXRegI rax, eBXRegI rbx, eCXRegI rcx) %{
10513 predicate (UseSSE<=1);
10514 match(Set Y (PowD X Y)); // Raise X to the Yth power
10515 effect(KILL rax, KILL rbx, KILL rcx);
10516 format %{ "SUB ESP,8\t\t# Fast-path POW encoding\n\t"
10517 "FLD_D $X\n\t"
10518 "FYL2X \t\t\t# Q=Y*ln2(X)\n\t"
10519
10520 "FDUP \t\t\t# Q Q\n\t"
10521 "FRNDINT\t\t\t# int(Q) Q\n\t"
10522 "FSUB ST(1),ST(0)\t# int(Q) frac(Q)\n\t"
10523 "FISTP dword [ESP]\n\t"
10524 "F2XM1 \t\t\t# 2^frac(Q)-1 int(Q)\n\t"
10525 "FLD1 \t\t\t# 1 2^frac(Q)-1 int(Q)\n\t"
10526 "FADDP \t\t\t# 2^frac(Q) int(Q)\n\t" // could use FADD [1.000] instead
10527 "MOV EAX,[ESP]\t# Pick up int(Q)\n\t"
10528 "MOV ECX,0xFFFFF800\t# Overflow mask\n\t"
10529 "ADD EAX,1023\t\t# Double exponent bias\n\t"
10530 "MOV EBX,EAX\t\t# Preshifted biased expo\n\t"
10531 "SHL EAX,20\t\t# Shift exponent into place\n\t"
10532 "TEST EBX,ECX\t\t# Check for overflow\n\t"
10533 "CMOVne EAX,ECX\t\t# If overflow, stuff NaN into EAX\n\t"
10534 "MOV [ESP+4],EAX\t# Marshal 64-bit scaling double\n\t"
10535 "MOV [ESP+0],0\n\t"
10536 "FMUL ST(0),[ESP+0]\t# Scale\n\t"
10537
10538 "ADD ESP,8"
10539 %}
10540 ins_encode( push_stack_temp_qword,
10541 Push_Reg_D(X),
10542 Opcode(0xD9), Opcode(0xF1), // fyl2x
10543 pow_exp_core_encoding,
10544 pop_stack_temp_qword);
10545 ins_pipe( pipe_slow );
10546 %}
10547
10548 instruct powXD_reg(regXD dst, regXD src0, regXD src1, regDPR1 tmp1, eAXRegI rax, eBXRegI rbx, eCXRegI rcx ) %{
10549 predicate (UseSSE>=2);
10550 match(Set dst (PowD src0 src1)); // Raise src0 to the src1'th power
10551 effect(KILL tmp1, KILL rax, KILL rbx, KILL rcx );
10552 format %{ "SUB ESP,8\t\t# Fast-path POW encoding\n\t"
10553 "MOVSD [ESP],$src1\n\t"
10554 "FLD FPR1,$src1\n\t"
10555 "MOVSD [ESP],$src0\n\t"
10556 "FLD FPR1,$src0\n\t"
10557 "FYL2X \t\t\t# Q=Y*ln2(X)\n\t"
10558
10559 "FDUP \t\t\t# Q Q\n\t"
10560 "FRNDINT\t\t\t# int(Q) Q\n\t"
10561 "FSUB ST(1),ST(0)\t# int(Q) frac(Q)\n\t"
10562 "FISTP dword [ESP]\n\t"
10563 "F2XM1 \t\t\t# 2^frac(Q)-1 int(Q)\n\t"
10564 "FLD1 \t\t\t# 1 2^frac(Q)-1 int(Q)\n\t"
10565 "FADDP \t\t\t# 2^frac(Q) int(Q)\n\t" // could use FADD [1.000] instead
10566 "MOV EAX,[ESP]\t# Pick up int(Q)\n\t"
10567 "MOV ECX,0xFFFFF800\t# Overflow mask\n\t"
10568 "ADD EAX,1023\t\t# Double exponent bias\n\t"
10569 "MOV EBX,EAX\t\t# Preshifted biased expo\n\t"
10570 "SHL EAX,20\t\t# Shift exponent into place\n\t"
10571 "TEST EBX,ECX\t\t# Check for overflow\n\t"
10572 "CMOVne EAX,ECX\t\t# If overflow, stuff NaN into EAX\n\t"
10573 "MOV [ESP+4],EAX\t# Marshal 64-bit scaling double\n\t"
10574 "MOV [ESP+0],0\n\t"
10575 "FMUL ST(0),[ESP+0]\t# Scale\n\t"
10576
10577 "FST_D [ESP]\n\t"
10578 "MOVSD $dst,[ESP]\n\t"
10579 "ADD ESP,8"
10580 %}
10581 ins_encode( push_stack_temp_qword,
10582 push_xmm_to_fpr1(src1),
10583 push_xmm_to_fpr1(src0),
10584 Opcode(0xD9), Opcode(0xF1), // fyl2x
10585 pow_exp_core_encoding,
10586 Push_ResultXD(dst) );
10587 ins_pipe( pipe_slow );
10588 %}
10589
10590
10591 instruct expD_reg(regDPR1 dpr1, eAXRegI rax, eBXRegI rbx, eCXRegI rcx) %{
10592 predicate (UseSSE<=1);
10593 match(Set dpr1 (ExpD dpr1));
10594 effect(KILL rax, KILL rbx, KILL rcx);
10595 format %{ "SUB ESP,8\t\t# Fast-path EXP encoding"
10596 "FLDL2E \t\t\t# Ld log2(e) X\n\t"
10597 "FMULP \t\t\t# Q=X*log2(e)\n\t"
10598
10599 "FDUP \t\t\t# Q Q\n\t"
10600 "FRNDINT\t\t\t# int(Q) Q\n\t"
10601 "FSUB ST(1),ST(0)\t# int(Q) frac(Q)\n\t"
10602 "FISTP dword [ESP]\n\t"
10603 "F2XM1 \t\t\t# 2^frac(Q)-1 int(Q)\n\t"
10604 "FLD1 \t\t\t# 1 2^frac(Q)-1 int(Q)\n\t"
10605 "FADDP \t\t\t# 2^frac(Q) int(Q)\n\t" // could use FADD [1.000] instead
10606 "MOV EAX,[ESP]\t# Pick up int(Q)\n\t"
10607 "MOV ECX,0xFFFFF800\t# Overflow mask\n\t"
10608 "ADD EAX,1023\t\t# Double exponent bias\n\t"
10609 "MOV EBX,EAX\t\t# Preshifted biased expo\n\t"
10610 "SHL EAX,20\t\t# Shift exponent into place\n\t"
10611 "TEST EBX,ECX\t\t# Check for overflow\n\t"
10612 "CMOVne EAX,ECX\t\t# If overflow, stuff NaN into EAX\n\t"
10613 "MOV [ESP+4],EAX\t# Marshal 64-bit scaling double\n\t"
10614 "MOV [ESP+0],0\n\t"
10615 "FMUL ST(0),[ESP+0]\t# Scale\n\t"
10616
10617 "ADD ESP,8"
10618 %}
10619 ins_encode( push_stack_temp_qword,
10620 Opcode(0xD9), Opcode(0xEA), // fldl2e
10621 Opcode(0xDE), Opcode(0xC9), // fmulp
10622 pow_exp_core_encoding,
10623 pop_stack_temp_qword);
10624 ins_pipe( pipe_slow );
10625 %}
10626
10627 instruct expXD_reg(regXD dst, regXD src, regDPR1 tmp1, eAXRegI rax, eBXRegI rbx, eCXRegI rcx) %{
10628 predicate (UseSSE>=2);
10629 match(Set dst (ExpD src));
10630 effect(KILL tmp1, KILL rax, KILL rbx, KILL rcx);
10631 format %{ "SUB ESP,8\t\t# Fast-path EXP encoding\n\t"
10632 "MOVSD [ESP],$src\n\t"
10633 "FLDL2E \t\t\t# Ld log2(e) X\n\t"
10634 "FMULP \t\t\t# Q=X*log2(e) X\n\t"
10635
10636 "FDUP \t\t\t# Q Q\n\t"
10637 "FRNDINT\t\t\t# int(Q) Q\n\t"
10638 "FSUB ST(1),ST(0)\t# int(Q) frac(Q)\n\t"
10639 "FISTP dword [ESP]\n\t"
10640 "F2XM1 \t\t\t# 2^frac(Q)-1 int(Q)\n\t"
10641 "FLD1 \t\t\t# 1 2^frac(Q)-1 int(Q)\n\t"
10642 "FADDP \t\t\t# 2^frac(Q) int(Q)\n\t" // could use FADD [1.000] instead
10643 "MOV EAX,[ESP]\t# Pick up int(Q)\n\t"
10644 "MOV ECX,0xFFFFF800\t# Overflow mask\n\t"
10645 "ADD EAX,1023\t\t# Double exponent bias\n\t"
10646 "MOV EBX,EAX\t\t# Preshifted biased expo\n\t"
10647 "SHL EAX,20\t\t# Shift exponent into place\n\t"
10648 "TEST EBX,ECX\t\t# Check for overflow\n\t"
10649 "CMOVne EAX,ECX\t\t# If overflow, stuff NaN into EAX\n\t"
10650 "MOV [ESP+4],EAX\t# Marshal 64-bit scaling double\n\t"
10651 "MOV [ESP+0],0\n\t"
10652 "FMUL ST(0),[ESP+0]\t# Scale\n\t"
10653
10654 "FST_D [ESP]\n\t"
10655 "MOVSD $dst,[ESP]\n\t"
10656 "ADD ESP,8"
10657 %}
10658 ins_encode( Push_SrcXD(src),
10659 Opcode(0xD9), Opcode(0xEA), // fldl2e
10660 Opcode(0xDE), Opcode(0xC9), // fmulp
10661 pow_exp_core_encoding,
10662 Push_ResultXD(dst) );
10663 ins_pipe( pipe_slow );
10664 %}
10665
10666
10667
10668 instruct log10D_reg(regDPR1 dst, regDPR1 src) %{
10669 predicate (UseSSE<=1);
10670 // The source Double operand on FPU stack
10671 match(Set dst (Log10D src));
10672 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number
10673 // fxch ; swap ST(0) with ST(1)
10674 // fyl2x ; compute log_10(2) * log_2(x)
10675 format %{ "FLDLG2 \t\t\t#Log10\n\t"
10676 "FXCH \n\t"
10677 "FYL2X \t\t\t# Q=Log10*Log_2(x)"
10678 %}
10679 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2
10680 Opcode(0xD9), Opcode(0xC9), // fxch
10681 Opcode(0xD9), Opcode(0xF1)); // fyl2x
10682
10683 ins_pipe( pipe_slow );
10684 %}
10685
10686 instruct log10XD_reg(regXD dst, regXD src, eFlagsReg cr) %{
10687 predicate (UseSSE>=2);
10688 effect(KILL cr);
10689 match(Set dst (Log10D src));
10690 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number
10691 // fyl2x ; compute log_10(2) * log_2(x)
10692 format %{ "FLDLG2 \t\t\t#Log10\n\t"
10693 "FYL2X \t\t\t# Q=Log10*Log_2(x)"
10694 %}
10695 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2
10696 Push_SrcXD(src),
10697 Opcode(0xD9), Opcode(0xF1), // fyl2x
10698 Push_ResultXD(dst));
10699
10700 ins_pipe( pipe_slow );
10701 %}
10702
10703 instruct logD_reg(regDPR1 dst, regDPR1 src) %{
10704 predicate (UseSSE<=1);
10705 // The source Double operand on FPU stack
10706 match(Set dst (LogD src));
10707 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number
10708 // fxch ; swap ST(0) with ST(1)
10709 // fyl2x ; compute log_e(2) * log_2(x)
10710 format %{ "FLDLN2 \t\t\t#Log_e\n\t"
10711 "FXCH \n\t"
10712 "FYL2X \t\t\t# Q=Log_e*Log_2(x)"
10713 %}
10714 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2
10715 Opcode(0xD9), Opcode(0xC9), // fxch
10716 Opcode(0xD9), Opcode(0xF1)); // fyl2x
10717
10718 ins_pipe( pipe_slow );
10719 %}
10720
10721 instruct logXD_reg(regXD dst, regXD src, eFlagsReg cr) %{
10722 predicate (UseSSE>=2);
10723 effect(KILL cr);
10724 // The source and result Double operands in XMM registers
10725 match(Set dst (LogD src));
10726 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number
10727 // fyl2x ; compute log_e(2) * log_2(x)
10728 format %{ "FLDLN2 \t\t\t#Log_e\n\t"
10729 "FYL2X \t\t\t# Q=Log_e*Log_2(x)"
10730 %}
10731 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2
10732 Push_SrcXD(src),
10733 Opcode(0xD9), Opcode(0xF1), // fyl2x
10734 Push_ResultXD(dst));
10735 ins_pipe( pipe_slow );
10736 %}
10737
10738 //-------------Float Instructions-------------------------------
10739 // Float Math
10740
10741 // Code for float compare:
10742 // fcompp();
10743 // fwait(); fnstsw_ax();
10744 // sahf();
10745 // movl(dst, unordered_result);
10746 // jcc(Assembler::parity, exit);
10747 // movl(dst, less_result);
10748 // jcc(Assembler::below, exit);
10749 // movl(dst, equal_result);
10750 // jcc(Assembler::equal, exit);
10751 // movl(dst, greater_result);
10752 // exit:
10753
10754 // P6 version of float compare, sets condition codes in EFLAGS
10755 instruct cmpF_cc_P6(eFlagsRegU cr, regF src1, regF src2, eAXRegI rax) %{
10756 predicate(VM_Version::supports_cmov() && UseSSE == 0);
10757 match(Set cr (CmpF src1 src2));
10758 effect(KILL rax);
10759 ins_cost(150);
10760 format %{ "FLD $src1\n\t"
10761 "FUCOMIP ST,$src2 // P6 instruction\n\t"
10762 "JNP exit\n\t"
10763 "MOV ah,1 // saw a NaN, set CF (treat as LT)\n\t"
10764 "SAHF\n"
10765 "exit:\tNOP // avoid branch to branch" %}
10766 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
10767 ins_encode( Push_Reg_D(src1),
10768 OpcP, RegOpc(src2),
10769 cmpF_P6_fixup );
10770 ins_pipe( pipe_slow );
10771 %}
10772
10773 instruct cmpF_cc_P6CF(eFlagsRegUCF cr, regF src1, regF src2) %{
10774 predicate(VM_Version::supports_cmov() && UseSSE == 0);
10775 match(Set cr (CmpF src1 src2));
10776 ins_cost(100);
10777 format %{ "FLD $src1\n\t"
10778 "FUCOMIP ST,$src2 // P6 instruction" %}
10779 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
10780 ins_encode( Push_Reg_D(src1),
10781 OpcP, RegOpc(src2));
10782 ins_pipe( pipe_slow );
10783 %}
10784
10785
10786 // Compare & branch
10787 instruct cmpF_cc(eFlagsRegU cr, regF src1, regF src2, eAXRegI rax) %{
10788 predicate(UseSSE == 0);
10789 match(Set cr (CmpF src1 src2));
10790 effect(KILL rax);
10791 ins_cost(200);
10792 format %{ "FLD $src1\n\t"
10793 "FCOMp $src2\n\t"
10794 "FNSTSW AX\n\t"
10795 "TEST AX,0x400\n\t"
10796 "JZ,s flags\n\t"
10797 "MOV AH,1\t# unordered treat as LT\n"
10798 "flags:\tSAHF" %}
10799 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
10800 ins_encode( Push_Reg_D(src1),
10801 OpcP, RegOpc(src2),
10802 fpu_flags);
10803 ins_pipe( pipe_slow );
10804 %}
10805
10806 // Compare vs zero into -1,0,1
10807 instruct cmpF_0(eRegI dst, regF src1, immF0 zero, eAXRegI rax, eFlagsReg cr) %{
10808 predicate(UseSSE == 0);
10809 match(Set dst (CmpF3 src1 zero));
10810 effect(KILL cr, KILL rax);
10811 ins_cost(280);
10812 format %{ "FTSTF $dst,$src1" %}
10813 opcode(0xE4, 0xD9);
10814 ins_encode( Push_Reg_D(src1),
10815 OpcS, OpcP, PopFPU,
10816 CmpF_Result(dst));
10817 ins_pipe( pipe_slow );
10818 %}
10819
10820 // Compare into -1,0,1
10821 instruct cmpF_reg(eRegI dst, regF src1, regF src2, eAXRegI rax, eFlagsReg cr) %{
10822 predicate(UseSSE == 0);
10823 match(Set dst (CmpF3 src1 src2));
10824 effect(KILL cr, KILL rax);
10825 ins_cost(300);
10826 format %{ "FCMPF $dst,$src1,$src2" %}
10827 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
10828 ins_encode( Push_Reg_D(src1),
10829 OpcP, RegOpc(src2),
10830 CmpF_Result(dst));
10831 ins_pipe( pipe_slow );
10832 %}
10833
10834 // float compare and set condition codes in EFLAGS by XMM regs
10835 instruct cmpX_cc(eFlagsRegU cr, regX dst, regX src, eAXRegI rax) %{
10836 predicate(UseSSE>=1);
10837 match(Set cr (CmpF dst src));
10838 effect(KILL rax);
10839 ins_cost(145);
10840 format %{ "COMISS $dst,$src\n"
10841 "\tJNP exit\n"
10842 "\tMOV ah,1 // saw a NaN, set CF\n"
10843 "\tSAHF\n"
10844 "exit:\tNOP // avoid branch to branch" %}
10845 opcode(0x0F, 0x2F);
10846 ins_encode(OpcP, OpcS, RegReg(dst, src), cmpF_P6_fixup);
10847 ins_pipe( pipe_slow );
10848 %}
10849
10850 instruct cmpX_ccCF(eFlagsRegUCF cr, regX dst, regX src) %{
10851 predicate(UseSSE>=1);
10852 match(Set cr (CmpF dst src));
10853 ins_cost(100);
10854 format %{ "COMISS $dst,$src" %}
10855 opcode(0x0F, 0x2F);
10856 ins_encode(OpcP, OpcS, RegReg(dst, src));
10857 ins_pipe( pipe_slow );
10858 %}
10859
10860 // float compare and set condition codes in EFLAGS by XMM regs
10861 instruct cmpX_ccmem(eFlagsRegU cr, regX dst, memory src, eAXRegI rax) %{
10862 predicate(UseSSE>=1);
10863 match(Set cr (CmpF dst (LoadF src)));
10864 effect(KILL rax);
10865 ins_cost(165);
10866 format %{ "COMISS $dst,$src\n"
10867 "\tJNP exit\n"
10868 "\tMOV ah,1 // saw a NaN, set CF\n"
10869 "\tSAHF\n"
10870 "exit:\tNOP // avoid branch to branch" %}
10871 opcode(0x0F, 0x2F);
10872 ins_encode(OpcP, OpcS, RegMem(dst, src), cmpF_P6_fixup);
10873 ins_pipe( pipe_slow );
10874 %}
10875
10876 instruct cmpX_ccmemCF(eFlagsRegUCF cr, regX dst, memory src) %{
10877 predicate(UseSSE>=1);
10878 match(Set cr (CmpF dst (LoadF src)));
10879 ins_cost(100);
10880 format %{ "COMISS $dst,$src" %}
10881 opcode(0x0F, 0x2F);
10882 ins_encode(OpcP, OpcS, RegMem(dst, src));
10883 ins_pipe( pipe_slow );
10884 %}
10885
10886 // Compare into -1,0,1 in XMM
10887 instruct cmpX_reg(eRegI dst, regX src1, regX src2, eFlagsReg cr) %{
10888 predicate(UseSSE>=1);
10889 match(Set dst (CmpF3 src1 src2));
10890 effect(KILL cr);
10891 ins_cost(255);
10892 format %{ "XOR $dst,$dst\n"
10893 "\tCOMISS $src1,$src2\n"
10894 "\tJP,s nan\n"
10895 "\tJEQ,s exit\n"
10896 "\tJA,s inc\n"
10897 "nan:\tDEC $dst\n"
10898 "\tJMP,s exit\n"
10899 "inc:\tINC $dst\n"
10900 "exit:"
10901 %}
10902 opcode(0x0F, 0x2F);
10903 ins_encode(Xor_Reg(dst), OpcP, OpcS, RegReg(src1, src2), CmpX_Result(dst));
10904 ins_pipe( pipe_slow );
10905 %}
10906
10907 // Compare into -1,0,1 in XMM and memory
10908 instruct cmpX_regmem(eRegI dst, regX src1, memory mem, eFlagsReg cr) %{
10909 predicate(UseSSE>=1);
10910 match(Set dst (CmpF3 src1 (LoadF mem)));
10911 effect(KILL cr);
10912 ins_cost(275);
10913 format %{ "COMISS $src1,$mem\n"
10914 "\tMOV $dst,0\t\t# do not blow flags\n"
10915 "\tJP,s nan\n"
10916 "\tJEQ,s exit\n"
10917 "\tJA,s inc\n"
10918 "nan:\tDEC $dst\n"
10919 "\tJMP,s exit\n"
10920 "inc:\tINC $dst\n"
10921 "exit:"
10922 %}
10923 opcode(0x0F, 0x2F);
10924 ins_encode(OpcP, OpcS, RegMem(src1, mem), LdImmI(dst,0x0), CmpX_Result(dst));
10925 ins_pipe( pipe_slow );
10926 %}
10927
10928 // Spill to obtain 24-bit precision
10929 instruct subF24_reg(stackSlotF dst, regF src1, regF src2) %{
10930 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10931 match(Set dst (SubF src1 src2));
10932
10933 format %{ "FSUB $dst,$src1 - $src2" %}
10934 opcode(0xD8, 0x4); /* D8 E0+i or D8 /4 mod==0x3 ;; result in TOS */
10935 ins_encode( Push_Reg_F(src1),
10936 OpcReg_F(src2),
10937 Pop_Mem_F(dst) );
10938 ins_pipe( fpu_mem_reg_reg );
10939 %}
10940 //
10941 // This instruction does not round to 24-bits
10942 instruct subF_reg(regF dst, regF src) %{
10943 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10944 match(Set dst (SubF dst src));
10945
10946 format %{ "FSUB $dst,$src" %}
10947 opcode(0xDE, 0x5); /* DE E8+i or DE /5 */
10948 ins_encode( Push_Reg_F(src),
10949 OpcP, RegOpc(dst) );
10950 ins_pipe( fpu_reg_reg );
10951 %}
10952
10953 // Spill to obtain 24-bit precision
10954 instruct addF24_reg(stackSlotF dst, regF src1, regF src2) %{
10955 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10956 match(Set dst (AddF src1 src2));
10957
10958 format %{ "FADD $dst,$src1,$src2" %}
10959 opcode(0xD8, 0x0); /* D8 C0+i */
10960 ins_encode( Push_Reg_F(src2),
10961 OpcReg_F(src1),
10962 Pop_Mem_F(dst) );
10963 ins_pipe( fpu_mem_reg_reg );
10964 %}
10965 //
10966 // This instruction does not round to 24-bits
10967 instruct addF_reg(regF dst, regF src) %{
10968 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10969 match(Set dst (AddF dst src));
10970
10971 format %{ "FLD $src\n\t"
10972 "FADDp $dst,ST" %}
10973 opcode(0xDE, 0x0); /* DE C0+i or DE /0*/
10974 ins_encode( Push_Reg_F(src),
10975 OpcP, RegOpc(dst) );
10976 ins_pipe( fpu_reg_reg );
10977 %}
10978
10979 // Add two single precision floating point values in xmm
10980 instruct addX_reg(regX dst, regX src) %{
10981 predicate(UseSSE>=1);
10982 match(Set dst (AddF dst src));
10983 format %{ "ADDSS $dst,$src" %}
10984 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x58), RegReg(dst, src));
10985 ins_pipe( pipe_slow );
10986 %}
10987
10988 instruct addX_imm(regX dst, immXF con) %{
10989 predicate(UseSSE>=1);
10990 match(Set dst (AddF dst con));
10991 format %{ "ADDSS $dst,[$con]" %}
10992 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x58), LdImmX(dst, con) );
10993 ins_pipe( pipe_slow );
10994 %}
10995
10996 instruct addX_mem(regX dst, memory mem) %{
10997 predicate(UseSSE>=1);
10998 match(Set dst (AddF dst (LoadF mem)));
10999 format %{ "ADDSS $dst,$mem" %}
11000 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x58), RegMem(dst, mem));
11001 ins_pipe( pipe_slow );
11002 %}
11003
11004 // Subtract two single precision floating point values in xmm
11005 instruct subX_reg(regX dst, regX src) %{
11006 predicate(UseSSE>=1);
11007 match(Set dst (SubF dst src));
11008 format %{ "SUBSS $dst,$src" %}
11009 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5C), RegReg(dst, src));
11010 ins_pipe( pipe_slow );
11011 %}
11012
11013 instruct subX_imm(regX dst, immXF con) %{
11014 predicate(UseSSE>=1);
11015 match(Set dst (SubF dst con));
11016 format %{ "SUBSS $dst,[$con]" %}
11017 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5C), LdImmX(dst, con) );
11018 ins_pipe( pipe_slow );
11019 %}
11020
11021 instruct subX_mem(regX dst, memory mem) %{
11022 predicate(UseSSE>=1);
11023 match(Set dst (SubF dst (LoadF mem)));
11024 format %{ "SUBSS $dst,$mem" %}
11025 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5C), RegMem(dst,mem));
11026 ins_pipe( pipe_slow );
11027 %}
11028
11029 // Multiply two single precision floating point values in xmm
11030 instruct mulX_reg(regX dst, regX src) %{
11031 predicate(UseSSE>=1);
11032 match(Set dst (MulF dst src));
11033 format %{ "MULSS $dst,$src" %}
11034 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x59), RegReg(dst, src));
11035 ins_pipe( pipe_slow );
11036 %}
11037
11038 instruct mulX_imm(regX dst, immXF con) %{
11039 predicate(UseSSE>=1);
11040 match(Set dst (MulF dst con));
11041 format %{ "MULSS $dst,[$con]" %}
11042 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x59), LdImmX(dst, con) );
11043 ins_pipe( pipe_slow );
11044 %}
11045
11046 instruct mulX_mem(regX dst, memory mem) %{
11047 predicate(UseSSE>=1);
11048 match(Set dst (MulF dst (LoadF mem)));
11049 format %{ "MULSS $dst,$mem" %}
11050 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x59), RegMem(dst,mem));
11051 ins_pipe( pipe_slow );
11052 %}
11053
11054 // Divide two single precision floating point values in xmm
11055 instruct divX_reg(regX dst, regX src) %{
11056 predicate(UseSSE>=1);
11057 match(Set dst (DivF dst src));
11058 format %{ "DIVSS $dst,$src" %}
11059 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5E), RegReg(dst, src));
11060 ins_pipe( pipe_slow );
11061 %}
11062
11063 instruct divX_imm(regX dst, immXF con) %{
11064 predicate(UseSSE>=1);
11065 match(Set dst (DivF dst con));
11066 format %{ "DIVSS $dst,[$con]" %}
11067 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5E), LdImmX(dst, con) );
11068 ins_pipe( pipe_slow );
11069 %}
11070
11071 instruct divX_mem(regX dst, memory mem) %{
11072 predicate(UseSSE>=1);
11073 match(Set dst (DivF dst (LoadF mem)));
11074 format %{ "DIVSS $dst,$mem" %}
11075 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5E), RegMem(dst,mem));
11076 ins_pipe( pipe_slow );
11077 %}
11078
11079 // Get the square root of a single precision floating point values in xmm
11080 instruct sqrtX_reg(regX dst, regX src) %{
11081 predicate(UseSSE>=1);
11082 match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
11083 format %{ "SQRTSS $dst,$src" %}
11084 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x51), RegReg(dst, src));
11085 ins_pipe( pipe_slow );
11086 %}
11087
11088 instruct sqrtX_mem(regX dst, memory mem) %{
11089 predicate(UseSSE>=1);
11090 match(Set dst (ConvD2F (SqrtD (ConvF2D (LoadF mem)))));
11091 format %{ "SQRTSS $dst,$mem" %}
11092 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x51), RegMem(dst, mem));
11093 ins_pipe( pipe_slow );
11094 %}
11095
11096 // Get the square root of a double precision floating point values in xmm
11097 instruct sqrtXD_reg(regXD dst, regXD src) %{
11098 predicate(UseSSE>=2);
11099 match(Set dst (SqrtD src));
11100 format %{ "SQRTSD $dst,$src" %}
11101 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x51), RegReg(dst, src));
11102 ins_pipe( pipe_slow );
11103 %}
11104
11105 instruct sqrtXD_mem(regXD dst, memory mem) %{
11106 predicate(UseSSE>=2);
11107 match(Set dst (SqrtD (LoadD mem)));
11108 format %{ "SQRTSD $dst,$mem" %}
11109 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x51), RegMem(dst, mem));
11110 ins_pipe( pipe_slow );
11111 %}
11112
11113 instruct absF_reg(regFPR1 dst, regFPR1 src) %{
11114 predicate(UseSSE==0);
11115 match(Set dst (AbsF src));
11116 ins_cost(100);
11117 format %{ "FABS" %}
11118 opcode(0xE1, 0xD9);
11119 ins_encode( OpcS, OpcP );
11120 ins_pipe( fpu_reg_reg );
11121 %}
11122
11123 instruct absX_reg(regX dst ) %{
11124 predicate(UseSSE>=1);
11125 match(Set dst (AbsF dst));
11126 format %{ "ANDPS $dst,[0x7FFFFFFF]\t# ABS F by sign masking" %}
11127 ins_encode( AbsXF_encoding(dst));
11128 ins_pipe( pipe_slow );
11129 %}
11130
11131 instruct negF_reg(regFPR1 dst, regFPR1 src) %{
11132 predicate(UseSSE==0);
11133 match(Set dst (NegF src));
11134 ins_cost(100);
11135 format %{ "FCHS" %}
11136 opcode(0xE0, 0xD9);
11137 ins_encode( OpcS, OpcP );
11138 ins_pipe( fpu_reg_reg );
11139 %}
11140
11141 instruct negX_reg( regX dst ) %{
11142 predicate(UseSSE>=1);
11143 match(Set dst (NegF dst));
11144 format %{ "XORPS $dst,[0x80000000]\t# CHS F by sign flipping" %}
11145 ins_encode( NegXF_encoding(dst));
11146 ins_pipe( pipe_slow );
11147 %}
11148
11149 // Cisc-alternate to addF_reg
11150 // Spill to obtain 24-bit precision
11151 instruct addF24_reg_mem(stackSlotF dst, regF src1, memory src2) %{
11152 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11153 match(Set dst (AddF src1 (LoadF src2)));
11154
11155 format %{ "FLD $src2\n\t"
11156 "FADD ST,$src1\n\t"
11157 "FSTP_S $dst" %}
11158 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
11159 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
11160 OpcReg_F(src1),
11161 Pop_Mem_F(dst) );
11162 ins_pipe( fpu_mem_reg_mem );
11163 %}
11164 //
11165 // Cisc-alternate to addF_reg
11166 // This instruction does not round to 24-bits
11167 instruct addF_reg_mem(regF dst, memory src) %{
11168 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11169 match(Set dst (AddF dst (LoadF src)));
11170
11171 format %{ "FADD $dst,$src" %}
11172 opcode(0xDE, 0x0, 0xD9); /* DE C0+i or DE /0*/ /* LoadF D9 /0 */
11173 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
11174 OpcP, RegOpc(dst) );
11175 ins_pipe( fpu_reg_mem );
11176 %}
11177
11178 // // Following two instructions for _222_mpegaudio
11179 // Spill to obtain 24-bit precision
11180 instruct addF24_mem_reg(stackSlotF dst, regF src2, memory src1 ) %{
11181 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11182 match(Set dst (AddF src1 src2));
11183
11184 format %{ "FADD $dst,$src1,$src2" %}
11185 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
11186 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src1),
11187 OpcReg_F(src2),
11188 Pop_Mem_F(dst) );
11189 ins_pipe( fpu_mem_reg_mem );
11190 %}
11191
11192 // Cisc-spill variant
11193 // Spill to obtain 24-bit precision
11194 instruct addF24_mem_cisc(stackSlotF dst, memory src1, memory src2) %{
11195 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11196 match(Set dst (AddF src1 (LoadF src2)));
11197
11198 format %{ "FADD $dst,$src1,$src2 cisc" %}
11199 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
11200 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
11201 set_instruction_start,
11202 OpcP, RMopc_Mem(secondary,src1),
11203 Pop_Mem_F(dst) );
11204 ins_pipe( fpu_mem_mem_mem );
11205 %}
11206
11207 // Spill to obtain 24-bit precision
11208 instruct addF24_mem_mem(stackSlotF dst, memory src1, memory src2) %{
11209 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11210 match(Set dst (AddF src1 src2));
11211
11212 format %{ "FADD $dst,$src1,$src2" %}
11213 opcode(0xD8, 0x0, 0xD9); /* D8 /0 */ /* LoadF D9 /0 */
11214 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
11215 set_instruction_start,
11216 OpcP, RMopc_Mem(secondary,src1),
11217 Pop_Mem_F(dst) );
11218 ins_pipe( fpu_mem_mem_mem );
11219 %}
11220
11221
11222 // Spill to obtain 24-bit precision
11223 instruct addF24_reg_imm(stackSlotF dst, regF src1, immF src2) %{
11224 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11225 match(Set dst (AddF src1 src2));
11226 format %{ "FLD $src1\n\t"
11227 "FADD $src2\n\t"
11228 "FSTP_S $dst" %}
11229 opcode(0xD8, 0x00); /* D8 /0 */
11230 ins_encode( Push_Reg_F(src1),
11231 Opc_MemImm_F(src2),
11232 Pop_Mem_F(dst));
11233 ins_pipe( fpu_mem_reg_con );
11234 %}
11235 //
11236 // This instruction does not round to 24-bits
11237 instruct addF_reg_imm(regF dst, regF src1, immF src2) %{
11238 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11239 match(Set dst (AddF src1 src2));
11240 format %{ "FLD $src1\n\t"
11241 "FADD $src2\n\t"
11242 "FSTP_S $dst" %}
11243 opcode(0xD8, 0x00); /* D8 /0 */
11244 ins_encode( Push_Reg_F(src1),
11245 Opc_MemImm_F(src2),
11246 Pop_Reg_F(dst));
11247 ins_pipe( fpu_reg_reg_con );
11248 %}
11249
11250 // Spill to obtain 24-bit precision
11251 instruct mulF24_reg(stackSlotF dst, regF src1, regF src2) %{
11252 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11253 match(Set dst (MulF src1 src2));
11254
11255 format %{ "FLD $src1\n\t"
11256 "FMUL $src2\n\t"
11257 "FSTP_S $dst" %}
11258 opcode(0xD8, 0x1); /* D8 C8+i or D8 /1 ;; result in TOS */
11259 ins_encode( Push_Reg_F(src1),
11260 OpcReg_F(src2),
11261 Pop_Mem_F(dst) );
11262 ins_pipe( fpu_mem_reg_reg );
11263 %}
11264 //
11265 // This instruction does not round to 24-bits
11266 instruct mulF_reg(regF dst, regF src1, regF src2) %{
11267 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11268 match(Set dst (MulF src1 src2));
11269
11270 format %{ "FLD $src1\n\t"
11271 "FMUL $src2\n\t"
11272 "FSTP_S $dst" %}
11273 opcode(0xD8, 0x1); /* D8 C8+i */
11274 ins_encode( Push_Reg_F(src2),
11275 OpcReg_F(src1),
11276 Pop_Reg_F(dst) );
11277 ins_pipe( fpu_reg_reg_reg );
11278 %}
11279
11280
11281 // Spill to obtain 24-bit precision
11282 // Cisc-alternate to reg-reg multiply
11283 instruct mulF24_reg_mem(stackSlotF dst, regF src1, memory src2) %{
11284 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11285 match(Set dst (MulF src1 (LoadF src2)));
11286
11287 format %{ "FLD_S $src2\n\t"
11288 "FMUL $src1\n\t"
11289 "FSTP_S $dst" %}
11290 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or DE /1*/ /* LoadF D9 /0 */
11291 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
11292 OpcReg_F(src1),
11293 Pop_Mem_F(dst) );
11294 ins_pipe( fpu_mem_reg_mem );
11295 %}
11296 //
11297 // This instruction does not round to 24-bits
11298 // Cisc-alternate to reg-reg multiply
11299 instruct mulF_reg_mem(regF dst, regF src1, memory src2) %{
11300 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11301 match(Set dst (MulF src1 (LoadF src2)));
11302
11303 format %{ "FMUL $dst,$src1,$src2" %}
11304 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */ /* LoadF D9 /0 */
11305 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
11306 OpcReg_F(src1),
11307 Pop_Reg_F(dst) );
11308 ins_pipe( fpu_reg_reg_mem );
11309 %}
11310
11311 // Spill to obtain 24-bit precision
11312 instruct mulF24_mem_mem(stackSlotF dst, memory src1, memory src2) %{
11313 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11314 match(Set dst (MulF src1 src2));
11315
11316 format %{ "FMUL $dst,$src1,$src2" %}
11317 opcode(0xD8, 0x1, 0xD9); /* D8 /1 */ /* LoadF D9 /0 */
11318 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
11319 set_instruction_start,
11320 OpcP, RMopc_Mem(secondary,src1),
11321 Pop_Mem_F(dst) );
11322 ins_pipe( fpu_mem_mem_mem );
11323 %}
11324
11325 // Spill to obtain 24-bit precision
11326 instruct mulF24_reg_imm(stackSlotF dst, regF src1, immF src2) %{
11327 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11328 match(Set dst (MulF src1 src2));
11329
11330 format %{ "FMULc $dst,$src1,$src2" %}
11331 opcode(0xD8, 0x1); /* D8 /1*/
11332 ins_encode( Push_Reg_F(src1),
11333 Opc_MemImm_F(src2),
11334 Pop_Mem_F(dst));
11335 ins_pipe( fpu_mem_reg_con );
11336 %}
11337 //
11338 // This instruction does not round to 24-bits
11339 instruct mulF_reg_imm(regF dst, regF src1, immF src2) %{
11340 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11341 match(Set dst (MulF src1 src2));
11342
11343 format %{ "FMULc $dst. $src1, $src2" %}
11344 opcode(0xD8, 0x1); /* D8 /1*/
11345 ins_encode( Push_Reg_F(src1),
11346 Opc_MemImm_F(src2),
11347 Pop_Reg_F(dst));
11348 ins_pipe( fpu_reg_reg_con );
11349 %}
11350
11351
11352 //
11353 // MACRO1 -- subsume unshared load into mulF
11354 // This instruction does not round to 24-bits
11355 instruct mulF_reg_load1(regF dst, regF src, memory mem1 ) %{
11356 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11357 match(Set dst (MulF (LoadF mem1) src));
11358
11359 format %{ "FLD $mem1 ===MACRO1===\n\t"
11360 "FMUL ST,$src\n\t"
11361 "FSTP $dst" %}
11362 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or D8 /1 */ /* LoadF D9 /0 */
11363 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem1),
11364 OpcReg_F(src),
11365 Pop_Reg_F(dst) );
11366 ins_pipe( fpu_reg_reg_mem );
11367 %}
11368 //
11369 // MACRO2 -- addF a mulF which subsumed an unshared load
11370 // This instruction does not round to 24-bits
11371 instruct addF_mulF_reg_load1(regF dst, memory mem1, regF src1, regF src2) %{
11372 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11373 match(Set dst (AddF (MulF (LoadF mem1) src1) src2));
11374 ins_cost(95);
11375
11376 format %{ "FLD $mem1 ===MACRO2===\n\t"
11377 "FMUL ST,$src1 subsume mulF left load\n\t"
11378 "FADD ST,$src2\n\t"
11379 "FSTP $dst" %}
11380 opcode(0xD9); /* LoadF D9 /0 */
11381 ins_encode( OpcP, RMopc_Mem(0x00,mem1),
11382 FMul_ST_reg(src1),
11383 FAdd_ST_reg(src2),
11384 Pop_Reg_F(dst) );
11385 ins_pipe( fpu_reg_mem_reg_reg );
11386 %}
11387
11388 // MACRO3 -- addF a mulF
11389 // This instruction does not round to 24-bits. It is a '2-address'
11390 // instruction in that the result goes back to src2. This eliminates
11391 // a move from the macro; possibly the register allocator will have
11392 // to add it back (and maybe not).
11393 instruct addF_mulF_reg(regF src2, regF src1, regF src0) %{
11394 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11395 match(Set src2 (AddF (MulF src0 src1) src2));
11396
11397 format %{ "FLD $src0 ===MACRO3===\n\t"
11398 "FMUL ST,$src1\n\t"
11399 "FADDP $src2,ST" %}
11400 opcode(0xD9); /* LoadF D9 /0 */
11401 ins_encode( Push_Reg_F(src0),
11402 FMul_ST_reg(src1),
11403 FAddP_reg_ST(src2) );
11404 ins_pipe( fpu_reg_reg_reg );
11405 %}
11406
11407 // MACRO4 -- divF subF
11408 // This instruction does not round to 24-bits
11409 instruct subF_divF_reg(regF dst, regF src1, regF src2, regF src3) %{
11410 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11411 match(Set dst (DivF (SubF src2 src1) src3));
11412
11413 format %{ "FLD $src2 ===MACRO4===\n\t"
11414 "FSUB ST,$src1\n\t"
11415 "FDIV ST,$src3\n\t"
11416 "FSTP $dst" %}
11417 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
11418 ins_encode( Push_Reg_F(src2),
11419 subF_divF_encode(src1,src3),
11420 Pop_Reg_F(dst) );
11421 ins_pipe( fpu_reg_reg_reg_reg );
11422 %}
11423
11424 // Spill to obtain 24-bit precision
11425 instruct divF24_reg(stackSlotF dst, regF src1, regF src2) %{
11426 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11427 match(Set dst (DivF src1 src2));
11428
11429 format %{ "FDIV $dst,$src1,$src2" %}
11430 opcode(0xD8, 0x6); /* D8 F0+i or DE /6*/
11431 ins_encode( Push_Reg_F(src1),
11432 OpcReg_F(src2),
11433 Pop_Mem_F(dst) );
11434 ins_pipe( fpu_mem_reg_reg );
11435 %}
11436 //
11437 // This instruction does not round to 24-bits
11438 instruct divF_reg(regF dst, regF src) %{
11439 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11440 match(Set dst (DivF dst src));
11441
11442 format %{ "FDIV $dst,$src" %}
11443 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
11444 ins_encode( Push_Reg_F(src),
11445 OpcP, RegOpc(dst) );
11446 ins_pipe( fpu_reg_reg );
11447 %}
11448
11449
11450 // Spill to obtain 24-bit precision
11451 instruct modF24_reg(stackSlotF dst, regF src1, regF src2, eAXRegI rax, eFlagsReg cr) %{
11452 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
11453 match(Set dst (ModF src1 src2));
11454 effect(KILL rax, KILL cr); // emitModD() uses EAX and EFLAGS
11455
11456 format %{ "FMOD $dst,$src1,$src2" %}
11457 ins_encode( Push_Reg_Mod_D(src1, src2),
11458 emitModD(),
11459 Push_Result_Mod_D(src2),
11460 Pop_Mem_F(dst));
11461 ins_pipe( pipe_slow );
11462 %}
11463 //
11464 // This instruction does not round to 24-bits
11465 instruct modF_reg(regF dst, regF src, eAXRegI rax, eFlagsReg cr) %{
11466 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
11467 match(Set dst (ModF dst src));
11468 effect(KILL rax, KILL cr); // emitModD() uses EAX and EFLAGS
11469
11470 format %{ "FMOD $dst,$src" %}
11471 ins_encode(Push_Reg_Mod_D(dst, src),
11472 emitModD(),
11473 Push_Result_Mod_D(src),
11474 Pop_Reg_F(dst));
11475 ins_pipe( pipe_slow );
11476 %}
11477
11478 instruct modX_reg(regX dst, regX src0, regX src1, eAXRegI rax, eFlagsReg cr) %{
11479 predicate(UseSSE>=1);
11480 match(Set dst (ModF src0 src1));
11481 effect(KILL rax, KILL cr);
11482 format %{ "SUB ESP,4\t # FMOD\n"
11483 "\tMOVSS [ESP+0],$src1\n"
11484 "\tFLD_S [ESP+0]\n"
11485 "\tMOVSS [ESP+0],$src0\n"
11486 "\tFLD_S [ESP+0]\n"
11487 "loop:\tFPREM\n"
11488 "\tFWAIT\n"
11489 "\tFNSTSW AX\n"
11490 "\tSAHF\n"
11491 "\tJP loop\n"
11492 "\tFSTP_S [ESP+0]\n"
11493 "\tMOVSS $dst,[ESP+0]\n"
11494 "\tADD ESP,4\n"
11495 "\tFSTP ST0\t # Restore FPU Stack"
11496 %}
11497 ins_cost(250);
11498 ins_encode( Push_ModX_encoding(src0, src1), emitModD(), Push_ResultX(dst,0x4), PopFPU);
11499 ins_pipe( pipe_slow );
11500 %}
11501
11502
11503 //----------Arithmetic Conversion Instructions---------------------------------
11504 // The conversions operations are all Alpha sorted. Please keep it that way!
11505
11506 instruct roundFloat_mem_reg(stackSlotF dst, regF src) %{
11507 predicate(UseSSE==0);
11508 match(Set dst (RoundFloat src));
11509 ins_cost(125);
11510 format %{ "FST_S $dst,$src\t# F-round" %}
11511 ins_encode( Pop_Mem_Reg_F(dst, src) );
11512 ins_pipe( fpu_mem_reg );
11513 %}
11514
11515 instruct roundDouble_mem_reg(stackSlotD dst, regD src) %{
11516 predicate(UseSSE<=1);
11517 match(Set dst (RoundDouble src));
11518 ins_cost(125);
11519 format %{ "FST_D $dst,$src\t# D-round" %}
11520 ins_encode( Pop_Mem_Reg_D(dst, src) );
11521 ins_pipe( fpu_mem_reg );
11522 %}
11523
11524 // Force rounding to 24-bit precision and 6-bit exponent
11525 instruct convD2F_reg(stackSlotF dst, regD src) %{
11526 predicate(UseSSE==0);
11527 match(Set dst (ConvD2F src));
11528 format %{ "FST_S $dst,$src\t# F-round" %}
11529 expand %{
11530 roundFloat_mem_reg(dst,src);
11531 %}
11532 %}
11533
11534 // Force rounding to 24-bit precision and 6-bit exponent
11535 instruct convD2X_reg(regX dst, regD src, eFlagsReg cr) %{
11536 predicate(UseSSE==1);
11537 match(Set dst (ConvD2F src));
11538 effect( KILL cr );
11539 format %{ "SUB ESP,4\n\t"
11540 "FST_S [ESP],$src\t# F-round\n\t"
11541 "MOVSS $dst,[ESP]\n\t"
11542 "ADD ESP,4" %}
11543 ins_encode( D2X_encoding(dst, src) );
11544 ins_pipe( pipe_slow );
11545 %}
11546
11547 // Force rounding double precision to single precision
11548 instruct convXD2X_reg(regX dst, regXD src) %{
11549 predicate(UseSSE>=2);
11550 match(Set dst (ConvD2F src));
11551 format %{ "CVTSD2SS $dst,$src\t# F-round" %}
11552 opcode(0xF2, 0x0F, 0x5A);
11553 ins_encode( OpcP, OpcS, Opcode(tertiary), RegReg(dst, src));
11554 ins_pipe( pipe_slow );
11555 %}
11556
11557 instruct convF2D_reg_reg(regD dst, regF src) %{
11558 predicate(UseSSE==0);
11559 match(Set dst (ConvF2D src));
11560 format %{ "FST_S $dst,$src\t# D-round" %}
11561 ins_encode( Pop_Reg_Reg_D(dst, src));
11562 ins_pipe( fpu_reg_reg );
11563 %}
11564
11565 instruct convF2D_reg(stackSlotD dst, regF src) %{
11566 predicate(UseSSE==1);
11567 match(Set dst (ConvF2D src));
11568 format %{ "FST_D $dst,$src\t# D-round" %}
11569 expand %{
11570 roundDouble_mem_reg(dst,src);
11571 %}
11572 %}
11573
11574 instruct convX2D_reg(regD dst, regX src, eFlagsReg cr) %{
11575 predicate(UseSSE==1);
11576 match(Set dst (ConvF2D src));
11577 effect( KILL cr );
11578 format %{ "SUB ESP,4\n\t"
11579 "MOVSS [ESP] $src\n\t"
11580 "FLD_S [ESP]\n\t"
11581 "ADD ESP,4\n\t"
11582 "FSTP $dst\t# D-round" %}
11583 ins_encode( X2D_encoding(dst, src), Pop_Reg_D(dst));
11584 ins_pipe( pipe_slow );
11585 %}
11586
11587 instruct convX2XD_reg(regXD dst, regX src) %{
11588 predicate(UseSSE>=2);
11589 match(Set dst (ConvF2D src));
11590 format %{ "CVTSS2SD $dst,$src\t# D-round" %}
11591 opcode(0xF3, 0x0F, 0x5A);
11592 ins_encode( OpcP, OpcS, Opcode(tertiary), RegReg(dst, src));
11593 ins_pipe( pipe_slow );
11594 %}
11595
11596 // Convert a double to an int. If the double is a NAN, stuff a zero in instead.
11597 instruct convD2I_reg_reg( eAXRegI dst, eDXRegI tmp, regD src, eFlagsReg cr ) %{
11598 predicate(UseSSE<=1);
11599 match(Set dst (ConvD2I src));
11600 effect( KILL tmp, KILL cr );
11601 format %{ "FLD $src\t# Convert double to int \n\t"
11602 "FLDCW trunc mode\n\t"
11603 "SUB ESP,4\n\t"
11604 "FISTp [ESP + #0]\n\t"
11605 "FLDCW std/24-bit mode\n\t"
11606 "POP EAX\n\t"
11607 "CMP EAX,0x80000000\n\t"
11608 "JNE,s fast\n\t"
11609 "FLD_D $src\n\t"
11610 "CALL d2i_wrapper\n"
11611 "fast:" %}
11612 ins_encode( Push_Reg_D(src), D2I_encoding(src) );
11613 ins_pipe( pipe_slow );
11614 %}
11615
11616 // Convert a double to an int. If the double is a NAN, stuff a zero in instead.
11617 instruct convXD2I_reg_reg( eAXRegI dst, eDXRegI tmp, regXD src, eFlagsReg cr ) %{
11618 predicate(UseSSE>=2);
11619 match(Set dst (ConvD2I src));
11620 effect( KILL tmp, KILL cr );
11621 format %{ "CVTTSD2SI $dst, $src\n\t"
11622 "CMP $dst,0x80000000\n\t"
11623 "JNE,s fast\n\t"
11624 "SUB ESP, 8\n\t"
11625 "MOVSD [ESP], $src\n\t"
11626 "FLD_D [ESP]\n\t"
11627 "ADD ESP, 8\n\t"
11628 "CALL d2i_wrapper\n"
11629 "fast:" %}
11630 opcode(0x1); // double-precision conversion
11631 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x2C), FX2I_encoding(src,dst));
11632 ins_pipe( pipe_slow );
11633 %}
11634
11635 instruct convD2L_reg_reg( eADXRegL dst, regD src, eFlagsReg cr ) %{
11636 predicate(UseSSE<=1);
11637 match(Set dst (ConvD2L src));
11638 effect( KILL cr );
11639 format %{ "FLD $src\t# Convert double to long\n\t"
11640 "FLDCW trunc mode\n\t"
11641 "SUB ESP,8\n\t"
11642 "FISTp [ESP + #0]\n\t"
11643 "FLDCW std/24-bit mode\n\t"
11644 "POP EAX\n\t"
11645 "POP EDX\n\t"
11646 "CMP EDX,0x80000000\n\t"
11647 "JNE,s fast\n\t"
11648 "TEST EAX,EAX\n\t"
11649 "JNE,s fast\n\t"
11650 "FLD $src\n\t"
11651 "CALL d2l_wrapper\n"
11652 "fast:" %}
11653 ins_encode( Push_Reg_D(src), D2L_encoding(src) );
11654 ins_pipe( pipe_slow );
11655 %}
11656
11657 // XMM lacks a float/double->long conversion, so use the old FPU stack.
11658 instruct convXD2L_reg_reg( eADXRegL dst, regXD src, eFlagsReg cr ) %{
11659 predicate (UseSSE>=2);
11660 match(Set dst (ConvD2L src));
11661 effect( KILL cr );
11662 format %{ "SUB ESP,8\t# Convert double to long\n\t"
11663 "MOVSD [ESP],$src\n\t"
11664 "FLD_D [ESP]\n\t"
11665 "FLDCW trunc mode\n\t"
11666 "FISTp [ESP + #0]\n\t"
11667 "FLDCW std/24-bit mode\n\t"
11668 "POP EAX\n\t"
11669 "POP EDX\n\t"
11670 "CMP EDX,0x80000000\n\t"
11671 "JNE,s fast\n\t"
11672 "TEST EAX,EAX\n\t"
11673 "JNE,s fast\n\t"
11674 "SUB ESP,8\n\t"
11675 "MOVSD [ESP],$src\n\t"
11676 "FLD_D [ESP]\n\t"
11677 "CALL d2l_wrapper\n"
11678 "fast:" %}
11679 ins_encode( XD2L_encoding(src) );
11680 ins_pipe( pipe_slow );
11681 %}
11682
11683 // Convert a double to an int. Java semantics require we do complex
11684 // manglations in the corner cases. So we set the rounding mode to
11685 // 'zero', store the darned double down as an int, and reset the
11686 // rounding mode to 'nearest'. The hardware stores a flag value down
11687 // if we would overflow or converted a NAN; we check for this and
11688 // and go the slow path if needed.
11689 instruct convF2I_reg_reg(eAXRegI dst, eDXRegI tmp, regF src, eFlagsReg cr ) %{
11690 predicate(UseSSE==0);
11691 match(Set dst (ConvF2I src));
11692 effect( KILL tmp, KILL cr );
11693 format %{ "FLD $src\t# Convert float to int \n\t"
11694 "FLDCW trunc mode\n\t"
11695 "SUB ESP,4\n\t"
11696 "FISTp [ESP + #0]\n\t"
11697 "FLDCW std/24-bit mode\n\t"
11698 "POP EAX\n\t"
11699 "CMP EAX,0x80000000\n\t"
11700 "JNE,s fast\n\t"
11701 "FLD $src\n\t"
11702 "CALL d2i_wrapper\n"
11703 "fast:" %}
11704 // D2I_encoding works for F2I
11705 ins_encode( Push_Reg_F(src), D2I_encoding(src) );
11706 ins_pipe( pipe_slow );
11707 %}
11708
11709 // Convert a float in xmm to an int reg.
11710 instruct convX2I_reg(eAXRegI dst, eDXRegI tmp, regX src, eFlagsReg cr ) %{
11711 predicate(UseSSE>=1);
11712 match(Set dst (ConvF2I src));
11713 effect( KILL tmp, KILL cr );
11714 format %{ "CVTTSS2SI $dst, $src\n\t"
11715 "CMP $dst,0x80000000\n\t"
11716 "JNE,s fast\n\t"
11717 "SUB ESP, 4\n\t"
11718 "MOVSS [ESP], $src\n\t"
11719 "FLD [ESP]\n\t"
11720 "ADD ESP, 4\n\t"
11721 "CALL d2i_wrapper\n"
11722 "fast:" %}
11723 opcode(0x0); // single-precision conversion
11724 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x2C), FX2I_encoding(src,dst));
11725 ins_pipe( pipe_slow );
11726 %}
11727
11728 instruct convF2L_reg_reg( eADXRegL dst, regF src, eFlagsReg cr ) %{
11729 predicate(UseSSE==0);
11730 match(Set dst (ConvF2L src));
11731 effect( KILL cr );
11732 format %{ "FLD $src\t# Convert float to long\n\t"
11733 "FLDCW trunc mode\n\t"
11734 "SUB ESP,8\n\t"
11735 "FISTp [ESP + #0]\n\t"
11736 "FLDCW std/24-bit mode\n\t"
11737 "POP EAX\n\t"
11738 "POP EDX\n\t"
11739 "CMP EDX,0x80000000\n\t"
11740 "JNE,s fast\n\t"
11741 "TEST EAX,EAX\n\t"
11742 "JNE,s fast\n\t"
11743 "FLD $src\n\t"
11744 "CALL d2l_wrapper\n"
11745 "fast:" %}
11746 // D2L_encoding works for F2L
11747 ins_encode( Push_Reg_F(src), D2L_encoding(src) );
11748 ins_pipe( pipe_slow );
11749 %}
11750
11751 // XMM lacks a float/double->long conversion, so use the old FPU stack.
11752 instruct convX2L_reg_reg( eADXRegL dst, regX src, eFlagsReg cr ) %{
11753 predicate (UseSSE>=1);
11754 match(Set dst (ConvF2L src));
11755 effect( KILL cr );
11756 format %{ "SUB ESP,8\t# Convert float to long\n\t"
11757 "MOVSS [ESP],$src\n\t"
11758 "FLD_S [ESP]\n\t"
11759 "FLDCW trunc mode\n\t"
11760 "FISTp [ESP + #0]\n\t"
11761 "FLDCW std/24-bit mode\n\t"
11762 "POP EAX\n\t"
11763 "POP EDX\n\t"
11764 "CMP EDX,0x80000000\n\t"
11765 "JNE,s fast\n\t"
11766 "TEST EAX,EAX\n\t"
11767 "JNE,s fast\n\t"
11768 "SUB ESP,4\t# Convert float to long\n\t"
11769 "MOVSS [ESP],$src\n\t"
11770 "FLD_S [ESP]\n\t"
11771 "ADD ESP,4\n\t"
11772 "CALL d2l_wrapper\n"
11773 "fast:" %}
11774 ins_encode( X2L_encoding(src) );
11775 ins_pipe( pipe_slow );
11776 %}
11777
11778 instruct convI2D_reg(regD dst, stackSlotI src) %{
11779 predicate( UseSSE<=1 );
11780 match(Set dst (ConvI2D src));
11781 format %{ "FILD $src\n\t"
11782 "FSTP $dst" %}
11783 opcode(0xDB, 0x0); /* DB /0 */
11784 ins_encode(Push_Mem_I(src), Pop_Reg_D(dst));
11785 ins_pipe( fpu_reg_mem );
11786 %}
11787
11788 instruct convI2XD_reg(regXD dst, eRegI src) %{
11789 predicate( UseSSE>=2 && !UseXmmI2D );
11790 match(Set dst (ConvI2D src));
11791 format %{ "CVTSI2SD $dst,$src" %}
11792 opcode(0xF2, 0x0F, 0x2A);
11793 ins_encode( OpcP, OpcS, Opcode(tertiary), RegReg(dst, src));
11794 ins_pipe( pipe_slow );
11795 %}
11796
11797 instruct convI2XD_mem(regXD dst, memory mem) %{
11798 predicate( UseSSE>=2 );
11799 match(Set dst (ConvI2D (LoadI mem)));
11800 format %{ "CVTSI2SD $dst,$mem" %}
11801 opcode(0xF2, 0x0F, 0x2A);
11802 ins_encode( OpcP, OpcS, Opcode(tertiary), RegMem(dst, mem));
11803 ins_pipe( pipe_slow );
11804 %}
11805
11806 instruct convXI2XD_reg(regXD dst, eRegI src)
11807 %{
11808 predicate( UseSSE>=2 && UseXmmI2D );
11809 match(Set dst (ConvI2D src));
11810
11811 format %{ "MOVD $dst,$src\n\t"
11812 "CVTDQ2PD $dst,$dst\t# i2d" %}
11813 ins_encode %{
11814 __ movdl($dst$$XMMRegister, $src$$Register);
11815 __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister);
11816 %}
11817 ins_pipe(pipe_slow); // XXX
11818 %}
11819
11820 instruct convI2D_mem(regD dst, memory mem) %{
11821 predicate( UseSSE<=1 && !Compile::current()->select_24_bit_instr());
11822 match(Set dst (ConvI2D (LoadI mem)));
11823 format %{ "FILD $mem\n\t"
11824 "FSTP $dst" %}
11825 opcode(0xDB); /* DB /0 */
11826 ins_encode( OpcP, RMopc_Mem(0x00,mem),
11827 Pop_Reg_D(dst));
11828 ins_pipe( fpu_reg_mem );
11829 %}
11830
11831 // Convert a byte to a float; no rounding step needed.
11832 instruct conv24I2F_reg(regF dst, stackSlotI src) %{
11833 predicate( UseSSE==0 && n->in(1)->Opcode() == Op_AndI && n->in(1)->in(2)->is_Con() && n->in(1)->in(2)->get_int() == 255 );
11834 match(Set dst (ConvI2F src));
11835 format %{ "FILD $src\n\t"
11836 "FSTP $dst" %}
11837
11838 opcode(0xDB, 0x0); /* DB /0 */
11839 ins_encode(Push_Mem_I(src), Pop_Reg_F(dst));
11840 ins_pipe( fpu_reg_mem );
11841 %}
11842
11843 // In 24-bit mode, force exponent rounding by storing back out
11844 instruct convI2F_SSF(stackSlotF dst, stackSlotI src) %{
11845 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
11846 match(Set dst (ConvI2F src));
11847 ins_cost(200);
11848 format %{ "FILD $src\n\t"
11849 "FSTP_S $dst" %}
11850 opcode(0xDB, 0x0); /* DB /0 */
11851 ins_encode( Push_Mem_I(src),
11852 Pop_Mem_F(dst));
11853 ins_pipe( fpu_mem_mem );
11854 %}
11855
11856 // In 24-bit mode, force exponent rounding by storing back out
11857 instruct convI2F_SSF_mem(stackSlotF dst, memory mem) %{
11858 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
11859 match(Set dst (ConvI2F (LoadI mem)));
11860 ins_cost(200);
11861 format %{ "FILD $mem\n\t"
11862 "FSTP_S $dst" %}
11863 opcode(0xDB); /* DB /0 */
11864 ins_encode( OpcP, RMopc_Mem(0x00,mem),
11865 Pop_Mem_F(dst));
11866 ins_pipe( fpu_mem_mem );
11867 %}
11868
11869 // This instruction does not round to 24-bits
11870 instruct convI2F_reg(regF dst, stackSlotI src) %{
11871 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
11872 match(Set dst (ConvI2F src));
11873 format %{ "FILD $src\n\t"
11874 "FSTP $dst" %}
11875 opcode(0xDB, 0x0); /* DB /0 */
11876 ins_encode( Push_Mem_I(src),
11877 Pop_Reg_F(dst));
11878 ins_pipe( fpu_reg_mem );
11879 %}
11880
11881 // This instruction does not round to 24-bits
11882 instruct convI2F_mem(regF dst, memory mem) %{
11883 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
11884 match(Set dst (ConvI2F (LoadI mem)));
11885 format %{ "FILD $mem\n\t"
11886 "FSTP $dst" %}
11887 opcode(0xDB); /* DB /0 */
11888 ins_encode( OpcP, RMopc_Mem(0x00,mem),
11889 Pop_Reg_F(dst));
11890 ins_pipe( fpu_reg_mem );
11891 %}
11892
11893 // Convert an int to a float in xmm; no rounding step needed.
11894 instruct convI2X_reg(regX dst, eRegI src) %{
11895 predicate( UseSSE==1 || UseSSE>=2 && !UseXmmI2F );
11896 match(Set dst (ConvI2F src));
11897 format %{ "CVTSI2SS $dst, $src" %}
11898
11899 opcode(0xF3, 0x0F, 0x2A); /* F3 0F 2A /r */
11900 ins_encode( OpcP, OpcS, Opcode(tertiary), RegReg(dst, src));
11901 ins_pipe( pipe_slow );
11902 %}
11903
11904 instruct convXI2X_reg(regX dst, eRegI src)
11905 %{
11906 predicate( UseSSE>=2 && UseXmmI2F );
11907 match(Set dst (ConvI2F src));
11908
11909 format %{ "MOVD $dst,$src\n\t"
11910 "CVTDQ2PS $dst,$dst\t# i2f" %}
11911 ins_encode %{
11912 __ movdl($dst$$XMMRegister, $src$$Register);
11913 __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister);
11914 %}
11915 ins_pipe(pipe_slow); // XXX
11916 %}
11917
11918 instruct convI2L_reg( eRegL dst, eRegI src, eFlagsReg cr) %{
11919 match(Set dst (ConvI2L src));
11920 effect(KILL cr);
11921 ins_cost(375);
11922 format %{ "MOV $dst.lo,$src\n\t"
11923 "MOV $dst.hi,$src\n\t"
11924 "SAR $dst.hi,31" %}
11925 ins_encode(convert_int_long(dst,src));
11926 ins_pipe( ialu_reg_reg_long );
11927 %}
11928
11929 // Zero-extend convert int to long
11930 instruct convI2L_reg_zex(eRegL dst, eRegI src, immL_32bits mask, eFlagsReg flags ) %{
11931 match(Set dst (AndL (ConvI2L src) mask) );
11932 effect( KILL flags );
11933 ins_cost(250);
11934 format %{ "MOV $dst.lo,$src\n\t"
11935 "XOR $dst.hi,$dst.hi" %}
11936 opcode(0x33); // XOR
11937 ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) );
11938 ins_pipe( ialu_reg_reg_long );
11939 %}
11940
11941 // Zero-extend long
11942 instruct zerox_long(eRegL dst, eRegL src, immL_32bits mask, eFlagsReg flags ) %{
11943 match(Set dst (AndL src mask) );
11944 effect( KILL flags );
11945 ins_cost(250);
11946 format %{ "MOV $dst.lo,$src.lo\n\t"
11947 "XOR $dst.hi,$dst.hi\n\t" %}
11948 opcode(0x33); // XOR
11949 ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) );
11950 ins_pipe( ialu_reg_reg_long );
11951 %}
11952
11953 instruct convL2D_reg( stackSlotD dst, eRegL src, eFlagsReg cr) %{
11954 predicate (UseSSE<=1);
11955 match(Set dst (ConvL2D src));
11956 effect( KILL cr );
11957 format %{ "PUSH $src.hi\t# Convert long to double\n\t"
11958 "PUSH $src.lo\n\t"
11959 "FILD ST,[ESP + #0]\n\t"
11960 "ADD ESP,8\n\t"
11961 "FSTP_D $dst\t# D-round" %}
11962 opcode(0xDF, 0x5); /* DF /5 */
11963 ins_encode(convert_long_double(src), Pop_Mem_D(dst));
11964 ins_pipe( pipe_slow );
11965 %}
11966
11967 instruct convL2XD_reg( regXD dst, eRegL src, eFlagsReg cr) %{
11968 predicate (UseSSE>=2);
11969 match(Set dst (ConvL2D src));
11970 effect( KILL cr );
11971 format %{ "PUSH $src.hi\t# Convert long to double\n\t"
11972 "PUSH $src.lo\n\t"
11973 "FILD_D [ESP]\n\t"
11974 "FSTP_D [ESP]\n\t"
11975 "MOVSD $dst,[ESP]\n\t"
11976 "ADD ESP,8" %}
11977 opcode(0xDF, 0x5); /* DF /5 */
11978 ins_encode(convert_long_double2(src), Push_ResultXD(dst));
11979 ins_pipe( pipe_slow );
11980 %}
11981
11982 instruct convL2X_reg( regX dst, eRegL src, eFlagsReg cr) %{
11983 predicate (UseSSE>=1);
11984 match(Set dst (ConvL2F src));
11985 effect( KILL cr );
11986 format %{ "PUSH $src.hi\t# Convert long to single float\n\t"
11987 "PUSH $src.lo\n\t"
11988 "FILD_D [ESP]\n\t"
11989 "FSTP_S [ESP]\n\t"
11990 "MOVSS $dst,[ESP]\n\t"
11991 "ADD ESP,8" %}
11992 opcode(0xDF, 0x5); /* DF /5 */
11993 ins_encode(convert_long_double2(src), Push_ResultX(dst,0x8));
11994 ins_pipe( pipe_slow );
11995 %}
11996
11997 instruct convL2F_reg( stackSlotF dst, eRegL src, eFlagsReg cr) %{
11998 match(Set dst (ConvL2F src));
11999 effect( KILL cr );
12000 format %{ "PUSH $src.hi\t# Convert long to single float\n\t"
12001 "PUSH $src.lo\n\t"
12002 "FILD ST,[ESP + #0]\n\t"
12003 "ADD ESP,8\n\t"
12004 "FSTP_S $dst\t# F-round" %}
12005 opcode(0xDF, 0x5); /* DF /5 */
12006 ins_encode(convert_long_double(src), Pop_Mem_F(dst));
12007 ins_pipe( pipe_slow );
12008 %}
12009
12010 instruct convL2I_reg( eRegI dst, eRegL src ) %{
12011 match(Set dst (ConvL2I src));
12012 effect( DEF dst, USE src );
12013 format %{ "MOV $dst,$src.lo" %}
12014 ins_encode(enc_CopyL_Lo(dst,src));
12015 ins_pipe( ialu_reg_reg );
12016 %}
12017
12018
12019 instruct MoveF2I_stack_reg(eRegI dst, stackSlotF src) %{
12020 match(Set dst (MoveF2I src));
12021 effect( DEF dst, USE src );
12022 ins_cost(100);
12023 format %{ "MOV $dst,$src\t# MoveF2I_stack_reg" %}
12024 opcode(0x8B);
12025 ins_encode( OpcP, RegMem(dst,src));
12026 ins_pipe( ialu_reg_mem );
12027 %}
12028
12029 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{
12030 predicate(UseSSE==0);
12031 match(Set dst (MoveF2I src));
12032 effect( DEF dst, USE src );
12033
12034 ins_cost(125);
12035 format %{ "FST_S $dst,$src\t# MoveF2I_reg_stack" %}
12036 ins_encode( Pop_Mem_Reg_F(dst, src) );
12037 ins_pipe( fpu_mem_reg );
12038 %}
12039
12040 instruct MoveF2I_reg_stack_sse(stackSlotI dst, regX src) %{
12041 predicate(UseSSE>=1);
12042 match(Set dst (MoveF2I src));
12043 effect( DEF dst, USE src );
12044
12045 ins_cost(95);
12046 format %{ "MOVSS $dst,$src\t# MoveF2I_reg_stack_sse" %}
12047 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x11), RegMem(src, dst));
12048 ins_pipe( pipe_slow );
12049 %}
12050
12051 instruct MoveF2I_reg_reg_sse(eRegI dst, regX src) %{
12052 predicate(UseSSE>=2);
12053 match(Set dst (MoveF2I src));
12054 effect( DEF dst, USE src );
12055 ins_cost(85);
12056 format %{ "MOVD $dst,$src\t# MoveF2I_reg_reg_sse" %}
12057 ins_encode( MovX2I_reg(dst, src));
12058 ins_pipe( pipe_slow );
12059 %}
12060
12061 instruct MoveI2F_reg_stack(stackSlotF dst, eRegI src) %{
12062 match(Set dst (MoveI2F src));
12063 effect( DEF dst, USE src );
12064
12065 ins_cost(100);
12066 format %{ "MOV $dst,$src\t# MoveI2F_reg_stack" %}
12067 opcode(0x89);
12068 ins_encode( OpcPRegSS( dst, src ) );
12069 ins_pipe( ialu_mem_reg );
12070 %}
12071
12072
12073 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
12074 predicate(UseSSE==0);
12075 match(Set dst (MoveI2F src));
12076 effect(DEF dst, USE src);
12077
12078 ins_cost(125);
12079 format %{ "FLD_S $src\n\t"
12080 "FSTP $dst\t# MoveI2F_stack_reg" %}
12081 opcode(0xD9); /* D9 /0, FLD m32real */
12082 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
12083 Pop_Reg_F(dst) );
12084 ins_pipe( fpu_reg_mem );
12085 %}
12086
12087 instruct MoveI2F_stack_reg_sse(regX dst, stackSlotI src) %{
12088 predicate(UseSSE>=1);
12089 match(Set dst (MoveI2F src));
12090 effect( DEF dst, USE src );
12091
12092 ins_cost(95);
12093 format %{ "MOVSS $dst,$src\t# MoveI2F_stack_reg_sse" %}
12094 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x10), RegMem(dst,src));
12095 ins_pipe( pipe_slow );
12096 %}
12097
12098 instruct MoveI2F_reg_reg_sse(regX dst, eRegI src) %{
12099 predicate(UseSSE>=2);
12100 match(Set dst (MoveI2F src));
12101 effect( DEF dst, USE src );
12102
12103 ins_cost(85);
12104 format %{ "MOVD $dst,$src\t# MoveI2F_reg_reg_sse" %}
12105 ins_encode( MovI2X_reg(dst, src) );
12106 ins_pipe( pipe_slow );
12107 %}
12108
12109 instruct MoveD2L_stack_reg(eRegL dst, stackSlotD src) %{
12110 match(Set dst (MoveD2L src));
12111 effect(DEF dst, USE src);
12112
12113 ins_cost(250);
12114 format %{ "MOV $dst.lo,$src\n\t"
12115 "MOV $dst.hi,$src+4\t# MoveD2L_stack_reg" %}
12116 opcode(0x8B, 0x8B);
12117 ins_encode( OpcP, RegMem(dst,src), OpcS, RegMem_Hi(dst,src));
12118 ins_pipe( ialu_mem_long_reg );
12119 %}
12120
12121 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
12122 predicate(UseSSE<=1);
12123 match(Set dst (MoveD2L src));
12124 effect(DEF dst, USE src);
12125
12126 ins_cost(125);
12127 format %{ "FST_D $dst,$src\t# MoveD2L_reg_stack" %}
12128 ins_encode( Pop_Mem_Reg_D(dst, src) );
12129 ins_pipe( fpu_mem_reg );
12130 %}
12131
12132 instruct MoveD2L_reg_stack_sse(stackSlotL dst, regXD src) %{
12133 predicate(UseSSE>=2);
12134 match(Set dst (MoveD2L src));
12135 effect(DEF dst, USE src);
12136 ins_cost(95);
12137
12138 format %{ "MOVSD $dst,$src\t# MoveD2L_reg_stack_sse" %}
12139 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x11), RegMem(src,dst));
12140 ins_pipe( pipe_slow );
12141 %}
12142
12143 instruct MoveD2L_reg_reg_sse(eRegL dst, regXD src, regXD tmp) %{
12144 predicate(UseSSE>=2);
12145 match(Set dst (MoveD2L src));
12146 effect(DEF dst, USE src, TEMP tmp);
12147 ins_cost(85);
12148 format %{ "MOVD $dst.lo,$src\n\t"
12149 "PSHUFLW $tmp,$src,0x4E\n\t"
12150 "MOVD $dst.hi,$tmp\t# MoveD2L_reg_reg_sse" %}
12151 ins_encode( MovXD2L_reg(dst, src, tmp) );
12152 ins_pipe( pipe_slow );
12153 %}
12154
12155 instruct MoveL2D_reg_stack(stackSlotD dst, eRegL src) %{
12156 match(Set dst (MoveL2D src));
12157 effect(DEF dst, USE src);
12158
12159 ins_cost(200);
12160 format %{ "MOV $dst,$src.lo\n\t"
12161 "MOV $dst+4,$src.hi\t# MoveL2D_reg_stack" %}
12162 opcode(0x89, 0x89);
12163 ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) );
12164 ins_pipe( ialu_mem_long_reg );
12165 %}
12166
12167
12168 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
12169 predicate(UseSSE<=1);
12170 match(Set dst (MoveL2D src));
12171 effect(DEF dst, USE src);
12172 ins_cost(125);
12173
12174 format %{ "FLD_D $src\n\t"
12175 "FSTP $dst\t# MoveL2D_stack_reg" %}
12176 opcode(0xDD); /* DD /0, FLD m64real */
12177 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
12178 Pop_Reg_D(dst) );
12179 ins_pipe( fpu_reg_mem );
12180 %}
12181
12182
12183 instruct MoveL2D_stack_reg_sse(regXD dst, stackSlotL src) %{
12184 predicate(UseSSE>=2 && UseXmmLoadAndClearUpper);
12185 match(Set dst (MoveL2D src));
12186 effect(DEF dst, USE src);
12187
12188 ins_cost(95);
12189 format %{ "MOVSD $dst,$src\t# MoveL2D_stack_reg_sse" %}
12190 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x10), RegMem(dst,src));
12191 ins_pipe( pipe_slow );
12192 %}
12193
12194 instruct MoveL2D_stack_reg_sse_partial(regXD dst, stackSlotL src) %{
12195 predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper);
12196 match(Set dst (MoveL2D src));
12197 effect(DEF dst, USE src);
12198
12199 ins_cost(95);
12200 format %{ "MOVLPD $dst,$src\t# MoveL2D_stack_reg_sse" %}
12201 ins_encode( Opcode(0x66), Opcode(0x0F), Opcode(0x12), RegMem(dst,src));
12202 ins_pipe( pipe_slow );
12203 %}
12204
12205 instruct MoveL2D_reg_reg_sse(regXD dst, eRegL src, regXD tmp) %{
12206 predicate(UseSSE>=2);
12207 match(Set dst (MoveL2D src));
12208 effect(TEMP dst, USE src, TEMP tmp);
12209 ins_cost(85);
12210 format %{ "MOVD $dst,$src.lo\n\t"
12211 "MOVD $tmp,$src.hi\n\t"
12212 "PUNPCKLDQ $dst,$tmp\t# MoveL2D_reg_reg_sse" %}
12213 ins_encode( MovL2XD_reg(dst, src, tmp) );
12214 ins_pipe( pipe_slow );
12215 %}
12216
12217 // Replicate scalar to packed byte (1 byte) values in xmm
12218 instruct Repl8B_reg(regXD dst, regXD src) %{
12219 predicate(UseSSE>=2);
12220 match(Set dst (Replicate8B src));
12221 format %{ "MOVDQA $dst,$src\n\t"
12222 "PUNPCKLBW $dst,$dst\n\t"
12223 "PSHUFLW $dst,$dst,0x00\t! replicate8B" %}
12224 ins_encode( pshufd_8x8(dst, src));
12225 ins_pipe( pipe_slow );
12226 %}
12227
12228 // Replicate scalar to packed byte (1 byte) values in xmm
12229 instruct Repl8B_eRegI(regXD dst, eRegI src) %{
12230 predicate(UseSSE>=2);
12231 match(Set dst (Replicate8B src));
12232 format %{ "MOVD $dst,$src\n\t"
12233 "PUNPCKLBW $dst,$dst\n\t"
12234 "PSHUFLW $dst,$dst,0x00\t! replicate8B" %}
12235 ins_encode( mov_i2x(dst, src), pshufd_8x8(dst, dst));
12236 ins_pipe( pipe_slow );
12237 %}
12238
12239 // Replicate scalar zero to packed byte (1 byte) values in xmm
12240 instruct Repl8B_immI0(regXD dst, immI0 zero) %{
12241 predicate(UseSSE>=2);
12242 match(Set dst (Replicate8B zero));
12243 format %{ "PXOR $dst,$dst\t! replicate8B" %}
12244 ins_encode( pxor(dst, dst));
12245 ins_pipe( fpu_reg_reg );
12246 %}
12247
12248 // Replicate scalar to packed shore (2 byte) values in xmm
12249 instruct Repl4S_reg(regXD dst, regXD src) %{
12250 predicate(UseSSE>=2);
12251 match(Set dst (Replicate4S src));
12252 format %{ "PSHUFLW $dst,$src,0x00\t! replicate4S" %}
12253 ins_encode( pshufd_4x16(dst, src));
12254 ins_pipe( fpu_reg_reg );
12255 %}
12256
12257 // Replicate scalar to packed shore (2 byte) values in xmm
12258 instruct Repl4S_eRegI(regXD dst, eRegI src) %{
12259 predicate(UseSSE>=2);
12260 match(Set dst (Replicate4S src));
12261 format %{ "MOVD $dst,$src\n\t"
12262 "PSHUFLW $dst,$dst,0x00\t! replicate4S" %}
12263 ins_encode( mov_i2x(dst, src), pshufd_4x16(dst, dst));
12264 ins_pipe( fpu_reg_reg );
12265 %}
12266
12267 // Replicate scalar zero to packed short (2 byte) values in xmm
12268 instruct Repl4S_immI0(regXD dst, immI0 zero) %{
12269 predicate(UseSSE>=2);
12270 match(Set dst (Replicate4S zero));
12271 format %{ "PXOR $dst,$dst\t! replicate4S" %}
12272 ins_encode( pxor(dst, dst));
12273 ins_pipe( fpu_reg_reg );
12274 %}
12275
12276 // Replicate scalar to packed char (2 byte) values in xmm
12277 instruct Repl4C_reg(regXD dst, regXD src) %{
12278 predicate(UseSSE>=2);
12279 match(Set dst (Replicate4C src));
12280 format %{ "PSHUFLW $dst,$src,0x00\t! replicate4C" %}
12281 ins_encode( pshufd_4x16(dst, src));
12282 ins_pipe( fpu_reg_reg );
12283 %}
12284
12285 // Replicate scalar to packed char (2 byte) values in xmm
12286 instruct Repl4C_eRegI(regXD dst, eRegI src) %{
12287 predicate(UseSSE>=2);
12288 match(Set dst (Replicate4C src));
12289 format %{ "MOVD $dst,$src\n\t"
12290 "PSHUFLW $dst,$dst,0x00\t! replicate4C" %}
12291 ins_encode( mov_i2x(dst, src), pshufd_4x16(dst, dst));
12292 ins_pipe( fpu_reg_reg );
12293 %}
12294
12295 // Replicate scalar zero to packed char (2 byte) values in xmm
12296 instruct Repl4C_immI0(regXD dst, immI0 zero) %{
12297 predicate(UseSSE>=2);
12298 match(Set dst (Replicate4C zero));
12299 format %{ "PXOR $dst,$dst\t! replicate4C" %}
12300 ins_encode( pxor(dst, dst));
12301 ins_pipe( fpu_reg_reg );
12302 %}
12303
12304 // Replicate scalar to packed integer (4 byte) values in xmm
12305 instruct Repl2I_reg(regXD dst, regXD src) %{
12306 predicate(UseSSE>=2);
12307 match(Set dst (Replicate2I src));
12308 format %{ "PSHUFD $dst,$src,0x00\t! replicate2I" %}
12309 ins_encode( pshufd(dst, src, 0x00));
12310 ins_pipe( fpu_reg_reg );
12311 %}
12312
12313 // Replicate scalar to packed integer (4 byte) values in xmm
12314 instruct Repl2I_eRegI(regXD dst, eRegI src) %{
12315 predicate(UseSSE>=2);
12316 match(Set dst (Replicate2I src));
12317 format %{ "MOVD $dst,$src\n\t"
12318 "PSHUFD $dst,$dst,0x00\t! replicate2I" %}
12319 ins_encode( mov_i2x(dst, src), pshufd(dst, dst, 0x00));
12320 ins_pipe( fpu_reg_reg );
12321 %}
12322
12323 // Replicate scalar zero to packed integer (2 byte) values in xmm
12324 instruct Repl2I_immI0(regXD dst, immI0 zero) %{
12325 predicate(UseSSE>=2);
12326 match(Set dst (Replicate2I zero));
12327 format %{ "PXOR $dst,$dst\t! replicate2I" %}
12328 ins_encode( pxor(dst, dst));
12329 ins_pipe( fpu_reg_reg );
12330 %}
12331
12332 // Replicate scalar to packed single precision floating point values in xmm
12333 instruct Repl2F_reg(regXD dst, regXD src) %{
12334 predicate(UseSSE>=2);
12335 match(Set dst (Replicate2F src));
12336 format %{ "PSHUFD $dst,$src,0xe0\t! replicate2F" %}
12337 ins_encode( pshufd(dst, src, 0xe0));
12338 ins_pipe( fpu_reg_reg );
12339 %}
12340
12341 // Replicate scalar to packed single precision floating point values in xmm
12342 instruct Repl2F_regX(regXD dst, regX src) %{
12343 predicate(UseSSE>=2);
12344 match(Set dst (Replicate2F src));
12345 format %{ "PSHUFD $dst,$src,0xe0\t! replicate2F" %}
12346 ins_encode( pshufd(dst, src, 0xe0));
12347 ins_pipe( fpu_reg_reg );
12348 %}
12349
12350 // Replicate scalar to packed single precision floating point values in xmm
12351 instruct Repl2F_immXF0(regXD dst, immXF0 zero) %{
12352 predicate(UseSSE>=2);
12353 match(Set dst (Replicate2F zero));
12354 format %{ "PXOR $dst,$dst\t! replicate2F" %}
12355 ins_encode( pxor(dst, dst));
12356 ins_pipe( fpu_reg_reg );
12357 %}
12358
12359 // =======================================================================
12360 // fast clearing of an array
12361 instruct rep_stos(eCXRegI cnt, eDIRegP base, eAXRegI zero, Universe dummy, eFlagsReg cr) %{
12362 match(Set dummy (ClearArray cnt base));
12363 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr);
12364 format %{ "SHL ECX,1\t# Convert doublewords to words\n\t"
12365 "XOR EAX,EAX\n\t"
12366 "REP STOS\t# store EAX into [EDI++] while ECX--" %}
12367 opcode(0,0x4);
12368 ins_encode( Opcode(0xD1), RegOpc(ECX),
12369 OpcRegReg(0x33,EAX,EAX),
12370 Opcode(0xF3), Opcode(0xAB) );
12371 ins_pipe( pipe_slow );
12372 %}
12373
12374 instruct string_compare(eDIRegP str1, eSIRegP str2, regXD tmp1, regXD tmp2,
12375 eAXRegI tmp3, eBXRegI tmp4, eCXRegI result, eFlagsReg cr) %{
12376 match(Set result (StrComp str1 str2));
12377 effect(TEMP tmp1, TEMP tmp2, USE_KILL str1, USE_KILL str2, KILL tmp3, KILL tmp4, KILL cr);
12378 //ins_cost(300);
12379
12380 format %{ "String Compare $str1,$str2 -> $result // KILL EAX, EBX" %}
12381 ins_encode( enc_String_Compare(str1, str2, tmp1, tmp2, tmp3, tmp4, result) );
12382 ins_pipe( pipe_slow );
12383 %}
12384
12385 // fast string equals
12386 instruct string_equals(eDIRegP str1, eSIRegP str2, regXD tmp1, regXD tmp2,
12387 eBXRegI tmp3, eCXRegI tmp4, eAXRegI result, eFlagsReg cr) %{
12388 match(Set result (StrEquals str1 str2));
12389 effect(TEMP tmp1, TEMP tmp2, USE_KILL str1, USE_KILL str2, KILL tmp3, KILL tmp4, KILL cr);
12390
12391 format %{ "String Equals $str1,$str2 -> $result // KILL EBX, ECX" %}
12392 ins_encode( enc_String_Equals(tmp1, tmp2, str1, str2, tmp3, tmp4, result) );
12393 ins_pipe( pipe_slow );
12394 %}
12395
12396 instruct string_indexof(eSIRegP str1, eDIRegP str2, regXD tmp1, eAXRegI tmp2,
12397 eCXRegI tmp3, eDXRegI tmp4, eBXRegI result, eFlagsReg cr) %{
12398 predicate(UseSSE42Intrinsics);
12399 match(Set result (StrIndexOf str1 str2));
12400 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, KILL tmp2, KILL tmp3, KILL tmp4, KILL cr);
12401
12402 format %{ "String IndexOf $str1,$str2 -> $result // KILL EAX, ECX, EDX" %}
12403 ins_encode( enc_String_IndexOf(str1, str2, tmp1, tmp2, tmp3, tmp4, result) );
12404 ins_pipe( pipe_slow );
12405 %}
12406
12407 // fast array equals
12408 instruct array_equals(eDIRegP ary1, eSIRegP ary2, regXD tmp1, regXD tmp2, eBXRegI tmp3,
12409 eDXRegI tmp4, eAXRegI result, eFlagsReg cr) %{
12410 match(Set result (AryEq ary1 ary2));
12411 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
12412 //ins_cost(300);
12413
12414 format %{ "Array Equals $ary1,$ary2 -> $result // KILL EBX, EDX" %}
12415 ins_encode( enc_Array_Equals(ary1, ary2, tmp1, tmp2, tmp3, tmp4, result) );
12416 ins_pipe( pipe_slow );
12417 %}
12418
12419 //----------Control Flow Instructions------------------------------------------
12420 // Signed compare Instructions
12421 instruct compI_eReg(eFlagsReg cr, eRegI op1, eRegI op2) %{
12422 match(Set cr (CmpI op1 op2));
12423 effect( DEF cr, USE op1, USE op2 );
12424 format %{ "CMP $op1,$op2" %}
12425 opcode(0x3B); /* Opcode 3B /r */
12426 ins_encode( OpcP, RegReg( op1, op2) );
12427 ins_pipe( ialu_cr_reg_reg );
12428 %}
12429
12430 instruct compI_eReg_imm(eFlagsReg cr, eRegI op1, immI op2) %{
12431 match(Set cr (CmpI op1 op2));
12432 effect( DEF cr, USE op1 );
12433 format %{ "CMP $op1,$op2" %}
12434 opcode(0x81,0x07); /* Opcode 81 /7 */
12435 // ins_encode( RegImm( op1, op2) ); /* Was CmpImm */
12436 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
12437 ins_pipe( ialu_cr_reg_imm );
12438 %}
12439
12440 // Cisc-spilled version of cmpI_eReg
12441 instruct compI_eReg_mem(eFlagsReg cr, eRegI op1, memory op2) %{
12442 match(Set cr (CmpI op1 (LoadI op2)));
12443
12444 format %{ "CMP $op1,$op2" %}
12445 ins_cost(500);
12446 opcode(0x3B); /* Opcode 3B /r */
12447 ins_encode( OpcP, RegMem( op1, op2) );
12448 ins_pipe( ialu_cr_reg_mem );
12449 %}
12450
12451 instruct testI_reg( eFlagsReg cr, eRegI src, immI0 zero ) %{
12452 match(Set cr (CmpI src zero));
12453 effect( DEF cr, USE src );
12454
12455 format %{ "TEST $src,$src" %}
12456 opcode(0x85);
12457 ins_encode( OpcP, RegReg( src, src ) );
12458 ins_pipe( ialu_cr_reg_imm );
12459 %}
12460
12461 instruct testI_reg_imm( eFlagsReg cr, eRegI src, immI con, immI0 zero ) %{
12462 match(Set cr (CmpI (AndI src con) zero));
12463
12464 format %{ "TEST $src,$con" %}
12465 opcode(0xF7,0x00);
12466 ins_encode( OpcP, RegOpc(src), Con32(con) );
12467 ins_pipe( ialu_cr_reg_imm );
12468 %}
12469
12470 instruct testI_reg_mem( eFlagsReg cr, eRegI src, memory mem, immI0 zero ) %{
12471 match(Set cr (CmpI (AndI src mem) zero));
12472
12473 format %{ "TEST $src,$mem" %}
12474 opcode(0x85);
12475 ins_encode( OpcP, RegMem( src, mem ) );
12476 ins_pipe( ialu_cr_reg_mem );
12477 %}
12478
12479 // Unsigned compare Instructions; really, same as signed except they
12480 // produce an eFlagsRegU instead of eFlagsReg.
12481 instruct compU_eReg(eFlagsRegU cr, eRegI op1, eRegI op2) %{
12482 match(Set cr (CmpU op1 op2));
12483
12484 format %{ "CMPu $op1,$op2" %}
12485 opcode(0x3B); /* Opcode 3B /r */
12486 ins_encode( OpcP, RegReg( op1, op2) );
12487 ins_pipe( ialu_cr_reg_reg );
12488 %}
12489
12490 instruct compU_eReg_imm(eFlagsRegU cr, eRegI op1, immI op2) %{
12491 match(Set cr (CmpU op1 op2));
12492
12493 format %{ "CMPu $op1,$op2" %}
12494 opcode(0x81,0x07); /* Opcode 81 /7 */
12495 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
12496 ins_pipe( ialu_cr_reg_imm );
12497 %}
12498
12499 // // Cisc-spilled version of cmpU_eReg
12500 instruct compU_eReg_mem(eFlagsRegU cr, eRegI op1, memory op2) %{
12501 match(Set cr (CmpU op1 (LoadI op2)));
12502
12503 format %{ "CMPu $op1,$op2" %}
12504 ins_cost(500);
12505 opcode(0x3B); /* Opcode 3B /r */
12506 ins_encode( OpcP, RegMem( op1, op2) );
12507 ins_pipe( ialu_cr_reg_mem );
12508 %}
12509
12510 // // Cisc-spilled version of cmpU_eReg
12511 //instruct compU_mem_eReg(eFlagsRegU cr, memory op1, eRegI op2) %{
12512 // match(Set cr (CmpU (LoadI op1) op2));
12513 //
12514 // format %{ "CMPu $op1,$op2" %}
12515 // ins_cost(500);
12516 // opcode(0x39); /* Opcode 39 /r */
12517 // ins_encode( OpcP, RegMem( op1, op2) );
12518 //%}
12519
12520 instruct testU_reg( eFlagsRegU cr, eRegI src, immI0 zero ) %{
12521 match(Set cr (CmpU src zero));
12522
12523 format %{ "TESTu $src,$src" %}
12524 opcode(0x85);
12525 ins_encode( OpcP, RegReg( src, src ) );
12526 ins_pipe( ialu_cr_reg_imm );
12527 %}
12528
12529 // Unsigned pointer compare Instructions
12530 instruct compP_eReg(eFlagsRegU cr, eRegP op1, eRegP op2) %{
12531 match(Set cr (CmpP op1 op2));
12532
12533 format %{ "CMPu $op1,$op2" %}
12534 opcode(0x3B); /* Opcode 3B /r */
12535 ins_encode( OpcP, RegReg( op1, op2) );
12536 ins_pipe( ialu_cr_reg_reg );
12537 %}
12538
12539 instruct compP_eReg_imm(eFlagsRegU cr, eRegP op1, immP op2) %{
12540 match(Set cr (CmpP op1 op2));
12541
12542 format %{ "CMPu $op1,$op2" %}
12543 opcode(0x81,0x07); /* Opcode 81 /7 */
12544 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
12545 ins_pipe( ialu_cr_reg_imm );
12546 %}
12547
12548 // // Cisc-spilled version of cmpP_eReg
12549 instruct compP_eReg_mem(eFlagsRegU cr, eRegP op1, memory op2) %{
12550 match(Set cr (CmpP op1 (LoadP op2)));
12551
12552 format %{ "CMPu $op1,$op2" %}
12553 ins_cost(500);
12554 opcode(0x3B); /* Opcode 3B /r */
12555 ins_encode( OpcP, RegMem( op1, op2) );
12556 ins_pipe( ialu_cr_reg_mem );
12557 %}
12558
12559 // // Cisc-spilled version of cmpP_eReg
12560 //instruct compP_mem_eReg(eFlagsRegU cr, memory op1, eRegP op2) %{
12561 // match(Set cr (CmpP (LoadP op1) op2));
12562 //
12563 // format %{ "CMPu $op1,$op2" %}
12564 // ins_cost(500);
12565 // opcode(0x39); /* Opcode 39 /r */
12566 // ins_encode( OpcP, RegMem( op1, op2) );
12567 //%}
12568
12569 // Compare raw pointer (used in out-of-heap check).
12570 // Only works because non-oop pointers must be raw pointers
12571 // and raw pointers have no anti-dependencies.
12572 instruct compP_mem_eReg( eFlagsRegU cr, eRegP op1, memory op2 ) %{
12573 predicate( !n->in(2)->in(2)->bottom_type()->isa_oop_ptr() );
12574 match(Set cr (CmpP op1 (LoadP op2)));
12575
12576 format %{ "CMPu $op1,$op2" %}
12577 opcode(0x3B); /* Opcode 3B /r */
12578 ins_encode( OpcP, RegMem( op1, op2) );
12579 ins_pipe( ialu_cr_reg_mem );
12580 %}
12581
12582 //
12583 // This will generate a signed flags result. This should be ok
12584 // since any compare to a zero should be eq/neq.
12585 instruct testP_reg( eFlagsReg cr, eRegP src, immP0 zero ) %{
12586 match(Set cr (CmpP src zero));
12587
12588 format %{ "TEST $src,$src" %}
12589 opcode(0x85);
12590 ins_encode( OpcP, RegReg( src, src ) );
12591 ins_pipe( ialu_cr_reg_imm );
12592 %}
12593
12594 // Cisc-spilled version of testP_reg
12595 // This will generate a signed flags result. This should be ok
12596 // since any compare to a zero should be eq/neq.
12597 instruct testP_Reg_mem( eFlagsReg cr, memory op, immI0 zero ) %{
12598 match(Set cr (CmpP (LoadP op) zero));
12599
12600 format %{ "TEST $op,0xFFFFFFFF" %}
12601 ins_cost(500);
12602 opcode(0xF7); /* Opcode F7 /0 */
12603 ins_encode( OpcP, RMopc_Mem(0x00,op), Con_d32(0xFFFFFFFF) );
12604 ins_pipe( ialu_cr_reg_imm );
12605 %}
12606
12607 // Yanked all unsigned pointer compare operations.
12608 // Pointer compares are done with CmpP which is already unsigned.
12609
12610 //----------Max and Min--------------------------------------------------------
12611 // Min Instructions
12612 ////
12613 // *** Min and Max using the conditional move are slower than the
12614 // *** branch version on a Pentium III.
12615 // // Conditional move for min
12616 //instruct cmovI_reg_lt( eRegI op2, eRegI op1, eFlagsReg cr ) %{
12617 // effect( USE_DEF op2, USE op1, USE cr );
12618 // format %{ "CMOVlt $op2,$op1\t! min" %}
12619 // opcode(0x4C,0x0F);
12620 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) );
12621 // ins_pipe( pipe_cmov_reg );
12622 //%}
12623 //
12624 //// Min Register with Register (P6 version)
12625 //instruct minI_eReg_p6( eRegI op1, eRegI op2 ) %{
12626 // predicate(VM_Version::supports_cmov() );
12627 // match(Set op2 (MinI op1 op2));
12628 // ins_cost(200);
12629 // expand %{
12630 // eFlagsReg cr;
12631 // compI_eReg(cr,op1,op2);
12632 // cmovI_reg_lt(op2,op1,cr);
12633 // %}
12634 //%}
12635
12636 // Min Register with Register (generic version)
12637 instruct minI_eReg(eRegI dst, eRegI src, eFlagsReg flags) %{
12638 match(Set dst (MinI dst src));
12639 effect(KILL flags);
12640 ins_cost(300);
12641
12642 format %{ "MIN $dst,$src" %}
12643 opcode(0xCC);
12644 ins_encode( min_enc(dst,src) );
12645 ins_pipe( pipe_slow );
12646 %}
12647
12648 // Max Register with Register
12649 // *** Min and Max using the conditional move are slower than the
12650 // *** branch version on a Pentium III.
12651 // // Conditional move for max
12652 //instruct cmovI_reg_gt( eRegI op2, eRegI op1, eFlagsReg cr ) %{
12653 // effect( USE_DEF op2, USE op1, USE cr );
12654 // format %{ "CMOVgt $op2,$op1\t! max" %}
12655 // opcode(0x4F,0x0F);
12656 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) );
12657 // ins_pipe( pipe_cmov_reg );
12658 //%}
12659 //
12660 // // Max Register with Register (P6 version)
12661 //instruct maxI_eReg_p6( eRegI op1, eRegI op2 ) %{
12662 // predicate(VM_Version::supports_cmov() );
12663 // match(Set op2 (MaxI op1 op2));
12664 // ins_cost(200);
12665 // expand %{
12666 // eFlagsReg cr;
12667 // compI_eReg(cr,op1,op2);
12668 // cmovI_reg_gt(op2,op1,cr);
12669 // %}
12670 //%}
12671
12672 // Max Register with Register (generic version)
12673 instruct maxI_eReg(eRegI dst, eRegI src, eFlagsReg flags) %{
12674 match(Set dst (MaxI dst src));
12675 effect(KILL flags);
12676 ins_cost(300);
12677
12678 format %{ "MAX $dst,$src" %}
12679 opcode(0xCC);
12680 ins_encode( max_enc(dst,src) );
12681 ins_pipe( pipe_slow );
12682 %}
12683
12684 // ============================================================================
12685 // Branch Instructions
12686 // Jump Table
12687 instruct jumpXtnd(eRegI switch_val) %{
12688 match(Jump switch_val);
12689 ins_cost(350);
12690
12691 format %{ "JMP [table_base](,$switch_val,1)\n\t" %}
12692
12693 ins_encode %{
12694 address table_base = __ address_table_constant(_index2label);
12695
12696 // Jump to Address(table_base + switch_reg)
12697 InternalAddress table(table_base);
12698 Address index(noreg, $switch_val$$Register, Address::times_1);
12699 __ jump(ArrayAddress(table, index));
12700 %}
12701 ins_pc_relative(1);
12702 ins_pipe(pipe_jmp);
12703 %}
12704
12705 // Jump Direct - Label defines a relative address from JMP+1
12706 instruct jmpDir(label labl) %{
12707 match(Goto);
12708 effect(USE labl);
12709
12710 ins_cost(300);
12711 format %{ "JMP $labl" %}
12712 size(5);
12713 opcode(0xE9);
12714 ins_encode( OpcP, Lbl( labl ) );
12715 ins_pipe( pipe_jmp );
12716 ins_pc_relative(1);
12717 %}
12718
12719 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12720 instruct jmpCon(cmpOp cop, eFlagsReg cr, label labl) %{
12721 match(If cop cr);
12722 effect(USE labl);
12723
12724 ins_cost(300);
12725 format %{ "J$cop $labl" %}
12726 size(6);
12727 opcode(0x0F, 0x80);
12728 ins_encode( Jcc( cop, labl) );
12729 ins_pipe( pipe_jcc );
12730 ins_pc_relative(1);
12731 %}
12732
12733 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12734 instruct jmpLoopEnd(cmpOp cop, eFlagsReg cr, label labl) %{
12735 match(CountedLoopEnd cop cr);
12736 effect(USE labl);
12737
12738 ins_cost(300);
12739 format %{ "J$cop $labl\t# Loop end" %}
12740 size(6);
12741 opcode(0x0F, 0x80);
12742 ins_encode( Jcc( cop, labl) );
12743 ins_pipe( pipe_jcc );
12744 ins_pc_relative(1);
12745 %}
12746
12747 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12748 instruct jmpLoopEndU(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12749 match(CountedLoopEnd cop cmp);
12750 effect(USE labl);
12751
12752 ins_cost(300);
12753 format %{ "J$cop,u $labl\t# Loop end" %}
12754 size(6);
12755 opcode(0x0F, 0x80);
12756 ins_encode( Jcc( cop, labl) );
12757 ins_pipe( pipe_jcc );
12758 ins_pc_relative(1);
12759 %}
12760
12761 instruct jmpLoopEndUCF(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12762 match(CountedLoopEnd cop cmp);
12763 effect(USE labl);
12764
12765 ins_cost(200);
12766 format %{ "J$cop,u $labl\t# Loop end" %}
12767 size(6);
12768 opcode(0x0F, 0x80);
12769 ins_encode( Jcc( cop, labl) );
12770 ins_pipe( pipe_jcc );
12771 ins_pc_relative(1);
12772 %}
12773
12774 // Jump Direct Conditional - using unsigned comparison
12775 instruct jmpConU(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12776 match(If cop cmp);
12777 effect(USE labl);
12778
12779 ins_cost(300);
12780 format %{ "J$cop,u $labl" %}
12781 size(6);
12782 opcode(0x0F, 0x80);
12783 ins_encode(Jcc(cop, labl));
12784 ins_pipe(pipe_jcc);
12785 ins_pc_relative(1);
12786 %}
12787
12788 instruct jmpConUCF(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12789 match(If cop cmp);
12790 effect(USE labl);
12791
12792 ins_cost(200);
12793 format %{ "J$cop,u $labl" %}
12794 size(6);
12795 opcode(0x0F, 0x80);
12796 ins_encode(Jcc(cop, labl));
12797 ins_pipe(pipe_jcc);
12798 ins_pc_relative(1);
12799 %}
12800
12801 instruct jmpConUCF2(cmpOpUCF2 cop, eFlagsRegUCF cmp, label labl) %{
12802 match(If cop cmp);
12803 effect(USE labl);
12804
12805 ins_cost(200);
12806 format %{ $$template
12807 if ($cop$$cmpcode == Assembler::notEqual) {
12808 $$emit$$"JP,u $labl\n\t"
12809 $$emit$$"J$cop,u $labl"
12810 } else {
12811 $$emit$$"JP,u done\n\t"
12812 $$emit$$"J$cop,u $labl\n\t"
12813 $$emit$$"done:"
12814 }
12815 %}
12816 size(12);
12817 opcode(0x0F, 0x80);
12818 ins_encode %{
12819 Label* l = $labl$$label;
12820 $$$emit8$primary;
12821 emit_cc(cbuf, $secondary, Assembler::parity);
12822 int parity_disp = -1;
12823 bool ok = false;
12824 if ($cop$$cmpcode == Assembler::notEqual) {
12825 // the two jumps 6 bytes apart so the jump distances are too
12826 parity_disp = l ? (l->loc_pos() - (cbuf.code_size() + 4)) : 0;
12827 } else if ($cop$$cmpcode == Assembler::equal) {
12828 parity_disp = 6;
12829 ok = true;
12830 } else {
12831 ShouldNotReachHere();
12832 }
12833 emit_d32(cbuf, parity_disp);
12834 $$$emit8$primary;
12835 emit_cc(cbuf, $secondary, $cop$$cmpcode);
12836 int disp = l ? (l->loc_pos() - (cbuf.code_size() + 4)) : 0;
12837 emit_d32(cbuf, disp);
12838 %}
12839 ins_pipe(pipe_jcc);
12840 ins_pc_relative(1);
12841 %}
12842
12843 // ============================================================================
12844 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
12845 // array for an instance of the superklass. Set a hidden internal cache on a
12846 // hit (cache is checked with exposed code in gen_subtype_check()). Return
12847 // NZ for a miss or zero for a hit. The encoding ALSO sets flags.
12848 instruct partialSubtypeCheck( eDIRegP result, eSIRegP sub, eAXRegP super, eCXRegI rcx, eFlagsReg cr ) %{
12849 match(Set result (PartialSubtypeCheck sub super));
12850 effect( KILL rcx, KILL cr );
12851
12852 ins_cost(1100); // slightly larger than the next version
12853 format %{ "MOV EDI,[$sub+Klass::secondary_supers]\n\t"
12854 "MOV ECX,[EDI+arrayKlass::length]\t# length to scan\n\t"
12855 "ADD EDI,arrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t"
12856 "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t"
12857 "JNE,s miss\t\t# Missed: EDI not-zero\n\t"
12858 "MOV [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache\n\t"
12859 "XOR $result,$result\t\t Hit: EDI zero\n\t"
12860 "miss:\t" %}
12861
12862 opcode(0x1); // Force a XOR of EDI
12863 ins_encode( enc_PartialSubtypeCheck() );
12864 ins_pipe( pipe_slow );
12865 %}
12866
12867 instruct partialSubtypeCheck_vs_Zero( eFlagsReg cr, eSIRegP sub, eAXRegP super, eCXRegI rcx, eDIRegP result, immP0 zero ) %{
12868 match(Set cr (CmpP (PartialSubtypeCheck sub super) zero));
12869 effect( KILL rcx, KILL result );
12870
12871 ins_cost(1000);
12872 format %{ "MOV EDI,[$sub+Klass::secondary_supers]\n\t"
12873 "MOV ECX,[EDI+arrayKlass::length]\t# length to scan\n\t"
12874 "ADD EDI,arrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t"
12875 "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t"
12876 "JNE,s miss\t\t# Missed: flags NZ\n\t"
12877 "MOV [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache, flags Z\n\t"
12878 "miss:\t" %}
12879
12880 opcode(0x0); // No need to XOR EDI
12881 ins_encode( enc_PartialSubtypeCheck() );
12882 ins_pipe( pipe_slow );
12883 %}
12884
12885 // ============================================================================
12886 // Branch Instructions -- short offset versions
12887 //
12888 // These instructions are used to replace jumps of a long offset (the default
12889 // match) with jumps of a shorter offset. These instructions are all tagged
12890 // with the ins_short_branch attribute, which causes the ADLC to suppress the
12891 // match rules in general matching. Instead, the ADLC generates a conversion
12892 // method in the MachNode which can be used to do in-place replacement of the
12893 // long variant with the shorter variant. The compiler will determine if a
12894 // branch can be taken by the is_short_branch_offset() predicate in the machine
12895 // specific code section of the file.
12896
12897 // Jump Direct - Label defines a relative address from JMP+1
12898 instruct jmpDir_short(label labl) %{
12899 match(Goto);
12900 effect(USE labl);
12901
12902 ins_cost(300);
12903 format %{ "JMP,s $labl" %}
12904 size(2);
12905 opcode(0xEB);
12906 ins_encode( OpcP, LblShort( labl ) );
12907 ins_pipe( pipe_jmp );
12908 ins_pc_relative(1);
12909 ins_short_branch(1);
12910 %}
12911
12912 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12913 instruct jmpCon_short(cmpOp cop, eFlagsReg cr, label labl) %{
12914 match(If cop cr);
12915 effect(USE labl);
12916
12917 ins_cost(300);
12918 format %{ "J$cop,s $labl" %}
12919 size(2);
12920 opcode(0x70);
12921 ins_encode( JccShort( cop, labl) );
12922 ins_pipe( pipe_jcc );
12923 ins_pc_relative(1);
12924 ins_short_branch(1);
12925 %}
12926
12927 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12928 instruct jmpLoopEnd_short(cmpOp cop, eFlagsReg cr, label labl) %{
12929 match(CountedLoopEnd cop cr);
12930 effect(USE labl);
12931
12932 ins_cost(300);
12933 format %{ "J$cop,s $labl\t# Loop end" %}
12934 size(2);
12935 opcode(0x70);
12936 ins_encode( JccShort( cop, labl) );
12937 ins_pipe( pipe_jcc );
12938 ins_pc_relative(1);
12939 ins_short_branch(1);
12940 %}
12941
12942 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12943 instruct jmpLoopEndU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12944 match(CountedLoopEnd cop cmp);
12945 effect(USE labl);
12946
12947 ins_cost(300);
12948 format %{ "J$cop,us $labl\t# Loop end" %}
12949 size(2);
12950 opcode(0x70);
12951 ins_encode( JccShort( cop, labl) );
12952 ins_pipe( pipe_jcc );
12953 ins_pc_relative(1);
12954 ins_short_branch(1);
12955 %}
12956
12957 instruct jmpLoopEndUCF_short(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12958 match(CountedLoopEnd cop cmp);
12959 effect(USE labl);
12960
12961 ins_cost(300);
12962 format %{ "J$cop,us $labl\t# Loop end" %}
12963 size(2);
12964 opcode(0x70);
12965 ins_encode( JccShort( cop, labl) );
12966 ins_pipe( pipe_jcc );
12967 ins_pc_relative(1);
12968 ins_short_branch(1);
12969 %}
12970
12971 // Jump Direct Conditional - using unsigned comparison
12972 instruct jmpConU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12973 match(If cop cmp);
12974 effect(USE labl);
12975
12976 ins_cost(300);
12977 format %{ "J$cop,us $labl" %}
12978 size(2);
12979 opcode(0x70);
12980 ins_encode( JccShort( cop, labl) );
12981 ins_pipe( pipe_jcc );
12982 ins_pc_relative(1);
12983 ins_short_branch(1);
12984 %}
12985
12986 instruct jmpConUCF_short(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12987 match(If cop cmp);
12988 effect(USE labl);
12989
12990 ins_cost(300);
12991 format %{ "J$cop,us $labl" %}
12992 size(2);
12993 opcode(0x70);
12994 ins_encode( JccShort( cop, labl) );
12995 ins_pipe( pipe_jcc );
12996 ins_pc_relative(1);
12997 ins_short_branch(1);
12998 %}
12999
13000 instruct jmpConUCF2_short(cmpOpUCF2 cop, eFlagsRegUCF cmp, label labl) %{
13001 match(If cop cmp);
13002 effect(USE labl);
13003
13004 ins_cost(300);
13005 format %{ $$template
13006 if ($cop$$cmpcode == Assembler::notEqual) {
13007 $$emit$$"JP,u,s $labl\n\t"
13008 $$emit$$"J$cop,u,s $labl"
13009 } else {
13010 $$emit$$"JP,u,s done\n\t"
13011 $$emit$$"J$cop,u,s $labl\n\t"
13012 $$emit$$"done:"
13013 }
13014 %}
13015 size(4);
13016 opcode(0x70);
13017 ins_encode %{
13018 Label* l = $labl$$label;
13019 emit_cc(cbuf, $primary, Assembler::parity);
13020 int parity_disp = -1;
13021 if ($cop$$cmpcode == Assembler::notEqual) {
13022 parity_disp = l ? (l->loc_pos() - (cbuf.code_size() + 1)) : 0;
13023 } else if ($cop$$cmpcode == Assembler::equal) {
13024 parity_disp = 2;
13025 } else {
13026 ShouldNotReachHere();
13027 }
13028 emit_d8(cbuf, parity_disp);
13029 emit_cc(cbuf, $primary, $cop$$cmpcode);
13030 int disp = l ? (l->loc_pos() - (cbuf.code_size() + 1)) : 0;
13031 emit_d8(cbuf, disp);
13032 assert(-128 <= disp && disp <= 127, "Displacement too large for short jmp");
13033 assert(-128 <= parity_disp && parity_disp <= 127, "Displacement too large for short jmp");
13034 %}
13035 ins_pipe(pipe_jcc);
13036 ins_pc_relative(1);
13037 ins_short_branch(1);
13038 %}
13039
13040 // ============================================================================
13041 // Long Compare
13042 //
13043 // Currently we hold longs in 2 registers. Comparing such values efficiently
13044 // is tricky. The flavor of compare used depends on whether we are testing
13045 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit.
13046 // The GE test is the negated LT test. The LE test can be had by commuting
13047 // the operands (yielding a GE test) and then negating; negate again for the
13048 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the
13049 // NE test is negated from that.
13050
13051 // Due to a shortcoming in the ADLC, it mixes up expressions like:
13052 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the
13053 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections
13054 // are collapsed internally in the ADLC's dfa-gen code. The match for
13055 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the
13056 // foo match ends up with the wrong leaf. One fix is to not match both
13057 // reg-reg and reg-zero forms of long-compare. This is unfortunate because
13058 // both forms beat the trinary form of long-compare and both are very useful
13059 // on Intel which has so few registers.
13060
13061 // Manifest a CmpL result in an integer register. Very painful.
13062 // This is the test to avoid.
13063 instruct cmpL3_reg_reg(eSIRegI dst, eRegL src1, eRegL src2, eFlagsReg flags ) %{
13064 match(Set dst (CmpL3 src1 src2));
13065 effect( KILL flags );
13066 ins_cost(1000);
13067 format %{ "XOR $dst,$dst\n\t"
13068 "CMP $src1.hi,$src2.hi\n\t"
13069 "JLT,s m_one\n\t"
13070 "JGT,s p_one\n\t"
13071 "CMP $src1.lo,$src2.lo\n\t"
13072 "JB,s m_one\n\t"
13073 "JEQ,s done\n"
13074 "p_one:\tINC $dst\n\t"
13075 "JMP,s done\n"
13076 "m_one:\tDEC $dst\n"
13077 "done:" %}
13078 ins_encode %{
13079 Label p_one, m_one, done;
13080 __ xorptr($dst$$Register, $dst$$Register);
13081 __ cmpl(HIGH_FROM_LOW($src1$$Register), HIGH_FROM_LOW($src2$$Register));
13082 __ jccb(Assembler::less, m_one);
13083 __ jccb(Assembler::greater, p_one);
13084 __ cmpl($src1$$Register, $src2$$Register);
13085 __ jccb(Assembler::below, m_one);
13086 __ jccb(Assembler::equal, done);
13087 __ bind(p_one);
13088 __ incrementl($dst$$Register);
13089 __ jmpb(done);
13090 __ bind(m_one);
13091 __ decrementl($dst$$Register);
13092 __ bind(done);
13093 %}
13094 ins_pipe( pipe_slow );
13095 %}
13096
13097 //======
13098 // Manifest a CmpL result in the normal flags. Only good for LT or GE
13099 // compares. Can be used for LE or GT compares by reversing arguments.
13100 // NOT GOOD FOR EQ/NE tests.
13101 instruct cmpL_zero_flags_LTGE( flagsReg_long_LTGE flags, eRegL src, immL0 zero ) %{
13102 match( Set flags (CmpL src zero ));
13103 ins_cost(100);
13104 format %{ "TEST $src.hi,$src.hi" %}
13105 opcode(0x85);
13106 ins_encode( OpcP, RegReg_Hi2( src, src ) );
13107 ins_pipe( ialu_cr_reg_reg );
13108 %}
13109
13110 // Manifest a CmpL result in the normal flags. Only good for LT or GE
13111 // compares. Can be used for LE or GT compares by reversing arguments.
13112 // NOT GOOD FOR EQ/NE tests.
13113 instruct cmpL_reg_flags_LTGE( flagsReg_long_LTGE flags, eRegL src1, eRegL src2, eRegI tmp ) %{
13114 match( Set flags (CmpL src1 src2 ));
13115 effect( TEMP tmp );
13116 ins_cost(300);
13117 format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t"
13118 "MOV $tmp,$src1.hi\n\t"
13119 "SBB $tmp,$src2.hi\t! Compute flags for long compare" %}
13120 ins_encode( long_cmp_flags2( src1, src2, tmp ) );
13121 ins_pipe( ialu_cr_reg_reg );
13122 %}
13123
13124 // Long compares reg < zero/req OR reg >= zero/req.
13125 // Just a wrapper for a normal branch, plus the predicate test.
13126 instruct cmpL_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, label labl) %{
13127 match(If cmp flags);
13128 effect(USE labl);
13129 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
13130 expand %{
13131 jmpCon(cmp,flags,labl); // JLT or JGE...
13132 %}
13133 %}
13134
13135 // Compare 2 longs and CMOVE longs.
13136 instruct cmovLL_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, eRegL src) %{
13137 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
13138 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
13139 ins_cost(400);
13140 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
13141 "CMOV$cmp $dst.hi,$src.hi" %}
13142 opcode(0x0F,0x40);
13143 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
13144 ins_pipe( pipe_cmov_reg_long );
13145 %}
13146
13147 instruct cmovLL_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, load_long_memory src) %{
13148 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
13149 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
13150 ins_cost(500);
13151 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
13152 "CMOV$cmp $dst.hi,$src.hi" %}
13153 opcode(0x0F,0x40);
13154 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
13155 ins_pipe( pipe_cmov_reg_long );
13156 %}
13157
13158 // Compare 2 longs and CMOVE ints.
13159 instruct cmovII_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegI dst, eRegI src) %{
13160 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
13161 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
13162 ins_cost(200);
13163 format %{ "CMOV$cmp $dst,$src" %}
13164 opcode(0x0F,0x40);
13165 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
13166 ins_pipe( pipe_cmov_reg );
13167 %}
13168
13169 instruct cmovII_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegI dst, memory src) %{
13170 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
13171 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
13172 ins_cost(250);
13173 format %{ "CMOV$cmp $dst,$src" %}
13174 opcode(0x0F,0x40);
13175 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
13176 ins_pipe( pipe_cmov_mem );
13177 %}
13178
13179 // Compare 2 longs and CMOVE ints.
13180 instruct cmovPP_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegP dst, eRegP src) %{
13181 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
13182 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
13183 ins_cost(200);
13184 format %{ "CMOV$cmp $dst,$src" %}
13185 opcode(0x0F,0x40);
13186 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
13187 ins_pipe( pipe_cmov_reg );
13188 %}
13189
13190 // Compare 2 longs and CMOVE doubles
13191 instruct cmovDD_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regD dst, regD src) %{
13192 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
13193 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
13194 ins_cost(200);
13195 expand %{
13196 fcmovD_regS(cmp,flags,dst,src);
13197 %}
13198 %}
13199
13200 // Compare 2 longs and CMOVE doubles
13201 instruct cmovXDD_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regXD dst, regXD src) %{
13202 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
13203 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
13204 ins_cost(200);
13205 expand %{
13206 fcmovXD_regS(cmp,flags,dst,src);
13207 %}
13208 %}
13209
13210 instruct cmovFF_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regF dst, regF src) %{
13211 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
13212 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
13213 ins_cost(200);
13214 expand %{
13215 fcmovF_regS(cmp,flags,dst,src);
13216 %}
13217 %}
13218
13219 instruct cmovXX_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regX dst, regX src) %{
13220 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
13221 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
13222 ins_cost(200);
13223 expand %{
13224 fcmovX_regS(cmp,flags,dst,src);
13225 %}
13226 %}
13227
13228 //======
13229 // Manifest a CmpL result in the normal flags. Only good for EQ/NE compares.
13230 instruct cmpL_zero_flags_EQNE( flagsReg_long_EQNE flags, eRegL src, immL0 zero, eRegI tmp ) %{
13231 match( Set flags (CmpL src zero ));
13232 effect(TEMP tmp);
13233 ins_cost(200);
13234 format %{ "MOV $tmp,$src.lo\n\t"
13235 "OR $tmp,$src.hi\t! Long is EQ/NE 0?" %}
13236 ins_encode( long_cmp_flags0( src, tmp ) );
13237 ins_pipe( ialu_reg_reg_long );
13238 %}
13239
13240 // Manifest a CmpL result in the normal flags. Only good for EQ/NE compares.
13241 instruct cmpL_reg_flags_EQNE( flagsReg_long_EQNE flags, eRegL src1, eRegL src2 ) %{
13242 match( Set flags (CmpL src1 src2 ));
13243 ins_cost(200+300);
13244 format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t"
13245 "JNE,s skip\n\t"
13246 "CMP $src1.hi,$src2.hi\n\t"
13247 "skip:\t" %}
13248 ins_encode( long_cmp_flags1( src1, src2 ) );
13249 ins_pipe( ialu_cr_reg_reg );
13250 %}
13251
13252 // Long compare reg == zero/reg OR reg != zero/reg
13253 // Just a wrapper for a normal branch, plus the predicate test.
13254 instruct cmpL_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, label labl) %{
13255 match(If cmp flags);
13256 effect(USE labl);
13257 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
13258 expand %{
13259 jmpCon(cmp,flags,labl); // JEQ or JNE...
13260 %}
13261 %}
13262
13263 // Compare 2 longs and CMOVE longs.
13264 instruct cmovLL_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, eRegL src) %{
13265 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
13266 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
13267 ins_cost(400);
13268 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
13269 "CMOV$cmp $dst.hi,$src.hi" %}
13270 opcode(0x0F,0x40);
13271 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
13272 ins_pipe( pipe_cmov_reg_long );
13273 %}
13274
13275 instruct cmovLL_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, load_long_memory src) %{
13276 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
13277 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
13278 ins_cost(500);
13279 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
13280 "CMOV$cmp $dst.hi,$src.hi" %}
13281 opcode(0x0F,0x40);
13282 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
13283 ins_pipe( pipe_cmov_reg_long );
13284 %}
13285
13286 // Compare 2 longs and CMOVE ints.
13287 instruct cmovII_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegI dst, eRegI src) %{
13288 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
13289 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
13290 ins_cost(200);
13291 format %{ "CMOV$cmp $dst,$src" %}
13292 opcode(0x0F,0x40);
13293 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
13294 ins_pipe( pipe_cmov_reg );
13295 %}
13296
13297 instruct cmovII_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegI dst, memory src) %{
13298 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
13299 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
13300 ins_cost(250);
13301 format %{ "CMOV$cmp $dst,$src" %}
13302 opcode(0x0F,0x40);
13303 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
13304 ins_pipe( pipe_cmov_mem );
13305 %}
13306
13307 // Compare 2 longs and CMOVE ints.
13308 instruct cmovPP_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegP dst, eRegP src) %{
13309 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
13310 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
13311 ins_cost(200);
13312 format %{ "CMOV$cmp $dst,$src" %}
13313 opcode(0x0F,0x40);
13314 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
13315 ins_pipe( pipe_cmov_reg );
13316 %}
13317
13318 // Compare 2 longs and CMOVE doubles
13319 instruct cmovDD_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regD dst, regD src) %{
13320 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
13321 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
13322 ins_cost(200);
13323 expand %{
13324 fcmovD_regS(cmp,flags,dst,src);
13325 %}
13326 %}
13327
13328 // Compare 2 longs and CMOVE doubles
13329 instruct cmovXDD_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regXD dst, regXD src) %{
13330 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
13331 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
13332 ins_cost(200);
13333 expand %{
13334 fcmovXD_regS(cmp,flags,dst,src);
13335 %}
13336 %}
13337
13338 instruct cmovFF_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regF dst, regF src) %{
13339 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
13340 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
13341 ins_cost(200);
13342 expand %{
13343 fcmovF_regS(cmp,flags,dst,src);
13344 %}
13345 %}
13346
13347 instruct cmovXX_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regX dst, regX src) %{
13348 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
13349 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
13350 ins_cost(200);
13351 expand %{
13352 fcmovX_regS(cmp,flags,dst,src);
13353 %}
13354 %}
13355
13356 //======
13357 // Manifest a CmpL result in the normal flags. Only good for LE or GT compares.
13358 // Same as cmpL_reg_flags_LEGT except must negate src
13359 instruct cmpL_zero_flags_LEGT( flagsReg_long_LEGT flags, eRegL src, immL0 zero, eRegI tmp ) %{
13360 match( Set flags (CmpL src zero ));
13361 effect( TEMP tmp );
13362 ins_cost(300);
13363 format %{ "XOR $tmp,$tmp\t# Long compare for -$src < 0, use commuted test\n\t"
13364 "CMP $tmp,$src.lo\n\t"
13365 "SBB $tmp,$src.hi\n\t" %}
13366 ins_encode( long_cmp_flags3(src, tmp) );
13367 ins_pipe( ialu_reg_reg_long );
13368 %}
13369
13370 // Manifest a CmpL result in the normal flags. Only good for LE or GT compares.
13371 // Same as cmpL_reg_flags_LTGE except operands swapped. Swapping operands
13372 // requires a commuted test to get the same result.
13373 instruct cmpL_reg_flags_LEGT( flagsReg_long_LEGT flags, eRegL src1, eRegL src2, eRegI tmp ) %{
13374 match( Set flags (CmpL src1 src2 ));
13375 effect( TEMP tmp );
13376 ins_cost(300);
13377 format %{ "CMP $src2.lo,$src1.lo\t! Long compare, swapped operands, use with commuted test\n\t"
13378 "MOV $tmp,$src2.hi\n\t"
13379 "SBB $tmp,$src1.hi\t! Compute flags for long compare" %}
13380 ins_encode( long_cmp_flags2( src2, src1, tmp ) );
13381 ins_pipe( ialu_cr_reg_reg );
13382 %}
13383
13384 // Long compares reg < zero/req OR reg >= zero/req.
13385 // Just a wrapper for a normal branch, plus the predicate test
13386 instruct cmpL_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, label labl) %{
13387 match(If cmp flags);
13388 effect(USE labl);
13389 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le );
13390 ins_cost(300);
13391 expand %{
13392 jmpCon(cmp,flags,labl); // JGT or JLE...
13393 %}
13394 %}
13395
13396 // Compare 2 longs and CMOVE longs.
13397 instruct cmovLL_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, eRegL src) %{
13398 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
13399 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
13400 ins_cost(400);
13401 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
13402 "CMOV$cmp $dst.hi,$src.hi" %}
13403 opcode(0x0F,0x40);
13404 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
13405 ins_pipe( pipe_cmov_reg_long );
13406 %}
13407
13408 instruct cmovLL_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, load_long_memory src) %{
13409 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
13410 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
13411 ins_cost(500);
13412 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
13413 "CMOV$cmp $dst.hi,$src.hi+4" %}
13414 opcode(0x0F,0x40);
13415 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
13416 ins_pipe( pipe_cmov_reg_long );
13417 %}
13418
13419 // Compare 2 longs and CMOVE ints.
13420 instruct cmovII_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegI dst, eRegI src) %{
13421 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
13422 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
13423 ins_cost(200);
13424 format %{ "CMOV$cmp $dst,$src" %}
13425 opcode(0x0F,0x40);
13426 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
13427 ins_pipe( pipe_cmov_reg );
13428 %}
13429
13430 instruct cmovII_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegI dst, memory src) %{
13431 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
13432 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
13433 ins_cost(250);
13434 format %{ "CMOV$cmp $dst,$src" %}
13435 opcode(0x0F,0x40);
13436 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
13437 ins_pipe( pipe_cmov_mem );
13438 %}
13439
13440 // Compare 2 longs and CMOVE ptrs.
13441 instruct cmovPP_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegP dst, eRegP src) %{
13442 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
13443 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
13444 ins_cost(200);
13445 format %{ "CMOV$cmp $dst,$src" %}
13446 opcode(0x0F,0x40);
13447 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
13448 ins_pipe( pipe_cmov_reg );
13449 %}
13450
13451 // Compare 2 longs and CMOVE doubles
13452 instruct cmovDD_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regD dst, regD src) %{
13453 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
13454 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
13455 ins_cost(200);
13456 expand %{
13457 fcmovD_regS(cmp,flags,dst,src);
13458 %}
13459 %}
13460
13461 // Compare 2 longs and CMOVE doubles
13462 instruct cmovXDD_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regXD dst, regXD src) %{
13463 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
13464 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
13465 ins_cost(200);
13466 expand %{
13467 fcmovXD_regS(cmp,flags,dst,src);
13468 %}
13469 %}
13470
13471 instruct cmovFF_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regF dst, regF src) %{
13472 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
13473 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
13474 ins_cost(200);
13475 expand %{
13476 fcmovF_regS(cmp,flags,dst,src);
13477 %}
13478 %}
13479
13480
13481 instruct cmovXX_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regX dst, regX src) %{
13482 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
13483 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
13484 ins_cost(200);
13485 expand %{
13486 fcmovX_regS(cmp,flags,dst,src);
13487 %}
13488 %}
13489
13490
13491 // ============================================================================
13492 // Procedure Call/Return Instructions
13493 // Call Java Static Instruction
13494 // Note: If this code changes, the corresponding ret_addr_offset() and
13495 // compute_padding() functions will have to be adjusted.
13496 instruct CallStaticJavaDirect(method meth) %{
13497 match(CallStaticJava);
13498 effect(USE meth);
13499
13500 ins_cost(300);
13501 format %{ "CALL,static " %}
13502 opcode(0xE8); /* E8 cd */
13503 ins_encode( pre_call_FPU,
13504 Java_Static_Call( meth ),
13505 call_epilog,
13506 post_call_FPU );
13507 ins_pipe( pipe_slow );
13508 ins_pc_relative(1);
13509 ins_alignment(4);
13510 %}
13511
13512 // Call Java Dynamic Instruction
13513 // Note: If this code changes, the corresponding ret_addr_offset() and
13514 // compute_padding() functions will have to be adjusted.
13515 instruct CallDynamicJavaDirect(method meth) %{
13516 match(CallDynamicJava);
13517 effect(USE meth);
13518
13519 ins_cost(300);
13520 format %{ "MOV EAX,(oop)-1\n\t"
13521 "CALL,dynamic" %}
13522 opcode(0xE8); /* E8 cd */
13523 ins_encode( pre_call_FPU,
13524 Java_Dynamic_Call( meth ),
13525 call_epilog,
13526 post_call_FPU );
13527 ins_pipe( pipe_slow );
13528 ins_pc_relative(1);
13529 ins_alignment(4);
13530 %}
13531
13532 // Call Runtime Instruction
13533 instruct CallRuntimeDirect(method meth) %{
13534 match(CallRuntime );
13535 effect(USE meth);
13536
13537 ins_cost(300);
13538 format %{ "CALL,runtime " %}
13539 opcode(0xE8); /* E8 cd */
13540 // Use FFREEs to clear entries in float stack
13541 ins_encode( pre_call_FPU,
13542 FFree_Float_Stack_All,
13543 Java_To_Runtime( meth ),
13544 post_call_FPU );
13545 ins_pipe( pipe_slow );
13546 ins_pc_relative(1);
13547 %}
13548
13549 // Call runtime without safepoint
13550 instruct CallLeafDirect(method meth) %{
13551 match(CallLeaf);
13552 effect(USE meth);
13553
13554 ins_cost(300);
13555 format %{ "CALL_LEAF,runtime " %}
13556 opcode(0xE8); /* E8 cd */
13557 ins_encode( pre_call_FPU,
13558 FFree_Float_Stack_All,
13559 Java_To_Runtime( meth ),
13560 Verify_FPU_For_Leaf, post_call_FPU );
13561 ins_pipe( pipe_slow );
13562 ins_pc_relative(1);
13563 %}
13564
13565 instruct CallLeafNoFPDirect(method meth) %{
13566 match(CallLeafNoFP);
13567 effect(USE meth);
13568
13569 ins_cost(300);
13570 format %{ "CALL_LEAF_NOFP,runtime " %}
13571 opcode(0xE8); /* E8 cd */
13572 ins_encode(Java_To_Runtime(meth));
13573 ins_pipe( pipe_slow );
13574 ins_pc_relative(1);
13575 %}
13576
13577
13578 // Return Instruction
13579 // Remove the return address & jump to it.
13580 instruct Ret() %{
13581 match(Return);
13582 format %{ "RET" %}
13583 opcode(0xC3);
13584 ins_encode(OpcP);
13585 ins_pipe( pipe_jmp );
13586 %}
13587
13588 // Tail Call; Jump from runtime stub to Java code.
13589 // Also known as an 'interprocedural jump'.
13590 // Target of jump will eventually return to caller.
13591 // TailJump below removes the return address.
13592 instruct TailCalljmpInd(eRegP_no_EBP jump_target, eBXRegP method_oop) %{
13593 match(TailCall jump_target method_oop );
13594 ins_cost(300);
13595 format %{ "JMP $jump_target \t# EBX holds method oop" %}
13596 opcode(0xFF, 0x4); /* Opcode FF /4 */
13597 ins_encode( OpcP, RegOpc(jump_target) );
13598 ins_pipe( pipe_jmp );
13599 %}
13600
13601
13602 // Tail Jump; remove the return address; jump to target.
13603 // TailCall above leaves the return address around.
13604 instruct tailjmpInd(eRegP_no_EBP jump_target, eAXRegP ex_oop) %{
13605 match( TailJump jump_target ex_oop );
13606 ins_cost(300);
13607 format %{ "POP EDX\t# pop return address into dummy\n\t"
13608 "JMP $jump_target " %}
13609 opcode(0xFF, 0x4); /* Opcode FF /4 */
13610 ins_encode( enc_pop_rdx,
13611 OpcP, RegOpc(jump_target) );
13612 ins_pipe( pipe_jmp );
13613 %}
13614
13615 // Create exception oop: created by stack-crawling runtime code.
13616 // Created exception is now available to this handler, and is setup
13617 // just prior to jumping to this handler. No code emitted.
13618 instruct CreateException( eAXRegP ex_oop )
13619 %{
13620 match(Set ex_oop (CreateEx));
13621
13622 size(0);
13623 // use the following format syntax
13624 format %{ "# exception oop is in EAX; no code emitted" %}
13625 ins_encode();
13626 ins_pipe( empty );
13627 %}
13628
13629
13630 // Rethrow exception:
13631 // The exception oop will come in the first argument position.
13632 // Then JUMP (not call) to the rethrow stub code.
13633 instruct RethrowException()
13634 %{
13635 match(Rethrow);
13636
13637 // use the following format syntax
13638 format %{ "JMP rethrow_stub" %}
13639 ins_encode(enc_rethrow);
13640 ins_pipe( pipe_jmp );
13641 %}
13642
13643 // inlined locking and unlocking
13644
13645
13646 instruct cmpFastLock( eFlagsReg cr, eRegP object, eRegP box, eAXRegI tmp, eRegP scr) %{
13647 match( Set cr (FastLock object box) );
13648 effect( TEMP tmp, TEMP scr );
13649 ins_cost(300);
13650 format %{ "FASTLOCK $object, $box KILLS $tmp,$scr" %}
13651 ins_encode( Fast_Lock(object,box,tmp,scr) );
13652 ins_pipe( pipe_slow );
13653 ins_pc_relative(1);
13654 %}
13655
13656 instruct cmpFastUnlock( eFlagsReg cr, eRegP object, eAXRegP box, eRegP tmp ) %{
13657 match( Set cr (FastUnlock object box) );
13658 effect( TEMP tmp );
13659 ins_cost(300);
13660 format %{ "FASTUNLOCK $object, $box, $tmp" %}
13661 ins_encode( Fast_Unlock(object,box,tmp) );
13662 ins_pipe( pipe_slow );
13663 ins_pc_relative(1);
13664 %}
13665
13666
13667
13668 // ============================================================================
13669 // Safepoint Instruction
13670 instruct safePoint_poll(eFlagsReg cr) %{
13671 match(SafePoint);
13672 effect(KILL cr);
13673
13674 // TODO-FIXME: we currently poll at offset 0 of the safepoint polling page.
13675 // On SPARC that might be acceptable as we can generate the address with
13676 // just a sethi, saving an or. By polling at offset 0 we can end up
13677 // putting additional pressure on the index-0 in the D$. Because of
13678 // alignment (just like the situation at hand) the lower indices tend
13679 // to see more traffic. It'd be better to change the polling address
13680 // to offset 0 of the last $line in the polling page.
13681
13682 format %{ "TSTL #polladdr,EAX\t! Safepoint: poll for GC" %}
13683 ins_cost(125);
13684 size(6) ;
13685 ins_encode( Safepoint_Poll() );
13686 ins_pipe( ialu_reg_mem );
13687 %}
13688
13689 //----------PEEPHOLE RULES-----------------------------------------------------
13690 // These must follow all instruction definitions as they use the names
13691 // defined in the instructions definitions.
13692 //
13693 // peepmatch ( root_instr_name [preceding_instruction]* );
13694 //
13695 // peepconstraint %{
13696 // (instruction_number.operand_name relational_op instruction_number.operand_name
13697 // [, ...] );
13698 // // instruction numbers are zero-based using left to right order in peepmatch
13699 //
13700 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
13701 // // provide an instruction_number.operand_name for each operand that appears
13702 // // in the replacement instruction's match rule
13703 //
13704 // ---------VM FLAGS---------------------------------------------------------
13705 //
13706 // All peephole optimizations can be turned off using -XX:-OptoPeephole
13707 //
13708 // Each peephole rule is given an identifying number starting with zero and
13709 // increasing by one in the order seen by the parser. An individual peephole
13710 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
13711 // on the command-line.
13712 //
13713 // ---------CURRENT LIMITATIONS----------------------------------------------
13714 //
13715 // Only match adjacent instructions in same basic block
13716 // Only equality constraints
13717 // Only constraints between operands, not (0.dest_reg == EAX_enc)
13718 // Only one replacement instruction
13719 //
13720 // ---------EXAMPLE----------------------------------------------------------
13721 //
13722 // // pertinent parts of existing instructions in architecture description
13723 // instruct movI(eRegI dst, eRegI src) %{
13724 // match(Set dst (CopyI src));
13725 // %}
13726 //
13727 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
13728 // match(Set dst (AddI dst src));
13729 // effect(KILL cr);
13730 // %}
13731 //
13732 // // Change (inc mov) to lea
13733 // peephole %{
13734 // // increment preceeded by register-register move
13735 // peepmatch ( incI_eReg movI );
13736 // // require that the destination register of the increment
13737 // // match the destination register of the move
13738 // peepconstraint ( 0.dst == 1.dst );
13739 // // construct a replacement instruction that sets
13740 // // the destination to ( move's source register + one )
13741 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13742 // %}
13743 //
13744 // Implementation no longer uses movX instructions since
13745 // machine-independent system no longer uses CopyX nodes.
13746 //
13747 // peephole %{
13748 // peepmatch ( incI_eReg movI );
13749 // peepconstraint ( 0.dst == 1.dst );
13750 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13751 // %}
13752 //
13753 // peephole %{
13754 // peepmatch ( decI_eReg movI );
13755 // peepconstraint ( 0.dst == 1.dst );
13756 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13757 // %}
13758 //
13759 // peephole %{
13760 // peepmatch ( addI_eReg_imm movI );
13761 // peepconstraint ( 0.dst == 1.dst );
13762 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13763 // %}
13764 //
13765 // peephole %{
13766 // peepmatch ( addP_eReg_imm movP );
13767 // peepconstraint ( 0.dst == 1.dst );
13768 // peepreplace ( leaP_eReg_immI( 0.dst 1.src 0.src ) );
13769 // %}
13770
13771 // // Change load of spilled value to only a spill
13772 // instruct storeI(memory mem, eRegI src) %{
13773 // match(Set mem (StoreI mem src));
13774 // %}
13775 //
13776 // instruct loadI(eRegI dst, memory mem) %{
13777 // match(Set dst (LoadI mem));
13778 // %}
13779 //
13780 peephole %{
13781 peepmatch ( loadI storeI );
13782 peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
13783 peepreplace ( storeI( 1.mem 1.mem 1.src ) );
13784 %}
13785
13786 //----------SMARTSPILL RULES---------------------------------------------------
13787 // These must follow all instruction definitions as they use the names
13788 // defined in the instructions definitions.