1 // 2 // Copyright 1997-2009 Sun Microsystems, Inc. All Rights Reserved. 3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 // 5 // This code is free software; you can redistribute it and/or modify it 6 // under the terms of the GNU General Public License version 2 only, as 7 // published by the Free Software Foundation. 8 // 9 // This code is distributed in the hope that it will be useful, but WITHOUT 10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 // version 2 for more details (a copy is included in the LICENSE file that 13 // accompanied this code). 14 // 15 // You should have received a copy of the GNU General Public License version 16 // 2 along with this work; if not, write to the Free Software Foundation, 17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 // 19 // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 20 // CA 95054 USA or visit www.sun.com if you need additional information or 21 // have any questions. 22 // 23 // 24 25 // X86 Architecture Description File 26 27 //----------REGISTER DEFINITION BLOCK------------------------------------------ 28 // This information is used by the matcher and the register allocator to 29 // describe individual registers and classes of registers within the target 30 // archtecture. 31 32 register %{ 33 //----------Architecture Description Register Definitions---------------------- 34 // General Registers 35 // "reg_def" name ( register save type, C convention save type, 36 // ideal register type, encoding ); 37 // Register Save Types: 38 // 39 // NS = No-Save: The register allocator assumes that these registers 40 // can be used without saving upon entry to the method, & 41 // that they do not need to be saved at call sites. 42 // 43 // SOC = Save-On-Call: The register allocator assumes that these registers 44 // can be used without saving upon entry to the method, 45 // but that they must be saved at call sites. 46 // 47 // SOE = Save-On-Entry: The register allocator assumes that these registers 48 // must be saved before using them upon entry to the 49 // method, but they do not need to be saved at call 50 // sites. 51 // 52 // AS = Always-Save: The register allocator assumes that these registers 53 // must be saved before using them upon entry to the 54 // method, & that they must be saved at call sites. 55 // 56 // Ideal Register Type is used to determine how to save & restore a 57 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get 58 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI. 59 // 60 // The encoding number is the actual bit-pattern placed into the opcodes. 61 62 // General Registers 63 // Previously set EBX, ESI, and EDI as save-on-entry for java code 64 // Turn off SOE in java-code due to frequent use of uncommon-traps. 65 // Now that allocator is better, turn on ESI and EDI as SOE registers. 66 67 reg_def EBX(SOC, SOE, Op_RegI, 3, rbx->as_VMReg()); 68 reg_def ECX(SOC, SOC, Op_RegI, 1, rcx->as_VMReg()); 69 reg_def ESI(SOC, SOE, Op_RegI, 6, rsi->as_VMReg()); 70 reg_def EDI(SOC, SOE, Op_RegI, 7, rdi->as_VMReg()); 71 // now that adapter frames are gone EBP is always saved and restored by the prolog/epilog code 72 reg_def EBP(NS, SOE, Op_RegI, 5, rbp->as_VMReg()); 73 reg_def EDX(SOC, SOC, Op_RegI, 2, rdx->as_VMReg()); 74 reg_def EAX(SOC, SOC, Op_RegI, 0, rax->as_VMReg()); 75 reg_def ESP( NS, NS, Op_RegI, 4, rsp->as_VMReg()); 76 77 // Special Registers 78 reg_def EFLAGS(SOC, SOC, 0, 8, VMRegImpl::Bad()); 79 80 // Float registers. We treat TOS/FPR0 special. It is invisible to the 81 // allocator, and only shows up in the encodings. 82 reg_def FPR0L( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad()); 83 reg_def FPR0H( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad()); 84 // Ok so here's the trick FPR1 is really st(0) except in the midst 85 // of emission of assembly for a machnode. During the emission the fpu stack 86 // is pushed making FPR1 == st(1) temporarily. However at any safepoint 87 // the stack will not have this element so FPR1 == st(0) from the 88 // oopMap viewpoint. This same weirdness with numbering causes 89 // instruction encoding to have to play games with the register 90 // encode to correct for this 0/1 issue. See MachSpillCopyNode::implementation 91 // where it does flt->flt moves to see an example 92 // 93 reg_def FPR1L( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg()); 94 reg_def FPR1H( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg()->next()); 95 reg_def FPR2L( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg()); 96 reg_def FPR2H( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg()->next()); 97 reg_def FPR3L( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg()); 98 reg_def FPR3H( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg()->next()); 99 reg_def FPR4L( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg()); 100 reg_def FPR4H( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg()->next()); 101 reg_def FPR5L( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg()); 102 reg_def FPR5H( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg()->next()); 103 reg_def FPR6L( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg()); 104 reg_def FPR6H( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg()->next()); 105 reg_def FPR7L( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg()); 106 reg_def FPR7H( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg()->next()); 107 108 // XMM registers. 128-bit registers or 4 words each, labeled a-d. 109 // Word a in each register holds a Float, words ab hold a Double. 110 // We currently do not use the SIMD capabilities, so registers cd 111 // are unused at the moment. 112 reg_def XMM0a( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()); 113 reg_def XMM0b( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()->next()); 114 reg_def XMM1a( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()); 115 reg_def XMM1b( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()->next()); 116 reg_def XMM2a( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()); 117 reg_def XMM2b( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()->next()); 118 reg_def XMM3a( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()); 119 reg_def XMM3b( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()->next()); 120 reg_def XMM4a( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()); 121 reg_def XMM4b( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()->next()); 122 reg_def XMM5a( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()); 123 reg_def XMM5b( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()->next()); 124 reg_def XMM6a( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()); 125 reg_def XMM6b( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()->next()); 126 reg_def XMM7a( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()); 127 reg_def XMM7b( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()->next()); 128 129 // Specify priority of register selection within phases of register 130 // allocation. Highest priority is first. A useful heuristic is to 131 // give registers a low priority when they are required by machine 132 // instructions, like EAX and EDX. Registers which are used as 133 // pairs must fall on an even boundary (witness the FPR#L's in this list). 134 // For the Intel integer registers, the equivalent Long pairs are 135 // EDX:EAX, EBX:ECX, and EDI:EBP. 136 alloc_class chunk0( ECX, EBX, EBP, EDI, EAX, EDX, ESI, ESP, 137 FPR0L, FPR0H, FPR1L, FPR1H, FPR2L, FPR2H, 138 FPR3L, FPR3H, FPR4L, FPR4H, FPR5L, FPR5H, 139 FPR6L, FPR6H, FPR7L, FPR7H ); 140 141 alloc_class chunk1( XMM0a, XMM0b, 142 XMM1a, XMM1b, 143 XMM2a, XMM2b, 144 XMM3a, XMM3b, 145 XMM4a, XMM4b, 146 XMM5a, XMM5b, 147 XMM6a, XMM6b, 148 XMM7a, XMM7b, EFLAGS); 149 150 151 //----------Architecture Description Register Classes-------------------------- 152 // Several register classes are automatically defined based upon information in 153 // this architecture description. 154 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ ) 155 // 2) reg_class compiler_method_oop_reg ( /* as def'd in frame section */ ) 156 // 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ ) 157 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ ) 158 // 159 // Class for all registers 160 reg_class any_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX, ESP); 161 // Class for general registers 162 reg_class e_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX); 163 // Class for general registers which may be used for implicit null checks on win95 164 // Also safe for use by tailjump. We don't want to allocate in rbp, 165 reg_class e_reg_no_rbp(EAX, EDX, EDI, ESI, ECX, EBX); 166 // Class of "X" registers 167 reg_class x_reg(EBX, ECX, EDX, EAX); 168 // Class of registers that can appear in an address with no offset. 169 // EBP and ESP require an extra instruction byte for zero offset. 170 // Used in fast-unlock 171 reg_class p_reg(EDX, EDI, ESI, EBX); 172 // Class for general registers not including ECX 173 reg_class ncx_reg(EAX, EDX, EBP, EDI, ESI, EBX); 174 // Class for general registers not including EAX 175 reg_class nax_reg(EDX, EDI, ESI, ECX, EBX); 176 // Class for general registers not including EAX or EBX. 177 reg_class nabx_reg(EDX, EDI, ESI, ECX, EBP); 178 // Class of EAX (for multiply and divide operations) 179 reg_class eax_reg(EAX); 180 // Class of EBX (for atomic add) 181 reg_class ebx_reg(EBX); 182 // Class of ECX (for shift and JCXZ operations and cmpLTMask) 183 reg_class ecx_reg(ECX); 184 // Class of EDX (for multiply and divide operations) 185 reg_class edx_reg(EDX); 186 // Class of EDI (for synchronization) 187 reg_class edi_reg(EDI); 188 // Class of ESI (for synchronization) 189 reg_class esi_reg(ESI); 190 // Singleton class for interpreter's stack pointer 191 reg_class ebp_reg(EBP); 192 // Singleton class for stack pointer 193 reg_class sp_reg(ESP); 194 // Singleton class for instruction pointer 195 // reg_class ip_reg(EIP); 196 // Singleton class for condition codes 197 reg_class int_flags(EFLAGS); 198 // Class of integer register pairs 199 reg_class long_reg( EAX,EDX, ECX,EBX, EBP,EDI ); 200 // Class of integer register pairs that aligns with calling convention 201 reg_class eadx_reg( EAX,EDX ); 202 reg_class ebcx_reg( ECX,EBX ); 203 // Not AX or DX, used in divides 204 reg_class nadx_reg( EBX,ECX,ESI,EDI,EBP ); 205 206 // Floating point registers. Notice FPR0 is not a choice. 207 // FPR0 is not ever allocated; we use clever encodings to fake 208 // a 2-address instructions out of Intels FP stack. 209 reg_class flt_reg( FPR1L,FPR2L,FPR3L,FPR4L,FPR5L,FPR6L,FPR7L ); 210 211 // make a register class for SSE registers 212 reg_class xmm_reg(XMM0a, XMM1a, XMM2a, XMM3a, XMM4a, XMM5a, XMM6a, XMM7a); 213 214 // make a double register class for SSE2 registers 215 reg_class xdb_reg(XMM0a,XMM0b, XMM1a,XMM1b, XMM2a,XMM2b, XMM3a,XMM3b, 216 XMM4a,XMM4b, XMM5a,XMM5b, XMM6a,XMM6b, XMM7a,XMM7b ); 217 218 reg_class dbl_reg( FPR1L,FPR1H, FPR2L,FPR2H, FPR3L,FPR3H, 219 FPR4L,FPR4H, FPR5L,FPR5H, FPR6L,FPR6H, 220 FPR7L,FPR7H ); 221 222 reg_class flt_reg0( FPR1L ); 223 reg_class dbl_reg0( FPR1L,FPR1H ); 224 reg_class dbl_reg1( FPR2L,FPR2H ); 225 reg_class dbl_notreg0( FPR2L,FPR2H, FPR3L,FPR3H, FPR4L,FPR4H, 226 FPR5L,FPR5H, FPR6L,FPR6H, FPR7L,FPR7H ); 227 228 // XMM6 and XMM7 could be used as temporary registers for long, float and 229 // double values for SSE2. 230 reg_class xdb_reg6( XMM6a,XMM6b ); 231 reg_class xdb_reg7( XMM7a,XMM7b ); 232 %} 233 234 235 //----------SOURCE BLOCK------------------------------------------------------- 236 // This is a block of C++ code which provides values, functions, and 237 // definitions necessary in the rest of the architecture description 238 source %{ 239 #define RELOC_IMM32 Assembler::imm_operand 240 #define RELOC_DISP32 Assembler::disp32_operand 241 242 #define __ _masm. 243 244 // How to find the high register of a Long pair, given the low register 245 #define HIGH_FROM_LOW(x) ((x)+2) 246 247 // These masks are used to provide 128-bit aligned bitmasks to the XMM 248 // instructions, to allow sign-masking or sign-bit flipping. They allow 249 // fast versions of NegF/NegD and AbsF/AbsD. 250 251 // Note: 'double' and 'long long' have 32-bits alignment on x86. 252 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) { 253 // Use the expression (adr)&(~0xF) to provide 128-bits aligned address 254 // of 128-bits operands for SSE instructions. 255 jlong *operand = (jlong*)(((uintptr_t)adr)&((uintptr_t)(~0xF))); 256 // Store the value to a 128-bits operand. 257 operand[0] = lo; 258 operand[1] = hi; 259 return operand; 260 } 261 262 // Buffer for 128-bits masks used by SSE instructions. 263 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment) 264 265 // Static initialization during VM startup. 266 static jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF)); 267 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF)); 268 static jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], CONST64(0x8000000080000000), CONST64(0x8000000080000000)); 269 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], CONST64(0x8000000000000000), CONST64(0x8000000000000000)); 270 271 // !!!!! Special hack to get all type of calls to specify the byte offset 272 // from the start of the call to the point where the return address 273 // will point. 274 int MachCallStaticJavaNode::ret_addr_offset() { 275 return 5 + (Compile::current()->in_24_bit_fp_mode() ? 6 : 0); // 5 bytes from start of call to where return address points 276 } 277 278 int MachCallDynamicJavaNode::ret_addr_offset() { 279 return 10 + (Compile::current()->in_24_bit_fp_mode() ? 6 : 0); // 10 bytes from start of call to where return address points 280 } 281 282 static int sizeof_FFree_Float_Stack_All = -1; 283 284 int MachCallRuntimeNode::ret_addr_offset() { 285 assert(sizeof_FFree_Float_Stack_All != -1, "must have been emitted already"); 286 return sizeof_FFree_Float_Stack_All + 5 + (Compile::current()->in_24_bit_fp_mode() ? 6 : 0); 287 } 288 289 // Indicate if the safepoint node needs the polling page as an input. 290 // Since x86 does have absolute addressing, it doesn't. 291 bool SafePointNode::needs_polling_address_input() { 292 return false; 293 } 294 295 // 296 // Compute padding required for nodes which need alignment 297 // 298 299 // The address of the call instruction needs to be 4-byte aligned to 300 // ensure that it does not span a cache line so that it can be patched. 301 int CallStaticJavaDirectNode::compute_padding(int current_offset) const { 302 if (Compile::current()->in_24_bit_fp_mode()) 303 current_offset += 6; // skip fldcw in pre_call_FPU, if any 304 current_offset += 1; // skip call opcode byte 305 return round_to(current_offset, alignment_required()) - current_offset; 306 } 307 308 // The address of the call instruction needs to be 4-byte aligned to 309 // ensure that it does not span a cache line so that it can be patched. 310 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const { 311 if (Compile::current()->in_24_bit_fp_mode()) 312 current_offset += 6; // skip fldcw in pre_call_FPU, if any 313 current_offset += 5; // skip MOV instruction 314 current_offset += 1; // skip call opcode byte 315 return round_to(current_offset, alignment_required()) - current_offset; 316 } 317 318 #ifndef PRODUCT 319 void MachBreakpointNode::format( PhaseRegAlloc *, outputStream* st ) const { 320 st->print("INT3"); 321 } 322 #endif 323 324 // EMIT_RM() 325 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) { 326 unsigned char c = (unsigned char)((f1 << 6) | (f2 << 3) | f3); 327 *(cbuf.code_end()) = c; 328 cbuf.set_code_end(cbuf.code_end() + 1); 329 } 330 331 // EMIT_CC() 332 void emit_cc(CodeBuffer &cbuf, int f1, int f2) { 333 unsigned char c = (unsigned char)( f1 | f2 ); 334 *(cbuf.code_end()) = c; 335 cbuf.set_code_end(cbuf.code_end() + 1); 336 } 337 338 // EMIT_OPCODE() 339 void emit_opcode(CodeBuffer &cbuf, int code) { 340 *(cbuf.code_end()) = (unsigned char)code; 341 cbuf.set_code_end(cbuf.code_end() + 1); 342 } 343 344 // EMIT_OPCODE() w/ relocation information 345 void emit_opcode(CodeBuffer &cbuf, int code, relocInfo::relocType reloc, int offset = 0) { 346 cbuf.relocate(cbuf.inst_mark() + offset, reloc); 347 emit_opcode(cbuf, code); 348 } 349 350 // EMIT_D8() 351 void emit_d8(CodeBuffer &cbuf, int d8) { 352 *(cbuf.code_end()) = (unsigned char)d8; 353 cbuf.set_code_end(cbuf.code_end() + 1); 354 } 355 356 // EMIT_D16() 357 void emit_d16(CodeBuffer &cbuf, int d16) { 358 *((short *)(cbuf.code_end())) = d16; 359 cbuf.set_code_end(cbuf.code_end() + 2); 360 } 361 362 // EMIT_D32() 363 void emit_d32(CodeBuffer &cbuf, int d32) { 364 *((int *)(cbuf.code_end())) = d32; 365 cbuf.set_code_end(cbuf.code_end() + 4); 366 } 367 368 // emit 32 bit value and construct relocation entry from relocInfo::relocType 369 void emit_d32_reloc(CodeBuffer &cbuf, int d32, relocInfo::relocType reloc, 370 int format) { 371 cbuf.relocate(cbuf.inst_mark(), reloc, format); 372 373 *((int *)(cbuf.code_end())) = d32; 374 cbuf.set_code_end(cbuf.code_end() + 4); 375 } 376 377 // emit 32 bit value and construct relocation entry from RelocationHolder 378 void emit_d32_reloc(CodeBuffer &cbuf, int d32, RelocationHolder const& rspec, 379 int format) { 380 #ifdef ASSERT 381 if (rspec.reloc()->type() == relocInfo::oop_type && d32 != 0 && d32 != (int)Universe::non_oop_word()) { 382 assert(oop(d32)->is_oop() && oop(d32)->is_perm(), "cannot embed non-perm oops in code"); 383 } 384 #endif 385 cbuf.relocate(cbuf.inst_mark(), rspec, format); 386 387 *((int *)(cbuf.code_end())) = d32; 388 cbuf.set_code_end(cbuf.code_end() + 4); 389 } 390 391 // Access stack slot for load or store 392 void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp) { 393 emit_opcode( cbuf, opcode ); // (e.g., FILD [ESP+src]) 394 if( -128 <= disp && disp <= 127 ) { 395 emit_rm( cbuf, 0x01, rm_field, ESP_enc ); // R/M byte 396 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte 397 emit_d8 (cbuf, disp); // Displacement // R/M byte 398 } else { 399 emit_rm( cbuf, 0x02, rm_field, ESP_enc ); // R/M byte 400 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte 401 emit_d32(cbuf, disp); // Displacement // R/M byte 402 } 403 } 404 405 // eRegI ereg, memory mem) %{ // emit_reg_mem 406 void encode_RegMem( CodeBuffer &cbuf, int reg_encoding, int base, int index, int scale, int displace, bool displace_is_oop ) { 407 // There is no index & no scale, use form without SIB byte 408 if ((index == 0x4) && 409 (scale == 0) && (base != ESP_enc)) { 410 // If no displacement, mode is 0x0; unless base is [EBP] 411 if ( (displace == 0) && (base != EBP_enc) ) { 412 emit_rm(cbuf, 0x0, reg_encoding, base); 413 } 414 else { // If 8-bit displacement, mode 0x1 415 if ((displace >= -128) && (displace <= 127) 416 && !(displace_is_oop) ) { 417 emit_rm(cbuf, 0x1, reg_encoding, base); 418 emit_d8(cbuf, displace); 419 } 420 else { // If 32-bit displacement 421 if (base == -1) { // Special flag for absolute address 422 emit_rm(cbuf, 0x0, reg_encoding, 0x5); 423 // (manual lies; no SIB needed here) 424 if ( displace_is_oop ) { 425 emit_d32_reloc(cbuf, displace, relocInfo::oop_type, 1); 426 } else { 427 emit_d32 (cbuf, displace); 428 } 429 } 430 else { // Normal base + offset 431 emit_rm(cbuf, 0x2, reg_encoding, base); 432 if ( displace_is_oop ) { 433 emit_d32_reloc(cbuf, displace, relocInfo::oop_type, 1); 434 } else { 435 emit_d32 (cbuf, displace); 436 } 437 } 438 } 439 } 440 } 441 else { // Else, encode with the SIB byte 442 // If no displacement, mode is 0x0; unless base is [EBP] 443 if (displace == 0 && (base != EBP_enc)) { // If no displacement 444 emit_rm(cbuf, 0x0, reg_encoding, 0x4); 445 emit_rm(cbuf, scale, index, base); 446 } 447 else { // If 8-bit displacement, mode 0x1 448 if ((displace >= -128) && (displace <= 127) 449 && !(displace_is_oop) ) { 450 emit_rm(cbuf, 0x1, reg_encoding, 0x4); 451 emit_rm(cbuf, scale, index, base); 452 emit_d8(cbuf, displace); 453 } 454 else { // If 32-bit displacement 455 if (base == 0x04 ) { 456 emit_rm(cbuf, 0x2, reg_encoding, 0x4); 457 emit_rm(cbuf, scale, index, 0x04); 458 } else { 459 emit_rm(cbuf, 0x2, reg_encoding, 0x4); 460 emit_rm(cbuf, scale, index, base); 461 } 462 if ( displace_is_oop ) { 463 emit_d32_reloc(cbuf, displace, relocInfo::oop_type, 1); 464 } else { 465 emit_d32 (cbuf, displace); 466 } 467 } 468 } 469 } 470 } 471 472 473 void encode_Copy( CodeBuffer &cbuf, int dst_encoding, int src_encoding ) { 474 if( dst_encoding == src_encoding ) { 475 // reg-reg copy, use an empty encoding 476 } else { 477 emit_opcode( cbuf, 0x8B ); 478 emit_rm(cbuf, 0x3, dst_encoding, src_encoding ); 479 } 480 } 481 482 void encode_CopyXD( CodeBuffer &cbuf, int dst_encoding, int src_encoding ) { 483 if( dst_encoding == src_encoding ) { 484 // reg-reg copy, use an empty encoding 485 } else { 486 MacroAssembler _masm(&cbuf); 487 488 __ movdqa(as_XMMRegister(dst_encoding), as_XMMRegister(src_encoding)); 489 } 490 } 491 492 493 //============================================================================= 494 #ifndef PRODUCT 495 void MachPrologNode::format( PhaseRegAlloc *ra_, outputStream* st ) const { 496 Compile* C = ra_->C; 497 if( C->in_24_bit_fp_mode() ) { 498 st->print("FLDCW 24 bit fpu control word"); 499 st->print_cr(""); st->print("\t"); 500 } 501 502 int framesize = C->frame_slots() << LogBytesPerInt; 503 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); 504 // Remove two words for return addr and rbp, 505 framesize -= 2*wordSize; 506 507 // Calls to C2R adapters often do not accept exceptional returns. 508 // We require that their callers must bang for them. But be careful, because 509 // some VM calls (such as call site linkage) can use several kilobytes of 510 // stack. But the stack safety zone should account for that. 511 // See bugs 4446381, 4468289, 4497237. 512 if (C->need_stack_bang(framesize)) { 513 st->print_cr("# stack bang"); st->print("\t"); 514 } 515 st->print_cr("PUSHL EBP"); st->print("\t"); 516 517 if( VerifyStackAtCalls ) { // Majik cookie to verify stack depth 518 st->print("PUSH 0xBADB100D\t# Majik cookie for stack depth check"); 519 st->print_cr(""); st->print("\t"); 520 framesize -= wordSize; 521 } 522 523 if ((C->in_24_bit_fp_mode() || VerifyStackAtCalls ) && framesize < 128 ) { 524 if (framesize) { 525 st->print("SUB ESP,%d\t# Create frame",framesize); 526 } 527 } else { 528 st->print("SUB ESP,%d\t# Create frame",framesize); 529 } 530 } 531 #endif 532 533 534 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 535 Compile* C = ra_->C; 536 537 if (UseSSE >= 2 && VerifyFPU) { 538 MacroAssembler masm(&cbuf); 539 masm.verify_FPU(0, "FPU stack must be clean on entry"); 540 } 541 542 // WARNING: Initial instruction MUST be 5 bytes or longer so that 543 // NativeJump::patch_verified_entry will be able to patch out the entry 544 // code safely. The fldcw is ok at 6 bytes, the push to verify stack 545 // depth is ok at 5 bytes, the frame allocation can be either 3 or 546 // 6 bytes. So if we don't do the fldcw or the push then we must 547 // use the 6 byte frame allocation even if we have no frame. :-( 548 // If method sets FPU control word do it now 549 if( C->in_24_bit_fp_mode() ) { 550 MacroAssembler masm(&cbuf); 551 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24())); 552 } 553 554 int framesize = C->frame_slots() << LogBytesPerInt; 555 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); 556 // Remove two words for return addr and rbp, 557 framesize -= 2*wordSize; 558 559 // Calls to C2R adapters often do not accept exceptional returns. 560 // We require that their callers must bang for them. But be careful, because 561 // some VM calls (such as call site linkage) can use several kilobytes of 562 // stack. But the stack safety zone should account for that. 563 // See bugs 4446381, 4468289, 4497237. 564 if (C->need_stack_bang(framesize)) { 565 MacroAssembler masm(&cbuf); 566 masm.generate_stack_overflow_check(framesize); 567 } 568 569 // We always push rbp, so that on return to interpreter rbp, will be 570 // restored correctly and we can correct the stack. 571 emit_opcode(cbuf, 0x50 | EBP_enc); 572 573 if( VerifyStackAtCalls ) { // Majik cookie to verify stack depth 574 emit_opcode(cbuf, 0x68); // push 0xbadb100d 575 emit_d32(cbuf, 0xbadb100d); 576 framesize -= wordSize; 577 } 578 579 if ((C->in_24_bit_fp_mode() || VerifyStackAtCalls ) && framesize < 128 ) { 580 if (framesize) { 581 emit_opcode(cbuf, 0x83); // sub SP,#framesize 582 emit_rm(cbuf, 0x3, 0x05, ESP_enc); 583 emit_d8(cbuf, framesize); 584 } 585 } else { 586 emit_opcode(cbuf, 0x81); // sub SP,#framesize 587 emit_rm(cbuf, 0x3, 0x05, ESP_enc); 588 emit_d32(cbuf, framesize); 589 } 590 C->set_frame_complete(cbuf.code_end() - cbuf.code_begin()); 591 592 #ifdef ASSERT 593 if (VerifyStackAtCalls) { 594 Label L; 595 MacroAssembler masm(&cbuf); 596 masm.push(rax); 597 masm.mov(rax, rsp); 598 masm.andptr(rax, StackAlignmentInBytes-1); 599 masm.cmpptr(rax, StackAlignmentInBytes-wordSize); 600 masm.pop(rax); 601 masm.jcc(Assembler::equal, L); 602 masm.stop("Stack is not properly aligned!"); 603 masm.bind(L); 604 } 605 #endif 606 607 } 608 609 uint MachPrologNode::size(PhaseRegAlloc *ra_) const { 610 return MachNode::size(ra_); // too many variables; just compute it the hard way 611 } 612 613 int MachPrologNode::reloc() const { 614 return 0; // a large enough number 615 } 616 617 //============================================================================= 618 #ifndef PRODUCT 619 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream* st ) const { 620 Compile *C = ra_->C; 621 int framesize = C->frame_slots() << LogBytesPerInt; 622 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); 623 // Remove two words for return addr and rbp, 624 framesize -= 2*wordSize; 625 626 if( C->in_24_bit_fp_mode() ) { 627 st->print("FLDCW standard control word"); 628 st->cr(); st->print("\t"); 629 } 630 if( framesize ) { 631 st->print("ADD ESP,%d\t# Destroy frame",framesize); 632 st->cr(); st->print("\t"); 633 } 634 st->print_cr("POPL EBP"); st->print("\t"); 635 if( do_polling() && C->is_method_compilation() ) { 636 st->print("TEST PollPage,EAX\t! Poll Safepoint"); 637 st->cr(); st->print("\t"); 638 } 639 } 640 #endif 641 642 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 643 Compile *C = ra_->C; 644 645 // If method set FPU control word, restore to standard control word 646 if( C->in_24_bit_fp_mode() ) { 647 MacroAssembler masm(&cbuf); 648 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std())); 649 } 650 651 int framesize = C->frame_slots() << LogBytesPerInt; 652 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); 653 // Remove two words for return addr and rbp, 654 framesize -= 2*wordSize; 655 656 // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here 657 658 if( framesize >= 128 ) { 659 emit_opcode(cbuf, 0x81); // add SP, #framesize 660 emit_rm(cbuf, 0x3, 0x00, ESP_enc); 661 emit_d32(cbuf, framesize); 662 } 663 else if( framesize ) { 664 emit_opcode(cbuf, 0x83); // add SP, #framesize 665 emit_rm(cbuf, 0x3, 0x00, ESP_enc); 666 emit_d8(cbuf, framesize); 667 } 668 669 emit_opcode(cbuf, 0x58 | EBP_enc); 670 671 if( do_polling() && C->is_method_compilation() ) { 672 cbuf.relocate(cbuf.code_end(), relocInfo::poll_return_type, 0); 673 emit_opcode(cbuf,0x85); 674 emit_rm(cbuf, 0x0, EAX_enc, 0x5); // EAX 675 emit_d32(cbuf, (intptr_t)os::get_polling_page()); 676 } 677 } 678 679 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const { 680 Compile *C = ra_->C; 681 // If method set FPU control word, restore to standard control word 682 int size = C->in_24_bit_fp_mode() ? 6 : 0; 683 if( do_polling() && C->is_method_compilation() ) size += 6; 684 685 int framesize = C->frame_slots() << LogBytesPerInt; 686 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); 687 // Remove two words for return addr and rbp, 688 framesize -= 2*wordSize; 689 690 size++; // popl rbp, 691 692 if( framesize >= 128 ) { 693 size += 6; 694 } else { 695 size += framesize ? 3 : 0; 696 } 697 return size; 698 } 699 700 int MachEpilogNode::reloc() const { 701 return 0; // a large enough number 702 } 703 704 const Pipeline * MachEpilogNode::pipeline() const { 705 return MachNode::pipeline_class(); 706 } 707 708 int MachEpilogNode::safepoint_offset() const { return 0; } 709 710 //============================================================================= 711 712 enum RC { rc_bad, rc_int, rc_float, rc_xmm, rc_stack }; 713 static enum RC rc_class( OptoReg::Name reg ) { 714 715 if( !OptoReg::is_valid(reg) ) return rc_bad; 716 if (OptoReg::is_stack(reg)) return rc_stack; 717 718 VMReg r = OptoReg::as_VMReg(reg); 719 if (r->is_Register()) return rc_int; 720 if (r->is_FloatRegister()) { 721 assert(UseSSE < 2, "shouldn't be used in SSE2+ mode"); 722 return rc_float; 723 } 724 assert(r->is_XMMRegister(), "must be"); 725 return rc_xmm; 726 } 727 728 static int impl_helper( CodeBuffer *cbuf, bool do_size, bool is_load, int offset, int reg, 729 int opcode, const char *op_str, int size, outputStream* st ) { 730 if( cbuf ) { 731 emit_opcode (*cbuf, opcode ); 732 encode_RegMem(*cbuf, Matcher::_regEncode[reg], ESP_enc, 0x4, 0, offset, false); 733 #ifndef PRODUCT 734 } else if( !do_size ) { 735 if( size != 0 ) st->print("\n\t"); 736 if( opcode == 0x8B || opcode == 0x89 ) { // MOV 737 if( is_load ) st->print("%s %s,[ESP + #%d]",op_str,Matcher::regName[reg],offset); 738 else st->print("%s [ESP + #%d],%s",op_str,offset,Matcher::regName[reg]); 739 } else { // FLD, FST, PUSH, POP 740 st->print("%s [ESP + #%d]",op_str,offset); 741 } 742 #endif 743 } 744 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4); 745 return size+3+offset_size; 746 } 747 748 // Helper for XMM registers. Extra opcode bits, limited syntax. 749 static int impl_x_helper( CodeBuffer *cbuf, bool do_size, bool is_load, 750 int offset, int reg_lo, int reg_hi, int size, outputStream* st ) { 751 if( cbuf ) { 752 if( reg_lo+1 == reg_hi ) { // double move? 753 if( is_load && !UseXmmLoadAndClearUpper ) 754 emit_opcode(*cbuf, 0x66 ); // use 'movlpd' for load 755 else 756 emit_opcode(*cbuf, 0xF2 ); // use 'movsd' otherwise 757 } else { 758 emit_opcode(*cbuf, 0xF3 ); 759 } 760 emit_opcode(*cbuf, 0x0F ); 761 if( reg_lo+1 == reg_hi && is_load && !UseXmmLoadAndClearUpper ) 762 emit_opcode(*cbuf, 0x12 ); // use 'movlpd' for load 763 else 764 emit_opcode(*cbuf, is_load ? 0x10 : 0x11 ); 765 encode_RegMem(*cbuf, Matcher::_regEncode[reg_lo], ESP_enc, 0x4, 0, offset, false); 766 #ifndef PRODUCT 767 } else if( !do_size ) { 768 if( size != 0 ) st->print("\n\t"); 769 if( reg_lo+1 == reg_hi ) { // double move? 770 if( is_load ) st->print("%s %s,[ESP + #%d]", 771 UseXmmLoadAndClearUpper ? "MOVSD " : "MOVLPD", 772 Matcher::regName[reg_lo], offset); 773 else st->print("MOVSD [ESP + #%d],%s", 774 offset, Matcher::regName[reg_lo]); 775 } else { 776 if( is_load ) st->print("MOVSS %s,[ESP + #%d]", 777 Matcher::regName[reg_lo], offset); 778 else st->print("MOVSS [ESP + #%d],%s", 779 offset, Matcher::regName[reg_lo]); 780 } 781 #endif 782 } 783 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4); 784 return size+5+offset_size; 785 } 786 787 788 static int impl_movx_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo, 789 int src_hi, int dst_hi, int size, outputStream* st ) { 790 if( UseXmmRegToRegMoveAll ) {//Use movaps,movapd to move between xmm registers 791 if( cbuf ) { 792 if( (src_lo+1 == src_hi && dst_lo+1 == dst_hi) ) { 793 emit_opcode(*cbuf, 0x66 ); 794 } 795 emit_opcode(*cbuf, 0x0F ); 796 emit_opcode(*cbuf, 0x28 ); 797 emit_rm (*cbuf, 0x3, Matcher::_regEncode[dst_lo], Matcher::_regEncode[src_lo] ); 798 #ifndef PRODUCT 799 } else if( !do_size ) { 800 if( size != 0 ) st->print("\n\t"); 801 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double move? 802 st->print("MOVAPD %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]); 803 } else { 804 st->print("MOVAPS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]); 805 } 806 #endif 807 } 808 return size + ((src_lo+1 == src_hi && dst_lo+1 == dst_hi) ? 4 : 3); 809 } else { 810 if( cbuf ) { 811 emit_opcode(*cbuf, (src_lo+1 == src_hi && dst_lo+1 == dst_hi) ? 0xF2 : 0xF3 ); 812 emit_opcode(*cbuf, 0x0F ); 813 emit_opcode(*cbuf, 0x10 ); 814 emit_rm (*cbuf, 0x3, Matcher::_regEncode[dst_lo], Matcher::_regEncode[src_lo] ); 815 #ifndef PRODUCT 816 } else if( !do_size ) { 817 if( size != 0 ) st->print("\n\t"); 818 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double move? 819 st->print("MOVSD %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]); 820 } else { 821 st->print("MOVSS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]); 822 } 823 #endif 824 } 825 return size+4; 826 } 827 } 828 829 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int size, outputStream* st ) { 830 if( cbuf ) { 831 emit_opcode(*cbuf, 0x8B ); 832 emit_rm (*cbuf, 0x3, Matcher::_regEncode[dst], Matcher::_regEncode[src] ); 833 #ifndef PRODUCT 834 } else if( !do_size ) { 835 if( size != 0 ) st->print("\n\t"); 836 st->print("MOV %s,%s",Matcher::regName[dst],Matcher::regName[src]); 837 #endif 838 } 839 return size+2; 840 } 841 842 static int impl_fp_store_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int src_hi, int dst_lo, int dst_hi, 843 int offset, int size, outputStream* st ) { 844 if( src_lo != FPR1L_num ) { // Move value to top of FP stack, if not already there 845 if( cbuf ) { 846 emit_opcode( *cbuf, 0xD9 ); // FLD (i.e., push it) 847 emit_d8( *cbuf, 0xC0-1+Matcher::_regEncode[src_lo] ); 848 #ifndef PRODUCT 849 } else if( !do_size ) { 850 if( size != 0 ) st->print("\n\t"); 851 st->print("FLD %s",Matcher::regName[src_lo]); 852 #endif 853 } 854 size += 2; 855 } 856 857 int st_op = (src_lo != FPR1L_num) ? EBX_num /*store & pop*/ : EDX_num /*store no pop*/; 858 const char *op_str; 859 int op; 860 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double store? 861 op_str = (src_lo != FPR1L_num) ? "FSTP_D" : "FST_D "; 862 op = 0xDD; 863 } else { // 32-bit store 864 op_str = (src_lo != FPR1L_num) ? "FSTP_S" : "FST_S "; 865 op = 0xD9; 866 assert( !OptoReg::is_valid(src_hi) && !OptoReg::is_valid(dst_hi), "no non-adjacent float-stores" ); 867 } 868 869 return impl_helper(cbuf,do_size,false,offset,st_op,op,op_str,size, st); 870 } 871 872 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream* st ) const { 873 // Get registers to move 874 OptoReg::Name src_second = ra_->get_reg_second(in(1)); 875 OptoReg::Name src_first = ra_->get_reg_first(in(1)); 876 OptoReg::Name dst_second = ra_->get_reg_second(this ); 877 OptoReg::Name dst_first = ra_->get_reg_first(this ); 878 879 enum RC src_second_rc = rc_class(src_second); 880 enum RC src_first_rc = rc_class(src_first); 881 enum RC dst_second_rc = rc_class(dst_second); 882 enum RC dst_first_rc = rc_class(dst_first); 883 884 assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" ); 885 886 // Generate spill code! 887 int size = 0; 888 889 if( src_first == dst_first && src_second == dst_second ) 890 return size; // Self copy, no move 891 892 // -------------------------------------- 893 // Check for mem-mem move. push/pop to move. 894 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) { 895 if( src_second == dst_first ) { // overlapping stack copy ranges 896 assert( src_second_rc == rc_stack && dst_second_rc == rc_stack, "we only expect a stk-stk copy here" ); 897 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH ",size, st); 898 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP ",size, st); 899 src_second_rc = dst_second_rc = rc_bad; // flag as already moved the second bits 900 } 901 // move low bits 902 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),ESI_num,0xFF,"PUSH ",size, st); 903 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),EAX_num,0x8F,"POP ",size, st); 904 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) { // mov second bits 905 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH ",size, st); 906 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP ",size, st); 907 } 908 return size; 909 } 910 911 // -------------------------------------- 912 // Check for integer reg-reg copy 913 if( src_first_rc == rc_int && dst_first_rc == rc_int ) 914 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,size, st); 915 916 // Check for integer store 917 if( src_first_rc == rc_int && dst_first_rc == rc_stack ) 918 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first,0x89,"MOV ",size, st); 919 920 // Check for integer load 921 if( dst_first_rc == rc_int && src_first_rc == rc_stack ) 922 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first,0x8B,"MOV ",size, st); 923 924 // -------------------------------------- 925 // Check for float reg-reg copy 926 if( src_first_rc == rc_float && dst_first_rc == rc_float ) { 927 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) || 928 (src_first+1 == src_second && dst_first+1 == dst_second), "no non-adjacent float-moves" ); 929 if( cbuf ) { 930 931 // Note the mucking with the register encode to compensate for the 0/1 932 // indexing issue mentioned in a comment in the reg_def sections 933 // for FPR registers many lines above here. 934 935 if( src_first != FPR1L_num ) { 936 emit_opcode (*cbuf, 0xD9 ); // FLD ST(i) 937 emit_d8 (*cbuf, 0xC0+Matcher::_regEncode[src_first]-1 ); 938 emit_opcode (*cbuf, 0xDD ); // FSTP ST(i) 939 emit_d8 (*cbuf, 0xD8+Matcher::_regEncode[dst_first] ); 940 } else { 941 emit_opcode (*cbuf, 0xDD ); // FST ST(i) 942 emit_d8 (*cbuf, 0xD0+Matcher::_regEncode[dst_first]-1 ); 943 } 944 #ifndef PRODUCT 945 } else if( !do_size ) { 946 if( size != 0 ) st->print("\n\t"); 947 if( src_first != FPR1L_num ) st->print("FLD %s\n\tFSTP %s",Matcher::regName[src_first],Matcher::regName[dst_first]); 948 else st->print( "FST %s", Matcher::regName[dst_first]); 949 #endif 950 } 951 return size + ((src_first != FPR1L_num) ? 2+2 : 2); 952 } 953 954 // Check for float store 955 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) { 956 return impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,ra_->reg2offset(dst_first),size, st); 957 } 958 959 // Check for float load 960 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) { 961 int offset = ra_->reg2offset(src_first); 962 const char *op_str; 963 int op; 964 if( src_first+1 == src_second && dst_first+1 == dst_second ) { // double load? 965 op_str = "FLD_D"; 966 op = 0xDD; 967 } else { // 32-bit load 968 op_str = "FLD_S"; 969 op = 0xD9; 970 assert( src_second_rc == rc_bad && dst_second_rc == rc_bad, "no non-adjacent float-loads" ); 971 } 972 if( cbuf ) { 973 emit_opcode (*cbuf, op ); 974 encode_RegMem(*cbuf, 0x0, ESP_enc, 0x4, 0, offset, false); 975 emit_opcode (*cbuf, 0xDD ); // FSTP ST(i) 976 emit_d8 (*cbuf, 0xD8+Matcher::_regEncode[dst_first] ); 977 #ifndef PRODUCT 978 } else if( !do_size ) { 979 if( size != 0 ) st->print("\n\t"); 980 st->print("%s ST,[ESP + #%d]\n\tFSTP %s",op_str, offset,Matcher::regName[dst_first]); 981 #endif 982 } 983 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4); 984 return size + 3+offset_size+2; 985 } 986 987 // Check for xmm reg-reg copy 988 if( src_first_rc == rc_xmm && dst_first_rc == rc_xmm ) { 989 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) || 990 (src_first+1 == src_second && dst_first+1 == dst_second), 991 "no non-adjacent float-moves" ); 992 return impl_movx_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st); 993 } 994 995 // Check for xmm store 996 if( src_first_rc == rc_xmm && dst_first_rc == rc_stack ) { 997 return impl_x_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first, src_second, size, st); 998 } 999 1000 // Check for float xmm load 1001 if( dst_first_rc == rc_xmm && src_first_rc == rc_stack ) { 1002 return impl_x_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first, dst_second, size, st); 1003 } 1004 1005 // Copy from float reg to xmm reg 1006 if( dst_first_rc == rc_xmm && src_first_rc == rc_float ) { 1007 // copy to the top of stack from floating point reg 1008 // and use LEA to preserve flags 1009 if( cbuf ) { 1010 emit_opcode(*cbuf,0x8D); // LEA ESP,[ESP-8] 1011 emit_rm(*cbuf, 0x1, ESP_enc, 0x04); 1012 emit_rm(*cbuf, 0x0, 0x04, ESP_enc); 1013 emit_d8(*cbuf,0xF8); 1014 #ifndef PRODUCT 1015 } else if( !do_size ) { 1016 if( size != 0 ) st->print("\n\t"); 1017 st->print("LEA ESP,[ESP-8]"); 1018 #endif 1019 } 1020 size += 4; 1021 1022 size = impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,0,size, st); 1023 1024 // Copy from the temp memory to the xmm reg. 1025 size = impl_x_helper(cbuf,do_size,true ,0,dst_first, dst_second, size, st); 1026 1027 if( cbuf ) { 1028 emit_opcode(*cbuf,0x8D); // LEA ESP,[ESP+8] 1029 emit_rm(*cbuf, 0x1, ESP_enc, 0x04); 1030 emit_rm(*cbuf, 0x0, 0x04, ESP_enc); 1031 emit_d8(*cbuf,0x08); 1032 #ifndef PRODUCT 1033 } else if( !do_size ) { 1034 if( size != 0 ) st->print("\n\t"); 1035 st->print("LEA ESP,[ESP+8]"); 1036 #endif 1037 } 1038 size += 4; 1039 return size; 1040 } 1041 1042 assert( size > 0, "missed a case" ); 1043 1044 // -------------------------------------------------------------------- 1045 // Check for second bits still needing moving. 1046 if( src_second == dst_second ) 1047 return size; // Self copy; no move 1048 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" ); 1049 1050 // Check for second word int-int move 1051 if( src_second_rc == rc_int && dst_second_rc == rc_int ) 1052 return impl_mov_helper(cbuf,do_size,src_second,dst_second,size, st); 1053 1054 // Check for second word integer store 1055 if( src_second_rc == rc_int && dst_second_rc == rc_stack ) 1056 return impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),src_second,0x89,"MOV ",size, st); 1057 1058 // Check for second word integer load 1059 if( dst_second_rc == rc_int && src_second_rc == rc_stack ) 1060 return impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),dst_second,0x8B,"MOV ",size, st); 1061 1062 1063 Unimplemented(); 1064 } 1065 1066 #ifndef PRODUCT 1067 void MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream* st ) const { 1068 implementation( NULL, ra_, false, st ); 1069 } 1070 #endif 1071 1072 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1073 implementation( &cbuf, ra_, false, NULL ); 1074 } 1075 1076 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const { 1077 return implementation( NULL, ra_, true, NULL ); 1078 } 1079 1080 //============================================================================= 1081 #ifndef PRODUCT 1082 void MachNopNode::format( PhaseRegAlloc *, outputStream* st ) const { 1083 st->print("NOP \t# %d bytes pad for loops and calls", _count); 1084 } 1085 #endif 1086 1087 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc * ) const { 1088 MacroAssembler _masm(&cbuf); 1089 __ nop(_count); 1090 } 1091 1092 uint MachNopNode::size(PhaseRegAlloc *) const { 1093 return _count; 1094 } 1095 1096 1097 //============================================================================= 1098 #ifndef PRODUCT 1099 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream* st ) const { 1100 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); 1101 int reg = ra_->get_reg_first(this); 1102 st->print("LEA %s,[ESP + #%d]",Matcher::regName[reg],offset); 1103 } 1104 #endif 1105 1106 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1107 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); 1108 int reg = ra_->get_encode(this); 1109 if( offset >= 128 ) { 1110 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset] 1111 emit_rm(cbuf, 0x2, reg, 0x04); 1112 emit_rm(cbuf, 0x0, 0x04, ESP_enc); 1113 emit_d32(cbuf, offset); 1114 } 1115 else { 1116 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset] 1117 emit_rm(cbuf, 0x1, reg, 0x04); 1118 emit_rm(cbuf, 0x0, 0x04, ESP_enc); 1119 emit_d8(cbuf, offset); 1120 } 1121 } 1122 1123 uint BoxLockNode::size(PhaseRegAlloc *ra_) const { 1124 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); 1125 if( offset >= 128 ) { 1126 return 7; 1127 } 1128 else { 1129 return 4; 1130 } 1131 } 1132 1133 //============================================================================= 1134 1135 // emit call stub, compiled java to interpreter 1136 void emit_java_to_interp(CodeBuffer &cbuf ) { 1137 // Stub is fixed up when the corresponding call is converted from calling 1138 // compiled code to calling interpreted code. 1139 // mov rbx,0 1140 // jmp -1 1141 1142 address mark = cbuf.inst_mark(); // get mark within main instrs section 1143 1144 // Note that the code buffer's inst_mark is always relative to insts. 1145 // That's why we must use the macroassembler to generate a stub. 1146 MacroAssembler _masm(&cbuf); 1147 1148 address base = 1149 __ start_a_stub(Compile::MAX_stubs_size); 1150 if (base == NULL) return; // CodeBuffer::expand failed 1151 // static stub relocation stores the instruction address of the call 1152 __ relocate(static_stub_Relocation::spec(mark), RELOC_IMM32); 1153 // static stub relocation also tags the methodOop in the code-stream. 1154 __ movoop(rbx, (jobject)NULL); // method is zapped till fixup time 1155 // This is recognized as unresolved by relocs/nativeInst/ic code 1156 __ jump(RuntimeAddress(__ pc())); 1157 1158 __ end_a_stub(); 1159 // Update current stubs pointer and restore code_end. 1160 } 1161 // size of call stub, compiled java to interpretor 1162 uint size_java_to_interp() { 1163 return 10; // movl; jmp 1164 } 1165 // relocation entries for call stub, compiled java to interpretor 1166 uint reloc_java_to_interp() { 1167 return 4; // 3 in emit_java_to_interp + 1 in Java_Static_Call 1168 } 1169 1170 //============================================================================= 1171 #ifndef PRODUCT 1172 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream* st ) const { 1173 st->print_cr( "CMP EAX,[ECX+4]\t# Inline cache check"); 1174 st->print_cr("\tJNE SharedRuntime::handle_ic_miss_stub"); 1175 st->print_cr("\tNOP"); 1176 st->print_cr("\tNOP"); 1177 if( !OptoBreakpoint ) 1178 st->print_cr("\tNOP"); 1179 } 1180 #endif 1181 1182 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1183 MacroAssembler masm(&cbuf); 1184 #ifdef ASSERT 1185 uint code_size = cbuf.code_size(); 1186 #endif 1187 masm.cmpptr(rax, Address(rcx, oopDesc::klass_offset_in_bytes())); 1188 masm.jump_cc(Assembler::notEqual, 1189 RuntimeAddress(SharedRuntime::get_ic_miss_stub())); 1190 /* WARNING these NOPs are critical so that verified entry point is properly 1191 aligned for patching by NativeJump::patch_verified_entry() */ 1192 int nops_cnt = 2; 1193 if( !OptoBreakpoint ) // Leave space for int3 1194 nops_cnt += 1; 1195 masm.nop(nops_cnt); 1196 1197 assert(cbuf.code_size() - code_size == size(ra_), "checking code size of inline cache node"); 1198 } 1199 1200 uint MachUEPNode::size(PhaseRegAlloc *ra_) const { 1201 return OptoBreakpoint ? 11 : 12; 1202 } 1203 1204 1205 //============================================================================= 1206 uint size_exception_handler() { 1207 // NativeCall instruction size is the same as NativeJump. 1208 // exception handler starts out as jump and can be patched to 1209 // a call be deoptimization. (4932387) 1210 // Note that this value is also credited (in output.cpp) to 1211 // the size of the code section. 1212 return NativeJump::instruction_size; 1213 } 1214 1215 // Emit exception handler code. Stuff framesize into a register 1216 // and call a VM stub routine. 1217 int emit_exception_handler(CodeBuffer& cbuf) { 1218 1219 // Note that the code buffer's inst_mark is always relative to insts. 1220 // That's why we must use the macroassembler to generate a handler. 1221 MacroAssembler _masm(&cbuf); 1222 address base = 1223 __ start_a_stub(size_exception_handler()); 1224 if (base == NULL) return 0; // CodeBuffer::expand failed 1225 int offset = __ offset(); 1226 __ jump(RuntimeAddress(OptoRuntime::exception_blob()->instructions_begin())); 1227 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow"); 1228 __ end_a_stub(); 1229 return offset; 1230 } 1231 1232 uint size_deopt_handler() { 1233 // NativeCall instruction size is the same as NativeJump. 1234 // exception handler starts out as jump and can be patched to 1235 // a call be deoptimization. (4932387) 1236 // Note that this value is also credited (in output.cpp) to 1237 // the size of the code section. 1238 return 5 + NativeJump::instruction_size; // pushl(); jmp; 1239 } 1240 1241 // Emit deopt handler code. 1242 int emit_deopt_handler(CodeBuffer& cbuf) { 1243 1244 // Note that the code buffer's inst_mark is always relative to insts. 1245 // That's why we must use the macroassembler to generate a handler. 1246 MacroAssembler _masm(&cbuf); 1247 address base = 1248 __ start_a_stub(size_exception_handler()); 1249 if (base == NULL) return 0; // CodeBuffer::expand failed 1250 int offset = __ offset(); 1251 InternalAddress here(__ pc()); 1252 __ pushptr(here.addr()); 1253 1254 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack())); 1255 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow"); 1256 __ end_a_stub(); 1257 return offset; 1258 } 1259 1260 1261 static void emit_double_constant(CodeBuffer& cbuf, double x) { 1262 int mark = cbuf.insts()->mark_off(); 1263 MacroAssembler _masm(&cbuf); 1264 address double_address = __ double_constant(x); 1265 cbuf.insts()->set_mark_off(mark); // preserve mark across masm shift 1266 emit_d32_reloc(cbuf, 1267 (int)double_address, 1268 internal_word_Relocation::spec(double_address), 1269 RELOC_DISP32); 1270 } 1271 1272 static void emit_float_constant(CodeBuffer& cbuf, float x) { 1273 int mark = cbuf.insts()->mark_off(); 1274 MacroAssembler _masm(&cbuf); 1275 address float_address = __ float_constant(x); 1276 cbuf.insts()->set_mark_off(mark); // preserve mark across masm shift 1277 emit_d32_reloc(cbuf, 1278 (int)float_address, 1279 internal_word_Relocation::spec(float_address), 1280 RELOC_DISP32); 1281 } 1282 1283 1284 const bool Matcher::match_rule_supported(int opcode) { 1285 if (!has_match_rule(opcode)) 1286 return false; 1287 1288 return true; // Per default match rules are supported. 1289 } 1290 1291 int Matcher::regnum_to_fpu_offset(int regnum) { 1292 return regnum - 32; // The FP registers are in the second chunk 1293 } 1294 1295 bool is_positive_zero_float(jfloat f) { 1296 return jint_cast(f) == jint_cast(0.0F); 1297 } 1298 1299 bool is_positive_one_float(jfloat f) { 1300 return jint_cast(f) == jint_cast(1.0F); 1301 } 1302 1303 bool is_positive_zero_double(jdouble d) { 1304 return jlong_cast(d) == jlong_cast(0.0); 1305 } 1306 1307 bool is_positive_one_double(jdouble d) { 1308 return jlong_cast(d) == jlong_cast(1.0); 1309 } 1310 1311 // This is UltraSparc specific, true just means we have fast l2f conversion 1312 const bool Matcher::convL2FSupported(void) { 1313 return true; 1314 } 1315 1316 // Vector width in bytes 1317 const uint Matcher::vector_width_in_bytes(void) { 1318 return UseSSE >= 2 ? 8 : 0; 1319 } 1320 1321 // Vector ideal reg 1322 const uint Matcher::vector_ideal_reg(void) { 1323 return Op_RegD; 1324 } 1325 1326 // Is this branch offset short enough that a short branch can be used? 1327 // 1328 // NOTE: If the platform does not provide any short branch variants, then 1329 // this method should return false for offset 0. 1330 bool Matcher::is_short_branch_offset(int rule, int offset) { 1331 // the short version of jmpConUCF2 contains multiple branches, 1332 // making the reach slightly less 1333 if (rule == jmpConUCF2_rule) 1334 return (-126 <= offset && offset <= 125); 1335 return (-128 <= offset && offset <= 127); 1336 } 1337 1338 const bool Matcher::isSimpleConstant64(jlong value) { 1339 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?. 1340 return false; 1341 } 1342 1343 // The ecx parameter to rep stos for the ClearArray node is in dwords. 1344 const bool Matcher::init_array_count_is_in_bytes = false; 1345 1346 // Threshold size for cleararray. 1347 const int Matcher::init_array_short_size = 8 * BytesPerLong; 1348 1349 // Should the Matcher clone shifts on addressing modes, expecting them to 1350 // be subsumed into complex addressing expressions or compute them into 1351 // registers? True for Intel but false for most RISCs 1352 const bool Matcher::clone_shift_expressions = true; 1353 1354 // Is it better to copy float constants, or load them directly from memory? 1355 // Intel can load a float constant from a direct address, requiring no 1356 // extra registers. Most RISCs will have to materialize an address into a 1357 // register first, so they would do better to copy the constant from stack. 1358 const bool Matcher::rematerialize_float_constants = true; 1359 1360 // If CPU can load and store mis-aligned doubles directly then no fixup is 1361 // needed. Else we split the double into 2 integer pieces and move it 1362 // piece-by-piece. Only happens when passing doubles into C code as the 1363 // Java calling convention forces doubles to be aligned. 1364 const bool Matcher::misaligned_doubles_ok = true; 1365 1366 1367 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) { 1368 // Get the memory operand from the node 1369 uint numopnds = node->num_opnds(); // Virtual call for number of operands 1370 uint skipped = node->oper_input_base(); // Sum of leaves skipped so far 1371 assert( idx >= skipped, "idx too low in pd_implicit_null_fixup" ); 1372 uint opcnt = 1; // First operand 1373 uint num_edges = node->_opnds[1]->num_edges(); // leaves for first operand 1374 while( idx >= skipped+num_edges ) { 1375 skipped += num_edges; 1376 opcnt++; // Bump operand count 1377 assert( opcnt < numopnds, "Accessing non-existent operand" ); 1378 num_edges = node->_opnds[opcnt]->num_edges(); // leaves for next operand 1379 } 1380 1381 MachOper *memory = node->_opnds[opcnt]; 1382 MachOper *new_memory = NULL; 1383 switch (memory->opcode()) { 1384 case DIRECT: 1385 case INDOFFSET32X: 1386 // No transformation necessary. 1387 return; 1388 case INDIRECT: 1389 new_memory = new (C) indirect_win95_safeOper( ); 1390 break; 1391 case INDOFFSET8: 1392 new_memory = new (C) indOffset8_win95_safeOper(memory->disp(NULL, NULL, 0)); 1393 break; 1394 case INDOFFSET32: 1395 new_memory = new (C) indOffset32_win95_safeOper(memory->disp(NULL, NULL, 0)); 1396 break; 1397 case INDINDEXOFFSET: 1398 new_memory = new (C) indIndexOffset_win95_safeOper(memory->disp(NULL, NULL, 0)); 1399 break; 1400 case INDINDEXSCALE: 1401 new_memory = new (C) indIndexScale_win95_safeOper(memory->scale()); 1402 break; 1403 case INDINDEXSCALEOFFSET: 1404 new_memory = new (C) indIndexScaleOffset_win95_safeOper(memory->scale(), memory->disp(NULL, NULL, 0)); 1405 break; 1406 case LOAD_LONG_INDIRECT: 1407 case LOAD_LONG_INDOFFSET32: 1408 // Does not use EBP as address register, use { EDX, EBX, EDI, ESI} 1409 return; 1410 default: 1411 assert(false, "unexpected memory operand in pd_implicit_null_fixup()"); 1412 return; 1413 } 1414 node->_opnds[opcnt] = new_memory; 1415 } 1416 1417 // Advertise here if the CPU requires explicit rounding operations 1418 // to implement the UseStrictFP mode. 1419 const bool Matcher::strict_fp_requires_explicit_rounding = true; 1420 1421 // Do floats take an entire double register or just half? 1422 const bool Matcher::float_in_double = true; 1423 // Do ints take an entire long register or just half? 1424 const bool Matcher::int_in_long = false; 1425 1426 // Return whether or not this register is ever used as an argument. This 1427 // function is used on startup to build the trampoline stubs in generateOptoStub. 1428 // Registers not mentioned will be killed by the VM call in the trampoline, and 1429 // arguments in those registers not be available to the callee. 1430 bool Matcher::can_be_java_arg( int reg ) { 1431 if( reg == ECX_num || reg == EDX_num ) return true; 1432 if( (reg == XMM0a_num || reg == XMM1a_num) && UseSSE>=1 ) return true; 1433 if( (reg == XMM0b_num || reg == XMM1b_num) && UseSSE>=2 ) return true; 1434 return false; 1435 } 1436 1437 bool Matcher::is_spillable_arg( int reg ) { 1438 return can_be_java_arg(reg); 1439 } 1440 1441 // Register for DIVI projection of divmodI 1442 RegMask Matcher::divI_proj_mask() { 1443 return EAX_REG_mask; 1444 } 1445 1446 // Register for MODI projection of divmodI 1447 RegMask Matcher::modI_proj_mask() { 1448 return EDX_REG_mask; 1449 } 1450 1451 // Register for DIVL projection of divmodL 1452 RegMask Matcher::divL_proj_mask() { 1453 ShouldNotReachHere(); 1454 return RegMask(); 1455 } 1456 1457 // Register for MODL projection of divmodL 1458 RegMask Matcher::modL_proj_mask() { 1459 ShouldNotReachHere(); 1460 return RegMask(); 1461 } 1462 1463 %} 1464 1465 //----------ENCODING BLOCK----------------------------------------------------- 1466 // This block specifies the encoding classes used by the compiler to output 1467 // byte streams. Encoding classes generate functions which are called by 1468 // Machine Instruction Nodes in order to generate the bit encoding of the 1469 // instruction. Operands specify their base encoding interface with the 1470 // interface keyword. There are currently supported four interfaces, 1471 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an 1472 // operand to generate a function which returns its register number when 1473 // queried. CONST_INTER causes an operand to generate a function which 1474 // returns the value of the constant when queried. MEMORY_INTER causes an 1475 // operand to generate four functions which return the Base Register, the 1476 // Index Register, the Scale Value, and the Offset Value of the operand when 1477 // queried. COND_INTER causes an operand to generate six functions which 1478 // return the encoding code (ie - encoding bits for the instruction) 1479 // associated with each basic boolean condition for a conditional instruction. 1480 // Instructions specify two basic values for encoding. They use the 1481 // ins_encode keyword to specify their encoding class (which must be one of 1482 // the class names specified in the encoding block), and they use the 1483 // opcode keyword to specify, in order, their primary, secondary, and 1484 // tertiary opcode. Only the opcode sections which a particular instruction 1485 // needs for encoding need to be specified. 1486 encode %{ 1487 // Build emit functions for each basic byte or larger field in the intel 1488 // encoding scheme (opcode, rm, sib, immediate), and call them from C++ 1489 // code in the enc_class source block. Emit functions will live in the 1490 // main source block for now. In future, we can generalize this by 1491 // adding a syntax that specifies the sizes of fields in an order, 1492 // so that the adlc can build the emit functions automagically 1493 1494 // Emit primary opcode 1495 enc_class OpcP %{ 1496 emit_opcode(cbuf, $primary); 1497 %} 1498 1499 // Emit secondary opcode 1500 enc_class OpcS %{ 1501 emit_opcode(cbuf, $secondary); 1502 %} 1503 1504 // Emit opcode directly 1505 enc_class Opcode(immI d8) %{ 1506 emit_opcode(cbuf, $d8$$constant); 1507 %} 1508 1509 enc_class SizePrefix %{ 1510 emit_opcode(cbuf,0x66); 1511 %} 1512 1513 enc_class RegReg (eRegI dst, eRegI src) %{ // RegReg(Many) 1514 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); 1515 %} 1516 1517 enc_class OpcRegReg (immI opcode, eRegI dst, eRegI src) %{ // OpcRegReg(Many) 1518 emit_opcode(cbuf,$opcode$$constant); 1519 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); 1520 %} 1521 1522 enc_class mov_r32_imm0( eRegI dst ) %{ 1523 emit_opcode( cbuf, 0xB8 + $dst$$reg ); // 0xB8+ rd -- MOV r32 ,imm32 1524 emit_d32 ( cbuf, 0x0 ); // imm32==0x0 1525 %} 1526 1527 enc_class cdq_enc %{ 1528 // Full implementation of Java idiv and irem; checks for 1529 // special case as described in JVM spec., p.243 & p.271. 1530 // 1531 // normal case special case 1532 // 1533 // input : rax,: dividend min_int 1534 // reg: divisor -1 1535 // 1536 // output: rax,: quotient (= rax, idiv reg) min_int 1537 // rdx: remainder (= rax, irem reg) 0 1538 // 1539 // Code sequnce: 1540 // 1541 // 81 F8 00 00 00 80 cmp rax,80000000h 1542 // 0F 85 0B 00 00 00 jne normal_case 1543 // 33 D2 xor rdx,edx 1544 // 83 F9 FF cmp rcx,0FFh 1545 // 0F 84 03 00 00 00 je done 1546 // normal_case: 1547 // 99 cdq 1548 // F7 F9 idiv rax,ecx 1549 // done: 1550 // 1551 emit_opcode(cbuf,0x81); emit_d8(cbuf,0xF8); 1552 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); 1553 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x80); // cmp rax,80000000h 1554 emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x85); 1555 emit_opcode(cbuf,0x0B); emit_d8(cbuf,0x00); 1556 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); // jne normal_case 1557 emit_opcode(cbuf,0x33); emit_d8(cbuf,0xD2); // xor rdx,edx 1558 emit_opcode(cbuf,0x83); emit_d8(cbuf,0xF9); emit_d8(cbuf,0xFF); // cmp rcx,0FFh 1559 emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x84); 1560 emit_opcode(cbuf,0x03); emit_d8(cbuf,0x00); 1561 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); // je done 1562 // normal_case: 1563 emit_opcode(cbuf,0x99); // cdq 1564 // idiv (note: must be emitted by the user of this rule) 1565 // normal: 1566 %} 1567 1568 // Dense encoding for older common ops 1569 enc_class Opc_plus(immI opcode, eRegI reg) %{ 1570 emit_opcode(cbuf, $opcode$$constant + $reg$$reg); 1571 %} 1572 1573 1574 // Opcde enc_class for 8/32 bit immediate instructions with sign-extension 1575 enc_class OpcSE (immI imm) %{ // Emit primary opcode and set sign-extend bit 1576 // Check for 8-bit immediate, and set sign extend bit in opcode 1577 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) { 1578 emit_opcode(cbuf, $primary | 0x02); 1579 } 1580 else { // If 32-bit immediate 1581 emit_opcode(cbuf, $primary); 1582 } 1583 %} 1584 1585 enc_class OpcSErm (eRegI dst, immI imm) %{ // OpcSEr/m 1586 // Emit primary opcode and set sign-extend bit 1587 // Check for 8-bit immediate, and set sign extend bit in opcode 1588 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) { 1589 emit_opcode(cbuf, $primary | 0x02); } 1590 else { // If 32-bit immediate 1591 emit_opcode(cbuf, $primary); 1592 } 1593 // Emit r/m byte with secondary opcode, after primary opcode. 1594 emit_rm(cbuf, 0x3, $secondary, $dst$$reg); 1595 %} 1596 1597 enc_class Con8or32 (immI imm) %{ // Con8or32(storeImmI), 8 or 32 bits 1598 // Check for 8-bit immediate, and set sign extend bit in opcode 1599 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) { 1600 $$$emit8$imm$$constant; 1601 } 1602 else { // If 32-bit immediate 1603 // Output immediate 1604 $$$emit32$imm$$constant; 1605 } 1606 %} 1607 1608 enc_class Long_OpcSErm_Lo(eRegL dst, immL imm) %{ 1609 // Emit primary opcode and set sign-extend bit 1610 // Check for 8-bit immediate, and set sign extend bit in opcode 1611 int con = (int)$imm$$constant; // Throw away top bits 1612 emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary); 1613 // Emit r/m byte with secondary opcode, after primary opcode. 1614 emit_rm(cbuf, 0x3, $secondary, $dst$$reg); 1615 if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con); 1616 else emit_d32(cbuf,con); 1617 %} 1618 1619 enc_class Long_OpcSErm_Hi(eRegL dst, immL imm) %{ 1620 // Emit primary opcode and set sign-extend bit 1621 // Check for 8-bit immediate, and set sign extend bit in opcode 1622 int con = (int)($imm$$constant >> 32); // Throw away bottom bits 1623 emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary); 1624 // Emit r/m byte with tertiary opcode, after primary opcode. 1625 emit_rm(cbuf, 0x3, $tertiary, HIGH_FROM_LOW($dst$$reg)); 1626 if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con); 1627 else emit_d32(cbuf,con); 1628 %} 1629 1630 enc_class Lbl (label labl) %{ // JMP, CALL 1631 Label *l = $labl$$label; 1632 emit_d32(cbuf, l ? (l->loc_pos() - (cbuf.code_size()+4)) : 0); 1633 %} 1634 1635 enc_class LblShort (label labl) %{ // JMP, CALL 1636 Label *l = $labl$$label; 1637 int disp = l ? (l->loc_pos() - (cbuf.code_size()+1)) : 0; 1638 assert(-128 <= disp && disp <= 127, "Displacement too large for short jmp"); 1639 emit_d8(cbuf, disp); 1640 %} 1641 1642 enc_class OpcSReg (eRegI dst) %{ // BSWAP 1643 emit_cc(cbuf, $secondary, $dst$$reg ); 1644 %} 1645 1646 enc_class bswap_long_bytes(eRegL dst) %{ // BSWAP 1647 int destlo = $dst$$reg; 1648 int desthi = HIGH_FROM_LOW(destlo); 1649 // bswap lo 1650 emit_opcode(cbuf, 0x0F); 1651 emit_cc(cbuf, 0xC8, destlo); 1652 // bswap hi 1653 emit_opcode(cbuf, 0x0F); 1654 emit_cc(cbuf, 0xC8, desthi); 1655 // xchg lo and hi 1656 emit_opcode(cbuf, 0x87); 1657 emit_rm(cbuf, 0x3, destlo, desthi); 1658 %} 1659 1660 enc_class RegOpc (eRegI div) %{ // IDIV, IMOD, JMP indirect, ... 1661 emit_rm(cbuf, 0x3, $secondary, $div$$reg ); 1662 %} 1663 1664 enc_class Jcc (cmpOp cop, label labl) %{ // JCC 1665 Label *l = $labl$$label; 1666 $$$emit8$primary; 1667 emit_cc(cbuf, $secondary, $cop$$cmpcode); 1668 emit_d32(cbuf, l ? (l->loc_pos() - (cbuf.code_size()+4)) : 0); 1669 %} 1670 1671 enc_class JccShort (cmpOp cop, label labl) %{ // JCC 1672 Label *l = $labl$$label; 1673 emit_cc(cbuf, $primary, $cop$$cmpcode); 1674 int disp = l ? (l->loc_pos() - (cbuf.code_size()+1)) : 0; 1675 assert(-128 <= disp && disp <= 127, "Displacement too large for short jmp"); 1676 emit_d8(cbuf, disp); 1677 %} 1678 1679 enc_class enc_cmov(cmpOp cop ) %{ // CMOV 1680 $$$emit8$primary; 1681 emit_cc(cbuf, $secondary, $cop$$cmpcode); 1682 %} 1683 1684 enc_class enc_cmov_d(cmpOp cop, regD src ) %{ // CMOV 1685 int op = 0xDA00 + $cop$$cmpcode + ($src$$reg-1); 1686 emit_d8(cbuf, op >> 8 ); 1687 emit_d8(cbuf, op & 255); 1688 %} 1689 1690 // emulate a CMOV with a conditional branch around a MOV 1691 enc_class enc_cmov_branch( cmpOp cop, immI brOffs ) %{ // CMOV 1692 // Invert sense of branch from sense of CMOV 1693 emit_cc( cbuf, 0x70, ($cop$$cmpcode^1) ); 1694 emit_d8( cbuf, $brOffs$$constant ); 1695 %} 1696 1697 enc_class enc_PartialSubtypeCheck( ) %{ 1698 Register Redi = as_Register(EDI_enc); // result register 1699 Register Reax = as_Register(EAX_enc); // super class 1700 Register Recx = as_Register(ECX_enc); // killed 1701 Register Resi = as_Register(ESI_enc); // sub class 1702 Label miss; 1703 1704 MacroAssembler _masm(&cbuf); 1705 __ check_klass_subtype_slow_path(Resi, Reax, Recx, Redi, 1706 NULL, &miss, 1707 /*set_cond_codes:*/ true); 1708 if ($primary) { 1709 __ xorptr(Redi, Redi); 1710 } 1711 __ bind(miss); 1712 %} 1713 1714 enc_class FFree_Float_Stack_All %{ // Free_Float_Stack_All 1715 MacroAssembler masm(&cbuf); 1716 int start = masm.offset(); 1717 if (UseSSE >= 2) { 1718 if (VerifyFPU) { 1719 masm.verify_FPU(0, "must be empty in SSE2+ mode"); 1720 } 1721 } else { 1722 // External c_calling_convention expects the FPU stack to be 'clean'. 1723 // Compiled code leaves it dirty. Do cleanup now. 1724 masm.empty_FPU_stack(); 1725 } 1726 if (sizeof_FFree_Float_Stack_All == -1) { 1727 sizeof_FFree_Float_Stack_All = masm.offset() - start; 1728 } else { 1729 assert(masm.offset() - start == sizeof_FFree_Float_Stack_All, "wrong size"); 1730 } 1731 %} 1732 1733 enc_class Verify_FPU_For_Leaf %{ 1734 if( VerifyFPU ) { 1735 MacroAssembler masm(&cbuf); 1736 masm.verify_FPU( -3, "Returning from Runtime Leaf call"); 1737 } 1738 %} 1739 1740 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime, Java_To_Runtime_Leaf 1741 // This is the instruction starting address for relocation info. 1742 cbuf.set_inst_mark(); 1743 $$$emit8$primary; 1744 // CALL directly to the runtime 1745 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.code_end()) - 4), 1746 runtime_call_Relocation::spec(), RELOC_IMM32 ); 1747 1748 if (UseSSE >= 2) { 1749 MacroAssembler _masm(&cbuf); 1750 BasicType rt = tf()->return_type(); 1751 1752 if ((rt == T_FLOAT || rt == T_DOUBLE) && !return_value_is_used()) { 1753 // A C runtime call where the return value is unused. In SSE2+ 1754 // mode the result needs to be removed from the FPU stack. It's 1755 // likely that this function call could be removed by the 1756 // optimizer if the C function is a pure function. 1757 __ ffree(0); 1758 } else if (rt == T_FLOAT) { 1759 __ lea(rsp, Address(rsp, -4)); 1760 __ fstp_s(Address(rsp, 0)); 1761 __ movflt(xmm0, Address(rsp, 0)); 1762 __ lea(rsp, Address(rsp, 4)); 1763 } else if (rt == T_DOUBLE) { 1764 __ lea(rsp, Address(rsp, -8)); 1765 __ fstp_d(Address(rsp, 0)); 1766 __ movdbl(xmm0, Address(rsp, 0)); 1767 __ lea(rsp, Address(rsp, 8)); 1768 } 1769 } 1770 %} 1771 1772 1773 enc_class pre_call_FPU %{ 1774 // If method sets FPU control word restore it here 1775 if( Compile::current()->in_24_bit_fp_mode() ) { 1776 MacroAssembler masm(&cbuf); 1777 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std())); 1778 } 1779 %} 1780 1781 enc_class post_call_FPU %{ 1782 // If method sets FPU control word do it here also 1783 if( Compile::current()->in_24_bit_fp_mode() ) { 1784 MacroAssembler masm(&cbuf); 1785 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24())); 1786 } 1787 %} 1788 1789 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL 1790 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine 1791 // who we intended to call. 1792 cbuf.set_inst_mark(); 1793 $$$emit8$primary; 1794 if ( !_method ) { 1795 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.code_end()) - 4), 1796 runtime_call_Relocation::spec(), RELOC_IMM32 ); 1797 } else if(_optimized_virtual) { 1798 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.code_end()) - 4), 1799 opt_virtual_call_Relocation::spec(), RELOC_IMM32 ); 1800 } else { 1801 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.code_end()) - 4), 1802 static_call_Relocation::spec(), RELOC_IMM32 ); 1803 } 1804 if( _method ) { // Emit stub for static call 1805 emit_java_to_interp(cbuf); 1806 } 1807 %} 1808 1809 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL 1810 // !!!!! 1811 // Generate "Mov EAX,0x00", placeholder instruction to load oop-info 1812 // emit_call_dynamic_prologue( cbuf ); 1813 cbuf.set_inst_mark(); 1814 emit_opcode(cbuf, 0xB8 + EAX_enc); // mov EAX,-1 1815 emit_d32_reloc(cbuf, (int)Universe::non_oop_word(), oop_Relocation::spec_for_immediate(), RELOC_IMM32); 1816 address virtual_call_oop_addr = cbuf.inst_mark(); 1817 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine 1818 // who we intended to call. 1819 cbuf.set_inst_mark(); 1820 $$$emit8$primary; 1821 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.code_end()) - 4), 1822 virtual_call_Relocation::spec(virtual_call_oop_addr), RELOC_IMM32 ); 1823 %} 1824 1825 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL 1826 int disp = in_bytes(methodOopDesc::from_compiled_offset()); 1827 assert( -128 <= disp && disp <= 127, "compiled_code_offset isn't small"); 1828 1829 // CALL *[EAX+in_bytes(methodOopDesc::from_compiled_code_entry_point_offset())] 1830 cbuf.set_inst_mark(); 1831 $$$emit8$primary; 1832 emit_rm(cbuf, 0x01, $secondary, EAX_enc ); // R/M byte 1833 emit_d8(cbuf, disp); // Displacement 1834 1835 %} 1836 1837 enc_class Xor_Reg (eRegI dst) %{ 1838 emit_opcode(cbuf, 0x33); 1839 emit_rm(cbuf, 0x3, $dst$$reg, $dst$$reg); 1840 %} 1841 1842 // Following encoding is no longer used, but may be restored if calling 1843 // convention changes significantly. 1844 // Became: Xor_Reg(EBP), Java_To_Runtime( labl ) 1845 // 1846 // enc_class Java_Interpreter_Call (label labl) %{ // JAVA INTERPRETER CALL 1847 // // int ic_reg = Matcher::inline_cache_reg(); 1848 // // int ic_encode = Matcher::_regEncode[ic_reg]; 1849 // // int imo_reg = Matcher::interpreter_method_oop_reg(); 1850 // // int imo_encode = Matcher::_regEncode[imo_reg]; 1851 // 1852 // // // Interpreter expects method_oop in EBX, currently a callee-saved register, 1853 // // // so we load it immediately before the call 1854 // // emit_opcode(cbuf, 0x8B); // MOV imo_reg,ic_reg # method_oop 1855 // // emit_rm(cbuf, 0x03, imo_encode, ic_encode ); // R/M byte 1856 // 1857 // // xor rbp,ebp 1858 // emit_opcode(cbuf, 0x33); 1859 // emit_rm(cbuf, 0x3, EBP_enc, EBP_enc); 1860 // 1861 // // CALL to interpreter. 1862 // cbuf.set_inst_mark(); 1863 // $$$emit8$primary; 1864 // emit_d32_reloc(cbuf, ($labl$$label - (int)(cbuf.code_end()) - 4), 1865 // runtime_call_Relocation::spec(), RELOC_IMM32 ); 1866 // %} 1867 1868 enc_class RegOpcImm (eRegI dst, immI8 shift) %{ // SHL, SAR, SHR 1869 $$$emit8$primary; 1870 emit_rm(cbuf, 0x3, $secondary, $dst$$reg); 1871 $$$emit8$shift$$constant; 1872 %} 1873 1874 enc_class LdImmI (eRegI dst, immI src) %{ // Load Immediate 1875 // Load immediate does not have a zero or sign extended version 1876 // for 8-bit immediates 1877 emit_opcode(cbuf, 0xB8 + $dst$$reg); 1878 $$$emit32$src$$constant; 1879 %} 1880 1881 enc_class LdImmP (eRegI dst, immI src) %{ // Load Immediate 1882 // Load immediate does not have a zero or sign extended version 1883 // for 8-bit immediates 1884 emit_opcode(cbuf, $primary + $dst$$reg); 1885 $$$emit32$src$$constant; 1886 %} 1887 1888 enc_class LdImmL_Lo( eRegL dst, immL src) %{ // Load Immediate 1889 // Load immediate does not have a zero or sign extended version 1890 // for 8-bit immediates 1891 int dst_enc = $dst$$reg; 1892 int src_con = $src$$constant & 0x0FFFFFFFFL; 1893 if (src_con == 0) { 1894 // xor dst, dst 1895 emit_opcode(cbuf, 0x33); 1896 emit_rm(cbuf, 0x3, dst_enc, dst_enc); 1897 } else { 1898 emit_opcode(cbuf, $primary + dst_enc); 1899 emit_d32(cbuf, src_con); 1900 } 1901 %} 1902 1903 enc_class LdImmL_Hi( eRegL dst, immL src) %{ // Load Immediate 1904 // Load immediate does not have a zero or sign extended version 1905 // for 8-bit immediates 1906 int dst_enc = $dst$$reg + 2; 1907 int src_con = ((julong)($src$$constant)) >> 32; 1908 if (src_con == 0) { 1909 // xor dst, dst 1910 emit_opcode(cbuf, 0x33); 1911 emit_rm(cbuf, 0x3, dst_enc, dst_enc); 1912 } else { 1913 emit_opcode(cbuf, $primary + dst_enc); 1914 emit_d32(cbuf, src_con); 1915 } 1916 %} 1917 1918 1919 enc_class LdImmD (immD src) %{ // Load Immediate 1920 if( is_positive_zero_double($src$$constant)) { 1921 // FLDZ 1922 emit_opcode(cbuf,0xD9); 1923 emit_opcode(cbuf,0xEE); 1924 } else if( is_positive_one_double($src$$constant)) { 1925 // FLD1 1926 emit_opcode(cbuf,0xD9); 1927 emit_opcode(cbuf,0xE8); 1928 } else { 1929 emit_opcode(cbuf,0xDD); 1930 emit_rm(cbuf, 0x0, 0x0, 0x5); 1931 emit_double_constant(cbuf, $src$$constant); 1932 } 1933 %} 1934 1935 1936 enc_class LdImmF (immF src) %{ // Load Immediate 1937 if( is_positive_zero_float($src$$constant)) { 1938 emit_opcode(cbuf,0xD9); 1939 emit_opcode(cbuf,0xEE); 1940 } else if( is_positive_one_float($src$$constant)) { 1941 emit_opcode(cbuf,0xD9); 1942 emit_opcode(cbuf,0xE8); 1943 } else { 1944 $$$emit8$primary; 1945 // Load immediate does not have a zero or sign extended version 1946 // for 8-bit immediates 1947 // First load to TOS, then move to dst 1948 emit_rm(cbuf, 0x0, 0x0, 0x5); 1949 emit_float_constant(cbuf, $src$$constant); 1950 } 1951 %} 1952 1953 enc_class LdImmX (regX dst, immXF con) %{ // Load Immediate 1954 emit_rm(cbuf, 0x0, $dst$$reg, 0x5); 1955 emit_float_constant(cbuf, $con$$constant); 1956 %} 1957 1958 enc_class LdImmXD (regXD dst, immXD con) %{ // Load Immediate 1959 emit_rm(cbuf, 0x0, $dst$$reg, 0x5); 1960 emit_double_constant(cbuf, $con$$constant); 1961 %} 1962 1963 enc_class load_conXD (regXD dst, immXD con) %{ // Load double constant 1964 // UseXmmLoadAndClearUpper ? movsd(dst, con) : movlpd(dst, con) 1965 emit_opcode(cbuf, UseXmmLoadAndClearUpper ? 0xF2 : 0x66); 1966 emit_opcode(cbuf, 0x0F); 1967 emit_opcode(cbuf, UseXmmLoadAndClearUpper ? 0x10 : 0x12); 1968 emit_rm(cbuf, 0x0, $dst$$reg, 0x5); 1969 emit_double_constant(cbuf, $con$$constant); 1970 %} 1971 1972 enc_class Opc_MemImm_F(immF src) %{ 1973 cbuf.set_inst_mark(); 1974 $$$emit8$primary; 1975 emit_rm(cbuf, 0x0, $secondary, 0x5); 1976 emit_float_constant(cbuf, $src$$constant); 1977 %} 1978 1979 1980 enc_class MovI2X_reg(regX dst, eRegI src) %{ 1981 emit_opcode(cbuf, 0x66 ); // MOVD dst,src 1982 emit_opcode(cbuf, 0x0F ); 1983 emit_opcode(cbuf, 0x6E ); 1984 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); 1985 %} 1986 1987 enc_class MovX2I_reg(eRegI dst, regX src) %{ 1988 emit_opcode(cbuf, 0x66 ); // MOVD dst,src 1989 emit_opcode(cbuf, 0x0F ); 1990 emit_opcode(cbuf, 0x7E ); 1991 emit_rm(cbuf, 0x3, $src$$reg, $dst$$reg); 1992 %} 1993 1994 enc_class MovL2XD_reg(regXD dst, eRegL src, regXD tmp) %{ 1995 { // MOVD $dst,$src.lo 1996 emit_opcode(cbuf,0x66); 1997 emit_opcode(cbuf,0x0F); 1998 emit_opcode(cbuf,0x6E); 1999 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); 2000 } 2001 { // MOVD $tmp,$src.hi 2002 emit_opcode(cbuf,0x66); 2003 emit_opcode(cbuf,0x0F); 2004 emit_opcode(cbuf,0x6E); 2005 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg)); 2006 } 2007 { // PUNPCKLDQ $dst,$tmp 2008 emit_opcode(cbuf,0x66); 2009 emit_opcode(cbuf,0x0F); 2010 emit_opcode(cbuf,0x62); 2011 emit_rm(cbuf, 0x3, $dst$$reg, $tmp$$reg); 2012 } 2013 %} 2014 2015 enc_class MovXD2L_reg(eRegL dst, regXD src, regXD tmp) %{ 2016 { // MOVD $dst.lo,$src 2017 emit_opcode(cbuf,0x66); 2018 emit_opcode(cbuf,0x0F); 2019 emit_opcode(cbuf,0x7E); 2020 emit_rm(cbuf, 0x3, $src$$reg, $dst$$reg); 2021 } 2022 { // PSHUFLW $tmp,$src,0x4E (01001110b) 2023 emit_opcode(cbuf,0xF2); 2024 emit_opcode(cbuf,0x0F); 2025 emit_opcode(cbuf,0x70); 2026 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg); 2027 emit_d8(cbuf, 0x4E); 2028 } 2029 { // MOVD $dst.hi,$tmp 2030 emit_opcode(cbuf,0x66); 2031 emit_opcode(cbuf,0x0F); 2032 emit_opcode(cbuf,0x7E); 2033 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg)); 2034 } 2035 %} 2036 2037 2038 // Encode a reg-reg copy. If it is useless, then empty encoding. 2039 enc_class enc_Copy( eRegI dst, eRegI src ) %{ 2040 encode_Copy( cbuf, $dst$$reg, $src$$reg ); 2041 %} 2042 2043 enc_class enc_CopyL_Lo( eRegI dst, eRegL src ) %{ 2044 encode_Copy( cbuf, $dst$$reg, $src$$reg ); 2045 %} 2046 2047 // Encode xmm reg-reg copy. If it is useless, then empty encoding. 2048 enc_class enc_CopyXD( RegXD dst, RegXD src ) %{ 2049 encode_CopyXD( cbuf, $dst$$reg, $src$$reg ); 2050 %} 2051 2052 enc_class RegReg (eRegI dst, eRegI src) %{ // RegReg(Many) 2053 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); 2054 %} 2055 2056 enc_class RegReg_Lo(eRegL dst, eRegL src) %{ // RegReg(Many) 2057 $$$emit8$primary; 2058 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); 2059 %} 2060 2061 enc_class RegReg_Hi(eRegL dst, eRegL src) %{ // RegReg(Many) 2062 $$$emit8$secondary; 2063 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg)); 2064 %} 2065 2066 enc_class RegReg_Lo2(eRegL dst, eRegL src) %{ // RegReg(Many) 2067 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); 2068 %} 2069 2070 enc_class RegReg_Hi2(eRegL dst, eRegL src) %{ // RegReg(Many) 2071 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg)); 2072 %} 2073 2074 enc_class RegReg_HiLo( eRegL src, eRegI dst ) %{ 2075 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($src$$reg)); 2076 %} 2077 2078 enc_class Con32 (immI src) %{ // Con32(storeImmI) 2079 // Output immediate 2080 $$$emit32$src$$constant; 2081 %} 2082 2083 enc_class Con32F_as_bits(immF src) %{ // storeF_imm 2084 // Output Float immediate bits 2085 jfloat jf = $src$$constant; 2086 int jf_as_bits = jint_cast( jf ); 2087 emit_d32(cbuf, jf_as_bits); 2088 %} 2089 2090 enc_class Con32XF_as_bits(immXF src) %{ // storeX_imm 2091 // Output Float immediate bits 2092 jfloat jf = $src$$constant; 2093 int jf_as_bits = jint_cast( jf ); 2094 emit_d32(cbuf, jf_as_bits); 2095 %} 2096 2097 enc_class Con16 (immI src) %{ // Con16(storeImmI) 2098 // Output immediate 2099 $$$emit16$src$$constant; 2100 %} 2101 2102 enc_class Con_d32(immI src) %{ 2103 emit_d32(cbuf,$src$$constant); 2104 %} 2105 2106 enc_class conmemref (eRegP t1) %{ // Con32(storeImmI) 2107 // Output immediate memory reference 2108 emit_rm(cbuf, 0x00, $t1$$reg, 0x05 ); 2109 emit_d32(cbuf, 0x00); 2110 %} 2111 2112 enc_class lock_prefix( ) %{ 2113 if( os::is_MP() ) 2114 emit_opcode(cbuf,0xF0); // [Lock] 2115 %} 2116 2117 // Cmp-xchg long value. 2118 // Note: we need to swap rbx, and rcx before and after the 2119 // cmpxchg8 instruction because the instruction uses 2120 // rcx as the high order word of the new value to store but 2121 // our register encoding uses rbx,. 2122 enc_class enc_cmpxchg8(eSIRegP mem_ptr) %{ 2123 2124 // XCHG rbx,ecx 2125 emit_opcode(cbuf,0x87); 2126 emit_opcode(cbuf,0xD9); 2127 // [Lock] 2128 if( os::is_MP() ) 2129 emit_opcode(cbuf,0xF0); 2130 // CMPXCHG8 [Eptr] 2131 emit_opcode(cbuf,0x0F); 2132 emit_opcode(cbuf,0xC7); 2133 emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg ); 2134 // XCHG rbx,ecx 2135 emit_opcode(cbuf,0x87); 2136 emit_opcode(cbuf,0xD9); 2137 %} 2138 2139 enc_class enc_cmpxchg(eSIRegP mem_ptr) %{ 2140 // [Lock] 2141 if( os::is_MP() ) 2142 emit_opcode(cbuf,0xF0); 2143 2144 // CMPXCHG [Eptr] 2145 emit_opcode(cbuf,0x0F); 2146 emit_opcode(cbuf,0xB1); 2147 emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg ); 2148 %} 2149 2150 enc_class enc_flags_ne_to_boolean( iRegI res ) %{ 2151 int res_encoding = $res$$reg; 2152 2153 // MOV res,0 2154 emit_opcode( cbuf, 0xB8 + res_encoding); 2155 emit_d32( cbuf, 0 ); 2156 // JNE,s fail 2157 emit_opcode(cbuf,0x75); 2158 emit_d8(cbuf, 5 ); 2159 // MOV res,1 2160 emit_opcode( cbuf, 0xB8 + res_encoding); 2161 emit_d32( cbuf, 1 ); 2162 // fail: 2163 %} 2164 2165 enc_class set_instruction_start( ) %{ 2166 cbuf.set_inst_mark(); // Mark start of opcode for reloc info in mem operand 2167 %} 2168 2169 enc_class RegMem (eRegI ereg, memory mem) %{ // emit_reg_mem 2170 int reg_encoding = $ereg$$reg; 2171 int base = $mem$$base; 2172 int index = $mem$$index; 2173 int scale = $mem$$scale; 2174 int displace = $mem$$disp; 2175 bool disp_is_oop = $mem->disp_is_oop(); 2176 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop); 2177 %} 2178 2179 enc_class RegMem_Hi(eRegL ereg, memory mem) %{ // emit_reg_mem 2180 int reg_encoding = HIGH_FROM_LOW($ereg$$reg); // Hi register of pair, computed from lo 2181 int base = $mem$$base; 2182 int index = $mem$$index; 2183 int scale = $mem$$scale; 2184 int displace = $mem$$disp + 4; // Offset is 4 further in memory 2185 assert( !$mem->disp_is_oop(), "Cannot add 4 to oop" ); 2186 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, false/*disp_is_oop*/); 2187 %} 2188 2189 enc_class move_long_small_shift( eRegL dst, immI_1_31 cnt ) %{ 2190 int r1, r2; 2191 if( $tertiary == 0xA4 ) { r1 = $dst$$reg; r2 = HIGH_FROM_LOW($dst$$reg); } 2192 else { r2 = $dst$$reg; r1 = HIGH_FROM_LOW($dst$$reg); } 2193 emit_opcode(cbuf,0x0F); 2194 emit_opcode(cbuf,$tertiary); 2195 emit_rm(cbuf, 0x3, r1, r2); 2196 emit_d8(cbuf,$cnt$$constant); 2197 emit_d8(cbuf,$primary); 2198 emit_rm(cbuf, 0x3, $secondary, r1); 2199 emit_d8(cbuf,$cnt$$constant); 2200 %} 2201 2202 enc_class move_long_big_shift_sign( eRegL dst, immI_32_63 cnt ) %{ 2203 emit_opcode( cbuf, 0x8B ); // Move 2204 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg)); 2205 emit_d8(cbuf,$primary); 2206 emit_rm(cbuf, 0x3, $secondary, $dst$$reg); 2207 emit_d8(cbuf,$cnt$$constant-32); 2208 emit_d8(cbuf,$primary); 2209 emit_rm(cbuf, 0x3, $secondary, HIGH_FROM_LOW($dst$$reg)); 2210 emit_d8(cbuf,31); 2211 %} 2212 2213 enc_class move_long_big_shift_clr( eRegL dst, immI_32_63 cnt ) %{ 2214 int r1, r2; 2215 if( $secondary == 0x5 ) { r1 = $dst$$reg; r2 = HIGH_FROM_LOW($dst$$reg); } 2216 else { r2 = $dst$$reg; r1 = HIGH_FROM_LOW($dst$$reg); } 2217 2218 emit_opcode( cbuf, 0x8B ); // Move r1,r2 2219 emit_rm(cbuf, 0x3, r1, r2); 2220 if( $cnt$$constant > 32 ) { // Shift, if not by zero 2221 emit_opcode(cbuf,$primary); 2222 emit_rm(cbuf, 0x3, $secondary, r1); 2223 emit_d8(cbuf,$cnt$$constant-32); 2224 } 2225 emit_opcode(cbuf,0x33); // XOR r2,r2 2226 emit_rm(cbuf, 0x3, r2, r2); 2227 %} 2228 2229 // Clone of RegMem but accepts an extra parameter to access each 2230 // half of a double in memory; it never needs relocation info. 2231 enc_class Mov_MemD_half_to_Reg (immI opcode, memory mem, immI disp_for_half, eRegI rm_reg) %{ 2232 emit_opcode(cbuf,$opcode$$constant); 2233 int reg_encoding = $rm_reg$$reg; 2234 int base = $mem$$base; 2235 int index = $mem$$index; 2236 int scale = $mem$$scale; 2237 int displace = $mem$$disp + $disp_for_half$$constant; 2238 bool disp_is_oop = false; 2239 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop); 2240 %} 2241 2242 // !!!!! Special Custom Code used by MemMove, and stack access instructions !!!!! 2243 // 2244 // Clone of RegMem except the RM-byte's reg/opcode field is an ADLC-time constant 2245 // and it never needs relocation information. 2246 // Frequently used to move data between FPU's Stack Top and memory. 2247 enc_class RMopc_Mem_no_oop (immI rm_opcode, memory mem) %{ 2248 int rm_byte_opcode = $rm_opcode$$constant; 2249 int base = $mem$$base; 2250 int index = $mem$$index; 2251 int scale = $mem$$scale; 2252 int displace = $mem$$disp; 2253 assert( !$mem->disp_is_oop(), "No oops here because no relo info allowed" ); 2254 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, false); 2255 %} 2256 2257 enc_class RMopc_Mem (immI rm_opcode, memory mem) %{ 2258 int rm_byte_opcode = $rm_opcode$$constant; 2259 int base = $mem$$base; 2260 int index = $mem$$index; 2261 int scale = $mem$$scale; 2262 int displace = $mem$$disp; 2263 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals 2264 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_is_oop); 2265 %} 2266 2267 enc_class RegLea (eRegI dst, eRegI src0, immI src1 ) %{ // emit_reg_lea 2268 int reg_encoding = $dst$$reg; 2269 int base = $src0$$reg; // 0xFFFFFFFF indicates no base 2270 int index = 0x04; // 0x04 indicates no index 2271 int scale = 0x00; // 0x00 indicates no scale 2272 int displace = $src1$$constant; // 0x00 indicates no displacement 2273 bool disp_is_oop = false; 2274 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop); 2275 %} 2276 2277 enc_class min_enc (eRegI dst, eRegI src) %{ // MIN 2278 // Compare dst,src 2279 emit_opcode(cbuf,0x3B); 2280 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); 2281 // jmp dst < src around move 2282 emit_opcode(cbuf,0x7C); 2283 emit_d8(cbuf,2); 2284 // move dst,src 2285 emit_opcode(cbuf,0x8B); 2286 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); 2287 %} 2288 2289 enc_class max_enc (eRegI dst, eRegI src) %{ // MAX 2290 // Compare dst,src 2291 emit_opcode(cbuf,0x3B); 2292 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); 2293 // jmp dst > src around move 2294 emit_opcode(cbuf,0x7F); 2295 emit_d8(cbuf,2); 2296 // move dst,src 2297 emit_opcode(cbuf,0x8B); 2298 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); 2299 %} 2300 2301 enc_class enc_FP_store(memory mem, regD src) %{ 2302 // If src is FPR1, we can just FST to store it. 2303 // Else we need to FLD it to FPR1, then FSTP to store/pop it. 2304 int reg_encoding = 0x2; // Just store 2305 int base = $mem$$base; 2306 int index = $mem$$index; 2307 int scale = $mem$$scale; 2308 int displace = $mem$$disp; 2309 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals 2310 if( $src$$reg != FPR1L_enc ) { 2311 reg_encoding = 0x3; // Store & pop 2312 emit_opcode( cbuf, 0xD9 ); // FLD (i.e., push it) 2313 emit_d8( cbuf, 0xC0-1+$src$$reg ); 2314 } 2315 cbuf.set_inst_mark(); // Mark start of opcode for reloc info in mem operand 2316 emit_opcode(cbuf,$primary); 2317 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop); 2318 %} 2319 2320 enc_class neg_reg(eRegI dst) %{ 2321 // NEG $dst 2322 emit_opcode(cbuf,0xF7); 2323 emit_rm(cbuf, 0x3, 0x03, $dst$$reg ); 2324 %} 2325 2326 enc_class setLT_reg(eCXRegI dst) %{ 2327 // SETLT $dst 2328 emit_opcode(cbuf,0x0F); 2329 emit_opcode(cbuf,0x9C); 2330 emit_rm( cbuf, 0x3, 0x4, $dst$$reg ); 2331 %} 2332 2333 enc_class enc_cmpLTP(ncxRegI p, ncxRegI q, ncxRegI y, eCXRegI tmp) %{ // cadd_cmpLT 2334 int tmpReg = $tmp$$reg; 2335 2336 // SUB $p,$q 2337 emit_opcode(cbuf,0x2B); 2338 emit_rm(cbuf, 0x3, $p$$reg, $q$$reg); 2339 // SBB $tmp,$tmp 2340 emit_opcode(cbuf,0x1B); 2341 emit_rm(cbuf, 0x3, tmpReg, tmpReg); 2342 // AND $tmp,$y 2343 emit_opcode(cbuf,0x23); 2344 emit_rm(cbuf, 0x3, tmpReg, $y$$reg); 2345 // ADD $p,$tmp 2346 emit_opcode(cbuf,0x03); 2347 emit_rm(cbuf, 0x3, $p$$reg, tmpReg); 2348 %} 2349 2350 enc_class enc_cmpLTP_mem(eRegI p, eRegI q, memory mem, eCXRegI tmp) %{ // cadd_cmpLT 2351 int tmpReg = $tmp$$reg; 2352 2353 // SUB $p,$q 2354 emit_opcode(cbuf,0x2B); 2355 emit_rm(cbuf, 0x3, $p$$reg, $q$$reg); 2356 // SBB $tmp,$tmp 2357 emit_opcode(cbuf,0x1B); 2358 emit_rm(cbuf, 0x3, tmpReg, tmpReg); 2359 // AND $tmp,$y 2360 cbuf.set_inst_mark(); // Mark start of opcode for reloc info in mem operand 2361 emit_opcode(cbuf,0x23); 2362 int reg_encoding = tmpReg; 2363 int base = $mem$$base; 2364 int index = $mem$$index; 2365 int scale = $mem$$scale; 2366 int displace = $mem$$disp; 2367 bool disp_is_oop = $mem->disp_is_oop(); 2368 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop); 2369 // ADD $p,$tmp 2370 emit_opcode(cbuf,0x03); 2371 emit_rm(cbuf, 0x3, $p$$reg, tmpReg); 2372 %} 2373 2374 enc_class shift_left_long( eRegL dst, eCXRegI shift ) %{ 2375 // TEST shift,32 2376 emit_opcode(cbuf,0xF7); 2377 emit_rm(cbuf, 0x3, 0, ECX_enc); 2378 emit_d32(cbuf,0x20); 2379 // JEQ,s small 2380 emit_opcode(cbuf, 0x74); 2381 emit_d8(cbuf, 0x04); 2382 // MOV $dst.hi,$dst.lo 2383 emit_opcode( cbuf, 0x8B ); 2384 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg ); 2385 // CLR $dst.lo 2386 emit_opcode(cbuf, 0x33); 2387 emit_rm(cbuf, 0x3, $dst$$reg, $dst$$reg); 2388 // small: 2389 // SHLD $dst.hi,$dst.lo,$shift 2390 emit_opcode(cbuf,0x0F); 2391 emit_opcode(cbuf,0xA5); 2392 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg)); 2393 // SHL $dst.lo,$shift" 2394 emit_opcode(cbuf,0xD3); 2395 emit_rm(cbuf, 0x3, 0x4, $dst$$reg ); 2396 %} 2397 2398 enc_class shift_right_long( eRegL dst, eCXRegI shift ) %{ 2399 // TEST shift,32 2400 emit_opcode(cbuf,0xF7); 2401 emit_rm(cbuf, 0x3, 0, ECX_enc); 2402 emit_d32(cbuf,0x20); 2403 // JEQ,s small 2404 emit_opcode(cbuf, 0x74); 2405 emit_d8(cbuf, 0x04); 2406 // MOV $dst.lo,$dst.hi 2407 emit_opcode( cbuf, 0x8B ); 2408 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) ); 2409 // CLR $dst.hi 2410 emit_opcode(cbuf, 0x33); 2411 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($dst$$reg)); 2412 // small: 2413 // SHRD $dst.lo,$dst.hi,$shift 2414 emit_opcode(cbuf,0x0F); 2415 emit_opcode(cbuf,0xAD); 2416 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg); 2417 // SHR $dst.hi,$shift" 2418 emit_opcode(cbuf,0xD3); 2419 emit_rm(cbuf, 0x3, 0x5, HIGH_FROM_LOW($dst$$reg) ); 2420 %} 2421 2422 enc_class shift_right_arith_long( eRegL dst, eCXRegI shift ) %{ 2423 // TEST shift,32 2424 emit_opcode(cbuf,0xF7); 2425 emit_rm(cbuf, 0x3, 0, ECX_enc); 2426 emit_d32(cbuf,0x20); 2427 // JEQ,s small 2428 emit_opcode(cbuf, 0x74); 2429 emit_d8(cbuf, 0x05); 2430 // MOV $dst.lo,$dst.hi 2431 emit_opcode( cbuf, 0x8B ); 2432 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) ); 2433 // SAR $dst.hi,31 2434 emit_opcode(cbuf, 0xC1); 2435 emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW($dst$$reg) ); 2436 emit_d8(cbuf, 0x1F ); 2437 // small: 2438 // SHRD $dst.lo,$dst.hi,$shift 2439 emit_opcode(cbuf,0x0F); 2440 emit_opcode(cbuf,0xAD); 2441 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg); 2442 // SAR $dst.hi,$shift" 2443 emit_opcode(cbuf,0xD3); 2444 emit_rm(cbuf, 0x3, 0x7, HIGH_FROM_LOW($dst$$reg) ); 2445 %} 2446 2447 2448 // ----------------- Encodings for floating point unit ----------------- 2449 // May leave result in FPU-TOS or FPU reg depending on opcodes 2450 enc_class OpcReg_F (regF src) %{ // FMUL, FDIV 2451 $$$emit8$primary; 2452 emit_rm(cbuf, 0x3, $secondary, $src$$reg ); 2453 %} 2454 2455 // Pop argument in FPR0 with FSTP ST(0) 2456 enc_class PopFPU() %{ 2457 emit_opcode( cbuf, 0xDD ); 2458 emit_d8( cbuf, 0xD8 ); 2459 %} 2460 2461 // !!!!! equivalent to Pop_Reg_F 2462 enc_class Pop_Reg_D( regD dst ) %{ 2463 emit_opcode( cbuf, 0xDD ); // FSTP ST(i) 2464 emit_d8( cbuf, 0xD8+$dst$$reg ); 2465 %} 2466 2467 enc_class Push_Reg_D( regD dst ) %{ 2468 emit_opcode( cbuf, 0xD9 ); 2469 emit_d8( cbuf, 0xC0-1+$dst$$reg ); // FLD ST(i-1) 2470 %} 2471 2472 enc_class strictfp_bias1( regD dst ) %{ 2473 emit_opcode( cbuf, 0xDB ); // FLD m80real 2474 emit_opcode( cbuf, 0x2D ); 2475 emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias1() ); 2476 emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0 2477 emit_opcode( cbuf, 0xC8+$dst$$reg ); 2478 %} 2479 2480 enc_class strictfp_bias2( regD dst ) %{ 2481 emit_opcode( cbuf, 0xDB ); // FLD m80real 2482 emit_opcode( cbuf, 0x2D ); 2483 emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias2() ); 2484 emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0 2485 emit_opcode( cbuf, 0xC8+$dst$$reg ); 2486 %} 2487 2488 // Special case for moving an integer register to a stack slot. 2489 enc_class OpcPRegSS( stackSlotI dst, eRegI src ) %{ // RegSS 2490 store_to_stackslot( cbuf, $primary, $src$$reg, $dst$$disp ); 2491 %} 2492 2493 // Special case for moving a register to a stack slot. 2494 enc_class RegSS( stackSlotI dst, eRegI src ) %{ // RegSS 2495 // Opcode already emitted 2496 emit_rm( cbuf, 0x02, $src$$reg, ESP_enc ); // R/M byte 2497 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte 2498 emit_d32(cbuf, $dst$$disp); // Displacement 2499 %} 2500 2501 // Push the integer in stackSlot 'src' onto FP-stack 2502 enc_class Push_Mem_I( memory src ) %{ // FILD [ESP+src] 2503 store_to_stackslot( cbuf, $primary, $secondary, $src$$disp ); 2504 %} 2505 2506 // Push the float in stackSlot 'src' onto FP-stack 2507 enc_class Push_Mem_F( memory src ) %{ // FLD_S [ESP+src] 2508 store_to_stackslot( cbuf, 0xD9, 0x00, $src$$disp ); 2509 %} 2510 2511 // Push the double in stackSlot 'src' onto FP-stack 2512 enc_class Push_Mem_D( memory src ) %{ // FLD_D [ESP+src] 2513 store_to_stackslot( cbuf, 0xDD, 0x00, $src$$disp ); 2514 %} 2515 2516 // Push FPU's TOS float to a stack-slot, and pop FPU-stack 2517 enc_class Pop_Mem_F( stackSlotF dst ) %{ // FSTP_S [ESP+dst] 2518 store_to_stackslot( cbuf, 0xD9, 0x03, $dst$$disp ); 2519 %} 2520 2521 // Same as Pop_Mem_F except for opcode 2522 // Push FPU's TOS double to a stack-slot, and pop FPU-stack 2523 enc_class Pop_Mem_D( stackSlotD dst ) %{ // FSTP_D [ESP+dst] 2524 store_to_stackslot( cbuf, 0xDD, 0x03, $dst$$disp ); 2525 %} 2526 2527 enc_class Pop_Reg_F( regF dst ) %{ 2528 emit_opcode( cbuf, 0xDD ); // FSTP ST(i) 2529 emit_d8( cbuf, 0xD8+$dst$$reg ); 2530 %} 2531 2532 enc_class Push_Reg_F( regF dst ) %{ 2533 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1) 2534 emit_d8( cbuf, 0xC0-1+$dst$$reg ); 2535 %} 2536 2537 // Push FPU's float to a stack-slot, and pop FPU-stack 2538 enc_class Pop_Mem_Reg_F( stackSlotF dst, regF src ) %{ 2539 int pop = 0x02; 2540 if ($src$$reg != FPR1L_enc) { 2541 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1) 2542 emit_d8( cbuf, 0xC0-1+$src$$reg ); 2543 pop = 0x03; 2544 } 2545 store_to_stackslot( cbuf, 0xD9, pop, $dst$$disp ); // FST<P>_S [ESP+dst] 2546 %} 2547 2548 // Push FPU's double to a stack-slot, and pop FPU-stack 2549 enc_class Pop_Mem_Reg_D( stackSlotD dst, regD src ) %{ 2550 int pop = 0x02; 2551 if ($src$$reg != FPR1L_enc) { 2552 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1) 2553 emit_d8( cbuf, 0xC0-1+$src$$reg ); 2554 pop = 0x03; 2555 } 2556 store_to_stackslot( cbuf, 0xDD, pop, $dst$$disp ); // FST<P>_D [ESP+dst] 2557 %} 2558 2559 // Push FPU's double to a FPU-stack-slot, and pop FPU-stack 2560 enc_class Pop_Reg_Reg_D( regD dst, regF src ) %{ 2561 int pop = 0xD0 - 1; // -1 since we skip FLD 2562 if ($src$$reg != FPR1L_enc) { 2563 emit_opcode( cbuf, 0xD9 ); // FLD ST(src-1) 2564 emit_d8( cbuf, 0xC0-1+$src$$reg ); 2565 pop = 0xD8; 2566 } 2567 emit_opcode( cbuf, 0xDD ); 2568 emit_d8( cbuf, pop+$dst$$reg ); // FST<P> ST(i) 2569 %} 2570 2571 2572 enc_class Mul_Add_F( regF dst, regF src, regF src1, regF src2 ) %{ 2573 MacroAssembler masm(&cbuf); 2574 masm.fld_s( $src1$$reg-1); // nothing at TOS, load TOS from src1.reg 2575 masm.fmul( $src2$$reg+0); // value at TOS 2576 masm.fadd( $src$$reg+0); // value at TOS 2577 masm.fstp_d( $dst$$reg+0); // value at TOS, popped off after store 2578 %} 2579 2580 2581 enc_class Push_Reg_Mod_D( regD dst, regD src) %{ 2582 // load dst in FPR0 2583 emit_opcode( cbuf, 0xD9 ); 2584 emit_d8( cbuf, 0xC0-1+$dst$$reg ); 2585 if ($src$$reg != FPR1L_enc) { 2586 // fincstp 2587 emit_opcode (cbuf, 0xD9); 2588 emit_opcode (cbuf, 0xF7); 2589 // swap src with FPR1: 2590 // FXCH FPR1 with src 2591 emit_opcode(cbuf, 0xD9); 2592 emit_d8(cbuf, 0xC8-1+$src$$reg ); 2593 // fdecstp 2594 emit_opcode (cbuf, 0xD9); 2595 emit_opcode (cbuf, 0xF6); 2596 } 2597 %} 2598 2599 enc_class Push_ModD_encoding( regXD src0, regXD src1) %{ 2600 // Allocate a word 2601 emit_opcode(cbuf,0x83); // SUB ESP,8 2602 emit_opcode(cbuf,0xEC); 2603 emit_d8(cbuf,0x08); 2604 2605 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], src1 2606 emit_opcode (cbuf, 0x0F ); 2607 emit_opcode (cbuf, 0x11 ); 2608 encode_RegMem(cbuf, $src1$$reg, ESP_enc, 0x4, 0, 0, false); 2609 2610 emit_opcode(cbuf,0xDD ); // FLD_D [ESP] 2611 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false); 2612 2613 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], src0 2614 emit_opcode (cbuf, 0x0F ); 2615 emit_opcode (cbuf, 0x11 ); 2616 encode_RegMem(cbuf, $src0$$reg, ESP_enc, 0x4, 0, 0, false); 2617 2618 emit_opcode(cbuf,0xDD ); // FLD_D [ESP] 2619 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false); 2620 2621 %} 2622 2623 enc_class Push_ModX_encoding( regX src0, regX src1) %{ 2624 // Allocate a word 2625 emit_opcode(cbuf,0x83); // SUB ESP,4 2626 emit_opcode(cbuf,0xEC); 2627 emit_d8(cbuf,0x04); 2628 2629 emit_opcode (cbuf, 0xF3 ); // MOVSS [ESP], src1 2630 emit_opcode (cbuf, 0x0F ); 2631 emit_opcode (cbuf, 0x11 ); 2632 encode_RegMem(cbuf, $src1$$reg, ESP_enc, 0x4, 0, 0, false); 2633 2634 emit_opcode(cbuf,0xD9 ); // FLD [ESP] 2635 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false); 2636 2637 emit_opcode (cbuf, 0xF3 ); // MOVSS [ESP], src0 2638 emit_opcode (cbuf, 0x0F ); 2639 emit_opcode (cbuf, 0x11 ); 2640 encode_RegMem(cbuf, $src0$$reg, ESP_enc, 0x4, 0, 0, false); 2641 2642 emit_opcode(cbuf,0xD9 ); // FLD [ESP] 2643 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false); 2644 2645 %} 2646 2647 enc_class Push_ResultXD(regXD dst) %{ 2648 store_to_stackslot( cbuf, 0xDD, 0x03, 0 ); //FSTP [ESP] 2649 2650 // UseXmmLoadAndClearUpper ? movsd dst,[esp] : movlpd dst,[esp] 2651 emit_opcode (cbuf, UseXmmLoadAndClearUpper ? 0xF2 : 0x66); 2652 emit_opcode (cbuf, 0x0F ); 2653 emit_opcode (cbuf, UseXmmLoadAndClearUpper ? 0x10 : 0x12); 2654 encode_RegMem(cbuf, $dst$$reg, ESP_enc, 0x4, 0, 0, false); 2655 2656 emit_opcode(cbuf,0x83); // ADD ESP,8 2657 emit_opcode(cbuf,0xC4); 2658 emit_d8(cbuf,0x08); 2659 %} 2660 2661 enc_class Push_ResultX(regX dst, immI d8) %{ 2662 store_to_stackslot( cbuf, 0xD9, 0x03, 0 ); //FSTP_S [ESP] 2663 2664 emit_opcode (cbuf, 0xF3 ); // MOVSS dst(xmm), [ESP] 2665 emit_opcode (cbuf, 0x0F ); 2666 emit_opcode (cbuf, 0x10 ); 2667 encode_RegMem(cbuf, $dst$$reg, ESP_enc, 0x4, 0, 0, false); 2668 2669 emit_opcode(cbuf,0x83); // ADD ESP,d8 (4 or 8) 2670 emit_opcode(cbuf,0xC4); 2671 emit_d8(cbuf,$d8$$constant); 2672 %} 2673 2674 enc_class Push_SrcXD(regXD src) %{ 2675 // Allocate a word 2676 emit_opcode(cbuf,0x83); // SUB ESP,8 2677 emit_opcode(cbuf,0xEC); 2678 emit_d8(cbuf,0x08); 2679 2680 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], src 2681 emit_opcode (cbuf, 0x0F ); 2682 emit_opcode (cbuf, 0x11 ); 2683 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false); 2684 2685 emit_opcode(cbuf,0xDD ); // FLD_D [ESP] 2686 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false); 2687 %} 2688 2689 enc_class push_stack_temp_qword() %{ 2690 emit_opcode(cbuf,0x83); // SUB ESP,8 2691 emit_opcode(cbuf,0xEC); 2692 emit_d8 (cbuf,0x08); 2693 %} 2694 2695 enc_class pop_stack_temp_qword() %{ 2696 emit_opcode(cbuf,0x83); // ADD ESP,8 2697 emit_opcode(cbuf,0xC4); 2698 emit_d8 (cbuf,0x08); 2699 %} 2700 2701 enc_class push_xmm_to_fpr1( regXD xmm_src ) %{ 2702 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], xmm_src 2703 emit_opcode (cbuf, 0x0F ); 2704 emit_opcode (cbuf, 0x11 ); 2705 encode_RegMem(cbuf, $xmm_src$$reg, ESP_enc, 0x4, 0, 0, false); 2706 2707 emit_opcode(cbuf,0xDD ); // FLD_D [ESP] 2708 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false); 2709 %} 2710 2711 // Compute X^Y using Intel's fast hardware instructions, if possible. 2712 // Otherwise return a NaN. 2713 enc_class pow_exp_core_encoding %{ 2714 // FPR1 holds Y*ln2(X). Compute FPR1 = 2^(Y*ln2(X)) 2715 emit_opcode(cbuf,0xD9); emit_opcode(cbuf,0xC0); // fdup = fld st(0) Q Q 2716 emit_opcode(cbuf,0xD9); emit_opcode(cbuf,0xFC); // frndint int(Q) Q 2717 emit_opcode(cbuf,0xDC); emit_opcode(cbuf,0xE9); // fsub st(1) -= st(0); int(Q) frac(Q) 2718 emit_opcode(cbuf,0xDB); // FISTP [ESP] frac(Q) 2719 emit_opcode(cbuf,0x1C); 2720 emit_d8(cbuf,0x24); 2721 emit_opcode(cbuf,0xD9); emit_opcode(cbuf,0xF0); // f2xm1 2^frac(Q)-1 2722 emit_opcode(cbuf,0xD9); emit_opcode(cbuf,0xE8); // fld1 1 2^frac(Q)-1 2723 emit_opcode(cbuf,0xDE); emit_opcode(cbuf,0xC1); // faddp 2^frac(Q) 2724 emit_opcode(cbuf,0x8B); // mov rax,[esp+0]=int(Q) 2725 encode_RegMem(cbuf, EAX_enc, ESP_enc, 0x4, 0, 0, false); 2726 emit_opcode(cbuf,0xC7); // mov rcx,0xFFFFF800 - overflow mask 2727 emit_rm(cbuf, 0x3, 0x0, ECX_enc); 2728 emit_d32(cbuf,0xFFFFF800); 2729 emit_opcode(cbuf,0x81); // add rax,1023 - the double exponent bias 2730 emit_rm(cbuf, 0x3, 0x0, EAX_enc); 2731 emit_d32(cbuf,1023); 2732 emit_opcode(cbuf,0x8B); // mov rbx,eax 2733 emit_rm(cbuf, 0x3, EBX_enc, EAX_enc); 2734 emit_opcode(cbuf,0xC1); // shl rax,20 - Slide to exponent position 2735 emit_rm(cbuf,0x3,0x4,EAX_enc); 2736 emit_d8(cbuf,20); 2737 emit_opcode(cbuf,0x85); // test rbx,ecx - check for overflow 2738 emit_rm(cbuf, 0x3, EBX_enc, ECX_enc); 2739 emit_opcode(cbuf,0x0F); emit_opcode(cbuf,0x45); // CMOVne rax,ecx - overflow; stuff NAN into EAX 2740 emit_rm(cbuf, 0x3, EAX_enc, ECX_enc); 2741 emit_opcode(cbuf,0x89); // mov [esp+4],eax - Store as part of double word 2742 encode_RegMem(cbuf, EAX_enc, ESP_enc, 0x4, 0, 4, false); 2743 emit_opcode(cbuf,0xC7); // mov [esp+0],0 - [ESP] = (double)(1<<int(Q)) = 2^int(Q) 2744 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false); 2745 emit_d32(cbuf,0); 2746 emit_opcode(cbuf,0xDC); // fmul dword st(0),[esp+0]; FPR1 = 2^int(Q)*2^frac(Q) = 2^Q 2747 encode_RegMem(cbuf, 0x1, ESP_enc, 0x4, 0, 0, false); 2748 %} 2749 2750 // enc_class Pop_Reg_Mod_D( regD dst, regD src) 2751 // was replaced by Push_Result_Mod_D followed by Pop_Reg_X() or Pop_Mem_X() 2752 2753 enc_class Push_Result_Mod_D( regD src) %{ 2754 if ($src$$reg != FPR1L_enc) { 2755 // fincstp 2756 emit_opcode (cbuf, 0xD9); 2757 emit_opcode (cbuf, 0xF7); 2758 // FXCH FPR1 with src 2759 emit_opcode(cbuf, 0xD9); 2760 emit_d8(cbuf, 0xC8-1+$src$$reg ); 2761 // fdecstp 2762 emit_opcode (cbuf, 0xD9); 2763 emit_opcode (cbuf, 0xF6); 2764 } 2765 // // following asm replaced with Pop_Reg_F or Pop_Mem_F 2766 // // FSTP FPR$dst$$reg 2767 // emit_opcode( cbuf, 0xDD ); 2768 // emit_d8( cbuf, 0xD8+$dst$$reg ); 2769 %} 2770 2771 enc_class fnstsw_sahf_skip_parity() %{ 2772 // fnstsw ax 2773 emit_opcode( cbuf, 0xDF ); 2774 emit_opcode( cbuf, 0xE0 ); 2775 // sahf 2776 emit_opcode( cbuf, 0x9E ); 2777 // jnp ::skip 2778 emit_opcode( cbuf, 0x7B ); 2779 emit_opcode( cbuf, 0x05 ); 2780 %} 2781 2782 enc_class emitModD() %{ 2783 // fprem must be iterative 2784 // :: loop 2785 // fprem 2786 emit_opcode( cbuf, 0xD9 ); 2787 emit_opcode( cbuf, 0xF8 ); 2788 // wait 2789 emit_opcode( cbuf, 0x9b ); 2790 // fnstsw ax 2791 emit_opcode( cbuf, 0xDF ); 2792 emit_opcode( cbuf, 0xE0 ); 2793 // sahf 2794 emit_opcode( cbuf, 0x9E ); 2795 // jp ::loop 2796 emit_opcode( cbuf, 0x0F ); 2797 emit_opcode( cbuf, 0x8A ); 2798 emit_opcode( cbuf, 0xF4 ); 2799 emit_opcode( cbuf, 0xFF ); 2800 emit_opcode( cbuf, 0xFF ); 2801 emit_opcode( cbuf, 0xFF ); 2802 %} 2803 2804 enc_class fpu_flags() %{ 2805 // fnstsw_ax 2806 emit_opcode( cbuf, 0xDF); 2807 emit_opcode( cbuf, 0xE0); 2808 // test ax,0x0400 2809 emit_opcode( cbuf, 0x66 ); // operand-size prefix for 16-bit immediate 2810 emit_opcode( cbuf, 0xA9 ); 2811 emit_d16 ( cbuf, 0x0400 ); 2812 // // // This sequence works, but stalls for 12-16 cycles on PPro 2813 // // test rax,0x0400 2814 // emit_opcode( cbuf, 0xA9 ); 2815 // emit_d32 ( cbuf, 0x00000400 ); 2816 // 2817 // jz exit (no unordered comparison) 2818 emit_opcode( cbuf, 0x74 ); 2819 emit_d8 ( cbuf, 0x02 ); 2820 // mov ah,1 - treat as LT case (set carry flag) 2821 emit_opcode( cbuf, 0xB4 ); 2822 emit_d8 ( cbuf, 0x01 ); 2823 // sahf 2824 emit_opcode( cbuf, 0x9E); 2825 %} 2826 2827 enc_class cmpF_P6_fixup() %{ 2828 // Fixup the integer flags in case comparison involved a NaN 2829 // 2830 // JNP exit (no unordered comparison, P-flag is set by NaN) 2831 emit_opcode( cbuf, 0x7B ); 2832 emit_d8 ( cbuf, 0x03 ); 2833 // MOV AH,1 - treat as LT case (set carry flag) 2834 emit_opcode( cbuf, 0xB4 ); 2835 emit_d8 ( cbuf, 0x01 ); 2836 // SAHF 2837 emit_opcode( cbuf, 0x9E); 2838 // NOP // target for branch to avoid branch to branch 2839 emit_opcode( cbuf, 0x90); 2840 %} 2841 2842 // fnstsw_ax(); 2843 // sahf(); 2844 // movl(dst, nan_result); 2845 // jcc(Assembler::parity, exit); 2846 // movl(dst, less_result); 2847 // jcc(Assembler::below, exit); 2848 // movl(dst, equal_result); 2849 // jcc(Assembler::equal, exit); 2850 // movl(dst, greater_result); 2851 2852 // less_result = 1; 2853 // greater_result = -1; 2854 // equal_result = 0; 2855 // nan_result = -1; 2856 2857 enc_class CmpF_Result(eRegI dst) %{ 2858 // fnstsw_ax(); 2859 emit_opcode( cbuf, 0xDF); 2860 emit_opcode( cbuf, 0xE0); 2861 // sahf 2862 emit_opcode( cbuf, 0x9E); 2863 // movl(dst, nan_result); 2864 emit_opcode( cbuf, 0xB8 + $dst$$reg); 2865 emit_d32( cbuf, -1 ); 2866 // jcc(Assembler::parity, exit); 2867 emit_opcode( cbuf, 0x7A ); 2868 emit_d8 ( cbuf, 0x13 ); 2869 // movl(dst, less_result); 2870 emit_opcode( cbuf, 0xB8 + $dst$$reg); 2871 emit_d32( cbuf, -1 ); 2872 // jcc(Assembler::below, exit); 2873 emit_opcode( cbuf, 0x72 ); 2874 emit_d8 ( cbuf, 0x0C ); 2875 // movl(dst, equal_result); 2876 emit_opcode( cbuf, 0xB8 + $dst$$reg); 2877 emit_d32( cbuf, 0 ); 2878 // jcc(Assembler::equal, exit); 2879 emit_opcode( cbuf, 0x74 ); 2880 emit_d8 ( cbuf, 0x05 ); 2881 // movl(dst, greater_result); 2882 emit_opcode( cbuf, 0xB8 + $dst$$reg); 2883 emit_d32( cbuf, 1 ); 2884 %} 2885 2886 2887 // XMM version of CmpF_Result. Because the XMM compare 2888 // instructions set the EFLAGS directly. It becomes simpler than 2889 // the float version above. 2890 enc_class CmpX_Result(eRegI dst) %{ 2891 MacroAssembler _masm(&cbuf); 2892 Label nan, inc, done; 2893 2894 __ jccb(Assembler::parity, nan); 2895 __ jccb(Assembler::equal, done); 2896 __ jccb(Assembler::above, inc); 2897 __ bind(nan); 2898 __ decrement(as_Register($dst$$reg)); // NO L qqq 2899 __ jmpb(done); 2900 __ bind(inc); 2901 __ increment(as_Register($dst$$reg)); // NO L qqq 2902 __ bind(done); 2903 %} 2904 2905 // Compare the longs and set flags 2906 // BROKEN! Do Not use as-is 2907 enc_class cmpl_test( eRegL src1, eRegL src2 ) %{ 2908 // CMP $src1.hi,$src2.hi 2909 emit_opcode( cbuf, 0x3B ); 2910 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) ); 2911 // JNE,s done 2912 emit_opcode(cbuf,0x75); 2913 emit_d8(cbuf, 2 ); 2914 // CMP $src1.lo,$src2.lo 2915 emit_opcode( cbuf, 0x3B ); 2916 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg ); 2917 // done: 2918 %} 2919 2920 enc_class convert_int_long( regL dst, eRegI src ) %{ 2921 // mov $dst.lo,$src 2922 int dst_encoding = $dst$$reg; 2923 int src_encoding = $src$$reg; 2924 encode_Copy( cbuf, dst_encoding , src_encoding ); 2925 // mov $dst.hi,$src 2926 encode_Copy( cbuf, HIGH_FROM_LOW(dst_encoding), src_encoding ); 2927 // sar $dst.hi,31 2928 emit_opcode( cbuf, 0xC1 ); 2929 emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW(dst_encoding) ); 2930 emit_d8(cbuf, 0x1F ); 2931 %} 2932 2933 enc_class convert_long_double( eRegL src ) %{ 2934 // push $src.hi 2935 emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg)); 2936 // push $src.lo 2937 emit_opcode(cbuf, 0x50+$src$$reg ); 2938 // fild 64-bits at [SP] 2939 emit_opcode(cbuf,0xdf); 2940 emit_d8(cbuf, 0x6C); 2941 emit_d8(cbuf, 0x24); 2942 emit_d8(cbuf, 0x00); 2943 // pop stack 2944 emit_opcode(cbuf, 0x83); // add SP, #8 2945 emit_rm(cbuf, 0x3, 0x00, ESP_enc); 2946 emit_d8(cbuf, 0x8); 2947 %} 2948 2949 enc_class multiply_con_and_shift_high( eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr ) %{ 2950 // IMUL EDX:EAX,$src1 2951 emit_opcode( cbuf, 0xF7 ); 2952 emit_rm( cbuf, 0x3, 0x5, $src1$$reg ); 2953 // SAR EDX,$cnt-32 2954 int shift_count = ((int)$cnt$$constant) - 32; 2955 if (shift_count > 0) { 2956 emit_opcode(cbuf, 0xC1); 2957 emit_rm(cbuf, 0x3, 7, $dst$$reg ); 2958 emit_d8(cbuf, shift_count); 2959 } 2960 %} 2961 2962 // this version doesn't have add sp, 8 2963 enc_class convert_long_double2( eRegL src ) %{ 2964 // push $src.hi 2965 emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg)); 2966 // push $src.lo 2967 emit_opcode(cbuf, 0x50+$src$$reg ); 2968 // fild 64-bits at [SP] 2969 emit_opcode(cbuf,0xdf); 2970 emit_d8(cbuf, 0x6C); 2971 emit_d8(cbuf, 0x24); 2972 emit_d8(cbuf, 0x00); 2973 %} 2974 2975 enc_class long_int_multiply( eADXRegL dst, nadxRegI src) %{ 2976 // Basic idea: long = (long)int * (long)int 2977 // IMUL EDX:EAX, src 2978 emit_opcode( cbuf, 0xF7 ); 2979 emit_rm( cbuf, 0x3, 0x5, $src$$reg); 2980 %} 2981 2982 enc_class long_uint_multiply( eADXRegL dst, nadxRegI src) %{ 2983 // Basic Idea: long = (int & 0xffffffffL) * (int & 0xffffffffL) 2984 // MUL EDX:EAX, src 2985 emit_opcode( cbuf, 0xF7 ); 2986 emit_rm( cbuf, 0x3, 0x4, $src$$reg); 2987 %} 2988 2989 enc_class long_multiply( eADXRegL dst, eRegL src, eRegI tmp ) %{ 2990 // Basic idea: lo(result) = lo(x_lo * y_lo) 2991 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi) 2992 // MOV $tmp,$src.lo 2993 encode_Copy( cbuf, $tmp$$reg, $src$$reg ); 2994 // IMUL $tmp,EDX 2995 emit_opcode( cbuf, 0x0F ); 2996 emit_opcode( cbuf, 0xAF ); 2997 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) ); 2998 // MOV EDX,$src.hi 2999 encode_Copy( cbuf, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg) ); 3000 // IMUL EDX,EAX 3001 emit_opcode( cbuf, 0x0F ); 3002 emit_opcode( cbuf, 0xAF ); 3003 emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg ); 3004 // ADD $tmp,EDX 3005 emit_opcode( cbuf, 0x03 ); 3006 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) ); 3007 // MUL EDX:EAX,$src.lo 3008 emit_opcode( cbuf, 0xF7 ); 3009 emit_rm( cbuf, 0x3, 0x4, $src$$reg ); 3010 // ADD EDX,ESI 3011 emit_opcode( cbuf, 0x03 ); 3012 emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $tmp$$reg ); 3013 %} 3014 3015 enc_class long_multiply_con( eADXRegL dst, immL_127 src, eRegI tmp ) %{ 3016 // Basic idea: lo(result) = lo(src * y_lo) 3017 // hi(result) = hi(src * y_lo) + lo(src * y_hi) 3018 // IMUL $tmp,EDX,$src 3019 emit_opcode( cbuf, 0x6B ); 3020 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) ); 3021 emit_d8( cbuf, (int)$src$$constant ); 3022 // MOV EDX,$src 3023 emit_opcode(cbuf, 0xB8 + EDX_enc); 3024 emit_d32( cbuf, (int)$src$$constant ); 3025 // MUL EDX:EAX,EDX 3026 emit_opcode( cbuf, 0xF7 ); 3027 emit_rm( cbuf, 0x3, 0x4, EDX_enc ); 3028 // ADD EDX,ESI 3029 emit_opcode( cbuf, 0x03 ); 3030 emit_rm( cbuf, 0x3, EDX_enc, $tmp$$reg ); 3031 %} 3032 3033 enc_class long_div( eRegL src1, eRegL src2 ) %{ 3034 // PUSH src1.hi 3035 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) ); 3036 // PUSH src1.lo 3037 emit_opcode(cbuf, 0x50+$src1$$reg ); 3038 // PUSH src2.hi 3039 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) ); 3040 // PUSH src2.lo 3041 emit_opcode(cbuf, 0x50+$src2$$reg ); 3042 // CALL directly to the runtime 3043 cbuf.set_inst_mark(); 3044 emit_opcode(cbuf,0xE8); // Call into runtime 3045 emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::ldiv) - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 ); 3046 // Restore stack 3047 emit_opcode(cbuf, 0x83); // add SP, #framesize 3048 emit_rm(cbuf, 0x3, 0x00, ESP_enc); 3049 emit_d8(cbuf, 4*4); 3050 %} 3051 3052 enc_class long_mod( eRegL src1, eRegL src2 ) %{ 3053 // PUSH src1.hi 3054 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) ); 3055 // PUSH src1.lo 3056 emit_opcode(cbuf, 0x50+$src1$$reg ); 3057 // PUSH src2.hi 3058 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) ); 3059 // PUSH src2.lo 3060 emit_opcode(cbuf, 0x50+$src2$$reg ); 3061 // CALL directly to the runtime 3062 cbuf.set_inst_mark(); 3063 emit_opcode(cbuf,0xE8); // Call into runtime 3064 emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::lrem ) - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 ); 3065 // Restore stack 3066 emit_opcode(cbuf, 0x83); // add SP, #framesize 3067 emit_rm(cbuf, 0x3, 0x00, ESP_enc); 3068 emit_d8(cbuf, 4*4); 3069 %} 3070 3071 enc_class long_cmp_flags0( eRegL src, eRegI tmp ) %{ 3072 // MOV $tmp,$src.lo 3073 emit_opcode(cbuf, 0x8B); 3074 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg); 3075 // OR $tmp,$src.hi 3076 emit_opcode(cbuf, 0x0B); 3077 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg)); 3078 %} 3079 3080 enc_class long_cmp_flags1( eRegL src1, eRegL src2 ) %{ 3081 // CMP $src1.lo,$src2.lo 3082 emit_opcode( cbuf, 0x3B ); 3083 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg ); 3084 // JNE,s skip 3085 emit_cc(cbuf, 0x70, 0x5); 3086 emit_d8(cbuf,2); 3087 // CMP $src1.hi,$src2.hi 3088 emit_opcode( cbuf, 0x3B ); 3089 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) ); 3090 %} 3091 3092 enc_class long_cmp_flags2( eRegL src1, eRegL src2, eRegI tmp ) %{ 3093 // CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits 3094 emit_opcode( cbuf, 0x3B ); 3095 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg ); 3096 // MOV $tmp,$src1.hi 3097 emit_opcode( cbuf, 0x8B ); 3098 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src1$$reg) ); 3099 // SBB $tmp,$src2.hi\t! Compute flags for long compare 3100 emit_opcode( cbuf, 0x1B ); 3101 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src2$$reg) ); 3102 %} 3103 3104 enc_class long_cmp_flags3( eRegL src, eRegI tmp ) %{ 3105 // XOR $tmp,$tmp 3106 emit_opcode(cbuf,0x33); // XOR 3107 emit_rm(cbuf,0x3, $tmp$$reg, $tmp$$reg); 3108 // CMP $tmp,$src.lo 3109 emit_opcode( cbuf, 0x3B ); 3110 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg ); 3111 // SBB $tmp,$src.hi 3112 emit_opcode( cbuf, 0x1B ); 3113 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg) ); 3114 %} 3115 3116 // Sniff, sniff... smells like Gnu Superoptimizer 3117 enc_class neg_long( eRegL dst ) %{ 3118 emit_opcode(cbuf,0xF7); // NEG hi 3119 emit_rm (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg)); 3120 emit_opcode(cbuf,0xF7); // NEG lo 3121 emit_rm (cbuf,0x3, 0x3, $dst$$reg ); 3122 emit_opcode(cbuf,0x83); // SBB hi,0 3123 emit_rm (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg)); 3124 emit_d8 (cbuf,0 ); 3125 %} 3126 3127 enc_class movq_ld(regXD dst, memory mem) %{ 3128 MacroAssembler _masm(&cbuf); 3129 __ movq($dst$$XMMRegister, $mem$$Address); 3130 %} 3131 3132 enc_class movq_st(memory mem, regXD src) %{ 3133 MacroAssembler _masm(&cbuf); 3134 __ movq($mem$$Address, $src$$XMMRegister); 3135 %} 3136 3137 enc_class pshufd_8x8(regX dst, regX src) %{ 3138 MacroAssembler _masm(&cbuf); 3139 3140 encode_CopyXD(cbuf, $dst$$reg, $src$$reg); 3141 __ punpcklbw(as_XMMRegister($dst$$reg), as_XMMRegister($dst$$reg)); 3142 __ pshuflw(as_XMMRegister($dst$$reg), as_XMMRegister($dst$$reg), 0x00); 3143 %} 3144 3145 enc_class pshufd_4x16(regX dst, regX src) %{ 3146 MacroAssembler _masm(&cbuf); 3147 3148 __ pshuflw(as_XMMRegister($dst$$reg), as_XMMRegister($src$$reg), 0x00); 3149 %} 3150 3151 enc_class pshufd(regXD dst, regXD src, int mode) %{ 3152 MacroAssembler _masm(&cbuf); 3153 3154 __ pshufd(as_XMMRegister($dst$$reg), as_XMMRegister($src$$reg), $mode); 3155 %} 3156 3157 enc_class pxor(regXD dst, regXD src) %{ 3158 MacroAssembler _masm(&cbuf); 3159 3160 __ pxor(as_XMMRegister($dst$$reg), as_XMMRegister($src$$reg)); 3161 %} 3162 3163 enc_class mov_i2x(regXD dst, eRegI src) %{ 3164 MacroAssembler _masm(&cbuf); 3165 3166 __ movdl(as_XMMRegister($dst$$reg), as_Register($src$$reg)); 3167 %} 3168 3169 3170 // Because the transitions from emitted code to the runtime 3171 // monitorenter/exit helper stubs are so slow it's critical that 3172 // we inline both the stack-locking fast-path and the inflated fast path. 3173 // 3174 // See also: cmpFastLock and cmpFastUnlock. 3175 // 3176 // What follows is a specialized inline transliteration of the code 3177 // in slow_enter() and slow_exit(). If we're concerned about I$ bloat 3178 // another option would be to emit TrySlowEnter and TrySlowExit methods 3179 // at startup-time. These methods would accept arguments as 3180 // (rax,=Obj, rbx=Self, rcx=box, rdx=Scratch) and return success-failure 3181 // indications in the icc.ZFlag. Fast_Lock and Fast_Unlock would simply 3182 // marshal the arguments and emit calls to TrySlowEnter and TrySlowExit. 3183 // In practice, however, the # of lock sites is bounded and is usually small. 3184 // Besides the call overhead, TrySlowEnter and TrySlowExit might suffer 3185 // if the processor uses simple bimodal branch predictors keyed by EIP 3186 // Since the helper routines would be called from multiple synchronization 3187 // sites. 3188 // 3189 // An even better approach would be write "MonitorEnter()" and "MonitorExit()" 3190 // in java - using j.u.c and unsafe - and just bind the lock and unlock sites 3191 // to those specialized methods. That'd give us a mostly platform-independent 3192 // implementation that the JITs could optimize and inline at their pleasure. 3193 // Done correctly, the only time we'd need to cross to native could would be 3194 // to park() or unpark() threads. We'd also need a few more unsafe operators 3195 // to (a) prevent compiler-JIT reordering of non-volatile accesses, and 3196 // (b) explicit barriers or fence operations. 3197 // 3198 // TODO: 3199 // 3200 // * Arrange for C2 to pass "Self" into Fast_Lock and Fast_Unlock in one of the registers (scr). 3201 // This avoids manifesting the Self pointer in the Fast_Lock and Fast_Unlock terminals. 3202 // Given TLAB allocation, Self is usually manifested in a register, so passing it into 3203 // the lock operators would typically be faster than reifying Self. 3204 // 3205 // * Ideally I'd define the primitives as: 3206 // fast_lock (nax Obj, nax box, EAX tmp, nax scr) where box, tmp and scr are KILLED. 3207 // fast_unlock (nax Obj, EAX box, nax tmp) where box and tmp are KILLED 3208 // Unfortunately ADLC bugs prevent us from expressing the ideal form. 3209 // Instead, we're stuck with a rather awkward and brittle register assignments below. 3210 // Furthermore the register assignments are overconstrained, possibly resulting in 3211 // sub-optimal code near the synchronization site. 3212 // 3213 // * Eliminate the sp-proximity tests and just use "== Self" tests instead. 3214 // Alternately, use a better sp-proximity test. 3215 // 3216 // * Currently ObjectMonitor._Owner can hold either an sp value or a (THREAD *) value. 3217 // Either one is sufficient to uniquely identify a thread. 3218 // TODO: eliminate use of sp in _owner and use get_thread(tr) instead. 3219 // 3220 // * Intrinsify notify() and notifyAll() for the common cases where the 3221 // object is locked by the calling thread but the waitlist is empty. 3222 // avoid the expensive JNI call to JVM_Notify() and JVM_NotifyAll(). 3223 // 3224 // * use jccb and jmpb instead of jcc and jmp to improve code density. 3225 // But beware of excessive branch density on AMD Opterons. 3226 // 3227 // * Both Fast_Lock and Fast_Unlock set the ICC.ZF to indicate success 3228 // or failure of the fast-path. If the fast-path fails then we pass 3229 // control to the slow-path, typically in C. In Fast_Lock and 3230 // Fast_Unlock we often branch to DONE_LABEL, just to find that C2 3231 // will emit a conditional branch immediately after the node. 3232 // So we have branches to branches and lots of ICC.ZF games. 3233 // Instead, it might be better to have C2 pass a "FailureLabel" 3234 // into Fast_Lock and Fast_Unlock. In the case of success, control 3235 // will drop through the node. ICC.ZF is undefined at exit. 3236 // In the case of failure, the node will branch directly to the 3237 // FailureLabel 3238 3239 3240 // obj: object to lock 3241 // box: on-stack box address (displaced header location) - KILLED 3242 // rax,: tmp -- KILLED 3243 // scr: tmp -- KILLED 3244 enc_class Fast_Lock( eRegP obj, eRegP box, eAXRegI tmp, eRegP scr ) %{ 3245 3246 Register objReg = as_Register($obj$$reg); 3247 Register boxReg = as_Register($box$$reg); 3248 Register tmpReg = as_Register($tmp$$reg); 3249 Register scrReg = as_Register($scr$$reg); 3250 3251 // Ensure the register assignents are disjoint 3252 guarantee (objReg != boxReg, "") ; 3253 guarantee (objReg != tmpReg, "") ; 3254 guarantee (objReg != scrReg, "") ; 3255 guarantee (boxReg != tmpReg, "") ; 3256 guarantee (boxReg != scrReg, "") ; 3257 guarantee (tmpReg == as_Register(EAX_enc), "") ; 3258 3259 MacroAssembler masm(&cbuf); 3260 3261 if (_counters != NULL) { 3262 masm.atomic_incl(ExternalAddress((address) _counters->total_entry_count_addr())); 3263 } 3264 if (EmitSync & 1) { 3265 // set box->dhw = unused_mark (3) 3266 // Force all sync thru slow-path: slow_enter() and slow_exit() 3267 masm.movptr (Address(boxReg, 0), int32_t(markOopDesc::unused_mark())) ; 3268 masm.cmpptr (rsp, (int32_t)0) ; 3269 } else 3270 if (EmitSync & 2) { 3271 Label DONE_LABEL ; 3272 if (UseBiasedLocking) { 3273 // Note: tmpReg maps to the swap_reg argument and scrReg to the tmp_reg argument. 3274 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters); 3275 } 3276 3277 masm.movptr(tmpReg, Address(objReg, 0)) ; // fetch markword 3278 masm.orptr (tmpReg, 0x1); 3279 masm.movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS 3280 if (os::is_MP()) { masm.lock(); } 3281 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg 3282 masm.jcc(Assembler::equal, DONE_LABEL); 3283 // Recursive locking 3284 masm.subptr(tmpReg, rsp); 3285 masm.andptr(tmpReg, (int32_t) 0xFFFFF003 ); 3286 masm.movptr(Address(boxReg, 0), tmpReg); 3287 masm.bind(DONE_LABEL) ; 3288 } else { 3289 // Possible cases that we'll encounter in fast_lock 3290 // ------------------------------------------------ 3291 // * Inflated 3292 // -- unlocked 3293 // -- Locked 3294 // = by self 3295 // = by other 3296 // * biased 3297 // -- by Self 3298 // -- by other 3299 // * neutral 3300 // * stack-locked 3301 // -- by self 3302 // = sp-proximity test hits 3303 // = sp-proximity test generates false-negative 3304 // -- by other 3305 // 3306 3307 Label IsInflated, DONE_LABEL, PopDone ; 3308 3309 // TODO: optimize away redundant LDs of obj->mark and improve the markword triage 3310 // order to reduce the number of conditional branches in the most common cases. 3311 // Beware -- there's a subtle invariant that fetch of the markword 3312 // at [FETCH], below, will never observe a biased encoding (*101b). 3313 // If this invariant is not held we risk exclusion (safety) failure. 3314 if (UseBiasedLocking && !UseOptoBiasInlining) { 3315 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters); 3316 } 3317 3318 masm.movptr(tmpReg, Address(objReg, 0)) ; // [FETCH] 3319 masm.testptr(tmpReg, 0x02) ; // Inflated v (Stack-locked or neutral) 3320 masm.jccb (Assembler::notZero, IsInflated) ; 3321 3322 // Attempt stack-locking ... 3323 masm.orptr (tmpReg, 0x1); 3324 masm.movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS 3325 if (os::is_MP()) { masm.lock(); } 3326 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg 3327 if (_counters != NULL) { 3328 masm.cond_inc32(Assembler::equal, 3329 ExternalAddress((address)_counters->fast_path_entry_count_addr())); 3330 } 3331 masm.jccb (Assembler::equal, DONE_LABEL); 3332 3333 // Recursive locking 3334 masm.subptr(tmpReg, rsp); 3335 masm.andptr(tmpReg, 0xFFFFF003 ); 3336 masm.movptr(Address(boxReg, 0), tmpReg); 3337 if (_counters != NULL) { 3338 masm.cond_inc32(Assembler::equal, 3339 ExternalAddress((address)_counters->fast_path_entry_count_addr())); 3340 } 3341 masm.jmp (DONE_LABEL) ; 3342 3343 masm.bind (IsInflated) ; 3344 3345 // The object is inflated. 3346 // 3347 // TODO-FIXME: eliminate the ugly use of manifest constants: 3348 // Use markOopDesc::monitor_value instead of "2". 3349 // use markOop::unused_mark() instead of "3". 3350 // The tmpReg value is an objectMonitor reference ORed with 3351 // markOopDesc::monitor_value (2). We can either convert tmpReg to an 3352 // objectmonitor pointer by masking off the "2" bit or we can just 3353 // use tmpReg as an objectmonitor pointer but bias the objectmonitor 3354 // field offsets with "-2" to compensate for and annul the low-order tag bit. 3355 // 3356 // I use the latter as it avoids AGI stalls. 3357 // As such, we write "mov r, [tmpReg+OFFSETOF(Owner)-2]" 3358 // instead of "mov r, [tmpReg+OFFSETOF(Owner)]". 3359 // 3360 #define OFFSET_SKEWED(f) ((ObjectMonitor::f ## _offset_in_bytes())-2) 3361 3362 // boxReg refers to the on-stack BasicLock in the current frame. 3363 // We'd like to write: 3364 // set box->_displaced_header = markOop::unused_mark(). Any non-0 value suffices. 3365 // This is convenient but results a ST-before-CAS penalty. The following CAS suffers 3366 // additional latency as we have another ST in the store buffer that must drain. 3367 3368 if (EmitSync & 8192) { 3369 masm.movptr(Address(boxReg, 0), 3) ; // results in ST-before-CAS penalty 3370 masm.get_thread (scrReg) ; 3371 masm.movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2] 3372 masm.movptr(tmpReg, NULL_WORD); // consider: xor vs mov 3373 if (os::is_MP()) { masm.lock(); } 3374 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; 3375 } else 3376 if ((EmitSync & 128) == 0) { // avoid ST-before-CAS 3377 masm.movptr(scrReg, boxReg) ; 3378 masm.movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2] 3379 3380 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes 3381 if ((EmitSync & 2048) && VM_Version::supports_3dnow() && os::is_MP()) { 3382 // prefetchw [eax + Offset(_owner)-2] 3383 masm.prefetchw(Address(rax, ObjectMonitor::owner_offset_in_bytes()-2)); 3384 } 3385 3386 if ((EmitSync & 64) == 0) { 3387 // Optimistic form: consider XORL tmpReg,tmpReg 3388 masm.movptr(tmpReg, NULL_WORD) ; 3389 } else { 3390 // Can suffer RTS->RTO upgrades on shared or cold $ lines 3391 // Test-And-CAS instead of CAS 3392 masm.movptr(tmpReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; // rax, = m->_owner 3393 masm.testptr(tmpReg, tmpReg) ; // Locked ? 3394 masm.jccb (Assembler::notZero, DONE_LABEL) ; 3395 } 3396 3397 // Appears unlocked - try to swing _owner from null to non-null. 3398 // Ideally, I'd manifest "Self" with get_thread and then attempt 3399 // to CAS the register containing Self into m->Owner. 3400 // But we don't have enough registers, so instead we can either try to CAS 3401 // rsp or the address of the box (in scr) into &m->owner. If the CAS succeeds 3402 // we later store "Self" into m->Owner. Transiently storing a stack address 3403 // (rsp or the address of the box) into m->owner is harmless. 3404 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand. 3405 if (os::is_MP()) { masm.lock(); } 3406 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; 3407 masm.movptr(Address(scrReg, 0), 3) ; // box->_displaced_header = 3 3408 masm.jccb (Assembler::notZero, DONE_LABEL) ; 3409 masm.get_thread (scrReg) ; // beware: clobbers ICCs 3410 masm.movptr(Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2), scrReg) ; 3411 masm.xorptr(boxReg, boxReg) ; // set icc.ZFlag = 1 to indicate success 3412 3413 // If the CAS fails we can either retry or pass control to the slow-path. 3414 // We use the latter tactic. 3415 // Pass the CAS result in the icc.ZFlag into DONE_LABEL 3416 // If the CAS was successful ... 3417 // Self has acquired the lock 3418 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it. 3419 // Intentional fall-through into DONE_LABEL ... 3420 } else { 3421 masm.movptr(Address(boxReg, 0), 3) ; // results in ST-before-CAS penalty 3422 masm.movptr(boxReg, tmpReg) ; 3423 3424 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes 3425 if ((EmitSync & 2048) && VM_Version::supports_3dnow() && os::is_MP()) { 3426 // prefetchw [eax + Offset(_owner)-2] 3427 masm.prefetchw(Address(rax, ObjectMonitor::owner_offset_in_bytes()-2)); 3428 } 3429 3430 if ((EmitSync & 64) == 0) { 3431 // Optimistic form 3432 masm.xorptr (tmpReg, tmpReg) ; 3433 } else { 3434 // Can suffer RTS->RTO upgrades on shared or cold $ lines 3435 masm.movptr(tmpReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; // rax, = m->_owner 3436 masm.testptr(tmpReg, tmpReg) ; // Locked ? 3437 masm.jccb (Assembler::notZero, DONE_LABEL) ; 3438 } 3439 3440 // Appears unlocked - try to swing _owner from null to non-null. 3441 // Use either "Self" (in scr) or rsp as thread identity in _owner. 3442 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand. 3443 masm.get_thread (scrReg) ; 3444 if (os::is_MP()) { masm.lock(); } 3445 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; 3446 3447 // If the CAS fails we can either retry or pass control to the slow-path. 3448 // We use the latter tactic. 3449 // Pass the CAS result in the icc.ZFlag into DONE_LABEL 3450 // If the CAS was successful ... 3451 // Self has acquired the lock 3452 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it. 3453 // Intentional fall-through into DONE_LABEL ... 3454 } 3455 3456 // DONE_LABEL is a hot target - we'd really like to place it at the 3457 // start of cache line by padding with NOPs. 3458 // See the AMD and Intel software optimization manuals for the 3459 // most efficient "long" NOP encodings. 3460 // Unfortunately none of our alignment mechanisms suffice. 3461 masm.bind(DONE_LABEL); 3462 3463 // Avoid branch-to-branch on AMD processors 3464 // This appears to be superstition. 3465 if (EmitSync & 32) masm.nop() ; 3466 3467 3468 // At DONE_LABEL the icc ZFlag is set as follows ... 3469 // Fast_Unlock uses the same protocol. 3470 // ZFlag == 1 -> Success 3471 // ZFlag == 0 -> Failure - force control through the slow-path 3472 } 3473 %} 3474 3475 // obj: object to unlock 3476 // box: box address (displaced header location), killed. Must be EAX. 3477 // rbx,: killed tmp; cannot be obj nor box. 3478 // 3479 // Some commentary on balanced locking: 3480 // 3481 // Fast_Lock and Fast_Unlock are emitted only for provably balanced lock sites. 3482 // Methods that don't have provably balanced locking are forced to run in the 3483 // interpreter - such methods won't be compiled to use fast_lock and fast_unlock. 3484 // The interpreter provides two properties: 3485 // I1: At return-time the interpreter automatically and quietly unlocks any 3486 // objects acquired the current activation (frame). Recall that the 3487 // interpreter maintains an on-stack list of locks currently held by 3488 // a frame. 3489 // I2: If a method attempts to unlock an object that is not held by the 3490 // the frame the interpreter throws IMSX. 3491 // 3492 // Lets say A(), which has provably balanced locking, acquires O and then calls B(). 3493 // B() doesn't have provably balanced locking so it runs in the interpreter. 3494 // Control returns to A() and A() unlocks O. By I1 and I2, above, we know that O 3495 // is still locked by A(). 3496 // 3497 // The only other source of unbalanced locking would be JNI. The "Java Native Interface: 3498 // Programmer's Guide and Specification" claims that an object locked by jni_monitorenter 3499 // should not be unlocked by "normal" java-level locking and vice-versa. The specification 3500 // doesn't specify what will occur if a program engages in such mixed-mode locking, however. 3501 3502 enc_class Fast_Unlock( nabxRegP obj, eAXRegP box, eRegP tmp) %{ 3503 3504 Register objReg = as_Register($obj$$reg); 3505 Register boxReg = as_Register($box$$reg); 3506 Register tmpReg = as_Register($tmp$$reg); 3507 3508 guarantee (objReg != boxReg, "") ; 3509 guarantee (objReg != tmpReg, "") ; 3510 guarantee (boxReg != tmpReg, "") ; 3511 guarantee (boxReg == as_Register(EAX_enc), "") ; 3512 MacroAssembler masm(&cbuf); 3513 3514 if (EmitSync & 4) { 3515 // Disable - inhibit all inlining. Force control through the slow-path 3516 masm.cmpptr (rsp, 0) ; 3517 } else 3518 if (EmitSync & 8) { 3519 Label DONE_LABEL ; 3520 if (UseBiasedLocking) { 3521 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL); 3522 } 3523 // classic stack-locking code ... 3524 masm.movptr(tmpReg, Address(boxReg, 0)) ; 3525 masm.testptr(tmpReg, tmpReg) ; 3526 masm.jcc (Assembler::zero, DONE_LABEL) ; 3527 if (os::is_MP()) { masm.lock(); } 3528 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses EAX which is box 3529 masm.bind(DONE_LABEL); 3530 } else { 3531 Label DONE_LABEL, Stacked, CheckSucc, Inflated ; 3532 3533 // Critically, the biased locking test must have precedence over 3534 // and appear before the (box->dhw == 0) recursive stack-lock test. 3535 if (UseBiasedLocking && !UseOptoBiasInlining) { 3536 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL); 3537 } 3538 3539 masm.cmpptr(Address(boxReg, 0), 0) ; // Examine the displaced header 3540 masm.movptr(tmpReg, Address(objReg, 0)) ; // Examine the object's markword 3541 masm.jccb (Assembler::zero, DONE_LABEL) ; // 0 indicates recursive stack-lock 3542 3543 masm.testptr(tmpReg, 0x02) ; // Inflated? 3544 masm.jccb (Assembler::zero, Stacked) ; 3545 3546 masm.bind (Inflated) ; 3547 // It's inflated. 3548 // Despite our balanced locking property we still check that m->_owner == Self 3549 // as java routines or native JNI code called by this thread might 3550 // have released the lock. 3551 // Refer to the comments in synchronizer.cpp for how we might encode extra 3552 // state in _succ so we can avoid fetching EntryList|cxq. 3553 // 3554 // I'd like to add more cases in fast_lock() and fast_unlock() -- 3555 // such as recursive enter and exit -- but we have to be wary of 3556 // I$ bloat, T$ effects and BP$ effects. 3557 // 3558 // If there's no contention try a 1-0 exit. That is, exit without 3559 // a costly MEMBAR or CAS. See synchronizer.cpp for details on how 3560 // we detect and recover from the race that the 1-0 exit admits. 3561 // 3562 // Conceptually Fast_Unlock() must execute a STST|LDST "release" barrier 3563 // before it STs null into _owner, releasing the lock. Updates 3564 // to data protected by the critical section must be visible before 3565 // we drop the lock (and thus before any other thread could acquire 3566 // the lock and observe the fields protected by the lock). 3567 // IA32's memory-model is SPO, so STs are ordered with respect to 3568 // each other and there's no need for an explicit barrier (fence). 3569 // See also http://gee.cs.oswego.edu/dl/jmm/cookbook.html. 3570 3571 masm.get_thread (boxReg) ; 3572 if ((EmitSync & 4096) && VM_Version::supports_3dnow() && os::is_MP()) { 3573 // prefetchw [ebx + Offset(_owner)-2] 3574 masm.prefetchw(Address(rbx, ObjectMonitor::owner_offset_in_bytes()-2)); 3575 } 3576 3577 // Note that we could employ various encoding schemes to reduce 3578 // the number of loads below (currently 4) to just 2 or 3. 3579 // Refer to the comments in synchronizer.cpp. 3580 // In practice the chain of fetches doesn't seem to impact performance, however. 3581 if ((EmitSync & 65536) == 0 && (EmitSync & 256)) { 3582 // Attempt to reduce branch density - AMD's branch predictor. 3583 masm.xorptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; 3584 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ; 3585 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ; 3586 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ; 3587 masm.jccb (Assembler::notZero, DONE_LABEL) ; 3588 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ; 3589 masm.jmpb (DONE_LABEL) ; 3590 } else { 3591 masm.xorptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; 3592 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ; 3593 masm.jccb (Assembler::notZero, DONE_LABEL) ; 3594 masm.movptr(boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ; 3595 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ; 3596 masm.jccb (Assembler::notZero, CheckSucc) ; 3597 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ; 3598 masm.jmpb (DONE_LABEL) ; 3599 } 3600 3601 // The Following code fragment (EmitSync & 65536) improves the performance of 3602 // contended applications and contended synchronization microbenchmarks. 3603 // Unfortunately the emission of the code - even though not executed - causes regressions 3604 // in scimark and jetstream, evidently because of $ effects. Replacing the code 3605 // with an equal number of never-executed NOPs results in the same regression. 3606 // We leave it off by default. 3607 3608 if ((EmitSync & 65536) != 0) { 3609 Label LSuccess, LGoSlowPath ; 3610 3611 masm.bind (CheckSucc) ; 3612 3613 // Optional pre-test ... it's safe to elide this 3614 if ((EmitSync & 16) == 0) { 3615 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), 0) ; 3616 masm.jccb (Assembler::zero, LGoSlowPath) ; 3617 } 3618 3619 // We have a classic Dekker-style idiom: 3620 // ST m->_owner = 0 ; MEMBAR; LD m->_succ 3621 // There are a number of ways to implement the barrier: 3622 // (1) lock:andl &m->_owner, 0 3623 // is fast, but mask doesn't currently support the "ANDL M,IMM32" form. 3624 // LOCK: ANDL [ebx+Offset(_Owner)-2], 0 3625 // Encodes as 81 31 OFF32 IMM32 or 83 63 OFF8 IMM8 3626 // (2) If supported, an explicit MFENCE is appealing. 3627 // In older IA32 processors MFENCE is slower than lock:add or xchg 3628 // particularly if the write-buffer is full as might be the case if 3629 // if stores closely precede the fence or fence-equivalent instruction. 3630 // In more modern implementations MFENCE appears faster, however. 3631 // (3) In lieu of an explicit fence, use lock:addl to the top-of-stack 3632 // The $lines underlying the top-of-stack should be in M-state. 3633 // The locked add instruction is serializing, of course. 3634 // (4) Use xchg, which is serializing 3635 // mov boxReg, 0; xchgl boxReg, [tmpReg + Offset(_owner)-2] also works 3636 // (5) ST m->_owner = 0 and then execute lock:orl &m->_succ, 0. 3637 // The integer condition codes will tell us if succ was 0. 3638 // Since _succ and _owner should reside in the same $line and 3639 // we just stored into _owner, it's likely that the $line 3640 // remains in M-state for the lock:orl. 3641 // 3642 // We currently use (3), although it's likely that switching to (2) 3643 // is correct for the future. 3644 3645 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ; 3646 if (os::is_MP()) { 3647 if (VM_Version::supports_sse2() && 1 == FenceInstruction) { 3648 masm.mfence(); 3649 } else { 3650 masm.lock () ; masm.addptr(Address(rsp, 0), 0) ; 3651 } 3652 } 3653 // Ratify _succ remains non-null 3654 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), 0) ; 3655 masm.jccb (Assembler::notZero, LSuccess) ; 3656 3657 masm.xorptr(boxReg, boxReg) ; // box is really EAX 3658 if (os::is_MP()) { masm.lock(); } 3659 masm.cmpxchgptr(rsp, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)); 3660 masm.jccb (Assembler::notEqual, LSuccess) ; 3661 // Since we're low on registers we installed rsp as a placeholding in _owner. 3662 // Now install Self over rsp. This is safe as we're transitioning from 3663 // non-null to non=null 3664 masm.get_thread (boxReg) ; 3665 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), boxReg) ; 3666 // Intentional fall-through into LGoSlowPath ... 3667 3668 masm.bind (LGoSlowPath) ; 3669 masm.orptr(boxReg, 1) ; // set ICC.ZF=0 to indicate failure 3670 masm.jmpb (DONE_LABEL) ; 3671 3672 masm.bind (LSuccess) ; 3673 masm.xorptr(boxReg, boxReg) ; // set ICC.ZF=1 to indicate success 3674 masm.jmpb (DONE_LABEL) ; 3675 } 3676 3677 masm.bind (Stacked) ; 3678 // It's not inflated and it's not recursively stack-locked and it's not biased. 3679 // It must be stack-locked. 3680 // Try to reset the header to displaced header. 3681 // The "box" value on the stack is stable, so we can reload 3682 // and be assured we observe the same value as above. 3683 masm.movptr(tmpReg, Address(boxReg, 0)) ; 3684 if (os::is_MP()) { masm.lock(); } 3685 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses EAX which is box 3686 // Intention fall-thru into DONE_LABEL 3687 3688 3689 // DONE_LABEL is a hot target - we'd really like to place it at the 3690 // start of cache line by padding with NOPs. 3691 // See the AMD and Intel software optimization manuals for the 3692 // most efficient "long" NOP encodings. 3693 // Unfortunately none of our alignment mechanisms suffice. 3694 if ((EmitSync & 65536) == 0) { 3695 masm.bind (CheckSucc) ; 3696 } 3697 masm.bind(DONE_LABEL); 3698 3699 // Avoid branch to branch on AMD processors 3700 if (EmitSync & 32768) { masm.nop() ; } 3701 } 3702 %} 3703 3704 enc_class enc_String_Compare(eDIRegP str1, eSIRegP str2, regXD tmp1, regXD tmp2, 3705 eAXRegI tmp3, eBXRegI tmp4, eCXRegI result) %{ 3706 Label ECX_GOOD_LABEL, LENGTH_DIFF_LABEL, 3707 POP_LABEL, DONE_LABEL, CONT_LABEL, 3708 WHILE_HEAD_LABEL; 3709 MacroAssembler masm(&cbuf); 3710 3711 XMMRegister tmp1Reg = as_XMMRegister($tmp1$$reg); 3712 XMMRegister tmp2Reg = as_XMMRegister($tmp2$$reg); 3713 3714 // Get the first character position in both strings 3715 // [8] char array, [12] offset, [16] count 3716 int value_offset = java_lang_String::value_offset_in_bytes(); 3717 int offset_offset = java_lang_String::offset_offset_in_bytes(); 3718 int count_offset = java_lang_String::count_offset_in_bytes(); 3719 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR); 3720 3721 masm.movptr(rax, Address(rsi, value_offset)); 3722 masm.movl(rcx, Address(rsi, offset_offset)); 3723 masm.lea(rax, Address(rax, rcx, Address::times_2, base_offset)); 3724 masm.movptr(rbx, Address(rdi, value_offset)); 3725 masm.movl(rcx, Address(rdi, offset_offset)); 3726 masm.lea(rbx, Address(rbx, rcx, Address::times_2, base_offset)); 3727 3728 // Compute the minimum of the string lengths(rsi) and the 3729 // difference of the string lengths (stack) 3730 3731 if (VM_Version::supports_cmov()) { 3732 masm.movl(rdi, Address(rdi, count_offset)); 3733 masm.movl(rsi, Address(rsi, count_offset)); 3734 masm.movl(rcx, rdi); 3735 masm.subl(rdi, rsi); 3736 masm.push(rdi); 3737 masm.cmovl(Assembler::lessEqual, rsi, rcx); 3738 } else { 3739 masm.movl(rdi, Address(rdi, count_offset)); 3740 masm.movl(rcx, Address(rsi, count_offset)); 3741 masm.movl(rsi, rdi); 3742 masm.subl(rdi, rcx); 3743 masm.push(rdi); 3744 masm.jccb(Assembler::lessEqual, ECX_GOOD_LABEL); 3745 masm.movl(rsi, rcx); 3746 // rsi holds min, rcx is unused 3747 } 3748 3749 // Is the minimum length zero? 3750 masm.bind(ECX_GOOD_LABEL); 3751 masm.testl(rsi, rsi); 3752 masm.jcc(Assembler::zero, LENGTH_DIFF_LABEL); 3753 3754 // Load first characters 3755 masm.load_unsigned_short(rcx, Address(rbx, 0)); 3756 masm.load_unsigned_short(rdi, Address(rax, 0)); 3757 3758 // Compare first characters 3759 masm.subl(rcx, rdi); 3760 masm.jcc(Assembler::notZero, POP_LABEL); 3761 masm.decrementl(rsi); 3762 masm.jcc(Assembler::zero, LENGTH_DIFF_LABEL); 3763 3764 { 3765 // Check after comparing first character to see if strings are equivalent 3766 Label LSkip2; 3767 // Check if the strings start at same location 3768 masm.cmpptr(rbx,rax); 3769 masm.jccb(Assembler::notEqual, LSkip2); 3770 3771 // Check if the length difference is zero (from stack) 3772 masm.cmpl(Address(rsp, 0), 0x0); 3773 masm.jcc(Assembler::equal, LENGTH_DIFF_LABEL); 3774 3775 // Strings might not be equivalent 3776 masm.bind(LSkip2); 3777 } 3778 3779 // Advance to next character 3780 masm.addptr(rax, 2); 3781 masm.addptr(rbx, 2); 3782 3783 if (UseSSE42Intrinsics) { 3784 // With SSE4.2, use double quad vector compare 3785 Label COMPARE_VECTORS, VECTOR_NOT_EQUAL, COMPARE_TAIL; 3786 // Setup to compare 16-byte vectors 3787 masm.movl(rdi, rsi); 3788 masm.andl(rsi, 0xfffffff8); // rsi holds the vector count 3789 masm.andl(rdi, 0x00000007); // rdi holds the tail count 3790 masm.testl(rsi, rsi); 3791 masm.jccb(Assembler::zero, COMPARE_TAIL); 3792 3793 masm.lea(rax, Address(rax, rsi, Address::times_2)); 3794 masm.lea(rbx, Address(rbx, rsi, Address::times_2)); 3795 masm.negl(rsi); 3796 3797 masm.bind(COMPARE_VECTORS); 3798 masm.movdqu(tmp1Reg, Address(rax, rsi, Address::times_2)); 3799 masm.movdqu(tmp2Reg, Address(rbx, rsi, Address::times_2)); 3800 masm.pxor(tmp1Reg, tmp2Reg); 3801 masm.ptest(tmp1Reg, tmp1Reg); 3802 masm.jccb(Assembler::notZero, VECTOR_NOT_EQUAL); 3803 masm.addl(rsi, 8); 3804 masm.jcc(Assembler::notZero, COMPARE_VECTORS); 3805 masm.jmpb(COMPARE_TAIL); 3806 3807 // Mismatched characters in the vectors 3808 masm.bind(VECTOR_NOT_EQUAL); 3809 masm.lea(rax, Address(rax, rsi, Address::times_2)); 3810 masm.lea(rbx, Address(rbx, rsi, Address::times_2)); 3811 masm.movl(rdi, 8); 3812 3813 // Compare tail (< 8 chars), or rescan last vectors to 3814 // find 1st mismatched characters 3815 masm.bind(COMPARE_TAIL); 3816 masm.testl(rdi, rdi); 3817 masm.jccb(Assembler::zero, LENGTH_DIFF_LABEL); 3818 masm.movl(rsi, rdi); 3819 // Fallthru to tail compare 3820 } 3821 3822 //Shift rax, and rbx, to the end of the arrays, negate min 3823 masm.lea(rax, Address(rax, rsi, Address::times_2, 0)); 3824 masm.lea(rbx, Address(rbx, rsi, Address::times_2, 0)); 3825 masm.negl(rsi); 3826 3827 // Compare the rest of the characters 3828 masm.bind(WHILE_HEAD_LABEL); 3829 masm.load_unsigned_short(rcx, Address(rbx, rsi, Address::times_2, 0)); 3830 masm.load_unsigned_short(rdi, Address(rax, rsi, Address::times_2, 0)); 3831 masm.subl(rcx, rdi); 3832 masm.jccb(Assembler::notZero, POP_LABEL); 3833 masm.incrementl(rsi); 3834 masm.jcc(Assembler::notZero, WHILE_HEAD_LABEL); 3835 3836 // Strings are equal up to min length. Return the length difference. 3837 masm.bind(LENGTH_DIFF_LABEL); 3838 masm.pop(rcx); 3839 masm.jmpb(DONE_LABEL); 3840 3841 // Discard the stored length difference 3842 masm.bind(POP_LABEL); 3843 masm.addptr(rsp, 4); 3844 3845 // That's it 3846 masm.bind(DONE_LABEL); 3847 %} 3848 3849 enc_class enc_String_Equals(eDIRegP str1, eSIRegP str2, regXD tmp1, regXD tmp2, 3850 eBXRegI tmp3, eCXRegI tmp4, eAXRegI result) %{ 3851 Label RET_TRUE, RET_FALSE, DONE, COMPARE_VECTORS, COMPARE_CHAR; 3852 MacroAssembler masm(&cbuf); 3853 3854 XMMRegister tmp1Reg = as_XMMRegister($tmp1$$reg); 3855 XMMRegister tmp2Reg = as_XMMRegister($tmp2$$reg); 3856 3857 int value_offset = java_lang_String::value_offset_in_bytes(); 3858 int offset_offset = java_lang_String::offset_offset_in_bytes(); 3859 int count_offset = java_lang_String::count_offset_in_bytes(); 3860 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR); 3861 3862 // does source == target string? 3863 masm.cmpptr(rdi, rsi); 3864 masm.jcc(Assembler::equal, RET_TRUE); 3865 3866 // get and compare counts 3867 masm.movl(rcx, Address(rdi, count_offset)); 3868 masm.movl(rax, Address(rsi, count_offset)); 3869 masm.cmpl(rcx, rax); 3870 masm.jcc(Assembler::notEqual, RET_FALSE); 3871 masm.testl(rax, rax); 3872 masm.jcc(Assembler::zero, RET_TRUE); 3873 3874 // get source string offset and value 3875 masm.movptr(rbx, Address(rsi, value_offset)); 3876 masm.movl(rax, Address(rsi, offset_offset)); 3877 masm.leal(rsi, Address(rbx, rax, Address::times_2, base_offset)); 3878 3879 // get compare string offset and value 3880 masm.movptr(rbx, Address(rdi, value_offset)); 3881 masm.movl(rax, Address(rdi, offset_offset)); 3882 masm.leal(rdi, Address(rbx, rax, Address::times_2, base_offset)); 3883 3884 // Set byte count 3885 masm.shll(rcx, 1); 3886 masm.movl(rax, rcx); 3887 3888 if (UseSSE42Intrinsics) { 3889 // With SSE4.2, use double quad vector compare 3890 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL; 3891 // Compare 16-byte vectors 3892 masm.andl(rcx, 0xfffffff0); // vector count (in bytes) 3893 masm.andl(rax, 0x0000000e); // tail count (in bytes) 3894 masm.testl(rcx, rcx); 3895 masm.jccb(Assembler::zero, COMPARE_TAIL); 3896 masm.lea(rdi, Address(rdi, rcx, Address::times_1)); 3897 masm.lea(rsi, Address(rsi, rcx, Address::times_1)); 3898 masm.negl(rcx); 3899 3900 masm.bind(COMPARE_WIDE_VECTORS); 3901 masm.movdqu(tmp1Reg, Address(rdi, rcx, Address::times_1)); 3902 masm.movdqu(tmp2Reg, Address(rsi, rcx, Address::times_1)); 3903 masm.pxor(tmp1Reg, tmp2Reg); 3904 masm.ptest(tmp1Reg, tmp1Reg); 3905 masm.jccb(Assembler::notZero, RET_FALSE); 3906 masm.addl(rcx, 16); 3907 masm.jcc(Assembler::notZero, COMPARE_WIDE_VECTORS); 3908 masm.bind(COMPARE_TAIL); 3909 masm.movl(rcx, rax); 3910 // Fallthru to tail compare 3911 } 3912 3913 // Compare 4-byte vectors 3914 masm.andl(rcx, 0xfffffffc); // vector count (in bytes) 3915 masm.andl(rax, 0x00000002); // tail char (in bytes) 3916 masm.testl(rcx, rcx); 3917 masm.jccb(Assembler::zero, COMPARE_CHAR); 3918 masm.lea(rdi, Address(rdi, rcx, Address::times_1)); 3919 masm.lea(rsi, Address(rsi, rcx, Address::times_1)); 3920 masm.negl(rcx); 3921 3922 masm.bind(COMPARE_VECTORS); 3923 masm.movl(rbx, Address(rdi, rcx, Address::times_1)); 3924 masm.cmpl(rbx, Address(rsi, rcx, Address::times_1)); 3925 masm.jccb(Assembler::notEqual, RET_FALSE); 3926 masm.addl(rcx, 4); 3927 masm.jcc(Assembler::notZero, COMPARE_VECTORS); 3928 3929 // Compare trailing char (final 2 bytes), if any 3930 masm.bind(COMPARE_CHAR); 3931 masm.testl(rax, rax); 3932 masm.jccb(Assembler::zero, RET_TRUE); 3933 masm.load_unsigned_short(rbx, Address(rdi, 0)); 3934 masm.load_unsigned_short(rcx, Address(rsi, 0)); 3935 masm.cmpl(rbx, rcx); 3936 masm.jccb(Assembler::notEqual, RET_FALSE); 3937 3938 masm.bind(RET_TRUE); 3939 masm.movl(rax, 1); // return true 3940 masm.jmpb(DONE); 3941 3942 masm.bind(RET_FALSE); 3943 masm.xorl(rax, rax); // return false 3944 3945 masm.bind(DONE); 3946 %} 3947 3948 enc_class enc_String_IndexOf(eSIRegP str1, eDIRegP str2, regXD tmp1, eAXRegI tmp2, 3949 eCXRegI tmp3, eDXRegI tmp4, eBXRegI result) %{ 3950 // SSE4.2 version 3951 Label LOAD_SUBSTR, PREP_FOR_SCAN, SCAN_TO_SUBSTR, 3952 SCAN_SUBSTR, RET_NEG_ONE, RET_NOT_FOUND, CLEANUP, DONE; 3953 MacroAssembler masm(&cbuf); 3954 3955 XMMRegister tmp1Reg = as_XMMRegister($tmp1$$reg); 3956 3957 // Get the first character position in both strings 3958 // [8] char array, [12] offset, [16] count 3959 int value_offset = java_lang_String::value_offset_in_bytes(); 3960 int offset_offset = java_lang_String::offset_offset_in_bytes(); 3961 int count_offset = java_lang_String::count_offset_in_bytes(); 3962 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR); 3963 3964 // Get counts for string and substr 3965 masm.movl(rdx, Address(rsi, count_offset)); 3966 masm.movl(rax, Address(rdi, count_offset)); 3967 // Check for substr count > string count 3968 masm.cmpl(rax, rdx); 3969 masm.jcc(Assembler::greater, RET_NEG_ONE); 3970 3971 // Start the indexOf operation 3972 // Get start addr of string 3973 masm.movptr(rbx, Address(rsi, value_offset)); 3974 masm.movl(rcx, Address(rsi, offset_offset)); 3975 masm.lea(rsi, Address(rbx, rcx, Address::times_2, base_offset)); 3976 masm.push(rsi); 3977 3978 // Get start addr of substr 3979 masm.movptr(rbx, Address(rdi, value_offset)); 3980 masm.movl(rcx, Address(rdi, offset_offset)); 3981 masm.lea(rdi, Address(rbx, rcx, Address::times_2, base_offset)); 3982 masm.push(rdi); 3983 masm.push(rax); 3984 masm.jmpb(PREP_FOR_SCAN); 3985 3986 // Substr count saved at sp 3987 // Substr saved at sp+4 3988 // String saved at sp+8 3989 3990 // Prep to load substr for scan 3991 masm.bind(LOAD_SUBSTR); 3992 masm.movptr(rdi, Address(rsp, 4)); 3993 masm.movl(rax, Address(rsp, 0)); 3994 3995 // Load substr 3996 masm.bind(PREP_FOR_SCAN); 3997 masm.movdqu(tmp1Reg, Address(rdi, 0)); 3998 masm.addl(rdx, 8); // prime the loop 3999 masm.subptr(rsi, 16); 4000 4001 // Scan string for substr in 16-byte vectors 4002 masm.bind(SCAN_TO_SUBSTR); 4003 masm.subl(rdx, 8); 4004 masm.addptr(rsi, 16); 4005 masm.pcmpestri(tmp1Reg, Address(rsi, 0), 0x0d); 4006 masm.jcc(Assembler::above, SCAN_TO_SUBSTR); // CF == 0 && ZF == 0 4007 masm.jccb(Assembler::aboveEqual, RET_NOT_FOUND); // CF == 0 4008 4009 // Fallthru: found a potential substr 4010 4011 // Make sure string is still long enough 4012 masm.subl(rdx, rcx); 4013 masm.cmpl(rdx, rax); 4014 masm.jccb(Assembler::negative, RET_NOT_FOUND); 4015 // Compute start addr of substr 4016 masm.lea(rsi, Address(rsi, rcx, Address::times_2)); 4017 masm.movptr(rbx, rsi); 4018 4019 // Compare potential substr 4020 masm.addl(rdx, 8); // prime the loop 4021 masm.addl(rax, 8); 4022 masm.subptr(rsi, 16); 4023 masm.subptr(rdi, 16); 4024 4025 // Scan 16-byte vectors of string and substr 4026 masm.bind(SCAN_SUBSTR); 4027 masm.subl(rax, 8); 4028 masm.subl(rdx, 8); 4029 masm.addptr(rsi, 16); 4030 masm.addptr(rdi, 16); 4031 masm.movdqu(tmp1Reg, Address(rdi, 0)); 4032 masm.pcmpestri(tmp1Reg, Address(rsi, 0), 0x0d); 4033 masm.jcc(Assembler::noOverflow, LOAD_SUBSTR); // OF == 0 4034 masm.jcc(Assembler::positive, SCAN_SUBSTR); // SF == 0 4035 4036 // Compute substr offset 4037 masm.movptr(rsi, Address(rsp, 8)); 4038 masm.subptr(rbx, rsi); 4039 masm.shrl(rbx, 1); 4040 masm.jmpb(CLEANUP); 4041 4042 masm.bind(RET_NEG_ONE); 4043 masm.movl(rbx, -1); 4044 masm.jmpb(DONE); 4045 4046 masm.bind(RET_NOT_FOUND); 4047 masm.movl(rbx, -1); 4048 4049 masm.bind(CLEANUP); 4050 masm.addptr(rsp, 12); 4051 4052 masm.bind(DONE); 4053 %} 4054 4055 enc_class enc_Array_Equals(eDIRegP ary1, eSIRegP ary2, regXD tmp1, regXD tmp2, 4056 eBXRegI tmp3, eDXRegI tmp4, eAXRegI result) %{ 4057 Label TRUE_LABEL, FALSE_LABEL, DONE, COMPARE_VECTORS, COMPARE_CHAR; 4058 MacroAssembler masm(&cbuf); 4059 4060 XMMRegister tmp1Reg = as_XMMRegister($tmp1$$reg); 4061 XMMRegister tmp2Reg = as_XMMRegister($tmp2$$reg); 4062 Register ary1Reg = as_Register($ary1$$reg); 4063 Register ary2Reg = as_Register($ary2$$reg); 4064 Register tmp3Reg = as_Register($tmp3$$reg); 4065 Register tmp4Reg = as_Register($tmp4$$reg); 4066 Register resultReg = as_Register($result$$reg); 4067 4068 int length_offset = arrayOopDesc::length_offset_in_bytes(); 4069 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR); 4070 4071 // Check the input args 4072 masm.cmpptr(ary1Reg, ary2Reg); 4073 masm.jcc(Assembler::equal, TRUE_LABEL); 4074 masm.testptr(ary1Reg, ary1Reg); 4075 masm.jcc(Assembler::zero, FALSE_LABEL); 4076 masm.testptr(ary2Reg, ary2Reg); 4077 masm.jcc(Assembler::zero, FALSE_LABEL); 4078 4079 // Check the lengths 4080 masm.movl(tmp4Reg, Address(ary1Reg, length_offset)); 4081 masm.movl(resultReg, Address(ary2Reg, length_offset)); 4082 masm.cmpl(tmp4Reg, resultReg); 4083 masm.jcc(Assembler::notEqual, FALSE_LABEL); 4084 masm.testl(resultReg, resultReg); 4085 masm.jcc(Assembler::zero, TRUE_LABEL); 4086 4087 // Load array addrs 4088 masm.lea(ary1Reg, Address(ary1Reg, base_offset)); 4089 masm.lea(ary2Reg, Address(ary2Reg, base_offset)); 4090 4091 // Set byte count 4092 masm.shll(tmp4Reg, 1); 4093 masm.movl(resultReg, tmp4Reg); 4094 4095 if (UseSSE42Intrinsics) { 4096 // With SSE4.2, use double quad vector compare 4097 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL; 4098 // Compare 16-byte vectors 4099 masm.andl(tmp4Reg, 0xfffffff0); // vector count (in bytes) 4100 masm.andl(resultReg, 0x0000000e); // tail count (in bytes) 4101 masm.testl(tmp4Reg, tmp4Reg); 4102 masm.jccb(Assembler::zero, COMPARE_TAIL); 4103 masm.lea(ary1Reg, Address(ary1Reg, tmp4Reg, Address::times_1)); 4104 masm.lea(ary2Reg, Address(ary2Reg, tmp4Reg, Address::times_1)); 4105 masm.negl(tmp4Reg); 4106 4107 masm.bind(COMPARE_WIDE_VECTORS); 4108 masm.movdqu(tmp1Reg, Address(ary1Reg, tmp4Reg, Address::times_1)); 4109 masm.movdqu(tmp2Reg, Address(ary2Reg, tmp4Reg, Address::times_1)); 4110 masm.pxor(tmp1Reg, tmp2Reg); 4111 masm.ptest(tmp1Reg, tmp1Reg); 4112 4113 masm.jccb(Assembler::notZero, FALSE_LABEL); 4114 masm.addl(tmp4Reg, 16); 4115 masm.jcc(Assembler::notZero, COMPARE_WIDE_VECTORS); 4116 masm.bind(COMPARE_TAIL); 4117 masm.movl(tmp4Reg, resultReg); 4118 // Fallthru to tail compare 4119 } 4120 4121 // Compare 4-byte vectors 4122 masm.andl(tmp4Reg, 0xfffffffc); // vector count (in bytes) 4123 masm.andl(resultReg, 0x00000002); // tail char (in bytes) 4124 masm.testl(tmp4Reg, tmp4Reg); 4125 masm.jccb(Assembler::zero, COMPARE_CHAR); 4126 masm.lea(ary1Reg, Address(ary1Reg, tmp4Reg, Address::times_1)); 4127 masm.lea(ary2Reg, Address(ary2Reg, tmp4Reg, Address::times_1)); 4128 masm.negl(tmp4Reg); 4129 4130 masm.bind(COMPARE_VECTORS); 4131 masm.movl(tmp3Reg, Address(ary1Reg, tmp4Reg, Address::times_1)); 4132 masm.cmpl(tmp3Reg, Address(ary2Reg, tmp4Reg, Address::times_1)); 4133 masm.jccb(Assembler::notEqual, FALSE_LABEL); 4134 masm.addl(tmp4Reg, 4); 4135 masm.jcc(Assembler::notZero, COMPARE_VECTORS); 4136 4137 // Compare trailing char (final 2 bytes), if any 4138 masm.bind(COMPARE_CHAR); 4139 masm.testl(resultReg, resultReg); 4140 masm.jccb(Assembler::zero, TRUE_LABEL); 4141 masm.load_unsigned_short(tmp3Reg, Address(ary1Reg, 0)); 4142 masm.load_unsigned_short(tmp4Reg, Address(ary2Reg, 0)); 4143 masm.cmpl(tmp3Reg, tmp4Reg); 4144 masm.jccb(Assembler::notEqual, FALSE_LABEL); 4145 4146 masm.bind(TRUE_LABEL); 4147 masm.movl(resultReg, 1); // return true 4148 masm.jmpb(DONE); 4149 4150 masm.bind(FALSE_LABEL); 4151 masm.xorl(resultReg, resultReg); // return false 4152 4153 // That's it 4154 masm.bind(DONE); 4155 %} 4156 4157 enc_class enc_pop_rdx() %{ 4158 emit_opcode(cbuf,0x5A); 4159 %} 4160 4161 enc_class enc_rethrow() %{ 4162 cbuf.set_inst_mark(); 4163 emit_opcode(cbuf, 0xE9); // jmp entry 4164 emit_d32_reloc(cbuf, (int)OptoRuntime::rethrow_stub() - ((int)cbuf.code_end())-4, 4165 runtime_call_Relocation::spec(), RELOC_IMM32 ); 4166 %} 4167 4168 4169 // Convert a double to an int. Java semantics require we do complex 4170 // manglelations in the corner cases. So we set the rounding mode to 4171 // 'zero', store the darned double down as an int, and reset the 4172 // rounding mode to 'nearest'. The hardware throws an exception which 4173 // patches up the correct value directly to the stack. 4174 enc_class D2I_encoding( regD src ) %{ 4175 // Flip to round-to-zero mode. We attempted to allow invalid-op 4176 // exceptions here, so that a NAN or other corner-case value will 4177 // thrown an exception (but normal values get converted at full speed). 4178 // However, I2C adapters and other float-stack manglers leave pending 4179 // invalid-op exceptions hanging. We would have to clear them before 4180 // enabling them and that is more expensive than just testing for the 4181 // invalid value Intel stores down in the corner cases. 4182 emit_opcode(cbuf,0xD9); // FLDCW trunc 4183 emit_opcode(cbuf,0x2D); 4184 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc()); 4185 // Allocate a word 4186 emit_opcode(cbuf,0x83); // SUB ESP,4 4187 emit_opcode(cbuf,0xEC); 4188 emit_d8(cbuf,0x04); 4189 // Encoding assumes a double has been pushed into FPR0. 4190 // Store down the double as an int, popping the FPU stack 4191 emit_opcode(cbuf,0xDB); // FISTP [ESP] 4192 emit_opcode(cbuf,0x1C); 4193 emit_d8(cbuf,0x24); 4194 // Restore the rounding mode; mask the exception 4195 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode 4196 emit_opcode(cbuf,0x2D); 4197 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode() 4198 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24() 4199 : (int)StubRoutines::addr_fpu_cntrl_wrd_std()); 4200 4201 // Load the converted int; adjust CPU stack 4202 emit_opcode(cbuf,0x58); // POP EAX 4203 emit_opcode(cbuf,0x3D); // CMP EAX,imm 4204 emit_d32 (cbuf,0x80000000); // 0x80000000 4205 emit_opcode(cbuf,0x75); // JNE around_slow_call 4206 emit_d8 (cbuf,0x07); // Size of slow_call 4207 // Push src onto stack slow-path 4208 emit_opcode(cbuf,0xD9 ); // FLD ST(i) 4209 emit_d8 (cbuf,0xC0-1+$src$$reg ); 4210 // CALL directly to the runtime 4211 cbuf.set_inst_mark(); 4212 emit_opcode(cbuf,0xE8); // Call into runtime 4213 emit_d32_reloc(cbuf, (StubRoutines::d2i_wrapper() - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 ); 4214 // Carry on here... 4215 %} 4216 4217 enc_class D2L_encoding( regD src ) %{ 4218 emit_opcode(cbuf,0xD9); // FLDCW trunc 4219 emit_opcode(cbuf,0x2D); 4220 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc()); 4221 // Allocate a word 4222 emit_opcode(cbuf,0x83); // SUB ESP,8 4223 emit_opcode(cbuf,0xEC); 4224 emit_d8(cbuf,0x08); 4225 // Encoding assumes a double has been pushed into FPR0. 4226 // Store down the double as a long, popping the FPU stack 4227 emit_opcode(cbuf,0xDF); // FISTP [ESP] 4228 emit_opcode(cbuf,0x3C); 4229 emit_d8(cbuf,0x24); 4230 // Restore the rounding mode; mask the exception 4231 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode 4232 emit_opcode(cbuf,0x2D); 4233 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode() 4234 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24() 4235 : (int)StubRoutines::addr_fpu_cntrl_wrd_std()); 4236 4237 // Load the converted int; adjust CPU stack 4238 emit_opcode(cbuf,0x58); // POP EAX 4239 emit_opcode(cbuf,0x5A); // POP EDX 4240 emit_opcode(cbuf,0x81); // CMP EDX,imm 4241 emit_d8 (cbuf,0xFA); // rdx 4242 emit_d32 (cbuf,0x80000000); // 0x80000000 4243 emit_opcode(cbuf,0x75); // JNE around_slow_call 4244 emit_d8 (cbuf,0x07+4); // Size of slow_call 4245 emit_opcode(cbuf,0x85); // TEST EAX,EAX 4246 emit_opcode(cbuf,0xC0); // 2/rax,/rax, 4247 emit_opcode(cbuf,0x75); // JNE around_slow_call 4248 emit_d8 (cbuf,0x07); // Size of slow_call 4249 // Push src onto stack slow-path 4250 emit_opcode(cbuf,0xD9 ); // FLD ST(i) 4251 emit_d8 (cbuf,0xC0-1+$src$$reg ); 4252 // CALL directly to the runtime 4253 cbuf.set_inst_mark(); 4254 emit_opcode(cbuf,0xE8); // Call into runtime 4255 emit_d32_reloc(cbuf, (StubRoutines::d2l_wrapper() - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 ); 4256 // Carry on here... 4257 %} 4258 4259 enc_class X2L_encoding( regX src ) %{ 4260 // Allocate a word 4261 emit_opcode(cbuf,0x83); // SUB ESP,8 4262 emit_opcode(cbuf,0xEC); 4263 emit_d8(cbuf,0x08); 4264 4265 emit_opcode (cbuf, 0xF3 ); // MOVSS [ESP], src 4266 emit_opcode (cbuf, 0x0F ); 4267 emit_opcode (cbuf, 0x11 ); 4268 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false); 4269 4270 emit_opcode(cbuf,0xD9 ); // FLD_S [ESP] 4271 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false); 4272 4273 emit_opcode(cbuf,0xD9); // FLDCW trunc 4274 emit_opcode(cbuf,0x2D); 4275 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc()); 4276 4277 // Encoding assumes a double has been pushed into FPR0. 4278 // Store down the double as a long, popping the FPU stack 4279 emit_opcode(cbuf,0xDF); // FISTP [ESP] 4280 emit_opcode(cbuf,0x3C); 4281 emit_d8(cbuf,0x24); 4282 4283 // Restore the rounding mode; mask the exception 4284 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode 4285 emit_opcode(cbuf,0x2D); 4286 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode() 4287 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24() 4288 : (int)StubRoutines::addr_fpu_cntrl_wrd_std()); 4289 4290 // Load the converted int; adjust CPU stack 4291 emit_opcode(cbuf,0x58); // POP EAX 4292 4293 emit_opcode(cbuf,0x5A); // POP EDX 4294 4295 emit_opcode(cbuf,0x81); // CMP EDX,imm 4296 emit_d8 (cbuf,0xFA); // rdx 4297 emit_d32 (cbuf,0x80000000);// 0x80000000 4298 4299 emit_opcode(cbuf,0x75); // JNE around_slow_call 4300 emit_d8 (cbuf,0x13+4); // Size of slow_call 4301 4302 emit_opcode(cbuf,0x85); // TEST EAX,EAX 4303 emit_opcode(cbuf,0xC0); // 2/rax,/rax, 4304 4305 emit_opcode(cbuf,0x75); // JNE around_slow_call 4306 emit_d8 (cbuf,0x13); // Size of slow_call 4307 4308 // Allocate a word 4309 emit_opcode(cbuf,0x83); // SUB ESP,4 4310 emit_opcode(cbuf,0xEC); 4311 emit_d8(cbuf,0x04); 4312 4313 emit_opcode (cbuf, 0xF3 ); // MOVSS [ESP], src 4314 emit_opcode (cbuf, 0x0F ); 4315 emit_opcode (cbuf, 0x11 ); 4316 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false); 4317 4318 emit_opcode(cbuf,0xD9 ); // FLD_S [ESP] 4319 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false); 4320 4321 emit_opcode(cbuf,0x83); // ADD ESP,4 4322 emit_opcode(cbuf,0xC4); 4323 emit_d8(cbuf,0x04); 4324 4325 // CALL directly to the runtime 4326 cbuf.set_inst_mark(); 4327 emit_opcode(cbuf,0xE8); // Call into runtime 4328 emit_d32_reloc(cbuf, (StubRoutines::d2l_wrapper() - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 ); 4329 // Carry on here... 4330 %} 4331 4332 enc_class XD2L_encoding( regXD src ) %{ 4333 // Allocate a word 4334 emit_opcode(cbuf,0x83); // SUB ESP,8 4335 emit_opcode(cbuf,0xEC); 4336 emit_d8(cbuf,0x08); 4337 4338 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], src 4339 emit_opcode (cbuf, 0x0F ); 4340 emit_opcode (cbuf, 0x11 ); 4341 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false); 4342 4343 emit_opcode(cbuf,0xDD ); // FLD_D [ESP] 4344 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false); 4345 4346 emit_opcode(cbuf,0xD9); // FLDCW trunc 4347 emit_opcode(cbuf,0x2D); 4348 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc()); 4349 4350 // Encoding assumes a double has been pushed into FPR0. 4351 // Store down the double as a long, popping the FPU stack 4352 emit_opcode(cbuf,0xDF); // FISTP [ESP] 4353 emit_opcode(cbuf,0x3C); 4354 emit_d8(cbuf,0x24); 4355 4356 // Restore the rounding mode; mask the exception 4357 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode 4358 emit_opcode(cbuf,0x2D); 4359 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode() 4360 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24() 4361 : (int)StubRoutines::addr_fpu_cntrl_wrd_std()); 4362 4363 // Load the converted int; adjust CPU stack 4364 emit_opcode(cbuf,0x58); // POP EAX 4365 4366 emit_opcode(cbuf,0x5A); // POP EDX 4367 4368 emit_opcode(cbuf,0x81); // CMP EDX,imm 4369 emit_d8 (cbuf,0xFA); // rdx 4370 emit_d32 (cbuf,0x80000000); // 0x80000000 4371 4372 emit_opcode(cbuf,0x75); // JNE around_slow_call 4373 emit_d8 (cbuf,0x13+4); // Size of slow_call 4374 4375 emit_opcode(cbuf,0x85); // TEST EAX,EAX 4376 emit_opcode(cbuf,0xC0); // 2/rax,/rax, 4377 4378 emit_opcode(cbuf,0x75); // JNE around_slow_call 4379 emit_d8 (cbuf,0x13); // Size of slow_call 4380 4381 // Push src onto stack slow-path 4382 // Allocate a word 4383 emit_opcode(cbuf,0x83); // SUB ESP,8 4384 emit_opcode(cbuf,0xEC); 4385 emit_d8(cbuf,0x08); 4386 4387 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], src 4388 emit_opcode (cbuf, 0x0F ); 4389 emit_opcode (cbuf, 0x11 ); 4390 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false); 4391 4392 emit_opcode(cbuf,0xDD ); // FLD_D [ESP] 4393 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false); 4394 4395 emit_opcode(cbuf,0x83); // ADD ESP,8 4396 emit_opcode(cbuf,0xC4); 4397 emit_d8(cbuf,0x08); 4398 4399 // CALL directly to the runtime 4400 cbuf.set_inst_mark(); 4401 emit_opcode(cbuf,0xE8); // Call into runtime 4402 emit_d32_reloc(cbuf, (StubRoutines::d2l_wrapper() - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 ); 4403 // Carry on here... 4404 %} 4405 4406 enc_class D2X_encoding( regX dst, regD src ) %{ 4407 // Allocate a word 4408 emit_opcode(cbuf,0x83); // SUB ESP,4 4409 emit_opcode(cbuf,0xEC); 4410 emit_d8(cbuf,0x04); 4411 int pop = 0x02; 4412 if ($src$$reg != FPR1L_enc) { 4413 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1) 4414 emit_d8( cbuf, 0xC0-1+$src$$reg ); 4415 pop = 0x03; 4416 } 4417 store_to_stackslot( cbuf, 0xD9, pop, 0 ); // FST<P>_S [ESP] 4418 4419 emit_opcode (cbuf, 0xF3 ); // MOVSS dst(xmm), [ESP] 4420 emit_opcode (cbuf, 0x0F ); 4421 emit_opcode (cbuf, 0x10 ); 4422 encode_RegMem(cbuf, $dst$$reg, ESP_enc, 0x4, 0, 0, false); 4423 4424 emit_opcode(cbuf,0x83); // ADD ESP,4 4425 emit_opcode(cbuf,0xC4); 4426 emit_d8(cbuf,0x04); 4427 // Carry on here... 4428 %} 4429 4430 enc_class FX2I_encoding( regX src, eRegI dst ) %{ 4431 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); 4432 4433 // Compare the result to see if we need to go to the slow path 4434 emit_opcode(cbuf,0x81); // CMP dst,imm 4435 emit_rm (cbuf,0x3,0x7,$dst$$reg); 4436 emit_d32 (cbuf,0x80000000); // 0x80000000 4437 4438 emit_opcode(cbuf,0x75); // JNE around_slow_call 4439 emit_d8 (cbuf,0x13); // Size of slow_call 4440 // Store xmm to a temp memory 4441 // location and push it onto stack. 4442 4443 emit_opcode(cbuf,0x83); // SUB ESP,4 4444 emit_opcode(cbuf,0xEC); 4445 emit_d8(cbuf, $primary ? 0x8 : 0x4); 4446 4447 emit_opcode (cbuf, $primary ? 0xF2 : 0xF3 ); // MOVSS [ESP], xmm 4448 emit_opcode (cbuf, 0x0F ); 4449 emit_opcode (cbuf, 0x11 ); 4450 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false); 4451 4452 emit_opcode(cbuf, $primary ? 0xDD : 0xD9 ); // FLD [ESP] 4453 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false); 4454 4455 emit_opcode(cbuf,0x83); // ADD ESP,4 4456 emit_opcode(cbuf,0xC4); 4457 emit_d8(cbuf, $primary ? 0x8 : 0x4); 4458 4459 // CALL directly to the runtime 4460 cbuf.set_inst_mark(); 4461 emit_opcode(cbuf,0xE8); // Call into runtime 4462 emit_d32_reloc(cbuf, (StubRoutines::d2i_wrapper() - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 ); 4463 4464 // Carry on here... 4465 %} 4466 4467 enc_class X2D_encoding( regD dst, regX src ) %{ 4468 // Allocate a word 4469 emit_opcode(cbuf,0x83); // SUB ESP,4 4470 emit_opcode(cbuf,0xEC); 4471 emit_d8(cbuf,0x04); 4472 4473 emit_opcode (cbuf, 0xF3 ); // MOVSS [ESP], xmm 4474 emit_opcode (cbuf, 0x0F ); 4475 emit_opcode (cbuf, 0x11 ); 4476 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false); 4477 4478 emit_opcode(cbuf,0xD9 ); // FLD_S [ESP] 4479 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false); 4480 4481 emit_opcode(cbuf,0x83); // ADD ESP,4 4482 emit_opcode(cbuf,0xC4); 4483 emit_d8(cbuf,0x04); 4484 4485 // Carry on here... 4486 %} 4487 4488 enc_class AbsXF_encoding(regX dst) %{ 4489 address signmask_address=(address)float_signmask_pool; 4490 // andpd:\tANDPS $dst,[signconst] 4491 emit_opcode(cbuf, 0x0F); 4492 emit_opcode(cbuf, 0x54); 4493 emit_rm(cbuf, 0x0, $dst$$reg, 0x5); 4494 emit_d32(cbuf, (int)signmask_address); 4495 %} 4496 4497 enc_class AbsXD_encoding(regXD dst) %{ 4498 address signmask_address=(address)double_signmask_pool; 4499 // andpd:\tANDPD $dst,[signconst] 4500 emit_opcode(cbuf, 0x66); 4501 emit_opcode(cbuf, 0x0F); 4502 emit_opcode(cbuf, 0x54); 4503 emit_rm(cbuf, 0x0, $dst$$reg, 0x5); 4504 emit_d32(cbuf, (int)signmask_address); 4505 %} 4506 4507 enc_class NegXF_encoding(regX dst) %{ 4508 address signmask_address=(address)float_signflip_pool; 4509 // andpd:\tXORPS $dst,[signconst] 4510 emit_opcode(cbuf, 0x0F); 4511 emit_opcode(cbuf, 0x57); 4512 emit_rm(cbuf, 0x0, $dst$$reg, 0x5); 4513 emit_d32(cbuf, (int)signmask_address); 4514 %} 4515 4516 enc_class NegXD_encoding(regXD dst) %{ 4517 address signmask_address=(address)double_signflip_pool; 4518 // andpd:\tXORPD $dst,[signconst] 4519 emit_opcode(cbuf, 0x66); 4520 emit_opcode(cbuf, 0x0F); 4521 emit_opcode(cbuf, 0x57); 4522 emit_rm(cbuf, 0x0, $dst$$reg, 0x5); 4523 emit_d32(cbuf, (int)signmask_address); 4524 %} 4525 4526 enc_class FMul_ST_reg( eRegF src1 ) %{ 4527 // Operand was loaded from memory into fp ST (stack top) 4528 // FMUL ST,$src /* D8 C8+i */ 4529 emit_opcode(cbuf, 0xD8); 4530 emit_opcode(cbuf, 0xC8 + $src1$$reg); 4531 %} 4532 4533 enc_class FAdd_ST_reg( eRegF src2 ) %{ 4534 // FADDP ST,src2 /* D8 C0+i */ 4535 emit_opcode(cbuf, 0xD8); 4536 emit_opcode(cbuf, 0xC0 + $src2$$reg); 4537 //could use FADDP src2,fpST /* DE C0+i */ 4538 %} 4539 4540 enc_class FAddP_reg_ST( eRegF src2 ) %{ 4541 // FADDP src2,ST /* DE C0+i */ 4542 emit_opcode(cbuf, 0xDE); 4543 emit_opcode(cbuf, 0xC0 + $src2$$reg); 4544 %} 4545 4546 enc_class subF_divF_encode( eRegF src1, eRegF src2) %{ 4547 // Operand has been loaded into fp ST (stack top) 4548 // FSUB ST,$src1 4549 emit_opcode(cbuf, 0xD8); 4550 emit_opcode(cbuf, 0xE0 + $src1$$reg); 4551 4552 // FDIV 4553 emit_opcode(cbuf, 0xD8); 4554 emit_opcode(cbuf, 0xF0 + $src2$$reg); 4555 %} 4556 4557 enc_class MulFAddF (eRegF src1, eRegF src2) %{ 4558 // Operand was loaded from memory into fp ST (stack top) 4559 // FADD ST,$src /* D8 C0+i */ 4560 emit_opcode(cbuf, 0xD8); 4561 emit_opcode(cbuf, 0xC0 + $src1$$reg); 4562 4563 // FMUL ST,src2 /* D8 C*+i */ 4564 emit_opcode(cbuf, 0xD8); 4565 emit_opcode(cbuf, 0xC8 + $src2$$reg); 4566 %} 4567 4568 4569 enc_class MulFAddFreverse (eRegF src1, eRegF src2) %{ 4570 // Operand was loaded from memory into fp ST (stack top) 4571 // FADD ST,$src /* D8 C0+i */ 4572 emit_opcode(cbuf, 0xD8); 4573 emit_opcode(cbuf, 0xC0 + $src1$$reg); 4574 4575 // FMULP src2,ST /* DE C8+i */ 4576 emit_opcode(cbuf, 0xDE); 4577 emit_opcode(cbuf, 0xC8 + $src2$$reg); 4578 %} 4579 4580 // Atomically load the volatile long 4581 enc_class enc_loadL_volatile( memory mem, stackSlotL dst ) %{ 4582 emit_opcode(cbuf,0xDF); 4583 int rm_byte_opcode = 0x05; 4584 int base = $mem$$base; 4585 int index = $mem$$index; 4586 int scale = $mem$$scale; 4587 int displace = $mem$$disp; 4588 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals 4589 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_is_oop); 4590 store_to_stackslot( cbuf, 0x0DF, 0x07, $dst$$disp ); 4591 %} 4592 4593 enc_class enc_loadLX_volatile( memory mem, stackSlotL dst, regXD tmp ) %{ 4594 { // Atomic long load 4595 // UseXmmLoadAndClearUpper ? movsd $tmp,$mem : movlpd $tmp,$mem 4596 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0xF2 : 0x66); 4597 emit_opcode(cbuf,0x0F); 4598 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0x10 : 0x12); 4599 int base = $mem$$base; 4600 int index = $mem$$index; 4601 int scale = $mem$$scale; 4602 int displace = $mem$$disp; 4603 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals 4604 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop); 4605 } 4606 { // MOVSD $dst,$tmp ! atomic long store 4607 emit_opcode(cbuf,0xF2); 4608 emit_opcode(cbuf,0x0F); 4609 emit_opcode(cbuf,0x11); 4610 int base = $dst$$base; 4611 int index = $dst$$index; 4612 int scale = $dst$$scale; 4613 int displace = $dst$$disp; 4614 bool disp_is_oop = $dst->disp_is_oop(); // disp-as-oop when working with static globals 4615 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop); 4616 } 4617 %} 4618 4619 enc_class enc_loadLX_reg_volatile( memory mem, eRegL dst, regXD tmp ) %{ 4620 { // Atomic long load 4621 // UseXmmLoadAndClearUpper ? movsd $tmp,$mem : movlpd $tmp,$mem 4622 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0xF2 : 0x66); 4623 emit_opcode(cbuf,0x0F); 4624 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0x10 : 0x12); 4625 int base = $mem$$base; 4626 int index = $mem$$index; 4627 int scale = $mem$$scale; 4628 int displace = $mem$$disp; 4629 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals 4630 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop); 4631 } 4632 { // MOVD $dst.lo,$tmp 4633 emit_opcode(cbuf,0x66); 4634 emit_opcode(cbuf,0x0F); 4635 emit_opcode(cbuf,0x7E); 4636 emit_rm(cbuf, 0x3, $tmp$$reg, $dst$$reg); 4637 } 4638 { // PSRLQ $tmp,32 4639 emit_opcode(cbuf,0x66); 4640 emit_opcode(cbuf,0x0F); 4641 emit_opcode(cbuf,0x73); 4642 emit_rm(cbuf, 0x3, 0x02, $tmp$$reg); 4643 emit_d8(cbuf, 0x20); 4644 } 4645 { // MOVD $dst.hi,$tmp 4646 emit_opcode(cbuf,0x66); 4647 emit_opcode(cbuf,0x0F); 4648 emit_opcode(cbuf,0x7E); 4649 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg)); 4650 } 4651 %} 4652 4653 // Volatile Store Long. Must be atomic, so move it into 4654 // the FP TOS and then do a 64-bit FIST. Has to probe the 4655 // target address before the store (for null-ptr checks) 4656 // so the memory operand is used twice in the encoding. 4657 enc_class enc_storeL_volatile( memory mem, stackSlotL src ) %{ 4658 store_to_stackslot( cbuf, 0x0DF, 0x05, $src$$disp ); 4659 cbuf.set_inst_mark(); // Mark start of FIST in case $mem has an oop 4660 emit_opcode(cbuf,0xDF); 4661 int rm_byte_opcode = 0x07; 4662 int base = $mem$$base; 4663 int index = $mem$$index; 4664 int scale = $mem$$scale; 4665 int displace = $mem$$disp; 4666 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals 4667 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_is_oop); 4668 %} 4669 4670 enc_class enc_storeLX_volatile( memory mem, stackSlotL src, regXD tmp) %{ 4671 { // Atomic long load 4672 // UseXmmLoadAndClearUpper ? movsd $tmp,[$src] : movlpd $tmp,[$src] 4673 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0xF2 : 0x66); 4674 emit_opcode(cbuf,0x0F); 4675 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0x10 : 0x12); 4676 int base = $src$$base; 4677 int index = $src$$index; 4678 int scale = $src$$scale; 4679 int displace = $src$$disp; 4680 bool disp_is_oop = $src->disp_is_oop(); // disp-as-oop when working with static globals 4681 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop); 4682 } 4683 cbuf.set_inst_mark(); // Mark start of MOVSD in case $mem has an oop 4684 { // MOVSD $mem,$tmp ! atomic long store 4685 emit_opcode(cbuf,0xF2); 4686 emit_opcode(cbuf,0x0F); 4687 emit_opcode(cbuf,0x11); 4688 int base = $mem$$base; 4689 int index = $mem$$index; 4690 int scale = $mem$$scale; 4691 int displace = $mem$$disp; 4692 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals 4693 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop); 4694 } 4695 %} 4696 4697 enc_class enc_storeLX_reg_volatile( memory mem, eRegL src, regXD tmp, regXD tmp2) %{ 4698 { // MOVD $tmp,$src.lo 4699 emit_opcode(cbuf,0x66); 4700 emit_opcode(cbuf,0x0F); 4701 emit_opcode(cbuf,0x6E); 4702 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg); 4703 } 4704 { // MOVD $tmp2,$src.hi 4705 emit_opcode(cbuf,0x66); 4706 emit_opcode(cbuf,0x0F); 4707 emit_opcode(cbuf,0x6E); 4708 emit_rm(cbuf, 0x3, $tmp2$$reg, HIGH_FROM_LOW($src$$reg)); 4709 } 4710 { // PUNPCKLDQ $tmp,$tmp2 4711 emit_opcode(cbuf,0x66); 4712 emit_opcode(cbuf,0x0F); 4713 emit_opcode(cbuf,0x62); 4714 emit_rm(cbuf, 0x3, $tmp$$reg, $tmp2$$reg); 4715 } 4716 cbuf.set_inst_mark(); // Mark start of MOVSD in case $mem has an oop 4717 { // MOVSD $mem,$tmp ! atomic long store 4718 emit_opcode(cbuf,0xF2); 4719 emit_opcode(cbuf,0x0F); 4720 emit_opcode(cbuf,0x11); 4721 int base = $mem$$base; 4722 int index = $mem$$index; 4723 int scale = $mem$$scale; 4724 int displace = $mem$$disp; 4725 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals 4726 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop); 4727 } 4728 %} 4729 4730 // Safepoint Poll. This polls the safepoint page, and causes an 4731 // exception if it is not readable. Unfortunately, it kills the condition code 4732 // in the process 4733 // We current use TESTL [spp],EDI 4734 // A better choice might be TESTB [spp + pagesize() - CacheLineSize()],0 4735 4736 enc_class Safepoint_Poll() %{ 4737 cbuf.relocate(cbuf.inst_mark(), relocInfo::poll_type, 0); 4738 emit_opcode(cbuf,0x85); 4739 emit_rm (cbuf, 0x0, 0x7, 0x5); 4740 emit_d32(cbuf, (intptr_t)os::get_polling_page()); 4741 %} 4742 %} 4743 4744 4745 //----------FRAME-------------------------------------------------------------- 4746 // Definition of frame structure and management information. 4747 // 4748 // S T A C K L A Y O U T Allocators stack-slot number 4749 // | (to get allocators register number 4750 // G Owned by | | v add OptoReg::stack0()) 4751 // r CALLER | | 4752 // o | +--------+ pad to even-align allocators stack-slot 4753 // w V | pad0 | numbers; owned by CALLER 4754 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned 4755 // h ^ | in | 5 4756 // | | args | 4 Holes in incoming args owned by SELF 4757 // | | | | 3 4758 // | | +--------+ 4759 // V | | old out| Empty on Intel, window on Sparc 4760 // | old |preserve| Must be even aligned. 4761 // | SP-+--------+----> Matcher::_old_SP, even aligned 4762 // | | in | 3 area for Intel ret address 4763 // Owned by |preserve| Empty on Sparc. 4764 // SELF +--------+ 4765 // | | pad2 | 2 pad to align old SP 4766 // | +--------+ 1 4767 // | | locks | 0 4768 // | +--------+----> OptoReg::stack0(), even aligned 4769 // | | pad1 | 11 pad to align new SP 4770 // | +--------+ 4771 // | | | 10 4772 // | | spills | 9 spills 4773 // V | | 8 (pad0 slot for callee) 4774 // -----------+--------+----> Matcher::_out_arg_limit, unaligned 4775 // ^ | out | 7 4776 // | | args | 6 Holes in outgoing args owned by CALLEE 4777 // Owned by +--------+ 4778 // CALLEE | new out| 6 Empty on Intel, window on Sparc 4779 // | new |preserve| Must be even-aligned. 4780 // | SP-+--------+----> Matcher::_new_SP, even aligned 4781 // | | | 4782 // 4783 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is 4784 // known from SELF's arguments and the Java calling convention. 4785 // Region 6-7 is determined per call site. 4786 // Note 2: If the calling convention leaves holes in the incoming argument 4787 // area, those holes are owned by SELF. Holes in the outgoing area 4788 // are owned by the CALLEE. Holes should not be nessecary in the 4789 // incoming area, as the Java calling convention is completely under 4790 // the control of the AD file. Doubles can be sorted and packed to 4791 // avoid holes. Holes in the outgoing arguments may be nessecary for 4792 // varargs C calling conventions. 4793 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is 4794 // even aligned with pad0 as needed. 4795 // Region 6 is even aligned. Region 6-7 is NOT even aligned; 4796 // region 6-11 is even aligned; it may be padded out more so that 4797 // the region from SP to FP meets the minimum stack alignment. 4798 4799 frame %{ 4800 // What direction does stack grow in (assumed to be same for C & Java) 4801 stack_direction(TOWARDS_LOW); 4802 4803 // These three registers define part of the calling convention 4804 // between compiled code and the interpreter. 4805 inline_cache_reg(EAX); // Inline Cache Register 4806 interpreter_method_oop_reg(EBX); // Method Oop Register when calling interpreter 4807 4808 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset] 4809 cisc_spilling_operand_name(indOffset32); 4810 4811 // Number of stack slots consumed by locking an object 4812 sync_stack_slots(1); 4813 4814 // Compiled code's Frame Pointer 4815 frame_pointer(ESP); 4816 // Interpreter stores its frame pointer in a register which is 4817 // stored to the stack by I2CAdaptors. 4818 // I2CAdaptors convert from interpreted java to compiled java. 4819 interpreter_frame_pointer(EBP); 4820 4821 // Stack alignment requirement 4822 // Alignment size in bytes (128-bit -> 16 bytes) 4823 stack_alignment(StackAlignmentInBytes); 4824 4825 // Number of stack slots between incoming argument block and the start of 4826 // a new frame. The PROLOG must add this many slots to the stack. The 4827 // EPILOG must remove this many slots. Intel needs one slot for 4828 // return address and one for rbp, (must save rbp) 4829 in_preserve_stack_slots(2+VerifyStackAtCalls); 4830 4831 // Number of outgoing stack slots killed above the out_preserve_stack_slots 4832 // for calls to C. Supports the var-args backing area for register parms. 4833 varargs_C_out_slots_killed(0); 4834 4835 // The after-PROLOG location of the return address. Location of 4836 // return address specifies a type (REG or STACK) and a number 4837 // representing the register number (i.e. - use a register name) or 4838 // stack slot. 4839 // Ret Addr is on stack in slot 0 if no locks or verification or alignment. 4840 // Otherwise, it is above the locks and verification slot and alignment word 4841 return_addr(STACK - 1 + 4842 round_to(1+VerifyStackAtCalls+ 4843 Compile::current()->fixed_slots(), 4844 (StackAlignmentInBytes/wordSize))); 4845 4846 // Body of function which returns an integer array locating 4847 // arguments either in registers or in stack slots. Passed an array 4848 // of ideal registers called "sig" and a "length" count. Stack-slot 4849 // offsets are based on outgoing arguments, i.e. a CALLER setting up 4850 // arguments for a CALLEE. Incoming stack arguments are 4851 // automatically biased by the preserve_stack_slots field above. 4852 calling_convention %{ 4853 // No difference between ingoing/outgoing just pass false 4854 SharedRuntime::java_calling_convention(sig_bt, regs, length, false); 4855 %} 4856 4857 4858 // Body of function which returns an integer array locating 4859 // arguments either in registers or in stack slots. Passed an array 4860 // of ideal registers called "sig" and a "length" count. Stack-slot 4861 // offsets are based on outgoing arguments, i.e. a CALLER setting up 4862 // arguments for a CALLEE. Incoming stack arguments are 4863 // automatically biased by the preserve_stack_slots field above. 4864 c_calling_convention %{ 4865 // This is obviously always outgoing 4866 (void) SharedRuntime::c_calling_convention(sig_bt, regs, length); 4867 %} 4868 4869 // Location of C & interpreter return values 4870 c_return_value %{ 4871 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" ); 4872 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num }; 4873 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num }; 4874 4875 // in SSE2+ mode we want to keep the FPU stack clean so pretend 4876 // that C functions return float and double results in XMM0. 4877 if( ideal_reg == Op_RegD && UseSSE>=2 ) 4878 return OptoRegPair(XMM0b_num,XMM0a_num); 4879 if( ideal_reg == Op_RegF && UseSSE>=2 ) 4880 return OptoRegPair(OptoReg::Bad,XMM0a_num); 4881 4882 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]); 4883 %} 4884 4885 // Location of return values 4886 return_value %{ 4887 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" ); 4888 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num }; 4889 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num }; 4890 if( ideal_reg == Op_RegD && UseSSE>=2 ) 4891 return OptoRegPair(XMM0b_num,XMM0a_num); 4892 if( ideal_reg == Op_RegF && UseSSE>=1 ) 4893 return OptoRegPair(OptoReg::Bad,XMM0a_num); 4894 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]); 4895 %} 4896 4897 %} 4898 4899 //----------ATTRIBUTES--------------------------------------------------------- 4900 //----------Operand Attributes------------------------------------------------- 4901 op_attrib op_cost(0); // Required cost attribute 4902 4903 //----------Instruction Attributes--------------------------------------------- 4904 ins_attrib ins_cost(100); // Required cost attribute 4905 ins_attrib ins_size(8); // Required size attribute (in bits) 4906 ins_attrib ins_pc_relative(0); // Required PC Relative flag 4907 ins_attrib ins_short_branch(0); // Required flag: is this instruction a 4908 // non-matching short branch variant of some 4909 // long branch? 4910 ins_attrib ins_alignment(1); // Required alignment attribute (must be a power of 2) 4911 // specifies the alignment that some part of the instruction (not 4912 // necessarily the start) requires. If > 1, a compute_padding() 4913 // function must be provided for the instruction 4914 4915 //----------OPERANDS----------------------------------------------------------- 4916 // Operand definitions must precede instruction definitions for correct parsing 4917 // in the ADLC because operands constitute user defined types which are used in 4918 // instruction definitions. 4919 4920 //----------Simple Operands---------------------------------------------------- 4921 // Immediate Operands 4922 // Integer Immediate 4923 operand immI() %{ 4924 match(ConI); 4925 4926 op_cost(10); 4927 format %{ %} 4928 interface(CONST_INTER); 4929 %} 4930 4931 // Constant for test vs zero 4932 operand immI0() %{ 4933 predicate(n->get_int() == 0); 4934 match(ConI); 4935 4936 op_cost(0); 4937 format %{ %} 4938 interface(CONST_INTER); 4939 %} 4940 4941 // Constant for increment 4942 operand immI1() %{ 4943 predicate(n->get_int() == 1); 4944 match(ConI); 4945 4946 op_cost(0); 4947 format %{ %} 4948 interface(CONST_INTER); 4949 %} 4950 4951 // Constant for decrement 4952 operand immI_M1() %{ 4953 predicate(n->get_int() == -1); 4954 match(ConI); 4955 4956 op_cost(0); 4957 format %{ %} 4958 interface(CONST_INTER); 4959 %} 4960 4961 // Valid scale values for addressing modes 4962 operand immI2() %{ 4963 predicate(0 <= n->get_int() && (n->get_int() <= 3)); 4964 match(ConI); 4965 4966 format %{ %} 4967 interface(CONST_INTER); 4968 %} 4969 4970 operand immI8() %{ 4971 predicate((-128 <= n->get_int()) && (n->get_int() <= 127)); 4972 match(ConI); 4973 4974 op_cost(5); 4975 format %{ %} 4976 interface(CONST_INTER); 4977 %} 4978 4979 operand immI16() %{ 4980 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767)); 4981 match(ConI); 4982 4983 op_cost(10); 4984 format %{ %} 4985 interface(CONST_INTER); 4986 %} 4987 4988 // Constant for long shifts 4989 operand immI_32() %{ 4990 predicate( n->get_int() == 32 ); 4991 match(ConI); 4992 4993 op_cost(0); 4994 format %{ %} 4995 interface(CONST_INTER); 4996 %} 4997 4998 operand immI_1_31() %{ 4999 predicate( n->get_int() >= 1 && n->get_int() <= 31 ); 5000 match(ConI); 5001 5002 op_cost(0); 5003 format %{ %} 5004 interface(CONST_INTER); 5005 %} 5006 5007 operand immI_32_63() %{ 5008 predicate( n->get_int() >= 32 && n->get_int() <= 63 ); 5009 match(ConI); 5010 op_cost(0); 5011 5012 format %{ %} 5013 interface(CONST_INTER); 5014 %} 5015 5016 operand immI_1() %{ 5017 predicate( n->get_int() == 1 ); 5018 match(ConI); 5019 5020 op_cost(0); 5021 format %{ %} 5022 interface(CONST_INTER); 5023 %} 5024 5025 operand immI_2() %{ 5026 predicate( n->get_int() == 2 ); 5027 match(ConI); 5028 5029 op_cost(0); 5030 format %{ %} 5031 interface(CONST_INTER); 5032 %} 5033 5034 operand immI_3() %{ 5035 predicate( n->get_int() == 3 ); 5036 match(ConI); 5037 5038 op_cost(0); 5039 format %{ %} 5040 interface(CONST_INTER); 5041 %} 5042 5043 // Pointer Immediate 5044 operand immP() %{ 5045 match(ConP); 5046 5047 op_cost(10); 5048 format %{ %} 5049 interface(CONST_INTER); 5050 %} 5051 5052 // NULL Pointer Immediate 5053 operand immP0() %{ 5054 predicate( n->get_ptr() == 0 ); 5055 match(ConP); 5056 op_cost(0); 5057 5058 format %{ %} 5059 interface(CONST_INTER); 5060 %} 5061 5062 // Long Immediate 5063 operand immL() %{ 5064 match(ConL); 5065 5066 op_cost(20); 5067 format %{ %} 5068 interface(CONST_INTER); 5069 %} 5070 5071 // Long Immediate zero 5072 operand immL0() %{ 5073 predicate( n->get_long() == 0L ); 5074 match(ConL); 5075 op_cost(0); 5076 5077 format %{ %} 5078 interface(CONST_INTER); 5079 %} 5080 5081 // Long Immediate zero 5082 operand immL_M1() %{ 5083 predicate( n->get_long() == -1L ); 5084 match(ConL); 5085 op_cost(0); 5086 5087 format %{ %} 5088 interface(CONST_INTER); 5089 %} 5090 5091 // Long immediate from 0 to 127. 5092 // Used for a shorter form of long mul by 10. 5093 operand immL_127() %{ 5094 predicate((0 <= n->get_long()) && (n->get_long() <= 127)); 5095 match(ConL); 5096 op_cost(0); 5097 5098 format %{ %} 5099 interface(CONST_INTER); 5100 %} 5101 5102 // Long Immediate: low 32-bit mask 5103 operand immL_32bits() %{ 5104 predicate(n->get_long() == 0xFFFFFFFFL); 5105 match(ConL); 5106 op_cost(0); 5107 5108 format %{ %} 5109 interface(CONST_INTER); 5110 %} 5111 5112 // Long Immediate: low 32-bit mask 5113 operand immL32() %{ 5114 predicate(n->get_long() == (int)(n->get_long())); 5115 match(ConL); 5116 op_cost(20); 5117 5118 format %{ %} 5119 interface(CONST_INTER); 5120 %} 5121 5122 //Double Immediate zero 5123 operand immD0() %{ 5124 // Do additional (and counter-intuitive) test against NaN to work around VC++ 5125 // bug that generates code such that NaNs compare equal to 0.0 5126 predicate( UseSSE<=1 && n->getd() == 0.0 && !g_isnan(n->getd()) ); 5127 match(ConD); 5128 5129 op_cost(5); 5130 format %{ %} 5131 interface(CONST_INTER); 5132 %} 5133 5134 // Double Immediate 5135 operand immD1() %{ 5136 predicate( UseSSE<=1 && n->getd() == 1.0 ); 5137 match(ConD); 5138 5139 op_cost(5); 5140 format %{ %} 5141 interface(CONST_INTER); 5142 %} 5143 5144 // Double Immediate 5145 operand immD() %{ 5146 predicate(UseSSE<=1); 5147 match(ConD); 5148 5149 op_cost(5); 5150 format %{ %} 5151 interface(CONST_INTER); 5152 %} 5153 5154 operand immXD() %{ 5155 predicate(UseSSE>=2); 5156 match(ConD); 5157 5158 op_cost(5); 5159 format %{ %} 5160 interface(CONST_INTER); 5161 %} 5162 5163 // Double Immediate zero 5164 operand immXD0() %{ 5165 // Do additional (and counter-intuitive) test against NaN to work around VC++ 5166 // bug that generates code such that NaNs compare equal to 0.0 AND do not 5167 // compare equal to -0.0. 5168 predicate( UseSSE>=2 && jlong_cast(n->getd()) == 0 ); 5169 match(ConD); 5170 5171 format %{ %} 5172 interface(CONST_INTER); 5173 %} 5174 5175 // Float Immediate zero 5176 operand immF0() %{ 5177 predicate( UseSSE == 0 && n->getf() == 0.0 ); 5178 match(ConF); 5179 5180 op_cost(5); 5181 format %{ %} 5182 interface(CONST_INTER); 5183 %} 5184 5185 // Float Immediate 5186 operand immF() %{ 5187 predicate( UseSSE == 0 ); 5188 match(ConF); 5189 5190 op_cost(5); 5191 format %{ %} 5192 interface(CONST_INTER); 5193 %} 5194 5195 // Float Immediate 5196 operand immXF() %{ 5197 predicate(UseSSE >= 1); 5198 match(ConF); 5199 5200 op_cost(5); 5201 format %{ %} 5202 interface(CONST_INTER); 5203 %} 5204 5205 // Float Immediate zero. Zero and not -0.0 5206 operand immXF0() %{ 5207 predicate( UseSSE >= 1 && jint_cast(n->getf()) == 0 ); 5208 match(ConF); 5209 5210 op_cost(5); 5211 format %{ %} 5212 interface(CONST_INTER); 5213 %} 5214 5215 // Immediates for special shifts (sign extend) 5216 5217 // Constants for increment 5218 operand immI_16() %{ 5219 predicate( n->get_int() == 16 ); 5220 match(ConI); 5221 5222 format %{ %} 5223 interface(CONST_INTER); 5224 %} 5225 5226 operand immI_24() %{ 5227 predicate( n->get_int() == 24 ); 5228 match(ConI); 5229 5230 format %{ %} 5231 interface(CONST_INTER); 5232 %} 5233 5234 // Constant for byte-wide masking 5235 operand immI_255() %{ 5236 predicate( n->get_int() == 255 ); 5237 match(ConI); 5238 5239 format %{ %} 5240 interface(CONST_INTER); 5241 %} 5242 5243 // Register Operands 5244 // Integer Register 5245 operand eRegI() %{ 5246 constraint(ALLOC_IN_RC(e_reg)); 5247 match(RegI); 5248 match(xRegI); 5249 match(eAXRegI); 5250 match(eBXRegI); 5251 match(eCXRegI); 5252 match(eDXRegI); 5253 match(eDIRegI); 5254 match(eSIRegI); 5255 5256 format %{ %} 5257 interface(REG_INTER); 5258 %} 5259 5260 // Subset of Integer Register 5261 operand xRegI(eRegI reg) %{ 5262 constraint(ALLOC_IN_RC(x_reg)); 5263 match(reg); 5264 match(eAXRegI); 5265 match(eBXRegI); 5266 match(eCXRegI); 5267 match(eDXRegI); 5268 5269 format %{ %} 5270 interface(REG_INTER); 5271 %} 5272 5273 // Special Registers 5274 operand eAXRegI(xRegI reg) %{ 5275 constraint(ALLOC_IN_RC(eax_reg)); 5276 match(reg); 5277 match(eRegI); 5278 5279 format %{ "EAX" %} 5280 interface(REG_INTER); 5281 %} 5282 5283 // Special Registers 5284 operand eBXRegI(xRegI reg) %{ 5285 constraint(ALLOC_IN_RC(ebx_reg)); 5286 match(reg); 5287 match(eRegI); 5288 5289 format %{ "EBX" %} 5290 interface(REG_INTER); 5291 %} 5292 5293 operand eCXRegI(xRegI reg) %{ 5294 constraint(ALLOC_IN_RC(ecx_reg)); 5295 match(reg); 5296 match(eRegI); 5297 5298 format %{ "ECX" %} 5299 interface(REG_INTER); 5300 %} 5301 5302 operand eDXRegI(xRegI reg) %{ 5303 constraint(ALLOC_IN_RC(edx_reg)); 5304 match(reg); 5305 match(eRegI); 5306 5307 format %{ "EDX" %} 5308 interface(REG_INTER); 5309 %} 5310 5311 operand eDIRegI(xRegI reg) %{ 5312 constraint(ALLOC_IN_RC(edi_reg)); 5313 match(reg); 5314 match(eRegI); 5315 5316 format %{ "EDI" %} 5317 interface(REG_INTER); 5318 %} 5319 5320 operand naxRegI() %{ 5321 constraint(ALLOC_IN_RC(nax_reg)); 5322 match(RegI); 5323 match(eCXRegI); 5324 match(eDXRegI); 5325 match(eSIRegI); 5326 match(eDIRegI); 5327 5328 format %{ %} 5329 interface(REG_INTER); 5330 %} 5331 5332 operand nadxRegI() %{ 5333 constraint(ALLOC_IN_RC(nadx_reg)); 5334 match(RegI); 5335 match(eBXRegI); 5336 match(eCXRegI); 5337 match(eSIRegI); 5338 match(eDIRegI); 5339 5340 format %{ %} 5341 interface(REG_INTER); 5342 %} 5343 5344 operand ncxRegI() %{ 5345 constraint(ALLOC_IN_RC(ncx_reg)); 5346 match(RegI); 5347 match(eAXRegI); 5348 match(eDXRegI); 5349 match(eSIRegI); 5350 match(eDIRegI); 5351 5352 format %{ %} 5353 interface(REG_INTER); 5354 %} 5355 5356 // // This operand was used by cmpFastUnlock, but conflicted with 'object' reg 5357 // // 5358 operand eSIRegI(xRegI reg) %{ 5359 constraint(ALLOC_IN_RC(esi_reg)); 5360 match(reg); 5361 match(eRegI); 5362 5363 format %{ "ESI" %} 5364 interface(REG_INTER); 5365 %} 5366 5367 // Pointer Register 5368 operand anyRegP() %{ 5369 constraint(ALLOC_IN_RC(any_reg)); 5370 match(RegP); 5371 match(eAXRegP); 5372 match(eBXRegP); 5373 match(eCXRegP); 5374 match(eDIRegP); 5375 match(eRegP); 5376 5377 format %{ %} 5378 interface(REG_INTER); 5379 %} 5380 5381 operand eRegP() %{ 5382 constraint(ALLOC_IN_RC(e_reg)); 5383 match(RegP); 5384 match(eAXRegP); 5385 match(eBXRegP); 5386 match(eCXRegP); 5387 match(eDIRegP); 5388 5389 format %{ %} 5390 interface(REG_INTER); 5391 %} 5392 5393 // On windows95, EBP is not safe to use for implicit null tests. 5394 operand eRegP_no_EBP() %{ 5395 constraint(ALLOC_IN_RC(e_reg_no_rbp)); 5396 match(RegP); 5397 match(eAXRegP); 5398 match(eBXRegP); 5399 match(eCXRegP); 5400 match(eDIRegP); 5401 5402 op_cost(100); 5403 format %{ %} 5404 interface(REG_INTER); 5405 %} 5406 5407 operand naxRegP() %{ 5408 constraint(ALLOC_IN_RC(nax_reg)); 5409 match(RegP); 5410 match(eBXRegP); 5411 match(eDXRegP); 5412 match(eCXRegP); 5413 match(eSIRegP); 5414 match(eDIRegP); 5415 5416 format %{ %} 5417 interface(REG_INTER); 5418 %} 5419 5420 operand nabxRegP() %{ 5421 constraint(ALLOC_IN_RC(nabx_reg)); 5422 match(RegP); 5423 match(eCXRegP); 5424 match(eDXRegP); 5425 match(eSIRegP); 5426 match(eDIRegP); 5427 5428 format %{ %} 5429 interface(REG_INTER); 5430 %} 5431 5432 operand pRegP() %{ 5433 constraint(ALLOC_IN_RC(p_reg)); 5434 match(RegP); 5435 match(eBXRegP); 5436 match(eDXRegP); 5437 match(eSIRegP); 5438 match(eDIRegP); 5439 5440 format %{ %} 5441 interface(REG_INTER); 5442 %} 5443 5444 // Special Registers 5445 // Return a pointer value 5446 operand eAXRegP(eRegP reg) %{ 5447 constraint(ALLOC_IN_RC(eax_reg)); 5448 match(reg); 5449 format %{ "EAX" %} 5450 interface(REG_INTER); 5451 %} 5452 5453 // Used in AtomicAdd 5454 operand eBXRegP(eRegP reg) %{ 5455 constraint(ALLOC_IN_RC(ebx_reg)); 5456 match(reg); 5457 format %{ "EBX" %} 5458 interface(REG_INTER); 5459 %} 5460 5461 // Tail-call (interprocedural jump) to interpreter 5462 operand eCXRegP(eRegP reg) %{ 5463 constraint(ALLOC_IN_RC(ecx_reg)); 5464 match(reg); 5465 format %{ "ECX" %} 5466 interface(REG_INTER); 5467 %} 5468 5469 operand eSIRegP(eRegP reg) %{ 5470 constraint(ALLOC_IN_RC(esi_reg)); 5471 match(reg); 5472 format %{ "ESI" %} 5473 interface(REG_INTER); 5474 %} 5475 5476 // Used in rep stosw 5477 operand eDIRegP(eRegP reg) %{ 5478 constraint(ALLOC_IN_RC(edi_reg)); 5479 match(reg); 5480 format %{ "EDI" %} 5481 interface(REG_INTER); 5482 %} 5483 5484 operand eBPRegP() %{ 5485 constraint(ALLOC_IN_RC(ebp_reg)); 5486 match(RegP); 5487 format %{ "EBP" %} 5488 interface(REG_INTER); 5489 %} 5490 5491 operand eRegL() %{ 5492 constraint(ALLOC_IN_RC(long_reg)); 5493 match(RegL); 5494 match(eADXRegL); 5495 5496 format %{ %} 5497 interface(REG_INTER); 5498 %} 5499 5500 operand eADXRegL( eRegL reg ) %{ 5501 constraint(ALLOC_IN_RC(eadx_reg)); 5502 match(reg); 5503 5504 format %{ "EDX:EAX" %} 5505 interface(REG_INTER); 5506 %} 5507 5508 operand eBCXRegL( eRegL reg ) %{ 5509 constraint(ALLOC_IN_RC(ebcx_reg)); 5510 match(reg); 5511 5512 format %{ "EBX:ECX" %} 5513 interface(REG_INTER); 5514 %} 5515 5516 // Special case for integer high multiply 5517 operand eADXRegL_low_only() %{ 5518 constraint(ALLOC_IN_RC(eadx_reg)); 5519 match(RegL); 5520 5521 format %{ "EAX" %} 5522 interface(REG_INTER); 5523 %} 5524 5525 // Flags register, used as output of compare instructions 5526 operand eFlagsReg() %{ 5527 constraint(ALLOC_IN_RC(int_flags)); 5528 match(RegFlags); 5529 5530 format %{ "EFLAGS" %} 5531 interface(REG_INTER); 5532 %} 5533 5534 // Flags register, used as output of FLOATING POINT compare instructions 5535 operand eFlagsRegU() %{ 5536 constraint(ALLOC_IN_RC(int_flags)); 5537 match(RegFlags); 5538 5539 format %{ "EFLAGS_U" %} 5540 interface(REG_INTER); 5541 %} 5542 5543 operand eFlagsRegUCF() %{ 5544 constraint(ALLOC_IN_RC(int_flags)); 5545 match(RegFlags); 5546 predicate(false); 5547 5548 format %{ "EFLAGS_U_CF" %} 5549 interface(REG_INTER); 5550 %} 5551 5552 // Condition Code Register used by long compare 5553 operand flagsReg_long_LTGE() %{ 5554 constraint(ALLOC_IN_RC(int_flags)); 5555 match(RegFlags); 5556 format %{ "FLAGS_LTGE" %} 5557 interface(REG_INTER); 5558 %} 5559 operand flagsReg_long_EQNE() %{ 5560 constraint(ALLOC_IN_RC(int_flags)); 5561 match(RegFlags); 5562 format %{ "FLAGS_EQNE" %} 5563 interface(REG_INTER); 5564 %} 5565 operand flagsReg_long_LEGT() %{ 5566 constraint(ALLOC_IN_RC(int_flags)); 5567 match(RegFlags); 5568 format %{ "FLAGS_LEGT" %} 5569 interface(REG_INTER); 5570 %} 5571 5572 // Float register operands 5573 operand regD() %{ 5574 predicate( UseSSE < 2 ); 5575 constraint(ALLOC_IN_RC(dbl_reg)); 5576 match(RegD); 5577 match(regDPR1); 5578 match(regDPR2); 5579 format %{ %} 5580 interface(REG_INTER); 5581 %} 5582 5583 operand regDPR1(regD reg) %{ 5584 predicate( UseSSE < 2 ); 5585 constraint(ALLOC_IN_RC(dbl_reg0)); 5586 match(reg); 5587 format %{ "FPR1" %} 5588 interface(REG_INTER); 5589 %} 5590 5591 operand regDPR2(regD reg) %{ 5592 predicate( UseSSE < 2 ); 5593 constraint(ALLOC_IN_RC(dbl_reg1)); 5594 match(reg); 5595 format %{ "FPR2" %} 5596 interface(REG_INTER); 5597 %} 5598 5599 operand regnotDPR1(regD reg) %{ 5600 predicate( UseSSE < 2 ); 5601 constraint(ALLOC_IN_RC(dbl_notreg0)); 5602 match(reg); 5603 format %{ %} 5604 interface(REG_INTER); 5605 %} 5606 5607 // XMM Double register operands 5608 operand regXD() %{ 5609 predicate( UseSSE>=2 ); 5610 constraint(ALLOC_IN_RC(xdb_reg)); 5611 match(RegD); 5612 match(regXD6); 5613 match(regXD7); 5614 format %{ %} 5615 interface(REG_INTER); 5616 %} 5617 5618 // XMM6 double register operands 5619 operand regXD6(regXD reg) %{ 5620 predicate( UseSSE>=2 ); 5621 constraint(ALLOC_IN_RC(xdb_reg6)); 5622 match(reg); 5623 format %{ "XMM6" %} 5624 interface(REG_INTER); 5625 %} 5626 5627 // XMM7 double register operands 5628 operand regXD7(regXD reg) %{ 5629 predicate( UseSSE>=2 ); 5630 constraint(ALLOC_IN_RC(xdb_reg7)); 5631 match(reg); 5632 format %{ "XMM7" %} 5633 interface(REG_INTER); 5634 %} 5635 5636 // Float register operands 5637 operand regF() %{ 5638 predicate( UseSSE < 2 ); 5639 constraint(ALLOC_IN_RC(flt_reg)); 5640 match(RegF); 5641 match(regFPR1); 5642 format %{ %} 5643 interface(REG_INTER); 5644 %} 5645 5646 // Float register operands 5647 operand regFPR1(regF reg) %{ 5648 predicate( UseSSE < 2 ); 5649 constraint(ALLOC_IN_RC(flt_reg0)); 5650 match(reg); 5651 format %{ "FPR1" %} 5652 interface(REG_INTER); 5653 %} 5654 5655 // XMM register operands 5656 operand regX() %{ 5657 predicate( UseSSE>=1 ); 5658 constraint(ALLOC_IN_RC(xmm_reg)); 5659 match(RegF); 5660 format %{ %} 5661 interface(REG_INTER); 5662 %} 5663 5664 5665 //----------Memory Operands---------------------------------------------------- 5666 // Direct Memory Operand 5667 operand direct(immP addr) %{ 5668 match(addr); 5669 5670 format %{ "[$addr]" %} 5671 interface(MEMORY_INTER) %{ 5672 base(0xFFFFFFFF); 5673 index(0x4); 5674 scale(0x0); 5675 disp($addr); 5676 %} 5677 %} 5678 5679 // Indirect Memory Operand 5680 operand indirect(eRegP reg) %{ 5681 constraint(ALLOC_IN_RC(e_reg)); 5682 match(reg); 5683 5684 format %{ "[$reg]" %} 5685 interface(MEMORY_INTER) %{ 5686 base($reg); 5687 index(0x4); 5688 scale(0x0); 5689 disp(0x0); 5690 %} 5691 %} 5692 5693 // Indirect Memory Plus Short Offset Operand 5694 operand indOffset8(eRegP reg, immI8 off) %{ 5695 match(AddP reg off); 5696 5697 format %{ "[$reg + $off]" %} 5698 interface(MEMORY_INTER) %{ 5699 base($reg); 5700 index(0x4); 5701 scale(0x0); 5702 disp($off); 5703 %} 5704 %} 5705 5706 // Indirect Memory Plus Long Offset Operand 5707 operand indOffset32(eRegP reg, immI off) %{ 5708 match(AddP reg off); 5709 5710 format %{ "[$reg + $off]" %} 5711 interface(MEMORY_INTER) %{ 5712 base($reg); 5713 index(0x4); 5714 scale(0x0); 5715 disp($off); 5716 %} 5717 %} 5718 5719 // Indirect Memory Plus Long Offset Operand 5720 operand indOffset32X(eRegI reg, immP off) %{ 5721 match(AddP off reg); 5722 5723 format %{ "[$reg + $off]" %} 5724 interface(MEMORY_INTER) %{ 5725 base($reg); 5726 index(0x4); 5727 scale(0x0); 5728 disp($off); 5729 %} 5730 %} 5731 5732 // Indirect Memory Plus Index Register Plus Offset Operand 5733 operand indIndexOffset(eRegP reg, eRegI ireg, immI off) %{ 5734 match(AddP (AddP reg ireg) off); 5735 5736 op_cost(10); 5737 format %{"[$reg + $off + $ireg]" %} 5738 interface(MEMORY_INTER) %{ 5739 base($reg); 5740 index($ireg); 5741 scale(0x0); 5742 disp($off); 5743 %} 5744 %} 5745 5746 // Indirect Memory Plus Index Register Plus Offset Operand 5747 operand indIndex(eRegP reg, eRegI ireg) %{ 5748 match(AddP reg ireg); 5749 5750 op_cost(10); 5751 format %{"[$reg + $ireg]" %} 5752 interface(MEMORY_INTER) %{ 5753 base($reg); 5754 index($ireg); 5755 scale(0x0); 5756 disp(0x0); 5757 %} 5758 %} 5759 5760 // // ------------------------------------------------------------------------- 5761 // // 486 architecture doesn't support "scale * index + offset" with out a base 5762 // // ------------------------------------------------------------------------- 5763 // // Scaled Memory Operands 5764 // // Indirect Memory Times Scale Plus Offset Operand 5765 // operand indScaleOffset(immP off, eRegI ireg, immI2 scale) %{ 5766 // match(AddP off (LShiftI ireg scale)); 5767 // 5768 // op_cost(10); 5769 // format %{"[$off + $ireg << $scale]" %} 5770 // interface(MEMORY_INTER) %{ 5771 // base(0x4); 5772 // index($ireg); 5773 // scale($scale); 5774 // disp($off); 5775 // %} 5776 // %} 5777 5778 // Indirect Memory Times Scale Plus Index Register 5779 operand indIndexScale(eRegP reg, eRegI ireg, immI2 scale) %{ 5780 match(AddP reg (LShiftI ireg scale)); 5781 5782 op_cost(10); 5783 format %{"[$reg + $ireg << $scale]" %} 5784 interface(MEMORY_INTER) %{ 5785 base($reg); 5786 index($ireg); 5787 scale($scale); 5788 disp(0x0); 5789 %} 5790 %} 5791 5792 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand 5793 operand indIndexScaleOffset(eRegP reg, immI off, eRegI ireg, immI2 scale) %{ 5794 match(AddP (AddP reg (LShiftI ireg scale)) off); 5795 5796 op_cost(10); 5797 format %{"[$reg + $off + $ireg << $scale]" %} 5798 interface(MEMORY_INTER) %{ 5799 base($reg); 5800 index($ireg); 5801 scale($scale); 5802 disp($off); 5803 %} 5804 %} 5805 5806 //----------Load Long Memory Operands------------------------------------------ 5807 // The load-long idiom will use it's address expression again after loading 5808 // the first word of the long. If the load-long destination overlaps with 5809 // registers used in the addressing expression, the 2nd half will be loaded 5810 // from a clobbered address. Fix this by requiring that load-long use 5811 // address registers that do not overlap with the load-long target. 5812 5813 // load-long support 5814 operand load_long_RegP() %{ 5815 constraint(ALLOC_IN_RC(esi_reg)); 5816 match(RegP); 5817 match(eSIRegP); 5818 op_cost(100); 5819 format %{ %} 5820 interface(REG_INTER); 5821 %} 5822 5823 // Indirect Memory Operand Long 5824 operand load_long_indirect(load_long_RegP reg) %{ 5825 constraint(ALLOC_IN_RC(esi_reg)); 5826 match(reg); 5827 5828 format %{ "[$reg]" %} 5829 interface(MEMORY_INTER) %{ 5830 base($reg); 5831 index(0x4); 5832 scale(0x0); 5833 disp(0x0); 5834 %} 5835 %} 5836 5837 // Indirect Memory Plus Long Offset Operand 5838 operand load_long_indOffset32(load_long_RegP reg, immI off) %{ 5839 match(AddP reg off); 5840 5841 format %{ "[$reg + $off]" %} 5842 interface(MEMORY_INTER) %{ 5843 base($reg); 5844 index(0x4); 5845 scale(0x0); 5846 disp($off); 5847 %} 5848 %} 5849 5850 opclass load_long_memory(load_long_indirect, load_long_indOffset32); 5851 5852 5853 //----------Special Memory Operands-------------------------------------------- 5854 // Stack Slot Operand - This operand is used for loading and storing temporary 5855 // values on the stack where a match requires a value to 5856 // flow through memory. 5857 operand stackSlotP(sRegP reg) %{ 5858 constraint(ALLOC_IN_RC(stack_slots)); 5859 // No match rule because this operand is only generated in matching 5860 format %{ "[$reg]" %} 5861 interface(MEMORY_INTER) %{ 5862 base(0x4); // ESP 5863 index(0x4); // No Index 5864 scale(0x0); // No Scale 5865 disp($reg); // Stack Offset 5866 %} 5867 %} 5868 5869 operand stackSlotI(sRegI reg) %{ 5870 constraint(ALLOC_IN_RC(stack_slots)); 5871 // No match rule because this operand is only generated in matching 5872 format %{ "[$reg]" %} 5873 interface(MEMORY_INTER) %{ 5874 base(0x4); // ESP 5875 index(0x4); // No Index 5876 scale(0x0); // No Scale 5877 disp($reg); // Stack Offset 5878 %} 5879 %} 5880 5881 operand stackSlotF(sRegF reg) %{ 5882 constraint(ALLOC_IN_RC(stack_slots)); 5883 // No match rule because this operand is only generated in matching 5884 format %{ "[$reg]" %} 5885 interface(MEMORY_INTER) %{ 5886 base(0x4); // ESP 5887 index(0x4); // No Index 5888 scale(0x0); // No Scale 5889 disp($reg); // Stack Offset 5890 %} 5891 %} 5892 5893 operand stackSlotD(sRegD reg) %{ 5894 constraint(ALLOC_IN_RC(stack_slots)); 5895 // No match rule because this operand is only generated in matching 5896 format %{ "[$reg]" %} 5897 interface(MEMORY_INTER) %{ 5898 base(0x4); // ESP 5899 index(0x4); // No Index 5900 scale(0x0); // No Scale 5901 disp($reg); // Stack Offset 5902 %} 5903 %} 5904 5905 operand stackSlotL(sRegL reg) %{ 5906 constraint(ALLOC_IN_RC(stack_slots)); 5907 // No match rule because this operand is only generated in matching 5908 format %{ "[$reg]" %} 5909 interface(MEMORY_INTER) %{ 5910 base(0x4); // ESP 5911 index(0x4); // No Index 5912 scale(0x0); // No Scale 5913 disp($reg); // Stack Offset 5914 %} 5915 %} 5916 5917 //----------Memory Operands - Win95 Implicit Null Variants---------------- 5918 // Indirect Memory Operand 5919 operand indirect_win95_safe(eRegP_no_EBP reg) 5920 %{ 5921 constraint(ALLOC_IN_RC(e_reg)); 5922 match(reg); 5923 5924 op_cost(100); 5925 format %{ "[$reg]" %} 5926 interface(MEMORY_INTER) %{ 5927 base($reg); 5928 index(0x4); 5929 scale(0x0); 5930 disp(0x0); 5931 %} 5932 %} 5933 5934 // Indirect Memory Plus Short Offset Operand 5935 operand indOffset8_win95_safe(eRegP_no_EBP reg, immI8 off) 5936 %{ 5937 match(AddP reg off); 5938 5939 op_cost(100); 5940 format %{ "[$reg + $off]" %} 5941 interface(MEMORY_INTER) %{ 5942 base($reg); 5943 index(0x4); 5944 scale(0x0); 5945 disp($off); 5946 %} 5947 %} 5948 5949 // Indirect Memory Plus Long Offset Operand 5950 operand indOffset32_win95_safe(eRegP_no_EBP reg, immI off) 5951 %{ 5952 match(AddP reg off); 5953 5954 op_cost(100); 5955 format %{ "[$reg + $off]" %} 5956 interface(MEMORY_INTER) %{ 5957 base($reg); 5958 index(0x4); 5959 scale(0x0); 5960 disp($off); 5961 %} 5962 %} 5963 5964 // Indirect Memory Plus Index Register Plus Offset Operand 5965 operand indIndexOffset_win95_safe(eRegP_no_EBP reg, eRegI ireg, immI off) 5966 %{ 5967 match(AddP (AddP reg ireg) off); 5968 5969 op_cost(100); 5970 format %{"[$reg + $off + $ireg]" %} 5971 interface(MEMORY_INTER) %{ 5972 base($reg); 5973 index($ireg); 5974 scale(0x0); 5975 disp($off); 5976 %} 5977 %} 5978 5979 // Indirect Memory Times Scale Plus Index Register 5980 operand indIndexScale_win95_safe(eRegP_no_EBP reg, eRegI ireg, immI2 scale) 5981 %{ 5982 match(AddP reg (LShiftI ireg scale)); 5983 5984 op_cost(100); 5985 format %{"[$reg + $ireg << $scale]" %} 5986 interface(MEMORY_INTER) %{ 5987 base($reg); 5988 index($ireg); 5989 scale($scale); 5990 disp(0x0); 5991 %} 5992 %} 5993 5994 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand 5995 operand indIndexScaleOffset_win95_safe(eRegP_no_EBP reg, immI off, eRegI ireg, immI2 scale) 5996 %{ 5997 match(AddP (AddP reg (LShiftI ireg scale)) off); 5998 5999 op_cost(100); 6000 format %{"[$reg + $off + $ireg << $scale]" %} 6001 interface(MEMORY_INTER) %{ 6002 base($reg); 6003 index($ireg); 6004 scale($scale); 6005 disp($off); 6006 %} 6007 %} 6008 6009 //----------Conditional Branch Operands---------------------------------------- 6010 // Comparison Op - This is the operation of the comparison, and is limited to 6011 // the following set of codes: 6012 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=) 6013 // 6014 // Other attributes of the comparison, such as unsignedness, are specified 6015 // by the comparison instruction that sets a condition code flags register. 6016 // That result is represented by a flags operand whose subtype is appropriate 6017 // to the unsignedness (etc.) of the comparison. 6018 // 6019 // Later, the instruction which matches both the Comparison Op (a Bool) and 6020 // the flags (produced by the Cmp) specifies the coding of the comparison op 6021 // by matching a specific subtype of Bool operand below, such as cmpOpU. 6022 6023 // Comparision Code 6024 operand cmpOp() %{ 6025 match(Bool); 6026 6027 format %{ "" %} 6028 interface(COND_INTER) %{ 6029 equal(0x4, "e"); 6030 not_equal(0x5, "ne"); 6031 less(0xC, "l"); 6032 greater_equal(0xD, "ge"); 6033 less_equal(0xE, "le"); 6034 greater(0xF, "g"); 6035 %} 6036 %} 6037 6038 // Comparison Code, unsigned compare. Used by FP also, with 6039 // C2 (unordered) turned into GT or LT already. The other bits 6040 // C0 and C3 are turned into Carry & Zero flags. 6041 operand cmpOpU() %{ 6042 match(Bool); 6043 6044 format %{ "" %} 6045 interface(COND_INTER) %{ 6046 equal(0x4, "e"); 6047 not_equal(0x5, "ne"); 6048 less(0x2, "b"); 6049 greater_equal(0x3, "nb"); 6050 less_equal(0x6, "be"); 6051 greater(0x7, "nbe"); 6052 %} 6053 %} 6054 6055 // Floating comparisons that don't require any fixup for the unordered case 6056 operand cmpOpUCF() %{ 6057 match(Bool); 6058 predicate(n->as_Bool()->_test._test == BoolTest::lt || 6059 n->as_Bool()->_test._test == BoolTest::ge || 6060 n->as_Bool()->_test._test == BoolTest::le || 6061 n->as_Bool()->_test._test == BoolTest::gt); 6062 format %{ "" %} 6063 interface(COND_INTER) %{ 6064 equal(0x4, "e"); 6065 not_equal(0x5, "ne"); 6066 less(0x2, "b"); 6067 greater_equal(0x3, "nb"); 6068 less_equal(0x6, "be"); 6069 greater(0x7, "nbe"); 6070 %} 6071 %} 6072 6073 6074 // Floating comparisons that can be fixed up with extra conditional jumps 6075 operand cmpOpUCF2() %{ 6076 match(Bool); 6077 predicate(n->as_Bool()->_test._test == BoolTest::ne || 6078 n->as_Bool()->_test._test == BoolTest::eq); 6079 format %{ "" %} 6080 interface(COND_INTER) %{ 6081 equal(0x4, "e"); 6082 not_equal(0x5, "ne"); 6083 less(0x2, "b"); 6084 greater_equal(0x3, "nb"); 6085 less_equal(0x6, "be"); 6086 greater(0x7, "nbe"); 6087 %} 6088 %} 6089 6090 // Comparison Code for FP conditional move 6091 operand cmpOp_fcmov() %{ 6092 match(Bool); 6093 6094 format %{ "" %} 6095 interface(COND_INTER) %{ 6096 equal (0x0C8); 6097 not_equal (0x1C8); 6098 less (0x0C0); 6099 greater_equal(0x1C0); 6100 less_equal (0x0D0); 6101 greater (0x1D0); 6102 %} 6103 %} 6104 6105 // Comparision Code used in long compares 6106 operand cmpOp_commute() %{ 6107 match(Bool); 6108 6109 format %{ "" %} 6110 interface(COND_INTER) %{ 6111 equal(0x4, "e"); 6112 not_equal(0x5, "ne"); 6113 less(0xF, "g"); 6114 greater_equal(0xE, "le"); 6115 less_equal(0xD, "ge"); 6116 greater(0xC, "l"); 6117 %} 6118 %} 6119 6120 //----------OPERAND CLASSES---------------------------------------------------- 6121 // Operand Classes are groups of operands that are used as to simplify 6122 // instruction definitions by not requiring the AD writer to specify separate 6123 // instructions for every form of operand when the instruction accepts 6124 // multiple operand types with the same basic encoding and format. The classic 6125 // case of this is memory operands. 6126 6127 opclass memory(direct, indirect, indOffset8, indOffset32, indOffset32X, indIndexOffset, 6128 indIndex, indIndexScale, indIndexScaleOffset); 6129 6130 // Long memory operations are encoded in 2 instructions and a +4 offset. 6131 // This means some kind of offset is always required and you cannot use 6132 // an oop as the offset (done when working on static globals). 6133 opclass long_memory(direct, indirect, indOffset8, indOffset32, indIndexOffset, 6134 indIndex, indIndexScale, indIndexScaleOffset); 6135 6136 6137 //----------PIPELINE----------------------------------------------------------- 6138 // Rules which define the behavior of the target architectures pipeline. 6139 pipeline %{ 6140 6141 //----------ATTRIBUTES--------------------------------------------------------- 6142 attributes %{ 6143 variable_size_instructions; // Fixed size instructions 6144 max_instructions_per_bundle = 3; // Up to 3 instructions per bundle 6145 instruction_unit_size = 1; // An instruction is 1 bytes long 6146 instruction_fetch_unit_size = 16; // The processor fetches one line 6147 instruction_fetch_units = 1; // of 16 bytes 6148 6149 // List of nop instructions 6150 nops( MachNop ); 6151 %} 6152 6153 //----------RESOURCES---------------------------------------------------------- 6154 // Resources are the functional units available to the machine 6155 6156 // Generic P2/P3 pipeline 6157 // 3 decoders, only D0 handles big operands; a "bundle" is the limit of 6158 // 3 instructions decoded per cycle. 6159 // 2 load/store ops per cycle, 1 branch, 1 FPU, 6160 // 2 ALU op, only ALU0 handles mul/div instructions. 6161 resources( D0, D1, D2, DECODE = D0 | D1 | D2, 6162 MS0, MS1, MEM = MS0 | MS1, 6163 BR, FPU, 6164 ALU0, ALU1, ALU = ALU0 | ALU1 ); 6165 6166 //----------PIPELINE DESCRIPTION----------------------------------------------- 6167 // Pipeline Description specifies the stages in the machine's pipeline 6168 6169 // Generic P2/P3 pipeline 6170 pipe_desc(S0, S1, S2, S3, S4, S5); 6171 6172 //----------PIPELINE CLASSES--------------------------------------------------- 6173 // Pipeline Classes describe the stages in which input and output are 6174 // referenced by the hardware pipeline. 6175 6176 // Naming convention: ialu or fpu 6177 // Then: _reg 6178 // Then: _reg if there is a 2nd register 6179 // Then: _long if it's a pair of instructions implementing a long 6180 // Then: _fat if it requires the big decoder 6181 // Or: _mem if it requires the big decoder and a memory unit. 6182 6183 // Integer ALU reg operation 6184 pipe_class ialu_reg(eRegI dst) %{ 6185 single_instruction; 6186 dst : S4(write); 6187 dst : S3(read); 6188 DECODE : S0; // any decoder 6189 ALU : S3; // any alu 6190 %} 6191 6192 // Long ALU reg operation 6193 pipe_class ialu_reg_long(eRegL dst) %{ 6194 instruction_count(2); 6195 dst : S4(write); 6196 dst : S3(read); 6197 DECODE : S0(2); // any 2 decoders 6198 ALU : S3(2); // both alus 6199 %} 6200 6201 // Integer ALU reg operation using big decoder 6202 pipe_class ialu_reg_fat(eRegI dst) %{ 6203 single_instruction; 6204 dst : S4(write); 6205 dst : S3(read); 6206 D0 : S0; // big decoder only 6207 ALU : S3; // any alu 6208 %} 6209 6210 // Long ALU reg operation using big decoder 6211 pipe_class ialu_reg_long_fat(eRegL dst) %{ 6212 instruction_count(2); 6213 dst : S4(write); 6214 dst : S3(read); 6215 D0 : S0(2); // big decoder only; twice 6216 ALU : S3(2); // any 2 alus 6217 %} 6218 6219 // Integer ALU reg-reg operation 6220 pipe_class ialu_reg_reg(eRegI dst, eRegI src) %{ 6221 single_instruction; 6222 dst : S4(write); 6223 src : S3(read); 6224 DECODE : S0; // any decoder 6225 ALU : S3; // any alu 6226 %} 6227 6228 // Long ALU reg-reg operation 6229 pipe_class ialu_reg_reg_long(eRegL dst, eRegL src) %{ 6230 instruction_count(2); 6231 dst : S4(write); 6232 src : S3(read); 6233 DECODE : S0(2); // any 2 decoders 6234 ALU : S3(2); // both alus 6235 %} 6236 6237 // Integer ALU reg-reg operation 6238 pipe_class ialu_reg_reg_fat(eRegI dst, memory src) %{ 6239 single_instruction; 6240 dst : S4(write); 6241 src : S3(read); 6242 D0 : S0; // big decoder only 6243 ALU : S3; // any alu 6244 %} 6245 6246 // Long ALU reg-reg operation 6247 pipe_class ialu_reg_reg_long_fat(eRegL dst, eRegL src) %{ 6248 instruction_count(2); 6249 dst : S4(write); 6250 src : S3(read); 6251 D0 : S0(2); // big decoder only; twice 6252 ALU : S3(2); // both alus 6253 %} 6254 6255 // Integer ALU reg-mem operation 6256 pipe_class ialu_reg_mem(eRegI dst, memory mem) %{ 6257 single_instruction; 6258 dst : S5(write); 6259 mem : S3(read); 6260 D0 : S0; // big decoder only 6261 ALU : S4; // any alu 6262 MEM : S3; // any mem 6263 %} 6264 6265 // Long ALU reg-mem operation 6266 pipe_class ialu_reg_long_mem(eRegL dst, load_long_memory mem) %{ 6267 instruction_count(2); 6268 dst : S5(write); 6269 mem : S3(read); 6270 D0 : S0(2); // big decoder only; twice 6271 ALU : S4(2); // any 2 alus 6272 MEM : S3(2); // both mems 6273 %} 6274 6275 // Integer mem operation (prefetch) 6276 pipe_class ialu_mem(memory mem) 6277 %{ 6278 single_instruction; 6279 mem : S3(read); 6280 D0 : S0; // big decoder only 6281 MEM : S3; // any mem 6282 %} 6283 6284 // Integer Store to Memory 6285 pipe_class ialu_mem_reg(memory mem, eRegI src) %{ 6286 single_instruction; 6287 mem : S3(read); 6288 src : S5(read); 6289 D0 : S0; // big decoder only 6290 ALU : S4; // any alu 6291 MEM : S3; 6292 %} 6293 6294 // Long Store to Memory 6295 pipe_class ialu_mem_long_reg(memory mem, eRegL src) %{ 6296 instruction_count(2); 6297 mem : S3(read); 6298 src : S5(read); 6299 D0 : S0(2); // big decoder only; twice 6300 ALU : S4(2); // any 2 alus 6301 MEM : S3(2); // Both mems 6302 %} 6303 6304 // Integer Store to Memory 6305 pipe_class ialu_mem_imm(memory mem) %{ 6306 single_instruction; 6307 mem : S3(read); 6308 D0 : S0; // big decoder only 6309 ALU : S4; // any alu 6310 MEM : S3; 6311 %} 6312 6313 // Integer ALU0 reg-reg operation 6314 pipe_class ialu_reg_reg_alu0(eRegI dst, eRegI src) %{ 6315 single_instruction; 6316 dst : S4(write); 6317 src : S3(read); 6318 D0 : S0; // Big decoder only 6319 ALU0 : S3; // only alu0 6320 %} 6321 6322 // Integer ALU0 reg-mem operation 6323 pipe_class ialu_reg_mem_alu0(eRegI dst, memory mem) %{ 6324 single_instruction; 6325 dst : S5(write); 6326 mem : S3(read); 6327 D0 : S0; // big decoder only 6328 ALU0 : S4; // ALU0 only 6329 MEM : S3; // any mem 6330 %} 6331 6332 // Integer ALU reg-reg operation 6333 pipe_class ialu_cr_reg_reg(eFlagsReg cr, eRegI src1, eRegI src2) %{ 6334 single_instruction; 6335 cr : S4(write); 6336 src1 : S3(read); 6337 src2 : S3(read); 6338 DECODE : S0; // any decoder 6339 ALU : S3; // any alu 6340 %} 6341 6342 // Integer ALU reg-imm operation 6343 pipe_class ialu_cr_reg_imm(eFlagsReg cr, eRegI src1) %{ 6344 single_instruction; 6345 cr : S4(write); 6346 src1 : S3(read); 6347 DECODE : S0; // any decoder 6348 ALU : S3; // any alu 6349 %} 6350 6351 // Integer ALU reg-mem operation 6352 pipe_class ialu_cr_reg_mem(eFlagsReg cr, eRegI src1, memory src2) %{ 6353 single_instruction; 6354 cr : S4(write); 6355 src1 : S3(read); 6356 src2 : S3(read); 6357 D0 : S0; // big decoder only 6358 ALU : S4; // any alu 6359 MEM : S3; 6360 %} 6361 6362 // Conditional move reg-reg 6363 pipe_class pipe_cmplt( eRegI p, eRegI q, eRegI y ) %{ 6364 instruction_count(4); 6365 y : S4(read); 6366 q : S3(read); 6367 p : S3(read); 6368 DECODE : S0(4); // any decoder 6369 %} 6370 6371 // Conditional move reg-reg 6372 pipe_class pipe_cmov_reg( eRegI dst, eRegI src, eFlagsReg cr ) %{ 6373 single_instruction; 6374 dst : S4(write); 6375 src : S3(read); 6376 cr : S3(read); 6377 DECODE : S0; // any decoder 6378 %} 6379 6380 // Conditional move reg-mem 6381 pipe_class pipe_cmov_mem( eFlagsReg cr, eRegI dst, memory src) %{ 6382 single_instruction; 6383 dst : S4(write); 6384 src : S3(read); 6385 cr : S3(read); 6386 DECODE : S0; // any decoder 6387 MEM : S3; 6388 %} 6389 6390 // Conditional move reg-reg long 6391 pipe_class pipe_cmov_reg_long( eFlagsReg cr, eRegL dst, eRegL src) %{ 6392 single_instruction; 6393 dst : S4(write); 6394 src : S3(read); 6395 cr : S3(read); 6396 DECODE : S0(2); // any 2 decoders 6397 %} 6398 6399 // Conditional move double reg-reg 6400 pipe_class pipe_cmovD_reg( eFlagsReg cr, regDPR1 dst, regD src) %{ 6401 single_instruction; 6402 dst : S4(write); 6403 src : S3(read); 6404 cr : S3(read); 6405 DECODE : S0; // any decoder 6406 %} 6407 6408 // Float reg-reg operation 6409 pipe_class fpu_reg(regD dst) %{ 6410 instruction_count(2); 6411 dst : S3(read); 6412 DECODE : S0(2); // any 2 decoders 6413 FPU : S3; 6414 %} 6415 6416 // Float reg-reg operation 6417 pipe_class fpu_reg_reg(regD dst, regD src) %{ 6418 instruction_count(2); 6419 dst : S4(write); 6420 src : S3(read); 6421 DECODE : S0(2); // any 2 decoders 6422 FPU : S3; 6423 %} 6424 6425 // Float reg-reg operation 6426 pipe_class fpu_reg_reg_reg(regD dst, regD src1, regD src2) %{ 6427 instruction_count(3); 6428 dst : S4(write); 6429 src1 : S3(read); 6430 src2 : S3(read); 6431 DECODE : S0(3); // any 3 decoders 6432 FPU : S3(2); 6433 %} 6434 6435 // Float reg-reg operation 6436 pipe_class fpu_reg_reg_reg_reg(regD dst, regD src1, regD src2, regD src3) %{ 6437 instruction_count(4); 6438 dst : S4(write); 6439 src1 : S3(read); 6440 src2 : S3(read); 6441 src3 : S3(read); 6442 DECODE : S0(4); // any 3 decoders 6443 FPU : S3(2); 6444 %} 6445 6446 // Float reg-reg operation 6447 pipe_class fpu_reg_mem_reg_reg(regD dst, memory src1, regD src2, regD src3) %{ 6448 instruction_count(4); 6449 dst : S4(write); 6450 src1 : S3(read); 6451 src2 : S3(read); 6452 src3 : S3(read); 6453 DECODE : S1(3); // any 3 decoders 6454 D0 : S0; // Big decoder only 6455 FPU : S3(2); 6456 MEM : S3; 6457 %} 6458 6459 // Float reg-mem operation 6460 pipe_class fpu_reg_mem(regD dst, memory mem) %{ 6461 instruction_count(2); 6462 dst : S5(write); 6463 mem : S3(read); 6464 D0 : S0; // big decoder only 6465 DECODE : S1; // any decoder for FPU POP 6466 FPU : S4; 6467 MEM : S3; // any mem 6468 %} 6469 6470 // Float reg-mem operation 6471 pipe_class fpu_reg_reg_mem(regD dst, regD src1, memory mem) %{ 6472 instruction_count(3); 6473 dst : S5(write); 6474 src1 : S3(read); 6475 mem : S3(read); 6476 D0 : S0; // big decoder only 6477 DECODE : S1(2); // any decoder for FPU POP 6478 FPU : S4; 6479 MEM : S3; // any mem 6480 %} 6481 6482 // Float mem-reg operation 6483 pipe_class fpu_mem_reg(memory mem, regD src) %{ 6484 instruction_count(2); 6485 src : S5(read); 6486 mem : S3(read); 6487 DECODE : S0; // any decoder for FPU PUSH 6488 D0 : S1; // big decoder only 6489 FPU : S4; 6490 MEM : S3; // any mem 6491 %} 6492 6493 pipe_class fpu_mem_reg_reg(memory mem, regD src1, regD src2) %{ 6494 instruction_count(3); 6495 src1 : S3(read); 6496 src2 : S3(read); 6497 mem : S3(read); 6498 DECODE : S0(2); // any decoder for FPU PUSH 6499 D0 : S1; // big decoder only 6500 FPU : S4; 6501 MEM : S3; // any mem 6502 %} 6503 6504 pipe_class fpu_mem_reg_mem(memory mem, regD src1, memory src2) %{ 6505 instruction_count(3); 6506 src1 : S3(read); 6507 src2 : S3(read); 6508 mem : S4(read); 6509 DECODE : S0; // any decoder for FPU PUSH 6510 D0 : S0(2); // big decoder only 6511 FPU : S4; 6512 MEM : S3(2); // any mem 6513 %} 6514 6515 pipe_class fpu_mem_mem(memory dst, memory src1) %{ 6516 instruction_count(2); 6517 src1 : S3(read); 6518 dst : S4(read); 6519 D0 : S0(2); // big decoder only 6520 MEM : S3(2); // any mem 6521 %} 6522 6523 pipe_class fpu_mem_mem_mem(memory dst, memory src1, memory src2) %{ 6524 instruction_count(3); 6525 src1 : S3(read); 6526 src2 : S3(read); 6527 dst : S4(read); 6528 D0 : S0(3); // big decoder only 6529 FPU : S4; 6530 MEM : S3(3); // any mem 6531 %} 6532 6533 pipe_class fpu_mem_reg_con(memory mem, regD src1) %{ 6534 instruction_count(3); 6535 src1 : S4(read); 6536 mem : S4(read); 6537 DECODE : S0; // any decoder for FPU PUSH 6538 D0 : S0(2); // big decoder only 6539 FPU : S4; 6540 MEM : S3(2); // any mem 6541 %} 6542 6543 // Float load constant 6544 pipe_class fpu_reg_con(regD dst) %{ 6545 instruction_count(2); 6546 dst : S5(write); 6547 D0 : S0; // big decoder only for the load 6548 DECODE : S1; // any decoder for FPU POP 6549 FPU : S4; 6550 MEM : S3; // any mem 6551 %} 6552 6553 // Float load constant 6554 pipe_class fpu_reg_reg_con(regD dst, regD src) %{ 6555 instruction_count(3); 6556 dst : S5(write); 6557 src : S3(read); 6558 D0 : S0; // big decoder only for the load 6559 DECODE : S1(2); // any decoder for FPU POP 6560 FPU : S4; 6561 MEM : S3; // any mem 6562 %} 6563 6564 // UnConditional branch 6565 pipe_class pipe_jmp( label labl ) %{ 6566 single_instruction; 6567 BR : S3; 6568 %} 6569 6570 // Conditional branch 6571 pipe_class pipe_jcc( cmpOp cmp, eFlagsReg cr, label labl ) %{ 6572 single_instruction; 6573 cr : S1(read); 6574 BR : S3; 6575 %} 6576 6577 // Allocation idiom 6578 pipe_class pipe_cmpxchg( eRegP dst, eRegP heap_ptr ) %{ 6579 instruction_count(1); force_serialization; 6580 fixed_latency(6); 6581 heap_ptr : S3(read); 6582 DECODE : S0(3); 6583 D0 : S2; 6584 MEM : S3; 6585 ALU : S3(2); 6586 dst : S5(write); 6587 BR : S5; 6588 %} 6589 6590 // Generic big/slow expanded idiom 6591 pipe_class pipe_slow( ) %{ 6592 instruction_count(10); multiple_bundles; force_serialization; 6593 fixed_latency(100); 6594 D0 : S0(2); 6595 MEM : S3(2); 6596 %} 6597 6598 // The real do-nothing guy 6599 pipe_class empty( ) %{ 6600 instruction_count(0); 6601 %} 6602 6603 // Define the class for the Nop node 6604 define %{ 6605 MachNop = empty; 6606 %} 6607 6608 %} 6609 6610 //----------INSTRUCTIONS------------------------------------------------------- 6611 // 6612 // match -- States which machine-independent subtree may be replaced 6613 // by this instruction. 6614 // ins_cost -- The estimated cost of this instruction is used by instruction 6615 // selection to identify a minimum cost tree of machine 6616 // instructions that matches a tree of machine-independent 6617 // instructions. 6618 // format -- A string providing the disassembly for this instruction. 6619 // The value of an instruction's operand may be inserted 6620 // by referring to it with a '$' prefix. 6621 // opcode -- Three instruction opcodes may be provided. These are referred 6622 // to within an encode class as $primary, $secondary, and $tertiary 6623 // respectively. The primary opcode is commonly used to 6624 // indicate the type of machine instruction, while secondary 6625 // and tertiary are often used for prefix options or addressing 6626 // modes. 6627 // ins_encode -- A list of encode classes with parameters. The encode class 6628 // name must have been defined in an 'enc_class' specification 6629 // in the encode section of the architecture description. 6630 6631 //----------BSWAP-Instruction-------------------------------------------------- 6632 instruct bytes_reverse_int(eRegI dst) %{ 6633 match(Set dst (ReverseBytesI dst)); 6634 6635 format %{ "BSWAP $dst" %} 6636 opcode(0x0F, 0xC8); 6637 ins_encode( OpcP, OpcSReg(dst) ); 6638 ins_pipe( ialu_reg ); 6639 %} 6640 6641 instruct bytes_reverse_long(eRegL dst) %{ 6642 match(Set dst (ReverseBytesL dst)); 6643 6644 format %{ "BSWAP $dst.lo\n\t" 6645 "BSWAP $dst.hi\n\t" 6646 "XCHG $dst.lo $dst.hi" %} 6647 6648 ins_cost(125); 6649 ins_encode( bswap_long_bytes(dst) ); 6650 ins_pipe( ialu_reg_reg); 6651 %} 6652 6653 6654 //---------- Zeros Count Instructions ------------------------------------------ 6655 6656 instruct countLeadingZerosI(eRegI dst, eRegI src, eFlagsReg cr) %{ 6657 predicate(UseCountLeadingZerosInstruction); 6658 match(Set dst (CountLeadingZerosI src)); 6659 effect(KILL cr); 6660 6661 format %{ "LZCNT $dst, $src\t# count leading zeros (int)" %} 6662 ins_encode %{ 6663 __ lzcntl($dst$$Register, $src$$Register); 6664 %} 6665 ins_pipe(ialu_reg); 6666 %} 6667 6668 instruct countLeadingZerosI_bsr(eRegI dst, eRegI src, eRegI tmp, eFlagsReg cr) %{ 6669 predicate(!UseCountLeadingZerosInstruction); 6670 match(Set dst (CountLeadingZerosI src)); 6671 effect(TEMP dst, TEMP tmp, KILL cr); 6672 6673 format %{ "BSR $tmp, $src\t# count leading zeros (int)\n\t" 6674 "JNZ skip\n\t" 6675 "MOV $tmp, -1\n" 6676 "skip:\n\t" 6677 "MOV $dst, 31\n\t" 6678 "SUB $dst, $tmp" %} 6679 ins_encode %{ 6680 Label skip; 6681 __ bsrl($tmp$$Register, $src$$Register); 6682 __ jccb(Assembler::notZero, skip); 6683 __ movl($tmp$$Register, -1); 6684 __ bind(skip); 6685 __ movl($dst$$Register, BitsPerInt - 1); 6686 __ subl($dst$$Register, $tmp$$Register); 6687 %} 6688 ins_pipe(ialu_reg); 6689 %} 6690 6691 instruct countLeadingZerosL(eRegI dst, eRegL src, eRegI tmp, eFlagsReg cr) %{ 6692 predicate(UseCountLeadingZerosInstruction); 6693 match(Set dst (CountLeadingZerosL src)); 6694 effect(TEMP dst, TEMP tmp, KILL cr); 6695 6696 format %{ "LZCNT $dst, $src.hi\t# count leading zeros (long)\n\t" 6697 "JNC done\n\t" 6698 "LZCNT $tmp, $src.lo\n\t" 6699 "ADD $dst, $tmp\n" 6700 "done:" %} 6701 ins_encode %{ 6702 Register Rdst = $dst$$Register; 6703 Register Rsrc = $src$$Register; 6704 Register Rtmp = $tmp$$Register; 6705 Label done; 6706 __ lzcntl(Rdst, HIGH_FROM_LOW(Rsrc)); 6707 __ jccb(Assembler::carryClear, done); 6708 __ lzcntl(Rtmp, Rsrc); 6709 __ addl(Rdst, Rtmp); 6710 __ bind(done); 6711 %} 6712 ins_pipe(ialu_reg); 6713 %} 6714 6715 instruct countLeadingZerosL_bsr(eRegI dst, eRegL src, eRegI tmp, eFlagsReg cr) %{ 6716 predicate(!UseCountLeadingZerosInstruction); 6717 match(Set dst (CountLeadingZerosL src)); 6718 effect(TEMP dst, TEMP tmp, KILL cr); 6719 6720 format %{ "BSR $tmp, $src.hi\t# count leading zeros (long)\n\t" 6721 "JZ msw_is_zero\n\t" 6722 "MOV $dst, 31\n\t" 6723 "SUB $dst, $tmp\n\t" 6724 "JMP done\n" 6725 "msw_is_zero:\n\t" 6726 "BSR $tmp, $src.lo\n\t" 6727 "JNZ lsw_is_not_zero\n\t" 6728 "MOV $tmp, -1\n" 6729 "lsw_is_not_zero:\n\t" 6730 "MOV $dst, 63\n\t" 6731 "SUB $dst, $tmp\n" 6732 "done:" %} 6733 ins_encode %{ 6734 Register Rdst = $dst$$Register; 6735 Register Rsrc = $src$$Register; 6736 Register Rtmp = $tmp$$Register; 6737 Label msw_is_zero; 6738 Label lsw_is_not_zero; 6739 Label done; 6740 __ bsrl(Rtmp, HIGH_FROM_LOW(Rsrc)); 6741 __ jccb(Assembler::zero, msw_is_zero); 6742 __ movl(Rdst, BitsPerLong - 1 - BitsPerInt); // Subtract 32 bit positions for LSW 6743 __ subl(Rdst, Rtmp); 6744 __ jmpb(done); 6745 __ bind(msw_is_zero); 6746 __ bsrl(Rtmp, Rsrc); 6747 __ jccb(Assembler::notZero, lsw_is_not_zero); 6748 __ movl(Rtmp, -1); 6749 __ bind(lsw_is_not_zero); 6750 __ movl(Rdst, BitsPerLong - 1); 6751 __ subl(Rdst, Rtmp); 6752 __ bind(done); 6753 6754 %} 6755 ins_pipe(ialu_reg); 6756 %} 6757 6758 instruct countTrailingZerosI(eRegI dst, eRegI src, eRegI tmp, eFlagsReg cr) %{ 6759 match(Set dst (CountTrailingZerosI src)); 6760 effect(TEMP tmp, KILL cr); 6761 6762 format %{ "BSF $dst, $src\t# count trailing zeros (int)\n\t" 6763 "JNZ done\n\t" 6764 "MOV $dst, 32\n" 6765 "done:" %} 6766 ins_encode %{ 6767 Label done; 6768 __ bsfl($dst$$Register, $src$$Register); 6769 __ jccb(Assembler::notZero, done); 6770 __ movl($dst$$Register, BitsPerInt); 6771 __ bind(done); 6772 %} 6773 ins_pipe(ialu_reg); 6774 %} 6775 6776 instruct countTrailingZerosL(eRegI dst, eRegL src, eRegI tmp, eFlagsReg cr) %{ 6777 match(Set dst (CountTrailingZerosL src)); 6778 effect(TEMP dst, TEMP tmp, KILL cr); 6779 6780 format %{ "BSF $dst, $src.lo\t# count trailing zeros (long)\n\t" 6781 "JNZ done\n\t" 6782 "BSF $tmp, $src.hi\n\t" 6783 "MOV $dst, 32\n\t" 6784 "CMOVZ $tmp, $dst\n\t" 6785 "ADD $dst, $tmp\n" 6786 "done:" %} 6787 ins_encode %{ 6788 Register Rdst = $dst$$Register; 6789 Register Rsrc = $src$$Register; 6790 Register Rtmp = $tmp$$Register; 6791 Label done; 6792 __ bsfl(Rdst, Rsrc); 6793 __ jccb(Assembler::notZero, done); 6794 __ bsfl(Rtmp, HIGH_FROM_LOW(Rsrc)); 6795 __ movl(Rdst, BitsPerInt); 6796 __ cmovl(Assembler::zero, Rtmp, Rdst); 6797 __ addl(Rdst, Rtmp); 6798 __ bind(done); 6799 %} 6800 ins_pipe(ialu_reg); 6801 %} 6802 6803 6804 //---------- Population Count Instructions ------------------------------------- 6805 6806 instruct popCountI(eRegI dst, eRegI src) %{ 6807 predicate(UsePopCountInstruction); 6808 match(Set dst (PopCountI src)); 6809 6810 format %{ "POPCNT $dst, $src" %} 6811 ins_encode %{ 6812 __ popcntl($dst$$Register, $src$$Register); 6813 %} 6814 ins_pipe(ialu_reg); 6815 %} 6816 6817 instruct popCountI_mem(eRegI dst, memory mem) %{ 6818 predicate(UsePopCountInstruction); 6819 match(Set dst (PopCountI (LoadI mem))); 6820 6821 format %{ "POPCNT $dst, $mem" %} 6822 ins_encode %{ 6823 __ popcntl($dst$$Register, $mem$$Address); 6824 %} 6825 ins_pipe(ialu_reg); 6826 %} 6827 6828 // Note: Long.bitCount(long) returns an int. 6829 instruct popCountL(eRegI dst, eRegL src, eRegI tmp, eFlagsReg cr) %{ 6830 predicate(UsePopCountInstruction); 6831 match(Set dst (PopCountL src)); 6832 effect(KILL cr, TEMP tmp, TEMP dst); 6833 6834 format %{ "POPCNT $dst, $src.lo\n\t" 6835 "POPCNT $tmp, $src.hi\n\t" 6836 "ADD $dst, $tmp" %} 6837 ins_encode %{ 6838 __ popcntl($dst$$Register, $src$$Register); 6839 __ popcntl($tmp$$Register, HIGH_FROM_LOW($src$$Register)); 6840 __ addl($dst$$Register, $tmp$$Register); 6841 %} 6842 ins_pipe(ialu_reg); 6843 %} 6844 6845 // Note: Long.bitCount(long) returns an int. 6846 instruct popCountL_mem(eRegI dst, memory mem, eRegI tmp, eFlagsReg cr) %{ 6847 predicate(UsePopCountInstruction); 6848 match(Set dst (PopCountL (LoadL mem))); 6849 effect(KILL cr, TEMP tmp, TEMP dst); 6850 6851 format %{ "POPCNT $dst, $mem\n\t" 6852 "POPCNT $tmp, $mem+4\n\t" 6853 "ADD $dst, $tmp" %} 6854 ins_encode %{ 6855 //__ popcntl($dst$$Register, $mem$$Address$$first); 6856 //__ popcntl($tmp$$Register, $mem$$Address$$second); 6857 __ popcntl($dst$$Register, Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp, false)); 6858 __ popcntl($tmp$$Register, Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp + 4, false)); 6859 __ addl($dst$$Register, $tmp$$Register); 6860 %} 6861 ins_pipe(ialu_reg); 6862 %} 6863 6864 6865 //----------Load/Store/Move Instructions--------------------------------------- 6866 //----------Load Instructions-------------------------------------------------- 6867 // Load Byte (8bit signed) 6868 instruct loadB(xRegI dst, memory mem) %{ 6869 match(Set dst (LoadB mem)); 6870 6871 ins_cost(125); 6872 format %{ "MOVSX8 $dst,$mem\t# byte" %} 6873 6874 ins_encode %{ 6875 __ movsbl($dst$$Register, $mem$$Address); 6876 %} 6877 6878 ins_pipe(ialu_reg_mem); 6879 %} 6880 6881 // Load Byte (8bit signed) into Long Register 6882 instruct loadB2L(eRegL dst, memory mem) %{ 6883 match(Set dst (ConvI2L (LoadB mem))); 6884 6885 ins_cost(375); 6886 format %{ "MOVSX8 $dst.lo,$mem\t# byte -> long\n\t" 6887 "MOV $dst.hi,$dst.lo\n\t" 6888 "SAR $dst.hi,7" %} 6889 6890 ins_encode %{ 6891 __ movsbl($dst$$Register, $mem$$Address); 6892 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register. 6893 __ sarl(HIGH_FROM_LOW($dst$$Register), 7); // 24+1 MSB are already signed extended. 6894 %} 6895 6896 ins_pipe(ialu_reg_mem); 6897 %} 6898 6899 // Load Unsigned Byte (8bit UNsigned) 6900 instruct loadUB(xRegI dst, memory mem) %{ 6901 match(Set dst (LoadUB mem)); 6902 6903 ins_cost(125); 6904 format %{ "MOVZX8 $dst,$mem\t# ubyte -> int" %} 6905 6906 ins_encode %{ 6907 __ movzbl($dst$$Register, $mem$$Address); 6908 %} 6909 6910 ins_pipe(ialu_reg_mem); 6911 %} 6912 6913 // Load Unsigned Byte (8 bit UNsigned) into Long Register 6914 instruct loadUB2L(eRegL dst, memory mem) 6915 %{ 6916 match(Set dst (ConvI2L (LoadUB mem))); 6917 6918 ins_cost(250); 6919 format %{ "MOVZX8 $dst.lo,$mem\t# ubyte -> long\n\t" 6920 "XOR $dst.hi,$dst.hi" %} 6921 6922 ins_encode %{ 6923 __ movzbl($dst$$Register, $mem$$Address); 6924 __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register)); 6925 %} 6926 6927 ins_pipe(ialu_reg_mem); 6928 %} 6929 6930 // Load Short (16bit signed) 6931 instruct loadS(eRegI dst, memory mem) %{ 6932 match(Set dst (LoadS mem)); 6933 6934 ins_cost(125); 6935 format %{ "MOVSX $dst,$mem\t# short" %} 6936 6937 ins_encode %{ 6938 __ movswl($dst$$Register, $mem$$Address); 6939 %} 6940 6941 ins_pipe(ialu_reg_mem); 6942 %} 6943 6944 // Load Short (16bit signed) into Long Register 6945 instruct loadS2L(eRegL dst, memory mem) %{ 6946 match(Set dst (ConvI2L (LoadS mem))); 6947 6948 ins_cost(375); 6949 format %{ "MOVSX $dst.lo,$mem\t# short -> long\n\t" 6950 "MOV $dst.hi,$dst.lo\n\t" 6951 "SAR $dst.hi,15" %} 6952 6953 ins_encode %{ 6954 __ movswl($dst$$Register, $mem$$Address); 6955 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register. 6956 __ sarl(HIGH_FROM_LOW($dst$$Register), 15); // 16+1 MSB are already signed extended. 6957 %} 6958 6959 ins_pipe(ialu_reg_mem); 6960 %} 6961 6962 // Load Unsigned Short/Char (16bit unsigned) 6963 instruct loadUS(eRegI dst, memory mem) %{ 6964 match(Set dst (LoadUS mem)); 6965 6966 ins_cost(125); 6967 format %{ "MOVZX $dst,$mem\t# ushort/char -> int" %} 6968 6969 ins_encode %{ 6970 __ movzwl($dst$$Register, $mem$$Address); 6971 %} 6972 6973 ins_pipe(ialu_reg_mem); 6974 %} 6975 6976 // Load Unsigned Short/Char (16 bit UNsigned) into Long Register 6977 instruct loadUS2L(eRegL dst, memory mem) 6978 %{ 6979 match(Set dst (ConvI2L (LoadUS mem))); 6980 6981 ins_cost(250); 6982 format %{ "MOVZX $dst.lo,$mem\t# ushort/char -> long\n\t" 6983 "XOR $dst.hi,$dst.hi" %} 6984 6985 ins_encode %{ 6986 __ movzwl($dst$$Register, $mem$$Address); 6987 __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register)); 6988 %} 6989 6990 ins_pipe(ialu_reg_mem); 6991 %} 6992 6993 // Load Integer 6994 instruct loadI(eRegI dst, memory mem) %{ 6995 match(Set dst (LoadI mem)); 6996 6997 ins_cost(125); 6998 format %{ "MOV $dst,$mem\t# int" %} 6999 7000 ins_encode %{ 7001 __ movl($dst$$Register, $mem$$Address); 7002 %} 7003 7004 ins_pipe(ialu_reg_mem); 7005 %} 7006 7007 // Load Integer into Long Register 7008 instruct loadI2L(eRegL dst, memory mem) %{ 7009 match(Set dst (ConvI2L (LoadI mem))); 7010 7011 ins_cost(375); 7012 format %{ "MOV $dst.lo,$mem\t# int -> long\n\t" 7013 "MOV $dst.hi,$dst.lo\n\t" 7014 "SAR $dst.hi,31" %} 7015 7016 ins_encode %{ 7017 __ movl($dst$$Register, $mem$$Address); 7018 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register. 7019 __ sarl(HIGH_FROM_LOW($dst$$Register), 31); 7020 %} 7021 7022 ins_pipe(ialu_reg_mem); 7023 %} 7024 7025 // Load Unsigned Integer into Long Register 7026 instruct loadUI2L(eRegL dst, memory mem) %{ 7027 match(Set dst (LoadUI2L mem)); 7028 7029 ins_cost(250); 7030 format %{ "MOV $dst.lo,$mem\t# uint -> long\n\t" 7031 "XOR $dst.hi,$dst.hi" %} 7032 7033 ins_encode %{ 7034 __ movl($dst$$Register, $mem$$Address); 7035 __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register)); 7036 %} 7037 7038 ins_pipe(ialu_reg_mem); 7039 %} 7040 7041 // Load Long. Cannot clobber address while loading, so restrict address 7042 // register to ESI 7043 instruct loadL(eRegL dst, load_long_memory mem) %{ 7044 predicate(!((LoadLNode*)n)->require_atomic_access()); 7045 match(Set dst (LoadL mem)); 7046 7047 ins_cost(250); 7048 format %{ "MOV $dst.lo,$mem\t# long\n\t" 7049 "MOV $dst.hi,$mem+4" %} 7050 7051 ins_encode %{ 7052 Address Amemlo = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp, false); 7053 Address Amemhi = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp + 4, false); 7054 __ movl($dst$$Register, Amemlo); 7055 __ movl(HIGH_FROM_LOW($dst$$Register), Amemhi); 7056 %} 7057 7058 ins_pipe(ialu_reg_long_mem); 7059 %} 7060 7061 // Volatile Load Long. Must be atomic, so do 64-bit FILD 7062 // then store it down to the stack and reload on the int 7063 // side. 7064 instruct loadL_volatile(stackSlotL dst, memory mem) %{ 7065 predicate(UseSSE<=1 && ((LoadLNode*)n)->require_atomic_access()); 7066 match(Set dst (LoadL mem)); 7067 7068 ins_cost(200); 7069 format %{ "FILD $mem\t# Atomic volatile long load\n\t" 7070 "FISTp $dst" %} 7071 ins_encode(enc_loadL_volatile(mem,dst)); 7072 ins_pipe( fpu_reg_mem ); 7073 %} 7074 7075 instruct loadLX_volatile(stackSlotL dst, memory mem, regXD tmp) %{ 7076 predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access()); 7077 match(Set dst (LoadL mem)); 7078 effect(TEMP tmp); 7079 ins_cost(180); 7080 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t" 7081 "MOVSD $dst,$tmp" %} 7082 ins_encode(enc_loadLX_volatile(mem, dst, tmp)); 7083 ins_pipe( pipe_slow ); 7084 %} 7085 7086 instruct loadLX_reg_volatile(eRegL dst, memory mem, regXD tmp) %{ 7087 predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access()); 7088 match(Set dst (LoadL mem)); 7089 effect(TEMP tmp); 7090 ins_cost(160); 7091 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t" 7092 "MOVD $dst.lo,$tmp\n\t" 7093 "PSRLQ $tmp,32\n\t" 7094 "MOVD $dst.hi,$tmp" %} 7095 ins_encode(enc_loadLX_reg_volatile(mem, dst, tmp)); 7096 ins_pipe( pipe_slow ); 7097 %} 7098 7099 // Load Range 7100 instruct loadRange(eRegI dst, memory mem) %{ 7101 match(Set dst (LoadRange mem)); 7102 7103 ins_cost(125); 7104 format %{ "MOV $dst,$mem" %} 7105 opcode(0x8B); 7106 ins_encode( OpcP, RegMem(dst,mem)); 7107 ins_pipe( ialu_reg_mem ); 7108 %} 7109 7110 7111 // Load Pointer 7112 instruct loadP(eRegP dst, memory mem) %{ 7113 match(Set dst (LoadP mem)); 7114 7115 ins_cost(125); 7116 format %{ "MOV $dst,$mem" %} 7117 opcode(0x8B); 7118 ins_encode( OpcP, RegMem(dst,mem)); 7119 ins_pipe( ialu_reg_mem ); 7120 %} 7121 7122 // Load Klass Pointer 7123 instruct loadKlass(eRegP dst, memory mem) %{ 7124 match(Set dst (LoadKlass mem)); 7125 7126 ins_cost(125); 7127 format %{ "MOV $dst,$mem" %} 7128 opcode(0x8B); 7129 ins_encode( OpcP, RegMem(dst,mem)); 7130 ins_pipe( ialu_reg_mem ); 7131 %} 7132 7133 // Load Double 7134 instruct loadD(regD dst, memory mem) %{ 7135 predicate(UseSSE<=1); 7136 match(Set dst (LoadD mem)); 7137 7138 ins_cost(150); 7139 format %{ "FLD_D ST,$mem\n\t" 7140 "FSTP $dst" %} 7141 opcode(0xDD); /* DD /0 */ 7142 ins_encode( OpcP, RMopc_Mem(0x00,mem), 7143 Pop_Reg_D(dst) ); 7144 ins_pipe( fpu_reg_mem ); 7145 %} 7146 7147 // Load Double to XMM 7148 instruct loadXD(regXD dst, memory mem) %{ 7149 predicate(UseSSE>=2 && UseXmmLoadAndClearUpper); 7150 match(Set dst (LoadD mem)); 7151 ins_cost(145); 7152 format %{ "MOVSD $dst,$mem" %} 7153 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x10), RegMem(dst,mem)); 7154 ins_pipe( pipe_slow ); 7155 %} 7156 7157 instruct loadXD_partial(regXD dst, memory mem) %{ 7158 predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper); 7159 match(Set dst (LoadD mem)); 7160 ins_cost(145); 7161 format %{ "MOVLPD $dst,$mem" %} 7162 ins_encode( Opcode(0x66), Opcode(0x0F), Opcode(0x12), RegMem(dst,mem)); 7163 ins_pipe( pipe_slow ); 7164 %} 7165 7166 // Load to XMM register (single-precision floating point) 7167 // MOVSS instruction 7168 instruct loadX(regX dst, memory mem) %{ 7169 predicate(UseSSE>=1); 7170 match(Set dst (LoadF mem)); 7171 ins_cost(145); 7172 format %{ "MOVSS $dst,$mem" %} 7173 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x10), RegMem(dst,mem)); 7174 ins_pipe( pipe_slow ); 7175 %} 7176 7177 // Load Float 7178 instruct loadF(regF dst, memory mem) %{ 7179 predicate(UseSSE==0); 7180 match(Set dst (LoadF mem)); 7181 7182 ins_cost(150); 7183 format %{ "FLD_S ST,$mem\n\t" 7184 "FSTP $dst" %} 7185 opcode(0xD9); /* D9 /0 */ 7186 ins_encode( OpcP, RMopc_Mem(0x00,mem), 7187 Pop_Reg_F(dst) ); 7188 ins_pipe( fpu_reg_mem ); 7189 %} 7190 7191 // Load Aligned Packed Byte to XMM register 7192 instruct loadA8B(regXD dst, memory mem) %{ 7193 predicate(UseSSE>=1); 7194 match(Set dst (Load8B mem)); 7195 ins_cost(125); 7196 format %{ "MOVQ $dst,$mem\t! packed8B" %} 7197 ins_encode( movq_ld(dst, mem)); 7198 ins_pipe( pipe_slow ); 7199 %} 7200 7201 // Load Aligned Packed Short to XMM register 7202 instruct loadA4S(regXD dst, memory mem) %{ 7203 predicate(UseSSE>=1); 7204 match(Set dst (Load4S mem)); 7205 ins_cost(125); 7206 format %{ "MOVQ $dst,$mem\t! packed4S" %} 7207 ins_encode( movq_ld(dst, mem)); 7208 ins_pipe( pipe_slow ); 7209 %} 7210 7211 // Load Aligned Packed Char to XMM register 7212 instruct loadA4C(regXD dst, memory mem) %{ 7213 predicate(UseSSE>=1); 7214 match(Set dst (Load4C mem)); 7215 ins_cost(125); 7216 format %{ "MOVQ $dst,$mem\t! packed4C" %} 7217 ins_encode( movq_ld(dst, mem)); 7218 ins_pipe( pipe_slow ); 7219 %} 7220 7221 // Load Aligned Packed Integer to XMM register 7222 instruct load2IU(regXD dst, memory mem) %{ 7223 predicate(UseSSE>=1); 7224 match(Set dst (Load2I mem)); 7225 ins_cost(125); 7226 format %{ "MOVQ $dst,$mem\t! packed2I" %} 7227 ins_encode( movq_ld(dst, mem)); 7228 ins_pipe( pipe_slow ); 7229 %} 7230 7231 // Load Aligned Packed Single to XMM 7232 instruct loadA2F(regXD dst, memory mem) %{ 7233 predicate(UseSSE>=1); 7234 match(Set dst (Load2F mem)); 7235 ins_cost(145); 7236 format %{ "MOVQ $dst,$mem\t! packed2F" %} 7237 ins_encode( movq_ld(dst, mem)); 7238 ins_pipe( pipe_slow ); 7239 %} 7240 7241 // Load Effective Address 7242 instruct leaP8(eRegP dst, indOffset8 mem) %{ 7243 match(Set dst mem); 7244 7245 ins_cost(110); 7246 format %{ "LEA $dst,$mem" %} 7247 opcode(0x8D); 7248 ins_encode( OpcP, RegMem(dst,mem)); 7249 ins_pipe( ialu_reg_reg_fat ); 7250 %} 7251 7252 instruct leaP32(eRegP dst, indOffset32 mem) %{ 7253 match(Set dst mem); 7254 7255 ins_cost(110); 7256 format %{ "LEA $dst,$mem" %} 7257 opcode(0x8D); 7258 ins_encode( OpcP, RegMem(dst,mem)); 7259 ins_pipe( ialu_reg_reg_fat ); 7260 %} 7261 7262 instruct leaPIdxOff(eRegP dst, indIndexOffset mem) %{ 7263 match(Set dst mem); 7264 7265 ins_cost(110); 7266 format %{ "LEA $dst,$mem" %} 7267 opcode(0x8D); 7268 ins_encode( OpcP, RegMem(dst,mem)); 7269 ins_pipe( ialu_reg_reg_fat ); 7270 %} 7271 7272 instruct leaPIdxScale(eRegP dst, indIndexScale mem) %{ 7273 match(Set dst mem); 7274 7275 ins_cost(110); 7276 format %{ "LEA $dst,$mem" %} 7277 opcode(0x8D); 7278 ins_encode( OpcP, RegMem(dst,mem)); 7279 ins_pipe( ialu_reg_reg_fat ); 7280 %} 7281 7282 instruct leaPIdxScaleOff(eRegP dst, indIndexScaleOffset mem) %{ 7283 match(Set dst mem); 7284 7285 ins_cost(110); 7286 format %{ "LEA $dst,$mem" %} 7287 opcode(0x8D); 7288 ins_encode( OpcP, RegMem(dst,mem)); 7289 ins_pipe( ialu_reg_reg_fat ); 7290 %} 7291 7292 // Load Constant 7293 instruct loadConI(eRegI dst, immI src) %{ 7294 match(Set dst src); 7295 7296 format %{ "MOV $dst,$src" %} 7297 ins_encode( LdImmI(dst, src) ); 7298 ins_pipe( ialu_reg_fat ); 7299 %} 7300 7301 // Load Constant zero 7302 instruct loadConI0(eRegI dst, immI0 src, eFlagsReg cr) %{ 7303 match(Set dst src); 7304 effect(KILL cr); 7305 7306 ins_cost(50); 7307 format %{ "XOR $dst,$dst" %} 7308 opcode(0x33); /* + rd */ 7309 ins_encode( OpcP, RegReg( dst, dst ) ); 7310 ins_pipe( ialu_reg ); 7311 %} 7312 7313 instruct loadConP(eRegP dst, immP src) %{ 7314 match(Set dst src); 7315 7316 format %{ "MOV $dst,$src" %} 7317 opcode(0xB8); /* + rd */ 7318 ins_encode( LdImmP(dst, src) ); 7319 ins_pipe( ialu_reg_fat ); 7320 %} 7321 7322 instruct loadConL(eRegL dst, immL src, eFlagsReg cr) %{ 7323 match(Set dst src); 7324 effect(KILL cr); 7325 ins_cost(200); 7326 format %{ "MOV $dst.lo,$src.lo\n\t" 7327 "MOV $dst.hi,$src.hi" %} 7328 opcode(0xB8); 7329 ins_encode( LdImmL_Lo(dst, src), LdImmL_Hi(dst, src) ); 7330 ins_pipe( ialu_reg_long_fat ); 7331 %} 7332 7333 instruct loadConL0(eRegL dst, immL0 src, eFlagsReg cr) %{ 7334 match(Set dst src); 7335 effect(KILL cr); 7336 ins_cost(150); 7337 format %{ "XOR $dst.lo,$dst.lo\n\t" 7338 "XOR $dst.hi,$dst.hi" %} 7339 opcode(0x33,0x33); 7340 ins_encode( RegReg_Lo(dst,dst), RegReg_Hi(dst, dst) ); 7341 ins_pipe( ialu_reg_long ); 7342 %} 7343 7344 // The instruction usage is guarded by predicate in operand immF(). 7345 instruct loadConF(regF dst, immF src) %{ 7346 match(Set dst src); 7347 ins_cost(125); 7348 7349 format %{ "FLD_S ST,$src\n\t" 7350 "FSTP $dst" %} 7351 opcode(0xD9, 0x00); /* D9 /0 */ 7352 ins_encode(LdImmF(src), Pop_Reg_F(dst) ); 7353 ins_pipe( fpu_reg_con ); 7354 %} 7355 7356 // The instruction usage is guarded by predicate in operand immXF(). 7357 instruct loadConX(regX dst, immXF con) %{ 7358 match(Set dst con); 7359 ins_cost(125); 7360 format %{ "MOVSS $dst,[$con]" %} 7361 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x10), LdImmX(dst, con)); 7362 ins_pipe( pipe_slow ); 7363 %} 7364 7365 // The instruction usage is guarded by predicate in operand immXF0(). 7366 instruct loadConX0(regX dst, immXF0 src) %{ 7367 match(Set dst src); 7368 ins_cost(100); 7369 format %{ "XORPS $dst,$dst\t# float 0.0" %} 7370 ins_encode( Opcode(0x0F), Opcode(0x57), RegReg(dst,dst)); 7371 ins_pipe( pipe_slow ); 7372 %} 7373 7374 // The instruction usage is guarded by predicate in operand immD(). 7375 instruct loadConD(regD dst, immD src) %{ 7376 match(Set dst src); 7377 ins_cost(125); 7378 7379 format %{ "FLD_D ST,$src\n\t" 7380 "FSTP $dst" %} 7381 ins_encode(LdImmD(src), Pop_Reg_D(dst) ); 7382 ins_pipe( fpu_reg_con ); 7383 %} 7384 7385 // The instruction usage is guarded by predicate in operand immXD(). 7386 instruct loadConXD(regXD dst, immXD con) %{ 7387 match(Set dst con); 7388 ins_cost(125); 7389 format %{ "MOVSD $dst,[$con]" %} 7390 ins_encode(load_conXD(dst, con)); 7391 ins_pipe( pipe_slow ); 7392 %} 7393 7394 // The instruction usage is guarded by predicate in operand immXD0(). 7395 instruct loadConXD0(regXD dst, immXD0 src) %{ 7396 match(Set dst src); 7397 ins_cost(100); 7398 format %{ "XORPD $dst,$dst\t# double 0.0" %} 7399 ins_encode( Opcode(0x66), Opcode(0x0F), Opcode(0x57), RegReg(dst,dst)); 7400 ins_pipe( pipe_slow ); 7401 %} 7402 7403 // Load Stack Slot 7404 instruct loadSSI(eRegI dst, stackSlotI src) %{ 7405 match(Set dst src); 7406 ins_cost(125); 7407 7408 format %{ "MOV $dst,$src" %} 7409 opcode(0x8B); 7410 ins_encode( OpcP, RegMem(dst,src)); 7411 ins_pipe( ialu_reg_mem ); 7412 %} 7413 7414 instruct loadSSL(eRegL dst, stackSlotL src) %{ 7415 match(Set dst src); 7416 7417 ins_cost(200); 7418 format %{ "MOV $dst,$src.lo\n\t" 7419 "MOV $dst+4,$src.hi" %} 7420 opcode(0x8B, 0x8B); 7421 ins_encode( OpcP, RegMem( dst, src ), OpcS, RegMem_Hi( dst, src ) ); 7422 ins_pipe( ialu_mem_long_reg ); 7423 %} 7424 7425 // Load Stack Slot 7426 instruct loadSSP(eRegP dst, stackSlotP src) %{ 7427 match(Set dst src); 7428 ins_cost(125); 7429 7430 format %{ "MOV $dst,$src" %} 7431 opcode(0x8B); 7432 ins_encode( OpcP, RegMem(dst,src)); 7433 ins_pipe( ialu_reg_mem ); 7434 %} 7435 7436 // Load Stack Slot 7437 instruct loadSSF(regF dst, stackSlotF src) %{ 7438 match(Set dst src); 7439 ins_cost(125); 7440 7441 format %{ "FLD_S $src\n\t" 7442 "FSTP $dst" %} 7443 opcode(0xD9); /* D9 /0, FLD m32real */ 7444 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src), 7445 Pop_Reg_F(dst) ); 7446 ins_pipe( fpu_reg_mem ); 7447 %} 7448 7449 // Load Stack Slot 7450 instruct loadSSD(regD dst, stackSlotD src) %{ 7451 match(Set dst src); 7452 ins_cost(125); 7453 7454 format %{ "FLD_D $src\n\t" 7455 "FSTP $dst" %} 7456 opcode(0xDD); /* DD /0, FLD m64real */ 7457 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src), 7458 Pop_Reg_D(dst) ); 7459 ins_pipe( fpu_reg_mem ); 7460 %} 7461 7462 // Prefetch instructions. 7463 // Must be safe to execute with invalid address (cannot fault). 7464 7465 instruct prefetchr0( memory mem ) %{ 7466 predicate(UseSSE==0 && !VM_Version::supports_3dnow()); 7467 match(PrefetchRead mem); 7468 ins_cost(0); 7469 size(0); 7470 format %{ "PREFETCHR (non-SSE is empty encoding)" %} 7471 ins_encode(); 7472 ins_pipe(empty); 7473 %} 7474 7475 instruct prefetchr( memory mem ) %{ 7476 predicate(UseSSE==0 && VM_Version::supports_3dnow() || ReadPrefetchInstr==3); 7477 match(PrefetchRead mem); 7478 ins_cost(100); 7479 7480 format %{ "PREFETCHR $mem\t! Prefetch into level 1 cache for read" %} 7481 opcode(0x0F, 0x0d); /* Opcode 0F 0d /0 */ 7482 ins_encode(OpcP, OpcS, RMopc_Mem(0x00,mem)); 7483 ins_pipe(ialu_mem); 7484 %} 7485 7486 instruct prefetchrNTA( memory mem ) %{ 7487 predicate(UseSSE>=1 && ReadPrefetchInstr==0); 7488 match(PrefetchRead mem); 7489 ins_cost(100); 7490 7491 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for read" %} 7492 opcode(0x0F, 0x18); /* Opcode 0F 18 /0 */ 7493 ins_encode(OpcP, OpcS, RMopc_Mem(0x00,mem)); 7494 ins_pipe(ialu_mem); 7495 %} 7496 7497 instruct prefetchrT0( memory mem ) %{ 7498 predicate(UseSSE>=1 && ReadPrefetchInstr==1); 7499 match(PrefetchRead mem); 7500 ins_cost(100); 7501 7502 format %{ "PREFETCHT0 $mem\t! Prefetch into L1 and L2 caches for read" %} 7503 opcode(0x0F, 0x18); /* Opcode 0F 18 /1 */ 7504 ins_encode(OpcP, OpcS, RMopc_Mem(0x01,mem)); 7505 ins_pipe(ialu_mem); 7506 %} 7507 7508 instruct prefetchrT2( memory mem ) %{ 7509 predicate(UseSSE>=1 && ReadPrefetchInstr==2); 7510 match(PrefetchRead mem); 7511 ins_cost(100); 7512 7513 format %{ "PREFETCHT2 $mem\t! Prefetch into L2 cache for read" %} 7514 opcode(0x0F, 0x18); /* Opcode 0F 18 /3 */ 7515 ins_encode(OpcP, OpcS, RMopc_Mem(0x03,mem)); 7516 ins_pipe(ialu_mem); 7517 %} 7518 7519 instruct prefetchw0( memory mem ) %{ 7520 predicate(UseSSE==0 && !VM_Version::supports_3dnow()); 7521 match(PrefetchWrite mem); 7522 ins_cost(0); 7523 size(0); 7524 format %{ "Prefetch (non-SSE is empty encoding)" %} 7525 ins_encode(); 7526 ins_pipe(empty); 7527 %} 7528 7529 instruct prefetchw( memory mem ) %{ 7530 predicate(UseSSE==0 && VM_Version::supports_3dnow() || AllocatePrefetchInstr==3); 7531 match( PrefetchWrite mem ); 7532 ins_cost(100); 7533 7534 format %{ "PREFETCHW $mem\t! Prefetch into L1 cache and mark modified" %} 7535 opcode(0x0F, 0x0D); /* Opcode 0F 0D /1 */ 7536 ins_encode(OpcP, OpcS, RMopc_Mem(0x01,mem)); 7537 ins_pipe(ialu_mem); 7538 %} 7539 7540 instruct prefetchwNTA( memory mem ) %{ 7541 predicate(UseSSE>=1 && AllocatePrefetchInstr==0); 7542 match(PrefetchWrite mem); 7543 ins_cost(100); 7544 7545 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for write" %} 7546 opcode(0x0F, 0x18); /* Opcode 0F 18 /0 */ 7547 ins_encode(OpcP, OpcS, RMopc_Mem(0x00,mem)); 7548 ins_pipe(ialu_mem); 7549 %} 7550 7551 instruct prefetchwT0( memory mem ) %{ 7552 predicate(UseSSE>=1 && AllocatePrefetchInstr==1); 7553 match(PrefetchWrite mem); 7554 ins_cost(100); 7555 7556 format %{ "PREFETCHT0 $mem\t! Prefetch into L1 and L2 caches for write" %} 7557 opcode(0x0F, 0x18); /* Opcode 0F 18 /1 */ 7558 ins_encode(OpcP, OpcS, RMopc_Mem(0x01,mem)); 7559 ins_pipe(ialu_mem); 7560 %} 7561 7562 instruct prefetchwT2( memory mem ) %{ 7563 predicate(UseSSE>=1 && AllocatePrefetchInstr==2); 7564 match(PrefetchWrite mem); 7565 ins_cost(100); 7566 7567 format %{ "PREFETCHT2 $mem\t! Prefetch into L2 cache for write" %} 7568 opcode(0x0F, 0x18); /* Opcode 0F 18 /3 */ 7569 ins_encode(OpcP, OpcS, RMopc_Mem(0x03,mem)); 7570 ins_pipe(ialu_mem); 7571 %} 7572 7573 //----------Store Instructions------------------------------------------------- 7574 7575 // Store Byte 7576 instruct storeB(memory mem, xRegI src) %{ 7577 match(Set mem (StoreB mem src)); 7578 7579 ins_cost(125); 7580 format %{ "MOV8 $mem,$src" %} 7581 opcode(0x88); 7582 ins_encode( OpcP, RegMem( src, mem ) ); 7583 ins_pipe( ialu_mem_reg ); 7584 %} 7585 7586 // Store Char/Short 7587 instruct storeC(memory mem, eRegI src) %{ 7588 match(Set mem (StoreC mem src)); 7589 7590 ins_cost(125); 7591 format %{ "MOV16 $mem,$src" %} 7592 opcode(0x89, 0x66); 7593 ins_encode( OpcS, OpcP, RegMem( src, mem ) ); 7594 ins_pipe( ialu_mem_reg ); 7595 %} 7596 7597 // Store Integer 7598 instruct storeI(memory mem, eRegI src) %{ 7599 match(Set mem (StoreI mem src)); 7600 7601 ins_cost(125); 7602 format %{ "MOV $mem,$src" %} 7603 opcode(0x89); 7604 ins_encode( OpcP, RegMem( src, mem ) ); 7605 ins_pipe( ialu_mem_reg ); 7606 %} 7607 7608 // Store Long 7609 instruct storeL(long_memory mem, eRegL src) %{ 7610 predicate(!((StoreLNode*)n)->require_atomic_access()); 7611 match(Set mem (StoreL mem src)); 7612 7613 ins_cost(200); 7614 format %{ "MOV $mem,$src.lo\n\t" 7615 "MOV $mem+4,$src.hi" %} 7616 opcode(0x89, 0x89); 7617 ins_encode( OpcP, RegMem( src, mem ), OpcS, RegMem_Hi( src, mem ) ); 7618 ins_pipe( ialu_mem_long_reg ); 7619 %} 7620 7621 // Volatile Store Long. Must be atomic, so move it into 7622 // the FP TOS and then do a 64-bit FIST. Has to probe the 7623 // target address before the store (for null-ptr checks) 7624 // so the memory operand is used twice in the encoding. 7625 instruct storeL_volatile(memory mem, stackSlotL src, eFlagsReg cr ) %{ 7626 predicate(UseSSE<=1 && ((StoreLNode*)n)->require_atomic_access()); 7627 match(Set mem (StoreL mem src)); 7628 effect( KILL cr ); 7629 ins_cost(400); 7630 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t" 7631 "FILD $src\n\t" 7632 "FISTp $mem\t # 64-bit atomic volatile long store" %} 7633 opcode(0x3B); 7634 ins_encode( OpcP, RegMem( EAX, mem ), enc_storeL_volatile(mem,src)); 7635 ins_pipe( fpu_reg_mem ); 7636 %} 7637 7638 instruct storeLX_volatile(memory mem, stackSlotL src, regXD tmp, eFlagsReg cr) %{ 7639 predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access()); 7640 match(Set mem (StoreL mem src)); 7641 effect( TEMP tmp, KILL cr ); 7642 ins_cost(380); 7643 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t" 7644 "MOVSD $tmp,$src\n\t" 7645 "MOVSD $mem,$tmp\t # 64-bit atomic volatile long store" %} 7646 opcode(0x3B); 7647 ins_encode( OpcP, RegMem( EAX, mem ), enc_storeLX_volatile(mem, src, tmp)); 7648 ins_pipe( pipe_slow ); 7649 %} 7650 7651 instruct storeLX_reg_volatile(memory mem, eRegL src, regXD tmp2, regXD tmp, eFlagsReg cr) %{ 7652 predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access()); 7653 match(Set mem (StoreL mem src)); 7654 effect( TEMP tmp2 , TEMP tmp, KILL cr ); 7655 ins_cost(360); 7656 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t" 7657 "MOVD $tmp,$src.lo\n\t" 7658 "MOVD $tmp2,$src.hi\n\t" 7659 "PUNPCKLDQ $tmp,$tmp2\n\t" 7660 "MOVSD $mem,$tmp\t # 64-bit atomic volatile long store" %} 7661 opcode(0x3B); 7662 ins_encode( OpcP, RegMem( EAX, mem ), enc_storeLX_reg_volatile(mem, src, tmp, tmp2)); 7663 ins_pipe( pipe_slow ); 7664 %} 7665 7666 // Store Pointer; for storing unknown oops and raw pointers 7667 instruct storeP(memory mem, anyRegP src) %{ 7668 match(Set mem (StoreP mem src)); 7669 7670 ins_cost(125); 7671 format %{ "MOV $mem,$src" %} 7672 opcode(0x89); 7673 ins_encode( OpcP, RegMem( src, mem ) ); 7674 ins_pipe( ialu_mem_reg ); 7675 %} 7676 7677 // Store Integer Immediate 7678 instruct storeImmI(memory mem, immI src) %{ 7679 match(Set mem (StoreI mem src)); 7680 7681 ins_cost(150); 7682 format %{ "MOV $mem,$src" %} 7683 opcode(0xC7); /* C7 /0 */ 7684 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32( src )); 7685 ins_pipe( ialu_mem_imm ); 7686 %} 7687 7688 // Store Short/Char Immediate 7689 instruct storeImmI16(memory mem, immI16 src) %{ 7690 predicate(UseStoreImmI16); 7691 match(Set mem (StoreC mem src)); 7692 7693 ins_cost(150); 7694 format %{ "MOV16 $mem,$src" %} 7695 opcode(0xC7); /* C7 /0 Same as 32 store immediate with prefix */ 7696 ins_encode( SizePrefix, OpcP, RMopc_Mem(0x00,mem), Con16( src )); 7697 ins_pipe( ialu_mem_imm ); 7698 %} 7699 7700 // Store Pointer Immediate; null pointers or constant oops that do not 7701 // need card-mark barriers. 7702 instruct storeImmP(memory mem, immP src) %{ 7703 match(Set mem (StoreP mem src)); 7704 7705 ins_cost(150); 7706 format %{ "MOV $mem,$src" %} 7707 opcode(0xC7); /* C7 /0 */ 7708 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32( src )); 7709 ins_pipe( ialu_mem_imm ); 7710 %} 7711 7712 // Store Byte Immediate 7713 instruct storeImmB(memory mem, immI8 src) %{ 7714 match(Set mem (StoreB mem src)); 7715 7716 ins_cost(150); 7717 format %{ "MOV8 $mem,$src" %} 7718 opcode(0xC6); /* C6 /0 */ 7719 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con8or32( src )); 7720 ins_pipe( ialu_mem_imm ); 7721 %} 7722 7723 // Store Aligned Packed Byte XMM register to memory 7724 instruct storeA8B(memory mem, regXD src) %{ 7725 predicate(UseSSE>=1); 7726 match(Set mem (Store8B mem src)); 7727 ins_cost(145); 7728 format %{ "MOVQ $mem,$src\t! packed8B" %} 7729 ins_encode( movq_st(mem, src)); 7730 ins_pipe( pipe_slow ); 7731 %} 7732 7733 // Store Aligned Packed Char/Short XMM register to memory 7734 instruct storeA4C(memory mem, regXD src) %{ 7735 predicate(UseSSE>=1); 7736 match(Set mem (Store4C mem src)); 7737 ins_cost(145); 7738 format %{ "MOVQ $mem,$src\t! packed4C" %} 7739 ins_encode( movq_st(mem, src)); 7740 ins_pipe( pipe_slow ); 7741 %} 7742 7743 // Store Aligned Packed Integer XMM register to memory 7744 instruct storeA2I(memory mem, regXD src) %{ 7745 predicate(UseSSE>=1); 7746 match(Set mem (Store2I mem src)); 7747 ins_cost(145); 7748 format %{ "MOVQ $mem,$src\t! packed2I" %} 7749 ins_encode( movq_st(mem, src)); 7750 ins_pipe( pipe_slow ); 7751 %} 7752 7753 // Store CMS card-mark Immediate 7754 instruct storeImmCM(memory mem, immI8 src) %{ 7755 match(Set mem (StoreCM mem src)); 7756 7757 ins_cost(150); 7758 format %{ "MOV8 $mem,$src\t! CMS card-mark imm0" %} 7759 opcode(0xC6); /* C6 /0 */ 7760 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con8or32( src )); 7761 ins_pipe( ialu_mem_imm ); 7762 %} 7763 7764 // Store Double 7765 instruct storeD( memory mem, regDPR1 src) %{ 7766 predicate(UseSSE<=1); 7767 match(Set mem (StoreD mem src)); 7768 7769 ins_cost(100); 7770 format %{ "FST_D $mem,$src" %} 7771 opcode(0xDD); /* DD /2 */ 7772 ins_encode( enc_FP_store(mem,src) ); 7773 ins_pipe( fpu_mem_reg ); 7774 %} 7775 7776 // Store double does rounding on x86 7777 instruct storeD_rounded( memory mem, regDPR1 src) %{ 7778 predicate(UseSSE<=1); 7779 match(Set mem (StoreD mem (RoundDouble src))); 7780 7781 ins_cost(100); 7782 format %{ "FST_D $mem,$src\t# round" %} 7783 opcode(0xDD); /* DD /2 */ 7784 ins_encode( enc_FP_store(mem,src) ); 7785 ins_pipe( fpu_mem_reg ); 7786 %} 7787 7788 // Store XMM register to memory (double-precision floating points) 7789 // MOVSD instruction 7790 instruct storeXD(memory mem, regXD src) %{ 7791 predicate(UseSSE>=2); 7792 match(Set mem (StoreD mem src)); 7793 ins_cost(95); 7794 format %{ "MOVSD $mem,$src" %} 7795 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x11), RegMem(src, mem)); 7796 ins_pipe( pipe_slow ); 7797 %} 7798 7799 // Store XMM register to memory (single-precision floating point) 7800 // MOVSS instruction 7801 instruct storeX(memory mem, regX src) %{ 7802 predicate(UseSSE>=1); 7803 match(Set mem (StoreF mem src)); 7804 ins_cost(95); 7805 format %{ "MOVSS $mem,$src" %} 7806 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x11), RegMem(src, mem)); 7807 ins_pipe( pipe_slow ); 7808 %} 7809 7810 // Store Aligned Packed Single Float XMM register to memory 7811 instruct storeA2F(memory mem, regXD src) %{ 7812 predicate(UseSSE>=1); 7813 match(Set mem (Store2F mem src)); 7814 ins_cost(145); 7815 format %{ "MOVQ $mem,$src\t! packed2F" %} 7816 ins_encode( movq_st(mem, src)); 7817 ins_pipe( pipe_slow ); 7818 %} 7819 7820 // Store Float 7821 instruct storeF( memory mem, regFPR1 src) %{ 7822 predicate(UseSSE==0); 7823 match(Set mem (StoreF mem src)); 7824 7825 ins_cost(100); 7826 format %{ "FST_S $mem,$src" %} 7827 opcode(0xD9); /* D9 /2 */ 7828 ins_encode( enc_FP_store(mem,src) ); 7829 ins_pipe( fpu_mem_reg ); 7830 %} 7831 7832 // Store Float does rounding on x86 7833 instruct storeF_rounded( memory mem, regFPR1 src) %{ 7834 predicate(UseSSE==0); 7835 match(Set mem (StoreF mem (RoundFloat src))); 7836 7837 ins_cost(100); 7838 format %{ "FST_S $mem,$src\t# round" %} 7839 opcode(0xD9); /* D9 /2 */ 7840 ins_encode( enc_FP_store(mem,src) ); 7841 ins_pipe( fpu_mem_reg ); 7842 %} 7843 7844 // Store Float does rounding on x86 7845 instruct storeF_Drounded( memory mem, regDPR1 src) %{ 7846 predicate(UseSSE<=1); 7847 match(Set mem (StoreF mem (ConvD2F src))); 7848 7849 ins_cost(100); 7850 format %{ "FST_S $mem,$src\t# D-round" %} 7851 opcode(0xD9); /* D9 /2 */ 7852 ins_encode( enc_FP_store(mem,src) ); 7853 ins_pipe( fpu_mem_reg ); 7854 %} 7855 7856 // Store immediate Float value (it is faster than store from FPU register) 7857 // The instruction usage is guarded by predicate in operand immF(). 7858 instruct storeF_imm( memory mem, immF src) %{ 7859 match(Set mem (StoreF mem src)); 7860 7861 ins_cost(50); 7862 format %{ "MOV $mem,$src\t# store float" %} 7863 opcode(0xC7); /* C7 /0 */ 7864 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32F_as_bits( src )); 7865 ins_pipe( ialu_mem_imm ); 7866 %} 7867 7868 // Store immediate Float value (it is faster than store from XMM register) 7869 // The instruction usage is guarded by predicate in operand immXF(). 7870 instruct storeX_imm( memory mem, immXF src) %{ 7871 match(Set mem (StoreF mem src)); 7872 7873 ins_cost(50); 7874 format %{ "MOV $mem,$src\t# store float" %} 7875 opcode(0xC7); /* C7 /0 */ 7876 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32XF_as_bits( src )); 7877 ins_pipe( ialu_mem_imm ); 7878 %} 7879 7880 // Store Integer to stack slot 7881 instruct storeSSI(stackSlotI dst, eRegI src) %{ 7882 match(Set dst src); 7883 7884 ins_cost(100); 7885 format %{ "MOV $dst,$src" %} 7886 opcode(0x89); 7887 ins_encode( OpcPRegSS( dst, src ) ); 7888 ins_pipe( ialu_mem_reg ); 7889 %} 7890 7891 // Store Integer to stack slot 7892 instruct storeSSP(stackSlotP dst, eRegP src) %{ 7893 match(Set dst src); 7894 7895 ins_cost(100); 7896 format %{ "MOV $dst,$src" %} 7897 opcode(0x89); 7898 ins_encode( OpcPRegSS( dst, src ) ); 7899 ins_pipe( ialu_mem_reg ); 7900 %} 7901 7902 // Store Long to stack slot 7903 instruct storeSSL(stackSlotL dst, eRegL src) %{ 7904 match(Set dst src); 7905 7906 ins_cost(200); 7907 format %{ "MOV $dst,$src.lo\n\t" 7908 "MOV $dst+4,$src.hi" %} 7909 opcode(0x89, 0x89); 7910 ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) ); 7911 ins_pipe( ialu_mem_long_reg ); 7912 %} 7913 7914 //----------MemBar Instructions----------------------------------------------- 7915 // Memory barrier flavors 7916 7917 instruct membar_acquire() %{ 7918 match(MemBarAcquire); 7919 ins_cost(400); 7920 7921 size(0); 7922 format %{ "MEMBAR-acquire ! (empty encoding)" %} 7923 ins_encode(); 7924 ins_pipe(empty); 7925 %} 7926 7927 instruct membar_acquire_lock() %{ 7928 match(MemBarAcquire); 7929 predicate(Matcher::prior_fast_lock(n)); 7930 ins_cost(0); 7931 7932 size(0); 7933 format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)" %} 7934 ins_encode( ); 7935 ins_pipe(empty); 7936 %} 7937 7938 instruct membar_release() %{ 7939 match(MemBarRelease); 7940 ins_cost(400); 7941 7942 size(0); 7943 format %{ "MEMBAR-release ! (empty encoding)" %} 7944 ins_encode( ); 7945 ins_pipe(empty); 7946 %} 7947 7948 instruct membar_release_lock() %{ 7949 match(MemBarRelease); 7950 predicate(Matcher::post_fast_unlock(n)); 7951 ins_cost(0); 7952 7953 size(0); 7954 format %{ "MEMBAR-release (a FastUnlock follows so empty encoding)" %} 7955 ins_encode( ); 7956 ins_pipe(empty); 7957 %} 7958 7959 instruct membar_volatile(eFlagsReg cr) %{ 7960 match(MemBarVolatile); 7961 effect(KILL cr); 7962 ins_cost(400); 7963 7964 format %{ 7965 $$template 7966 if (os::is_MP()) { 7967 $$emit$$"LOCK ADDL [ESP + #0], 0\t! membar_volatile" 7968 } else { 7969 $$emit$$"MEMBAR-volatile ! (empty encoding)" 7970 } 7971 %} 7972 ins_encode %{ 7973 __ membar(Assembler::StoreLoad); 7974 %} 7975 ins_pipe(pipe_slow); 7976 %} 7977 7978 instruct unnecessary_membar_volatile() %{ 7979 match(MemBarVolatile); 7980 predicate(Matcher::post_store_load_barrier(n)); 7981 ins_cost(0); 7982 7983 size(0); 7984 format %{ "MEMBAR-volatile (unnecessary so empty encoding)" %} 7985 ins_encode( ); 7986 ins_pipe(empty); 7987 %} 7988 7989 //----------Move Instructions-------------------------------------------------- 7990 instruct castX2P(eAXRegP dst, eAXRegI src) %{ 7991 match(Set dst (CastX2P src)); 7992 format %{ "# X2P $dst, $src" %} 7993 ins_encode( /*empty encoding*/ ); 7994 ins_cost(0); 7995 ins_pipe(empty); 7996 %} 7997 7998 instruct castP2X(eRegI dst, eRegP src ) %{ 7999 match(Set dst (CastP2X src)); 8000 ins_cost(50); 8001 format %{ "MOV $dst, $src\t# CastP2X" %} 8002 ins_encode( enc_Copy( dst, src) ); 8003 ins_pipe( ialu_reg_reg ); 8004 %} 8005 8006 //----------Conditional Move--------------------------------------------------- 8007 // Conditional move 8008 instruct cmovI_reg(eRegI dst, eRegI src, eFlagsReg cr, cmpOp cop ) %{ 8009 predicate(VM_Version::supports_cmov() ); 8010 match(Set dst (CMoveI (Binary cop cr) (Binary dst src))); 8011 ins_cost(200); 8012 format %{ "CMOV$cop $dst,$src" %} 8013 opcode(0x0F,0x40); 8014 ins_encode( enc_cmov(cop), RegReg( dst, src ) ); 8015 ins_pipe( pipe_cmov_reg ); 8016 %} 8017 8018 instruct cmovI_regU( cmpOpU cop, eFlagsRegU cr, eRegI dst, eRegI src ) %{ 8019 predicate(VM_Version::supports_cmov() ); 8020 match(Set dst (CMoveI (Binary cop cr) (Binary dst src))); 8021 ins_cost(200); 8022 format %{ "CMOV$cop $dst,$src" %} 8023 opcode(0x0F,0x40); 8024 ins_encode( enc_cmov(cop), RegReg( dst, src ) ); 8025 ins_pipe( pipe_cmov_reg ); 8026 %} 8027 8028 instruct cmovI_regUCF( cmpOpUCF cop, eFlagsRegUCF cr, eRegI dst, eRegI src ) %{ 8029 predicate(VM_Version::supports_cmov() ); 8030 match(Set dst (CMoveI (Binary cop cr) (Binary dst src))); 8031 ins_cost(200); 8032 expand %{ 8033 cmovI_regU(cop, cr, dst, src); 8034 %} 8035 %} 8036 8037 // Conditional move 8038 instruct cmovI_mem(cmpOp cop, eFlagsReg cr, eRegI dst, memory src) %{ 8039 predicate(VM_Version::supports_cmov() ); 8040 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src)))); 8041 ins_cost(250); 8042 format %{ "CMOV$cop $dst,$src" %} 8043 opcode(0x0F,0x40); 8044 ins_encode( enc_cmov(cop), RegMem( dst, src ) ); 8045 ins_pipe( pipe_cmov_mem ); 8046 %} 8047 8048 // Conditional move 8049 instruct cmovI_memU(cmpOpU cop, eFlagsRegU cr, eRegI dst, memory src) %{ 8050 predicate(VM_Version::supports_cmov() ); 8051 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src)))); 8052 ins_cost(250); 8053 format %{ "CMOV$cop $dst,$src" %} 8054 opcode(0x0F,0x40); 8055 ins_encode( enc_cmov(cop), RegMem( dst, src ) ); 8056 ins_pipe( pipe_cmov_mem ); 8057 %} 8058 8059 instruct cmovI_memUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegI dst, memory src) %{ 8060 predicate(VM_Version::supports_cmov() ); 8061 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src)))); 8062 ins_cost(250); 8063 expand %{ 8064 cmovI_memU(cop, cr, dst, src); 8065 %} 8066 %} 8067 8068 // Conditional move 8069 instruct cmovP_reg(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{ 8070 predicate(VM_Version::supports_cmov() ); 8071 match(Set dst (CMoveP (Binary cop cr) (Binary dst src))); 8072 ins_cost(200); 8073 format %{ "CMOV$cop $dst,$src\t# ptr" %} 8074 opcode(0x0F,0x40); 8075 ins_encode( enc_cmov(cop), RegReg( dst, src ) ); 8076 ins_pipe( pipe_cmov_reg ); 8077 %} 8078 8079 // Conditional move (non-P6 version) 8080 // Note: a CMoveP is generated for stubs and native wrappers 8081 // regardless of whether we are on a P6, so we 8082 // emulate a cmov here 8083 instruct cmovP_reg_nonP6(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{ 8084 match(Set dst (CMoveP (Binary cop cr) (Binary dst src))); 8085 ins_cost(300); 8086 format %{ "Jn$cop skip\n\t" 8087 "MOV $dst,$src\t# pointer\n" 8088 "skip:" %} 8089 opcode(0x8b); 8090 ins_encode( enc_cmov_branch(cop, 0x2), OpcP, RegReg(dst, src)); 8091 ins_pipe( pipe_cmov_reg ); 8092 %} 8093 8094 // Conditional move 8095 instruct cmovP_regU(cmpOpU cop, eFlagsRegU cr, eRegP dst, eRegP src ) %{ 8096 predicate(VM_Version::supports_cmov() ); 8097 match(Set dst (CMoveP (Binary cop cr) (Binary dst src))); 8098 ins_cost(200); 8099 format %{ "CMOV$cop $dst,$src\t# ptr" %} 8100 opcode(0x0F,0x40); 8101 ins_encode( enc_cmov(cop), RegReg( dst, src ) ); 8102 ins_pipe( pipe_cmov_reg ); 8103 %} 8104 8105 instruct cmovP_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegP dst, eRegP src ) %{ 8106 predicate(VM_Version::supports_cmov() ); 8107 match(Set dst (CMoveP (Binary cop cr) (Binary dst src))); 8108 ins_cost(200); 8109 expand %{ 8110 cmovP_regU(cop, cr, dst, src); 8111 %} 8112 %} 8113 8114 // DISABLED: Requires the ADLC to emit a bottom_type call that 8115 // correctly meets the two pointer arguments; one is an incoming 8116 // register but the other is a memory operand. ALSO appears to 8117 // be buggy with implicit null checks. 8118 // 8119 //// Conditional move 8120 //instruct cmovP_mem(cmpOp cop, eFlagsReg cr, eRegP dst, memory src) %{ 8121 // predicate(VM_Version::supports_cmov() ); 8122 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src)))); 8123 // ins_cost(250); 8124 // format %{ "CMOV$cop $dst,$src\t# ptr" %} 8125 // opcode(0x0F,0x40); 8126 // ins_encode( enc_cmov(cop), RegMem( dst, src ) ); 8127 // ins_pipe( pipe_cmov_mem ); 8128 //%} 8129 // 8130 //// Conditional move 8131 //instruct cmovP_memU(cmpOpU cop, eFlagsRegU cr, eRegP dst, memory src) %{ 8132 // predicate(VM_Version::supports_cmov() ); 8133 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src)))); 8134 // ins_cost(250); 8135 // format %{ "CMOV$cop $dst,$src\t# ptr" %} 8136 // opcode(0x0F,0x40); 8137 // ins_encode( enc_cmov(cop), RegMem( dst, src ) ); 8138 // ins_pipe( pipe_cmov_mem ); 8139 //%} 8140 8141 // Conditional move 8142 instruct fcmovD_regU(cmpOp_fcmov cop, eFlagsRegU cr, regDPR1 dst, regD src) %{ 8143 predicate(UseSSE<=1); 8144 match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); 8145 ins_cost(200); 8146 format %{ "FCMOV$cop $dst,$src\t# double" %} 8147 opcode(0xDA); 8148 ins_encode( enc_cmov_d(cop,src) ); 8149 ins_pipe( pipe_cmovD_reg ); 8150 %} 8151 8152 // Conditional move 8153 instruct fcmovF_regU(cmpOp_fcmov cop, eFlagsRegU cr, regFPR1 dst, regF src) %{ 8154 predicate(UseSSE==0); 8155 match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); 8156 ins_cost(200); 8157 format %{ "FCMOV$cop $dst,$src\t# float" %} 8158 opcode(0xDA); 8159 ins_encode( enc_cmov_d(cop,src) ); 8160 ins_pipe( pipe_cmovD_reg ); 8161 %} 8162 8163 // Float CMOV on Intel doesn't handle *signed* compares, only unsigned. 8164 instruct fcmovD_regS(cmpOp cop, eFlagsReg cr, regD dst, regD src) %{ 8165 predicate(UseSSE<=1); 8166 match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); 8167 ins_cost(200); 8168 format %{ "Jn$cop skip\n\t" 8169 "MOV $dst,$src\t# double\n" 8170 "skip:" %} 8171 opcode (0xdd, 0x3); /* DD D8+i or DD /3 */ 8172 ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_D(src), OpcP, RegOpc(dst) ); 8173 ins_pipe( pipe_cmovD_reg ); 8174 %} 8175 8176 // Float CMOV on Intel doesn't handle *signed* compares, only unsigned. 8177 instruct fcmovF_regS(cmpOp cop, eFlagsReg cr, regF dst, regF src) %{ 8178 predicate(UseSSE==0); 8179 match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); 8180 ins_cost(200); 8181 format %{ "Jn$cop skip\n\t" 8182 "MOV $dst,$src\t# float\n" 8183 "skip:" %} 8184 opcode (0xdd, 0x3); /* DD D8+i or DD /3 */ 8185 ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_F(src), OpcP, RegOpc(dst) ); 8186 ins_pipe( pipe_cmovD_reg ); 8187 %} 8188 8189 // No CMOVE with SSE/SSE2 8190 instruct fcmovX_regS(cmpOp cop, eFlagsReg cr, regX dst, regX src) %{ 8191 predicate (UseSSE>=1); 8192 match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); 8193 ins_cost(200); 8194 format %{ "Jn$cop skip\n\t" 8195 "MOVSS $dst,$src\t# float\n" 8196 "skip:" %} 8197 ins_encode %{ 8198 Label skip; 8199 // Invert sense of branch from sense of CMOV 8200 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip); 8201 __ movflt($dst$$XMMRegister, $src$$XMMRegister); 8202 __ bind(skip); 8203 %} 8204 ins_pipe( pipe_slow ); 8205 %} 8206 8207 // No CMOVE with SSE/SSE2 8208 instruct fcmovXD_regS(cmpOp cop, eFlagsReg cr, regXD dst, regXD src) %{ 8209 predicate (UseSSE>=2); 8210 match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); 8211 ins_cost(200); 8212 format %{ "Jn$cop skip\n\t" 8213 "MOVSD $dst,$src\t# float\n" 8214 "skip:" %} 8215 ins_encode %{ 8216 Label skip; 8217 // Invert sense of branch from sense of CMOV 8218 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip); 8219 __ movdbl($dst$$XMMRegister, $src$$XMMRegister); 8220 __ bind(skip); 8221 %} 8222 ins_pipe( pipe_slow ); 8223 %} 8224 8225 // unsigned version 8226 instruct fcmovX_regU(cmpOpU cop, eFlagsRegU cr, regX dst, regX src) %{ 8227 predicate (UseSSE>=1); 8228 match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); 8229 ins_cost(200); 8230 format %{ "Jn$cop skip\n\t" 8231 "MOVSS $dst,$src\t# float\n" 8232 "skip:" %} 8233 ins_encode %{ 8234 Label skip; 8235 // Invert sense of branch from sense of CMOV 8236 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip); 8237 __ movflt($dst$$XMMRegister, $src$$XMMRegister); 8238 __ bind(skip); 8239 %} 8240 ins_pipe( pipe_slow ); 8241 %} 8242 8243 instruct fcmovX_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, regX dst, regX src) %{ 8244 predicate (UseSSE>=1); 8245 match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); 8246 ins_cost(200); 8247 expand %{ 8248 fcmovX_regU(cop, cr, dst, src); 8249 %} 8250 %} 8251 8252 // unsigned version 8253 instruct fcmovXD_regU(cmpOpU cop, eFlagsRegU cr, regXD dst, regXD src) %{ 8254 predicate (UseSSE>=2); 8255 match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); 8256 ins_cost(200); 8257 format %{ "Jn$cop skip\n\t" 8258 "MOVSD $dst,$src\t# float\n" 8259 "skip:" %} 8260 ins_encode %{ 8261 Label skip; 8262 // Invert sense of branch from sense of CMOV 8263 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip); 8264 __ movdbl($dst$$XMMRegister, $src$$XMMRegister); 8265 __ bind(skip); 8266 %} 8267 ins_pipe( pipe_slow ); 8268 %} 8269 8270 instruct fcmovXD_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, regXD dst, regXD src) %{ 8271 predicate (UseSSE>=2); 8272 match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); 8273 ins_cost(200); 8274 expand %{ 8275 fcmovXD_regU(cop, cr, dst, src); 8276 %} 8277 %} 8278 8279 instruct cmovL_reg(cmpOp cop, eFlagsReg cr, eRegL dst, eRegL src) %{ 8280 predicate(VM_Version::supports_cmov() ); 8281 match(Set dst (CMoveL (Binary cop cr) (Binary dst src))); 8282 ins_cost(200); 8283 format %{ "CMOV$cop $dst.lo,$src.lo\n\t" 8284 "CMOV$cop $dst.hi,$src.hi" %} 8285 opcode(0x0F,0x40); 8286 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) ); 8287 ins_pipe( pipe_cmov_reg_long ); 8288 %} 8289 8290 instruct cmovL_regU(cmpOpU cop, eFlagsRegU cr, eRegL dst, eRegL src) %{ 8291 predicate(VM_Version::supports_cmov() ); 8292 match(Set dst (CMoveL (Binary cop cr) (Binary dst src))); 8293 ins_cost(200); 8294 format %{ "CMOV$cop $dst.lo,$src.lo\n\t" 8295 "CMOV$cop $dst.hi,$src.hi" %} 8296 opcode(0x0F,0x40); 8297 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) ); 8298 ins_pipe( pipe_cmov_reg_long ); 8299 %} 8300 8301 instruct cmovL_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegL dst, eRegL src) %{ 8302 predicate(VM_Version::supports_cmov() ); 8303 match(Set dst (CMoveL (Binary cop cr) (Binary dst src))); 8304 ins_cost(200); 8305 expand %{ 8306 cmovL_regU(cop, cr, dst, src); 8307 %} 8308 %} 8309 8310 //----------Arithmetic Instructions-------------------------------------------- 8311 //----------Addition Instructions---------------------------------------------- 8312 // Integer Addition Instructions 8313 instruct addI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{ 8314 match(Set dst (AddI dst src)); 8315 effect(KILL cr); 8316 8317 size(2); 8318 format %{ "ADD $dst,$src" %} 8319 opcode(0x03); 8320 ins_encode( OpcP, RegReg( dst, src) ); 8321 ins_pipe( ialu_reg_reg ); 8322 %} 8323 8324 instruct addI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{ 8325 match(Set dst (AddI dst src)); 8326 effect(KILL cr); 8327 8328 format %{ "ADD $dst,$src" %} 8329 opcode(0x81, 0x00); /* /0 id */ 8330 ins_encode( OpcSErm( dst, src ), Con8or32( src ) ); 8331 ins_pipe( ialu_reg ); 8332 %} 8333 8334 instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{ 8335 predicate(UseIncDec); 8336 match(Set dst (AddI dst src)); 8337 effect(KILL cr); 8338 8339 size(1); 8340 format %{ "INC $dst" %} 8341 opcode(0x40); /* */ 8342 ins_encode( Opc_plus( primary, dst ) ); 8343 ins_pipe( ialu_reg ); 8344 %} 8345 8346 instruct leaI_eReg_immI(eRegI dst, eRegI src0, immI src1) %{ 8347 match(Set dst (AddI src0 src1)); 8348 ins_cost(110); 8349 8350 format %{ "LEA $dst,[$src0 + $src1]" %} 8351 opcode(0x8D); /* 0x8D /r */ 8352 ins_encode( OpcP, RegLea( dst, src0, src1 ) ); 8353 ins_pipe( ialu_reg_reg ); 8354 %} 8355 8356 instruct leaP_eReg_immI(eRegP dst, eRegP src0, immI src1) %{ 8357 match(Set dst (AddP src0 src1)); 8358 ins_cost(110); 8359 8360 format %{ "LEA $dst,[$src0 + $src1]\t# ptr" %} 8361 opcode(0x8D); /* 0x8D /r */ 8362 ins_encode( OpcP, RegLea( dst, src0, src1 ) ); 8363 ins_pipe( ialu_reg_reg ); 8364 %} 8365 8366 instruct decI_eReg(eRegI dst, immI_M1 src, eFlagsReg cr) %{ 8367 predicate(UseIncDec); 8368 match(Set dst (AddI dst src)); 8369 effect(KILL cr); 8370 8371 size(1); 8372 format %{ "DEC $dst" %} 8373 opcode(0x48); /* */ 8374 ins_encode( Opc_plus( primary, dst ) ); 8375 ins_pipe( ialu_reg ); 8376 %} 8377 8378 instruct addP_eReg(eRegP dst, eRegI src, eFlagsReg cr) %{ 8379 match(Set dst (AddP dst src)); 8380 effect(KILL cr); 8381 8382 size(2); 8383 format %{ "ADD $dst,$src" %} 8384 opcode(0x03); 8385 ins_encode( OpcP, RegReg( dst, src) ); 8386 ins_pipe( ialu_reg_reg ); 8387 %} 8388 8389 instruct addP_eReg_imm(eRegP dst, immI src, eFlagsReg cr) %{ 8390 match(Set dst (AddP dst src)); 8391 effect(KILL cr); 8392 8393 format %{ "ADD $dst,$src" %} 8394 opcode(0x81,0x00); /* Opcode 81 /0 id */ 8395 // ins_encode( RegImm( dst, src) ); 8396 ins_encode( OpcSErm( dst, src ), Con8or32( src ) ); 8397 ins_pipe( ialu_reg ); 8398 %} 8399 8400 instruct addI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{ 8401 match(Set dst (AddI dst (LoadI src))); 8402 effect(KILL cr); 8403 8404 ins_cost(125); 8405 format %{ "ADD $dst,$src" %} 8406 opcode(0x03); 8407 ins_encode( OpcP, RegMem( dst, src) ); 8408 ins_pipe( ialu_reg_mem ); 8409 %} 8410 8411 instruct addI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{ 8412 match(Set dst (StoreI dst (AddI (LoadI dst) src))); 8413 effect(KILL cr); 8414 8415 ins_cost(150); 8416 format %{ "ADD $dst,$src" %} 8417 opcode(0x01); /* Opcode 01 /r */ 8418 ins_encode( OpcP, RegMem( src, dst ) ); 8419 ins_pipe( ialu_mem_reg ); 8420 %} 8421 8422 // Add Memory with Immediate 8423 instruct addI_mem_imm(memory dst, immI src, eFlagsReg cr) %{ 8424 match(Set dst (StoreI dst (AddI (LoadI dst) src))); 8425 effect(KILL cr); 8426 8427 ins_cost(125); 8428 format %{ "ADD $dst,$src" %} 8429 opcode(0x81); /* Opcode 81 /0 id */ 8430 ins_encode( OpcSE( src ), RMopc_Mem(0x00,dst), Con8or32( src ) ); 8431 ins_pipe( ialu_mem_imm ); 8432 %} 8433 8434 instruct incI_mem(memory dst, immI1 src, eFlagsReg cr) %{ 8435 match(Set dst (StoreI dst (AddI (LoadI dst) src))); 8436 effect(KILL cr); 8437 8438 ins_cost(125); 8439 format %{ "INC $dst" %} 8440 opcode(0xFF); /* Opcode FF /0 */ 8441 ins_encode( OpcP, RMopc_Mem(0x00,dst)); 8442 ins_pipe( ialu_mem_imm ); 8443 %} 8444 8445 instruct decI_mem(memory dst, immI_M1 src, eFlagsReg cr) %{ 8446 match(Set dst (StoreI dst (AddI (LoadI dst) src))); 8447 effect(KILL cr); 8448 8449 ins_cost(125); 8450 format %{ "DEC $dst" %} 8451 opcode(0xFF); /* Opcode FF /1 */ 8452 ins_encode( OpcP, RMopc_Mem(0x01,dst)); 8453 ins_pipe( ialu_mem_imm ); 8454 %} 8455 8456 8457 instruct checkCastPP( eRegP dst ) %{ 8458 match(Set dst (CheckCastPP dst)); 8459 8460 size(0); 8461 format %{ "#checkcastPP of $dst" %} 8462 ins_encode( /*empty encoding*/ ); 8463 ins_pipe( empty ); 8464 %} 8465 8466 instruct castPP( eRegP dst ) %{ 8467 match(Set dst (CastPP dst)); 8468 format %{ "#castPP of $dst" %} 8469 ins_encode( /*empty encoding*/ ); 8470 ins_pipe( empty ); 8471 %} 8472 8473 instruct castII( eRegI dst ) %{ 8474 match(Set dst (CastII dst)); 8475 format %{ "#castII of $dst" %} 8476 ins_encode( /*empty encoding*/ ); 8477 ins_cost(0); 8478 ins_pipe( empty ); 8479 %} 8480 8481 8482 // Load-locked - same as a regular pointer load when used with compare-swap 8483 instruct loadPLocked(eRegP dst, memory mem) %{ 8484 match(Set dst (LoadPLocked mem)); 8485 8486 ins_cost(125); 8487 format %{ "MOV $dst,$mem\t# Load ptr. locked" %} 8488 opcode(0x8B); 8489 ins_encode( OpcP, RegMem(dst,mem)); 8490 ins_pipe( ialu_reg_mem ); 8491 %} 8492 8493 // LoadLong-locked - same as a volatile long load when used with compare-swap 8494 instruct loadLLocked(stackSlotL dst, load_long_memory mem) %{ 8495 predicate(UseSSE<=1); 8496 match(Set dst (LoadLLocked mem)); 8497 8498 ins_cost(200); 8499 format %{ "FILD $mem\t# Atomic volatile long load\n\t" 8500 "FISTp $dst" %} 8501 ins_encode(enc_loadL_volatile(mem,dst)); 8502 ins_pipe( fpu_reg_mem ); 8503 %} 8504 8505 instruct loadLX_Locked(stackSlotL dst, load_long_memory mem, regXD tmp) %{ 8506 predicate(UseSSE>=2); 8507 match(Set dst (LoadLLocked mem)); 8508 effect(TEMP tmp); 8509 ins_cost(180); 8510 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t" 8511 "MOVSD $dst,$tmp" %} 8512 ins_encode(enc_loadLX_volatile(mem, dst, tmp)); 8513 ins_pipe( pipe_slow ); 8514 %} 8515 8516 instruct loadLX_reg_Locked(eRegL dst, load_long_memory mem, regXD tmp) %{ 8517 predicate(UseSSE>=2); 8518 match(Set dst (LoadLLocked mem)); 8519 effect(TEMP tmp); 8520 ins_cost(160); 8521 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t" 8522 "MOVD $dst.lo,$tmp\n\t" 8523 "PSRLQ $tmp,32\n\t" 8524 "MOVD $dst.hi,$tmp" %} 8525 ins_encode(enc_loadLX_reg_volatile(mem, dst, tmp)); 8526 ins_pipe( pipe_slow ); 8527 %} 8528 8529 // Conditional-store of the updated heap-top. 8530 // Used during allocation of the shared heap. 8531 // Sets flags (EQ) on success. Implemented with a CMPXCHG on Intel. 8532 instruct storePConditional( memory heap_top_ptr, eAXRegP oldval, eRegP newval, eFlagsReg cr ) %{ 8533 match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval))); 8534 // EAX is killed if there is contention, but then it's also unused. 8535 // In the common case of no contention, EAX holds the new oop address. 8536 format %{ "CMPXCHG $heap_top_ptr,$newval\t# If EAX==$heap_top_ptr Then store $newval into $heap_top_ptr" %} 8537 ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval,heap_top_ptr) ); 8538 ins_pipe( pipe_cmpxchg ); 8539 %} 8540 8541 // Conditional-store of an int value. 8542 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG on Intel. 8543 instruct storeIConditional( memory mem, eAXRegI oldval, eRegI newval, eFlagsReg cr ) %{ 8544 match(Set cr (StoreIConditional mem (Binary oldval newval))); 8545 effect(KILL oldval); 8546 format %{ "CMPXCHG $mem,$newval\t# If EAX==$mem Then store $newval into $mem" %} 8547 ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval, mem) ); 8548 ins_pipe( pipe_cmpxchg ); 8549 %} 8550 8551 // Conditional-store of a long value. 8552 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG8 on Intel. 8553 instruct storeLConditional( memory mem, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{ 8554 match(Set cr (StoreLConditional mem (Binary oldval newval))); 8555 effect(KILL oldval); 8556 format %{ "XCHG EBX,ECX\t# correct order for CMPXCHG8 instruction\n\t" 8557 "CMPXCHG8 $mem,ECX:EBX\t# If EDX:EAX==$mem Then store ECX:EBX into $mem\n\t" 8558 "XCHG EBX,ECX" 8559 %} 8560 ins_encode %{ 8561 // Note: we need to swap rbx, and rcx before and after the 8562 // cmpxchg8 instruction because the instruction uses 8563 // rcx as the high order word of the new value to store but 8564 // our register encoding uses rbx. 8565 __ xchgl(as_Register(EBX_enc), as_Register(ECX_enc)); 8566 if( os::is_MP() ) 8567 __ lock(); 8568 __ cmpxchg8($mem$$Address); 8569 __ xchgl(as_Register(EBX_enc), as_Register(ECX_enc)); 8570 %} 8571 ins_pipe( pipe_cmpxchg ); 8572 %} 8573 8574 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them 8575 8576 instruct compareAndSwapL( eRegI res, eSIRegP mem_ptr, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{ 8577 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval))); 8578 effect(KILL cr, KILL oldval); 8579 format %{ "CMPXCHG8 [$mem_ptr],$newval\t# If EDX:EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t" 8580 "MOV $res,0\n\t" 8581 "JNE,s fail\n\t" 8582 "MOV $res,1\n" 8583 "fail:" %} 8584 ins_encode( enc_cmpxchg8(mem_ptr), 8585 enc_flags_ne_to_boolean(res) ); 8586 ins_pipe( pipe_cmpxchg ); 8587 %} 8588 8589 instruct compareAndSwapP( eRegI res, pRegP mem_ptr, eAXRegP oldval, eCXRegP newval, eFlagsReg cr) %{ 8590 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval))); 8591 effect(KILL cr, KILL oldval); 8592 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t" 8593 "MOV $res,0\n\t" 8594 "JNE,s fail\n\t" 8595 "MOV $res,1\n" 8596 "fail:" %} 8597 ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) ); 8598 ins_pipe( pipe_cmpxchg ); 8599 %} 8600 8601 instruct compareAndSwapI( eRegI res, pRegP mem_ptr, eAXRegI oldval, eCXRegI newval, eFlagsReg cr) %{ 8602 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval))); 8603 effect(KILL cr, KILL oldval); 8604 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t" 8605 "MOV $res,0\n\t" 8606 "JNE,s fail\n\t" 8607 "MOV $res,1\n" 8608 "fail:" %} 8609 ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) ); 8610 ins_pipe( pipe_cmpxchg ); 8611 %} 8612 8613 //----------Subtraction Instructions------------------------------------------- 8614 // Integer Subtraction Instructions 8615 instruct subI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{ 8616 match(Set dst (SubI dst src)); 8617 effect(KILL cr); 8618 8619 size(2); 8620 format %{ "SUB $dst,$src" %} 8621 opcode(0x2B); 8622 ins_encode( OpcP, RegReg( dst, src) ); 8623 ins_pipe( ialu_reg_reg ); 8624 %} 8625 8626 instruct subI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{ 8627 match(Set dst (SubI dst src)); 8628 effect(KILL cr); 8629 8630 format %{ "SUB $dst,$src" %} 8631 opcode(0x81,0x05); /* Opcode 81 /5 */ 8632 // ins_encode( RegImm( dst, src) ); 8633 ins_encode( OpcSErm( dst, src ), Con8or32( src ) ); 8634 ins_pipe( ialu_reg ); 8635 %} 8636 8637 instruct subI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{ 8638 match(Set dst (SubI dst (LoadI src))); 8639 effect(KILL cr); 8640 8641 ins_cost(125); 8642 format %{ "SUB $dst,$src" %} 8643 opcode(0x2B); 8644 ins_encode( OpcP, RegMem( dst, src) ); 8645 ins_pipe( ialu_reg_mem ); 8646 %} 8647 8648 instruct subI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{ 8649 match(Set dst (StoreI dst (SubI (LoadI dst) src))); 8650 effect(KILL cr); 8651 8652 ins_cost(150); 8653 format %{ "SUB $dst,$src" %} 8654 opcode(0x29); /* Opcode 29 /r */ 8655 ins_encode( OpcP, RegMem( src, dst ) ); 8656 ins_pipe( ialu_mem_reg ); 8657 %} 8658 8659 // Subtract from a pointer 8660 instruct subP_eReg(eRegP dst, eRegI src, immI0 zero, eFlagsReg cr) %{ 8661 match(Set dst (AddP dst (SubI zero src))); 8662 effect(KILL cr); 8663 8664 size(2); 8665 format %{ "SUB $dst,$src" %} 8666 opcode(0x2B); 8667 ins_encode( OpcP, RegReg( dst, src) ); 8668 ins_pipe( ialu_reg_reg ); 8669 %} 8670 8671 instruct negI_eReg(eRegI dst, immI0 zero, eFlagsReg cr) %{ 8672 match(Set dst (SubI zero dst)); 8673 effect(KILL cr); 8674 8675 size(2); 8676 format %{ "NEG $dst" %} 8677 opcode(0xF7,0x03); // Opcode F7 /3 8678 ins_encode( OpcP, RegOpc( dst ) ); 8679 ins_pipe( ialu_reg ); 8680 %} 8681 8682 8683 //----------Multiplication/Division Instructions------------------------------- 8684 // Integer Multiplication Instructions 8685 // Multiply Register 8686 instruct mulI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{ 8687 match(Set dst (MulI dst src)); 8688 effect(KILL cr); 8689 8690 size(3); 8691 ins_cost(300); 8692 format %{ "IMUL $dst,$src" %} 8693 opcode(0xAF, 0x0F); 8694 ins_encode( OpcS, OpcP, RegReg( dst, src) ); 8695 ins_pipe( ialu_reg_reg_alu0 ); 8696 %} 8697 8698 // Multiply 32-bit Immediate 8699 instruct mulI_eReg_imm(eRegI dst, eRegI src, immI imm, eFlagsReg cr) %{ 8700 match(Set dst (MulI src imm)); 8701 effect(KILL cr); 8702 8703 ins_cost(300); 8704 format %{ "IMUL $dst,$src,$imm" %} 8705 opcode(0x69); /* 69 /r id */ 8706 ins_encode( OpcSE(imm), RegReg( dst, src ), Con8or32( imm ) ); 8707 ins_pipe( ialu_reg_reg_alu0 ); 8708 %} 8709 8710 instruct loadConL_low_only(eADXRegL_low_only dst, immL32 src, eFlagsReg cr) %{ 8711 match(Set dst src); 8712 effect(KILL cr); 8713 8714 // Note that this is artificially increased to make it more expensive than loadConL 8715 ins_cost(250); 8716 format %{ "MOV EAX,$src\t// low word only" %} 8717 opcode(0xB8); 8718 ins_encode( LdImmL_Lo(dst, src) ); 8719 ins_pipe( ialu_reg_fat ); 8720 %} 8721 8722 // Multiply by 32-bit Immediate, taking the shifted high order results 8723 // (special case for shift by 32) 8724 instruct mulI_imm_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32 cnt, eFlagsReg cr) %{ 8725 match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt))); 8726 predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL && 8727 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint && 8728 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint ); 8729 effect(USE src1, KILL cr); 8730 8731 // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only 8732 ins_cost(0*100 + 1*400 - 150); 8733 format %{ "IMUL EDX:EAX,$src1" %} 8734 ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) ); 8735 ins_pipe( pipe_slow ); 8736 %} 8737 8738 // Multiply by 32-bit Immediate, taking the shifted high order results 8739 instruct mulI_imm_RShift_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr) %{ 8740 match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt))); 8741 predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL && 8742 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint && 8743 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint ); 8744 effect(USE src1, KILL cr); 8745 8746 // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only 8747 ins_cost(1*100 + 1*400 - 150); 8748 format %{ "IMUL EDX:EAX,$src1\n\t" 8749 "SAR EDX,$cnt-32" %} 8750 ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) ); 8751 ins_pipe( pipe_slow ); 8752 %} 8753 8754 // Multiply Memory 32-bit Immediate 8755 instruct mulI_mem_imm(eRegI dst, memory src, immI imm, eFlagsReg cr) %{ 8756 match(Set dst (MulI (LoadI src) imm)); 8757 effect(KILL cr); 8758 8759 ins_cost(300); 8760 format %{ "IMUL $dst,$src,$imm" %} 8761 opcode(0x69); /* 69 /r id */ 8762 ins_encode( OpcSE(imm), RegMem( dst, src ), Con8or32( imm ) ); 8763 ins_pipe( ialu_reg_mem_alu0 ); 8764 %} 8765 8766 // Multiply Memory 8767 instruct mulI(eRegI dst, memory src, eFlagsReg cr) %{ 8768 match(Set dst (MulI dst (LoadI src))); 8769 effect(KILL cr); 8770 8771 ins_cost(350); 8772 format %{ "IMUL $dst,$src" %} 8773 opcode(0xAF, 0x0F); 8774 ins_encode( OpcS, OpcP, RegMem( dst, src) ); 8775 ins_pipe( ialu_reg_mem_alu0 ); 8776 %} 8777 8778 // Multiply Register Int to Long 8779 instruct mulI2L(eADXRegL dst, eAXRegI src, nadxRegI src1, eFlagsReg flags) %{ 8780 // Basic Idea: long = (long)int * (long)int 8781 match(Set dst (MulL (ConvI2L src) (ConvI2L src1))); 8782 effect(DEF dst, USE src, USE src1, KILL flags); 8783 8784 ins_cost(300); 8785 format %{ "IMUL $dst,$src1" %} 8786 8787 ins_encode( long_int_multiply( dst, src1 ) ); 8788 ins_pipe( ialu_reg_reg_alu0 ); 8789 %} 8790 8791 instruct mulIS_eReg(eADXRegL dst, immL_32bits mask, eFlagsReg flags, eAXRegI src, nadxRegI src1) %{ 8792 // Basic Idea: long = (int & 0xffffffffL) * (int & 0xffffffffL) 8793 match(Set dst (MulL (AndL (ConvI2L src) mask) (AndL (ConvI2L src1) mask))); 8794 effect(KILL flags); 8795 8796 ins_cost(300); 8797 format %{ "MUL $dst,$src1" %} 8798 8799 ins_encode( long_uint_multiply(dst, src1) ); 8800 ins_pipe( ialu_reg_reg_alu0 ); 8801 %} 8802 8803 // Multiply Register Long 8804 instruct mulL_eReg(eADXRegL dst, eRegL src, eRegI tmp, eFlagsReg cr) %{ 8805 match(Set dst (MulL dst src)); 8806 effect(KILL cr, TEMP tmp); 8807 ins_cost(4*100+3*400); 8808 // Basic idea: lo(result) = lo(x_lo * y_lo) 8809 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi) 8810 format %{ "MOV $tmp,$src.lo\n\t" 8811 "IMUL $tmp,EDX\n\t" 8812 "MOV EDX,$src.hi\n\t" 8813 "IMUL EDX,EAX\n\t" 8814 "ADD $tmp,EDX\n\t" 8815 "MUL EDX:EAX,$src.lo\n\t" 8816 "ADD EDX,$tmp" %} 8817 ins_encode( long_multiply( dst, src, tmp ) ); 8818 ins_pipe( pipe_slow ); 8819 %} 8820 8821 // Multiply Register Long by small constant 8822 instruct mulL_eReg_con(eADXRegL dst, immL_127 src, eRegI tmp, eFlagsReg cr) %{ 8823 match(Set dst (MulL dst src)); 8824 effect(KILL cr, TEMP tmp); 8825 ins_cost(2*100+2*400); 8826 size(12); 8827 // Basic idea: lo(result) = lo(src * EAX) 8828 // hi(result) = hi(src * EAX) + lo(src * EDX) 8829 format %{ "IMUL $tmp,EDX,$src\n\t" 8830 "MOV EDX,$src\n\t" 8831 "MUL EDX\t# EDX*EAX -> EDX:EAX\n\t" 8832 "ADD EDX,$tmp" %} 8833 ins_encode( long_multiply_con( dst, src, tmp ) ); 8834 ins_pipe( pipe_slow ); 8835 %} 8836 8837 // Integer DIV with Register 8838 instruct divI_eReg(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{ 8839 match(Set rax (DivI rax div)); 8840 effect(KILL rdx, KILL cr); 8841 size(26); 8842 ins_cost(30*100+10*100); 8843 format %{ "CMP EAX,0x80000000\n\t" 8844 "JNE,s normal\n\t" 8845 "XOR EDX,EDX\n\t" 8846 "CMP ECX,-1\n\t" 8847 "JE,s done\n" 8848 "normal: CDQ\n\t" 8849 "IDIV $div\n\t" 8850 "done:" %} 8851 opcode(0xF7, 0x7); /* Opcode F7 /7 */ 8852 ins_encode( cdq_enc, OpcP, RegOpc(div) ); 8853 ins_pipe( ialu_reg_reg_alu0 ); 8854 %} 8855 8856 // Divide Register Long 8857 instruct divL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{ 8858 match(Set dst (DivL src1 src2)); 8859 effect( KILL cr, KILL cx, KILL bx ); 8860 ins_cost(10000); 8861 format %{ "PUSH $src1.hi\n\t" 8862 "PUSH $src1.lo\n\t" 8863 "PUSH $src2.hi\n\t" 8864 "PUSH $src2.lo\n\t" 8865 "CALL SharedRuntime::ldiv\n\t" 8866 "ADD ESP,16" %} 8867 ins_encode( long_div(src1,src2) ); 8868 ins_pipe( pipe_slow ); 8869 %} 8870 8871 // Integer DIVMOD with Register, both quotient and mod results 8872 instruct divModI_eReg_divmod(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{ 8873 match(DivModI rax div); 8874 effect(KILL cr); 8875 size(26); 8876 ins_cost(30*100+10*100); 8877 format %{ "CMP EAX,0x80000000\n\t" 8878 "JNE,s normal\n\t" 8879 "XOR EDX,EDX\n\t" 8880 "CMP ECX,-1\n\t" 8881 "JE,s done\n" 8882 "normal: CDQ\n\t" 8883 "IDIV $div\n\t" 8884 "done:" %} 8885 opcode(0xF7, 0x7); /* Opcode F7 /7 */ 8886 ins_encode( cdq_enc, OpcP, RegOpc(div) ); 8887 ins_pipe( pipe_slow ); 8888 %} 8889 8890 // Integer MOD with Register 8891 instruct modI_eReg(eDXRegI rdx, eAXRegI rax, eCXRegI div, eFlagsReg cr) %{ 8892 match(Set rdx (ModI rax div)); 8893 effect(KILL rax, KILL cr); 8894 8895 size(26); 8896 ins_cost(300); 8897 format %{ "CDQ\n\t" 8898 "IDIV $div" %} 8899 opcode(0xF7, 0x7); /* Opcode F7 /7 */ 8900 ins_encode( cdq_enc, OpcP, RegOpc(div) ); 8901 ins_pipe( ialu_reg_reg_alu0 ); 8902 %} 8903 8904 // Remainder Register Long 8905 instruct modL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{ 8906 match(Set dst (ModL src1 src2)); 8907 effect( KILL cr, KILL cx, KILL bx ); 8908 ins_cost(10000); 8909 format %{ "PUSH $src1.hi\n\t" 8910 "PUSH $src1.lo\n\t" 8911 "PUSH $src2.hi\n\t" 8912 "PUSH $src2.lo\n\t" 8913 "CALL SharedRuntime::lrem\n\t" 8914 "ADD ESP,16" %} 8915 ins_encode( long_mod(src1,src2) ); 8916 ins_pipe( pipe_slow ); 8917 %} 8918 8919 // Integer Shift Instructions 8920 // Shift Left by one 8921 instruct shlI_eReg_1(eRegI dst, immI1 shift, eFlagsReg cr) %{ 8922 match(Set dst (LShiftI dst shift)); 8923 effect(KILL cr); 8924 8925 size(2); 8926 format %{ "SHL $dst,$shift" %} 8927 opcode(0xD1, 0x4); /* D1 /4 */ 8928 ins_encode( OpcP, RegOpc( dst ) ); 8929 ins_pipe( ialu_reg ); 8930 %} 8931 8932 // Shift Left by 8-bit immediate 8933 instruct salI_eReg_imm(eRegI dst, immI8 shift, eFlagsReg cr) %{ 8934 match(Set dst (LShiftI dst shift)); 8935 effect(KILL cr); 8936 8937 size(3); 8938 format %{ "SHL $dst,$shift" %} 8939 opcode(0xC1, 0x4); /* C1 /4 ib */ 8940 ins_encode( RegOpcImm( dst, shift) ); 8941 ins_pipe( ialu_reg ); 8942 %} 8943 8944 // Shift Left by variable 8945 instruct salI_eReg_CL(eRegI dst, eCXRegI shift, eFlagsReg cr) %{ 8946 match(Set dst (LShiftI dst shift)); 8947 effect(KILL cr); 8948 8949 size(2); 8950 format %{ "SHL $dst,$shift" %} 8951 opcode(0xD3, 0x4); /* D3 /4 */ 8952 ins_encode( OpcP, RegOpc( dst ) ); 8953 ins_pipe( ialu_reg_reg ); 8954 %} 8955 8956 // Arithmetic shift right by one 8957 instruct sarI_eReg_1(eRegI dst, immI1 shift, eFlagsReg cr) %{ 8958 match(Set dst (RShiftI dst shift)); 8959 effect(KILL cr); 8960 8961 size(2); 8962 format %{ "SAR $dst,$shift" %} 8963 opcode(0xD1, 0x7); /* D1 /7 */ 8964 ins_encode( OpcP, RegOpc( dst ) ); 8965 ins_pipe( ialu_reg ); 8966 %} 8967 8968 // Arithmetic shift right by one 8969 instruct sarI_mem_1(memory dst, immI1 shift, eFlagsReg cr) %{ 8970 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift))); 8971 effect(KILL cr); 8972 format %{ "SAR $dst,$shift" %} 8973 opcode(0xD1, 0x7); /* D1 /7 */ 8974 ins_encode( OpcP, RMopc_Mem(secondary,dst) ); 8975 ins_pipe( ialu_mem_imm ); 8976 %} 8977 8978 // Arithmetic Shift Right by 8-bit immediate 8979 instruct sarI_eReg_imm(eRegI dst, immI8 shift, eFlagsReg cr) %{ 8980 match(Set dst (RShiftI dst shift)); 8981 effect(KILL cr); 8982 8983 size(3); 8984 format %{ "SAR $dst,$shift" %} 8985 opcode(0xC1, 0x7); /* C1 /7 ib */ 8986 ins_encode( RegOpcImm( dst, shift ) ); 8987 ins_pipe( ialu_mem_imm ); 8988 %} 8989 8990 // Arithmetic Shift Right by 8-bit immediate 8991 instruct sarI_mem_imm(memory dst, immI8 shift, eFlagsReg cr) %{ 8992 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift))); 8993 effect(KILL cr); 8994 8995 format %{ "SAR $dst,$shift" %} 8996 opcode(0xC1, 0x7); /* C1 /7 ib */ 8997 ins_encode( OpcP, RMopc_Mem(secondary, dst ), Con8or32( shift ) ); 8998 ins_pipe( ialu_mem_imm ); 8999 %} 9000 9001 // Arithmetic Shift Right by variable 9002 instruct sarI_eReg_CL(eRegI dst, eCXRegI shift, eFlagsReg cr) %{ 9003 match(Set dst (RShiftI dst shift)); 9004 effect(KILL cr); 9005 9006 size(2); 9007 format %{ "SAR $dst,$shift" %} 9008 opcode(0xD3, 0x7); /* D3 /7 */ 9009 ins_encode( OpcP, RegOpc( dst ) ); 9010 ins_pipe( ialu_reg_reg ); 9011 %} 9012 9013 // Logical shift right by one 9014 instruct shrI_eReg_1(eRegI dst, immI1 shift, eFlagsReg cr) %{ 9015 match(Set dst (URShiftI dst shift)); 9016 effect(KILL cr); 9017 9018 size(2); 9019 format %{ "SHR $dst,$shift" %} 9020 opcode(0xD1, 0x5); /* D1 /5 */ 9021 ins_encode( OpcP, RegOpc( dst ) ); 9022 ins_pipe( ialu_reg ); 9023 %} 9024 9025 // Logical Shift Right by 8-bit immediate 9026 instruct shrI_eReg_imm(eRegI dst, immI8 shift, eFlagsReg cr) %{ 9027 match(Set dst (URShiftI dst shift)); 9028 effect(KILL cr); 9029 9030 size(3); 9031 format %{ "SHR $dst,$shift" %} 9032 opcode(0xC1, 0x5); /* C1 /5 ib */ 9033 ins_encode( RegOpcImm( dst, shift) ); 9034 ins_pipe( ialu_reg ); 9035 %} 9036 9037 9038 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24. 9039 // This idiom is used by the compiler for the i2b bytecode. 9040 instruct i2b(eRegI dst, xRegI src, immI_24 twentyfour, eFlagsReg cr) %{ 9041 match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour)); 9042 effect(KILL cr); 9043 9044 size(3); 9045 format %{ "MOVSX $dst,$src :8" %} 9046 opcode(0xBE, 0x0F); 9047 ins_encode( OpcS, OpcP, RegReg( dst, src)); 9048 ins_pipe( ialu_reg_reg ); 9049 %} 9050 9051 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16. 9052 // This idiom is used by the compiler the i2s bytecode. 9053 instruct i2s(eRegI dst, xRegI src, immI_16 sixteen, eFlagsReg cr) %{ 9054 match(Set dst (RShiftI (LShiftI src sixteen) sixteen)); 9055 effect(KILL cr); 9056 9057 size(3); 9058 format %{ "MOVSX $dst,$src :16" %} 9059 opcode(0xBF, 0x0F); 9060 ins_encode( OpcS, OpcP, RegReg( dst, src)); 9061 ins_pipe( ialu_reg_reg ); 9062 %} 9063 9064 9065 // Logical Shift Right by variable 9066 instruct shrI_eReg_CL(eRegI dst, eCXRegI shift, eFlagsReg cr) %{ 9067 match(Set dst (URShiftI dst shift)); 9068 effect(KILL cr); 9069 9070 size(2); 9071 format %{ "SHR $dst,$shift" %} 9072 opcode(0xD3, 0x5); /* D3 /5 */ 9073 ins_encode( OpcP, RegOpc( dst ) ); 9074 ins_pipe( ialu_reg_reg ); 9075 %} 9076 9077 9078 //----------Logical Instructions----------------------------------------------- 9079 //----------Integer Logical Instructions--------------------------------------- 9080 // And Instructions 9081 // And Register with Register 9082 instruct andI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{ 9083 match(Set dst (AndI dst src)); 9084 effect(KILL cr); 9085 9086 size(2); 9087 format %{ "AND $dst,$src" %} 9088 opcode(0x23); 9089 ins_encode( OpcP, RegReg( dst, src) ); 9090 ins_pipe( ialu_reg_reg ); 9091 %} 9092 9093 // And Register with Immediate 9094 instruct andI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{ 9095 match(Set dst (AndI dst src)); 9096 effect(KILL cr); 9097 9098 format %{ "AND $dst,$src" %} 9099 opcode(0x81,0x04); /* Opcode 81 /4 */ 9100 // ins_encode( RegImm( dst, src) ); 9101 ins_encode( OpcSErm( dst, src ), Con8or32( src ) ); 9102 ins_pipe( ialu_reg ); 9103 %} 9104 9105 // And Register with Memory 9106 instruct andI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{ 9107 match(Set dst (AndI dst (LoadI src))); 9108 effect(KILL cr); 9109 9110 ins_cost(125); 9111 format %{ "AND $dst,$src" %} 9112 opcode(0x23); 9113 ins_encode( OpcP, RegMem( dst, src) ); 9114 ins_pipe( ialu_reg_mem ); 9115 %} 9116 9117 // And Memory with Register 9118 instruct andI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{ 9119 match(Set dst (StoreI dst (AndI (LoadI dst) src))); 9120 effect(KILL cr); 9121 9122 ins_cost(150); 9123 format %{ "AND $dst,$src" %} 9124 opcode(0x21); /* Opcode 21 /r */ 9125 ins_encode( OpcP, RegMem( src, dst ) ); 9126 ins_pipe( ialu_mem_reg ); 9127 %} 9128 9129 // And Memory with Immediate 9130 instruct andI_mem_imm(memory dst, immI src, eFlagsReg cr) %{ 9131 match(Set dst (StoreI dst (AndI (LoadI dst) src))); 9132 effect(KILL cr); 9133 9134 ins_cost(125); 9135 format %{ "AND $dst,$src" %} 9136 opcode(0x81, 0x4); /* Opcode 81 /4 id */ 9137 // ins_encode( MemImm( dst, src) ); 9138 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) ); 9139 ins_pipe( ialu_mem_imm ); 9140 %} 9141 9142 // Or Instructions 9143 // Or Register with Register 9144 instruct orI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{ 9145 match(Set dst (OrI dst src)); 9146 effect(KILL cr); 9147 9148 size(2); 9149 format %{ "OR $dst,$src" %} 9150 opcode(0x0B); 9151 ins_encode( OpcP, RegReg( dst, src) ); 9152 ins_pipe( ialu_reg_reg ); 9153 %} 9154 9155 instruct orI_eReg_castP2X(eRegI dst, eRegP src, eFlagsReg cr) %{ 9156 match(Set dst (OrI dst (CastP2X src))); 9157 effect(KILL cr); 9158 9159 size(2); 9160 format %{ "OR $dst,$src" %} 9161 opcode(0x0B); 9162 ins_encode( OpcP, RegReg( dst, src) ); 9163 ins_pipe( ialu_reg_reg ); 9164 %} 9165 9166 9167 // Or Register with Immediate 9168 instruct orI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{ 9169 match(Set dst (OrI dst src)); 9170 effect(KILL cr); 9171 9172 format %{ "OR $dst,$src" %} 9173 opcode(0x81,0x01); /* Opcode 81 /1 id */ 9174 // ins_encode( RegImm( dst, src) ); 9175 ins_encode( OpcSErm( dst, src ), Con8or32( src ) ); 9176 ins_pipe( ialu_reg ); 9177 %} 9178 9179 // Or Register with Memory 9180 instruct orI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{ 9181 match(Set dst (OrI dst (LoadI src))); 9182 effect(KILL cr); 9183 9184 ins_cost(125); 9185 format %{ "OR $dst,$src" %} 9186 opcode(0x0B); 9187 ins_encode( OpcP, RegMem( dst, src) ); 9188 ins_pipe( ialu_reg_mem ); 9189 %} 9190 9191 // Or Memory with Register 9192 instruct orI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{ 9193 match(Set dst (StoreI dst (OrI (LoadI dst) src))); 9194 effect(KILL cr); 9195 9196 ins_cost(150); 9197 format %{ "OR $dst,$src" %} 9198 opcode(0x09); /* Opcode 09 /r */ 9199 ins_encode( OpcP, RegMem( src, dst ) ); 9200 ins_pipe( ialu_mem_reg ); 9201 %} 9202 9203 // Or Memory with Immediate 9204 instruct orI_mem_imm(memory dst, immI src, eFlagsReg cr) %{ 9205 match(Set dst (StoreI dst (OrI (LoadI dst) src))); 9206 effect(KILL cr); 9207 9208 ins_cost(125); 9209 format %{ "OR $dst,$src" %} 9210 opcode(0x81,0x1); /* Opcode 81 /1 id */ 9211 // ins_encode( MemImm( dst, src) ); 9212 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) ); 9213 ins_pipe( ialu_mem_imm ); 9214 %} 9215 9216 // ROL/ROR 9217 // ROL expand 9218 instruct rolI_eReg_imm1(eRegI dst, immI1 shift, eFlagsReg cr) %{ 9219 effect(USE_DEF dst, USE shift, KILL cr); 9220 9221 format %{ "ROL $dst, $shift" %} 9222 opcode(0xD1, 0x0); /* Opcode D1 /0 */ 9223 ins_encode( OpcP, RegOpc( dst )); 9224 ins_pipe( ialu_reg ); 9225 %} 9226 9227 instruct rolI_eReg_imm8(eRegI dst, immI8 shift, eFlagsReg cr) %{ 9228 effect(USE_DEF dst, USE shift, KILL cr); 9229 9230 format %{ "ROL $dst, $shift" %} 9231 opcode(0xC1, 0x0); /*Opcode /C1 /0 */ 9232 ins_encode( RegOpcImm(dst, shift) ); 9233 ins_pipe(ialu_reg); 9234 %} 9235 9236 instruct rolI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr) %{ 9237 effect(USE_DEF dst, USE shift, KILL cr); 9238 9239 format %{ "ROL $dst, $shift" %} 9240 opcode(0xD3, 0x0); /* Opcode D3 /0 */ 9241 ins_encode(OpcP, RegOpc(dst)); 9242 ins_pipe( ialu_reg_reg ); 9243 %} 9244 // end of ROL expand 9245 9246 // ROL 32bit by one once 9247 instruct rolI_eReg_i1(eRegI dst, immI1 lshift, immI_M1 rshift, eFlagsReg cr) %{ 9248 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift))); 9249 9250 expand %{ 9251 rolI_eReg_imm1(dst, lshift, cr); 9252 %} 9253 %} 9254 9255 // ROL 32bit var by imm8 once 9256 instruct rolI_eReg_i8(eRegI dst, immI8 lshift, immI8 rshift, eFlagsReg cr) %{ 9257 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f)); 9258 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift))); 9259 9260 expand %{ 9261 rolI_eReg_imm8(dst, lshift, cr); 9262 %} 9263 %} 9264 9265 // ROL 32bit var by var once 9266 instruct rolI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{ 9267 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI zero shift)))); 9268 9269 expand %{ 9270 rolI_eReg_CL(dst, shift, cr); 9271 %} 9272 %} 9273 9274 // ROL 32bit var by var once 9275 instruct rolI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{ 9276 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI c32 shift)))); 9277 9278 expand %{ 9279 rolI_eReg_CL(dst, shift, cr); 9280 %} 9281 %} 9282 9283 // ROR expand 9284 instruct rorI_eReg_imm1(eRegI dst, immI1 shift, eFlagsReg cr) %{ 9285 effect(USE_DEF dst, USE shift, KILL cr); 9286 9287 format %{ "ROR $dst, $shift" %} 9288 opcode(0xD1,0x1); /* Opcode D1 /1 */ 9289 ins_encode( OpcP, RegOpc( dst ) ); 9290 ins_pipe( ialu_reg ); 9291 %} 9292 9293 instruct rorI_eReg_imm8(eRegI dst, immI8 shift, eFlagsReg cr) %{ 9294 effect (USE_DEF dst, USE shift, KILL cr); 9295 9296 format %{ "ROR $dst, $shift" %} 9297 opcode(0xC1, 0x1); /* Opcode /C1 /1 ib */ 9298 ins_encode( RegOpcImm(dst, shift) ); 9299 ins_pipe( ialu_reg ); 9300 %} 9301 9302 instruct rorI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr)%{ 9303 effect(USE_DEF dst, USE shift, KILL cr); 9304 9305 format %{ "ROR $dst, $shift" %} 9306 opcode(0xD3, 0x1); /* Opcode D3 /1 */ 9307 ins_encode(OpcP, RegOpc(dst)); 9308 ins_pipe( ialu_reg_reg ); 9309 %} 9310 // end of ROR expand 9311 9312 // ROR right once 9313 instruct rorI_eReg_i1(eRegI dst, immI1 rshift, immI_M1 lshift, eFlagsReg cr) %{ 9314 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift))); 9315 9316 expand %{ 9317 rorI_eReg_imm1(dst, rshift, cr); 9318 %} 9319 %} 9320 9321 // ROR 32bit by immI8 once 9322 instruct rorI_eReg_i8(eRegI dst, immI8 rshift, immI8 lshift, eFlagsReg cr) %{ 9323 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f)); 9324 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift))); 9325 9326 expand %{ 9327 rorI_eReg_imm8(dst, rshift, cr); 9328 %} 9329 %} 9330 9331 // ROR 32bit var by var once 9332 instruct rorI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{ 9333 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI zero shift)))); 9334 9335 expand %{ 9336 rorI_eReg_CL(dst, shift, cr); 9337 %} 9338 %} 9339 9340 // ROR 32bit var by var once 9341 instruct rorI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{ 9342 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI c32 shift)))); 9343 9344 expand %{ 9345 rorI_eReg_CL(dst, shift, cr); 9346 %} 9347 %} 9348 9349 // Xor Instructions 9350 // Xor Register with Register 9351 instruct xorI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{ 9352 match(Set dst (XorI dst src)); 9353 effect(KILL cr); 9354 9355 size(2); 9356 format %{ "XOR $dst,$src" %} 9357 opcode(0x33); 9358 ins_encode( OpcP, RegReg( dst, src) ); 9359 ins_pipe( ialu_reg_reg ); 9360 %} 9361 9362 // Xor Register with Immediate -1 9363 instruct xorI_eReg_im1(eRegI dst, immI_M1 imm) %{ 9364 match(Set dst (XorI dst imm)); 9365 9366 size(2); 9367 format %{ "NOT $dst" %} 9368 ins_encode %{ 9369 __ notl($dst$$Register); 9370 %} 9371 ins_pipe( ialu_reg ); 9372 %} 9373 9374 // Xor Register with Immediate 9375 instruct xorI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{ 9376 match(Set dst (XorI dst src)); 9377 effect(KILL cr); 9378 9379 format %{ "XOR $dst,$src" %} 9380 opcode(0x81,0x06); /* Opcode 81 /6 id */ 9381 // ins_encode( RegImm( dst, src) ); 9382 ins_encode( OpcSErm( dst, src ), Con8or32( src ) ); 9383 ins_pipe( ialu_reg ); 9384 %} 9385 9386 // Xor Register with Memory 9387 instruct xorI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{ 9388 match(Set dst (XorI dst (LoadI src))); 9389 effect(KILL cr); 9390 9391 ins_cost(125); 9392 format %{ "XOR $dst,$src" %} 9393 opcode(0x33); 9394 ins_encode( OpcP, RegMem(dst, src) ); 9395 ins_pipe( ialu_reg_mem ); 9396 %} 9397 9398 // Xor Memory with Register 9399 instruct xorI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{ 9400 match(Set dst (StoreI dst (XorI (LoadI dst) src))); 9401 effect(KILL cr); 9402 9403 ins_cost(150); 9404 format %{ "XOR $dst,$src" %} 9405 opcode(0x31); /* Opcode 31 /r */ 9406 ins_encode( OpcP, RegMem( src, dst ) ); 9407 ins_pipe( ialu_mem_reg ); 9408 %} 9409 9410 // Xor Memory with Immediate 9411 instruct xorI_mem_imm(memory dst, immI src, eFlagsReg cr) %{ 9412 match(Set dst (StoreI dst (XorI (LoadI dst) src))); 9413 effect(KILL cr); 9414 9415 ins_cost(125); 9416 format %{ "XOR $dst,$src" %} 9417 opcode(0x81,0x6); /* Opcode 81 /6 id */ 9418 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) ); 9419 ins_pipe( ialu_mem_imm ); 9420 %} 9421 9422 //----------Convert Int to Boolean--------------------------------------------- 9423 9424 instruct movI_nocopy(eRegI dst, eRegI src) %{ 9425 effect( DEF dst, USE src ); 9426 format %{ "MOV $dst,$src" %} 9427 ins_encode( enc_Copy( dst, src) ); 9428 ins_pipe( ialu_reg_reg ); 9429 %} 9430 9431 instruct ci2b( eRegI dst, eRegI src, eFlagsReg cr ) %{ 9432 effect( USE_DEF dst, USE src, KILL cr ); 9433 9434 size(4); 9435 format %{ "NEG $dst\n\t" 9436 "ADC $dst,$src" %} 9437 ins_encode( neg_reg(dst), 9438 OpcRegReg(0x13,dst,src) ); 9439 ins_pipe( ialu_reg_reg_long ); 9440 %} 9441 9442 instruct convI2B( eRegI dst, eRegI src, eFlagsReg cr ) %{ 9443 match(Set dst (Conv2B src)); 9444 9445 expand %{ 9446 movI_nocopy(dst,src); 9447 ci2b(dst,src,cr); 9448 %} 9449 %} 9450 9451 instruct movP_nocopy(eRegI dst, eRegP src) %{ 9452 effect( DEF dst, USE src ); 9453 format %{ "MOV $dst,$src" %} 9454 ins_encode( enc_Copy( dst, src) ); 9455 ins_pipe( ialu_reg_reg ); 9456 %} 9457 9458 instruct cp2b( eRegI dst, eRegP src, eFlagsReg cr ) %{ 9459 effect( USE_DEF dst, USE src, KILL cr ); 9460 format %{ "NEG $dst\n\t" 9461 "ADC $dst,$src" %} 9462 ins_encode( neg_reg(dst), 9463 OpcRegReg(0x13,dst,src) ); 9464 ins_pipe( ialu_reg_reg_long ); 9465 %} 9466 9467 instruct convP2B( eRegI dst, eRegP src, eFlagsReg cr ) %{ 9468 match(Set dst (Conv2B src)); 9469 9470 expand %{ 9471 movP_nocopy(dst,src); 9472 cp2b(dst,src,cr); 9473 %} 9474 %} 9475 9476 instruct cmpLTMask( eCXRegI dst, ncxRegI p, ncxRegI q, eFlagsReg cr ) %{ 9477 match(Set dst (CmpLTMask p q)); 9478 effect( KILL cr ); 9479 ins_cost(400); 9480 9481 // SETlt can only use low byte of EAX,EBX, ECX, or EDX as destination 9482 format %{ "XOR $dst,$dst\n\t" 9483 "CMP $p,$q\n\t" 9484 "SETlt $dst\n\t" 9485 "NEG $dst" %} 9486 ins_encode( OpcRegReg(0x33,dst,dst), 9487 OpcRegReg(0x3B,p,q), 9488 setLT_reg(dst), neg_reg(dst) ); 9489 ins_pipe( pipe_slow ); 9490 %} 9491 9492 instruct cmpLTMask0( eRegI dst, immI0 zero, eFlagsReg cr ) %{ 9493 match(Set dst (CmpLTMask dst zero)); 9494 effect( DEF dst, KILL cr ); 9495 ins_cost(100); 9496 9497 format %{ "SAR $dst,31" %} 9498 opcode(0xC1, 0x7); /* C1 /7 ib */ 9499 ins_encode( RegOpcImm( dst, 0x1F ) ); 9500 ins_pipe( ialu_reg ); 9501 %} 9502 9503 9504 instruct cadd_cmpLTMask( ncxRegI p, ncxRegI q, ncxRegI y, eCXRegI tmp, eFlagsReg cr ) %{ 9505 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q))); 9506 effect( KILL tmp, KILL cr ); 9507 ins_cost(400); 9508 // annoyingly, $tmp has no edges so you cant ask for it in 9509 // any format or encoding 9510 format %{ "SUB $p,$q\n\t" 9511 "SBB ECX,ECX\n\t" 9512 "AND ECX,$y\n\t" 9513 "ADD $p,ECX" %} 9514 ins_encode( enc_cmpLTP(p,q,y,tmp) ); 9515 ins_pipe( pipe_cmplt ); 9516 %} 9517 9518 /* If I enable this, I encourage spilling in the inner loop of compress. 9519 instruct cadd_cmpLTMask_mem( ncxRegI p, ncxRegI q, memory y, eCXRegI tmp, eFlagsReg cr ) %{ 9520 match(Set p (AddI (AndI (CmpLTMask p q) (LoadI y)) (SubI p q))); 9521 effect( USE_KILL tmp, KILL cr ); 9522 ins_cost(400); 9523 9524 format %{ "SUB $p,$q\n\t" 9525 "SBB ECX,ECX\n\t" 9526 "AND ECX,$y\n\t" 9527 "ADD $p,ECX" %} 9528 ins_encode( enc_cmpLTP_mem(p,q,y,tmp) ); 9529 %} 9530 */ 9531 9532 //----------Long Instructions------------------------------------------------ 9533 // Add Long Register with Register 9534 instruct addL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{ 9535 match(Set dst (AddL dst src)); 9536 effect(KILL cr); 9537 ins_cost(200); 9538 format %{ "ADD $dst.lo,$src.lo\n\t" 9539 "ADC $dst.hi,$src.hi" %} 9540 opcode(0x03, 0x13); 9541 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) ); 9542 ins_pipe( ialu_reg_reg_long ); 9543 %} 9544 9545 // Add Long Register with Immediate 9546 instruct addL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{ 9547 match(Set dst (AddL dst src)); 9548 effect(KILL cr); 9549 format %{ "ADD $dst.lo,$src.lo\n\t" 9550 "ADC $dst.hi,$src.hi" %} 9551 opcode(0x81,0x00,0x02); /* Opcode 81 /0, 81 /2 */ 9552 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) ); 9553 ins_pipe( ialu_reg_long ); 9554 %} 9555 9556 // Add Long Register with Memory 9557 instruct addL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{ 9558 match(Set dst (AddL dst (LoadL mem))); 9559 effect(KILL cr); 9560 ins_cost(125); 9561 format %{ "ADD $dst.lo,$mem\n\t" 9562 "ADC $dst.hi,$mem+4" %} 9563 opcode(0x03, 0x13); 9564 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) ); 9565 ins_pipe( ialu_reg_long_mem ); 9566 %} 9567 9568 // Subtract Long Register with Register. 9569 instruct subL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{ 9570 match(Set dst (SubL dst src)); 9571 effect(KILL cr); 9572 ins_cost(200); 9573 format %{ "SUB $dst.lo,$src.lo\n\t" 9574 "SBB $dst.hi,$src.hi" %} 9575 opcode(0x2B, 0x1B); 9576 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) ); 9577 ins_pipe( ialu_reg_reg_long ); 9578 %} 9579 9580 // Subtract Long Register with Immediate 9581 instruct subL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{ 9582 match(Set dst (SubL dst src)); 9583 effect(KILL cr); 9584 format %{ "SUB $dst.lo,$src.lo\n\t" 9585 "SBB $dst.hi,$src.hi" %} 9586 opcode(0x81,0x05,0x03); /* Opcode 81 /5, 81 /3 */ 9587 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) ); 9588 ins_pipe( ialu_reg_long ); 9589 %} 9590 9591 // Subtract Long Register with Memory 9592 instruct subL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{ 9593 match(Set dst (SubL dst (LoadL mem))); 9594 effect(KILL cr); 9595 ins_cost(125); 9596 format %{ "SUB $dst.lo,$mem\n\t" 9597 "SBB $dst.hi,$mem+4" %} 9598 opcode(0x2B, 0x1B); 9599 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) ); 9600 ins_pipe( ialu_reg_long_mem ); 9601 %} 9602 9603 instruct negL_eReg(eRegL dst, immL0 zero, eFlagsReg cr) %{ 9604 match(Set dst (SubL zero dst)); 9605 effect(KILL cr); 9606 ins_cost(300); 9607 format %{ "NEG $dst.hi\n\tNEG $dst.lo\n\tSBB $dst.hi,0" %} 9608 ins_encode( neg_long(dst) ); 9609 ins_pipe( ialu_reg_reg_long ); 9610 %} 9611 9612 // And Long Register with Register 9613 instruct andL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{ 9614 match(Set dst (AndL dst src)); 9615 effect(KILL cr); 9616 format %{ "AND $dst.lo,$src.lo\n\t" 9617 "AND $dst.hi,$src.hi" %} 9618 opcode(0x23,0x23); 9619 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) ); 9620 ins_pipe( ialu_reg_reg_long ); 9621 %} 9622 9623 // And Long Register with Immediate 9624 instruct andL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{ 9625 match(Set dst (AndL dst src)); 9626 effect(KILL cr); 9627 format %{ "AND $dst.lo,$src.lo\n\t" 9628 "AND $dst.hi,$src.hi" %} 9629 opcode(0x81,0x04,0x04); /* Opcode 81 /4, 81 /4 */ 9630 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) ); 9631 ins_pipe( ialu_reg_long ); 9632 %} 9633 9634 // And Long Register with Memory 9635 instruct andL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{ 9636 match(Set dst (AndL dst (LoadL mem))); 9637 effect(KILL cr); 9638 ins_cost(125); 9639 format %{ "AND $dst.lo,$mem\n\t" 9640 "AND $dst.hi,$mem+4" %} 9641 opcode(0x23, 0x23); 9642 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) ); 9643 ins_pipe( ialu_reg_long_mem ); 9644 %} 9645 9646 // Or Long Register with Register 9647 instruct orl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{ 9648 match(Set dst (OrL dst src)); 9649 effect(KILL cr); 9650 format %{ "OR $dst.lo,$src.lo\n\t" 9651 "OR $dst.hi,$src.hi" %} 9652 opcode(0x0B,0x0B); 9653 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) ); 9654 ins_pipe( ialu_reg_reg_long ); 9655 %} 9656 9657 // Or Long Register with Immediate 9658 instruct orl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{ 9659 match(Set dst (OrL dst src)); 9660 effect(KILL cr); 9661 format %{ "OR $dst.lo,$src.lo\n\t" 9662 "OR $dst.hi,$src.hi" %} 9663 opcode(0x81,0x01,0x01); /* Opcode 81 /1, 81 /1 */ 9664 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) ); 9665 ins_pipe( ialu_reg_long ); 9666 %} 9667 9668 // Or Long Register with Memory 9669 instruct orl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{ 9670 match(Set dst (OrL dst (LoadL mem))); 9671 effect(KILL cr); 9672 ins_cost(125); 9673 format %{ "OR $dst.lo,$mem\n\t" 9674 "OR $dst.hi,$mem+4" %} 9675 opcode(0x0B,0x0B); 9676 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) ); 9677 ins_pipe( ialu_reg_long_mem ); 9678 %} 9679 9680 // Xor Long Register with Register 9681 instruct xorl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{ 9682 match(Set dst (XorL dst src)); 9683 effect(KILL cr); 9684 format %{ "XOR $dst.lo,$src.lo\n\t" 9685 "XOR $dst.hi,$src.hi" %} 9686 opcode(0x33,0x33); 9687 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) ); 9688 ins_pipe( ialu_reg_reg_long ); 9689 %} 9690 9691 // Xor Long Register with Immediate -1 9692 instruct xorl_eReg_im1(eRegL dst, immL_M1 imm) %{ 9693 match(Set dst (XorL dst imm)); 9694 format %{ "NOT $dst.lo\n\t" 9695 "NOT $dst.hi" %} 9696 ins_encode %{ 9697 __ notl($dst$$Register); 9698 __ notl(HIGH_FROM_LOW($dst$$Register)); 9699 %} 9700 ins_pipe( ialu_reg_long ); 9701 %} 9702 9703 // Xor Long Register with Immediate 9704 instruct xorl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{ 9705 match(Set dst (XorL dst src)); 9706 effect(KILL cr); 9707 format %{ "XOR $dst.lo,$src.lo\n\t" 9708 "XOR $dst.hi,$src.hi" %} 9709 opcode(0x81,0x06,0x06); /* Opcode 81 /6, 81 /6 */ 9710 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) ); 9711 ins_pipe( ialu_reg_long ); 9712 %} 9713 9714 // Xor Long Register with Memory 9715 instruct xorl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{ 9716 match(Set dst (XorL dst (LoadL mem))); 9717 effect(KILL cr); 9718 ins_cost(125); 9719 format %{ "XOR $dst.lo,$mem\n\t" 9720 "XOR $dst.hi,$mem+4" %} 9721 opcode(0x33,0x33); 9722 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) ); 9723 ins_pipe( ialu_reg_long_mem ); 9724 %} 9725 9726 // Shift Left Long by 1 9727 instruct shlL_eReg_1(eRegL dst, immI_1 cnt, eFlagsReg cr) %{ 9728 predicate(UseNewLongLShift); 9729 match(Set dst (LShiftL dst cnt)); 9730 effect(KILL cr); 9731 ins_cost(100); 9732 format %{ "ADD $dst.lo,$dst.lo\n\t" 9733 "ADC $dst.hi,$dst.hi" %} 9734 ins_encode %{ 9735 __ addl($dst$$Register,$dst$$Register); 9736 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register)); 9737 %} 9738 ins_pipe( ialu_reg_long ); 9739 %} 9740 9741 // Shift Left Long by 2 9742 instruct shlL_eReg_2(eRegL dst, immI_2 cnt, eFlagsReg cr) %{ 9743 predicate(UseNewLongLShift); 9744 match(Set dst (LShiftL dst cnt)); 9745 effect(KILL cr); 9746 ins_cost(100); 9747 format %{ "ADD $dst.lo,$dst.lo\n\t" 9748 "ADC $dst.hi,$dst.hi\n\t" 9749 "ADD $dst.lo,$dst.lo\n\t" 9750 "ADC $dst.hi,$dst.hi" %} 9751 ins_encode %{ 9752 __ addl($dst$$Register,$dst$$Register); 9753 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register)); 9754 __ addl($dst$$Register,$dst$$Register); 9755 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register)); 9756 %} 9757 ins_pipe( ialu_reg_long ); 9758 %} 9759 9760 // Shift Left Long by 3 9761 instruct shlL_eReg_3(eRegL dst, immI_3 cnt, eFlagsReg cr) %{ 9762 predicate(UseNewLongLShift); 9763 match(Set dst (LShiftL dst cnt)); 9764 effect(KILL cr); 9765 ins_cost(100); 9766 format %{ "ADD $dst.lo,$dst.lo\n\t" 9767 "ADC $dst.hi,$dst.hi\n\t" 9768 "ADD $dst.lo,$dst.lo\n\t" 9769 "ADC $dst.hi,$dst.hi\n\t" 9770 "ADD $dst.lo,$dst.lo\n\t" 9771 "ADC $dst.hi,$dst.hi" %} 9772 ins_encode %{ 9773 __ addl($dst$$Register,$dst$$Register); 9774 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register)); 9775 __ addl($dst$$Register,$dst$$Register); 9776 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register)); 9777 __ addl($dst$$Register,$dst$$Register); 9778 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register)); 9779 %} 9780 ins_pipe( ialu_reg_long ); 9781 %} 9782 9783 // Shift Left Long by 1-31 9784 instruct shlL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{ 9785 match(Set dst (LShiftL dst cnt)); 9786 effect(KILL cr); 9787 ins_cost(200); 9788 format %{ "SHLD $dst.hi,$dst.lo,$cnt\n\t" 9789 "SHL $dst.lo,$cnt" %} 9790 opcode(0xC1, 0x4, 0xA4); /* 0F/A4, then C1 /4 ib */ 9791 ins_encode( move_long_small_shift(dst,cnt) ); 9792 ins_pipe( ialu_reg_long ); 9793 %} 9794 9795 // Shift Left Long by 32-63 9796 instruct shlL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{ 9797 match(Set dst (LShiftL dst cnt)); 9798 effect(KILL cr); 9799 ins_cost(300); 9800 format %{ "MOV $dst.hi,$dst.lo\n" 9801 "\tSHL $dst.hi,$cnt-32\n" 9802 "\tXOR $dst.lo,$dst.lo" %} 9803 opcode(0xC1, 0x4); /* C1 /4 ib */ 9804 ins_encode( move_long_big_shift_clr(dst,cnt) ); 9805 ins_pipe( ialu_reg_long ); 9806 %} 9807 9808 // Shift Left Long by variable 9809 instruct salL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{ 9810 match(Set dst (LShiftL dst shift)); 9811 effect(KILL cr); 9812 ins_cost(500+200); 9813 size(17); 9814 format %{ "TEST $shift,32\n\t" 9815 "JEQ,s small\n\t" 9816 "MOV $dst.hi,$dst.lo\n\t" 9817 "XOR $dst.lo,$dst.lo\n" 9818 "small:\tSHLD $dst.hi,$dst.lo,$shift\n\t" 9819 "SHL $dst.lo,$shift" %} 9820 ins_encode( shift_left_long( dst, shift ) ); 9821 ins_pipe( pipe_slow ); 9822 %} 9823 9824 // Shift Right Long by 1-31 9825 instruct shrL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{ 9826 match(Set dst (URShiftL dst cnt)); 9827 effect(KILL cr); 9828 ins_cost(200); 9829 format %{ "SHRD $dst.lo,$dst.hi,$cnt\n\t" 9830 "SHR $dst.hi,$cnt" %} 9831 opcode(0xC1, 0x5, 0xAC); /* 0F/AC, then C1 /5 ib */ 9832 ins_encode( move_long_small_shift(dst,cnt) ); 9833 ins_pipe( ialu_reg_long ); 9834 %} 9835 9836 // Shift Right Long by 32-63 9837 instruct shrL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{ 9838 match(Set dst (URShiftL dst cnt)); 9839 effect(KILL cr); 9840 ins_cost(300); 9841 format %{ "MOV $dst.lo,$dst.hi\n" 9842 "\tSHR $dst.lo,$cnt-32\n" 9843 "\tXOR $dst.hi,$dst.hi" %} 9844 opcode(0xC1, 0x5); /* C1 /5 ib */ 9845 ins_encode( move_long_big_shift_clr(dst,cnt) ); 9846 ins_pipe( ialu_reg_long ); 9847 %} 9848 9849 // Shift Right Long by variable 9850 instruct shrL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{ 9851 match(Set dst (URShiftL dst shift)); 9852 effect(KILL cr); 9853 ins_cost(600); 9854 size(17); 9855 format %{ "TEST $shift,32\n\t" 9856 "JEQ,s small\n\t" 9857 "MOV $dst.lo,$dst.hi\n\t" 9858 "XOR $dst.hi,$dst.hi\n" 9859 "small:\tSHRD $dst.lo,$dst.hi,$shift\n\t" 9860 "SHR $dst.hi,$shift" %} 9861 ins_encode( shift_right_long( dst, shift ) ); 9862 ins_pipe( pipe_slow ); 9863 %} 9864 9865 // Shift Right Long by 1-31 9866 instruct sarL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{ 9867 match(Set dst (RShiftL dst cnt)); 9868 effect(KILL cr); 9869 ins_cost(200); 9870 format %{ "SHRD $dst.lo,$dst.hi,$cnt\n\t" 9871 "SAR $dst.hi,$cnt" %} 9872 opcode(0xC1, 0x7, 0xAC); /* 0F/AC, then C1 /7 ib */ 9873 ins_encode( move_long_small_shift(dst,cnt) ); 9874 ins_pipe( ialu_reg_long ); 9875 %} 9876 9877 // Shift Right Long by 32-63 9878 instruct sarL_eReg_32_63( eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{ 9879 match(Set dst (RShiftL dst cnt)); 9880 effect(KILL cr); 9881 ins_cost(300); 9882 format %{ "MOV $dst.lo,$dst.hi\n" 9883 "\tSAR $dst.lo,$cnt-32\n" 9884 "\tSAR $dst.hi,31" %} 9885 opcode(0xC1, 0x7); /* C1 /7 ib */ 9886 ins_encode( move_long_big_shift_sign(dst,cnt) ); 9887 ins_pipe( ialu_reg_long ); 9888 %} 9889 9890 // Shift Right arithmetic Long by variable 9891 instruct sarL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{ 9892 match(Set dst (RShiftL dst shift)); 9893 effect(KILL cr); 9894 ins_cost(600); 9895 size(18); 9896 format %{ "TEST $shift,32\n\t" 9897 "JEQ,s small\n\t" 9898 "MOV $dst.lo,$dst.hi\n\t" 9899 "SAR $dst.hi,31\n" 9900 "small:\tSHRD $dst.lo,$dst.hi,$shift\n\t" 9901 "SAR $dst.hi,$shift" %} 9902 ins_encode( shift_right_arith_long( dst, shift ) ); 9903 ins_pipe( pipe_slow ); 9904 %} 9905 9906 9907 //----------Double Instructions------------------------------------------------ 9908 // Double Math 9909 9910 // Compare & branch 9911 9912 // P6 version of float compare, sets condition codes in EFLAGS 9913 instruct cmpD_cc_P6(eFlagsRegU cr, regD src1, regD src2, eAXRegI rax) %{ 9914 predicate(VM_Version::supports_cmov() && UseSSE <=1); 9915 match(Set cr (CmpD src1 src2)); 9916 effect(KILL rax); 9917 ins_cost(150); 9918 format %{ "FLD $src1\n\t" 9919 "FUCOMIP ST,$src2 // P6 instruction\n\t" 9920 "JNP exit\n\t" 9921 "MOV ah,1 // saw a NaN, set CF\n\t" 9922 "SAHF\n" 9923 "exit:\tNOP // avoid branch to branch" %} 9924 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */ 9925 ins_encode( Push_Reg_D(src1), 9926 OpcP, RegOpc(src2), 9927 cmpF_P6_fixup ); 9928 ins_pipe( pipe_slow ); 9929 %} 9930 9931 instruct cmpD_cc_P6CF(eFlagsRegUCF cr, regD src1, regD src2) %{ 9932 predicate(VM_Version::supports_cmov() && UseSSE <=1); 9933 match(Set cr (CmpD src1 src2)); 9934 ins_cost(150); 9935 format %{ "FLD $src1\n\t" 9936 "FUCOMIP ST,$src2 // P6 instruction" %} 9937 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */ 9938 ins_encode( Push_Reg_D(src1), 9939 OpcP, RegOpc(src2)); 9940 ins_pipe( pipe_slow ); 9941 %} 9942 9943 // Compare & branch 9944 instruct cmpD_cc(eFlagsRegU cr, regD src1, regD src2, eAXRegI rax) %{ 9945 predicate(UseSSE<=1); 9946 match(Set cr (CmpD src1 src2)); 9947 effect(KILL rax); 9948 ins_cost(200); 9949 format %{ "FLD $src1\n\t" 9950 "FCOMp $src2\n\t" 9951 "FNSTSW AX\n\t" 9952 "TEST AX,0x400\n\t" 9953 "JZ,s flags\n\t" 9954 "MOV AH,1\t# unordered treat as LT\n" 9955 "flags:\tSAHF" %} 9956 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */ 9957 ins_encode( Push_Reg_D(src1), 9958 OpcP, RegOpc(src2), 9959 fpu_flags); 9960 ins_pipe( pipe_slow ); 9961 %} 9962 9963 // Compare vs zero into -1,0,1 9964 instruct cmpD_0(eRegI dst, regD src1, immD0 zero, eAXRegI rax, eFlagsReg cr) %{ 9965 predicate(UseSSE<=1); 9966 match(Set dst (CmpD3 src1 zero)); 9967 effect(KILL cr, KILL rax); 9968 ins_cost(280); 9969 format %{ "FTSTD $dst,$src1" %} 9970 opcode(0xE4, 0xD9); 9971 ins_encode( Push_Reg_D(src1), 9972 OpcS, OpcP, PopFPU, 9973 CmpF_Result(dst)); 9974 ins_pipe( pipe_slow ); 9975 %} 9976 9977 // Compare into -1,0,1 9978 instruct cmpD_reg(eRegI dst, regD src1, regD src2, eAXRegI rax, eFlagsReg cr) %{ 9979 predicate(UseSSE<=1); 9980 match(Set dst (CmpD3 src1 src2)); 9981 effect(KILL cr, KILL rax); 9982 ins_cost(300); 9983 format %{ "FCMPD $dst,$src1,$src2" %} 9984 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */ 9985 ins_encode( Push_Reg_D(src1), 9986 OpcP, RegOpc(src2), 9987 CmpF_Result(dst)); 9988 ins_pipe( pipe_slow ); 9989 %} 9990 9991 // float compare and set condition codes in EFLAGS by XMM regs 9992 instruct cmpXD_cc(eFlagsRegU cr, regXD dst, regXD src, eAXRegI rax) %{ 9993 predicate(UseSSE>=2); 9994 match(Set cr (CmpD dst src)); 9995 effect(KILL rax); 9996 ins_cost(125); 9997 format %{ "COMISD $dst,$src\n" 9998 "\tJNP exit\n" 9999 "\tMOV ah,1 // saw a NaN, set CF\n" 10000 "\tSAHF\n" 10001 "exit:\tNOP // avoid branch to branch" %} 10002 opcode(0x66, 0x0F, 0x2F); 10003 ins_encode(OpcP, OpcS, Opcode(tertiary), RegReg(dst, src), cmpF_P6_fixup); 10004 ins_pipe( pipe_slow ); 10005 %} 10006 10007 instruct cmpXD_ccCF(eFlagsRegUCF cr, regXD dst, regXD src) %{ 10008 predicate(UseSSE>=2); 10009 match(Set cr (CmpD dst src)); 10010 ins_cost(100); 10011 format %{ "COMISD $dst,$src" %} 10012 opcode(0x66, 0x0F, 0x2F); 10013 ins_encode(OpcP, OpcS, Opcode(tertiary), RegReg(dst, src)); 10014 ins_pipe( pipe_slow ); 10015 %} 10016 10017 // float compare and set condition codes in EFLAGS by XMM regs 10018 instruct cmpXD_ccmem(eFlagsRegU cr, regXD dst, memory src, eAXRegI rax) %{ 10019 predicate(UseSSE>=2); 10020 match(Set cr (CmpD dst (LoadD src))); 10021 effect(KILL rax); 10022 ins_cost(145); 10023 format %{ "COMISD $dst,$src\n" 10024 "\tJNP exit\n" 10025 "\tMOV ah,1 // saw a NaN, set CF\n" 10026 "\tSAHF\n" 10027 "exit:\tNOP // avoid branch to branch" %} 10028 opcode(0x66, 0x0F, 0x2F); 10029 ins_encode(OpcP, OpcS, Opcode(tertiary), RegMem(dst, src), cmpF_P6_fixup); 10030 ins_pipe( pipe_slow ); 10031 %} 10032 10033 instruct cmpXD_ccmemCF(eFlagsRegUCF cr, regXD dst, memory src) %{ 10034 predicate(UseSSE>=2); 10035 match(Set cr (CmpD dst (LoadD src))); 10036 ins_cost(100); 10037 format %{ "COMISD $dst,$src" %} 10038 opcode(0x66, 0x0F, 0x2F); 10039 ins_encode(OpcP, OpcS, Opcode(tertiary), RegMem(dst, src)); 10040 ins_pipe( pipe_slow ); 10041 %} 10042 10043 // Compare into -1,0,1 in XMM 10044 instruct cmpXD_reg(eRegI dst, regXD src1, regXD src2, eFlagsReg cr) %{ 10045 predicate(UseSSE>=2); 10046 match(Set dst (CmpD3 src1 src2)); 10047 effect(KILL cr); 10048 ins_cost(255); 10049 format %{ "XOR $dst,$dst\n" 10050 "\tCOMISD $src1,$src2\n" 10051 "\tJP,s nan\n" 10052 "\tJEQ,s exit\n" 10053 "\tJA,s inc\n" 10054 "nan:\tDEC $dst\n" 10055 "\tJMP,s exit\n" 10056 "inc:\tINC $dst\n" 10057 "exit:" 10058 %} 10059 opcode(0x66, 0x0F, 0x2F); 10060 ins_encode(Xor_Reg(dst), OpcP, OpcS, Opcode(tertiary), RegReg(src1, src2), 10061 CmpX_Result(dst)); 10062 ins_pipe( pipe_slow ); 10063 %} 10064 10065 // Compare into -1,0,1 in XMM and memory 10066 instruct cmpXD_regmem(eRegI dst, regXD src1, memory mem, eFlagsReg cr) %{ 10067 predicate(UseSSE>=2); 10068 match(Set dst (CmpD3 src1 (LoadD mem))); 10069 effect(KILL cr); 10070 ins_cost(275); 10071 format %{ "COMISD $src1,$mem\n" 10072 "\tMOV $dst,0\t\t# do not blow flags\n" 10073 "\tJP,s nan\n" 10074 "\tJEQ,s exit\n" 10075 "\tJA,s inc\n" 10076 "nan:\tDEC $dst\n" 10077 "\tJMP,s exit\n" 10078 "inc:\tINC $dst\n" 10079 "exit:" 10080 %} 10081 opcode(0x66, 0x0F, 0x2F); 10082 ins_encode(OpcP, OpcS, Opcode(tertiary), RegMem(src1, mem), 10083 LdImmI(dst,0x0), CmpX_Result(dst)); 10084 ins_pipe( pipe_slow ); 10085 %} 10086 10087 10088 instruct subD_reg(regD dst, regD src) %{ 10089 predicate (UseSSE <=1); 10090 match(Set dst (SubD dst src)); 10091 10092 format %{ "FLD $src\n\t" 10093 "DSUBp $dst,ST" %} 10094 opcode(0xDE, 0x5); /* DE E8+i or DE /5 */ 10095 ins_cost(150); 10096 ins_encode( Push_Reg_D(src), 10097 OpcP, RegOpc(dst) ); 10098 ins_pipe( fpu_reg_reg ); 10099 %} 10100 10101 instruct subD_reg_round(stackSlotD dst, regD src1, regD src2) %{ 10102 predicate (UseSSE <=1); 10103 match(Set dst (RoundDouble (SubD src1 src2))); 10104 ins_cost(250); 10105 10106 format %{ "FLD $src2\n\t" 10107 "DSUB ST,$src1\n\t" 10108 "FSTP_D $dst\t# D-round" %} 10109 opcode(0xD8, 0x5); 10110 ins_encode( Push_Reg_D(src2), 10111 OpcP, RegOpc(src1), Pop_Mem_D(dst) ); 10112 ins_pipe( fpu_mem_reg_reg ); 10113 %} 10114 10115 10116 instruct subD_reg_mem(regD dst, memory src) %{ 10117 predicate (UseSSE <=1); 10118 match(Set dst (SubD dst (LoadD src))); 10119 ins_cost(150); 10120 10121 format %{ "FLD $src\n\t" 10122 "DSUBp $dst,ST" %} 10123 opcode(0xDE, 0x5, 0xDD); /* DE C0+i */ /* LoadD DD /0 */ 10124 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src), 10125 OpcP, RegOpc(dst) ); 10126 ins_pipe( fpu_reg_mem ); 10127 %} 10128 10129 instruct absD_reg(regDPR1 dst, regDPR1 src) %{ 10130 predicate (UseSSE<=1); 10131 match(Set dst (AbsD src)); 10132 ins_cost(100); 10133 format %{ "FABS" %} 10134 opcode(0xE1, 0xD9); 10135 ins_encode( OpcS, OpcP ); 10136 ins_pipe( fpu_reg_reg ); 10137 %} 10138 10139 instruct absXD_reg( regXD dst ) %{ 10140 predicate(UseSSE>=2); 10141 match(Set dst (AbsD dst)); 10142 format %{ "ANDPD $dst,[0x7FFFFFFFFFFFFFFF]\t# ABS D by sign masking" %} 10143 ins_encode( AbsXD_encoding(dst)); 10144 ins_pipe( pipe_slow ); 10145 %} 10146 10147 instruct negD_reg(regDPR1 dst, regDPR1 src) %{ 10148 predicate(UseSSE<=1); 10149 match(Set dst (NegD src)); 10150 ins_cost(100); 10151 format %{ "FCHS" %} 10152 opcode(0xE0, 0xD9); 10153 ins_encode( OpcS, OpcP ); 10154 ins_pipe( fpu_reg_reg ); 10155 %} 10156 10157 instruct negXD_reg( regXD dst ) %{ 10158 predicate(UseSSE>=2); 10159 match(Set dst (NegD dst)); 10160 format %{ "XORPD $dst,[0x8000000000000000]\t# CHS D by sign flipping" %} 10161 ins_encode %{ 10162 __ xorpd($dst$$XMMRegister, 10163 ExternalAddress((address)double_signflip_pool)); 10164 %} 10165 ins_pipe( pipe_slow ); 10166 %} 10167 10168 instruct addD_reg(regD dst, regD src) %{ 10169 predicate(UseSSE<=1); 10170 match(Set dst (AddD dst src)); 10171 format %{ "FLD $src\n\t" 10172 "DADD $dst,ST" %} 10173 size(4); 10174 ins_cost(150); 10175 opcode(0xDE, 0x0); /* DE C0+i or DE /0*/ 10176 ins_encode( Push_Reg_D(src), 10177 OpcP, RegOpc(dst) ); 10178 ins_pipe( fpu_reg_reg ); 10179 %} 10180 10181 10182 instruct addD_reg_round(stackSlotD dst, regD src1, regD src2) %{ 10183 predicate(UseSSE<=1); 10184 match(Set dst (RoundDouble (AddD src1 src2))); 10185 ins_cost(250); 10186 10187 format %{ "FLD $src2\n\t" 10188 "DADD ST,$src1\n\t" 10189 "FSTP_D $dst\t# D-round" %} 10190 opcode(0xD8, 0x0); /* D8 C0+i or D8 /0*/ 10191 ins_encode( Push_Reg_D(src2), 10192 OpcP, RegOpc(src1), Pop_Mem_D(dst) ); 10193 ins_pipe( fpu_mem_reg_reg ); 10194 %} 10195 10196 10197 instruct addD_reg_mem(regD dst, memory src) %{ 10198 predicate(UseSSE<=1); 10199 match(Set dst (AddD dst (LoadD src))); 10200 ins_cost(150); 10201 10202 format %{ "FLD $src\n\t" 10203 "DADDp $dst,ST" %} 10204 opcode(0xDE, 0x0, 0xDD); /* DE C0+i */ /* LoadD DD /0 */ 10205 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src), 10206 OpcP, RegOpc(dst) ); 10207 ins_pipe( fpu_reg_mem ); 10208 %} 10209 10210 // add-to-memory 10211 instruct addD_mem_reg(memory dst, regD src) %{ 10212 predicate(UseSSE<=1); 10213 match(Set dst (StoreD dst (RoundDouble (AddD (LoadD dst) src)))); 10214 ins_cost(150); 10215 10216 format %{ "FLD_D $dst\n\t" 10217 "DADD ST,$src\n\t" 10218 "FST_D $dst" %} 10219 opcode(0xDD, 0x0); 10220 ins_encode( Opcode(0xDD), RMopc_Mem(0x00,dst), 10221 Opcode(0xD8), RegOpc(src), 10222 set_instruction_start, 10223 Opcode(0xDD), RMopc_Mem(0x03,dst) ); 10224 ins_pipe( fpu_reg_mem ); 10225 %} 10226 10227 instruct addD_reg_imm1(regD dst, immD1 src) %{ 10228 predicate(UseSSE<=1); 10229 match(Set dst (AddD dst src)); 10230 ins_cost(125); 10231 format %{ "FLD1\n\t" 10232 "DADDp $dst,ST" %} 10233 opcode(0xDE, 0x00); 10234 ins_encode( LdImmD(src), 10235 OpcP, RegOpc(dst) ); 10236 ins_pipe( fpu_reg ); 10237 %} 10238 10239 instruct addD_reg_imm(regD dst, immD src) %{ 10240 predicate(UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 ); 10241 match(Set dst (AddD dst src)); 10242 ins_cost(200); 10243 format %{ "FLD_D [$src]\n\t" 10244 "DADDp $dst,ST" %} 10245 opcode(0xDE, 0x00); /* DE /0 */ 10246 ins_encode( LdImmD(src), 10247 OpcP, RegOpc(dst)); 10248 ins_pipe( fpu_reg_mem ); 10249 %} 10250 10251 instruct addD_reg_imm_round(stackSlotD dst, regD src, immD con) %{ 10252 predicate(UseSSE<=1 && _kids[0]->_kids[1]->_leaf->getd() != 0.0 && _kids[0]->_kids[1]->_leaf->getd() != 1.0 ); 10253 match(Set dst (RoundDouble (AddD src con))); 10254 ins_cost(200); 10255 format %{ "FLD_D [$con]\n\t" 10256 "DADD ST,$src\n\t" 10257 "FSTP_D $dst\t# D-round" %} 10258 opcode(0xD8, 0x00); /* D8 /0 */ 10259 ins_encode( LdImmD(con), 10260 OpcP, RegOpc(src), Pop_Mem_D(dst)); 10261 ins_pipe( fpu_mem_reg_con ); 10262 %} 10263 10264 // Add two double precision floating point values in xmm 10265 instruct addXD_reg(regXD dst, regXD src) %{ 10266 predicate(UseSSE>=2); 10267 match(Set dst (AddD dst src)); 10268 format %{ "ADDSD $dst,$src" %} 10269 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x58), RegReg(dst, src)); 10270 ins_pipe( pipe_slow ); 10271 %} 10272 10273 instruct addXD_imm(regXD dst, immXD con) %{ 10274 predicate(UseSSE>=2); 10275 match(Set dst (AddD dst con)); 10276 format %{ "ADDSD $dst,[$con]" %} 10277 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x58), LdImmXD(dst, con) ); 10278 ins_pipe( pipe_slow ); 10279 %} 10280 10281 instruct addXD_mem(regXD dst, memory mem) %{ 10282 predicate(UseSSE>=2); 10283 match(Set dst (AddD dst (LoadD mem))); 10284 format %{ "ADDSD $dst,$mem" %} 10285 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x58), RegMem(dst,mem)); 10286 ins_pipe( pipe_slow ); 10287 %} 10288 10289 // Sub two double precision floating point values in xmm 10290 instruct subXD_reg(regXD dst, regXD src) %{ 10291 predicate(UseSSE>=2); 10292 match(Set dst (SubD dst src)); 10293 format %{ "SUBSD $dst,$src" %} 10294 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5C), RegReg(dst, src)); 10295 ins_pipe( pipe_slow ); 10296 %} 10297 10298 instruct subXD_imm(regXD dst, immXD con) %{ 10299 predicate(UseSSE>=2); 10300 match(Set dst (SubD dst con)); 10301 format %{ "SUBSD $dst,[$con]" %} 10302 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5C), LdImmXD(dst, con) ); 10303 ins_pipe( pipe_slow ); 10304 %} 10305 10306 instruct subXD_mem(regXD dst, memory mem) %{ 10307 predicate(UseSSE>=2); 10308 match(Set dst (SubD dst (LoadD mem))); 10309 format %{ "SUBSD $dst,$mem" %} 10310 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5C), RegMem(dst,mem)); 10311 ins_pipe( pipe_slow ); 10312 %} 10313 10314 // Mul two double precision floating point values in xmm 10315 instruct mulXD_reg(regXD dst, regXD src) %{ 10316 predicate(UseSSE>=2); 10317 match(Set dst (MulD dst src)); 10318 format %{ "MULSD $dst,$src" %} 10319 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x59), RegReg(dst, src)); 10320 ins_pipe( pipe_slow ); 10321 %} 10322 10323 instruct mulXD_imm(regXD dst, immXD con) %{ 10324 predicate(UseSSE>=2); 10325 match(Set dst (MulD dst con)); 10326 format %{ "MULSD $dst,[$con]" %} 10327 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x59), LdImmXD(dst, con) ); 10328 ins_pipe( pipe_slow ); 10329 %} 10330 10331 instruct mulXD_mem(regXD dst, memory mem) %{ 10332 predicate(UseSSE>=2); 10333 match(Set dst (MulD dst (LoadD mem))); 10334 format %{ "MULSD $dst,$mem" %} 10335 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x59), RegMem(dst,mem)); 10336 ins_pipe( pipe_slow ); 10337 %} 10338 10339 // Div two double precision floating point values in xmm 10340 instruct divXD_reg(regXD dst, regXD src) %{ 10341 predicate(UseSSE>=2); 10342 match(Set dst (DivD dst src)); 10343 format %{ "DIVSD $dst,$src" %} 10344 opcode(0xF2, 0x0F, 0x5E); 10345 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5E), RegReg(dst, src)); 10346 ins_pipe( pipe_slow ); 10347 %} 10348 10349 instruct divXD_imm(regXD dst, immXD con) %{ 10350 predicate(UseSSE>=2); 10351 match(Set dst (DivD dst con)); 10352 format %{ "DIVSD $dst,[$con]" %} 10353 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5E), LdImmXD(dst, con)); 10354 ins_pipe( pipe_slow ); 10355 %} 10356 10357 instruct divXD_mem(regXD dst, memory mem) %{ 10358 predicate(UseSSE>=2); 10359 match(Set dst (DivD dst (LoadD mem))); 10360 format %{ "DIVSD $dst,$mem" %} 10361 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5E), RegMem(dst,mem)); 10362 ins_pipe( pipe_slow ); 10363 %} 10364 10365 10366 instruct mulD_reg(regD dst, regD src) %{ 10367 predicate(UseSSE<=1); 10368 match(Set dst (MulD dst src)); 10369 format %{ "FLD $src\n\t" 10370 "DMULp $dst,ST" %} 10371 opcode(0xDE, 0x1); /* DE C8+i or DE /1*/ 10372 ins_cost(150); 10373 ins_encode( Push_Reg_D(src), 10374 OpcP, RegOpc(dst) ); 10375 ins_pipe( fpu_reg_reg ); 10376 %} 10377 10378 // Strict FP instruction biases argument before multiply then 10379 // biases result to avoid double rounding of subnormals. 10380 // 10381 // scale arg1 by multiplying arg1 by 2^(-15360) 10382 // load arg2 10383 // multiply scaled arg1 by arg2 10384 // rescale product by 2^(15360) 10385 // 10386 instruct strictfp_mulD_reg(regDPR1 dst, regnotDPR1 src) %{ 10387 predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() ); 10388 match(Set dst (MulD dst src)); 10389 ins_cost(1); // Select this instruction for all strict FP double multiplies 10390 10391 format %{ "FLD StubRoutines::_fpu_subnormal_bias1\n\t" 10392 "DMULp $dst,ST\n\t" 10393 "FLD $src\n\t" 10394 "DMULp $dst,ST\n\t" 10395 "FLD StubRoutines::_fpu_subnormal_bias2\n\t" 10396 "DMULp $dst,ST\n\t" %} 10397 opcode(0xDE, 0x1); /* DE C8+i or DE /1*/ 10398 ins_encode( strictfp_bias1(dst), 10399 Push_Reg_D(src), 10400 OpcP, RegOpc(dst), 10401 strictfp_bias2(dst) ); 10402 ins_pipe( fpu_reg_reg ); 10403 %} 10404 10405 instruct mulD_reg_imm(regD dst, immD src) %{ 10406 predicate( UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 ); 10407 match(Set dst (MulD dst src)); 10408 ins_cost(200); 10409 format %{ "FLD_D [$src]\n\t" 10410 "DMULp $dst,ST" %} 10411 opcode(0xDE, 0x1); /* DE /1 */ 10412 ins_encode( LdImmD(src), 10413 OpcP, RegOpc(dst) ); 10414 ins_pipe( fpu_reg_mem ); 10415 %} 10416 10417 10418 instruct mulD_reg_mem(regD dst, memory src) %{ 10419 predicate( UseSSE<=1 ); 10420 match(Set dst (MulD dst (LoadD src))); 10421 ins_cost(200); 10422 format %{ "FLD_D $src\n\t" 10423 "DMULp $dst,ST" %} 10424 opcode(0xDE, 0x1, 0xDD); /* DE C8+i or DE /1*/ /* LoadD DD /0 */ 10425 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src), 10426 OpcP, RegOpc(dst) ); 10427 ins_pipe( fpu_reg_mem ); 10428 %} 10429 10430 // 10431 // Cisc-alternate to reg-reg multiply 10432 instruct mulD_reg_mem_cisc(regD dst, regD src, memory mem) %{ 10433 predicate( UseSSE<=1 ); 10434 match(Set dst (MulD src (LoadD mem))); 10435 ins_cost(250); 10436 format %{ "FLD_D $mem\n\t" 10437 "DMUL ST,$src\n\t" 10438 "FSTP_D $dst" %} 10439 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */ /* LoadD D9 /0 */ 10440 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem), 10441 OpcReg_F(src), 10442 Pop_Reg_D(dst) ); 10443 ins_pipe( fpu_reg_reg_mem ); 10444 %} 10445 10446 10447 // MACRO3 -- addD a mulD 10448 // This instruction is a '2-address' instruction in that the result goes 10449 // back to src2. This eliminates a move from the macro; possibly the 10450 // register allocator will have to add it back (and maybe not). 10451 instruct addD_mulD_reg(regD src2, regD src1, regD src0) %{ 10452 predicate( UseSSE<=1 ); 10453 match(Set src2 (AddD (MulD src0 src1) src2)); 10454 format %{ "FLD $src0\t# ===MACRO3d===\n\t" 10455 "DMUL ST,$src1\n\t" 10456 "DADDp $src2,ST" %} 10457 ins_cost(250); 10458 opcode(0xDD); /* LoadD DD /0 */ 10459 ins_encode( Push_Reg_F(src0), 10460 FMul_ST_reg(src1), 10461 FAddP_reg_ST(src2) ); 10462 ins_pipe( fpu_reg_reg_reg ); 10463 %} 10464 10465 10466 // MACRO3 -- subD a mulD 10467 instruct subD_mulD_reg(regD src2, regD src1, regD src0) %{ 10468 predicate( UseSSE<=1 ); 10469 match(Set src2 (SubD (MulD src0 src1) src2)); 10470 format %{ "FLD $src0\t# ===MACRO3d===\n\t" 10471 "DMUL ST,$src1\n\t" 10472 "DSUBRp $src2,ST" %} 10473 ins_cost(250); 10474 ins_encode( Push_Reg_F(src0), 10475 FMul_ST_reg(src1), 10476 Opcode(0xDE), Opc_plus(0xE0,src2)); 10477 ins_pipe( fpu_reg_reg_reg ); 10478 %} 10479 10480 10481 instruct divD_reg(regD dst, regD src) %{ 10482 predicate( UseSSE<=1 ); 10483 match(Set dst (DivD dst src)); 10484 10485 format %{ "FLD $src\n\t" 10486 "FDIVp $dst,ST" %} 10487 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/ 10488 ins_cost(150); 10489 ins_encode( Push_Reg_D(src), 10490 OpcP, RegOpc(dst) ); 10491 ins_pipe( fpu_reg_reg ); 10492 %} 10493 10494 // Strict FP instruction biases argument before division then 10495 // biases result, to avoid double rounding of subnormals. 10496 // 10497 // scale dividend by multiplying dividend by 2^(-15360) 10498 // load divisor 10499 // divide scaled dividend by divisor 10500 // rescale quotient by 2^(15360) 10501 // 10502 instruct strictfp_divD_reg(regDPR1 dst, regnotDPR1 src) %{ 10503 predicate (UseSSE<=1); 10504 match(Set dst (DivD dst src)); 10505 predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() ); 10506 ins_cost(01); 10507 10508 format %{ "FLD StubRoutines::_fpu_subnormal_bias1\n\t" 10509 "DMULp $dst,ST\n\t" 10510 "FLD $src\n\t" 10511 "FDIVp $dst,ST\n\t" 10512 "FLD StubRoutines::_fpu_subnormal_bias2\n\t" 10513 "DMULp $dst,ST\n\t" %} 10514 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/ 10515 ins_encode( strictfp_bias1(dst), 10516 Push_Reg_D(src), 10517 OpcP, RegOpc(dst), 10518 strictfp_bias2(dst) ); 10519 ins_pipe( fpu_reg_reg ); 10520 %} 10521 10522 instruct divD_reg_round(stackSlotD dst, regD src1, regD src2) %{ 10523 predicate( UseSSE<=1 && !(Compile::current()->has_method() && Compile::current()->method()->is_strict()) ); 10524 match(Set dst (RoundDouble (DivD src1 src2))); 10525 10526 format %{ "FLD $src1\n\t" 10527 "FDIV ST,$src2\n\t" 10528 "FSTP_D $dst\t# D-round" %} 10529 opcode(0xD8, 0x6); /* D8 F0+i or D8 /6 */ 10530 ins_encode( Push_Reg_D(src1), 10531 OpcP, RegOpc(src2), Pop_Mem_D(dst) ); 10532 ins_pipe( fpu_mem_reg_reg ); 10533 %} 10534 10535 10536 instruct modD_reg(regD dst, regD src, eAXRegI rax, eFlagsReg cr) %{ 10537 predicate(UseSSE<=1); 10538 match(Set dst (ModD dst src)); 10539 effect(KILL rax, KILL cr); // emitModD() uses EAX and EFLAGS 10540 10541 format %{ "DMOD $dst,$src" %} 10542 ins_cost(250); 10543 ins_encode(Push_Reg_Mod_D(dst, src), 10544 emitModD(), 10545 Push_Result_Mod_D(src), 10546 Pop_Reg_D(dst)); 10547 ins_pipe( pipe_slow ); 10548 %} 10549 10550 instruct modXD_reg(regXD dst, regXD src0, regXD src1, eAXRegI rax, eFlagsReg cr) %{ 10551 predicate(UseSSE>=2); 10552 match(Set dst (ModD src0 src1)); 10553 effect(KILL rax, KILL cr); 10554 10555 format %{ "SUB ESP,8\t # DMOD\n" 10556 "\tMOVSD [ESP+0],$src1\n" 10557 "\tFLD_D [ESP+0]\n" 10558 "\tMOVSD [ESP+0],$src0\n" 10559 "\tFLD_D [ESP+0]\n" 10560 "loop:\tFPREM\n" 10561 "\tFWAIT\n" 10562 "\tFNSTSW AX\n" 10563 "\tSAHF\n" 10564 "\tJP loop\n" 10565 "\tFSTP_D [ESP+0]\n" 10566 "\tMOVSD $dst,[ESP+0]\n" 10567 "\tADD ESP,8\n" 10568 "\tFSTP ST0\t # Restore FPU Stack" 10569 %} 10570 ins_cost(250); 10571 ins_encode( Push_ModD_encoding(src0, src1), emitModD(), Push_ResultXD(dst), PopFPU); 10572 ins_pipe( pipe_slow ); 10573 %} 10574 10575 instruct sinD_reg(regDPR1 dst, regDPR1 src) %{ 10576 predicate (UseSSE<=1); 10577 match(Set dst (SinD src)); 10578 ins_cost(1800); 10579 format %{ "DSIN $dst" %} 10580 opcode(0xD9, 0xFE); 10581 ins_encode( OpcP, OpcS ); 10582 ins_pipe( pipe_slow ); 10583 %} 10584 10585 instruct sinXD_reg(regXD dst, eFlagsReg cr) %{ 10586 predicate (UseSSE>=2); 10587 match(Set dst (SinD dst)); 10588 effect(KILL cr); // Push_{Src|Result}XD() uses "{SUB|ADD} ESP,8" 10589 ins_cost(1800); 10590 format %{ "DSIN $dst" %} 10591 opcode(0xD9, 0xFE); 10592 ins_encode( Push_SrcXD(dst), OpcP, OpcS, Push_ResultXD(dst) ); 10593 ins_pipe( pipe_slow ); 10594 %} 10595 10596 instruct cosD_reg(regDPR1 dst, regDPR1 src) %{ 10597 predicate (UseSSE<=1); 10598 match(Set dst (CosD src)); 10599 ins_cost(1800); 10600 format %{ "DCOS $dst" %} 10601 opcode(0xD9, 0xFF); 10602 ins_encode( OpcP, OpcS ); 10603 ins_pipe( pipe_slow ); 10604 %} 10605 10606 instruct cosXD_reg(regXD dst, eFlagsReg cr) %{ 10607 predicate (UseSSE>=2); 10608 match(Set dst (CosD dst)); 10609 effect(KILL cr); // Push_{Src|Result}XD() uses "{SUB|ADD} ESP,8" 10610 ins_cost(1800); 10611 format %{ "DCOS $dst" %} 10612 opcode(0xD9, 0xFF); 10613 ins_encode( Push_SrcXD(dst), OpcP, OpcS, Push_ResultXD(dst) ); 10614 ins_pipe( pipe_slow ); 10615 %} 10616 10617 instruct tanD_reg(regDPR1 dst, regDPR1 src) %{ 10618 predicate (UseSSE<=1); 10619 match(Set dst(TanD src)); 10620 format %{ "DTAN $dst" %} 10621 ins_encode( Opcode(0xD9), Opcode(0xF2), // fptan 10622 Opcode(0xDD), Opcode(0xD8)); // fstp st 10623 ins_pipe( pipe_slow ); 10624 %} 10625 10626 instruct tanXD_reg(regXD dst, eFlagsReg cr) %{ 10627 predicate (UseSSE>=2); 10628 match(Set dst(TanD dst)); 10629 effect(KILL cr); // Push_{Src|Result}XD() uses "{SUB|ADD} ESP,8" 10630 format %{ "DTAN $dst" %} 10631 ins_encode( Push_SrcXD(dst), 10632 Opcode(0xD9), Opcode(0xF2), // fptan 10633 Opcode(0xDD), Opcode(0xD8), // fstp st 10634 Push_ResultXD(dst) ); 10635 ins_pipe( pipe_slow ); 10636 %} 10637 10638 instruct atanD_reg(regD dst, regD src) %{ 10639 predicate (UseSSE<=1); 10640 match(Set dst(AtanD dst src)); 10641 format %{ "DATA $dst,$src" %} 10642 opcode(0xD9, 0xF3); 10643 ins_encode( Push_Reg_D(src), 10644 OpcP, OpcS, RegOpc(dst) ); 10645 ins_pipe( pipe_slow ); 10646 %} 10647 10648 instruct atanXD_reg(regXD dst, regXD src, eFlagsReg cr) %{ 10649 predicate (UseSSE>=2); 10650 match(Set dst(AtanD dst src)); 10651 effect(KILL cr); // Push_{Src|Result}XD() uses "{SUB|ADD} ESP,8" 10652 format %{ "DATA $dst,$src" %} 10653 opcode(0xD9, 0xF3); 10654 ins_encode( Push_SrcXD(src), 10655 OpcP, OpcS, Push_ResultXD(dst) ); 10656 ins_pipe( pipe_slow ); 10657 %} 10658 10659 instruct sqrtD_reg(regD dst, regD src) %{ 10660 predicate (UseSSE<=1); 10661 match(Set dst (SqrtD src)); 10662 format %{ "DSQRT $dst,$src" %} 10663 opcode(0xFA, 0xD9); 10664 ins_encode( Push_Reg_D(src), 10665 OpcS, OpcP, Pop_Reg_D(dst) ); 10666 ins_pipe( pipe_slow ); 10667 %} 10668 10669 instruct powD_reg(regD X, regDPR1 Y, eAXRegI rax, eBXRegI rbx, eCXRegI rcx) %{ 10670 predicate (UseSSE<=1); 10671 match(Set Y (PowD X Y)); // Raise X to the Yth power 10672 effect(KILL rax, KILL rbx, KILL rcx); 10673 format %{ "SUB ESP,8\t\t# Fast-path POW encoding\n\t" 10674 "FLD_D $X\n\t" 10675 "FYL2X \t\t\t# Q=Y*ln2(X)\n\t" 10676 10677 "FDUP \t\t\t# Q Q\n\t" 10678 "FRNDINT\t\t\t# int(Q) Q\n\t" 10679 "FSUB ST(1),ST(0)\t# int(Q) frac(Q)\n\t" 10680 "FISTP dword [ESP]\n\t" 10681 "F2XM1 \t\t\t# 2^frac(Q)-1 int(Q)\n\t" 10682 "FLD1 \t\t\t# 1 2^frac(Q)-1 int(Q)\n\t" 10683 "FADDP \t\t\t# 2^frac(Q) int(Q)\n\t" // could use FADD [1.000] instead 10684 "MOV EAX,[ESP]\t# Pick up int(Q)\n\t" 10685 "MOV ECX,0xFFFFF800\t# Overflow mask\n\t" 10686 "ADD EAX,1023\t\t# Double exponent bias\n\t" 10687 "MOV EBX,EAX\t\t# Preshifted biased expo\n\t" 10688 "SHL EAX,20\t\t# Shift exponent into place\n\t" 10689 "TEST EBX,ECX\t\t# Check for overflow\n\t" 10690 "CMOVne EAX,ECX\t\t# If overflow, stuff NaN into EAX\n\t" 10691 "MOV [ESP+4],EAX\t# Marshal 64-bit scaling double\n\t" 10692 "MOV [ESP+0],0\n\t" 10693 "FMUL ST(0),[ESP+0]\t# Scale\n\t" 10694 10695 "ADD ESP,8" 10696 %} 10697 ins_encode( push_stack_temp_qword, 10698 Push_Reg_D(X), 10699 Opcode(0xD9), Opcode(0xF1), // fyl2x 10700 pow_exp_core_encoding, 10701 pop_stack_temp_qword); 10702 ins_pipe( pipe_slow ); 10703 %} 10704 10705 instruct powXD_reg(regXD dst, regXD src0, regXD src1, regDPR1 tmp1, eAXRegI rax, eBXRegI rbx, eCXRegI rcx ) %{ 10706 predicate (UseSSE>=2); 10707 match(Set dst (PowD src0 src1)); // Raise src0 to the src1'th power 10708 effect(KILL tmp1, KILL rax, KILL rbx, KILL rcx ); 10709 format %{ "SUB ESP,8\t\t# Fast-path POW encoding\n\t" 10710 "MOVSD [ESP],$src1\n\t" 10711 "FLD FPR1,$src1\n\t" 10712 "MOVSD [ESP],$src0\n\t" 10713 "FLD FPR1,$src0\n\t" 10714 "FYL2X \t\t\t# Q=Y*ln2(X)\n\t" 10715 10716 "FDUP \t\t\t# Q Q\n\t" 10717 "FRNDINT\t\t\t# int(Q) Q\n\t" 10718 "FSUB ST(1),ST(0)\t# int(Q) frac(Q)\n\t" 10719 "FISTP dword [ESP]\n\t" 10720 "F2XM1 \t\t\t# 2^frac(Q)-1 int(Q)\n\t" 10721 "FLD1 \t\t\t# 1 2^frac(Q)-1 int(Q)\n\t" 10722 "FADDP \t\t\t# 2^frac(Q) int(Q)\n\t" // could use FADD [1.000] instead 10723 "MOV EAX,[ESP]\t# Pick up int(Q)\n\t" 10724 "MOV ECX,0xFFFFF800\t# Overflow mask\n\t" 10725 "ADD EAX,1023\t\t# Double exponent bias\n\t" 10726 "MOV EBX,EAX\t\t# Preshifted biased expo\n\t" 10727 "SHL EAX,20\t\t# Shift exponent into place\n\t" 10728 "TEST EBX,ECX\t\t# Check for overflow\n\t" 10729 "CMOVne EAX,ECX\t\t# If overflow, stuff NaN into EAX\n\t" 10730 "MOV [ESP+4],EAX\t# Marshal 64-bit scaling double\n\t" 10731 "MOV [ESP+0],0\n\t" 10732 "FMUL ST(0),[ESP+0]\t# Scale\n\t" 10733 10734 "FST_D [ESP]\n\t" 10735 "MOVSD $dst,[ESP]\n\t" 10736 "ADD ESP,8" 10737 %} 10738 ins_encode( push_stack_temp_qword, 10739 push_xmm_to_fpr1(src1), 10740 push_xmm_to_fpr1(src0), 10741 Opcode(0xD9), Opcode(0xF1), // fyl2x 10742 pow_exp_core_encoding, 10743 Push_ResultXD(dst) ); 10744 ins_pipe( pipe_slow ); 10745 %} 10746 10747 10748 instruct expD_reg(regDPR1 dpr1, eAXRegI rax, eBXRegI rbx, eCXRegI rcx) %{ 10749 predicate (UseSSE<=1); 10750 match(Set dpr1 (ExpD dpr1)); 10751 effect(KILL rax, KILL rbx, KILL rcx); 10752 format %{ "SUB ESP,8\t\t# Fast-path EXP encoding" 10753 "FLDL2E \t\t\t# Ld log2(e) X\n\t" 10754 "FMULP \t\t\t# Q=X*log2(e)\n\t" 10755 10756 "FDUP \t\t\t# Q Q\n\t" 10757 "FRNDINT\t\t\t# int(Q) Q\n\t" 10758 "FSUB ST(1),ST(0)\t# int(Q) frac(Q)\n\t" 10759 "FISTP dword [ESP]\n\t" 10760 "F2XM1 \t\t\t# 2^frac(Q)-1 int(Q)\n\t" 10761 "FLD1 \t\t\t# 1 2^frac(Q)-1 int(Q)\n\t" 10762 "FADDP \t\t\t# 2^frac(Q) int(Q)\n\t" // could use FADD [1.000] instead 10763 "MOV EAX,[ESP]\t# Pick up int(Q)\n\t" 10764 "MOV ECX,0xFFFFF800\t# Overflow mask\n\t" 10765 "ADD EAX,1023\t\t# Double exponent bias\n\t" 10766 "MOV EBX,EAX\t\t# Preshifted biased expo\n\t" 10767 "SHL EAX,20\t\t# Shift exponent into place\n\t" 10768 "TEST EBX,ECX\t\t# Check for overflow\n\t" 10769 "CMOVne EAX,ECX\t\t# If overflow, stuff NaN into EAX\n\t" 10770 "MOV [ESP+4],EAX\t# Marshal 64-bit scaling double\n\t" 10771 "MOV [ESP+0],0\n\t" 10772 "FMUL ST(0),[ESP+0]\t# Scale\n\t" 10773 10774 "ADD ESP,8" 10775 %} 10776 ins_encode( push_stack_temp_qword, 10777 Opcode(0xD9), Opcode(0xEA), // fldl2e 10778 Opcode(0xDE), Opcode(0xC9), // fmulp 10779 pow_exp_core_encoding, 10780 pop_stack_temp_qword); 10781 ins_pipe( pipe_slow ); 10782 %} 10783 10784 instruct expXD_reg(regXD dst, regXD src, regDPR1 tmp1, eAXRegI rax, eBXRegI rbx, eCXRegI rcx) %{ 10785 predicate (UseSSE>=2); 10786 match(Set dst (ExpD src)); 10787 effect(KILL tmp1, KILL rax, KILL rbx, KILL rcx); 10788 format %{ "SUB ESP,8\t\t# Fast-path EXP encoding\n\t" 10789 "MOVSD [ESP],$src\n\t" 10790 "FLDL2E \t\t\t# Ld log2(e) X\n\t" 10791 "FMULP \t\t\t# Q=X*log2(e) X\n\t" 10792 10793 "FDUP \t\t\t# Q Q\n\t" 10794 "FRNDINT\t\t\t# int(Q) Q\n\t" 10795 "FSUB ST(1),ST(0)\t# int(Q) frac(Q)\n\t" 10796 "FISTP dword [ESP]\n\t" 10797 "F2XM1 \t\t\t# 2^frac(Q)-1 int(Q)\n\t" 10798 "FLD1 \t\t\t# 1 2^frac(Q)-1 int(Q)\n\t" 10799 "FADDP \t\t\t# 2^frac(Q) int(Q)\n\t" // could use FADD [1.000] instead 10800 "MOV EAX,[ESP]\t# Pick up int(Q)\n\t" 10801 "MOV ECX,0xFFFFF800\t# Overflow mask\n\t" 10802 "ADD EAX,1023\t\t# Double exponent bias\n\t" 10803 "MOV EBX,EAX\t\t# Preshifted biased expo\n\t" 10804 "SHL EAX,20\t\t# Shift exponent into place\n\t" 10805 "TEST EBX,ECX\t\t# Check for overflow\n\t" 10806 "CMOVne EAX,ECX\t\t# If overflow, stuff NaN into EAX\n\t" 10807 "MOV [ESP+4],EAX\t# Marshal 64-bit scaling double\n\t" 10808 "MOV [ESP+0],0\n\t" 10809 "FMUL ST(0),[ESP+0]\t# Scale\n\t" 10810 10811 "FST_D [ESP]\n\t" 10812 "MOVSD $dst,[ESP]\n\t" 10813 "ADD ESP,8" 10814 %} 10815 ins_encode( Push_SrcXD(src), 10816 Opcode(0xD9), Opcode(0xEA), // fldl2e 10817 Opcode(0xDE), Opcode(0xC9), // fmulp 10818 pow_exp_core_encoding, 10819 Push_ResultXD(dst) ); 10820 ins_pipe( pipe_slow ); 10821 %} 10822 10823 10824 10825 instruct log10D_reg(regDPR1 dst, regDPR1 src) %{ 10826 predicate (UseSSE<=1); 10827 // The source Double operand on FPU stack 10828 match(Set dst (Log10D src)); 10829 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number 10830 // fxch ; swap ST(0) with ST(1) 10831 // fyl2x ; compute log_10(2) * log_2(x) 10832 format %{ "FLDLG2 \t\t\t#Log10\n\t" 10833 "FXCH \n\t" 10834 "FYL2X \t\t\t# Q=Log10*Log_2(x)" 10835 %} 10836 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2 10837 Opcode(0xD9), Opcode(0xC9), // fxch 10838 Opcode(0xD9), Opcode(0xF1)); // fyl2x 10839 10840 ins_pipe( pipe_slow ); 10841 %} 10842 10843 instruct log10XD_reg(regXD dst, regXD src, eFlagsReg cr) %{ 10844 predicate (UseSSE>=2); 10845 effect(KILL cr); 10846 match(Set dst (Log10D src)); 10847 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number 10848 // fyl2x ; compute log_10(2) * log_2(x) 10849 format %{ "FLDLG2 \t\t\t#Log10\n\t" 10850 "FYL2X \t\t\t# Q=Log10*Log_2(x)" 10851 %} 10852 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2 10853 Push_SrcXD(src), 10854 Opcode(0xD9), Opcode(0xF1), // fyl2x 10855 Push_ResultXD(dst)); 10856 10857 ins_pipe( pipe_slow ); 10858 %} 10859 10860 instruct logD_reg(regDPR1 dst, regDPR1 src) %{ 10861 predicate (UseSSE<=1); 10862 // The source Double operand on FPU stack 10863 match(Set dst (LogD src)); 10864 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number 10865 // fxch ; swap ST(0) with ST(1) 10866 // fyl2x ; compute log_e(2) * log_2(x) 10867 format %{ "FLDLN2 \t\t\t#Log_e\n\t" 10868 "FXCH \n\t" 10869 "FYL2X \t\t\t# Q=Log_e*Log_2(x)" 10870 %} 10871 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2 10872 Opcode(0xD9), Opcode(0xC9), // fxch 10873 Opcode(0xD9), Opcode(0xF1)); // fyl2x 10874 10875 ins_pipe( pipe_slow ); 10876 %} 10877 10878 instruct logXD_reg(regXD dst, regXD src, eFlagsReg cr) %{ 10879 predicate (UseSSE>=2); 10880 effect(KILL cr); 10881 // The source and result Double operands in XMM registers 10882 match(Set dst (LogD src)); 10883 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number 10884 // fyl2x ; compute log_e(2) * log_2(x) 10885 format %{ "FLDLN2 \t\t\t#Log_e\n\t" 10886 "FYL2X \t\t\t# Q=Log_e*Log_2(x)" 10887 %} 10888 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2 10889 Push_SrcXD(src), 10890 Opcode(0xD9), Opcode(0xF1), // fyl2x 10891 Push_ResultXD(dst)); 10892 ins_pipe( pipe_slow ); 10893 %} 10894 10895 //-------------Float Instructions------------------------------- 10896 // Float Math 10897 10898 // Code for float compare: 10899 // fcompp(); 10900 // fwait(); fnstsw_ax(); 10901 // sahf(); 10902 // movl(dst, unordered_result); 10903 // jcc(Assembler::parity, exit); 10904 // movl(dst, less_result); 10905 // jcc(Assembler::below, exit); 10906 // movl(dst, equal_result); 10907 // jcc(Assembler::equal, exit); 10908 // movl(dst, greater_result); 10909 // exit: 10910 10911 // P6 version of float compare, sets condition codes in EFLAGS 10912 instruct cmpF_cc_P6(eFlagsRegU cr, regF src1, regF src2, eAXRegI rax) %{ 10913 predicate(VM_Version::supports_cmov() && UseSSE == 0); 10914 match(Set cr (CmpF src1 src2)); 10915 effect(KILL rax); 10916 ins_cost(150); 10917 format %{ "FLD $src1\n\t" 10918 "FUCOMIP ST,$src2 // P6 instruction\n\t" 10919 "JNP exit\n\t" 10920 "MOV ah,1 // saw a NaN, set CF (treat as LT)\n\t" 10921 "SAHF\n" 10922 "exit:\tNOP // avoid branch to branch" %} 10923 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */ 10924 ins_encode( Push_Reg_D(src1), 10925 OpcP, RegOpc(src2), 10926 cmpF_P6_fixup ); 10927 ins_pipe( pipe_slow ); 10928 %} 10929 10930 instruct cmpF_cc_P6CF(eFlagsRegUCF cr, regF src1, regF src2) %{ 10931 predicate(VM_Version::supports_cmov() && UseSSE == 0); 10932 match(Set cr (CmpF src1 src2)); 10933 ins_cost(100); 10934 format %{ "FLD $src1\n\t" 10935 "FUCOMIP ST,$src2 // P6 instruction" %} 10936 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */ 10937 ins_encode( Push_Reg_D(src1), 10938 OpcP, RegOpc(src2)); 10939 ins_pipe( pipe_slow ); 10940 %} 10941 10942 10943 // Compare & branch 10944 instruct cmpF_cc(eFlagsRegU cr, regF src1, regF src2, eAXRegI rax) %{ 10945 predicate(UseSSE == 0); 10946 match(Set cr (CmpF src1 src2)); 10947 effect(KILL rax); 10948 ins_cost(200); 10949 format %{ "FLD $src1\n\t" 10950 "FCOMp $src2\n\t" 10951 "FNSTSW AX\n\t" 10952 "TEST AX,0x400\n\t" 10953 "JZ,s flags\n\t" 10954 "MOV AH,1\t# unordered treat as LT\n" 10955 "flags:\tSAHF" %} 10956 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */ 10957 ins_encode( Push_Reg_D(src1), 10958 OpcP, RegOpc(src2), 10959 fpu_flags); 10960 ins_pipe( pipe_slow ); 10961 %} 10962 10963 // Compare vs zero into -1,0,1 10964 instruct cmpF_0(eRegI dst, regF src1, immF0 zero, eAXRegI rax, eFlagsReg cr) %{ 10965 predicate(UseSSE == 0); 10966 match(Set dst (CmpF3 src1 zero)); 10967 effect(KILL cr, KILL rax); 10968 ins_cost(280); 10969 format %{ "FTSTF $dst,$src1" %} 10970 opcode(0xE4, 0xD9); 10971 ins_encode( Push_Reg_D(src1), 10972 OpcS, OpcP, PopFPU, 10973 CmpF_Result(dst)); 10974 ins_pipe( pipe_slow ); 10975 %} 10976 10977 // Compare into -1,0,1 10978 instruct cmpF_reg(eRegI dst, regF src1, regF src2, eAXRegI rax, eFlagsReg cr) %{ 10979 predicate(UseSSE == 0); 10980 match(Set dst (CmpF3 src1 src2)); 10981 effect(KILL cr, KILL rax); 10982 ins_cost(300); 10983 format %{ "FCMPF $dst,$src1,$src2" %} 10984 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */ 10985 ins_encode( Push_Reg_D(src1), 10986 OpcP, RegOpc(src2), 10987 CmpF_Result(dst)); 10988 ins_pipe( pipe_slow ); 10989 %} 10990 10991 // float compare and set condition codes in EFLAGS by XMM regs 10992 instruct cmpX_cc(eFlagsRegU cr, regX dst, regX src, eAXRegI rax) %{ 10993 predicate(UseSSE>=1); 10994 match(Set cr (CmpF dst src)); 10995 effect(KILL rax); 10996 ins_cost(145); 10997 format %{ "COMISS $dst,$src\n" 10998 "\tJNP exit\n" 10999 "\tMOV ah,1 // saw a NaN, set CF\n" 11000 "\tSAHF\n" 11001 "exit:\tNOP // avoid branch to branch" %} 11002 opcode(0x0F, 0x2F); 11003 ins_encode(OpcP, OpcS, RegReg(dst, src), cmpF_P6_fixup); 11004 ins_pipe( pipe_slow ); 11005 %} 11006 11007 instruct cmpX_ccCF(eFlagsRegUCF cr, regX dst, regX src) %{ 11008 predicate(UseSSE>=1); 11009 match(Set cr (CmpF dst src)); 11010 ins_cost(100); 11011 format %{ "COMISS $dst,$src" %} 11012 opcode(0x0F, 0x2F); 11013 ins_encode(OpcP, OpcS, RegReg(dst, src)); 11014 ins_pipe( pipe_slow ); 11015 %} 11016 11017 // float compare and set condition codes in EFLAGS by XMM regs 11018 instruct cmpX_ccmem(eFlagsRegU cr, regX dst, memory src, eAXRegI rax) %{ 11019 predicate(UseSSE>=1); 11020 match(Set cr (CmpF dst (LoadF src))); 11021 effect(KILL rax); 11022 ins_cost(165); 11023 format %{ "COMISS $dst,$src\n" 11024 "\tJNP exit\n" 11025 "\tMOV ah,1 // saw a NaN, set CF\n" 11026 "\tSAHF\n" 11027 "exit:\tNOP // avoid branch to branch" %} 11028 opcode(0x0F, 0x2F); 11029 ins_encode(OpcP, OpcS, RegMem(dst, src), cmpF_P6_fixup); 11030 ins_pipe( pipe_slow ); 11031 %} 11032 11033 instruct cmpX_ccmemCF(eFlagsRegUCF cr, regX dst, memory src) %{ 11034 predicate(UseSSE>=1); 11035 match(Set cr (CmpF dst (LoadF src))); 11036 ins_cost(100); 11037 format %{ "COMISS $dst,$src" %} 11038 opcode(0x0F, 0x2F); 11039 ins_encode(OpcP, OpcS, RegMem(dst, src)); 11040 ins_pipe( pipe_slow ); 11041 %} 11042 11043 // Compare into -1,0,1 in XMM 11044 instruct cmpX_reg(eRegI dst, regX src1, regX src2, eFlagsReg cr) %{ 11045 predicate(UseSSE>=1); 11046 match(Set dst (CmpF3 src1 src2)); 11047 effect(KILL cr); 11048 ins_cost(255); 11049 format %{ "XOR $dst,$dst\n" 11050 "\tCOMISS $src1,$src2\n" 11051 "\tJP,s nan\n" 11052 "\tJEQ,s exit\n" 11053 "\tJA,s inc\n" 11054 "nan:\tDEC $dst\n" 11055 "\tJMP,s exit\n" 11056 "inc:\tINC $dst\n" 11057 "exit:" 11058 %} 11059 opcode(0x0F, 0x2F); 11060 ins_encode(Xor_Reg(dst), OpcP, OpcS, RegReg(src1, src2), CmpX_Result(dst)); 11061 ins_pipe( pipe_slow ); 11062 %} 11063 11064 // Compare into -1,0,1 in XMM and memory 11065 instruct cmpX_regmem(eRegI dst, regX src1, memory mem, eFlagsReg cr) %{ 11066 predicate(UseSSE>=1); 11067 match(Set dst (CmpF3 src1 (LoadF mem))); 11068 effect(KILL cr); 11069 ins_cost(275); 11070 format %{ "COMISS $src1,$mem\n" 11071 "\tMOV $dst,0\t\t# do not blow flags\n" 11072 "\tJP,s nan\n" 11073 "\tJEQ,s exit\n" 11074 "\tJA,s inc\n" 11075 "nan:\tDEC $dst\n" 11076 "\tJMP,s exit\n" 11077 "inc:\tINC $dst\n" 11078 "exit:" 11079 %} 11080 opcode(0x0F, 0x2F); 11081 ins_encode(OpcP, OpcS, RegMem(src1, mem), LdImmI(dst,0x0), CmpX_Result(dst)); 11082 ins_pipe( pipe_slow ); 11083 %} 11084 11085 // Spill to obtain 24-bit precision 11086 instruct subF24_reg(stackSlotF dst, regF src1, regF src2) %{ 11087 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); 11088 match(Set dst (SubF src1 src2)); 11089 11090 format %{ "FSUB $dst,$src1 - $src2" %} 11091 opcode(0xD8, 0x4); /* D8 E0+i or D8 /4 mod==0x3 ;; result in TOS */ 11092 ins_encode( Push_Reg_F(src1), 11093 OpcReg_F(src2), 11094 Pop_Mem_F(dst) ); 11095 ins_pipe( fpu_mem_reg_reg ); 11096 %} 11097 // 11098 // This instruction does not round to 24-bits 11099 instruct subF_reg(regF dst, regF src) %{ 11100 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); 11101 match(Set dst (SubF dst src)); 11102 11103 format %{ "FSUB $dst,$src" %} 11104 opcode(0xDE, 0x5); /* DE E8+i or DE /5 */ 11105 ins_encode( Push_Reg_F(src), 11106 OpcP, RegOpc(dst) ); 11107 ins_pipe( fpu_reg_reg ); 11108 %} 11109 11110 // Spill to obtain 24-bit precision 11111 instruct addF24_reg(stackSlotF dst, regF src1, regF src2) %{ 11112 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); 11113 match(Set dst (AddF src1 src2)); 11114 11115 format %{ "FADD $dst,$src1,$src2" %} 11116 opcode(0xD8, 0x0); /* D8 C0+i */ 11117 ins_encode( Push_Reg_F(src2), 11118 OpcReg_F(src1), 11119 Pop_Mem_F(dst) ); 11120 ins_pipe( fpu_mem_reg_reg ); 11121 %} 11122 // 11123 // This instruction does not round to 24-bits 11124 instruct addF_reg(regF dst, regF src) %{ 11125 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); 11126 match(Set dst (AddF dst src)); 11127 11128 format %{ "FLD $src\n\t" 11129 "FADDp $dst,ST" %} 11130 opcode(0xDE, 0x0); /* DE C0+i or DE /0*/ 11131 ins_encode( Push_Reg_F(src), 11132 OpcP, RegOpc(dst) ); 11133 ins_pipe( fpu_reg_reg ); 11134 %} 11135 11136 // Add two single precision floating point values in xmm 11137 instruct addX_reg(regX dst, regX src) %{ 11138 predicate(UseSSE>=1); 11139 match(Set dst (AddF dst src)); 11140 format %{ "ADDSS $dst,$src" %} 11141 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x58), RegReg(dst, src)); 11142 ins_pipe( pipe_slow ); 11143 %} 11144 11145 instruct addX_imm(regX dst, immXF con) %{ 11146 predicate(UseSSE>=1); 11147 match(Set dst (AddF dst con)); 11148 format %{ "ADDSS $dst,[$con]" %} 11149 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x58), LdImmX(dst, con) ); 11150 ins_pipe( pipe_slow ); 11151 %} 11152 11153 instruct addX_mem(regX dst, memory mem) %{ 11154 predicate(UseSSE>=1); 11155 match(Set dst (AddF dst (LoadF mem))); 11156 format %{ "ADDSS $dst,$mem" %} 11157 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x58), RegMem(dst, mem)); 11158 ins_pipe( pipe_slow ); 11159 %} 11160 11161 // Subtract two single precision floating point values in xmm 11162 instruct subX_reg(regX dst, regX src) %{ 11163 predicate(UseSSE>=1); 11164 match(Set dst (SubF dst src)); 11165 format %{ "SUBSS $dst,$src" %} 11166 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5C), RegReg(dst, src)); 11167 ins_pipe( pipe_slow ); 11168 %} 11169 11170 instruct subX_imm(regX dst, immXF con) %{ 11171 predicate(UseSSE>=1); 11172 match(Set dst (SubF dst con)); 11173 format %{ "SUBSS $dst,[$con]" %} 11174 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5C), LdImmX(dst, con) ); 11175 ins_pipe( pipe_slow ); 11176 %} 11177 11178 instruct subX_mem(regX dst, memory mem) %{ 11179 predicate(UseSSE>=1); 11180 match(Set dst (SubF dst (LoadF mem))); 11181 format %{ "SUBSS $dst,$mem" %} 11182 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5C), RegMem(dst,mem)); 11183 ins_pipe( pipe_slow ); 11184 %} 11185 11186 // Multiply two single precision floating point values in xmm 11187 instruct mulX_reg(regX dst, regX src) %{ 11188 predicate(UseSSE>=1); 11189 match(Set dst (MulF dst src)); 11190 format %{ "MULSS $dst,$src" %} 11191 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x59), RegReg(dst, src)); 11192 ins_pipe( pipe_slow ); 11193 %} 11194 11195 instruct mulX_imm(regX dst, immXF con) %{ 11196 predicate(UseSSE>=1); 11197 match(Set dst (MulF dst con)); 11198 format %{ "MULSS $dst,[$con]" %} 11199 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x59), LdImmX(dst, con) ); 11200 ins_pipe( pipe_slow ); 11201 %} 11202 11203 instruct mulX_mem(regX dst, memory mem) %{ 11204 predicate(UseSSE>=1); 11205 match(Set dst (MulF dst (LoadF mem))); 11206 format %{ "MULSS $dst,$mem" %} 11207 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x59), RegMem(dst,mem)); 11208 ins_pipe( pipe_slow ); 11209 %} 11210 11211 // Divide two single precision floating point values in xmm 11212 instruct divX_reg(regX dst, regX src) %{ 11213 predicate(UseSSE>=1); 11214 match(Set dst (DivF dst src)); 11215 format %{ "DIVSS $dst,$src" %} 11216 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5E), RegReg(dst, src)); 11217 ins_pipe( pipe_slow ); 11218 %} 11219 11220 instruct divX_imm(regX dst, immXF con) %{ 11221 predicate(UseSSE>=1); 11222 match(Set dst (DivF dst con)); 11223 format %{ "DIVSS $dst,[$con]" %} 11224 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5E), LdImmX(dst, con) ); 11225 ins_pipe( pipe_slow ); 11226 %} 11227 11228 instruct divX_mem(regX dst, memory mem) %{ 11229 predicate(UseSSE>=1); 11230 match(Set dst (DivF dst (LoadF mem))); 11231 format %{ "DIVSS $dst,$mem" %} 11232 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5E), RegMem(dst,mem)); 11233 ins_pipe( pipe_slow ); 11234 %} 11235 11236 // Get the square root of a single precision floating point values in xmm 11237 instruct sqrtX_reg(regX dst, regX src) %{ 11238 predicate(UseSSE>=1); 11239 match(Set dst (ConvD2F (SqrtD (ConvF2D src)))); 11240 format %{ "SQRTSS $dst,$src" %} 11241 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x51), RegReg(dst, src)); 11242 ins_pipe( pipe_slow ); 11243 %} 11244 11245 instruct sqrtX_mem(regX dst, memory mem) %{ 11246 predicate(UseSSE>=1); 11247 match(Set dst (ConvD2F (SqrtD (ConvF2D (LoadF mem))))); 11248 format %{ "SQRTSS $dst,$mem" %} 11249 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x51), RegMem(dst, mem)); 11250 ins_pipe( pipe_slow ); 11251 %} 11252 11253 // Get the square root of a double precision floating point values in xmm 11254 instruct sqrtXD_reg(regXD dst, regXD src) %{ 11255 predicate(UseSSE>=2); 11256 match(Set dst (SqrtD src)); 11257 format %{ "SQRTSD $dst,$src" %} 11258 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x51), RegReg(dst, src)); 11259 ins_pipe( pipe_slow ); 11260 %} 11261 11262 instruct sqrtXD_mem(regXD dst, memory mem) %{ 11263 predicate(UseSSE>=2); 11264 match(Set dst (SqrtD (LoadD mem))); 11265 format %{ "SQRTSD $dst,$mem" %} 11266 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x51), RegMem(dst, mem)); 11267 ins_pipe( pipe_slow ); 11268 %} 11269 11270 instruct absF_reg(regFPR1 dst, regFPR1 src) %{ 11271 predicate(UseSSE==0); 11272 match(Set dst (AbsF src)); 11273 ins_cost(100); 11274 format %{ "FABS" %} 11275 opcode(0xE1, 0xD9); 11276 ins_encode( OpcS, OpcP ); 11277 ins_pipe( fpu_reg_reg ); 11278 %} 11279 11280 instruct absX_reg(regX dst ) %{ 11281 predicate(UseSSE>=1); 11282 match(Set dst (AbsF dst)); 11283 format %{ "ANDPS $dst,[0x7FFFFFFF]\t# ABS F by sign masking" %} 11284 ins_encode( AbsXF_encoding(dst)); 11285 ins_pipe( pipe_slow ); 11286 %} 11287 11288 instruct negF_reg(regFPR1 dst, regFPR1 src) %{ 11289 predicate(UseSSE==0); 11290 match(Set dst (NegF src)); 11291 ins_cost(100); 11292 format %{ "FCHS" %} 11293 opcode(0xE0, 0xD9); 11294 ins_encode( OpcS, OpcP ); 11295 ins_pipe( fpu_reg_reg ); 11296 %} 11297 11298 instruct negX_reg( regX dst ) %{ 11299 predicate(UseSSE>=1); 11300 match(Set dst (NegF dst)); 11301 format %{ "XORPS $dst,[0x80000000]\t# CHS F by sign flipping" %} 11302 ins_encode( NegXF_encoding(dst)); 11303 ins_pipe( pipe_slow ); 11304 %} 11305 11306 // Cisc-alternate to addF_reg 11307 // Spill to obtain 24-bit precision 11308 instruct addF24_reg_mem(stackSlotF dst, regF src1, memory src2) %{ 11309 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); 11310 match(Set dst (AddF src1 (LoadF src2))); 11311 11312 format %{ "FLD $src2\n\t" 11313 "FADD ST,$src1\n\t" 11314 "FSTP_S $dst" %} 11315 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */ 11316 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2), 11317 OpcReg_F(src1), 11318 Pop_Mem_F(dst) ); 11319 ins_pipe( fpu_mem_reg_mem ); 11320 %} 11321 // 11322 // Cisc-alternate to addF_reg 11323 // This instruction does not round to 24-bits 11324 instruct addF_reg_mem(regF dst, memory src) %{ 11325 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); 11326 match(Set dst (AddF dst (LoadF src))); 11327 11328 format %{ "FADD $dst,$src" %} 11329 opcode(0xDE, 0x0, 0xD9); /* DE C0+i or DE /0*/ /* LoadF D9 /0 */ 11330 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src), 11331 OpcP, RegOpc(dst) ); 11332 ins_pipe( fpu_reg_mem ); 11333 %} 11334 11335 // // Following two instructions for _222_mpegaudio 11336 // Spill to obtain 24-bit precision 11337 instruct addF24_mem_reg(stackSlotF dst, regF src2, memory src1 ) %{ 11338 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); 11339 match(Set dst (AddF src1 src2)); 11340 11341 format %{ "FADD $dst,$src1,$src2" %} 11342 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */ 11343 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src1), 11344 OpcReg_F(src2), 11345 Pop_Mem_F(dst) ); 11346 ins_pipe( fpu_mem_reg_mem ); 11347 %} 11348 11349 // Cisc-spill variant 11350 // Spill to obtain 24-bit precision 11351 instruct addF24_mem_cisc(stackSlotF dst, memory src1, memory src2) %{ 11352 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); 11353 match(Set dst (AddF src1 (LoadF src2))); 11354 11355 format %{ "FADD $dst,$src1,$src2 cisc" %} 11356 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */ 11357 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2), 11358 set_instruction_start, 11359 OpcP, RMopc_Mem(secondary,src1), 11360 Pop_Mem_F(dst) ); 11361 ins_pipe( fpu_mem_mem_mem ); 11362 %} 11363 11364 // Spill to obtain 24-bit precision 11365 instruct addF24_mem_mem(stackSlotF dst, memory src1, memory src2) %{ 11366 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); 11367 match(Set dst (AddF src1 src2)); 11368 11369 format %{ "FADD $dst,$src1,$src2" %} 11370 opcode(0xD8, 0x0, 0xD9); /* D8 /0 */ /* LoadF D9 /0 */ 11371 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2), 11372 set_instruction_start, 11373 OpcP, RMopc_Mem(secondary,src1), 11374 Pop_Mem_F(dst) ); 11375 ins_pipe( fpu_mem_mem_mem ); 11376 %} 11377 11378 11379 // Spill to obtain 24-bit precision 11380 instruct addF24_reg_imm(stackSlotF dst, regF src1, immF src2) %{ 11381 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); 11382 match(Set dst (AddF src1 src2)); 11383 format %{ "FLD $src1\n\t" 11384 "FADD $src2\n\t" 11385 "FSTP_S $dst" %} 11386 opcode(0xD8, 0x00); /* D8 /0 */ 11387 ins_encode( Push_Reg_F(src1), 11388 Opc_MemImm_F(src2), 11389 Pop_Mem_F(dst)); 11390 ins_pipe( fpu_mem_reg_con ); 11391 %} 11392 // 11393 // This instruction does not round to 24-bits 11394 instruct addF_reg_imm(regF dst, regF src1, immF src2) %{ 11395 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); 11396 match(Set dst (AddF src1 src2)); 11397 format %{ "FLD $src1\n\t" 11398 "FADD $src2\n\t" 11399 "FSTP_S $dst" %} 11400 opcode(0xD8, 0x00); /* D8 /0 */ 11401 ins_encode( Push_Reg_F(src1), 11402 Opc_MemImm_F(src2), 11403 Pop_Reg_F(dst)); 11404 ins_pipe( fpu_reg_reg_con ); 11405 %} 11406 11407 // Spill to obtain 24-bit precision 11408 instruct mulF24_reg(stackSlotF dst, regF src1, regF src2) %{ 11409 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); 11410 match(Set dst (MulF src1 src2)); 11411 11412 format %{ "FLD $src1\n\t" 11413 "FMUL $src2\n\t" 11414 "FSTP_S $dst" %} 11415 opcode(0xD8, 0x1); /* D8 C8+i or D8 /1 ;; result in TOS */ 11416 ins_encode( Push_Reg_F(src1), 11417 OpcReg_F(src2), 11418 Pop_Mem_F(dst) ); 11419 ins_pipe( fpu_mem_reg_reg ); 11420 %} 11421 // 11422 // This instruction does not round to 24-bits 11423 instruct mulF_reg(regF dst, regF src1, regF src2) %{ 11424 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); 11425 match(Set dst (MulF src1 src2)); 11426 11427 format %{ "FLD $src1\n\t" 11428 "FMUL $src2\n\t" 11429 "FSTP_S $dst" %} 11430 opcode(0xD8, 0x1); /* D8 C8+i */ 11431 ins_encode( Push_Reg_F(src2), 11432 OpcReg_F(src1), 11433 Pop_Reg_F(dst) ); 11434 ins_pipe( fpu_reg_reg_reg ); 11435 %} 11436 11437 11438 // Spill to obtain 24-bit precision 11439 // Cisc-alternate to reg-reg multiply 11440 instruct mulF24_reg_mem(stackSlotF dst, regF src1, memory src2) %{ 11441 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); 11442 match(Set dst (MulF src1 (LoadF src2))); 11443 11444 format %{ "FLD_S $src2\n\t" 11445 "FMUL $src1\n\t" 11446 "FSTP_S $dst" %} 11447 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or DE /1*/ /* LoadF D9 /0 */ 11448 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2), 11449 OpcReg_F(src1), 11450 Pop_Mem_F(dst) ); 11451 ins_pipe( fpu_mem_reg_mem ); 11452 %} 11453 // 11454 // This instruction does not round to 24-bits 11455 // Cisc-alternate to reg-reg multiply 11456 instruct mulF_reg_mem(regF dst, regF src1, memory src2) %{ 11457 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); 11458 match(Set dst (MulF src1 (LoadF src2))); 11459 11460 format %{ "FMUL $dst,$src1,$src2" %} 11461 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */ /* LoadF D9 /0 */ 11462 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2), 11463 OpcReg_F(src1), 11464 Pop_Reg_F(dst) ); 11465 ins_pipe( fpu_reg_reg_mem ); 11466 %} 11467 11468 // Spill to obtain 24-bit precision 11469 instruct mulF24_mem_mem(stackSlotF dst, memory src1, memory src2) %{ 11470 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); 11471 match(Set dst (MulF src1 src2)); 11472 11473 format %{ "FMUL $dst,$src1,$src2" %} 11474 opcode(0xD8, 0x1, 0xD9); /* D8 /1 */ /* LoadF D9 /0 */ 11475 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2), 11476 set_instruction_start, 11477 OpcP, RMopc_Mem(secondary,src1), 11478 Pop_Mem_F(dst) ); 11479 ins_pipe( fpu_mem_mem_mem ); 11480 %} 11481 11482 // Spill to obtain 24-bit precision 11483 instruct mulF24_reg_imm(stackSlotF dst, regF src1, immF src2) %{ 11484 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); 11485 match(Set dst (MulF src1 src2)); 11486 11487 format %{ "FMULc $dst,$src1,$src2" %} 11488 opcode(0xD8, 0x1); /* D8 /1*/ 11489 ins_encode( Push_Reg_F(src1), 11490 Opc_MemImm_F(src2), 11491 Pop_Mem_F(dst)); 11492 ins_pipe( fpu_mem_reg_con ); 11493 %} 11494 // 11495 // This instruction does not round to 24-bits 11496 instruct mulF_reg_imm(regF dst, regF src1, immF src2) %{ 11497 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); 11498 match(Set dst (MulF src1 src2)); 11499 11500 format %{ "FMULc $dst. $src1, $src2" %} 11501 opcode(0xD8, 0x1); /* D8 /1*/ 11502 ins_encode( Push_Reg_F(src1), 11503 Opc_MemImm_F(src2), 11504 Pop_Reg_F(dst)); 11505 ins_pipe( fpu_reg_reg_con ); 11506 %} 11507 11508 11509 // 11510 // MACRO1 -- subsume unshared load into mulF 11511 // This instruction does not round to 24-bits 11512 instruct mulF_reg_load1(regF dst, regF src, memory mem1 ) %{ 11513 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); 11514 match(Set dst (MulF (LoadF mem1) src)); 11515 11516 format %{ "FLD $mem1 ===MACRO1===\n\t" 11517 "FMUL ST,$src\n\t" 11518 "FSTP $dst" %} 11519 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or D8 /1 */ /* LoadF D9 /0 */ 11520 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem1), 11521 OpcReg_F(src), 11522 Pop_Reg_F(dst) ); 11523 ins_pipe( fpu_reg_reg_mem ); 11524 %} 11525 // 11526 // MACRO2 -- addF a mulF which subsumed an unshared load 11527 // This instruction does not round to 24-bits 11528 instruct addF_mulF_reg_load1(regF dst, memory mem1, regF src1, regF src2) %{ 11529 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); 11530 match(Set dst (AddF (MulF (LoadF mem1) src1) src2)); 11531 ins_cost(95); 11532 11533 format %{ "FLD $mem1 ===MACRO2===\n\t" 11534 "FMUL ST,$src1 subsume mulF left load\n\t" 11535 "FADD ST,$src2\n\t" 11536 "FSTP $dst" %} 11537 opcode(0xD9); /* LoadF D9 /0 */ 11538 ins_encode( OpcP, RMopc_Mem(0x00,mem1), 11539 FMul_ST_reg(src1), 11540 FAdd_ST_reg(src2), 11541 Pop_Reg_F(dst) ); 11542 ins_pipe( fpu_reg_mem_reg_reg ); 11543 %} 11544 11545 // MACRO3 -- addF a mulF 11546 // This instruction does not round to 24-bits. It is a '2-address' 11547 // instruction in that the result goes back to src2. This eliminates 11548 // a move from the macro; possibly the register allocator will have 11549 // to add it back (and maybe not). 11550 instruct addF_mulF_reg(regF src2, regF src1, regF src0) %{ 11551 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); 11552 match(Set src2 (AddF (MulF src0 src1) src2)); 11553 11554 format %{ "FLD $src0 ===MACRO3===\n\t" 11555 "FMUL ST,$src1\n\t" 11556 "FADDP $src2,ST" %} 11557 opcode(0xD9); /* LoadF D9 /0 */ 11558 ins_encode( Push_Reg_F(src0), 11559 FMul_ST_reg(src1), 11560 FAddP_reg_ST(src2) ); 11561 ins_pipe( fpu_reg_reg_reg ); 11562 %} 11563 11564 // MACRO4 -- divF subF 11565 // This instruction does not round to 24-bits 11566 instruct subF_divF_reg(regF dst, regF src1, regF src2, regF src3) %{ 11567 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); 11568 match(Set dst (DivF (SubF src2 src1) src3)); 11569 11570 format %{ "FLD $src2 ===MACRO4===\n\t" 11571 "FSUB ST,$src1\n\t" 11572 "FDIV ST,$src3\n\t" 11573 "FSTP $dst" %} 11574 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/ 11575 ins_encode( Push_Reg_F(src2), 11576 subF_divF_encode(src1,src3), 11577 Pop_Reg_F(dst) ); 11578 ins_pipe( fpu_reg_reg_reg_reg ); 11579 %} 11580 11581 // Spill to obtain 24-bit precision 11582 instruct divF24_reg(stackSlotF dst, regF src1, regF src2) %{ 11583 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); 11584 match(Set dst (DivF src1 src2)); 11585 11586 format %{ "FDIV $dst,$src1,$src2" %} 11587 opcode(0xD8, 0x6); /* D8 F0+i or DE /6*/ 11588 ins_encode( Push_Reg_F(src1), 11589 OpcReg_F(src2), 11590 Pop_Mem_F(dst) ); 11591 ins_pipe( fpu_mem_reg_reg ); 11592 %} 11593 // 11594 // This instruction does not round to 24-bits 11595 instruct divF_reg(regF dst, regF src) %{ 11596 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); 11597 match(Set dst (DivF dst src)); 11598 11599 format %{ "FDIV $dst,$src" %} 11600 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/ 11601 ins_encode( Push_Reg_F(src), 11602 OpcP, RegOpc(dst) ); 11603 ins_pipe( fpu_reg_reg ); 11604 %} 11605 11606 11607 // Spill to obtain 24-bit precision 11608 instruct modF24_reg(stackSlotF dst, regF src1, regF src2, eAXRegI rax, eFlagsReg cr) %{ 11609 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr()); 11610 match(Set dst (ModF src1 src2)); 11611 effect(KILL rax, KILL cr); // emitModD() uses EAX and EFLAGS 11612 11613 format %{ "FMOD $dst,$src1,$src2" %} 11614 ins_encode( Push_Reg_Mod_D(src1, src2), 11615 emitModD(), 11616 Push_Result_Mod_D(src2), 11617 Pop_Mem_F(dst)); 11618 ins_pipe( pipe_slow ); 11619 %} 11620 // 11621 // This instruction does not round to 24-bits 11622 instruct modF_reg(regF dst, regF src, eAXRegI rax, eFlagsReg cr) %{ 11623 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr()); 11624 match(Set dst (ModF dst src)); 11625 effect(KILL rax, KILL cr); // emitModD() uses EAX and EFLAGS 11626 11627 format %{ "FMOD $dst,$src" %} 11628 ins_encode(Push_Reg_Mod_D(dst, src), 11629 emitModD(), 11630 Push_Result_Mod_D(src), 11631 Pop_Reg_F(dst)); 11632 ins_pipe( pipe_slow ); 11633 %} 11634 11635 instruct modX_reg(regX dst, regX src0, regX src1, eAXRegI rax, eFlagsReg cr) %{ 11636 predicate(UseSSE>=1); 11637 match(Set dst (ModF src0 src1)); 11638 effect(KILL rax, KILL cr); 11639 format %{ "SUB ESP,4\t # FMOD\n" 11640 "\tMOVSS [ESP+0],$src1\n" 11641 "\tFLD_S [ESP+0]\n" 11642 "\tMOVSS [ESP+0],$src0\n" 11643 "\tFLD_S [ESP+0]\n" 11644 "loop:\tFPREM\n" 11645 "\tFWAIT\n" 11646 "\tFNSTSW AX\n" 11647 "\tSAHF\n" 11648 "\tJP loop\n" 11649 "\tFSTP_S [ESP+0]\n" 11650 "\tMOVSS $dst,[ESP+0]\n" 11651 "\tADD ESP,4\n" 11652 "\tFSTP ST0\t # Restore FPU Stack" 11653 %} 11654 ins_cost(250); 11655 ins_encode( Push_ModX_encoding(src0, src1), emitModD(), Push_ResultX(dst,0x4), PopFPU); 11656 ins_pipe( pipe_slow ); 11657 %} 11658 11659 11660 //----------Arithmetic Conversion Instructions--------------------------------- 11661 // The conversions operations are all Alpha sorted. Please keep it that way! 11662 11663 instruct roundFloat_mem_reg(stackSlotF dst, regF src) %{ 11664 predicate(UseSSE==0); 11665 match(Set dst (RoundFloat src)); 11666 ins_cost(125); 11667 format %{ "FST_S $dst,$src\t# F-round" %} 11668 ins_encode( Pop_Mem_Reg_F(dst, src) ); 11669 ins_pipe( fpu_mem_reg ); 11670 %} 11671 11672 instruct roundDouble_mem_reg(stackSlotD dst, regD src) %{ 11673 predicate(UseSSE<=1); 11674 match(Set dst (RoundDouble src)); 11675 ins_cost(125); 11676 format %{ "FST_D $dst,$src\t# D-round" %} 11677 ins_encode( Pop_Mem_Reg_D(dst, src) ); 11678 ins_pipe( fpu_mem_reg ); 11679 %} 11680 11681 // Force rounding to 24-bit precision and 6-bit exponent 11682 instruct convD2F_reg(stackSlotF dst, regD src) %{ 11683 predicate(UseSSE==0); 11684 match(Set dst (ConvD2F src)); 11685 format %{ "FST_S $dst,$src\t# F-round" %} 11686 expand %{ 11687 roundFloat_mem_reg(dst,src); 11688 %} 11689 %} 11690 11691 // Force rounding to 24-bit precision and 6-bit exponent 11692 instruct convD2X_reg(regX dst, regD src, eFlagsReg cr) %{ 11693 predicate(UseSSE==1); 11694 match(Set dst (ConvD2F src)); 11695 effect( KILL cr ); 11696 format %{ "SUB ESP,4\n\t" 11697 "FST_S [ESP],$src\t# F-round\n\t" 11698 "MOVSS $dst,[ESP]\n\t" 11699 "ADD ESP,4" %} 11700 ins_encode( D2X_encoding(dst, src) ); 11701 ins_pipe( pipe_slow ); 11702 %} 11703 11704 // Force rounding double precision to single precision 11705 instruct convXD2X_reg(regX dst, regXD src) %{ 11706 predicate(UseSSE>=2); 11707 match(Set dst (ConvD2F src)); 11708 format %{ "CVTSD2SS $dst,$src\t# F-round" %} 11709 opcode(0xF2, 0x0F, 0x5A); 11710 ins_encode( OpcP, OpcS, Opcode(tertiary), RegReg(dst, src)); 11711 ins_pipe( pipe_slow ); 11712 %} 11713 11714 instruct convF2D_reg_reg(regD dst, regF src) %{ 11715 predicate(UseSSE==0); 11716 match(Set dst (ConvF2D src)); 11717 format %{ "FST_S $dst,$src\t# D-round" %} 11718 ins_encode( Pop_Reg_Reg_D(dst, src)); 11719 ins_pipe( fpu_reg_reg ); 11720 %} 11721 11722 instruct convF2D_reg(stackSlotD dst, regF src) %{ 11723 predicate(UseSSE==1); 11724 match(Set dst (ConvF2D src)); 11725 format %{ "FST_D $dst,$src\t# D-round" %} 11726 expand %{ 11727 roundDouble_mem_reg(dst,src); 11728 %} 11729 %} 11730 11731 instruct convX2D_reg(regD dst, regX src, eFlagsReg cr) %{ 11732 predicate(UseSSE==1); 11733 match(Set dst (ConvF2D src)); 11734 effect( KILL cr ); 11735 format %{ "SUB ESP,4\n\t" 11736 "MOVSS [ESP] $src\n\t" 11737 "FLD_S [ESP]\n\t" 11738 "ADD ESP,4\n\t" 11739 "FSTP $dst\t# D-round" %} 11740 ins_encode( X2D_encoding(dst, src), Pop_Reg_D(dst)); 11741 ins_pipe( pipe_slow ); 11742 %} 11743 11744 instruct convX2XD_reg(regXD dst, regX src) %{ 11745 predicate(UseSSE>=2); 11746 match(Set dst (ConvF2D src)); 11747 format %{ "CVTSS2SD $dst,$src\t# D-round" %} 11748 opcode(0xF3, 0x0F, 0x5A); 11749 ins_encode( OpcP, OpcS, Opcode(tertiary), RegReg(dst, src)); 11750 ins_pipe( pipe_slow ); 11751 %} 11752 11753 // Convert a double to an int. If the double is a NAN, stuff a zero in instead. 11754 instruct convD2I_reg_reg( eAXRegI dst, eDXRegI tmp, regD src, eFlagsReg cr ) %{ 11755 predicate(UseSSE<=1); 11756 match(Set dst (ConvD2I src)); 11757 effect( KILL tmp, KILL cr ); 11758 format %{ "FLD $src\t# Convert double to int \n\t" 11759 "FLDCW trunc mode\n\t" 11760 "SUB ESP,4\n\t" 11761 "FISTp [ESP + #0]\n\t" 11762 "FLDCW std/24-bit mode\n\t" 11763 "POP EAX\n\t" 11764 "CMP EAX,0x80000000\n\t" 11765 "JNE,s fast\n\t" 11766 "FLD_D $src\n\t" 11767 "CALL d2i_wrapper\n" 11768 "fast:" %} 11769 ins_encode( Push_Reg_D(src), D2I_encoding(src) ); 11770 ins_pipe( pipe_slow ); 11771 %} 11772 11773 // Convert a double to an int. If the double is a NAN, stuff a zero in instead. 11774 instruct convXD2I_reg_reg( eAXRegI dst, eDXRegI tmp, regXD src, eFlagsReg cr ) %{ 11775 predicate(UseSSE>=2); 11776 match(Set dst (ConvD2I src)); 11777 effect( KILL tmp, KILL cr ); 11778 format %{ "CVTTSD2SI $dst, $src\n\t" 11779 "CMP $dst,0x80000000\n\t" 11780 "JNE,s fast\n\t" 11781 "SUB ESP, 8\n\t" 11782 "MOVSD [ESP], $src\n\t" 11783 "FLD_D [ESP]\n\t" 11784 "ADD ESP, 8\n\t" 11785 "CALL d2i_wrapper\n" 11786 "fast:" %} 11787 opcode(0x1); // double-precision conversion 11788 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x2C), FX2I_encoding(src,dst)); 11789 ins_pipe( pipe_slow ); 11790 %} 11791 11792 instruct convD2L_reg_reg( eADXRegL dst, regD src, eFlagsReg cr ) %{ 11793 predicate(UseSSE<=1); 11794 match(Set dst (ConvD2L src)); 11795 effect( KILL cr ); 11796 format %{ "FLD $src\t# Convert double to long\n\t" 11797 "FLDCW trunc mode\n\t" 11798 "SUB ESP,8\n\t" 11799 "FISTp [ESP + #0]\n\t" 11800 "FLDCW std/24-bit mode\n\t" 11801 "POP EAX\n\t" 11802 "POP EDX\n\t" 11803 "CMP EDX,0x80000000\n\t" 11804 "JNE,s fast\n\t" 11805 "TEST EAX,EAX\n\t" 11806 "JNE,s fast\n\t" 11807 "FLD $src\n\t" 11808 "CALL d2l_wrapper\n" 11809 "fast:" %} 11810 ins_encode( Push_Reg_D(src), D2L_encoding(src) ); 11811 ins_pipe( pipe_slow ); 11812 %} 11813 11814 // XMM lacks a float/double->long conversion, so use the old FPU stack. 11815 instruct convXD2L_reg_reg( eADXRegL dst, regXD src, eFlagsReg cr ) %{ 11816 predicate (UseSSE>=2); 11817 match(Set dst (ConvD2L src)); 11818 effect( KILL cr ); 11819 format %{ "SUB ESP,8\t# Convert double to long\n\t" 11820 "MOVSD [ESP],$src\n\t" 11821 "FLD_D [ESP]\n\t" 11822 "FLDCW trunc mode\n\t" 11823 "FISTp [ESP + #0]\n\t" 11824 "FLDCW std/24-bit mode\n\t" 11825 "POP EAX\n\t" 11826 "POP EDX\n\t" 11827 "CMP EDX,0x80000000\n\t" 11828 "JNE,s fast\n\t" 11829 "TEST EAX,EAX\n\t" 11830 "JNE,s fast\n\t" 11831 "SUB ESP,8\n\t" 11832 "MOVSD [ESP],$src\n\t" 11833 "FLD_D [ESP]\n\t" 11834 "CALL d2l_wrapper\n" 11835 "fast:" %} 11836 ins_encode( XD2L_encoding(src) ); 11837 ins_pipe( pipe_slow ); 11838 %} 11839 11840 // Convert a double to an int. Java semantics require we do complex 11841 // manglations in the corner cases. So we set the rounding mode to 11842 // 'zero', store the darned double down as an int, and reset the 11843 // rounding mode to 'nearest'. The hardware stores a flag value down 11844 // if we would overflow or converted a NAN; we check for this and 11845 // and go the slow path if needed. 11846 instruct convF2I_reg_reg(eAXRegI dst, eDXRegI tmp, regF src, eFlagsReg cr ) %{ 11847 predicate(UseSSE==0); 11848 match(Set dst (ConvF2I src)); 11849 effect( KILL tmp, KILL cr ); 11850 format %{ "FLD $src\t# Convert float to int \n\t" 11851 "FLDCW trunc mode\n\t" 11852 "SUB ESP,4\n\t" 11853 "FISTp [ESP + #0]\n\t" 11854 "FLDCW std/24-bit mode\n\t" 11855 "POP EAX\n\t" 11856 "CMP EAX,0x80000000\n\t" 11857 "JNE,s fast\n\t" 11858 "FLD $src\n\t" 11859 "CALL d2i_wrapper\n" 11860 "fast:" %} 11861 // D2I_encoding works for F2I 11862 ins_encode( Push_Reg_F(src), D2I_encoding(src) ); 11863 ins_pipe( pipe_slow ); 11864 %} 11865 11866 // Convert a float in xmm to an int reg. 11867 instruct convX2I_reg(eAXRegI dst, eDXRegI tmp, regX src, eFlagsReg cr ) %{ 11868 predicate(UseSSE>=1); 11869 match(Set dst (ConvF2I src)); 11870 effect( KILL tmp, KILL cr ); 11871 format %{ "CVTTSS2SI $dst, $src\n\t" 11872 "CMP $dst,0x80000000\n\t" 11873 "JNE,s fast\n\t" 11874 "SUB ESP, 4\n\t" 11875 "MOVSS [ESP], $src\n\t" 11876 "FLD [ESP]\n\t" 11877 "ADD ESP, 4\n\t" 11878 "CALL d2i_wrapper\n" 11879 "fast:" %} 11880 opcode(0x0); // single-precision conversion 11881 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x2C), FX2I_encoding(src,dst)); 11882 ins_pipe( pipe_slow ); 11883 %} 11884 11885 instruct convF2L_reg_reg( eADXRegL dst, regF src, eFlagsReg cr ) %{ 11886 predicate(UseSSE==0); 11887 match(Set dst (ConvF2L src)); 11888 effect( KILL cr ); 11889 format %{ "FLD $src\t# Convert float to long\n\t" 11890 "FLDCW trunc mode\n\t" 11891 "SUB ESP,8\n\t" 11892 "FISTp [ESP + #0]\n\t" 11893 "FLDCW std/24-bit mode\n\t" 11894 "POP EAX\n\t" 11895 "POP EDX\n\t" 11896 "CMP EDX,0x80000000\n\t" 11897 "JNE,s fast\n\t" 11898 "TEST EAX,EAX\n\t" 11899 "JNE,s fast\n\t" 11900 "FLD $src\n\t" 11901 "CALL d2l_wrapper\n" 11902 "fast:" %} 11903 // D2L_encoding works for F2L 11904 ins_encode( Push_Reg_F(src), D2L_encoding(src) ); 11905 ins_pipe( pipe_slow ); 11906 %} 11907 11908 // XMM lacks a float/double->long conversion, so use the old FPU stack. 11909 instruct convX2L_reg_reg( eADXRegL dst, regX src, eFlagsReg cr ) %{ 11910 predicate (UseSSE>=1); 11911 match(Set dst (ConvF2L src)); 11912 effect( KILL cr ); 11913 format %{ "SUB ESP,8\t# Convert float to long\n\t" 11914 "MOVSS [ESP],$src\n\t" 11915 "FLD_S [ESP]\n\t" 11916 "FLDCW trunc mode\n\t" 11917 "FISTp [ESP + #0]\n\t" 11918 "FLDCW std/24-bit mode\n\t" 11919 "POP EAX\n\t" 11920 "POP EDX\n\t" 11921 "CMP EDX,0x80000000\n\t" 11922 "JNE,s fast\n\t" 11923 "TEST EAX,EAX\n\t" 11924 "JNE,s fast\n\t" 11925 "SUB ESP,4\t# Convert float to long\n\t" 11926 "MOVSS [ESP],$src\n\t" 11927 "FLD_S [ESP]\n\t" 11928 "ADD ESP,4\n\t" 11929 "CALL d2l_wrapper\n" 11930 "fast:" %} 11931 ins_encode( X2L_encoding(src) ); 11932 ins_pipe( pipe_slow ); 11933 %} 11934 11935 instruct convI2D_reg(regD dst, stackSlotI src) %{ 11936 predicate( UseSSE<=1 ); 11937 match(Set dst (ConvI2D src)); 11938 format %{ "FILD $src\n\t" 11939 "FSTP $dst" %} 11940 opcode(0xDB, 0x0); /* DB /0 */ 11941 ins_encode(Push_Mem_I(src), Pop_Reg_D(dst)); 11942 ins_pipe( fpu_reg_mem ); 11943 %} 11944 11945 instruct convI2XD_reg(regXD dst, eRegI src) %{ 11946 predicate( UseSSE>=2 && !UseXmmI2D ); 11947 match(Set dst (ConvI2D src)); 11948 format %{ "CVTSI2SD $dst,$src" %} 11949 opcode(0xF2, 0x0F, 0x2A); 11950 ins_encode( OpcP, OpcS, Opcode(tertiary), RegReg(dst, src)); 11951 ins_pipe( pipe_slow ); 11952 %} 11953 11954 instruct convI2XD_mem(regXD dst, memory mem) %{ 11955 predicate( UseSSE>=2 ); 11956 match(Set dst (ConvI2D (LoadI mem))); 11957 format %{ "CVTSI2SD $dst,$mem" %} 11958 opcode(0xF2, 0x0F, 0x2A); 11959 ins_encode( OpcP, OpcS, Opcode(tertiary), RegMem(dst, mem)); 11960 ins_pipe( pipe_slow ); 11961 %} 11962 11963 instruct convXI2XD_reg(regXD dst, eRegI src) 11964 %{ 11965 predicate( UseSSE>=2 && UseXmmI2D ); 11966 match(Set dst (ConvI2D src)); 11967 11968 format %{ "MOVD $dst,$src\n\t" 11969 "CVTDQ2PD $dst,$dst\t# i2d" %} 11970 ins_encode %{ 11971 __ movdl($dst$$XMMRegister, $src$$Register); 11972 __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister); 11973 %} 11974 ins_pipe(pipe_slow); // XXX 11975 %} 11976 11977 instruct convI2D_mem(regD dst, memory mem) %{ 11978 predicate( UseSSE<=1 && !Compile::current()->select_24_bit_instr()); 11979 match(Set dst (ConvI2D (LoadI mem))); 11980 format %{ "FILD $mem\n\t" 11981 "FSTP $dst" %} 11982 opcode(0xDB); /* DB /0 */ 11983 ins_encode( OpcP, RMopc_Mem(0x00,mem), 11984 Pop_Reg_D(dst)); 11985 ins_pipe( fpu_reg_mem ); 11986 %} 11987 11988 // Convert a byte to a float; no rounding step needed. 11989 instruct conv24I2F_reg(regF dst, stackSlotI src) %{ 11990 predicate( UseSSE==0 && n->in(1)->Opcode() == Op_AndI && n->in(1)->in(2)->is_Con() && n->in(1)->in(2)->get_int() == 255 ); 11991 match(Set dst (ConvI2F src)); 11992 format %{ "FILD $src\n\t" 11993 "FSTP $dst" %} 11994 11995 opcode(0xDB, 0x0); /* DB /0 */ 11996 ins_encode(Push_Mem_I(src), Pop_Reg_F(dst)); 11997 ins_pipe( fpu_reg_mem ); 11998 %} 11999 12000 // In 24-bit mode, force exponent rounding by storing back out 12001 instruct convI2F_SSF(stackSlotF dst, stackSlotI src) %{ 12002 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr()); 12003 match(Set dst (ConvI2F src)); 12004 ins_cost(200); 12005 format %{ "FILD $src\n\t" 12006 "FSTP_S $dst" %} 12007 opcode(0xDB, 0x0); /* DB /0 */ 12008 ins_encode( Push_Mem_I(src), 12009 Pop_Mem_F(dst)); 12010 ins_pipe( fpu_mem_mem ); 12011 %} 12012 12013 // In 24-bit mode, force exponent rounding by storing back out 12014 instruct convI2F_SSF_mem(stackSlotF dst, memory mem) %{ 12015 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr()); 12016 match(Set dst (ConvI2F (LoadI mem))); 12017 ins_cost(200); 12018 format %{ "FILD $mem\n\t" 12019 "FSTP_S $dst" %} 12020 opcode(0xDB); /* DB /0 */ 12021 ins_encode( OpcP, RMopc_Mem(0x00,mem), 12022 Pop_Mem_F(dst)); 12023 ins_pipe( fpu_mem_mem ); 12024 %} 12025 12026 // This instruction does not round to 24-bits 12027 instruct convI2F_reg(regF dst, stackSlotI src) %{ 12028 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr()); 12029 match(Set dst (ConvI2F src)); 12030 format %{ "FILD $src\n\t" 12031 "FSTP $dst" %} 12032 opcode(0xDB, 0x0); /* DB /0 */ 12033 ins_encode( Push_Mem_I(src), 12034 Pop_Reg_F(dst)); 12035 ins_pipe( fpu_reg_mem ); 12036 %} 12037 12038 // This instruction does not round to 24-bits 12039 instruct convI2F_mem(regF dst, memory mem) %{ 12040 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr()); 12041 match(Set dst (ConvI2F (LoadI mem))); 12042 format %{ "FILD $mem\n\t" 12043 "FSTP $dst" %} 12044 opcode(0xDB); /* DB /0 */ 12045 ins_encode( OpcP, RMopc_Mem(0x00,mem), 12046 Pop_Reg_F(dst)); 12047 ins_pipe( fpu_reg_mem ); 12048 %} 12049 12050 // Convert an int to a float in xmm; no rounding step needed. 12051 instruct convI2X_reg(regX dst, eRegI src) %{ 12052 predicate( UseSSE==1 || UseSSE>=2 && !UseXmmI2F ); 12053 match(Set dst (ConvI2F src)); 12054 format %{ "CVTSI2SS $dst, $src" %} 12055 12056 opcode(0xF3, 0x0F, 0x2A); /* F3 0F 2A /r */ 12057 ins_encode( OpcP, OpcS, Opcode(tertiary), RegReg(dst, src)); 12058 ins_pipe( pipe_slow ); 12059 %} 12060 12061 instruct convXI2X_reg(regX dst, eRegI src) 12062 %{ 12063 predicate( UseSSE>=2 && UseXmmI2F ); 12064 match(Set dst (ConvI2F src)); 12065 12066 format %{ "MOVD $dst,$src\n\t" 12067 "CVTDQ2PS $dst,$dst\t# i2f" %} 12068 ins_encode %{ 12069 __ movdl($dst$$XMMRegister, $src$$Register); 12070 __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister); 12071 %} 12072 ins_pipe(pipe_slow); // XXX 12073 %} 12074 12075 instruct convI2L_reg( eRegL dst, eRegI src, eFlagsReg cr) %{ 12076 match(Set dst (ConvI2L src)); 12077 effect(KILL cr); 12078 ins_cost(375); 12079 format %{ "MOV $dst.lo,$src\n\t" 12080 "MOV $dst.hi,$src\n\t" 12081 "SAR $dst.hi,31" %} 12082 ins_encode(convert_int_long(dst,src)); 12083 ins_pipe( ialu_reg_reg_long ); 12084 %} 12085 12086 // Zero-extend convert int to long 12087 instruct convI2L_reg_zex(eRegL dst, eRegI src, immL_32bits mask, eFlagsReg flags ) %{ 12088 match(Set dst (AndL (ConvI2L src) mask) ); 12089 effect( KILL flags ); 12090 ins_cost(250); 12091 format %{ "MOV $dst.lo,$src\n\t" 12092 "XOR $dst.hi,$dst.hi" %} 12093 opcode(0x33); // XOR 12094 ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) ); 12095 ins_pipe( ialu_reg_reg_long ); 12096 %} 12097 12098 // Zero-extend long 12099 instruct zerox_long(eRegL dst, eRegL src, immL_32bits mask, eFlagsReg flags ) %{ 12100 match(Set dst (AndL src mask) ); 12101 effect( KILL flags ); 12102 ins_cost(250); 12103 format %{ "MOV $dst.lo,$src.lo\n\t" 12104 "XOR $dst.hi,$dst.hi\n\t" %} 12105 opcode(0x33); // XOR 12106 ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) ); 12107 ins_pipe( ialu_reg_reg_long ); 12108 %} 12109 12110 instruct convL2D_reg( stackSlotD dst, eRegL src, eFlagsReg cr) %{ 12111 predicate (UseSSE<=1); 12112 match(Set dst (ConvL2D src)); 12113 effect( KILL cr ); 12114 format %{ "PUSH $src.hi\t# Convert long to double\n\t" 12115 "PUSH $src.lo\n\t" 12116 "FILD ST,[ESP + #0]\n\t" 12117 "ADD ESP,8\n\t" 12118 "FSTP_D $dst\t# D-round" %} 12119 opcode(0xDF, 0x5); /* DF /5 */ 12120 ins_encode(convert_long_double(src), Pop_Mem_D(dst)); 12121 ins_pipe( pipe_slow ); 12122 %} 12123 12124 instruct convL2XD_reg( regXD dst, eRegL src, eFlagsReg cr) %{ 12125 predicate (UseSSE>=2); 12126 match(Set dst (ConvL2D src)); 12127 effect( KILL cr ); 12128 format %{ "PUSH $src.hi\t# Convert long to double\n\t" 12129 "PUSH $src.lo\n\t" 12130 "FILD_D [ESP]\n\t" 12131 "FSTP_D [ESP]\n\t" 12132 "MOVSD $dst,[ESP]\n\t" 12133 "ADD ESP,8" %} 12134 opcode(0xDF, 0x5); /* DF /5 */ 12135 ins_encode(convert_long_double2(src), Push_ResultXD(dst)); 12136 ins_pipe( pipe_slow ); 12137 %} 12138 12139 instruct convL2X_reg( regX dst, eRegL src, eFlagsReg cr) %{ 12140 predicate (UseSSE>=1); 12141 match(Set dst (ConvL2F src)); 12142 effect( KILL cr ); 12143 format %{ "PUSH $src.hi\t# Convert long to single float\n\t" 12144 "PUSH $src.lo\n\t" 12145 "FILD_D [ESP]\n\t" 12146 "FSTP_S [ESP]\n\t" 12147 "MOVSS $dst,[ESP]\n\t" 12148 "ADD ESP,8" %} 12149 opcode(0xDF, 0x5); /* DF /5 */ 12150 ins_encode(convert_long_double2(src), Push_ResultX(dst,0x8)); 12151 ins_pipe( pipe_slow ); 12152 %} 12153 12154 instruct convL2F_reg( stackSlotF dst, eRegL src, eFlagsReg cr) %{ 12155 match(Set dst (ConvL2F src)); 12156 effect( KILL cr ); 12157 format %{ "PUSH $src.hi\t# Convert long to single float\n\t" 12158 "PUSH $src.lo\n\t" 12159 "FILD ST,[ESP + #0]\n\t" 12160 "ADD ESP,8\n\t" 12161 "FSTP_S $dst\t# F-round" %} 12162 opcode(0xDF, 0x5); /* DF /5 */ 12163 ins_encode(convert_long_double(src), Pop_Mem_F(dst)); 12164 ins_pipe( pipe_slow ); 12165 %} 12166 12167 instruct convL2I_reg( eRegI dst, eRegL src ) %{ 12168 match(Set dst (ConvL2I src)); 12169 effect( DEF dst, USE src ); 12170 format %{ "MOV $dst,$src.lo" %} 12171 ins_encode(enc_CopyL_Lo(dst,src)); 12172 ins_pipe( ialu_reg_reg ); 12173 %} 12174 12175 12176 instruct MoveF2I_stack_reg(eRegI dst, stackSlotF src) %{ 12177 match(Set dst (MoveF2I src)); 12178 effect( DEF dst, USE src ); 12179 ins_cost(100); 12180 format %{ "MOV $dst,$src\t# MoveF2I_stack_reg" %} 12181 opcode(0x8B); 12182 ins_encode( OpcP, RegMem(dst,src)); 12183 ins_pipe( ialu_reg_mem ); 12184 %} 12185 12186 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{ 12187 predicate(UseSSE==0); 12188 match(Set dst (MoveF2I src)); 12189 effect( DEF dst, USE src ); 12190 12191 ins_cost(125); 12192 format %{ "FST_S $dst,$src\t# MoveF2I_reg_stack" %} 12193 ins_encode( Pop_Mem_Reg_F(dst, src) ); 12194 ins_pipe( fpu_mem_reg ); 12195 %} 12196 12197 instruct MoveF2I_reg_stack_sse(stackSlotI dst, regX src) %{ 12198 predicate(UseSSE>=1); 12199 match(Set dst (MoveF2I src)); 12200 effect( DEF dst, USE src ); 12201 12202 ins_cost(95); 12203 format %{ "MOVSS $dst,$src\t# MoveF2I_reg_stack_sse" %} 12204 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x11), RegMem(src, dst)); 12205 ins_pipe( pipe_slow ); 12206 %} 12207 12208 instruct MoveF2I_reg_reg_sse(eRegI dst, regX src) %{ 12209 predicate(UseSSE>=2); 12210 match(Set dst (MoveF2I src)); 12211 effect( DEF dst, USE src ); 12212 ins_cost(85); 12213 format %{ "MOVD $dst,$src\t# MoveF2I_reg_reg_sse" %} 12214 ins_encode( MovX2I_reg(dst, src)); 12215 ins_pipe( pipe_slow ); 12216 %} 12217 12218 instruct MoveI2F_reg_stack(stackSlotF dst, eRegI src) %{ 12219 match(Set dst (MoveI2F src)); 12220 effect( DEF dst, USE src ); 12221 12222 ins_cost(100); 12223 format %{ "MOV $dst,$src\t# MoveI2F_reg_stack" %} 12224 opcode(0x89); 12225 ins_encode( OpcPRegSS( dst, src ) ); 12226 ins_pipe( ialu_mem_reg ); 12227 %} 12228 12229 12230 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{ 12231 predicate(UseSSE==0); 12232 match(Set dst (MoveI2F src)); 12233 effect(DEF dst, USE src); 12234 12235 ins_cost(125); 12236 format %{ "FLD_S $src\n\t" 12237 "FSTP $dst\t# MoveI2F_stack_reg" %} 12238 opcode(0xD9); /* D9 /0, FLD m32real */ 12239 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src), 12240 Pop_Reg_F(dst) ); 12241 ins_pipe( fpu_reg_mem ); 12242 %} 12243 12244 instruct MoveI2F_stack_reg_sse(regX dst, stackSlotI src) %{ 12245 predicate(UseSSE>=1); 12246 match(Set dst (MoveI2F src)); 12247 effect( DEF dst, USE src ); 12248 12249 ins_cost(95); 12250 format %{ "MOVSS $dst,$src\t# MoveI2F_stack_reg_sse" %} 12251 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x10), RegMem(dst,src)); 12252 ins_pipe( pipe_slow ); 12253 %} 12254 12255 instruct MoveI2F_reg_reg_sse(regX dst, eRegI src) %{ 12256 predicate(UseSSE>=2); 12257 match(Set dst (MoveI2F src)); 12258 effect( DEF dst, USE src ); 12259 12260 ins_cost(85); 12261 format %{ "MOVD $dst,$src\t# MoveI2F_reg_reg_sse" %} 12262 ins_encode( MovI2X_reg(dst, src) ); 12263 ins_pipe( pipe_slow ); 12264 %} 12265 12266 instruct MoveD2L_stack_reg(eRegL dst, stackSlotD src) %{ 12267 match(Set dst (MoveD2L src)); 12268 effect(DEF dst, USE src); 12269 12270 ins_cost(250); 12271 format %{ "MOV $dst.lo,$src\n\t" 12272 "MOV $dst.hi,$src+4\t# MoveD2L_stack_reg" %} 12273 opcode(0x8B, 0x8B); 12274 ins_encode( OpcP, RegMem(dst,src), OpcS, RegMem_Hi(dst,src)); 12275 ins_pipe( ialu_mem_long_reg ); 12276 %} 12277 12278 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{ 12279 predicate(UseSSE<=1); 12280 match(Set dst (MoveD2L src)); 12281 effect(DEF dst, USE src); 12282 12283 ins_cost(125); 12284 format %{ "FST_D $dst,$src\t# MoveD2L_reg_stack" %} 12285 ins_encode( Pop_Mem_Reg_D(dst, src) ); 12286 ins_pipe( fpu_mem_reg ); 12287 %} 12288 12289 instruct MoveD2L_reg_stack_sse(stackSlotL dst, regXD src) %{ 12290 predicate(UseSSE>=2); 12291 match(Set dst (MoveD2L src)); 12292 effect(DEF dst, USE src); 12293 ins_cost(95); 12294 12295 format %{ "MOVSD $dst,$src\t# MoveD2L_reg_stack_sse" %} 12296 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x11), RegMem(src,dst)); 12297 ins_pipe( pipe_slow ); 12298 %} 12299 12300 instruct MoveD2L_reg_reg_sse(eRegL dst, regXD src, regXD tmp) %{ 12301 predicate(UseSSE>=2); 12302 match(Set dst (MoveD2L src)); 12303 effect(DEF dst, USE src, TEMP tmp); 12304 ins_cost(85); 12305 format %{ "MOVD $dst.lo,$src\n\t" 12306 "PSHUFLW $tmp,$src,0x4E\n\t" 12307 "MOVD $dst.hi,$tmp\t# MoveD2L_reg_reg_sse" %} 12308 ins_encode( MovXD2L_reg(dst, src, tmp) ); 12309 ins_pipe( pipe_slow ); 12310 %} 12311 12312 instruct MoveL2D_reg_stack(stackSlotD dst, eRegL src) %{ 12313 match(Set dst (MoveL2D src)); 12314 effect(DEF dst, USE src); 12315 12316 ins_cost(200); 12317 format %{ "MOV $dst,$src.lo\n\t" 12318 "MOV $dst+4,$src.hi\t# MoveL2D_reg_stack" %} 12319 opcode(0x89, 0x89); 12320 ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) ); 12321 ins_pipe( ialu_mem_long_reg ); 12322 %} 12323 12324 12325 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{ 12326 predicate(UseSSE<=1); 12327 match(Set dst (MoveL2D src)); 12328 effect(DEF dst, USE src); 12329 ins_cost(125); 12330 12331 format %{ "FLD_D $src\n\t" 12332 "FSTP $dst\t# MoveL2D_stack_reg" %} 12333 opcode(0xDD); /* DD /0, FLD m64real */ 12334 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src), 12335 Pop_Reg_D(dst) ); 12336 ins_pipe( fpu_reg_mem ); 12337 %} 12338 12339 12340 instruct MoveL2D_stack_reg_sse(regXD dst, stackSlotL src) %{ 12341 predicate(UseSSE>=2 && UseXmmLoadAndClearUpper); 12342 match(Set dst (MoveL2D src)); 12343 effect(DEF dst, USE src); 12344 12345 ins_cost(95); 12346 format %{ "MOVSD $dst,$src\t# MoveL2D_stack_reg_sse" %} 12347 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x10), RegMem(dst,src)); 12348 ins_pipe( pipe_slow ); 12349 %} 12350 12351 instruct MoveL2D_stack_reg_sse_partial(regXD dst, stackSlotL src) %{ 12352 predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper); 12353 match(Set dst (MoveL2D src)); 12354 effect(DEF dst, USE src); 12355 12356 ins_cost(95); 12357 format %{ "MOVLPD $dst,$src\t# MoveL2D_stack_reg_sse" %} 12358 ins_encode( Opcode(0x66), Opcode(0x0F), Opcode(0x12), RegMem(dst,src)); 12359 ins_pipe( pipe_slow ); 12360 %} 12361 12362 instruct MoveL2D_reg_reg_sse(regXD dst, eRegL src, regXD tmp) %{ 12363 predicate(UseSSE>=2); 12364 match(Set dst (MoveL2D src)); 12365 effect(TEMP dst, USE src, TEMP tmp); 12366 ins_cost(85); 12367 format %{ "MOVD $dst,$src.lo\n\t" 12368 "MOVD $tmp,$src.hi\n\t" 12369 "PUNPCKLDQ $dst,$tmp\t# MoveL2D_reg_reg_sse" %} 12370 ins_encode( MovL2XD_reg(dst, src, tmp) ); 12371 ins_pipe( pipe_slow ); 12372 %} 12373 12374 // Replicate scalar to packed byte (1 byte) values in xmm 12375 instruct Repl8B_reg(regXD dst, regXD src) %{ 12376 predicate(UseSSE>=2); 12377 match(Set dst (Replicate8B src)); 12378 format %{ "MOVDQA $dst,$src\n\t" 12379 "PUNPCKLBW $dst,$dst\n\t" 12380 "PSHUFLW $dst,$dst,0x00\t! replicate8B" %} 12381 ins_encode( pshufd_8x8(dst, src)); 12382 ins_pipe( pipe_slow ); 12383 %} 12384 12385 // Replicate scalar to packed byte (1 byte) values in xmm 12386 instruct Repl8B_eRegI(regXD dst, eRegI src) %{ 12387 predicate(UseSSE>=2); 12388 match(Set dst (Replicate8B src)); 12389 format %{ "MOVD $dst,$src\n\t" 12390 "PUNPCKLBW $dst,$dst\n\t" 12391 "PSHUFLW $dst,$dst,0x00\t! replicate8B" %} 12392 ins_encode( mov_i2x(dst, src), pshufd_8x8(dst, dst)); 12393 ins_pipe( pipe_slow ); 12394 %} 12395 12396 // Replicate scalar zero to packed byte (1 byte) values in xmm 12397 instruct Repl8B_immI0(regXD dst, immI0 zero) %{ 12398 predicate(UseSSE>=2); 12399 match(Set dst (Replicate8B zero)); 12400 format %{ "PXOR $dst,$dst\t! replicate8B" %} 12401 ins_encode( pxor(dst, dst)); 12402 ins_pipe( fpu_reg_reg ); 12403 %} 12404 12405 // Replicate scalar to packed shore (2 byte) values in xmm 12406 instruct Repl4S_reg(regXD dst, regXD src) %{ 12407 predicate(UseSSE>=2); 12408 match(Set dst (Replicate4S src)); 12409 format %{ "PSHUFLW $dst,$src,0x00\t! replicate4S" %} 12410 ins_encode( pshufd_4x16(dst, src)); 12411 ins_pipe( fpu_reg_reg ); 12412 %} 12413 12414 // Replicate scalar to packed shore (2 byte) values in xmm 12415 instruct Repl4S_eRegI(regXD dst, eRegI src) %{ 12416 predicate(UseSSE>=2); 12417 match(Set dst (Replicate4S src)); 12418 format %{ "MOVD $dst,$src\n\t" 12419 "PSHUFLW $dst,$dst,0x00\t! replicate4S" %} 12420 ins_encode( mov_i2x(dst, src), pshufd_4x16(dst, dst)); 12421 ins_pipe( fpu_reg_reg ); 12422 %} 12423 12424 // Replicate scalar zero to packed short (2 byte) values in xmm 12425 instruct Repl4S_immI0(regXD dst, immI0 zero) %{ 12426 predicate(UseSSE>=2); 12427 match(Set dst (Replicate4S zero)); 12428 format %{ "PXOR $dst,$dst\t! replicate4S" %} 12429 ins_encode( pxor(dst, dst)); 12430 ins_pipe( fpu_reg_reg ); 12431 %} 12432 12433 // Replicate scalar to packed char (2 byte) values in xmm 12434 instruct Repl4C_reg(regXD dst, regXD src) %{ 12435 predicate(UseSSE>=2); 12436 match(Set dst (Replicate4C src)); 12437 format %{ "PSHUFLW $dst,$src,0x00\t! replicate4C" %} 12438 ins_encode( pshufd_4x16(dst, src)); 12439 ins_pipe( fpu_reg_reg ); 12440 %} 12441 12442 // Replicate scalar to packed char (2 byte) values in xmm 12443 instruct Repl4C_eRegI(regXD dst, eRegI src) %{ 12444 predicate(UseSSE>=2); 12445 match(Set dst (Replicate4C src)); 12446 format %{ "MOVD $dst,$src\n\t" 12447 "PSHUFLW $dst,$dst,0x00\t! replicate4C" %} 12448 ins_encode( mov_i2x(dst, src), pshufd_4x16(dst, dst)); 12449 ins_pipe( fpu_reg_reg ); 12450 %} 12451 12452 // Replicate scalar zero to packed char (2 byte) values in xmm 12453 instruct Repl4C_immI0(regXD dst, immI0 zero) %{ 12454 predicate(UseSSE>=2); 12455 match(Set dst (Replicate4C zero)); 12456 format %{ "PXOR $dst,$dst\t! replicate4C" %} 12457 ins_encode( pxor(dst, dst)); 12458 ins_pipe( fpu_reg_reg ); 12459 %} 12460 12461 // Replicate scalar to packed integer (4 byte) values in xmm 12462 instruct Repl2I_reg(regXD dst, regXD src) %{ 12463 predicate(UseSSE>=2); 12464 match(Set dst (Replicate2I src)); 12465 format %{ "PSHUFD $dst,$src,0x00\t! replicate2I" %} 12466 ins_encode( pshufd(dst, src, 0x00)); 12467 ins_pipe( fpu_reg_reg ); 12468 %} 12469 12470 // Replicate scalar to packed integer (4 byte) values in xmm 12471 instruct Repl2I_eRegI(regXD dst, eRegI src) %{ 12472 predicate(UseSSE>=2); 12473 match(Set dst (Replicate2I src)); 12474 format %{ "MOVD $dst,$src\n\t" 12475 "PSHUFD $dst,$dst,0x00\t! replicate2I" %} 12476 ins_encode( mov_i2x(dst, src), pshufd(dst, dst, 0x00)); 12477 ins_pipe( fpu_reg_reg ); 12478 %} 12479 12480 // Replicate scalar zero to packed integer (2 byte) values in xmm 12481 instruct Repl2I_immI0(regXD dst, immI0 zero) %{ 12482 predicate(UseSSE>=2); 12483 match(Set dst (Replicate2I zero)); 12484 format %{ "PXOR $dst,$dst\t! replicate2I" %} 12485 ins_encode( pxor(dst, dst)); 12486 ins_pipe( fpu_reg_reg ); 12487 %} 12488 12489 // Replicate scalar to packed single precision floating point values in xmm 12490 instruct Repl2F_reg(regXD dst, regXD src) %{ 12491 predicate(UseSSE>=2); 12492 match(Set dst (Replicate2F src)); 12493 format %{ "PSHUFD $dst,$src,0xe0\t! replicate2F" %} 12494 ins_encode( pshufd(dst, src, 0xe0)); 12495 ins_pipe( fpu_reg_reg ); 12496 %} 12497 12498 // Replicate scalar to packed single precision floating point values in xmm 12499 instruct Repl2F_regX(regXD dst, regX src) %{ 12500 predicate(UseSSE>=2); 12501 match(Set dst (Replicate2F src)); 12502 format %{ "PSHUFD $dst,$src,0xe0\t! replicate2F" %} 12503 ins_encode( pshufd(dst, src, 0xe0)); 12504 ins_pipe( fpu_reg_reg ); 12505 %} 12506 12507 // Replicate scalar to packed single precision floating point values in xmm 12508 instruct Repl2F_immXF0(regXD dst, immXF0 zero) %{ 12509 predicate(UseSSE>=2); 12510 match(Set dst (Replicate2F zero)); 12511 format %{ "PXOR $dst,$dst\t! replicate2F" %} 12512 ins_encode( pxor(dst, dst)); 12513 ins_pipe( fpu_reg_reg ); 12514 %} 12515 12516 // ======================================================================= 12517 // fast clearing of an array 12518 instruct rep_stos(eCXRegI cnt, eDIRegP base, eAXRegI zero, Universe dummy, eFlagsReg cr) %{ 12519 match(Set dummy (ClearArray cnt base)); 12520 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr); 12521 format %{ "SHL ECX,1\t# Convert doublewords to words\n\t" 12522 "XOR EAX,EAX\n\t" 12523 "REP STOS\t# store EAX into [EDI++] while ECX--" %} 12524 opcode(0,0x4); 12525 ins_encode( Opcode(0xD1), RegOpc(ECX), 12526 OpcRegReg(0x33,EAX,EAX), 12527 Opcode(0xF3), Opcode(0xAB) ); 12528 ins_pipe( pipe_slow ); 12529 %} 12530 12531 instruct string_compare(eDIRegP str1, eSIRegP str2, regXD tmp1, regXD tmp2, 12532 eAXRegI tmp3, eBXRegI tmp4, eCXRegI result, eFlagsReg cr) %{ 12533 match(Set result (StrComp str1 str2)); 12534 effect(TEMP tmp1, TEMP tmp2, USE_KILL str1, USE_KILL str2, KILL tmp3, KILL tmp4, KILL cr); 12535 //ins_cost(300); 12536 12537 format %{ "String Compare $str1,$str2 -> $result // KILL EAX, EBX" %} 12538 ins_encode( enc_String_Compare(str1, str2, tmp1, tmp2, tmp3, tmp4, result) ); 12539 ins_pipe( pipe_slow ); 12540 %} 12541 12542 // fast string equals 12543 instruct string_equals(eDIRegP str1, eSIRegP str2, regXD tmp1, regXD tmp2, 12544 eBXRegI tmp3, eCXRegI tmp4, eAXRegI result, eFlagsReg cr) %{ 12545 match(Set result (StrEquals str1 str2)); 12546 effect(TEMP tmp1, TEMP tmp2, USE_KILL str1, USE_KILL str2, KILL tmp3, KILL tmp4, KILL cr); 12547 12548 format %{ "String Equals $str1,$str2 -> $result // KILL EBX, ECX" %} 12549 ins_encode( enc_String_Equals(tmp1, tmp2, str1, str2, tmp3, tmp4, result) ); 12550 ins_pipe( pipe_slow ); 12551 %} 12552 12553 instruct string_indexof(eSIRegP str1, eDIRegP str2, regXD tmp1, eAXRegI tmp2, 12554 eCXRegI tmp3, eDXRegI tmp4, eBXRegI result, eFlagsReg cr) %{ 12555 predicate(UseSSE42Intrinsics); 12556 match(Set result (StrIndexOf str1 str2)); 12557 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, KILL tmp2, KILL tmp3, KILL tmp4, KILL cr); 12558 12559 format %{ "String IndexOf $str1,$str2 -> $result // KILL EAX, ECX, EDX" %} 12560 ins_encode( enc_String_IndexOf(str1, str2, tmp1, tmp2, tmp3, tmp4, result) ); 12561 ins_pipe( pipe_slow ); 12562 %} 12563 12564 // fast array equals 12565 instruct array_equals(eDIRegP ary1, eSIRegP ary2, regXD tmp1, regXD tmp2, eBXRegI tmp3, 12566 eDXRegI tmp4, eAXRegI result, eFlagsReg cr) %{ 12567 match(Set result (AryEq ary1 ary2)); 12568 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr); 12569 //ins_cost(300); 12570 12571 format %{ "Array Equals $ary1,$ary2 -> $result // KILL EBX, EDX" %} 12572 ins_encode( enc_Array_Equals(ary1, ary2, tmp1, tmp2, tmp3, tmp4, result) ); 12573 ins_pipe( pipe_slow ); 12574 %} 12575 12576 //----------Control Flow Instructions------------------------------------------ 12577 // Signed compare Instructions 12578 instruct compI_eReg(eFlagsReg cr, eRegI op1, eRegI op2) %{ 12579 match(Set cr (CmpI op1 op2)); 12580 effect( DEF cr, USE op1, USE op2 ); 12581 format %{ "CMP $op1,$op2" %} 12582 opcode(0x3B); /* Opcode 3B /r */ 12583 ins_encode( OpcP, RegReg( op1, op2) ); 12584 ins_pipe( ialu_cr_reg_reg ); 12585 %} 12586 12587 instruct compI_eReg_imm(eFlagsReg cr, eRegI op1, immI op2) %{ 12588 match(Set cr (CmpI op1 op2)); 12589 effect( DEF cr, USE op1 ); 12590 format %{ "CMP $op1,$op2" %} 12591 opcode(0x81,0x07); /* Opcode 81 /7 */ 12592 // ins_encode( RegImm( op1, op2) ); /* Was CmpImm */ 12593 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) ); 12594 ins_pipe( ialu_cr_reg_imm ); 12595 %} 12596 12597 // Cisc-spilled version of cmpI_eReg 12598 instruct compI_eReg_mem(eFlagsReg cr, eRegI op1, memory op2) %{ 12599 match(Set cr (CmpI op1 (LoadI op2))); 12600 12601 format %{ "CMP $op1,$op2" %} 12602 ins_cost(500); 12603 opcode(0x3B); /* Opcode 3B /r */ 12604 ins_encode( OpcP, RegMem( op1, op2) ); 12605 ins_pipe( ialu_cr_reg_mem ); 12606 %} 12607 12608 instruct testI_reg( eFlagsReg cr, eRegI src, immI0 zero ) %{ 12609 match(Set cr (CmpI src zero)); 12610 effect( DEF cr, USE src ); 12611 12612 format %{ "TEST $src,$src" %} 12613 opcode(0x85); 12614 ins_encode( OpcP, RegReg( src, src ) ); 12615 ins_pipe( ialu_cr_reg_imm ); 12616 %} 12617 12618 instruct testI_reg_imm( eFlagsReg cr, eRegI src, immI con, immI0 zero ) %{ 12619 match(Set cr (CmpI (AndI src con) zero)); 12620 12621 format %{ "TEST $src,$con" %} 12622 opcode(0xF7,0x00); 12623 ins_encode( OpcP, RegOpc(src), Con32(con) ); 12624 ins_pipe( ialu_cr_reg_imm ); 12625 %} 12626 12627 instruct testI_reg_mem( eFlagsReg cr, eRegI src, memory mem, immI0 zero ) %{ 12628 match(Set cr (CmpI (AndI src mem) zero)); 12629 12630 format %{ "TEST $src,$mem" %} 12631 opcode(0x85); 12632 ins_encode( OpcP, RegMem( src, mem ) ); 12633 ins_pipe( ialu_cr_reg_mem ); 12634 %} 12635 12636 // Unsigned compare Instructions; really, same as signed except they 12637 // produce an eFlagsRegU instead of eFlagsReg. 12638 instruct compU_eReg(eFlagsRegU cr, eRegI op1, eRegI op2) %{ 12639 match(Set cr (CmpU op1 op2)); 12640 12641 format %{ "CMPu $op1,$op2" %} 12642 opcode(0x3B); /* Opcode 3B /r */ 12643 ins_encode( OpcP, RegReg( op1, op2) ); 12644 ins_pipe( ialu_cr_reg_reg ); 12645 %} 12646 12647 instruct compU_eReg_imm(eFlagsRegU cr, eRegI op1, immI op2) %{ 12648 match(Set cr (CmpU op1 op2)); 12649 12650 format %{ "CMPu $op1,$op2" %} 12651 opcode(0x81,0x07); /* Opcode 81 /7 */ 12652 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) ); 12653 ins_pipe( ialu_cr_reg_imm ); 12654 %} 12655 12656 // // Cisc-spilled version of cmpU_eReg 12657 instruct compU_eReg_mem(eFlagsRegU cr, eRegI op1, memory op2) %{ 12658 match(Set cr (CmpU op1 (LoadI op2))); 12659 12660 format %{ "CMPu $op1,$op2" %} 12661 ins_cost(500); 12662 opcode(0x3B); /* Opcode 3B /r */ 12663 ins_encode( OpcP, RegMem( op1, op2) ); 12664 ins_pipe( ialu_cr_reg_mem ); 12665 %} 12666 12667 // // Cisc-spilled version of cmpU_eReg 12668 //instruct compU_mem_eReg(eFlagsRegU cr, memory op1, eRegI op2) %{ 12669 // match(Set cr (CmpU (LoadI op1) op2)); 12670 // 12671 // format %{ "CMPu $op1,$op2" %} 12672 // ins_cost(500); 12673 // opcode(0x39); /* Opcode 39 /r */ 12674 // ins_encode( OpcP, RegMem( op1, op2) ); 12675 //%} 12676 12677 instruct testU_reg( eFlagsRegU cr, eRegI src, immI0 zero ) %{ 12678 match(Set cr (CmpU src zero)); 12679 12680 format %{ "TESTu $src,$src" %} 12681 opcode(0x85); 12682 ins_encode( OpcP, RegReg( src, src ) ); 12683 ins_pipe( ialu_cr_reg_imm ); 12684 %} 12685 12686 // Unsigned pointer compare Instructions 12687 instruct compP_eReg(eFlagsRegU cr, eRegP op1, eRegP op2) %{ 12688 match(Set cr (CmpP op1 op2)); 12689 12690 format %{ "CMPu $op1,$op2" %} 12691 opcode(0x3B); /* Opcode 3B /r */ 12692 ins_encode( OpcP, RegReg( op1, op2) ); 12693 ins_pipe( ialu_cr_reg_reg ); 12694 %} 12695 12696 instruct compP_eReg_imm(eFlagsRegU cr, eRegP op1, immP op2) %{ 12697 match(Set cr (CmpP op1 op2)); 12698 12699 format %{ "CMPu $op1,$op2" %} 12700 opcode(0x81,0x07); /* Opcode 81 /7 */ 12701 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) ); 12702 ins_pipe( ialu_cr_reg_imm ); 12703 %} 12704 12705 // // Cisc-spilled version of cmpP_eReg 12706 instruct compP_eReg_mem(eFlagsRegU cr, eRegP op1, memory op2) %{ 12707 match(Set cr (CmpP op1 (LoadP op2))); 12708 12709 format %{ "CMPu $op1,$op2" %} 12710 ins_cost(500); 12711 opcode(0x3B); /* Opcode 3B /r */ 12712 ins_encode( OpcP, RegMem( op1, op2) ); 12713 ins_pipe( ialu_cr_reg_mem ); 12714 %} 12715 12716 // // Cisc-spilled version of cmpP_eReg 12717 //instruct compP_mem_eReg(eFlagsRegU cr, memory op1, eRegP op2) %{ 12718 // match(Set cr (CmpP (LoadP op1) op2)); 12719 // 12720 // format %{ "CMPu $op1,$op2" %} 12721 // ins_cost(500); 12722 // opcode(0x39); /* Opcode 39 /r */ 12723 // ins_encode( OpcP, RegMem( op1, op2) ); 12724 //%} 12725 12726 // Compare raw pointer (used in out-of-heap check). 12727 // Only works because non-oop pointers must be raw pointers 12728 // and raw pointers have no anti-dependencies. 12729 instruct compP_mem_eReg( eFlagsRegU cr, eRegP op1, memory op2 ) %{ 12730 predicate( !n->in(2)->in(2)->bottom_type()->isa_oop_ptr() ); 12731 match(Set cr (CmpP op1 (LoadP op2))); 12732 12733 format %{ "CMPu $op1,$op2" %} 12734 opcode(0x3B); /* Opcode 3B /r */ 12735 ins_encode( OpcP, RegMem( op1, op2) ); 12736 ins_pipe( ialu_cr_reg_mem ); 12737 %} 12738 12739 // 12740 // This will generate a signed flags result. This should be ok 12741 // since any compare to a zero should be eq/neq. 12742 instruct testP_reg( eFlagsReg cr, eRegP src, immP0 zero ) %{ 12743 match(Set cr (CmpP src zero)); 12744 12745 format %{ "TEST $src,$src" %} 12746 opcode(0x85); 12747 ins_encode( OpcP, RegReg( src, src ) ); 12748 ins_pipe( ialu_cr_reg_imm ); 12749 %} 12750 12751 // Cisc-spilled version of testP_reg 12752 // This will generate a signed flags result. This should be ok 12753 // since any compare to a zero should be eq/neq. 12754 instruct testP_Reg_mem( eFlagsReg cr, memory op, immI0 zero ) %{ 12755 match(Set cr (CmpP (LoadP op) zero)); 12756 12757 format %{ "TEST $op,0xFFFFFFFF" %} 12758 ins_cost(500); 12759 opcode(0xF7); /* Opcode F7 /0 */ 12760 ins_encode( OpcP, RMopc_Mem(0x00,op), Con_d32(0xFFFFFFFF) ); 12761 ins_pipe( ialu_cr_reg_imm ); 12762 %} 12763 12764 // Yanked all unsigned pointer compare operations. 12765 // Pointer compares are done with CmpP which is already unsigned. 12766 12767 //----------Max and Min-------------------------------------------------------- 12768 // Min Instructions 12769 //// 12770 // *** Min and Max using the conditional move are slower than the 12771 // *** branch version on a Pentium III. 12772 // // Conditional move for min 12773 //instruct cmovI_reg_lt( eRegI op2, eRegI op1, eFlagsReg cr ) %{ 12774 // effect( USE_DEF op2, USE op1, USE cr ); 12775 // format %{ "CMOVlt $op2,$op1\t! min" %} 12776 // opcode(0x4C,0x0F); 12777 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) ); 12778 // ins_pipe( pipe_cmov_reg ); 12779 //%} 12780 // 12781 //// Min Register with Register (P6 version) 12782 //instruct minI_eReg_p6( eRegI op1, eRegI op2 ) %{ 12783 // predicate(VM_Version::supports_cmov() ); 12784 // match(Set op2 (MinI op1 op2)); 12785 // ins_cost(200); 12786 // expand %{ 12787 // eFlagsReg cr; 12788 // compI_eReg(cr,op1,op2); 12789 // cmovI_reg_lt(op2,op1,cr); 12790 // %} 12791 //%} 12792 12793 // Min Register with Register (generic version) 12794 instruct minI_eReg(eRegI dst, eRegI src, eFlagsReg flags) %{ 12795 match(Set dst (MinI dst src)); 12796 effect(KILL flags); 12797 ins_cost(300); 12798 12799 format %{ "MIN $dst,$src" %} 12800 opcode(0xCC); 12801 ins_encode( min_enc(dst,src) ); 12802 ins_pipe( pipe_slow ); 12803 %} 12804 12805 // Max Register with Register 12806 // *** Min and Max using the conditional move are slower than the 12807 // *** branch version on a Pentium III. 12808 // // Conditional move for max 12809 //instruct cmovI_reg_gt( eRegI op2, eRegI op1, eFlagsReg cr ) %{ 12810 // effect( USE_DEF op2, USE op1, USE cr ); 12811 // format %{ "CMOVgt $op2,$op1\t! max" %} 12812 // opcode(0x4F,0x0F); 12813 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) ); 12814 // ins_pipe( pipe_cmov_reg ); 12815 //%} 12816 // 12817 // // Max Register with Register (P6 version) 12818 //instruct maxI_eReg_p6( eRegI op1, eRegI op2 ) %{ 12819 // predicate(VM_Version::supports_cmov() ); 12820 // match(Set op2 (MaxI op1 op2)); 12821 // ins_cost(200); 12822 // expand %{ 12823 // eFlagsReg cr; 12824 // compI_eReg(cr,op1,op2); 12825 // cmovI_reg_gt(op2,op1,cr); 12826 // %} 12827 //%} 12828 12829 // Max Register with Register (generic version) 12830 instruct maxI_eReg(eRegI dst, eRegI src, eFlagsReg flags) %{ 12831 match(Set dst (MaxI dst src)); 12832 effect(KILL flags); 12833 ins_cost(300); 12834 12835 format %{ "MAX $dst,$src" %} 12836 opcode(0xCC); 12837 ins_encode( max_enc(dst,src) ); 12838 ins_pipe( pipe_slow ); 12839 %} 12840 12841 // ============================================================================ 12842 // Branch Instructions 12843 // Jump Table 12844 instruct jumpXtnd(eRegI switch_val) %{ 12845 match(Jump switch_val); 12846 ins_cost(350); 12847 12848 format %{ "JMP [table_base](,$switch_val,1)\n\t" %} 12849 12850 ins_encode %{ 12851 address table_base = __ address_table_constant(_index2label); 12852 12853 // Jump to Address(table_base + switch_reg) 12854 InternalAddress table(table_base); 12855 Address index(noreg, $switch_val$$Register, Address::times_1); 12856 __ jump(ArrayAddress(table, index)); 12857 %} 12858 ins_pc_relative(1); 12859 ins_pipe(pipe_jmp); 12860 %} 12861 12862 // Jump Direct - Label defines a relative address from JMP+1 12863 instruct jmpDir(label labl) %{ 12864 match(Goto); 12865 effect(USE labl); 12866 12867 ins_cost(300); 12868 format %{ "JMP $labl" %} 12869 size(5); 12870 opcode(0xE9); 12871 ins_encode( OpcP, Lbl( labl ) ); 12872 ins_pipe( pipe_jmp ); 12873 ins_pc_relative(1); 12874 %} 12875 12876 // Jump Direct Conditional - Label defines a relative address from Jcc+1 12877 instruct jmpCon(cmpOp cop, eFlagsReg cr, label labl) %{ 12878 match(If cop cr); 12879 effect(USE labl); 12880 12881 ins_cost(300); 12882 format %{ "J$cop $labl" %} 12883 size(6); 12884 opcode(0x0F, 0x80); 12885 ins_encode( Jcc( cop, labl) ); 12886 ins_pipe( pipe_jcc ); 12887 ins_pc_relative(1); 12888 %} 12889 12890 // Jump Direct Conditional - Label defines a relative address from Jcc+1 12891 instruct jmpLoopEnd(cmpOp cop, eFlagsReg cr, label labl) %{ 12892 match(CountedLoopEnd cop cr); 12893 effect(USE labl); 12894 12895 ins_cost(300); 12896 format %{ "J$cop $labl\t# Loop end" %} 12897 size(6); 12898 opcode(0x0F, 0x80); 12899 ins_encode( Jcc( cop, labl) ); 12900 ins_pipe( pipe_jcc ); 12901 ins_pc_relative(1); 12902 %} 12903 12904 // Jump Direct Conditional - Label defines a relative address from Jcc+1 12905 instruct jmpLoopEndU(cmpOpU cop, eFlagsRegU cmp, label labl) %{ 12906 match(CountedLoopEnd cop cmp); 12907 effect(USE labl); 12908 12909 ins_cost(300); 12910 format %{ "J$cop,u $labl\t# Loop end" %} 12911 size(6); 12912 opcode(0x0F, 0x80); 12913 ins_encode( Jcc( cop, labl) ); 12914 ins_pipe( pipe_jcc ); 12915 ins_pc_relative(1); 12916 %} 12917 12918 instruct jmpLoopEndUCF(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{ 12919 match(CountedLoopEnd cop cmp); 12920 effect(USE labl); 12921 12922 ins_cost(200); 12923 format %{ "J$cop,u $labl\t# Loop end" %} 12924 size(6); 12925 opcode(0x0F, 0x80); 12926 ins_encode( Jcc( cop, labl) ); 12927 ins_pipe( pipe_jcc ); 12928 ins_pc_relative(1); 12929 %} 12930 12931 // Jump Direct Conditional - using unsigned comparison 12932 instruct jmpConU(cmpOpU cop, eFlagsRegU cmp, label labl) %{ 12933 match(If cop cmp); 12934 effect(USE labl); 12935 12936 ins_cost(300); 12937 format %{ "J$cop,u $labl" %} 12938 size(6); 12939 opcode(0x0F, 0x80); 12940 ins_encode(Jcc(cop, labl)); 12941 ins_pipe(pipe_jcc); 12942 ins_pc_relative(1); 12943 %} 12944 12945 instruct jmpConUCF(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{ 12946 match(If cop cmp); 12947 effect(USE labl); 12948 12949 ins_cost(200); 12950 format %{ "J$cop,u $labl" %} 12951 size(6); 12952 opcode(0x0F, 0x80); 12953 ins_encode(Jcc(cop, labl)); 12954 ins_pipe(pipe_jcc); 12955 ins_pc_relative(1); 12956 %} 12957 12958 instruct jmpConUCF2(cmpOpUCF2 cop, eFlagsRegUCF cmp, label labl) %{ 12959 match(If cop cmp); 12960 effect(USE labl); 12961 12962 ins_cost(200); 12963 format %{ $$template 12964 if ($cop$$cmpcode == Assembler::notEqual) { 12965 $$emit$$"JP,u $labl\n\t" 12966 $$emit$$"J$cop,u $labl" 12967 } else { 12968 $$emit$$"JP,u done\n\t" 12969 $$emit$$"J$cop,u $labl\n\t" 12970 $$emit$$"done:" 12971 } 12972 %} 12973 size(12); 12974 opcode(0x0F, 0x80); 12975 ins_encode %{ 12976 Label* l = $labl$$label; 12977 $$$emit8$primary; 12978 emit_cc(cbuf, $secondary, Assembler::parity); 12979 int parity_disp = -1; 12980 bool ok = false; 12981 if ($cop$$cmpcode == Assembler::notEqual) { 12982 // the two jumps 6 bytes apart so the jump distances are too 12983 parity_disp = l ? (l->loc_pos() - (cbuf.code_size() + 4)) : 0; 12984 } else if ($cop$$cmpcode == Assembler::equal) { 12985 parity_disp = 6; 12986 ok = true; 12987 } else { 12988 ShouldNotReachHere(); 12989 } 12990 emit_d32(cbuf, parity_disp); 12991 $$$emit8$primary; 12992 emit_cc(cbuf, $secondary, $cop$$cmpcode); 12993 int disp = l ? (l->loc_pos() - (cbuf.code_size() + 4)) : 0; 12994 emit_d32(cbuf, disp); 12995 %} 12996 ins_pipe(pipe_jcc); 12997 ins_pc_relative(1); 12998 %} 12999 13000 // ============================================================================ 13001 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass 13002 // array for an instance of the superklass. Set a hidden internal cache on a 13003 // hit (cache is checked with exposed code in gen_subtype_check()). Return 13004 // NZ for a miss or zero for a hit. The encoding ALSO sets flags. 13005 instruct partialSubtypeCheck( eDIRegP result, eSIRegP sub, eAXRegP super, eCXRegI rcx, eFlagsReg cr ) %{ 13006 match(Set result (PartialSubtypeCheck sub super)); 13007 effect( KILL rcx, KILL cr ); 13008 13009 ins_cost(1100); // slightly larger than the next version 13010 format %{ "MOV EDI,[$sub+Klass::secondary_supers]\n\t" 13011 "MOV ECX,[EDI+arrayKlass::length]\t# length to scan\n\t" 13012 "ADD EDI,arrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t" 13013 "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t" 13014 "JNE,s miss\t\t# Missed: EDI not-zero\n\t" 13015 "MOV [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache\n\t" 13016 "XOR $result,$result\t\t Hit: EDI zero\n\t" 13017 "miss:\t" %} 13018 13019 opcode(0x1); // Force a XOR of EDI 13020 ins_encode( enc_PartialSubtypeCheck() ); 13021 ins_pipe( pipe_slow ); 13022 %} 13023 13024 instruct partialSubtypeCheck_vs_Zero( eFlagsReg cr, eSIRegP sub, eAXRegP super, eCXRegI rcx, eDIRegP result, immP0 zero ) %{ 13025 match(Set cr (CmpP (PartialSubtypeCheck sub super) zero)); 13026 effect( KILL rcx, KILL result ); 13027 13028 ins_cost(1000); 13029 format %{ "MOV EDI,[$sub+Klass::secondary_supers]\n\t" 13030 "MOV ECX,[EDI+arrayKlass::length]\t# length to scan\n\t" 13031 "ADD EDI,arrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t" 13032 "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t" 13033 "JNE,s miss\t\t# Missed: flags NZ\n\t" 13034 "MOV [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache, flags Z\n\t" 13035 "miss:\t" %} 13036 13037 opcode(0x0); // No need to XOR EDI 13038 ins_encode( enc_PartialSubtypeCheck() ); 13039 ins_pipe( pipe_slow ); 13040 %} 13041 13042 // ============================================================================ 13043 // Branch Instructions -- short offset versions 13044 // 13045 // These instructions are used to replace jumps of a long offset (the default 13046 // match) with jumps of a shorter offset. These instructions are all tagged 13047 // with the ins_short_branch attribute, which causes the ADLC to suppress the 13048 // match rules in general matching. Instead, the ADLC generates a conversion 13049 // method in the MachNode which can be used to do in-place replacement of the 13050 // long variant with the shorter variant. The compiler will determine if a 13051 // branch can be taken by the is_short_branch_offset() predicate in the machine 13052 // specific code section of the file. 13053 13054 // Jump Direct - Label defines a relative address from JMP+1 13055 instruct jmpDir_short(label labl) %{ 13056 match(Goto); 13057 effect(USE labl); 13058 13059 ins_cost(300); 13060 format %{ "JMP,s $labl" %} 13061 size(2); 13062 opcode(0xEB); 13063 ins_encode( OpcP, LblShort( labl ) ); 13064 ins_pipe( pipe_jmp ); 13065 ins_pc_relative(1); 13066 ins_short_branch(1); 13067 %} 13068 13069 // Jump Direct Conditional - Label defines a relative address from Jcc+1 13070 instruct jmpCon_short(cmpOp cop, eFlagsReg cr, label labl) %{ 13071 match(If cop cr); 13072 effect(USE labl); 13073 13074 ins_cost(300); 13075 format %{ "J$cop,s $labl" %} 13076 size(2); 13077 opcode(0x70); 13078 ins_encode( JccShort( cop, labl) ); 13079 ins_pipe( pipe_jcc ); 13080 ins_pc_relative(1); 13081 ins_short_branch(1); 13082 %} 13083 13084 // Jump Direct Conditional - Label defines a relative address from Jcc+1 13085 instruct jmpLoopEnd_short(cmpOp cop, eFlagsReg cr, label labl) %{ 13086 match(CountedLoopEnd cop cr); 13087 effect(USE labl); 13088 13089 ins_cost(300); 13090 format %{ "J$cop,s $labl\t# Loop end" %} 13091 size(2); 13092 opcode(0x70); 13093 ins_encode( JccShort( cop, labl) ); 13094 ins_pipe( pipe_jcc ); 13095 ins_pc_relative(1); 13096 ins_short_branch(1); 13097 %} 13098 13099 // Jump Direct Conditional - Label defines a relative address from Jcc+1 13100 instruct jmpLoopEndU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{ 13101 match(CountedLoopEnd cop cmp); 13102 effect(USE labl); 13103 13104 ins_cost(300); 13105 format %{ "J$cop,us $labl\t# Loop end" %} 13106 size(2); 13107 opcode(0x70); 13108 ins_encode( JccShort( cop, labl) ); 13109 ins_pipe( pipe_jcc ); 13110 ins_pc_relative(1); 13111 ins_short_branch(1); 13112 %} 13113 13114 instruct jmpLoopEndUCF_short(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{ 13115 match(CountedLoopEnd cop cmp); 13116 effect(USE labl); 13117 13118 ins_cost(300); 13119 format %{ "J$cop,us $labl\t# Loop end" %} 13120 size(2); 13121 opcode(0x70); 13122 ins_encode( JccShort( cop, labl) ); 13123 ins_pipe( pipe_jcc ); 13124 ins_pc_relative(1); 13125 ins_short_branch(1); 13126 %} 13127 13128 // Jump Direct Conditional - using unsigned comparison 13129 instruct jmpConU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{ 13130 match(If cop cmp); 13131 effect(USE labl); 13132 13133 ins_cost(300); 13134 format %{ "J$cop,us $labl" %} 13135 size(2); 13136 opcode(0x70); 13137 ins_encode( JccShort( cop, labl) ); 13138 ins_pipe( pipe_jcc ); 13139 ins_pc_relative(1); 13140 ins_short_branch(1); 13141 %} 13142 13143 instruct jmpConUCF_short(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{ 13144 match(If cop cmp); 13145 effect(USE labl); 13146 13147 ins_cost(300); 13148 format %{ "J$cop,us $labl" %} 13149 size(2); 13150 opcode(0x70); 13151 ins_encode( JccShort( cop, labl) ); 13152 ins_pipe( pipe_jcc ); 13153 ins_pc_relative(1); 13154 ins_short_branch(1); 13155 %} 13156 13157 instruct jmpConUCF2_short(cmpOpUCF2 cop, eFlagsRegUCF cmp, label labl) %{ 13158 match(If cop cmp); 13159 effect(USE labl); 13160 13161 ins_cost(300); 13162 format %{ $$template 13163 if ($cop$$cmpcode == Assembler::notEqual) { 13164 $$emit$$"JP,u,s $labl\n\t" 13165 $$emit$$"J$cop,u,s $labl" 13166 } else { 13167 $$emit$$"JP,u,s done\n\t" 13168 $$emit$$"J$cop,u,s $labl\n\t" 13169 $$emit$$"done:" 13170 } 13171 %} 13172 size(4); 13173 opcode(0x70); 13174 ins_encode %{ 13175 Label* l = $labl$$label; 13176 emit_cc(cbuf, $primary, Assembler::parity); 13177 int parity_disp = -1; 13178 if ($cop$$cmpcode == Assembler::notEqual) { 13179 parity_disp = l ? (l->loc_pos() - (cbuf.code_size() + 1)) : 0; 13180 } else if ($cop$$cmpcode == Assembler::equal) { 13181 parity_disp = 2; 13182 } else { 13183 ShouldNotReachHere(); 13184 } 13185 emit_d8(cbuf, parity_disp); 13186 emit_cc(cbuf, $primary, $cop$$cmpcode); 13187 int disp = l ? (l->loc_pos() - (cbuf.code_size() + 1)) : 0; 13188 emit_d8(cbuf, disp); 13189 assert(-128 <= disp && disp <= 127, "Displacement too large for short jmp"); 13190 assert(-128 <= parity_disp && parity_disp <= 127, "Displacement too large for short jmp"); 13191 %} 13192 ins_pipe(pipe_jcc); 13193 ins_pc_relative(1); 13194 ins_short_branch(1); 13195 %} 13196 13197 // ============================================================================ 13198 // Long Compare 13199 // 13200 // Currently we hold longs in 2 registers. Comparing such values efficiently 13201 // is tricky. The flavor of compare used depends on whether we are testing 13202 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit. 13203 // The GE test is the negated LT test. The LE test can be had by commuting 13204 // the operands (yielding a GE test) and then negating; negate again for the 13205 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the 13206 // NE test is negated from that. 13207 13208 // Due to a shortcoming in the ADLC, it mixes up expressions like: 13209 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the 13210 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections 13211 // are collapsed internally in the ADLC's dfa-gen code. The match for 13212 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the 13213 // foo match ends up with the wrong leaf. One fix is to not match both 13214 // reg-reg and reg-zero forms of long-compare. This is unfortunate because 13215 // both forms beat the trinary form of long-compare and both are very useful 13216 // on Intel which has so few registers. 13217 13218 // Manifest a CmpL result in an integer register. Very painful. 13219 // This is the test to avoid. 13220 instruct cmpL3_reg_reg(eSIRegI dst, eRegL src1, eRegL src2, eFlagsReg flags ) %{ 13221 match(Set dst (CmpL3 src1 src2)); 13222 effect( KILL flags ); 13223 ins_cost(1000); 13224 format %{ "XOR $dst,$dst\n\t" 13225 "CMP $src1.hi,$src2.hi\n\t" 13226 "JLT,s m_one\n\t" 13227 "JGT,s p_one\n\t" 13228 "CMP $src1.lo,$src2.lo\n\t" 13229 "JB,s m_one\n\t" 13230 "JEQ,s done\n" 13231 "p_one:\tINC $dst\n\t" 13232 "JMP,s done\n" 13233 "m_one:\tDEC $dst\n" 13234 "done:" %} 13235 ins_encode %{ 13236 Label p_one, m_one, done; 13237 __ xorptr($dst$$Register, $dst$$Register); 13238 __ cmpl(HIGH_FROM_LOW($src1$$Register), HIGH_FROM_LOW($src2$$Register)); 13239 __ jccb(Assembler::less, m_one); 13240 __ jccb(Assembler::greater, p_one); 13241 __ cmpl($src1$$Register, $src2$$Register); 13242 __ jccb(Assembler::below, m_one); 13243 __ jccb(Assembler::equal, done); 13244 __ bind(p_one); 13245 __ incrementl($dst$$Register); 13246 __ jmpb(done); 13247 __ bind(m_one); 13248 __ decrementl($dst$$Register); 13249 __ bind(done); 13250 %} 13251 ins_pipe( pipe_slow ); 13252 %} 13253 13254 //====== 13255 // Manifest a CmpL result in the normal flags. Only good for LT or GE 13256 // compares. Can be used for LE or GT compares by reversing arguments. 13257 // NOT GOOD FOR EQ/NE tests. 13258 instruct cmpL_zero_flags_LTGE( flagsReg_long_LTGE flags, eRegL src, immL0 zero ) %{ 13259 match( Set flags (CmpL src zero )); 13260 ins_cost(100); 13261 format %{ "TEST $src.hi,$src.hi" %} 13262 opcode(0x85); 13263 ins_encode( OpcP, RegReg_Hi2( src, src ) ); 13264 ins_pipe( ialu_cr_reg_reg ); 13265 %} 13266 13267 // Manifest a CmpL result in the normal flags. Only good for LT or GE 13268 // compares. Can be used for LE or GT compares by reversing arguments. 13269 // NOT GOOD FOR EQ/NE tests. 13270 instruct cmpL_reg_flags_LTGE( flagsReg_long_LTGE flags, eRegL src1, eRegL src2, eRegI tmp ) %{ 13271 match( Set flags (CmpL src1 src2 )); 13272 effect( TEMP tmp ); 13273 ins_cost(300); 13274 format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t" 13275 "MOV $tmp,$src1.hi\n\t" 13276 "SBB $tmp,$src2.hi\t! Compute flags for long compare" %} 13277 ins_encode( long_cmp_flags2( src1, src2, tmp ) ); 13278 ins_pipe( ialu_cr_reg_reg ); 13279 %} 13280 13281 // Long compares reg < zero/req OR reg >= zero/req. 13282 // Just a wrapper for a normal branch, plus the predicate test. 13283 instruct cmpL_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, label labl) %{ 13284 match(If cmp flags); 13285 effect(USE labl); 13286 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ); 13287 expand %{ 13288 jmpCon(cmp,flags,labl); // JLT or JGE... 13289 %} 13290 %} 13291 13292 // Compare 2 longs and CMOVE longs. 13293 instruct cmovLL_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, eRegL src) %{ 13294 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src))); 13295 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge )); 13296 ins_cost(400); 13297 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t" 13298 "CMOV$cmp $dst.hi,$src.hi" %} 13299 opcode(0x0F,0x40); 13300 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) ); 13301 ins_pipe( pipe_cmov_reg_long ); 13302 %} 13303 13304 instruct cmovLL_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, load_long_memory src) %{ 13305 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src)))); 13306 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge )); 13307 ins_cost(500); 13308 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t" 13309 "CMOV$cmp $dst.hi,$src.hi" %} 13310 opcode(0x0F,0x40); 13311 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) ); 13312 ins_pipe( pipe_cmov_reg_long ); 13313 %} 13314 13315 // Compare 2 longs and CMOVE ints. 13316 instruct cmovII_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegI dst, eRegI src) %{ 13317 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge )); 13318 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src))); 13319 ins_cost(200); 13320 format %{ "CMOV$cmp $dst,$src" %} 13321 opcode(0x0F,0x40); 13322 ins_encode( enc_cmov(cmp), RegReg( dst, src ) ); 13323 ins_pipe( pipe_cmov_reg ); 13324 %} 13325 13326 instruct cmovII_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegI dst, memory src) %{ 13327 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge )); 13328 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src)))); 13329 ins_cost(250); 13330 format %{ "CMOV$cmp $dst,$src" %} 13331 opcode(0x0F,0x40); 13332 ins_encode( enc_cmov(cmp), RegMem( dst, src ) ); 13333 ins_pipe( pipe_cmov_mem ); 13334 %} 13335 13336 // Compare 2 longs and CMOVE ints. 13337 instruct cmovPP_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegP dst, eRegP src) %{ 13338 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge )); 13339 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src))); 13340 ins_cost(200); 13341 format %{ "CMOV$cmp $dst,$src" %} 13342 opcode(0x0F,0x40); 13343 ins_encode( enc_cmov(cmp), RegReg( dst, src ) ); 13344 ins_pipe( pipe_cmov_reg ); 13345 %} 13346 13347 // Compare 2 longs and CMOVE doubles 13348 instruct cmovDD_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regD dst, regD src) %{ 13349 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ); 13350 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src))); 13351 ins_cost(200); 13352 expand %{ 13353 fcmovD_regS(cmp,flags,dst,src); 13354 %} 13355 %} 13356 13357 // Compare 2 longs and CMOVE doubles 13358 instruct cmovXDD_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regXD dst, regXD src) %{ 13359 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ); 13360 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src))); 13361 ins_cost(200); 13362 expand %{ 13363 fcmovXD_regS(cmp,flags,dst,src); 13364 %} 13365 %} 13366 13367 instruct cmovFF_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regF dst, regF src) %{ 13368 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ); 13369 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src))); 13370 ins_cost(200); 13371 expand %{ 13372 fcmovF_regS(cmp,flags,dst,src); 13373 %} 13374 %} 13375 13376 instruct cmovXX_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regX dst, regX src) %{ 13377 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ); 13378 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src))); 13379 ins_cost(200); 13380 expand %{ 13381 fcmovX_regS(cmp,flags,dst,src); 13382 %} 13383 %} 13384 13385 //====== 13386 // Manifest a CmpL result in the normal flags. Only good for EQ/NE compares. 13387 instruct cmpL_zero_flags_EQNE( flagsReg_long_EQNE flags, eRegL src, immL0 zero, eRegI tmp ) %{ 13388 match( Set flags (CmpL src zero )); 13389 effect(TEMP tmp); 13390 ins_cost(200); 13391 format %{ "MOV $tmp,$src.lo\n\t" 13392 "OR $tmp,$src.hi\t! Long is EQ/NE 0?" %} 13393 ins_encode( long_cmp_flags0( src, tmp ) ); 13394 ins_pipe( ialu_reg_reg_long ); 13395 %} 13396 13397 // Manifest a CmpL result in the normal flags. Only good for EQ/NE compares. 13398 instruct cmpL_reg_flags_EQNE( flagsReg_long_EQNE flags, eRegL src1, eRegL src2 ) %{ 13399 match( Set flags (CmpL src1 src2 )); 13400 ins_cost(200+300); 13401 format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t" 13402 "JNE,s skip\n\t" 13403 "CMP $src1.hi,$src2.hi\n\t" 13404 "skip:\t" %} 13405 ins_encode( long_cmp_flags1( src1, src2 ) ); 13406 ins_pipe( ialu_cr_reg_reg ); 13407 %} 13408 13409 // Long compare reg == zero/reg OR reg != zero/reg 13410 // Just a wrapper for a normal branch, plus the predicate test. 13411 instruct cmpL_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, label labl) %{ 13412 match(If cmp flags); 13413 effect(USE labl); 13414 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ); 13415 expand %{ 13416 jmpCon(cmp,flags,labl); // JEQ or JNE... 13417 %} 13418 %} 13419 13420 // Compare 2 longs and CMOVE longs. 13421 instruct cmovLL_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, eRegL src) %{ 13422 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src))); 13423 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne )); 13424 ins_cost(400); 13425 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t" 13426 "CMOV$cmp $dst.hi,$src.hi" %} 13427 opcode(0x0F,0x40); 13428 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) ); 13429 ins_pipe( pipe_cmov_reg_long ); 13430 %} 13431 13432 instruct cmovLL_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, load_long_memory src) %{ 13433 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src)))); 13434 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne )); 13435 ins_cost(500); 13436 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t" 13437 "CMOV$cmp $dst.hi,$src.hi" %} 13438 opcode(0x0F,0x40); 13439 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) ); 13440 ins_pipe( pipe_cmov_reg_long ); 13441 %} 13442 13443 // Compare 2 longs and CMOVE ints. 13444 instruct cmovII_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegI dst, eRegI src) %{ 13445 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne )); 13446 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src))); 13447 ins_cost(200); 13448 format %{ "CMOV$cmp $dst,$src" %} 13449 opcode(0x0F,0x40); 13450 ins_encode( enc_cmov(cmp), RegReg( dst, src ) ); 13451 ins_pipe( pipe_cmov_reg ); 13452 %} 13453 13454 instruct cmovII_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegI dst, memory src) %{ 13455 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne )); 13456 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src)))); 13457 ins_cost(250); 13458 format %{ "CMOV$cmp $dst,$src" %} 13459 opcode(0x0F,0x40); 13460 ins_encode( enc_cmov(cmp), RegMem( dst, src ) ); 13461 ins_pipe( pipe_cmov_mem ); 13462 %} 13463 13464 // Compare 2 longs and CMOVE ints. 13465 instruct cmovPP_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegP dst, eRegP src) %{ 13466 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne )); 13467 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src))); 13468 ins_cost(200); 13469 format %{ "CMOV$cmp $dst,$src" %} 13470 opcode(0x0F,0x40); 13471 ins_encode( enc_cmov(cmp), RegReg( dst, src ) ); 13472 ins_pipe( pipe_cmov_reg ); 13473 %} 13474 13475 // Compare 2 longs and CMOVE doubles 13476 instruct cmovDD_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regD dst, regD src) %{ 13477 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ); 13478 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src))); 13479 ins_cost(200); 13480 expand %{ 13481 fcmovD_regS(cmp,flags,dst,src); 13482 %} 13483 %} 13484 13485 // Compare 2 longs and CMOVE doubles 13486 instruct cmovXDD_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regXD dst, regXD src) %{ 13487 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ); 13488 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src))); 13489 ins_cost(200); 13490 expand %{ 13491 fcmovXD_regS(cmp,flags,dst,src); 13492 %} 13493 %} 13494 13495 instruct cmovFF_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regF dst, regF src) %{ 13496 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ); 13497 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src))); 13498 ins_cost(200); 13499 expand %{ 13500 fcmovF_regS(cmp,flags,dst,src); 13501 %} 13502 %} 13503 13504 instruct cmovXX_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regX dst, regX src) %{ 13505 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ); 13506 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src))); 13507 ins_cost(200); 13508 expand %{ 13509 fcmovX_regS(cmp,flags,dst,src); 13510 %} 13511 %} 13512 13513 //====== 13514 // Manifest a CmpL result in the normal flags. Only good for LE or GT compares. 13515 // Same as cmpL_reg_flags_LEGT except must negate src 13516 instruct cmpL_zero_flags_LEGT( flagsReg_long_LEGT flags, eRegL src, immL0 zero, eRegI tmp ) %{ 13517 match( Set flags (CmpL src zero )); 13518 effect( TEMP tmp ); 13519 ins_cost(300); 13520 format %{ "XOR $tmp,$tmp\t# Long compare for -$src < 0, use commuted test\n\t" 13521 "CMP $tmp,$src.lo\n\t" 13522 "SBB $tmp,$src.hi\n\t" %} 13523 ins_encode( long_cmp_flags3(src, tmp) ); 13524 ins_pipe( ialu_reg_reg_long ); 13525 %} 13526 13527 // Manifest a CmpL result in the normal flags. Only good for LE or GT compares. 13528 // Same as cmpL_reg_flags_LTGE except operands swapped. Swapping operands 13529 // requires a commuted test to get the same result. 13530 instruct cmpL_reg_flags_LEGT( flagsReg_long_LEGT flags, eRegL src1, eRegL src2, eRegI tmp ) %{ 13531 match( Set flags (CmpL src1 src2 )); 13532 effect( TEMP tmp ); 13533 ins_cost(300); 13534 format %{ "CMP $src2.lo,$src1.lo\t! Long compare, swapped operands, use with commuted test\n\t" 13535 "MOV $tmp,$src2.hi\n\t" 13536 "SBB $tmp,$src1.hi\t! Compute flags for long compare" %} 13537 ins_encode( long_cmp_flags2( src2, src1, tmp ) ); 13538 ins_pipe( ialu_cr_reg_reg ); 13539 %} 13540 13541 // Long compares reg < zero/req OR reg >= zero/req. 13542 // Just a wrapper for a normal branch, plus the predicate test 13543 instruct cmpL_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, label labl) %{ 13544 match(If cmp flags); 13545 effect(USE labl); 13546 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le ); 13547 ins_cost(300); 13548 expand %{ 13549 jmpCon(cmp,flags,labl); // JGT or JLE... 13550 %} 13551 %} 13552 13553 // Compare 2 longs and CMOVE longs. 13554 instruct cmovLL_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, eRegL src) %{ 13555 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src))); 13556 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt )); 13557 ins_cost(400); 13558 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t" 13559 "CMOV$cmp $dst.hi,$src.hi" %} 13560 opcode(0x0F,0x40); 13561 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) ); 13562 ins_pipe( pipe_cmov_reg_long ); 13563 %} 13564 13565 instruct cmovLL_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, load_long_memory src) %{ 13566 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src)))); 13567 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt )); 13568 ins_cost(500); 13569 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t" 13570 "CMOV$cmp $dst.hi,$src.hi+4" %} 13571 opcode(0x0F,0x40); 13572 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) ); 13573 ins_pipe( pipe_cmov_reg_long ); 13574 %} 13575 13576 // Compare 2 longs and CMOVE ints. 13577 instruct cmovII_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegI dst, eRegI src) %{ 13578 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt )); 13579 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src))); 13580 ins_cost(200); 13581 format %{ "CMOV$cmp $dst,$src" %} 13582 opcode(0x0F,0x40); 13583 ins_encode( enc_cmov(cmp), RegReg( dst, src ) ); 13584 ins_pipe( pipe_cmov_reg ); 13585 %} 13586 13587 instruct cmovII_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegI dst, memory src) %{ 13588 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt )); 13589 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src)))); 13590 ins_cost(250); 13591 format %{ "CMOV$cmp $dst,$src" %} 13592 opcode(0x0F,0x40); 13593 ins_encode( enc_cmov(cmp), RegMem( dst, src ) ); 13594 ins_pipe( pipe_cmov_mem ); 13595 %} 13596 13597 // Compare 2 longs and CMOVE ptrs. 13598 instruct cmovPP_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegP dst, eRegP src) %{ 13599 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt )); 13600 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src))); 13601 ins_cost(200); 13602 format %{ "CMOV$cmp $dst,$src" %} 13603 opcode(0x0F,0x40); 13604 ins_encode( enc_cmov(cmp), RegReg( dst, src ) ); 13605 ins_pipe( pipe_cmov_reg ); 13606 %} 13607 13608 // Compare 2 longs and CMOVE doubles 13609 instruct cmovDD_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regD dst, regD src) %{ 13610 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ); 13611 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src))); 13612 ins_cost(200); 13613 expand %{ 13614 fcmovD_regS(cmp,flags,dst,src); 13615 %} 13616 %} 13617 13618 // Compare 2 longs and CMOVE doubles 13619 instruct cmovXDD_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regXD dst, regXD src) %{ 13620 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ); 13621 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src))); 13622 ins_cost(200); 13623 expand %{ 13624 fcmovXD_regS(cmp,flags,dst,src); 13625 %} 13626 %} 13627 13628 instruct cmovFF_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regF dst, regF src) %{ 13629 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ); 13630 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src))); 13631 ins_cost(200); 13632 expand %{ 13633 fcmovF_regS(cmp,flags,dst,src); 13634 %} 13635 %} 13636 13637 13638 instruct cmovXX_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regX dst, regX src) %{ 13639 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ); 13640 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src))); 13641 ins_cost(200); 13642 expand %{ 13643 fcmovX_regS(cmp,flags,dst,src); 13644 %} 13645 %} 13646 13647 13648 // ============================================================================ 13649 // Procedure Call/Return Instructions 13650 // Call Java Static Instruction 13651 // Note: If this code changes, the corresponding ret_addr_offset() and 13652 // compute_padding() functions will have to be adjusted. 13653 instruct CallStaticJavaDirect(method meth) %{ 13654 match(CallStaticJava); 13655 effect(USE meth); 13656 13657 ins_cost(300); 13658 format %{ "CALL,static " %} 13659 opcode(0xE8); /* E8 cd */ 13660 ins_encode( pre_call_FPU, 13661 Java_Static_Call( meth ), 13662 call_epilog, 13663 post_call_FPU ); 13664 ins_pipe( pipe_slow ); 13665 ins_pc_relative(1); 13666 ins_alignment(4); 13667 %} 13668 13669 // Call Java Dynamic Instruction 13670 // Note: If this code changes, the corresponding ret_addr_offset() and 13671 // compute_padding() functions will have to be adjusted. 13672 instruct CallDynamicJavaDirect(method meth) %{ 13673 match(CallDynamicJava); 13674 effect(USE meth); 13675 13676 ins_cost(300); 13677 format %{ "MOV EAX,(oop)-1\n\t" 13678 "CALL,dynamic" %} 13679 opcode(0xE8); /* E8 cd */ 13680 ins_encode( pre_call_FPU, 13681 Java_Dynamic_Call( meth ), 13682 call_epilog, 13683 post_call_FPU ); 13684 ins_pipe( pipe_slow ); 13685 ins_pc_relative(1); 13686 ins_alignment(4); 13687 %} 13688 13689 // Call Runtime Instruction 13690 instruct CallRuntimeDirect(method meth) %{ 13691 match(CallRuntime ); 13692 effect(USE meth); 13693 13694 ins_cost(300); 13695 format %{ "CALL,runtime " %} 13696 opcode(0xE8); /* E8 cd */ 13697 // Use FFREEs to clear entries in float stack 13698 ins_encode( pre_call_FPU, 13699 FFree_Float_Stack_All, 13700 Java_To_Runtime( meth ), 13701 post_call_FPU ); 13702 ins_pipe( pipe_slow ); 13703 ins_pc_relative(1); 13704 %} 13705 13706 // Call runtime without safepoint 13707 instruct CallLeafDirect(method meth) %{ 13708 match(CallLeaf); 13709 effect(USE meth); 13710 13711 ins_cost(300); 13712 format %{ "CALL_LEAF,runtime " %} 13713 opcode(0xE8); /* E8 cd */ 13714 ins_encode( pre_call_FPU, 13715 FFree_Float_Stack_All, 13716 Java_To_Runtime( meth ), 13717 Verify_FPU_For_Leaf, post_call_FPU ); 13718 ins_pipe( pipe_slow ); 13719 ins_pc_relative(1); 13720 %} 13721 13722 instruct CallLeafNoFPDirect(method meth) %{ 13723 match(CallLeafNoFP); 13724 effect(USE meth); 13725 13726 ins_cost(300); 13727 format %{ "CALL_LEAF_NOFP,runtime " %} 13728 opcode(0xE8); /* E8 cd */ 13729 ins_encode(Java_To_Runtime(meth)); 13730 ins_pipe( pipe_slow ); 13731 ins_pc_relative(1); 13732 %} 13733 13734 13735 // Return Instruction 13736 // Remove the return address & jump to it. 13737 instruct Ret() %{ 13738 match(Return); 13739 format %{ "RET" %} 13740 opcode(0xC3); 13741 ins_encode(OpcP); 13742 ins_pipe( pipe_jmp ); 13743 %} 13744 13745 // Tail Call; Jump from runtime stub to Java code. 13746 // Also known as an 'interprocedural jump'. 13747 // Target of jump will eventually return to caller. 13748 // TailJump below removes the return address. 13749 instruct TailCalljmpInd(eRegP_no_EBP jump_target, eBXRegP method_oop) %{ 13750 match(TailCall jump_target method_oop ); 13751 ins_cost(300); 13752 format %{ "JMP $jump_target \t# EBX holds method oop" %} 13753 opcode(0xFF, 0x4); /* Opcode FF /4 */ 13754 ins_encode( OpcP, RegOpc(jump_target) ); 13755 ins_pipe( pipe_jmp ); 13756 %} 13757 13758 13759 // Tail Jump; remove the return address; jump to target. 13760 // TailCall above leaves the return address around. 13761 instruct tailjmpInd(eRegP_no_EBP jump_target, eAXRegP ex_oop) %{ 13762 match( TailJump jump_target ex_oop ); 13763 ins_cost(300); 13764 format %{ "POP EDX\t# pop return address into dummy\n\t" 13765 "JMP $jump_target " %} 13766 opcode(0xFF, 0x4); /* Opcode FF /4 */ 13767 ins_encode( enc_pop_rdx, 13768 OpcP, RegOpc(jump_target) ); 13769 ins_pipe( pipe_jmp ); 13770 %} 13771 13772 // Create exception oop: created by stack-crawling runtime code. 13773 // Created exception is now available to this handler, and is setup 13774 // just prior to jumping to this handler. No code emitted. 13775 instruct CreateException( eAXRegP ex_oop ) 13776 %{ 13777 match(Set ex_oop (CreateEx)); 13778 13779 size(0); 13780 // use the following format syntax 13781 format %{ "# exception oop is in EAX; no code emitted" %} 13782 ins_encode(); 13783 ins_pipe( empty ); 13784 %} 13785 13786 13787 // Rethrow exception: 13788 // The exception oop will come in the first argument position. 13789 // Then JUMP (not call) to the rethrow stub code. 13790 instruct RethrowException() 13791 %{ 13792 match(Rethrow); 13793 13794 // use the following format syntax 13795 format %{ "JMP rethrow_stub" %} 13796 ins_encode(enc_rethrow); 13797 ins_pipe( pipe_jmp ); 13798 %} 13799 13800 // inlined locking and unlocking 13801 13802 13803 instruct cmpFastLock( eFlagsReg cr, eRegP object, eRegP box, eAXRegI tmp, eRegP scr) %{ 13804 match( Set cr (FastLock object box) ); 13805 effect( TEMP tmp, TEMP scr ); 13806 ins_cost(300); 13807 format %{ "FASTLOCK $object, $box KILLS $tmp,$scr" %} 13808 ins_encode( Fast_Lock(object,box,tmp,scr) ); 13809 ins_pipe( pipe_slow ); 13810 ins_pc_relative(1); 13811 %} 13812 13813 instruct cmpFastUnlock( eFlagsReg cr, eRegP object, eAXRegP box, eRegP tmp ) %{ 13814 match( Set cr (FastUnlock object box) ); 13815 effect( TEMP tmp ); 13816 ins_cost(300); 13817 format %{ "FASTUNLOCK $object, $box, $tmp" %} 13818 ins_encode( Fast_Unlock(object,box,tmp) ); 13819 ins_pipe( pipe_slow ); 13820 ins_pc_relative(1); 13821 %} 13822 13823 13824 13825 // ============================================================================ 13826 // Safepoint Instruction 13827 instruct safePoint_poll(eFlagsReg cr) %{ 13828 match(SafePoint); 13829 effect(KILL cr); 13830 13831 // TODO-FIXME: we currently poll at offset 0 of the safepoint polling page. 13832 // On SPARC that might be acceptable as we can generate the address with 13833 // just a sethi, saving an or. By polling at offset 0 we can end up 13834 // putting additional pressure on the index-0 in the D$. Because of 13835 // alignment (just like the situation at hand) the lower indices tend 13836 // to see more traffic. It'd be better to change the polling address 13837 // to offset 0 of the last $line in the polling page. 13838 13839 format %{ "TSTL #polladdr,EAX\t! Safepoint: poll for GC" %} 13840 ins_cost(125); 13841 size(6) ; 13842 ins_encode( Safepoint_Poll() ); 13843 ins_pipe( ialu_reg_mem ); 13844 %} 13845 13846 //----------PEEPHOLE RULES----------------------------------------------------- 13847 // These must follow all instruction definitions as they use the names 13848 // defined in the instructions definitions. 13849 // 13850 // peepmatch ( root_instr_name [preceding_instruction]* ); 13851 // 13852 // peepconstraint %{ 13853 // (instruction_number.operand_name relational_op instruction_number.operand_name 13854 // [, ...] ); 13855 // // instruction numbers are zero-based using left to right order in peepmatch 13856 // 13857 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) ); 13858 // // provide an instruction_number.operand_name for each operand that appears 13859 // // in the replacement instruction's match rule 13860 // 13861 // ---------VM FLAGS--------------------------------------------------------- 13862 // 13863 // All peephole optimizations can be turned off using -XX:-OptoPeephole 13864 // 13865 // Each peephole rule is given an identifying number starting with zero and 13866 // increasing by one in the order seen by the parser. An individual peephole 13867 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=# 13868 // on the command-line. 13869 // 13870 // ---------CURRENT LIMITATIONS---------------------------------------------- 13871 // 13872 // Only match adjacent instructions in same basic block 13873 // Only equality constraints 13874 // Only constraints between operands, not (0.dest_reg == EAX_enc) 13875 // Only one replacement instruction 13876 // 13877 // ---------EXAMPLE---------------------------------------------------------- 13878 // 13879 // // pertinent parts of existing instructions in architecture description 13880 // instruct movI(eRegI dst, eRegI src) %{ 13881 // match(Set dst (CopyI src)); 13882 // %} 13883 // 13884 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{ 13885 // match(Set dst (AddI dst src)); 13886 // effect(KILL cr); 13887 // %} 13888 // 13889 // // Change (inc mov) to lea 13890 // peephole %{ 13891 // // increment preceeded by register-register move 13892 // peepmatch ( incI_eReg movI ); 13893 // // require that the destination register of the increment 13894 // // match the destination register of the move 13895 // peepconstraint ( 0.dst == 1.dst ); 13896 // // construct a replacement instruction that sets 13897 // // the destination to ( move's source register + one ) 13898 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) ); 13899 // %} 13900 // 13901 // Implementation no longer uses movX instructions since 13902 // machine-independent system no longer uses CopyX nodes. 13903 // 13904 // peephole %{ 13905 // peepmatch ( incI_eReg movI ); 13906 // peepconstraint ( 0.dst == 1.dst ); 13907 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) ); 13908 // %} 13909 // 13910 // peephole %{ 13911 // peepmatch ( decI_eReg movI ); 13912 // peepconstraint ( 0.dst == 1.dst ); 13913 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) ); 13914 // %} 13915 // 13916 // peephole %{ 13917 // peepmatch ( addI_eReg_imm movI ); 13918 // peepconstraint ( 0.dst == 1.dst ); 13919 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) ); 13920 // %} 13921 // 13922 // peephole %{ 13923 // peepmatch ( addP_eReg_imm movP ); 13924 // peepconstraint ( 0.dst == 1.dst ); 13925 // peepreplace ( leaP_eReg_immI( 0.dst 1.src 0.src ) ); 13926 // %} 13927 13928 // // Change load of spilled value to only a spill 13929 // instruct storeI(memory mem, eRegI src) %{ 13930 // match(Set mem (StoreI mem src)); 13931 // %} 13932 // 13933 // instruct loadI(eRegI dst, memory mem) %{ 13934 // match(Set dst (LoadI mem)); 13935 // %} 13936 // 13937 peephole %{ 13938 peepmatch ( loadI storeI ); 13939 peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem ); 13940 peepreplace ( storeI( 1.mem 1.mem 1.src ) ); 13941 %} 13942 13943 //----------SMARTSPILL RULES--------------------------------------------------- 13944 // These must follow all instruction definitions as they use the names 13945 // defined in the instructions definitions.