1264 address double_address = __ double_constant(x);
1265 cbuf.insts()->set_mark_off(mark); // preserve mark across masm shift
1266 emit_d32_reloc(cbuf,
1267 (int)double_address,
1268 internal_word_Relocation::spec(double_address),
1269 RELOC_DISP32);
1270 }
1271
1272 static void emit_float_constant(CodeBuffer& cbuf, float x) {
1273 int mark = cbuf.insts()->mark_off();
1274 MacroAssembler _masm(&cbuf);
1275 address float_address = __ float_constant(x);
1276 cbuf.insts()->set_mark_off(mark); // preserve mark across masm shift
1277 emit_d32_reloc(cbuf,
1278 (int)float_address,
1279 internal_word_Relocation::spec(float_address),
1280 RELOC_DISP32);
1281 }
1282
1283
1284 int Matcher::regnum_to_fpu_offset(int regnum) {
1285 return regnum - 32; // The FP registers are in the second chunk
1286 }
1287
1288 bool is_positive_zero_float(jfloat f) {
1289 return jint_cast(f) == jint_cast(0.0F);
1290 }
1291
1292 bool is_positive_one_float(jfloat f) {
1293 return jint_cast(f) == jint_cast(1.0F);
1294 }
1295
1296 bool is_positive_zero_double(jdouble d) {
1297 return jlong_cast(d) == jlong_cast(0.0);
1298 }
1299
1300 bool is_positive_one_double(jdouble d) {
1301 return jlong_cast(d) == jlong_cast(1.0);
1302 }
1303
6627
6628 format %{ "BSWAP $dst" %}
6629 opcode(0x0F, 0xC8);
6630 ins_encode( OpcP, OpcSReg(dst) );
6631 ins_pipe( ialu_reg );
6632 %}
6633
6634 instruct bytes_reverse_long(eRegL dst) %{
6635 match(Set dst (ReverseBytesL dst));
6636
6637 format %{ "BSWAP $dst.lo\n\t"
6638 "BSWAP $dst.hi\n\t"
6639 "XCHG $dst.lo $dst.hi" %}
6640
6641 ins_cost(125);
6642 ins_encode( bswap_long_bytes(dst) );
6643 ins_pipe( ialu_reg_reg);
6644 %}
6645
6646
6647 //---------- Population Count Instructions -------------------------------------
6648
6649 instruct popCountI(eRegI dst, eRegI src) %{
6650 predicate(UsePopCountInstruction);
6651 match(Set dst (PopCountI src));
6652
6653 format %{ "POPCNT $dst, $src" %}
6654 ins_encode %{
6655 __ popcntl($dst$$Register, $src$$Register);
6656 %}
6657 ins_pipe(ialu_reg);
6658 %}
6659
6660 instruct popCountI_mem(eRegI dst, memory mem) %{
6661 predicate(UsePopCountInstruction);
6662 match(Set dst (PopCountI (LoadI mem)));
6663
6664 format %{ "POPCNT $dst, $mem" %}
6665 ins_encode %{
6666 __ popcntl($dst$$Register, $mem$$Address);
|
1264 address double_address = __ double_constant(x);
1265 cbuf.insts()->set_mark_off(mark); // preserve mark across masm shift
1266 emit_d32_reloc(cbuf,
1267 (int)double_address,
1268 internal_word_Relocation::spec(double_address),
1269 RELOC_DISP32);
1270 }
1271
1272 static void emit_float_constant(CodeBuffer& cbuf, float x) {
1273 int mark = cbuf.insts()->mark_off();
1274 MacroAssembler _masm(&cbuf);
1275 address float_address = __ float_constant(x);
1276 cbuf.insts()->set_mark_off(mark); // preserve mark across masm shift
1277 emit_d32_reloc(cbuf,
1278 (int)float_address,
1279 internal_word_Relocation::spec(float_address),
1280 RELOC_DISP32);
1281 }
1282
1283
1284 const bool Matcher::match_rule_supported(int opcode) {
1285 if (!has_match_rule(opcode))
1286 return false;
1287
1288 return true; // Per default match rules are supported.
1289 }
1290
1291 int Matcher::regnum_to_fpu_offset(int regnum) {
1292 return regnum - 32; // The FP registers are in the second chunk
1293 }
1294
1295 bool is_positive_zero_float(jfloat f) {
1296 return jint_cast(f) == jint_cast(0.0F);
1297 }
1298
1299 bool is_positive_one_float(jfloat f) {
1300 return jint_cast(f) == jint_cast(1.0F);
1301 }
1302
1303 bool is_positive_zero_double(jdouble d) {
1304 return jlong_cast(d) == jlong_cast(0.0);
1305 }
1306
1307 bool is_positive_one_double(jdouble d) {
1308 return jlong_cast(d) == jlong_cast(1.0);
1309 }
1310
6634
6635 format %{ "BSWAP $dst" %}
6636 opcode(0x0F, 0xC8);
6637 ins_encode( OpcP, OpcSReg(dst) );
6638 ins_pipe( ialu_reg );
6639 %}
6640
6641 instruct bytes_reverse_long(eRegL dst) %{
6642 match(Set dst (ReverseBytesL dst));
6643
6644 format %{ "BSWAP $dst.lo\n\t"
6645 "BSWAP $dst.hi\n\t"
6646 "XCHG $dst.lo $dst.hi" %}
6647
6648 ins_cost(125);
6649 ins_encode( bswap_long_bytes(dst) );
6650 ins_pipe( ialu_reg_reg);
6651 %}
6652
6653
6654 //---------- Zeros Count Instructions ------------------------------------------
6655
6656 instruct countLeadingZerosI(eRegI dst, eRegI src, eFlagsReg cr) %{
6657 predicate(UseCountLeadingZerosInstruction);
6658 match(Set dst (CountLeadingZerosI src));
6659 effect(KILL cr);
6660
6661 format %{ "LZCNT $dst, $src\t# count leading zeros (int)" %}
6662 ins_encode %{
6663 __ lzcntl($dst$$Register, $src$$Register);
6664 %}
6665 ins_pipe(ialu_reg);
6666 %}
6667
6668 instruct countLeadingZerosI_bsr(eRegI dst, eRegI src, eRegI tmp, eFlagsReg cr) %{
6669 predicate(!UseCountLeadingZerosInstruction);
6670 match(Set dst (CountLeadingZerosI src));
6671 effect(TEMP dst, TEMP tmp, KILL cr);
6672
6673 format %{ "BSR $tmp, $src\t# count leading zeros (int)\n\t"
6674 "JNZ skip\n\t"
6675 "MOV $tmp, -1\n"
6676 "skip:\n\t"
6677 "MOV $dst, 31\n\t"
6678 "SUB $dst, $tmp" %}
6679 ins_encode %{
6680 Label skip;
6681 __ bsrl($tmp$$Register, $src$$Register);
6682 __ jccb(Assembler::notZero, skip);
6683 __ movl($tmp$$Register, -1);
6684 __ bind(skip);
6685 __ movl($dst$$Register, BitsPerInt - 1);
6686 __ subl($dst$$Register, $tmp$$Register);
6687 %}
6688 ins_pipe(ialu_reg);
6689 %}
6690
6691 instruct countLeadingZerosL(eRegI dst, eRegL src, eRegI tmp, eFlagsReg cr) %{
6692 predicate(UseCountLeadingZerosInstruction);
6693 match(Set dst (CountLeadingZerosL src));
6694 effect(TEMP dst, TEMP tmp, KILL cr);
6695
6696 format %{ "LZCNT $dst, $src.hi\t# count leading zeros (long)\n\t"
6697 "JNC done\n\t"
6698 "LZCNT $tmp, $src.lo\n\t"
6699 "ADD $dst, $tmp\n"
6700 "done:" %}
6701 ins_encode %{
6702 Register Rdst = $dst$$Register;
6703 Register Rsrc = $src$$Register;
6704 Register Rtmp = $tmp$$Register;
6705 Label done;
6706 __ lzcntl(Rdst, HIGH_FROM_LOW(Rsrc));
6707 __ jccb(Assembler::carryClear, done);
6708 __ lzcntl(Rtmp, Rsrc);
6709 __ addl(Rdst, Rtmp);
6710 __ bind(done);
6711 %}
6712 ins_pipe(ialu_reg);
6713 %}
6714
6715 instruct countLeadingZerosL_bsr(eRegI dst, eRegL src, eRegI tmp, eFlagsReg cr) %{
6716 predicate(!UseCountLeadingZerosInstruction);
6717 match(Set dst (CountLeadingZerosL src));
6718 effect(TEMP dst, TEMP tmp, KILL cr);
6719
6720 format %{ "BSR $tmp, $src.hi\t# count leading zeros (long)\n\t"
6721 "JZ msw_is_zero\n\t"
6722 "MOV $dst, 31\n\t"
6723 "SUB $dst, $tmp\n\t"
6724 "JMP done\n"
6725 "msw_is_zero:\n\t"
6726 "BSR $tmp, $src.lo\n\t"
6727 "JNZ lsw_is_not_zero\n\t"
6728 "MOV $tmp, -1\n"
6729 "lsw_is_not_zero:\n\t"
6730 "MOV $dst, 63\n\t"
6731 "SUB $dst, $tmp\n"
6732 "done:" %}
6733 ins_encode %{
6734 Register Rdst = $dst$$Register;
6735 Register Rsrc = $src$$Register;
6736 Register Rtmp = $tmp$$Register;
6737 Label msw_is_zero;
6738 Label lsw_is_not_zero;
6739 Label done;
6740 __ bsrl(Rtmp, HIGH_FROM_LOW(Rsrc));
6741 __ jccb(Assembler::zero, msw_is_zero);
6742 __ movl(Rdst, BitsPerLong - 1 - BitsPerInt); // Subtract 32 bit positions for LSW
6743 __ subl(Rdst, Rtmp);
6744 __ jmpb(done);
6745 __ bind(msw_is_zero);
6746 __ bsrl(Rtmp, Rsrc);
6747 __ jccb(Assembler::notZero, lsw_is_not_zero);
6748 __ movl(Rtmp, -1);
6749 __ bind(lsw_is_not_zero);
6750 __ movl(Rdst, BitsPerLong - 1);
6751 __ subl(Rdst, Rtmp);
6752 __ bind(done);
6753
6754 %}
6755 ins_pipe(ialu_reg);
6756 %}
6757
6758 instruct countTrailingZerosI(eRegI dst, eRegI src, eRegI tmp, eFlagsReg cr) %{
6759 match(Set dst (CountTrailingZerosI src));
6760 effect(TEMP tmp, KILL cr);
6761
6762 format %{ "BSF $dst, $src\t# count trailing zeros (int)\n\t"
6763 "JNZ done\n\t"
6764 "MOV $dst, 32\n"
6765 "done:" %}
6766 ins_encode %{
6767 Label done;
6768 __ bsfl($dst$$Register, $src$$Register);
6769 __ jccb(Assembler::notZero, done);
6770 __ movl($dst$$Register, BitsPerInt);
6771 __ bind(done);
6772 %}
6773 ins_pipe(ialu_reg);
6774 %}
6775
6776 instruct countTrailingZerosL(eRegI dst, eRegL src, eRegI tmp, eFlagsReg cr) %{
6777 match(Set dst (CountTrailingZerosL src));
6778 effect(TEMP dst, TEMP tmp, KILL cr);
6779
6780 format %{ "BSF $dst, $src.lo\t# count trailing zeros (long)\n\t"
6781 "JNZ done\n\t"
6782 "BSF $tmp, $src.hi\n\t"
6783 "MOV $dst, 32\n\t"
6784 "CMOVZ $tmp, $dst\n\t"
6785 "ADD $dst, $tmp\n"
6786 "done:" %}
6787 ins_encode %{
6788 Register Rdst = $dst$$Register;
6789 Register Rsrc = $src$$Register;
6790 Register Rtmp = $tmp$$Register;
6791 Label done;
6792 __ bsfl(Rdst, Rsrc);
6793 __ jccb(Assembler::notZero, done);
6794 __ bsfl(Rtmp, HIGH_FROM_LOW(Rsrc));
6795 __ movl(Rdst, BitsPerInt);
6796 __ cmovl(Assembler::zero, Rtmp, Rdst);
6797 __ addl(Rdst, Rtmp);
6798 __ bind(done);
6799 %}
6800 ins_pipe(ialu_reg);
6801 %}
6802
6803
6804 //---------- Population Count Instructions -------------------------------------
6805
6806 instruct popCountI(eRegI dst, eRegI src) %{
6807 predicate(UsePopCountInstruction);
6808 match(Set dst (PopCountI src));
6809
6810 format %{ "POPCNT $dst, $src" %}
6811 ins_encode %{
6812 __ popcntl($dst$$Register, $src$$Register);
6813 %}
6814 ins_pipe(ialu_reg);
6815 %}
6816
6817 instruct popCountI_mem(eRegI dst, memory mem) %{
6818 predicate(UsePopCountInstruction);
6819 match(Set dst (PopCountI (LoadI mem)));
6820
6821 format %{ "POPCNT $dst, $mem" %}
6822 ins_encode %{
6823 __ popcntl($dst$$Register, $mem$$Address);
|