1963 address double_address = __ double_constant(x);
1964 cbuf.insts()->set_mark_off(mark); // preserve mark across masm shift
1965 emit_d32_reloc(cbuf,
1966 (int) (double_address - cbuf.code_end() - 4),
1967 internal_word_Relocation::spec(double_address),
1968 RELOC_DISP32);
1969 }
1970
1971 static void emit_float_constant(CodeBuffer& cbuf, float x) {
1972 int mark = cbuf.insts()->mark_off();
1973 MacroAssembler _masm(&cbuf);
1974 address float_address = __ float_constant(x);
1975 cbuf.insts()->set_mark_off(mark); // preserve mark across masm shift
1976 emit_d32_reloc(cbuf,
1977 (int) (float_address - cbuf.code_end() - 4),
1978 internal_word_Relocation::spec(float_address),
1979 RELOC_DISP32);
1980 }
1981
1982
1983 int Matcher::regnum_to_fpu_offset(int regnum)
1984 {
1985 return regnum - 32; // The FP registers are in the second chunk
1986 }
1987
1988 // This is UltraSparc specific, true just means we have fast l2f conversion
1989 const bool Matcher::convL2FSupported(void) {
1990 return true;
1991 }
1992
1993 // Vector width in bytes
1994 const uint Matcher::vector_width_in_bytes(void) {
1995 return 8;
1996 }
1997
1998 // Vector ideal reg
1999 const uint Matcher::vector_ideal_reg(void) {
2000 return Op_RegD;
2001 }
2002
7639
7640 instruct storeI_reversed(memory dst, rRegI src) %{
7641 match(Set dst (StoreI dst (ReverseBytesI src)));
7642
7643 format %{ "movl_bswap $dst, $src" %}
7644 opcode(0x0F, 0xC8, 0x89); /* Opcode 0F C8 89 */
7645 ins_encode( REX_reg(src), OpcP, opc2_reg(src), REX_reg_mem(src, dst), OpcT, reg_mem(src, dst) );
7646 ins_pipe( ialu_mem_reg );
7647 %}
7648
7649 instruct storeL_reversed(memory dst, rRegL src) %{
7650 match(Set dst (StoreL dst (ReverseBytesL src)));
7651
7652 format %{ "movq_bswap $dst, $src" %}
7653 opcode(0x0F, 0xC8, 0x89); /* Opcode 0F C8 89 */
7654 ins_encode( REX_reg_wide(src), OpcP, opc2_reg(src), REX_reg_mem_wide(src, dst), OpcT, reg_mem(src, dst) );
7655 ins_pipe( ialu_mem_reg );
7656 %}
7657
7658
7659 //---------- Population Count Instructions -------------------------------------
7660
7661 instruct popCountI(rRegI dst, rRegI src) %{
7662 predicate(UsePopCountInstruction);
7663 match(Set dst (PopCountI src));
7664
7665 format %{ "popcnt $dst, $src" %}
7666 ins_encode %{
7667 __ popcntl($dst$$Register, $src$$Register);
7668 %}
7669 ins_pipe(ialu_reg);
7670 %}
7671
7672 instruct popCountI_mem(rRegI dst, memory mem) %{
7673 predicate(UsePopCountInstruction);
7674 match(Set dst (PopCountI (LoadI mem)));
7675
7676 format %{ "popcnt $dst, $mem" %}
7677 ins_encode %{
7678 __ popcntl($dst$$Register, $mem$$Address);
|
1963 address double_address = __ double_constant(x);
1964 cbuf.insts()->set_mark_off(mark); // preserve mark across masm shift
1965 emit_d32_reloc(cbuf,
1966 (int) (double_address - cbuf.code_end() - 4),
1967 internal_word_Relocation::spec(double_address),
1968 RELOC_DISP32);
1969 }
1970
1971 static void emit_float_constant(CodeBuffer& cbuf, float x) {
1972 int mark = cbuf.insts()->mark_off();
1973 MacroAssembler _masm(&cbuf);
1974 address float_address = __ float_constant(x);
1975 cbuf.insts()->set_mark_off(mark); // preserve mark across masm shift
1976 emit_d32_reloc(cbuf,
1977 (int) (float_address - cbuf.code_end() - 4),
1978 internal_word_Relocation::spec(float_address),
1979 RELOC_DISP32);
1980 }
1981
1982
1983 const bool Matcher::match_rule_supported(int opcode) {
1984 if (!has_match_rule(opcode))
1985 return false;
1986
1987 return true; // Per default match rules are supported.
1988 }
1989
1990 int Matcher::regnum_to_fpu_offset(int regnum)
1991 {
1992 return regnum - 32; // The FP registers are in the second chunk
1993 }
1994
1995 // This is UltraSparc specific, true just means we have fast l2f conversion
1996 const bool Matcher::convL2FSupported(void) {
1997 return true;
1998 }
1999
2000 // Vector width in bytes
2001 const uint Matcher::vector_width_in_bytes(void) {
2002 return 8;
2003 }
2004
2005 // Vector ideal reg
2006 const uint Matcher::vector_ideal_reg(void) {
2007 return Op_RegD;
2008 }
2009
7646
7647 instruct storeI_reversed(memory dst, rRegI src) %{
7648 match(Set dst (StoreI dst (ReverseBytesI src)));
7649
7650 format %{ "movl_bswap $dst, $src" %}
7651 opcode(0x0F, 0xC8, 0x89); /* Opcode 0F C8 89 */
7652 ins_encode( REX_reg(src), OpcP, opc2_reg(src), REX_reg_mem(src, dst), OpcT, reg_mem(src, dst) );
7653 ins_pipe( ialu_mem_reg );
7654 %}
7655
7656 instruct storeL_reversed(memory dst, rRegL src) %{
7657 match(Set dst (StoreL dst (ReverseBytesL src)));
7658
7659 format %{ "movq_bswap $dst, $src" %}
7660 opcode(0x0F, 0xC8, 0x89); /* Opcode 0F C8 89 */
7661 ins_encode( REX_reg_wide(src), OpcP, opc2_reg(src), REX_reg_mem_wide(src, dst), OpcT, reg_mem(src, dst) );
7662 ins_pipe( ialu_mem_reg );
7663 %}
7664
7665
7666 //---------- Zeros Count Instructions ------------------------------------------
7667
7668 instruct countLeadingZerosI(rRegI dst, rRegI src, rFlagsReg cr) %{
7669 predicate(UseCountLeadingZerosInstruction);
7670 match(Set dst (CountLeadingZerosI src));
7671 effect(KILL cr);
7672
7673 format %{ "lzcntl $dst, $src\t# count leading zeros (int)" %}
7674 ins_encode %{
7675 __ lzcntl($dst$$Register, $src$$Register);
7676 %}
7677 ins_pipe(ialu_reg);
7678 %}
7679
7680 instruct countLeadingZerosI_bsr(rRegI dst, rRegI src, rRegI tmp, rFlagsReg cr) %{
7681 predicate(!UseCountLeadingZerosInstruction);
7682 match(Set dst (CountLeadingZerosI src));
7683 effect(TEMP dst, TEMP tmp, KILL cr);
7684
7685 format %{ "bsrl $tmp, $src\t# count leading zeros (int)\n\t"
7686 "jnz skip\n\t"
7687 "movl $tmp, -1\n"
7688 "skip:\n\t"
7689 "movl $dst, 31\n\t"
7690 "subl $dst, $tmp" %}
7691 ins_encode %{
7692 Label skip;
7693 __ bsrl($tmp$$Register, $src$$Register);
7694 __ jccb(Assembler::notZero, skip);
7695 __ movl($tmp$$Register, -1);
7696 __ bind(skip);
7697 __ movl($dst$$Register, BitsPerInt - 1);
7698 __ subl($dst$$Register, $tmp$$Register);
7699 %}
7700 ins_pipe(ialu_reg);
7701 %}
7702
7703 instruct countLeadingZerosL(rRegI dst, rRegL src, rFlagsReg cr) %{
7704 predicate(UseCountLeadingZerosInstruction);
7705 match(Set dst (CountLeadingZerosL src));
7706 effect(KILL cr);
7707
7708 format %{ "lzcntq $dst, $src\t# count leading zeros (long)" %}
7709 ins_encode %{
7710 __ lzcntq($dst$$Register, $src$$Register);
7711 %}
7712 ins_pipe(ialu_reg);
7713 %}
7714
7715 instruct countLeadingZerosL_bsr(rRegI dst, rRegL src, rRegI tmp, rFlagsReg cr) %{
7716 predicate(!UseCountLeadingZerosInstruction);
7717 match(Set dst (CountLeadingZerosL src));
7718 effect(TEMP dst, TEMP tmp, KILL cr);
7719
7720 format %{ "bsrq $tmp, $src\t# count leading zeros (long)\n\t"
7721 "jnz skip\n\t"
7722 "movl $tmp, -1\n"
7723 "skip:\n\t"
7724 "movl $dst, 63\n\t"
7725 "subl $dst, $tmp" %}
7726 ins_encode %{
7727 Label skip;
7728 __ bsrq($tmp$$Register, $src$$Register);
7729 __ jccb(Assembler::notZero, skip);
7730 __ movl($tmp$$Register, -1);
7731 __ bind(skip);
7732 __ movl($dst$$Register, BitsPerLong - 1);
7733 __ subl($dst$$Register, $tmp$$Register);
7734 %}
7735 ins_pipe(ialu_reg);
7736 %}
7737
7738 instruct countTrailingZerosI(rRegI dst, rRegI src, rFlagsReg cr) %{
7739 match(Set dst (CountTrailingZerosI src));
7740 effect(KILL cr);
7741
7742 format %{ "bsfl $dst, $src\t# count trailing zeros (int)\n\t"
7743 "jnz done\n\t"
7744 "movl $dst, 32\n"
7745 "done:" %}
7746 ins_encode %{
7747 Label done;
7748 __ bsfl($dst$$Register, $src$$Register);
7749 __ jccb(Assembler::notZero, done);
7750 __ movl($dst$$Register, BitsPerInt);
7751 __ bind(done);
7752 %}
7753 ins_pipe(ialu_reg);
7754 %}
7755
7756 instruct countTrailingZerosL(rRegI dst, rRegL src, rFlagsReg cr) %{
7757 match(Set dst (CountTrailingZerosL src));
7758 effect(KILL cr);
7759
7760 format %{ "bsfq $dst, $src\t# count trailing zeros (long)\n\t"
7761 "jnz done\n\t"
7762 "movl $dst, 64\n"
7763 "done:" %}
7764 ins_encode %{
7765 Label done;
7766 __ bsfq($dst$$Register, $src$$Register);
7767 __ jccb(Assembler::notZero, done);
7768 __ movl($dst$$Register, BitsPerLong);
7769 __ bind(done);
7770 %}
7771 ins_pipe(ialu_reg);
7772 %}
7773
7774
7775 //---------- Population Count Instructions -------------------------------------
7776
7777 instruct popCountI(rRegI dst, rRegI src) %{
7778 predicate(UsePopCountInstruction);
7779 match(Set dst (PopCountI src));
7780
7781 format %{ "popcnt $dst, $src" %}
7782 ins_encode %{
7783 __ popcntl($dst$$Register, $src$$Register);
7784 %}
7785 ins_pipe(ialu_reg);
7786 %}
7787
7788 instruct popCountI_mem(rRegI dst, memory mem) %{
7789 predicate(UsePopCountInstruction);
7790 match(Set dst (PopCountI (LoadI mem)));
7791
7792 format %{ "popcnt $dst, $mem" %}
7793 ins_encode %{
7794 __ popcntl($dst$$Register, $mem$$Address);
|