1 //
2 // Copyright 1998-2009 Sun Microsystems, Inc. All Rights Reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
9 // This code is distributed in the hope that it will be useful, but WITHOUT
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
15 // You should have received a copy of the GNU General Public License version
16 // 2 along with this work; if not, write to the Free Software Foundation,
17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 //
19 // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
20 // CA 95054 USA or visit www.sun.com if you need additional information or
21 // have any questions.
22 //
23 //
24
25 // SPARC Architecture Description File
26
27 //----------REGISTER DEFINITION BLOCK------------------------------------------
28 // This information is used by the matcher and the register allocator to
29 // describe individual registers and classes of registers within the target
30 // archtecture.
31 register %{
32 //----------Architecture Description Register Definitions----------------------
33 // General Registers
34 // "reg_def" name ( register save type, C convention save type,
35 // ideal register type, encoding, vm name );
36 // Register Save Types:
37 //
38 // NS = No-Save: The register allocator assumes that these registers
39 // can be used without saving upon entry to the method, &
40 // that they do not need to be saved at call sites.
41 //
42 // SOC = Save-On-Call: The register allocator assumes that these registers
43 // can be used without saving upon entry to the method,
44 // but that they must be saved at call sites.
45 //
46 // SOE = Save-On-Entry: The register allocator assumes that these registers
47 // must be saved before using them upon entry to the
48 // method, but they do not need to be saved at call
49 // sites.
50 //
51 // AS = Always-Save: The register allocator assumes that these registers
52 // must be saved before using them upon entry to the
53 // method, & that they must be saved at call sites.
54 //
55 // Ideal Register Type is used to determine how to save & restore a
56 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
57 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
58 //
59 // The encoding number is the actual bit-pattern placed into the opcodes.
60
61
62 // ----------------------------
63 // Integer/Long Registers
64 // ----------------------------
65
66 // Need to expose the hi/lo aspect of 64-bit registers
67 // This register set is used for both the 64-bit build and
68 // the 32-bit build with 1-register longs.
69
70 // Global Registers 0-7
71 reg_def R_G0H( NS, NS, Op_RegI,128, G0->as_VMReg()->next());
72 reg_def R_G0 ( NS, NS, Op_RegI, 0, G0->as_VMReg());
73 reg_def R_G1H(SOC, SOC, Op_RegI,129, G1->as_VMReg()->next());
74 reg_def R_G1 (SOC, SOC, Op_RegI, 1, G1->as_VMReg());
75 reg_def R_G2H( NS, NS, Op_RegI,130, G2->as_VMReg()->next());
76 reg_def R_G2 ( NS, NS, Op_RegI, 2, G2->as_VMReg());
77 reg_def R_G3H(SOC, SOC, Op_RegI,131, G3->as_VMReg()->next());
78 reg_def R_G3 (SOC, SOC, Op_RegI, 3, G3->as_VMReg());
79 reg_def R_G4H(SOC, SOC, Op_RegI,132, G4->as_VMReg()->next());
80 reg_def R_G4 (SOC, SOC, Op_RegI, 4, G4->as_VMReg());
81 reg_def R_G5H(SOC, SOC, Op_RegI,133, G5->as_VMReg()->next());
82 reg_def R_G5 (SOC, SOC, Op_RegI, 5, G5->as_VMReg());
83 reg_def R_G6H( NS, NS, Op_RegI,134, G6->as_VMReg()->next());
84 reg_def R_G6 ( NS, NS, Op_RegI, 6, G6->as_VMReg());
85 reg_def R_G7H( NS, NS, Op_RegI,135, G7->as_VMReg()->next());
86 reg_def R_G7 ( NS, NS, Op_RegI, 7, G7->as_VMReg());
87
88 // Output Registers 0-7
89 reg_def R_O0H(SOC, SOC, Op_RegI,136, O0->as_VMReg()->next());
90 reg_def R_O0 (SOC, SOC, Op_RegI, 8, O0->as_VMReg());
91 reg_def R_O1H(SOC, SOC, Op_RegI,137, O1->as_VMReg()->next());
92 reg_def R_O1 (SOC, SOC, Op_RegI, 9, O1->as_VMReg());
93 reg_def R_O2H(SOC, SOC, Op_RegI,138, O2->as_VMReg()->next());
94 reg_def R_O2 (SOC, SOC, Op_RegI, 10, O2->as_VMReg());
95 reg_def R_O3H(SOC, SOC, Op_RegI,139, O3->as_VMReg()->next());
96 reg_def R_O3 (SOC, SOC, Op_RegI, 11, O3->as_VMReg());
97 reg_def R_O4H(SOC, SOC, Op_RegI,140, O4->as_VMReg()->next());
98 reg_def R_O4 (SOC, SOC, Op_RegI, 12, O4->as_VMReg());
99 reg_def R_O5H(SOC, SOC, Op_RegI,141, O5->as_VMReg()->next());
100 reg_def R_O5 (SOC, SOC, Op_RegI, 13, O5->as_VMReg());
101 reg_def R_SPH( NS, NS, Op_RegI,142, SP->as_VMReg()->next());
102 reg_def R_SP ( NS, NS, Op_RegI, 14, SP->as_VMReg());
103 reg_def R_O7H(SOC, SOC, Op_RegI,143, O7->as_VMReg()->next());
104 reg_def R_O7 (SOC, SOC, Op_RegI, 15, O7->as_VMReg());
105
106 // Local Registers 0-7
107 reg_def R_L0H( NS, NS, Op_RegI,144, L0->as_VMReg()->next());
108 reg_def R_L0 ( NS, NS, Op_RegI, 16, L0->as_VMReg());
109 reg_def R_L1H( NS, NS, Op_RegI,145, L1->as_VMReg()->next());
110 reg_def R_L1 ( NS, NS, Op_RegI, 17, L1->as_VMReg());
111 reg_def R_L2H( NS, NS, Op_RegI,146, L2->as_VMReg()->next());
112 reg_def R_L2 ( NS, NS, Op_RegI, 18, L2->as_VMReg());
113 reg_def R_L3H( NS, NS, Op_RegI,147, L3->as_VMReg()->next());
114 reg_def R_L3 ( NS, NS, Op_RegI, 19, L3->as_VMReg());
115 reg_def R_L4H( NS, NS, Op_RegI,148, L4->as_VMReg()->next());
116 reg_def R_L4 ( NS, NS, Op_RegI, 20, L4->as_VMReg());
117 reg_def R_L5H( NS, NS, Op_RegI,149, L5->as_VMReg()->next());
118 reg_def R_L5 ( NS, NS, Op_RegI, 21, L5->as_VMReg());
119 reg_def R_L6H( NS, NS, Op_RegI,150, L6->as_VMReg()->next());
120 reg_def R_L6 ( NS, NS, Op_RegI, 22, L6->as_VMReg());
121 reg_def R_L7H( NS, NS, Op_RegI,151, L7->as_VMReg()->next());
122 reg_def R_L7 ( NS, NS, Op_RegI, 23, L7->as_VMReg());
123
124 // Input Registers 0-7
125 reg_def R_I0H( NS, NS, Op_RegI,152, I0->as_VMReg()->next());
126 reg_def R_I0 ( NS, NS, Op_RegI, 24, I0->as_VMReg());
127 reg_def R_I1H( NS, NS, Op_RegI,153, I1->as_VMReg()->next());
128 reg_def R_I1 ( NS, NS, Op_RegI, 25, I1->as_VMReg());
129 reg_def R_I2H( NS, NS, Op_RegI,154, I2->as_VMReg()->next());
130 reg_def R_I2 ( NS, NS, Op_RegI, 26, I2->as_VMReg());
131 reg_def R_I3H( NS, NS, Op_RegI,155, I3->as_VMReg()->next());
132 reg_def R_I3 ( NS, NS, Op_RegI, 27, I3->as_VMReg());
133 reg_def R_I4H( NS, NS, Op_RegI,156, I4->as_VMReg()->next());
134 reg_def R_I4 ( NS, NS, Op_RegI, 28, I4->as_VMReg());
135 reg_def R_I5H( NS, NS, Op_RegI,157, I5->as_VMReg()->next());
136 reg_def R_I5 ( NS, NS, Op_RegI, 29, I5->as_VMReg());
137 reg_def R_FPH( NS, NS, Op_RegI,158, FP->as_VMReg()->next());
138 reg_def R_FP ( NS, NS, Op_RegI, 30, FP->as_VMReg());
139 reg_def R_I7H( NS, NS, Op_RegI,159, I7->as_VMReg()->next());
140 reg_def R_I7 ( NS, NS, Op_RegI, 31, I7->as_VMReg());
141
142 // ----------------------------
143 // Float/Double Registers
144 // ----------------------------
145
146 // Float Registers
147 reg_def R_F0 ( SOC, SOC, Op_RegF, 0, F0->as_VMReg());
148 reg_def R_F1 ( SOC, SOC, Op_RegF, 1, F1->as_VMReg());
149 reg_def R_F2 ( SOC, SOC, Op_RegF, 2, F2->as_VMReg());
150 reg_def R_F3 ( SOC, SOC, Op_RegF, 3, F3->as_VMReg());
151 reg_def R_F4 ( SOC, SOC, Op_RegF, 4, F4->as_VMReg());
152 reg_def R_F5 ( SOC, SOC, Op_RegF, 5, F5->as_VMReg());
153 reg_def R_F6 ( SOC, SOC, Op_RegF, 6, F6->as_VMReg());
154 reg_def R_F7 ( SOC, SOC, Op_RegF, 7, F7->as_VMReg());
155 reg_def R_F8 ( SOC, SOC, Op_RegF, 8, F8->as_VMReg());
156 reg_def R_F9 ( SOC, SOC, Op_RegF, 9, F9->as_VMReg());
157 reg_def R_F10( SOC, SOC, Op_RegF, 10, F10->as_VMReg());
158 reg_def R_F11( SOC, SOC, Op_RegF, 11, F11->as_VMReg());
159 reg_def R_F12( SOC, SOC, Op_RegF, 12, F12->as_VMReg());
160 reg_def R_F13( SOC, SOC, Op_RegF, 13, F13->as_VMReg());
161 reg_def R_F14( SOC, SOC, Op_RegF, 14, F14->as_VMReg());
162 reg_def R_F15( SOC, SOC, Op_RegF, 15, F15->as_VMReg());
163 reg_def R_F16( SOC, SOC, Op_RegF, 16, F16->as_VMReg());
164 reg_def R_F17( SOC, SOC, Op_RegF, 17, F17->as_VMReg());
165 reg_def R_F18( SOC, SOC, Op_RegF, 18, F18->as_VMReg());
166 reg_def R_F19( SOC, SOC, Op_RegF, 19, F19->as_VMReg());
167 reg_def R_F20( SOC, SOC, Op_RegF, 20, F20->as_VMReg());
168 reg_def R_F21( SOC, SOC, Op_RegF, 21, F21->as_VMReg());
169 reg_def R_F22( SOC, SOC, Op_RegF, 22, F22->as_VMReg());
170 reg_def R_F23( SOC, SOC, Op_RegF, 23, F23->as_VMReg());
171 reg_def R_F24( SOC, SOC, Op_RegF, 24, F24->as_VMReg());
172 reg_def R_F25( SOC, SOC, Op_RegF, 25, F25->as_VMReg());
173 reg_def R_F26( SOC, SOC, Op_RegF, 26, F26->as_VMReg());
174 reg_def R_F27( SOC, SOC, Op_RegF, 27, F27->as_VMReg());
175 reg_def R_F28( SOC, SOC, Op_RegF, 28, F28->as_VMReg());
176 reg_def R_F29( SOC, SOC, Op_RegF, 29, F29->as_VMReg());
177 reg_def R_F30( SOC, SOC, Op_RegF, 30, F30->as_VMReg());
178 reg_def R_F31( SOC, SOC, Op_RegF, 31, F31->as_VMReg());
179
180 // Double Registers
181 // The rules of ADL require that double registers be defined in pairs.
182 // Each pair must be two 32-bit values, but not necessarily a pair of
183 // single float registers. In each pair, ADLC-assigned register numbers
184 // must be adjacent, with the lower number even. Finally, when the
185 // CPU stores such a register pair to memory, the word associated with
186 // the lower ADLC-assigned number must be stored to the lower address.
187
188 // These definitions specify the actual bit encodings of the sparc
189 // double fp register numbers. FloatRegisterImpl in register_sparc.hpp
190 // wants 0-63, so we have to convert every time we want to use fp regs
191 // with the macroassembler, using reg_to_DoubleFloatRegister_object().
192 // 255 is a flag meaning "don't go here".
193 // I believe we can't handle callee-save doubles D32 and up until
194 // the place in the sparc stack crawler that asserts on the 255 is
195 // fixed up.
196 reg_def R_D32x(SOC, SOC, Op_RegD,255, F32->as_VMReg());
197 reg_def R_D32 (SOC, SOC, Op_RegD, 1, F32->as_VMReg()->next());
198 reg_def R_D34x(SOC, SOC, Op_RegD,255, F34->as_VMReg());
199 reg_def R_D34 (SOC, SOC, Op_RegD, 3, F34->as_VMReg()->next());
200 reg_def R_D36x(SOC, SOC, Op_RegD,255, F36->as_VMReg());
201 reg_def R_D36 (SOC, SOC, Op_RegD, 5, F36->as_VMReg()->next());
202 reg_def R_D38x(SOC, SOC, Op_RegD,255, F38->as_VMReg());
203 reg_def R_D38 (SOC, SOC, Op_RegD, 7, F38->as_VMReg()->next());
204 reg_def R_D40x(SOC, SOC, Op_RegD,255, F40->as_VMReg());
205 reg_def R_D40 (SOC, SOC, Op_RegD, 9, F40->as_VMReg()->next());
206 reg_def R_D42x(SOC, SOC, Op_RegD,255, F42->as_VMReg());
207 reg_def R_D42 (SOC, SOC, Op_RegD, 11, F42->as_VMReg()->next());
208 reg_def R_D44x(SOC, SOC, Op_RegD,255, F44->as_VMReg());
209 reg_def R_D44 (SOC, SOC, Op_RegD, 13, F44->as_VMReg()->next());
210 reg_def R_D46x(SOC, SOC, Op_RegD,255, F46->as_VMReg());
211 reg_def R_D46 (SOC, SOC, Op_RegD, 15, F46->as_VMReg()->next());
212 reg_def R_D48x(SOC, SOC, Op_RegD,255, F48->as_VMReg());
213 reg_def R_D48 (SOC, SOC, Op_RegD, 17, F48->as_VMReg()->next());
214 reg_def R_D50x(SOC, SOC, Op_RegD,255, F50->as_VMReg());
215 reg_def R_D50 (SOC, SOC, Op_RegD, 19, F50->as_VMReg()->next());
216 reg_def R_D52x(SOC, SOC, Op_RegD,255, F52->as_VMReg());
217 reg_def R_D52 (SOC, SOC, Op_RegD, 21, F52->as_VMReg()->next());
218 reg_def R_D54x(SOC, SOC, Op_RegD,255, F54->as_VMReg());
219 reg_def R_D54 (SOC, SOC, Op_RegD, 23, F54->as_VMReg()->next());
220 reg_def R_D56x(SOC, SOC, Op_RegD,255, F56->as_VMReg());
221 reg_def R_D56 (SOC, SOC, Op_RegD, 25, F56->as_VMReg()->next());
222 reg_def R_D58x(SOC, SOC, Op_RegD,255, F58->as_VMReg());
223 reg_def R_D58 (SOC, SOC, Op_RegD, 27, F58->as_VMReg()->next());
224 reg_def R_D60x(SOC, SOC, Op_RegD,255, F60->as_VMReg());
225 reg_def R_D60 (SOC, SOC, Op_RegD, 29, F60->as_VMReg()->next());
226 reg_def R_D62x(SOC, SOC, Op_RegD,255, F62->as_VMReg());
227 reg_def R_D62 (SOC, SOC, Op_RegD, 31, F62->as_VMReg()->next());
228
229
230 // ----------------------------
231 // Special Registers
232 // Condition Codes Flag Registers
233 // I tried to break out ICC and XCC but it's not very pretty.
234 // Every Sparc instruction which defs/kills one also kills the other.
235 // Hence every compare instruction which defs one kind of flags ends
236 // up needing a kill of the other.
237 reg_def CCR (SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad());
238
239 reg_def FCC0(SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad());
240 reg_def FCC1(SOC, SOC, Op_RegFlags, 1, VMRegImpl::Bad());
241 reg_def FCC2(SOC, SOC, Op_RegFlags, 2, VMRegImpl::Bad());
242 reg_def FCC3(SOC, SOC, Op_RegFlags, 3, VMRegImpl::Bad());
243
244 // ----------------------------
245 // Specify the enum values for the registers. These enums are only used by the
246 // OptoReg "class". We can convert these enum values at will to VMReg when needed
247 // for visibility to the rest of the vm. The order of this enum influences the
248 // register allocator so having the freedom to set this order and not be stuck
249 // with the order that is natural for the rest of the vm is worth it.
250 alloc_class chunk0(
251 R_L0,R_L0H, R_L1,R_L1H, R_L2,R_L2H, R_L3,R_L3H, R_L4,R_L4H, R_L5,R_L5H, R_L6,R_L6H, R_L7,R_L7H,
252 R_G0,R_G0H, R_G1,R_G1H, R_G2,R_G2H, R_G3,R_G3H, R_G4,R_G4H, R_G5,R_G5H, R_G6,R_G6H, R_G7,R_G7H,
253 R_O7,R_O7H, R_SP,R_SPH, R_O0,R_O0H, R_O1,R_O1H, R_O2,R_O2H, R_O3,R_O3H, R_O4,R_O4H, R_O5,R_O5H,
254 R_I0,R_I0H, R_I1,R_I1H, R_I2,R_I2H, R_I3,R_I3H, R_I4,R_I4H, R_I5,R_I5H, R_FP,R_FPH, R_I7,R_I7H);
255
256 // Note that a register is not allocatable unless it is also mentioned
257 // in a widely-used reg_class below. Thus, R_G7 and R_G0 are outside i_reg.
258
259 alloc_class chunk1(
260 // The first registers listed here are those most likely to be used
261 // as temporaries. We move F0..F7 away from the front of the list,
262 // to reduce the likelihood of interferences with parameters and
263 // return values. Likewise, we avoid using F0/F1 for parameters,
264 // since they are used for return values.
265 // This FPU fine-tuning is worth about 1% on the SPEC geomean.
266 R_F8 ,R_F9 ,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
267 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,
268 R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,R_F30,R_F31,
269 R_F0 ,R_F1 ,R_F2 ,R_F3 ,R_F4 ,R_F5 ,R_F6 ,R_F7 , // used for arguments and return values
270 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,
271 R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x,
272 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,
273 R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x);
274
275 alloc_class chunk2(CCR, FCC0, FCC1, FCC2, FCC3);
276
277 //----------Architecture Description Register Classes--------------------------
278 // Several register classes are automatically defined based upon information in
279 // this architecture description.
280 // 1) reg_class inline_cache_reg ( as defined in frame section )
281 // 2) reg_class interpreter_method_oop_reg ( as defined in frame section )
282 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
283 //
284
285 // G0 is not included in integer class since it has special meaning.
286 reg_class g0_reg(R_G0);
287
288 // ----------------------------
289 // Integer Register Classes
290 // ----------------------------
291 // Exclusions from i_reg:
292 // R_G0: hardwired zero
293 // R_G2: reserved by HotSpot to the TLS register (invariant within Java)
294 // R_G6: reserved by Solaris ABI to tools
295 // R_G7: reserved by Solaris ABI to libthread
296 // R_O7: Used as a temp in many encodings
297 reg_class int_reg(R_G1,R_G3,R_G4,R_G5,R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
298
299 // Class for all integer registers, except the G registers. This is used for
300 // encodings which use G registers as temps. The regular inputs to such
301 // instructions use a "notemp_" prefix, as a hack to ensure that the allocator
302 // will not put an input into a temp register.
303 reg_class notemp_int_reg(R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
304
305 reg_class g1_regI(R_G1);
306 reg_class g3_regI(R_G3);
307 reg_class g4_regI(R_G4);
308 reg_class o0_regI(R_O0);
309 reg_class o7_regI(R_O7);
310
311 // ----------------------------
312 // Pointer Register Classes
313 // ----------------------------
314 #ifdef _LP64
315 // 64-bit build means 64-bit pointers means hi/lo pairs
316 reg_class ptr_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5,
317 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5,
318 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
319 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 );
320 // Lock encodings use G3 and G4 internally
321 reg_class lock_ptr_reg( R_G1H,R_G1, R_G5H,R_G5,
322 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5,
323 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
324 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 );
325 // Special class for storeP instructions, which can store SP or RPC to TLS.
326 // It is also used for memory addressing, allowing direct TLS addressing.
327 reg_class sp_ptr_reg( R_G1H,R_G1, R_G2H,R_G2, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5,
328 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, R_SPH,R_SP,
329 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
330 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5, R_FPH,R_FP );
331 // R_L7 is the lowest-priority callee-save (i.e., NS) register
332 // We use it to save R_G2 across calls out of Java.
333 reg_class l7_regP(R_L7H,R_L7);
334
335 // Other special pointer regs
336 reg_class g1_regP(R_G1H,R_G1);
337 reg_class g2_regP(R_G2H,R_G2);
338 reg_class g3_regP(R_G3H,R_G3);
339 reg_class g4_regP(R_G4H,R_G4);
340 reg_class g5_regP(R_G5H,R_G5);
341 reg_class i0_regP(R_I0H,R_I0);
342 reg_class o0_regP(R_O0H,R_O0);
343 reg_class o1_regP(R_O1H,R_O1);
344 reg_class o2_regP(R_O2H,R_O2);
345 reg_class o7_regP(R_O7H,R_O7);
346
347 #else // _LP64
348 // 32-bit build means 32-bit pointers means 1 register.
349 reg_class ptr_reg( R_G1, R_G3,R_G4,R_G5,
350 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,
351 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
352 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
353 // Lock encodings use G3 and G4 internally
354 reg_class lock_ptr_reg(R_G1, R_G5,
355 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,
356 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
357 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
358 // Special class for storeP instructions, which can store SP or RPC to TLS.
359 // It is also used for memory addressing, allowing direct TLS addressing.
360 reg_class sp_ptr_reg( R_G1,R_G2,R_G3,R_G4,R_G5,
361 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_SP,
362 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
363 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5,R_FP);
364 // R_L7 is the lowest-priority callee-save (i.e., NS) register
365 // We use it to save R_G2 across calls out of Java.
366 reg_class l7_regP(R_L7);
367
368 // Other special pointer regs
369 reg_class g1_regP(R_G1);
370 reg_class g2_regP(R_G2);
371 reg_class g3_regP(R_G3);
372 reg_class g4_regP(R_G4);
373 reg_class g5_regP(R_G5);
374 reg_class i0_regP(R_I0);
375 reg_class o0_regP(R_O0);
376 reg_class o1_regP(R_O1);
377 reg_class o2_regP(R_O2);
378 reg_class o7_regP(R_O7);
379 #endif // _LP64
380
381
382 // ----------------------------
383 // Long Register Classes
384 // ----------------------------
385 // Longs in 1 register. Aligned adjacent hi/lo pairs.
386 // Note: O7 is never in this class; it is sometimes used as an encoding temp.
387 reg_class long_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5
388 ,R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5
389 #ifdef _LP64
390 // 64-bit, longs in 1 register: use all 64-bit integer registers
391 // 32-bit, longs in 1 register: cannot use I's and L's. Restrict to O's and G's.
392 ,R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7
393 ,R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5
394 #endif // _LP64
395 );
396
397 reg_class g1_regL(R_G1H,R_G1);
398 reg_class g3_regL(R_G3H,R_G3);
399 reg_class o2_regL(R_O2H,R_O2);
400 reg_class o7_regL(R_O7H,R_O7);
401
402 // ----------------------------
403 // Special Class for Condition Code Flags Register
404 reg_class int_flags(CCR);
405 reg_class float_flags(FCC0,FCC1,FCC2,FCC3);
406 reg_class float_flag0(FCC0);
407
408
409 // ----------------------------
410 // Float Point Register Classes
411 // ----------------------------
412 // Skip F30/F31, they are reserved for mem-mem copies
413 reg_class sflt_reg(R_F0,R_F1,R_F2,R_F3,R_F4,R_F5,R_F6,R_F7,R_F8,R_F9,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29);
414
415 // Paired floating point registers--they show up in the same order as the floats,
416 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs.
417 reg_class dflt_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
418 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,
419 /* Use extra V9 double registers; this AD file does not support V8 */
420 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x,
421 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x
422 );
423
424 // Paired floating point registers--they show up in the same order as the floats,
425 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs.
426 // This class is usable for mis-aligned loads as happen in I2C adapters.
427 reg_class dflt_low_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
428 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,R_F30,R_F31 );
429 %}
430
431 //----------DEFINITION BLOCK---------------------------------------------------
432 // Define name --> value mappings to inform the ADLC of an integer valued name
433 // Current support includes integer values in the range [0, 0x7FFFFFFF]
434 // Format:
435 // int_def <name> ( <int_value>, <expression>);
436 // Generated Code in ad_<arch>.hpp
437 // #define <name> (<expression>)
438 // // value == <int_value>
439 // Generated code in ad_<arch>.cpp adlc_verification()
440 // assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>");
441 //
442 definitions %{
443 // The default cost (of an ALU instruction).
444 int_def DEFAULT_COST ( 100, 100);
445 int_def HUGE_COST (1000000, 1000000);
446
447 // Memory refs are twice as expensive as run-of-the-mill.
448 int_def MEMORY_REF_COST ( 200, DEFAULT_COST * 2);
449
450 // Branches are even more expensive.
451 int_def BRANCH_COST ( 300, DEFAULT_COST * 3);
452 int_def CALL_COST ( 300, DEFAULT_COST * 3);
453 %}
454
455
456 //----------SOURCE BLOCK-------------------------------------------------------
457 // This is a block of C++ code which provides values, functions, and
458 // definitions necessary in the rest of the architecture description
459 source_hpp %{
460 // Must be visible to the DFA in dfa_sparc.cpp
461 extern bool can_branch_register( Node *bol, Node *cmp );
462
463 // Macros to extract hi & lo halves from a long pair.
464 // G0 is not part of any long pair, so assert on that.
465 // Prevents accidentally using G1 instead of G0.
466 #define LONG_HI_REG(x) (x)
467 #define LONG_LO_REG(x) (x)
468
469 %}
470
471 source %{
472 #define __ _masm.
473
474 // tertiary op of a LoadP or StoreP encoding
475 #define REGP_OP true
476
477 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding);
478 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding);
479 static Register reg_to_register_object(int register_encoding);
480
481 // Used by the DFA in dfa_sparc.cpp.
482 // Check for being able to use a V9 branch-on-register. Requires a
483 // compare-vs-zero, equal/not-equal, of a value which was zero- or sign-
484 // extended. Doesn't work following an integer ADD, for example, because of
485 // overflow (-1 incremented yields 0 plus a carry in the high-order word). On
486 // 32-bit V9 systems, interrupts currently blow away the high-order 32 bits and
487 // replace them with zero, which could become sign-extension in a different OS
488 // release. There's no obvious reason why an interrupt will ever fill these
489 // bits with non-zero junk (the registers are reloaded with standard LD
490 // instructions which either zero-fill or sign-fill).
491 bool can_branch_register( Node *bol, Node *cmp ) {
492 if( !BranchOnRegister ) return false;
493 #ifdef _LP64
494 if( cmp->Opcode() == Op_CmpP )
495 return true; // No problems with pointer compares
496 #endif
497 if( cmp->Opcode() == Op_CmpL )
498 return true; // No problems with long compares
499
500 if( !SparcV9RegsHiBitsZero ) return false;
501 if( bol->as_Bool()->_test._test != BoolTest::ne &&
502 bol->as_Bool()->_test._test != BoolTest::eq )
503 return false;
504
505 // Check for comparing against a 'safe' value. Any operation which
506 // clears out the high word is safe. Thus, loads and certain shifts
507 // are safe, as are non-negative constants. Any operation which
508 // preserves zero bits in the high word is safe as long as each of its
509 // inputs are safe. Thus, phis and bitwise booleans are safe if their
510 // inputs are safe. At present, the only important case to recognize
511 // seems to be loads. Constants should fold away, and shifts &
512 // logicals can use the 'cc' forms.
513 Node *x = cmp->in(1);
514 if( x->is_Load() ) return true;
515 if( x->is_Phi() ) {
516 for( uint i = 1; i < x->req(); i++ )
517 if( !x->in(i)->is_Load() )
518 return false;
519 return true;
520 }
521 return false;
522 }
523
524 // ****************************************************************************
525
526 // REQUIRED FUNCTIONALITY
527
528 // !!!!! Special hack to get all type of calls to specify the byte offset
529 // from the start of the call to the point where the return address
530 // will point.
531 // The "return address" is the address of the call instruction, plus 8.
532
533 int MachCallStaticJavaNode::ret_addr_offset() {
534 return NativeCall::instruction_size; // call; delay slot
535 }
536
537 int MachCallDynamicJavaNode::ret_addr_offset() {
538 int vtable_index = this->_vtable_index;
539 if (vtable_index < 0) {
540 // must be invalid_vtable_index, not nonvirtual_vtable_index
541 assert(vtable_index == methodOopDesc::invalid_vtable_index, "correct sentinel value");
542 return (NativeMovConstReg::instruction_size +
543 NativeCall::instruction_size); // sethi; setlo; call; delay slot
544 } else {
545 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
546 int entry_offset = instanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size();
547 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes();
548 int klass_load_size;
549 if (UseCompressedOops) {
550 assert(Universe::heap() != NULL, "java heap should be initialized");
551 if (Universe::narrow_oop_base() == NULL)
552 klass_load_size = 2*BytesPerInstWord; // see MacroAssembler::load_klass()
553 else
554 klass_load_size = 3*BytesPerInstWord;
555 } else {
556 klass_load_size = 1*BytesPerInstWord;
557 }
558 if( Assembler::is_simm13(v_off) ) {
559 return klass_load_size +
560 (2*BytesPerInstWord + // ld_ptr, ld_ptr
561 NativeCall::instruction_size); // call; delay slot
562 } else {
563 return klass_load_size +
564 (4*BytesPerInstWord + // set_hi, set, ld_ptr, ld_ptr
565 NativeCall::instruction_size); // call; delay slot
566 }
567 }
568 }
569
570 int MachCallRuntimeNode::ret_addr_offset() {
571 #ifdef _LP64
572 return NativeFarCall::instruction_size; // farcall; delay slot
573 #else
574 return NativeCall::instruction_size; // call; delay slot
575 #endif
576 }
577
578 // Indicate if the safepoint node needs the polling page as an input.
579 // Since Sparc does not have absolute addressing, it does.
580 bool SafePointNode::needs_polling_address_input() {
581 return true;
582 }
583
584 // emit an interrupt that is caught by the debugger (for debugging compiler)
585 void emit_break(CodeBuffer &cbuf) {
586 MacroAssembler _masm(&cbuf);
587 __ breakpoint_trap();
588 }
589
590 #ifndef PRODUCT
591 void MachBreakpointNode::format( PhaseRegAlloc *, outputStream *st ) const {
592 st->print("TA");
593 }
594 #endif
595
596 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
597 emit_break(cbuf);
598 }
599
600 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {
601 return MachNode::size(ra_);
602 }
603
604 // Traceable jump
605 void emit_jmpl(CodeBuffer &cbuf, int jump_target) {
606 MacroAssembler _masm(&cbuf);
607 Register rdest = reg_to_register_object(jump_target);
608 __ JMP(rdest, 0);
609 __ delayed()->nop();
610 }
611
612 // Traceable jump and set exception pc
613 void emit_jmpl_set_exception_pc(CodeBuffer &cbuf, int jump_target) {
614 MacroAssembler _masm(&cbuf);
615 Register rdest = reg_to_register_object(jump_target);
616 __ JMP(rdest, 0);
617 __ delayed()->add(O7, frame::pc_return_offset, Oissuing_pc );
618 }
619
620 void emit_nop(CodeBuffer &cbuf) {
621 MacroAssembler _masm(&cbuf);
622 __ nop();
623 }
624
625 void emit_illtrap(CodeBuffer &cbuf) {
626 MacroAssembler _masm(&cbuf);
627 __ illtrap(0);
628 }
629
630
631 intptr_t get_offset_from_base(const MachNode* n, const TypePtr* atype, int disp32) {
632 assert(n->rule() != loadUB_rule, "");
633
634 intptr_t offset = 0;
635 const TypePtr *adr_type = TYPE_PTR_SENTINAL; // Check for base==RegI, disp==immP
636 const Node* addr = n->get_base_and_disp(offset, adr_type);
637 assert(adr_type == (const TypePtr*)-1, "VerifyOops: no support for sparc operands with base==RegI, disp==immP");
638 assert(addr != NULL && addr != (Node*)-1, "invalid addr");
639 assert(addr->bottom_type()->isa_oopptr() == atype, "");
640 atype = atype->add_offset(offset);
641 assert(disp32 == offset, "wrong disp32");
642 return atype->_offset;
643 }
644
645
646 intptr_t get_offset_from_base_2(const MachNode* n, const TypePtr* atype, int disp32) {
647 assert(n->rule() != loadUB_rule, "");
648
649 intptr_t offset = 0;
650 Node* addr = n->in(2);
651 assert(addr->bottom_type()->isa_oopptr() == atype, "");
652 if (addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP) {
653 Node* a = addr->in(2/*AddPNode::Address*/);
654 Node* o = addr->in(3/*AddPNode::Offset*/);
655 offset = o->is_Con() ? o->bottom_type()->is_intptr_t()->get_con() : Type::OffsetBot;
656 atype = a->bottom_type()->is_ptr()->add_offset(offset);
657 assert(atype->isa_oop_ptr(), "still an oop");
658 }
659 offset = atype->is_ptr()->_offset;
660 if (offset != Type::OffsetBot) offset += disp32;
661 return offset;
662 }
663
664 // Standard Sparc opcode form2 field breakdown
665 static inline void emit2_19(CodeBuffer &cbuf, int f30, int f29, int f25, int f22, int f20, int f19, int f0 ) {
666 f0 &= (1<<19)-1; // Mask displacement to 19 bits
667 int op = (f30 << 30) |
668 (f29 << 29) |
669 (f25 << 25) |
670 (f22 << 22) |
671 (f20 << 20) |
672 (f19 << 19) |
673 (f0 << 0);
674 *((int*)(cbuf.code_end())) = op;
675 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
676 }
677
678 // Standard Sparc opcode form2 field breakdown
679 static inline void emit2_22(CodeBuffer &cbuf, int f30, int f25, int f22, int f0 ) {
680 f0 >>= 10; // Drop 10 bits
681 f0 &= (1<<22)-1; // Mask displacement to 22 bits
682 int op = (f30 << 30) |
683 (f25 << 25) |
684 (f22 << 22) |
685 (f0 << 0);
686 *((int*)(cbuf.code_end())) = op;
687 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
688 }
689
690 // Standard Sparc opcode form3 field breakdown
691 static inline void emit3(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int f5, int f0 ) {
692 int op = (f30 << 30) |
693 (f25 << 25) |
694 (f19 << 19) |
695 (f14 << 14) |
696 (f5 << 5) |
697 (f0 << 0);
698 *((int*)(cbuf.code_end())) = op;
699 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
700 }
701
702 // Standard Sparc opcode form3 field breakdown
703 static inline void emit3_simm13(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm13 ) {
704 simm13 &= (1<<13)-1; // Mask to 13 bits
705 int op = (f30 << 30) |
706 (f25 << 25) |
707 (f19 << 19) |
708 (f14 << 14) |
709 (1 << 13) | // bit to indicate immediate-mode
710 (simm13<<0);
711 *((int*)(cbuf.code_end())) = op;
712 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
713 }
714
715 static inline void emit3_simm10(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm10 ) {
716 simm10 &= (1<<10)-1; // Mask to 10 bits
717 emit3_simm13(cbuf,f30,f25,f19,f14,simm10);
718 }
719
720 #ifdef ASSERT
721 // Helper function for VerifyOops in emit_form3_mem_reg
722 void verify_oops_warning(const MachNode *n, int ideal_op, int mem_op) {
723 warning("VerifyOops encountered unexpected instruction:");
724 n->dump(2);
725 warning("Instruction has ideal_Opcode==Op_%s and op_ld==Op_%s \n", NodeClassNames[ideal_op], NodeClassNames[mem_op]);
726 }
727 #endif
728
729
730 void emit_form3_mem_reg(CodeBuffer &cbuf, const MachNode* n, int primary, int tertiary,
731 int src1_enc, int disp32, int src2_enc, int dst_enc) {
732
733 #ifdef ASSERT
734 // The following code implements the +VerifyOops feature.
735 // It verifies oop values which are loaded into or stored out of
736 // the current method activation. +VerifyOops complements techniques
737 // like ScavengeALot, because it eagerly inspects oops in transit,
738 // as they enter or leave the stack, as opposed to ScavengeALot,
739 // which inspects oops "at rest", in the stack or heap, at safepoints.
740 // For this reason, +VerifyOops can sometimes detect bugs very close
741 // to their point of creation. It can also serve as a cross-check
742 // on the validity of oop maps, when used toegether with ScavengeALot.
743
744 // It would be good to verify oops at other points, especially
745 // when an oop is used as a base pointer for a load or store.
746 // This is presently difficult, because it is hard to know when
747 // a base address is biased or not. (If we had such information,
748 // it would be easy and useful to make a two-argument version of
749 // verify_oop which unbiases the base, and performs verification.)
750
751 assert((uint)tertiary == 0xFFFFFFFF || tertiary == REGP_OP, "valid tertiary");
752 bool is_verified_oop_base = false;
753 bool is_verified_oop_load = false;
754 bool is_verified_oop_store = false;
755 int tmp_enc = -1;
756 if (VerifyOops && src1_enc != R_SP_enc) {
757 // classify the op, mainly for an assert check
758 int st_op = 0, ld_op = 0;
759 switch (primary) {
760 case Assembler::stb_op3: st_op = Op_StoreB; break;
761 case Assembler::sth_op3: st_op = Op_StoreC; break;
762 case Assembler::stx_op3: // may become StoreP or stay StoreI or StoreD0
763 case Assembler::stw_op3: st_op = Op_StoreI; break;
764 case Assembler::std_op3: st_op = Op_StoreL; break;
765 case Assembler::stf_op3: st_op = Op_StoreF; break;
766 case Assembler::stdf_op3: st_op = Op_StoreD; break;
767
768 case Assembler::ldsb_op3: ld_op = Op_LoadB; break;
769 case Assembler::lduh_op3: ld_op = Op_LoadUS; break;
770 case Assembler::ldsh_op3: ld_op = Op_LoadS; break;
771 case Assembler::ldx_op3: // may become LoadP or stay LoadI
772 case Assembler::ldsw_op3: // may become LoadP or stay LoadI
773 case Assembler::lduw_op3: ld_op = Op_LoadI; break;
774 case Assembler::ldd_op3: ld_op = Op_LoadL; break;
775 case Assembler::ldf_op3: ld_op = Op_LoadF; break;
776 case Assembler::lddf_op3: ld_op = Op_LoadD; break;
777 case Assembler::ldub_op3: ld_op = Op_LoadB; break;
778 case Assembler::prefetch_op3: ld_op = Op_LoadI; break;
779
780 default: ShouldNotReachHere();
781 }
782 if (tertiary == REGP_OP) {
783 if (st_op == Op_StoreI) st_op = Op_StoreP;
784 else if (ld_op == Op_LoadI) ld_op = Op_LoadP;
785 else ShouldNotReachHere();
786 if (st_op) {
787 // a store
788 // inputs are (0:control, 1:memory, 2:address, 3:value)
789 Node* n2 = n->in(3);
790 if (n2 != NULL) {
791 const Type* t = n2->bottom_type();
792 is_verified_oop_store = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false;
793 }
794 } else {
795 // a load
796 const Type* t = n->bottom_type();
797 is_verified_oop_load = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false;
798 }
799 }
800
801 if (ld_op) {
802 // a Load
803 // inputs are (0:control, 1:memory, 2:address)
804 if (!(n->ideal_Opcode()==ld_op) && // Following are special cases
805 !(n->ideal_Opcode()==Op_LoadLLocked && ld_op==Op_LoadI) &&
806 !(n->ideal_Opcode()==Op_LoadPLocked && ld_op==Op_LoadP) &&
807 !(n->ideal_Opcode()==Op_LoadI && ld_op==Op_LoadF) &&
808 !(n->ideal_Opcode()==Op_LoadF && ld_op==Op_LoadI) &&
809 !(n->ideal_Opcode()==Op_LoadRange && ld_op==Op_LoadI) &&
810 !(n->ideal_Opcode()==Op_LoadKlass && ld_op==Op_LoadP) &&
811 !(n->ideal_Opcode()==Op_LoadL && ld_op==Op_LoadI) &&
812 !(n->ideal_Opcode()==Op_LoadL_unaligned && ld_op==Op_LoadI) &&
813 !(n->ideal_Opcode()==Op_LoadD_unaligned && ld_op==Op_LoadF) &&
814 !(n->ideal_Opcode()==Op_ConvI2F && ld_op==Op_LoadF) &&
815 !(n->ideal_Opcode()==Op_ConvI2D && ld_op==Op_LoadF) &&
816 !(n->ideal_Opcode()==Op_PrefetchRead && ld_op==Op_LoadI) &&
817 !(n->ideal_Opcode()==Op_PrefetchWrite && ld_op==Op_LoadI) &&
818 !(n->rule() == loadUB_rule)) {
819 verify_oops_warning(n, n->ideal_Opcode(), ld_op);
820 }
821 } else if (st_op) {
822 // a Store
823 // inputs are (0:control, 1:memory, 2:address, 3:value)
824 if (!(n->ideal_Opcode()==st_op) && // Following are special cases
825 !(n->ideal_Opcode()==Op_StoreCM && st_op==Op_StoreB) &&
826 !(n->ideal_Opcode()==Op_StoreI && st_op==Op_StoreF) &&
827 !(n->ideal_Opcode()==Op_StoreF && st_op==Op_StoreI) &&
828 !(n->ideal_Opcode()==Op_StoreL && st_op==Op_StoreI) &&
829 !(n->ideal_Opcode()==Op_StoreD && st_op==Op_StoreI && n->rule() == storeD0_rule)) {
830 verify_oops_warning(n, n->ideal_Opcode(), st_op);
831 }
832 }
833
834 if (src2_enc == R_G0_enc && n->rule() != loadUB_rule && n->ideal_Opcode() != Op_StoreCM ) {
835 Node* addr = n->in(2);
836 if (!(addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP)) {
837 const TypeOopPtr* atype = addr->bottom_type()->isa_instptr(); // %%% oopptr?
838 if (atype != NULL) {
839 intptr_t offset = get_offset_from_base(n, atype, disp32);
840 intptr_t offset_2 = get_offset_from_base_2(n, atype, disp32);
841 if (offset != offset_2) {
842 get_offset_from_base(n, atype, disp32);
843 get_offset_from_base_2(n, atype, disp32);
844 }
845 assert(offset == offset_2, "different offsets");
846 if (offset == disp32) {
847 // we now know that src1 is a true oop pointer
848 is_verified_oop_base = true;
849 if (ld_op && src1_enc == dst_enc && ld_op != Op_LoadF && ld_op != Op_LoadD) {
850 if( primary == Assembler::ldd_op3 ) {
851 is_verified_oop_base = false; // Cannot 'ldd' into O7
852 } else {
853 tmp_enc = dst_enc;
854 dst_enc = R_O7_enc; // Load into O7; preserve source oop
855 assert(src1_enc != dst_enc, "");
856 }
857 }
858 }
859 if (st_op && (( offset == oopDesc::klass_offset_in_bytes())
860 || offset == oopDesc::mark_offset_in_bytes())) {
861 // loading the mark should not be allowed either, but
862 // we don't check this since it conflicts with InlineObjectHash
863 // usage of LoadINode to get the mark. We could keep the
864 // check if we create a new LoadMarkNode
865 // but do not verify the object before its header is initialized
866 ShouldNotReachHere();
867 }
868 }
869 }
870 }
871 }
872 #endif
873
874 uint instr;
875 instr = (Assembler::ldst_op << 30)
876 | (dst_enc << 25)
877 | (primary << 19)
878 | (src1_enc << 14);
879
880 uint index = src2_enc;
881 int disp = disp32;
882
883 if (src1_enc == R_SP_enc || src1_enc == R_FP_enc)
884 disp += STACK_BIAS;
885
886 // We should have a compiler bailout here rather than a guarantee.
887 // Better yet would be some mechanism to handle variable-size matches correctly.
888 guarantee(Assembler::is_simm13(disp), "Do not match large constant offsets" );
889
890 if( disp == 0 ) {
891 // use reg-reg form
892 // bit 13 is already zero
893 instr |= index;
894 } else {
895 // use reg-imm form
896 instr |= 0x00002000; // set bit 13 to one
897 instr |= disp & 0x1FFF;
898 }
899
900 uint *code = (uint*)cbuf.code_end();
901 *code = instr;
902 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
903
904 #ifdef ASSERT
905 {
906 MacroAssembler _masm(&cbuf);
907 if (is_verified_oop_base) {
908 __ verify_oop(reg_to_register_object(src1_enc));
909 }
910 if (is_verified_oop_store) {
911 __ verify_oop(reg_to_register_object(dst_enc));
912 }
913 if (tmp_enc != -1) {
914 __ mov(O7, reg_to_register_object(tmp_enc));
915 }
916 if (is_verified_oop_load) {
917 __ verify_oop(reg_to_register_object(dst_enc));
918 }
919 }
920 #endif
921 }
922
923 void emit_form3_mem_reg_asi(CodeBuffer &cbuf, const MachNode* n, int primary, int tertiary,
924 int src1_enc, int disp32, int src2_enc, int dst_enc, int asi) {
925
926 uint instr;
927 instr = (Assembler::ldst_op << 30)
928 | (dst_enc << 25)
929 | (primary << 19)
930 | (src1_enc << 14);
931
932 int disp = disp32;
933 int index = src2_enc;
934
935 if (src1_enc == R_SP_enc || src1_enc == R_FP_enc)
936 disp += STACK_BIAS;
937
938 // We should have a compiler bailout here rather than a guarantee.
939 // Better yet would be some mechanism to handle variable-size matches correctly.
940 guarantee(Assembler::is_simm13(disp), "Do not match large constant offsets" );
941
942 if( disp != 0 ) {
943 // use reg-reg form
944 // set src2=R_O7 contains offset
945 index = R_O7_enc;
946 emit3_simm13( cbuf, Assembler::arith_op, index, Assembler::or_op3, 0, disp);
947 }
948 instr |= (asi << 5);
949 instr |= index;
950 uint *code = (uint*)cbuf.code_end();
951 *code = instr;
952 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
953 }
954
955 void emit_call_reloc(CodeBuffer &cbuf, intptr_t entry_point, relocInfo::relocType rtype, bool preserve_g2 = false, bool force_far_call = false) {
956 // The method which records debug information at every safepoint
957 // expects the call to be the first instruction in the snippet as
958 // it creates a PcDesc structure which tracks the offset of a call
959 // from the start of the codeBlob. This offset is computed as
960 // code_end() - code_begin() of the code which has been emitted
961 // so far.
962 // In this particular case we have skirted around the problem by
963 // putting the "mov" instruction in the delay slot but the problem
964 // may bite us again at some other point and a cleaner/generic
965 // solution using relocations would be needed.
966 MacroAssembler _masm(&cbuf);
967 __ set_inst_mark();
968
969 // We flush the current window just so that there is a valid stack copy
970 // the fact that the current window becomes active again instantly is
971 // not a problem there is nothing live in it.
972
973 #ifdef ASSERT
974 int startpos = __ offset();
975 #endif /* ASSERT */
976
977 #ifdef _LP64
978 // Calls to the runtime or native may not be reachable from compiled code,
979 // so we generate the far call sequence on 64 bit sparc.
980 // This code sequence is relocatable to any address, even on LP64.
981 if ( force_far_call ) {
982 __ relocate(rtype);
983 AddressLiteral dest(entry_point);
984 __ jumpl_to(dest, O7, O7);
985 }
986 else
987 #endif
988 {
989 __ call((address)entry_point, rtype);
990 }
991
992 if (preserve_g2) __ delayed()->mov(G2, L7);
993 else __ delayed()->nop();
994
995 if (preserve_g2) __ mov(L7, G2);
996
997 #ifdef ASSERT
998 if (preserve_g2 && (VerifyCompiledCode || VerifyOops)) {
999 #ifdef _LP64
1000 // Trash argument dump slots.
1001 __ set(0xb0b8ac0db0b8ac0d, G1);
1002 __ mov(G1, G5);
1003 __ stx(G1, SP, STACK_BIAS + 0x80);
1004 __ stx(G1, SP, STACK_BIAS + 0x88);
1005 __ stx(G1, SP, STACK_BIAS + 0x90);
1006 __ stx(G1, SP, STACK_BIAS + 0x98);
1007 __ stx(G1, SP, STACK_BIAS + 0xA0);
1008 __ stx(G1, SP, STACK_BIAS + 0xA8);
1009 #else // _LP64
1010 // this is also a native call, so smash the first 7 stack locations,
1011 // and the various registers
1012
1013 // Note: [SP+0x40] is sp[callee_aggregate_return_pointer_sp_offset],
1014 // while [SP+0x44..0x58] are the argument dump slots.
1015 __ set((intptr_t)0xbaadf00d, G1);
1016 __ mov(G1, G5);
1017 __ sllx(G1, 32, G1);
1018 __ or3(G1, G5, G1);
1019 __ mov(G1, G5);
1020 __ stx(G1, SP, 0x40);
1021 __ stx(G1, SP, 0x48);
1022 __ stx(G1, SP, 0x50);
1023 __ stw(G1, SP, 0x58); // Do not trash [SP+0x5C] which is a usable spill slot
1024 #endif // _LP64
1025 }
1026 #endif /*ASSERT*/
1027 }
1028
1029 //=============================================================================
1030 // REQUIRED FUNCTIONALITY for encoding
1031 void emit_lo(CodeBuffer &cbuf, int val) { }
1032 void emit_hi(CodeBuffer &cbuf, int val) { }
1033
1034
1035 //=============================================================================
1036
1037 #ifndef PRODUCT
1038 void MachPrologNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1039 Compile* C = ra_->C;
1040
1041 for (int i = 0; i < OptoPrologueNops; i++) {
1042 st->print_cr("NOP"); st->print("\t");
1043 }
1044
1045 if( VerifyThread ) {
1046 st->print_cr("Verify_Thread"); st->print("\t");
1047 }
1048
1049 size_t framesize = C->frame_slots() << LogBytesPerInt;
1050
1051 // Calls to C2R adapters often do not accept exceptional returns.
1052 // We require that their callers must bang for them. But be careful, because
1053 // some VM calls (such as call site linkage) can use several kilobytes of
1054 // stack. But the stack safety zone should account for that.
1055 // See bugs 4446381, 4468289, 4497237.
1056 if (C->need_stack_bang(framesize)) {
1057 st->print_cr("! stack bang"); st->print("\t");
1058 }
1059
1060 if (Assembler::is_simm13(-framesize)) {
1061 st->print ("SAVE R_SP,-%d,R_SP",framesize);
1062 } else {
1063 st->print_cr("SETHI R_SP,hi%%(-%d),R_G3",framesize); st->print("\t");
1064 st->print_cr("ADD R_G3,lo%%(-%d),R_G3",framesize); st->print("\t");
1065 st->print ("SAVE R_SP,R_G3,R_SP");
1066 }
1067
1068 }
1069 #endif
1070
1071 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1072 Compile* C = ra_->C;
1073 MacroAssembler _masm(&cbuf);
1074
1075 for (int i = 0; i < OptoPrologueNops; i++) {
1076 __ nop();
1077 }
1078
1079 __ verify_thread();
1080
1081 size_t framesize = C->frame_slots() << LogBytesPerInt;
1082 assert(framesize >= 16*wordSize, "must have room for reg. save area");
1083 assert(framesize%(2*wordSize) == 0, "must preserve 2*wordSize alignment");
1084
1085 // Calls to C2R adapters often do not accept exceptional returns.
1086 // We require that their callers must bang for them. But be careful, because
1087 // some VM calls (such as call site linkage) can use several kilobytes of
1088 // stack. But the stack safety zone should account for that.
1089 // See bugs 4446381, 4468289, 4497237.
1090 if (C->need_stack_bang(framesize)) {
1091 __ generate_stack_overflow_check(framesize);
1092 }
1093
1094 if (Assembler::is_simm13(-framesize)) {
1095 __ save(SP, -framesize, SP);
1096 } else {
1097 __ sethi(-framesize & ~0x3ff, G3);
1098 __ add(G3, -framesize & 0x3ff, G3);
1099 __ save(SP, G3, SP);
1100 }
1101 C->set_frame_complete( __ offset() );
1102 }
1103
1104 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
1105 return MachNode::size(ra_);
1106 }
1107
1108 int MachPrologNode::reloc() const {
1109 return 10; // a large enough number
1110 }
1111
1112 //=============================================================================
1113 #ifndef PRODUCT
1114 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1115 Compile* C = ra_->C;
1116
1117 if( do_polling() && ra_->C->is_method_compilation() ) {
1118 st->print("SETHI #PollAddr,L0\t! Load Polling address\n\t");
1119 #ifdef _LP64
1120 st->print("LDX [L0],G0\t!Poll for Safepointing\n\t");
1121 #else
1122 st->print("LDUW [L0],G0\t!Poll for Safepointing\n\t");
1123 #endif
1124 }
1125
1126 if( do_polling() )
1127 st->print("RET\n\t");
1128
1129 st->print("RESTORE");
1130 }
1131 #endif
1132
1133 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1134 MacroAssembler _masm(&cbuf);
1135 Compile* C = ra_->C;
1136
1137 __ verify_thread();
1138
1139 // If this does safepoint polling, then do it here
1140 if( do_polling() && ra_->C->is_method_compilation() ) {
1141 AddressLiteral polling_page(os::get_polling_page());
1142 __ sethi(polling_page, L0);
1143 __ relocate(relocInfo::poll_return_type);
1144 __ ld_ptr( L0, 0, G0 );
1145 }
1146
1147 // If this is a return, then stuff the restore in the delay slot
1148 if( do_polling() ) {
1149 __ ret();
1150 __ delayed()->restore();
1151 } else {
1152 __ restore();
1153 }
1154 }
1155
1156 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
1157 return MachNode::size(ra_);
1158 }
1159
1160 int MachEpilogNode::reloc() const {
1161 return 16; // a large enough number
1162 }
1163
1164 const Pipeline * MachEpilogNode::pipeline() const {
1165 return MachNode::pipeline_class();
1166 }
1167
1168 int MachEpilogNode::safepoint_offset() const {
1169 assert( do_polling(), "no return for this epilog node");
1170 return MacroAssembler::size_of_sethi(os::get_polling_page());
1171 }
1172
1173 //=============================================================================
1174
1175 // Figure out which register class each belongs in: rc_int, rc_float, rc_stack
1176 enum RC { rc_bad, rc_int, rc_float, rc_stack };
1177 static enum RC rc_class( OptoReg::Name reg ) {
1178 if( !OptoReg::is_valid(reg) ) return rc_bad;
1179 if (OptoReg::is_stack(reg)) return rc_stack;
1180 VMReg r = OptoReg::as_VMReg(reg);
1181 if (r->is_Register()) return rc_int;
1182 assert(r->is_FloatRegister(), "must be");
1183 return rc_float;
1184 }
1185
1186 static int impl_helper( const MachNode *mach, CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, bool is_load, int offset, int reg, int opcode, const char *op_str, int size, outputStream* st ) {
1187 if( cbuf ) {
1188 // Better yet would be some mechanism to handle variable-size matches correctly
1189 if (!Assembler::is_simm13(offset + STACK_BIAS)) {
1190 ra_->C->record_method_not_compilable("unable to handle large constant offsets");
1191 } else {
1192 emit_form3_mem_reg(*cbuf, mach, opcode, -1, R_SP_enc, offset, 0, Matcher::_regEncode[reg]);
1193 }
1194 }
1195 #ifndef PRODUCT
1196 else if( !do_size ) {
1197 if( size != 0 ) st->print("\n\t");
1198 if( is_load ) st->print("%s [R_SP + #%d],R_%s\t! spill",op_str,offset,OptoReg::regname(reg));
1199 else st->print("%s R_%s,[R_SP + #%d]\t! spill",op_str,OptoReg::regname(reg),offset);
1200 }
1201 #endif
1202 return size+4;
1203 }
1204
1205 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int op1, int op2, const char *op_str, int size, outputStream* st ) {
1206 if( cbuf ) emit3( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst], op1, 0, op2, Matcher::_regEncode[src] );
1207 #ifndef PRODUCT
1208 else if( !do_size ) {
1209 if( size != 0 ) st->print("\n\t");
1210 st->print("%s R_%s,R_%s\t! spill",op_str,OptoReg::regname(src),OptoReg::regname(dst));
1211 }
1212 #endif
1213 return size+4;
1214 }
1215
1216 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf,
1217 PhaseRegAlloc *ra_,
1218 bool do_size,
1219 outputStream* st ) const {
1220 // Get registers to move
1221 OptoReg::Name src_second = ra_->get_reg_second(in(1));
1222 OptoReg::Name src_first = ra_->get_reg_first(in(1));
1223 OptoReg::Name dst_second = ra_->get_reg_second(this );
1224 OptoReg::Name dst_first = ra_->get_reg_first(this );
1225
1226 enum RC src_second_rc = rc_class(src_second);
1227 enum RC src_first_rc = rc_class(src_first);
1228 enum RC dst_second_rc = rc_class(dst_second);
1229 enum RC dst_first_rc = rc_class(dst_first);
1230
1231 assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" );
1232
1233 // Generate spill code!
1234 int size = 0;
1235
1236 if( src_first == dst_first && src_second == dst_second )
1237 return size; // Self copy, no move
1238
1239 // --------------------------------------
1240 // Check for mem-mem move. Load into unused float registers and fall into
1241 // the float-store case.
1242 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
1243 int offset = ra_->reg2offset(src_first);
1244 // Further check for aligned-adjacent pair, so we can use a double load
1245 if( (src_first&1)==0 && src_first+1 == src_second ) {
1246 src_second = OptoReg::Name(R_F31_num);
1247 src_second_rc = rc_float;
1248 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::lddf_op3,"LDDF",size, st);
1249 } else {
1250 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::ldf_op3 ,"LDF ",size, st);
1251 }
1252 src_first = OptoReg::Name(R_F30_num);
1253 src_first_rc = rc_float;
1254 }
1255
1256 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) {
1257 int offset = ra_->reg2offset(src_second);
1258 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F31_num,Assembler::ldf_op3,"LDF ",size, st);
1259 src_second = OptoReg::Name(R_F31_num);
1260 src_second_rc = rc_float;
1261 }
1262
1263 // --------------------------------------
1264 // Check for float->int copy; requires a trip through memory
1265 if( src_first_rc == rc_float && dst_first_rc == rc_int ) {
1266 int offset = frame::register_save_words*wordSize;
1267 if( cbuf ) {
1268 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::sub_op3, R_SP_enc, 16 );
1269 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
1270 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
1271 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::add_op3, R_SP_enc, 16 );
1272 }
1273 #ifndef PRODUCT
1274 else if( !do_size ) {
1275 if( size != 0 ) st->print("\n\t");
1276 st->print( "SUB R_SP,16,R_SP\n");
1277 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
1278 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
1279 st->print("\tADD R_SP,16,R_SP\n");
1280 }
1281 #endif
1282 size += 16;
1283 }
1284
1285 // --------------------------------------
1286 // In the 32-bit 1-reg-longs build ONLY, I see mis-aligned long destinations.
1287 // In such cases, I have to do the big-endian swap. For aligned targets, the
1288 // hardware does the flop for me. Doubles are always aligned, so no problem
1289 // there. Misaligned sources only come from native-long-returns (handled
1290 // special below).
1291 #ifndef _LP64
1292 if( src_first_rc == rc_int && // source is already big-endian
1293 src_second_rc != rc_bad && // 64-bit move
1294 ((dst_first&1)!=0 || dst_second != dst_first+1) ) { // misaligned dst
1295 assert( (src_first&1)==0 && src_second == src_first+1, "source must be aligned" );
1296 // Do the big-endian flop.
1297 OptoReg::Name tmp = dst_first ; dst_first = dst_second ; dst_second = tmp ;
1298 enum RC tmp_rc = dst_first_rc; dst_first_rc = dst_second_rc; dst_second_rc = tmp_rc;
1299 }
1300 #endif
1301
1302 // --------------------------------------
1303 // Check for integer reg-reg copy
1304 if( src_first_rc == rc_int && dst_first_rc == rc_int ) {
1305 #ifndef _LP64
1306 if( src_first == R_O0_num && src_second == R_O1_num ) { // Check for the evil O0/O1 native long-return case
1307 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value
1308 // as stored in memory. On a big-endian machine like SPARC, this means that the _second
1309 // operand contains the least significant word of the 64-bit value and vice versa.
1310 OptoReg::Name tmp = OptoReg::Name(R_O7_num);
1311 assert( (dst_first&1)==0 && dst_second == dst_first+1, "return a native O0/O1 long to an aligned-adjacent 64-bit reg" );
1312 // Shift O0 left in-place, zero-extend O1, then OR them into the dst
1313 if( cbuf ) {
1314 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tmp], Assembler::sllx_op3, Matcher::_regEncode[src_first], 0x1020 );
1315 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[src_second], Assembler::srl_op3, Matcher::_regEncode[src_second], 0x0000 );
1316 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler:: or_op3, Matcher::_regEncode[tmp], 0, Matcher::_regEncode[src_second] );
1317 #ifndef PRODUCT
1318 } else if( !do_size ) {
1319 if( size != 0 ) st->print("\n\t");
1320 st->print("SLLX R_%s,32,R_%s\t! Move O0-first to O7-high\n\t", OptoReg::regname(src_first), OptoReg::regname(tmp));
1321 st->print("SRL R_%s, 0,R_%s\t! Zero-extend O1\n\t", OptoReg::regname(src_second), OptoReg::regname(src_second));
1322 st->print("OR R_%s,R_%s,R_%s\t! spill",OptoReg::regname(tmp), OptoReg::regname(src_second), OptoReg::regname(dst_first));
1323 #endif
1324 }
1325 return size+12;
1326 }
1327 else if( dst_first == R_I0_num && dst_second == R_I1_num ) {
1328 // returning a long value in I0/I1
1329 // a SpillCopy must be able to target a return instruction's reg_class
1330 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value
1331 // as stored in memory. On a big-endian machine like SPARC, this means that the _second
1332 // operand contains the least significant word of the 64-bit value and vice versa.
1333 OptoReg::Name tdest = dst_first;
1334
1335 if (src_first == dst_first) {
1336 tdest = OptoReg::Name(R_O7_num);
1337 size += 4;
1338 }
1339
1340 if( cbuf ) {
1341 assert( (src_first&1) == 0 && (src_first+1) == src_second, "return value was in an aligned-adjacent 64-bit reg");
1342 // Shift value in upper 32-bits of src to lower 32-bits of I0; move lower 32-bits to I1
1343 // ShrL_reg_imm6
1344 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tdest], Assembler::srlx_op3, Matcher::_regEncode[src_second], 32 | 0x1000 );
1345 // ShrR_reg_imm6 src, 0, dst
1346 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srl_op3, Matcher::_regEncode[src_first], 0x0000 );
1347 if (tdest != dst_first) {
1348 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler::or_op3, 0/*G0*/, 0/*op2*/, Matcher::_regEncode[tdest] );
1349 }
1350 }
1351 #ifndef PRODUCT
1352 else if( !do_size ) {
1353 if( size != 0 ) st->print("\n\t"); // %%%%% !!!!!
1354 st->print("SRLX R_%s,32,R_%s\t! Extract MSW\n\t",OptoReg::regname(src_second),OptoReg::regname(tdest));
1355 st->print("SRL R_%s, 0,R_%s\t! Extract LSW\n\t",OptoReg::regname(src_first),OptoReg::regname(dst_second));
1356 if (tdest != dst_first) {
1357 st->print("MOV R_%s,R_%s\t! spill\n\t", OptoReg::regname(tdest), OptoReg::regname(dst_first));
1358 }
1359 }
1360 #endif // PRODUCT
1361 return size+8;
1362 }
1363 #endif // !_LP64
1364 // Else normal reg-reg copy
1365 assert( src_second != dst_first, "smashed second before evacuating it" );
1366 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::or_op3,0,"MOV ",size, st);
1367 assert( (src_first&1) == 0 && (dst_first&1) == 0, "never move second-halves of int registers" );
1368 // This moves an aligned adjacent pair.
1369 // See if we are done.
1370 if( src_first+1 == src_second && dst_first+1 == dst_second )
1371 return size;
1372 }
1373
1374 // Check for integer store
1375 if( src_first_rc == rc_int && dst_first_rc == rc_stack ) {
1376 int offset = ra_->reg2offset(dst_first);
1377 // Further check for aligned-adjacent pair, so we can use a double store
1378 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1379 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stx_op3,"STX ",size, st);
1380 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stw_op3,"STW ",size, st);
1381 }
1382
1383 // Check for integer load
1384 if( dst_first_rc == rc_int && src_first_rc == rc_stack ) {
1385 int offset = ra_->reg2offset(src_first);
1386 // Further check for aligned-adjacent pair, so we can use a double load
1387 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1388 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldx_op3 ,"LDX ",size, st);
1389 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
1390 }
1391
1392 // Check for float reg-reg copy
1393 if( src_first_rc == rc_float && dst_first_rc == rc_float ) {
1394 // Further check for aligned-adjacent pair, so we can use a double move
1395 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1396 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovd_opf,"FMOVD",size, st);
1397 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovs_opf,"FMOVS",size, st);
1398 }
1399
1400 // Check for float store
1401 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) {
1402 int offset = ra_->reg2offset(dst_first);
1403 // Further check for aligned-adjacent pair, so we can use a double store
1404 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1405 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stdf_op3,"STDF",size, st);
1406 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
1407 }
1408
1409 // Check for float load
1410 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) {
1411 int offset = ra_->reg2offset(src_first);
1412 // Further check for aligned-adjacent pair, so we can use a double load
1413 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1414 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lddf_op3,"LDDF",size, st);
1415 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldf_op3 ,"LDF ",size, st);
1416 }
1417
1418 // --------------------------------------------------------------------
1419 // Check for hi bits still needing moving. Only happens for misaligned
1420 // arguments to native calls.
1421 if( src_second == dst_second )
1422 return size; // Self copy; no move
1423 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" );
1424
1425 #ifndef _LP64
1426 // In the LP64 build, all registers can be moved as aligned/adjacent
1427 // pairs, so there's never any need to move the high bits separately.
1428 // The 32-bit builds have to deal with the 32-bit ABI which can force
1429 // all sorts of silly alignment problems.
1430
1431 // Check for integer reg-reg copy. Hi bits are stuck up in the top
1432 // 32-bits of a 64-bit register, but are needed in low bits of another
1433 // register (else it's a hi-bits-to-hi-bits copy which should have
1434 // happened already as part of a 64-bit move)
1435 if( src_second_rc == rc_int && dst_second_rc == rc_int ) {
1436 assert( (src_second&1)==1, "its the evil O0/O1 native return case" );
1437 assert( (dst_second&1)==0, "should have moved with 1 64-bit move" );
1438 // Shift src_second down to dst_second's low bits.
1439 if( cbuf ) {
1440 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 );
1441 #ifndef PRODUCT
1442 } else if( !do_size ) {
1443 if( size != 0 ) st->print("\n\t");
1444 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(dst_second));
1445 #endif
1446 }
1447 return size+4;
1448 }
1449
1450 // Check for high word integer store. Must down-shift the hi bits
1451 // into a temp register, then fall into the case of storing int bits.
1452 if( src_second_rc == rc_int && dst_second_rc == rc_stack && (src_second&1)==1 ) {
1453 // Shift src_second down to dst_second's low bits.
1454 if( cbuf ) {
1455 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[R_O7_num], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 );
1456 #ifndef PRODUCT
1457 } else if( !do_size ) {
1458 if( size != 0 ) st->print("\n\t");
1459 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(R_O7_num));
1460 #endif
1461 }
1462 size+=4;
1463 src_second = OptoReg::Name(R_O7_num); // Not R_O7H_num!
1464 }
1465
1466 // Check for high word integer load
1467 if( dst_second_rc == rc_int && src_second_rc == rc_stack )
1468 return impl_helper(this,cbuf,ra_,do_size,true ,ra_->reg2offset(src_second),dst_second,Assembler::lduw_op3,"LDUW",size, st);
1469
1470 // Check for high word integer store
1471 if( src_second_rc == rc_int && dst_second_rc == rc_stack )
1472 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stw_op3 ,"STW ",size, st);
1473
1474 // Check for high word float store
1475 if( src_second_rc == rc_float && dst_second_rc == rc_stack )
1476 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stf_op3 ,"STF ",size, st);
1477
1478 #endif // !_LP64
1479
1480 Unimplemented();
1481 }
1482
1483 #ifndef PRODUCT
1484 void MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1485 implementation( NULL, ra_, false, st );
1486 }
1487 #endif
1488
1489 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1490 implementation( &cbuf, ra_, false, NULL );
1491 }
1492
1493 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1494 return implementation( NULL, ra_, true, NULL );
1495 }
1496
1497 //=============================================================================
1498 #ifndef PRODUCT
1499 void MachNopNode::format( PhaseRegAlloc *, outputStream *st ) const {
1500 st->print("NOP \t# %d bytes pad for loops and calls", 4 * _count);
1501 }
1502 #endif
1503
1504 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc * ) const {
1505 MacroAssembler _masm(&cbuf);
1506 for(int i = 0; i < _count; i += 1) {
1507 __ nop();
1508 }
1509 }
1510
1511 uint MachNopNode::size(PhaseRegAlloc *ra_) const {
1512 return 4 * _count;
1513 }
1514
1515
1516 //=============================================================================
1517 #ifndef PRODUCT
1518 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1519 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1520 int reg = ra_->get_reg_first(this);
1521 st->print("LEA [R_SP+#%d+BIAS],%s",offset,Matcher::regName[reg]);
1522 }
1523 #endif
1524
1525 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1526 MacroAssembler _masm(&cbuf);
1527 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()) + STACK_BIAS;
1528 int reg = ra_->get_encode(this);
1529
1530 if (Assembler::is_simm13(offset)) {
1531 __ add(SP, offset, reg_to_register_object(reg));
1532 } else {
1533 __ set(offset, O7);
1534 __ add(SP, O7, reg_to_register_object(reg));
1535 }
1536 }
1537
1538 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1539 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_)
1540 assert(ra_ == ra_->C->regalloc(), "sanity");
1541 return ra_->C->scratch_emit_size(this);
1542 }
1543
1544 //=============================================================================
1545
1546 // emit call stub, compiled java to interpretor
1547 void emit_java_to_interp(CodeBuffer &cbuf ) {
1548
1549 // Stub is fixed up when the corresponding call is converted from calling
1550 // compiled code to calling interpreted code.
1551 // set (empty), G5
1552 // jmp -1
1553
1554 address mark = cbuf.inst_mark(); // get mark within main instrs section
1555
1556 MacroAssembler _masm(&cbuf);
1557
1558 address base =
1559 __ start_a_stub(Compile::MAX_stubs_size);
1560 if (base == NULL) return; // CodeBuffer::expand failed
1561
1562 // static stub relocation stores the instruction address of the call
1563 __ relocate(static_stub_Relocation::spec(mark));
1564
1565 __ set_oop(NULL, reg_to_register_object(Matcher::inline_cache_reg_encode()));
1566
1567 __ set_inst_mark();
1568 AddressLiteral addrlit(-1);
1569 __ JUMP(addrlit, G3, 0);
1570
1571 __ delayed()->nop();
1572
1573 // Update current stubs pointer and restore code_end.
1574 __ end_a_stub();
1575 }
1576
1577 // size of call stub, compiled java to interpretor
1578 uint size_java_to_interp() {
1579 // This doesn't need to be accurate but it must be larger or equal to
1580 // the real size of the stub.
1581 return (NativeMovConstReg::instruction_size + // sethi/setlo;
1582 NativeJump::instruction_size + // sethi; jmp; nop
1583 (TraceJumps ? 20 * BytesPerInstWord : 0) );
1584 }
1585 // relocation entries for call stub, compiled java to interpretor
1586 uint reloc_java_to_interp() {
1587 return 10; // 4 in emit_java_to_interp + 1 in Java_Static_Call
1588 }
1589
1590
1591 //=============================================================================
1592 #ifndef PRODUCT
1593 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1594 st->print_cr("\nUEP:");
1595 #ifdef _LP64
1596 if (UseCompressedOops) {
1597 assert(Universe::heap() != NULL, "java heap should be initialized");
1598 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check - compressed klass");
1599 st->print_cr("\tSLL R_G5,3,R_G5");
1600 if (Universe::narrow_oop_base() != NULL)
1601 st->print_cr("\tADD R_G5,R_G6_heap_base,R_G5");
1602 } else {
1603 st->print_cr("\tLDX [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check");
1604 }
1605 st->print_cr("\tCMP R_G5,R_G3" );
1606 st->print ("\tTne xcc,R_G0+ST_RESERVED_FOR_USER_0+2");
1607 #else // _LP64
1608 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check");
1609 st->print_cr("\tCMP R_G5,R_G3" );
1610 st->print ("\tTne icc,R_G0+ST_RESERVED_FOR_USER_0+2");
1611 #endif // _LP64
1612 }
1613 #endif
1614
1615 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1616 MacroAssembler _masm(&cbuf);
1617 Label L;
1618 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
1619 Register temp_reg = G3;
1620 assert( G5_ic_reg != temp_reg, "conflicting registers" );
1621
1622 // Load klass from receiver
1623 __ load_klass(O0, temp_reg);
1624 // Compare against expected klass
1625 __ cmp(temp_reg, G5_ic_reg);
1626 // Branch to miss code, checks xcc or icc depending
1627 __ trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2);
1628 }
1629
1630 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
1631 return MachNode::size(ra_);
1632 }
1633
1634
1635 //=============================================================================
1636
1637 uint size_exception_handler() {
1638 if (TraceJumps) {
1639 return (400); // just a guess
1640 }
1641 return ( NativeJump::instruction_size ); // sethi;jmp;nop
1642 }
1643
1644 uint size_deopt_handler() {
1645 if (TraceJumps) {
1646 return (400); // just a guess
1647 }
1648 return ( 4+ NativeJump::instruction_size ); // save;sethi;jmp;restore
1649 }
1650
1651 // Emit exception handler code.
1652 int emit_exception_handler(CodeBuffer& cbuf) {
1653 Register temp_reg = G3;
1654 AddressLiteral exception_blob(OptoRuntime::exception_blob()->instructions_begin());
1655 MacroAssembler _masm(&cbuf);
1656
1657 address base =
1658 __ start_a_stub(size_exception_handler());
1659 if (base == NULL) return 0; // CodeBuffer::expand failed
1660
1661 int offset = __ offset();
1662
1663 __ JUMP(exception_blob, temp_reg, 0); // sethi;jmp
1664 __ delayed()->nop();
1665
1666 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
1667
1668 __ end_a_stub();
1669
1670 return offset;
1671 }
1672
1673 int emit_deopt_handler(CodeBuffer& cbuf) {
1674 // Can't use any of the current frame's registers as we may have deopted
1675 // at a poll and everything (including G3) can be live.
1676 Register temp_reg = L0;
1677 AddressLiteral deopt_blob(SharedRuntime::deopt_blob()->unpack());
1678 MacroAssembler _masm(&cbuf);
1679
1680 address base =
1681 __ start_a_stub(size_deopt_handler());
1682 if (base == NULL) return 0; // CodeBuffer::expand failed
1683
1684 int offset = __ offset();
1685 __ save_frame(0);
1686 __ JUMP(deopt_blob, temp_reg, 0); // sethi;jmp
1687 __ delayed()->restore();
1688
1689 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
1690
1691 __ end_a_stub();
1692 return offset;
1693
1694 }
1695
1696 // Given a register encoding, produce a Integer Register object
1697 static Register reg_to_register_object(int register_encoding) {
1698 assert(L5->encoding() == R_L5_enc && G1->encoding() == R_G1_enc, "right coding");
1699 return as_Register(register_encoding);
1700 }
1701
1702 // Given a register encoding, produce a single-precision Float Register object
1703 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding) {
1704 assert(F5->encoding(FloatRegisterImpl::S) == R_F5_enc && F12->encoding(FloatRegisterImpl::S) == R_F12_enc, "right coding");
1705 return as_SingleFloatRegister(register_encoding);
1706 }
1707
1708 // Given a register encoding, produce a double-precision Float Register object
1709 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding) {
1710 assert(F4->encoding(FloatRegisterImpl::D) == R_F4_enc, "right coding");
1711 assert(F32->encoding(FloatRegisterImpl::D) == R_D32_enc, "right coding");
1712 return as_DoubleFloatRegister(register_encoding);
1713 }
1714
1715 int Matcher::regnum_to_fpu_offset(int regnum) {
1716 return regnum - 32; // The FP registers are in the second chunk
1717 }
1718
1719 #ifdef ASSERT
1720 address last_rethrow = NULL; // debugging aid for Rethrow encoding
1721 #endif
1722
1723 // Vector width in bytes
1724 const uint Matcher::vector_width_in_bytes(void) {
1725 return 8;
1726 }
1727
1728 // Vector ideal reg
1729 const uint Matcher::vector_ideal_reg(void) {
1730 return Op_RegD;
1731 }
1732
1733 // USII supports fxtof through the whole range of number, USIII doesn't
1734 const bool Matcher::convL2FSupported(void) {
1735 return VM_Version::has_fast_fxtof();
1736 }
1737
1738 // Is this branch offset short enough that a short branch can be used?
1739 //
1740 // NOTE: If the platform does not provide any short branch variants, then
1741 // this method should return false for offset 0.
1742 bool Matcher::is_short_branch_offset(int rule, int offset) {
1743 return false;
1744 }
1745
1746 const bool Matcher::isSimpleConstant64(jlong value) {
1747 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1748 // Depends on optimizations in MacroAssembler::setx.
1749 int hi = (int)(value >> 32);
1750 int lo = (int)(value & ~0);
1751 return (hi == 0) || (hi == -1) || (lo == 0);
1752 }
1753
1754 // No scaling for the parameter the ClearArray node.
1755 const bool Matcher::init_array_count_is_in_bytes = true;
1756
1757 // Threshold size for cleararray.
1758 const int Matcher::init_array_short_size = 8 * BytesPerLong;
1759
1760 // Should the Matcher clone shifts on addressing modes, expecting them to
1761 // be subsumed into complex addressing expressions or compute them into
1762 // registers? True for Intel but false for most RISCs
1763 const bool Matcher::clone_shift_expressions = false;
1764
1765 // Is it better to copy float constants, or load them directly from memory?
1766 // Intel can load a float constant from a direct address, requiring no
1767 // extra registers. Most RISCs will have to materialize an address into a
1768 // register first, so they would do better to copy the constant from stack.
1769 const bool Matcher::rematerialize_float_constants = false;
1770
1771 // If CPU can load and store mis-aligned doubles directly then no fixup is
1772 // needed. Else we split the double into 2 integer pieces and move it
1773 // piece-by-piece. Only happens when passing doubles into C code as the
1774 // Java calling convention forces doubles to be aligned.
1775 #ifdef _LP64
1776 const bool Matcher::misaligned_doubles_ok = true;
1777 #else
1778 const bool Matcher::misaligned_doubles_ok = false;
1779 #endif
1780
1781 // No-op on SPARC.
1782 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
1783 }
1784
1785 // Advertise here if the CPU requires explicit rounding operations
1786 // to implement the UseStrictFP mode.
1787 const bool Matcher::strict_fp_requires_explicit_rounding = false;
1788
1789 // Do floats take an entire double register or just half?
1790 const bool Matcher::float_in_double = false;
1791
1792 // Do ints take an entire long register or just half?
1793 // Note that we if-def off of _LP64.
1794 // The relevant question is how the int is callee-saved. In _LP64
1795 // the whole long is written but de-opt'ing will have to extract
1796 // the relevant 32 bits, in not-_LP64 only the low 32 bits is written.
1797 #ifdef _LP64
1798 const bool Matcher::int_in_long = true;
1799 #else
1800 const bool Matcher::int_in_long = false;
1801 #endif
1802
1803 // Return whether or not this register is ever used as an argument. This
1804 // function is used on startup to build the trampoline stubs in generateOptoStub.
1805 // Registers not mentioned will be killed by the VM call in the trampoline, and
1806 // arguments in those registers not be available to the callee.
1807 bool Matcher::can_be_java_arg( int reg ) {
1808 // Standard sparc 6 args in registers
1809 if( reg == R_I0_num ||
1810 reg == R_I1_num ||
1811 reg == R_I2_num ||
1812 reg == R_I3_num ||
1813 reg == R_I4_num ||
1814 reg == R_I5_num ) return true;
1815 #ifdef _LP64
1816 // 64-bit builds can pass 64-bit pointers and longs in
1817 // the high I registers
1818 if( reg == R_I0H_num ||
1819 reg == R_I1H_num ||
1820 reg == R_I2H_num ||
1821 reg == R_I3H_num ||
1822 reg == R_I4H_num ||
1823 reg == R_I5H_num ) return true;
1824
1825 if ((UseCompressedOops) && (reg == R_G6_num || reg == R_G6H_num)) {
1826 return true;
1827 }
1828
1829 #else
1830 // 32-bit builds with longs-in-one-entry pass longs in G1 & G4.
1831 // Longs cannot be passed in O regs, because O regs become I regs
1832 // after a 'save' and I regs get their high bits chopped off on
1833 // interrupt.
1834 if( reg == R_G1H_num || reg == R_G1_num ) return true;
1835 if( reg == R_G4H_num || reg == R_G4_num ) return true;
1836 #endif
1837 // A few float args in registers
1838 if( reg >= R_F0_num && reg <= R_F7_num ) return true;
1839
1840 return false;
1841 }
1842
1843 bool Matcher::is_spillable_arg( int reg ) {
1844 return can_be_java_arg(reg);
1845 }
1846
1847 // Register for DIVI projection of divmodI
1848 RegMask Matcher::divI_proj_mask() {
1849 ShouldNotReachHere();
1850 return RegMask();
1851 }
1852
1853 // Register for MODI projection of divmodI
1854 RegMask Matcher::modI_proj_mask() {
1855 ShouldNotReachHere();
1856 return RegMask();
1857 }
1858
1859 // Register for DIVL projection of divmodL
1860 RegMask Matcher::divL_proj_mask() {
1861 ShouldNotReachHere();
1862 return RegMask();
1863 }
1864
1865 // Register for MODL projection of divmodL
1866 RegMask Matcher::modL_proj_mask() {
1867 ShouldNotReachHere();
1868 return RegMask();
1869 }
1870
1871 %}
1872
1873
1874 // The intptr_t operand types, defined by textual substitution.
1875 // (Cf. opto/type.hpp. This lets us avoid many, many other ifdefs.)
1876 #ifdef _LP64
1877 #define immX immL
1878 #define immX13 immL13
1879 #define iRegX iRegL
1880 #define g1RegX g1RegL
1881 #else
1882 #define immX immI
1883 #define immX13 immI13
1884 #define iRegX iRegI
1885 #define g1RegX g1RegI
1886 #endif
1887
1888 //----------ENCODING BLOCK-----------------------------------------------------
1889 // This block specifies the encoding classes used by the compiler to output
1890 // byte streams. Encoding classes are parameterized macros used by
1891 // Machine Instruction Nodes in order to generate the bit encoding of the
1892 // instruction. Operands specify their base encoding interface with the
1893 // interface keyword. There are currently supported four interfaces,
1894 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
1895 // operand to generate a function which returns its register number when
1896 // queried. CONST_INTER causes an operand to generate a function which
1897 // returns the value of the constant when queried. MEMORY_INTER causes an
1898 // operand to generate four functions which return the Base Register, the
1899 // Index Register, the Scale Value, and the Offset Value of the operand when
1900 // queried. COND_INTER causes an operand to generate six functions which
1901 // return the encoding code (ie - encoding bits for the instruction)
1902 // associated with each basic boolean condition for a conditional instruction.
1903 //
1904 // Instructions specify two basic values for encoding. Again, a function
1905 // is available to check if the constant displacement is an oop. They use the
1906 // ins_encode keyword to specify their encoding classes (which must be
1907 // a sequence of enc_class names, and their parameters, specified in
1908 // the encoding block), and they use the
1909 // opcode keyword to specify, in order, their primary, secondary, and
1910 // tertiary opcode. Only the opcode sections which a particular instruction
1911 // needs for encoding need to be specified.
1912 encode %{
1913 enc_class enc_untested %{
1914 #ifdef ASSERT
1915 MacroAssembler _masm(&cbuf);
1916 __ untested("encoding");
1917 #endif
1918 %}
1919
1920 enc_class form3_mem_reg( memory mem, iRegI dst ) %{
1921 emit_form3_mem_reg(cbuf, this, $primary, $tertiary,
1922 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg);
1923 %}
1924
1925 enc_class simple_form3_mem_reg( memory mem, iRegI dst ) %{
1926 emit_form3_mem_reg(cbuf, this, $primary, -1,
1927 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg);
1928 %}
1929
1930 enc_class form3_mem_reg_little( memory mem, iRegI dst) %{
1931 emit_form3_mem_reg_asi(cbuf, this, $primary, -1,
1932 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg, Assembler::ASI_PRIMARY_LITTLE);
1933 %}
1934
1935 enc_class form3_mem_prefetch_read( memory mem ) %{
1936 emit_form3_mem_reg(cbuf, this, $primary, -1,
1937 $mem$$base, $mem$$disp, $mem$$index, 0/*prefetch function many-reads*/);
1938 %}
1939
1940 enc_class form3_mem_prefetch_write( memory mem ) %{
1941 emit_form3_mem_reg(cbuf, this, $primary, -1,
1942 $mem$$base, $mem$$disp, $mem$$index, 2/*prefetch function many-writes*/);
1943 %}
1944
1945 enc_class form3_mem_reg_long_unaligned_marshal( memory mem, iRegL reg ) %{
1946 assert( Assembler::is_simm13($mem$$disp ), "need disp and disp+4" );
1947 assert( Assembler::is_simm13($mem$$disp+4), "need disp and disp+4" );
1948 guarantee($mem$$index == R_G0_enc, "double index?");
1949 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, R_O7_enc );
1950 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg );
1951 emit3_simm13( cbuf, Assembler::arith_op, $reg$$reg, Assembler::sllx_op3, $reg$$reg, 0x1020 );
1952 emit3( cbuf, Assembler::arith_op, $reg$$reg, Assembler::or_op3, $reg$$reg, 0, R_O7_enc );
1953 %}
1954
1955 enc_class form3_mem_reg_double_unaligned( memory mem, RegD_low reg ) %{
1956 assert( Assembler::is_simm13($mem$$disp ), "need disp and disp+4" );
1957 assert( Assembler::is_simm13($mem$$disp+4), "need disp and disp+4" );
1958 guarantee($mem$$index == R_G0_enc, "double index?");
1959 // Load long with 2 instructions
1960 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg+0 );
1961 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, $reg$$reg+1 );
1962 %}
1963
1964 //%%% form3_mem_plus_4_reg is a hack--get rid of it
1965 enc_class form3_mem_plus_4_reg( memory mem, iRegI dst ) %{
1966 guarantee($mem$$disp, "cannot offset a reg-reg operand by 4");
1967 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp + 4, $mem$$index, $dst$$reg);
1968 %}
1969
1970 enc_class form3_g0_rs2_rd_move( iRegI rs2, iRegI rd ) %{
1971 // Encode a reg-reg copy. If it is useless, then empty encoding.
1972 if( $rs2$$reg != $rd$$reg )
1973 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, $rs2$$reg );
1974 %}
1975
1976 // Target lo half of long
1977 enc_class form3_g0_rs2_rd_move_lo( iRegI rs2, iRegL rd ) %{
1978 // Encode a reg-reg copy. If it is useless, then empty encoding.
1979 if( $rs2$$reg != LONG_LO_REG($rd$$reg) )
1980 emit3( cbuf, Assembler::arith_op, LONG_LO_REG($rd$$reg), Assembler::or_op3, 0, 0, $rs2$$reg );
1981 %}
1982
1983 // Source lo half of long
1984 enc_class form3_g0_rs2_rd_move_lo2( iRegL rs2, iRegI rd ) %{
1985 // Encode a reg-reg copy. If it is useless, then empty encoding.
1986 if( LONG_LO_REG($rs2$$reg) != $rd$$reg )
1987 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_LO_REG($rs2$$reg) );
1988 %}
1989
1990 // Target hi half of long
1991 enc_class form3_rs1_rd_copysign_hi( iRegI rs1, iRegL rd ) %{
1992 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 31 );
1993 %}
1994
1995 // Source lo half of long, and leave it sign extended.
1996 enc_class form3_rs1_rd_signextend_lo1( iRegL rs1, iRegI rd ) %{
1997 // Sign extend low half
1998 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 0, 0 );
1999 %}
2000
2001 // Source hi half of long, and leave it sign extended.
2002 enc_class form3_rs1_rd_copy_hi1( iRegL rs1, iRegI rd ) %{
2003 // Shift high half to low half
2004 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::srlx_op3, $rs1$$reg, 32 );
2005 %}
2006
2007 // Source hi half of long
2008 enc_class form3_g0_rs2_rd_move_hi2( iRegL rs2, iRegI rd ) %{
2009 // Encode a reg-reg copy. If it is useless, then empty encoding.
2010 if( LONG_HI_REG($rs2$$reg) != $rd$$reg )
2011 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_HI_REG($rs2$$reg) );
2012 %}
2013
2014 enc_class form3_rs1_rs2_rd( iRegI rs1, iRegI rs2, iRegI rd ) %{
2015 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0, $rs2$$reg );
2016 %}
2017
2018 enc_class enc_to_bool( iRegI src, iRegI dst ) %{
2019 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, 0, 0, $src$$reg );
2020 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::addc_op3 , 0, 0 );
2021 %}
2022
2023 enc_class enc_ltmask( iRegI p, iRegI q, iRegI dst ) %{
2024 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $p$$reg, 0, $q$$reg );
2025 // clear if nothing else is happening
2026 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 0 );
2027 // blt,a,pn done
2028 emit2_19 ( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less, Assembler::bp_op2, Assembler::icc, 0/*predict not taken*/, 2 );
2029 // mov dst,-1 in delay slot
2030 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 );
2031 %}
2032
2033 enc_class form3_rs1_imm5_rd( iRegI rs1, immU5 imm5, iRegI rd ) %{
2034 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $imm5$$constant & 0x1F );
2035 %}
2036
2037 enc_class form3_sd_rs1_imm6_rd( iRegL rs1, immU6 imm6, iRegL rd ) %{
2038 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, ($imm6$$constant & 0x3F) | 0x1000 );
2039 %}
2040
2041 enc_class form3_sd_rs1_rs2_rd( iRegL rs1, iRegI rs2, iRegL rd ) %{
2042 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0x80, $rs2$$reg );
2043 %}
2044
2045 enc_class form3_rs1_simm13_rd( iRegI rs1, immI13 simm13, iRegI rd ) %{
2046 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $simm13$$constant );
2047 %}
2048
2049 enc_class move_return_pc_to_o1() %{
2050 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::add_op3, R_O7_enc, frame::pc_return_offset );
2051 %}
2052
2053 #ifdef _LP64
2054 /* %%% merge with enc_to_bool */
2055 enc_class enc_convP2B( iRegI dst, iRegP src ) %{
2056 MacroAssembler _masm(&cbuf);
2057
2058 Register src_reg = reg_to_register_object($src$$reg);
2059 Register dst_reg = reg_to_register_object($dst$$reg);
2060 __ movr(Assembler::rc_nz, src_reg, 1, dst_reg);
2061 %}
2062 #endif
2063
2064 enc_class enc_cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp ) %{
2065 // (Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)))
2066 MacroAssembler _masm(&cbuf);
2067
2068 Register p_reg = reg_to_register_object($p$$reg);
2069 Register q_reg = reg_to_register_object($q$$reg);
2070 Register y_reg = reg_to_register_object($y$$reg);
2071 Register tmp_reg = reg_to_register_object($tmp$$reg);
2072
2073 __ subcc( p_reg, q_reg, p_reg );
2074 __ add ( p_reg, y_reg, tmp_reg );
2075 __ movcc( Assembler::less, false, Assembler::icc, tmp_reg, p_reg );
2076 %}
2077
2078 enc_class form_d2i_helper(regD src, regF dst) %{
2079 // fcmp %fcc0,$src,$src
2080 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg );
2081 // branch %fcc0 not-nan, predict taken
2082 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2083 // fdtoi $src,$dst
2084 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtoi_opf, $src$$reg );
2085 // fitos $dst,$dst (if nan)
2086 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg );
2087 // clear $dst (if nan)
2088 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg );
2089 // carry on here...
2090 %}
2091
2092 enc_class form_d2l_helper(regD src, regD dst) %{
2093 // fcmp %fcc0,$src,$src check for NAN
2094 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg );
2095 // branch %fcc0 not-nan, predict taken
2096 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2097 // fdtox $src,$dst convert in delay slot
2098 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtox_opf, $src$$reg );
2099 // fxtod $dst,$dst (if nan)
2100 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg );
2101 // clear $dst (if nan)
2102 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg );
2103 // carry on here...
2104 %}
2105
2106 enc_class form_f2i_helper(regF src, regF dst) %{
2107 // fcmps %fcc0,$src,$src
2108 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg );
2109 // branch %fcc0 not-nan, predict taken
2110 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2111 // fstoi $src,$dst
2112 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstoi_opf, $src$$reg );
2113 // fitos $dst,$dst (if nan)
2114 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg );
2115 // clear $dst (if nan)
2116 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg );
2117 // carry on here...
2118 %}
2119
2120 enc_class form_f2l_helper(regF src, regD dst) %{
2121 // fcmps %fcc0,$src,$src
2122 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg );
2123 // branch %fcc0 not-nan, predict taken
2124 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2125 // fstox $src,$dst
2126 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstox_opf, $src$$reg );
2127 // fxtod $dst,$dst (if nan)
2128 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg );
2129 // clear $dst (if nan)
2130 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg );
2131 // carry on here...
2132 %}
2133
2134 enc_class form3_opf_rs2F_rdF(regF rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2135 enc_class form3_opf_rs2F_rdD(regF rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2136 enc_class form3_opf_rs2D_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2137 enc_class form3_opf_rs2D_rdD(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2138
2139 enc_class form3_opf_rs2D_lo_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg+1); %}
2140
2141 enc_class form3_opf_rs2D_hi_rdD_hi(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2142 enc_class form3_opf_rs2D_lo_rdD_lo(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg+1,$primary,0,$tertiary,$rs2$$reg+1); %}
2143
2144 enc_class form3_opf_rs1F_rs2F_rdF( regF rs1, regF rs2, regF rd ) %{
2145 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2146 %}
2147
2148 enc_class form3_opf_rs1D_rs2D_rdD( regD rs1, regD rs2, regD rd ) %{
2149 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2150 %}
2151
2152 enc_class form3_opf_rs1F_rs2F_fcc( regF rs1, regF rs2, flagsRegF fcc ) %{
2153 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2154 %}
2155
2156 enc_class form3_opf_rs1D_rs2D_fcc( regD rs1, regD rs2, flagsRegF fcc ) %{
2157 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2158 %}
2159
2160 enc_class form3_convI2F(regF rs2, regF rd) %{
2161 emit3(cbuf,Assembler::arith_op,$rd$$reg,Assembler::fpop1_op3,0,$secondary,$rs2$$reg);
2162 %}
2163
2164 // Encloding class for traceable jumps
2165 enc_class form_jmpl(g3RegP dest) %{
2166 emit_jmpl(cbuf, $dest$$reg);
2167 %}
2168
2169 enc_class form_jmpl_set_exception_pc(g1RegP dest) %{
2170 emit_jmpl_set_exception_pc(cbuf, $dest$$reg);
2171 %}
2172
2173 enc_class form2_nop() %{
2174 emit_nop(cbuf);
2175 %}
2176
2177 enc_class form2_illtrap() %{
2178 emit_illtrap(cbuf);
2179 %}
2180
2181
2182 // Compare longs and convert into -1, 0, 1.
2183 enc_class cmpl_flag( iRegL src1, iRegL src2, iRegI dst ) %{
2184 // CMP $src1,$src2
2185 emit3( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $src1$$reg, 0, $src2$$reg );
2186 // blt,a,pn done
2187 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less , Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 5 );
2188 // mov dst,-1 in delay slot
2189 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 );
2190 // bgt,a,pn done
2191 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::greater, Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 3 );
2192 // mov dst,1 in delay slot
2193 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 1 );
2194 // CLR $dst
2195 emit3( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3 , 0, 0, 0 );
2196 %}
2197
2198 enc_class enc_PartialSubtypeCheck() %{
2199 MacroAssembler _masm(&cbuf);
2200 __ call(StubRoutines::Sparc::partial_subtype_check(), relocInfo::runtime_call_type);
2201 __ delayed()->nop();
2202 %}
2203
2204 enc_class enc_bp( Label labl, cmpOp cmp, flagsReg cc ) %{
2205 MacroAssembler _masm(&cbuf);
2206 Label &L = *($labl$$label);
2207 Assembler::Predict predict_taken =
2208 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn;
2209
2210 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, L);
2211 __ delayed()->nop();
2212 %}
2213
2214 enc_class enc_bpl( Label labl, cmpOp cmp, flagsRegL cc ) %{
2215 MacroAssembler _masm(&cbuf);
2216 Label &L = *($labl$$label);
2217 Assembler::Predict predict_taken =
2218 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn;
2219
2220 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, L);
2221 __ delayed()->nop();
2222 %}
2223
2224 enc_class enc_bpx( Label labl, cmpOp cmp, flagsRegP cc ) %{
2225 MacroAssembler _masm(&cbuf);
2226 Label &L = *($labl$$label);
2227 Assembler::Predict predict_taken =
2228 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn;
2229
2230 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, L);
2231 __ delayed()->nop();
2232 %}
2233
2234 enc_class enc_fbp( Label labl, cmpOpF cmp, flagsRegF cc ) %{
2235 MacroAssembler _masm(&cbuf);
2236 Label &L = *($labl$$label);
2237 Assembler::Predict predict_taken =
2238 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn;
2239
2240 __ fbp( (Assembler::Condition)($cmp$$cmpcode), false, (Assembler::CC)($cc$$reg), predict_taken, L);
2241 __ delayed()->nop();
2242 %}
2243
2244 enc_class jump_enc( iRegX switch_val, o7RegI table) %{
2245 MacroAssembler _masm(&cbuf);
2246
2247 Register switch_reg = as_Register($switch_val$$reg);
2248 Register table_reg = O7;
2249
2250 address table_base = __ address_table_constant(_index2label);
2251 RelocationHolder rspec = internal_word_Relocation::spec(table_base);
2252
2253 // Move table address into a register.
2254 __ set(table_base, table_reg, rspec);
2255
2256 // Jump to base address + switch value
2257 __ ld_ptr(table_reg, switch_reg, table_reg);
2258 __ jmp(table_reg, G0);
2259 __ delayed()->nop();
2260
2261 %}
2262
2263 enc_class enc_ba( Label labl ) %{
2264 MacroAssembler _masm(&cbuf);
2265 Label &L = *($labl$$label);
2266 __ ba(false, L);
2267 __ delayed()->nop();
2268 %}
2269
2270 enc_class enc_bpr( Label labl, cmpOp_reg cmp, iRegI op1 ) %{
2271 MacroAssembler _masm(&cbuf);
2272 Label &L = *$labl$$label;
2273 Assembler::Predict predict_taken =
2274 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn;
2275
2276 __ bpr( (Assembler::RCondition)($cmp$$cmpcode), false, predict_taken, as_Register($op1$$reg), L);
2277 __ delayed()->nop();
2278 %}
2279
2280 enc_class enc_cmov_reg( cmpOp cmp, iRegI dst, iRegI src, immI pcc) %{
2281 int op = (Assembler::arith_op << 30) |
2282 ($dst$$reg << 25) |
2283 (Assembler::movcc_op3 << 19) |
2284 (1 << 18) | // cc2 bit for 'icc'
2285 ($cmp$$cmpcode << 14) |
2286 (0 << 13) | // select register move
2287 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc' or 'xcc'
2288 ($src$$reg << 0);
2289 *((int*)(cbuf.code_end())) = op;
2290 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
2291 %}
2292
2293 enc_class enc_cmov_imm( cmpOp cmp, iRegI dst, immI11 src, immI pcc ) %{
2294 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits
2295 int op = (Assembler::arith_op << 30) |
2296 ($dst$$reg << 25) |
2297 (Assembler::movcc_op3 << 19) |
2298 (1 << 18) | // cc2 bit for 'icc'
2299 ($cmp$$cmpcode << 14) |
2300 (1 << 13) | // select immediate move
2301 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc'
2302 (simm11 << 0);
2303 *((int*)(cbuf.code_end())) = op;
2304 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
2305 %}
2306
2307 enc_class enc_cmov_reg_f( cmpOpF cmp, iRegI dst, iRegI src, flagsRegF fcc ) %{
2308 int op = (Assembler::arith_op << 30) |
2309 ($dst$$reg << 25) |
2310 (Assembler::movcc_op3 << 19) |
2311 (0 << 18) | // cc2 bit for 'fccX'
2312 ($cmp$$cmpcode << 14) |
2313 (0 << 13) | // select register move
2314 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3
2315 ($src$$reg << 0);
2316 *((int*)(cbuf.code_end())) = op;
2317 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
2318 %}
2319
2320 enc_class enc_cmov_imm_f( cmpOp cmp, iRegI dst, immI11 src, flagsRegF fcc ) %{
2321 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits
2322 int op = (Assembler::arith_op << 30) |
2323 ($dst$$reg << 25) |
2324 (Assembler::movcc_op3 << 19) |
2325 (0 << 18) | // cc2 bit for 'fccX'
2326 ($cmp$$cmpcode << 14) |
2327 (1 << 13) | // select immediate move
2328 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3
2329 (simm11 << 0);
2330 *((int*)(cbuf.code_end())) = op;
2331 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
2332 %}
2333
2334 enc_class enc_cmovf_reg( cmpOp cmp, regD dst, regD src, immI pcc ) %{
2335 int op = (Assembler::arith_op << 30) |
2336 ($dst$$reg << 25) |
2337 (Assembler::fpop2_op3 << 19) |
2338 (0 << 18) |
2339 ($cmp$$cmpcode << 14) |
2340 (1 << 13) | // select register move
2341 ($pcc$$constant << 11) | // cc1-cc0 bits for 'icc' or 'xcc'
2342 ($primary << 5) | // select single, double or quad
2343 ($src$$reg << 0);
2344 *((int*)(cbuf.code_end())) = op;
2345 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
2346 %}
2347
2348 enc_class enc_cmovff_reg( cmpOpF cmp, flagsRegF fcc, regD dst, regD src ) %{
2349 int op = (Assembler::arith_op << 30) |
2350 ($dst$$reg << 25) |
2351 (Assembler::fpop2_op3 << 19) |
2352 (0 << 18) |
2353 ($cmp$$cmpcode << 14) |
2354 ($fcc$$reg << 11) | // cc2-cc0 bits for 'fccX'
2355 ($primary << 5) | // select single, double or quad
2356 ($src$$reg << 0);
2357 *((int*)(cbuf.code_end())) = op;
2358 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
2359 %}
2360
2361 // Used by the MIN/MAX encodings. Same as a CMOV, but
2362 // the condition comes from opcode-field instead of an argument.
2363 enc_class enc_cmov_reg_minmax( iRegI dst, iRegI src ) %{
2364 int op = (Assembler::arith_op << 30) |
2365 ($dst$$reg << 25) |
2366 (Assembler::movcc_op3 << 19) |
2367 (1 << 18) | // cc2 bit for 'icc'
2368 ($primary << 14) |
2369 (0 << 13) | // select register move
2370 (0 << 11) | // cc1, cc0 bits for 'icc'
2371 ($src$$reg << 0);
2372 *((int*)(cbuf.code_end())) = op;
2373 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
2374 %}
2375
2376 enc_class enc_cmov_reg_minmax_long( iRegL dst, iRegL src ) %{
2377 int op = (Assembler::arith_op << 30) |
2378 ($dst$$reg << 25) |
2379 (Assembler::movcc_op3 << 19) |
2380 (6 << 16) | // cc2 bit for 'xcc'
2381 ($primary << 14) |
2382 (0 << 13) | // select register move
2383 (0 << 11) | // cc1, cc0 bits for 'icc'
2384 ($src$$reg << 0);
2385 *((int*)(cbuf.code_end())) = op;
2386 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
2387 %}
2388
2389 // Utility encoding for loading a 64 bit Pointer into a register
2390 // The 64 bit pointer is stored in the generated code stream
2391 enc_class SetPtr( immP src, iRegP rd ) %{
2392 Register dest = reg_to_register_object($rd$$reg);
2393 MacroAssembler _masm(&cbuf);
2394 // [RGV] This next line should be generated from ADLC
2395 if ( _opnds[1]->constant_is_oop() ) {
2396 intptr_t val = $src$$constant;
2397 __ set_oop_constant((jobject)val, dest);
2398 } else { // non-oop pointers, e.g. card mark base, heap top
2399 __ set($src$$constant, dest);
2400 }
2401 %}
2402
2403 enc_class Set13( immI13 src, iRegI rd ) %{
2404 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, $src$$constant );
2405 %}
2406
2407 enc_class SetHi22( immI src, iRegI rd ) %{
2408 emit2_22( cbuf, Assembler::branch_op, $rd$$reg, Assembler::sethi_op2, $src$$constant );
2409 %}
2410
2411 enc_class Set32( immI src, iRegI rd ) %{
2412 MacroAssembler _masm(&cbuf);
2413 __ set($src$$constant, reg_to_register_object($rd$$reg));
2414 %}
2415
2416 enc_class SetNull( iRegI rd ) %{
2417 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0 );
2418 %}
2419
2420 enc_class call_epilog %{
2421 if( VerifyStackAtCalls ) {
2422 MacroAssembler _masm(&cbuf);
2423 int framesize = ra_->C->frame_slots() << LogBytesPerInt;
2424 Register temp_reg = G3;
2425 __ add(SP, framesize, temp_reg);
2426 __ cmp(temp_reg, FP);
2427 __ breakpoint_trap(Assembler::notEqual, Assembler::ptr_cc);
2428 }
2429 %}
2430
2431 // Long values come back from native calls in O0:O1 in the 32-bit VM, copy the value
2432 // to G1 so the register allocator will not have to deal with the misaligned register
2433 // pair.
2434 enc_class adjust_long_from_native_call %{
2435 #ifndef _LP64
2436 if (returns_long()) {
2437 // sllx O0,32,O0
2438 emit3_simm13( cbuf, Assembler::arith_op, R_O0_enc, Assembler::sllx_op3, R_O0_enc, 0x1020 );
2439 // srl O1,0,O1
2440 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::srl_op3, R_O1_enc, 0x0000 );
2441 // or O0,O1,G1
2442 emit3 ( cbuf, Assembler::arith_op, R_G1_enc, Assembler:: or_op3, R_O0_enc, 0, R_O1_enc );
2443 }
2444 #endif
2445 %}
2446
2447 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime
2448 // CALL directly to the runtime
2449 // The user of this is responsible for ensuring that R_L7 is empty (killed).
2450 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type,
2451 /*preserve_g2=*/true, /*force far call*/true);
2452 %}
2453
2454 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL
2455 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
2456 // who we intended to call.
2457 if ( !_method ) {
2458 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type);
2459 } else if (_optimized_virtual) {
2460 emit_call_reloc(cbuf, $meth$$method, relocInfo::opt_virtual_call_type);
2461 } else {
2462 emit_call_reloc(cbuf, $meth$$method, relocInfo::static_call_type);
2463 }
2464 if( _method ) { // Emit stub for static call
2465 emit_java_to_interp(cbuf);
2466 }
2467 %}
2468
2469 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL
2470 MacroAssembler _masm(&cbuf);
2471 __ set_inst_mark();
2472 int vtable_index = this->_vtable_index;
2473 // MachCallDynamicJavaNode::ret_addr_offset uses this same test
2474 if (vtable_index < 0) {
2475 // must be invalid_vtable_index, not nonvirtual_vtable_index
2476 assert(vtable_index == methodOopDesc::invalid_vtable_index, "correct sentinel value");
2477 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
2478 assert(G5_ic_reg == G5_inline_cache_reg, "G5_inline_cache_reg used in assemble_ic_buffer_code()");
2479 assert(G5_ic_reg == G5_megamorphic_method, "G5_megamorphic_method used in megamorphic call stub");
2480 // !!!!!
2481 // Generate "set 0x01, R_G5", placeholder instruction to load oop-info
2482 // emit_call_dynamic_prologue( cbuf );
2483 __ set_oop((jobject)Universe::non_oop_word(), G5_ic_reg);
2484
2485 address virtual_call_oop_addr = __ inst_mark();
2486 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
2487 // who we intended to call.
2488 __ relocate(virtual_call_Relocation::spec(virtual_call_oop_addr));
2489 emit_call_reloc(cbuf, $meth$$method, relocInfo::none);
2490 } else {
2491 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
2492 // Just go thru the vtable
2493 // get receiver klass (receiver already checked for non-null)
2494 // If we end up going thru a c2i adapter interpreter expects method in G5
2495 int off = __ offset();
2496 __ load_klass(O0, G3_scratch);
2497 int klass_load_size;
2498 if (UseCompressedOops) {
2499 assert(Universe::heap() != NULL, "java heap should be initialized");
2500 if (Universe::narrow_oop_base() == NULL)
2501 klass_load_size = 2*BytesPerInstWord;
2502 else
2503 klass_load_size = 3*BytesPerInstWord;
2504 } else {
2505 klass_load_size = 1*BytesPerInstWord;
2506 }
2507 int entry_offset = instanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size();
2508 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes();
2509 if( __ is_simm13(v_off) ) {
2510 __ ld_ptr(G3, v_off, G5_method);
2511 } else {
2512 // Generate 2 instructions
2513 __ Assembler::sethi(v_off & ~0x3ff, G5_method);
2514 __ or3(G5_method, v_off & 0x3ff, G5_method);
2515 // ld_ptr, set_hi, set
2516 assert(__ offset() - off == klass_load_size + 2*BytesPerInstWord,
2517 "Unexpected instruction size(s)");
2518 __ ld_ptr(G3, G5_method, G5_method);
2519 }
2520 // NOTE: for vtable dispatches, the vtable entry will never be null.
2521 // However it may very well end up in handle_wrong_method if the
2522 // method is abstract for the particular class.
2523 __ ld_ptr(G5_method, in_bytes(methodOopDesc::from_compiled_offset()), G3_scratch);
2524 // jump to target (either compiled code or c2iadapter)
2525 __ jmpl(G3_scratch, G0, O7);
2526 __ delayed()->nop();
2527 }
2528 %}
2529
2530 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL
2531 MacroAssembler _masm(&cbuf);
2532
2533 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
2534 Register temp_reg = G3; // caller must kill G3! We cannot reuse G5_ic_reg here because
2535 // we might be calling a C2I adapter which needs it.
2536
2537 assert(temp_reg != G5_ic_reg, "conflicting registers");
2538 // Load nmethod
2539 __ ld_ptr(G5_ic_reg, in_bytes(methodOopDesc::from_compiled_offset()), temp_reg);
2540
2541 // CALL to compiled java, indirect the contents of G3
2542 __ set_inst_mark();
2543 __ callr(temp_reg, G0);
2544 __ delayed()->nop();
2545 %}
2546
2547 enc_class idiv_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst) %{
2548 MacroAssembler _masm(&cbuf);
2549 Register Rdividend = reg_to_register_object($src1$$reg);
2550 Register Rdivisor = reg_to_register_object($src2$$reg);
2551 Register Rresult = reg_to_register_object($dst$$reg);
2552
2553 __ sra(Rdivisor, 0, Rdivisor);
2554 __ sra(Rdividend, 0, Rdividend);
2555 __ sdivx(Rdividend, Rdivisor, Rresult);
2556 %}
2557
2558 enc_class idiv_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst) %{
2559 MacroAssembler _masm(&cbuf);
2560
2561 Register Rdividend = reg_to_register_object($src1$$reg);
2562 int divisor = $imm$$constant;
2563 Register Rresult = reg_to_register_object($dst$$reg);
2564
2565 __ sra(Rdividend, 0, Rdividend);
2566 __ sdivx(Rdividend, divisor, Rresult);
2567 %}
2568
2569 enc_class enc_mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2) %{
2570 MacroAssembler _masm(&cbuf);
2571 Register Rsrc1 = reg_to_register_object($src1$$reg);
2572 Register Rsrc2 = reg_to_register_object($src2$$reg);
2573 Register Rdst = reg_to_register_object($dst$$reg);
2574
2575 __ sra( Rsrc1, 0, Rsrc1 );
2576 __ sra( Rsrc2, 0, Rsrc2 );
2577 __ mulx( Rsrc1, Rsrc2, Rdst );
2578 __ srlx( Rdst, 32, Rdst );
2579 %}
2580
2581 enc_class irem_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst, o7RegL scratch) %{
2582 MacroAssembler _masm(&cbuf);
2583 Register Rdividend = reg_to_register_object($src1$$reg);
2584 Register Rdivisor = reg_to_register_object($src2$$reg);
2585 Register Rresult = reg_to_register_object($dst$$reg);
2586 Register Rscratch = reg_to_register_object($scratch$$reg);
2587
2588 assert(Rdividend != Rscratch, "");
2589 assert(Rdivisor != Rscratch, "");
2590
2591 __ sra(Rdividend, 0, Rdividend);
2592 __ sra(Rdivisor, 0, Rdivisor);
2593 __ sdivx(Rdividend, Rdivisor, Rscratch);
2594 __ mulx(Rscratch, Rdivisor, Rscratch);
2595 __ sub(Rdividend, Rscratch, Rresult);
2596 %}
2597
2598 enc_class irem_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst, o7RegL scratch) %{
2599 MacroAssembler _masm(&cbuf);
2600
2601 Register Rdividend = reg_to_register_object($src1$$reg);
2602 int divisor = $imm$$constant;
2603 Register Rresult = reg_to_register_object($dst$$reg);
2604 Register Rscratch = reg_to_register_object($scratch$$reg);
2605
2606 assert(Rdividend != Rscratch, "");
2607
2608 __ sra(Rdividend, 0, Rdividend);
2609 __ sdivx(Rdividend, divisor, Rscratch);
2610 __ mulx(Rscratch, divisor, Rscratch);
2611 __ sub(Rdividend, Rscratch, Rresult);
2612 %}
2613
2614 enc_class fabss (sflt_reg dst, sflt_reg src) %{
2615 MacroAssembler _masm(&cbuf);
2616
2617 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2618 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2619
2620 __ fabs(FloatRegisterImpl::S, Fsrc, Fdst);
2621 %}
2622
2623 enc_class fabsd (dflt_reg dst, dflt_reg src) %{
2624 MacroAssembler _masm(&cbuf);
2625
2626 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2627 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2628
2629 __ fabs(FloatRegisterImpl::D, Fsrc, Fdst);
2630 %}
2631
2632 enc_class fnegd (dflt_reg dst, dflt_reg src) %{
2633 MacroAssembler _masm(&cbuf);
2634
2635 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2636 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2637
2638 __ fneg(FloatRegisterImpl::D, Fsrc, Fdst);
2639 %}
2640
2641 enc_class fsqrts (sflt_reg dst, sflt_reg src) %{
2642 MacroAssembler _masm(&cbuf);
2643
2644 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2645 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2646
2647 __ fsqrt(FloatRegisterImpl::S, Fsrc, Fdst);
2648 %}
2649
2650 enc_class fsqrtd (dflt_reg dst, dflt_reg src) %{
2651 MacroAssembler _masm(&cbuf);
2652
2653 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2654 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2655
2656 __ fsqrt(FloatRegisterImpl::D, Fsrc, Fdst);
2657 %}
2658
2659 enc_class fmovs (dflt_reg dst, dflt_reg src) %{
2660 MacroAssembler _masm(&cbuf);
2661
2662 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2663 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2664
2665 __ fmov(FloatRegisterImpl::S, Fsrc, Fdst);
2666 %}
2667
2668 enc_class fmovd (dflt_reg dst, dflt_reg src) %{
2669 MacroAssembler _masm(&cbuf);
2670
2671 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2672 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2673
2674 __ fmov(FloatRegisterImpl::D, Fsrc, Fdst);
2675 %}
2676
2677 enc_class Fast_Lock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{
2678 MacroAssembler _masm(&cbuf);
2679
2680 Register Roop = reg_to_register_object($oop$$reg);
2681 Register Rbox = reg_to_register_object($box$$reg);
2682 Register Rscratch = reg_to_register_object($scratch$$reg);
2683 Register Rmark = reg_to_register_object($scratch2$$reg);
2684
2685 assert(Roop != Rscratch, "");
2686 assert(Roop != Rmark, "");
2687 assert(Rbox != Rscratch, "");
2688 assert(Rbox != Rmark, "");
2689
2690 __ compiler_lock_object(Roop, Rmark, Rbox, Rscratch, _counters, UseBiasedLocking && !UseOptoBiasInlining);
2691 %}
2692
2693 enc_class Fast_Unlock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{
2694 MacroAssembler _masm(&cbuf);
2695
2696 Register Roop = reg_to_register_object($oop$$reg);
2697 Register Rbox = reg_to_register_object($box$$reg);
2698 Register Rscratch = reg_to_register_object($scratch$$reg);
2699 Register Rmark = reg_to_register_object($scratch2$$reg);
2700
2701 assert(Roop != Rscratch, "");
2702 assert(Roop != Rmark, "");
2703 assert(Rbox != Rscratch, "");
2704 assert(Rbox != Rmark, "");
2705
2706 __ compiler_unlock_object(Roop, Rmark, Rbox, Rscratch, UseBiasedLocking && !UseOptoBiasInlining);
2707 %}
2708
2709 enc_class enc_cas( iRegP mem, iRegP old, iRegP new ) %{
2710 MacroAssembler _masm(&cbuf);
2711 Register Rmem = reg_to_register_object($mem$$reg);
2712 Register Rold = reg_to_register_object($old$$reg);
2713 Register Rnew = reg_to_register_object($new$$reg);
2714
2715 // casx_under_lock picks 1 of 3 encodings:
2716 // For 32-bit pointers you get a 32-bit CAS
2717 // For 64-bit pointers you get a 64-bit CASX
2718 __ casn(Rmem, Rold, Rnew); // Swap(*Rmem,Rnew) if *Rmem == Rold
2719 __ cmp( Rold, Rnew );
2720 %}
2721
2722 enc_class enc_casx( iRegP mem, iRegL old, iRegL new) %{
2723 Register Rmem = reg_to_register_object($mem$$reg);
2724 Register Rold = reg_to_register_object($old$$reg);
2725 Register Rnew = reg_to_register_object($new$$reg);
2726
2727 MacroAssembler _masm(&cbuf);
2728 __ mov(Rnew, O7);
2729 __ casx(Rmem, Rold, O7);
2730 __ cmp( Rold, O7 );
2731 %}
2732
2733 // raw int cas, used for compareAndSwap
2734 enc_class enc_casi( iRegP mem, iRegL old, iRegL new) %{
2735 Register Rmem = reg_to_register_object($mem$$reg);
2736 Register Rold = reg_to_register_object($old$$reg);
2737 Register Rnew = reg_to_register_object($new$$reg);
2738
2739 MacroAssembler _masm(&cbuf);
2740 __ mov(Rnew, O7);
2741 __ cas(Rmem, Rold, O7);
2742 __ cmp( Rold, O7 );
2743 %}
2744
2745 enc_class enc_lflags_ne_to_boolean( iRegI res ) %{
2746 Register Rres = reg_to_register_object($res$$reg);
2747
2748 MacroAssembler _masm(&cbuf);
2749 __ mov(1, Rres);
2750 __ movcc( Assembler::notEqual, false, Assembler::xcc, G0, Rres );
2751 %}
2752
2753 enc_class enc_iflags_ne_to_boolean( iRegI res ) %{
2754 Register Rres = reg_to_register_object($res$$reg);
2755
2756 MacroAssembler _masm(&cbuf);
2757 __ mov(1, Rres);
2758 __ movcc( Assembler::notEqual, false, Assembler::icc, G0, Rres );
2759 %}
2760
2761 enc_class floating_cmp ( iRegP dst, regF src1, regF src2 ) %{
2762 MacroAssembler _masm(&cbuf);
2763 Register Rdst = reg_to_register_object($dst$$reg);
2764 FloatRegister Fsrc1 = $primary ? reg_to_SingleFloatRegister_object($src1$$reg)
2765 : reg_to_DoubleFloatRegister_object($src1$$reg);
2766 FloatRegister Fsrc2 = $primary ? reg_to_SingleFloatRegister_object($src2$$reg)
2767 : reg_to_DoubleFloatRegister_object($src2$$reg);
2768
2769 // Convert condition code fcc0 into -1,0,1; unordered reports less-than (-1)
2770 __ float_cmp( $primary, -1, Fsrc1, Fsrc2, Rdst);
2771 %}
2772
2773 enc_class LdImmL (immL src, iRegL dst, o7RegL tmp) %{ // Load Immediate
2774 MacroAssembler _masm(&cbuf);
2775 Register dest = reg_to_register_object($dst$$reg);
2776 Register temp = reg_to_register_object($tmp$$reg);
2777 __ set64( $src$$constant, dest, temp );
2778 %}
2779
2780 enc_class LdReplImmI(immI src, regD dst, o7RegP tmp, int count, int width) %{
2781 // Load a constant replicated "count" times with width "width"
2782 int bit_width = $width$$constant * 8;
2783 jlong elt_val = $src$$constant;
2784 elt_val &= (((jlong)1) << bit_width) - 1; // mask off sign bits
2785 jlong val = elt_val;
2786 for (int i = 0; i < $count$$constant - 1; i++) {
2787 val <<= bit_width;
2788 val |= elt_val;
2789 }
2790 jdouble dval = *(jdouble*)&val; // coerce to double type
2791 MacroAssembler _masm(&cbuf);
2792 address double_address = __ double_constant(dval);
2793 RelocationHolder rspec = internal_word_Relocation::spec(double_address);
2794 AddressLiteral addrlit(double_address, rspec);
2795
2796 __ sethi(addrlit, $tmp$$Register);
2797 // XXX This is a quick fix for 6833573.
2798 //__ ldf(FloatRegisterImpl::D, $tmp$$Register, addrlit.low10(), $dst$$FloatRegister, rspec);
2799 __ ldf(FloatRegisterImpl::D, $tmp$$Register, addrlit.low10(), as_DoubleFloatRegister($dst$$reg), rspec);
2800 %}
2801
2802 // Compiler ensures base is doubleword aligned and cnt is count of doublewords
2803 enc_class enc_Clear_Array(iRegX cnt, iRegP base, iRegX temp) %{
2804 MacroAssembler _masm(&cbuf);
2805 Register nof_bytes_arg = reg_to_register_object($cnt$$reg);
2806 Register nof_bytes_tmp = reg_to_register_object($temp$$reg);
2807 Register base_pointer_arg = reg_to_register_object($base$$reg);
2808
2809 Label loop;
2810 __ mov(nof_bytes_arg, nof_bytes_tmp);
2811
2812 // Loop and clear, walking backwards through the array.
2813 // nof_bytes_tmp (if >0) is always the number of bytes to zero
2814 __ bind(loop);
2815 __ deccc(nof_bytes_tmp, 8);
2816 __ br(Assembler::greaterEqual, true, Assembler::pt, loop);
2817 __ delayed()-> stx(G0, base_pointer_arg, nof_bytes_tmp);
2818 // %%%% this mini-loop must not cross a cache boundary!
2819 %}
2820
2821
2822 enc_class enc_String_Compare(o0RegP str1, o1RegP str2, g3RegP tmp1, g4RegP tmp2, notemp_iRegI result) %{
2823 Label Ldone, Lloop;
2824 MacroAssembler _masm(&cbuf);
2825
2826 Register str1_reg = reg_to_register_object($str1$$reg);
2827 Register str2_reg = reg_to_register_object($str2$$reg);
2828 Register tmp1_reg = reg_to_register_object($tmp1$$reg);
2829 Register tmp2_reg = reg_to_register_object($tmp2$$reg);
2830 Register result_reg = reg_to_register_object($result$$reg);
2831
2832 // Get the first character position in both strings
2833 // [8] char array, [12] offset, [16] count
2834 int value_offset = java_lang_String:: value_offset_in_bytes();
2835 int offset_offset = java_lang_String::offset_offset_in_bytes();
2836 int count_offset = java_lang_String:: count_offset_in_bytes();
2837
2838 // load str1 (jchar*) base address into tmp1_reg
2839 __ load_heap_oop(str1_reg, value_offset, tmp1_reg);
2840 __ ld(str1_reg, offset_offset, result_reg);
2841 __ add(tmp1_reg, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp1_reg);
2842 __ ld(str1_reg, count_offset, str1_reg); // hoisted
2843 __ sll(result_reg, exact_log2(sizeof(jchar)), result_reg);
2844 __ load_heap_oop(str2_reg, value_offset, tmp2_reg); // hoisted
2845 __ add(result_reg, tmp1_reg, tmp1_reg);
2846
2847 // load str2 (jchar*) base address into tmp2_reg
2848 // __ ld_ptr(str2_reg, value_offset, tmp2_reg); // hoisted
2849 __ ld(str2_reg, offset_offset, result_reg);
2850 __ add(tmp2_reg, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp2_reg);
2851 __ ld(str2_reg, count_offset, str2_reg); // hoisted
2852 __ sll(result_reg, exact_log2(sizeof(jchar)), result_reg);
2853 __ subcc(str1_reg, str2_reg, O7); // hoisted
2854 __ add(result_reg, tmp2_reg, tmp2_reg);
2855
2856 // Compute the minimum of the string lengths(str1_reg) and the
2857 // difference of the string lengths (stack)
2858
2859 // discard string base pointers, after loading up the lengths
2860 // __ ld(str1_reg, count_offset, str1_reg); // hoisted
2861 // __ ld(str2_reg, count_offset, str2_reg); // hoisted
2862
2863 // See if the lengths are different, and calculate min in str1_reg.
2864 // Stash diff in O7 in case we need it for a tie-breaker.
2865 Label Lskip;
2866 // __ subcc(str1_reg, str2_reg, O7); // hoisted
2867 __ sll(str1_reg, exact_log2(sizeof(jchar)), str1_reg); // scale the limit
2868 __ br(Assembler::greater, true, Assembler::pt, Lskip);
2869 // str2 is shorter, so use its count:
2870 __ delayed()->sll(str2_reg, exact_log2(sizeof(jchar)), str1_reg); // scale the limit
2871 __ bind(Lskip);
2872
2873 // reallocate str1_reg, str2_reg, result_reg
2874 // Note: limit_reg holds the string length pre-scaled by 2
2875 Register limit_reg = str1_reg;
2876 Register chr2_reg = str2_reg;
2877 Register chr1_reg = result_reg;
2878 // tmp{12} are the base pointers
2879
2880 // Is the minimum length zero?
2881 __ cmp(limit_reg, (int)(0 * sizeof(jchar))); // use cast to resolve overloading ambiguity
2882 __ br(Assembler::equal, true, Assembler::pn, Ldone);
2883 __ delayed()->mov(O7, result_reg); // result is difference in lengths
2884
2885 // Load first characters
2886 __ lduh(tmp1_reg, 0, chr1_reg);
2887 __ lduh(tmp2_reg, 0, chr2_reg);
2888
2889 // Compare first characters
2890 __ subcc(chr1_reg, chr2_reg, chr1_reg);
2891 __ br(Assembler::notZero, false, Assembler::pt, Ldone);
2892 assert(chr1_reg == result_reg, "result must be pre-placed");
2893 __ delayed()->nop();
2894
2895 {
2896 // Check after comparing first character to see if strings are equivalent
2897 Label LSkip2;
2898 // Check if the strings start at same location
2899 __ cmp(tmp1_reg, tmp2_reg);
2900 __ brx(Assembler::notEqual, true, Assembler::pt, LSkip2);
2901 __ delayed()->nop();
2902
2903 // Check if the length difference is zero (in O7)
2904 __ cmp(G0, O7);
2905 __ br(Assembler::equal, true, Assembler::pn, Ldone);
2906 __ delayed()->mov(G0, result_reg); // result is zero
2907
2908 // Strings might not be equal
2909 __ bind(LSkip2);
2910 }
2911
2912 __ subcc(limit_reg, 1 * sizeof(jchar), chr1_reg);
2913 __ br(Assembler::equal, true, Assembler::pn, Ldone);
2914 __ delayed()->mov(O7, result_reg); // result is difference in lengths
2915
2916 // Shift tmp1_reg and tmp2_reg to the end of the arrays, negate limit
2917 __ add(tmp1_reg, limit_reg, tmp1_reg);
2918 __ add(tmp2_reg, limit_reg, tmp2_reg);
2919 __ neg(chr1_reg, limit_reg); // limit = -(limit-2)
2920
2921 // Compare the rest of the characters
2922 __ lduh(tmp1_reg, limit_reg, chr1_reg);
2923 __ bind(Lloop);
2924 // __ lduh(tmp1_reg, limit_reg, chr1_reg); // hoisted
2925 __ lduh(tmp2_reg, limit_reg, chr2_reg);
2926 __ subcc(chr1_reg, chr2_reg, chr1_reg);
2927 __ br(Assembler::notZero, false, Assembler::pt, Ldone);
2928 assert(chr1_reg == result_reg, "result must be pre-placed");
2929 __ delayed()->inccc(limit_reg, sizeof(jchar));
2930 // annul LDUH if branch is not taken to prevent access past end of string
2931 __ br(Assembler::notZero, true, Assembler::pt, Lloop);
2932 __ delayed()->lduh(tmp1_reg, limit_reg, chr1_reg); // hoisted
2933
2934 // If strings are equal up to min length, return the length difference.
2935 __ mov(O7, result_reg);
2936
2937 // Otherwise, return the difference between the first mismatched chars.
2938 __ bind(Ldone);
2939 %}
2940
2941 enc_class enc_String_Equals(o0RegP str1, o1RegP str2, g3RegP tmp1, g4RegP tmp2, notemp_iRegI result) %{
2942 Label Lword, Lword_loop, Lpost_word, Lchar, Lchar_loop, Ldone;
2943 MacroAssembler _masm(&cbuf);
2944
2945 Register str1_reg = reg_to_register_object($str1$$reg);
2946 Register str2_reg = reg_to_register_object($str2$$reg);
2947 Register tmp1_reg = reg_to_register_object($tmp1$$reg);
2948 Register tmp2_reg = reg_to_register_object($tmp2$$reg);
2949 Register result_reg = reg_to_register_object($result$$reg);
2950
2951 // Get the first character position in both strings
2952 // [8] char array, [12] offset, [16] count
2953 int value_offset = java_lang_String:: value_offset_in_bytes();
2954 int offset_offset = java_lang_String::offset_offset_in_bytes();
2955 int count_offset = java_lang_String:: count_offset_in_bytes();
2956
2957 // load str1 (jchar*) base address into tmp1_reg
2958 __ load_heap_oop(Address(str1_reg, value_offset), tmp1_reg);
2959 __ ld(Address(str1_reg, offset_offset), result_reg);
2960 __ add(tmp1_reg, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp1_reg);
2961 __ ld(Address(str1_reg, count_offset), str1_reg); // hoisted
2962 __ sll(result_reg, exact_log2(sizeof(jchar)), result_reg);
2963 __ load_heap_oop(Address(str2_reg, value_offset), tmp2_reg); // hoisted
2964 __ add(result_reg, tmp1_reg, tmp1_reg);
2965
2966 // load str2 (jchar*) base address into tmp2_reg
2967 // __ ld_ptr(Address(str2_reg, value_offset), tmp2_reg); // hoisted
2968 __ ld(Address(str2_reg, offset_offset), result_reg);
2969 __ add(tmp2_reg, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp2_reg);
2970 __ ld(Address(str2_reg, count_offset), str2_reg); // hoisted
2971 __ sll(result_reg, exact_log2(sizeof(jchar)), result_reg);
2972 __ cmp(str1_reg, str2_reg); // hoisted
2973 __ add(result_reg, tmp2_reg, tmp2_reg);
2974
2975 __ sll(str1_reg, exact_log2(sizeof(jchar)), str1_reg);
2976 __ br(Assembler::notEqual, true, Assembler::pt, Ldone);
2977 __ delayed()->mov(G0, result_reg); // not equal
2978
2979 __ br_zero(Assembler::equal, true, Assembler::pn, str1_reg, Ldone);
2980 __ delayed()->add(G0, 1, result_reg); //equals
2981
2982 __ cmp(tmp1_reg, tmp2_reg); //same string ?
2983 __ brx(Assembler::equal, true, Assembler::pn, Ldone);
2984 __ delayed()->add(G0, 1, result_reg);
2985
2986 //rename registers
2987 Register limit_reg = str1_reg;
2988 Register chr2_reg = str2_reg;
2989 Register chr1_reg = result_reg;
2990 // tmp{12} are the base pointers
2991
2992 //check for alignment and position the pointers to the ends
2993 __ or3(tmp1_reg, tmp2_reg, chr1_reg);
2994 __ andcc(chr1_reg, 0x3, chr1_reg); // notZero means at least one not 4-byte aligned
2995 __ br(Assembler::notZero, false, Assembler::pn, Lchar);
2996 __ delayed()->nop();
2997
2998 __ bind(Lword);
2999 __ and3(limit_reg, 0x2, O7); //remember the remainder (either 0 or 2)
3000 __ andn(limit_reg, 0x3, limit_reg);
3001 __ br_zero(Assembler::zero, false, Assembler::pn, limit_reg, Lpost_word);
3002 __ delayed()->nop();
3003
3004 __ add(tmp1_reg, limit_reg, tmp1_reg);
3005 __ add(tmp2_reg, limit_reg, tmp2_reg);
3006 __ neg(limit_reg);
3007
3008 __ lduw(tmp1_reg, limit_reg, chr1_reg);
3009 __ bind(Lword_loop);
3010 __ lduw(tmp2_reg, limit_reg, chr2_reg);
3011 __ cmp(chr1_reg, chr2_reg);
3012 __ br(Assembler::notEqual, true, Assembler::pt, Ldone);
3013 __ delayed()->mov(G0, result_reg);
3014 __ inccc(limit_reg, 2*sizeof(jchar));
3015 // annul LDUW if branch i s not taken to prevent access past end of string
3016 __ br(Assembler::notZero, true, Assembler::pt, Lword_loop); //annul on taken
3017 __ delayed()->lduw(tmp1_reg, limit_reg, chr1_reg); // hoisted
3018
3019 __ bind(Lpost_word);
3020 __ br_zero(Assembler::zero, true, Assembler::pt, O7, Ldone);
3021 __ delayed()->add(G0, 1, result_reg);
3022
3023 __ lduh(tmp1_reg, 0, chr1_reg);
3024 __ lduh(tmp2_reg, 0, chr2_reg);
3025 __ cmp (chr1_reg, chr2_reg);
3026 __ br(Assembler::notEqual, true, Assembler::pt, Ldone);
3027 __ delayed()->mov(G0, result_reg);
3028 __ ba(false,Ldone);
3029 __ delayed()->add(G0, 1, result_reg);
3030
3031 __ bind(Lchar);
3032 __ add(tmp1_reg, limit_reg, tmp1_reg);
3033 __ add(tmp2_reg, limit_reg, tmp2_reg);
3034 __ neg(limit_reg); //negate count
3035
3036 __ lduh(tmp1_reg, limit_reg, chr1_reg);
3037 __ bind(Lchar_loop);
3038 __ lduh(tmp2_reg, limit_reg, chr2_reg);
3039 __ cmp(chr1_reg, chr2_reg);
3040 __ br(Assembler::notEqual, true, Assembler::pt, Ldone);
3041 __ delayed()->mov(G0, result_reg); //not equal
3042 __ inccc(limit_reg, sizeof(jchar));
3043 // annul LDUH if branch is not taken to prevent access past end of string
3044 __ br(Assembler::notZero, true, Assembler::pt, Lchar_loop); //annul on taken
3045 __ delayed()->lduh(tmp1_reg, limit_reg, chr1_reg); // hoisted
3046
3047 __ add(G0, 1, result_reg); //equal
3048
3049 __ bind(Ldone);
3050 %}
3051
3052 enc_class enc_Array_Equals(o0RegP ary1, o1RegP ary2, g3RegP tmp1, g4RegP tmp2, notemp_iRegI result) %{
3053 Label Lvector, Ldone, Lloop;
3054 MacroAssembler _masm(&cbuf);
3055
3056 Register ary1_reg = reg_to_register_object($ary1$$reg);
3057 Register ary2_reg = reg_to_register_object($ary2$$reg);
3058 Register tmp1_reg = reg_to_register_object($tmp1$$reg);
3059 Register tmp2_reg = reg_to_register_object($tmp2$$reg);
3060 Register result_reg = reg_to_register_object($result$$reg);
3061
3062 int length_offset = arrayOopDesc::length_offset_in_bytes();
3063 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR);
3064
3065 // return true if the same array
3066 __ cmp(ary1_reg, ary2_reg);
3067 __ br(Assembler::equal, true, Assembler::pn, Ldone);
3068 __ delayed()->add(G0, 1, result_reg); // equal
3069
3070 __ br_null(ary1_reg, true, Assembler::pn, Ldone);
3071 __ delayed()->mov(G0, result_reg); // not equal
3072
3073 __ br_null(ary2_reg, true, Assembler::pn, Ldone);
3074 __ delayed()->mov(G0, result_reg); // not equal
3075
3076 //load the lengths of arrays
3077 __ ld(Address(ary1_reg, length_offset), tmp1_reg);
3078 __ ld(Address(ary2_reg, length_offset), tmp2_reg);
3079
3080 // return false if the two arrays are not equal length
3081 __ cmp(tmp1_reg, tmp2_reg);
3082 __ br(Assembler::notEqual, true, Assembler::pn, Ldone);
3083 __ delayed()->mov(G0, result_reg); // not equal
3084
3085 __ br_zero(Assembler::zero, true, Assembler::pn, tmp1_reg, Ldone);
3086 __ delayed()->add(G0, 1, result_reg); // zero-length arrays are equal
3087
3088 // load array addresses
3089 __ add(ary1_reg, base_offset, ary1_reg);
3090 __ add(ary2_reg, base_offset, ary2_reg);
3091
3092 // renaming registers
3093 Register chr1_reg = tmp2_reg; // for characters in ary1
3094 Register chr2_reg = result_reg; // for characters in ary2
3095 Register limit_reg = tmp1_reg; // length
3096
3097 // set byte count
3098 __ sll(limit_reg, exact_log2(sizeof(jchar)), limit_reg);
3099 __ andcc(limit_reg, 0x2, chr1_reg); //trailing character ?
3100 __ br(Assembler::zero, false, Assembler::pt, Lvector);
3101 __ delayed()->nop();
3102
3103 //compare the trailing char
3104 __ sub(limit_reg, sizeof(jchar), limit_reg);
3105 __ lduh(ary1_reg, limit_reg, chr1_reg);
3106 __ lduh(ary2_reg, limit_reg, chr2_reg);
3107 __ cmp(chr1_reg, chr2_reg);
3108 __ br(Assembler::notEqual, true, Assembler::pt, Ldone);
3109 __ delayed()->mov(G0, result_reg); // not equal
3110
3111 // only one char ?
3112 __ br_zero(Assembler::zero, true, Assembler::pn, limit_reg, Ldone);
3113 __ delayed()->add(G0, 1, result_reg); // zero-length arrays are equal
3114
3115 __ bind(Lvector);
3116 // Shift ary1_reg and ary2_reg to the end of the arrays, negate limit
3117 __ add(ary1_reg, limit_reg, ary1_reg);
3118 __ add(ary2_reg, limit_reg, ary2_reg);
3119 __ neg(limit_reg, limit_reg);
3120
3121 __ lduw(ary1_reg, limit_reg, chr1_reg);
3122 __ bind(Lloop);
3123 __ lduw(ary2_reg, limit_reg, chr2_reg);
3124 __ cmp(chr1_reg, chr2_reg);
3125 __ br(Assembler::notEqual, false, Assembler::pt, Ldone);
3126 __ delayed()->mov(G0, result_reg); // not equal
3127 __ inccc(limit_reg, 2*sizeof(jchar));
3128 // annul LDUW if branch is not taken to prevent access past end of string
3129 __ br(Assembler::notZero, true, Assembler::pt, Lloop); //annul on taken
3130 __ delayed()->lduw(ary1_reg, limit_reg, chr1_reg); // hoisted
3131
3132 __ add(G0, 1, result_reg); // equals
3133
3134 __ bind(Ldone);
3135 %}
3136
3137 enc_class enc_rethrow() %{
3138 cbuf.set_inst_mark();
3139 Register temp_reg = G3;
3140 AddressLiteral rethrow_stub(OptoRuntime::rethrow_stub());
3141 assert(temp_reg != reg_to_register_object(R_I0_num), "temp must not break oop_reg");
3142 MacroAssembler _masm(&cbuf);
3143 #ifdef ASSERT
3144 __ save_frame(0);
3145 AddressLiteral last_rethrow_addrlit(&last_rethrow);
3146 __ sethi(last_rethrow_addrlit, L1);
3147 Address addr(L1, last_rethrow_addrlit.low10());
3148 __ get_pc(L2);
3149 __ inc(L2, 3 * BytesPerInstWord); // skip this & 2 more insns to point at jump_to
3150 __ st_ptr(L2, addr);
3151 __ restore();
3152 #endif
3153 __ JUMP(rethrow_stub, temp_reg, 0); // sethi;jmp
3154 __ delayed()->nop();
3155 %}
3156
3157 enc_class emit_mem_nop() %{
3158 // Generates the instruction LDUXA [o6,g0],#0x82,g0
3159 unsigned int *code = (unsigned int*)cbuf.code_end();
3160 *code = (unsigned int)0xc0839040;
3161 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
3162 %}
3163
3164 enc_class emit_fadd_nop() %{
3165 // Generates the instruction FMOVS f31,f31
3166 unsigned int *code = (unsigned int*)cbuf.code_end();
3167 *code = (unsigned int)0xbfa0003f;
3168 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
3169 %}
3170
3171 enc_class emit_br_nop() %{
3172 // Generates the instruction BPN,PN .
3173 unsigned int *code = (unsigned int*)cbuf.code_end();
3174 *code = (unsigned int)0x00400000;
3175 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
3176 %}
3177
3178 enc_class enc_membar_acquire %{
3179 MacroAssembler _masm(&cbuf);
3180 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::LoadLoad) );
3181 %}
3182
3183 enc_class enc_membar_release %{
3184 MacroAssembler _masm(&cbuf);
3185 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::StoreStore) );
3186 %}
3187
3188 enc_class enc_membar_volatile %{
3189 MacroAssembler _masm(&cbuf);
3190 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad) );
3191 %}
3192
3193 enc_class enc_repl8b( iRegI src, iRegL dst ) %{
3194 MacroAssembler _masm(&cbuf);
3195 Register src_reg = reg_to_register_object($src$$reg);
3196 Register dst_reg = reg_to_register_object($dst$$reg);
3197 __ sllx(src_reg, 56, dst_reg);
3198 __ srlx(dst_reg, 8, O7);
3199 __ or3 (dst_reg, O7, dst_reg);
3200 __ srlx(dst_reg, 16, O7);
3201 __ or3 (dst_reg, O7, dst_reg);
3202 __ srlx(dst_reg, 32, O7);
3203 __ or3 (dst_reg, O7, dst_reg);
3204 %}
3205
3206 enc_class enc_repl4b( iRegI src, iRegL dst ) %{
3207 MacroAssembler _masm(&cbuf);
3208 Register src_reg = reg_to_register_object($src$$reg);
3209 Register dst_reg = reg_to_register_object($dst$$reg);
3210 __ sll(src_reg, 24, dst_reg);
3211 __ srl(dst_reg, 8, O7);
3212 __ or3(dst_reg, O7, dst_reg);
3213 __ srl(dst_reg, 16, O7);
3214 __ or3(dst_reg, O7, dst_reg);
3215 %}
3216
3217 enc_class enc_repl4s( iRegI src, iRegL dst ) %{
3218 MacroAssembler _masm(&cbuf);
3219 Register src_reg = reg_to_register_object($src$$reg);
3220 Register dst_reg = reg_to_register_object($dst$$reg);
3221 __ sllx(src_reg, 48, dst_reg);
3222 __ srlx(dst_reg, 16, O7);
3223 __ or3 (dst_reg, O7, dst_reg);
3224 __ srlx(dst_reg, 32, O7);
3225 __ or3 (dst_reg, O7, dst_reg);
3226 %}
3227
3228 enc_class enc_repl2i( iRegI src, iRegL dst ) %{
3229 MacroAssembler _masm(&cbuf);
3230 Register src_reg = reg_to_register_object($src$$reg);
3231 Register dst_reg = reg_to_register_object($dst$$reg);
3232 __ sllx(src_reg, 32, dst_reg);
3233 __ srlx(dst_reg, 32, O7);
3234 __ or3 (dst_reg, O7, dst_reg);
3235 %}
3236
3237 %}
3238
3239 //----------FRAME--------------------------------------------------------------
3240 // Definition of frame structure and management information.
3241 //
3242 // S T A C K L A Y O U T Allocators stack-slot number
3243 // | (to get allocators register number
3244 // G Owned by | | v add VMRegImpl::stack0)
3245 // r CALLER | |
3246 // o | +--------+ pad to even-align allocators stack-slot
3247 // w V | pad0 | numbers; owned by CALLER
3248 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
3249 // h ^ | in | 5
3250 // | | args | 4 Holes in incoming args owned by SELF
3251 // | | | | 3
3252 // | | +--------+
3253 // V | | old out| Empty on Intel, window on Sparc
3254 // | old |preserve| Must be even aligned.
3255 // | SP-+--------+----> Matcher::_old_SP, 8 (or 16 in LP64)-byte aligned
3256 // | | in | 3 area for Intel ret address
3257 // Owned by |preserve| Empty on Sparc.
3258 // SELF +--------+
3259 // | | pad2 | 2 pad to align old SP
3260 // | +--------+ 1
3261 // | | locks | 0
3262 // | +--------+----> VMRegImpl::stack0, 8 (or 16 in LP64)-byte aligned
3263 // | | pad1 | 11 pad to align new SP
3264 // | +--------+
3265 // | | | 10
3266 // | | spills | 9 spills
3267 // V | | 8 (pad0 slot for callee)
3268 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
3269 // ^ | out | 7
3270 // | | args | 6 Holes in outgoing args owned by CALLEE
3271 // Owned by +--------+
3272 // CALLEE | new out| 6 Empty on Intel, window on Sparc
3273 // | new |preserve| Must be even-aligned.
3274 // | SP-+--------+----> Matcher::_new_SP, even aligned
3275 // | | |
3276 //
3277 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
3278 // known from SELF's arguments and the Java calling convention.
3279 // Region 6-7 is determined per call site.
3280 // Note 2: If the calling convention leaves holes in the incoming argument
3281 // area, those holes are owned by SELF. Holes in the outgoing area
3282 // are owned by the CALLEE. Holes should not be nessecary in the
3283 // incoming area, as the Java calling convention is completely under
3284 // the control of the AD file. Doubles can be sorted and packed to
3285 // avoid holes. Holes in the outgoing arguments may be nessecary for
3286 // varargs C calling conventions.
3287 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
3288 // even aligned with pad0 as needed.
3289 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
3290 // region 6-11 is even aligned; it may be padded out more so that
3291 // the region from SP to FP meets the minimum stack alignment.
3292
3293 frame %{
3294 // What direction does stack grow in (assumed to be same for native & Java)
3295 stack_direction(TOWARDS_LOW);
3296
3297 // These two registers define part of the calling convention
3298 // between compiled code and the interpreter.
3299 inline_cache_reg(R_G5); // Inline Cache Register or methodOop for I2C
3300 interpreter_method_oop_reg(R_G5); // Method Oop Register when calling interpreter
3301
3302 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
3303 cisc_spilling_operand_name(indOffset);
3304
3305 // Number of stack slots consumed by a Monitor enter
3306 #ifdef _LP64
3307 sync_stack_slots(2);
3308 #else
3309 sync_stack_slots(1);
3310 #endif
3311
3312 // Compiled code's Frame Pointer
3313 frame_pointer(R_SP);
3314
3315 // Stack alignment requirement
3316 stack_alignment(StackAlignmentInBytes);
3317 // LP64: Alignment size in bytes (128-bit -> 16 bytes)
3318 // !LP64: Alignment size in bytes (64-bit -> 8 bytes)
3319
3320 // Number of stack slots between incoming argument block and the start of
3321 // a new frame. The PROLOG must add this many slots to the stack. The
3322 // EPILOG must remove this many slots.
3323 in_preserve_stack_slots(0);
3324
3325 // Number of outgoing stack slots killed above the out_preserve_stack_slots
3326 // for calls to C. Supports the var-args backing area for register parms.
3327 // ADLC doesn't support parsing expressions, so I folded the math by hand.
3328 #ifdef _LP64
3329 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (0)) * 2-stack-slots-per-word
3330 varargs_C_out_slots_killed(12);
3331 #else
3332 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (1)) * 1-stack-slots-per-word
3333 varargs_C_out_slots_killed( 7);
3334 #endif
3335
3336 // The after-PROLOG location of the return address. Location of
3337 // return address specifies a type (REG or STACK) and a number
3338 // representing the register number (i.e. - use a register name) or
3339 // stack slot.
3340 return_addr(REG R_I7); // Ret Addr is in register I7
3341
3342 // Body of function which returns an OptoRegs array locating
3343 // arguments either in registers or in stack slots for calling
3344 // java
3345 calling_convention %{
3346 (void) SharedRuntime::java_calling_convention(sig_bt, regs, length, is_outgoing);
3347
3348 %}
3349
3350 // Body of function which returns an OptoRegs array locating
3351 // arguments either in registers or in stack slots for callin
3352 // C.
3353 c_calling_convention %{
3354 // This is obviously always outgoing
3355 (void) SharedRuntime::c_calling_convention(sig_bt, regs, length);
3356 %}
3357
3358 // Location of native (C/C++) and interpreter return values. This is specified to
3359 // be the same as Java. In the 32-bit VM, long values are actually returned from
3360 // native calls in O0:O1 and returned to the interpreter in I0:I1. The copying
3361 // to and from the register pairs is done by the appropriate call and epilog
3362 // opcodes. This simplifies the register allocator.
3363 c_return_value %{
3364 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3365 #ifdef _LP64
3366 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num };
3367 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num};
3368 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num };
3369 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num};
3370 #else // !_LP64
3371 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num };
3372 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num };
3373 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num };
3374 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num };
3375 #endif
3376 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg],
3377 (is_outgoing?lo_out:lo_in)[ideal_reg] );
3378 %}
3379
3380 // Location of compiled Java return values. Same as C
3381 return_value %{
3382 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3383 #ifdef _LP64
3384 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num };
3385 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num};
3386 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num };
3387 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num};
3388 #else // !_LP64
3389 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num };
3390 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num};
3391 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num };
3392 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num};
3393 #endif
3394 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg],
3395 (is_outgoing?lo_out:lo_in)[ideal_reg] );
3396 %}
3397
3398 %}
3399
3400
3401 //----------ATTRIBUTES---------------------------------------------------------
3402 //----------Operand Attributes-------------------------------------------------
3403 op_attrib op_cost(1); // Required cost attribute
3404
3405 //----------Instruction Attributes---------------------------------------------
3406 ins_attrib ins_cost(DEFAULT_COST); // Required cost attribute
3407 ins_attrib ins_size(32); // Required size attribute (in bits)
3408 ins_attrib ins_pc_relative(0); // Required PC Relative flag
3409 ins_attrib ins_short_branch(0); // Required flag: is this instruction a
3410 // non-matching short branch variant of some
3411 // long branch?
3412
3413 //----------OPERANDS-----------------------------------------------------------
3414 // Operand definitions must precede instruction definitions for correct parsing
3415 // in the ADLC because operands constitute user defined types which are used in
3416 // instruction definitions.
3417
3418 //----------Simple Operands----------------------------------------------------
3419 // Immediate Operands
3420 // Integer Immediate: 32-bit
3421 operand immI() %{
3422 match(ConI);
3423
3424 op_cost(0);
3425 // formats are generated automatically for constants and base registers
3426 format %{ %}
3427 interface(CONST_INTER);
3428 %}
3429
3430 // Integer Immediate: 13-bit
3431 operand immI13() %{
3432 predicate(Assembler::is_simm13(n->get_int()));
3433 match(ConI);
3434 op_cost(0);
3435
3436 format %{ %}
3437 interface(CONST_INTER);
3438 %}
3439
3440 // Unsigned (positive) Integer Immediate: 13-bit
3441 operand immU13() %{
3442 predicate((0 <= n->get_int()) && Assembler::is_simm13(n->get_int()));
3443 match(ConI);
3444 op_cost(0);
3445
3446 format %{ %}
3447 interface(CONST_INTER);
3448 %}
3449
3450 // Integer Immediate: 6-bit
3451 operand immU6() %{
3452 predicate(n->get_int() >= 0 && n->get_int() <= 63);
3453 match(ConI);
3454 op_cost(0);
3455 format %{ %}
3456 interface(CONST_INTER);
3457 %}
3458
3459 // Integer Immediate: 11-bit
3460 operand immI11() %{
3461 predicate(Assembler::is_simm(n->get_int(),11));
3462 match(ConI);
3463 op_cost(0);
3464 format %{ %}
3465 interface(CONST_INTER);
3466 %}
3467
3468 // Integer Immediate: 0-bit
3469 operand immI0() %{
3470 predicate(n->get_int() == 0);
3471 match(ConI);
3472 op_cost(0);
3473
3474 format %{ %}
3475 interface(CONST_INTER);
3476 %}
3477
3478 // Integer Immediate: the value 10
3479 operand immI10() %{
3480 predicate(n->get_int() == 10);
3481 match(ConI);
3482 op_cost(0);
3483
3484 format %{ %}
3485 interface(CONST_INTER);
3486 %}
3487
3488 // Integer Immediate: the values 0-31
3489 operand immU5() %{
3490 predicate(n->get_int() >= 0 && n->get_int() <= 31);
3491 match(ConI);
3492 op_cost(0);
3493
3494 format %{ %}
3495 interface(CONST_INTER);
3496 %}
3497
3498 // Integer Immediate: the values 1-31
3499 operand immI_1_31() %{
3500 predicate(n->get_int() >= 1 && n->get_int() <= 31);
3501 match(ConI);
3502 op_cost(0);
3503
3504 format %{ %}
3505 interface(CONST_INTER);
3506 %}
3507
3508 // Integer Immediate: the values 32-63
3509 operand immI_32_63() %{
3510 predicate(n->get_int() >= 32 && n->get_int() <= 63);
3511 match(ConI);
3512 op_cost(0);
3513
3514 format %{ %}
3515 interface(CONST_INTER);
3516 %}
3517
3518 // Integer Immediate: the value 255
3519 operand immI_255() %{
3520 predicate( n->get_int() == 255 );
3521 match(ConI);
3522 op_cost(0);
3523
3524 format %{ %}
3525 interface(CONST_INTER);
3526 %}
3527
3528 // Long Immediate: the value FF
3529 operand immL_FF() %{
3530 predicate( n->get_long() == 0xFFL );
3531 match(ConL);
3532 op_cost(0);
3533
3534 format %{ %}
3535 interface(CONST_INTER);
3536 %}
3537
3538 // Long Immediate: the value FFFF
3539 operand immL_FFFF() %{
3540 predicate( n->get_long() == 0xFFFFL );
3541 match(ConL);
3542 op_cost(0);
3543
3544 format %{ %}
3545 interface(CONST_INTER);
3546 %}
3547
3548 // Pointer Immediate: 32 or 64-bit
3549 operand immP() %{
3550 match(ConP);
3551
3552 op_cost(5);
3553 // formats are generated automatically for constants and base registers
3554 format %{ %}
3555 interface(CONST_INTER);
3556 %}
3557
3558 operand immP13() %{
3559 predicate((-4096 < n->get_ptr()) && (n->get_ptr() <= 4095));
3560 match(ConP);
3561 op_cost(0);
3562
3563 format %{ %}
3564 interface(CONST_INTER);
3565 %}
3566
3567 operand immP0() %{
3568 predicate(n->get_ptr() == 0);
3569 match(ConP);
3570 op_cost(0);
3571
3572 format %{ %}
3573 interface(CONST_INTER);
3574 %}
3575
3576 operand immP_poll() %{
3577 predicate(n->get_ptr() != 0 && n->get_ptr() == (intptr_t)os::get_polling_page());
3578 match(ConP);
3579
3580 // formats are generated automatically for constants and base registers
3581 format %{ %}
3582 interface(CONST_INTER);
3583 %}
3584
3585 // Pointer Immediate
3586 operand immN()
3587 %{
3588 match(ConN);
3589
3590 op_cost(10);
3591 format %{ %}
3592 interface(CONST_INTER);
3593 %}
3594
3595 // NULL Pointer Immediate
3596 operand immN0()
3597 %{
3598 predicate(n->get_narrowcon() == 0);
3599 match(ConN);
3600
3601 op_cost(0);
3602 format %{ %}
3603 interface(CONST_INTER);
3604 %}
3605
3606 operand immL() %{
3607 match(ConL);
3608 op_cost(40);
3609 // formats are generated automatically for constants and base registers
3610 format %{ %}
3611 interface(CONST_INTER);
3612 %}
3613
3614 operand immL0() %{
3615 predicate(n->get_long() == 0L);
3616 match(ConL);
3617 op_cost(0);
3618 // formats are generated automatically for constants and base registers
3619 format %{ %}
3620 interface(CONST_INTER);
3621 %}
3622
3623 // Long Immediate: 13-bit
3624 operand immL13() %{
3625 predicate((-4096L < n->get_long()) && (n->get_long() <= 4095L));
3626 match(ConL);
3627 op_cost(0);
3628
3629 format %{ %}
3630 interface(CONST_INTER);
3631 %}
3632
3633 // Long Immediate: low 32-bit mask
3634 operand immL_32bits() %{
3635 predicate(n->get_long() == 0xFFFFFFFFL);
3636 match(ConL);
3637 op_cost(0);
3638
3639 format %{ %}
3640 interface(CONST_INTER);
3641 %}
3642
3643 // Double Immediate
3644 operand immD() %{
3645 match(ConD);
3646
3647 op_cost(40);
3648 format %{ %}
3649 interface(CONST_INTER);
3650 %}
3651
3652 operand immD0() %{
3653 #ifdef _LP64
3654 // on 64-bit architectures this comparision is faster
3655 predicate(jlong_cast(n->getd()) == 0);
3656 #else
3657 predicate((n->getd() == 0) && (fpclass(n->getd()) == FP_PZERO));
3658 #endif
3659 match(ConD);
3660
3661 op_cost(0);
3662 format %{ %}
3663 interface(CONST_INTER);
3664 %}
3665
3666 // Float Immediate
3667 operand immF() %{
3668 match(ConF);
3669
3670 op_cost(20);
3671 format %{ %}
3672 interface(CONST_INTER);
3673 %}
3674
3675 // Float Immediate: 0
3676 operand immF0() %{
3677 predicate((n->getf() == 0) && (fpclass(n->getf()) == FP_PZERO));
3678 match(ConF);
3679
3680 op_cost(0);
3681 format %{ %}
3682 interface(CONST_INTER);
3683 %}
3684
3685 // Integer Register Operands
3686 // Integer Register
3687 operand iRegI() %{
3688 constraint(ALLOC_IN_RC(int_reg));
3689 match(RegI);
3690
3691 match(notemp_iRegI);
3692 match(g1RegI);
3693 match(o0RegI);
3694 match(iRegIsafe);
3695
3696 format %{ %}
3697 interface(REG_INTER);
3698 %}
3699
3700 operand notemp_iRegI() %{
3701 constraint(ALLOC_IN_RC(notemp_int_reg));
3702 match(RegI);
3703
3704 match(o0RegI);
3705
3706 format %{ %}
3707 interface(REG_INTER);
3708 %}
3709
3710 operand o0RegI() %{
3711 constraint(ALLOC_IN_RC(o0_regI));
3712 match(iRegI);
3713
3714 format %{ %}
3715 interface(REG_INTER);
3716 %}
3717
3718 // Pointer Register
3719 operand iRegP() %{
3720 constraint(ALLOC_IN_RC(ptr_reg));
3721 match(RegP);
3722
3723 match(lock_ptr_RegP);
3724 match(g1RegP);
3725 match(g2RegP);
3726 match(g3RegP);
3727 match(g4RegP);
3728 match(i0RegP);
3729 match(o0RegP);
3730 match(o1RegP);
3731 match(l7RegP);
3732
3733 format %{ %}
3734 interface(REG_INTER);
3735 %}
3736
3737 operand sp_ptr_RegP() %{
3738 constraint(ALLOC_IN_RC(sp_ptr_reg));
3739 match(RegP);
3740 match(iRegP);
3741
3742 format %{ %}
3743 interface(REG_INTER);
3744 %}
3745
3746 operand lock_ptr_RegP() %{
3747 constraint(ALLOC_IN_RC(lock_ptr_reg));
3748 match(RegP);
3749 match(i0RegP);
3750 match(o0RegP);
3751 match(o1RegP);
3752 match(l7RegP);
3753
3754 format %{ %}
3755 interface(REG_INTER);
3756 %}
3757
3758 operand g1RegP() %{
3759 constraint(ALLOC_IN_RC(g1_regP));
3760 match(iRegP);
3761
3762 format %{ %}
3763 interface(REG_INTER);
3764 %}
3765
3766 operand g2RegP() %{
3767 constraint(ALLOC_IN_RC(g2_regP));
3768 match(iRegP);
3769
3770 format %{ %}
3771 interface(REG_INTER);
3772 %}
3773
3774 operand g3RegP() %{
3775 constraint(ALLOC_IN_RC(g3_regP));
3776 match(iRegP);
3777
3778 format %{ %}
3779 interface(REG_INTER);
3780 %}
3781
3782 operand g1RegI() %{
3783 constraint(ALLOC_IN_RC(g1_regI));
3784 match(iRegI);
3785
3786 format %{ %}
3787 interface(REG_INTER);
3788 %}
3789
3790 operand g3RegI() %{
3791 constraint(ALLOC_IN_RC(g3_regI));
3792 match(iRegI);
3793
3794 format %{ %}
3795 interface(REG_INTER);
3796 %}
3797
3798 operand g4RegI() %{
3799 constraint(ALLOC_IN_RC(g4_regI));
3800 match(iRegI);
3801
3802 format %{ %}
3803 interface(REG_INTER);
3804 %}
3805
3806 operand g4RegP() %{
3807 constraint(ALLOC_IN_RC(g4_regP));
3808 match(iRegP);
3809
3810 format %{ %}
3811 interface(REG_INTER);
3812 %}
3813
3814 operand i0RegP() %{
3815 constraint(ALLOC_IN_RC(i0_regP));
3816 match(iRegP);
3817
3818 format %{ %}
3819 interface(REG_INTER);
3820 %}
3821
3822 operand o0RegP() %{
3823 constraint(ALLOC_IN_RC(o0_regP));
3824 match(iRegP);
3825
3826 format %{ %}
3827 interface(REG_INTER);
3828 %}
3829
3830 operand o1RegP() %{
3831 constraint(ALLOC_IN_RC(o1_regP));
3832 match(iRegP);
3833
3834 format %{ %}
3835 interface(REG_INTER);
3836 %}
3837
3838 operand o2RegP() %{
3839 constraint(ALLOC_IN_RC(o2_regP));
3840 match(iRegP);
3841
3842 format %{ %}
3843 interface(REG_INTER);
3844 %}
3845
3846 operand o7RegP() %{
3847 constraint(ALLOC_IN_RC(o7_regP));
3848 match(iRegP);
3849
3850 format %{ %}
3851 interface(REG_INTER);
3852 %}
3853
3854 operand l7RegP() %{
3855 constraint(ALLOC_IN_RC(l7_regP));
3856 match(iRegP);
3857
3858 format %{ %}
3859 interface(REG_INTER);
3860 %}
3861
3862 operand o7RegI() %{
3863 constraint(ALLOC_IN_RC(o7_regI));
3864 match(iRegI);
3865
3866 format %{ %}
3867 interface(REG_INTER);
3868 %}
3869
3870 operand iRegN() %{
3871 constraint(ALLOC_IN_RC(int_reg));
3872 match(RegN);
3873
3874 format %{ %}
3875 interface(REG_INTER);
3876 %}
3877
3878 // Long Register
3879 operand iRegL() %{
3880 constraint(ALLOC_IN_RC(long_reg));
3881 match(RegL);
3882
3883 format %{ %}
3884 interface(REG_INTER);
3885 %}
3886
3887 operand o2RegL() %{
3888 constraint(ALLOC_IN_RC(o2_regL));
3889 match(iRegL);
3890
3891 format %{ %}
3892 interface(REG_INTER);
3893 %}
3894
3895 operand o7RegL() %{
3896 constraint(ALLOC_IN_RC(o7_regL));
3897 match(iRegL);
3898
3899 format %{ %}
3900 interface(REG_INTER);
3901 %}
3902
3903 operand g1RegL() %{
3904 constraint(ALLOC_IN_RC(g1_regL));
3905 match(iRegL);
3906
3907 format %{ %}
3908 interface(REG_INTER);
3909 %}
3910
3911 operand g3RegL() %{
3912 constraint(ALLOC_IN_RC(g3_regL));
3913 match(iRegL);
3914
3915 format %{ %}
3916 interface(REG_INTER);
3917 %}
3918
3919 // Int Register safe
3920 // This is 64bit safe
3921 operand iRegIsafe() %{
3922 constraint(ALLOC_IN_RC(long_reg));
3923
3924 match(iRegI);
3925
3926 format %{ %}
3927 interface(REG_INTER);
3928 %}
3929
3930 // Condition Code Flag Register
3931 operand flagsReg() %{
3932 constraint(ALLOC_IN_RC(int_flags));
3933 match(RegFlags);
3934
3935 format %{ "ccr" %} // both ICC and XCC
3936 interface(REG_INTER);
3937 %}
3938
3939 // Condition Code Register, unsigned comparisons.
3940 operand flagsRegU() %{
3941 constraint(ALLOC_IN_RC(int_flags));
3942 match(RegFlags);
3943
3944 format %{ "icc_U" %}
3945 interface(REG_INTER);
3946 %}
3947
3948 // Condition Code Register, pointer comparisons.
3949 operand flagsRegP() %{
3950 constraint(ALLOC_IN_RC(int_flags));
3951 match(RegFlags);
3952
3953 #ifdef _LP64
3954 format %{ "xcc_P" %}
3955 #else
3956 format %{ "icc_P" %}
3957 #endif
3958 interface(REG_INTER);
3959 %}
3960
3961 // Condition Code Register, long comparisons.
3962 operand flagsRegL() %{
3963 constraint(ALLOC_IN_RC(int_flags));
3964 match(RegFlags);
3965
3966 format %{ "xcc_L" %}
3967 interface(REG_INTER);
3968 %}
3969
3970 // Condition Code Register, floating comparisons, unordered same as "less".
3971 operand flagsRegF() %{
3972 constraint(ALLOC_IN_RC(float_flags));
3973 match(RegFlags);
3974 match(flagsRegF0);
3975
3976 format %{ %}
3977 interface(REG_INTER);
3978 %}
3979
3980 operand flagsRegF0() %{
3981 constraint(ALLOC_IN_RC(float_flag0));
3982 match(RegFlags);
3983
3984 format %{ %}
3985 interface(REG_INTER);
3986 %}
3987
3988
3989 // Condition Code Flag Register used by long compare
3990 operand flagsReg_long_LTGE() %{
3991 constraint(ALLOC_IN_RC(int_flags));
3992 match(RegFlags);
3993 format %{ "icc_LTGE" %}
3994 interface(REG_INTER);
3995 %}
3996 operand flagsReg_long_EQNE() %{
3997 constraint(ALLOC_IN_RC(int_flags));
3998 match(RegFlags);
3999 format %{ "icc_EQNE" %}
4000 interface(REG_INTER);
4001 %}
4002 operand flagsReg_long_LEGT() %{
4003 constraint(ALLOC_IN_RC(int_flags));
4004 match(RegFlags);
4005 format %{ "icc_LEGT" %}
4006 interface(REG_INTER);
4007 %}
4008
4009
4010 operand regD() %{
4011 constraint(ALLOC_IN_RC(dflt_reg));
4012 match(RegD);
4013
4014 match(regD_low);
4015
4016 format %{ %}
4017 interface(REG_INTER);
4018 %}
4019
4020 operand regF() %{
4021 constraint(ALLOC_IN_RC(sflt_reg));
4022 match(RegF);
4023
4024 format %{ %}
4025 interface(REG_INTER);
4026 %}
4027
4028 operand regD_low() %{
4029 constraint(ALLOC_IN_RC(dflt_low_reg));
4030 match(regD);
4031
4032 format %{ %}
4033 interface(REG_INTER);
4034 %}
4035
4036 // Special Registers
4037
4038 // Method Register
4039 operand inline_cache_regP(iRegP reg) %{
4040 constraint(ALLOC_IN_RC(g5_regP)); // G5=inline_cache_reg but uses 2 bits instead of 1
4041 match(reg);
4042 format %{ %}
4043 interface(REG_INTER);
4044 %}
4045
4046 operand interpreter_method_oop_regP(iRegP reg) %{
4047 constraint(ALLOC_IN_RC(g5_regP)); // G5=interpreter_method_oop_reg but uses 2 bits instead of 1
4048 match(reg);
4049 format %{ %}
4050 interface(REG_INTER);
4051 %}
4052
4053
4054 //----------Complex Operands---------------------------------------------------
4055 // Indirect Memory Reference
4056 operand indirect(sp_ptr_RegP reg) %{
4057 constraint(ALLOC_IN_RC(sp_ptr_reg));
4058 match(reg);
4059
4060 op_cost(100);
4061 format %{ "[$reg]" %}
4062 interface(MEMORY_INTER) %{
4063 base($reg);
4064 index(0x0);
4065 scale(0x0);
4066 disp(0x0);
4067 %}
4068 %}
4069
4070 // Indirect with Offset
4071 operand indOffset13(sp_ptr_RegP reg, immX13 offset) %{
4072 constraint(ALLOC_IN_RC(sp_ptr_reg));
4073 match(AddP reg offset);
4074
4075 op_cost(100);
4076 format %{ "[$reg + $offset]" %}
4077 interface(MEMORY_INTER) %{
4078 base($reg);
4079 index(0x0);
4080 scale(0x0);
4081 disp($offset);
4082 %}
4083 %}
4084
4085 // Note: Intel has a swapped version also, like this:
4086 //operand indOffsetX(iRegI reg, immP offset) %{
4087 // constraint(ALLOC_IN_RC(int_reg));
4088 // match(AddP offset reg);
4089 //
4090 // op_cost(100);
4091 // format %{ "[$reg + $offset]" %}
4092 // interface(MEMORY_INTER) %{
4093 // base($reg);
4094 // index(0x0);
4095 // scale(0x0);
4096 // disp($offset);
4097 // %}
4098 //%}
4099 //// However, it doesn't make sense for SPARC, since
4100 // we have no particularly good way to embed oops in
4101 // single instructions.
4102
4103 // Indirect with Register Index
4104 operand indIndex(iRegP addr, iRegX index) %{
4105 constraint(ALLOC_IN_RC(ptr_reg));
4106 match(AddP addr index);
4107
4108 op_cost(100);
4109 format %{ "[$addr + $index]" %}
4110 interface(MEMORY_INTER) %{
4111 base($addr);
4112 index($index);
4113 scale(0x0);
4114 disp(0x0);
4115 %}
4116 %}
4117
4118 //----------Special Memory Operands--------------------------------------------
4119 // Stack Slot Operand - This operand is used for loading and storing temporary
4120 // values on the stack where a match requires a value to
4121 // flow through memory.
4122 operand stackSlotI(sRegI reg) %{
4123 constraint(ALLOC_IN_RC(stack_slots));
4124 op_cost(100);
4125 //match(RegI);
4126 format %{ "[$reg]" %}
4127 interface(MEMORY_INTER) %{
4128 base(0xE); // R_SP
4129 index(0x0);
4130 scale(0x0);
4131 disp($reg); // Stack Offset
4132 %}
4133 %}
4134
4135 operand stackSlotP(sRegP reg) %{
4136 constraint(ALLOC_IN_RC(stack_slots));
4137 op_cost(100);
4138 //match(RegP);
4139 format %{ "[$reg]" %}
4140 interface(MEMORY_INTER) %{
4141 base(0xE); // R_SP
4142 index(0x0);
4143 scale(0x0);
4144 disp($reg); // Stack Offset
4145 %}
4146 %}
4147
4148 operand stackSlotF(sRegF reg) %{
4149 constraint(ALLOC_IN_RC(stack_slots));
4150 op_cost(100);
4151 //match(RegF);
4152 format %{ "[$reg]" %}
4153 interface(MEMORY_INTER) %{
4154 base(0xE); // R_SP
4155 index(0x0);
4156 scale(0x0);
4157 disp($reg); // Stack Offset
4158 %}
4159 %}
4160 operand stackSlotD(sRegD reg) %{
4161 constraint(ALLOC_IN_RC(stack_slots));
4162 op_cost(100);
4163 //match(RegD);
4164 format %{ "[$reg]" %}
4165 interface(MEMORY_INTER) %{
4166 base(0xE); // R_SP
4167 index(0x0);
4168 scale(0x0);
4169 disp($reg); // Stack Offset
4170 %}
4171 %}
4172 operand stackSlotL(sRegL reg) %{
4173 constraint(ALLOC_IN_RC(stack_slots));
4174 op_cost(100);
4175 //match(RegL);
4176 format %{ "[$reg]" %}
4177 interface(MEMORY_INTER) %{
4178 base(0xE); // R_SP
4179 index(0x0);
4180 scale(0x0);
4181 disp($reg); // Stack Offset
4182 %}
4183 %}
4184
4185 // Operands for expressing Control Flow
4186 // NOTE: Label is a predefined operand which should not be redefined in
4187 // the AD file. It is generically handled within the ADLC.
4188
4189 //----------Conditional Branch Operands----------------------------------------
4190 // Comparison Op - This is the operation of the comparison, and is limited to
4191 // the following set of codes:
4192 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
4193 //
4194 // Other attributes of the comparison, such as unsignedness, are specified
4195 // by the comparison instruction that sets a condition code flags register.
4196 // That result is represented by a flags operand whose subtype is appropriate
4197 // to the unsignedness (etc.) of the comparison.
4198 //
4199 // Later, the instruction which matches both the Comparison Op (a Bool) and
4200 // the flags (produced by the Cmp) specifies the coding of the comparison op
4201 // by matching a specific subtype of Bool operand below, such as cmpOpU.
4202
4203 operand cmpOp() %{
4204 match(Bool);
4205
4206 format %{ "" %}
4207 interface(COND_INTER) %{
4208 equal(0x1);
4209 not_equal(0x9);
4210 less(0x3);
4211 greater_equal(0xB);
4212 less_equal(0x2);
4213 greater(0xA);
4214 %}
4215 %}
4216
4217 // Comparison Op, unsigned
4218 operand cmpOpU() %{
4219 match(Bool);
4220
4221 format %{ "u" %}
4222 interface(COND_INTER) %{
4223 equal(0x1);
4224 not_equal(0x9);
4225 less(0x5);
4226 greater_equal(0xD);
4227 less_equal(0x4);
4228 greater(0xC);
4229 %}
4230 %}
4231
4232 // Comparison Op, pointer (same as unsigned)
4233 operand cmpOpP() %{
4234 match(Bool);
4235
4236 format %{ "p" %}
4237 interface(COND_INTER) %{
4238 equal(0x1);
4239 not_equal(0x9);
4240 less(0x5);
4241 greater_equal(0xD);
4242 less_equal(0x4);
4243 greater(0xC);
4244 %}
4245 %}
4246
4247 // Comparison Op, branch-register encoding
4248 operand cmpOp_reg() %{
4249 match(Bool);
4250
4251 format %{ "" %}
4252 interface(COND_INTER) %{
4253 equal (0x1);
4254 not_equal (0x5);
4255 less (0x3);
4256 greater_equal(0x7);
4257 less_equal (0x2);
4258 greater (0x6);
4259 %}
4260 %}
4261
4262 // Comparison Code, floating, unordered same as less
4263 operand cmpOpF() %{
4264 match(Bool);
4265
4266 format %{ "fl" %}
4267 interface(COND_INTER) %{
4268 equal(0x9);
4269 not_equal(0x1);
4270 less(0x3);
4271 greater_equal(0xB);
4272 less_equal(0xE);
4273 greater(0x6);
4274 %}
4275 %}
4276
4277 // Used by long compare
4278 operand cmpOp_commute() %{
4279 match(Bool);
4280
4281 format %{ "" %}
4282 interface(COND_INTER) %{
4283 equal(0x1);
4284 not_equal(0x9);
4285 less(0xA);
4286 greater_equal(0x2);
4287 less_equal(0xB);
4288 greater(0x3);
4289 %}
4290 %}
4291
4292 //----------OPERAND CLASSES----------------------------------------------------
4293 // Operand Classes are groups of operands that are used to simplify
4294 // instruction definitions by not requiring the AD writer to specify separate
4295 // instructions for every form of operand when the instruction accepts
4296 // multiple operand types with the same basic encoding and format. The classic
4297 // case of this is memory operands.
4298 // Indirect is not included since its use is limited to Compare & Swap
4299 opclass memory( indirect, indOffset13, indIndex );
4300
4301 //----------PIPELINE-----------------------------------------------------------
4302 pipeline %{
4303
4304 //----------ATTRIBUTES---------------------------------------------------------
4305 attributes %{
4306 fixed_size_instructions; // Fixed size instructions
4307 branch_has_delay_slot; // Branch has delay slot following
4308 max_instructions_per_bundle = 4; // Up to 4 instructions per bundle
4309 instruction_unit_size = 4; // An instruction is 4 bytes long
4310 instruction_fetch_unit_size = 16; // The processor fetches one line
4311 instruction_fetch_units = 1; // of 16 bytes
4312
4313 // List of nop instructions
4314 nops( Nop_A0, Nop_A1, Nop_MS, Nop_FA, Nop_BR );
4315 %}
4316
4317 //----------RESOURCES----------------------------------------------------------
4318 // Resources are the functional units available to the machine
4319 resources(A0, A1, MS, BR, FA, FM, IDIV, FDIV, IALU = A0 | A1);
4320
4321 //----------PIPELINE DESCRIPTION-----------------------------------------------
4322 // Pipeline Description specifies the stages in the machine's pipeline
4323
4324 pipe_desc(A, P, F, B, I, J, S, R, E, C, M, W, X, T, D);
4325
4326 //----------PIPELINE CLASSES---------------------------------------------------
4327 // Pipeline Classes describe the stages in which input and output are
4328 // referenced by the hardware pipeline.
4329
4330 // Integer ALU reg-reg operation
4331 pipe_class ialu_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
4332 single_instruction;
4333 dst : E(write);
4334 src1 : R(read);
4335 src2 : R(read);
4336 IALU : R;
4337 %}
4338
4339 // Integer ALU reg-reg long operation
4340 pipe_class ialu_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{
4341 instruction_count(2);
4342 dst : E(write);
4343 src1 : R(read);
4344 src2 : R(read);
4345 IALU : R;
4346 IALU : R;
4347 %}
4348
4349 // Integer ALU reg-reg long dependent operation
4350 pipe_class ialu_reg_reg_2_dep(iRegL dst, iRegL src1, iRegL src2, flagsReg cr) %{
4351 instruction_count(1); multiple_bundles;
4352 dst : E(write);
4353 src1 : R(read);
4354 src2 : R(read);
4355 cr : E(write);
4356 IALU : R(2);
4357 %}
4358
4359 // Integer ALU reg-imm operaion
4360 pipe_class ialu_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{
4361 single_instruction;
4362 dst : E(write);
4363 src1 : R(read);
4364 IALU : R;
4365 %}
4366
4367 // Integer ALU reg-reg operation with condition code
4368 pipe_class ialu_cc_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
4369 single_instruction;
4370 dst : E(write);
4371 cr : E(write);
4372 src1 : R(read);
4373 src2 : R(read);
4374 IALU : R;
4375 %}
4376
4377 // Integer ALU reg-imm operation with condition code
4378 pipe_class ialu_cc_reg_imm(iRegI dst, iRegI src1, immI13 src2, flagsReg cr) %{
4379 single_instruction;
4380 dst : E(write);
4381 cr : E(write);
4382 src1 : R(read);
4383 IALU : R;
4384 %}
4385
4386 // Integer ALU zero-reg operation
4387 pipe_class ialu_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{
4388 single_instruction;
4389 dst : E(write);
4390 src2 : R(read);
4391 IALU : R;
4392 %}
4393
4394 // Integer ALU zero-reg operation with condition code only
4395 pipe_class ialu_cconly_zero_reg(flagsReg cr, iRegI src) %{
4396 single_instruction;
4397 cr : E(write);
4398 src : R(read);
4399 IALU : R;
4400 %}
4401
4402 // Integer ALU reg-reg operation with condition code only
4403 pipe_class ialu_cconly_reg_reg(flagsReg cr, iRegI src1, iRegI src2) %{
4404 single_instruction;
4405 cr : E(write);
4406 src1 : R(read);
4407 src2 : R(read);
4408 IALU : R;
4409 %}
4410
4411 // Integer ALU reg-imm operation with condition code only
4412 pipe_class ialu_cconly_reg_imm(flagsReg cr, iRegI src1, immI13 src2) %{
4413 single_instruction;
4414 cr : E(write);
4415 src1 : R(read);
4416 IALU : R;
4417 %}
4418
4419 // Integer ALU reg-reg-zero operation with condition code only
4420 pipe_class ialu_cconly_reg_reg_zero(flagsReg cr, iRegI src1, iRegI src2, immI0 zero) %{
4421 single_instruction;
4422 cr : E(write);
4423 src1 : R(read);
4424 src2 : R(read);
4425 IALU : R;
4426 %}
4427
4428 // Integer ALU reg-imm-zero operation with condition code only
4429 pipe_class ialu_cconly_reg_imm_zero(flagsReg cr, iRegI src1, immI13 src2, immI0 zero) %{
4430 single_instruction;
4431 cr : E(write);
4432 src1 : R(read);
4433 IALU : R;
4434 %}
4435
4436 // Integer ALU reg-reg operation with condition code, src1 modified
4437 pipe_class ialu_cc_rwreg_reg(flagsReg cr, iRegI src1, iRegI src2) %{
4438 single_instruction;
4439 cr : E(write);
4440 src1 : E(write);
4441 src1 : R(read);
4442 src2 : R(read);
4443 IALU : R;
4444 %}
4445
4446 // Integer ALU reg-imm operation with condition code, src1 modified
4447 pipe_class ialu_cc_rwreg_imm(flagsReg cr, iRegI src1, immI13 src2) %{
4448 single_instruction;
4449 cr : E(write);
4450 src1 : E(write);
4451 src1 : R(read);
4452 IALU : R;
4453 %}
4454
4455 pipe_class cmpL_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg cr ) %{
4456 multiple_bundles;
4457 dst : E(write)+4;
4458 cr : E(write);
4459 src1 : R(read);
4460 src2 : R(read);
4461 IALU : R(3);
4462 BR : R(2);
4463 %}
4464
4465 // Integer ALU operation
4466 pipe_class ialu_none(iRegI dst) %{
4467 single_instruction;
4468 dst : E(write);
4469 IALU : R;
4470 %}
4471
4472 // Integer ALU reg operation
4473 pipe_class ialu_reg(iRegI dst, iRegI src) %{
4474 single_instruction; may_have_no_code;
4475 dst : E(write);
4476 src : R(read);
4477 IALU : R;
4478 %}
4479
4480 // Integer ALU reg conditional operation
4481 // This instruction has a 1 cycle stall, and cannot execute
4482 // in the same cycle as the instruction setting the condition
4483 // code. We kludge this by pretending to read the condition code
4484 // 1 cycle earlier, and by marking the functional units as busy
4485 // for 2 cycles with the result available 1 cycle later than
4486 // is really the case.
4487 pipe_class ialu_reg_flags( iRegI op2_out, iRegI op2_in, iRegI op1, flagsReg cr ) %{
4488 single_instruction;
4489 op2_out : C(write);
4490 op1 : R(read);
4491 cr : R(read); // This is really E, with a 1 cycle stall
4492 BR : R(2);
4493 MS : R(2);
4494 %}
4495
4496 #ifdef _LP64
4497 pipe_class ialu_clr_and_mover( iRegI dst, iRegP src ) %{
4498 instruction_count(1); multiple_bundles;
4499 dst : C(write)+1;
4500 src : R(read)+1;
4501 IALU : R(1);
4502 BR : E(2);
4503 MS : E(2);
4504 %}
4505 #endif
4506
4507 // Integer ALU reg operation
4508 pipe_class ialu_move_reg_L_to_I(iRegI dst, iRegL src) %{
4509 single_instruction; may_have_no_code;
4510 dst : E(write);
4511 src : R(read);
4512 IALU : R;
4513 %}
4514 pipe_class ialu_move_reg_I_to_L(iRegL dst, iRegI src) %{
4515 single_instruction; may_have_no_code;
4516 dst : E(write);
4517 src : R(read);
4518 IALU : R;
4519 %}
4520
4521 // Two integer ALU reg operations
4522 pipe_class ialu_reg_2(iRegL dst, iRegL src) %{
4523 instruction_count(2);
4524 dst : E(write);
4525 src : R(read);
4526 A0 : R;
4527 A1 : R;
4528 %}
4529
4530 // Two integer ALU reg operations
4531 pipe_class ialu_move_reg_L_to_L(iRegL dst, iRegL src) %{
4532 instruction_count(2); may_have_no_code;
4533 dst : E(write);
4534 src : R(read);
4535 A0 : R;
4536 A1 : R;
4537 %}
4538
4539 // Integer ALU imm operation
4540 pipe_class ialu_imm(iRegI dst, immI13 src) %{
4541 single_instruction;
4542 dst : E(write);
4543 IALU : R;
4544 %}
4545
4546 // Integer ALU reg-reg with carry operation
4547 pipe_class ialu_reg_reg_cy(iRegI dst, iRegI src1, iRegI src2, iRegI cy) %{
4548 single_instruction;
4549 dst : E(write);
4550 src1 : R(read);
4551 src2 : R(read);
4552 IALU : R;
4553 %}
4554
4555 // Integer ALU cc operation
4556 pipe_class ialu_cc(iRegI dst, flagsReg cc) %{
4557 single_instruction;
4558 dst : E(write);
4559 cc : R(read);
4560 IALU : R;
4561 %}
4562
4563 // Integer ALU cc / second IALU operation
4564 pipe_class ialu_reg_ialu( iRegI dst, iRegI src ) %{
4565 instruction_count(1); multiple_bundles;
4566 dst : E(write)+1;
4567 src : R(read);
4568 IALU : R;
4569 %}
4570
4571 // Integer ALU cc / second IALU operation
4572 pipe_class ialu_reg_reg_ialu( iRegI dst, iRegI p, iRegI q ) %{
4573 instruction_count(1); multiple_bundles;
4574 dst : E(write)+1;
4575 p : R(read);
4576 q : R(read);
4577 IALU : R;
4578 %}
4579
4580 // Integer ALU hi-lo-reg operation
4581 pipe_class ialu_hi_lo_reg(iRegI dst, immI src) %{
4582 instruction_count(1); multiple_bundles;
4583 dst : E(write)+1;
4584 IALU : R(2);
4585 %}
4586
4587 // Float ALU hi-lo-reg operation (with temp)
4588 pipe_class ialu_hi_lo_reg_temp(regF dst, immF src, g3RegP tmp) %{
4589 instruction_count(1); multiple_bundles;
4590 dst : E(write)+1;
4591 IALU : R(2);
4592 %}
4593
4594 // Long Constant
4595 pipe_class loadConL( iRegL dst, immL src ) %{
4596 instruction_count(2); multiple_bundles;
4597 dst : E(write)+1;
4598 IALU : R(2);
4599 IALU : R(2);
4600 %}
4601
4602 // Pointer Constant
4603 pipe_class loadConP( iRegP dst, immP src ) %{
4604 instruction_count(0); multiple_bundles;
4605 fixed_latency(6);
4606 %}
4607
4608 // Polling Address
4609 pipe_class loadConP_poll( iRegP dst, immP_poll src ) %{
4610 #ifdef _LP64
4611 instruction_count(0); multiple_bundles;
4612 fixed_latency(6);
4613 #else
4614 dst : E(write);
4615 IALU : R;
4616 #endif
4617 %}
4618
4619 // Long Constant small
4620 pipe_class loadConLlo( iRegL dst, immL src ) %{
4621 instruction_count(2);
4622 dst : E(write);
4623 IALU : R;
4624 IALU : R;
4625 %}
4626
4627 // [PHH] This is wrong for 64-bit. See LdImmF/D.
4628 pipe_class loadConFD(regF dst, immF src, g3RegP tmp) %{
4629 instruction_count(1); multiple_bundles;
4630 src : R(read);
4631 dst : M(write)+1;
4632 IALU : R;
4633 MS : E;
4634 %}
4635
4636 // Integer ALU nop operation
4637 pipe_class ialu_nop() %{
4638 single_instruction;
4639 IALU : R;
4640 %}
4641
4642 // Integer ALU nop operation
4643 pipe_class ialu_nop_A0() %{
4644 single_instruction;
4645 A0 : R;
4646 %}
4647
4648 // Integer ALU nop operation
4649 pipe_class ialu_nop_A1() %{
4650 single_instruction;
4651 A1 : R;
4652 %}
4653
4654 // Integer Multiply reg-reg operation
4655 pipe_class imul_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
4656 single_instruction;
4657 dst : E(write);
4658 src1 : R(read);
4659 src2 : R(read);
4660 MS : R(5);
4661 %}
4662
4663 // Integer Multiply reg-imm operation
4664 pipe_class imul_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{
4665 single_instruction;
4666 dst : E(write);
4667 src1 : R(read);
4668 MS : R(5);
4669 %}
4670
4671 pipe_class mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
4672 single_instruction;
4673 dst : E(write)+4;
4674 src1 : R(read);
4675 src2 : R(read);
4676 MS : R(6);
4677 %}
4678
4679 pipe_class mulL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{
4680 single_instruction;
4681 dst : E(write)+4;
4682 src1 : R(read);
4683 MS : R(6);
4684 %}
4685
4686 // Integer Divide reg-reg
4687 pipe_class sdiv_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI temp, flagsReg cr) %{
4688 instruction_count(1); multiple_bundles;
4689 dst : E(write);
4690 temp : E(write);
4691 src1 : R(read);
4692 src2 : R(read);
4693 temp : R(read);
4694 MS : R(38);
4695 %}
4696
4697 // Integer Divide reg-imm
4698 pipe_class sdiv_reg_imm(iRegI dst, iRegI src1, immI13 src2, iRegI temp, flagsReg cr) %{
4699 instruction_count(1); multiple_bundles;
4700 dst : E(write);
4701 temp : E(write);
4702 src1 : R(read);
4703 temp : R(read);
4704 MS : R(38);
4705 %}
4706
4707 // Long Divide
4708 pipe_class divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
4709 dst : E(write)+71;
4710 src1 : R(read);
4711 src2 : R(read)+1;
4712 MS : R(70);
4713 %}
4714
4715 pipe_class divL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{
4716 dst : E(write)+71;
4717 src1 : R(read);
4718 MS : R(70);
4719 %}
4720
4721 // Floating Point Add Float
4722 pipe_class faddF_reg_reg(regF dst, regF src1, regF src2) %{
4723 single_instruction;
4724 dst : X(write);
4725 src1 : E(read);
4726 src2 : E(read);
4727 FA : R;
4728 %}
4729
4730 // Floating Point Add Double
4731 pipe_class faddD_reg_reg(regD dst, regD src1, regD src2) %{
4732 single_instruction;
4733 dst : X(write);
4734 src1 : E(read);
4735 src2 : E(read);
4736 FA : R;
4737 %}
4738
4739 // Floating Point Conditional Move based on integer flags
4740 pipe_class int_conditional_float_move (cmpOp cmp, flagsReg cr, regF dst, regF src) %{
4741 single_instruction;
4742 dst : X(write);
4743 src : E(read);
4744 cr : R(read);
4745 FA : R(2);
4746 BR : R(2);
4747 %}
4748
4749 // Floating Point Conditional Move based on integer flags
4750 pipe_class int_conditional_double_move (cmpOp cmp, flagsReg cr, regD dst, regD src) %{
4751 single_instruction;
4752 dst : X(write);
4753 src : E(read);
4754 cr : R(read);
4755 FA : R(2);
4756 BR : R(2);
4757 %}
4758
4759 // Floating Point Multiply Float
4760 pipe_class fmulF_reg_reg(regF dst, regF src1, regF src2) %{
4761 single_instruction;
4762 dst : X(write);
4763 src1 : E(read);
4764 src2 : E(read);
4765 FM : R;
4766 %}
4767
4768 // Floating Point Multiply Double
4769 pipe_class fmulD_reg_reg(regD dst, regD src1, regD src2) %{
4770 single_instruction;
4771 dst : X(write);
4772 src1 : E(read);
4773 src2 : E(read);
4774 FM : R;
4775 %}
4776
4777 // Floating Point Divide Float
4778 pipe_class fdivF_reg_reg(regF dst, regF src1, regF src2) %{
4779 single_instruction;
4780 dst : X(write);
4781 src1 : E(read);
4782 src2 : E(read);
4783 FM : R;
4784 FDIV : C(14);
4785 %}
4786
4787 // Floating Point Divide Double
4788 pipe_class fdivD_reg_reg(regD dst, regD src1, regD src2) %{
4789 single_instruction;
4790 dst : X(write);
4791 src1 : E(read);
4792 src2 : E(read);
4793 FM : R;
4794 FDIV : C(17);
4795 %}
4796
4797 // Floating Point Move/Negate/Abs Float
4798 pipe_class faddF_reg(regF dst, regF src) %{
4799 single_instruction;
4800 dst : W(write);
4801 src : E(read);
4802 FA : R(1);
4803 %}
4804
4805 // Floating Point Move/Negate/Abs Double
4806 pipe_class faddD_reg(regD dst, regD src) %{
4807 single_instruction;
4808 dst : W(write);
4809 src : E(read);
4810 FA : R;
4811 %}
4812
4813 // Floating Point Convert F->D
4814 pipe_class fcvtF2D(regD dst, regF src) %{
4815 single_instruction;
4816 dst : X(write);
4817 src : E(read);
4818 FA : R;
4819 %}
4820
4821 // Floating Point Convert I->D
4822 pipe_class fcvtI2D(regD dst, regF src) %{
4823 single_instruction;
4824 dst : X(write);
4825 src : E(read);
4826 FA : R;
4827 %}
4828
4829 // Floating Point Convert LHi->D
4830 pipe_class fcvtLHi2D(regD dst, regD src) %{
4831 single_instruction;
4832 dst : X(write);
4833 src : E(read);
4834 FA : R;
4835 %}
4836
4837 // Floating Point Convert L->D
4838 pipe_class fcvtL2D(regD dst, regF src) %{
4839 single_instruction;
4840 dst : X(write);
4841 src : E(read);
4842 FA : R;
4843 %}
4844
4845 // Floating Point Convert L->F
4846 pipe_class fcvtL2F(regD dst, regF src) %{
4847 single_instruction;
4848 dst : X(write);
4849 src : E(read);
4850 FA : R;
4851 %}
4852
4853 // Floating Point Convert D->F
4854 pipe_class fcvtD2F(regD dst, regF src) %{
4855 single_instruction;
4856 dst : X(write);
4857 src : E(read);
4858 FA : R;
4859 %}
4860
4861 // Floating Point Convert I->L
4862 pipe_class fcvtI2L(regD dst, regF src) %{
4863 single_instruction;
4864 dst : X(write);
4865 src : E(read);
4866 FA : R;
4867 %}
4868
4869 // Floating Point Convert D->F
4870 pipe_class fcvtD2I(regF dst, regD src, flagsReg cr) %{
4871 instruction_count(1); multiple_bundles;
4872 dst : X(write)+6;
4873 src : E(read);
4874 FA : R;
4875 %}
4876
4877 // Floating Point Convert D->L
4878 pipe_class fcvtD2L(regD dst, regD src, flagsReg cr) %{
4879 instruction_count(1); multiple_bundles;
4880 dst : X(write)+6;
4881 src : E(read);
4882 FA : R;
4883 %}
4884
4885 // Floating Point Convert F->I
4886 pipe_class fcvtF2I(regF dst, regF src, flagsReg cr) %{
4887 instruction_count(1); multiple_bundles;
4888 dst : X(write)+6;
4889 src : E(read);
4890 FA : R;
4891 %}
4892
4893 // Floating Point Convert F->L
4894 pipe_class fcvtF2L(regD dst, regF src, flagsReg cr) %{
4895 instruction_count(1); multiple_bundles;
4896 dst : X(write)+6;
4897 src : E(read);
4898 FA : R;
4899 %}
4900
4901 // Floating Point Convert I->F
4902 pipe_class fcvtI2F(regF dst, regF src) %{
4903 single_instruction;
4904 dst : X(write);
4905 src : E(read);
4906 FA : R;
4907 %}
4908
4909 // Floating Point Compare
4910 pipe_class faddF_fcc_reg_reg_zero(flagsRegF cr, regF src1, regF src2, immI0 zero) %{
4911 single_instruction;
4912 cr : X(write);
4913 src1 : E(read);
4914 src2 : E(read);
4915 FA : R;
4916 %}
4917
4918 // Floating Point Compare
4919 pipe_class faddD_fcc_reg_reg_zero(flagsRegF cr, regD src1, regD src2, immI0 zero) %{
4920 single_instruction;
4921 cr : X(write);
4922 src1 : E(read);
4923 src2 : E(read);
4924 FA : R;
4925 %}
4926
4927 // Floating Add Nop
4928 pipe_class fadd_nop() %{
4929 single_instruction;
4930 FA : R;
4931 %}
4932
4933 // Integer Store to Memory
4934 pipe_class istore_mem_reg(memory mem, iRegI src) %{
4935 single_instruction;
4936 mem : R(read);
4937 src : C(read);
4938 MS : R;
4939 %}
4940
4941 // Integer Store to Memory
4942 pipe_class istore_mem_spORreg(memory mem, sp_ptr_RegP src) %{
4943 single_instruction;
4944 mem : R(read);
4945 src : C(read);
4946 MS : R;
4947 %}
4948
4949 // Integer Store Zero to Memory
4950 pipe_class istore_mem_zero(memory mem, immI0 src) %{
4951 single_instruction;
4952 mem : R(read);
4953 MS : R;
4954 %}
4955
4956 // Special Stack Slot Store
4957 pipe_class istore_stk_reg(stackSlotI stkSlot, iRegI src) %{
4958 single_instruction;
4959 stkSlot : R(read);
4960 src : C(read);
4961 MS : R;
4962 %}
4963
4964 // Special Stack Slot Store
4965 pipe_class lstoreI_stk_reg(stackSlotL stkSlot, iRegI src) %{
4966 instruction_count(2); multiple_bundles;
4967 stkSlot : R(read);
4968 src : C(read);
4969 MS : R(2);
4970 %}
4971
4972 // Float Store
4973 pipe_class fstoreF_mem_reg(memory mem, RegF src) %{
4974 single_instruction;
4975 mem : R(read);
4976 src : C(read);
4977 MS : R;
4978 %}
4979
4980 // Float Store
4981 pipe_class fstoreF_mem_zero(memory mem, immF0 src) %{
4982 single_instruction;
4983 mem : R(read);
4984 MS : R;
4985 %}
4986
4987 // Double Store
4988 pipe_class fstoreD_mem_reg(memory mem, RegD src) %{
4989 instruction_count(1);
4990 mem : R(read);
4991 src : C(read);
4992 MS : R;
4993 %}
4994
4995 // Double Store
4996 pipe_class fstoreD_mem_zero(memory mem, immD0 src) %{
4997 single_instruction;
4998 mem : R(read);
4999 MS : R;
5000 %}
5001
5002 // Special Stack Slot Float Store
5003 pipe_class fstoreF_stk_reg(stackSlotI stkSlot, RegF src) %{
5004 single_instruction;
5005 stkSlot : R(read);
5006 src : C(read);
5007 MS : R;
5008 %}
5009
5010 // Special Stack Slot Double Store
5011 pipe_class fstoreD_stk_reg(stackSlotI stkSlot, RegD src) %{
5012 single_instruction;
5013 stkSlot : R(read);
5014 src : C(read);
5015 MS : R;
5016 %}
5017
5018 // Integer Load (when sign bit propagation not needed)
5019 pipe_class iload_mem(iRegI dst, memory mem) %{
5020 single_instruction;
5021 mem : R(read);
5022 dst : C(write);
5023 MS : R;
5024 %}
5025
5026 // Integer Load from stack operand
5027 pipe_class iload_stkD(iRegI dst, stackSlotD mem ) %{
5028 single_instruction;
5029 mem : R(read);
5030 dst : C(write);
5031 MS : R;
5032 %}
5033
5034 // Integer Load (when sign bit propagation or masking is needed)
5035 pipe_class iload_mask_mem(iRegI dst, memory mem) %{
5036 single_instruction;
5037 mem : R(read);
5038 dst : M(write);
5039 MS : R;
5040 %}
5041
5042 // Float Load
5043 pipe_class floadF_mem(regF dst, memory mem) %{
5044 single_instruction;
5045 mem : R(read);
5046 dst : M(write);
5047 MS : R;
5048 %}
5049
5050 // Float Load
5051 pipe_class floadD_mem(regD dst, memory mem) %{
5052 instruction_count(1); multiple_bundles; // Again, unaligned argument is only multiple case
5053 mem : R(read);
5054 dst : M(write);
5055 MS : R;
5056 %}
5057
5058 // Float Load
5059 pipe_class floadF_stk(regF dst, stackSlotI stkSlot) %{
5060 single_instruction;
5061 stkSlot : R(read);
5062 dst : M(write);
5063 MS : R;
5064 %}
5065
5066 // Float Load
5067 pipe_class floadD_stk(regD dst, stackSlotI stkSlot) %{
5068 single_instruction;
5069 stkSlot : R(read);
5070 dst : M(write);
5071 MS : R;
5072 %}
5073
5074 // Memory Nop
5075 pipe_class mem_nop() %{
5076 single_instruction;
5077 MS : R;
5078 %}
5079
5080 pipe_class sethi(iRegP dst, immI src) %{
5081 single_instruction;
5082 dst : E(write);
5083 IALU : R;
5084 %}
5085
5086 pipe_class loadPollP(iRegP poll) %{
5087 single_instruction;
5088 poll : R(read);
5089 MS : R;
5090 %}
5091
5092 pipe_class br(Universe br, label labl) %{
5093 single_instruction_with_delay_slot;
5094 BR : R;
5095 %}
5096
5097 pipe_class br_cc(Universe br, cmpOp cmp, flagsReg cr, label labl) %{
5098 single_instruction_with_delay_slot;
5099 cr : E(read);
5100 BR : R;
5101 %}
5102
5103 pipe_class br_reg(Universe br, cmpOp cmp, iRegI op1, label labl) %{
5104 single_instruction_with_delay_slot;
5105 op1 : E(read);
5106 BR : R;
5107 MS : R;
5108 %}
5109
5110 pipe_class br_fcc(Universe br, cmpOpF cc, flagsReg cr, label labl) %{
5111 single_instruction_with_delay_slot;
5112 cr : E(read);
5113 BR : R;
5114 %}
5115
5116 pipe_class br_nop() %{
5117 single_instruction;
5118 BR : R;
5119 %}
5120
5121 pipe_class simple_call(method meth) %{
5122 instruction_count(2); multiple_bundles; force_serialization;
5123 fixed_latency(100);
5124 BR : R(1);
5125 MS : R(1);
5126 A0 : R(1);
5127 %}
5128
5129 pipe_class compiled_call(method meth) %{
5130 instruction_count(1); multiple_bundles; force_serialization;
5131 fixed_latency(100);
5132 MS : R(1);
5133 %}
5134
5135 pipe_class call(method meth) %{
5136 instruction_count(0); multiple_bundles; force_serialization;
5137 fixed_latency(100);
5138 %}
5139
5140 pipe_class tail_call(Universe ignore, label labl) %{
5141 single_instruction; has_delay_slot;
5142 fixed_latency(100);
5143 BR : R(1);
5144 MS : R(1);
5145 %}
5146
5147 pipe_class ret(Universe ignore) %{
5148 single_instruction; has_delay_slot;
5149 BR : R(1);
5150 MS : R(1);
5151 %}
5152
5153 pipe_class ret_poll(g3RegP poll) %{
5154 instruction_count(3); has_delay_slot;
5155 poll : E(read);
5156 MS : R;
5157 %}
5158
5159 // The real do-nothing guy
5160 pipe_class empty( ) %{
5161 instruction_count(0);
5162 %}
5163
5164 pipe_class long_memory_op() %{
5165 instruction_count(0); multiple_bundles; force_serialization;
5166 fixed_latency(25);
5167 MS : R(1);
5168 %}
5169
5170 // Check-cast
5171 pipe_class partial_subtype_check_pipe(Universe ignore, iRegP array, iRegP match ) %{
5172 array : R(read);
5173 match : R(read);
5174 IALU : R(2);
5175 BR : R(2);
5176 MS : R;
5177 %}
5178
5179 // Convert FPU flags into +1,0,-1
5180 pipe_class floating_cmp( iRegI dst, regF src1, regF src2 ) %{
5181 src1 : E(read);
5182 src2 : E(read);
5183 dst : E(write);
5184 FA : R;
5185 MS : R(2);
5186 BR : R(2);
5187 %}
5188
5189 // Compare for p < q, and conditionally add y
5190 pipe_class cadd_cmpltmask( iRegI p, iRegI q, iRegI y ) %{
5191 p : E(read);
5192 q : E(read);
5193 y : E(read);
5194 IALU : R(3)
5195 %}
5196
5197 // Perform a compare, then move conditionally in a branch delay slot.
5198 pipe_class min_max( iRegI src2, iRegI srcdst ) %{
5199 src2 : E(read);
5200 srcdst : E(read);
5201 IALU : R;
5202 BR : R;
5203 %}
5204
5205 // Define the class for the Nop node
5206 define %{
5207 MachNop = ialu_nop;
5208 %}
5209
5210 %}
5211
5212 //----------INSTRUCTIONS-------------------------------------------------------
5213
5214 //------------Special Stack Slot instructions - no match rules-----------------
5215 instruct stkI_to_regF(regF dst, stackSlotI src) %{
5216 // No match rule to avoid chain rule match.
5217 effect(DEF dst, USE src);
5218 ins_cost(MEMORY_REF_COST);
5219 size(4);
5220 format %{ "LDF $src,$dst\t! stkI to regF" %}
5221 opcode(Assembler::ldf_op3);
5222 ins_encode(simple_form3_mem_reg(src, dst));
5223 ins_pipe(floadF_stk);
5224 %}
5225
5226 instruct stkL_to_regD(regD dst, stackSlotL src) %{
5227 // No match rule to avoid chain rule match.
5228 effect(DEF dst, USE src);
5229 ins_cost(MEMORY_REF_COST);
5230 size(4);
5231 format %{ "LDDF $src,$dst\t! stkL to regD" %}
5232 opcode(Assembler::lddf_op3);
5233 ins_encode(simple_form3_mem_reg(src, dst));
5234 ins_pipe(floadD_stk);
5235 %}
5236
5237 instruct regF_to_stkI(stackSlotI dst, regF src) %{
5238 // No match rule to avoid chain rule match.
5239 effect(DEF dst, USE src);
5240 ins_cost(MEMORY_REF_COST);
5241 size(4);
5242 format %{ "STF $src,$dst\t! regF to stkI" %}
5243 opcode(Assembler::stf_op3);
5244 ins_encode(simple_form3_mem_reg(dst, src));
5245 ins_pipe(fstoreF_stk_reg);
5246 %}
5247
5248 instruct regD_to_stkL(stackSlotL dst, regD src) %{
5249 // No match rule to avoid chain rule match.
5250 effect(DEF dst, USE src);
5251 ins_cost(MEMORY_REF_COST);
5252 size(4);
5253 format %{ "STDF $src,$dst\t! regD to stkL" %}
5254 opcode(Assembler::stdf_op3);
5255 ins_encode(simple_form3_mem_reg(dst, src));
5256 ins_pipe(fstoreD_stk_reg);
5257 %}
5258
5259 instruct regI_to_stkLHi(stackSlotL dst, iRegI src) %{
5260 effect(DEF dst, USE src);
5261 ins_cost(MEMORY_REF_COST*2);
5262 size(8);
5263 format %{ "STW $src,$dst.hi\t! long\n\t"
5264 "STW R_G0,$dst.lo" %}
5265 opcode(Assembler::stw_op3);
5266 ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, R_G0));
5267 ins_pipe(lstoreI_stk_reg);
5268 %}
5269
5270 instruct regL_to_stkD(stackSlotD dst, iRegL src) %{
5271 // No match rule to avoid chain rule match.
5272 effect(DEF dst, USE src);
5273 ins_cost(MEMORY_REF_COST);
5274 size(4);
5275 format %{ "STX $src,$dst\t! regL to stkD" %}
5276 opcode(Assembler::stx_op3);
5277 ins_encode(simple_form3_mem_reg( dst, src ) );
5278 ins_pipe(istore_stk_reg);
5279 %}
5280
5281 //---------- Chain stack slots between similar types --------
5282
5283 // Load integer from stack slot
5284 instruct stkI_to_regI( iRegI dst, stackSlotI src ) %{
5285 match(Set dst src);
5286 ins_cost(MEMORY_REF_COST);
5287
5288 size(4);
5289 format %{ "LDUW $src,$dst\t!stk" %}
5290 opcode(Assembler::lduw_op3);
5291 ins_encode(simple_form3_mem_reg( src, dst ) );
5292 ins_pipe(iload_mem);
5293 %}
5294
5295 // Store integer to stack slot
5296 instruct regI_to_stkI( stackSlotI dst, iRegI src ) %{
5297 match(Set dst src);
5298 ins_cost(MEMORY_REF_COST);
5299
5300 size(4);
5301 format %{ "STW $src,$dst\t!stk" %}
5302 opcode(Assembler::stw_op3);
5303 ins_encode(simple_form3_mem_reg( dst, src ) );
5304 ins_pipe(istore_mem_reg);
5305 %}
5306
5307 // Load long from stack slot
5308 instruct stkL_to_regL( iRegL dst, stackSlotL src ) %{
5309 match(Set dst src);
5310
5311 ins_cost(MEMORY_REF_COST);
5312 size(4);
5313 format %{ "LDX $src,$dst\t! long" %}
5314 opcode(Assembler::ldx_op3);
5315 ins_encode(simple_form3_mem_reg( src, dst ) );
5316 ins_pipe(iload_mem);
5317 %}
5318
5319 // Store long to stack slot
5320 instruct regL_to_stkL(stackSlotL dst, iRegL src) %{
5321 match(Set dst src);
5322
5323 ins_cost(MEMORY_REF_COST);
5324 size(4);
5325 format %{ "STX $src,$dst\t! long" %}
5326 opcode(Assembler::stx_op3);
5327 ins_encode(simple_form3_mem_reg( dst, src ) );
5328 ins_pipe(istore_mem_reg);
5329 %}
5330
5331 #ifdef _LP64
5332 // Load pointer from stack slot, 64-bit encoding
5333 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{
5334 match(Set dst src);
5335 ins_cost(MEMORY_REF_COST);
5336 size(4);
5337 format %{ "LDX $src,$dst\t!ptr" %}
5338 opcode(Assembler::ldx_op3);
5339 ins_encode(simple_form3_mem_reg( src, dst ) );
5340 ins_pipe(iload_mem);
5341 %}
5342
5343 // Store pointer to stack slot
5344 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{
5345 match(Set dst src);
5346 ins_cost(MEMORY_REF_COST);
5347 size(4);
5348 format %{ "STX $src,$dst\t!ptr" %}
5349 opcode(Assembler::stx_op3);
5350 ins_encode(simple_form3_mem_reg( dst, src ) );
5351 ins_pipe(istore_mem_reg);
5352 %}
5353 #else // _LP64
5354 // Load pointer from stack slot, 32-bit encoding
5355 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{
5356 match(Set dst src);
5357 ins_cost(MEMORY_REF_COST);
5358 format %{ "LDUW $src,$dst\t!ptr" %}
5359 opcode(Assembler::lduw_op3, Assembler::ldst_op);
5360 ins_encode(simple_form3_mem_reg( src, dst ) );
5361 ins_pipe(iload_mem);
5362 %}
5363
5364 // Store pointer to stack slot
5365 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{
5366 match(Set dst src);
5367 ins_cost(MEMORY_REF_COST);
5368 format %{ "STW $src,$dst\t!ptr" %}
5369 opcode(Assembler::stw_op3, Assembler::ldst_op);
5370 ins_encode(simple_form3_mem_reg( dst, src ) );
5371 ins_pipe(istore_mem_reg);
5372 %}
5373 #endif // _LP64
5374
5375 //------------Special Nop instructions for bundling - no match rules-----------
5376 // Nop using the A0 functional unit
5377 instruct Nop_A0() %{
5378 ins_cost(0);
5379
5380 format %{ "NOP ! Alu Pipeline" %}
5381 opcode(Assembler::or_op3, Assembler::arith_op);
5382 ins_encode( form2_nop() );
5383 ins_pipe(ialu_nop_A0);
5384 %}
5385
5386 // Nop using the A1 functional unit
5387 instruct Nop_A1( ) %{
5388 ins_cost(0);
5389
5390 format %{ "NOP ! Alu Pipeline" %}
5391 opcode(Assembler::or_op3, Assembler::arith_op);
5392 ins_encode( form2_nop() );
5393 ins_pipe(ialu_nop_A1);
5394 %}
5395
5396 // Nop using the memory functional unit
5397 instruct Nop_MS( ) %{
5398 ins_cost(0);
5399
5400 format %{ "NOP ! Memory Pipeline" %}
5401 ins_encode( emit_mem_nop );
5402 ins_pipe(mem_nop);
5403 %}
5404
5405 // Nop using the floating add functional unit
5406 instruct Nop_FA( ) %{
5407 ins_cost(0);
5408
5409 format %{ "NOP ! Floating Add Pipeline" %}
5410 ins_encode( emit_fadd_nop );
5411 ins_pipe(fadd_nop);
5412 %}
5413
5414 // Nop using the branch functional unit
5415 instruct Nop_BR( ) %{
5416 ins_cost(0);
5417
5418 format %{ "NOP ! Branch Pipeline" %}
5419 ins_encode( emit_br_nop );
5420 ins_pipe(br_nop);
5421 %}
5422
5423 //----------Load/Store/Move Instructions---------------------------------------
5424 //----------Load Instructions--------------------------------------------------
5425 // Load Byte (8bit signed)
5426 instruct loadB(iRegI dst, memory mem) %{
5427 match(Set dst (LoadB mem));
5428 ins_cost(MEMORY_REF_COST);
5429
5430 size(4);
5431 format %{ "LDSB $mem,$dst\t! byte" %}
5432 ins_encode %{
5433 __ ldsb($mem$$Address, $dst$$Register);
5434 %}
5435 ins_pipe(iload_mask_mem);
5436 %}
5437
5438 // Load Byte (8bit signed) into a Long Register
5439 instruct loadB2L(iRegL dst, memory mem) %{
5440 match(Set dst (ConvI2L (LoadB mem)));
5441 ins_cost(MEMORY_REF_COST);
5442
5443 size(4);
5444 format %{ "LDSB $mem,$dst\t! byte -> long" %}
5445 ins_encode %{
5446 __ ldsb($mem$$Address, $dst$$Register);
5447 %}
5448 ins_pipe(iload_mask_mem);
5449 %}
5450
5451 // Load Unsigned Byte (8bit UNsigned) into an int reg
5452 instruct loadUB(iRegI dst, memory mem) %{
5453 match(Set dst (LoadUB mem));
5454 ins_cost(MEMORY_REF_COST);
5455
5456 size(4);
5457 format %{ "LDUB $mem,$dst\t! ubyte" %}
5458 ins_encode %{
5459 __ ldub($mem$$Address, $dst$$Register);
5460 %}
5461 ins_pipe(iload_mask_mem);
5462 %}
5463
5464 // Load Unsigned Byte (8bit UNsigned) into a Long Register
5465 instruct loadUB2L(iRegL dst, memory mem) %{
5466 match(Set dst (ConvI2L (LoadUB mem)));
5467 ins_cost(MEMORY_REF_COST);
5468
5469 size(4);
5470 format %{ "LDUB $mem,$dst\t! ubyte -> long" %}
5471 ins_encode %{
5472 __ ldub($mem$$Address, $dst$$Register);
5473 %}
5474 ins_pipe(iload_mask_mem);
5475 %}
5476
5477 // Load Short (16bit signed)
5478 instruct loadS(iRegI dst, memory mem) %{
5479 match(Set dst (LoadS mem));
5480 ins_cost(MEMORY_REF_COST);
5481
5482 size(4);
5483 format %{ "LDSH $mem,$dst\t! short" %}
5484 ins_encode %{
5485 __ ldsh($mem$$Address, $dst$$Register);
5486 %}
5487 ins_pipe(iload_mask_mem);
5488 %}
5489
5490 // Load Short (16bit signed) into a Long Register
5491 instruct loadS2L(iRegL dst, memory mem) %{
5492 match(Set dst (ConvI2L (LoadS mem)));
5493 ins_cost(MEMORY_REF_COST);
5494
5495 size(4);
5496 format %{ "LDSH $mem,$dst\t! short -> long" %}
5497 ins_encode %{
5498 __ ldsh($mem$$Address, $dst$$Register);
5499 %}
5500 ins_pipe(iload_mask_mem);
5501 %}
5502
5503 // Load Unsigned Short/Char (16bit UNsigned)
5504 instruct loadUS(iRegI dst, memory mem) %{
5505 match(Set dst (LoadUS mem));
5506 ins_cost(MEMORY_REF_COST);
5507
5508 size(4);
5509 format %{ "LDUH $mem,$dst\t! ushort/char" %}
5510 ins_encode %{
5511 __ lduh($mem$$Address, $dst$$Register);
5512 %}
5513 ins_pipe(iload_mask_mem);
5514 %}
5515
5516 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register
5517 instruct loadUS2L(iRegL dst, memory mem) %{
5518 match(Set dst (ConvI2L (LoadUS mem)));
5519 ins_cost(MEMORY_REF_COST);
5520
5521 size(4);
5522 format %{ "LDUH $mem,$dst\t! ushort/char -> long" %}
5523 ins_encode %{
5524 __ lduh($mem$$Address, $dst$$Register);
5525 %}
5526 ins_pipe(iload_mask_mem);
5527 %}
5528
5529 // Load Integer
5530 instruct loadI(iRegI dst, memory mem) %{
5531 match(Set dst (LoadI mem));
5532 ins_cost(MEMORY_REF_COST);
5533
5534 size(4);
5535 format %{ "LDUW $mem,$dst\t! int" %}
5536 ins_encode %{
5537 __ lduw($mem$$Address, $dst$$Register);
5538 %}
5539 ins_pipe(iload_mem);
5540 %}
5541
5542 // Load Integer into a Long Register
5543 instruct loadI2L(iRegL dst, memory mem) %{
5544 match(Set dst (ConvI2L (LoadI mem)));
5545 ins_cost(MEMORY_REF_COST);
5546
5547 size(4);
5548 format %{ "LDSW $mem,$dst\t! int -> long" %}
5549 ins_encode %{
5550 __ ldsw($mem$$Address, $dst$$Register);
5551 %}
5552 ins_pipe(iload_mem);
5553 %}
5554
5555 // Load Unsigned Integer into a Long Register
5556 instruct loadUI2L(iRegL dst, memory mem) %{
5557 match(Set dst (LoadUI2L mem));
5558 ins_cost(MEMORY_REF_COST);
5559
5560 size(4);
5561 format %{ "LDUW $mem,$dst\t! uint -> long" %}
5562 ins_encode %{
5563 __ lduw($mem$$Address, $dst$$Register);
5564 %}
5565 ins_pipe(iload_mem);
5566 %}
5567
5568 // Load Long - aligned
5569 instruct loadL(iRegL dst, memory mem ) %{
5570 match(Set dst (LoadL mem));
5571 ins_cost(MEMORY_REF_COST);
5572
5573 size(4);
5574 format %{ "LDX $mem,$dst\t! long" %}
5575 ins_encode %{
5576 __ ldx($mem$$Address, $dst$$Register);
5577 %}
5578 ins_pipe(iload_mem);
5579 %}
5580
5581 // Load Long - UNaligned
5582 instruct loadL_unaligned(iRegL dst, memory mem, o7RegI tmp) %{
5583 match(Set dst (LoadL_unaligned mem));
5584 effect(KILL tmp);
5585 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST);
5586 size(16);
5587 format %{ "LDUW $mem+4,R_O7\t! misaligned long\n"
5588 "\tLDUW $mem ,$dst\n"
5589 "\tSLLX #32, $dst, $dst\n"
5590 "\tOR $dst, R_O7, $dst" %}
5591 opcode(Assembler::lduw_op3);
5592 ins_encode(form3_mem_reg_long_unaligned_marshal( mem, dst ));
5593 ins_pipe(iload_mem);
5594 %}
5595
5596 // Load Aligned Packed Byte into a Double Register
5597 instruct loadA8B(regD dst, memory mem) %{
5598 match(Set dst (Load8B mem));
5599 ins_cost(MEMORY_REF_COST);
5600 size(4);
5601 format %{ "LDDF $mem,$dst\t! packed8B" %}
5602 opcode(Assembler::lddf_op3);
5603 ins_encode(simple_form3_mem_reg( mem, dst ) );
5604 ins_pipe(floadD_mem);
5605 %}
5606
5607 // Load Aligned Packed Char into a Double Register
5608 instruct loadA4C(regD dst, memory mem) %{
5609 match(Set dst (Load4C mem));
5610 ins_cost(MEMORY_REF_COST);
5611 size(4);
5612 format %{ "LDDF $mem,$dst\t! packed4C" %}
5613 opcode(Assembler::lddf_op3);
5614 ins_encode(simple_form3_mem_reg( mem, dst ) );
5615 ins_pipe(floadD_mem);
5616 %}
5617
5618 // Load Aligned Packed Short into a Double Register
5619 instruct loadA4S(regD dst, memory mem) %{
5620 match(Set dst (Load4S mem));
5621 ins_cost(MEMORY_REF_COST);
5622 size(4);
5623 format %{ "LDDF $mem,$dst\t! packed4S" %}
5624 opcode(Assembler::lddf_op3);
5625 ins_encode(simple_form3_mem_reg( mem, dst ) );
5626 ins_pipe(floadD_mem);
5627 %}
5628
5629 // Load Aligned Packed Int into a Double Register
5630 instruct loadA2I(regD dst, memory mem) %{
5631 match(Set dst (Load2I mem));
5632 ins_cost(MEMORY_REF_COST);
5633 size(4);
5634 format %{ "LDDF $mem,$dst\t! packed2I" %}
5635 opcode(Assembler::lddf_op3);
5636 ins_encode(simple_form3_mem_reg( mem, dst ) );
5637 ins_pipe(floadD_mem);
5638 %}
5639
5640 // Load Range
5641 instruct loadRange(iRegI dst, memory mem) %{
5642 match(Set dst (LoadRange mem));
5643 ins_cost(MEMORY_REF_COST);
5644
5645 size(4);
5646 format %{ "LDUW $mem,$dst\t! range" %}
5647 opcode(Assembler::lduw_op3);
5648 ins_encode(simple_form3_mem_reg( mem, dst ) );
5649 ins_pipe(iload_mem);
5650 %}
5651
5652 // Load Integer into %f register (for fitos/fitod)
5653 instruct loadI_freg(regF dst, memory mem) %{
5654 match(Set dst (LoadI mem));
5655 ins_cost(MEMORY_REF_COST);
5656 size(4);
5657
5658 format %{ "LDF $mem,$dst\t! for fitos/fitod" %}
5659 opcode(Assembler::ldf_op3);
5660 ins_encode(simple_form3_mem_reg( mem, dst ) );
5661 ins_pipe(floadF_mem);
5662 %}
5663
5664 // Load Pointer
5665 instruct loadP(iRegP dst, memory mem) %{
5666 match(Set dst (LoadP mem));
5667 ins_cost(MEMORY_REF_COST);
5668 size(4);
5669
5670 #ifndef _LP64
5671 format %{ "LDUW $mem,$dst\t! ptr" %}
5672 ins_encode %{
5673 __ lduw($mem$$Address, $dst$$Register);
5674 %}
5675 #else
5676 format %{ "LDX $mem,$dst\t! ptr" %}
5677 ins_encode %{
5678 __ ldx($mem$$Address, $dst$$Register);
5679 %}
5680 #endif
5681 ins_pipe(iload_mem);
5682 %}
5683
5684 // Load Compressed Pointer
5685 instruct loadN(iRegN dst, memory mem) %{
5686 match(Set dst (LoadN mem));
5687 ins_cost(MEMORY_REF_COST);
5688 size(4);
5689
5690 format %{ "LDUW $mem,$dst\t! compressed ptr" %}
5691 ins_encode %{
5692 __ lduw($mem$$Address, $dst$$Register);
5693 %}
5694 ins_pipe(iload_mem);
5695 %}
5696
5697 // Load Klass Pointer
5698 instruct loadKlass(iRegP dst, memory mem) %{
5699 match(Set dst (LoadKlass mem));
5700 ins_cost(MEMORY_REF_COST);
5701 size(4);
5702
5703 #ifndef _LP64
5704 format %{ "LDUW $mem,$dst\t! klass ptr" %}
5705 ins_encode %{
5706 __ lduw($mem$$Address, $dst$$Register);
5707 %}
5708 #else
5709 format %{ "LDX $mem,$dst\t! klass ptr" %}
5710 ins_encode %{
5711 __ ldx($mem$$Address, $dst$$Register);
5712 %}
5713 #endif
5714 ins_pipe(iload_mem);
5715 %}
5716
5717 // Load narrow Klass Pointer
5718 instruct loadNKlass(iRegN dst, memory mem) %{
5719 match(Set dst (LoadNKlass mem));
5720 ins_cost(MEMORY_REF_COST);
5721 size(4);
5722
5723 format %{ "LDUW $mem,$dst\t! compressed klass ptr" %}
5724 ins_encode %{
5725 __ lduw($mem$$Address, $dst$$Register);
5726 %}
5727 ins_pipe(iload_mem);
5728 %}
5729
5730 // Load Double
5731 instruct loadD(regD dst, memory mem) %{
5732 match(Set dst (LoadD mem));
5733 ins_cost(MEMORY_REF_COST);
5734
5735 size(4);
5736 format %{ "LDDF $mem,$dst" %}
5737 opcode(Assembler::lddf_op3);
5738 ins_encode(simple_form3_mem_reg( mem, dst ) );
5739 ins_pipe(floadD_mem);
5740 %}
5741
5742 // Load Double - UNaligned
5743 instruct loadD_unaligned(regD_low dst, memory mem ) %{
5744 match(Set dst (LoadD_unaligned mem));
5745 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST);
5746 size(8);
5747 format %{ "LDF $mem ,$dst.hi\t! misaligned double\n"
5748 "\tLDF $mem+4,$dst.lo\t!" %}
5749 opcode(Assembler::ldf_op3);
5750 ins_encode( form3_mem_reg_double_unaligned( mem, dst ));
5751 ins_pipe(iload_mem);
5752 %}
5753
5754 // Load Float
5755 instruct loadF(regF dst, memory mem) %{
5756 match(Set dst (LoadF mem));
5757 ins_cost(MEMORY_REF_COST);
5758
5759 size(4);
5760 format %{ "LDF $mem,$dst" %}
5761 opcode(Assembler::ldf_op3);
5762 ins_encode(simple_form3_mem_reg( mem, dst ) );
5763 ins_pipe(floadF_mem);
5764 %}
5765
5766 // Load Constant
5767 instruct loadConI( iRegI dst, immI src ) %{
5768 match(Set dst src);
5769 ins_cost(DEFAULT_COST * 3/2);
5770 format %{ "SET $src,$dst" %}
5771 ins_encode( Set32(src, dst) );
5772 ins_pipe(ialu_hi_lo_reg);
5773 %}
5774
5775 instruct loadConI13( iRegI dst, immI13 src ) %{
5776 match(Set dst src);
5777
5778 size(4);
5779 format %{ "MOV $src,$dst" %}
5780 ins_encode( Set13( src, dst ) );
5781 ins_pipe(ialu_imm);
5782 %}
5783
5784 instruct loadConP(iRegP dst, immP src) %{
5785 match(Set dst src);
5786 ins_cost(DEFAULT_COST * 3/2);
5787 format %{ "SET $src,$dst\t!ptr" %}
5788 // This rule does not use "expand" unlike loadConI because then
5789 // the result type is not known to be an Oop. An ADLC
5790 // enhancement will be needed to make that work - not worth it!
5791
5792 ins_encode( SetPtr( src, dst ) );
5793 ins_pipe(loadConP);
5794
5795 %}
5796
5797 instruct loadConP0(iRegP dst, immP0 src) %{
5798 match(Set dst src);
5799
5800 size(4);
5801 format %{ "CLR $dst\t!ptr" %}
5802 ins_encode( SetNull( dst ) );
5803 ins_pipe(ialu_imm);
5804 %}
5805
5806 instruct loadConP_poll(iRegP dst, immP_poll src) %{
5807 match(Set dst src);
5808 ins_cost(DEFAULT_COST);
5809 format %{ "SET $src,$dst\t!ptr" %}
5810 ins_encode %{
5811 AddressLiteral polling_page(os::get_polling_page());
5812 __ sethi(polling_page, reg_to_register_object($dst$$reg));
5813 %}
5814 ins_pipe(loadConP_poll);
5815 %}
5816
5817 instruct loadConN0(iRegN dst, immN0 src) %{
5818 match(Set dst src);
5819
5820 size(4);
5821 format %{ "CLR $dst\t! compressed NULL ptr" %}
5822 ins_encode( SetNull( dst ) );
5823 ins_pipe(ialu_imm);
5824 %}
5825
5826 instruct loadConN(iRegN dst, immN src) %{
5827 match(Set dst src);
5828 ins_cost(DEFAULT_COST * 3/2);
5829 format %{ "SET $src,$dst\t! compressed ptr" %}
5830 ins_encode %{
5831 Register dst = $dst$$Register;
5832 __ set_narrow_oop((jobject)$src$$constant, dst);
5833 %}
5834 ins_pipe(ialu_hi_lo_reg);
5835 %}
5836
5837 instruct loadConL(iRegL dst, immL src, o7RegL tmp) %{
5838 // %%% maybe this should work like loadConD
5839 match(Set dst src);
5840 effect(KILL tmp);
5841 ins_cost(DEFAULT_COST * 4);
5842 format %{ "SET64 $src,$dst KILL $tmp\t! long" %}
5843 ins_encode( LdImmL(src, dst, tmp) );
5844 ins_pipe(loadConL);
5845 %}
5846
5847 instruct loadConL0( iRegL dst, immL0 src ) %{
5848 match(Set dst src);
5849 ins_cost(DEFAULT_COST);
5850 size(4);
5851 format %{ "CLR $dst\t! long" %}
5852 ins_encode( Set13( src, dst ) );
5853 ins_pipe(ialu_imm);
5854 %}
5855
5856 instruct loadConL13( iRegL dst, immL13 src ) %{
5857 match(Set dst src);
5858 ins_cost(DEFAULT_COST * 2);
5859
5860 size(4);
5861 format %{ "MOV $src,$dst\t! long" %}
5862 ins_encode( Set13( src, dst ) );
5863 ins_pipe(ialu_imm);
5864 %}
5865
5866 instruct loadConF(regF dst, immF src, o7RegP tmp) %{
5867 match(Set dst src);
5868 effect(KILL tmp);
5869
5870 #ifdef _LP64
5871 size(8*4);
5872 #else
5873 size(2*4);
5874 #endif
5875
5876 format %{ "SETHI hi(&$src),$tmp\t!get float $src from table\n\t"
5877 "LDF [$tmp+lo(&$src)],$dst" %}
5878 ins_encode %{
5879 address float_address = __ float_constant($src$$constant);
5880 RelocationHolder rspec = internal_word_Relocation::spec(float_address);
5881 AddressLiteral addrlit(float_address, rspec);
5882
5883 __ sethi(addrlit, $tmp$$Register);
5884 __ ldf(FloatRegisterImpl::S, $tmp$$Register, addrlit.low10(), $dst$$FloatRegister, rspec);
5885 %}
5886 ins_pipe(loadConFD);
5887 %}
5888
5889 instruct loadConD(regD dst, immD src, o7RegP tmp) %{
5890 match(Set dst src);
5891 effect(KILL tmp);
5892
5893 #ifdef _LP64
5894 size(8*4);
5895 #else
5896 size(2*4);
5897 #endif
5898
5899 format %{ "SETHI hi(&$src),$tmp\t!get double $src from table\n\t"
5900 "LDDF [$tmp+lo(&$src)],$dst" %}
5901 ins_encode %{
5902 address double_address = __ double_constant($src$$constant);
5903 RelocationHolder rspec = internal_word_Relocation::spec(double_address);
5904 AddressLiteral addrlit(double_address, rspec);
5905
5906 __ sethi(addrlit, $tmp$$Register);
5907 // XXX This is a quick fix for 6833573.
5908 //__ ldf(FloatRegisterImpl::D, $tmp$$Register, addrlit.low10(), $dst$$FloatRegister, rspec);
5909 __ ldf(FloatRegisterImpl::D, $tmp$$Register, addrlit.low10(), as_DoubleFloatRegister($dst$$reg), rspec);
5910 %}
5911 ins_pipe(loadConFD);
5912 %}
5913
5914 // Prefetch instructions.
5915 // Must be safe to execute with invalid address (cannot fault).
5916
5917 instruct prefetchr( memory mem ) %{
5918 match( PrefetchRead mem );
5919 ins_cost(MEMORY_REF_COST);
5920
5921 format %{ "PREFETCH $mem,0\t! Prefetch read-many" %}
5922 opcode(Assembler::prefetch_op3);
5923 ins_encode( form3_mem_prefetch_read( mem ) );
5924 ins_pipe(iload_mem);
5925 %}
5926
5927 instruct prefetchw( memory mem ) %{
5928 match( PrefetchWrite mem );
5929 ins_cost(MEMORY_REF_COST);
5930
5931 format %{ "PREFETCH $mem,2\t! Prefetch write-many (and read)" %}
5932 opcode(Assembler::prefetch_op3);
5933 ins_encode( form3_mem_prefetch_write( mem ) );
5934 ins_pipe(iload_mem);
5935 %}
5936
5937
5938 //----------Store Instructions-------------------------------------------------
5939 // Store Byte
5940 instruct storeB(memory mem, iRegI src) %{
5941 match(Set mem (StoreB mem src));
5942 ins_cost(MEMORY_REF_COST);
5943
5944 size(4);
5945 format %{ "STB $src,$mem\t! byte" %}
5946 opcode(Assembler::stb_op3);
5947 ins_encode(simple_form3_mem_reg( mem, src ) );
5948 ins_pipe(istore_mem_reg);
5949 %}
5950
5951 instruct storeB0(memory mem, immI0 src) %{
5952 match(Set mem (StoreB mem src));
5953 ins_cost(MEMORY_REF_COST);
5954
5955 size(4);
5956 format %{ "STB $src,$mem\t! byte" %}
5957 opcode(Assembler::stb_op3);
5958 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
5959 ins_pipe(istore_mem_zero);
5960 %}
5961
5962 instruct storeCM0(memory mem, immI0 src) %{
5963 match(Set mem (StoreCM mem src));
5964 ins_cost(MEMORY_REF_COST);
5965
5966 size(4);
5967 format %{ "STB $src,$mem\t! CMS card-mark byte 0" %}
5968 opcode(Assembler::stb_op3);
5969 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
5970 ins_pipe(istore_mem_zero);
5971 %}
5972
5973 // Store Char/Short
5974 instruct storeC(memory mem, iRegI src) %{
5975 match(Set mem (StoreC mem src));
5976 ins_cost(MEMORY_REF_COST);
5977
5978 size(4);
5979 format %{ "STH $src,$mem\t! short" %}
5980 opcode(Assembler::sth_op3);
5981 ins_encode(simple_form3_mem_reg( mem, src ) );
5982 ins_pipe(istore_mem_reg);
5983 %}
5984
5985 instruct storeC0(memory mem, immI0 src) %{
5986 match(Set mem (StoreC mem src));
5987 ins_cost(MEMORY_REF_COST);
5988
5989 size(4);
5990 format %{ "STH $src,$mem\t! short" %}
5991 opcode(Assembler::sth_op3);
5992 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
5993 ins_pipe(istore_mem_zero);
5994 %}
5995
5996 // Store Integer
5997 instruct storeI(memory mem, iRegI src) %{
5998 match(Set mem (StoreI mem src));
5999 ins_cost(MEMORY_REF_COST);
6000
6001 size(4);
6002 format %{ "STW $src,$mem" %}
6003 opcode(Assembler::stw_op3);
6004 ins_encode(simple_form3_mem_reg( mem, src ) );
6005 ins_pipe(istore_mem_reg);
6006 %}
6007
6008 // Store Long
6009 instruct storeL(memory mem, iRegL src) %{
6010 match(Set mem (StoreL mem src));
6011 ins_cost(MEMORY_REF_COST);
6012 size(4);
6013 format %{ "STX $src,$mem\t! long" %}
6014 opcode(Assembler::stx_op3);
6015 ins_encode(simple_form3_mem_reg( mem, src ) );
6016 ins_pipe(istore_mem_reg);
6017 %}
6018
6019 instruct storeI0(memory mem, immI0 src) %{
6020 match(Set mem (StoreI mem src));
6021 ins_cost(MEMORY_REF_COST);
6022
6023 size(4);
6024 format %{ "STW $src,$mem" %}
6025 opcode(Assembler::stw_op3);
6026 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6027 ins_pipe(istore_mem_zero);
6028 %}
6029
6030 instruct storeL0(memory mem, immL0 src) %{
6031 match(Set mem (StoreL mem src));
6032 ins_cost(MEMORY_REF_COST);
6033
6034 size(4);
6035 format %{ "STX $src,$mem" %}
6036 opcode(Assembler::stx_op3);
6037 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6038 ins_pipe(istore_mem_zero);
6039 %}
6040
6041 // Store Integer from float register (used after fstoi)
6042 instruct storeI_Freg(memory mem, regF src) %{
6043 match(Set mem (StoreI mem src));
6044 ins_cost(MEMORY_REF_COST);
6045
6046 size(4);
6047 format %{ "STF $src,$mem\t! after fstoi/fdtoi" %}
6048 opcode(Assembler::stf_op3);
6049 ins_encode(simple_form3_mem_reg( mem, src ) );
6050 ins_pipe(fstoreF_mem_reg);
6051 %}
6052
6053 // Store Pointer
6054 instruct storeP(memory dst, sp_ptr_RegP src) %{
6055 match(Set dst (StoreP dst src));
6056 ins_cost(MEMORY_REF_COST);
6057 size(4);
6058
6059 #ifndef _LP64
6060 format %{ "STW $src,$dst\t! ptr" %}
6061 opcode(Assembler::stw_op3, 0, REGP_OP);
6062 #else
6063 format %{ "STX $src,$dst\t! ptr" %}
6064 opcode(Assembler::stx_op3, 0, REGP_OP);
6065 #endif
6066 ins_encode( form3_mem_reg( dst, src ) );
6067 ins_pipe(istore_mem_spORreg);
6068 %}
6069
6070 instruct storeP0(memory dst, immP0 src) %{
6071 match(Set dst (StoreP dst src));
6072 ins_cost(MEMORY_REF_COST);
6073 size(4);
6074
6075 #ifndef _LP64
6076 format %{ "STW $src,$dst\t! ptr" %}
6077 opcode(Assembler::stw_op3, 0, REGP_OP);
6078 #else
6079 format %{ "STX $src,$dst\t! ptr" %}
6080 opcode(Assembler::stx_op3, 0, REGP_OP);
6081 #endif
6082 ins_encode( form3_mem_reg( dst, R_G0 ) );
6083 ins_pipe(istore_mem_zero);
6084 %}
6085
6086 // Store Compressed Pointer
6087 instruct storeN(memory dst, iRegN src) %{
6088 match(Set dst (StoreN dst src));
6089 ins_cost(MEMORY_REF_COST);
6090 size(4);
6091
6092 format %{ "STW $src,$dst\t! compressed ptr" %}
6093 ins_encode %{
6094 Register base = as_Register($dst$$base);
6095 Register index = as_Register($dst$$index);
6096 Register src = $src$$Register;
6097 if (index != G0) {
6098 __ stw(src, base, index);
6099 } else {
6100 __ stw(src, base, $dst$$disp);
6101 }
6102 %}
6103 ins_pipe(istore_mem_spORreg);
6104 %}
6105
6106 instruct storeN0(memory dst, immN0 src) %{
6107 match(Set dst (StoreN dst src));
6108 ins_cost(MEMORY_REF_COST);
6109 size(4);
6110
6111 format %{ "STW $src,$dst\t! compressed ptr" %}
6112 ins_encode %{
6113 Register base = as_Register($dst$$base);
6114 Register index = as_Register($dst$$index);
6115 if (index != G0) {
6116 __ stw(0, base, index);
6117 } else {
6118 __ stw(0, base, $dst$$disp);
6119 }
6120 %}
6121 ins_pipe(istore_mem_zero);
6122 %}
6123
6124 // Store Double
6125 instruct storeD( memory mem, regD src) %{
6126 match(Set mem (StoreD mem src));
6127 ins_cost(MEMORY_REF_COST);
6128
6129 size(4);
6130 format %{ "STDF $src,$mem" %}
6131 opcode(Assembler::stdf_op3);
6132 ins_encode(simple_form3_mem_reg( mem, src ) );
6133 ins_pipe(fstoreD_mem_reg);
6134 %}
6135
6136 instruct storeD0( memory mem, immD0 src) %{
6137 match(Set mem (StoreD mem src));
6138 ins_cost(MEMORY_REF_COST);
6139
6140 size(4);
6141 format %{ "STX $src,$mem" %}
6142 opcode(Assembler::stx_op3);
6143 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6144 ins_pipe(fstoreD_mem_zero);
6145 %}
6146
6147 // Store Float
6148 instruct storeF( memory mem, regF src) %{
6149 match(Set mem (StoreF mem src));
6150 ins_cost(MEMORY_REF_COST);
6151
6152 size(4);
6153 format %{ "STF $src,$mem" %}
6154 opcode(Assembler::stf_op3);
6155 ins_encode(simple_form3_mem_reg( mem, src ) );
6156 ins_pipe(fstoreF_mem_reg);
6157 %}
6158
6159 instruct storeF0( memory mem, immF0 src) %{
6160 match(Set mem (StoreF mem src));
6161 ins_cost(MEMORY_REF_COST);
6162
6163 size(4);
6164 format %{ "STW $src,$mem\t! storeF0" %}
6165 opcode(Assembler::stw_op3);
6166 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6167 ins_pipe(fstoreF_mem_zero);
6168 %}
6169
6170 // Store Aligned Packed Bytes in Double register to memory
6171 instruct storeA8B(memory mem, regD src) %{
6172 match(Set mem (Store8B mem src));
6173 ins_cost(MEMORY_REF_COST);
6174 size(4);
6175 format %{ "STDF $src,$mem\t! packed8B" %}
6176 opcode(Assembler::stdf_op3);
6177 ins_encode(simple_form3_mem_reg( mem, src ) );
6178 ins_pipe(fstoreD_mem_reg);
6179 %}
6180
6181 // Convert oop pointer into compressed form
6182 instruct encodeHeapOop(iRegN dst, iRegP src) %{
6183 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
6184 match(Set dst (EncodeP src));
6185 format %{ "encode_heap_oop $src, $dst" %}
6186 ins_encode %{
6187 __ encode_heap_oop($src$$Register, $dst$$Register);
6188 %}
6189 ins_pipe(ialu_reg);
6190 %}
6191
6192 instruct encodeHeapOop_not_null(iRegN dst, iRegP src) %{
6193 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
6194 match(Set dst (EncodeP src));
6195 format %{ "encode_heap_oop_not_null $src, $dst" %}
6196 ins_encode %{
6197 __ encode_heap_oop_not_null($src$$Register, $dst$$Register);
6198 %}
6199 ins_pipe(ialu_reg);
6200 %}
6201
6202 instruct decodeHeapOop(iRegP dst, iRegN src) %{
6203 predicate(n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull &&
6204 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant);
6205 match(Set dst (DecodeN src));
6206 format %{ "decode_heap_oop $src, $dst" %}
6207 ins_encode %{
6208 __ decode_heap_oop($src$$Register, $dst$$Register);
6209 %}
6210 ins_pipe(ialu_reg);
6211 %}
6212
6213 instruct decodeHeapOop_not_null(iRegP dst, iRegN src) %{
6214 predicate(n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull ||
6215 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant);
6216 match(Set dst (DecodeN src));
6217 format %{ "decode_heap_oop_not_null $src, $dst" %}
6218 ins_encode %{
6219 __ decode_heap_oop_not_null($src$$Register, $dst$$Register);
6220 %}
6221 ins_pipe(ialu_reg);
6222 %}
6223
6224
6225 // Store Zero into Aligned Packed Bytes
6226 instruct storeA8B0(memory mem, immI0 zero) %{
6227 match(Set mem (Store8B mem zero));
6228 ins_cost(MEMORY_REF_COST);
6229 size(4);
6230 format %{ "STX $zero,$mem\t! packed8B" %}
6231 opcode(Assembler::stx_op3);
6232 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6233 ins_pipe(fstoreD_mem_zero);
6234 %}
6235
6236 // Store Aligned Packed Chars/Shorts in Double register to memory
6237 instruct storeA4C(memory mem, regD src) %{
6238 match(Set mem (Store4C mem src));
6239 ins_cost(MEMORY_REF_COST);
6240 size(4);
6241 format %{ "STDF $src,$mem\t! packed4C" %}
6242 opcode(Assembler::stdf_op3);
6243 ins_encode(simple_form3_mem_reg( mem, src ) );
6244 ins_pipe(fstoreD_mem_reg);
6245 %}
6246
6247 // Store Zero into Aligned Packed Chars/Shorts
6248 instruct storeA4C0(memory mem, immI0 zero) %{
6249 match(Set mem (Store4C mem (Replicate4C zero)));
6250 ins_cost(MEMORY_REF_COST);
6251 size(4);
6252 format %{ "STX $zero,$mem\t! packed4C" %}
6253 opcode(Assembler::stx_op3);
6254 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6255 ins_pipe(fstoreD_mem_zero);
6256 %}
6257
6258 // Store Aligned Packed Ints in Double register to memory
6259 instruct storeA2I(memory mem, regD src) %{
6260 match(Set mem (Store2I mem src));
6261 ins_cost(MEMORY_REF_COST);
6262 size(4);
6263 format %{ "STDF $src,$mem\t! packed2I" %}
6264 opcode(Assembler::stdf_op3);
6265 ins_encode(simple_form3_mem_reg( mem, src ) );
6266 ins_pipe(fstoreD_mem_reg);
6267 %}
6268
6269 // Store Zero into Aligned Packed Ints
6270 instruct storeA2I0(memory mem, immI0 zero) %{
6271 match(Set mem (Store2I mem zero));
6272 ins_cost(MEMORY_REF_COST);
6273 size(4);
6274 format %{ "STX $zero,$mem\t! packed2I" %}
6275 opcode(Assembler::stx_op3);
6276 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6277 ins_pipe(fstoreD_mem_zero);
6278 %}
6279
6280
6281 //----------MemBar Instructions-----------------------------------------------
6282 // Memory barrier flavors
6283
6284 instruct membar_acquire() %{
6285 match(MemBarAcquire);
6286 ins_cost(4*MEMORY_REF_COST);
6287
6288 size(0);
6289 format %{ "MEMBAR-acquire" %}
6290 ins_encode( enc_membar_acquire );
6291 ins_pipe(long_memory_op);
6292 %}
6293
6294 instruct membar_acquire_lock() %{
6295 match(MemBarAcquire);
6296 predicate(Matcher::prior_fast_lock(n));
6297 ins_cost(0);
6298
6299 size(0);
6300 format %{ "!MEMBAR-acquire (CAS in prior FastLock so empty encoding)" %}
6301 ins_encode( );
6302 ins_pipe(empty);
6303 %}
6304
6305 instruct membar_release() %{
6306 match(MemBarRelease);
6307 ins_cost(4*MEMORY_REF_COST);
6308
6309 size(0);
6310 format %{ "MEMBAR-release" %}
6311 ins_encode( enc_membar_release );
6312 ins_pipe(long_memory_op);
6313 %}
6314
6315 instruct membar_release_lock() %{
6316 match(MemBarRelease);
6317 predicate(Matcher::post_fast_unlock(n));
6318 ins_cost(0);
6319
6320 size(0);
6321 format %{ "!MEMBAR-release (CAS in succeeding FastUnlock so empty encoding)" %}
6322 ins_encode( );
6323 ins_pipe(empty);
6324 %}
6325
6326 instruct membar_volatile() %{
6327 match(MemBarVolatile);
6328 ins_cost(4*MEMORY_REF_COST);
6329
6330 size(4);
6331 format %{ "MEMBAR-volatile" %}
6332 ins_encode( enc_membar_volatile );
6333 ins_pipe(long_memory_op);
6334 %}
6335
6336 instruct unnecessary_membar_volatile() %{
6337 match(MemBarVolatile);
6338 predicate(Matcher::post_store_load_barrier(n));
6339 ins_cost(0);
6340
6341 size(0);
6342 format %{ "!MEMBAR-volatile (unnecessary so empty encoding)" %}
6343 ins_encode( );
6344 ins_pipe(empty);
6345 %}
6346
6347 //----------Register Move Instructions-----------------------------------------
6348 instruct roundDouble_nop(regD dst) %{
6349 match(Set dst (RoundDouble dst));
6350 ins_cost(0);
6351 // SPARC results are already "rounded" (i.e., normal-format IEEE)
6352 ins_encode( );
6353 ins_pipe(empty);
6354 %}
6355
6356
6357 instruct roundFloat_nop(regF dst) %{
6358 match(Set dst (RoundFloat dst));
6359 ins_cost(0);
6360 // SPARC results are already "rounded" (i.e., normal-format IEEE)
6361 ins_encode( );
6362 ins_pipe(empty);
6363 %}
6364
6365
6366 // Cast Index to Pointer for unsafe natives
6367 instruct castX2P(iRegX src, iRegP dst) %{
6368 match(Set dst (CastX2P src));
6369
6370 format %{ "MOV $src,$dst\t! IntX->Ptr" %}
6371 ins_encode( form3_g0_rs2_rd_move( src, dst ) );
6372 ins_pipe(ialu_reg);
6373 %}
6374
6375 // Cast Pointer to Index for unsafe natives
6376 instruct castP2X(iRegP src, iRegX dst) %{
6377 match(Set dst (CastP2X src));
6378
6379 format %{ "MOV $src,$dst\t! Ptr->IntX" %}
6380 ins_encode( form3_g0_rs2_rd_move( src, dst ) );
6381 ins_pipe(ialu_reg);
6382 %}
6383
6384 instruct stfSSD(stackSlotD stkSlot, regD src) %{
6385 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6386 match(Set stkSlot src); // chain rule
6387 ins_cost(MEMORY_REF_COST);
6388 format %{ "STDF $src,$stkSlot\t!stk" %}
6389 opcode(Assembler::stdf_op3);
6390 ins_encode(simple_form3_mem_reg(stkSlot, src));
6391 ins_pipe(fstoreD_stk_reg);
6392 %}
6393
6394 instruct ldfSSD(regD dst, stackSlotD stkSlot) %{
6395 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6396 match(Set dst stkSlot); // chain rule
6397 ins_cost(MEMORY_REF_COST);
6398 format %{ "LDDF $stkSlot,$dst\t!stk" %}
6399 opcode(Assembler::lddf_op3);
6400 ins_encode(simple_form3_mem_reg(stkSlot, dst));
6401 ins_pipe(floadD_stk);
6402 %}
6403
6404 instruct stfSSF(stackSlotF stkSlot, regF src) %{
6405 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6406 match(Set stkSlot src); // chain rule
6407 ins_cost(MEMORY_REF_COST);
6408 format %{ "STF $src,$stkSlot\t!stk" %}
6409 opcode(Assembler::stf_op3);
6410 ins_encode(simple_form3_mem_reg(stkSlot, src));
6411 ins_pipe(fstoreF_stk_reg);
6412 %}
6413
6414 //----------Conditional Move---------------------------------------------------
6415 // Conditional move
6416 instruct cmovIP_reg(cmpOpP cmp, flagsRegP pcc, iRegI dst, iRegI src) %{
6417 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src)));
6418 ins_cost(150);
6419 format %{ "MOV$cmp $pcc,$src,$dst" %}
6420 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6421 ins_pipe(ialu_reg);
6422 %}
6423
6424 instruct cmovIP_imm(cmpOpP cmp, flagsRegP pcc, iRegI dst, immI11 src) %{
6425 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src)));
6426 ins_cost(140);
6427 format %{ "MOV$cmp $pcc,$src,$dst" %}
6428 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
6429 ins_pipe(ialu_imm);
6430 %}
6431
6432 instruct cmovII_reg(cmpOp cmp, flagsReg icc, iRegI dst, iRegI src) %{
6433 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6434 ins_cost(150);
6435 size(4);
6436 format %{ "MOV$cmp $icc,$src,$dst" %}
6437 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6438 ins_pipe(ialu_reg);
6439 %}
6440
6441 instruct cmovII_imm(cmpOp cmp, flagsReg icc, iRegI dst, immI11 src) %{
6442 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6443 ins_cost(140);
6444 size(4);
6445 format %{ "MOV$cmp $icc,$src,$dst" %}
6446 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6447 ins_pipe(ialu_imm);
6448 %}
6449
6450 instruct cmovII_U_reg(cmpOpU cmp, flagsRegU icc, iRegI dst, iRegI src) %{
6451 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6452 ins_cost(150);
6453 size(4);
6454 format %{ "MOV$cmp $icc,$src,$dst" %}
6455 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6456 ins_pipe(ialu_reg);
6457 %}
6458
6459 instruct cmovII_U_imm(cmpOpU cmp, flagsRegU icc, iRegI dst, immI11 src) %{
6460 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6461 ins_cost(140);
6462 size(4);
6463 format %{ "MOV$cmp $icc,$src,$dst" %}
6464 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6465 ins_pipe(ialu_imm);
6466 %}
6467
6468 instruct cmovIF_reg(cmpOpF cmp, flagsRegF fcc, iRegI dst, iRegI src) %{
6469 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src)));
6470 ins_cost(150);
6471 size(4);
6472 format %{ "MOV$cmp $fcc,$src,$dst" %}
6473 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6474 ins_pipe(ialu_reg);
6475 %}
6476
6477 instruct cmovIF_imm(cmpOpF cmp, flagsRegF fcc, iRegI dst, immI11 src) %{
6478 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src)));
6479 ins_cost(140);
6480 size(4);
6481 format %{ "MOV$cmp $fcc,$src,$dst" %}
6482 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) );
6483 ins_pipe(ialu_imm);
6484 %}
6485
6486 // Conditional move for RegN. Only cmov(reg,reg).
6487 instruct cmovNP_reg(cmpOpP cmp, flagsRegP pcc, iRegN dst, iRegN src) %{
6488 match(Set dst (CMoveN (Binary cmp pcc) (Binary dst src)));
6489 ins_cost(150);
6490 format %{ "MOV$cmp $pcc,$src,$dst" %}
6491 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6492 ins_pipe(ialu_reg);
6493 %}
6494
6495 // This instruction also works with CmpN so we don't need cmovNN_reg.
6496 instruct cmovNI_reg(cmpOp cmp, flagsReg icc, iRegN dst, iRegN src) %{
6497 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src)));
6498 ins_cost(150);
6499 size(4);
6500 format %{ "MOV$cmp $icc,$src,$dst" %}
6501 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6502 ins_pipe(ialu_reg);
6503 %}
6504
6505 instruct cmovNF_reg(cmpOpF cmp, flagsRegF fcc, iRegN dst, iRegN src) %{
6506 match(Set dst (CMoveN (Binary cmp fcc) (Binary dst src)));
6507 ins_cost(150);
6508 size(4);
6509 format %{ "MOV$cmp $fcc,$src,$dst" %}
6510 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6511 ins_pipe(ialu_reg);
6512 %}
6513
6514 // Conditional move
6515 instruct cmovPP_reg(cmpOpP cmp, flagsRegP pcc, iRegP dst, iRegP src) %{
6516 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src)));
6517 ins_cost(150);
6518 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %}
6519 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6520 ins_pipe(ialu_reg);
6521 %}
6522
6523 instruct cmovPP_imm(cmpOpP cmp, flagsRegP pcc, iRegP dst, immP0 src) %{
6524 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src)));
6525 ins_cost(140);
6526 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %}
6527 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
6528 ins_pipe(ialu_imm);
6529 %}
6530
6531 // This instruction also works with CmpN so we don't need cmovPN_reg.
6532 instruct cmovPI_reg(cmpOp cmp, flagsReg icc, iRegP dst, iRegP src) %{
6533 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6534 ins_cost(150);
6535
6536 size(4);
6537 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6538 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6539 ins_pipe(ialu_reg);
6540 %}
6541
6542 instruct cmovPI_imm(cmpOp cmp, flagsReg icc, iRegP dst, immP0 src) %{
6543 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6544 ins_cost(140);
6545
6546 size(4);
6547 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6548 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6549 ins_pipe(ialu_imm);
6550 %}
6551
6552 instruct cmovPF_reg(cmpOpF cmp, flagsRegF fcc, iRegP dst, iRegP src) %{
6553 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src)));
6554 ins_cost(150);
6555 size(4);
6556 format %{ "MOV$cmp $fcc,$src,$dst" %}
6557 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6558 ins_pipe(ialu_imm);
6559 %}
6560
6561 instruct cmovPF_imm(cmpOpF cmp, flagsRegF fcc, iRegP dst, immP0 src) %{
6562 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src)));
6563 ins_cost(140);
6564 size(4);
6565 format %{ "MOV$cmp $fcc,$src,$dst" %}
6566 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) );
6567 ins_pipe(ialu_imm);
6568 %}
6569
6570 // Conditional move
6571 instruct cmovFP_reg(cmpOpP cmp, flagsRegP pcc, regF dst, regF src) %{
6572 match(Set dst (CMoveF (Binary cmp pcc) (Binary dst src)));
6573 ins_cost(150);
6574 opcode(0x101);
6575 format %{ "FMOVD$cmp $pcc,$src,$dst" %}
6576 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6577 ins_pipe(int_conditional_float_move);
6578 %}
6579
6580 instruct cmovFI_reg(cmpOp cmp, flagsReg icc, regF dst, regF src) %{
6581 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src)));
6582 ins_cost(150);
6583
6584 size(4);
6585 format %{ "FMOVS$cmp $icc,$src,$dst" %}
6586 opcode(0x101);
6587 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6588 ins_pipe(int_conditional_float_move);
6589 %}
6590
6591 // Conditional move,
6592 instruct cmovFF_reg(cmpOpF cmp, flagsRegF fcc, regF dst, regF src) %{
6593 match(Set dst (CMoveF (Binary cmp fcc) (Binary dst src)));
6594 ins_cost(150);
6595 size(4);
6596 format %{ "FMOVF$cmp $fcc,$src,$dst" %}
6597 opcode(0x1);
6598 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) );
6599 ins_pipe(int_conditional_double_move);
6600 %}
6601
6602 // Conditional move
6603 instruct cmovDP_reg(cmpOpP cmp, flagsRegP pcc, regD dst, regD src) %{
6604 match(Set dst (CMoveD (Binary cmp pcc) (Binary dst src)));
6605 ins_cost(150);
6606 size(4);
6607 opcode(0x102);
6608 format %{ "FMOVD$cmp $pcc,$src,$dst" %}
6609 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6610 ins_pipe(int_conditional_double_move);
6611 %}
6612
6613 instruct cmovDI_reg(cmpOp cmp, flagsReg icc, regD dst, regD src) %{
6614 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src)));
6615 ins_cost(150);
6616
6617 size(4);
6618 format %{ "FMOVD$cmp $icc,$src,$dst" %}
6619 opcode(0x102);
6620 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6621 ins_pipe(int_conditional_double_move);
6622 %}
6623
6624 // Conditional move,
6625 instruct cmovDF_reg(cmpOpF cmp, flagsRegF fcc, regD dst, regD src) %{
6626 match(Set dst (CMoveD (Binary cmp fcc) (Binary dst src)));
6627 ins_cost(150);
6628 size(4);
6629 format %{ "FMOVD$cmp $fcc,$src,$dst" %}
6630 opcode(0x2);
6631 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) );
6632 ins_pipe(int_conditional_double_move);
6633 %}
6634
6635 // Conditional move
6636 instruct cmovLP_reg(cmpOpP cmp, flagsRegP pcc, iRegL dst, iRegL src) %{
6637 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src)));
6638 ins_cost(150);
6639 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %}
6640 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6641 ins_pipe(ialu_reg);
6642 %}
6643
6644 instruct cmovLP_imm(cmpOpP cmp, flagsRegP pcc, iRegL dst, immI11 src) %{
6645 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src)));
6646 ins_cost(140);
6647 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %}
6648 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
6649 ins_pipe(ialu_imm);
6650 %}
6651
6652 instruct cmovLI_reg(cmpOp cmp, flagsReg icc, iRegL dst, iRegL src) %{
6653 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src)));
6654 ins_cost(150);
6655
6656 size(4);
6657 format %{ "MOV$cmp $icc,$src,$dst\t! long" %}
6658 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6659 ins_pipe(ialu_reg);
6660 %}
6661
6662
6663 instruct cmovLF_reg(cmpOpF cmp, flagsRegF fcc, iRegL dst, iRegL src) %{
6664 match(Set dst (CMoveL (Binary cmp fcc) (Binary dst src)));
6665 ins_cost(150);
6666
6667 size(4);
6668 format %{ "MOV$cmp $fcc,$src,$dst\t! long" %}
6669 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6670 ins_pipe(ialu_reg);
6671 %}
6672
6673
6674
6675 //----------OS and Locking Instructions----------------------------------------
6676
6677 // This name is KNOWN by the ADLC and cannot be changed.
6678 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
6679 // for this guy.
6680 instruct tlsLoadP(g2RegP dst) %{
6681 match(Set dst (ThreadLocal));
6682
6683 size(0);
6684 ins_cost(0);
6685 format %{ "# TLS is in G2" %}
6686 ins_encode( /*empty encoding*/ );
6687 ins_pipe(ialu_none);
6688 %}
6689
6690 instruct checkCastPP( iRegP dst ) %{
6691 match(Set dst (CheckCastPP dst));
6692
6693 size(0);
6694 format %{ "# checkcastPP of $dst" %}
6695 ins_encode( /*empty encoding*/ );
6696 ins_pipe(empty);
6697 %}
6698
6699
6700 instruct castPP( iRegP dst ) %{
6701 match(Set dst (CastPP dst));
6702 format %{ "# castPP of $dst" %}
6703 ins_encode( /*empty encoding*/ );
6704 ins_pipe(empty);
6705 %}
6706
6707 instruct castII( iRegI dst ) %{
6708 match(Set dst (CastII dst));
6709 format %{ "# castII of $dst" %}
6710 ins_encode( /*empty encoding*/ );
6711 ins_cost(0);
6712 ins_pipe(empty);
6713 %}
6714
6715 //----------Arithmetic Instructions--------------------------------------------
6716 // Addition Instructions
6717 // Register Addition
6718 instruct addI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
6719 match(Set dst (AddI src1 src2));
6720
6721 size(4);
6722 format %{ "ADD $src1,$src2,$dst" %}
6723 ins_encode %{
6724 __ add($src1$$Register, $src2$$Register, $dst$$Register);
6725 %}
6726 ins_pipe(ialu_reg_reg);
6727 %}
6728
6729 // Immediate Addition
6730 instruct addI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
6731 match(Set dst (AddI src1 src2));
6732
6733 size(4);
6734 format %{ "ADD $src1,$src2,$dst" %}
6735 opcode(Assembler::add_op3, Assembler::arith_op);
6736 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
6737 ins_pipe(ialu_reg_imm);
6738 %}
6739
6740 // Pointer Register Addition
6741 instruct addP_reg_reg(iRegP dst, iRegP src1, iRegX src2) %{
6742 match(Set dst (AddP src1 src2));
6743
6744 size(4);
6745 format %{ "ADD $src1,$src2,$dst" %}
6746 opcode(Assembler::add_op3, Assembler::arith_op);
6747 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
6748 ins_pipe(ialu_reg_reg);
6749 %}
6750
6751 // Pointer Immediate Addition
6752 instruct addP_reg_imm13(iRegP dst, iRegP src1, immX13 src2) %{
6753 match(Set dst (AddP src1 src2));
6754
6755 size(4);
6756 format %{ "ADD $src1,$src2,$dst" %}
6757 opcode(Assembler::add_op3, Assembler::arith_op);
6758 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
6759 ins_pipe(ialu_reg_imm);
6760 %}
6761
6762 // Long Addition
6763 instruct addL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
6764 match(Set dst (AddL src1 src2));
6765
6766 size(4);
6767 format %{ "ADD $src1,$src2,$dst\t! long" %}
6768 opcode(Assembler::add_op3, Assembler::arith_op);
6769 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
6770 ins_pipe(ialu_reg_reg);
6771 %}
6772
6773 instruct addL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
6774 match(Set dst (AddL src1 con));
6775
6776 size(4);
6777 format %{ "ADD $src1,$con,$dst" %}
6778 opcode(Assembler::add_op3, Assembler::arith_op);
6779 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
6780 ins_pipe(ialu_reg_imm);
6781 %}
6782
6783 //----------Conditional_store--------------------------------------------------
6784 // Conditional-store of the updated heap-top.
6785 // Used during allocation of the shared heap.
6786 // Sets flags (EQ) on success. Implemented with a CASA on Sparc.
6787
6788 // LoadP-locked. Same as a regular pointer load when used with a compare-swap
6789 instruct loadPLocked(iRegP dst, memory mem) %{
6790 match(Set dst (LoadPLocked mem));
6791 ins_cost(MEMORY_REF_COST);
6792
6793 #ifndef _LP64
6794 size(4);
6795 format %{ "LDUW $mem,$dst\t! ptr" %}
6796 opcode(Assembler::lduw_op3, 0, REGP_OP);
6797 #else
6798 format %{ "LDX $mem,$dst\t! ptr" %}
6799 opcode(Assembler::ldx_op3, 0, REGP_OP);
6800 #endif
6801 ins_encode( form3_mem_reg( mem, dst ) );
6802 ins_pipe(iload_mem);
6803 %}
6804
6805 // LoadL-locked. Same as a regular long load when used with a compare-swap
6806 instruct loadLLocked(iRegL dst, memory mem) %{
6807 match(Set dst (LoadLLocked mem));
6808 ins_cost(MEMORY_REF_COST);
6809 size(4);
6810 format %{ "LDX $mem,$dst\t! long" %}
6811 opcode(Assembler::ldx_op3);
6812 ins_encode(simple_form3_mem_reg( mem, dst ) );
6813 ins_pipe(iload_mem);
6814 %}
6815
6816 instruct storePConditional( iRegP heap_top_ptr, iRegP oldval, g3RegP newval, flagsRegP pcc ) %{
6817 match(Set pcc (StorePConditional heap_top_ptr (Binary oldval newval)));
6818 effect( KILL newval );
6819 format %{ "CASA [$heap_top_ptr],$oldval,R_G3\t! If $oldval==[$heap_top_ptr] Then store R_G3 into [$heap_top_ptr], set R_G3=[$heap_top_ptr] in any case\n\t"
6820 "CMP R_G3,$oldval\t\t! See if we made progress" %}
6821 ins_encode( enc_cas(heap_top_ptr,oldval,newval) );
6822 ins_pipe( long_memory_op );
6823 %}
6824
6825 // Conditional-store of an int value.
6826 instruct storeIConditional( iRegP mem_ptr, iRegI oldval, g3RegI newval, flagsReg icc ) %{
6827 match(Set icc (StoreIConditional mem_ptr (Binary oldval newval)));
6828 effect( KILL newval );
6829 format %{ "CASA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t"
6830 "CMP $oldval,$newval\t\t! See if we made progress" %}
6831 ins_encode( enc_cas(mem_ptr,oldval,newval) );
6832 ins_pipe( long_memory_op );
6833 %}
6834
6835 // Conditional-store of a long value.
6836 instruct storeLConditional( iRegP mem_ptr, iRegL oldval, g3RegL newval, flagsRegL xcc ) %{
6837 match(Set xcc (StoreLConditional mem_ptr (Binary oldval newval)));
6838 effect( KILL newval );
6839 format %{ "CASXA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t"
6840 "CMP $oldval,$newval\t\t! See if we made progress" %}
6841 ins_encode( enc_cas(mem_ptr,oldval,newval) );
6842 ins_pipe( long_memory_op );
6843 %}
6844
6845 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
6846
6847 instruct compareAndSwapL_bool(iRegP mem_ptr, iRegL oldval, iRegL newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
6848 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
6849 effect( USE mem_ptr, KILL ccr, KILL tmp1);
6850 format %{
6851 "MOV $newval,O7\n\t"
6852 "CASXA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
6853 "CMP $oldval,O7\t\t! See if we made progress\n\t"
6854 "MOV 1,$res\n\t"
6855 "MOVne xcc,R_G0,$res"
6856 %}
6857 ins_encode( enc_casx(mem_ptr, oldval, newval),
6858 enc_lflags_ne_to_boolean(res) );
6859 ins_pipe( long_memory_op );
6860 %}
6861
6862
6863 instruct compareAndSwapI_bool(iRegP mem_ptr, iRegI oldval, iRegI newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
6864 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
6865 effect( USE mem_ptr, KILL ccr, KILL tmp1);
6866 format %{
6867 "MOV $newval,O7\n\t"
6868 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
6869 "CMP $oldval,O7\t\t! See if we made progress\n\t"
6870 "MOV 1,$res\n\t"
6871 "MOVne icc,R_G0,$res"
6872 %}
6873 ins_encode( enc_casi(mem_ptr, oldval, newval),
6874 enc_iflags_ne_to_boolean(res) );
6875 ins_pipe( long_memory_op );
6876 %}
6877
6878 instruct compareAndSwapP_bool(iRegP mem_ptr, iRegP oldval, iRegP newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
6879 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
6880 effect( USE mem_ptr, KILL ccr, KILL tmp1);
6881 format %{
6882 "MOV $newval,O7\n\t"
6883 "CASA_PTR [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
6884 "CMP $oldval,O7\t\t! See if we made progress\n\t"
6885 "MOV 1,$res\n\t"
6886 "MOVne xcc,R_G0,$res"
6887 %}
6888 #ifdef _LP64
6889 ins_encode( enc_casx(mem_ptr, oldval, newval),
6890 enc_lflags_ne_to_boolean(res) );
6891 #else
6892 ins_encode( enc_casi(mem_ptr, oldval, newval),
6893 enc_iflags_ne_to_boolean(res) );
6894 #endif
6895 ins_pipe( long_memory_op );
6896 %}
6897
6898 instruct compareAndSwapN_bool(iRegP mem_ptr, iRegN oldval, iRegN newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
6899 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval)));
6900 effect( USE mem_ptr, KILL ccr, KILL tmp1);
6901 format %{
6902 "MOV $newval,O7\n\t"
6903 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
6904 "CMP $oldval,O7\t\t! See if we made progress\n\t"
6905 "MOV 1,$res\n\t"
6906 "MOVne icc,R_G0,$res"
6907 %}
6908 ins_encode( enc_casi(mem_ptr, oldval, newval),
6909 enc_iflags_ne_to_boolean(res) );
6910 ins_pipe( long_memory_op );
6911 %}
6912
6913 //---------------------
6914 // Subtraction Instructions
6915 // Register Subtraction
6916 instruct subI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
6917 match(Set dst (SubI src1 src2));
6918
6919 size(4);
6920 format %{ "SUB $src1,$src2,$dst" %}
6921 opcode(Assembler::sub_op3, Assembler::arith_op);
6922 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
6923 ins_pipe(ialu_reg_reg);
6924 %}
6925
6926 // Immediate Subtraction
6927 instruct subI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
6928 match(Set dst (SubI src1 src2));
6929
6930 size(4);
6931 format %{ "SUB $src1,$src2,$dst" %}
6932 opcode(Assembler::sub_op3, Assembler::arith_op);
6933 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
6934 ins_pipe(ialu_reg_imm);
6935 %}
6936
6937 instruct subI_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{
6938 match(Set dst (SubI zero src2));
6939
6940 size(4);
6941 format %{ "NEG $src2,$dst" %}
6942 opcode(Assembler::sub_op3, Assembler::arith_op);
6943 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) );
6944 ins_pipe(ialu_zero_reg);
6945 %}
6946
6947 // Long subtraction
6948 instruct subL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
6949 match(Set dst (SubL src1 src2));
6950
6951 size(4);
6952 format %{ "SUB $src1,$src2,$dst\t! long" %}
6953 opcode(Assembler::sub_op3, Assembler::arith_op);
6954 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
6955 ins_pipe(ialu_reg_reg);
6956 %}
6957
6958 // Immediate Subtraction
6959 instruct subL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
6960 match(Set dst (SubL src1 con));
6961
6962 size(4);
6963 format %{ "SUB $src1,$con,$dst\t! long" %}
6964 opcode(Assembler::sub_op3, Assembler::arith_op);
6965 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
6966 ins_pipe(ialu_reg_imm);
6967 %}
6968
6969 // Long negation
6970 instruct negL_reg_reg(iRegL dst, immL0 zero, iRegL src2) %{
6971 match(Set dst (SubL zero src2));
6972
6973 size(4);
6974 format %{ "NEG $src2,$dst\t! long" %}
6975 opcode(Assembler::sub_op3, Assembler::arith_op);
6976 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) );
6977 ins_pipe(ialu_zero_reg);
6978 %}
6979
6980 // Multiplication Instructions
6981 // Integer Multiplication
6982 // Register Multiplication
6983 instruct mulI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
6984 match(Set dst (MulI src1 src2));
6985
6986 size(4);
6987 format %{ "MULX $src1,$src2,$dst" %}
6988 opcode(Assembler::mulx_op3, Assembler::arith_op);
6989 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
6990 ins_pipe(imul_reg_reg);
6991 %}
6992
6993 // Immediate Multiplication
6994 instruct mulI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
6995 match(Set dst (MulI src1 src2));
6996
6997 size(4);
6998 format %{ "MULX $src1,$src2,$dst" %}
6999 opcode(Assembler::mulx_op3, Assembler::arith_op);
7000 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7001 ins_pipe(imul_reg_imm);
7002 %}
7003
7004 instruct mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7005 match(Set dst (MulL src1 src2));
7006 ins_cost(DEFAULT_COST * 5);
7007 size(4);
7008 format %{ "MULX $src1,$src2,$dst\t! long" %}
7009 opcode(Assembler::mulx_op3, Assembler::arith_op);
7010 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7011 ins_pipe(mulL_reg_reg);
7012 %}
7013
7014 // Immediate Multiplication
7015 instruct mulL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7016 match(Set dst (MulL src1 src2));
7017 ins_cost(DEFAULT_COST * 5);
7018 size(4);
7019 format %{ "MULX $src1,$src2,$dst" %}
7020 opcode(Assembler::mulx_op3, Assembler::arith_op);
7021 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7022 ins_pipe(mulL_reg_imm);
7023 %}
7024
7025 // Integer Division
7026 // Register Division
7027 instruct divI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2) %{
7028 match(Set dst (DivI src1 src2));
7029 ins_cost((2+71)*DEFAULT_COST);
7030
7031 format %{ "SRA $src2,0,$src2\n\t"
7032 "SRA $src1,0,$src1\n\t"
7033 "SDIVX $src1,$src2,$dst" %}
7034 ins_encode( idiv_reg( src1, src2, dst ) );
7035 ins_pipe(sdiv_reg_reg);
7036 %}
7037
7038 // Immediate Division
7039 instruct divI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2) %{
7040 match(Set dst (DivI src1 src2));
7041 ins_cost((2+71)*DEFAULT_COST);
7042
7043 format %{ "SRA $src1,0,$src1\n\t"
7044 "SDIVX $src1,$src2,$dst" %}
7045 ins_encode( idiv_imm( src1, src2, dst ) );
7046 ins_pipe(sdiv_reg_imm);
7047 %}
7048
7049 //----------Div-By-10-Expansion------------------------------------------------
7050 // Extract hi bits of a 32x32->64 bit multiply.
7051 // Expand rule only, not matched
7052 instruct mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2 ) %{
7053 effect( DEF dst, USE src1, USE src2 );
7054 format %{ "MULX $src1,$src2,$dst\t! Used in div-by-10\n\t"
7055 "SRLX $dst,#32,$dst\t\t! Extract only hi word of result" %}
7056 ins_encode( enc_mul_hi(dst,src1,src2));
7057 ins_pipe(sdiv_reg_reg);
7058 %}
7059
7060 // Magic constant, reciprocal of 10
7061 instruct loadConI_x66666667(iRegIsafe dst) %{
7062 effect( DEF dst );
7063
7064 size(8);
7065 format %{ "SET 0x66666667,$dst\t! Used in div-by-10" %}
7066 ins_encode( Set32(0x66666667, dst) );
7067 ins_pipe(ialu_hi_lo_reg);
7068 %}
7069
7070 // Register Shift Right Arithmetic Long by 32-63
7071 instruct sra_31( iRegI dst, iRegI src ) %{
7072 effect( DEF dst, USE src );
7073 format %{ "SRA $src,31,$dst\t! Used in div-by-10" %}
7074 ins_encode( form3_rs1_rd_copysign_hi(src,dst) );
7075 ins_pipe(ialu_reg_reg);
7076 %}
7077
7078 // Arithmetic Shift Right by 8-bit immediate
7079 instruct sra_reg_2( iRegI dst, iRegI src ) %{
7080 effect( DEF dst, USE src );
7081 format %{ "SRA $src,2,$dst\t! Used in div-by-10" %}
7082 opcode(Assembler::sra_op3, Assembler::arith_op);
7083 ins_encode( form3_rs1_simm13_rd( src, 0x2, dst ) );
7084 ins_pipe(ialu_reg_imm);
7085 %}
7086
7087 // Integer DIV with 10
7088 instruct divI_10( iRegI dst, iRegIsafe src, immI10 div ) %{
7089 match(Set dst (DivI src div));
7090 ins_cost((6+6)*DEFAULT_COST);
7091 expand %{
7092 iRegIsafe tmp1; // Killed temps;
7093 iRegIsafe tmp2; // Killed temps;
7094 iRegI tmp3; // Killed temps;
7095 iRegI tmp4; // Killed temps;
7096 loadConI_x66666667( tmp1 ); // SET 0x66666667 -> tmp1
7097 mul_hi( tmp2, src, tmp1 ); // MUL hibits(src * tmp1) -> tmp2
7098 sra_31( tmp3, src ); // SRA src,31 -> tmp3
7099 sra_reg_2( tmp4, tmp2 ); // SRA tmp2,2 -> tmp4
7100 subI_reg_reg( dst,tmp4,tmp3); // SUB tmp4 - tmp3 -> dst
7101 %}
7102 %}
7103
7104 // Register Long Division
7105 instruct divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7106 match(Set dst (DivL src1 src2));
7107 ins_cost(DEFAULT_COST*71);
7108 size(4);
7109 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7110 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7111 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7112 ins_pipe(divL_reg_reg);
7113 %}
7114
7115 // Register Long Division
7116 instruct divL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7117 match(Set dst (DivL src1 src2));
7118 ins_cost(DEFAULT_COST*71);
7119 size(4);
7120 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7121 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7122 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7123 ins_pipe(divL_reg_imm);
7124 %}
7125
7126 // Integer Remainder
7127 // Register Remainder
7128 instruct modI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2, o7RegP temp, flagsReg ccr ) %{
7129 match(Set dst (ModI src1 src2));
7130 effect( KILL ccr, KILL temp);
7131
7132 format %{ "SREM $src1,$src2,$dst" %}
7133 ins_encode( irem_reg(src1, src2, dst, temp) );
7134 ins_pipe(sdiv_reg_reg);
7135 %}
7136
7137 // Immediate Remainder
7138 instruct modI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2, o7RegP temp, flagsReg ccr ) %{
7139 match(Set dst (ModI src1 src2));
7140 effect( KILL ccr, KILL temp);
7141
7142 format %{ "SREM $src1,$src2,$dst" %}
7143 ins_encode( irem_imm(src1, src2, dst, temp) );
7144 ins_pipe(sdiv_reg_imm);
7145 %}
7146
7147 // Register Long Remainder
7148 instruct divL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7149 effect(DEF dst, USE src1, USE src2);
7150 size(4);
7151 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7152 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7153 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7154 ins_pipe(divL_reg_reg);
7155 %}
7156
7157 // Register Long Division
7158 instruct divL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{
7159 effect(DEF dst, USE src1, USE src2);
7160 size(4);
7161 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7162 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7163 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7164 ins_pipe(divL_reg_imm);
7165 %}
7166
7167 instruct mulL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7168 effect(DEF dst, USE src1, USE src2);
7169 size(4);
7170 format %{ "MULX $src1,$src2,$dst\t! long" %}
7171 opcode(Assembler::mulx_op3, Assembler::arith_op);
7172 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7173 ins_pipe(mulL_reg_reg);
7174 %}
7175
7176 // Immediate Multiplication
7177 instruct mulL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{
7178 effect(DEF dst, USE src1, USE src2);
7179 size(4);
7180 format %{ "MULX $src1,$src2,$dst" %}
7181 opcode(Assembler::mulx_op3, Assembler::arith_op);
7182 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7183 ins_pipe(mulL_reg_imm);
7184 %}
7185
7186 instruct subL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7187 effect(DEF dst, USE src1, USE src2);
7188 size(4);
7189 format %{ "SUB $src1,$src2,$dst\t! long" %}
7190 opcode(Assembler::sub_op3, Assembler::arith_op);
7191 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7192 ins_pipe(ialu_reg_reg);
7193 %}
7194
7195 instruct subL_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{
7196 effect(DEF dst, USE src1, USE src2);
7197 size(4);
7198 format %{ "SUB $src1,$src2,$dst\t! long" %}
7199 opcode(Assembler::sub_op3, Assembler::arith_op);
7200 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7201 ins_pipe(ialu_reg_reg);
7202 %}
7203
7204 // Register Long Remainder
7205 instruct modL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7206 match(Set dst (ModL src1 src2));
7207 ins_cost(DEFAULT_COST*(71 + 6 + 1));
7208 expand %{
7209 iRegL tmp1;
7210 iRegL tmp2;
7211 divL_reg_reg_1(tmp1, src1, src2);
7212 mulL_reg_reg_1(tmp2, tmp1, src2);
7213 subL_reg_reg_1(dst, src1, tmp2);
7214 %}
7215 %}
7216
7217 // Register Long Remainder
7218 instruct modL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7219 match(Set dst (ModL src1 src2));
7220 ins_cost(DEFAULT_COST*(71 + 6 + 1));
7221 expand %{
7222 iRegL tmp1;
7223 iRegL tmp2;
7224 divL_reg_imm13_1(tmp1, src1, src2);
7225 mulL_reg_imm13_1(tmp2, tmp1, src2);
7226 subL_reg_reg_2 (dst, src1, tmp2);
7227 %}
7228 %}
7229
7230 // Integer Shift Instructions
7231 // Register Shift Left
7232 instruct shlI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7233 match(Set dst (LShiftI src1 src2));
7234
7235 size(4);
7236 format %{ "SLL $src1,$src2,$dst" %}
7237 opcode(Assembler::sll_op3, Assembler::arith_op);
7238 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7239 ins_pipe(ialu_reg_reg);
7240 %}
7241
7242 // Register Shift Left Immediate
7243 instruct shlI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7244 match(Set dst (LShiftI src1 src2));
7245
7246 size(4);
7247 format %{ "SLL $src1,$src2,$dst" %}
7248 opcode(Assembler::sll_op3, Assembler::arith_op);
7249 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7250 ins_pipe(ialu_reg_imm);
7251 %}
7252
7253 // Register Shift Left
7254 instruct shlL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7255 match(Set dst (LShiftL src1 src2));
7256
7257 size(4);
7258 format %{ "SLLX $src1,$src2,$dst" %}
7259 opcode(Assembler::sllx_op3, Assembler::arith_op);
7260 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7261 ins_pipe(ialu_reg_reg);
7262 %}
7263
7264 // Register Shift Left Immediate
7265 instruct shlL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7266 match(Set dst (LShiftL src1 src2));
7267
7268 size(4);
7269 format %{ "SLLX $src1,$src2,$dst" %}
7270 opcode(Assembler::sllx_op3, Assembler::arith_op);
7271 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7272 ins_pipe(ialu_reg_imm);
7273 %}
7274
7275 // Register Arithmetic Shift Right
7276 instruct sarI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7277 match(Set dst (RShiftI src1 src2));
7278 size(4);
7279 format %{ "SRA $src1,$src2,$dst" %}
7280 opcode(Assembler::sra_op3, Assembler::arith_op);
7281 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7282 ins_pipe(ialu_reg_reg);
7283 %}
7284
7285 // Register Arithmetic Shift Right Immediate
7286 instruct sarI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7287 match(Set dst (RShiftI src1 src2));
7288
7289 size(4);
7290 format %{ "SRA $src1,$src2,$dst" %}
7291 opcode(Assembler::sra_op3, Assembler::arith_op);
7292 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7293 ins_pipe(ialu_reg_imm);
7294 %}
7295
7296 // Register Shift Right Arithmatic Long
7297 instruct sarL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7298 match(Set dst (RShiftL src1 src2));
7299
7300 size(4);
7301 format %{ "SRAX $src1,$src2,$dst" %}
7302 opcode(Assembler::srax_op3, Assembler::arith_op);
7303 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7304 ins_pipe(ialu_reg_reg);
7305 %}
7306
7307 // Register Shift Left Immediate
7308 instruct sarL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7309 match(Set dst (RShiftL src1 src2));
7310
7311 size(4);
7312 format %{ "SRAX $src1,$src2,$dst" %}
7313 opcode(Assembler::srax_op3, Assembler::arith_op);
7314 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7315 ins_pipe(ialu_reg_imm);
7316 %}
7317
7318 // Register Shift Right
7319 instruct shrI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7320 match(Set dst (URShiftI src1 src2));
7321
7322 size(4);
7323 format %{ "SRL $src1,$src2,$dst" %}
7324 opcode(Assembler::srl_op3, Assembler::arith_op);
7325 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7326 ins_pipe(ialu_reg_reg);
7327 %}
7328
7329 // Register Shift Right Immediate
7330 instruct shrI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7331 match(Set dst (URShiftI src1 src2));
7332
7333 size(4);
7334 format %{ "SRL $src1,$src2,$dst" %}
7335 opcode(Assembler::srl_op3, Assembler::arith_op);
7336 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7337 ins_pipe(ialu_reg_imm);
7338 %}
7339
7340 // Register Shift Right
7341 instruct shrL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7342 match(Set dst (URShiftL src1 src2));
7343
7344 size(4);
7345 format %{ "SRLX $src1,$src2,$dst" %}
7346 opcode(Assembler::srlx_op3, Assembler::arith_op);
7347 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7348 ins_pipe(ialu_reg_reg);
7349 %}
7350
7351 // Register Shift Right Immediate
7352 instruct shrL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7353 match(Set dst (URShiftL src1 src2));
7354
7355 size(4);
7356 format %{ "SRLX $src1,$src2,$dst" %}
7357 opcode(Assembler::srlx_op3, Assembler::arith_op);
7358 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7359 ins_pipe(ialu_reg_imm);
7360 %}
7361
7362 // Register Shift Right Immediate with a CastP2X
7363 #ifdef _LP64
7364 instruct shrP_reg_imm6(iRegL dst, iRegP src1, immU6 src2) %{
7365 match(Set dst (URShiftL (CastP2X src1) src2));
7366 size(4);
7367 format %{ "SRLX $src1,$src2,$dst\t! Cast ptr $src1 to long and shift" %}
7368 opcode(Assembler::srlx_op3, Assembler::arith_op);
7369 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7370 ins_pipe(ialu_reg_imm);
7371 %}
7372 #else
7373 instruct shrP_reg_imm5(iRegI dst, iRegP src1, immU5 src2) %{
7374 match(Set dst (URShiftI (CastP2X src1) src2));
7375 size(4);
7376 format %{ "SRL $src1,$src2,$dst\t! Cast ptr $src1 to int and shift" %}
7377 opcode(Assembler::srl_op3, Assembler::arith_op);
7378 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7379 ins_pipe(ialu_reg_imm);
7380 %}
7381 #endif
7382
7383
7384 //----------Floating Point Arithmetic Instructions-----------------------------
7385
7386 // Add float single precision
7387 instruct addF_reg_reg(regF dst, regF src1, regF src2) %{
7388 match(Set dst (AddF src1 src2));
7389
7390 size(4);
7391 format %{ "FADDS $src1,$src2,$dst" %}
7392 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fadds_opf);
7393 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7394 ins_pipe(faddF_reg_reg);
7395 %}
7396
7397 // Add float double precision
7398 instruct addD_reg_reg(regD dst, regD src1, regD src2) %{
7399 match(Set dst (AddD src1 src2));
7400
7401 size(4);
7402 format %{ "FADDD $src1,$src2,$dst" %}
7403 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf);
7404 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7405 ins_pipe(faddD_reg_reg);
7406 %}
7407
7408 // Sub float single precision
7409 instruct subF_reg_reg(regF dst, regF src1, regF src2) %{
7410 match(Set dst (SubF src1 src2));
7411
7412 size(4);
7413 format %{ "FSUBS $src1,$src2,$dst" %}
7414 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubs_opf);
7415 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7416 ins_pipe(faddF_reg_reg);
7417 %}
7418
7419 // Sub float double precision
7420 instruct subD_reg_reg(regD dst, regD src1, regD src2) %{
7421 match(Set dst (SubD src1 src2));
7422
7423 size(4);
7424 format %{ "FSUBD $src1,$src2,$dst" %}
7425 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf);
7426 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7427 ins_pipe(faddD_reg_reg);
7428 %}
7429
7430 // Mul float single precision
7431 instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{
7432 match(Set dst (MulF src1 src2));
7433
7434 size(4);
7435 format %{ "FMULS $src1,$src2,$dst" %}
7436 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuls_opf);
7437 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7438 ins_pipe(fmulF_reg_reg);
7439 %}
7440
7441 // Mul float double precision
7442 instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{
7443 match(Set dst (MulD src1 src2));
7444
7445 size(4);
7446 format %{ "FMULD $src1,$src2,$dst" %}
7447 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf);
7448 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7449 ins_pipe(fmulD_reg_reg);
7450 %}
7451
7452 // Div float single precision
7453 instruct divF_reg_reg(regF dst, regF src1, regF src2) %{
7454 match(Set dst (DivF src1 src2));
7455
7456 size(4);
7457 format %{ "FDIVS $src1,$src2,$dst" %}
7458 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivs_opf);
7459 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7460 ins_pipe(fdivF_reg_reg);
7461 %}
7462
7463 // Div float double precision
7464 instruct divD_reg_reg(regD dst, regD src1, regD src2) %{
7465 match(Set dst (DivD src1 src2));
7466
7467 size(4);
7468 format %{ "FDIVD $src1,$src2,$dst" %}
7469 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivd_opf);
7470 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7471 ins_pipe(fdivD_reg_reg);
7472 %}
7473
7474 // Absolute float double precision
7475 instruct absD_reg(regD dst, regD src) %{
7476 match(Set dst (AbsD src));
7477
7478 format %{ "FABSd $src,$dst" %}
7479 ins_encode(fabsd(dst, src));
7480 ins_pipe(faddD_reg);
7481 %}
7482
7483 // Absolute float single precision
7484 instruct absF_reg(regF dst, regF src) %{
7485 match(Set dst (AbsF src));
7486
7487 format %{ "FABSs $src,$dst" %}
7488 ins_encode(fabss(dst, src));
7489 ins_pipe(faddF_reg);
7490 %}
7491
7492 instruct negF_reg(regF dst, regF src) %{
7493 match(Set dst (NegF src));
7494
7495 size(4);
7496 format %{ "FNEGs $src,$dst" %}
7497 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fnegs_opf);
7498 ins_encode(form3_opf_rs2F_rdF(src, dst));
7499 ins_pipe(faddF_reg);
7500 %}
7501
7502 instruct negD_reg(regD dst, regD src) %{
7503 match(Set dst (NegD src));
7504
7505 format %{ "FNEGd $src,$dst" %}
7506 ins_encode(fnegd(dst, src));
7507 ins_pipe(faddD_reg);
7508 %}
7509
7510 // Sqrt float double precision
7511 instruct sqrtF_reg_reg(regF dst, regF src) %{
7512 match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
7513
7514 size(4);
7515 format %{ "FSQRTS $src,$dst" %}
7516 ins_encode(fsqrts(dst, src));
7517 ins_pipe(fdivF_reg_reg);
7518 %}
7519
7520 // Sqrt float double precision
7521 instruct sqrtD_reg_reg(regD dst, regD src) %{
7522 match(Set dst (SqrtD src));
7523
7524 size(4);
7525 format %{ "FSQRTD $src,$dst" %}
7526 ins_encode(fsqrtd(dst, src));
7527 ins_pipe(fdivD_reg_reg);
7528 %}
7529
7530 //----------Logical Instructions-----------------------------------------------
7531 // And Instructions
7532 // Register And
7533 instruct andI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7534 match(Set dst (AndI src1 src2));
7535
7536 size(4);
7537 format %{ "AND $src1,$src2,$dst" %}
7538 opcode(Assembler::and_op3, Assembler::arith_op);
7539 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7540 ins_pipe(ialu_reg_reg);
7541 %}
7542
7543 // Immediate And
7544 instruct andI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7545 match(Set dst (AndI src1 src2));
7546
7547 size(4);
7548 format %{ "AND $src1,$src2,$dst" %}
7549 opcode(Assembler::and_op3, Assembler::arith_op);
7550 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7551 ins_pipe(ialu_reg_imm);
7552 %}
7553
7554 // Register And Long
7555 instruct andL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7556 match(Set dst (AndL src1 src2));
7557
7558 ins_cost(DEFAULT_COST);
7559 size(4);
7560 format %{ "AND $src1,$src2,$dst\t! long" %}
7561 opcode(Assembler::and_op3, Assembler::arith_op);
7562 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7563 ins_pipe(ialu_reg_reg);
7564 %}
7565
7566 instruct andL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7567 match(Set dst (AndL src1 con));
7568
7569 ins_cost(DEFAULT_COST);
7570 size(4);
7571 format %{ "AND $src1,$con,$dst\t! long" %}
7572 opcode(Assembler::and_op3, Assembler::arith_op);
7573 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7574 ins_pipe(ialu_reg_imm);
7575 %}
7576
7577 // Or Instructions
7578 // Register Or
7579 instruct orI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7580 match(Set dst (OrI src1 src2));
7581
7582 size(4);
7583 format %{ "OR $src1,$src2,$dst" %}
7584 opcode(Assembler::or_op3, Assembler::arith_op);
7585 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7586 ins_pipe(ialu_reg_reg);
7587 %}
7588
7589 // Immediate Or
7590 instruct orI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7591 match(Set dst (OrI src1 src2));
7592
7593 size(4);
7594 format %{ "OR $src1,$src2,$dst" %}
7595 opcode(Assembler::or_op3, Assembler::arith_op);
7596 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7597 ins_pipe(ialu_reg_imm);
7598 %}
7599
7600 // Register Or Long
7601 instruct orL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7602 match(Set dst (OrL src1 src2));
7603
7604 ins_cost(DEFAULT_COST);
7605 size(4);
7606 format %{ "OR $src1,$src2,$dst\t! long" %}
7607 opcode(Assembler::or_op3, Assembler::arith_op);
7608 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7609 ins_pipe(ialu_reg_reg);
7610 %}
7611
7612 instruct orL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7613 match(Set dst (OrL src1 con));
7614 ins_cost(DEFAULT_COST*2);
7615
7616 ins_cost(DEFAULT_COST);
7617 size(4);
7618 format %{ "OR $src1,$con,$dst\t! long" %}
7619 opcode(Assembler::or_op3, Assembler::arith_op);
7620 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7621 ins_pipe(ialu_reg_imm);
7622 %}
7623
7624 #ifndef _LP64
7625
7626 // Use sp_ptr_RegP to match G2 (TLS register) without spilling.
7627 instruct orI_reg_castP2X(iRegI dst, iRegI src1, sp_ptr_RegP src2) %{
7628 match(Set dst (OrI src1 (CastP2X src2)));
7629
7630 size(4);
7631 format %{ "OR $src1,$src2,$dst" %}
7632 opcode(Assembler::or_op3, Assembler::arith_op);
7633 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7634 ins_pipe(ialu_reg_reg);
7635 %}
7636
7637 #else
7638
7639 instruct orL_reg_castP2X(iRegL dst, iRegL src1, sp_ptr_RegP src2) %{
7640 match(Set dst (OrL src1 (CastP2X src2)));
7641
7642 ins_cost(DEFAULT_COST);
7643 size(4);
7644 format %{ "OR $src1,$src2,$dst\t! long" %}
7645 opcode(Assembler::or_op3, Assembler::arith_op);
7646 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7647 ins_pipe(ialu_reg_reg);
7648 %}
7649
7650 #endif
7651
7652 // Xor Instructions
7653 // Register Xor
7654 instruct xorI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7655 match(Set dst (XorI src1 src2));
7656
7657 size(4);
7658 format %{ "XOR $src1,$src2,$dst" %}
7659 opcode(Assembler::xor_op3, Assembler::arith_op);
7660 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7661 ins_pipe(ialu_reg_reg);
7662 %}
7663
7664 // Immediate Xor
7665 instruct xorI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7666 match(Set dst (XorI src1 src2));
7667
7668 size(4);
7669 format %{ "XOR $src1,$src2,$dst" %}
7670 opcode(Assembler::xor_op3, Assembler::arith_op);
7671 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7672 ins_pipe(ialu_reg_imm);
7673 %}
7674
7675 // Register Xor Long
7676 instruct xorL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7677 match(Set dst (XorL src1 src2));
7678
7679 ins_cost(DEFAULT_COST);
7680 size(4);
7681 format %{ "XOR $src1,$src2,$dst\t! long" %}
7682 opcode(Assembler::xor_op3, Assembler::arith_op);
7683 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7684 ins_pipe(ialu_reg_reg);
7685 %}
7686
7687 instruct xorL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7688 match(Set dst (XorL src1 con));
7689
7690 ins_cost(DEFAULT_COST);
7691 size(4);
7692 format %{ "XOR $src1,$con,$dst\t! long" %}
7693 opcode(Assembler::xor_op3, Assembler::arith_op);
7694 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7695 ins_pipe(ialu_reg_imm);
7696 %}
7697
7698 //----------Convert to Boolean-------------------------------------------------
7699 // Nice hack for 32-bit tests but doesn't work for
7700 // 64-bit pointers.
7701 instruct convI2B( iRegI dst, iRegI src, flagsReg ccr ) %{
7702 match(Set dst (Conv2B src));
7703 effect( KILL ccr );
7704 ins_cost(DEFAULT_COST*2);
7705 format %{ "CMP R_G0,$src\n\t"
7706 "ADDX R_G0,0,$dst" %}
7707 ins_encode( enc_to_bool( src, dst ) );
7708 ins_pipe(ialu_reg_ialu);
7709 %}
7710
7711 #ifndef _LP64
7712 instruct convP2B( iRegI dst, iRegP src, flagsReg ccr ) %{
7713 match(Set dst (Conv2B src));
7714 effect( KILL ccr );
7715 ins_cost(DEFAULT_COST*2);
7716 format %{ "CMP R_G0,$src\n\t"
7717 "ADDX R_G0,0,$dst" %}
7718 ins_encode( enc_to_bool( src, dst ) );
7719 ins_pipe(ialu_reg_ialu);
7720 %}
7721 #else
7722 instruct convP2B( iRegI dst, iRegP src ) %{
7723 match(Set dst (Conv2B src));
7724 ins_cost(DEFAULT_COST*2);
7725 format %{ "MOV $src,$dst\n\t"
7726 "MOVRNZ $src,1,$dst" %}
7727 ins_encode( form3_g0_rs2_rd_move( src, dst ), enc_convP2B( dst, src ) );
7728 ins_pipe(ialu_clr_and_mover);
7729 %}
7730 #endif
7731
7732 instruct cmpLTMask_reg_reg( iRegI dst, iRegI p, iRegI q, flagsReg ccr ) %{
7733 match(Set dst (CmpLTMask p q));
7734 effect( KILL ccr );
7735 ins_cost(DEFAULT_COST*4);
7736 format %{ "CMP $p,$q\n\t"
7737 "MOV #0,$dst\n\t"
7738 "BLT,a .+8\n\t"
7739 "MOV #-1,$dst" %}
7740 ins_encode( enc_ltmask(p,q,dst) );
7741 ins_pipe(ialu_reg_reg_ialu);
7742 %}
7743
7744 instruct cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp, flagsReg ccr ) %{
7745 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
7746 effect(KILL ccr, TEMP tmp);
7747 ins_cost(DEFAULT_COST*3);
7748
7749 format %{ "SUBcc $p,$q,$p\t! p' = p-q\n\t"
7750 "ADD $p,$y,$tmp\t! g3=p-q+y\n\t"
7751 "MOVl $tmp,$p\t! p' < 0 ? p'+y : p'" %}
7752 ins_encode( enc_cadd_cmpLTMask(p, q, y, tmp) );
7753 ins_pipe( cadd_cmpltmask );
7754 %}
7755
7756 instruct cadd_cmpLTMask2( iRegI p, iRegI q, iRegI y, iRegI tmp, flagsReg ccr ) %{
7757 match(Set p (AddI (SubI p q) (AndI (CmpLTMask p q) y)));
7758 effect( KILL ccr, TEMP tmp);
7759 ins_cost(DEFAULT_COST*3);
7760
7761 format %{ "SUBcc $p,$q,$p\t! p' = p-q\n\t"
7762 "ADD $p,$y,$tmp\t! g3=p-q+y\n\t"
7763 "MOVl $tmp,$p\t! p' < 0 ? p'+y : p'" %}
7764 ins_encode( enc_cadd_cmpLTMask(p, q, y, tmp) );
7765 ins_pipe( cadd_cmpltmask );
7766 %}
7767
7768 //----------Arithmetic Conversion Instructions---------------------------------
7769 // The conversions operations are all Alpha sorted. Please keep it that way!
7770
7771 instruct convD2F_reg(regF dst, regD src) %{
7772 match(Set dst (ConvD2F src));
7773 size(4);
7774 format %{ "FDTOS $src,$dst" %}
7775 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdtos_opf);
7776 ins_encode(form3_opf_rs2D_rdF(src, dst));
7777 ins_pipe(fcvtD2F);
7778 %}
7779
7780
7781 // Convert a double to an int in a float register.
7782 // If the double is a NAN, stuff a zero in instead.
7783 instruct convD2I_helper(regF dst, regD src, flagsRegF0 fcc0) %{
7784 effect(DEF dst, USE src, KILL fcc0);
7785 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t"
7786 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
7787 "FDTOI $src,$dst\t! convert in delay slot\n\t"
7788 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t"
7789 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n"
7790 "skip:" %}
7791 ins_encode(form_d2i_helper(src,dst));
7792 ins_pipe(fcvtD2I);
7793 %}
7794
7795 instruct convD2I_reg(stackSlotI dst, regD src) %{
7796 match(Set dst (ConvD2I src));
7797 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
7798 expand %{
7799 regF tmp;
7800 convD2I_helper(tmp, src);
7801 regF_to_stkI(dst, tmp);
7802 %}
7803 %}
7804
7805 // Convert a double to a long in a double register.
7806 // If the double is a NAN, stuff a zero in instead.
7807 instruct convD2L_helper(regD dst, regD src, flagsRegF0 fcc0) %{
7808 effect(DEF dst, USE src, KILL fcc0);
7809 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t"
7810 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
7811 "FDTOX $src,$dst\t! convert in delay slot\n\t"
7812 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t"
7813 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n"
7814 "skip:" %}
7815 ins_encode(form_d2l_helper(src,dst));
7816 ins_pipe(fcvtD2L);
7817 %}
7818
7819
7820 // Double to Long conversion
7821 instruct convD2L_reg(stackSlotL dst, regD src) %{
7822 match(Set dst (ConvD2L src));
7823 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
7824 expand %{
7825 regD tmp;
7826 convD2L_helper(tmp, src);
7827 regD_to_stkL(dst, tmp);
7828 %}
7829 %}
7830
7831
7832 instruct convF2D_reg(regD dst, regF src) %{
7833 match(Set dst (ConvF2D src));
7834 format %{ "FSTOD $src,$dst" %}
7835 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fstod_opf);
7836 ins_encode(form3_opf_rs2F_rdD(src, dst));
7837 ins_pipe(fcvtF2D);
7838 %}
7839
7840
7841 instruct convF2I_helper(regF dst, regF src, flagsRegF0 fcc0) %{
7842 effect(DEF dst, USE src, KILL fcc0);
7843 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t"
7844 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
7845 "FSTOI $src,$dst\t! convert in delay slot\n\t"
7846 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t"
7847 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n"
7848 "skip:" %}
7849 ins_encode(form_f2i_helper(src,dst));
7850 ins_pipe(fcvtF2I);
7851 %}
7852
7853 instruct convF2I_reg(stackSlotI dst, regF src) %{
7854 match(Set dst (ConvF2I src));
7855 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
7856 expand %{
7857 regF tmp;
7858 convF2I_helper(tmp, src);
7859 regF_to_stkI(dst, tmp);
7860 %}
7861 %}
7862
7863
7864 instruct convF2L_helper(regD dst, regF src, flagsRegF0 fcc0) %{
7865 effect(DEF dst, USE src, KILL fcc0);
7866 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t"
7867 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
7868 "FSTOX $src,$dst\t! convert in delay slot\n\t"
7869 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t"
7870 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n"
7871 "skip:" %}
7872 ins_encode(form_f2l_helper(src,dst));
7873 ins_pipe(fcvtF2L);
7874 %}
7875
7876 // Float to Long conversion
7877 instruct convF2L_reg(stackSlotL dst, regF src) %{
7878 match(Set dst (ConvF2L src));
7879 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
7880 expand %{
7881 regD tmp;
7882 convF2L_helper(tmp, src);
7883 regD_to_stkL(dst, tmp);
7884 %}
7885 %}
7886
7887
7888 instruct convI2D_helper(regD dst, regF tmp) %{
7889 effect(USE tmp, DEF dst);
7890 format %{ "FITOD $tmp,$dst" %}
7891 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf);
7892 ins_encode(form3_opf_rs2F_rdD(tmp, dst));
7893 ins_pipe(fcvtI2D);
7894 %}
7895
7896 instruct convI2D_reg(stackSlotI src, regD dst) %{
7897 match(Set dst (ConvI2D src));
7898 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
7899 expand %{
7900 regF tmp;
7901 stkI_to_regF( tmp, src);
7902 convI2D_helper( dst, tmp);
7903 %}
7904 %}
7905
7906 instruct convI2D_mem( regD_low dst, memory mem ) %{
7907 match(Set dst (ConvI2D (LoadI mem)));
7908 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
7909 size(8);
7910 format %{ "LDF $mem,$dst\n\t"
7911 "FITOD $dst,$dst" %}
7912 opcode(Assembler::ldf_op3, Assembler::fitod_opf);
7913 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst));
7914 ins_pipe(floadF_mem);
7915 %}
7916
7917
7918 instruct convI2F_helper(regF dst, regF tmp) %{
7919 effect(DEF dst, USE tmp);
7920 format %{ "FITOS $tmp,$dst" %}
7921 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitos_opf);
7922 ins_encode(form3_opf_rs2F_rdF(tmp, dst));
7923 ins_pipe(fcvtI2F);
7924 %}
7925
7926 instruct convI2F_reg( regF dst, stackSlotI src ) %{
7927 match(Set dst (ConvI2F src));
7928 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
7929 expand %{
7930 regF tmp;
7931 stkI_to_regF(tmp,src);
7932 convI2F_helper(dst, tmp);
7933 %}
7934 %}
7935
7936 instruct convI2F_mem( regF dst, memory mem ) %{
7937 match(Set dst (ConvI2F (LoadI mem)));
7938 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
7939 size(8);
7940 format %{ "LDF $mem,$dst\n\t"
7941 "FITOS $dst,$dst" %}
7942 opcode(Assembler::ldf_op3, Assembler::fitos_opf);
7943 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst));
7944 ins_pipe(floadF_mem);
7945 %}
7946
7947
7948 instruct convI2L_reg(iRegL dst, iRegI src) %{
7949 match(Set dst (ConvI2L src));
7950 size(4);
7951 format %{ "SRA $src,0,$dst\t! int->long" %}
7952 opcode(Assembler::sra_op3, Assembler::arith_op);
7953 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
7954 ins_pipe(ialu_reg_reg);
7955 %}
7956
7957 // Zero-extend convert int to long
7958 instruct convI2L_reg_zex(iRegL dst, iRegI src, immL_32bits mask ) %{
7959 match(Set dst (AndL (ConvI2L src) mask) );
7960 size(4);
7961 format %{ "SRL $src,0,$dst\t! zero-extend int to long" %}
7962 opcode(Assembler::srl_op3, Assembler::arith_op);
7963 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
7964 ins_pipe(ialu_reg_reg);
7965 %}
7966
7967 // Zero-extend long
7968 instruct zerox_long(iRegL dst, iRegL src, immL_32bits mask ) %{
7969 match(Set dst (AndL src mask) );
7970 size(4);
7971 format %{ "SRL $src,0,$dst\t! zero-extend long" %}
7972 opcode(Assembler::srl_op3, Assembler::arith_op);
7973 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
7974 ins_pipe(ialu_reg_reg);
7975 %}
7976
7977 instruct MoveF2I_stack_reg(iRegI dst, stackSlotF src) %{
7978 match(Set dst (MoveF2I src));
7979 effect(DEF dst, USE src);
7980 ins_cost(MEMORY_REF_COST);
7981
7982 size(4);
7983 format %{ "LDUW $src,$dst\t! MoveF2I" %}
7984 opcode(Assembler::lduw_op3);
7985 ins_encode(simple_form3_mem_reg( src, dst ) );
7986 ins_pipe(iload_mem);
7987 %}
7988
7989 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
7990 match(Set dst (MoveI2F src));
7991 effect(DEF dst, USE src);
7992 ins_cost(MEMORY_REF_COST);
7993
7994 size(4);
7995 format %{ "LDF $src,$dst\t! MoveI2F" %}
7996 opcode(Assembler::ldf_op3);
7997 ins_encode(simple_form3_mem_reg(src, dst));
7998 ins_pipe(floadF_stk);
7999 %}
8000
8001 instruct MoveD2L_stack_reg(iRegL dst, stackSlotD src) %{
8002 match(Set dst (MoveD2L src));
8003 effect(DEF dst, USE src);
8004 ins_cost(MEMORY_REF_COST);
8005
8006 size(4);
8007 format %{ "LDX $src,$dst\t! MoveD2L" %}
8008 opcode(Assembler::ldx_op3);
8009 ins_encode(simple_form3_mem_reg( src, dst ) );
8010 ins_pipe(iload_mem);
8011 %}
8012
8013 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
8014 match(Set dst (MoveL2D src));
8015 effect(DEF dst, USE src);
8016 ins_cost(MEMORY_REF_COST);
8017
8018 size(4);
8019 format %{ "LDDF $src,$dst\t! MoveL2D" %}
8020 opcode(Assembler::lddf_op3);
8021 ins_encode(simple_form3_mem_reg(src, dst));
8022 ins_pipe(floadD_stk);
8023 %}
8024
8025 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{
8026 match(Set dst (MoveF2I src));
8027 effect(DEF dst, USE src);
8028 ins_cost(MEMORY_REF_COST);
8029
8030 size(4);
8031 format %{ "STF $src,$dst\t!MoveF2I" %}
8032 opcode(Assembler::stf_op3);
8033 ins_encode(simple_form3_mem_reg(dst, src));
8034 ins_pipe(fstoreF_stk_reg);
8035 %}
8036
8037 instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{
8038 match(Set dst (MoveI2F src));
8039 effect(DEF dst, USE src);
8040 ins_cost(MEMORY_REF_COST);
8041
8042 size(4);
8043 format %{ "STW $src,$dst\t!MoveI2F" %}
8044 opcode(Assembler::stw_op3);
8045 ins_encode(simple_form3_mem_reg( dst, src ) );
8046 ins_pipe(istore_mem_reg);
8047 %}
8048
8049 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
8050 match(Set dst (MoveD2L src));
8051 effect(DEF dst, USE src);
8052 ins_cost(MEMORY_REF_COST);
8053
8054 size(4);
8055 format %{ "STDF $src,$dst\t!MoveD2L" %}
8056 opcode(Assembler::stdf_op3);
8057 ins_encode(simple_form3_mem_reg(dst, src));
8058 ins_pipe(fstoreD_stk_reg);
8059 %}
8060
8061 instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{
8062 match(Set dst (MoveL2D src));
8063 effect(DEF dst, USE src);
8064 ins_cost(MEMORY_REF_COST);
8065
8066 size(4);
8067 format %{ "STX $src,$dst\t!MoveL2D" %}
8068 opcode(Assembler::stx_op3);
8069 ins_encode(simple_form3_mem_reg( dst, src ) );
8070 ins_pipe(istore_mem_reg);
8071 %}
8072
8073
8074 //-----------
8075 // Long to Double conversion using V8 opcodes.
8076 // Still useful because cheetah traps and becomes
8077 // amazingly slow for some common numbers.
8078
8079 // Magic constant, 0x43300000
8080 instruct loadConI_x43300000(iRegI dst) %{
8081 effect(DEF dst);
8082 size(4);
8083 format %{ "SETHI HI(0x43300000),$dst\t! 2^52" %}
8084 ins_encode(SetHi22(0x43300000, dst));
8085 ins_pipe(ialu_none);
8086 %}
8087
8088 // Magic constant, 0x41f00000
8089 instruct loadConI_x41f00000(iRegI dst) %{
8090 effect(DEF dst);
8091 size(4);
8092 format %{ "SETHI HI(0x41f00000),$dst\t! 2^32" %}
8093 ins_encode(SetHi22(0x41f00000, dst));
8094 ins_pipe(ialu_none);
8095 %}
8096
8097 // Construct a double from two float halves
8098 instruct regDHi_regDLo_to_regD(regD_low dst, regD_low src1, regD_low src2) %{
8099 effect(DEF dst, USE src1, USE src2);
8100 size(8);
8101 format %{ "FMOVS $src1.hi,$dst.hi\n\t"
8102 "FMOVS $src2.lo,$dst.lo" %}
8103 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmovs_opf);
8104 ins_encode(form3_opf_rs2D_hi_rdD_hi(src1, dst), form3_opf_rs2D_lo_rdD_lo(src2, dst));
8105 ins_pipe(faddD_reg_reg);
8106 %}
8107
8108 // Convert integer in high half of a double register (in the lower half of
8109 // the double register file) to double
8110 instruct convI2D_regDHi_regD(regD dst, regD_low src) %{
8111 effect(DEF dst, USE src);
8112 size(4);
8113 format %{ "FITOD $src,$dst" %}
8114 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf);
8115 ins_encode(form3_opf_rs2D_rdD(src, dst));
8116 ins_pipe(fcvtLHi2D);
8117 %}
8118
8119 // Add float double precision
8120 instruct addD_regD_regD(regD dst, regD src1, regD src2) %{
8121 effect(DEF dst, USE src1, USE src2);
8122 size(4);
8123 format %{ "FADDD $src1,$src2,$dst" %}
8124 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf);
8125 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8126 ins_pipe(faddD_reg_reg);
8127 %}
8128
8129 // Sub float double precision
8130 instruct subD_regD_regD(regD dst, regD src1, regD src2) %{
8131 effect(DEF dst, USE src1, USE src2);
8132 size(4);
8133 format %{ "FSUBD $src1,$src2,$dst" %}
8134 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf);
8135 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8136 ins_pipe(faddD_reg_reg);
8137 %}
8138
8139 // Mul float double precision
8140 instruct mulD_regD_regD(regD dst, regD src1, regD src2) %{
8141 effect(DEF dst, USE src1, USE src2);
8142 size(4);
8143 format %{ "FMULD $src1,$src2,$dst" %}
8144 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf);
8145 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8146 ins_pipe(fmulD_reg_reg);
8147 %}
8148
8149 instruct convL2D_reg_slow_fxtof(regD dst, stackSlotL src) %{
8150 match(Set dst (ConvL2D src));
8151 ins_cost(DEFAULT_COST*8 + MEMORY_REF_COST*6);
8152
8153 expand %{
8154 regD_low tmpsrc;
8155 iRegI ix43300000;
8156 iRegI ix41f00000;
8157 stackSlotL lx43300000;
8158 stackSlotL lx41f00000;
8159 regD_low dx43300000;
8160 regD dx41f00000;
8161 regD tmp1;
8162 regD_low tmp2;
8163 regD tmp3;
8164 regD tmp4;
8165
8166 stkL_to_regD(tmpsrc, src);
8167
8168 loadConI_x43300000(ix43300000);
8169 loadConI_x41f00000(ix41f00000);
8170 regI_to_stkLHi(lx43300000, ix43300000);
8171 regI_to_stkLHi(lx41f00000, ix41f00000);
8172 stkL_to_regD(dx43300000, lx43300000);
8173 stkL_to_regD(dx41f00000, lx41f00000);
8174
8175 convI2D_regDHi_regD(tmp1, tmpsrc);
8176 regDHi_regDLo_to_regD(tmp2, dx43300000, tmpsrc);
8177 subD_regD_regD(tmp3, tmp2, dx43300000);
8178 mulD_regD_regD(tmp4, tmp1, dx41f00000);
8179 addD_regD_regD(dst, tmp3, tmp4);
8180 %}
8181 %}
8182
8183 // Long to Double conversion using fast fxtof
8184 instruct convL2D_helper(regD dst, regD tmp) %{
8185 effect(DEF dst, USE tmp);
8186 size(4);
8187 format %{ "FXTOD $tmp,$dst" %}
8188 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtod_opf);
8189 ins_encode(form3_opf_rs2D_rdD(tmp, dst));
8190 ins_pipe(fcvtL2D);
8191 %}
8192
8193 instruct convL2D_reg_fast_fxtof(regD dst, stackSlotL src) %{
8194 predicate(VM_Version::has_fast_fxtof());
8195 match(Set dst (ConvL2D src));
8196 ins_cost(DEFAULT_COST + 3 * MEMORY_REF_COST);
8197 expand %{
8198 regD tmp;
8199 stkL_to_regD(tmp, src);
8200 convL2D_helper(dst, tmp);
8201 %}
8202 %}
8203
8204 //-----------
8205 // Long to Float conversion using V8 opcodes.
8206 // Still useful because cheetah traps and becomes
8207 // amazingly slow for some common numbers.
8208
8209 // Long to Float conversion using fast fxtof
8210 instruct convL2F_helper(regF dst, regD tmp) %{
8211 effect(DEF dst, USE tmp);
8212 size(4);
8213 format %{ "FXTOS $tmp,$dst" %}
8214 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtos_opf);
8215 ins_encode(form3_opf_rs2D_rdF(tmp, dst));
8216 ins_pipe(fcvtL2F);
8217 %}
8218
8219 instruct convL2F_reg_fast_fxtof(regF dst, stackSlotL src) %{
8220 match(Set dst (ConvL2F src));
8221 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8222 expand %{
8223 regD tmp;
8224 stkL_to_regD(tmp, src);
8225 convL2F_helper(dst, tmp);
8226 %}
8227 %}
8228 //-----------
8229
8230 instruct convL2I_reg(iRegI dst, iRegL src) %{
8231 match(Set dst (ConvL2I src));
8232 #ifndef _LP64
8233 format %{ "MOV $src.lo,$dst\t! long->int" %}
8234 ins_encode( form3_g0_rs2_rd_move_lo2( src, dst ) );
8235 ins_pipe(ialu_move_reg_I_to_L);
8236 #else
8237 size(4);
8238 format %{ "SRA $src,R_G0,$dst\t! long->int" %}
8239 ins_encode( form3_rs1_rd_signextend_lo1( src, dst ) );
8240 ins_pipe(ialu_reg);
8241 #endif
8242 %}
8243
8244 // Register Shift Right Immediate
8245 instruct shrL_reg_imm6_L2I(iRegI dst, iRegL src, immI_32_63 cnt) %{
8246 match(Set dst (ConvL2I (RShiftL src cnt)));
8247
8248 size(4);
8249 format %{ "SRAX $src,$cnt,$dst" %}
8250 opcode(Assembler::srax_op3, Assembler::arith_op);
8251 ins_encode( form3_sd_rs1_imm6_rd( src, cnt, dst ) );
8252 ins_pipe(ialu_reg_imm);
8253 %}
8254
8255 // Replicate scalar to packed byte values in Double register
8256 instruct Repl8B_reg_helper(iRegL dst, iRegI src) %{
8257 effect(DEF dst, USE src);
8258 format %{ "SLLX $src,56,$dst\n\t"
8259 "SRLX $dst, 8,O7\n\t"
8260 "OR $dst,O7,$dst\n\t"
8261 "SRLX $dst,16,O7\n\t"
8262 "OR $dst,O7,$dst\n\t"
8263 "SRLX $dst,32,O7\n\t"
8264 "OR $dst,O7,$dst\t! replicate8B" %}
8265 ins_encode( enc_repl8b(src, dst));
8266 ins_pipe(ialu_reg);
8267 %}
8268
8269 // Replicate scalar to packed byte values in Double register
8270 instruct Repl8B_reg(stackSlotD dst, iRegI src) %{
8271 match(Set dst (Replicate8B src));
8272 expand %{
8273 iRegL tmp;
8274 Repl8B_reg_helper(tmp, src);
8275 regL_to_stkD(dst, tmp);
8276 %}
8277 %}
8278
8279 // Replicate scalar constant to packed byte values in Double register
8280 instruct Repl8B_immI(regD dst, immI13 src, o7RegP tmp) %{
8281 match(Set dst (Replicate8B src));
8282 #ifdef _LP64
8283 size(36);
8284 #else
8285 size(8);
8286 #endif
8287 format %{ "SETHI hi(&Repl8($src)),$tmp\t!get Repl8B($src) from table\n\t"
8288 "LDDF [$tmp+lo(&Repl8($src))],$dst" %}
8289 ins_encode( LdReplImmI(src, dst, tmp, (8), (1)) );
8290 ins_pipe(loadConFD);
8291 %}
8292
8293 // Replicate scalar to packed char values into stack slot
8294 instruct Repl4C_reg_helper(iRegL dst, iRegI src) %{
8295 effect(DEF dst, USE src);
8296 format %{ "SLLX $src,48,$dst\n\t"
8297 "SRLX $dst,16,O7\n\t"
8298 "OR $dst,O7,$dst\n\t"
8299 "SRLX $dst,32,O7\n\t"
8300 "OR $dst,O7,$dst\t! replicate4C" %}
8301 ins_encode( enc_repl4s(src, dst) );
8302 ins_pipe(ialu_reg);
8303 %}
8304
8305 // Replicate scalar to packed char values into stack slot
8306 instruct Repl4C_reg(stackSlotD dst, iRegI src) %{
8307 match(Set dst (Replicate4C src));
8308 expand %{
8309 iRegL tmp;
8310 Repl4C_reg_helper(tmp, src);
8311 regL_to_stkD(dst, tmp);
8312 %}
8313 %}
8314
8315 // Replicate scalar constant to packed char values in Double register
8316 instruct Repl4C_immI(regD dst, immI src, o7RegP tmp) %{
8317 match(Set dst (Replicate4C src));
8318 #ifdef _LP64
8319 size(36);
8320 #else
8321 size(8);
8322 #endif
8323 format %{ "SETHI hi(&Repl4($src)),$tmp\t!get Repl4C($src) from table\n\t"
8324 "LDDF [$tmp+lo(&Repl4($src))],$dst" %}
8325 ins_encode( LdReplImmI(src, dst, tmp, (4), (2)) );
8326 ins_pipe(loadConFD);
8327 %}
8328
8329 // Replicate scalar to packed short values into stack slot
8330 instruct Repl4S_reg_helper(iRegL dst, iRegI src) %{
8331 effect(DEF dst, USE src);
8332 format %{ "SLLX $src,48,$dst\n\t"
8333 "SRLX $dst,16,O7\n\t"
8334 "OR $dst,O7,$dst\n\t"
8335 "SRLX $dst,32,O7\n\t"
8336 "OR $dst,O7,$dst\t! replicate4S" %}
8337 ins_encode( enc_repl4s(src, dst) );
8338 ins_pipe(ialu_reg);
8339 %}
8340
8341 // Replicate scalar to packed short values into stack slot
8342 instruct Repl4S_reg(stackSlotD dst, iRegI src) %{
8343 match(Set dst (Replicate4S src));
8344 expand %{
8345 iRegL tmp;
8346 Repl4S_reg_helper(tmp, src);
8347 regL_to_stkD(dst, tmp);
8348 %}
8349 %}
8350
8351 // Replicate scalar constant to packed short values in Double register
8352 instruct Repl4S_immI(regD dst, immI src, o7RegP tmp) %{
8353 match(Set dst (Replicate4S src));
8354 #ifdef _LP64
8355 size(36);
8356 #else
8357 size(8);
8358 #endif
8359 format %{ "SETHI hi(&Repl4($src)),$tmp\t!get Repl4S($src) from table\n\t"
8360 "LDDF [$tmp+lo(&Repl4($src))],$dst" %}
8361 ins_encode( LdReplImmI(src, dst, tmp, (4), (2)) );
8362 ins_pipe(loadConFD);
8363 %}
8364
8365 // Replicate scalar to packed int values in Double register
8366 instruct Repl2I_reg_helper(iRegL dst, iRegI src) %{
8367 effect(DEF dst, USE src);
8368 format %{ "SLLX $src,32,$dst\n\t"
8369 "SRLX $dst,32,O7\n\t"
8370 "OR $dst,O7,$dst\t! replicate2I" %}
8371 ins_encode( enc_repl2i(src, dst));
8372 ins_pipe(ialu_reg);
8373 %}
8374
8375 // Replicate scalar to packed int values in Double register
8376 instruct Repl2I_reg(stackSlotD dst, iRegI src) %{
8377 match(Set dst (Replicate2I src));
8378 expand %{
8379 iRegL tmp;
8380 Repl2I_reg_helper(tmp, src);
8381 regL_to_stkD(dst, tmp);
8382 %}
8383 %}
8384
8385 // Replicate scalar zero constant to packed int values in Double register
8386 instruct Repl2I_immI(regD dst, immI src, o7RegP tmp) %{
8387 match(Set dst (Replicate2I src));
8388 #ifdef _LP64
8389 size(36);
8390 #else
8391 size(8);
8392 #endif
8393 format %{ "SETHI hi(&Repl2($src)),$tmp\t!get Repl2I($src) from table\n\t"
8394 "LDDF [$tmp+lo(&Repl2($src))],$dst" %}
8395 ins_encode( LdReplImmI(src, dst, tmp, (2), (4)) );
8396 ins_pipe(loadConFD);
8397 %}
8398
8399 //----------Control Flow Instructions------------------------------------------
8400 // Compare Instructions
8401 // Compare Integers
8402 instruct compI_iReg(flagsReg icc, iRegI op1, iRegI op2) %{
8403 match(Set icc (CmpI op1 op2));
8404 effect( DEF icc, USE op1, USE op2 );
8405
8406 size(4);
8407 format %{ "CMP $op1,$op2" %}
8408 opcode(Assembler::subcc_op3, Assembler::arith_op);
8409 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8410 ins_pipe(ialu_cconly_reg_reg);
8411 %}
8412
8413 instruct compU_iReg(flagsRegU icc, iRegI op1, iRegI op2) %{
8414 match(Set icc (CmpU op1 op2));
8415
8416 size(4);
8417 format %{ "CMP $op1,$op2\t! unsigned" %}
8418 opcode(Assembler::subcc_op3, Assembler::arith_op);
8419 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8420 ins_pipe(ialu_cconly_reg_reg);
8421 %}
8422
8423 instruct compI_iReg_imm13(flagsReg icc, iRegI op1, immI13 op2) %{
8424 match(Set icc (CmpI op1 op2));
8425 effect( DEF icc, USE op1 );
8426
8427 size(4);
8428 format %{ "CMP $op1,$op2" %}
8429 opcode(Assembler::subcc_op3, Assembler::arith_op);
8430 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8431 ins_pipe(ialu_cconly_reg_imm);
8432 %}
8433
8434 instruct testI_reg_reg( flagsReg icc, iRegI op1, iRegI op2, immI0 zero ) %{
8435 match(Set icc (CmpI (AndI op1 op2) zero));
8436
8437 size(4);
8438 format %{ "BTST $op2,$op1" %}
8439 opcode(Assembler::andcc_op3, Assembler::arith_op);
8440 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8441 ins_pipe(ialu_cconly_reg_reg_zero);
8442 %}
8443
8444 instruct testI_reg_imm( flagsReg icc, iRegI op1, immI13 op2, immI0 zero ) %{
8445 match(Set icc (CmpI (AndI op1 op2) zero));
8446
8447 size(4);
8448 format %{ "BTST $op2,$op1" %}
8449 opcode(Assembler::andcc_op3, Assembler::arith_op);
8450 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8451 ins_pipe(ialu_cconly_reg_imm_zero);
8452 %}
8453
8454 instruct compL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2 ) %{
8455 match(Set xcc (CmpL op1 op2));
8456 effect( DEF xcc, USE op1, USE op2 );
8457
8458 size(4);
8459 format %{ "CMP $op1,$op2\t\t! long" %}
8460 opcode(Assembler::subcc_op3, Assembler::arith_op);
8461 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8462 ins_pipe(ialu_cconly_reg_reg);
8463 %}
8464
8465 instruct compL_reg_con(flagsRegL xcc, iRegL op1, immL13 con) %{
8466 match(Set xcc (CmpL op1 con));
8467 effect( DEF xcc, USE op1, USE con );
8468
8469 size(4);
8470 format %{ "CMP $op1,$con\t\t! long" %}
8471 opcode(Assembler::subcc_op3, Assembler::arith_op);
8472 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) );
8473 ins_pipe(ialu_cconly_reg_reg);
8474 %}
8475
8476 instruct testL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2, immL0 zero) %{
8477 match(Set xcc (CmpL (AndL op1 op2) zero));
8478 effect( DEF xcc, USE op1, USE op2 );
8479
8480 size(4);
8481 format %{ "BTST $op1,$op2\t\t! long" %}
8482 opcode(Assembler::andcc_op3, Assembler::arith_op);
8483 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8484 ins_pipe(ialu_cconly_reg_reg);
8485 %}
8486
8487 // useful for checking the alignment of a pointer:
8488 instruct testL_reg_con(flagsRegL xcc, iRegL op1, immL13 con, immL0 zero) %{
8489 match(Set xcc (CmpL (AndL op1 con) zero));
8490 effect( DEF xcc, USE op1, USE con );
8491
8492 size(4);
8493 format %{ "BTST $op1,$con\t\t! long" %}
8494 opcode(Assembler::andcc_op3, Assembler::arith_op);
8495 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) );
8496 ins_pipe(ialu_cconly_reg_reg);
8497 %}
8498
8499 instruct compU_iReg_imm13(flagsRegU icc, iRegI op1, immU13 op2 ) %{
8500 match(Set icc (CmpU op1 op2));
8501
8502 size(4);
8503 format %{ "CMP $op1,$op2\t! unsigned" %}
8504 opcode(Assembler::subcc_op3, Assembler::arith_op);
8505 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8506 ins_pipe(ialu_cconly_reg_imm);
8507 %}
8508
8509 // Compare Pointers
8510 instruct compP_iRegP(flagsRegP pcc, iRegP op1, iRegP op2 ) %{
8511 match(Set pcc (CmpP op1 op2));
8512
8513 size(4);
8514 format %{ "CMP $op1,$op2\t! ptr" %}
8515 opcode(Assembler::subcc_op3, Assembler::arith_op);
8516 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8517 ins_pipe(ialu_cconly_reg_reg);
8518 %}
8519
8520 instruct compP_iRegP_imm13(flagsRegP pcc, iRegP op1, immP13 op2 ) %{
8521 match(Set pcc (CmpP op1 op2));
8522
8523 size(4);
8524 format %{ "CMP $op1,$op2\t! ptr" %}
8525 opcode(Assembler::subcc_op3, Assembler::arith_op);
8526 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8527 ins_pipe(ialu_cconly_reg_imm);
8528 %}
8529
8530 // Compare Narrow oops
8531 instruct compN_iRegN(flagsReg icc, iRegN op1, iRegN op2 ) %{
8532 match(Set icc (CmpN op1 op2));
8533
8534 size(4);
8535 format %{ "CMP $op1,$op2\t! compressed ptr" %}
8536 opcode(Assembler::subcc_op3, Assembler::arith_op);
8537 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8538 ins_pipe(ialu_cconly_reg_reg);
8539 %}
8540
8541 instruct compN_iRegN_immN0(flagsReg icc, iRegN op1, immN0 op2 ) %{
8542 match(Set icc (CmpN op1 op2));
8543
8544 size(4);
8545 format %{ "CMP $op1,$op2\t! compressed ptr" %}
8546 opcode(Assembler::subcc_op3, Assembler::arith_op);
8547 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8548 ins_pipe(ialu_cconly_reg_imm);
8549 %}
8550
8551 //----------Max and Min--------------------------------------------------------
8552 // Min Instructions
8553 // Conditional move for min
8554 instruct cmovI_reg_lt( iRegI op2, iRegI op1, flagsReg icc ) %{
8555 effect( USE_DEF op2, USE op1, USE icc );
8556
8557 size(4);
8558 format %{ "MOVlt icc,$op1,$op2\t! min" %}
8559 opcode(Assembler::less);
8560 ins_encode( enc_cmov_reg_minmax(op2,op1) );
8561 ins_pipe(ialu_reg_flags);
8562 %}
8563
8564 // Min Register with Register.
8565 instruct minI_eReg(iRegI op1, iRegI op2) %{
8566 match(Set op2 (MinI op1 op2));
8567 ins_cost(DEFAULT_COST*2);
8568 expand %{
8569 flagsReg icc;
8570 compI_iReg(icc,op1,op2);
8571 cmovI_reg_lt(op2,op1,icc);
8572 %}
8573 %}
8574
8575 // Max Instructions
8576 // Conditional move for max
8577 instruct cmovI_reg_gt( iRegI op2, iRegI op1, flagsReg icc ) %{
8578 effect( USE_DEF op2, USE op1, USE icc );
8579 format %{ "MOVgt icc,$op1,$op2\t! max" %}
8580 opcode(Assembler::greater);
8581 ins_encode( enc_cmov_reg_minmax(op2,op1) );
8582 ins_pipe(ialu_reg_flags);
8583 %}
8584
8585 // Max Register with Register
8586 instruct maxI_eReg(iRegI op1, iRegI op2) %{
8587 match(Set op2 (MaxI op1 op2));
8588 ins_cost(DEFAULT_COST*2);
8589 expand %{
8590 flagsReg icc;
8591 compI_iReg(icc,op1,op2);
8592 cmovI_reg_gt(op2,op1,icc);
8593 %}
8594 %}
8595
8596
8597 //----------Float Compares----------------------------------------------------
8598 // Compare floating, generate condition code
8599 instruct cmpF_cc(flagsRegF fcc, regF src1, regF src2) %{
8600 match(Set fcc (CmpF src1 src2));
8601
8602 size(4);
8603 format %{ "FCMPs $fcc,$src1,$src2" %}
8604 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmps_opf);
8605 ins_encode( form3_opf_rs1F_rs2F_fcc( src1, src2, fcc ) );
8606 ins_pipe(faddF_fcc_reg_reg_zero);
8607 %}
8608
8609 instruct cmpD_cc(flagsRegF fcc, regD src1, regD src2) %{
8610 match(Set fcc (CmpD src1 src2));
8611
8612 size(4);
8613 format %{ "FCMPd $fcc,$src1,$src2" %}
8614 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmpd_opf);
8615 ins_encode( form3_opf_rs1D_rs2D_fcc( src1, src2, fcc ) );
8616 ins_pipe(faddD_fcc_reg_reg_zero);
8617 %}
8618
8619
8620 // Compare floating, generate -1,0,1
8621 instruct cmpF_reg(iRegI dst, regF src1, regF src2, flagsRegF0 fcc0) %{
8622 match(Set dst (CmpF3 src1 src2));
8623 effect(KILL fcc0);
8624 ins_cost(DEFAULT_COST*3+BRANCH_COST*3);
8625 format %{ "fcmpl $dst,$src1,$src2" %}
8626 // Primary = float
8627 opcode( true );
8628 ins_encode( floating_cmp( dst, src1, src2 ) );
8629 ins_pipe( floating_cmp );
8630 %}
8631
8632 instruct cmpD_reg(iRegI dst, regD src1, regD src2, flagsRegF0 fcc0) %{
8633 match(Set dst (CmpD3 src1 src2));
8634 effect(KILL fcc0);
8635 ins_cost(DEFAULT_COST*3+BRANCH_COST*3);
8636 format %{ "dcmpl $dst,$src1,$src2" %}
8637 // Primary = double (not float)
8638 opcode( false );
8639 ins_encode( floating_cmp( dst, src1, src2 ) );
8640 ins_pipe( floating_cmp );
8641 %}
8642
8643 //----------Branches---------------------------------------------------------
8644 // Jump
8645 // (compare 'operand indIndex' and 'instruct addP_reg_reg' above)
8646 instruct jumpXtnd(iRegX switch_val, o7RegI table) %{
8647 match(Jump switch_val);
8648
8649 ins_cost(350);
8650
8651 format %{ "SETHI [hi(table_base)],O7\n\t"
8652 "ADD O7, lo(table_base), O7\n\t"
8653 "LD [O7+$switch_val], O7\n\t"
8654 "JUMP O7"
8655 %}
8656 ins_encode( jump_enc( switch_val, table) );
8657 ins_pc_relative(1);
8658 ins_pipe(ialu_reg_reg);
8659 %}
8660
8661 // Direct Branch. Use V8 version with longer range.
8662 instruct branch(label labl) %{
8663 match(Goto);
8664 effect(USE labl);
8665
8666 size(8);
8667 ins_cost(BRANCH_COST);
8668 format %{ "BA $labl" %}
8669 // Prim = bits 24-22, Secnd = bits 31-30, Tert = cond
8670 opcode(Assembler::br_op2, Assembler::branch_op, Assembler::always);
8671 ins_encode( enc_ba( labl ) );
8672 ins_pc_relative(1);
8673 ins_pipe(br);
8674 %}
8675
8676 // Conditional Direct Branch
8677 instruct branchCon(cmpOp cmp, flagsReg icc, label labl) %{
8678 match(If cmp icc);
8679 effect(USE labl);
8680
8681 size(8);
8682 ins_cost(BRANCH_COST);
8683 format %{ "BP$cmp $icc,$labl" %}
8684 // Prim = bits 24-22, Secnd = bits 31-30
8685 ins_encode( enc_bp( labl, cmp, icc ) );
8686 ins_pc_relative(1);
8687 ins_pipe(br_cc);
8688 %}
8689
8690 // Branch-on-register tests all 64 bits. We assume that values
8691 // in 64-bit registers always remains zero or sign extended
8692 // unless our code munges the high bits. Interrupts can chop
8693 // the high order bits to zero or sign at any time.
8694 instruct branchCon_regI(cmpOp_reg cmp, iRegI op1, immI0 zero, label labl) %{
8695 match(If cmp (CmpI op1 zero));
8696 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
8697 effect(USE labl);
8698
8699 size(8);
8700 ins_cost(BRANCH_COST);
8701 format %{ "BR$cmp $op1,$labl" %}
8702 ins_encode( enc_bpr( labl, cmp, op1 ) );
8703 ins_pc_relative(1);
8704 ins_pipe(br_reg);
8705 %}
8706
8707 instruct branchCon_regP(cmpOp_reg cmp, iRegP op1, immP0 null, label labl) %{
8708 match(If cmp (CmpP op1 null));
8709 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
8710 effect(USE labl);
8711
8712 size(8);
8713 ins_cost(BRANCH_COST);
8714 format %{ "BR$cmp $op1,$labl" %}
8715 ins_encode( enc_bpr( labl, cmp, op1 ) );
8716 ins_pc_relative(1);
8717 ins_pipe(br_reg);
8718 %}
8719
8720 instruct branchCon_regL(cmpOp_reg cmp, iRegL op1, immL0 zero, label labl) %{
8721 match(If cmp (CmpL op1 zero));
8722 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
8723 effect(USE labl);
8724
8725 size(8);
8726 ins_cost(BRANCH_COST);
8727 format %{ "BR$cmp $op1,$labl" %}
8728 ins_encode( enc_bpr( labl, cmp, op1 ) );
8729 ins_pc_relative(1);
8730 ins_pipe(br_reg);
8731 %}
8732
8733 instruct branchConU(cmpOpU cmp, flagsRegU icc, label labl) %{
8734 match(If cmp icc);
8735 effect(USE labl);
8736
8737 format %{ "BP$cmp $icc,$labl" %}
8738 // Prim = bits 24-22, Secnd = bits 31-30
8739 ins_encode( enc_bp( labl, cmp, icc ) );
8740 ins_pc_relative(1);
8741 ins_pipe(br_cc);
8742 %}
8743
8744 instruct branchConP(cmpOpP cmp, flagsRegP pcc, label labl) %{
8745 match(If cmp pcc);
8746 effect(USE labl);
8747
8748 size(8);
8749 ins_cost(BRANCH_COST);
8750 format %{ "BP$cmp $pcc,$labl" %}
8751 // Prim = bits 24-22, Secnd = bits 31-30
8752 ins_encode( enc_bpx( labl, cmp, pcc ) );
8753 ins_pc_relative(1);
8754 ins_pipe(br_cc);
8755 %}
8756
8757 instruct branchConF(cmpOpF cmp, flagsRegF fcc, label labl) %{
8758 match(If cmp fcc);
8759 effect(USE labl);
8760
8761 size(8);
8762 ins_cost(BRANCH_COST);
8763 format %{ "FBP$cmp $fcc,$labl" %}
8764 // Prim = bits 24-22, Secnd = bits 31-30
8765 ins_encode( enc_fbp( labl, cmp, fcc ) );
8766 ins_pc_relative(1);
8767 ins_pipe(br_fcc);
8768 %}
8769
8770 instruct branchLoopEnd(cmpOp cmp, flagsReg icc, label labl) %{
8771 match(CountedLoopEnd cmp icc);
8772 effect(USE labl);
8773
8774 size(8);
8775 ins_cost(BRANCH_COST);
8776 format %{ "BP$cmp $icc,$labl\t! Loop end" %}
8777 // Prim = bits 24-22, Secnd = bits 31-30
8778 ins_encode( enc_bp( labl, cmp, icc ) );
8779 ins_pc_relative(1);
8780 ins_pipe(br_cc);
8781 %}
8782
8783 instruct branchLoopEndU(cmpOpU cmp, flagsRegU icc, label labl) %{
8784 match(CountedLoopEnd cmp icc);
8785 effect(USE labl);
8786
8787 size(8);
8788 ins_cost(BRANCH_COST);
8789 format %{ "BP$cmp $icc,$labl\t! Loop end" %}
8790 // Prim = bits 24-22, Secnd = bits 31-30
8791 ins_encode( enc_bp( labl, cmp, icc ) );
8792 ins_pc_relative(1);
8793 ins_pipe(br_cc);
8794 %}
8795
8796 // ============================================================================
8797 // Long Compare
8798 //
8799 // Currently we hold longs in 2 registers. Comparing such values efficiently
8800 // is tricky. The flavor of compare used depends on whether we are testing
8801 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit.
8802 // The GE test is the negated LT test. The LE test can be had by commuting
8803 // the operands (yielding a GE test) and then negating; negate again for the
8804 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the
8805 // NE test is negated from that.
8806
8807 // Due to a shortcoming in the ADLC, it mixes up expressions like:
8808 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the
8809 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections
8810 // are collapsed internally in the ADLC's dfa-gen code. The match for
8811 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the
8812 // foo match ends up with the wrong leaf. One fix is to not match both
8813 // reg-reg and reg-zero forms of long-compare. This is unfortunate because
8814 // both forms beat the trinary form of long-compare and both are very useful
8815 // on Intel which has so few registers.
8816
8817 instruct branchCon_long(cmpOp cmp, flagsRegL xcc, label labl) %{
8818 match(If cmp xcc);
8819 effect(USE labl);
8820
8821 size(8);
8822 ins_cost(BRANCH_COST);
8823 format %{ "BP$cmp $xcc,$labl" %}
8824 // Prim = bits 24-22, Secnd = bits 31-30
8825 ins_encode( enc_bpl( labl, cmp, xcc ) );
8826 ins_pc_relative(1);
8827 ins_pipe(br_cc);
8828 %}
8829
8830 // Manifest a CmpL3 result in an integer register. Very painful.
8831 // This is the test to avoid.
8832 instruct cmpL3_reg_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg ccr ) %{
8833 match(Set dst (CmpL3 src1 src2) );
8834 effect( KILL ccr );
8835 ins_cost(6*DEFAULT_COST);
8836 size(24);
8837 format %{ "CMP $src1,$src2\t\t! long\n"
8838 "\tBLT,a,pn done\n"
8839 "\tMOV -1,$dst\t! delay slot\n"
8840 "\tBGT,a,pn done\n"
8841 "\tMOV 1,$dst\t! delay slot\n"
8842 "\tCLR $dst\n"
8843 "done:" %}
8844 ins_encode( cmpl_flag(src1,src2,dst) );
8845 ins_pipe(cmpL_reg);
8846 %}
8847
8848 // Conditional move
8849 instruct cmovLL_reg(cmpOp cmp, flagsRegL xcc, iRegL dst, iRegL src) %{
8850 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src)));
8851 ins_cost(150);
8852 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %}
8853 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
8854 ins_pipe(ialu_reg);
8855 %}
8856
8857 instruct cmovLL_imm(cmpOp cmp, flagsRegL xcc, iRegL dst, immL0 src) %{
8858 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src)));
8859 ins_cost(140);
8860 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %}
8861 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
8862 ins_pipe(ialu_imm);
8863 %}
8864
8865 instruct cmovIL_reg(cmpOp cmp, flagsRegL xcc, iRegI dst, iRegI src) %{
8866 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src)));
8867 ins_cost(150);
8868 format %{ "MOV$cmp $xcc,$src,$dst" %}
8869 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
8870 ins_pipe(ialu_reg);
8871 %}
8872
8873 instruct cmovIL_imm(cmpOp cmp, flagsRegL xcc, iRegI dst, immI11 src) %{
8874 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src)));
8875 ins_cost(140);
8876 format %{ "MOV$cmp $xcc,$src,$dst" %}
8877 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
8878 ins_pipe(ialu_imm);
8879 %}
8880
8881 instruct cmovNL_reg(cmpOp cmp, flagsRegL xcc, iRegN dst, iRegN src) %{
8882 match(Set dst (CMoveN (Binary cmp xcc) (Binary dst src)));
8883 ins_cost(150);
8884 format %{ "MOV$cmp $xcc,$src,$dst" %}
8885 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
8886 ins_pipe(ialu_reg);
8887 %}
8888
8889 instruct cmovPL_reg(cmpOp cmp, flagsRegL xcc, iRegP dst, iRegP src) %{
8890 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src)));
8891 ins_cost(150);
8892 format %{ "MOV$cmp $xcc,$src,$dst" %}
8893 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
8894 ins_pipe(ialu_reg);
8895 %}
8896
8897 instruct cmovPL_imm(cmpOp cmp, flagsRegL xcc, iRegP dst, immP0 src) %{
8898 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src)));
8899 ins_cost(140);
8900 format %{ "MOV$cmp $xcc,$src,$dst" %}
8901 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
8902 ins_pipe(ialu_imm);
8903 %}
8904
8905 instruct cmovFL_reg(cmpOp cmp, flagsRegL xcc, regF dst, regF src) %{
8906 match(Set dst (CMoveF (Binary cmp xcc) (Binary dst src)));
8907 ins_cost(150);
8908 opcode(0x101);
8909 format %{ "FMOVS$cmp $xcc,$src,$dst" %}
8910 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) );
8911 ins_pipe(int_conditional_float_move);
8912 %}
8913
8914 instruct cmovDL_reg(cmpOp cmp, flagsRegL xcc, regD dst, regD src) %{
8915 match(Set dst (CMoveD (Binary cmp xcc) (Binary dst src)));
8916 ins_cost(150);
8917 opcode(0x102);
8918 format %{ "FMOVD$cmp $xcc,$src,$dst" %}
8919 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) );
8920 ins_pipe(int_conditional_float_move);
8921 %}
8922
8923 // ============================================================================
8924 // Safepoint Instruction
8925 instruct safePoint_poll(iRegP poll) %{
8926 match(SafePoint poll);
8927 effect(USE poll);
8928
8929 size(4);
8930 #ifdef _LP64
8931 format %{ "LDX [$poll],R_G0\t! Safepoint: poll for GC" %}
8932 #else
8933 format %{ "LDUW [$poll],R_G0\t! Safepoint: poll for GC" %}
8934 #endif
8935 ins_encode %{
8936 __ relocate(relocInfo::poll_type);
8937 __ ld_ptr($poll$$Register, 0, G0);
8938 %}
8939 ins_pipe(loadPollP);
8940 %}
8941
8942 // ============================================================================
8943 // Call Instructions
8944 // Call Java Static Instruction
8945 instruct CallStaticJavaDirect( method meth ) %{
8946 match(CallStaticJava);
8947 effect(USE meth);
8948
8949 size(8);
8950 ins_cost(CALL_COST);
8951 format %{ "CALL,static ; NOP ==> " %}
8952 ins_encode( Java_Static_Call( meth ), call_epilog );
8953 ins_pc_relative(1);
8954 ins_pipe(simple_call);
8955 %}
8956
8957 // Call Java Dynamic Instruction
8958 instruct CallDynamicJavaDirect( method meth ) %{
8959 match(CallDynamicJava);
8960 effect(USE meth);
8961
8962 ins_cost(CALL_COST);
8963 format %{ "SET (empty),R_G5\n\t"
8964 "CALL,dynamic ; NOP ==> " %}
8965 ins_encode( Java_Dynamic_Call( meth ), call_epilog );
8966 ins_pc_relative(1);
8967 ins_pipe(call);
8968 %}
8969
8970 // Call Runtime Instruction
8971 instruct CallRuntimeDirect(method meth, l7RegP l7) %{
8972 match(CallRuntime);
8973 effect(USE meth, KILL l7);
8974 ins_cost(CALL_COST);
8975 format %{ "CALL,runtime" %}
8976 ins_encode( Java_To_Runtime( meth ),
8977 call_epilog, adjust_long_from_native_call );
8978 ins_pc_relative(1);
8979 ins_pipe(simple_call);
8980 %}
8981
8982 // Call runtime without safepoint - same as CallRuntime
8983 instruct CallLeafDirect(method meth, l7RegP l7) %{
8984 match(CallLeaf);
8985 effect(USE meth, KILL l7);
8986 ins_cost(CALL_COST);
8987 format %{ "CALL,runtime leaf" %}
8988 ins_encode( Java_To_Runtime( meth ),
8989 call_epilog,
8990 adjust_long_from_native_call );
8991 ins_pc_relative(1);
8992 ins_pipe(simple_call);
8993 %}
8994
8995 // Call runtime without safepoint - same as CallLeaf
8996 instruct CallLeafNoFPDirect(method meth, l7RegP l7) %{
8997 match(CallLeafNoFP);
8998 effect(USE meth, KILL l7);
8999 ins_cost(CALL_COST);
9000 format %{ "CALL,runtime leaf nofp" %}
9001 ins_encode( Java_To_Runtime( meth ),
9002 call_epilog,
9003 adjust_long_from_native_call );
9004 ins_pc_relative(1);
9005 ins_pipe(simple_call);
9006 %}
9007
9008 // Tail Call; Jump from runtime stub to Java code.
9009 // Also known as an 'interprocedural jump'.
9010 // Target of jump will eventually return to caller.
9011 // TailJump below removes the return address.
9012 instruct TailCalljmpInd(g3RegP jump_target, inline_cache_regP method_oop) %{
9013 match(TailCall jump_target method_oop );
9014
9015 ins_cost(CALL_COST);
9016 format %{ "Jmp $jump_target ; NOP \t! $method_oop holds method oop" %}
9017 ins_encode(form_jmpl(jump_target));
9018 ins_pipe(tail_call);
9019 %}
9020
9021
9022 // Return Instruction
9023 instruct Ret() %{
9024 match(Return);
9025
9026 // The epilogue node did the ret already.
9027 size(0);
9028 format %{ "! return" %}
9029 ins_encode();
9030 ins_pipe(empty);
9031 %}
9032
9033
9034 // Tail Jump; remove the return address; jump to target.
9035 // TailCall above leaves the return address around.
9036 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2).
9037 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a
9038 // "restore" before this instruction (in Epilogue), we need to materialize it
9039 // in %i0.
9040 instruct tailjmpInd(g1RegP jump_target, i0RegP ex_oop) %{
9041 match( TailJump jump_target ex_oop );
9042 ins_cost(CALL_COST);
9043 format %{ "! discard R_O7\n\t"
9044 "Jmp $jump_target ; ADD O7,8,O1 \t! $ex_oop holds exc. oop" %}
9045 ins_encode(form_jmpl_set_exception_pc(jump_target));
9046 // opcode(Assembler::jmpl_op3, Assembler::arith_op);
9047 // The hack duplicates the exception oop into G3, so that CreateEx can use it there.
9048 // ins_encode( form3_rs1_simm13_rd( jump_target, 0x00, R_G0 ), move_return_pc_to_o1() );
9049 ins_pipe(tail_call);
9050 %}
9051
9052 // Create exception oop: created by stack-crawling runtime code.
9053 // Created exception is now available to this handler, and is setup
9054 // just prior to jumping to this handler. No code emitted.
9055 instruct CreateException( o0RegP ex_oop )
9056 %{
9057 match(Set ex_oop (CreateEx));
9058 ins_cost(0);
9059
9060 size(0);
9061 // use the following format syntax
9062 format %{ "! exception oop is in R_O0; no code emitted" %}
9063 ins_encode();
9064 ins_pipe(empty);
9065 %}
9066
9067
9068 // Rethrow exception:
9069 // The exception oop will come in the first argument position.
9070 // Then JUMP (not call) to the rethrow stub code.
9071 instruct RethrowException()
9072 %{
9073 match(Rethrow);
9074 ins_cost(CALL_COST);
9075
9076 // use the following format syntax
9077 format %{ "Jmp rethrow_stub" %}
9078 ins_encode(enc_rethrow);
9079 ins_pipe(tail_call);
9080 %}
9081
9082
9083 // Die now
9084 instruct ShouldNotReachHere( )
9085 %{
9086 match(Halt);
9087 ins_cost(CALL_COST);
9088
9089 size(4);
9090 // Use the following format syntax
9091 format %{ "ILLTRAP ; ShouldNotReachHere" %}
9092 ins_encode( form2_illtrap() );
9093 ins_pipe(tail_call);
9094 %}
9095
9096 // ============================================================================
9097 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
9098 // array for an instance of the superklass. Set a hidden internal cache on a
9099 // hit (cache is checked with exposed code in gen_subtype_check()). Return
9100 // not zero for a miss or zero for a hit. The encoding ALSO sets flags.
9101 instruct partialSubtypeCheck( o0RegP index, o1RegP sub, o2RegP super, flagsRegP pcc, o7RegP o7 ) %{
9102 match(Set index (PartialSubtypeCheck sub super));
9103 effect( KILL pcc, KILL o7 );
9104 ins_cost(DEFAULT_COST*10);
9105 format %{ "CALL PartialSubtypeCheck\n\tNOP" %}
9106 ins_encode( enc_PartialSubtypeCheck() );
9107 ins_pipe(partial_subtype_check_pipe);
9108 %}
9109
9110 instruct partialSubtypeCheck_vs_zero( flagsRegP pcc, o1RegP sub, o2RegP super, immP0 zero, o0RegP idx, o7RegP o7 ) %{
9111 match(Set pcc (CmpP (PartialSubtypeCheck sub super) zero));
9112 effect( KILL idx, KILL o7 );
9113 ins_cost(DEFAULT_COST*10);
9114 format %{ "CALL PartialSubtypeCheck\n\tNOP\t# (sets condition codes)" %}
9115 ins_encode( enc_PartialSubtypeCheck() );
9116 ins_pipe(partial_subtype_check_pipe);
9117 %}
9118
9119
9120 // ============================================================================
9121 // inlined locking and unlocking
9122
9123 instruct cmpFastLock(flagsRegP pcc, iRegP object, iRegP box, iRegP scratch2, o7RegP scratch ) %{
9124 match(Set pcc (FastLock object box));
9125
9126 effect(KILL scratch, TEMP scratch2);
9127 ins_cost(100);
9128
9129 size(4*112); // conservative overestimation ...
9130 format %{ "FASTLOCK $object, $box; KILL $scratch, $scratch2, $box" %}
9131 ins_encode( Fast_Lock(object, box, scratch, scratch2) );
9132 ins_pipe(long_memory_op);
9133 %}
9134
9135
9136 instruct cmpFastUnlock(flagsRegP pcc, iRegP object, iRegP box, iRegP scratch2, o7RegP scratch ) %{
9137 match(Set pcc (FastUnlock object box));
9138 effect(KILL scratch, TEMP scratch2);
9139 ins_cost(100);
9140
9141 size(4*120); // conservative overestimation ...
9142 format %{ "FASTUNLOCK $object, $box; KILL $scratch, $scratch2, $box" %}
9143 ins_encode( Fast_Unlock(object, box, scratch, scratch2) );
9144 ins_pipe(long_memory_op);
9145 %}
9146
9147 // Count and Base registers are fixed because the allocator cannot
9148 // kill unknown registers. The encodings are generic.
9149 instruct clear_array(iRegX cnt, iRegP base, iRegX temp, Universe dummy, flagsReg ccr) %{
9150 match(Set dummy (ClearArray cnt base));
9151 effect(TEMP temp, KILL ccr);
9152 ins_cost(300);
9153 format %{ "MOV $cnt,$temp\n"
9154 "loop: SUBcc $temp,8,$temp\t! Count down a dword of bytes\n"
9155 " BRge loop\t\t! Clearing loop\n"
9156 " STX G0,[$base+$temp]\t! delay slot" %}
9157 ins_encode( enc_Clear_Array(cnt, base, temp) );
9158 ins_pipe(long_memory_op);
9159 %}
9160
9161 instruct string_compare(o0RegP str1, o1RegP str2, g3RegP tmp1, g4RegP tmp2, notemp_iRegI result,
9162 o7RegI tmp3, flagsReg ccr) %{
9163 match(Set result (StrComp str1 str2));
9164 effect(USE_KILL str1, USE_KILL str2, KILL tmp1, KILL tmp2, KILL ccr, KILL tmp3);
9165 ins_cost(300);
9166 format %{ "String Compare $str1,$str2 -> $result" %}
9167 ins_encode( enc_String_Compare(str1, str2, tmp1, tmp2, result) );
9168 ins_pipe(long_memory_op);
9169 %}
9170
9171 instruct string_equals(o0RegP str1, o1RegP str2, g3RegP tmp1, g4RegP tmp2, notemp_iRegI result,
9172 o7RegI tmp3, flagsReg ccr) %{
9173 match(Set result (StrEquals str1 str2));
9174 effect(USE_KILL str1, USE_KILL str2, KILL tmp1, KILL tmp2, KILL ccr, KILL tmp3);
9175 ins_cost(300);
9176 format %{ "String Equals $str1,$str2 -> $result" %}
9177 ins_encode( enc_String_Equals(str1, str2, tmp1, tmp2, result) );
9178 ins_pipe(long_memory_op);
9179 %}
9180
9181 instruct array_equals(o0RegP ary1, o1RegP ary2, g3RegP tmp1, g4RegP tmp2, notemp_iRegI result,
9182 flagsReg ccr) %{
9183 match(Set result (AryEq ary1 ary2));
9184 effect(USE_KILL ary1, USE_KILL ary2, KILL tmp1, KILL tmp2, KILL ccr);
9185 ins_cost(300);
9186 format %{ "Array Equals $ary1,$ary2 -> $result" %}
9187 ins_encode( enc_Array_Equals(ary1, ary2, tmp1, tmp2, result));
9188 ins_pipe(long_memory_op);
9189 %}
9190
9191 //---------- Population Count Instructions -------------------------------------
9192
9193 instruct popCountI(iRegI dst, iRegI src) %{
9194 predicate(UsePopCountInstruction);
9195 match(Set dst (PopCountI src));
9196
9197 format %{ "POPC $src, $dst" %}
9198 ins_encode %{
9199 __ popc($src$$Register, $dst$$Register);
9200 %}
9201 ins_pipe(ialu_reg);
9202 %}
9203
9204 // Note: Long.bitCount(long) returns an int.
9205 instruct popCountL(iRegI dst, iRegL src) %{
9206 predicate(UsePopCountInstruction);
9207 match(Set dst (PopCountL src));
9208
9209 format %{ "POPC $src, $dst" %}
9210 ins_encode %{
9211 __ popc($src$$Register, $dst$$Register);
9212 %}
9213 ins_pipe(ialu_reg);
9214 %}
9215
9216
9217 // ============================================================================
9218 //------------Bytes reverse--------------------------------------------------
9219
9220 instruct bytes_reverse_int(iRegI dst, stackSlotI src) %{
9221 match(Set dst (ReverseBytesI src));
9222 effect(DEF dst, USE src);
9223
9224 // Op cost is artificially doubled to make sure that load or store
9225 // instructions are preferred over this one which requires a spill
9226 // onto a stack slot.
9227 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
9228 size(8);
9229 format %{ "LDUWA $src, $dst\t!asi=primary_little" %}
9230 opcode(Assembler::lduwa_op3);
9231 ins_encode( form3_mem_reg_little(src, dst) );
9232 ins_pipe( iload_mem );
9233 %}
9234
9235 instruct bytes_reverse_long(iRegL dst, stackSlotL src) %{
9236 match(Set dst (ReverseBytesL src));
9237 effect(DEF dst, USE src);
9238
9239 // Op cost is artificially doubled to make sure that load or store
9240 // instructions are preferred over this one which requires a spill
9241 // onto a stack slot.
9242 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
9243 size(8);
9244 format %{ "LDXA $src, $dst\t!asi=primary_little" %}
9245
9246 opcode(Assembler::ldxa_op3);
9247 ins_encode( form3_mem_reg_little(src, dst) );
9248 ins_pipe( iload_mem );
9249 %}
9250
9251 // Load Integer reversed byte order
9252 instruct loadI_reversed(iRegI dst, memory src) %{
9253 match(Set dst (ReverseBytesI (LoadI src)));
9254
9255 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
9256 size(8);
9257 format %{ "LDUWA $src, $dst\t!asi=primary_little" %}
9258
9259 opcode(Assembler::lduwa_op3);
9260 ins_encode( form3_mem_reg_little( src, dst) );
9261 ins_pipe(iload_mem);
9262 %}
9263
9264 // Load Long - aligned and reversed
9265 instruct loadL_reversed(iRegL dst, memory src) %{
9266 match(Set dst (ReverseBytesL (LoadL src)));
9267
9268 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
9269 size(8);
9270 format %{ "LDXA $src, $dst\t!asi=primary_little" %}
9271
9272 opcode(Assembler::ldxa_op3);
9273 ins_encode( form3_mem_reg_little( src, dst ) );
9274 ins_pipe(iload_mem);
9275 %}
9276
9277 // Store Integer reversed byte order
9278 instruct storeI_reversed(memory dst, iRegI src) %{
9279 match(Set dst (StoreI dst (ReverseBytesI src)));
9280
9281 ins_cost(MEMORY_REF_COST);
9282 size(8);
9283 format %{ "STWA $src, $dst\t!asi=primary_little" %}
9284
9285 opcode(Assembler::stwa_op3);
9286 ins_encode( form3_mem_reg_little( dst, src) );
9287 ins_pipe(istore_mem_reg);
9288 %}
9289
9290 // Store Long reversed byte order
9291 instruct storeL_reversed(memory dst, iRegL src) %{
9292 match(Set dst (StoreL dst (ReverseBytesL src)));
9293
9294 ins_cost(MEMORY_REF_COST);
9295 size(8);
9296 format %{ "STXA $src, $dst\t!asi=primary_little" %}
9297
9298 opcode(Assembler::stxa_op3);
9299 ins_encode( form3_mem_reg_little( dst, src) );
9300 ins_pipe(istore_mem_reg);
9301 %}
9302
9303 //----------PEEPHOLE RULES-----------------------------------------------------
9304 // These must follow all instruction definitions as they use the names
9305 // defined in the instructions definitions.
9306 //
9307 // peepmatch ( root_instr_name [preceding_instruction]* );
9308 //
9309 // peepconstraint %{
9310 // (instruction_number.operand_name relational_op instruction_number.operand_name
9311 // [, ...] );
9312 // // instruction numbers are zero-based using left to right order in peepmatch
9313 //
9314 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
9315 // // provide an instruction_number.operand_name for each operand that appears
9316 // // in the replacement instruction's match rule
9317 //
9318 // ---------VM FLAGS---------------------------------------------------------
9319 //
9320 // All peephole optimizations can be turned off using -XX:-OptoPeephole
9321 //
9322 // Each peephole rule is given an identifying number starting with zero and
9323 // increasing by one in the order seen by the parser. An individual peephole
9324 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
9325 // on the command-line.
9326 //
9327 // ---------CURRENT LIMITATIONS----------------------------------------------
9328 //
9329 // Only match adjacent instructions in same basic block
9330 // Only equality constraints
9331 // Only constraints between operands, not (0.dest_reg == EAX_enc)
9332 // Only one replacement instruction
9333 //
9334 // ---------EXAMPLE----------------------------------------------------------
9335 //
9336 // // pertinent parts of existing instructions in architecture description
9337 // instruct movI(eRegI dst, eRegI src) %{
9338 // match(Set dst (CopyI src));
9339 // %}
9340 //
9341 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
9342 // match(Set dst (AddI dst src));
9343 // effect(KILL cr);
9344 // %}
9345 //
9346 // // Change (inc mov) to lea
9347 // peephole %{
9348 // // increment preceeded by register-register move
9349 // peepmatch ( incI_eReg movI );
9350 // // require that the destination register of the increment
9351 // // match the destination register of the move
9352 // peepconstraint ( 0.dst == 1.dst );
9353 // // construct a replacement instruction that sets
9354 // // the destination to ( move's source register + one )
9355 // peepreplace ( incI_eReg_immI1( 0.dst 1.src 0.src ) );
9356 // %}
9357 //
9358
9359 // // Change load of spilled value to only a spill
9360 // instruct storeI(memory mem, eRegI src) %{
9361 // match(Set mem (StoreI mem src));
9362 // %}
9363 //
9364 // instruct loadI(eRegI dst, memory mem) %{
9365 // match(Set dst (LoadI mem));
9366 // %}
9367 //
9368 // peephole %{
9369 // peepmatch ( loadI storeI );
9370 // peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
9371 // peepreplace ( storeI( 1.mem 1.mem 1.src ) );
9372 // %}
9373
9374 //----------SMARTSPILL RULES---------------------------------------------------
9375 // These must follow all instruction definitions as they use the names
9376 // defined in the instructions definitions.
9377 //
9378 // SPARC will probably not have any of these rules due to RISC instruction set.
9379
9380 //----------PIPELINE-----------------------------------------------------------
9381 // Rules which define the behavior of the target architectures pipeline.