1 //
2 // Copyright 1998-2009 Sun Microsystems, Inc. All Rights Reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
9 // This code is distributed in the hope that it will be useful, but WITHOUT
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
15 // You should have received a copy of the GNU General Public License version
16 // 2 along with this work; if not, write to the Free Software Foundation,
17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 //
19 // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
20 // CA 95054 USA or visit www.sun.com if you need additional information or
21 // have any questions.
22 //
23 //
24
25 // SPARC Architecture Description File
26
27 //----------REGISTER DEFINITION BLOCK------------------------------------------
28 // This information is used by the matcher and the register allocator to
29 // describe individual registers and classes of registers within the target
30 // archtecture.
31 register %{
32 //----------Architecture Description Register Definitions----------------------
33 // General Registers
34 // "reg_def" name ( register save type, C convention save type,
35 // ideal register type, encoding, vm name );
36 // Register Save Types:
37 //
38 // NS = No-Save: The register allocator assumes that these registers
39 // can be used without saving upon entry to the method, &
40 // that they do not need to be saved at call sites.
41 //
42 // SOC = Save-On-Call: The register allocator assumes that these registers
43 // can be used without saving upon entry to the method,
44 // but that they must be saved at call sites.
45 //
46 // SOE = Save-On-Entry: The register allocator assumes that these registers
47 // must be saved before using them upon entry to the
48 // method, but they do not need to be saved at call
49 // sites.
50 //
51 // AS = Always-Save: The register allocator assumes that these registers
52 // must be saved before using them upon entry to the
53 // method, & that they must be saved at call sites.
54 //
55 // Ideal Register Type is used to determine how to save & restore a
56 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
57 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
58 //
59 // The encoding number is the actual bit-pattern placed into the opcodes.
60
61
62 // ----------------------------
63 // Integer/Long Registers
64 // ----------------------------
65
66 // Need to expose the hi/lo aspect of 64-bit registers
67 // This register set is used for both the 64-bit build and
68 // the 32-bit build with 1-register longs.
69
70 // Global Registers 0-7
71 reg_def R_G0H( NS, NS, Op_RegI,128, G0->as_VMReg()->next());
72 reg_def R_G0 ( NS, NS, Op_RegI, 0, G0->as_VMReg());
73 reg_def R_G1H(SOC, SOC, Op_RegI,129, G1->as_VMReg()->next());
74 reg_def R_G1 (SOC, SOC, Op_RegI, 1, G1->as_VMReg());
75 reg_def R_G2H( NS, NS, Op_RegI,130, G2->as_VMReg()->next());
76 reg_def R_G2 ( NS, NS, Op_RegI, 2, G2->as_VMReg());
77 reg_def R_G3H(SOC, SOC, Op_RegI,131, G3->as_VMReg()->next());
78 reg_def R_G3 (SOC, SOC, Op_RegI, 3, G3->as_VMReg());
79 reg_def R_G4H(SOC, SOC, Op_RegI,132, G4->as_VMReg()->next());
80 reg_def R_G4 (SOC, SOC, Op_RegI, 4, G4->as_VMReg());
81 reg_def R_G5H(SOC, SOC, Op_RegI,133, G5->as_VMReg()->next());
82 reg_def R_G5 (SOC, SOC, Op_RegI, 5, G5->as_VMReg());
83 reg_def R_G6H( NS, NS, Op_RegI,134, G6->as_VMReg()->next());
84 reg_def R_G6 ( NS, NS, Op_RegI, 6, G6->as_VMReg());
85 reg_def R_G7H( NS, NS, Op_RegI,135, G7->as_VMReg()->next());
86 reg_def R_G7 ( NS, NS, Op_RegI, 7, G7->as_VMReg());
87
88 // Output Registers 0-7
89 reg_def R_O0H(SOC, SOC, Op_RegI,136, O0->as_VMReg()->next());
90 reg_def R_O0 (SOC, SOC, Op_RegI, 8, O0->as_VMReg());
91 reg_def R_O1H(SOC, SOC, Op_RegI,137, O1->as_VMReg()->next());
92 reg_def R_O1 (SOC, SOC, Op_RegI, 9, O1->as_VMReg());
93 reg_def R_O2H(SOC, SOC, Op_RegI,138, O2->as_VMReg()->next());
94 reg_def R_O2 (SOC, SOC, Op_RegI, 10, O2->as_VMReg());
95 reg_def R_O3H(SOC, SOC, Op_RegI,139, O3->as_VMReg()->next());
96 reg_def R_O3 (SOC, SOC, Op_RegI, 11, O3->as_VMReg());
97 reg_def R_O4H(SOC, SOC, Op_RegI,140, O4->as_VMReg()->next());
98 reg_def R_O4 (SOC, SOC, Op_RegI, 12, O4->as_VMReg());
99 reg_def R_O5H(SOC, SOC, Op_RegI,141, O5->as_VMReg()->next());
100 reg_def R_O5 (SOC, SOC, Op_RegI, 13, O5->as_VMReg());
101 reg_def R_SPH( NS, NS, Op_RegI,142, SP->as_VMReg()->next());
102 reg_def R_SP ( NS, NS, Op_RegI, 14, SP->as_VMReg());
103 reg_def R_O7H(SOC, SOC, Op_RegI,143, O7->as_VMReg()->next());
104 reg_def R_O7 (SOC, SOC, Op_RegI, 15, O7->as_VMReg());
105
106 // Local Registers 0-7
107 reg_def R_L0H( NS, NS, Op_RegI,144, L0->as_VMReg()->next());
108 reg_def R_L0 ( NS, NS, Op_RegI, 16, L0->as_VMReg());
109 reg_def R_L1H( NS, NS, Op_RegI,145, L1->as_VMReg()->next());
110 reg_def R_L1 ( NS, NS, Op_RegI, 17, L1->as_VMReg());
111 reg_def R_L2H( NS, NS, Op_RegI,146, L2->as_VMReg()->next());
112 reg_def R_L2 ( NS, NS, Op_RegI, 18, L2->as_VMReg());
113 reg_def R_L3H( NS, NS, Op_RegI,147, L3->as_VMReg()->next());
114 reg_def R_L3 ( NS, NS, Op_RegI, 19, L3->as_VMReg());
115 reg_def R_L4H( NS, NS, Op_RegI,148, L4->as_VMReg()->next());
116 reg_def R_L4 ( NS, NS, Op_RegI, 20, L4->as_VMReg());
117 reg_def R_L5H( NS, NS, Op_RegI,149, L5->as_VMReg()->next());
118 reg_def R_L5 ( NS, NS, Op_RegI, 21, L5->as_VMReg());
119 reg_def R_L6H( NS, NS, Op_RegI,150, L6->as_VMReg()->next());
120 reg_def R_L6 ( NS, NS, Op_RegI, 22, L6->as_VMReg());
121 reg_def R_L7H( NS, NS, Op_RegI,151, L7->as_VMReg()->next());
122 reg_def R_L7 ( NS, NS, Op_RegI, 23, L7->as_VMReg());
123
124 // Input Registers 0-7
125 reg_def R_I0H( NS, NS, Op_RegI,152, I0->as_VMReg()->next());
126 reg_def R_I0 ( NS, NS, Op_RegI, 24, I0->as_VMReg());
127 reg_def R_I1H( NS, NS, Op_RegI,153, I1->as_VMReg()->next());
128 reg_def R_I1 ( NS, NS, Op_RegI, 25, I1->as_VMReg());
129 reg_def R_I2H( NS, NS, Op_RegI,154, I2->as_VMReg()->next());
130 reg_def R_I2 ( NS, NS, Op_RegI, 26, I2->as_VMReg());
131 reg_def R_I3H( NS, NS, Op_RegI,155, I3->as_VMReg()->next());
132 reg_def R_I3 ( NS, NS, Op_RegI, 27, I3->as_VMReg());
133 reg_def R_I4H( NS, NS, Op_RegI,156, I4->as_VMReg()->next());
134 reg_def R_I4 ( NS, NS, Op_RegI, 28, I4->as_VMReg());
135 reg_def R_I5H( NS, NS, Op_RegI,157, I5->as_VMReg()->next());
136 reg_def R_I5 ( NS, NS, Op_RegI, 29, I5->as_VMReg());
137 reg_def R_FPH( NS, NS, Op_RegI,158, FP->as_VMReg()->next());
138 reg_def R_FP ( NS, NS, Op_RegI, 30, FP->as_VMReg());
139 reg_def R_I7H( NS, NS, Op_RegI,159, I7->as_VMReg()->next());
140 reg_def R_I7 ( NS, NS, Op_RegI, 31, I7->as_VMReg());
141
142 // ----------------------------
143 // Float/Double Registers
144 // ----------------------------
145
146 // Float Registers
147 reg_def R_F0 ( SOC, SOC, Op_RegF, 0, F0->as_VMReg());
148 reg_def R_F1 ( SOC, SOC, Op_RegF, 1, F1->as_VMReg());
149 reg_def R_F2 ( SOC, SOC, Op_RegF, 2, F2->as_VMReg());
150 reg_def R_F3 ( SOC, SOC, Op_RegF, 3, F3->as_VMReg());
151 reg_def R_F4 ( SOC, SOC, Op_RegF, 4, F4->as_VMReg());
152 reg_def R_F5 ( SOC, SOC, Op_RegF, 5, F5->as_VMReg());
153 reg_def R_F6 ( SOC, SOC, Op_RegF, 6, F6->as_VMReg());
154 reg_def R_F7 ( SOC, SOC, Op_RegF, 7, F7->as_VMReg());
155 reg_def R_F8 ( SOC, SOC, Op_RegF, 8, F8->as_VMReg());
156 reg_def R_F9 ( SOC, SOC, Op_RegF, 9, F9->as_VMReg());
157 reg_def R_F10( SOC, SOC, Op_RegF, 10, F10->as_VMReg());
158 reg_def R_F11( SOC, SOC, Op_RegF, 11, F11->as_VMReg());
159 reg_def R_F12( SOC, SOC, Op_RegF, 12, F12->as_VMReg());
160 reg_def R_F13( SOC, SOC, Op_RegF, 13, F13->as_VMReg());
161 reg_def R_F14( SOC, SOC, Op_RegF, 14, F14->as_VMReg());
162 reg_def R_F15( SOC, SOC, Op_RegF, 15, F15->as_VMReg());
163 reg_def R_F16( SOC, SOC, Op_RegF, 16, F16->as_VMReg());
164 reg_def R_F17( SOC, SOC, Op_RegF, 17, F17->as_VMReg());
165 reg_def R_F18( SOC, SOC, Op_RegF, 18, F18->as_VMReg());
166 reg_def R_F19( SOC, SOC, Op_RegF, 19, F19->as_VMReg());
167 reg_def R_F20( SOC, SOC, Op_RegF, 20, F20->as_VMReg());
168 reg_def R_F21( SOC, SOC, Op_RegF, 21, F21->as_VMReg());
169 reg_def R_F22( SOC, SOC, Op_RegF, 22, F22->as_VMReg());
170 reg_def R_F23( SOC, SOC, Op_RegF, 23, F23->as_VMReg());
171 reg_def R_F24( SOC, SOC, Op_RegF, 24, F24->as_VMReg());
172 reg_def R_F25( SOC, SOC, Op_RegF, 25, F25->as_VMReg());
173 reg_def R_F26( SOC, SOC, Op_RegF, 26, F26->as_VMReg());
174 reg_def R_F27( SOC, SOC, Op_RegF, 27, F27->as_VMReg());
175 reg_def R_F28( SOC, SOC, Op_RegF, 28, F28->as_VMReg());
176 reg_def R_F29( SOC, SOC, Op_RegF, 29, F29->as_VMReg());
177 reg_def R_F30( SOC, SOC, Op_RegF, 30, F30->as_VMReg());
178 reg_def R_F31( SOC, SOC, Op_RegF, 31, F31->as_VMReg());
179
180 // Double Registers
181 // The rules of ADL require that double registers be defined in pairs.
182 // Each pair must be two 32-bit values, but not necessarily a pair of
183 // single float registers. In each pair, ADLC-assigned register numbers
184 // must be adjacent, with the lower number even. Finally, when the
185 // CPU stores such a register pair to memory, the word associated with
186 // the lower ADLC-assigned number must be stored to the lower address.
187
188 // These definitions specify the actual bit encodings of the sparc
189 // double fp register numbers. FloatRegisterImpl in register_sparc.hpp
190 // wants 0-63, so we have to convert every time we want to use fp regs
191 // with the macroassembler, using reg_to_DoubleFloatRegister_object().
192 // 255 is a flag meaning "don't go here".
193 // I believe we can't handle callee-save doubles D32 and up until
194 // the place in the sparc stack crawler that asserts on the 255 is
195 // fixed up.
196 reg_def R_D32x(SOC, SOC, Op_RegD,255, F32->as_VMReg());
197 reg_def R_D32 (SOC, SOC, Op_RegD, 1, F32->as_VMReg()->next());
198 reg_def R_D34x(SOC, SOC, Op_RegD,255, F34->as_VMReg());
199 reg_def R_D34 (SOC, SOC, Op_RegD, 3, F34->as_VMReg()->next());
200 reg_def R_D36x(SOC, SOC, Op_RegD,255, F36->as_VMReg());
201 reg_def R_D36 (SOC, SOC, Op_RegD, 5, F36->as_VMReg()->next());
202 reg_def R_D38x(SOC, SOC, Op_RegD,255, F38->as_VMReg());
203 reg_def R_D38 (SOC, SOC, Op_RegD, 7, F38->as_VMReg()->next());
204 reg_def R_D40x(SOC, SOC, Op_RegD,255, F40->as_VMReg());
205 reg_def R_D40 (SOC, SOC, Op_RegD, 9, F40->as_VMReg()->next());
206 reg_def R_D42x(SOC, SOC, Op_RegD,255, F42->as_VMReg());
207 reg_def R_D42 (SOC, SOC, Op_RegD, 11, F42->as_VMReg()->next());
208 reg_def R_D44x(SOC, SOC, Op_RegD,255, F44->as_VMReg());
209 reg_def R_D44 (SOC, SOC, Op_RegD, 13, F44->as_VMReg()->next());
210 reg_def R_D46x(SOC, SOC, Op_RegD,255, F46->as_VMReg());
211 reg_def R_D46 (SOC, SOC, Op_RegD, 15, F46->as_VMReg()->next());
212 reg_def R_D48x(SOC, SOC, Op_RegD,255, F48->as_VMReg());
213 reg_def R_D48 (SOC, SOC, Op_RegD, 17, F48->as_VMReg()->next());
214 reg_def R_D50x(SOC, SOC, Op_RegD,255, F50->as_VMReg());
215 reg_def R_D50 (SOC, SOC, Op_RegD, 19, F50->as_VMReg()->next());
216 reg_def R_D52x(SOC, SOC, Op_RegD,255, F52->as_VMReg());
217 reg_def R_D52 (SOC, SOC, Op_RegD, 21, F52->as_VMReg()->next());
218 reg_def R_D54x(SOC, SOC, Op_RegD,255, F54->as_VMReg());
219 reg_def R_D54 (SOC, SOC, Op_RegD, 23, F54->as_VMReg()->next());
220 reg_def R_D56x(SOC, SOC, Op_RegD,255, F56->as_VMReg());
221 reg_def R_D56 (SOC, SOC, Op_RegD, 25, F56->as_VMReg()->next());
222 reg_def R_D58x(SOC, SOC, Op_RegD,255, F58->as_VMReg());
223 reg_def R_D58 (SOC, SOC, Op_RegD, 27, F58->as_VMReg()->next());
224 reg_def R_D60x(SOC, SOC, Op_RegD,255, F60->as_VMReg());
225 reg_def R_D60 (SOC, SOC, Op_RegD, 29, F60->as_VMReg()->next());
226 reg_def R_D62x(SOC, SOC, Op_RegD,255, F62->as_VMReg());
227 reg_def R_D62 (SOC, SOC, Op_RegD, 31, F62->as_VMReg()->next());
228
229
230 // ----------------------------
231 // Special Registers
232 // Condition Codes Flag Registers
233 // I tried to break out ICC and XCC but it's not very pretty.
234 // Every Sparc instruction which defs/kills one also kills the other.
235 // Hence every compare instruction which defs one kind of flags ends
236 // up needing a kill of the other.
237 reg_def CCR (SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad());
238
239 reg_def FCC0(SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad());
240 reg_def FCC1(SOC, SOC, Op_RegFlags, 1, VMRegImpl::Bad());
241 reg_def FCC2(SOC, SOC, Op_RegFlags, 2, VMRegImpl::Bad());
242 reg_def FCC3(SOC, SOC, Op_RegFlags, 3, VMRegImpl::Bad());
243
244 // ----------------------------
245 // Specify the enum values for the registers. These enums are only used by the
246 // OptoReg "class". We can convert these enum values at will to VMReg when needed
247 // for visibility to the rest of the vm. The order of this enum influences the
248 // register allocator so having the freedom to set this order and not be stuck
249 // with the order that is natural for the rest of the vm is worth it.
250 alloc_class chunk0(
251 R_L0,R_L0H, R_L1,R_L1H, R_L2,R_L2H, R_L3,R_L3H, R_L4,R_L4H, R_L5,R_L5H, R_L6,R_L6H, R_L7,R_L7H,
252 R_G0,R_G0H, R_G1,R_G1H, R_G2,R_G2H, R_G3,R_G3H, R_G4,R_G4H, R_G5,R_G5H, R_G6,R_G6H, R_G7,R_G7H,
253 R_O7,R_O7H, R_SP,R_SPH, R_O0,R_O0H, R_O1,R_O1H, R_O2,R_O2H, R_O3,R_O3H, R_O4,R_O4H, R_O5,R_O5H,
254 R_I0,R_I0H, R_I1,R_I1H, R_I2,R_I2H, R_I3,R_I3H, R_I4,R_I4H, R_I5,R_I5H, R_FP,R_FPH, R_I7,R_I7H);
255
256 // Note that a register is not allocatable unless it is also mentioned
257 // in a widely-used reg_class below. Thus, R_G7 and R_G0 are outside i_reg.
258
259 alloc_class chunk1(
260 // The first registers listed here are those most likely to be used
261 // as temporaries. We move F0..F7 away from the front of the list,
262 // to reduce the likelihood of interferences with parameters and
263 // return values. Likewise, we avoid using F0/F1 for parameters,
264 // since they are used for return values.
265 // This FPU fine-tuning is worth about 1% on the SPEC geomean.
266 R_F8 ,R_F9 ,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
267 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,
268 R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,R_F30,R_F31,
269 R_F0 ,R_F1 ,R_F2 ,R_F3 ,R_F4 ,R_F5 ,R_F6 ,R_F7 , // used for arguments and return values
270 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,
271 R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x,
272 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,
273 R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x);
274
275 alloc_class chunk2(CCR, FCC0, FCC1, FCC2, FCC3);
276
277 //----------Architecture Description Register Classes--------------------------
278 // Several register classes are automatically defined based upon information in
279 // this architecture description.
280 // 1) reg_class inline_cache_reg ( as defined in frame section )
281 // 2) reg_class interpreter_method_oop_reg ( as defined in frame section )
282 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
283 //
284
285 // G0 is not included in integer class since it has special meaning.
286 reg_class g0_reg(R_G0);
287
288 // ----------------------------
289 // Integer Register Classes
290 // ----------------------------
291 // Exclusions from i_reg:
292 // R_G0: hardwired zero
293 // R_G2: reserved by HotSpot to the TLS register (invariant within Java)
294 // R_G6: reserved by Solaris ABI to tools
295 // R_G7: reserved by Solaris ABI to libthread
296 // R_O7: Used as a temp in many encodings
297 reg_class int_reg(R_G1,R_G3,R_G4,R_G5,R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
298
299 // Class for all integer registers, except the G registers. This is used for
300 // encodings which use G registers as temps. The regular inputs to such
301 // instructions use a "notemp_" prefix, as a hack to ensure that the allocator
302 // will not put an input into a temp register.
303 reg_class notemp_int_reg(R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
304
305 reg_class g1_regI(R_G1);
306 reg_class g3_regI(R_G3);
307 reg_class g4_regI(R_G4);
308 reg_class o0_regI(R_O0);
309 reg_class o7_regI(R_O7);
310
311 // ----------------------------
312 // Pointer Register Classes
313 // ----------------------------
314 #ifdef _LP64
315 // 64-bit build means 64-bit pointers means hi/lo pairs
316 reg_class ptr_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5,
317 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5,
318 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
319 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 );
320 // Lock encodings use G3 and G4 internally
321 reg_class lock_ptr_reg( R_G1H,R_G1, R_G5H,R_G5,
322 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5,
323 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
324 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 );
325 // Special class for storeP instructions, which can store SP or RPC to TLS.
326 // It is also used for memory addressing, allowing direct TLS addressing.
327 reg_class sp_ptr_reg( R_G1H,R_G1, R_G2H,R_G2, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5,
328 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, R_SPH,R_SP,
329 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
330 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5, R_FPH,R_FP );
331 // R_L7 is the lowest-priority callee-save (i.e., NS) register
332 // We use it to save R_G2 across calls out of Java.
333 reg_class l7_regP(R_L7H,R_L7);
334
335 // Other special pointer regs
336 reg_class g1_regP(R_G1H,R_G1);
337 reg_class g2_regP(R_G2H,R_G2);
338 reg_class g3_regP(R_G3H,R_G3);
339 reg_class g4_regP(R_G4H,R_G4);
340 reg_class g5_regP(R_G5H,R_G5);
341 reg_class i0_regP(R_I0H,R_I0);
342 reg_class o0_regP(R_O0H,R_O0);
343 reg_class o1_regP(R_O1H,R_O1);
344 reg_class o2_regP(R_O2H,R_O2);
345 reg_class o7_regP(R_O7H,R_O7);
346
347 #else // _LP64
348 // 32-bit build means 32-bit pointers means 1 register.
349 reg_class ptr_reg( R_G1, R_G3,R_G4,R_G5,
350 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,
351 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
352 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
353 // Lock encodings use G3 and G4 internally
354 reg_class lock_ptr_reg(R_G1, R_G5,
355 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,
356 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
357 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
358 // Special class for storeP instructions, which can store SP or RPC to TLS.
359 // It is also used for memory addressing, allowing direct TLS addressing.
360 reg_class sp_ptr_reg( R_G1,R_G2,R_G3,R_G4,R_G5,
361 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_SP,
362 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
363 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5,R_FP);
364 // R_L7 is the lowest-priority callee-save (i.e., NS) register
365 // We use it to save R_G2 across calls out of Java.
366 reg_class l7_regP(R_L7);
367
368 // Other special pointer regs
369 reg_class g1_regP(R_G1);
370 reg_class g2_regP(R_G2);
371 reg_class g3_regP(R_G3);
372 reg_class g4_regP(R_G4);
373 reg_class g5_regP(R_G5);
374 reg_class i0_regP(R_I0);
375 reg_class o0_regP(R_O0);
376 reg_class o1_regP(R_O1);
377 reg_class o2_regP(R_O2);
378 reg_class o7_regP(R_O7);
379 #endif // _LP64
380
381
382 // ----------------------------
383 // Long Register Classes
384 // ----------------------------
385 // Longs in 1 register. Aligned adjacent hi/lo pairs.
386 // Note: O7 is never in this class; it is sometimes used as an encoding temp.
387 reg_class long_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5
388 ,R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5
389 #ifdef _LP64
390 // 64-bit, longs in 1 register: use all 64-bit integer registers
391 // 32-bit, longs in 1 register: cannot use I's and L's. Restrict to O's and G's.
392 ,R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7
393 ,R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5
394 #endif // _LP64
395 );
396
397 reg_class g1_regL(R_G1H,R_G1);
398 reg_class g3_regL(R_G3H,R_G3);
399 reg_class o2_regL(R_O2H,R_O2);
400 reg_class o7_regL(R_O7H,R_O7);
401
402 // ----------------------------
403 // Special Class for Condition Code Flags Register
404 reg_class int_flags(CCR);
405 reg_class float_flags(FCC0,FCC1,FCC2,FCC3);
406 reg_class float_flag0(FCC0);
407
408
409 // ----------------------------
410 // Float Point Register Classes
411 // ----------------------------
412 // Skip F30/F31, they are reserved for mem-mem copies
413 reg_class sflt_reg(R_F0,R_F1,R_F2,R_F3,R_F4,R_F5,R_F6,R_F7,R_F8,R_F9,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29);
414
415 // Paired floating point registers--they show up in the same order as the floats,
416 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs.
417 reg_class dflt_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
418 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,
419 /* Use extra V9 double registers; this AD file does not support V8 */
420 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x,
421 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x
422 );
423
424 // Paired floating point registers--they show up in the same order as the floats,
425 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs.
426 // This class is usable for mis-aligned loads as happen in I2C adapters.
427 reg_class dflt_low_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
428 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,R_F30,R_F31 );
429 %}
430
431 //----------DEFINITION BLOCK---------------------------------------------------
432 // Define name --> value mappings to inform the ADLC of an integer valued name
433 // Current support includes integer values in the range [0, 0x7FFFFFFF]
434 // Format:
435 // int_def <name> ( <int_value>, <expression>);
436 // Generated Code in ad_<arch>.hpp
437 // #define <name> (<expression>)
438 // // value == <int_value>
439 // Generated code in ad_<arch>.cpp adlc_verification()
440 // assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>");
441 //
442 definitions %{
443 // The default cost (of an ALU instruction).
444 int_def DEFAULT_COST ( 100, 100);
445 int_def HUGE_COST (1000000, 1000000);
446
447 // Memory refs are twice as expensive as run-of-the-mill.
448 int_def MEMORY_REF_COST ( 200, DEFAULT_COST * 2);
449
450 // Branches are even more expensive.
451 int_def BRANCH_COST ( 300, DEFAULT_COST * 3);
452 int_def CALL_COST ( 300, DEFAULT_COST * 3);
453 %}
454
455
456 //----------SOURCE BLOCK-------------------------------------------------------
457 // This is a block of C++ code which provides values, functions, and
458 // definitions necessary in the rest of the architecture description
459 source_hpp %{
460 // Must be visible to the DFA in dfa_sparc.cpp
461 extern bool can_branch_register( Node *bol, Node *cmp );
462
463 // Macros to extract hi & lo halves from a long pair.
464 // G0 is not part of any long pair, so assert on that.
465 // Prevents accidentally using G1 instead of G0.
466 #define LONG_HI_REG(x) (x)
467 #define LONG_LO_REG(x) (x)
468
469 %}
470
471 source %{
472 #define __ _masm.
473
474 // tertiary op of a LoadP or StoreP encoding
475 #define REGP_OP true
476
477 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding);
478 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding);
479 static Register reg_to_register_object(int register_encoding);
480
481 // Used by the DFA in dfa_sparc.cpp.
482 // Check for being able to use a V9 branch-on-register. Requires a
483 // compare-vs-zero, equal/not-equal, of a value which was zero- or sign-
484 // extended. Doesn't work following an integer ADD, for example, because of
485 // overflow (-1 incremented yields 0 plus a carry in the high-order word). On
486 // 32-bit V9 systems, interrupts currently blow away the high-order 32 bits and
487 // replace them with zero, which could become sign-extension in a different OS
488 // release. There's no obvious reason why an interrupt will ever fill these
489 // bits with non-zero junk (the registers are reloaded with standard LD
490 // instructions which either zero-fill or sign-fill).
491 bool can_branch_register( Node *bol, Node *cmp ) {
492 if( !BranchOnRegister ) return false;
493 #ifdef _LP64
494 if( cmp->Opcode() == Op_CmpP )
495 return true; // No problems with pointer compares
496 #endif
497 if( cmp->Opcode() == Op_CmpL )
498 return true; // No problems with long compares
499
500 if( !SparcV9RegsHiBitsZero ) return false;
501 if( bol->as_Bool()->_test._test != BoolTest::ne &&
502 bol->as_Bool()->_test._test != BoolTest::eq )
503 return false;
504
505 // Check for comparing against a 'safe' value. Any operation which
506 // clears out the high word is safe. Thus, loads and certain shifts
507 // are safe, as are non-negative constants. Any operation which
508 // preserves zero bits in the high word is safe as long as each of its
509 // inputs are safe. Thus, phis and bitwise booleans are safe if their
510 // inputs are safe. At present, the only important case to recognize
511 // seems to be loads. Constants should fold away, and shifts &
512 // logicals can use the 'cc' forms.
513 Node *x = cmp->in(1);
514 if( x->is_Load() ) return true;
515 if( x->is_Phi() ) {
516 for( uint i = 1; i < x->req(); i++ )
517 if( !x->in(i)->is_Load() )
518 return false;
519 return true;
520 }
521 return false;
522 }
523
524 // ****************************************************************************
525
526 // REQUIRED FUNCTIONALITY
527
528 // !!!!! Special hack to get all type of calls to specify the byte offset
529 // from the start of the call to the point where the return address
530 // will point.
531 // The "return address" is the address of the call instruction, plus 8.
532
533 int MachCallStaticJavaNode::ret_addr_offset() {
534 return NativeCall::instruction_size; // call; delay slot
535 }
536
537 int MachCallDynamicJavaNode::ret_addr_offset() {
538 int vtable_index = this->_vtable_index;
539 if (vtable_index < 0) {
540 // must be invalid_vtable_index, not nonvirtual_vtable_index
541 assert(vtable_index == methodOopDesc::invalid_vtable_index, "correct sentinel value");
542 return (NativeMovConstReg::instruction_size +
543 NativeCall::instruction_size); // sethi; setlo; call; delay slot
544 } else {
545 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
546 int entry_offset = instanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size();
547 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes();
548 int klass_load_size;
549 if (UseCompressedOops) {
550 assert(Universe::heap() != NULL, "java heap should be initialized");
551 if (Universe::narrow_oop_base() == NULL)
552 klass_load_size = 2*BytesPerInstWord; // see MacroAssembler::load_klass()
553 else
554 klass_load_size = 3*BytesPerInstWord;
555 } else {
556 klass_load_size = 1*BytesPerInstWord;
557 }
558 if( Assembler::is_simm13(v_off) ) {
559 return klass_load_size +
560 (2*BytesPerInstWord + // ld_ptr, ld_ptr
561 NativeCall::instruction_size); // call; delay slot
562 } else {
563 return klass_load_size +
564 (4*BytesPerInstWord + // set_hi, set, ld_ptr, ld_ptr
565 NativeCall::instruction_size); // call; delay slot
566 }
567 }
568 }
569
570 int MachCallRuntimeNode::ret_addr_offset() {
571 #ifdef _LP64
572 return NativeFarCall::instruction_size; // farcall; delay slot
573 #else
574 return NativeCall::instruction_size; // call; delay slot
575 #endif
576 }
577
578 // Indicate if the safepoint node needs the polling page as an input.
579 // Since Sparc does not have absolute addressing, it does.
580 bool SafePointNode::needs_polling_address_input() {
581 return true;
582 }
583
584 // emit an interrupt that is caught by the debugger (for debugging compiler)
585 void emit_break(CodeBuffer &cbuf) {
586 MacroAssembler _masm(&cbuf);
587 __ breakpoint_trap();
588 }
589
590 #ifndef PRODUCT
591 void MachBreakpointNode::format( PhaseRegAlloc *, outputStream *st ) const {
592 st->print("TA");
593 }
594 #endif
595
596 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
597 emit_break(cbuf);
598 }
599
600 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {
601 return MachNode::size(ra_);
602 }
603
604 // Traceable jump
605 void emit_jmpl(CodeBuffer &cbuf, int jump_target) {
606 MacroAssembler _masm(&cbuf);
607 Register rdest = reg_to_register_object(jump_target);
608 __ JMP(rdest, 0);
609 __ delayed()->nop();
610 }
611
612 // Traceable jump and set exception pc
613 void emit_jmpl_set_exception_pc(CodeBuffer &cbuf, int jump_target) {
614 MacroAssembler _masm(&cbuf);
615 Register rdest = reg_to_register_object(jump_target);
616 __ JMP(rdest, 0);
617 __ delayed()->add(O7, frame::pc_return_offset, Oissuing_pc );
618 }
619
620 void emit_nop(CodeBuffer &cbuf) {
621 MacroAssembler _masm(&cbuf);
622 __ nop();
623 }
624
625 void emit_illtrap(CodeBuffer &cbuf) {
626 MacroAssembler _masm(&cbuf);
627 __ illtrap(0);
628 }
629
630
631 intptr_t get_offset_from_base(const MachNode* n, const TypePtr* atype, int disp32) {
632 assert(n->rule() != loadUB_rule, "");
633
634 intptr_t offset = 0;
635 const TypePtr *adr_type = TYPE_PTR_SENTINAL; // Check for base==RegI, disp==immP
636 const Node* addr = n->get_base_and_disp(offset, adr_type);
637 assert(adr_type == (const TypePtr*)-1, "VerifyOops: no support for sparc operands with base==RegI, disp==immP");
638 assert(addr != NULL && addr != (Node*)-1, "invalid addr");
639 assert(addr->bottom_type()->isa_oopptr() == atype, "");
640 atype = atype->add_offset(offset);
641 assert(disp32 == offset, "wrong disp32");
642 return atype->_offset;
643 }
644
645
646 intptr_t get_offset_from_base_2(const MachNode* n, const TypePtr* atype, int disp32) {
647 assert(n->rule() != loadUB_rule, "");
648
649 intptr_t offset = 0;
650 Node* addr = n->in(2);
651 assert(addr->bottom_type()->isa_oopptr() == atype, "");
652 if (addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP) {
653 Node* a = addr->in(2/*AddPNode::Address*/);
654 Node* o = addr->in(3/*AddPNode::Offset*/);
655 offset = o->is_Con() ? o->bottom_type()->is_intptr_t()->get_con() : Type::OffsetBot;
656 atype = a->bottom_type()->is_ptr()->add_offset(offset);
657 assert(atype->isa_oop_ptr(), "still an oop");
658 }
659 offset = atype->is_ptr()->_offset;
660 if (offset != Type::OffsetBot) offset += disp32;
661 return offset;
662 }
663
664 // Standard Sparc opcode form2 field breakdown
665 static inline void emit2_19(CodeBuffer &cbuf, int f30, int f29, int f25, int f22, int f20, int f19, int f0 ) {
666 f0 &= (1<<19)-1; // Mask displacement to 19 bits
667 int op = (f30 << 30) |
668 (f29 << 29) |
669 (f25 << 25) |
670 (f22 << 22) |
671 (f20 << 20) |
672 (f19 << 19) |
673 (f0 << 0);
674 *((int*)(cbuf.code_end())) = op;
675 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
676 }
677
678 // Standard Sparc opcode form2 field breakdown
679 static inline void emit2_22(CodeBuffer &cbuf, int f30, int f25, int f22, int f0 ) {
680 f0 >>= 10; // Drop 10 bits
681 f0 &= (1<<22)-1; // Mask displacement to 22 bits
682 int op = (f30 << 30) |
683 (f25 << 25) |
684 (f22 << 22) |
685 (f0 << 0);
686 *((int*)(cbuf.code_end())) = op;
687 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
688 }
689
690 // Standard Sparc opcode form3 field breakdown
691 static inline void emit3(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int f5, int f0 ) {
692 int op = (f30 << 30) |
693 (f25 << 25) |
694 (f19 << 19) |
695 (f14 << 14) |
696 (f5 << 5) |
697 (f0 << 0);
698 *((int*)(cbuf.code_end())) = op;
699 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
700 }
701
702 // Standard Sparc opcode form3 field breakdown
703 static inline void emit3_simm13(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm13 ) {
704 simm13 &= (1<<13)-1; // Mask to 13 bits
705 int op = (f30 << 30) |
706 (f25 << 25) |
707 (f19 << 19) |
708 (f14 << 14) |
709 (1 << 13) | // bit to indicate immediate-mode
710 (simm13<<0);
711 *((int*)(cbuf.code_end())) = op;
712 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
713 }
714
715 static inline void emit3_simm10(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm10 ) {
716 simm10 &= (1<<10)-1; // Mask to 10 bits
717 emit3_simm13(cbuf,f30,f25,f19,f14,simm10);
718 }
719
720 #ifdef ASSERT
721 // Helper function for VerifyOops in emit_form3_mem_reg
722 void verify_oops_warning(const MachNode *n, int ideal_op, int mem_op) {
723 warning("VerifyOops encountered unexpected instruction:");
724 n->dump(2);
725 warning("Instruction has ideal_Opcode==Op_%s and op_ld==Op_%s \n", NodeClassNames[ideal_op], NodeClassNames[mem_op]);
726 }
727 #endif
728
729
730 void emit_form3_mem_reg(CodeBuffer &cbuf, const MachNode* n, int primary, int tertiary,
731 int src1_enc, int disp32, int src2_enc, int dst_enc) {
732
733 #ifdef ASSERT
734 // The following code implements the +VerifyOops feature.
735 // It verifies oop values which are loaded into or stored out of
736 // the current method activation. +VerifyOops complements techniques
737 // like ScavengeALot, because it eagerly inspects oops in transit,
738 // as they enter or leave the stack, as opposed to ScavengeALot,
739 // which inspects oops "at rest", in the stack or heap, at safepoints.
740 // For this reason, +VerifyOops can sometimes detect bugs very close
741 // to their point of creation. It can also serve as a cross-check
742 // on the validity of oop maps, when used toegether with ScavengeALot.
743
744 // It would be good to verify oops at other points, especially
745 // when an oop is used as a base pointer for a load or store.
746 // This is presently difficult, because it is hard to know when
747 // a base address is biased or not. (If we had such information,
748 // it would be easy and useful to make a two-argument version of
749 // verify_oop which unbiases the base, and performs verification.)
750
751 assert((uint)tertiary == 0xFFFFFFFF || tertiary == REGP_OP, "valid tertiary");
752 bool is_verified_oop_base = false;
753 bool is_verified_oop_load = false;
754 bool is_verified_oop_store = false;
755 int tmp_enc = -1;
756 if (VerifyOops && src1_enc != R_SP_enc) {
757 // classify the op, mainly for an assert check
758 int st_op = 0, ld_op = 0;
759 switch (primary) {
760 case Assembler::stb_op3: st_op = Op_StoreB; break;
761 case Assembler::sth_op3: st_op = Op_StoreC; break;
762 case Assembler::stx_op3: // may become StoreP or stay StoreI or StoreD0
763 case Assembler::stw_op3: st_op = Op_StoreI; break;
764 case Assembler::std_op3: st_op = Op_StoreL; break;
765 case Assembler::stf_op3: st_op = Op_StoreF; break;
766 case Assembler::stdf_op3: st_op = Op_StoreD; break;
767
768 case Assembler::ldsb_op3: ld_op = Op_LoadB; break;
769 case Assembler::lduh_op3: ld_op = Op_LoadUS; break;
770 case Assembler::ldsh_op3: ld_op = Op_LoadS; break;
771 case Assembler::ldx_op3: // may become LoadP or stay LoadI
772 case Assembler::ldsw_op3: // may become LoadP or stay LoadI
773 case Assembler::lduw_op3: ld_op = Op_LoadI; break;
774 case Assembler::ldd_op3: ld_op = Op_LoadL; break;
775 case Assembler::ldf_op3: ld_op = Op_LoadF; break;
776 case Assembler::lddf_op3: ld_op = Op_LoadD; break;
777 case Assembler::ldub_op3: ld_op = Op_LoadB; break;
778 case Assembler::prefetch_op3: ld_op = Op_LoadI; break;
779
780 default: ShouldNotReachHere();
781 }
782 if (tertiary == REGP_OP) {
783 if (st_op == Op_StoreI) st_op = Op_StoreP;
784 else if (ld_op == Op_LoadI) ld_op = Op_LoadP;
785 else ShouldNotReachHere();
786 if (st_op) {
787 // a store
788 // inputs are (0:control, 1:memory, 2:address, 3:value)
789 Node* n2 = n->in(3);
790 if (n2 != NULL) {
791 const Type* t = n2->bottom_type();
792 is_verified_oop_store = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false;
793 }
794 } else {
795 // a load
796 const Type* t = n->bottom_type();
797 is_verified_oop_load = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false;
798 }
799 }
800
801 if (ld_op) {
802 // a Load
803 // inputs are (0:control, 1:memory, 2:address)
804 if (!(n->ideal_Opcode()==ld_op) && // Following are special cases
805 !(n->ideal_Opcode()==Op_LoadLLocked && ld_op==Op_LoadI) &&
806 !(n->ideal_Opcode()==Op_LoadPLocked && ld_op==Op_LoadP) &&
807 !(n->ideal_Opcode()==Op_LoadI && ld_op==Op_LoadF) &&
808 !(n->ideal_Opcode()==Op_LoadF && ld_op==Op_LoadI) &&
809 !(n->ideal_Opcode()==Op_LoadRange && ld_op==Op_LoadI) &&
810 !(n->ideal_Opcode()==Op_LoadKlass && ld_op==Op_LoadP) &&
811 !(n->ideal_Opcode()==Op_LoadL && ld_op==Op_LoadI) &&
812 !(n->ideal_Opcode()==Op_LoadL_unaligned && ld_op==Op_LoadI) &&
813 !(n->ideal_Opcode()==Op_LoadD_unaligned && ld_op==Op_LoadF) &&
814 !(n->ideal_Opcode()==Op_ConvI2F && ld_op==Op_LoadF) &&
815 !(n->ideal_Opcode()==Op_ConvI2D && ld_op==Op_LoadF) &&
816 !(n->ideal_Opcode()==Op_PrefetchRead && ld_op==Op_LoadI) &&
817 !(n->ideal_Opcode()==Op_PrefetchWrite && ld_op==Op_LoadI) &&
818 !(n->rule() == loadUB_rule)) {
819 verify_oops_warning(n, n->ideal_Opcode(), ld_op);
820 }
821 } else if (st_op) {
822 // a Store
823 // inputs are (0:control, 1:memory, 2:address, 3:value)
824 if (!(n->ideal_Opcode()==st_op) && // Following are special cases
825 !(n->ideal_Opcode()==Op_StoreCM && st_op==Op_StoreB) &&
826 !(n->ideal_Opcode()==Op_StoreI && st_op==Op_StoreF) &&
827 !(n->ideal_Opcode()==Op_StoreF && st_op==Op_StoreI) &&
828 !(n->ideal_Opcode()==Op_StoreL && st_op==Op_StoreI) &&
829 !(n->ideal_Opcode()==Op_StoreD && st_op==Op_StoreI && n->rule() == storeD0_rule)) {
830 verify_oops_warning(n, n->ideal_Opcode(), st_op);
831 }
832 }
833
834 if (src2_enc == R_G0_enc && n->rule() != loadUB_rule && n->ideal_Opcode() != Op_StoreCM ) {
835 Node* addr = n->in(2);
836 if (!(addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP)) {
837 const TypeOopPtr* atype = addr->bottom_type()->isa_instptr(); // %%% oopptr?
838 if (atype != NULL) {
839 intptr_t offset = get_offset_from_base(n, atype, disp32);
840 intptr_t offset_2 = get_offset_from_base_2(n, atype, disp32);
841 if (offset != offset_2) {
842 get_offset_from_base(n, atype, disp32);
843 get_offset_from_base_2(n, atype, disp32);
844 }
845 assert(offset == offset_2, "different offsets");
846 if (offset == disp32) {
847 // we now know that src1 is a true oop pointer
848 is_verified_oop_base = true;
849 if (ld_op && src1_enc == dst_enc && ld_op != Op_LoadF && ld_op != Op_LoadD) {
850 if( primary == Assembler::ldd_op3 ) {
851 is_verified_oop_base = false; // Cannot 'ldd' into O7
852 } else {
853 tmp_enc = dst_enc;
854 dst_enc = R_O7_enc; // Load into O7; preserve source oop
855 assert(src1_enc != dst_enc, "");
856 }
857 }
858 }
859 if (st_op && (( offset == oopDesc::klass_offset_in_bytes())
860 || offset == oopDesc::mark_offset_in_bytes())) {
861 // loading the mark should not be allowed either, but
862 // we don't check this since it conflicts with InlineObjectHash
863 // usage of LoadINode to get the mark. We could keep the
864 // check if we create a new LoadMarkNode
865 // but do not verify the object before its header is initialized
866 ShouldNotReachHere();
867 }
868 }
869 }
870 }
871 }
872 #endif
873
874 uint instr;
875 instr = (Assembler::ldst_op << 30)
876 | (dst_enc << 25)
877 | (primary << 19)
878 | (src1_enc << 14);
879
880 uint index = src2_enc;
881 int disp = disp32;
882
883 if (src1_enc == R_SP_enc || src1_enc == R_FP_enc)
884 disp += STACK_BIAS;
885
886 // We should have a compiler bailout here rather than a guarantee.
887 // Better yet would be some mechanism to handle variable-size matches correctly.
888 guarantee(Assembler::is_simm13(disp), "Do not match large constant offsets" );
889
890 if( disp == 0 ) {
891 // use reg-reg form
892 // bit 13 is already zero
893 instr |= index;
894 } else {
895 // use reg-imm form
896 instr |= 0x00002000; // set bit 13 to one
897 instr |= disp & 0x1FFF;
898 }
899
900 uint *code = (uint*)cbuf.code_end();
901 *code = instr;
902 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
903
904 #ifdef ASSERT
905 {
906 MacroAssembler _masm(&cbuf);
907 if (is_verified_oop_base) {
908 __ verify_oop(reg_to_register_object(src1_enc));
909 }
910 if (is_verified_oop_store) {
911 __ verify_oop(reg_to_register_object(dst_enc));
912 }
913 if (tmp_enc != -1) {
914 __ mov(O7, reg_to_register_object(tmp_enc));
915 }
916 if (is_verified_oop_load) {
917 __ verify_oop(reg_to_register_object(dst_enc));
918 }
919 }
920 #endif
921 }
922
923 void emit_form3_mem_reg_asi(CodeBuffer &cbuf, const MachNode* n, int primary, int tertiary,
924 int src1_enc, int disp32, int src2_enc, int dst_enc, int asi) {
925
926 uint instr;
927 instr = (Assembler::ldst_op << 30)
928 | (dst_enc << 25)
929 | (primary << 19)
930 | (src1_enc << 14);
931
932 int disp = disp32;
933 int index = src2_enc;
934
935 if (src1_enc == R_SP_enc || src1_enc == R_FP_enc)
936 disp += STACK_BIAS;
937
938 // We should have a compiler bailout here rather than a guarantee.
939 // Better yet would be some mechanism to handle variable-size matches correctly.
940 guarantee(Assembler::is_simm13(disp), "Do not match large constant offsets" );
941
942 if( disp != 0 ) {
943 // use reg-reg form
944 // set src2=R_O7 contains offset
945 index = R_O7_enc;
946 emit3_simm13( cbuf, Assembler::arith_op, index, Assembler::or_op3, 0, disp);
947 }
948 instr |= (asi << 5);
949 instr |= index;
950 uint *code = (uint*)cbuf.code_end();
951 *code = instr;
952 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
953 }
954
955 void emit_call_reloc(CodeBuffer &cbuf, intptr_t entry_point, relocInfo::relocType rtype, bool preserve_g2 = false, bool force_far_call = false) {
956 // The method which records debug information at every safepoint
957 // expects the call to be the first instruction in the snippet as
958 // it creates a PcDesc structure which tracks the offset of a call
959 // from the start of the codeBlob. This offset is computed as
960 // code_end() - code_begin() of the code which has been emitted
961 // so far.
962 // In this particular case we have skirted around the problem by
963 // putting the "mov" instruction in the delay slot but the problem
964 // may bite us again at some other point and a cleaner/generic
965 // solution using relocations would be needed.
966 MacroAssembler _masm(&cbuf);
967 __ set_inst_mark();
968
969 // We flush the current window just so that there is a valid stack copy
970 // the fact that the current window becomes active again instantly is
971 // not a problem there is nothing live in it.
972
973 #ifdef ASSERT
974 int startpos = __ offset();
975 #endif /* ASSERT */
976
977 #ifdef _LP64
978 // Calls to the runtime or native may not be reachable from compiled code,
979 // so we generate the far call sequence on 64 bit sparc.
980 // This code sequence is relocatable to any address, even on LP64.
981 if ( force_far_call ) {
982 __ relocate(rtype);
983 AddressLiteral dest(entry_point);
984 __ jumpl_to(dest, O7, O7);
985 }
986 else
987 #endif
988 {
989 __ call((address)entry_point, rtype);
990 }
991
992 if (preserve_g2) __ delayed()->mov(G2, L7);
993 else __ delayed()->nop();
994
995 if (preserve_g2) __ mov(L7, G2);
996
997 #ifdef ASSERT
998 if (preserve_g2 && (VerifyCompiledCode || VerifyOops)) {
999 #ifdef _LP64
1000 // Trash argument dump slots.
1001 __ set(0xb0b8ac0db0b8ac0d, G1);
1002 __ mov(G1, G5);
1003 __ stx(G1, SP, STACK_BIAS + 0x80);
1004 __ stx(G1, SP, STACK_BIAS + 0x88);
1005 __ stx(G1, SP, STACK_BIAS + 0x90);
1006 __ stx(G1, SP, STACK_BIAS + 0x98);
1007 __ stx(G1, SP, STACK_BIAS + 0xA0);
1008 __ stx(G1, SP, STACK_BIAS + 0xA8);
1009 #else // _LP64
1010 // this is also a native call, so smash the first 7 stack locations,
1011 // and the various registers
1012
1013 // Note: [SP+0x40] is sp[callee_aggregate_return_pointer_sp_offset],
1014 // while [SP+0x44..0x58] are the argument dump slots.
1015 __ set((intptr_t)0xbaadf00d, G1);
1016 __ mov(G1, G5);
1017 __ sllx(G1, 32, G1);
1018 __ or3(G1, G5, G1);
1019 __ mov(G1, G5);
1020 __ stx(G1, SP, 0x40);
1021 __ stx(G1, SP, 0x48);
1022 __ stx(G1, SP, 0x50);
1023 __ stw(G1, SP, 0x58); // Do not trash [SP+0x5C] which is a usable spill slot
1024 #endif // _LP64
1025 }
1026 #endif /*ASSERT*/
1027 }
1028
1029 //=============================================================================
1030 // REQUIRED FUNCTIONALITY for encoding
1031 void emit_lo(CodeBuffer &cbuf, int val) { }
1032 void emit_hi(CodeBuffer &cbuf, int val) { }
1033
1034
1035 //=============================================================================
1036
1037 #ifndef PRODUCT
1038 void MachPrologNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1039 Compile* C = ra_->C;
1040
1041 for (int i = 0; i < OptoPrologueNops; i++) {
1042 st->print_cr("NOP"); st->print("\t");
1043 }
1044
1045 if( VerifyThread ) {
1046 st->print_cr("Verify_Thread"); st->print("\t");
1047 }
1048
1049 size_t framesize = C->frame_slots() << LogBytesPerInt;
1050
1051 // Calls to C2R adapters often do not accept exceptional returns.
1052 // We require that their callers must bang for them. But be careful, because
1053 // some VM calls (such as call site linkage) can use several kilobytes of
1054 // stack. But the stack safety zone should account for that.
1055 // See bugs 4446381, 4468289, 4497237.
1056 if (C->need_stack_bang(framesize)) {
1057 st->print_cr("! stack bang"); st->print("\t");
1058 }
1059
1060 if (Assembler::is_simm13(-framesize)) {
1061 st->print ("SAVE R_SP,-%d,R_SP",framesize);
1062 } else {
1063 st->print_cr("SETHI R_SP,hi%%(-%d),R_G3",framesize); st->print("\t");
1064 st->print_cr("ADD R_G3,lo%%(-%d),R_G3",framesize); st->print("\t");
1065 st->print ("SAVE R_SP,R_G3,R_SP");
1066 }
1067
1068 }
1069 #endif
1070
1071 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1072 Compile* C = ra_->C;
1073 MacroAssembler _masm(&cbuf);
1074
1075 for (int i = 0; i < OptoPrologueNops; i++) {
1076 __ nop();
1077 }
1078
1079 __ verify_thread();
1080
1081 size_t framesize = C->frame_slots() << LogBytesPerInt;
1082 assert(framesize >= 16*wordSize, "must have room for reg. save area");
1083 assert(framesize%(2*wordSize) == 0, "must preserve 2*wordSize alignment");
1084
1085 // Calls to C2R adapters often do not accept exceptional returns.
1086 // We require that their callers must bang for them. But be careful, because
1087 // some VM calls (such as call site linkage) can use several kilobytes of
1088 // stack. But the stack safety zone should account for that.
1089 // See bugs 4446381, 4468289, 4497237.
1090 if (C->need_stack_bang(framesize)) {
1091 __ generate_stack_overflow_check(framesize);
1092 }
1093
1094 if (Assembler::is_simm13(-framesize)) {
1095 __ save(SP, -framesize, SP);
1096 } else {
1097 __ sethi(-framesize & ~0x3ff, G3);
1098 __ add(G3, -framesize & 0x3ff, G3);
1099 __ save(SP, G3, SP);
1100 }
1101 C->set_frame_complete( __ offset() );
1102 }
1103
1104 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
1105 return MachNode::size(ra_);
1106 }
1107
1108 int MachPrologNode::reloc() const {
1109 return 10; // a large enough number
1110 }
1111
1112 //=============================================================================
1113 #ifndef PRODUCT
1114 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1115 Compile* C = ra_->C;
1116
1117 if( do_polling() && ra_->C->is_method_compilation() ) {
1118 st->print("SETHI #PollAddr,L0\t! Load Polling address\n\t");
1119 #ifdef _LP64
1120 st->print("LDX [L0],G0\t!Poll for Safepointing\n\t");
1121 #else
1122 st->print("LDUW [L0],G0\t!Poll for Safepointing\n\t");
1123 #endif
1124 }
1125
1126 if( do_polling() )
1127 st->print("RET\n\t");
1128
1129 st->print("RESTORE");
1130 }
1131 #endif
1132
1133 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1134 MacroAssembler _masm(&cbuf);
1135 Compile* C = ra_->C;
1136
1137 __ verify_thread();
1138
1139 // If this does safepoint polling, then do it here
1140 if( do_polling() && ra_->C->is_method_compilation() ) {
1141 AddressLiteral polling_page(os::get_polling_page());
1142 __ sethi(polling_page, L0);
1143 __ relocate(relocInfo::poll_return_type);
1144 __ ld_ptr( L0, 0, G0 );
1145 }
1146
1147 // If this is a return, then stuff the restore in the delay slot
1148 if( do_polling() ) {
1149 __ ret();
1150 __ delayed()->restore();
1151 } else {
1152 __ restore();
1153 }
1154 }
1155
1156 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
1157 return MachNode::size(ra_);
1158 }
1159
1160 int MachEpilogNode::reloc() const {
1161 return 16; // a large enough number
1162 }
1163
1164 const Pipeline * MachEpilogNode::pipeline() const {
1165 return MachNode::pipeline_class();
1166 }
1167
1168 int MachEpilogNode::safepoint_offset() const {
1169 assert( do_polling(), "no return for this epilog node");
1170 return MacroAssembler::size_of_sethi(os::get_polling_page());
1171 }
1172
1173 //=============================================================================
1174
1175 // Figure out which register class each belongs in: rc_int, rc_float, rc_stack
1176 enum RC { rc_bad, rc_int, rc_float, rc_stack };
1177 static enum RC rc_class( OptoReg::Name reg ) {
1178 if( !OptoReg::is_valid(reg) ) return rc_bad;
1179 if (OptoReg::is_stack(reg)) return rc_stack;
1180 VMReg r = OptoReg::as_VMReg(reg);
1181 if (r->is_Register()) return rc_int;
1182 assert(r->is_FloatRegister(), "must be");
1183 return rc_float;
1184 }
1185
1186 static int impl_helper( const MachNode *mach, CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, bool is_load, int offset, int reg, int opcode, const char *op_str, int size, outputStream* st ) {
1187 if( cbuf ) {
1188 // Better yet would be some mechanism to handle variable-size matches correctly
1189 if (!Assembler::is_simm13(offset + STACK_BIAS)) {
1190 ra_->C->record_method_not_compilable("unable to handle large constant offsets");
1191 } else {
1192 emit_form3_mem_reg(*cbuf, mach, opcode, -1, R_SP_enc, offset, 0, Matcher::_regEncode[reg]);
1193 }
1194 }
1195 #ifndef PRODUCT
1196 else if( !do_size ) {
1197 if( size != 0 ) st->print("\n\t");
1198 if( is_load ) st->print("%s [R_SP + #%d],R_%s\t! spill",op_str,offset,OptoReg::regname(reg));
1199 else st->print("%s R_%s,[R_SP + #%d]\t! spill",op_str,OptoReg::regname(reg),offset);
1200 }
1201 #endif
1202 return size+4;
1203 }
1204
1205 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int op1, int op2, const char *op_str, int size, outputStream* st ) {
1206 if( cbuf ) emit3( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst], op1, 0, op2, Matcher::_regEncode[src] );
1207 #ifndef PRODUCT
1208 else if( !do_size ) {
1209 if( size != 0 ) st->print("\n\t");
1210 st->print("%s R_%s,R_%s\t! spill",op_str,OptoReg::regname(src),OptoReg::regname(dst));
1211 }
1212 #endif
1213 return size+4;
1214 }
1215
1216 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf,
1217 PhaseRegAlloc *ra_,
1218 bool do_size,
1219 outputStream* st ) const {
1220 // Get registers to move
1221 OptoReg::Name src_second = ra_->get_reg_second(in(1));
1222 OptoReg::Name src_first = ra_->get_reg_first(in(1));
1223 OptoReg::Name dst_second = ra_->get_reg_second(this );
1224 OptoReg::Name dst_first = ra_->get_reg_first(this );
1225
1226 enum RC src_second_rc = rc_class(src_second);
1227 enum RC src_first_rc = rc_class(src_first);
1228 enum RC dst_second_rc = rc_class(dst_second);
1229 enum RC dst_first_rc = rc_class(dst_first);
1230
1231 assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" );
1232
1233 // Generate spill code!
1234 int size = 0;
1235
1236 if( src_first == dst_first && src_second == dst_second )
1237 return size; // Self copy, no move
1238
1239 // --------------------------------------
1240 // Check for mem-mem move. Load into unused float registers and fall into
1241 // the float-store case.
1242 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
1243 int offset = ra_->reg2offset(src_first);
1244 // Further check for aligned-adjacent pair, so we can use a double load
1245 if( (src_first&1)==0 && src_first+1 == src_second ) {
1246 src_second = OptoReg::Name(R_F31_num);
1247 src_second_rc = rc_float;
1248 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::lddf_op3,"LDDF",size, st);
1249 } else {
1250 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::ldf_op3 ,"LDF ",size, st);
1251 }
1252 src_first = OptoReg::Name(R_F30_num);
1253 src_first_rc = rc_float;
1254 }
1255
1256 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) {
1257 int offset = ra_->reg2offset(src_second);
1258 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F31_num,Assembler::ldf_op3,"LDF ",size, st);
1259 src_second = OptoReg::Name(R_F31_num);
1260 src_second_rc = rc_float;
1261 }
1262
1263 // --------------------------------------
1264 // Check for float->int copy; requires a trip through memory
1265 if( src_first_rc == rc_float && dst_first_rc == rc_int ) {
1266 int offset = frame::register_save_words*wordSize;
1267 if( cbuf ) {
1268 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::sub_op3, R_SP_enc, 16 );
1269 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
1270 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
1271 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::add_op3, R_SP_enc, 16 );
1272 }
1273 #ifndef PRODUCT
1274 else if( !do_size ) {
1275 if( size != 0 ) st->print("\n\t");
1276 st->print( "SUB R_SP,16,R_SP\n");
1277 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
1278 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
1279 st->print("\tADD R_SP,16,R_SP\n");
1280 }
1281 #endif
1282 size += 16;
1283 }
1284
1285 // --------------------------------------
1286 // In the 32-bit 1-reg-longs build ONLY, I see mis-aligned long destinations.
1287 // In such cases, I have to do the big-endian swap. For aligned targets, the
1288 // hardware does the flop for me. Doubles are always aligned, so no problem
1289 // there. Misaligned sources only come from native-long-returns (handled
1290 // special below).
1291 #ifndef _LP64
1292 if( src_first_rc == rc_int && // source is already big-endian
1293 src_second_rc != rc_bad && // 64-bit move
1294 ((dst_first&1)!=0 || dst_second != dst_first+1) ) { // misaligned dst
1295 assert( (src_first&1)==0 && src_second == src_first+1, "source must be aligned" );
1296 // Do the big-endian flop.
1297 OptoReg::Name tmp = dst_first ; dst_first = dst_second ; dst_second = tmp ;
1298 enum RC tmp_rc = dst_first_rc; dst_first_rc = dst_second_rc; dst_second_rc = tmp_rc;
1299 }
1300 #endif
1301
1302 // --------------------------------------
1303 // Check for integer reg-reg copy
1304 if( src_first_rc == rc_int && dst_first_rc == rc_int ) {
1305 #ifndef _LP64
1306 if( src_first == R_O0_num && src_second == R_O1_num ) { // Check for the evil O0/O1 native long-return case
1307 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value
1308 // as stored in memory. On a big-endian machine like SPARC, this means that the _second
1309 // operand contains the least significant word of the 64-bit value and vice versa.
1310 OptoReg::Name tmp = OptoReg::Name(R_O7_num);
1311 assert( (dst_first&1)==0 && dst_second == dst_first+1, "return a native O0/O1 long to an aligned-adjacent 64-bit reg" );
1312 // Shift O0 left in-place, zero-extend O1, then OR them into the dst
1313 if( cbuf ) {
1314 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tmp], Assembler::sllx_op3, Matcher::_regEncode[src_first], 0x1020 );
1315 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[src_second], Assembler::srl_op3, Matcher::_regEncode[src_second], 0x0000 );
1316 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler:: or_op3, Matcher::_regEncode[tmp], 0, Matcher::_regEncode[src_second] );
1317 #ifndef PRODUCT
1318 } else if( !do_size ) {
1319 if( size != 0 ) st->print("\n\t");
1320 st->print("SLLX R_%s,32,R_%s\t! Move O0-first to O7-high\n\t", OptoReg::regname(src_first), OptoReg::regname(tmp));
1321 st->print("SRL R_%s, 0,R_%s\t! Zero-extend O1\n\t", OptoReg::regname(src_second), OptoReg::regname(src_second));
1322 st->print("OR R_%s,R_%s,R_%s\t! spill",OptoReg::regname(tmp), OptoReg::regname(src_second), OptoReg::regname(dst_first));
1323 #endif
1324 }
1325 return size+12;
1326 }
1327 else if( dst_first == R_I0_num && dst_second == R_I1_num ) {
1328 // returning a long value in I0/I1
1329 // a SpillCopy must be able to target a return instruction's reg_class
1330 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value
1331 // as stored in memory. On a big-endian machine like SPARC, this means that the _second
1332 // operand contains the least significant word of the 64-bit value and vice versa.
1333 OptoReg::Name tdest = dst_first;
1334
1335 if (src_first == dst_first) {
1336 tdest = OptoReg::Name(R_O7_num);
1337 size += 4;
1338 }
1339
1340 if( cbuf ) {
1341 assert( (src_first&1) == 0 && (src_first+1) == src_second, "return value was in an aligned-adjacent 64-bit reg");
1342 // Shift value in upper 32-bits of src to lower 32-bits of I0; move lower 32-bits to I1
1343 // ShrL_reg_imm6
1344 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tdest], Assembler::srlx_op3, Matcher::_regEncode[src_second], 32 | 0x1000 );
1345 // ShrR_reg_imm6 src, 0, dst
1346 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srl_op3, Matcher::_regEncode[src_first], 0x0000 );
1347 if (tdest != dst_first) {
1348 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler::or_op3, 0/*G0*/, 0/*op2*/, Matcher::_regEncode[tdest] );
1349 }
1350 }
1351 #ifndef PRODUCT
1352 else if( !do_size ) {
1353 if( size != 0 ) st->print("\n\t"); // %%%%% !!!!!
1354 st->print("SRLX R_%s,32,R_%s\t! Extract MSW\n\t",OptoReg::regname(src_second),OptoReg::regname(tdest));
1355 st->print("SRL R_%s, 0,R_%s\t! Extract LSW\n\t",OptoReg::regname(src_first),OptoReg::regname(dst_second));
1356 if (tdest != dst_first) {
1357 st->print("MOV R_%s,R_%s\t! spill\n\t", OptoReg::regname(tdest), OptoReg::regname(dst_first));
1358 }
1359 }
1360 #endif // PRODUCT
1361 return size+8;
1362 }
1363 #endif // !_LP64
1364 // Else normal reg-reg copy
1365 assert( src_second != dst_first, "smashed second before evacuating it" );
1366 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::or_op3,0,"MOV ",size, st);
1367 assert( (src_first&1) == 0 && (dst_first&1) == 0, "never move second-halves of int registers" );
1368 // This moves an aligned adjacent pair.
1369 // See if we are done.
1370 if( src_first+1 == src_second && dst_first+1 == dst_second )
1371 return size;
1372 }
1373
1374 // Check for integer store
1375 if( src_first_rc == rc_int && dst_first_rc == rc_stack ) {
1376 int offset = ra_->reg2offset(dst_first);
1377 // Further check for aligned-adjacent pair, so we can use a double store
1378 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1379 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stx_op3,"STX ",size, st);
1380 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stw_op3,"STW ",size, st);
1381 }
1382
1383 // Check for integer load
1384 if( dst_first_rc == rc_int && src_first_rc == rc_stack ) {
1385 int offset = ra_->reg2offset(src_first);
1386 // Further check for aligned-adjacent pair, so we can use a double load
1387 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1388 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldx_op3 ,"LDX ",size, st);
1389 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
1390 }
1391
1392 // Check for float reg-reg copy
1393 if( src_first_rc == rc_float && dst_first_rc == rc_float ) {
1394 // Further check for aligned-adjacent pair, so we can use a double move
1395 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1396 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovd_opf,"FMOVD",size, st);
1397 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovs_opf,"FMOVS",size, st);
1398 }
1399
1400 // Check for float store
1401 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) {
1402 int offset = ra_->reg2offset(dst_first);
1403 // Further check for aligned-adjacent pair, so we can use a double store
1404 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1405 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stdf_op3,"STDF",size, st);
1406 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
1407 }
1408
1409 // Check for float load
1410 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) {
1411 int offset = ra_->reg2offset(src_first);
1412 // Further check for aligned-adjacent pair, so we can use a double load
1413 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1414 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lddf_op3,"LDDF",size, st);
1415 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldf_op3 ,"LDF ",size, st);
1416 }
1417
1418 // --------------------------------------------------------------------
1419 // Check for hi bits still needing moving. Only happens for misaligned
1420 // arguments to native calls.
1421 if( src_second == dst_second )
1422 return size; // Self copy; no move
1423 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" );
1424
1425 #ifndef _LP64
1426 // In the LP64 build, all registers can be moved as aligned/adjacent
1427 // pairs, so there's never any need to move the high bits separately.
1428 // The 32-bit builds have to deal with the 32-bit ABI which can force
1429 // all sorts of silly alignment problems.
1430
1431 // Check for integer reg-reg copy. Hi bits are stuck up in the top
1432 // 32-bits of a 64-bit register, but are needed in low bits of another
1433 // register (else it's a hi-bits-to-hi-bits copy which should have
1434 // happened already as part of a 64-bit move)
1435 if( src_second_rc == rc_int && dst_second_rc == rc_int ) {
1436 assert( (src_second&1)==1, "its the evil O0/O1 native return case" );
1437 assert( (dst_second&1)==0, "should have moved with 1 64-bit move" );
1438 // Shift src_second down to dst_second's low bits.
1439 if( cbuf ) {
1440 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 );
1441 #ifndef PRODUCT
1442 } else if( !do_size ) {
1443 if( size != 0 ) st->print("\n\t");
1444 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(dst_second));
1445 #endif
1446 }
1447 return size+4;
1448 }
1449
1450 // Check for high word integer store. Must down-shift the hi bits
1451 // into a temp register, then fall into the case of storing int bits.
1452 if( src_second_rc == rc_int && dst_second_rc == rc_stack && (src_second&1)==1 ) {
1453 // Shift src_second down to dst_second's low bits.
1454 if( cbuf ) {
1455 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[R_O7_num], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 );
1456 #ifndef PRODUCT
1457 } else if( !do_size ) {
1458 if( size != 0 ) st->print("\n\t");
1459 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(R_O7_num));
1460 #endif
1461 }
1462 size+=4;
1463 src_second = OptoReg::Name(R_O7_num); // Not R_O7H_num!
1464 }
1465
1466 // Check for high word integer load
1467 if( dst_second_rc == rc_int && src_second_rc == rc_stack )
1468 return impl_helper(this,cbuf,ra_,do_size,true ,ra_->reg2offset(src_second),dst_second,Assembler::lduw_op3,"LDUW",size, st);
1469
1470 // Check for high word integer store
1471 if( src_second_rc == rc_int && dst_second_rc == rc_stack )
1472 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stw_op3 ,"STW ",size, st);
1473
1474 // Check for high word float store
1475 if( src_second_rc == rc_float && dst_second_rc == rc_stack )
1476 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stf_op3 ,"STF ",size, st);
1477
1478 #endif // !_LP64
1479
1480 Unimplemented();
1481 }
1482
1483 #ifndef PRODUCT
1484 void MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1485 implementation( NULL, ra_, false, st );
1486 }
1487 #endif
1488
1489 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1490 implementation( &cbuf, ra_, false, NULL );
1491 }
1492
1493 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1494 return implementation( NULL, ra_, true, NULL );
1495 }
1496
1497 //=============================================================================
1498 #ifndef PRODUCT
1499 void MachNopNode::format( PhaseRegAlloc *, outputStream *st ) const {
1500 st->print("NOP \t# %d bytes pad for loops and calls", 4 * _count);
1501 }
1502 #endif
1503
1504 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc * ) const {
1505 MacroAssembler _masm(&cbuf);
1506 for(int i = 0; i < _count; i += 1) {
1507 __ nop();
1508 }
1509 }
1510
1511 uint MachNopNode::size(PhaseRegAlloc *ra_) const {
1512 return 4 * _count;
1513 }
1514
1515
1516 //=============================================================================
1517 #ifndef PRODUCT
1518 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1519 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1520 int reg = ra_->get_reg_first(this);
1521 st->print("LEA [R_SP+#%d+BIAS],%s",offset,Matcher::regName[reg]);
1522 }
1523 #endif
1524
1525 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1526 MacroAssembler _masm(&cbuf);
1527 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()) + STACK_BIAS;
1528 int reg = ra_->get_encode(this);
1529
1530 if (Assembler::is_simm13(offset)) {
1531 __ add(SP, offset, reg_to_register_object(reg));
1532 } else {
1533 __ set(offset, O7);
1534 __ add(SP, O7, reg_to_register_object(reg));
1535 }
1536 }
1537
1538 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1539 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_)
1540 assert(ra_ == ra_->C->regalloc(), "sanity");
1541 return ra_->C->scratch_emit_size(this);
1542 }
1543
1544 //=============================================================================
1545
1546 // emit call stub, compiled java to interpretor
1547 void emit_java_to_interp(CodeBuffer &cbuf ) {
1548
1549 // Stub is fixed up when the corresponding call is converted from calling
1550 // compiled code to calling interpreted code.
1551 // set (empty), G5
1552 // jmp -1
1553
1554 address mark = cbuf.inst_mark(); // get mark within main instrs section
1555
1556 MacroAssembler _masm(&cbuf);
1557
1558 address base =
1559 __ start_a_stub(Compile::MAX_stubs_size);
1560 if (base == NULL) return; // CodeBuffer::expand failed
1561
1562 // static stub relocation stores the instruction address of the call
1563 __ relocate(static_stub_Relocation::spec(mark));
1564
1565 __ set_oop(NULL, reg_to_register_object(Matcher::inline_cache_reg_encode()));
1566
1567 __ set_inst_mark();
1568 AddressLiteral addrlit(-1);
1569 __ JUMP(addrlit, G3, 0);
1570
1571 __ delayed()->nop();
1572
1573 // Update current stubs pointer and restore code_end.
1574 __ end_a_stub();
1575 }
1576
1577 // size of call stub, compiled java to interpretor
1578 uint size_java_to_interp() {
1579 // This doesn't need to be accurate but it must be larger or equal to
1580 // the real size of the stub.
1581 return (NativeMovConstReg::instruction_size + // sethi/setlo;
1582 NativeJump::instruction_size + // sethi; jmp; nop
1583 (TraceJumps ? 20 * BytesPerInstWord : 0) );
1584 }
1585 // relocation entries for call stub, compiled java to interpretor
1586 uint reloc_java_to_interp() {
1587 return 10; // 4 in emit_java_to_interp + 1 in Java_Static_Call
1588 }
1589
1590
1591 //=============================================================================
1592 #ifndef PRODUCT
1593 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1594 st->print_cr("\nUEP:");
1595 #ifdef _LP64
1596 if (UseCompressedOops) {
1597 assert(Universe::heap() != NULL, "java heap should be initialized");
1598 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check - compressed klass");
1599 st->print_cr("\tSLL R_G5,3,R_G5");
1600 if (Universe::narrow_oop_base() != NULL)
1601 st->print_cr("\tADD R_G5,R_G6_heap_base,R_G5");
1602 } else {
1603 st->print_cr("\tLDX [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check");
1604 }
1605 st->print_cr("\tCMP R_G5,R_G3" );
1606 st->print ("\tTne xcc,R_G0+ST_RESERVED_FOR_USER_0+2");
1607 #else // _LP64
1608 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check");
1609 st->print_cr("\tCMP R_G5,R_G3" );
1610 st->print ("\tTne icc,R_G0+ST_RESERVED_FOR_USER_0+2");
1611 #endif // _LP64
1612 }
1613 #endif
1614
1615 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1616 MacroAssembler _masm(&cbuf);
1617 Label L;
1618 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
1619 Register temp_reg = G3;
1620 assert( G5_ic_reg != temp_reg, "conflicting registers" );
1621
1622 // Load klass from receiver
1623 __ load_klass(O0, temp_reg);
1624 // Compare against expected klass
1625 __ cmp(temp_reg, G5_ic_reg);
1626 // Branch to miss code, checks xcc or icc depending
1627 __ trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2);
1628 }
1629
1630 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
1631 return MachNode::size(ra_);
1632 }
1633
1634
1635 //=============================================================================
1636
1637 uint size_exception_handler() {
1638 if (TraceJumps) {
1639 return (400); // just a guess
1640 }
1641 return ( NativeJump::instruction_size ); // sethi;jmp;nop
1642 }
1643
1644 uint size_deopt_handler() {
1645 if (TraceJumps) {
1646 return (400); // just a guess
1647 }
1648 return ( 4+ NativeJump::instruction_size ); // save;sethi;jmp;restore
1649 }
1650
1651 // Emit exception handler code.
1652 int emit_exception_handler(CodeBuffer& cbuf) {
1653 Register temp_reg = G3;
1654 AddressLiteral exception_blob(OptoRuntime::exception_blob()->instructions_begin());
1655 MacroAssembler _masm(&cbuf);
1656
1657 address base =
1658 __ start_a_stub(size_exception_handler());
1659 if (base == NULL) return 0; // CodeBuffer::expand failed
1660
1661 int offset = __ offset();
1662
1663 __ JUMP(exception_blob, temp_reg, 0); // sethi;jmp
1664 __ delayed()->nop();
1665
1666 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
1667
1668 __ end_a_stub();
1669
1670 return offset;
1671 }
1672
1673 int emit_deopt_handler(CodeBuffer& cbuf) {
1674 // Can't use any of the current frame's registers as we may have deopted
1675 // at a poll and everything (including G3) can be live.
1676 Register temp_reg = L0;
1677 AddressLiteral deopt_blob(SharedRuntime::deopt_blob()->unpack());
1678 MacroAssembler _masm(&cbuf);
1679
1680 address base =
1681 __ start_a_stub(size_deopt_handler());
1682 if (base == NULL) return 0; // CodeBuffer::expand failed
1683
1684 int offset = __ offset();
1685 __ save_frame(0);
1686 __ JUMP(deopt_blob, temp_reg, 0); // sethi;jmp
1687 __ delayed()->restore();
1688
1689 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
1690
1691 __ end_a_stub();
1692 return offset;
1693
1694 }
1695
1696 // Given a register encoding, produce a Integer Register object
1697 static Register reg_to_register_object(int register_encoding) {
1698 assert(L5->encoding() == R_L5_enc && G1->encoding() == R_G1_enc, "right coding");
1699 return as_Register(register_encoding);
1700 }
1701
1702 // Given a register encoding, produce a single-precision Float Register object
1703 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding) {
1704 assert(F5->encoding(FloatRegisterImpl::S) == R_F5_enc && F12->encoding(FloatRegisterImpl::S) == R_F12_enc, "right coding");
1705 return as_SingleFloatRegister(register_encoding);
1706 }
1707
1708 // Given a register encoding, produce a double-precision Float Register object
1709 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding) {
1710 assert(F4->encoding(FloatRegisterImpl::D) == R_F4_enc, "right coding");
1711 assert(F32->encoding(FloatRegisterImpl::D) == R_D32_enc, "right coding");
1712 return as_DoubleFloatRegister(register_encoding);
1713 }
1714
1715 const bool Matcher::match_rule_supported(int opcode) {
1716 if (!has_match_rule(opcode))
1717 return false;
1718
1719 switch (opcode) {
1720 case Op_CountLeadingZerosI:
1721 case Op_CountLeadingZerosL:
1722 case Op_CountTrailingZerosI:
1723 case Op_CountTrailingZerosL:
1724 if (!UsePopCountInstruction)
1725 return false;
1726 break;
1727 }
1728
1729 return true; // Per default match rules are supported.
1730 }
1731
1732 int Matcher::regnum_to_fpu_offset(int regnum) {
1733 return regnum - 32; // The FP registers are in the second chunk
1734 }
1735
1736 #ifdef ASSERT
1737 address last_rethrow = NULL; // debugging aid for Rethrow encoding
1738 #endif
1739
1740 // Vector width in bytes
1741 const uint Matcher::vector_width_in_bytes(void) {
1742 return 8;
1743 }
1744
1745 // Vector ideal reg
1746 const uint Matcher::vector_ideal_reg(void) {
1747 return Op_RegD;
1748 }
1749
1750 // USII supports fxtof through the whole range of number, USIII doesn't
1751 const bool Matcher::convL2FSupported(void) {
1752 return VM_Version::has_fast_fxtof();
1753 }
1754
1755 // Is this branch offset short enough that a short branch can be used?
1756 //
1757 // NOTE: If the platform does not provide any short branch variants, then
1758 // this method should return false for offset 0.
1759 bool Matcher::is_short_branch_offset(int rule, int offset) {
1760 return false;
1761 }
1762
1763 const bool Matcher::isSimpleConstant64(jlong value) {
1764 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1765 // Depends on optimizations in MacroAssembler::setx.
1766 int hi = (int)(value >> 32);
1767 int lo = (int)(value & ~0);
1768 return (hi == 0) || (hi == -1) || (lo == 0);
1769 }
1770
1771 // No scaling for the parameter the ClearArray node.
1772 const bool Matcher::init_array_count_is_in_bytes = true;
1773
1774 // Threshold size for cleararray.
1775 const int Matcher::init_array_short_size = 8 * BytesPerLong;
1776
1777 // Should the Matcher clone shifts on addressing modes, expecting them to
1778 // be subsumed into complex addressing expressions or compute them into
1779 // registers? True for Intel but false for most RISCs
1780 const bool Matcher::clone_shift_expressions = false;
1781
1782 // Is it better to copy float constants, or load them directly from memory?
1783 // Intel can load a float constant from a direct address, requiring no
1784 // extra registers. Most RISCs will have to materialize an address into a
1785 // register first, so they would do better to copy the constant from stack.
1786 const bool Matcher::rematerialize_float_constants = false;
1787
1788 // If CPU can load and store mis-aligned doubles directly then no fixup is
1789 // needed. Else we split the double into 2 integer pieces and move it
1790 // piece-by-piece. Only happens when passing doubles into C code as the
1791 // Java calling convention forces doubles to be aligned.
1792 #ifdef _LP64
1793 const bool Matcher::misaligned_doubles_ok = true;
1794 #else
1795 const bool Matcher::misaligned_doubles_ok = false;
1796 #endif
1797
1798 // No-op on SPARC.
1799 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
1800 }
1801
1802 // Advertise here if the CPU requires explicit rounding operations
1803 // to implement the UseStrictFP mode.
1804 const bool Matcher::strict_fp_requires_explicit_rounding = false;
1805
1806 // Do floats take an entire double register or just half?
1807 const bool Matcher::float_in_double = false;
1808
1809 // Do ints take an entire long register or just half?
1810 // Note that we if-def off of _LP64.
1811 // The relevant question is how the int is callee-saved. In _LP64
1812 // the whole long is written but de-opt'ing will have to extract
1813 // the relevant 32 bits, in not-_LP64 only the low 32 bits is written.
1814 #ifdef _LP64
1815 const bool Matcher::int_in_long = true;
1816 #else
1817 const bool Matcher::int_in_long = false;
1818 #endif
1819
1820 // Return whether or not this register is ever used as an argument. This
1821 // function is used on startup to build the trampoline stubs in generateOptoStub.
1822 // Registers not mentioned will be killed by the VM call in the trampoline, and
1823 // arguments in those registers not be available to the callee.
1824 bool Matcher::can_be_java_arg( int reg ) {
1825 // Standard sparc 6 args in registers
1826 if( reg == R_I0_num ||
1827 reg == R_I1_num ||
1828 reg == R_I2_num ||
1829 reg == R_I3_num ||
1830 reg == R_I4_num ||
1831 reg == R_I5_num ) return true;
1832 #ifdef _LP64
1833 // 64-bit builds can pass 64-bit pointers and longs in
1834 // the high I registers
1835 if( reg == R_I0H_num ||
1836 reg == R_I1H_num ||
1837 reg == R_I2H_num ||
1838 reg == R_I3H_num ||
1839 reg == R_I4H_num ||
1840 reg == R_I5H_num ) return true;
1841
1842 if ((UseCompressedOops) && (reg == R_G6_num || reg == R_G6H_num)) {
1843 return true;
1844 }
1845
1846 #else
1847 // 32-bit builds with longs-in-one-entry pass longs in G1 & G4.
1848 // Longs cannot be passed in O regs, because O regs become I regs
1849 // after a 'save' and I regs get their high bits chopped off on
1850 // interrupt.
1851 if( reg == R_G1H_num || reg == R_G1_num ) return true;
1852 if( reg == R_G4H_num || reg == R_G4_num ) return true;
1853 #endif
1854 // A few float args in registers
1855 if( reg >= R_F0_num && reg <= R_F7_num ) return true;
1856
1857 return false;
1858 }
1859
1860 bool Matcher::is_spillable_arg( int reg ) {
1861 return can_be_java_arg(reg);
1862 }
1863
1864 // Register for DIVI projection of divmodI
1865 RegMask Matcher::divI_proj_mask() {
1866 ShouldNotReachHere();
1867 return RegMask();
1868 }
1869
1870 // Register for MODI projection of divmodI
1871 RegMask Matcher::modI_proj_mask() {
1872 ShouldNotReachHere();
1873 return RegMask();
1874 }
1875
1876 // Register for DIVL projection of divmodL
1877 RegMask Matcher::divL_proj_mask() {
1878 ShouldNotReachHere();
1879 return RegMask();
1880 }
1881
1882 // Register for MODL projection of divmodL
1883 RegMask Matcher::modL_proj_mask() {
1884 ShouldNotReachHere();
1885 return RegMask();
1886 }
1887
1888 %}
1889
1890
1891 // The intptr_t operand types, defined by textual substitution.
1892 // (Cf. opto/type.hpp. This lets us avoid many, many other ifdefs.)
1893 #ifdef _LP64
1894 #define immX immL
1895 #define immX13 immL13
1896 #define iRegX iRegL
1897 #define g1RegX g1RegL
1898 #else
1899 #define immX immI
1900 #define immX13 immI13
1901 #define iRegX iRegI
1902 #define g1RegX g1RegI
1903 #endif
1904
1905 //----------ENCODING BLOCK-----------------------------------------------------
1906 // This block specifies the encoding classes used by the compiler to output
1907 // byte streams. Encoding classes are parameterized macros used by
1908 // Machine Instruction Nodes in order to generate the bit encoding of the
1909 // instruction. Operands specify their base encoding interface with the
1910 // interface keyword. There are currently supported four interfaces,
1911 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
1912 // operand to generate a function which returns its register number when
1913 // queried. CONST_INTER causes an operand to generate a function which
1914 // returns the value of the constant when queried. MEMORY_INTER causes an
1915 // operand to generate four functions which return the Base Register, the
1916 // Index Register, the Scale Value, and the Offset Value of the operand when
1917 // queried. COND_INTER causes an operand to generate six functions which
1918 // return the encoding code (ie - encoding bits for the instruction)
1919 // associated with each basic boolean condition for a conditional instruction.
1920 //
1921 // Instructions specify two basic values for encoding. Again, a function
1922 // is available to check if the constant displacement is an oop. They use the
1923 // ins_encode keyword to specify their encoding classes (which must be
1924 // a sequence of enc_class names, and their parameters, specified in
1925 // the encoding block), and they use the
1926 // opcode keyword to specify, in order, their primary, secondary, and
1927 // tertiary opcode. Only the opcode sections which a particular instruction
1928 // needs for encoding need to be specified.
1929 encode %{
1930 enc_class enc_untested %{
1931 #ifdef ASSERT
1932 MacroAssembler _masm(&cbuf);
1933 __ untested("encoding");
1934 #endif
1935 %}
1936
1937 enc_class form3_mem_reg( memory mem, iRegI dst ) %{
1938 emit_form3_mem_reg(cbuf, this, $primary, $tertiary,
1939 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg);
1940 %}
1941
1942 enc_class simple_form3_mem_reg( memory mem, iRegI dst ) %{
1943 emit_form3_mem_reg(cbuf, this, $primary, -1,
1944 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg);
1945 %}
1946
1947 enc_class form3_mem_reg_little( memory mem, iRegI dst) %{
1948 emit_form3_mem_reg_asi(cbuf, this, $primary, -1,
1949 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg, Assembler::ASI_PRIMARY_LITTLE);
1950 %}
1951
1952 enc_class form3_mem_prefetch_read( memory mem ) %{
1953 emit_form3_mem_reg(cbuf, this, $primary, -1,
1954 $mem$$base, $mem$$disp, $mem$$index, 0/*prefetch function many-reads*/);
1955 %}
1956
1957 enc_class form3_mem_prefetch_write( memory mem ) %{
1958 emit_form3_mem_reg(cbuf, this, $primary, -1,
1959 $mem$$base, $mem$$disp, $mem$$index, 2/*prefetch function many-writes*/);
1960 %}
1961
1962 enc_class form3_mem_reg_long_unaligned_marshal( memory mem, iRegL reg ) %{
1963 assert( Assembler::is_simm13($mem$$disp ), "need disp and disp+4" );
1964 assert( Assembler::is_simm13($mem$$disp+4), "need disp and disp+4" );
1965 guarantee($mem$$index == R_G0_enc, "double index?");
1966 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, R_O7_enc );
1967 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg );
1968 emit3_simm13( cbuf, Assembler::arith_op, $reg$$reg, Assembler::sllx_op3, $reg$$reg, 0x1020 );
1969 emit3( cbuf, Assembler::arith_op, $reg$$reg, Assembler::or_op3, $reg$$reg, 0, R_O7_enc );
1970 %}
1971
1972 enc_class form3_mem_reg_double_unaligned( memory mem, RegD_low reg ) %{
1973 assert( Assembler::is_simm13($mem$$disp ), "need disp and disp+4" );
1974 assert( Assembler::is_simm13($mem$$disp+4), "need disp and disp+4" );
1975 guarantee($mem$$index == R_G0_enc, "double index?");
1976 // Load long with 2 instructions
1977 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg+0 );
1978 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, $reg$$reg+1 );
1979 %}
1980
1981 //%%% form3_mem_plus_4_reg is a hack--get rid of it
1982 enc_class form3_mem_plus_4_reg( memory mem, iRegI dst ) %{
1983 guarantee($mem$$disp, "cannot offset a reg-reg operand by 4");
1984 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp + 4, $mem$$index, $dst$$reg);
1985 %}
1986
1987 enc_class form3_g0_rs2_rd_move( iRegI rs2, iRegI rd ) %{
1988 // Encode a reg-reg copy. If it is useless, then empty encoding.
1989 if( $rs2$$reg != $rd$$reg )
1990 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, $rs2$$reg );
1991 %}
1992
1993 // Target lo half of long
1994 enc_class form3_g0_rs2_rd_move_lo( iRegI rs2, iRegL rd ) %{
1995 // Encode a reg-reg copy. If it is useless, then empty encoding.
1996 if( $rs2$$reg != LONG_LO_REG($rd$$reg) )
1997 emit3( cbuf, Assembler::arith_op, LONG_LO_REG($rd$$reg), Assembler::or_op3, 0, 0, $rs2$$reg );
1998 %}
1999
2000 // Source lo half of long
2001 enc_class form3_g0_rs2_rd_move_lo2( iRegL rs2, iRegI rd ) %{
2002 // Encode a reg-reg copy. If it is useless, then empty encoding.
2003 if( LONG_LO_REG($rs2$$reg) != $rd$$reg )
2004 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_LO_REG($rs2$$reg) );
2005 %}
2006
2007 // Target hi half of long
2008 enc_class form3_rs1_rd_copysign_hi( iRegI rs1, iRegL rd ) %{
2009 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 31 );
2010 %}
2011
2012 // Source lo half of long, and leave it sign extended.
2013 enc_class form3_rs1_rd_signextend_lo1( iRegL rs1, iRegI rd ) %{
2014 // Sign extend low half
2015 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 0, 0 );
2016 %}
2017
2018 // Source hi half of long, and leave it sign extended.
2019 enc_class form3_rs1_rd_copy_hi1( iRegL rs1, iRegI rd ) %{
2020 // Shift high half to low half
2021 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::srlx_op3, $rs1$$reg, 32 );
2022 %}
2023
2024 // Source hi half of long
2025 enc_class form3_g0_rs2_rd_move_hi2( iRegL rs2, iRegI rd ) %{
2026 // Encode a reg-reg copy. If it is useless, then empty encoding.
2027 if( LONG_HI_REG($rs2$$reg) != $rd$$reg )
2028 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_HI_REG($rs2$$reg) );
2029 %}
2030
2031 enc_class form3_rs1_rs2_rd( iRegI rs1, iRegI rs2, iRegI rd ) %{
2032 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0, $rs2$$reg );
2033 %}
2034
2035 enc_class enc_to_bool( iRegI src, iRegI dst ) %{
2036 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, 0, 0, $src$$reg );
2037 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::addc_op3 , 0, 0 );
2038 %}
2039
2040 enc_class enc_ltmask( iRegI p, iRegI q, iRegI dst ) %{
2041 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $p$$reg, 0, $q$$reg );
2042 // clear if nothing else is happening
2043 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 0 );
2044 // blt,a,pn done
2045 emit2_19 ( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less, Assembler::bp_op2, Assembler::icc, 0/*predict not taken*/, 2 );
2046 // mov dst,-1 in delay slot
2047 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 );
2048 %}
2049
2050 enc_class form3_rs1_imm5_rd( iRegI rs1, immU5 imm5, iRegI rd ) %{
2051 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $imm5$$constant & 0x1F );
2052 %}
2053
2054 enc_class form3_sd_rs1_imm6_rd( iRegL rs1, immU6 imm6, iRegL rd ) %{
2055 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, ($imm6$$constant & 0x3F) | 0x1000 );
2056 %}
2057
2058 enc_class form3_sd_rs1_rs2_rd( iRegL rs1, iRegI rs2, iRegL rd ) %{
2059 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0x80, $rs2$$reg );
2060 %}
2061
2062 enc_class form3_rs1_simm13_rd( iRegI rs1, immI13 simm13, iRegI rd ) %{
2063 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $simm13$$constant );
2064 %}
2065
2066 enc_class move_return_pc_to_o1() %{
2067 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::add_op3, R_O7_enc, frame::pc_return_offset );
2068 %}
2069
2070 #ifdef _LP64
2071 /* %%% merge with enc_to_bool */
2072 enc_class enc_convP2B( iRegI dst, iRegP src ) %{
2073 MacroAssembler _masm(&cbuf);
2074
2075 Register src_reg = reg_to_register_object($src$$reg);
2076 Register dst_reg = reg_to_register_object($dst$$reg);
2077 __ movr(Assembler::rc_nz, src_reg, 1, dst_reg);
2078 %}
2079 #endif
2080
2081 enc_class enc_cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp ) %{
2082 // (Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)))
2083 MacroAssembler _masm(&cbuf);
2084
2085 Register p_reg = reg_to_register_object($p$$reg);
2086 Register q_reg = reg_to_register_object($q$$reg);
2087 Register y_reg = reg_to_register_object($y$$reg);
2088 Register tmp_reg = reg_to_register_object($tmp$$reg);
2089
2090 __ subcc( p_reg, q_reg, p_reg );
2091 __ add ( p_reg, y_reg, tmp_reg );
2092 __ movcc( Assembler::less, false, Assembler::icc, tmp_reg, p_reg );
2093 %}
2094
2095 enc_class form_d2i_helper(regD src, regF dst) %{
2096 // fcmp %fcc0,$src,$src
2097 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg );
2098 // branch %fcc0 not-nan, predict taken
2099 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2100 // fdtoi $src,$dst
2101 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtoi_opf, $src$$reg );
2102 // fitos $dst,$dst (if nan)
2103 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg );
2104 // clear $dst (if nan)
2105 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg );
2106 // carry on here...
2107 %}
2108
2109 enc_class form_d2l_helper(regD src, regD dst) %{
2110 // fcmp %fcc0,$src,$src check for NAN
2111 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg );
2112 // branch %fcc0 not-nan, predict taken
2113 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2114 // fdtox $src,$dst convert in delay slot
2115 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtox_opf, $src$$reg );
2116 // fxtod $dst,$dst (if nan)
2117 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg );
2118 // clear $dst (if nan)
2119 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg );
2120 // carry on here...
2121 %}
2122
2123 enc_class form_f2i_helper(regF src, regF dst) %{
2124 // fcmps %fcc0,$src,$src
2125 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg );
2126 // branch %fcc0 not-nan, predict taken
2127 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2128 // fstoi $src,$dst
2129 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstoi_opf, $src$$reg );
2130 // fitos $dst,$dst (if nan)
2131 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg );
2132 // clear $dst (if nan)
2133 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg );
2134 // carry on here...
2135 %}
2136
2137 enc_class form_f2l_helper(regF src, regD dst) %{
2138 // fcmps %fcc0,$src,$src
2139 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg );
2140 // branch %fcc0 not-nan, predict taken
2141 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2142 // fstox $src,$dst
2143 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstox_opf, $src$$reg );
2144 // fxtod $dst,$dst (if nan)
2145 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg );
2146 // clear $dst (if nan)
2147 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg );
2148 // carry on here...
2149 %}
2150
2151 enc_class form3_opf_rs2F_rdF(regF rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2152 enc_class form3_opf_rs2F_rdD(regF rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2153 enc_class form3_opf_rs2D_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2154 enc_class form3_opf_rs2D_rdD(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2155
2156 enc_class form3_opf_rs2D_lo_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg+1); %}
2157
2158 enc_class form3_opf_rs2D_hi_rdD_hi(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2159 enc_class form3_opf_rs2D_lo_rdD_lo(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg+1,$primary,0,$tertiary,$rs2$$reg+1); %}
2160
2161 enc_class form3_opf_rs1F_rs2F_rdF( regF rs1, regF rs2, regF rd ) %{
2162 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2163 %}
2164
2165 enc_class form3_opf_rs1D_rs2D_rdD( regD rs1, regD rs2, regD rd ) %{
2166 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2167 %}
2168
2169 enc_class form3_opf_rs1F_rs2F_fcc( regF rs1, regF rs2, flagsRegF fcc ) %{
2170 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2171 %}
2172
2173 enc_class form3_opf_rs1D_rs2D_fcc( regD rs1, regD rs2, flagsRegF fcc ) %{
2174 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2175 %}
2176
2177 enc_class form3_convI2F(regF rs2, regF rd) %{
2178 emit3(cbuf,Assembler::arith_op,$rd$$reg,Assembler::fpop1_op3,0,$secondary,$rs2$$reg);
2179 %}
2180
2181 // Encloding class for traceable jumps
2182 enc_class form_jmpl(g3RegP dest) %{
2183 emit_jmpl(cbuf, $dest$$reg);
2184 %}
2185
2186 enc_class form_jmpl_set_exception_pc(g1RegP dest) %{
2187 emit_jmpl_set_exception_pc(cbuf, $dest$$reg);
2188 %}
2189
2190 enc_class form2_nop() %{
2191 emit_nop(cbuf);
2192 %}
2193
2194 enc_class form2_illtrap() %{
2195 emit_illtrap(cbuf);
2196 %}
2197
2198
2199 // Compare longs and convert into -1, 0, 1.
2200 enc_class cmpl_flag( iRegL src1, iRegL src2, iRegI dst ) %{
2201 // CMP $src1,$src2
2202 emit3( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $src1$$reg, 0, $src2$$reg );
2203 // blt,a,pn done
2204 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less , Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 5 );
2205 // mov dst,-1 in delay slot
2206 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 );
2207 // bgt,a,pn done
2208 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::greater, Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 3 );
2209 // mov dst,1 in delay slot
2210 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 1 );
2211 // CLR $dst
2212 emit3( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3 , 0, 0, 0 );
2213 %}
2214
2215 enc_class enc_PartialSubtypeCheck() %{
2216 MacroAssembler _masm(&cbuf);
2217 __ call(StubRoutines::Sparc::partial_subtype_check(), relocInfo::runtime_call_type);
2218 __ delayed()->nop();
2219 %}
2220
2221 enc_class enc_bp( Label labl, cmpOp cmp, flagsReg cc ) %{
2222 MacroAssembler _masm(&cbuf);
2223 Label &L = *($labl$$label);
2224 Assembler::Predict predict_taken =
2225 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn;
2226
2227 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, L);
2228 __ delayed()->nop();
2229 %}
2230
2231 enc_class enc_bpl( Label labl, cmpOp cmp, flagsRegL cc ) %{
2232 MacroAssembler _masm(&cbuf);
2233 Label &L = *($labl$$label);
2234 Assembler::Predict predict_taken =
2235 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn;
2236
2237 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, L);
2238 __ delayed()->nop();
2239 %}
2240
2241 enc_class enc_bpx( Label labl, cmpOp cmp, flagsRegP cc ) %{
2242 MacroAssembler _masm(&cbuf);
2243 Label &L = *($labl$$label);
2244 Assembler::Predict predict_taken =
2245 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn;
2246
2247 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, L);
2248 __ delayed()->nop();
2249 %}
2250
2251 enc_class enc_fbp( Label labl, cmpOpF cmp, flagsRegF cc ) %{
2252 MacroAssembler _masm(&cbuf);
2253 Label &L = *($labl$$label);
2254 Assembler::Predict predict_taken =
2255 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn;
2256
2257 __ fbp( (Assembler::Condition)($cmp$$cmpcode), false, (Assembler::CC)($cc$$reg), predict_taken, L);
2258 __ delayed()->nop();
2259 %}
2260
2261 enc_class jump_enc( iRegX switch_val, o7RegI table) %{
2262 MacroAssembler _masm(&cbuf);
2263
2264 Register switch_reg = as_Register($switch_val$$reg);
2265 Register table_reg = O7;
2266
2267 address table_base = __ address_table_constant(_index2label);
2268 RelocationHolder rspec = internal_word_Relocation::spec(table_base);
2269
2270 // Move table address into a register.
2271 __ set(table_base, table_reg, rspec);
2272
2273 // Jump to base address + switch value
2274 __ ld_ptr(table_reg, switch_reg, table_reg);
2275 __ jmp(table_reg, G0);
2276 __ delayed()->nop();
2277
2278 %}
2279
2280 enc_class enc_ba( Label labl ) %{
2281 MacroAssembler _masm(&cbuf);
2282 Label &L = *($labl$$label);
2283 __ ba(false, L);
2284 __ delayed()->nop();
2285 %}
2286
2287 enc_class enc_bpr( Label labl, cmpOp_reg cmp, iRegI op1 ) %{
2288 MacroAssembler _masm(&cbuf);
2289 Label &L = *$labl$$label;
2290 Assembler::Predict predict_taken =
2291 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn;
2292
2293 __ bpr( (Assembler::RCondition)($cmp$$cmpcode), false, predict_taken, as_Register($op1$$reg), L);
2294 __ delayed()->nop();
2295 %}
2296
2297 enc_class enc_cmov_reg( cmpOp cmp, iRegI dst, iRegI src, immI pcc) %{
2298 int op = (Assembler::arith_op << 30) |
2299 ($dst$$reg << 25) |
2300 (Assembler::movcc_op3 << 19) |
2301 (1 << 18) | // cc2 bit for 'icc'
2302 ($cmp$$cmpcode << 14) |
2303 (0 << 13) | // select register move
2304 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc' or 'xcc'
2305 ($src$$reg << 0);
2306 *((int*)(cbuf.code_end())) = op;
2307 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
2308 %}
2309
2310 enc_class enc_cmov_imm( cmpOp cmp, iRegI dst, immI11 src, immI pcc ) %{
2311 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits
2312 int op = (Assembler::arith_op << 30) |
2313 ($dst$$reg << 25) |
2314 (Assembler::movcc_op3 << 19) |
2315 (1 << 18) | // cc2 bit for 'icc'
2316 ($cmp$$cmpcode << 14) |
2317 (1 << 13) | // select immediate move
2318 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc'
2319 (simm11 << 0);
2320 *((int*)(cbuf.code_end())) = op;
2321 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
2322 %}
2323
2324 enc_class enc_cmov_reg_f( cmpOpF cmp, iRegI dst, iRegI src, flagsRegF fcc ) %{
2325 int op = (Assembler::arith_op << 30) |
2326 ($dst$$reg << 25) |
2327 (Assembler::movcc_op3 << 19) |
2328 (0 << 18) | // cc2 bit for 'fccX'
2329 ($cmp$$cmpcode << 14) |
2330 (0 << 13) | // select register move
2331 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3
2332 ($src$$reg << 0);
2333 *((int*)(cbuf.code_end())) = op;
2334 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
2335 %}
2336
2337 enc_class enc_cmov_imm_f( cmpOp cmp, iRegI dst, immI11 src, flagsRegF fcc ) %{
2338 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits
2339 int op = (Assembler::arith_op << 30) |
2340 ($dst$$reg << 25) |
2341 (Assembler::movcc_op3 << 19) |
2342 (0 << 18) | // cc2 bit for 'fccX'
2343 ($cmp$$cmpcode << 14) |
2344 (1 << 13) | // select immediate move
2345 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3
2346 (simm11 << 0);
2347 *((int*)(cbuf.code_end())) = op;
2348 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
2349 %}
2350
2351 enc_class enc_cmovf_reg( cmpOp cmp, regD dst, regD src, immI pcc ) %{
2352 int op = (Assembler::arith_op << 30) |
2353 ($dst$$reg << 25) |
2354 (Assembler::fpop2_op3 << 19) |
2355 (0 << 18) |
2356 ($cmp$$cmpcode << 14) |
2357 (1 << 13) | // select register move
2358 ($pcc$$constant << 11) | // cc1-cc0 bits for 'icc' or 'xcc'
2359 ($primary << 5) | // select single, double or quad
2360 ($src$$reg << 0);
2361 *((int*)(cbuf.code_end())) = op;
2362 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
2363 %}
2364
2365 enc_class enc_cmovff_reg( cmpOpF cmp, flagsRegF fcc, regD dst, regD src ) %{
2366 int op = (Assembler::arith_op << 30) |
2367 ($dst$$reg << 25) |
2368 (Assembler::fpop2_op3 << 19) |
2369 (0 << 18) |
2370 ($cmp$$cmpcode << 14) |
2371 ($fcc$$reg << 11) | // cc2-cc0 bits for 'fccX'
2372 ($primary << 5) | // select single, double or quad
2373 ($src$$reg << 0);
2374 *((int*)(cbuf.code_end())) = op;
2375 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
2376 %}
2377
2378 // Used by the MIN/MAX encodings. Same as a CMOV, but
2379 // the condition comes from opcode-field instead of an argument.
2380 enc_class enc_cmov_reg_minmax( iRegI dst, iRegI src ) %{
2381 int op = (Assembler::arith_op << 30) |
2382 ($dst$$reg << 25) |
2383 (Assembler::movcc_op3 << 19) |
2384 (1 << 18) | // cc2 bit for 'icc'
2385 ($primary << 14) |
2386 (0 << 13) | // select register move
2387 (0 << 11) | // cc1, cc0 bits for 'icc'
2388 ($src$$reg << 0);
2389 *((int*)(cbuf.code_end())) = op;
2390 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
2391 %}
2392
2393 enc_class enc_cmov_reg_minmax_long( iRegL dst, iRegL src ) %{
2394 int op = (Assembler::arith_op << 30) |
2395 ($dst$$reg << 25) |
2396 (Assembler::movcc_op3 << 19) |
2397 (6 << 16) | // cc2 bit for 'xcc'
2398 ($primary << 14) |
2399 (0 << 13) | // select register move
2400 (0 << 11) | // cc1, cc0 bits for 'icc'
2401 ($src$$reg << 0);
2402 *((int*)(cbuf.code_end())) = op;
2403 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
2404 %}
2405
2406 // Utility encoding for loading a 64 bit Pointer into a register
2407 // The 64 bit pointer is stored in the generated code stream
2408 enc_class SetPtr( immP src, iRegP rd ) %{
2409 Register dest = reg_to_register_object($rd$$reg);
2410 MacroAssembler _masm(&cbuf);
2411 // [RGV] This next line should be generated from ADLC
2412 if ( _opnds[1]->constant_is_oop() ) {
2413 intptr_t val = $src$$constant;
2414 __ set_oop_constant((jobject)val, dest);
2415 } else { // non-oop pointers, e.g. card mark base, heap top
2416 __ set($src$$constant, dest);
2417 }
2418 %}
2419
2420 enc_class Set13( immI13 src, iRegI rd ) %{
2421 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, $src$$constant );
2422 %}
2423
2424 enc_class SetHi22( immI src, iRegI rd ) %{
2425 emit2_22( cbuf, Assembler::branch_op, $rd$$reg, Assembler::sethi_op2, $src$$constant );
2426 %}
2427
2428 enc_class Set32( immI src, iRegI rd ) %{
2429 MacroAssembler _masm(&cbuf);
2430 __ set($src$$constant, reg_to_register_object($rd$$reg));
2431 %}
2432
2433 enc_class SetNull( iRegI rd ) %{
2434 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0 );
2435 %}
2436
2437 enc_class call_epilog %{
2438 if( VerifyStackAtCalls ) {
2439 MacroAssembler _masm(&cbuf);
2440 int framesize = ra_->C->frame_slots() << LogBytesPerInt;
2441 Register temp_reg = G3;
2442 __ add(SP, framesize, temp_reg);
2443 __ cmp(temp_reg, FP);
2444 __ breakpoint_trap(Assembler::notEqual, Assembler::ptr_cc);
2445 }
2446 %}
2447
2448 // Long values come back from native calls in O0:O1 in the 32-bit VM, copy the value
2449 // to G1 so the register allocator will not have to deal with the misaligned register
2450 // pair.
2451 enc_class adjust_long_from_native_call %{
2452 #ifndef _LP64
2453 if (returns_long()) {
2454 // sllx O0,32,O0
2455 emit3_simm13( cbuf, Assembler::arith_op, R_O0_enc, Assembler::sllx_op3, R_O0_enc, 0x1020 );
2456 // srl O1,0,O1
2457 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::srl_op3, R_O1_enc, 0x0000 );
2458 // or O0,O1,G1
2459 emit3 ( cbuf, Assembler::arith_op, R_G1_enc, Assembler:: or_op3, R_O0_enc, 0, R_O1_enc );
2460 }
2461 #endif
2462 %}
2463
2464 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime
2465 // CALL directly to the runtime
2466 // The user of this is responsible for ensuring that R_L7 is empty (killed).
2467 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type,
2468 /*preserve_g2=*/true, /*force far call*/true);
2469 %}
2470
2471 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL
2472 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
2473 // who we intended to call.
2474 if ( !_method ) {
2475 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type);
2476 } else if (_optimized_virtual) {
2477 emit_call_reloc(cbuf, $meth$$method, relocInfo::opt_virtual_call_type);
2478 } else {
2479 emit_call_reloc(cbuf, $meth$$method, relocInfo::static_call_type);
2480 }
2481 if( _method ) { // Emit stub for static call
2482 emit_java_to_interp(cbuf);
2483 }
2484 %}
2485
2486 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL
2487 MacroAssembler _masm(&cbuf);
2488 __ set_inst_mark();
2489 int vtable_index = this->_vtable_index;
2490 // MachCallDynamicJavaNode::ret_addr_offset uses this same test
2491 if (vtable_index < 0) {
2492 // must be invalid_vtable_index, not nonvirtual_vtable_index
2493 assert(vtable_index == methodOopDesc::invalid_vtable_index, "correct sentinel value");
2494 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
2495 assert(G5_ic_reg == G5_inline_cache_reg, "G5_inline_cache_reg used in assemble_ic_buffer_code()");
2496 assert(G5_ic_reg == G5_megamorphic_method, "G5_megamorphic_method used in megamorphic call stub");
2497 // !!!!!
2498 // Generate "set 0x01, R_G5", placeholder instruction to load oop-info
2499 // emit_call_dynamic_prologue( cbuf );
2500 __ set_oop((jobject)Universe::non_oop_word(), G5_ic_reg);
2501
2502 address virtual_call_oop_addr = __ inst_mark();
2503 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
2504 // who we intended to call.
2505 __ relocate(virtual_call_Relocation::spec(virtual_call_oop_addr));
2506 emit_call_reloc(cbuf, $meth$$method, relocInfo::none);
2507 } else {
2508 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
2509 // Just go thru the vtable
2510 // get receiver klass (receiver already checked for non-null)
2511 // If we end up going thru a c2i adapter interpreter expects method in G5
2512 int off = __ offset();
2513 __ load_klass(O0, G3_scratch);
2514 int klass_load_size;
2515 if (UseCompressedOops) {
2516 assert(Universe::heap() != NULL, "java heap should be initialized");
2517 if (Universe::narrow_oop_base() == NULL)
2518 klass_load_size = 2*BytesPerInstWord;
2519 else
2520 klass_load_size = 3*BytesPerInstWord;
2521 } else {
2522 klass_load_size = 1*BytesPerInstWord;
2523 }
2524 int entry_offset = instanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size();
2525 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes();
2526 if( __ is_simm13(v_off) ) {
2527 __ ld_ptr(G3, v_off, G5_method);
2528 } else {
2529 // Generate 2 instructions
2530 __ Assembler::sethi(v_off & ~0x3ff, G5_method);
2531 __ or3(G5_method, v_off & 0x3ff, G5_method);
2532 // ld_ptr, set_hi, set
2533 assert(__ offset() - off == klass_load_size + 2*BytesPerInstWord,
2534 "Unexpected instruction size(s)");
2535 __ ld_ptr(G3, G5_method, G5_method);
2536 }
2537 // NOTE: for vtable dispatches, the vtable entry will never be null.
2538 // However it may very well end up in handle_wrong_method if the
2539 // method is abstract for the particular class.
2540 __ ld_ptr(G5_method, in_bytes(methodOopDesc::from_compiled_offset()), G3_scratch);
2541 // jump to target (either compiled code or c2iadapter)
2542 __ jmpl(G3_scratch, G0, O7);
2543 __ delayed()->nop();
2544 }
2545 %}
2546
2547 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL
2548 MacroAssembler _masm(&cbuf);
2549
2550 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
2551 Register temp_reg = G3; // caller must kill G3! We cannot reuse G5_ic_reg here because
2552 // we might be calling a C2I adapter which needs it.
2553
2554 assert(temp_reg != G5_ic_reg, "conflicting registers");
2555 // Load nmethod
2556 __ ld_ptr(G5_ic_reg, in_bytes(methodOopDesc::from_compiled_offset()), temp_reg);
2557
2558 // CALL to compiled java, indirect the contents of G3
2559 __ set_inst_mark();
2560 __ callr(temp_reg, G0);
2561 __ delayed()->nop();
2562 %}
2563
2564 enc_class idiv_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst) %{
2565 MacroAssembler _masm(&cbuf);
2566 Register Rdividend = reg_to_register_object($src1$$reg);
2567 Register Rdivisor = reg_to_register_object($src2$$reg);
2568 Register Rresult = reg_to_register_object($dst$$reg);
2569
2570 __ sra(Rdivisor, 0, Rdivisor);
2571 __ sra(Rdividend, 0, Rdividend);
2572 __ sdivx(Rdividend, Rdivisor, Rresult);
2573 %}
2574
2575 enc_class idiv_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst) %{
2576 MacroAssembler _masm(&cbuf);
2577
2578 Register Rdividend = reg_to_register_object($src1$$reg);
2579 int divisor = $imm$$constant;
2580 Register Rresult = reg_to_register_object($dst$$reg);
2581
2582 __ sra(Rdividend, 0, Rdividend);
2583 __ sdivx(Rdividend, divisor, Rresult);
2584 %}
2585
2586 enc_class enc_mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2) %{
2587 MacroAssembler _masm(&cbuf);
2588 Register Rsrc1 = reg_to_register_object($src1$$reg);
2589 Register Rsrc2 = reg_to_register_object($src2$$reg);
2590 Register Rdst = reg_to_register_object($dst$$reg);
2591
2592 __ sra( Rsrc1, 0, Rsrc1 );
2593 __ sra( Rsrc2, 0, Rsrc2 );
2594 __ mulx( Rsrc1, Rsrc2, Rdst );
2595 __ srlx( Rdst, 32, Rdst );
2596 %}
2597
2598 enc_class irem_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst, o7RegL scratch) %{
2599 MacroAssembler _masm(&cbuf);
2600 Register Rdividend = reg_to_register_object($src1$$reg);
2601 Register Rdivisor = reg_to_register_object($src2$$reg);
2602 Register Rresult = reg_to_register_object($dst$$reg);
2603 Register Rscratch = reg_to_register_object($scratch$$reg);
2604
2605 assert(Rdividend != Rscratch, "");
2606 assert(Rdivisor != Rscratch, "");
2607
2608 __ sra(Rdividend, 0, Rdividend);
2609 __ sra(Rdivisor, 0, Rdivisor);
2610 __ sdivx(Rdividend, Rdivisor, Rscratch);
2611 __ mulx(Rscratch, Rdivisor, Rscratch);
2612 __ sub(Rdividend, Rscratch, Rresult);
2613 %}
2614
2615 enc_class irem_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst, o7RegL scratch) %{
2616 MacroAssembler _masm(&cbuf);
2617
2618 Register Rdividend = reg_to_register_object($src1$$reg);
2619 int divisor = $imm$$constant;
2620 Register Rresult = reg_to_register_object($dst$$reg);
2621 Register Rscratch = reg_to_register_object($scratch$$reg);
2622
2623 assert(Rdividend != Rscratch, "");
2624
2625 __ sra(Rdividend, 0, Rdividend);
2626 __ sdivx(Rdividend, divisor, Rscratch);
2627 __ mulx(Rscratch, divisor, Rscratch);
2628 __ sub(Rdividend, Rscratch, Rresult);
2629 %}
2630
2631 enc_class fabss (sflt_reg dst, sflt_reg src) %{
2632 MacroAssembler _masm(&cbuf);
2633
2634 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2635 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2636
2637 __ fabs(FloatRegisterImpl::S, Fsrc, Fdst);
2638 %}
2639
2640 enc_class fabsd (dflt_reg dst, dflt_reg src) %{
2641 MacroAssembler _masm(&cbuf);
2642
2643 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2644 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2645
2646 __ fabs(FloatRegisterImpl::D, Fsrc, Fdst);
2647 %}
2648
2649 enc_class fnegd (dflt_reg dst, dflt_reg src) %{
2650 MacroAssembler _masm(&cbuf);
2651
2652 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2653 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2654
2655 __ fneg(FloatRegisterImpl::D, Fsrc, Fdst);
2656 %}
2657
2658 enc_class fsqrts (sflt_reg dst, sflt_reg src) %{
2659 MacroAssembler _masm(&cbuf);
2660
2661 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2662 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2663
2664 __ fsqrt(FloatRegisterImpl::S, Fsrc, Fdst);
2665 %}
2666
2667 enc_class fsqrtd (dflt_reg dst, dflt_reg src) %{
2668 MacroAssembler _masm(&cbuf);
2669
2670 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2671 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2672
2673 __ fsqrt(FloatRegisterImpl::D, Fsrc, Fdst);
2674 %}
2675
2676 enc_class fmovs (dflt_reg dst, dflt_reg src) %{
2677 MacroAssembler _masm(&cbuf);
2678
2679 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2680 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2681
2682 __ fmov(FloatRegisterImpl::S, Fsrc, Fdst);
2683 %}
2684
2685 enc_class fmovd (dflt_reg dst, dflt_reg src) %{
2686 MacroAssembler _masm(&cbuf);
2687
2688 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2689 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2690
2691 __ fmov(FloatRegisterImpl::D, Fsrc, Fdst);
2692 %}
2693
2694 enc_class Fast_Lock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{
2695 MacroAssembler _masm(&cbuf);
2696
2697 Register Roop = reg_to_register_object($oop$$reg);
2698 Register Rbox = reg_to_register_object($box$$reg);
2699 Register Rscratch = reg_to_register_object($scratch$$reg);
2700 Register Rmark = reg_to_register_object($scratch2$$reg);
2701
2702 assert(Roop != Rscratch, "");
2703 assert(Roop != Rmark, "");
2704 assert(Rbox != Rscratch, "");
2705 assert(Rbox != Rmark, "");
2706
2707 __ compiler_lock_object(Roop, Rmark, Rbox, Rscratch, _counters, UseBiasedLocking && !UseOptoBiasInlining);
2708 %}
2709
2710 enc_class Fast_Unlock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{
2711 MacroAssembler _masm(&cbuf);
2712
2713 Register Roop = reg_to_register_object($oop$$reg);
2714 Register Rbox = reg_to_register_object($box$$reg);
2715 Register Rscratch = reg_to_register_object($scratch$$reg);
2716 Register Rmark = reg_to_register_object($scratch2$$reg);
2717
2718 assert(Roop != Rscratch, "");
2719 assert(Roop != Rmark, "");
2720 assert(Rbox != Rscratch, "");
2721 assert(Rbox != Rmark, "");
2722
2723 __ compiler_unlock_object(Roop, Rmark, Rbox, Rscratch, UseBiasedLocking && !UseOptoBiasInlining);
2724 %}
2725
2726 enc_class enc_cas( iRegP mem, iRegP old, iRegP new ) %{
2727 MacroAssembler _masm(&cbuf);
2728 Register Rmem = reg_to_register_object($mem$$reg);
2729 Register Rold = reg_to_register_object($old$$reg);
2730 Register Rnew = reg_to_register_object($new$$reg);
2731
2732 // casx_under_lock picks 1 of 3 encodings:
2733 // For 32-bit pointers you get a 32-bit CAS
2734 // For 64-bit pointers you get a 64-bit CASX
2735 __ casn(Rmem, Rold, Rnew); // Swap(*Rmem,Rnew) if *Rmem == Rold
2736 __ cmp( Rold, Rnew );
2737 %}
2738
2739 enc_class enc_casx( iRegP mem, iRegL old, iRegL new) %{
2740 Register Rmem = reg_to_register_object($mem$$reg);
2741 Register Rold = reg_to_register_object($old$$reg);
2742 Register Rnew = reg_to_register_object($new$$reg);
2743
2744 MacroAssembler _masm(&cbuf);
2745 __ mov(Rnew, O7);
2746 __ casx(Rmem, Rold, O7);
2747 __ cmp( Rold, O7 );
2748 %}
2749
2750 // raw int cas, used for compareAndSwap
2751 enc_class enc_casi( iRegP mem, iRegL old, iRegL new) %{
2752 Register Rmem = reg_to_register_object($mem$$reg);
2753 Register Rold = reg_to_register_object($old$$reg);
2754 Register Rnew = reg_to_register_object($new$$reg);
2755
2756 MacroAssembler _masm(&cbuf);
2757 __ mov(Rnew, O7);
2758 __ cas(Rmem, Rold, O7);
2759 __ cmp( Rold, O7 );
2760 %}
2761
2762 enc_class enc_lflags_ne_to_boolean( iRegI res ) %{
2763 Register Rres = reg_to_register_object($res$$reg);
2764
2765 MacroAssembler _masm(&cbuf);
2766 __ mov(1, Rres);
2767 __ movcc( Assembler::notEqual, false, Assembler::xcc, G0, Rres );
2768 %}
2769
2770 enc_class enc_iflags_ne_to_boolean( iRegI res ) %{
2771 Register Rres = reg_to_register_object($res$$reg);
2772
2773 MacroAssembler _masm(&cbuf);
2774 __ mov(1, Rres);
2775 __ movcc( Assembler::notEqual, false, Assembler::icc, G0, Rres );
2776 %}
2777
2778 enc_class floating_cmp ( iRegP dst, regF src1, regF src2 ) %{
2779 MacroAssembler _masm(&cbuf);
2780 Register Rdst = reg_to_register_object($dst$$reg);
2781 FloatRegister Fsrc1 = $primary ? reg_to_SingleFloatRegister_object($src1$$reg)
2782 : reg_to_DoubleFloatRegister_object($src1$$reg);
2783 FloatRegister Fsrc2 = $primary ? reg_to_SingleFloatRegister_object($src2$$reg)
2784 : reg_to_DoubleFloatRegister_object($src2$$reg);
2785
2786 // Convert condition code fcc0 into -1,0,1; unordered reports less-than (-1)
2787 __ float_cmp( $primary, -1, Fsrc1, Fsrc2, Rdst);
2788 %}
2789
2790 enc_class LdImmL (immL src, iRegL dst, o7RegL tmp) %{ // Load Immediate
2791 MacroAssembler _masm(&cbuf);
2792 Register dest = reg_to_register_object($dst$$reg);
2793 Register temp = reg_to_register_object($tmp$$reg);
2794 __ set64( $src$$constant, dest, temp );
2795 %}
2796
2797 enc_class LdReplImmI(immI src, regD dst, o7RegP tmp, int count, int width) %{
2798 // Load a constant replicated "count" times with width "width"
2799 int bit_width = $width$$constant * 8;
2800 jlong elt_val = $src$$constant;
2801 elt_val &= (((jlong)1) << bit_width) - 1; // mask off sign bits
2802 jlong val = elt_val;
2803 for (int i = 0; i < $count$$constant - 1; i++) {
2804 val <<= bit_width;
2805 val |= elt_val;
2806 }
2807 jdouble dval = *(jdouble*)&val; // coerce to double type
2808 MacroAssembler _masm(&cbuf);
2809 address double_address = __ double_constant(dval);
2810 RelocationHolder rspec = internal_word_Relocation::spec(double_address);
2811 AddressLiteral addrlit(double_address, rspec);
2812
2813 __ sethi(addrlit, $tmp$$Register);
2814 // XXX This is a quick fix for 6833573.
2815 //__ ldf(FloatRegisterImpl::D, $tmp$$Register, addrlit.low10(), $dst$$FloatRegister, rspec);
2816 __ ldf(FloatRegisterImpl::D, $tmp$$Register, addrlit.low10(), as_DoubleFloatRegister($dst$$reg), rspec);
2817 %}
2818
2819 // Compiler ensures base is doubleword aligned and cnt is count of doublewords
2820 enc_class enc_Clear_Array(iRegX cnt, iRegP base, iRegX temp) %{
2821 MacroAssembler _masm(&cbuf);
2822 Register nof_bytes_arg = reg_to_register_object($cnt$$reg);
2823 Register nof_bytes_tmp = reg_to_register_object($temp$$reg);
2824 Register base_pointer_arg = reg_to_register_object($base$$reg);
2825
2826 Label loop;
2827 __ mov(nof_bytes_arg, nof_bytes_tmp);
2828
2829 // Loop and clear, walking backwards through the array.
2830 // nof_bytes_tmp (if >0) is always the number of bytes to zero
2831 __ bind(loop);
2832 __ deccc(nof_bytes_tmp, 8);
2833 __ br(Assembler::greaterEqual, true, Assembler::pt, loop);
2834 __ delayed()-> stx(G0, base_pointer_arg, nof_bytes_tmp);
2835 // %%%% this mini-loop must not cross a cache boundary!
2836 %}
2837
2838
2839 enc_class enc_String_Compare(o0RegP str1, o1RegP str2, g3RegP tmp1, g4RegP tmp2, notemp_iRegI result) %{
2840 Label Ldone, Lloop;
2841 MacroAssembler _masm(&cbuf);
2842
2843 Register str1_reg = reg_to_register_object($str1$$reg);
2844 Register str2_reg = reg_to_register_object($str2$$reg);
2845 Register tmp1_reg = reg_to_register_object($tmp1$$reg);
2846 Register tmp2_reg = reg_to_register_object($tmp2$$reg);
2847 Register result_reg = reg_to_register_object($result$$reg);
2848
2849 // Get the first character position in both strings
2850 // [8] char array, [12] offset, [16] count
2851 int value_offset = java_lang_String:: value_offset_in_bytes();
2852 int offset_offset = java_lang_String::offset_offset_in_bytes();
2853 int count_offset = java_lang_String:: count_offset_in_bytes();
2854
2855 // load str1 (jchar*) base address into tmp1_reg
2856 __ load_heap_oop(str1_reg, value_offset, tmp1_reg);
2857 __ ld(str1_reg, offset_offset, result_reg);
2858 __ add(tmp1_reg, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp1_reg);
2859 __ ld(str1_reg, count_offset, str1_reg); // hoisted
2860 __ sll(result_reg, exact_log2(sizeof(jchar)), result_reg);
2861 __ load_heap_oop(str2_reg, value_offset, tmp2_reg); // hoisted
2862 __ add(result_reg, tmp1_reg, tmp1_reg);
2863
2864 // load str2 (jchar*) base address into tmp2_reg
2865 // __ ld_ptr(str2_reg, value_offset, tmp2_reg); // hoisted
2866 __ ld(str2_reg, offset_offset, result_reg);
2867 __ add(tmp2_reg, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp2_reg);
2868 __ ld(str2_reg, count_offset, str2_reg); // hoisted
2869 __ sll(result_reg, exact_log2(sizeof(jchar)), result_reg);
2870 __ subcc(str1_reg, str2_reg, O7); // hoisted
2871 __ add(result_reg, tmp2_reg, tmp2_reg);
2872
2873 // Compute the minimum of the string lengths(str1_reg) and the
2874 // difference of the string lengths (stack)
2875
2876 // discard string base pointers, after loading up the lengths
2877 // __ ld(str1_reg, count_offset, str1_reg); // hoisted
2878 // __ ld(str2_reg, count_offset, str2_reg); // hoisted
2879
2880 // See if the lengths are different, and calculate min in str1_reg.
2881 // Stash diff in O7 in case we need it for a tie-breaker.
2882 Label Lskip;
2883 // __ subcc(str1_reg, str2_reg, O7); // hoisted
2884 __ sll(str1_reg, exact_log2(sizeof(jchar)), str1_reg); // scale the limit
2885 __ br(Assembler::greater, true, Assembler::pt, Lskip);
2886 // str2 is shorter, so use its count:
2887 __ delayed()->sll(str2_reg, exact_log2(sizeof(jchar)), str1_reg); // scale the limit
2888 __ bind(Lskip);
2889
2890 // reallocate str1_reg, str2_reg, result_reg
2891 // Note: limit_reg holds the string length pre-scaled by 2
2892 Register limit_reg = str1_reg;
2893 Register chr2_reg = str2_reg;
2894 Register chr1_reg = result_reg;
2895 // tmp{12} are the base pointers
2896
2897 // Is the minimum length zero?
2898 __ cmp(limit_reg, (int)(0 * sizeof(jchar))); // use cast to resolve overloading ambiguity
2899 __ br(Assembler::equal, true, Assembler::pn, Ldone);
2900 __ delayed()->mov(O7, result_reg); // result is difference in lengths
2901
2902 // Load first characters
2903 __ lduh(tmp1_reg, 0, chr1_reg);
2904 __ lduh(tmp2_reg, 0, chr2_reg);
2905
2906 // Compare first characters
2907 __ subcc(chr1_reg, chr2_reg, chr1_reg);
2908 __ br(Assembler::notZero, false, Assembler::pt, Ldone);
2909 assert(chr1_reg == result_reg, "result must be pre-placed");
2910 __ delayed()->nop();
2911
2912 {
2913 // Check after comparing first character to see if strings are equivalent
2914 Label LSkip2;
2915 // Check if the strings start at same location
2916 __ cmp(tmp1_reg, tmp2_reg);
2917 __ brx(Assembler::notEqual, true, Assembler::pt, LSkip2);
2918 __ delayed()->nop();
2919
2920 // Check if the length difference is zero (in O7)
2921 __ cmp(G0, O7);
2922 __ br(Assembler::equal, true, Assembler::pn, Ldone);
2923 __ delayed()->mov(G0, result_reg); // result is zero
2924
2925 // Strings might not be equal
2926 __ bind(LSkip2);
2927 }
2928
2929 __ subcc(limit_reg, 1 * sizeof(jchar), chr1_reg);
2930 __ br(Assembler::equal, true, Assembler::pn, Ldone);
2931 __ delayed()->mov(O7, result_reg); // result is difference in lengths
2932
2933 // Shift tmp1_reg and tmp2_reg to the end of the arrays, negate limit
2934 __ add(tmp1_reg, limit_reg, tmp1_reg);
2935 __ add(tmp2_reg, limit_reg, tmp2_reg);
2936 __ neg(chr1_reg, limit_reg); // limit = -(limit-2)
2937
2938 // Compare the rest of the characters
2939 __ lduh(tmp1_reg, limit_reg, chr1_reg);
2940 __ bind(Lloop);
2941 // __ lduh(tmp1_reg, limit_reg, chr1_reg); // hoisted
2942 __ lduh(tmp2_reg, limit_reg, chr2_reg);
2943 __ subcc(chr1_reg, chr2_reg, chr1_reg);
2944 __ br(Assembler::notZero, false, Assembler::pt, Ldone);
2945 assert(chr1_reg == result_reg, "result must be pre-placed");
2946 __ delayed()->inccc(limit_reg, sizeof(jchar));
2947 // annul LDUH if branch is not taken to prevent access past end of string
2948 __ br(Assembler::notZero, true, Assembler::pt, Lloop);
2949 __ delayed()->lduh(tmp1_reg, limit_reg, chr1_reg); // hoisted
2950
2951 // If strings are equal up to min length, return the length difference.
2952 __ mov(O7, result_reg);
2953
2954 // Otherwise, return the difference between the first mismatched chars.
2955 __ bind(Ldone);
2956 %}
2957
2958 enc_class enc_String_Equals(o0RegP str1, o1RegP str2, g3RegP tmp1, g4RegP tmp2, notemp_iRegI result) %{
2959 Label Lword, Lword_loop, Lpost_word, Lchar, Lchar_loop, Ldone;
2960 MacroAssembler _masm(&cbuf);
2961
2962 Register str1_reg = reg_to_register_object($str1$$reg);
2963 Register str2_reg = reg_to_register_object($str2$$reg);
2964 Register tmp1_reg = reg_to_register_object($tmp1$$reg);
2965 Register tmp2_reg = reg_to_register_object($tmp2$$reg);
2966 Register result_reg = reg_to_register_object($result$$reg);
2967
2968 // Get the first character position in both strings
2969 // [8] char array, [12] offset, [16] count
2970 int value_offset = java_lang_String:: value_offset_in_bytes();
2971 int offset_offset = java_lang_String::offset_offset_in_bytes();
2972 int count_offset = java_lang_String:: count_offset_in_bytes();
2973
2974 // load str1 (jchar*) base address into tmp1_reg
2975 __ load_heap_oop(Address(str1_reg, value_offset), tmp1_reg);
2976 __ ld(Address(str1_reg, offset_offset), result_reg);
2977 __ add(tmp1_reg, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp1_reg);
2978 __ ld(Address(str1_reg, count_offset), str1_reg); // hoisted
2979 __ sll(result_reg, exact_log2(sizeof(jchar)), result_reg);
2980 __ load_heap_oop(Address(str2_reg, value_offset), tmp2_reg); // hoisted
2981 __ add(result_reg, tmp1_reg, tmp1_reg);
2982
2983 // load str2 (jchar*) base address into tmp2_reg
2984 // __ ld_ptr(Address(str2_reg, value_offset), tmp2_reg); // hoisted
2985 __ ld(Address(str2_reg, offset_offset), result_reg);
2986 __ add(tmp2_reg, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp2_reg);
2987 __ ld(Address(str2_reg, count_offset), str2_reg); // hoisted
2988 __ sll(result_reg, exact_log2(sizeof(jchar)), result_reg);
2989 __ cmp(str1_reg, str2_reg); // hoisted
2990 __ add(result_reg, tmp2_reg, tmp2_reg);
2991
2992 __ sll(str1_reg, exact_log2(sizeof(jchar)), str1_reg);
2993 __ br(Assembler::notEqual, true, Assembler::pt, Ldone);
2994 __ delayed()->mov(G0, result_reg); // not equal
2995
2996 __ br_zero(Assembler::equal, true, Assembler::pn, str1_reg, Ldone);
2997 __ delayed()->add(G0, 1, result_reg); //equals
2998
2999 __ cmp(tmp1_reg, tmp2_reg); //same string ?
3000 __ brx(Assembler::equal, true, Assembler::pn, Ldone);
3001 __ delayed()->add(G0, 1, result_reg);
3002
3003 //rename registers
3004 Register limit_reg = str1_reg;
3005 Register chr2_reg = str2_reg;
3006 Register chr1_reg = result_reg;
3007 // tmp{12} are the base pointers
3008
3009 //check for alignment and position the pointers to the ends
3010 __ or3(tmp1_reg, tmp2_reg, chr1_reg);
3011 __ andcc(chr1_reg, 0x3, chr1_reg); // notZero means at least one not 4-byte aligned
3012 __ br(Assembler::notZero, false, Assembler::pn, Lchar);
3013 __ delayed()->nop();
3014
3015 __ bind(Lword);
3016 __ and3(limit_reg, 0x2, O7); //remember the remainder (either 0 or 2)
3017 __ andn(limit_reg, 0x3, limit_reg);
3018 __ br_zero(Assembler::zero, false, Assembler::pn, limit_reg, Lpost_word);
3019 __ delayed()->nop();
3020
3021 __ add(tmp1_reg, limit_reg, tmp1_reg);
3022 __ add(tmp2_reg, limit_reg, tmp2_reg);
3023 __ neg(limit_reg);
3024
3025 __ lduw(tmp1_reg, limit_reg, chr1_reg);
3026 __ bind(Lword_loop);
3027 __ lduw(tmp2_reg, limit_reg, chr2_reg);
3028 __ cmp(chr1_reg, chr2_reg);
3029 __ br(Assembler::notEqual, true, Assembler::pt, Ldone);
3030 __ delayed()->mov(G0, result_reg);
3031 __ inccc(limit_reg, 2*sizeof(jchar));
3032 // annul LDUW if branch i s not taken to prevent access past end of string
3033 __ br(Assembler::notZero, true, Assembler::pt, Lword_loop); //annul on taken
3034 __ delayed()->lduw(tmp1_reg, limit_reg, chr1_reg); // hoisted
3035
3036 __ bind(Lpost_word);
3037 __ br_zero(Assembler::zero, true, Assembler::pt, O7, Ldone);
3038 __ delayed()->add(G0, 1, result_reg);
3039
3040 __ lduh(tmp1_reg, 0, chr1_reg);
3041 __ lduh(tmp2_reg, 0, chr2_reg);
3042 __ cmp (chr1_reg, chr2_reg);
3043 __ br(Assembler::notEqual, true, Assembler::pt, Ldone);
3044 __ delayed()->mov(G0, result_reg);
3045 __ ba(false,Ldone);
3046 __ delayed()->add(G0, 1, result_reg);
3047
3048 __ bind(Lchar);
3049 __ add(tmp1_reg, limit_reg, tmp1_reg);
3050 __ add(tmp2_reg, limit_reg, tmp2_reg);
3051 __ neg(limit_reg); //negate count
3052
3053 __ lduh(tmp1_reg, limit_reg, chr1_reg);
3054 __ bind(Lchar_loop);
3055 __ lduh(tmp2_reg, limit_reg, chr2_reg);
3056 __ cmp(chr1_reg, chr2_reg);
3057 __ br(Assembler::notEqual, true, Assembler::pt, Ldone);
3058 __ delayed()->mov(G0, result_reg); //not equal
3059 __ inccc(limit_reg, sizeof(jchar));
3060 // annul LDUH if branch is not taken to prevent access past end of string
3061 __ br(Assembler::notZero, true, Assembler::pt, Lchar_loop); //annul on taken
3062 __ delayed()->lduh(tmp1_reg, limit_reg, chr1_reg); // hoisted
3063
3064 __ add(G0, 1, result_reg); //equal
3065
3066 __ bind(Ldone);
3067 %}
3068
3069 enc_class enc_Array_Equals(o0RegP ary1, o1RegP ary2, g3RegP tmp1, g4RegP tmp2, notemp_iRegI result) %{
3070 Label Lvector, Ldone, Lloop;
3071 MacroAssembler _masm(&cbuf);
3072
3073 Register ary1_reg = reg_to_register_object($ary1$$reg);
3074 Register ary2_reg = reg_to_register_object($ary2$$reg);
3075 Register tmp1_reg = reg_to_register_object($tmp1$$reg);
3076 Register tmp2_reg = reg_to_register_object($tmp2$$reg);
3077 Register result_reg = reg_to_register_object($result$$reg);
3078
3079 int length_offset = arrayOopDesc::length_offset_in_bytes();
3080 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR);
3081
3082 // return true if the same array
3083 __ cmp(ary1_reg, ary2_reg);
3084 __ br(Assembler::equal, true, Assembler::pn, Ldone);
3085 __ delayed()->add(G0, 1, result_reg); // equal
3086
3087 __ br_null(ary1_reg, true, Assembler::pn, Ldone);
3088 __ delayed()->mov(G0, result_reg); // not equal
3089
3090 __ br_null(ary2_reg, true, Assembler::pn, Ldone);
3091 __ delayed()->mov(G0, result_reg); // not equal
3092
3093 //load the lengths of arrays
3094 __ ld(Address(ary1_reg, length_offset), tmp1_reg);
3095 __ ld(Address(ary2_reg, length_offset), tmp2_reg);
3096
3097 // return false if the two arrays are not equal length
3098 __ cmp(tmp1_reg, tmp2_reg);
3099 __ br(Assembler::notEqual, true, Assembler::pn, Ldone);
3100 __ delayed()->mov(G0, result_reg); // not equal
3101
3102 __ br_zero(Assembler::zero, true, Assembler::pn, tmp1_reg, Ldone);
3103 __ delayed()->add(G0, 1, result_reg); // zero-length arrays are equal
3104
3105 // load array addresses
3106 __ add(ary1_reg, base_offset, ary1_reg);
3107 __ add(ary2_reg, base_offset, ary2_reg);
3108
3109 // renaming registers
3110 Register chr1_reg = tmp2_reg; // for characters in ary1
3111 Register chr2_reg = result_reg; // for characters in ary2
3112 Register limit_reg = tmp1_reg; // length
3113
3114 // set byte count
3115 __ sll(limit_reg, exact_log2(sizeof(jchar)), limit_reg);
3116 __ andcc(limit_reg, 0x2, chr1_reg); //trailing character ?
3117 __ br(Assembler::zero, false, Assembler::pt, Lvector);
3118 __ delayed()->nop();
3119
3120 //compare the trailing char
3121 __ sub(limit_reg, sizeof(jchar), limit_reg);
3122 __ lduh(ary1_reg, limit_reg, chr1_reg);
3123 __ lduh(ary2_reg, limit_reg, chr2_reg);
3124 __ cmp(chr1_reg, chr2_reg);
3125 __ br(Assembler::notEqual, true, Assembler::pt, Ldone);
3126 __ delayed()->mov(G0, result_reg); // not equal
3127
3128 // only one char ?
3129 __ br_zero(Assembler::zero, true, Assembler::pn, limit_reg, Ldone);
3130 __ delayed()->add(G0, 1, result_reg); // zero-length arrays are equal
3131
3132 __ bind(Lvector);
3133 // Shift ary1_reg and ary2_reg to the end of the arrays, negate limit
3134 __ add(ary1_reg, limit_reg, ary1_reg);
3135 __ add(ary2_reg, limit_reg, ary2_reg);
3136 __ neg(limit_reg, limit_reg);
3137
3138 __ lduw(ary1_reg, limit_reg, chr1_reg);
3139 __ bind(Lloop);
3140 __ lduw(ary2_reg, limit_reg, chr2_reg);
3141 __ cmp(chr1_reg, chr2_reg);
3142 __ br(Assembler::notEqual, false, Assembler::pt, Ldone);
3143 __ delayed()->mov(G0, result_reg); // not equal
3144 __ inccc(limit_reg, 2*sizeof(jchar));
3145 // annul LDUW if branch is not taken to prevent access past end of string
3146 __ br(Assembler::notZero, true, Assembler::pt, Lloop); //annul on taken
3147 __ delayed()->lduw(ary1_reg, limit_reg, chr1_reg); // hoisted
3148
3149 __ add(G0, 1, result_reg); // equals
3150
3151 __ bind(Ldone);
3152 %}
3153
3154 enc_class enc_rethrow() %{
3155 cbuf.set_inst_mark();
3156 Register temp_reg = G3;
3157 AddressLiteral rethrow_stub(OptoRuntime::rethrow_stub());
3158 assert(temp_reg != reg_to_register_object(R_I0_num), "temp must not break oop_reg");
3159 MacroAssembler _masm(&cbuf);
3160 #ifdef ASSERT
3161 __ save_frame(0);
3162 AddressLiteral last_rethrow_addrlit(&last_rethrow);
3163 __ sethi(last_rethrow_addrlit, L1);
3164 Address addr(L1, last_rethrow_addrlit.low10());
3165 __ get_pc(L2);
3166 __ inc(L2, 3 * BytesPerInstWord); // skip this & 2 more insns to point at jump_to
3167 __ st_ptr(L2, addr);
3168 __ restore();
3169 #endif
3170 __ JUMP(rethrow_stub, temp_reg, 0); // sethi;jmp
3171 __ delayed()->nop();
3172 %}
3173
3174 enc_class emit_mem_nop() %{
3175 // Generates the instruction LDUXA [o6,g0],#0x82,g0
3176 unsigned int *code = (unsigned int*)cbuf.code_end();
3177 *code = (unsigned int)0xc0839040;
3178 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
3179 %}
3180
3181 enc_class emit_fadd_nop() %{
3182 // Generates the instruction FMOVS f31,f31
3183 unsigned int *code = (unsigned int*)cbuf.code_end();
3184 *code = (unsigned int)0xbfa0003f;
3185 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
3186 %}
3187
3188 enc_class emit_br_nop() %{
3189 // Generates the instruction BPN,PN .
3190 unsigned int *code = (unsigned int*)cbuf.code_end();
3191 *code = (unsigned int)0x00400000;
3192 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
3193 %}
3194
3195 enc_class enc_membar_acquire %{
3196 MacroAssembler _masm(&cbuf);
3197 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::LoadLoad) );
3198 %}
3199
3200 enc_class enc_membar_release %{
3201 MacroAssembler _masm(&cbuf);
3202 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::StoreStore) );
3203 %}
3204
3205 enc_class enc_membar_volatile %{
3206 MacroAssembler _masm(&cbuf);
3207 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad) );
3208 %}
3209
3210 enc_class enc_repl8b( iRegI src, iRegL dst ) %{
3211 MacroAssembler _masm(&cbuf);
3212 Register src_reg = reg_to_register_object($src$$reg);
3213 Register dst_reg = reg_to_register_object($dst$$reg);
3214 __ sllx(src_reg, 56, dst_reg);
3215 __ srlx(dst_reg, 8, O7);
3216 __ or3 (dst_reg, O7, dst_reg);
3217 __ srlx(dst_reg, 16, O7);
3218 __ or3 (dst_reg, O7, dst_reg);
3219 __ srlx(dst_reg, 32, O7);
3220 __ or3 (dst_reg, O7, dst_reg);
3221 %}
3222
3223 enc_class enc_repl4b( iRegI src, iRegL dst ) %{
3224 MacroAssembler _masm(&cbuf);
3225 Register src_reg = reg_to_register_object($src$$reg);
3226 Register dst_reg = reg_to_register_object($dst$$reg);
3227 __ sll(src_reg, 24, dst_reg);
3228 __ srl(dst_reg, 8, O7);
3229 __ or3(dst_reg, O7, dst_reg);
3230 __ srl(dst_reg, 16, O7);
3231 __ or3(dst_reg, O7, dst_reg);
3232 %}
3233
3234 enc_class enc_repl4s( iRegI src, iRegL dst ) %{
3235 MacroAssembler _masm(&cbuf);
3236 Register src_reg = reg_to_register_object($src$$reg);
3237 Register dst_reg = reg_to_register_object($dst$$reg);
3238 __ sllx(src_reg, 48, dst_reg);
3239 __ srlx(dst_reg, 16, O7);
3240 __ or3 (dst_reg, O7, dst_reg);
3241 __ srlx(dst_reg, 32, O7);
3242 __ or3 (dst_reg, O7, dst_reg);
3243 %}
3244
3245 enc_class enc_repl2i( iRegI src, iRegL dst ) %{
3246 MacroAssembler _masm(&cbuf);
3247 Register src_reg = reg_to_register_object($src$$reg);
3248 Register dst_reg = reg_to_register_object($dst$$reg);
3249 __ sllx(src_reg, 32, dst_reg);
3250 __ srlx(dst_reg, 32, O7);
3251 __ or3 (dst_reg, O7, dst_reg);
3252 %}
3253
3254 %}
3255
3256 //----------FRAME--------------------------------------------------------------
3257 // Definition of frame structure and management information.
3258 //
3259 // S T A C K L A Y O U T Allocators stack-slot number
3260 // | (to get allocators register number
3261 // G Owned by | | v add VMRegImpl::stack0)
3262 // r CALLER | |
3263 // o | +--------+ pad to even-align allocators stack-slot
3264 // w V | pad0 | numbers; owned by CALLER
3265 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
3266 // h ^ | in | 5
3267 // | | args | 4 Holes in incoming args owned by SELF
3268 // | | | | 3
3269 // | | +--------+
3270 // V | | old out| Empty on Intel, window on Sparc
3271 // | old |preserve| Must be even aligned.
3272 // | SP-+--------+----> Matcher::_old_SP, 8 (or 16 in LP64)-byte aligned
3273 // | | in | 3 area for Intel ret address
3274 // Owned by |preserve| Empty on Sparc.
3275 // SELF +--------+
3276 // | | pad2 | 2 pad to align old SP
3277 // | +--------+ 1
3278 // | | locks | 0
3279 // | +--------+----> VMRegImpl::stack0, 8 (or 16 in LP64)-byte aligned
3280 // | | pad1 | 11 pad to align new SP
3281 // | +--------+
3282 // | | | 10
3283 // | | spills | 9 spills
3284 // V | | 8 (pad0 slot for callee)
3285 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
3286 // ^ | out | 7
3287 // | | args | 6 Holes in outgoing args owned by CALLEE
3288 // Owned by +--------+
3289 // CALLEE | new out| 6 Empty on Intel, window on Sparc
3290 // | new |preserve| Must be even-aligned.
3291 // | SP-+--------+----> Matcher::_new_SP, even aligned
3292 // | | |
3293 //
3294 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
3295 // known from SELF's arguments and the Java calling convention.
3296 // Region 6-7 is determined per call site.
3297 // Note 2: If the calling convention leaves holes in the incoming argument
3298 // area, those holes are owned by SELF. Holes in the outgoing area
3299 // are owned by the CALLEE. Holes should not be nessecary in the
3300 // incoming area, as the Java calling convention is completely under
3301 // the control of the AD file. Doubles can be sorted and packed to
3302 // avoid holes. Holes in the outgoing arguments may be nessecary for
3303 // varargs C calling conventions.
3304 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
3305 // even aligned with pad0 as needed.
3306 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
3307 // region 6-11 is even aligned; it may be padded out more so that
3308 // the region from SP to FP meets the minimum stack alignment.
3309
3310 frame %{
3311 // What direction does stack grow in (assumed to be same for native & Java)
3312 stack_direction(TOWARDS_LOW);
3313
3314 // These two registers define part of the calling convention
3315 // between compiled code and the interpreter.
3316 inline_cache_reg(R_G5); // Inline Cache Register or methodOop for I2C
3317 interpreter_method_oop_reg(R_G5); // Method Oop Register when calling interpreter
3318
3319 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
3320 cisc_spilling_operand_name(indOffset);
3321
3322 // Number of stack slots consumed by a Monitor enter
3323 #ifdef _LP64
3324 sync_stack_slots(2);
3325 #else
3326 sync_stack_slots(1);
3327 #endif
3328
3329 // Compiled code's Frame Pointer
3330 frame_pointer(R_SP);
3331
3332 // Stack alignment requirement
3333 stack_alignment(StackAlignmentInBytes);
3334 // LP64: Alignment size in bytes (128-bit -> 16 bytes)
3335 // !LP64: Alignment size in bytes (64-bit -> 8 bytes)
3336
3337 // Number of stack slots between incoming argument block and the start of
3338 // a new frame. The PROLOG must add this many slots to the stack. The
3339 // EPILOG must remove this many slots.
3340 in_preserve_stack_slots(0);
3341
3342 // Number of outgoing stack slots killed above the out_preserve_stack_slots
3343 // for calls to C. Supports the var-args backing area for register parms.
3344 // ADLC doesn't support parsing expressions, so I folded the math by hand.
3345 #ifdef _LP64
3346 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (0)) * 2-stack-slots-per-word
3347 varargs_C_out_slots_killed(12);
3348 #else
3349 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (1)) * 1-stack-slots-per-word
3350 varargs_C_out_slots_killed( 7);
3351 #endif
3352
3353 // The after-PROLOG location of the return address. Location of
3354 // return address specifies a type (REG or STACK) and a number
3355 // representing the register number (i.e. - use a register name) or
3356 // stack slot.
3357 return_addr(REG R_I7); // Ret Addr is in register I7
3358
3359 // Body of function which returns an OptoRegs array locating
3360 // arguments either in registers or in stack slots for calling
3361 // java
3362 calling_convention %{
3363 (void) SharedRuntime::java_calling_convention(sig_bt, regs, length, is_outgoing);
3364
3365 %}
3366
3367 // Body of function which returns an OptoRegs array locating
3368 // arguments either in registers or in stack slots for callin
3369 // C.
3370 c_calling_convention %{
3371 // This is obviously always outgoing
3372 (void) SharedRuntime::c_calling_convention(sig_bt, regs, length);
3373 %}
3374
3375 // Location of native (C/C++) and interpreter return values. This is specified to
3376 // be the same as Java. In the 32-bit VM, long values are actually returned from
3377 // native calls in O0:O1 and returned to the interpreter in I0:I1. The copying
3378 // to and from the register pairs is done by the appropriate call and epilog
3379 // opcodes. This simplifies the register allocator.
3380 c_return_value %{
3381 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3382 #ifdef _LP64
3383 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num };
3384 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num};
3385 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num };
3386 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num};
3387 #else // !_LP64
3388 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num };
3389 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num };
3390 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num };
3391 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num };
3392 #endif
3393 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg],
3394 (is_outgoing?lo_out:lo_in)[ideal_reg] );
3395 %}
3396
3397 // Location of compiled Java return values. Same as C
3398 return_value %{
3399 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3400 #ifdef _LP64
3401 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num };
3402 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num};
3403 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num };
3404 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num};
3405 #else // !_LP64
3406 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num };
3407 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num};
3408 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num };
3409 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num};
3410 #endif
3411 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg],
3412 (is_outgoing?lo_out:lo_in)[ideal_reg] );
3413 %}
3414
3415 %}
3416
3417
3418 //----------ATTRIBUTES---------------------------------------------------------
3419 //----------Operand Attributes-------------------------------------------------
3420 op_attrib op_cost(1); // Required cost attribute
3421
3422 //----------Instruction Attributes---------------------------------------------
3423 ins_attrib ins_cost(DEFAULT_COST); // Required cost attribute
3424 ins_attrib ins_size(32); // Required size attribute (in bits)
3425 ins_attrib ins_pc_relative(0); // Required PC Relative flag
3426 ins_attrib ins_short_branch(0); // Required flag: is this instruction a
3427 // non-matching short branch variant of some
3428 // long branch?
3429
3430 //----------OPERANDS-----------------------------------------------------------
3431 // Operand definitions must precede instruction definitions for correct parsing
3432 // in the ADLC because operands constitute user defined types which are used in
3433 // instruction definitions.
3434
3435 //----------Simple Operands----------------------------------------------------
3436 // Immediate Operands
3437 // Integer Immediate: 32-bit
3438 operand immI() %{
3439 match(ConI);
3440
3441 op_cost(0);
3442 // formats are generated automatically for constants and base registers
3443 format %{ %}
3444 interface(CONST_INTER);
3445 %}
3446
3447 // Integer Immediate: 13-bit
3448 operand immI13() %{
3449 predicate(Assembler::is_simm13(n->get_int()));
3450 match(ConI);
3451 op_cost(0);
3452
3453 format %{ %}
3454 interface(CONST_INTER);
3455 %}
3456
3457 // Unsigned (positive) Integer Immediate: 13-bit
3458 operand immU13() %{
3459 predicate((0 <= n->get_int()) && Assembler::is_simm13(n->get_int()));
3460 match(ConI);
3461 op_cost(0);
3462
3463 format %{ %}
3464 interface(CONST_INTER);
3465 %}
3466
3467 // Integer Immediate: 6-bit
3468 operand immU6() %{
3469 predicate(n->get_int() >= 0 && n->get_int() <= 63);
3470 match(ConI);
3471 op_cost(0);
3472 format %{ %}
3473 interface(CONST_INTER);
3474 %}
3475
3476 // Integer Immediate: 11-bit
3477 operand immI11() %{
3478 predicate(Assembler::is_simm(n->get_int(),11));
3479 match(ConI);
3480 op_cost(0);
3481 format %{ %}
3482 interface(CONST_INTER);
3483 %}
3484
3485 // Integer Immediate: 0-bit
3486 operand immI0() %{
3487 predicate(n->get_int() == 0);
3488 match(ConI);
3489 op_cost(0);
3490
3491 format %{ %}
3492 interface(CONST_INTER);
3493 %}
3494
3495 // Integer Immediate: the value 10
3496 operand immI10() %{
3497 predicate(n->get_int() == 10);
3498 match(ConI);
3499 op_cost(0);
3500
3501 format %{ %}
3502 interface(CONST_INTER);
3503 %}
3504
3505 // Integer Immediate: the values 0-31
3506 operand immU5() %{
3507 predicate(n->get_int() >= 0 && n->get_int() <= 31);
3508 match(ConI);
3509 op_cost(0);
3510
3511 format %{ %}
3512 interface(CONST_INTER);
3513 %}
3514
3515 // Integer Immediate: the values 1-31
3516 operand immI_1_31() %{
3517 predicate(n->get_int() >= 1 && n->get_int() <= 31);
3518 match(ConI);
3519 op_cost(0);
3520
3521 format %{ %}
3522 interface(CONST_INTER);
3523 %}
3524
3525 // Integer Immediate: the values 32-63
3526 operand immI_32_63() %{
3527 predicate(n->get_int() >= 32 && n->get_int() <= 63);
3528 match(ConI);
3529 op_cost(0);
3530
3531 format %{ %}
3532 interface(CONST_INTER);
3533 %}
3534
3535 // Integer Immediate: the value 255
3536 operand immI_255() %{
3537 predicate( n->get_int() == 255 );
3538 match(ConI);
3539 op_cost(0);
3540
3541 format %{ %}
3542 interface(CONST_INTER);
3543 %}
3544
3545 // Long Immediate: the value FF
3546 operand immL_FF() %{
3547 predicate( n->get_long() == 0xFFL );
3548 match(ConL);
3549 op_cost(0);
3550
3551 format %{ %}
3552 interface(CONST_INTER);
3553 %}
3554
3555 // Long Immediate: the value FFFF
3556 operand immL_FFFF() %{
3557 predicate( n->get_long() == 0xFFFFL );
3558 match(ConL);
3559 op_cost(0);
3560
3561 format %{ %}
3562 interface(CONST_INTER);
3563 %}
3564
3565 // Pointer Immediate: 32 or 64-bit
3566 operand immP() %{
3567 match(ConP);
3568
3569 op_cost(5);
3570 // formats are generated automatically for constants and base registers
3571 format %{ %}
3572 interface(CONST_INTER);
3573 %}
3574
3575 operand immP13() %{
3576 predicate((-4096 < n->get_ptr()) && (n->get_ptr() <= 4095));
3577 match(ConP);
3578 op_cost(0);
3579
3580 format %{ %}
3581 interface(CONST_INTER);
3582 %}
3583
3584 operand immP0() %{
3585 predicate(n->get_ptr() == 0);
3586 match(ConP);
3587 op_cost(0);
3588
3589 format %{ %}
3590 interface(CONST_INTER);
3591 %}
3592
3593 operand immP_poll() %{
3594 predicate(n->get_ptr() != 0 && n->get_ptr() == (intptr_t)os::get_polling_page());
3595 match(ConP);
3596
3597 // formats are generated automatically for constants and base registers
3598 format %{ %}
3599 interface(CONST_INTER);
3600 %}
3601
3602 // Pointer Immediate
3603 operand immN()
3604 %{
3605 match(ConN);
3606
3607 op_cost(10);
3608 format %{ %}
3609 interface(CONST_INTER);
3610 %}
3611
3612 // NULL Pointer Immediate
3613 operand immN0()
3614 %{
3615 predicate(n->get_narrowcon() == 0);
3616 match(ConN);
3617
3618 op_cost(0);
3619 format %{ %}
3620 interface(CONST_INTER);
3621 %}
3622
3623 operand immL() %{
3624 match(ConL);
3625 op_cost(40);
3626 // formats are generated automatically for constants and base registers
3627 format %{ %}
3628 interface(CONST_INTER);
3629 %}
3630
3631 operand immL0() %{
3632 predicate(n->get_long() == 0L);
3633 match(ConL);
3634 op_cost(0);
3635 // formats are generated automatically for constants and base registers
3636 format %{ %}
3637 interface(CONST_INTER);
3638 %}
3639
3640 // Long Immediate: 13-bit
3641 operand immL13() %{
3642 predicate((-4096L < n->get_long()) && (n->get_long() <= 4095L));
3643 match(ConL);
3644 op_cost(0);
3645
3646 format %{ %}
3647 interface(CONST_INTER);
3648 %}
3649
3650 // Long Immediate: low 32-bit mask
3651 operand immL_32bits() %{
3652 predicate(n->get_long() == 0xFFFFFFFFL);
3653 match(ConL);
3654 op_cost(0);
3655
3656 format %{ %}
3657 interface(CONST_INTER);
3658 %}
3659
3660 // Double Immediate
3661 operand immD() %{
3662 match(ConD);
3663
3664 op_cost(40);
3665 format %{ %}
3666 interface(CONST_INTER);
3667 %}
3668
3669 operand immD0() %{
3670 #ifdef _LP64
3671 // on 64-bit architectures this comparision is faster
3672 predicate(jlong_cast(n->getd()) == 0);
3673 #else
3674 predicate((n->getd() == 0) && (fpclass(n->getd()) == FP_PZERO));
3675 #endif
3676 match(ConD);
3677
3678 op_cost(0);
3679 format %{ %}
3680 interface(CONST_INTER);
3681 %}
3682
3683 // Float Immediate
3684 operand immF() %{
3685 match(ConF);
3686
3687 op_cost(20);
3688 format %{ %}
3689 interface(CONST_INTER);
3690 %}
3691
3692 // Float Immediate: 0
3693 operand immF0() %{
3694 predicate((n->getf() == 0) && (fpclass(n->getf()) == FP_PZERO));
3695 match(ConF);
3696
3697 op_cost(0);
3698 format %{ %}
3699 interface(CONST_INTER);
3700 %}
3701
3702 // Integer Register Operands
3703 // Integer Register
3704 operand iRegI() %{
3705 constraint(ALLOC_IN_RC(int_reg));
3706 match(RegI);
3707
3708 match(notemp_iRegI);
3709 match(g1RegI);
3710 match(o0RegI);
3711 match(iRegIsafe);
3712
3713 format %{ %}
3714 interface(REG_INTER);
3715 %}
3716
3717 operand notemp_iRegI() %{
3718 constraint(ALLOC_IN_RC(notemp_int_reg));
3719 match(RegI);
3720
3721 match(o0RegI);
3722
3723 format %{ %}
3724 interface(REG_INTER);
3725 %}
3726
3727 operand o0RegI() %{
3728 constraint(ALLOC_IN_RC(o0_regI));
3729 match(iRegI);
3730
3731 format %{ %}
3732 interface(REG_INTER);
3733 %}
3734
3735 // Pointer Register
3736 operand iRegP() %{
3737 constraint(ALLOC_IN_RC(ptr_reg));
3738 match(RegP);
3739
3740 match(lock_ptr_RegP);
3741 match(g1RegP);
3742 match(g2RegP);
3743 match(g3RegP);
3744 match(g4RegP);
3745 match(i0RegP);
3746 match(o0RegP);
3747 match(o1RegP);
3748 match(l7RegP);
3749
3750 format %{ %}
3751 interface(REG_INTER);
3752 %}
3753
3754 operand sp_ptr_RegP() %{
3755 constraint(ALLOC_IN_RC(sp_ptr_reg));
3756 match(RegP);
3757 match(iRegP);
3758
3759 format %{ %}
3760 interface(REG_INTER);
3761 %}
3762
3763 operand lock_ptr_RegP() %{
3764 constraint(ALLOC_IN_RC(lock_ptr_reg));
3765 match(RegP);
3766 match(i0RegP);
3767 match(o0RegP);
3768 match(o1RegP);
3769 match(l7RegP);
3770
3771 format %{ %}
3772 interface(REG_INTER);
3773 %}
3774
3775 operand g1RegP() %{
3776 constraint(ALLOC_IN_RC(g1_regP));
3777 match(iRegP);
3778
3779 format %{ %}
3780 interface(REG_INTER);
3781 %}
3782
3783 operand g2RegP() %{
3784 constraint(ALLOC_IN_RC(g2_regP));
3785 match(iRegP);
3786
3787 format %{ %}
3788 interface(REG_INTER);
3789 %}
3790
3791 operand g3RegP() %{
3792 constraint(ALLOC_IN_RC(g3_regP));
3793 match(iRegP);
3794
3795 format %{ %}
3796 interface(REG_INTER);
3797 %}
3798
3799 operand g1RegI() %{
3800 constraint(ALLOC_IN_RC(g1_regI));
3801 match(iRegI);
3802
3803 format %{ %}
3804 interface(REG_INTER);
3805 %}
3806
3807 operand g3RegI() %{
3808 constraint(ALLOC_IN_RC(g3_regI));
3809 match(iRegI);
3810
3811 format %{ %}
3812 interface(REG_INTER);
3813 %}
3814
3815 operand g4RegI() %{
3816 constraint(ALLOC_IN_RC(g4_regI));
3817 match(iRegI);
3818
3819 format %{ %}
3820 interface(REG_INTER);
3821 %}
3822
3823 operand g4RegP() %{
3824 constraint(ALLOC_IN_RC(g4_regP));
3825 match(iRegP);
3826
3827 format %{ %}
3828 interface(REG_INTER);
3829 %}
3830
3831 operand i0RegP() %{
3832 constraint(ALLOC_IN_RC(i0_regP));
3833 match(iRegP);
3834
3835 format %{ %}
3836 interface(REG_INTER);
3837 %}
3838
3839 operand o0RegP() %{
3840 constraint(ALLOC_IN_RC(o0_regP));
3841 match(iRegP);
3842
3843 format %{ %}
3844 interface(REG_INTER);
3845 %}
3846
3847 operand o1RegP() %{
3848 constraint(ALLOC_IN_RC(o1_regP));
3849 match(iRegP);
3850
3851 format %{ %}
3852 interface(REG_INTER);
3853 %}
3854
3855 operand o2RegP() %{
3856 constraint(ALLOC_IN_RC(o2_regP));
3857 match(iRegP);
3858
3859 format %{ %}
3860 interface(REG_INTER);
3861 %}
3862
3863 operand o7RegP() %{
3864 constraint(ALLOC_IN_RC(o7_regP));
3865 match(iRegP);
3866
3867 format %{ %}
3868 interface(REG_INTER);
3869 %}
3870
3871 operand l7RegP() %{
3872 constraint(ALLOC_IN_RC(l7_regP));
3873 match(iRegP);
3874
3875 format %{ %}
3876 interface(REG_INTER);
3877 %}
3878
3879 operand o7RegI() %{
3880 constraint(ALLOC_IN_RC(o7_regI));
3881 match(iRegI);
3882
3883 format %{ %}
3884 interface(REG_INTER);
3885 %}
3886
3887 operand iRegN() %{
3888 constraint(ALLOC_IN_RC(int_reg));
3889 match(RegN);
3890
3891 format %{ %}
3892 interface(REG_INTER);
3893 %}
3894
3895 // Long Register
3896 operand iRegL() %{
3897 constraint(ALLOC_IN_RC(long_reg));
3898 match(RegL);
3899
3900 format %{ %}
3901 interface(REG_INTER);
3902 %}
3903
3904 operand o2RegL() %{
3905 constraint(ALLOC_IN_RC(o2_regL));
3906 match(iRegL);
3907
3908 format %{ %}
3909 interface(REG_INTER);
3910 %}
3911
3912 operand o7RegL() %{
3913 constraint(ALLOC_IN_RC(o7_regL));
3914 match(iRegL);
3915
3916 format %{ %}
3917 interface(REG_INTER);
3918 %}
3919
3920 operand g1RegL() %{
3921 constraint(ALLOC_IN_RC(g1_regL));
3922 match(iRegL);
3923
3924 format %{ %}
3925 interface(REG_INTER);
3926 %}
3927
3928 operand g3RegL() %{
3929 constraint(ALLOC_IN_RC(g3_regL));
3930 match(iRegL);
3931
3932 format %{ %}
3933 interface(REG_INTER);
3934 %}
3935
3936 // Int Register safe
3937 // This is 64bit safe
3938 operand iRegIsafe() %{
3939 constraint(ALLOC_IN_RC(long_reg));
3940
3941 match(iRegI);
3942
3943 format %{ %}
3944 interface(REG_INTER);
3945 %}
3946
3947 // Condition Code Flag Register
3948 operand flagsReg() %{
3949 constraint(ALLOC_IN_RC(int_flags));
3950 match(RegFlags);
3951
3952 format %{ "ccr" %} // both ICC and XCC
3953 interface(REG_INTER);
3954 %}
3955
3956 // Condition Code Register, unsigned comparisons.
3957 operand flagsRegU() %{
3958 constraint(ALLOC_IN_RC(int_flags));
3959 match(RegFlags);
3960
3961 format %{ "icc_U" %}
3962 interface(REG_INTER);
3963 %}
3964
3965 // Condition Code Register, pointer comparisons.
3966 operand flagsRegP() %{
3967 constraint(ALLOC_IN_RC(int_flags));
3968 match(RegFlags);
3969
3970 #ifdef _LP64
3971 format %{ "xcc_P" %}
3972 #else
3973 format %{ "icc_P" %}
3974 #endif
3975 interface(REG_INTER);
3976 %}
3977
3978 // Condition Code Register, long comparisons.
3979 operand flagsRegL() %{
3980 constraint(ALLOC_IN_RC(int_flags));
3981 match(RegFlags);
3982
3983 format %{ "xcc_L" %}
3984 interface(REG_INTER);
3985 %}
3986
3987 // Condition Code Register, floating comparisons, unordered same as "less".
3988 operand flagsRegF() %{
3989 constraint(ALLOC_IN_RC(float_flags));
3990 match(RegFlags);
3991 match(flagsRegF0);
3992
3993 format %{ %}
3994 interface(REG_INTER);
3995 %}
3996
3997 operand flagsRegF0() %{
3998 constraint(ALLOC_IN_RC(float_flag0));
3999 match(RegFlags);
4000
4001 format %{ %}
4002 interface(REG_INTER);
4003 %}
4004
4005
4006 // Condition Code Flag Register used by long compare
4007 operand flagsReg_long_LTGE() %{
4008 constraint(ALLOC_IN_RC(int_flags));
4009 match(RegFlags);
4010 format %{ "icc_LTGE" %}
4011 interface(REG_INTER);
4012 %}
4013 operand flagsReg_long_EQNE() %{
4014 constraint(ALLOC_IN_RC(int_flags));
4015 match(RegFlags);
4016 format %{ "icc_EQNE" %}
4017 interface(REG_INTER);
4018 %}
4019 operand flagsReg_long_LEGT() %{
4020 constraint(ALLOC_IN_RC(int_flags));
4021 match(RegFlags);
4022 format %{ "icc_LEGT" %}
4023 interface(REG_INTER);
4024 %}
4025
4026
4027 operand regD() %{
4028 constraint(ALLOC_IN_RC(dflt_reg));
4029 match(RegD);
4030
4031 match(regD_low);
4032
4033 format %{ %}
4034 interface(REG_INTER);
4035 %}
4036
4037 operand regF() %{
4038 constraint(ALLOC_IN_RC(sflt_reg));
4039 match(RegF);
4040
4041 format %{ %}
4042 interface(REG_INTER);
4043 %}
4044
4045 operand regD_low() %{
4046 constraint(ALLOC_IN_RC(dflt_low_reg));
4047 match(regD);
4048
4049 format %{ %}
4050 interface(REG_INTER);
4051 %}
4052
4053 // Special Registers
4054
4055 // Method Register
4056 operand inline_cache_regP(iRegP reg) %{
4057 constraint(ALLOC_IN_RC(g5_regP)); // G5=inline_cache_reg but uses 2 bits instead of 1
4058 match(reg);
4059 format %{ %}
4060 interface(REG_INTER);
4061 %}
4062
4063 operand interpreter_method_oop_regP(iRegP reg) %{
4064 constraint(ALLOC_IN_RC(g5_regP)); // G5=interpreter_method_oop_reg but uses 2 bits instead of 1
4065 match(reg);
4066 format %{ %}
4067 interface(REG_INTER);
4068 %}
4069
4070
4071 //----------Complex Operands---------------------------------------------------
4072 // Indirect Memory Reference
4073 operand indirect(sp_ptr_RegP reg) %{
4074 constraint(ALLOC_IN_RC(sp_ptr_reg));
4075 match(reg);
4076
4077 op_cost(100);
4078 format %{ "[$reg]" %}
4079 interface(MEMORY_INTER) %{
4080 base($reg);
4081 index(0x0);
4082 scale(0x0);
4083 disp(0x0);
4084 %}
4085 %}
4086
4087 // Indirect with Offset
4088 operand indOffset13(sp_ptr_RegP reg, immX13 offset) %{
4089 constraint(ALLOC_IN_RC(sp_ptr_reg));
4090 match(AddP reg offset);
4091
4092 op_cost(100);
4093 format %{ "[$reg + $offset]" %}
4094 interface(MEMORY_INTER) %{
4095 base($reg);
4096 index(0x0);
4097 scale(0x0);
4098 disp($offset);
4099 %}
4100 %}
4101
4102 // Note: Intel has a swapped version also, like this:
4103 //operand indOffsetX(iRegI reg, immP offset) %{
4104 // constraint(ALLOC_IN_RC(int_reg));
4105 // match(AddP offset reg);
4106 //
4107 // op_cost(100);
4108 // format %{ "[$reg + $offset]" %}
4109 // interface(MEMORY_INTER) %{
4110 // base($reg);
4111 // index(0x0);
4112 // scale(0x0);
4113 // disp($offset);
4114 // %}
4115 //%}
4116 //// However, it doesn't make sense for SPARC, since
4117 // we have no particularly good way to embed oops in
4118 // single instructions.
4119
4120 // Indirect with Register Index
4121 operand indIndex(iRegP addr, iRegX index) %{
4122 constraint(ALLOC_IN_RC(ptr_reg));
4123 match(AddP addr index);
4124
4125 op_cost(100);
4126 format %{ "[$addr + $index]" %}
4127 interface(MEMORY_INTER) %{
4128 base($addr);
4129 index($index);
4130 scale(0x0);
4131 disp(0x0);
4132 %}
4133 %}
4134
4135 //----------Special Memory Operands--------------------------------------------
4136 // Stack Slot Operand - This operand is used for loading and storing temporary
4137 // values on the stack where a match requires a value to
4138 // flow through memory.
4139 operand stackSlotI(sRegI reg) %{
4140 constraint(ALLOC_IN_RC(stack_slots));
4141 op_cost(100);
4142 //match(RegI);
4143 format %{ "[$reg]" %}
4144 interface(MEMORY_INTER) %{
4145 base(0xE); // R_SP
4146 index(0x0);
4147 scale(0x0);
4148 disp($reg); // Stack Offset
4149 %}
4150 %}
4151
4152 operand stackSlotP(sRegP reg) %{
4153 constraint(ALLOC_IN_RC(stack_slots));
4154 op_cost(100);
4155 //match(RegP);
4156 format %{ "[$reg]" %}
4157 interface(MEMORY_INTER) %{
4158 base(0xE); // R_SP
4159 index(0x0);
4160 scale(0x0);
4161 disp($reg); // Stack Offset
4162 %}
4163 %}
4164
4165 operand stackSlotF(sRegF reg) %{
4166 constraint(ALLOC_IN_RC(stack_slots));
4167 op_cost(100);
4168 //match(RegF);
4169 format %{ "[$reg]" %}
4170 interface(MEMORY_INTER) %{
4171 base(0xE); // R_SP
4172 index(0x0);
4173 scale(0x0);
4174 disp($reg); // Stack Offset
4175 %}
4176 %}
4177 operand stackSlotD(sRegD reg) %{
4178 constraint(ALLOC_IN_RC(stack_slots));
4179 op_cost(100);
4180 //match(RegD);
4181 format %{ "[$reg]" %}
4182 interface(MEMORY_INTER) %{
4183 base(0xE); // R_SP
4184 index(0x0);
4185 scale(0x0);
4186 disp($reg); // Stack Offset
4187 %}
4188 %}
4189 operand stackSlotL(sRegL reg) %{
4190 constraint(ALLOC_IN_RC(stack_slots));
4191 op_cost(100);
4192 //match(RegL);
4193 format %{ "[$reg]" %}
4194 interface(MEMORY_INTER) %{
4195 base(0xE); // R_SP
4196 index(0x0);
4197 scale(0x0);
4198 disp($reg); // Stack Offset
4199 %}
4200 %}
4201
4202 // Operands for expressing Control Flow
4203 // NOTE: Label is a predefined operand which should not be redefined in
4204 // the AD file. It is generically handled within the ADLC.
4205
4206 //----------Conditional Branch Operands----------------------------------------
4207 // Comparison Op - This is the operation of the comparison, and is limited to
4208 // the following set of codes:
4209 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
4210 //
4211 // Other attributes of the comparison, such as unsignedness, are specified
4212 // by the comparison instruction that sets a condition code flags register.
4213 // That result is represented by a flags operand whose subtype is appropriate
4214 // to the unsignedness (etc.) of the comparison.
4215 //
4216 // Later, the instruction which matches both the Comparison Op (a Bool) and
4217 // the flags (produced by the Cmp) specifies the coding of the comparison op
4218 // by matching a specific subtype of Bool operand below, such as cmpOpU.
4219
4220 operand cmpOp() %{
4221 match(Bool);
4222
4223 format %{ "" %}
4224 interface(COND_INTER) %{
4225 equal(0x1);
4226 not_equal(0x9);
4227 less(0x3);
4228 greater_equal(0xB);
4229 less_equal(0x2);
4230 greater(0xA);
4231 %}
4232 %}
4233
4234 // Comparison Op, unsigned
4235 operand cmpOpU() %{
4236 match(Bool);
4237
4238 format %{ "u" %}
4239 interface(COND_INTER) %{
4240 equal(0x1);
4241 not_equal(0x9);
4242 less(0x5);
4243 greater_equal(0xD);
4244 less_equal(0x4);
4245 greater(0xC);
4246 %}
4247 %}
4248
4249 // Comparison Op, pointer (same as unsigned)
4250 operand cmpOpP() %{
4251 match(Bool);
4252
4253 format %{ "p" %}
4254 interface(COND_INTER) %{
4255 equal(0x1);
4256 not_equal(0x9);
4257 less(0x5);
4258 greater_equal(0xD);
4259 less_equal(0x4);
4260 greater(0xC);
4261 %}
4262 %}
4263
4264 // Comparison Op, branch-register encoding
4265 operand cmpOp_reg() %{
4266 match(Bool);
4267
4268 format %{ "" %}
4269 interface(COND_INTER) %{
4270 equal (0x1);
4271 not_equal (0x5);
4272 less (0x3);
4273 greater_equal(0x7);
4274 less_equal (0x2);
4275 greater (0x6);
4276 %}
4277 %}
4278
4279 // Comparison Code, floating, unordered same as less
4280 operand cmpOpF() %{
4281 match(Bool);
4282
4283 format %{ "fl" %}
4284 interface(COND_INTER) %{
4285 equal(0x9);
4286 not_equal(0x1);
4287 less(0x3);
4288 greater_equal(0xB);
4289 less_equal(0xE);
4290 greater(0x6);
4291 %}
4292 %}
4293
4294 // Used by long compare
4295 operand cmpOp_commute() %{
4296 match(Bool);
4297
4298 format %{ "" %}
4299 interface(COND_INTER) %{
4300 equal(0x1);
4301 not_equal(0x9);
4302 less(0xA);
4303 greater_equal(0x2);
4304 less_equal(0xB);
4305 greater(0x3);
4306 %}
4307 %}
4308
4309 //----------OPERAND CLASSES----------------------------------------------------
4310 // Operand Classes are groups of operands that are used to simplify
4311 // instruction definitions by not requiring the AD writer to specify separate
4312 // instructions for every form of operand when the instruction accepts
4313 // multiple operand types with the same basic encoding and format. The classic
4314 // case of this is memory operands.
4315 // Indirect is not included since its use is limited to Compare & Swap
4316 opclass memory( indirect, indOffset13, indIndex );
4317
4318 //----------PIPELINE-----------------------------------------------------------
4319 pipeline %{
4320
4321 //----------ATTRIBUTES---------------------------------------------------------
4322 attributes %{
4323 fixed_size_instructions; // Fixed size instructions
4324 branch_has_delay_slot; // Branch has delay slot following
4325 max_instructions_per_bundle = 4; // Up to 4 instructions per bundle
4326 instruction_unit_size = 4; // An instruction is 4 bytes long
4327 instruction_fetch_unit_size = 16; // The processor fetches one line
4328 instruction_fetch_units = 1; // of 16 bytes
4329
4330 // List of nop instructions
4331 nops( Nop_A0, Nop_A1, Nop_MS, Nop_FA, Nop_BR );
4332 %}
4333
4334 //----------RESOURCES----------------------------------------------------------
4335 // Resources are the functional units available to the machine
4336 resources(A0, A1, MS, BR, FA, FM, IDIV, FDIV, IALU = A0 | A1);
4337
4338 //----------PIPELINE DESCRIPTION-----------------------------------------------
4339 // Pipeline Description specifies the stages in the machine's pipeline
4340
4341 pipe_desc(A, P, F, B, I, J, S, R, E, C, M, W, X, T, D);
4342
4343 //----------PIPELINE CLASSES---------------------------------------------------
4344 // Pipeline Classes describe the stages in which input and output are
4345 // referenced by the hardware pipeline.
4346
4347 // Integer ALU reg-reg operation
4348 pipe_class ialu_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
4349 single_instruction;
4350 dst : E(write);
4351 src1 : R(read);
4352 src2 : R(read);
4353 IALU : R;
4354 %}
4355
4356 // Integer ALU reg-reg long operation
4357 pipe_class ialu_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{
4358 instruction_count(2);
4359 dst : E(write);
4360 src1 : R(read);
4361 src2 : R(read);
4362 IALU : R;
4363 IALU : R;
4364 %}
4365
4366 // Integer ALU reg-reg long dependent operation
4367 pipe_class ialu_reg_reg_2_dep(iRegL dst, iRegL src1, iRegL src2, flagsReg cr) %{
4368 instruction_count(1); multiple_bundles;
4369 dst : E(write);
4370 src1 : R(read);
4371 src2 : R(read);
4372 cr : E(write);
4373 IALU : R(2);
4374 %}
4375
4376 // Integer ALU reg-imm operaion
4377 pipe_class ialu_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{
4378 single_instruction;
4379 dst : E(write);
4380 src1 : R(read);
4381 IALU : R;
4382 %}
4383
4384 // Integer ALU reg-reg operation with condition code
4385 pipe_class ialu_cc_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
4386 single_instruction;
4387 dst : E(write);
4388 cr : E(write);
4389 src1 : R(read);
4390 src2 : R(read);
4391 IALU : R;
4392 %}
4393
4394 // Integer ALU reg-imm operation with condition code
4395 pipe_class ialu_cc_reg_imm(iRegI dst, iRegI src1, immI13 src2, flagsReg cr) %{
4396 single_instruction;
4397 dst : E(write);
4398 cr : E(write);
4399 src1 : R(read);
4400 IALU : R;
4401 %}
4402
4403 // Integer ALU zero-reg operation
4404 pipe_class ialu_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{
4405 single_instruction;
4406 dst : E(write);
4407 src2 : R(read);
4408 IALU : R;
4409 %}
4410
4411 // Integer ALU zero-reg operation with condition code only
4412 pipe_class ialu_cconly_zero_reg(flagsReg cr, iRegI src) %{
4413 single_instruction;
4414 cr : E(write);
4415 src : R(read);
4416 IALU : R;
4417 %}
4418
4419 // Integer ALU reg-reg operation with condition code only
4420 pipe_class ialu_cconly_reg_reg(flagsReg cr, iRegI src1, iRegI src2) %{
4421 single_instruction;
4422 cr : E(write);
4423 src1 : R(read);
4424 src2 : R(read);
4425 IALU : R;
4426 %}
4427
4428 // Integer ALU reg-imm operation with condition code only
4429 pipe_class ialu_cconly_reg_imm(flagsReg cr, iRegI src1, immI13 src2) %{
4430 single_instruction;
4431 cr : E(write);
4432 src1 : R(read);
4433 IALU : R;
4434 %}
4435
4436 // Integer ALU reg-reg-zero operation with condition code only
4437 pipe_class ialu_cconly_reg_reg_zero(flagsReg cr, iRegI src1, iRegI src2, immI0 zero) %{
4438 single_instruction;
4439 cr : E(write);
4440 src1 : R(read);
4441 src2 : R(read);
4442 IALU : R;
4443 %}
4444
4445 // Integer ALU reg-imm-zero operation with condition code only
4446 pipe_class ialu_cconly_reg_imm_zero(flagsReg cr, iRegI src1, immI13 src2, immI0 zero) %{
4447 single_instruction;
4448 cr : E(write);
4449 src1 : R(read);
4450 IALU : R;
4451 %}
4452
4453 // Integer ALU reg-reg operation with condition code, src1 modified
4454 pipe_class ialu_cc_rwreg_reg(flagsReg cr, iRegI src1, iRegI src2) %{
4455 single_instruction;
4456 cr : E(write);
4457 src1 : E(write);
4458 src1 : R(read);
4459 src2 : R(read);
4460 IALU : R;
4461 %}
4462
4463 // Integer ALU reg-imm operation with condition code, src1 modified
4464 pipe_class ialu_cc_rwreg_imm(flagsReg cr, iRegI src1, immI13 src2) %{
4465 single_instruction;
4466 cr : E(write);
4467 src1 : E(write);
4468 src1 : R(read);
4469 IALU : R;
4470 %}
4471
4472 pipe_class cmpL_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg cr ) %{
4473 multiple_bundles;
4474 dst : E(write)+4;
4475 cr : E(write);
4476 src1 : R(read);
4477 src2 : R(read);
4478 IALU : R(3);
4479 BR : R(2);
4480 %}
4481
4482 // Integer ALU operation
4483 pipe_class ialu_none(iRegI dst) %{
4484 single_instruction;
4485 dst : E(write);
4486 IALU : R;
4487 %}
4488
4489 // Integer ALU reg operation
4490 pipe_class ialu_reg(iRegI dst, iRegI src) %{
4491 single_instruction; may_have_no_code;
4492 dst : E(write);
4493 src : R(read);
4494 IALU : R;
4495 %}
4496
4497 // Integer ALU reg conditional operation
4498 // This instruction has a 1 cycle stall, and cannot execute
4499 // in the same cycle as the instruction setting the condition
4500 // code. We kludge this by pretending to read the condition code
4501 // 1 cycle earlier, and by marking the functional units as busy
4502 // for 2 cycles with the result available 1 cycle later than
4503 // is really the case.
4504 pipe_class ialu_reg_flags( iRegI op2_out, iRegI op2_in, iRegI op1, flagsReg cr ) %{
4505 single_instruction;
4506 op2_out : C(write);
4507 op1 : R(read);
4508 cr : R(read); // This is really E, with a 1 cycle stall
4509 BR : R(2);
4510 MS : R(2);
4511 %}
4512
4513 #ifdef _LP64
4514 pipe_class ialu_clr_and_mover( iRegI dst, iRegP src ) %{
4515 instruction_count(1); multiple_bundles;
4516 dst : C(write)+1;
4517 src : R(read)+1;
4518 IALU : R(1);
4519 BR : E(2);
4520 MS : E(2);
4521 %}
4522 #endif
4523
4524 // Integer ALU reg operation
4525 pipe_class ialu_move_reg_L_to_I(iRegI dst, iRegL src) %{
4526 single_instruction; may_have_no_code;
4527 dst : E(write);
4528 src : R(read);
4529 IALU : R;
4530 %}
4531 pipe_class ialu_move_reg_I_to_L(iRegL dst, iRegI src) %{
4532 single_instruction; may_have_no_code;
4533 dst : E(write);
4534 src : R(read);
4535 IALU : R;
4536 %}
4537
4538 // Two integer ALU reg operations
4539 pipe_class ialu_reg_2(iRegL dst, iRegL src) %{
4540 instruction_count(2);
4541 dst : E(write);
4542 src : R(read);
4543 A0 : R;
4544 A1 : R;
4545 %}
4546
4547 // Two integer ALU reg operations
4548 pipe_class ialu_move_reg_L_to_L(iRegL dst, iRegL src) %{
4549 instruction_count(2); may_have_no_code;
4550 dst : E(write);
4551 src : R(read);
4552 A0 : R;
4553 A1 : R;
4554 %}
4555
4556 // Integer ALU imm operation
4557 pipe_class ialu_imm(iRegI dst, immI13 src) %{
4558 single_instruction;
4559 dst : E(write);
4560 IALU : R;
4561 %}
4562
4563 // Integer ALU reg-reg with carry operation
4564 pipe_class ialu_reg_reg_cy(iRegI dst, iRegI src1, iRegI src2, iRegI cy) %{
4565 single_instruction;
4566 dst : E(write);
4567 src1 : R(read);
4568 src2 : R(read);
4569 IALU : R;
4570 %}
4571
4572 // Integer ALU cc operation
4573 pipe_class ialu_cc(iRegI dst, flagsReg cc) %{
4574 single_instruction;
4575 dst : E(write);
4576 cc : R(read);
4577 IALU : R;
4578 %}
4579
4580 // Integer ALU cc / second IALU operation
4581 pipe_class ialu_reg_ialu( iRegI dst, iRegI src ) %{
4582 instruction_count(1); multiple_bundles;
4583 dst : E(write)+1;
4584 src : R(read);
4585 IALU : R;
4586 %}
4587
4588 // Integer ALU cc / second IALU operation
4589 pipe_class ialu_reg_reg_ialu( iRegI dst, iRegI p, iRegI q ) %{
4590 instruction_count(1); multiple_bundles;
4591 dst : E(write)+1;
4592 p : R(read);
4593 q : R(read);
4594 IALU : R;
4595 %}
4596
4597 // Integer ALU hi-lo-reg operation
4598 pipe_class ialu_hi_lo_reg(iRegI dst, immI src) %{
4599 instruction_count(1); multiple_bundles;
4600 dst : E(write)+1;
4601 IALU : R(2);
4602 %}
4603
4604 // Float ALU hi-lo-reg operation (with temp)
4605 pipe_class ialu_hi_lo_reg_temp(regF dst, immF src, g3RegP tmp) %{
4606 instruction_count(1); multiple_bundles;
4607 dst : E(write)+1;
4608 IALU : R(2);
4609 %}
4610
4611 // Long Constant
4612 pipe_class loadConL( iRegL dst, immL src ) %{
4613 instruction_count(2); multiple_bundles;
4614 dst : E(write)+1;
4615 IALU : R(2);
4616 IALU : R(2);
4617 %}
4618
4619 // Pointer Constant
4620 pipe_class loadConP( iRegP dst, immP src ) %{
4621 instruction_count(0); multiple_bundles;
4622 fixed_latency(6);
4623 %}
4624
4625 // Polling Address
4626 pipe_class loadConP_poll( iRegP dst, immP_poll src ) %{
4627 #ifdef _LP64
4628 instruction_count(0); multiple_bundles;
4629 fixed_latency(6);
4630 #else
4631 dst : E(write);
4632 IALU : R;
4633 #endif
4634 %}
4635
4636 // Long Constant small
4637 pipe_class loadConLlo( iRegL dst, immL src ) %{
4638 instruction_count(2);
4639 dst : E(write);
4640 IALU : R;
4641 IALU : R;
4642 %}
4643
4644 // [PHH] This is wrong for 64-bit. See LdImmF/D.
4645 pipe_class loadConFD(regF dst, immF src, g3RegP tmp) %{
4646 instruction_count(1); multiple_bundles;
4647 src : R(read);
4648 dst : M(write)+1;
4649 IALU : R;
4650 MS : E;
4651 %}
4652
4653 // Integer ALU nop operation
4654 pipe_class ialu_nop() %{
4655 single_instruction;
4656 IALU : R;
4657 %}
4658
4659 // Integer ALU nop operation
4660 pipe_class ialu_nop_A0() %{
4661 single_instruction;
4662 A0 : R;
4663 %}
4664
4665 // Integer ALU nop operation
4666 pipe_class ialu_nop_A1() %{
4667 single_instruction;
4668 A1 : R;
4669 %}
4670
4671 // Integer Multiply reg-reg operation
4672 pipe_class imul_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
4673 single_instruction;
4674 dst : E(write);
4675 src1 : R(read);
4676 src2 : R(read);
4677 MS : R(5);
4678 %}
4679
4680 // Integer Multiply reg-imm operation
4681 pipe_class imul_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{
4682 single_instruction;
4683 dst : E(write);
4684 src1 : R(read);
4685 MS : R(5);
4686 %}
4687
4688 pipe_class mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
4689 single_instruction;
4690 dst : E(write)+4;
4691 src1 : R(read);
4692 src2 : R(read);
4693 MS : R(6);
4694 %}
4695
4696 pipe_class mulL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{
4697 single_instruction;
4698 dst : E(write)+4;
4699 src1 : R(read);
4700 MS : R(6);
4701 %}
4702
4703 // Integer Divide reg-reg
4704 pipe_class sdiv_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI temp, flagsReg cr) %{
4705 instruction_count(1); multiple_bundles;
4706 dst : E(write);
4707 temp : E(write);
4708 src1 : R(read);
4709 src2 : R(read);
4710 temp : R(read);
4711 MS : R(38);
4712 %}
4713
4714 // Integer Divide reg-imm
4715 pipe_class sdiv_reg_imm(iRegI dst, iRegI src1, immI13 src2, iRegI temp, flagsReg cr) %{
4716 instruction_count(1); multiple_bundles;
4717 dst : E(write);
4718 temp : E(write);
4719 src1 : R(read);
4720 temp : R(read);
4721 MS : R(38);
4722 %}
4723
4724 // Long Divide
4725 pipe_class divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
4726 dst : E(write)+71;
4727 src1 : R(read);
4728 src2 : R(read)+1;
4729 MS : R(70);
4730 %}
4731
4732 pipe_class divL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{
4733 dst : E(write)+71;
4734 src1 : R(read);
4735 MS : R(70);
4736 %}
4737
4738 // Floating Point Add Float
4739 pipe_class faddF_reg_reg(regF dst, regF src1, regF src2) %{
4740 single_instruction;
4741 dst : X(write);
4742 src1 : E(read);
4743 src2 : E(read);
4744 FA : R;
4745 %}
4746
4747 // Floating Point Add Double
4748 pipe_class faddD_reg_reg(regD dst, regD src1, regD src2) %{
4749 single_instruction;
4750 dst : X(write);
4751 src1 : E(read);
4752 src2 : E(read);
4753 FA : R;
4754 %}
4755
4756 // Floating Point Conditional Move based on integer flags
4757 pipe_class int_conditional_float_move (cmpOp cmp, flagsReg cr, regF dst, regF src) %{
4758 single_instruction;
4759 dst : X(write);
4760 src : E(read);
4761 cr : R(read);
4762 FA : R(2);
4763 BR : R(2);
4764 %}
4765
4766 // Floating Point Conditional Move based on integer flags
4767 pipe_class int_conditional_double_move (cmpOp cmp, flagsReg cr, regD dst, regD src) %{
4768 single_instruction;
4769 dst : X(write);
4770 src : E(read);
4771 cr : R(read);
4772 FA : R(2);
4773 BR : R(2);
4774 %}
4775
4776 // Floating Point Multiply Float
4777 pipe_class fmulF_reg_reg(regF dst, regF src1, regF src2) %{
4778 single_instruction;
4779 dst : X(write);
4780 src1 : E(read);
4781 src2 : E(read);
4782 FM : R;
4783 %}
4784
4785 // Floating Point Multiply Double
4786 pipe_class fmulD_reg_reg(regD dst, regD src1, regD src2) %{
4787 single_instruction;
4788 dst : X(write);
4789 src1 : E(read);
4790 src2 : E(read);
4791 FM : R;
4792 %}
4793
4794 // Floating Point Divide Float
4795 pipe_class fdivF_reg_reg(regF dst, regF src1, regF src2) %{
4796 single_instruction;
4797 dst : X(write);
4798 src1 : E(read);
4799 src2 : E(read);
4800 FM : R;
4801 FDIV : C(14);
4802 %}
4803
4804 // Floating Point Divide Double
4805 pipe_class fdivD_reg_reg(regD dst, regD src1, regD src2) %{
4806 single_instruction;
4807 dst : X(write);
4808 src1 : E(read);
4809 src2 : E(read);
4810 FM : R;
4811 FDIV : C(17);
4812 %}
4813
4814 // Floating Point Move/Negate/Abs Float
4815 pipe_class faddF_reg(regF dst, regF src) %{
4816 single_instruction;
4817 dst : W(write);
4818 src : E(read);
4819 FA : R(1);
4820 %}
4821
4822 // Floating Point Move/Negate/Abs Double
4823 pipe_class faddD_reg(regD dst, regD src) %{
4824 single_instruction;
4825 dst : W(write);
4826 src : E(read);
4827 FA : R;
4828 %}
4829
4830 // Floating Point Convert F->D
4831 pipe_class fcvtF2D(regD dst, regF src) %{
4832 single_instruction;
4833 dst : X(write);
4834 src : E(read);
4835 FA : R;
4836 %}
4837
4838 // Floating Point Convert I->D
4839 pipe_class fcvtI2D(regD dst, regF src) %{
4840 single_instruction;
4841 dst : X(write);
4842 src : E(read);
4843 FA : R;
4844 %}
4845
4846 // Floating Point Convert LHi->D
4847 pipe_class fcvtLHi2D(regD dst, regD src) %{
4848 single_instruction;
4849 dst : X(write);
4850 src : E(read);
4851 FA : R;
4852 %}
4853
4854 // Floating Point Convert L->D
4855 pipe_class fcvtL2D(regD dst, regF src) %{
4856 single_instruction;
4857 dst : X(write);
4858 src : E(read);
4859 FA : R;
4860 %}
4861
4862 // Floating Point Convert L->F
4863 pipe_class fcvtL2F(regD dst, regF src) %{
4864 single_instruction;
4865 dst : X(write);
4866 src : E(read);
4867 FA : R;
4868 %}
4869
4870 // Floating Point Convert D->F
4871 pipe_class fcvtD2F(regD dst, regF src) %{
4872 single_instruction;
4873 dst : X(write);
4874 src : E(read);
4875 FA : R;
4876 %}
4877
4878 // Floating Point Convert I->L
4879 pipe_class fcvtI2L(regD dst, regF src) %{
4880 single_instruction;
4881 dst : X(write);
4882 src : E(read);
4883 FA : R;
4884 %}
4885
4886 // Floating Point Convert D->F
4887 pipe_class fcvtD2I(regF dst, regD src, flagsReg cr) %{
4888 instruction_count(1); multiple_bundles;
4889 dst : X(write)+6;
4890 src : E(read);
4891 FA : R;
4892 %}
4893
4894 // Floating Point Convert D->L
4895 pipe_class fcvtD2L(regD dst, regD src, flagsReg cr) %{
4896 instruction_count(1); multiple_bundles;
4897 dst : X(write)+6;
4898 src : E(read);
4899 FA : R;
4900 %}
4901
4902 // Floating Point Convert F->I
4903 pipe_class fcvtF2I(regF dst, regF src, flagsReg cr) %{
4904 instruction_count(1); multiple_bundles;
4905 dst : X(write)+6;
4906 src : E(read);
4907 FA : R;
4908 %}
4909
4910 // Floating Point Convert F->L
4911 pipe_class fcvtF2L(regD dst, regF src, flagsReg cr) %{
4912 instruction_count(1); multiple_bundles;
4913 dst : X(write)+6;
4914 src : E(read);
4915 FA : R;
4916 %}
4917
4918 // Floating Point Convert I->F
4919 pipe_class fcvtI2F(regF dst, regF src) %{
4920 single_instruction;
4921 dst : X(write);
4922 src : E(read);
4923 FA : R;
4924 %}
4925
4926 // Floating Point Compare
4927 pipe_class faddF_fcc_reg_reg_zero(flagsRegF cr, regF src1, regF src2, immI0 zero) %{
4928 single_instruction;
4929 cr : X(write);
4930 src1 : E(read);
4931 src2 : E(read);
4932 FA : R;
4933 %}
4934
4935 // Floating Point Compare
4936 pipe_class faddD_fcc_reg_reg_zero(flagsRegF cr, regD src1, regD src2, immI0 zero) %{
4937 single_instruction;
4938 cr : X(write);
4939 src1 : E(read);
4940 src2 : E(read);
4941 FA : R;
4942 %}
4943
4944 // Floating Add Nop
4945 pipe_class fadd_nop() %{
4946 single_instruction;
4947 FA : R;
4948 %}
4949
4950 // Integer Store to Memory
4951 pipe_class istore_mem_reg(memory mem, iRegI src) %{
4952 single_instruction;
4953 mem : R(read);
4954 src : C(read);
4955 MS : R;
4956 %}
4957
4958 // Integer Store to Memory
4959 pipe_class istore_mem_spORreg(memory mem, sp_ptr_RegP src) %{
4960 single_instruction;
4961 mem : R(read);
4962 src : C(read);
4963 MS : R;
4964 %}
4965
4966 // Integer Store Zero to Memory
4967 pipe_class istore_mem_zero(memory mem, immI0 src) %{
4968 single_instruction;
4969 mem : R(read);
4970 MS : R;
4971 %}
4972
4973 // Special Stack Slot Store
4974 pipe_class istore_stk_reg(stackSlotI stkSlot, iRegI src) %{
4975 single_instruction;
4976 stkSlot : R(read);
4977 src : C(read);
4978 MS : R;
4979 %}
4980
4981 // Special Stack Slot Store
4982 pipe_class lstoreI_stk_reg(stackSlotL stkSlot, iRegI src) %{
4983 instruction_count(2); multiple_bundles;
4984 stkSlot : R(read);
4985 src : C(read);
4986 MS : R(2);
4987 %}
4988
4989 // Float Store
4990 pipe_class fstoreF_mem_reg(memory mem, RegF src) %{
4991 single_instruction;
4992 mem : R(read);
4993 src : C(read);
4994 MS : R;
4995 %}
4996
4997 // Float Store
4998 pipe_class fstoreF_mem_zero(memory mem, immF0 src) %{
4999 single_instruction;
5000 mem : R(read);
5001 MS : R;
5002 %}
5003
5004 // Double Store
5005 pipe_class fstoreD_mem_reg(memory mem, RegD src) %{
5006 instruction_count(1);
5007 mem : R(read);
5008 src : C(read);
5009 MS : R;
5010 %}
5011
5012 // Double Store
5013 pipe_class fstoreD_mem_zero(memory mem, immD0 src) %{
5014 single_instruction;
5015 mem : R(read);
5016 MS : R;
5017 %}
5018
5019 // Special Stack Slot Float Store
5020 pipe_class fstoreF_stk_reg(stackSlotI stkSlot, RegF src) %{
5021 single_instruction;
5022 stkSlot : R(read);
5023 src : C(read);
5024 MS : R;
5025 %}
5026
5027 // Special Stack Slot Double Store
5028 pipe_class fstoreD_stk_reg(stackSlotI stkSlot, RegD src) %{
5029 single_instruction;
5030 stkSlot : R(read);
5031 src : C(read);
5032 MS : R;
5033 %}
5034
5035 // Integer Load (when sign bit propagation not needed)
5036 pipe_class iload_mem(iRegI dst, memory mem) %{
5037 single_instruction;
5038 mem : R(read);
5039 dst : C(write);
5040 MS : R;
5041 %}
5042
5043 // Integer Load from stack operand
5044 pipe_class iload_stkD(iRegI dst, stackSlotD mem ) %{
5045 single_instruction;
5046 mem : R(read);
5047 dst : C(write);
5048 MS : R;
5049 %}
5050
5051 // Integer Load (when sign bit propagation or masking is needed)
5052 pipe_class iload_mask_mem(iRegI dst, memory mem) %{
5053 single_instruction;
5054 mem : R(read);
5055 dst : M(write);
5056 MS : R;
5057 %}
5058
5059 // Float Load
5060 pipe_class floadF_mem(regF dst, memory mem) %{
5061 single_instruction;
5062 mem : R(read);
5063 dst : M(write);
5064 MS : R;
5065 %}
5066
5067 // Float Load
5068 pipe_class floadD_mem(regD dst, memory mem) %{
5069 instruction_count(1); multiple_bundles; // Again, unaligned argument is only multiple case
5070 mem : R(read);
5071 dst : M(write);
5072 MS : R;
5073 %}
5074
5075 // Float Load
5076 pipe_class floadF_stk(regF dst, stackSlotI stkSlot) %{
5077 single_instruction;
5078 stkSlot : R(read);
5079 dst : M(write);
5080 MS : R;
5081 %}
5082
5083 // Float Load
5084 pipe_class floadD_stk(regD dst, stackSlotI stkSlot) %{
5085 single_instruction;
5086 stkSlot : R(read);
5087 dst : M(write);
5088 MS : R;
5089 %}
5090
5091 // Memory Nop
5092 pipe_class mem_nop() %{
5093 single_instruction;
5094 MS : R;
5095 %}
5096
5097 pipe_class sethi(iRegP dst, immI src) %{
5098 single_instruction;
5099 dst : E(write);
5100 IALU : R;
5101 %}
5102
5103 pipe_class loadPollP(iRegP poll) %{
5104 single_instruction;
5105 poll : R(read);
5106 MS : R;
5107 %}
5108
5109 pipe_class br(Universe br, label labl) %{
5110 single_instruction_with_delay_slot;
5111 BR : R;
5112 %}
5113
5114 pipe_class br_cc(Universe br, cmpOp cmp, flagsReg cr, label labl) %{
5115 single_instruction_with_delay_slot;
5116 cr : E(read);
5117 BR : R;
5118 %}
5119
5120 pipe_class br_reg(Universe br, cmpOp cmp, iRegI op1, label labl) %{
5121 single_instruction_with_delay_slot;
5122 op1 : E(read);
5123 BR : R;
5124 MS : R;
5125 %}
5126
5127 pipe_class br_fcc(Universe br, cmpOpF cc, flagsReg cr, label labl) %{
5128 single_instruction_with_delay_slot;
5129 cr : E(read);
5130 BR : R;
5131 %}
5132
5133 pipe_class br_nop() %{
5134 single_instruction;
5135 BR : R;
5136 %}
5137
5138 pipe_class simple_call(method meth) %{
5139 instruction_count(2); multiple_bundles; force_serialization;
5140 fixed_latency(100);
5141 BR : R(1);
5142 MS : R(1);
5143 A0 : R(1);
5144 %}
5145
5146 pipe_class compiled_call(method meth) %{
5147 instruction_count(1); multiple_bundles; force_serialization;
5148 fixed_latency(100);
5149 MS : R(1);
5150 %}
5151
5152 pipe_class call(method meth) %{
5153 instruction_count(0); multiple_bundles; force_serialization;
5154 fixed_latency(100);
5155 %}
5156
5157 pipe_class tail_call(Universe ignore, label labl) %{
5158 single_instruction; has_delay_slot;
5159 fixed_latency(100);
5160 BR : R(1);
5161 MS : R(1);
5162 %}
5163
5164 pipe_class ret(Universe ignore) %{
5165 single_instruction; has_delay_slot;
5166 BR : R(1);
5167 MS : R(1);
5168 %}
5169
5170 pipe_class ret_poll(g3RegP poll) %{
5171 instruction_count(3); has_delay_slot;
5172 poll : E(read);
5173 MS : R;
5174 %}
5175
5176 // The real do-nothing guy
5177 pipe_class empty( ) %{
5178 instruction_count(0);
5179 %}
5180
5181 pipe_class long_memory_op() %{
5182 instruction_count(0); multiple_bundles; force_serialization;
5183 fixed_latency(25);
5184 MS : R(1);
5185 %}
5186
5187 // Check-cast
5188 pipe_class partial_subtype_check_pipe(Universe ignore, iRegP array, iRegP match ) %{
5189 array : R(read);
5190 match : R(read);
5191 IALU : R(2);
5192 BR : R(2);
5193 MS : R;
5194 %}
5195
5196 // Convert FPU flags into +1,0,-1
5197 pipe_class floating_cmp( iRegI dst, regF src1, regF src2 ) %{
5198 src1 : E(read);
5199 src2 : E(read);
5200 dst : E(write);
5201 FA : R;
5202 MS : R(2);
5203 BR : R(2);
5204 %}
5205
5206 // Compare for p < q, and conditionally add y
5207 pipe_class cadd_cmpltmask( iRegI p, iRegI q, iRegI y ) %{
5208 p : E(read);
5209 q : E(read);
5210 y : E(read);
5211 IALU : R(3)
5212 %}
5213
5214 // Perform a compare, then move conditionally in a branch delay slot.
5215 pipe_class min_max( iRegI src2, iRegI srcdst ) %{
5216 src2 : E(read);
5217 srcdst : E(read);
5218 IALU : R;
5219 BR : R;
5220 %}
5221
5222 // Define the class for the Nop node
5223 define %{
5224 MachNop = ialu_nop;
5225 %}
5226
5227 %}
5228
5229 //----------INSTRUCTIONS-------------------------------------------------------
5230
5231 //------------Special Stack Slot instructions - no match rules-----------------
5232 instruct stkI_to_regF(regF dst, stackSlotI src) %{
5233 // No match rule to avoid chain rule match.
5234 effect(DEF dst, USE src);
5235 ins_cost(MEMORY_REF_COST);
5236 size(4);
5237 format %{ "LDF $src,$dst\t! stkI to regF" %}
5238 opcode(Assembler::ldf_op3);
5239 ins_encode(simple_form3_mem_reg(src, dst));
5240 ins_pipe(floadF_stk);
5241 %}
5242
5243 instruct stkL_to_regD(regD dst, stackSlotL src) %{
5244 // No match rule to avoid chain rule match.
5245 effect(DEF dst, USE src);
5246 ins_cost(MEMORY_REF_COST);
5247 size(4);
5248 format %{ "LDDF $src,$dst\t! stkL to regD" %}
5249 opcode(Assembler::lddf_op3);
5250 ins_encode(simple_form3_mem_reg(src, dst));
5251 ins_pipe(floadD_stk);
5252 %}
5253
5254 instruct regF_to_stkI(stackSlotI dst, regF src) %{
5255 // No match rule to avoid chain rule match.
5256 effect(DEF dst, USE src);
5257 ins_cost(MEMORY_REF_COST);
5258 size(4);
5259 format %{ "STF $src,$dst\t! regF to stkI" %}
5260 opcode(Assembler::stf_op3);
5261 ins_encode(simple_form3_mem_reg(dst, src));
5262 ins_pipe(fstoreF_stk_reg);
5263 %}
5264
5265 instruct regD_to_stkL(stackSlotL dst, regD src) %{
5266 // No match rule to avoid chain rule match.
5267 effect(DEF dst, USE src);
5268 ins_cost(MEMORY_REF_COST);
5269 size(4);
5270 format %{ "STDF $src,$dst\t! regD to stkL" %}
5271 opcode(Assembler::stdf_op3);
5272 ins_encode(simple_form3_mem_reg(dst, src));
5273 ins_pipe(fstoreD_stk_reg);
5274 %}
5275
5276 instruct regI_to_stkLHi(stackSlotL dst, iRegI src) %{
5277 effect(DEF dst, USE src);
5278 ins_cost(MEMORY_REF_COST*2);
5279 size(8);
5280 format %{ "STW $src,$dst.hi\t! long\n\t"
5281 "STW R_G0,$dst.lo" %}
5282 opcode(Assembler::stw_op3);
5283 ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, R_G0));
5284 ins_pipe(lstoreI_stk_reg);
5285 %}
5286
5287 instruct regL_to_stkD(stackSlotD dst, iRegL src) %{
5288 // No match rule to avoid chain rule match.
5289 effect(DEF dst, USE src);
5290 ins_cost(MEMORY_REF_COST);
5291 size(4);
5292 format %{ "STX $src,$dst\t! regL to stkD" %}
5293 opcode(Assembler::stx_op3);
5294 ins_encode(simple_form3_mem_reg( dst, src ) );
5295 ins_pipe(istore_stk_reg);
5296 %}
5297
5298 //---------- Chain stack slots between similar types --------
5299
5300 // Load integer from stack slot
5301 instruct stkI_to_regI( iRegI dst, stackSlotI src ) %{
5302 match(Set dst src);
5303 ins_cost(MEMORY_REF_COST);
5304
5305 size(4);
5306 format %{ "LDUW $src,$dst\t!stk" %}
5307 opcode(Assembler::lduw_op3);
5308 ins_encode(simple_form3_mem_reg( src, dst ) );
5309 ins_pipe(iload_mem);
5310 %}
5311
5312 // Store integer to stack slot
5313 instruct regI_to_stkI( stackSlotI dst, iRegI src ) %{
5314 match(Set dst src);
5315 ins_cost(MEMORY_REF_COST);
5316
5317 size(4);
5318 format %{ "STW $src,$dst\t!stk" %}
5319 opcode(Assembler::stw_op3);
5320 ins_encode(simple_form3_mem_reg( dst, src ) );
5321 ins_pipe(istore_mem_reg);
5322 %}
5323
5324 // Load long from stack slot
5325 instruct stkL_to_regL( iRegL dst, stackSlotL src ) %{
5326 match(Set dst src);
5327
5328 ins_cost(MEMORY_REF_COST);
5329 size(4);
5330 format %{ "LDX $src,$dst\t! long" %}
5331 opcode(Assembler::ldx_op3);
5332 ins_encode(simple_form3_mem_reg( src, dst ) );
5333 ins_pipe(iload_mem);
5334 %}
5335
5336 // Store long to stack slot
5337 instruct regL_to_stkL(stackSlotL dst, iRegL src) %{
5338 match(Set dst src);
5339
5340 ins_cost(MEMORY_REF_COST);
5341 size(4);
5342 format %{ "STX $src,$dst\t! long" %}
5343 opcode(Assembler::stx_op3);
5344 ins_encode(simple_form3_mem_reg( dst, src ) );
5345 ins_pipe(istore_mem_reg);
5346 %}
5347
5348 #ifdef _LP64
5349 // Load pointer from stack slot, 64-bit encoding
5350 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{
5351 match(Set dst src);
5352 ins_cost(MEMORY_REF_COST);
5353 size(4);
5354 format %{ "LDX $src,$dst\t!ptr" %}
5355 opcode(Assembler::ldx_op3);
5356 ins_encode(simple_form3_mem_reg( src, dst ) );
5357 ins_pipe(iload_mem);
5358 %}
5359
5360 // Store pointer to stack slot
5361 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{
5362 match(Set dst src);
5363 ins_cost(MEMORY_REF_COST);
5364 size(4);
5365 format %{ "STX $src,$dst\t!ptr" %}
5366 opcode(Assembler::stx_op3);
5367 ins_encode(simple_form3_mem_reg( dst, src ) );
5368 ins_pipe(istore_mem_reg);
5369 %}
5370 #else // _LP64
5371 // Load pointer from stack slot, 32-bit encoding
5372 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{
5373 match(Set dst src);
5374 ins_cost(MEMORY_REF_COST);
5375 format %{ "LDUW $src,$dst\t!ptr" %}
5376 opcode(Assembler::lduw_op3, Assembler::ldst_op);
5377 ins_encode(simple_form3_mem_reg( src, dst ) );
5378 ins_pipe(iload_mem);
5379 %}
5380
5381 // Store pointer to stack slot
5382 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{
5383 match(Set dst src);
5384 ins_cost(MEMORY_REF_COST);
5385 format %{ "STW $src,$dst\t!ptr" %}
5386 opcode(Assembler::stw_op3, Assembler::ldst_op);
5387 ins_encode(simple_form3_mem_reg( dst, src ) );
5388 ins_pipe(istore_mem_reg);
5389 %}
5390 #endif // _LP64
5391
5392 //------------Special Nop instructions for bundling - no match rules-----------
5393 // Nop using the A0 functional unit
5394 instruct Nop_A0() %{
5395 ins_cost(0);
5396
5397 format %{ "NOP ! Alu Pipeline" %}
5398 opcode(Assembler::or_op3, Assembler::arith_op);
5399 ins_encode( form2_nop() );
5400 ins_pipe(ialu_nop_A0);
5401 %}
5402
5403 // Nop using the A1 functional unit
5404 instruct Nop_A1( ) %{
5405 ins_cost(0);
5406
5407 format %{ "NOP ! Alu Pipeline" %}
5408 opcode(Assembler::or_op3, Assembler::arith_op);
5409 ins_encode( form2_nop() );
5410 ins_pipe(ialu_nop_A1);
5411 %}
5412
5413 // Nop using the memory functional unit
5414 instruct Nop_MS( ) %{
5415 ins_cost(0);
5416
5417 format %{ "NOP ! Memory Pipeline" %}
5418 ins_encode( emit_mem_nop );
5419 ins_pipe(mem_nop);
5420 %}
5421
5422 // Nop using the floating add functional unit
5423 instruct Nop_FA( ) %{
5424 ins_cost(0);
5425
5426 format %{ "NOP ! Floating Add Pipeline" %}
5427 ins_encode( emit_fadd_nop );
5428 ins_pipe(fadd_nop);
5429 %}
5430
5431 // Nop using the branch functional unit
5432 instruct Nop_BR( ) %{
5433 ins_cost(0);
5434
5435 format %{ "NOP ! Branch Pipeline" %}
5436 ins_encode( emit_br_nop );
5437 ins_pipe(br_nop);
5438 %}
5439
5440 //----------Load/Store/Move Instructions---------------------------------------
5441 //----------Load Instructions--------------------------------------------------
5442 // Load Byte (8bit signed)
5443 instruct loadB(iRegI dst, memory mem) %{
5444 match(Set dst (LoadB mem));
5445 ins_cost(MEMORY_REF_COST);
5446
5447 size(4);
5448 format %{ "LDSB $mem,$dst\t! byte" %}
5449 ins_encode %{
5450 __ ldsb($mem$$Address, $dst$$Register);
5451 %}
5452 ins_pipe(iload_mask_mem);
5453 %}
5454
5455 // Load Byte (8bit signed) into a Long Register
5456 instruct loadB2L(iRegL dst, memory mem) %{
5457 match(Set dst (ConvI2L (LoadB mem)));
5458 ins_cost(MEMORY_REF_COST);
5459
5460 size(4);
5461 format %{ "LDSB $mem,$dst\t! byte -> long" %}
5462 ins_encode %{
5463 __ ldsb($mem$$Address, $dst$$Register);
5464 %}
5465 ins_pipe(iload_mask_mem);
5466 %}
5467
5468 // Load Unsigned Byte (8bit UNsigned) into an int reg
5469 instruct loadUB(iRegI dst, memory mem) %{
5470 match(Set dst (LoadUB mem));
5471 ins_cost(MEMORY_REF_COST);
5472
5473 size(4);
5474 format %{ "LDUB $mem,$dst\t! ubyte" %}
5475 ins_encode %{
5476 __ ldub($mem$$Address, $dst$$Register);
5477 %}
5478 ins_pipe(iload_mask_mem);
5479 %}
5480
5481 // Load Unsigned Byte (8bit UNsigned) into a Long Register
5482 instruct loadUB2L(iRegL dst, memory mem) %{
5483 match(Set dst (ConvI2L (LoadUB mem)));
5484 ins_cost(MEMORY_REF_COST);
5485
5486 size(4);
5487 format %{ "LDUB $mem,$dst\t! ubyte -> long" %}
5488 ins_encode %{
5489 __ ldub($mem$$Address, $dst$$Register);
5490 %}
5491 ins_pipe(iload_mask_mem);
5492 %}
5493
5494 // Load Short (16bit signed)
5495 instruct loadS(iRegI dst, memory mem) %{
5496 match(Set dst (LoadS mem));
5497 ins_cost(MEMORY_REF_COST);
5498
5499 size(4);
5500 format %{ "LDSH $mem,$dst\t! short" %}
5501 ins_encode %{
5502 __ ldsh($mem$$Address, $dst$$Register);
5503 %}
5504 ins_pipe(iload_mask_mem);
5505 %}
5506
5507 // Load Short (16bit signed) into a Long Register
5508 instruct loadS2L(iRegL dst, memory mem) %{
5509 match(Set dst (ConvI2L (LoadS mem)));
5510 ins_cost(MEMORY_REF_COST);
5511
5512 size(4);
5513 format %{ "LDSH $mem,$dst\t! short -> long" %}
5514 ins_encode %{
5515 __ ldsh($mem$$Address, $dst$$Register);
5516 %}
5517 ins_pipe(iload_mask_mem);
5518 %}
5519
5520 // Load Unsigned Short/Char (16bit UNsigned)
5521 instruct loadUS(iRegI dst, memory mem) %{
5522 match(Set dst (LoadUS mem));
5523 ins_cost(MEMORY_REF_COST);
5524
5525 size(4);
5526 format %{ "LDUH $mem,$dst\t! ushort/char" %}
5527 ins_encode %{
5528 __ lduh($mem$$Address, $dst$$Register);
5529 %}
5530 ins_pipe(iload_mask_mem);
5531 %}
5532
5533 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register
5534 instruct loadUS2L(iRegL dst, memory mem) %{
5535 match(Set dst (ConvI2L (LoadUS mem)));
5536 ins_cost(MEMORY_REF_COST);
5537
5538 size(4);
5539 format %{ "LDUH $mem,$dst\t! ushort/char -> long" %}
5540 ins_encode %{
5541 __ lduh($mem$$Address, $dst$$Register);
5542 %}
5543 ins_pipe(iload_mask_mem);
5544 %}
5545
5546 // Load Integer
5547 instruct loadI(iRegI dst, memory mem) %{
5548 match(Set dst (LoadI mem));
5549 ins_cost(MEMORY_REF_COST);
5550
5551 size(4);
5552 format %{ "LDUW $mem,$dst\t! int" %}
5553 ins_encode %{
5554 __ lduw($mem$$Address, $dst$$Register);
5555 %}
5556 ins_pipe(iload_mem);
5557 %}
5558
5559 // Load Integer into a Long Register
5560 instruct loadI2L(iRegL dst, memory mem) %{
5561 match(Set dst (ConvI2L (LoadI mem)));
5562 ins_cost(MEMORY_REF_COST);
5563
5564 size(4);
5565 format %{ "LDSW $mem,$dst\t! int -> long" %}
5566 ins_encode %{
5567 __ ldsw($mem$$Address, $dst$$Register);
5568 %}
5569 ins_pipe(iload_mem);
5570 %}
5571
5572 // Load Unsigned Integer into a Long Register
5573 instruct loadUI2L(iRegL dst, memory mem) %{
5574 match(Set dst (LoadUI2L mem));
5575 ins_cost(MEMORY_REF_COST);
5576
5577 size(4);
5578 format %{ "LDUW $mem,$dst\t! uint -> long" %}
5579 ins_encode %{
5580 __ lduw($mem$$Address, $dst$$Register);
5581 %}
5582 ins_pipe(iload_mem);
5583 %}
5584
5585 // Load Long - aligned
5586 instruct loadL(iRegL dst, memory mem ) %{
5587 match(Set dst (LoadL mem));
5588 ins_cost(MEMORY_REF_COST);
5589
5590 size(4);
5591 format %{ "LDX $mem,$dst\t! long" %}
5592 ins_encode %{
5593 __ ldx($mem$$Address, $dst$$Register);
5594 %}
5595 ins_pipe(iload_mem);
5596 %}
5597
5598 // Load Long - UNaligned
5599 instruct loadL_unaligned(iRegL dst, memory mem, o7RegI tmp) %{
5600 match(Set dst (LoadL_unaligned mem));
5601 effect(KILL tmp);
5602 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST);
5603 size(16);
5604 format %{ "LDUW $mem+4,R_O7\t! misaligned long\n"
5605 "\tLDUW $mem ,$dst\n"
5606 "\tSLLX #32, $dst, $dst\n"
5607 "\tOR $dst, R_O7, $dst" %}
5608 opcode(Assembler::lduw_op3);
5609 ins_encode(form3_mem_reg_long_unaligned_marshal( mem, dst ));
5610 ins_pipe(iload_mem);
5611 %}
5612
5613 // Load Aligned Packed Byte into a Double Register
5614 instruct loadA8B(regD dst, memory mem) %{
5615 match(Set dst (Load8B mem));
5616 ins_cost(MEMORY_REF_COST);
5617 size(4);
5618 format %{ "LDDF $mem,$dst\t! packed8B" %}
5619 opcode(Assembler::lddf_op3);
5620 ins_encode(simple_form3_mem_reg( mem, dst ) );
5621 ins_pipe(floadD_mem);
5622 %}
5623
5624 // Load Aligned Packed Char into a Double Register
5625 instruct loadA4C(regD dst, memory mem) %{
5626 match(Set dst (Load4C mem));
5627 ins_cost(MEMORY_REF_COST);
5628 size(4);
5629 format %{ "LDDF $mem,$dst\t! packed4C" %}
5630 opcode(Assembler::lddf_op3);
5631 ins_encode(simple_form3_mem_reg( mem, dst ) );
5632 ins_pipe(floadD_mem);
5633 %}
5634
5635 // Load Aligned Packed Short into a Double Register
5636 instruct loadA4S(regD dst, memory mem) %{
5637 match(Set dst (Load4S mem));
5638 ins_cost(MEMORY_REF_COST);
5639 size(4);
5640 format %{ "LDDF $mem,$dst\t! packed4S" %}
5641 opcode(Assembler::lddf_op3);
5642 ins_encode(simple_form3_mem_reg( mem, dst ) );
5643 ins_pipe(floadD_mem);
5644 %}
5645
5646 // Load Aligned Packed Int into a Double Register
5647 instruct loadA2I(regD dst, memory mem) %{
5648 match(Set dst (Load2I mem));
5649 ins_cost(MEMORY_REF_COST);
5650 size(4);
5651 format %{ "LDDF $mem,$dst\t! packed2I" %}
5652 opcode(Assembler::lddf_op3);
5653 ins_encode(simple_form3_mem_reg( mem, dst ) );
5654 ins_pipe(floadD_mem);
5655 %}
5656
5657 // Load Range
5658 instruct loadRange(iRegI dst, memory mem) %{
5659 match(Set dst (LoadRange mem));
5660 ins_cost(MEMORY_REF_COST);
5661
5662 size(4);
5663 format %{ "LDUW $mem,$dst\t! range" %}
5664 opcode(Assembler::lduw_op3);
5665 ins_encode(simple_form3_mem_reg( mem, dst ) );
5666 ins_pipe(iload_mem);
5667 %}
5668
5669 // Load Integer into %f register (for fitos/fitod)
5670 instruct loadI_freg(regF dst, memory mem) %{
5671 match(Set dst (LoadI mem));
5672 ins_cost(MEMORY_REF_COST);
5673 size(4);
5674
5675 format %{ "LDF $mem,$dst\t! for fitos/fitod" %}
5676 opcode(Assembler::ldf_op3);
5677 ins_encode(simple_form3_mem_reg( mem, dst ) );
5678 ins_pipe(floadF_mem);
5679 %}
5680
5681 // Load Pointer
5682 instruct loadP(iRegP dst, memory mem) %{
5683 match(Set dst (LoadP mem));
5684 ins_cost(MEMORY_REF_COST);
5685 size(4);
5686
5687 #ifndef _LP64
5688 format %{ "LDUW $mem,$dst\t! ptr" %}
5689 ins_encode %{
5690 __ lduw($mem$$Address, $dst$$Register);
5691 %}
5692 #else
5693 format %{ "LDX $mem,$dst\t! ptr" %}
5694 ins_encode %{
5695 __ ldx($mem$$Address, $dst$$Register);
5696 %}
5697 #endif
5698 ins_pipe(iload_mem);
5699 %}
5700
5701 // Load Compressed Pointer
5702 instruct loadN(iRegN dst, memory mem) %{
5703 match(Set dst (LoadN mem));
5704 ins_cost(MEMORY_REF_COST);
5705 size(4);
5706
5707 format %{ "LDUW $mem,$dst\t! compressed ptr" %}
5708 ins_encode %{
5709 __ lduw($mem$$Address, $dst$$Register);
5710 %}
5711 ins_pipe(iload_mem);
5712 %}
5713
5714 // Load Klass Pointer
5715 instruct loadKlass(iRegP dst, memory mem) %{
5716 match(Set dst (LoadKlass mem));
5717 ins_cost(MEMORY_REF_COST);
5718 size(4);
5719
5720 #ifndef _LP64
5721 format %{ "LDUW $mem,$dst\t! klass ptr" %}
5722 ins_encode %{
5723 __ lduw($mem$$Address, $dst$$Register);
5724 %}
5725 #else
5726 format %{ "LDX $mem,$dst\t! klass ptr" %}
5727 ins_encode %{
5728 __ ldx($mem$$Address, $dst$$Register);
5729 %}
5730 #endif
5731 ins_pipe(iload_mem);
5732 %}
5733
5734 // Load narrow Klass Pointer
5735 instruct loadNKlass(iRegN dst, memory mem) %{
5736 match(Set dst (LoadNKlass mem));
5737 ins_cost(MEMORY_REF_COST);
5738 size(4);
5739
5740 format %{ "LDUW $mem,$dst\t! compressed klass ptr" %}
5741 ins_encode %{
5742 __ lduw($mem$$Address, $dst$$Register);
5743 %}
5744 ins_pipe(iload_mem);
5745 %}
5746
5747 // Load Double
5748 instruct loadD(regD dst, memory mem) %{
5749 match(Set dst (LoadD mem));
5750 ins_cost(MEMORY_REF_COST);
5751
5752 size(4);
5753 format %{ "LDDF $mem,$dst" %}
5754 opcode(Assembler::lddf_op3);
5755 ins_encode(simple_form3_mem_reg( mem, dst ) );
5756 ins_pipe(floadD_mem);
5757 %}
5758
5759 // Load Double - UNaligned
5760 instruct loadD_unaligned(regD_low dst, memory mem ) %{
5761 match(Set dst (LoadD_unaligned mem));
5762 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST);
5763 size(8);
5764 format %{ "LDF $mem ,$dst.hi\t! misaligned double\n"
5765 "\tLDF $mem+4,$dst.lo\t!" %}
5766 opcode(Assembler::ldf_op3);
5767 ins_encode( form3_mem_reg_double_unaligned( mem, dst ));
5768 ins_pipe(iload_mem);
5769 %}
5770
5771 // Load Float
5772 instruct loadF(regF dst, memory mem) %{
5773 match(Set dst (LoadF mem));
5774 ins_cost(MEMORY_REF_COST);
5775
5776 size(4);
5777 format %{ "LDF $mem,$dst" %}
5778 opcode(Assembler::ldf_op3);
5779 ins_encode(simple_form3_mem_reg( mem, dst ) );
5780 ins_pipe(floadF_mem);
5781 %}
5782
5783 // Load Constant
5784 instruct loadConI( iRegI dst, immI src ) %{
5785 match(Set dst src);
5786 ins_cost(DEFAULT_COST * 3/2);
5787 format %{ "SET $src,$dst" %}
5788 ins_encode( Set32(src, dst) );
5789 ins_pipe(ialu_hi_lo_reg);
5790 %}
5791
5792 instruct loadConI13( iRegI dst, immI13 src ) %{
5793 match(Set dst src);
5794
5795 size(4);
5796 format %{ "MOV $src,$dst" %}
5797 ins_encode( Set13( src, dst ) );
5798 ins_pipe(ialu_imm);
5799 %}
5800
5801 instruct loadConP(iRegP dst, immP src) %{
5802 match(Set dst src);
5803 ins_cost(DEFAULT_COST * 3/2);
5804 format %{ "SET $src,$dst\t!ptr" %}
5805 // This rule does not use "expand" unlike loadConI because then
5806 // the result type is not known to be an Oop. An ADLC
5807 // enhancement will be needed to make that work - not worth it!
5808
5809 ins_encode( SetPtr( src, dst ) );
5810 ins_pipe(loadConP);
5811
5812 %}
5813
5814 instruct loadConP0(iRegP dst, immP0 src) %{
5815 match(Set dst src);
5816
5817 size(4);
5818 format %{ "CLR $dst\t!ptr" %}
5819 ins_encode( SetNull( dst ) );
5820 ins_pipe(ialu_imm);
5821 %}
5822
5823 instruct loadConP_poll(iRegP dst, immP_poll src) %{
5824 match(Set dst src);
5825 ins_cost(DEFAULT_COST);
5826 format %{ "SET $src,$dst\t!ptr" %}
5827 ins_encode %{
5828 AddressLiteral polling_page(os::get_polling_page());
5829 __ sethi(polling_page, reg_to_register_object($dst$$reg));
5830 %}
5831 ins_pipe(loadConP_poll);
5832 %}
5833
5834 instruct loadConN0(iRegN dst, immN0 src) %{
5835 match(Set dst src);
5836
5837 size(4);
5838 format %{ "CLR $dst\t! compressed NULL ptr" %}
5839 ins_encode( SetNull( dst ) );
5840 ins_pipe(ialu_imm);
5841 %}
5842
5843 instruct loadConN(iRegN dst, immN src) %{
5844 match(Set dst src);
5845 ins_cost(DEFAULT_COST * 3/2);
5846 format %{ "SET $src,$dst\t! compressed ptr" %}
5847 ins_encode %{
5848 Register dst = $dst$$Register;
5849 __ set_narrow_oop((jobject)$src$$constant, dst);
5850 %}
5851 ins_pipe(ialu_hi_lo_reg);
5852 %}
5853
5854 instruct loadConL(iRegL dst, immL src, o7RegL tmp) %{
5855 // %%% maybe this should work like loadConD
5856 match(Set dst src);
5857 effect(KILL tmp);
5858 ins_cost(DEFAULT_COST * 4);
5859 format %{ "SET64 $src,$dst KILL $tmp\t! long" %}
5860 ins_encode( LdImmL(src, dst, tmp) );
5861 ins_pipe(loadConL);
5862 %}
5863
5864 instruct loadConL0( iRegL dst, immL0 src ) %{
5865 match(Set dst src);
5866 ins_cost(DEFAULT_COST);
5867 size(4);
5868 format %{ "CLR $dst\t! long" %}
5869 ins_encode( Set13( src, dst ) );
5870 ins_pipe(ialu_imm);
5871 %}
5872
5873 instruct loadConL13( iRegL dst, immL13 src ) %{
5874 match(Set dst src);
5875 ins_cost(DEFAULT_COST * 2);
5876
5877 size(4);
5878 format %{ "MOV $src,$dst\t! long" %}
5879 ins_encode( Set13( src, dst ) );
5880 ins_pipe(ialu_imm);
5881 %}
5882
5883 instruct loadConF(regF dst, immF src, o7RegP tmp) %{
5884 match(Set dst src);
5885 effect(KILL tmp);
5886
5887 #ifdef _LP64
5888 size(8*4);
5889 #else
5890 size(2*4);
5891 #endif
5892
5893 format %{ "SETHI hi(&$src),$tmp\t!get float $src from table\n\t"
5894 "LDF [$tmp+lo(&$src)],$dst" %}
5895 ins_encode %{
5896 address float_address = __ float_constant($src$$constant);
5897 RelocationHolder rspec = internal_word_Relocation::spec(float_address);
5898 AddressLiteral addrlit(float_address, rspec);
5899
5900 __ sethi(addrlit, $tmp$$Register);
5901 __ ldf(FloatRegisterImpl::S, $tmp$$Register, addrlit.low10(), $dst$$FloatRegister, rspec);
5902 %}
5903 ins_pipe(loadConFD);
5904 %}
5905
5906 instruct loadConD(regD dst, immD src, o7RegP tmp) %{
5907 match(Set dst src);
5908 effect(KILL tmp);
5909
5910 #ifdef _LP64
5911 size(8*4);
5912 #else
5913 size(2*4);
5914 #endif
5915
5916 format %{ "SETHI hi(&$src),$tmp\t!get double $src from table\n\t"
5917 "LDDF [$tmp+lo(&$src)],$dst" %}
5918 ins_encode %{
5919 address double_address = __ double_constant($src$$constant);
5920 RelocationHolder rspec = internal_word_Relocation::spec(double_address);
5921 AddressLiteral addrlit(double_address, rspec);
5922
5923 __ sethi(addrlit, $tmp$$Register);
5924 // XXX This is a quick fix for 6833573.
5925 //__ ldf(FloatRegisterImpl::D, $tmp$$Register, addrlit.low10(), $dst$$FloatRegister, rspec);
5926 __ ldf(FloatRegisterImpl::D, $tmp$$Register, addrlit.low10(), as_DoubleFloatRegister($dst$$reg), rspec);
5927 %}
5928 ins_pipe(loadConFD);
5929 %}
5930
5931 // Prefetch instructions.
5932 // Must be safe to execute with invalid address (cannot fault).
5933
5934 instruct prefetchr( memory mem ) %{
5935 match( PrefetchRead mem );
5936 ins_cost(MEMORY_REF_COST);
5937
5938 format %{ "PREFETCH $mem,0\t! Prefetch read-many" %}
5939 opcode(Assembler::prefetch_op3);
5940 ins_encode( form3_mem_prefetch_read( mem ) );
5941 ins_pipe(iload_mem);
5942 %}
5943
5944 instruct prefetchw( memory mem ) %{
5945 match( PrefetchWrite mem );
5946 ins_cost(MEMORY_REF_COST);
5947
5948 format %{ "PREFETCH $mem,2\t! Prefetch write-many (and read)" %}
5949 opcode(Assembler::prefetch_op3);
5950 ins_encode( form3_mem_prefetch_write( mem ) );
5951 ins_pipe(iload_mem);
5952 %}
5953
5954
5955 //----------Store Instructions-------------------------------------------------
5956 // Store Byte
5957 instruct storeB(memory mem, iRegI src) %{
5958 match(Set mem (StoreB mem src));
5959 ins_cost(MEMORY_REF_COST);
5960
5961 size(4);
5962 format %{ "STB $src,$mem\t! byte" %}
5963 opcode(Assembler::stb_op3);
5964 ins_encode(simple_form3_mem_reg( mem, src ) );
5965 ins_pipe(istore_mem_reg);
5966 %}
5967
5968 instruct storeB0(memory mem, immI0 src) %{
5969 match(Set mem (StoreB mem src));
5970 ins_cost(MEMORY_REF_COST);
5971
5972 size(4);
5973 format %{ "STB $src,$mem\t! byte" %}
5974 opcode(Assembler::stb_op3);
5975 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
5976 ins_pipe(istore_mem_zero);
5977 %}
5978
5979 instruct storeCM0(memory mem, immI0 src) %{
5980 match(Set mem (StoreCM mem src));
5981 ins_cost(MEMORY_REF_COST);
5982
5983 size(4);
5984 format %{ "STB $src,$mem\t! CMS card-mark byte 0" %}
5985 opcode(Assembler::stb_op3);
5986 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
5987 ins_pipe(istore_mem_zero);
5988 %}
5989
5990 // Store Char/Short
5991 instruct storeC(memory mem, iRegI src) %{
5992 match(Set mem (StoreC mem src));
5993 ins_cost(MEMORY_REF_COST);
5994
5995 size(4);
5996 format %{ "STH $src,$mem\t! short" %}
5997 opcode(Assembler::sth_op3);
5998 ins_encode(simple_form3_mem_reg( mem, src ) );
5999 ins_pipe(istore_mem_reg);
6000 %}
6001
6002 instruct storeC0(memory mem, immI0 src) %{
6003 match(Set mem (StoreC mem src));
6004 ins_cost(MEMORY_REF_COST);
6005
6006 size(4);
6007 format %{ "STH $src,$mem\t! short" %}
6008 opcode(Assembler::sth_op3);
6009 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6010 ins_pipe(istore_mem_zero);
6011 %}
6012
6013 // Store Integer
6014 instruct storeI(memory mem, iRegI src) %{
6015 match(Set mem (StoreI mem src));
6016 ins_cost(MEMORY_REF_COST);
6017
6018 size(4);
6019 format %{ "STW $src,$mem" %}
6020 opcode(Assembler::stw_op3);
6021 ins_encode(simple_form3_mem_reg( mem, src ) );
6022 ins_pipe(istore_mem_reg);
6023 %}
6024
6025 // Store Long
6026 instruct storeL(memory mem, iRegL src) %{
6027 match(Set mem (StoreL mem src));
6028 ins_cost(MEMORY_REF_COST);
6029 size(4);
6030 format %{ "STX $src,$mem\t! long" %}
6031 opcode(Assembler::stx_op3);
6032 ins_encode(simple_form3_mem_reg( mem, src ) );
6033 ins_pipe(istore_mem_reg);
6034 %}
6035
6036 instruct storeI0(memory mem, immI0 src) %{
6037 match(Set mem (StoreI mem src));
6038 ins_cost(MEMORY_REF_COST);
6039
6040 size(4);
6041 format %{ "STW $src,$mem" %}
6042 opcode(Assembler::stw_op3);
6043 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6044 ins_pipe(istore_mem_zero);
6045 %}
6046
6047 instruct storeL0(memory mem, immL0 src) %{
6048 match(Set mem (StoreL mem src));
6049 ins_cost(MEMORY_REF_COST);
6050
6051 size(4);
6052 format %{ "STX $src,$mem" %}
6053 opcode(Assembler::stx_op3);
6054 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6055 ins_pipe(istore_mem_zero);
6056 %}
6057
6058 // Store Integer from float register (used after fstoi)
6059 instruct storeI_Freg(memory mem, regF src) %{
6060 match(Set mem (StoreI mem src));
6061 ins_cost(MEMORY_REF_COST);
6062
6063 size(4);
6064 format %{ "STF $src,$mem\t! after fstoi/fdtoi" %}
6065 opcode(Assembler::stf_op3);
6066 ins_encode(simple_form3_mem_reg( mem, src ) );
6067 ins_pipe(fstoreF_mem_reg);
6068 %}
6069
6070 // Store Pointer
6071 instruct storeP(memory dst, sp_ptr_RegP src) %{
6072 match(Set dst (StoreP dst src));
6073 ins_cost(MEMORY_REF_COST);
6074 size(4);
6075
6076 #ifndef _LP64
6077 format %{ "STW $src,$dst\t! ptr" %}
6078 opcode(Assembler::stw_op3, 0, REGP_OP);
6079 #else
6080 format %{ "STX $src,$dst\t! ptr" %}
6081 opcode(Assembler::stx_op3, 0, REGP_OP);
6082 #endif
6083 ins_encode( form3_mem_reg( dst, src ) );
6084 ins_pipe(istore_mem_spORreg);
6085 %}
6086
6087 instruct storeP0(memory dst, immP0 src) %{
6088 match(Set dst (StoreP dst src));
6089 ins_cost(MEMORY_REF_COST);
6090 size(4);
6091
6092 #ifndef _LP64
6093 format %{ "STW $src,$dst\t! ptr" %}
6094 opcode(Assembler::stw_op3, 0, REGP_OP);
6095 #else
6096 format %{ "STX $src,$dst\t! ptr" %}
6097 opcode(Assembler::stx_op3, 0, REGP_OP);
6098 #endif
6099 ins_encode( form3_mem_reg( dst, R_G0 ) );
6100 ins_pipe(istore_mem_zero);
6101 %}
6102
6103 // Store Compressed Pointer
6104 instruct storeN(memory dst, iRegN src) %{
6105 match(Set dst (StoreN dst src));
6106 ins_cost(MEMORY_REF_COST);
6107 size(4);
6108
6109 format %{ "STW $src,$dst\t! compressed ptr" %}
6110 ins_encode %{
6111 Register base = as_Register($dst$$base);
6112 Register index = as_Register($dst$$index);
6113 Register src = $src$$Register;
6114 if (index != G0) {
6115 __ stw(src, base, index);
6116 } else {
6117 __ stw(src, base, $dst$$disp);
6118 }
6119 %}
6120 ins_pipe(istore_mem_spORreg);
6121 %}
6122
6123 instruct storeN0(memory dst, immN0 src) %{
6124 match(Set dst (StoreN dst src));
6125 ins_cost(MEMORY_REF_COST);
6126 size(4);
6127
6128 format %{ "STW $src,$dst\t! compressed ptr" %}
6129 ins_encode %{
6130 Register base = as_Register($dst$$base);
6131 Register index = as_Register($dst$$index);
6132 if (index != G0) {
6133 __ stw(0, base, index);
6134 } else {
6135 __ stw(0, base, $dst$$disp);
6136 }
6137 %}
6138 ins_pipe(istore_mem_zero);
6139 %}
6140
6141 // Store Double
6142 instruct storeD( memory mem, regD src) %{
6143 match(Set mem (StoreD mem src));
6144 ins_cost(MEMORY_REF_COST);
6145
6146 size(4);
6147 format %{ "STDF $src,$mem" %}
6148 opcode(Assembler::stdf_op3);
6149 ins_encode(simple_form3_mem_reg( mem, src ) );
6150 ins_pipe(fstoreD_mem_reg);
6151 %}
6152
6153 instruct storeD0( memory mem, immD0 src) %{
6154 match(Set mem (StoreD mem src));
6155 ins_cost(MEMORY_REF_COST);
6156
6157 size(4);
6158 format %{ "STX $src,$mem" %}
6159 opcode(Assembler::stx_op3);
6160 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6161 ins_pipe(fstoreD_mem_zero);
6162 %}
6163
6164 // Store Float
6165 instruct storeF( memory mem, regF src) %{
6166 match(Set mem (StoreF mem src));
6167 ins_cost(MEMORY_REF_COST);
6168
6169 size(4);
6170 format %{ "STF $src,$mem" %}
6171 opcode(Assembler::stf_op3);
6172 ins_encode(simple_form3_mem_reg( mem, src ) );
6173 ins_pipe(fstoreF_mem_reg);
6174 %}
6175
6176 instruct storeF0( memory mem, immF0 src) %{
6177 match(Set mem (StoreF mem src));
6178 ins_cost(MEMORY_REF_COST);
6179
6180 size(4);
6181 format %{ "STW $src,$mem\t! storeF0" %}
6182 opcode(Assembler::stw_op3);
6183 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6184 ins_pipe(fstoreF_mem_zero);
6185 %}
6186
6187 // Store Aligned Packed Bytes in Double register to memory
6188 instruct storeA8B(memory mem, regD src) %{
6189 match(Set mem (Store8B mem src));
6190 ins_cost(MEMORY_REF_COST);
6191 size(4);
6192 format %{ "STDF $src,$mem\t! packed8B" %}
6193 opcode(Assembler::stdf_op3);
6194 ins_encode(simple_form3_mem_reg( mem, src ) );
6195 ins_pipe(fstoreD_mem_reg);
6196 %}
6197
6198 // Convert oop pointer into compressed form
6199 instruct encodeHeapOop(iRegN dst, iRegP src) %{
6200 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
6201 match(Set dst (EncodeP src));
6202 format %{ "encode_heap_oop $src, $dst" %}
6203 ins_encode %{
6204 __ encode_heap_oop($src$$Register, $dst$$Register);
6205 %}
6206 ins_pipe(ialu_reg);
6207 %}
6208
6209 instruct encodeHeapOop_not_null(iRegN dst, iRegP src) %{
6210 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
6211 match(Set dst (EncodeP src));
6212 format %{ "encode_heap_oop_not_null $src, $dst" %}
6213 ins_encode %{
6214 __ encode_heap_oop_not_null($src$$Register, $dst$$Register);
6215 %}
6216 ins_pipe(ialu_reg);
6217 %}
6218
6219 instruct decodeHeapOop(iRegP dst, iRegN src) %{
6220 predicate(n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull &&
6221 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant);
6222 match(Set dst (DecodeN src));
6223 format %{ "decode_heap_oop $src, $dst" %}
6224 ins_encode %{
6225 __ decode_heap_oop($src$$Register, $dst$$Register);
6226 %}
6227 ins_pipe(ialu_reg);
6228 %}
6229
6230 instruct decodeHeapOop_not_null(iRegP dst, iRegN src) %{
6231 predicate(n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull ||
6232 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant);
6233 match(Set dst (DecodeN src));
6234 format %{ "decode_heap_oop_not_null $src, $dst" %}
6235 ins_encode %{
6236 __ decode_heap_oop_not_null($src$$Register, $dst$$Register);
6237 %}
6238 ins_pipe(ialu_reg);
6239 %}
6240
6241
6242 // Store Zero into Aligned Packed Bytes
6243 instruct storeA8B0(memory mem, immI0 zero) %{
6244 match(Set mem (Store8B mem zero));
6245 ins_cost(MEMORY_REF_COST);
6246 size(4);
6247 format %{ "STX $zero,$mem\t! packed8B" %}
6248 opcode(Assembler::stx_op3);
6249 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6250 ins_pipe(fstoreD_mem_zero);
6251 %}
6252
6253 // Store Aligned Packed Chars/Shorts in Double register to memory
6254 instruct storeA4C(memory mem, regD src) %{
6255 match(Set mem (Store4C mem src));
6256 ins_cost(MEMORY_REF_COST);
6257 size(4);
6258 format %{ "STDF $src,$mem\t! packed4C" %}
6259 opcode(Assembler::stdf_op3);
6260 ins_encode(simple_form3_mem_reg( mem, src ) );
6261 ins_pipe(fstoreD_mem_reg);
6262 %}
6263
6264 // Store Zero into Aligned Packed Chars/Shorts
6265 instruct storeA4C0(memory mem, immI0 zero) %{
6266 match(Set mem (Store4C mem (Replicate4C zero)));
6267 ins_cost(MEMORY_REF_COST);
6268 size(4);
6269 format %{ "STX $zero,$mem\t! packed4C" %}
6270 opcode(Assembler::stx_op3);
6271 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6272 ins_pipe(fstoreD_mem_zero);
6273 %}
6274
6275 // Store Aligned Packed Ints in Double register to memory
6276 instruct storeA2I(memory mem, regD src) %{
6277 match(Set mem (Store2I mem src));
6278 ins_cost(MEMORY_REF_COST);
6279 size(4);
6280 format %{ "STDF $src,$mem\t! packed2I" %}
6281 opcode(Assembler::stdf_op3);
6282 ins_encode(simple_form3_mem_reg( mem, src ) );
6283 ins_pipe(fstoreD_mem_reg);
6284 %}
6285
6286 // Store Zero into Aligned Packed Ints
6287 instruct storeA2I0(memory mem, immI0 zero) %{
6288 match(Set mem (Store2I mem zero));
6289 ins_cost(MEMORY_REF_COST);
6290 size(4);
6291 format %{ "STX $zero,$mem\t! packed2I" %}
6292 opcode(Assembler::stx_op3);
6293 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6294 ins_pipe(fstoreD_mem_zero);
6295 %}
6296
6297
6298 //----------MemBar Instructions-----------------------------------------------
6299 // Memory barrier flavors
6300
6301 instruct membar_acquire() %{
6302 match(MemBarAcquire);
6303 ins_cost(4*MEMORY_REF_COST);
6304
6305 size(0);
6306 format %{ "MEMBAR-acquire" %}
6307 ins_encode( enc_membar_acquire );
6308 ins_pipe(long_memory_op);
6309 %}
6310
6311 instruct membar_acquire_lock() %{
6312 match(MemBarAcquire);
6313 predicate(Matcher::prior_fast_lock(n));
6314 ins_cost(0);
6315
6316 size(0);
6317 format %{ "!MEMBAR-acquire (CAS in prior FastLock so empty encoding)" %}
6318 ins_encode( );
6319 ins_pipe(empty);
6320 %}
6321
6322 instruct membar_release() %{
6323 match(MemBarRelease);
6324 ins_cost(4*MEMORY_REF_COST);
6325
6326 size(0);
6327 format %{ "MEMBAR-release" %}
6328 ins_encode( enc_membar_release );
6329 ins_pipe(long_memory_op);
6330 %}
6331
6332 instruct membar_release_lock() %{
6333 match(MemBarRelease);
6334 predicate(Matcher::post_fast_unlock(n));
6335 ins_cost(0);
6336
6337 size(0);
6338 format %{ "!MEMBAR-release (CAS in succeeding FastUnlock so empty encoding)" %}
6339 ins_encode( );
6340 ins_pipe(empty);
6341 %}
6342
6343 instruct membar_volatile() %{
6344 match(MemBarVolatile);
6345 ins_cost(4*MEMORY_REF_COST);
6346
6347 size(4);
6348 format %{ "MEMBAR-volatile" %}
6349 ins_encode( enc_membar_volatile );
6350 ins_pipe(long_memory_op);
6351 %}
6352
6353 instruct unnecessary_membar_volatile() %{
6354 match(MemBarVolatile);
6355 predicate(Matcher::post_store_load_barrier(n));
6356 ins_cost(0);
6357
6358 size(0);
6359 format %{ "!MEMBAR-volatile (unnecessary so empty encoding)" %}
6360 ins_encode( );
6361 ins_pipe(empty);
6362 %}
6363
6364 //----------Register Move Instructions-----------------------------------------
6365 instruct roundDouble_nop(regD dst) %{
6366 match(Set dst (RoundDouble dst));
6367 ins_cost(0);
6368 // SPARC results are already "rounded" (i.e., normal-format IEEE)
6369 ins_encode( );
6370 ins_pipe(empty);
6371 %}
6372
6373
6374 instruct roundFloat_nop(regF dst) %{
6375 match(Set dst (RoundFloat dst));
6376 ins_cost(0);
6377 // SPARC results are already "rounded" (i.e., normal-format IEEE)
6378 ins_encode( );
6379 ins_pipe(empty);
6380 %}
6381
6382
6383 // Cast Index to Pointer for unsafe natives
6384 instruct castX2P(iRegX src, iRegP dst) %{
6385 match(Set dst (CastX2P src));
6386
6387 format %{ "MOV $src,$dst\t! IntX->Ptr" %}
6388 ins_encode( form3_g0_rs2_rd_move( src, dst ) );
6389 ins_pipe(ialu_reg);
6390 %}
6391
6392 // Cast Pointer to Index for unsafe natives
6393 instruct castP2X(iRegP src, iRegX dst) %{
6394 match(Set dst (CastP2X src));
6395
6396 format %{ "MOV $src,$dst\t! Ptr->IntX" %}
6397 ins_encode( form3_g0_rs2_rd_move( src, dst ) );
6398 ins_pipe(ialu_reg);
6399 %}
6400
6401 instruct stfSSD(stackSlotD stkSlot, regD src) %{
6402 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6403 match(Set stkSlot src); // chain rule
6404 ins_cost(MEMORY_REF_COST);
6405 format %{ "STDF $src,$stkSlot\t!stk" %}
6406 opcode(Assembler::stdf_op3);
6407 ins_encode(simple_form3_mem_reg(stkSlot, src));
6408 ins_pipe(fstoreD_stk_reg);
6409 %}
6410
6411 instruct ldfSSD(regD dst, stackSlotD stkSlot) %{
6412 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6413 match(Set dst stkSlot); // chain rule
6414 ins_cost(MEMORY_REF_COST);
6415 format %{ "LDDF $stkSlot,$dst\t!stk" %}
6416 opcode(Assembler::lddf_op3);
6417 ins_encode(simple_form3_mem_reg(stkSlot, dst));
6418 ins_pipe(floadD_stk);
6419 %}
6420
6421 instruct stfSSF(stackSlotF stkSlot, regF src) %{
6422 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6423 match(Set stkSlot src); // chain rule
6424 ins_cost(MEMORY_REF_COST);
6425 format %{ "STF $src,$stkSlot\t!stk" %}
6426 opcode(Assembler::stf_op3);
6427 ins_encode(simple_form3_mem_reg(stkSlot, src));
6428 ins_pipe(fstoreF_stk_reg);
6429 %}
6430
6431 //----------Conditional Move---------------------------------------------------
6432 // Conditional move
6433 instruct cmovIP_reg(cmpOpP cmp, flagsRegP pcc, iRegI dst, iRegI src) %{
6434 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src)));
6435 ins_cost(150);
6436 format %{ "MOV$cmp $pcc,$src,$dst" %}
6437 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6438 ins_pipe(ialu_reg);
6439 %}
6440
6441 instruct cmovIP_imm(cmpOpP cmp, flagsRegP pcc, iRegI dst, immI11 src) %{
6442 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src)));
6443 ins_cost(140);
6444 format %{ "MOV$cmp $pcc,$src,$dst" %}
6445 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
6446 ins_pipe(ialu_imm);
6447 %}
6448
6449 instruct cmovII_reg(cmpOp cmp, flagsReg icc, iRegI dst, iRegI src) %{
6450 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6451 ins_cost(150);
6452 size(4);
6453 format %{ "MOV$cmp $icc,$src,$dst" %}
6454 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6455 ins_pipe(ialu_reg);
6456 %}
6457
6458 instruct cmovII_imm(cmpOp cmp, flagsReg icc, iRegI dst, immI11 src) %{
6459 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6460 ins_cost(140);
6461 size(4);
6462 format %{ "MOV$cmp $icc,$src,$dst" %}
6463 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6464 ins_pipe(ialu_imm);
6465 %}
6466
6467 instruct cmovII_U_reg(cmpOpU cmp, flagsRegU icc, iRegI dst, iRegI src) %{
6468 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6469 ins_cost(150);
6470 size(4);
6471 format %{ "MOV$cmp $icc,$src,$dst" %}
6472 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6473 ins_pipe(ialu_reg);
6474 %}
6475
6476 instruct cmovII_U_imm(cmpOpU cmp, flagsRegU icc, iRegI dst, immI11 src) %{
6477 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6478 ins_cost(140);
6479 size(4);
6480 format %{ "MOV$cmp $icc,$src,$dst" %}
6481 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6482 ins_pipe(ialu_imm);
6483 %}
6484
6485 instruct cmovIF_reg(cmpOpF cmp, flagsRegF fcc, iRegI dst, iRegI src) %{
6486 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src)));
6487 ins_cost(150);
6488 size(4);
6489 format %{ "MOV$cmp $fcc,$src,$dst" %}
6490 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6491 ins_pipe(ialu_reg);
6492 %}
6493
6494 instruct cmovIF_imm(cmpOpF cmp, flagsRegF fcc, iRegI dst, immI11 src) %{
6495 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src)));
6496 ins_cost(140);
6497 size(4);
6498 format %{ "MOV$cmp $fcc,$src,$dst" %}
6499 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) );
6500 ins_pipe(ialu_imm);
6501 %}
6502
6503 // Conditional move for RegN. Only cmov(reg,reg).
6504 instruct cmovNP_reg(cmpOpP cmp, flagsRegP pcc, iRegN dst, iRegN src) %{
6505 match(Set dst (CMoveN (Binary cmp pcc) (Binary dst src)));
6506 ins_cost(150);
6507 format %{ "MOV$cmp $pcc,$src,$dst" %}
6508 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6509 ins_pipe(ialu_reg);
6510 %}
6511
6512 // This instruction also works with CmpN so we don't need cmovNN_reg.
6513 instruct cmovNI_reg(cmpOp cmp, flagsReg icc, iRegN dst, iRegN src) %{
6514 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src)));
6515 ins_cost(150);
6516 size(4);
6517 format %{ "MOV$cmp $icc,$src,$dst" %}
6518 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6519 ins_pipe(ialu_reg);
6520 %}
6521
6522 instruct cmovNF_reg(cmpOpF cmp, flagsRegF fcc, iRegN dst, iRegN src) %{
6523 match(Set dst (CMoveN (Binary cmp fcc) (Binary dst src)));
6524 ins_cost(150);
6525 size(4);
6526 format %{ "MOV$cmp $fcc,$src,$dst" %}
6527 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6528 ins_pipe(ialu_reg);
6529 %}
6530
6531 // Conditional move
6532 instruct cmovPP_reg(cmpOpP cmp, flagsRegP pcc, iRegP dst, iRegP src) %{
6533 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src)));
6534 ins_cost(150);
6535 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %}
6536 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6537 ins_pipe(ialu_reg);
6538 %}
6539
6540 instruct cmovPP_imm(cmpOpP cmp, flagsRegP pcc, iRegP dst, immP0 src) %{
6541 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src)));
6542 ins_cost(140);
6543 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %}
6544 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
6545 ins_pipe(ialu_imm);
6546 %}
6547
6548 // This instruction also works with CmpN so we don't need cmovPN_reg.
6549 instruct cmovPI_reg(cmpOp cmp, flagsReg icc, iRegP dst, iRegP src) %{
6550 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6551 ins_cost(150);
6552
6553 size(4);
6554 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6555 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6556 ins_pipe(ialu_reg);
6557 %}
6558
6559 instruct cmovPI_imm(cmpOp cmp, flagsReg icc, iRegP dst, immP0 src) %{
6560 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6561 ins_cost(140);
6562
6563 size(4);
6564 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6565 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6566 ins_pipe(ialu_imm);
6567 %}
6568
6569 instruct cmovPF_reg(cmpOpF cmp, flagsRegF fcc, iRegP dst, iRegP src) %{
6570 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src)));
6571 ins_cost(150);
6572 size(4);
6573 format %{ "MOV$cmp $fcc,$src,$dst" %}
6574 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6575 ins_pipe(ialu_imm);
6576 %}
6577
6578 instruct cmovPF_imm(cmpOpF cmp, flagsRegF fcc, iRegP dst, immP0 src) %{
6579 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src)));
6580 ins_cost(140);
6581 size(4);
6582 format %{ "MOV$cmp $fcc,$src,$dst" %}
6583 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) );
6584 ins_pipe(ialu_imm);
6585 %}
6586
6587 // Conditional move
6588 instruct cmovFP_reg(cmpOpP cmp, flagsRegP pcc, regF dst, regF src) %{
6589 match(Set dst (CMoveF (Binary cmp pcc) (Binary dst src)));
6590 ins_cost(150);
6591 opcode(0x101);
6592 format %{ "FMOVD$cmp $pcc,$src,$dst" %}
6593 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6594 ins_pipe(int_conditional_float_move);
6595 %}
6596
6597 instruct cmovFI_reg(cmpOp cmp, flagsReg icc, regF dst, regF src) %{
6598 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src)));
6599 ins_cost(150);
6600
6601 size(4);
6602 format %{ "FMOVS$cmp $icc,$src,$dst" %}
6603 opcode(0x101);
6604 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6605 ins_pipe(int_conditional_float_move);
6606 %}
6607
6608 // Conditional move,
6609 instruct cmovFF_reg(cmpOpF cmp, flagsRegF fcc, regF dst, regF src) %{
6610 match(Set dst (CMoveF (Binary cmp fcc) (Binary dst src)));
6611 ins_cost(150);
6612 size(4);
6613 format %{ "FMOVF$cmp $fcc,$src,$dst" %}
6614 opcode(0x1);
6615 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) );
6616 ins_pipe(int_conditional_double_move);
6617 %}
6618
6619 // Conditional move
6620 instruct cmovDP_reg(cmpOpP cmp, flagsRegP pcc, regD dst, regD src) %{
6621 match(Set dst (CMoveD (Binary cmp pcc) (Binary dst src)));
6622 ins_cost(150);
6623 size(4);
6624 opcode(0x102);
6625 format %{ "FMOVD$cmp $pcc,$src,$dst" %}
6626 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6627 ins_pipe(int_conditional_double_move);
6628 %}
6629
6630 instruct cmovDI_reg(cmpOp cmp, flagsReg icc, regD dst, regD src) %{
6631 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src)));
6632 ins_cost(150);
6633
6634 size(4);
6635 format %{ "FMOVD$cmp $icc,$src,$dst" %}
6636 opcode(0x102);
6637 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6638 ins_pipe(int_conditional_double_move);
6639 %}
6640
6641 // Conditional move,
6642 instruct cmovDF_reg(cmpOpF cmp, flagsRegF fcc, regD dst, regD src) %{
6643 match(Set dst (CMoveD (Binary cmp fcc) (Binary dst src)));
6644 ins_cost(150);
6645 size(4);
6646 format %{ "FMOVD$cmp $fcc,$src,$dst" %}
6647 opcode(0x2);
6648 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) );
6649 ins_pipe(int_conditional_double_move);
6650 %}
6651
6652 // Conditional move
6653 instruct cmovLP_reg(cmpOpP cmp, flagsRegP pcc, iRegL dst, iRegL src) %{
6654 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src)));
6655 ins_cost(150);
6656 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %}
6657 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6658 ins_pipe(ialu_reg);
6659 %}
6660
6661 instruct cmovLP_imm(cmpOpP cmp, flagsRegP pcc, iRegL dst, immI11 src) %{
6662 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src)));
6663 ins_cost(140);
6664 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %}
6665 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
6666 ins_pipe(ialu_imm);
6667 %}
6668
6669 instruct cmovLI_reg(cmpOp cmp, flagsReg icc, iRegL dst, iRegL src) %{
6670 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src)));
6671 ins_cost(150);
6672
6673 size(4);
6674 format %{ "MOV$cmp $icc,$src,$dst\t! long" %}
6675 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6676 ins_pipe(ialu_reg);
6677 %}
6678
6679
6680 instruct cmovLF_reg(cmpOpF cmp, flagsRegF fcc, iRegL dst, iRegL src) %{
6681 match(Set dst (CMoveL (Binary cmp fcc) (Binary dst src)));
6682 ins_cost(150);
6683
6684 size(4);
6685 format %{ "MOV$cmp $fcc,$src,$dst\t! long" %}
6686 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6687 ins_pipe(ialu_reg);
6688 %}
6689
6690
6691
6692 //----------OS and Locking Instructions----------------------------------------
6693
6694 // This name is KNOWN by the ADLC and cannot be changed.
6695 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
6696 // for this guy.
6697 instruct tlsLoadP(g2RegP dst) %{
6698 match(Set dst (ThreadLocal));
6699
6700 size(0);
6701 ins_cost(0);
6702 format %{ "# TLS is in G2" %}
6703 ins_encode( /*empty encoding*/ );
6704 ins_pipe(ialu_none);
6705 %}
6706
6707 instruct checkCastPP( iRegP dst ) %{
6708 match(Set dst (CheckCastPP dst));
6709
6710 size(0);
6711 format %{ "# checkcastPP of $dst" %}
6712 ins_encode( /*empty encoding*/ );
6713 ins_pipe(empty);
6714 %}
6715
6716
6717 instruct castPP( iRegP dst ) %{
6718 match(Set dst (CastPP dst));
6719 format %{ "# castPP of $dst" %}
6720 ins_encode( /*empty encoding*/ );
6721 ins_pipe(empty);
6722 %}
6723
6724 instruct castII( iRegI dst ) %{
6725 match(Set dst (CastII dst));
6726 format %{ "# castII of $dst" %}
6727 ins_encode( /*empty encoding*/ );
6728 ins_cost(0);
6729 ins_pipe(empty);
6730 %}
6731
6732 //----------Arithmetic Instructions--------------------------------------------
6733 // Addition Instructions
6734 // Register Addition
6735 instruct addI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
6736 match(Set dst (AddI src1 src2));
6737
6738 size(4);
6739 format %{ "ADD $src1,$src2,$dst" %}
6740 ins_encode %{
6741 __ add($src1$$Register, $src2$$Register, $dst$$Register);
6742 %}
6743 ins_pipe(ialu_reg_reg);
6744 %}
6745
6746 // Immediate Addition
6747 instruct addI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
6748 match(Set dst (AddI src1 src2));
6749
6750 size(4);
6751 format %{ "ADD $src1,$src2,$dst" %}
6752 opcode(Assembler::add_op3, Assembler::arith_op);
6753 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
6754 ins_pipe(ialu_reg_imm);
6755 %}
6756
6757 // Pointer Register Addition
6758 instruct addP_reg_reg(iRegP dst, iRegP src1, iRegX src2) %{
6759 match(Set dst (AddP src1 src2));
6760
6761 size(4);
6762 format %{ "ADD $src1,$src2,$dst" %}
6763 opcode(Assembler::add_op3, Assembler::arith_op);
6764 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
6765 ins_pipe(ialu_reg_reg);
6766 %}
6767
6768 // Pointer Immediate Addition
6769 instruct addP_reg_imm13(iRegP dst, iRegP src1, immX13 src2) %{
6770 match(Set dst (AddP src1 src2));
6771
6772 size(4);
6773 format %{ "ADD $src1,$src2,$dst" %}
6774 opcode(Assembler::add_op3, Assembler::arith_op);
6775 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
6776 ins_pipe(ialu_reg_imm);
6777 %}
6778
6779 // Long Addition
6780 instruct addL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
6781 match(Set dst (AddL src1 src2));
6782
6783 size(4);
6784 format %{ "ADD $src1,$src2,$dst\t! long" %}
6785 opcode(Assembler::add_op3, Assembler::arith_op);
6786 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
6787 ins_pipe(ialu_reg_reg);
6788 %}
6789
6790 instruct addL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
6791 match(Set dst (AddL src1 con));
6792
6793 size(4);
6794 format %{ "ADD $src1,$con,$dst" %}
6795 opcode(Assembler::add_op3, Assembler::arith_op);
6796 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
6797 ins_pipe(ialu_reg_imm);
6798 %}
6799
6800 //----------Conditional_store--------------------------------------------------
6801 // Conditional-store of the updated heap-top.
6802 // Used during allocation of the shared heap.
6803 // Sets flags (EQ) on success. Implemented with a CASA on Sparc.
6804
6805 // LoadP-locked. Same as a regular pointer load when used with a compare-swap
6806 instruct loadPLocked(iRegP dst, memory mem) %{
6807 match(Set dst (LoadPLocked mem));
6808 ins_cost(MEMORY_REF_COST);
6809
6810 #ifndef _LP64
6811 size(4);
6812 format %{ "LDUW $mem,$dst\t! ptr" %}
6813 opcode(Assembler::lduw_op3, 0, REGP_OP);
6814 #else
6815 format %{ "LDX $mem,$dst\t! ptr" %}
6816 opcode(Assembler::ldx_op3, 0, REGP_OP);
6817 #endif
6818 ins_encode( form3_mem_reg( mem, dst ) );
6819 ins_pipe(iload_mem);
6820 %}
6821
6822 // LoadL-locked. Same as a regular long load when used with a compare-swap
6823 instruct loadLLocked(iRegL dst, memory mem) %{
6824 match(Set dst (LoadLLocked mem));
6825 ins_cost(MEMORY_REF_COST);
6826 size(4);
6827 format %{ "LDX $mem,$dst\t! long" %}
6828 opcode(Assembler::ldx_op3);
6829 ins_encode(simple_form3_mem_reg( mem, dst ) );
6830 ins_pipe(iload_mem);
6831 %}
6832
6833 instruct storePConditional( iRegP heap_top_ptr, iRegP oldval, g3RegP newval, flagsRegP pcc ) %{
6834 match(Set pcc (StorePConditional heap_top_ptr (Binary oldval newval)));
6835 effect( KILL newval );
6836 format %{ "CASA [$heap_top_ptr],$oldval,R_G3\t! If $oldval==[$heap_top_ptr] Then store R_G3 into [$heap_top_ptr], set R_G3=[$heap_top_ptr] in any case\n\t"
6837 "CMP R_G3,$oldval\t\t! See if we made progress" %}
6838 ins_encode( enc_cas(heap_top_ptr,oldval,newval) );
6839 ins_pipe( long_memory_op );
6840 %}
6841
6842 // Conditional-store of an int value.
6843 instruct storeIConditional( iRegP mem_ptr, iRegI oldval, g3RegI newval, flagsReg icc ) %{
6844 match(Set icc (StoreIConditional mem_ptr (Binary oldval newval)));
6845 effect( KILL newval );
6846 format %{ "CASA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t"
6847 "CMP $oldval,$newval\t\t! See if we made progress" %}
6848 ins_encode( enc_cas(mem_ptr,oldval,newval) );
6849 ins_pipe( long_memory_op );
6850 %}
6851
6852 // Conditional-store of a long value.
6853 instruct storeLConditional( iRegP mem_ptr, iRegL oldval, g3RegL newval, flagsRegL xcc ) %{
6854 match(Set xcc (StoreLConditional mem_ptr (Binary oldval newval)));
6855 effect( KILL newval );
6856 format %{ "CASXA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t"
6857 "CMP $oldval,$newval\t\t! See if we made progress" %}
6858 ins_encode( enc_cas(mem_ptr,oldval,newval) );
6859 ins_pipe( long_memory_op );
6860 %}
6861
6862 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
6863
6864 instruct compareAndSwapL_bool(iRegP mem_ptr, iRegL oldval, iRegL newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
6865 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
6866 effect( USE mem_ptr, KILL ccr, KILL tmp1);
6867 format %{
6868 "MOV $newval,O7\n\t"
6869 "CASXA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
6870 "CMP $oldval,O7\t\t! See if we made progress\n\t"
6871 "MOV 1,$res\n\t"
6872 "MOVne xcc,R_G0,$res"
6873 %}
6874 ins_encode( enc_casx(mem_ptr, oldval, newval),
6875 enc_lflags_ne_to_boolean(res) );
6876 ins_pipe( long_memory_op );
6877 %}
6878
6879
6880 instruct compareAndSwapI_bool(iRegP mem_ptr, iRegI oldval, iRegI newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
6881 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
6882 effect( USE mem_ptr, KILL ccr, KILL tmp1);
6883 format %{
6884 "MOV $newval,O7\n\t"
6885 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
6886 "CMP $oldval,O7\t\t! See if we made progress\n\t"
6887 "MOV 1,$res\n\t"
6888 "MOVne icc,R_G0,$res"
6889 %}
6890 ins_encode( enc_casi(mem_ptr, oldval, newval),
6891 enc_iflags_ne_to_boolean(res) );
6892 ins_pipe( long_memory_op );
6893 %}
6894
6895 instruct compareAndSwapP_bool(iRegP mem_ptr, iRegP oldval, iRegP newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
6896 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
6897 effect( USE mem_ptr, KILL ccr, KILL tmp1);
6898 format %{
6899 "MOV $newval,O7\n\t"
6900 "CASA_PTR [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
6901 "CMP $oldval,O7\t\t! See if we made progress\n\t"
6902 "MOV 1,$res\n\t"
6903 "MOVne xcc,R_G0,$res"
6904 %}
6905 #ifdef _LP64
6906 ins_encode( enc_casx(mem_ptr, oldval, newval),
6907 enc_lflags_ne_to_boolean(res) );
6908 #else
6909 ins_encode( enc_casi(mem_ptr, oldval, newval),
6910 enc_iflags_ne_to_boolean(res) );
6911 #endif
6912 ins_pipe( long_memory_op );
6913 %}
6914
6915 instruct compareAndSwapN_bool(iRegP mem_ptr, iRegN oldval, iRegN newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
6916 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval)));
6917 effect( USE mem_ptr, KILL ccr, KILL tmp1);
6918 format %{
6919 "MOV $newval,O7\n\t"
6920 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
6921 "CMP $oldval,O7\t\t! See if we made progress\n\t"
6922 "MOV 1,$res\n\t"
6923 "MOVne icc,R_G0,$res"
6924 %}
6925 ins_encode( enc_casi(mem_ptr, oldval, newval),
6926 enc_iflags_ne_to_boolean(res) );
6927 ins_pipe( long_memory_op );
6928 %}
6929
6930 //---------------------
6931 // Subtraction Instructions
6932 // Register Subtraction
6933 instruct subI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
6934 match(Set dst (SubI src1 src2));
6935
6936 size(4);
6937 format %{ "SUB $src1,$src2,$dst" %}
6938 opcode(Assembler::sub_op3, Assembler::arith_op);
6939 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
6940 ins_pipe(ialu_reg_reg);
6941 %}
6942
6943 // Immediate Subtraction
6944 instruct subI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
6945 match(Set dst (SubI src1 src2));
6946
6947 size(4);
6948 format %{ "SUB $src1,$src2,$dst" %}
6949 opcode(Assembler::sub_op3, Assembler::arith_op);
6950 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
6951 ins_pipe(ialu_reg_imm);
6952 %}
6953
6954 instruct subI_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{
6955 match(Set dst (SubI zero src2));
6956
6957 size(4);
6958 format %{ "NEG $src2,$dst" %}
6959 opcode(Assembler::sub_op3, Assembler::arith_op);
6960 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) );
6961 ins_pipe(ialu_zero_reg);
6962 %}
6963
6964 // Long subtraction
6965 instruct subL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
6966 match(Set dst (SubL src1 src2));
6967
6968 size(4);
6969 format %{ "SUB $src1,$src2,$dst\t! long" %}
6970 opcode(Assembler::sub_op3, Assembler::arith_op);
6971 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
6972 ins_pipe(ialu_reg_reg);
6973 %}
6974
6975 // Immediate Subtraction
6976 instruct subL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
6977 match(Set dst (SubL src1 con));
6978
6979 size(4);
6980 format %{ "SUB $src1,$con,$dst\t! long" %}
6981 opcode(Assembler::sub_op3, Assembler::arith_op);
6982 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
6983 ins_pipe(ialu_reg_imm);
6984 %}
6985
6986 // Long negation
6987 instruct negL_reg_reg(iRegL dst, immL0 zero, iRegL src2) %{
6988 match(Set dst (SubL zero src2));
6989
6990 size(4);
6991 format %{ "NEG $src2,$dst\t! long" %}
6992 opcode(Assembler::sub_op3, Assembler::arith_op);
6993 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) );
6994 ins_pipe(ialu_zero_reg);
6995 %}
6996
6997 // Multiplication Instructions
6998 // Integer Multiplication
6999 // Register Multiplication
7000 instruct mulI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7001 match(Set dst (MulI src1 src2));
7002
7003 size(4);
7004 format %{ "MULX $src1,$src2,$dst" %}
7005 opcode(Assembler::mulx_op3, Assembler::arith_op);
7006 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7007 ins_pipe(imul_reg_reg);
7008 %}
7009
7010 // Immediate Multiplication
7011 instruct mulI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7012 match(Set dst (MulI src1 src2));
7013
7014 size(4);
7015 format %{ "MULX $src1,$src2,$dst" %}
7016 opcode(Assembler::mulx_op3, Assembler::arith_op);
7017 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7018 ins_pipe(imul_reg_imm);
7019 %}
7020
7021 instruct mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7022 match(Set dst (MulL src1 src2));
7023 ins_cost(DEFAULT_COST * 5);
7024 size(4);
7025 format %{ "MULX $src1,$src2,$dst\t! long" %}
7026 opcode(Assembler::mulx_op3, Assembler::arith_op);
7027 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7028 ins_pipe(mulL_reg_reg);
7029 %}
7030
7031 // Immediate Multiplication
7032 instruct mulL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7033 match(Set dst (MulL src1 src2));
7034 ins_cost(DEFAULT_COST * 5);
7035 size(4);
7036 format %{ "MULX $src1,$src2,$dst" %}
7037 opcode(Assembler::mulx_op3, Assembler::arith_op);
7038 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7039 ins_pipe(mulL_reg_imm);
7040 %}
7041
7042 // Integer Division
7043 // Register Division
7044 instruct divI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2) %{
7045 match(Set dst (DivI src1 src2));
7046 ins_cost((2+71)*DEFAULT_COST);
7047
7048 format %{ "SRA $src2,0,$src2\n\t"
7049 "SRA $src1,0,$src1\n\t"
7050 "SDIVX $src1,$src2,$dst" %}
7051 ins_encode( idiv_reg( src1, src2, dst ) );
7052 ins_pipe(sdiv_reg_reg);
7053 %}
7054
7055 // Immediate Division
7056 instruct divI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2) %{
7057 match(Set dst (DivI src1 src2));
7058 ins_cost((2+71)*DEFAULT_COST);
7059
7060 format %{ "SRA $src1,0,$src1\n\t"
7061 "SDIVX $src1,$src2,$dst" %}
7062 ins_encode( idiv_imm( src1, src2, dst ) );
7063 ins_pipe(sdiv_reg_imm);
7064 %}
7065
7066 //----------Div-By-10-Expansion------------------------------------------------
7067 // Extract hi bits of a 32x32->64 bit multiply.
7068 // Expand rule only, not matched
7069 instruct mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2 ) %{
7070 effect( DEF dst, USE src1, USE src2 );
7071 format %{ "MULX $src1,$src2,$dst\t! Used in div-by-10\n\t"
7072 "SRLX $dst,#32,$dst\t\t! Extract only hi word of result" %}
7073 ins_encode( enc_mul_hi(dst,src1,src2));
7074 ins_pipe(sdiv_reg_reg);
7075 %}
7076
7077 // Magic constant, reciprocal of 10
7078 instruct loadConI_x66666667(iRegIsafe dst) %{
7079 effect( DEF dst );
7080
7081 size(8);
7082 format %{ "SET 0x66666667,$dst\t! Used in div-by-10" %}
7083 ins_encode( Set32(0x66666667, dst) );
7084 ins_pipe(ialu_hi_lo_reg);
7085 %}
7086
7087 // Register Shift Right Arithmetic Long by 32-63
7088 instruct sra_31( iRegI dst, iRegI src ) %{
7089 effect( DEF dst, USE src );
7090 format %{ "SRA $src,31,$dst\t! Used in div-by-10" %}
7091 ins_encode( form3_rs1_rd_copysign_hi(src,dst) );
7092 ins_pipe(ialu_reg_reg);
7093 %}
7094
7095 // Arithmetic Shift Right by 8-bit immediate
7096 instruct sra_reg_2( iRegI dst, iRegI src ) %{
7097 effect( DEF dst, USE src );
7098 format %{ "SRA $src,2,$dst\t! Used in div-by-10" %}
7099 opcode(Assembler::sra_op3, Assembler::arith_op);
7100 ins_encode( form3_rs1_simm13_rd( src, 0x2, dst ) );
7101 ins_pipe(ialu_reg_imm);
7102 %}
7103
7104 // Integer DIV with 10
7105 instruct divI_10( iRegI dst, iRegIsafe src, immI10 div ) %{
7106 match(Set dst (DivI src div));
7107 ins_cost((6+6)*DEFAULT_COST);
7108 expand %{
7109 iRegIsafe tmp1; // Killed temps;
7110 iRegIsafe tmp2; // Killed temps;
7111 iRegI tmp3; // Killed temps;
7112 iRegI tmp4; // Killed temps;
7113 loadConI_x66666667( tmp1 ); // SET 0x66666667 -> tmp1
7114 mul_hi( tmp2, src, tmp1 ); // MUL hibits(src * tmp1) -> tmp2
7115 sra_31( tmp3, src ); // SRA src,31 -> tmp3
7116 sra_reg_2( tmp4, tmp2 ); // SRA tmp2,2 -> tmp4
7117 subI_reg_reg( dst,tmp4,tmp3); // SUB tmp4 - tmp3 -> dst
7118 %}
7119 %}
7120
7121 // Register Long Division
7122 instruct divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7123 match(Set dst (DivL src1 src2));
7124 ins_cost(DEFAULT_COST*71);
7125 size(4);
7126 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7127 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7128 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7129 ins_pipe(divL_reg_reg);
7130 %}
7131
7132 // Register Long Division
7133 instruct divL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7134 match(Set dst (DivL src1 src2));
7135 ins_cost(DEFAULT_COST*71);
7136 size(4);
7137 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7138 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7139 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7140 ins_pipe(divL_reg_imm);
7141 %}
7142
7143 // Integer Remainder
7144 // Register Remainder
7145 instruct modI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2, o7RegP temp, flagsReg ccr ) %{
7146 match(Set dst (ModI src1 src2));
7147 effect( KILL ccr, KILL temp);
7148
7149 format %{ "SREM $src1,$src2,$dst" %}
7150 ins_encode( irem_reg(src1, src2, dst, temp) );
7151 ins_pipe(sdiv_reg_reg);
7152 %}
7153
7154 // Immediate Remainder
7155 instruct modI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2, o7RegP temp, flagsReg ccr ) %{
7156 match(Set dst (ModI src1 src2));
7157 effect( KILL ccr, KILL temp);
7158
7159 format %{ "SREM $src1,$src2,$dst" %}
7160 ins_encode( irem_imm(src1, src2, dst, temp) );
7161 ins_pipe(sdiv_reg_imm);
7162 %}
7163
7164 // Register Long Remainder
7165 instruct divL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7166 effect(DEF dst, USE src1, USE src2);
7167 size(4);
7168 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7169 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7170 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7171 ins_pipe(divL_reg_reg);
7172 %}
7173
7174 // Register Long Division
7175 instruct divL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{
7176 effect(DEF dst, USE src1, USE src2);
7177 size(4);
7178 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7179 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7180 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7181 ins_pipe(divL_reg_imm);
7182 %}
7183
7184 instruct mulL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7185 effect(DEF dst, USE src1, USE src2);
7186 size(4);
7187 format %{ "MULX $src1,$src2,$dst\t! long" %}
7188 opcode(Assembler::mulx_op3, Assembler::arith_op);
7189 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7190 ins_pipe(mulL_reg_reg);
7191 %}
7192
7193 // Immediate Multiplication
7194 instruct mulL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{
7195 effect(DEF dst, USE src1, USE src2);
7196 size(4);
7197 format %{ "MULX $src1,$src2,$dst" %}
7198 opcode(Assembler::mulx_op3, Assembler::arith_op);
7199 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7200 ins_pipe(mulL_reg_imm);
7201 %}
7202
7203 instruct subL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7204 effect(DEF dst, USE src1, USE src2);
7205 size(4);
7206 format %{ "SUB $src1,$src2,$dst\t! long" %}
7207 opcode(Assembler::sub_op3, Assembler::arith_op);
7208 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7209 ins_pipe(ialu_reg_reg);
7210 %}
7211
7212 instruct subL_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{
7213 effect(DEF dst, USE src1, USE src2);
7214 size(4);
7215 format %{ "SUB $src1,$src2,$dst\t! long" %}
7216 opcode(Assembler::sub_op3, Assembler::arith_op);
7217 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7218 ins_pipe(ialu_reg_reg);
7219 %}
7220
7221 // Register Long Remainder
7222 instruct modL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7223 match(Set dst (ModL src1 src2));
7224 ins_cost(DEFAULT_COST*(71 + 6 + 1));
7225 expand %{
7226 iRegL tmp1;
7227 iRegL tmp2;
7228 divL_reg_reg_1(tmp1, src1, src2);
7229 mulL_reg_reg_1(tmp2, tmp1, src2);
7230 subL_reg_reg_1(dst, src1, tmp2);
7231 %}
7232 %}
7233
7234 // Register Long Remainder
7235 instruct modL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7236 match(Set dst (ModL src1 src2));
7237 ins_cost(DEFAULT_COST*(71 + 6 + 1));
7238 expand %{
7239 iRegL tmp1;
7240 iRegL tmp2;
7241 divL_reg_imm13_1(tmp1, src1, src2);
7242 mulL_reg_imm13_1(tmp2, tmp1, src2);
7243 subL_reg_reg_2 (dst, src1, tmp2);
7244 %}
7245 %}
7246
7247 // Integer Shift Instructions
7248 // Register Shift Left
7249 instruct shlI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7250 match(Set dst (LShiftI src1 src2));
7251
7252 size(4);
7253 format %{ "SLL $src1,$src2,$dst" %}
7254 opcode(Assembler::sll_op3, Assembler::arith_op);
7255 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7256 ins_pipe(ialu_reg_reg);
7257 %}
7258
7259 // Register Shift Left Immediate
7260 instruct shlI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7261 match(Set dst (LShiftI src1 src2));
7262
7263 size(4);
7264 format %{ "SLL $src1,$src2,$dst" %}
7265 opcode(Assembler::sll_op3, Assembler::arith_op);
7266 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7267 ins_pipe(ialu_reg_imm);
7268 %}
7269
7270 // Register Shift Left
7271 instruct shlL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7272 match(Set dst (LShiftL src1 src2));
7273
7274 size(4);
7275 format %{ "SLLX $src1,$src2,$dst" %}
7276 opcode(Assembler::sllx_op3, Assembler::arith_op);
7277 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7278 ins_pipe(ialu_reg_reg);
7279 %}
7280
7281 // Register Shift Left Immediate
7282 instruct shlL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7283 match(Set dst (LShiftL src1 src2));
7284
7285 size(4);
7286 format %{ "SLLX $src1,$src2,$dst" %}
7287 opcode(Assembler::sllx_op3, Assembler::arith_op);
7288 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7289 ins_pipe(ialu_reg_imm);
7290 %}
7291
7292 // Register Arithmetic Shift Right
7293 instruct sarI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7294 match(Set dst (RShiftI src1 src2));
7295 size(4);
7296 format %{ "SRA $src1,$src2,$dst" %}
7297 opcode(Assembler::sra_op3, Assembler::arith_op);
7298 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7299 ins_pipe(ialu_reg_reg);
7300 %}
7301
7302 // Register Arithmetic Shift Right Immediate
7303 instruct sarI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7304 match(Set dst (RShiftI src1 src2));
7305
7306 size(4);
7307 format %{ "SRA $src1,$src2,$dst" %}
7308 opcode(Assembler::sra_op3, Assembler::arith_op);
7309 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7310 ins_pipe(ialu_reg_imm);
7311 %}
7312
7313 // Register Shift Right Arithmatic Long
7314 instruct sarL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7315 match(Set dst (RShiftL src1 src2));
7316
7317 size(4);
7318 format %{ "SRAX $src1,$src2,$dst" %}
7319 opcode(Assembler::srax_op3, Assembler::arith_op);
7320 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7321 ins_pipe(ialu_reg_reg);
7322 %}
7323
7324 // Register Shift Left Immediate
7325 instruct sarL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7326 match(Set dst (RShiftL src1 src2));
7327
7328 size(4);
7329 format %{ "SRAX $src1,$src2,$dst" %}
7330 opcode(Assembler::srax_op3, Assembler::arith_op);
7331 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7332 ins_pipe(ialu_reg_imm);
7333 %}
7334
7335 // Register Shift Right
7336 instruct shrI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7337 match(Set dst (URShiftI src1 src2));
7338
7339 size(4);
7340 format %{ "SRL $src1,$src2,$dst" %}
7341 opcode(Assembler::srl_op3, Assembler::arith_op);
7342 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7343 ins_pipe(ialu_reg_reg);
7344 %}
7345
7346 // Register Shift Right Immediate
7347 instruct shrI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7348 match(Set dst (URShiftI src1 src2));
7349
7350 size(4);
7351 format %{ "SRL $src1,$src2,$dst" %}
7352 opcode(Assembler::srl_op3, Assembler::arith_op);
7353 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7354 ins_pipe(ialu_reg_imm);
7355 %}
7356
7357 // Register Shift Right
7358 instruct shrL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7359 match(Set dst (URShiftL src1 src2));
7360
7361 size(4);
7362 format %{ "SRLX $src1,$src2,$dst" %}
7363 opcode(Assembler::srlx_op3, Assembler::arith_op);
7364 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7365 ins_pipe(ialu_reg_reg);
7366 %}
7367
7368 // Register Shift Right Immediate
7369 instruct shrL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7370 match(Set dst (URShiftL src1 src2));
7371
7372 size(4);
7373 format %{ "SRLX $src1,$src2,$dst" %}
7374 opcode(Assembler::srlx_op3, Assembler::arith_op);
7375 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7376 ins_pipe(ialu_reg_imm);
7377 %}
7378
7379 // Register Shift Right Immediate with a CastP2X
7380 #ifdef _LP64
7381 instruct shrP_reg_imm6(iRegL dst, iRegP src1, immU6 src2) %{
7382 match(Set dst (URShiftL (CastP2X src1) src2));
7383 size(4);
7384 format %{ "SRLX $src1,$src2,$dst\t! Cast ptr $src1 to long and shift" %}
7385 opcode(Assembler::srlx_op3, Assembler::arith_op);
7386 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7387 ins_pipe(ialu_reg_imm);
7388 %}
7389 #else
7390 instruct shrP_reg_imm5(iRegI dst, iRegP src1, immU5 src2) %{
7391 match(Set dst (URShiftI (CastP2X src1) src2));
7392 size(4);
7393 format %{ "SRL $src1,$src2,$dst\t! Cast ptr $src1 to int and shift" %}
7394 opcode(Assembler::srl_op3, Assembler::arith_op);
7395 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7396 ins_pipe(ialu_reg_imm);
7397 %}
7398 #endif
7399
7400
7401 //----------Floating Point Arithmetic Instructions-----------------------------
7402
7403 // Add float single precision
7404 instruct addF_reg_reg(regF dst, regF src1, regF src2) %{
7405 match(Set dst (AddF src1 src2));
7406
7407 size(4);
7408 format %{ "FADDS $src1,$src2,$dst" %}
7409 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fadds_opf);
7410 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7411 ins_pipe(faddF_reg_reg);
7412 %}
7413
7414 // Add float double precision
7415 instruct addD_reg_reg(regD dst, regD src1, regD src2) %{
7416 match(Set dst (AddD src1 src2));
7417
7418 size(4);
7419 format %{ "FADDD $src1,$src2,$dst" %}
7420 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf);
7421 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7422 ins_pipe(faddD_reg_reg);
7423 %}
7424
7425 // Sub float single precision
7426 instruct subF_reg_reg(regF dst, regF src1, regF src2) %{
7427 match(Set dst (SubF src1 src2));
7428
7429 size(4);
7430 format %{ "FSUBS $src1,$src2,$dst" %}
7431 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubs_opf);
7432 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7433 ins_pipe(faddF_reg_reg);
7434 %}
7435
7436 // Sub float double precision
7437 instruct subD_reg_reg(regD dst, regD src1, regD src2) %{
7438 match(Set dst (SubD src1 src2));
7439
7440 size(4);
7441 format %{ "FSUBD $src1,$src2,$dst" %}
7442 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf);
7443 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7444 ins_pipe(faddD_reg_reg);
7445 %}
7446
7447 // Mul float single precision
7448 instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{
7449 match(Set dst (MulF src1 src2));
7450
7451 size(4);
7452 format %{ "FMULS $src1,$src2,$dst" %}
7453 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuls_opf);
7454 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7455 ins_pipe(fmulF_reg_reg);
7456 %}
7457
7458 // Mul float double precision
7459 instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{
7460 match(Set dst (MulD src1 src2));
7461
7462 size(4);
7463 format %{ "FMULD $src1,$src2,$dst" %}
7464 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf);
7465 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7466 ins_pipe(fmulD_reg_reg);
7467 %}
7468
7469 // Div float single precision
7470 instruct divF_reg_reg(regF dst, regF src1, regF src2) %{
7471 match(Set dst (DivF src1 src2));
7472
7473 size(4);
7474 format %{ "FDIVS $src1,$src2,$dst" %}
7475 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivs_opf);
7476 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7477 ins_pipe(fdivF_reg_reg);
7478 %}
7479
7480 // Div float double precision
7481 instruct divD_reg_reg(regD dst, regD src1, regD src2) %{
7482 match(Set dst (DivD src1 src2));
7483
7484 size(4);
7485 format %{ "FDIVD $src1,$src2,$dst" %}
7486 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivd_opf);
7487 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7488 ins_pipe(fdivD_reg_reg);
7489 %}
7490
7491 // Absolute float double precision
7492 instruct absD_reg(regD dst, regD src) %{
7493 match(Set dst (AbsD src));
7494
7495 format %{ "FABSd $src,$dst" %}
7496 ins_encode(fabsd(dst, src));
7497 ins_pipe(faddD_reg);
7498 %}
7499
7500 // Absolute float single precision
7501 instruct absF_reg(regF dst, regF src) %{
7502 match(Set dst (AbsF src));
7503
7504 format %{ "FABSs $src,$dst" %}
7505 ins_encode(fabss(dst, src));
7506 ins_pipe(faddF_reg);
7507 %}
7508
7509 instruct negF_reg(regF dst, regF src) %{
7510 match(Set dst (NegF src));
7511
7512 size(4);
7513 format %{ "FNEGs $src,$dst" %}
7514 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fnegs_opf);
7515 ins_encode(form3_opf_rs2F_rdF(src, dst));
7516 ins_pipe(faddF_reg);
7517 %}
7518
7519 instruct negD_reg(regD dst, regD src) %{
7520 match(Set dst (NegD src));
7521
7522 format %{ "FNEGd $src,$dst" %}
7523 ins_encode(fnegd(dst, src));
7524 ins_pipe(faddD_reg);
7525 %}
7526
7527 // Sqrt float double precision
7528 instruct sqrtF_reg_reg(regF dst, regF src) %{
7529 match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
7530
7531 size(4);
7532 format %{ "FSQRTS $src,$dst" %}
7533 ins_encode(fsqrts(dst, src));
7534 ins_pipe(fdivF_reg_reg);
7535 %}
7536
7537 // Sqrt float double precision
7538 instruct sqrtD_reg_reg(regD dst, regD src) %{
7539 match(Set dst (SqrtD src));
7540
7541 size(4);
7542 format %{ "FSQRTD $src,$dst" %}
7543 ins_encode(fsqrtd(dst, src));
7544 ins_pipe(fdivD_reg_reg);
7545 %}
7546
7547 //----------Logical Instructions-----------------------------------------------
7548 // And Instructions
7549 // Register And
7550 instruct andI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7551 match(Set dst (AndI src1 src2));
7552
7553 size(4);
7554 format %{ "AND $src1,$src2,$dst" %}
7555 opcode(Assembler::and_op3, Assembler::arith_op);
7556 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7557 ins_pipe(ialu_reg_reg);
7558 %}
7559
7560 // Immediate And
7561 instruct andI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7562 match(Set dst (AndI src1 src2));
7563
7564 size(4);
7565 format %{ "AND $src1,$src2,$dst" %}
7566 opcode(Assembler::and_op3, Assembler::arith_op);
7567 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7568 ins_pipe(ialu_reg_imm);
7569 %}
7570
7571 // Register And Long
7572 instruct andL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7573 match(Set dst (AndL src1 src2));
7574
7575 ins_cost(DEFAULT_COST);
7576 size(4);
7577 format %{ "AND $src1,$src2,$dst\t! long" %}
7578 opcode(Assembler::and_op3, Assembler::arith_op);
7579 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7580 ins_pipe(ialu_reg_reg);
7581 %}
7582
7583 instruct andL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7584 match(Set dst (AndL src1 con));
7585
7586 ins_cost(DEFAULT_COST);
7587 size(4);
7588 format %{ "AND $src1,$con,$dst\t! long" %}
7589 opcode(Assembler::and_op3, Assembler::arith_op);
7590 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7591 ins_pipe(ialu_reg_imm);
7592 %}
7593
7594 // Or Instructions
7595 // Register Or
7596 instruct orI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7597 match(Set dst (OrI src1 src2));
7598
7599 size(4);
7600 format %{ "OR $src1,$src2,$dst" %}
7601 opcode(Assembler::or_op3, Assembler::arith_op);
7602 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7603 ins_pipe(ialu_reg_reg);
7604 %}
7605
7606 // Immediate Or
7607 instruct orI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7608 match(Set dst (OrI src1 src2));
7609
7610 size(4);
7611 format %{ "OR $src1,$src2,$dst" %}
7612 opcode(Assembler::or_op3, Assembler::arith_op);
7613 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7614 ins_pipe(ialu_reg_imm);
7615 %}
7616
7617 // Register Or Long
7618 instruct orL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7619 match(Set dst (OrL src1 src2));
7620
7621 ins_cost(DEFAULT_COST);
7622 size(4);
7623 format %{ "OR $src1,$src2,$dst\t! long" %}
7624 opcode(Assembler::or_op3, Assembler::arith_op);
7625 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7626 ins_pipe(ialu_reg_reg);
7627 %}
7628
7629 instruct orL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7630 match(Set dst (OrL src1 con));
7631 ins_cost(DEFAULT_COST*2);
7632
7633 ins_cost(DEFAULT_COST);
7634 size(4);
7635 format %{ "OR $src1,$con,$dst\t! long" %}
7636 opcode(Assembler::or_op3, Assembler::arith_op);
7637 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7638 ins_pipe(ialu_reg_imm);
7639 %}
7640
7641 #ifndef _LP64
7642
7643 // Use sp_ptr_RegP to match G2 (TLS register) without spilling.
7644 instruct orI_reg_castP2X(iRegI dst, iRegI src1, sp_ptr_RegP src2) %{
7645 match(Set dst (OrI src1 (CastP2X src2)));
7646
7647 size(4);
7648 format %{ "OR $src1,$src2,$dst" %}
7649 opcode(Assembler::or_op3, Assembler::arith_op);
7650 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7651 ins_pipe(ialu_reg_reg);
7652 %}
7653
7654 #else
7655
7656 instruct orL_reg_castP2X(iRegL dst, iRegL src1, sp_ptr_RegP src2) %{
7657 match(Set dst (OrL src1 (CastP2X src2)));
7658
7659 ins_cost(DEFAULT_COST);
7660 size(4);
7661 format %{ "OR $src1,$src2,$dst\t! long" %}
7662 opcode(Assembler::or_op3, Assembler::arith_op);
7663 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7664 ins_pipe(ialu_reg_reg);
7665 %}
7666
7667 #endif
7668
7669 // Xor Instructions
7670 // Register Xor
7671 instruct xorI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7672 match(Set dst (XorI src1 src2));
7673
7674 size(4);
7675 format %{ "XOR $src1,$src2,$dst" %}
7676 opcode(Assembler::xor_op3, Assembler::arith_op);
7677 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7678 ins_pipe(ialu_reg_reg);
7679 %}
7680
7681 // Immediate Xor
7682 instruct xorI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7683 match(Set dst (XorI src1 src2));
7684
7685 size(4);
7686 format %{ "XOR $src1,$src2,$dst" %}
7687 opcode(Assembler::xor_op3, Assembler::arith_op);
7688 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7689 ins_pipe(ialu_reg_imm);
7690 %}
7691
7692 // Register Xor Long
7693 instruct xorL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7694 match(Set dst (XorL src1 src2));
7695
7696 ins_cost(DEFAULT_COST);
7697 size(4);
7698 format %{ "XOR $src1,$src2,$dst\t! long" %}
7699 opcode(Assembler::xor_op3, Assembler::arith_op);
7700 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7701 ins_pipe(ialu_reg_reg);
7702 %}
7703
7704 instruct xorL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7705 match(Set dst (XorL src1 con));
7706
7707 ins_cost(DEFAULT_COST);
7708 size(4);
7709 format %{ "XOR $src1,$con,$dst\t! long" %}
7710 opcode(Assembler::xor_op3, Assembler::arith_op);
7711 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7712 ins_pipe(ialu_reg_imm);
7713 %}
7714
7715 //----------Convert to Boolean-------------------------------------------------
7716 // Nice hack for 32-bit tests but doesn't work for
7717 // 64-bit pointers.
7718 instruct convI2B( iRegI dst, iRegI src, flagsReg ccr ) %{
7719 match(Set dst (Conv2B src));
7720 effect( KILL ccr );
7721 ins_cost(DEFAULT_COST*2);
7722 format %{ "CMP R_G0,$src\n\t"
7723 "ADDX R_G0,0,$dst" %}
7724 ins_encode( enc_to_bool( src, dst ) );
7725 ins_pipe(ialu_reg_ialu);
7726 %}
7727
7728 #ifndef _LP64
7729 instruct convP2B( iRegI dst, iRegP src, flagsReg ccr ) %{
7730 match(Set dst (Conv2B src));
7731 effect( KILL ccr );
7732 ins_cost(DEFAULT_COST*2);
7733 format %{ "CMP R_G0,$src\n\t"
7734 "ADDX R_G0,0,$dst" %}
7735 ins_encode( enc_to_bool( src, dst ) );
7736 ins_pipe(ialu_reg_ialu);
7737 %}
7738 #else
7739 instruct convP2B( iRegI dst, iRegP src ) %{
7740 match(Set dst (Conv2B src));
7741 ins_cost(DEFAULT_COST*2);
7742 format %{ "MOV $src,$dst\n\t"
7743 "MOVRNZ $src,1,$dst" %}
7744 ins_encode( form3_g0_rs2_rd_move( src, dst ), enc_convP2B( dst, src ) );
7745 ins_pipe(ialu_clr_and_mover);
7746 %}
7747 #endif
7748
7749 instruct cmpLTMask_reg_reg( iRegI dst, iRegI p, iRegI q, flagsReg ccr ) %{
7750 match(Set dst (CmpLTMask p q));
7751 effect( KILL ccr );
7752 ins_cost(DEFAULT_COST*4);
7753 format %{ "CMP $p,$q\n\t"
7754 "MOV #0,$dst\n\t"
7755 "BLT,a .+8\n\t"
7756 "MOV #-1,$dst" %}
7757 ins_encode( enc_ltmask(p,q,dst) );
7758 ins_pipe(ialu_reg_reg_ialu);
7759 %}
7760
7761 instruct cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp, flagsReg ccr ) %{
7762 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
7763 effect(KILL ccr, TEMP tmp);
7764 ins_cost(DEFAULT_COST*3);
7765
7766 format %{ "SUBcc $p,$q,$p\t! p' = p-q\n\t"
7767 "ADD $p,$y,$tmp\t! g3=p-q+y\n\t"
7768 "MOVl $tmp,$p\t! p' < 0 ? p'+y : p'" %}
7769 ins_encode( enc_cadd_cmpLTMask(p, q, y, tmp) );
7770 ins_pipe( cadd_cmpltmask );
7771 %}
7772
7773 instruct cadd_cmpLTMask2( iRegI p, iRegI q, iRegI y, iRegI tmp, flagsReg ccr ) %{
7774 match(Set p (AddI (SubI p q) (AndI (CmpLTMask p q) y)));
7775 effect( KILL ccr, TEMP tmp);
7776 ins_cost(DEFAULT_COST*3);
7777
7778 format %{ "SUBcc $p,$q,$p\t! p' = p-q\n\t"
7779 "ADD $p,$y,$tmp\t! g3=p-q+y\n\t"
7780 "MOVl $tmp,$p\t! p' < 0 ? p'+y : p'" %}
7781 ins_encode( enc_cadd_cmpLTMask(p, q, y, tmp) );
7782 ins_pipe( cadd_cmpltmask );
7783 %}
7784
7785 //----------Arithmetic Conversion Instructions---------------------------------
7786 // The conversions operations are all Alpha sorted. Please keep it that way!
7787
7788 instruct convD2F_reg(regF dst, regD src) %{
7789 match(Set dst (ConvD2F src));
7790 size(4);
7791 format %{ "FDTOS $src,$dst" %}
7792 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdtos_opf);
7793 ins_encode(form3_opf_rs2D_rdF(src, dst));
7794 ins_pipe(fcvtD2F);
7795 %}
7796
7797
7798 // Convert a double to an int in a float register.
7799 // If the double is a NAN, stuff a zero in instead.
7800 instruct convD2I_helper(regF dst, regD src, flagsRegF0 fcc0) %{
7801 effect(DEF dst, USE src, KILL fcc0);
7802 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t"
7803 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
7804 "FDTOI $src,$dst\t! convert in delay slot\n\t"
7805 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t"
7806 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n"
7807 "skip:" %}
7808 ins_encode(form_d2i_helper(src,dst));
7809 ins_pipe(fcvtD2I);
7810 %}
7811
7812 instruct convD2I_reg(stackSlotI dst, regD src) %{
7813 match(Set dst (ConvD2I src));
7814 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
7815 expand %{
7816 regF tmp;
7817 convD2I_helper(tmp, src);
7818 regF_to_stkI(dst, tmp);
7819 %}
7820 %}
7821
7822 // Convert a double to a long in a double register.
7823 // If the double is a NAN, stuff a zero in instead.
7824 instruct convD2L_helper(regD dst, regD src, flagsRegF0 fcc0) %{
7825 effect(DEF dst, USE src, KILL fcc0);
7826 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t"
7827 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
7828 "FDTOX $src,$dst\t! convert in delay slot\n\t"
7829 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t"
7830 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n"
7831 "skip:" %}
7832 ins_encode(form_d2l_helper(src,dst));
7833 ins_pipe(fcvtD2L);
7834 %}
7835
7836
7837 // Double to Long conversion
7838 instruct convD2L_reg(stackSlotL dst, regD src) %{
7839 match(Set dst (ConvD2L src));
7840 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
7841 expand %{
7842 regD tmp;
7843 convD2L_helper(tmp, src);
7844 regD_to_stkL(dst, tmp);
7845 %}
7846 %}
7847
7848
7849 instruct convF2D_reg(regD dst, regF src) %{
7850 match(Set dst (ConvF2D src));
7851 format %{ "FSTOD $src,$dst" %}
7852 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fstod_opf);
7853 ins_encode(form3_opf_rs2F_rdD(src, dst));
7854 ins_pipe(fcvtF2D);
7855 %}
7856
7857
7858 instruct convF2I_helper(regF dst, regF src, flagsRegF0 fcc0) %{
7859 effect(DEF dst, USE src, KILL fcc0);
7860 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t"
7861 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
7862 "FSTOI $src,$dst\t! convert in delay slot\n\t"
7863 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t"
7864 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n"
7865 "skip:" %}
7866 ins_encode(form_f2i_helper(src,dst));
7867 ins_pipe(fcvtF2I);
7868 %}
7869
7870 instruct convF2I_reg(stackSlotI dst, regF src) %{
7871 match(Set dst (ConvF2I src));
7872 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
7873 expand %{
7874 regF tmp;
7875 convF2I_helper(tmp, src);
7876 regF_to_stkI(dst, tmp);
7877 %}
7878 %}
7879
7880
7881 instruct convF2L_helper(regD dst, regF src, flagsRegF0 fcc0) %{
7882 effect(DEF dst, USE src, KILL fcc0);
7883 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t"
7884 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
7885 "FSTOX $src,$dst\t! convert in delay slot\n\t"
7886 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t"
7887 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n"
7888 "skip:" %}
7889 ins_encode(form_f2l_helper(src,dst));
7890 ins_pipe(fcvtF2L);
7891 %}
7892
7893 // Float to Long conversion
7894 instruct convF2L_reg(stackSlotL dst, regF src) %{
7895 match(Set dst (ConvF2L src));
7896 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
7897 expand %{
7898 regD tmp;
7899 convF2L_helper(tmp, src);
7900 regD_to_stkL(dst, tmp);
7901 %}
7902 %}
7903
7904
7905 instruct convI2D_helper(regD dst, regF tmp) %{
7906 effect(USE tmp, DEF dst);
7907 format %{ "FITOD $tmp,$dst" %}
7908 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf);
7909 ins_encode(form3_opf_rs2F_rdD(tmp, dst));
7910 ins_pipe(fcvtI2D);
7911 %}
7912
7913 instruct convI2D_reg(stackSlotI src, regD dst) %{
7914 match(Set dst (ConvI2D src));
7915 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
7916 expand %{
7917 regF tmp;
7918 stkI_to_regF( tmp, src);
7919 convI2D_helper( dst, tmp);
7920 %}
7921 %}
7922
7923 instruct convI2D_mem( regD_low dst, memory mem ) %{
7924 match(Set dst (ConvI2D (LoadI mem)));
7925 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
7926 size(8);
7927 format %{ "LDF $mem,$dst\n\t"
7928 "FITOD $dst,$dst" %}
7929 opcode(Assembler::ldf_op3, Assembler::fitod_opf);
7930 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst));
7931 ins_pipe(floadF_mem);
7932 %}
7933
7934
7935 instruct convI2F_helper(regF dst, regF tmp) %{
7936 effect(DEF dst, USE tmp);
7937 format %{ "FITOS $tmp,$dst" %}
7938 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitos_opf);
7939 ins_encode(form3_opf_rs2F_rdF(tmp, dst));
7940 ins_pipe(fcvtI2F);
7941 %}
7942
7943 instruct convI2F_reg( regF dst, stackSlotI src ) %{
7944 match(Set dst (ConvI2F src));
7945 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
7946 expand %{
7947 regF tmp;
7948 stkI_to_regF(tmp,src);
7949 convI2F_helper(dst, tmp);
7950 %}
7951 %}
7952
7953 instruct convI2F_mem( regF dst, memory mem ) %{
7954 match(Set dst (ConvI2F (LoadI mem)));
7955 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
7956 size(8);
7957 format %{ "LDF $mem,$dst\n\t"
7958 "FITOS $dst,$dst" %}
7959 opcode(Assembler::ldf_op3, Assembler::fitos_opf);
7960 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst));
7961 ins_pipe(floadF_mem);
7962 %}
7963
7964
7965 instruct convI2L_reg(iRegL dst, iRegI src) %{
7966 match(Set dst (ConvI2L src));
7967 size(4);
7968 format %{ "SRA $src,0,$dst\t! int->long" %}
7969 opcode(Assembler::sra_op3, Assembler::arith_op);
7970 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
7971 ins_pipe(ialu_reg_reg);
7972 %}
7973
7974 // Zero-extend convert int to long
7975 instruct convI2L_reg_zex(iRegL dst, iRegI src, immL_32bits mask ) %{
7976 match(Set dst (AndL (ConvI2L src) mask) );
7977 size(4);
7978 format %{ "SRL $src,0,$dst\t! zero-extend int to long" %}
7979 opcode(Assembler::srl_op3, Assembler::arith_op);
7980 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
7981 ins_pipe(ialu_reg_reg);
7982 %}
7983
7984 // Zero-extend long
7985 instruct zerox_long(iRegL dst, iRegL src, immL_32bits mask ) %{
7986 match(Set dst (AndL src mask) );
7987 size(4);
7988 format %{ "SRL $src,0,$dst\t! zero-extend long" %}
7989 opcode(Assembler::srl_op3, Assembler::arith_op);
7990 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
7991 ins_pipe(ialu_reg_reg);
7992 %}
7993
7994 instruct MoveF2I_stack_reg(iRegI dst, stackSlotF src) %{
7995 match(Set dst (MoveF2I src));
7996 effect(DEF dst, USE src);
7997 ins_cost(MEMORY_REF_COST);
7998
7999 size(4);
8000 format %{ "LDUW $src,$dst\t! MoveF2I" %}
8001 opcode(Assembler::lduw_op3);
8002 ins_encode(simple_form3_mem_reg( src, dst ) );
8003 ins_pipe(iload_mem);
8004 %}
8005
8006 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
8007 match(Set dst (MoveI2F src));
8008 effect(DEF dst, USE src);
8009 ins_cost(MEMORY_REF_COST);
8010
8011 size(4);
8012 format %{ "LDF $src,$dst\t! MoveI2F" %}
8013 opcode(Assembler::ldf_op3);
8014 ins_encode(simple_form3_mem_reg(src, dst));
8015 ins_pipe(floadF_stk);
8016 %}
8017
8018 instruct MoveD2L_stack_reg(iRegL dst, stackSlotD src) %{
8019 match(Set dst (MoveD2L src));
8020 effect(DEF dst, USE src);
8021 ins_cost(MEMORY_REF_COST);
8022
8023 size(4);
8024 format %{ "LDX $src,$dst\t! MoveD2L" %}
8025 opcode(Assembler::ldx_op3);
8026 ins_encode(simple_form3_mem_reg( src, dst ) );
8027 ins_pipe(iload_mem);
8028 %}
8029
8030 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
8031 match(Set dst (MoveL2D src));
8032 effect(DEF dst, USE src);
8033 ins_cost(MEMORY_REF_COST);
8034
8035 size(4);
8036 format %{ "LDDF $src,$dst\t! MoveL2D" %}
8037 opcode(Assembler::lddf_op3);
8038 ins_encode(simple_form3_mem_reg(src, dst));
8039 ins_pipe(floadD_stk);
8040 %}
8041
8042 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{
8043 match(Set dst (MoveF2I src));
8044 effect(DEF dst, USE src);
8045 ins_cost(MEMORY_REF_COST);
8046
8047 size(4);
8048 format %{ "STF $src,$dst\t!MoveF2I" %}
8049 opcode(Assembler::stf_op3);
8050 ins_encode(simple_form3_mem_reg(dst, src));
8051 ins_pipe(fstoreF_stk_reg);
8052 %}
8053
8054 instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{
8055 match(Set dst (MoveI2F src));
8056 effect(DEF dst, USE src);
8057 ins_cost(MEMORY_REF_COST);
8058
8059 size(4);
8060 format %{ "STW $src,$dst\t!MoveI2F" %}
8061 opcode(Assembler::stw_op3);
8062 ins_encode(simple_form3_mem_reg( dst, src ) );
8063 ins_pipe(istore_mem_reg);
8064 %}
8065
8066 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
8067 match(Set dst (MoveD2L src));
8068 effect(DEF dst, USE src);
8069 ins_cost(MEMORY_REF_COST);
8070
8071 size(4);
8072 format %{ "STDF $src,$dst\t!MoveD2L" %}
8073 opcode(Assembler::stdf_op3);
8074 ins_encode(simple_form3_mem_reg(dst, src));
8075 ins_pipe(fstoreD_stk_reg);
8076 %}
8077
8078 instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{
8079 match(Set dst (MoveL2D src));
8080 effect(DEF dst, USE src);
8081 ins_cost(MEMORY_REF_COST);
8082
8083 size(4);
8084 format %{ "STX $src,$dst\t!MoveL2D" %}
8085 opcode(Assembler::stx_op3);
8086 ins_encode(simple_form3_mem_reg( dst, src ) );
8087 ins_pipe(istore_mem_reg);
8088 %}
8089
8090
8091 //-----------
8092 // Long to Double conversion using V8 opcodes.
8093 // Still useful because cheetah traps and becomes
8094 // amazingly slow for some common numbers.
8095
8096 // Magic constant, 0x43300000
8097 instruct loadConI_x43300000(iRegI dst) %{
8098 effect(DEF dst);
8099 size(4);
8100 format %{ "SETHI HI(0x43300000),$dst\t! 2^52" %}
8101 ins_encode(SetHi22(0x43300000, dst));
8102 ins_pipe(ialu_none);
8103 %}
8104
8105 // Magic constant, 0x41f00000
8106 instruct loadConI_x41f00000(iRegI dst) %{
8107 effect(DEF dst);
8108 size(4);
8109 format %{ "SETHI HI(0x41f00000),$dst\t! 2^32" %}
8110 ins_encode(SetHi22(0x41f00000, dst));
8111 ins_pipe(ialu_none);
8112 %}
8113
8114 // Construct a double from two float halves
8115 instruct regDHi_regDLo_to_regD(regD_low dst, regD_low src1, regD_low src2) %{
8116 effect(DEF dst, USE src1, USE src2);
8117 size(8);
8118 format %{ "FMOVS $src1.hi,$dst.hi\n\t"
8119 "FMOVS $src2.lo,$dst.lo" %}
8120 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmovs_opf);
8121 ins_encode(form3_opf_rs2D_hi_rdD_hi(src1, dst), form3_opf_rs2D_lo_rdD_lo(src2, dst));
8122 ins_pipe(faddD_reg_reg);
8123 %}
8124
8125 // Convert integer in high half of a double register (in the lower half of
8126 // the double register file) to double
8127 instruct convI2D_regDHi_regD(regD dst, regD_low src) %{
8128 effect(DEF dst, USE src);
8129 size(4);
8130 format %{ "FITOD $src,$dst" %}
8131 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf);
8132 ins_encode(form3_opf_rs2D_rdD(src, dst));
8133 ins_pipe(fcvtLHi2D);
8134 %}
8135
8136 // Add float double precision
8137 instruct addD_regD_regD(regD dst, regD src1, regD src2) %{
8138 effect(DEF dst, USE src1, USE src2);
8139 size(4);
8140 format %{ "FADDD $src1,$src2,$dst" %}
8141 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf);
8142 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8143 ins_pipe(faddD_reg_reg);
8144 %}
8145
8146 // Sub float double precision
8147 instruct subD_regD_regD(regD dst, regD src1, regD src2) %{
8148 effect(DEF dst, USE src1, USE src2);
8149 size(4);
8150 format %{ "FSUBD $src1,$src2,$dst" %}
8151 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf);
8152 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8153 ins_pipe(faddD_reg_reg);
8154 %}
8155
8156 // Mul float double precision
8157 instruct mulD_regD_regD(regD dst, regD src1, regD src2) %{
8158 effect(DEF dst, USE src1, USE src2);
8159 size(4);
8160 format %{ "FMULD $src1,$src2,$dst" %}
8161 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf);
8162 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8163 ins_pipe(fmulD_reg_reg);
8164 %}
8165
8166 instruct convL2D_reg_slow_fxtof(regD dst, stackSlotL src) %{
8167 match(Set dst (ConvL2D src));
8168 ins_cost(DEFAULT_COST*8 + MEMORY_REF_COST*6);
8169
8170 expand %{
8171 regD_low tmpsrc;
8172 iRegI ix43300000;
8173 iRegI ix41f00000;
8174 stackSlotL lx43300000;
8175 stackSlotL lx41f00000;
8176 regD_low dx43300000;
8177 regD dx41f00000;
8178 regD tmp1;
8179 regD_low tmp2;
8180 regD tmp3;
8181 regD tmp4;
8182
8183 stkL_to_regD(tmpsrc, src);
8184
8185 loadConI_x43300000(ix43300000);
8186 loadConI_x41f00000(ix41f00000);
8187 regI_to_stkLHi(lx43300000, ix43300000);
8188 regI_to_stkLHi(lx41f00000, ix41f00000);
8189 stkL_to_regD(dx43300000, lx43300000);
8190 stkL_to_regD(dx41f00000, lx41f00000);
8191
8192 convI2D_regDHi_regD(tmp1, tmpsrc);
8193 regDHi_regDLo_to_regD(tmp2, dx43300000, tmpsrc);
8194 subD_regD_regD(tmp3, tmp2, dx43300000);
8195 mulD_regD_regD(tmp4, tmp1, dx41f00000);
8196 addD_regD_regD(dst, tmp3, tmp4);
8197 %}
8198 %}
8199
8200 // Long to Double conversion using fast fxtof
8201 instruct convL2D_helper(regD dst, regD tmp) %{
8202 effect(DEF dst, USE tmp);
8203 size(4);
8204 format %{ "FXTOD $tmp,$dst" %}
8205 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtod_opf);
8206 ins_encode(form3_opf_rs2D_rdD(tmp, dst));
8207 ins_pipe(fcvtL2D);
8208 %}
8209
8210 instruct convL2D_reg_fast_fxtof(regD dst, stackSlotL src) %{
8211 predicate(VM_Version::has_fast_fxtof());
8212 match(Set dst (ConvL2D src));
8213 ins_cost(DEFAULT_COST + 3 * MEMORY_REF_COST);
8214 expand %{
8215 regD tmp;
8216 stkL_to_regD(tmp, src);
8217 convL2D_helper(dst, tmp);
8218 %}
8219 %}
8220
8221 //-----------
8222 // Long to Float conversion using V8 opcodes.
8223 // Still useful because cheetah traps and becomes
8224 // amazingly slow for some common numbers.
8225
8226 // Long to Float conversion using fast fxtof
8227 instruct convL2F_helper(regF dst, regD tmp) %{
8228 effect(DEF dst, USE tmp);
8229 size(4);
8230 format %{ "FXTOS $tmp,$dst" %}
8231 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtos_opf);
8232 ins_encode(form3_opf_rs2D_rdF(tmp, dst));
8233 ins_pipe(fcvtL2F);
8234 %}
8235
8236 instruct convL2F_reg_fast_fxtof(regF dst, stackSlotL src) %{
8237 match(Set dst (ConvL2F src));
8238 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8239 expand %{
8240 regD tmp;
8241 stkL_to_regD(tmp, src);
8242 convL2F_helper(dst, tmp);
8243 %}
8244 %}
8245 //-----------
8246
8247 instruct convL2I_reg(iRegI dst, iRegL src) %{
8248 match(Set dst (ConvL2I src));
8249 #ifndef _LP64
8250 format %{ "MOV $src.lo,$dst\t! long->int" %}
8251 ins_encode( form3_g0_rs2_rd_move_lo2( src, dst ) );
8252 ins_pipe(ialu_move_reg_I_to_L);
8253 #else
8254 size(4);
8255 format %{ "SRA $src,R_G0,$dst\t! long->int" %}
8256 ins_encode( form3_rs1_rd_signextend_lo1( src, dst ) );
8257 ins_pipe(ialu_reg);
8258 #endif
8259 %}
8260
8261 // Register Shift Right Immediate
8262 instruct shrL_reg_imm6_L2I(iRegI dst, iRegL src, immI_32_63 cnt) %{
8263 match(Set dst (ConvL2I (RShiftL src cnt)));
8264
8265 size(4);
8266 format %{ "SRAX $src,$cnt,$dst" %}
8267 opcode(Assembler::srax_op3, Assembler::arith_op);
8268 ins_encode( form3_sd_rs1_imm6_rd( src, cnt, dst ) );
8269 ins_pipe(ialu_reg_imm);
8270 %}
8271
8272 // Replicate scalar to packed byte values in Double register
8273 instruct Repl8B_reg_helper(iRegL dst, iRegI src) %{
8274 effect(DEF dst, USE src);
8275 format %{ "SLLX $src,56,$dst\n\t"
8276 "SRLX $dst, 8,O7\n\t"
8277 "OR $dst,O7,$dst\n\t"
8278 "SRLX $dst,16,O7\n\t"
8279 "OR $dst,O7,$dst\n\t"
8280 "SRLX $dst,32,O7\n\t"
8281 "OR $dst,O7,$dst\t! replicate8B" %}
8282 ins_encode( enc_repl8b(src, dst));
8283 ins_pipe(ialu_reg);
8284 %}
8285
8286 // Replicate scalar to packed byte values in Double register
8287 instruct Repl8B_reg(stackSlotD dst, iRegI src) %{
8288 match(Set dst (Replicate8B src));
8289 expand %{
8290 iRegL tmp;
8291 Repl8B_reg_helper(tmp, src);
8292 regL_to_stkD(dst, tmp);
8293 %}
8294 %}
8295
8296 // Replicate scalar constant to packed byte values in Double register
8297 instruct Repl8B_immI(regD dst, immI13 src, o7RegP tmp) %{
8298 match(Set dst (Replicate8B src));
8299 #ifdef _LP64
8300 size(36);
8301 #else
8302 size(8);
8303 #endif
8304 format %{ "SETHI hi(&Repl8($src)),$tmp\t!get Repl8B($src) from table\n\t"
8305 "LDDF [$tmp+lo(&Repl8($src))],$dst" %}
8306 ins_encode( LdReplImmI(src, dst, tmp, (8), (1)) );
8307 ins_pipe(loadConFD);
8308 %}
8309
8310 // Replicate scalar to packed char values into stack slot
8311 instruct Repl4C_reg_helper(iRegL dst, iRegI src) %{
8312 effect(DEF dst, USE src);
8313 format %{ "SLLX $src,48,$dst\n\t"
8314 "SRLX $dst,16,O7\n\t"
8315 "OR $dst,O7,$dst\n\t"
8316 "SRLX $dst,32,O7\n\t"
8317 "OR $dst,O7,$dst\t! replicate4C" %}
8318 ins_encode( enc_repl4s(src, dst) );
8319 ins_pipe(ialu_reg);
8320 %}
8321
8322 // Replicate scalar to packed char values into stack slot
8323 instruct Repl4C_reg(stackSlotD dst, iRegI src) %{
8324 match(Set dst (Replicate4C src));
8325 expand %{
8326 iRegL tmp;
8327 Repl4C_reg_helper(tmp, src);
8328 regL_to_stkD(dst, tmp);
8329 %}
8330 %}
8331
8332 // Replicate scalar constant to packed char values in Double register
8333 instruct Repl4C_immI(regD dst, immI src, o7RegP tmp) %{
8334 match(Set dst (Replicate4C src));
8335 #ifdef _LP64
8336 size(36);
8337 #else
8338 size(8);
8339 #endif
8340 format %{ "SETHI hi(&Repl4($src)),$tmp\t!get Repl4C($src) from table\n\t"
8341 "LDDF [$tmp+lo(&Repl4($src))],$dst" %}
8342 ins_encode( LdReplImmI(src, dst, tmp, (4), (2)) );
8343 ins_pipe(loadConFD);
8344 %}
8345
8346 // Replicate scalar to packed short values into stack slot
8347 instruct Repl4S_reg_helper(iRegL dst, iRegI src) %{
8348 effect(DEF dst, USE src);
8349 format %{ "SLLX $src,48,$dst\n\t"
8350 "SRLX $dst,16,O7\n\t"
8351 "OR $dst,O7,$dst\n\t"
8352 "SRLX $dst,32,O7\n\t"
8353 "OR $dst,O7,$dst\t! replicate4S" %}
8354 ins_encode( enc_repl4s(src, dst) );
8355 ins_pipe(ialu_reg);
8356 %}
8357
8358 // Replicate scalar to packed short values into stack slot
8359 instruct Repl4S_reg(stackSlotD dst, iRegI src) %{
8360 match(Set dst (Replicate4S src));
8361 expand %{
8362 iRegL tmp;
8363 Repl4S_reg_helper(tmp, src);
8364 regL_to_stkD(dst, tmp);
8365 %}
8366 %}
8367
8368 // Replicate scalar constant to packed short values in Double register
8369 instruct Repl4S_immI(regD dst, immI src, o7RegP tmp) %{
8370 match(Set dst (Replicate4S src));
8371 #ifdef _LP64
8372 size(36);
8373 #else
8374 size(8);
8375 #endif
8376 format %{ "SETHI hi(&Repl4($src)),$tmp\t!get Repl4S($src) from table\n\t"
8377 "LDDF [$tmp+lo(&Repl4($src))],$dst" %}
8378 ins_encode( LdReplImmI(src, dst, tmp, (4), (2)) );
8379 ins_pipe(loadConFD);
8380 %}
8381
8382 // Replicate scalar to packed int values in Double register
8383 instruct Repl2I_reg_helper(iRegL dst, iRegI src) %{
8384 effect(DEF dst, USE src);
8385 format %{ "SLLX $src,32,$dst\n\t"
8386 "SRLX $dst,32,O7\n\t"
8387 "OR $dst,O7,$dst\t! replicate2I" %}
8388 ins_encode( enc_repl2i(src, dst));
8389 ins_pipe(ialu_reg);
8390 %}
8391
8392 // Replicate scalar to packed int values in Double register
8393 instruct Repl2I_reg(stackSlotD dst, iRegI src) %{
8394 match(Set dst (Replicate2I src));
8395 expand %{
8396 iRegL tmp;
8397 Repl2I_reg_helper(tmp, src);
8398 regL_to_stkD(dst, tmp);
8399 %}
8400 %}
8401
8402 // Replicate scalar zero constant to packed int values in Double register
8403 instruct Repl2I_immI(regD dst, immI src, o7RegP tmp) %{
8404 match(Set dst (Replicate2I src));
8405 #ifdef _LP64
8406 size(36);
8407 #else
8408 size(8);
8409 #endif
8410 format %{ "SETHI hi(&Repl2($src)),$tmp\t!get Repl2I($src) from table\n\t"
8411 "LDDF [$tmp+lo(&Repl2($src))],$dst" %}
8412 ins_encode( LdReplImmI(src, dst, tmp, (2), (4)) );
8413 ins_pipe(loadConFD);
8414 %}
8415
8416 //----------Control Flow Instructions------------------------------------------
8417 // Compare Instructions
8418 // Compare Integers
8419 instruct compI_iReg(flagsReg icc, iRegI op1, iRegI op2) %{
8420 match(Set icc (CmpI op1 op2));
8421 effect( DEF icc, USE op1, USE op2 );
8422
8423 size(4);
8424 format %{ "CMP $op1,$op2" %}
8425 opcode(Assembler::subcc_op3, Assembler::arith_op);
8426 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8427 ins_pipe(ialu_cconly_reg_reg);
8428 %}
8429
8430 instruct compU_iReg(flagsRegU icc, iRegI op1, iRegI op2) %{
8431 match(Set icc (CmpU op1 op2));
8432
8433 size(4);
8434 format %{ "CMP $op1,$op2\t! unsigned" %}
8435 opcode(Assembler::subcc_op3, Assembler::arith_op);
8436 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8437 ins_pipe(ialu_cconly_reg_reg);
8438 %}
8439
8440 instruct compI_iReg_imm13(flagsReg icc, iRegI op1, immI13 op2) %{
8441 match(Set icc (CmpI op1 op2));
8442 effect( DEF icc, USE op1 );
8443
8444 size(4);
8445 format %{ "CMP $op1,$op2" %}
8446 opcode(Assembler::subcc_op3, Assembler::arith_op);
8447 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8448 ins_pipe(ialu_cconly_reg_imm);
8449 %}
8450
8451 instruct testI_reg_reg( flagsReg icc, iRegI op1, iRegI op2, immI0 zero ) %{
8452 match(Set icc (CmpI (AndI op1 op2) zero));
8453
8454 size(4);
8455 format %{ "BTST $op2,$op1" %}
8456 opcode(Assembler::andcc_op3, Assembler::arith_op);
8457 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8458 ins_pipe(ialu_cconly_reg_reg_zero);
8459 %}
8460
8461 instruct testI_reg_imm( flagsReg icc, iRegI op1, immI13 op2, immI0 zero ) %{
8462 match(Set icc (CmpI (AndI op1 op2) zero));
8463
8464 size(4);
8465 format %{ "BTST $op2,$op1" %}
8466 opcode(Assembler::andcc_op3, Assembler::arith_op);
8467 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8468 ins_pipe(ialu_cconly_reg_imm_zero);
8469 %}
8470
8471 instruct compL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2 ) %{
8472 match(Set xcc (CmpL op1 op2));
8473 effect( DEF xcc, USE op1, USE op2 );
8474
8475 size(4);
8476 format %{ "CMP $op1,$op2\t\t! long" %}
8477 opcode(Assembler::subcc_op3, Assembler::arith_op);
8478 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8479 ins_pipe(ialu_cconly_reg_reg);
8480 %}
8481
8482 instruct compL_reg_con(flagsRegL xcc, iRegL op1, immL13 con) %{
8483 match(Set xcc (CmpL op1 con));
8484 effect( DEF xcc, USE op1, USE con );
8485
8486 size(4);
8487 format %{ "CMP $op1,$con\t\t! long" %}
8488 opcode(Assembler::subcc_op3, Assembler::arith_op);
8489 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) );
8490 ins_pipe(ialu_cconly_reg_reg);
8491 %}
8492
8493 instruct testL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2, immL0 zero) %{
8494 match(Set xcc (CmpL (AndL op1 op2) zero));
8495 effect( DEF xcc, USE op1, USE op2 );
8496
8497 size(4);
8498 format %{ "BTST $op1,$op2\t\t! long" %}
8499 opcode(Assembler::andcc_op3, Assembler::arith_op);
8500 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8501 ins_pipe(ialu_cconly_reg_reg);
8502 %}
8503
8504 // useful for checking the alignment of a pointer:
8505 instruct testL_reg_con(flagsRegL xcc, iRegL op1, immL13 con, immL0 zero) %{
8506 match(Set xcc (CmpL (AndL op1 con) zero));
8507 effect( DEF xcc, USE op1, USE con );
8508
8509 size(4);
8510 format %{ "BTST $op1,$con\t\t! long" %}
8511 opcode(Assembler::andcc_op3, Assembler::arith_op);
8512 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) );
8513 ins_pipe(ialu_cconly_reg_reg);
8514 %}
8515
8516 instruct compU_iReg_imm13(flagsRegU icc, iRegI op1, immU13 op2 ) %{
8517 match(Set icc (CmpU op1 op2));
8518
8519 size(4);
8520 format %{ "CMP $op1,$op2\t! unsigned" %}
8521 opcode(Assembler::subcc_op3, Assembler::arith_op);
8522 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8523 ins_pipe(ialu_cconly_reg_imm);
8524 %}
8525
8526 // Compare Pointers
8527 instruct compP_iRegP(flagsRegP pcc, iRegP op1, iRegP op2 ) %{
8528 match(Set pcc (CmpP op1 op2));
8529
8530 size(4);
8531 format %{ "CMP $op1,$op2\t! ptr" %}
8532 opcode(Assembler::subcc_op3, Assembler::arith_op);
8533 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8534 ins_pipe(ialu_cconly_reg_reg);
8535 %}
8536
8537 instruct compP_iRegP_imm13(flagsRegP pcc, iRegP op1, immP13 op2 ) %{
8538 match(Set pcc (CmpP op1 op2));
8539
8540 size(4);
8541 format %{ "CMP $op1,$op2\t! ptr" %}
8542 opcode(Assembler::subcc_op3, Assembler::arith_op);
8543 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8544 ins_pipe(ialu_cconly_reg_imm);
8545 %}
8546
8547 // Compare Narrow oops
8548 instruct compN_iRegN(flagsReg icc, iRegN op1, iRegN op2 ) %{
8549 match(Set icc (CmpN op1 op2));
8550
8551 size(4);
8552 format %{ "CMP $op1,$op2\t! compressed ptr" %}
8553 opcode(Assembler::subcc_op3, Assembler::arith_op);
8554 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8555 ins_pipe(ialu_cconly_reg_reg);
8556 %}
8557
8558 instruct compN_iRegN_immN0(flagsReg icc, iRegN op1, immN0 op2 ) %{
8559 match(Set icc (CmpN op1 op2));
8560
8561 size(4);
8562 format %{ "CMP $op1,$op2\t! compressed ptr" %}
8563 opcode(Assembler::subcc_op3, Assembler::arith_op);
8564 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8565 ins_pipe(ialu_cconly_reg_imm);
8566 %}
8567
8568 //----------Max and Min--------------------------------------------------------
8569 // Min Instructions
8570 // Conditional move for min
8571 instruct cmovI_reg_lt( iRegI op2, iRegI op1, flagsReg icc ) %{
8572 effect( USE_DEF op2, USE op1, USE icc );
8573
8574 size(4);
8575 format %{ "MOVlt icc,$op1,$op2\t! min" %}
8576 opcode(Assembler::less);
8577 ins_encode( enc_cmov_reg_minmax(op2,op1) );
8578 ins_pipe(ialu_reg_flags);
8579 %}
8580
8581 // Min Register with Register.
8582 instruct minI_eReg(iRegI op1, iRegI op2) %{
8583 match(Set op2 (MinI op1 op2));
8584 ins_cost(DEFAULT_COST*2);
8585 expand %{
8586 flagsReg icc;
8587 compI_iReg(icc,op1,op2);
8588 cmovI_reg_lt(op2,op1,icc);
8589 %}
8590 %}
8591
8592 // Max Instructions
8593 // Conditional move for max
8594 instruct cmovI_reg_gt( iRegI op2, iRegI op1, flagsReg icc ) %{
8595 effect( USE_DEF op2, USE op1, USE icc );
8596 format %{ "MOVgt icc,$op1,$op2\t! max" %}
8597 opcode(Assembler::greater);
8598 ins_encode( enc_cmov_reg_minmax(op2,op1) );
8599 ins_pipe(ialu_reg_flags);
8600 %}
8601
8602 // Max Register with Register
8603 instruct maxI_eReg(iRegI op1, iRegI op2) %{
8604 match(Set op2 (MaxI op1 op2));
8605 ins_cost(DEFAULT_COST*2);
8606 expand %{
8607 flagsReg icc;
8608 compI_iReg(icc,op1,op2);
8609 cmovI_reg_gt(op2,op1,icc);
8610 %}
8611 %}
8612
8613
8614 //----------Float Compares----------------------------------------------------
8615 // Compare floating, generate condition code
8616 instruct cmpF_cc(flagsRegF fcc, regF src1, regF src2) %{
8617 match(Set fcc (CmpF src1 src2));
8618
8619 size(4);
8620 format %{ "FCMPs $fcc,$src1,$src2" %}
8621 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmps_opf);
8622 ins_encode( form3_opf_rs1F_rs2F_fcc( src1, src2, fcc ) );
8623 ins_pipe(faddF_fcc_reg_reg_zero);
8624 %}
8625
8626 instruct cmpD_cc(flagsRegF fcc, regD src1, regD src2) %{
8627 match(Set fcc (CmpD src1 src2));
8628
8629 size(4);
8630 format %{ "FCMPd $fcc,$src1,$src2" %}
8631 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmpd_opf);
8632 ins_encode( form3_opf_rs1D_rs2D_fcc( src1, src2, fcc ) );
8633 ins_pipe(faddD_fcc_reg_reg_zero);
8634 %}
8635
8636
8637 // Compare floating, generate -1,0,1
8638 instruct cmpF_reg(iRegI dst, regF src1, regF src2, flagsRegF0 fcc0) %{
8639 match(Set dst (CmpF3 src1 src2));
8640 effect(KILL fcc0);
8641 ins_cost(DEFAULT_COST*3+BRANCH_COST*3);
8642 format %{ "fcmpl $dst,$src1,$src2" %}
8643 // Primary = float
8644 opcode( true );
8645 ins_encode( floating_cmp( dst, src1, src2 ) );
8646 ins_pipe( floating_cmp );
8647 %}
8648
8649 instruct cmpD_reg(iRegI dst, regD src1, regD src2, flagsRegF0 fcc0) %{
8650 match(Set dst (CmpD3 src1 src2));
8651 effect(KILL fcc0);
8652 ins_cost(DEFAULT_COST*3+BRANCH_COST*3);
8653 format %{ "dcmpl $dst,$src1,$src2" %}
8654 // Primary = double (not float)
8655 opcode( false );
8656 ins_encode( floating_cmp( dst, src1, src2 ) );
8657 ins_pipe( floating_cmp );
8658 %}
8659
8660 //----------Branches---------------------------------------------------------
8661 // Jump
8662 // (compare 'operand indIndex' and 'instruct addP_reg_reg' above)
8663 instruct jumpXtnd(iRegX switch_val, o7RegI table) %{
8664 match(Jump switch_val);
8665
8666 ins_cost(350);
8667
8668 format %{ "SETHI [hi(table_base)],O7\n\t"
8669 "ADD O7, lo(table_base), O7\n\t"
8670 "LD [O7+$switch_val], O7\n\t"
8671 "JUMP O7"
8672 %}
8673 ins_encode( jump_enc( switch_val, table) );
8674 ins_pc_relative(1);
8675 ins_pipe(ialu_reg_reg);
8676 %}
8677
8678 // Direct Branch. Use V8 version with longer range.
8679 instruct branch(label labl) %{
8680 match(Goto);
8681 effect(USE labl);
8682
8683 size(8);
8684 ins_cost(BRANCH_COST);
8685 format %{ "BA $labl" %}
8686 // Prim = bits 24-22, Secnd = bits 31-30, Tert = cond
8687 opcode(Assembler::br_op2, Assembler::branch_op, Assembler::always);
8688 ins_encode( enc_ba( labl ) );
8689 ins_pc_relative(1);
8690 ins_pipe(br);
8691 %}
8692
8693 // Conditional Direct Branch
8694 instruct branchCon(cmpOp cmp, flagsReg icc, label labl) %{
8695 match(If cmp icc);
8696 effect(USE labl);
8697
8698 size(8);
8699 ins_cost(BRANCH_COST);
8700 format %{ "BP$cmp $icc,$labl" %}
8701 // Prim = bits 24-22, Secnd = bits 31-30
8702 ins_encode( enc_bp( labl, cmp, icc ) );
8703 ins_pc_relative(1);
8704 ins_pipe(br_cc);
8705 %}
8706
8707 // Branch-on-register tests all 64 bits. We assume that values
8708 // in 64-bit registers always remains zero or sign extended
8709 // unless our code munges the high bits. Interrupts can chop
8710 // the high order bits to zero or sign at any time.
8711 instruct branchCon_regI(cmpOp_reg cmp, iRegI op1, immI0 zero, label labl) %{
8712 match(If cmp (CmpI op1 zero));
8713 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
8714 effect(USE labl);
8715
8716 size(8);
8717 ins_cost(BRANCH_COST);
8718 format %{ "BR$cmp $op1,$labl" %}
8719 ins_encode( enc_bpr( labl, cmp, op1 ) );
8720 ins_pc_relative(1);
8721 ins_pipe(br_reg);
8722 %}
8723
8724 instruct branchCon_regP(cmpOp_reg cmp, iRegP op1, immP0 null, label labl) %{
8725 match(If cmp (CmpP op1 null));
8726 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
8727 effect(USE labl);
8728
8729 size(8);
8730 ins_cost(BRANCH_COST);
8731 format %{ "BR$cmp $op1,$labl" %}
8732 ins_encode( enc_bpr( labl, cmp, op1 ) );
8733 ins_pc_relative(1);
8734 ins_pipe(br_reg);
8735 %}
8736
8737 instruct branchCon_regL(cmpOp_reg cmp, iRegL op1, immL0 zero, label labl) %{
8738 match(If cmp (CmpL op1 zero));
8739 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
8740 effect(USE labl);
8741
8742 size(8);
8743 ins_cost(BRANCH_COST);
8744 format %{ "BR$cmp $op1,$labl" %}
8745 ins_encode( enc_bpr( labl, cmp, op1 ) );
8746 ins_pc_relative(1);
8747 ins_pipe(br_reg);
8748 %}
8749
8750 instruct branchConU(cmpOpU cmp, flagsRegU icc, label labl) %{
8751 match(If cmp icc);
8752 effect(USE labl);
8753
8754 format %{ "BP$cmp $icc,$labl" %}
8755 // Prim = bits 24-22, Secnd = bits 31-30
8756 ins_encode( enc_bp( labl, cmp, icc ) );
8757 ins_pc_relative(1);
8758 ins_pipe(br_cc);
8759 %}
8760
8761 instruct branchConP(cmpOpP cmp, flagsRegP pcc, label labl) %{
8762 match(If cmp pcc);
8763 effect(USE labl);
8764
8765 size(8);
8766 ins_cost(BRANCH_COST);
8767 format %{ "BP$cmp $pcc,$labl" %}
8768 // Prim = bits 24-22, Secnd = bits 31-30
8769 ins_encode( enc_bpx( labl, cmp, pcc ) );
8770 ins_pc_relative(1);
8771 ins_pipe(br_cc);
8772 %}
8773
8774 instruct branchConF(cmpOpF cmp, flagsRegF fcc, label labl) %{
8775 match(If cmp fcc);
8776 effect(USE labl);
8777
8778 size(8);
8779 ins_cost(BRANCH_COST);
8780 format %{ "FBP$cmp $fcc,$labl" %}
8781 // Prim = bits 24-22, Secnd = bits 31-30
8782 ins_encode( enc_fbp( labl, cmp, fcc ) );
8783 ins_pc_relative(1);
8784 ins_pipe(br_fcc);
8785 %}
8786
8787 instruct branchLoopEnd(cmpOp cmp, flagsReg icc, label labl) %{
8788 match(CountedLoopEnd cmp icc);
8789 effect(USE labl);
8790
8791 size(8);
8792 ins_cost(BRANCH_COST);
8793 format %{ "BP$cmp $icc,$labl\t! Loop end" %}
8794 // Prim = bits 24-22, Secnd = bits 31-30
8795 ins_encode( enc_bp( labl, cmp, icc ) );
8796 ins_pc_relative(1);
8797 ins_pipe(br_cc);
8798 %}
8799
8800 instruct branchLoopEndU(cmpOpU cmp, flagsRegU icc, label labl) %{
8801 match(CountedLoopEnd cmp icc);
8802 effect(USE labl);
8803
8804 size(8);
8805 ins_cost(BRANCH_COST);
8806 format %{ "BP$cmp $icc,$labl\t! Loop end" %}
8807 // Prim = bits 24-22, Secnd = bits 31-30
8808 ins_encode( enc_bp( labl, cmp, icc ) );
8809 ins_pc_relative(1);
8810 ins_pipe(br_cc);
8811 %}
8812
8813 // ============================================================================
8814 // Long Compare
8815 //
8816 // Currently we hold longs in 2 registers. Comparing such values efficiently
8817 // is tricky. The flavor of compare used depends on whether we are testing
8818 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit.
8819 // The GE test is the negated LT test. The LE test can be had by commuting
8820 // the operands (yielding a GE test) and then negating; negate again for the
8821 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the
8822 // NE test is negated from that.
8823
8824 // Due to a shortcoming in the ADLC, it mixes up expressions like:
8825 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the
8826 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections
8827 // are collapsed internally in the ADLC's dfa-gen code. The match for
8828 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the
8829 // foo match ends up with the wrong leaf. One fix is to not match both
8830 // reg-reg and reg-zero forms of long-compare. This is unfortunate because
8831 // both forms beat the trinary form of long-compare and both are very useful
8832 // on Intel which has so few registers.
8833
8834 instruct branchCon_long(cmpOp cmp, flagsRegL xcc, label labl) %{
8835 match(If cmp xcc);
8836 effect(USE labl);
8837
8838 size(8);
8839 ins_cost(BRANCH_COST);
8840 format %{ "BP$cmp $xcc,$labl" %}
8841 // Prim = bits 24-22, Secnd = bits 31-30
8842 ins_encode( enc_bpl( labl, cmp, xcc ) );
8843 ins_pc_relative(1);
8844 ins_pipe(br_cc);
8845 %}
8846
8847 // Manifest a CmpL3 result in an integer register. Very painful.
8848 // This is the test to avoid.
8849 instruct cmpL3_reg_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg ccr ) %{
8850 match(Set dst (CmpL3 src1 src2) );
8851 effect( KILL ccr );
8852 ins_cost(6*DEFAULT_COST);
8853 size(24);
8854 format %{ "CMP $src1,$src2\t\t! long\n"
8855 "\tBLT,a,pn done\n"
8856 "\tMOV -1,$dst\t! delay slot\n"
8857 "\tBGT,a,pn done\n"
8858 "\tMOV 1,$dst\t! delay slot\n"
8859 "\tCLR $dst\n"
8860 "done:" %}
8861 ins_encode( cmpl_flag(src1,src2,dst) );
8862 ins_pipe(cmpL_reg);
8863 %}
8864
8865 // Conditional move
8866 instruct cmovLL_reg(cmpOp cmp, flagsRegL xcc, iRegL dst, iRegL src) %{
8867 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src)));
8868 ins_cost(150);
8869 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %}
8870 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
8871 ins_pipe(ialu_reg);
8872 %}
8873
8874 instruct cmovLL_imm(cmpOp cmp, flagsRegL xcc, iRegL dst, immL0 src) %{
8875 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src)));
8876 ins_cost(140);
8877 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %}
8878 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
8879 ins_pipe(ialu_imm);
8880 %}
8881
8882 instruct cmovIL_reg(cmpOp cmp, flagsRegL xcc, iRegI dst, iRegI src) %{
8883 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src)));
8884 ins_cost(150);
8885 format %{ "MOV$cmp $xcc,$src,$dst" %}
8886 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
8887 ins_pipe(ialu_reg);
8888 %}
8889
8890 instruct cmovIL_imm(cmpOp cmp, flagsRegL xcc, iRegI dst, immI11 src) %{
8891 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src)));
8892 ins_cost(140);
8893 format %{ "MOV$cmp $xcc,$src,$dst" %}
8894 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
8895 ins_pipe(ialu_imm);
8896 %}
8897
8898 instruct cmovNL_reg(cmpOp cmp, flagsRegL xcc, iRegN dst, iRegN src) %{
8899 match(Set dst (CMoveN (Binary cmp xcc) (Binary dst src)));
8900 ins_cost(150);
8901 format %{ "MOV$cmp $xcc,$src,$dst" %}
8902 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
8903 ins_pipe(ialu_reg);
8904 %}
8905
8906 instruct cmovPL_reg(cmpOp cmp, flagsRegL xcc, iRegP dst, iRegP src) %{
8907 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src)));
8908 ins_cost(150);
8909 format %{ "MOV$cmp $xcc,$src,$dst" %}
8910 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
8911 ins_pipe(ialu_reg);
8912 %}
8913
8914 instruct cmovPL_imm(cmpOp cmp, flagsRegL xcc, iRegP dst, immP0 src) %{
8915 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src)));
8916 ins_cost(140);
8917 format %{ "MOV$cmp $xcc,$src,$dst" %}
8918 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
8919 ins_pipe(ialu_imm);
8920 %}
8921
8922 instruct cmovFL_reg(cmpOp cmp, flagsRegL xcc, regF dst, regF src) %{
8923 match(Set dst (CMoveF (Binary cmp xcc) (Binary dst src)));
8924 ins_cost(150);
8925 opcode(0x101);
8926 format %{ "FMOVS$cmp $xcc,$src,$dst" %}
8927 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) );
8928 ins_pipe(int_conditional_float_move);
8929 %}
8930
8931 instruct cmovDL_reg(cmpOp cmp, flagsRegL xcc, regD dst, regD src) %{
8932 match(Set dst (CMoveD (Binary cmp xcc) (Binary dst src)));
8933 ins_cost(150);
8934 opcode(0x102);
8935 format %{ "FMOVD$cmp $xcc,$src,$dst" %}
8936 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) );
8937 ins_pipe(int_conditional_float_move);
8938 %}
8939
8940 // ============================================================================
8941 // Safepoint Instruction
8942 instruct safePoint_poll(iRegP poll) %{
8943 match(SafePoint poll);
8944 effect(USE poll);
8945
8946 size(4);
8947 #ifdef _LP64
8948 format %{ "LDX [$poll],R_G0\t! Safepoint: poll for GC" %}
8949 #else
8950 format %{ "LDUW [$poll],R_G0\t! Safepoint: poll for GC" %}
8951 #endif
8952 ins_encode %{
8953 __ relocate(relocInfo::poll_type);
8954 __ ld_ptr($poll$$Register, 0, G0);
8955 %}
8956 ins_pipe(loadPollP);
8957 %}
8958
8959 // ============================================================================
8960 // Call Instructions
8961 // Call Java Static Instruction
8962 instruct CallStaticJavaDirect( method meth ) %{
8963 match(CallStaticJava);
8964 effect(USE meth);
8965
8966 size(8);
8967 ins_cost(CALL_COST);
8968 format %{ "CALL,static ; NOP ==> " %}
8969 ins_encode( Java_Static_Call( meth ), call_epilog );
8970 ins_pc_relative(1);
8971 ins_pipe(simple_call);
8972 %}
8973
8974 // Call Java Dynamic Instruction
8975 instruct CallDynamicJavaDirect( method meth ) %{
8976 match(CallDynamicJava);
8977 effect(USE meth);
8978
8979 ins_cost(CALL_COST);
8980 format %{ "SET (empty),R_G5\n\t"
8981 "CALL,dynamic ; NOP ==> " %}
8982 ins_encode( Java_Dynamic_Call( meth ), call_epilog );
8983 ins_pc_relative(1);
8984 ins_pipe(call);
8985 %}
8986
8987 // Call Runtime Instruction
8988 instruct CallRuntimeDirect(method meth, l7RegP l7) %{
8989 match(CallRuntime);
8990 effect(USE meth, KILL l7);
8991 ins_cost(CALL_COST);
8992 format %{ "CALL,runtime" %}
8993 ins_encode( Java_To_Runtime( meth ),
8994 call_epilog, adjust_long_from_native_call );
8995 ins_pc_relative(1);
8996 ins_pipe(simple_call);
8997 %}
8998
8999 // Call runtime without safepoint - same as CallRuntime
9000 instruct CallLeafDirect(method meth, l7RegP l7) %{
9001 match(CallLeaf);
9002 effect(USE meth, KILL l7);
9003 ins_cost(CALL_COST);
9004 format %{ "CALL,runtime leaf" %}
9005 ins_encode( Java_To_Runtime( meth ),
9006 call_epilog,
9007 adjust_long_from_native_call );
9008 ins_pc_relative(1);
9009 ins_pipe(simple_call);
9010 %}
9011
9012 // Call runtime without safepoint - same as CallLeaf
9013 instruct CallLeafNoFPDirect(method meth, l7RegP l7) %{
9014 match(CallLeafNoFP);
9015 effect(USE meth, KILL l7);
9016 ins_cost(CALL_COST);
9017 format %{ "CALL,runtime leaf nofp" %}
9018 ins_encode( Java_To_Runtime( meth ),
9019 call_epilog,
9020 adjust_long_from_native_call );
9021 ins_pc_relative(1);
9022 ins_pipe(simple_call);
9023 %}
9024
9025 // Tail Call; Jump from runtime stub to Java code.
9026 // Also known as an 'interprocedural jump'.
9027 // Target of jump will eventually return to caller.
9028 // TailJump below removes the return address.
9029 instruct TailCalljmpInd(g3RegP jump_target, inline_cache_regP method_oop) %{
9030 match(TailCall jump_target method_oop );
9031
9032 ins_cost(CALL_COST);
9033 format %{ "Jmp $jump_target ; NOP \t! $method_oop holds method oop" %}
9034 ins_encode(form_jmpl(jump_target));
9035 ins_pipe(tail_call);
9036 %}
9037
9038
9039 // Return Instruction
9040 instruct Ret() %{
9041 match(Return);
9042
9043 // The epilogue node did the ret already.
9044 size(0);
9045 format %{ "! return" %}
9046 ins_encode();
9047 ins_pipe(empty);
9048 %}
9049
9050
9051 // Tail Jump; remove the return address; jump to target.
9052 // TailCall above leaves the return address around.
9053 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2).
9054 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a
9055 // "restore" before this instruction (in Epilogue), we need to materialize it
9056 // in %i0.
9057 instruct tailjmpInd(g1RegP jump_target, i0RegP ex_oop) %{
9058 match( TailJump jump_target ex_oop );
9059 ins_cost(CALL_COST);
9060 format %{ "! discard R_O7\n\t"
9061 "Jmp $jump_target ; ADD O7,8,O1 \t! $ex_oop holds exc. oop" %}
9062 ins_encode(form_jmpl_set_exception_pc(jump_target));
9063 // opcode(Assembler::jmpl_op3, Assembler::arith_op);
9064 // The hack duplicates the exception oop into G3, so that CreateEx can use it there.
9065 // ins_encode( form3_rs1_simm13_rd( jump_target, 0x00, R_G0 ), move_return_pc_to_o1() );
9066 ins_pipe(tail_call);
9067 %}
9068
9069 // Create exception oop: created by stack-crawling runtime code.
9070 // Created exception is now available to this handler, and is setup
9071 // just prior to jumping to this handler. No code emitted.
9072 instruct CreateException( o0RegP ex_oop )
9073 %{
9074 match(Set ex_oop (CreateEx));
9075 ins_cost(0);
9076
9077 size(0);
9078 // use the following format syntax
9079 format %{ "! exception oop is in R_O0; no code emitted" %}
9080 ins_encode();
9081 ins_pipe(empty);
9082 %}
9083
9084
9085 // Rethrow exception:
9086 // The exception oop will come in the first argument position.
9087 // Then JUMP (not call) to the rethrow stub code.
9088 instruct RethrowException()
9089 %{
9090 match(Rethrow);
9091 ins_cost(CALL_COST);
9092
9093 // use the following format syntax
9094 format %{ "Jmp rethrow_stub" %}
9095 ins_encode(enc_rethrow);
9096 ins_pipe(tail_call);
9097 %}
9098
9099
9100 // Die now
9101 instruct ShouldNotReachHere( )
9102 %{
9103 match(Halt);
9104 ins_cost(CALL_COST);
9105
9106 size(4);
9107 // Use the following format syntax
9108 format %{ "ILLTRAP ; ShouldNotReachHere" %}
9109 ins_encode( form2_illtrap() );
9110 ins_pipe(tail_call);
9111 %}
9112
9113 // ============================================================================
9114 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
9115 // array for an instance of the superklass. Set a hidden internal cache on a
9116 // hit (cache is checked with exposed code in gen_subtype_check()). Return
9117 // not zero for a miss or zero for a hit. The encoding ALSO sets flags.
9118 instruct partialSubtypeCheck( o0RegP index, o1RegP sub, o2RegP super, flagsRegP pcc, o7RegP o7 ) %{
9119 match(Set index (PartialSubtypeCheck sub super));
9120 effect( KILL pcc, KILL o7 );
9121 ins_cost(DEFAULT_COST*10);
9122 format %{ "CALL PartialSubtypeCheck\n\tNOP" %}
9123 ins_encode( enc_PartialSubtypeCheck() );
9124 ins_pipe(partial_subtype_check_pipe);
9125 %}
9126
9127 instruct partialSubtypeCheck_vs_zero( flagsRegP pcc, o1RegP sub, o2RegP super, immP0 zero, o0RegP idx, o7RegP o7 ) %{
9128 match(Set pcc (CmpP (PartialSubtypeCheck sub super) zero));
9129 effect( KILL idx, KILL o7 );
9130 ins_cost(DEFAULT_COST*10);
9131 format %{ "CALL PartialSubtypeCheck\n\tNOP\t# (sets condition codes)" %}
9132 ins_encode( enc_PartialSubtypeCheck() );
9133 ins_pipe(partial_subtype_check_pipe);
9134 %}
9135
9136
9137 // ============================================================================
9138 // inlined locking and unlocking
9139
9140 instruct cmpFastLock(flagsRegP pcc, iRegP object, iRegP box, iRegP scratch2, o7RegP scratch ) %{
9141 match(Set pcc (FastLock object box));
9142
9143 effect(KILL scratch, TEMP scratch2);
9144 ins_cost(100);
9145
9146 size(4*112); // conservative overestimation ...
9147 format %{ "FASTLOCK $object, $box; KILL $scratch, $scratch2, $box" %}
9148 ins_encode( Fast_Lock(object, box, scratch, scratch2) );
9149 ins_pipe(long_memory_op);
9150 %}
9151
9152
9153 instruct cmpFastUnlock(flagsRegP pcc, iRegP object, iRegP box, iRegP scratch2, o7RegP scratch ) %{
9154 match(Set pcc (FastUnlock object box));
9155 effect(KILL scratch, TEMP scratch2);
9156 ins_cost(100);
9157
9158 size(4*120); // conservative overestimation ...
9159 format %{ "FASTUNLOCK $object, $box; KILL $scratch, $scratch2, $box" %}
9160 ins_encode( Fast_Unlock(object, box, scratch, scratch2) );
9161 ins_pipe(long_memory_op);
9162 %}
9163
9164 // Count and Base registers are fixed because the allocator cannot
9165 // kill unknown registers. The encodings are generic.
9166 instruct clear_array(iRegX cnt, iRegP base, iRegX temp, Universe dummy, flagsReg ccr) %{
9167 match(Set dummy (ClearArray cnt base));
9168 effect(TEMP temp, KILL ccr);
9169 ins_cost(300);
9170 format %{ "MOV $cnt,$temp\n"
9171 "loop: SUBcc $temp,8,$temp\t! Count down a dword of bytes\n"
9172 " BRge loop\t\t! Clearing loop\n"
9173 " STX G0,[$base+$temp]\t! delay slot" %}
9174 ins_encode( enc_Clear_Array(cnt, base, temp) );
9175 ins_pipe(long_memory_op);
9176 %}
9177
9178 instruct string_compare(o0RegP str1, o1RegP str2, g3RegP tmp1, g4RegP tmp2, notemp_iRegI result,
9179 o7RegI tmp3, flagsReg ccr) %{
9180 match(Set result (StrComp str1 str2));
9181 effect(USE_KILL str1, USE_KILL str2, KILL tmp1, KILL tmp2, KILL ccr, KILL tmp3);
9182 ins_cost(300);
9183 format %{ "String Compare $str1,$str2 -> $result" %}
9184 ins_encode( enc_String_Compare(str1, str2, tmp1, tmp2, result) );
9185 ins_pipe(long_memory_op);
9186 %}
9187
9188 instruct string_equals(o0RegP str1, o1RegP str2, g3RegP tmp1, g4RegP tmp2, notemp_iRegI result,
9189 o7RegI tmp3, flagsReg ccr) %{
9190 match(Set result (StrEquals str1 str2));
9191 effect(USE_KILL str1, USE_KILL str2, KILL tmp1, KILL tmp2, KILL ccr, KILL tmp3);
9192 ins_cost(300);
9193 format %{ "String Equals $str1,$str2 -> $result" %}
9194 ins_encode( enc_String_Equals(str1, str2, tmp1, tmp2, result) );
9195 ins_pipe(long_memory_op);
9196 %}
9197
9198 instruct array_equals(o0RegP ary1, o1RegP ary2, g3RegP tmp1, g4RegP tmp2, notemp_iRegI result,
9199 flagsReg ccr) %{
9200 match(Set result (AryEq ary1 ary2));
9201 effect(USE_KILL ary1, USE_KILL ary2, KILL tmp1, KILL tmp2, KILL ccr);
9202 ins_cost(300);
9203 format %{ "Array Equals $ary1,$ary2 -> $result" %}
9204 ins_encode( enc_Array_Equals(ary1, ary2, tmp1, tmp2, result));
9205 ins_pipe(long_memory_op);
9206 %}
9207
9208
9209 //---------- Zeros Count Instructions ------------------------------------------
9210
9211 instruct countLeadingZerosI(iRegI dst, iRegI src, iRegI tmp, flagsReg cr) %{
9212 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
9213 match(Set dst (CountLeadingZerosI src));
9214 effect(TEMP dst, TEMP tmp, KILL cr);
9215
9216 // x |= (x >> 1);
9217 // x |= (x >> 2);
9218 // x |= (x >> 4);
9219 // x |= (x >> 8);
9220 // x |= (x >> 16);
9221 // return (WORDBITS - popc(x));
9222 format %{ "SRL $src,1,$dst\t! count leading zeros (int)\n\t"
9223 "OR $src,$tmp,$dst\n\t"
9224 "SRL $dst,2,$tmp\n\t"
9225 "OR $dst,$tmp,$dst\n\t"
9226 "SRL $dst,4,$tmp\n\t"
9227 "OR $dst,$tmp,$dst\n\t"
9228 "SRL $dst,8,$tmp\n\t"
9229 "OR $dst,$tmp,$dst\n\t"
9230 "SRL $dst,16,$tmp\n\t"
9231 "OR $dst,$tmp,$dst\n\t"
9232 "POPC $dst,$dst\n\t"
9233 "MOV 32,$tmp\n\t"
9234 "SUB $tmp,$dst,$dst" %}
9235 ins_encode %{
9236 Register Rdst = $dst$$Register;
9237 Register Rsrc = $src$$Register;
9238 Register Rtmp = $tmp$$Register;
9239 __ srl(Rsrc, 1, Rtmp);
9240 __ or3(Rsrc, Rtmp, Rdst);
9241 __ srl(Rdst, 2, Rtmp);
9242 __ or3(Rdst, Rtmp, Rdst);
9243 __ srl(Rdst, 4, Rtmp);
9244 __ or3(Rdst, Rtmp, Rdst);
9245 __ srl(Rdst, 8, Rtmp);
9246 __ or3(Rdst, Rtmp, Rdst);
9247 __ srl(Rdst, 16, Rtmp);
9248 __ or3(Rdst, Rtmp, Rdst);
9249 __ popc(Rdst, Rdst);
9250 __ mov(BitsPerInt, Rtmp);
9251 __ sub(Rtmp, Rdst, Rdst);
9252 %}
9253 ins_pipe(ialu_reg);
9254 %}
9255
9256 instruct countLeadingZerosL(iRegI dst, iRegL src, iRegL tmp, flagsReg cr) %{
9257 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
9258 match(Set dst (CountLeadingZerosL src));
9259 effect(TEMP dst, TEMP tmp, KILL cr);
9260
9261 // x |= (x >> 1);
9262 // x |= (x >> 2);
9263 // x |= (x >> 4);
9264 // x |= (x >> 8);
9265 // x |= (x >> 16);
9266 // x |= (x >> 32);
9267 // return (WORDBITS - popc(x));
9268 format %{ "SRLX $src,1,$dst\t! count leading zeros (long)\n\t"
9269 "OR $src,$tmp,$dst\n\t"
9270 "SRLX $dst,2,$tmp\n\t"
9271 "OR $dst,$tmp,$dst\n\t"
9272 "SRLX $dst,4,$tmp\n\t"
9273 "OR $dst,$tmp,$dst\n\t"
9274 "SRLX $dst,8,$tmp\n\t"
9275 "OR $dst,$tmp,$dst\n\t"
9276 "SRLX $dst,16,$tmp\n\t"
9277 "OR $dst,$tmp,$dst\n\t"
9278 "SRLX $dst,32,$tmp\n\t"
9279 "OR $dst,$tmp,$dst\n\t"
9280 "POPC $dst,$dst\n\t"
9281 "MOV 64,$tmp\n\t"
9282 "SUB $tmp,$dst,$dst" %}
9283 ins_encode %{
9284 Register Rdst = $dst$$Register;
9285 Register Rsrc = $src$$Register;
9286 Register Rtmp = $tmp$$Register;
9287 __ srlx(Rsrc, 1, Rtmp);
9288 __ or3(Rsrc, Rtmp, Rdst);
9289 __ srlx(Rdst, 2, Rtmp);
9290 __ or3(Rdst, Rtmp, Rdst);
9291 __ srlx(Rdst, 4, Rtmp);
9292 __ or3(Rdst, Rtmp, Rdst);
9293 __ srlx(Rdst, 8, Rtmp);
9294 __ or3(Rdst, Rtmp, Rdst);
9295 __ srlx(Rdst, 16, Rtmp);
9296 __ or3(Rdst, Rtmp, Rdst);
9297 __ srlx(Rdst, 32, Rtmp);
9298 __ or3(Rdst, Rtmp, Rdst);
9299 __ popc(Rdst, Rdst);
9300 __ mov(BitsPerLong, Rtmp);
9301 __ sub(Rtmp, Rdst, Rdst);
9302 %}
9303 ins_pipe(ialu_reg);
9304 %}
9305
9306 instruct countTrailingZerosI(iRegI dst, iRegI src, flagsReg cr) %{
9307 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
9308 match(Set dst (CountTrailingZerosI src));
9309 effect(TEMP dst, KILL cr);
9310
9311 // return popc(~x & (x - 1));
9312 format %{ "SUB $src,1,$dst\t! count trailing zeros (int)\n\t"
9313 "ANDN $dst,$src,$dst\n\t"
9314 "SRL $dst,R_G0,$dst\n\t"
9315 "POPC $dst,$dst" %}
9316 ins_encode %{
9317 Register Rdst = $dst$$Register;
9318 Register Rsrc = $src$$Register;
9319 __ sub(Rsrc, 1, Rdst);
9320 __ andn(Rdst, Rsrc, Rdst);
9321 __ srl(Rdst, G0, Rdst);
9322 __ popc(Rdst, Rdst);
9323 %}
9324 ins_pipe(ialu_reg);
9325 %}
9326
9327 instruct countTrailingZerosL(iRegI dst, iRegL src, flagsReg cr) %{
9328 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
9329 match(Set dst (CountTrailingZerosL src));
9330 effect(TEMP dst, KILL cr);
9331
9332 // return popc(~x & (x - 1));
9333 format %{ "SUB $src,1,$dst\t! count trailing zeros (long)\n\t"
9334 "ANDN $dst,$src,$dst\n\t"
9335 "POPC $dst,$dst" %}
9336 ins_encode %{
9337 Register Rdst = $dst$$Register;
9338 Register Rsrc = $src$$Register;
9339 __ sub(Rsrc, 1, Rdst);
9340 __ andn(Rdst, Rsrc, Rdst);
9341 __ popc(Rdst, Rdst);
9342 %}
9343 ins_pipe(ialu_reg);
9344 %}
9345
9346
9347 //---------- Population Count Instructions -------------------------------------
9348
9349 instruct popCountI(iRegI dst, iRegI src) %{
9350 predicate(UsePopCountInstruction);
9351 match(Set dst (PopCountI src));
9352
9353 format %{ "POPC $src, $dst" %}
9354 ins_encode %{
9355 __ popc($src$$Register, $dst$$Register);
9356 %}
9357 ins_pipe(ialu_reg);
9358 %}
9359
9360 // Note: Long.bitCount(long) returns an int.
9361 instruct popCountL(iRegI dst, iRegL src) %{
9362 predicate(UsePopCountInstruction);
9363 match(Set dst (PopCountL src));
9364
9365 format %{ "POPC $src, $dst" %}
9366 ins_encode %{
9367 __ popc($src$$Register, $dst$$Register);
9368 %}
9369 ins_pipe(ialu_reg);
9370 %}
9371
9372
9373 // ============================================================================
9374 //------------Bytes reverse--------------------------------------------------
9375
9376 instruct bytes_reverse_int(iRegI dst, stackSlotI src) %{
9377 match(Set dst (ReverseBytesI src));
9378 effect(DEF dst, USE src);
9379
9380 // Op cost is artificially doubled to make sure that load or store
9381 // instructions are preferred over this one which requires a spill
9382 // onto a stack slot.
9383 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
9384 size(8);
9385 format %{ "LDUWA $src, $dst\t!asi=primary_little" %}
9386 opcode(Assembler::lduwa_op3);
9387 ins_encode( form3_mem_reg_little(src, dst) );
9388 ins_pipe( iload_mem );
9389 %}
9390
9391 instruct bytes_reverse_long(iRegL dst, stackSlotL src) %{
9392 match(Set dst (ReverseBytesL src));
9393 effect(DEF dst, USE src);
9394
9395 // Op cost is artificially doubled to make sure that load or store
9396 // instructions are preferred over this one which requires a spill
9397 // onto a stack slot.
9398 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
9399 size(8);
9400 format %{ "LDXA $src, $dst\t!asi=primary_little" %}
9401
9402 opcode(Assembler::ldxa_op3);
9403 ins_encode( form3_mem_reg_little(src, dst) );
9404 ins_pipe( iload_mem );
9405 %}
9406
9407 // Load Integer reversed byte order
9408 instruct loadI_reversed(iRegI dst, memory src) %{
9409 match(Set dst (ReverseBytesI (LoadI src)));
9410
9411 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
9412 size(8);
9413 format %{ "LDUWA $src, $dst\t!asi=primary_little" %}
9414
9415 opcode(Assembler::lduwa_op3);
9416 ins_encode( form3_mem_reg_little( src, dst) );
9417 ins_pipe(iload_mem);
9418 %}
9419
9420 // Load Long - aligned and reversed
9421 instruct loadL_reversed(iRegL dst, memory src) %{
9422 match(Set dst (ReverseBytesL (LoadL src)));
9423
9424 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
9425 size(8);
9426 format %{ "LDXA $src, $dst\t!asi=primary_little" %}
9427
9428 opcode(Assembler::ldxa_op3);
9429 ins_encode( form3_mem_reg_little( src, dst ) );
9430 ins_pipe(iload_mem);
9431 %}
9432
9433 // Store Integer reversed byte order
9434 instruct storeI_reversed(memory dst, iRegI src) %{
9435 match(Set dst (StoreI dst (ReverseBytesI src)));
9436
9437 ins_cost(MEMORY_REF_COST);
9438 size(8);
9439 format %{ "STWA $src, $dst\t!asi=primary_little" %}
9440
9441 opcode(Assembler::stwa_op3);
9442 ins_encode( form3_mem_reg_little( dst, src) );
9443 ins_pipe(istore_mem_reg);
9444 %}
9445
9446 // Store Long reversed byte order
9447 instruct storeL_reversed(memory dst, iRegL src) %{
9448 match(Set dst (StoreL dst (ReverseBytesL src)));
9449
9450 ins_cost(MEMORY_REF_COST);
9451 size(8);
9452 format %{ "STXA $src, $dst\t!asi=primary_little" %}
9453
9454 opcode(Assembler::stxa_op3);
9455 ins_encode( form3_mem_reg_little( dst, src) );
9456 ins_pipe(istore_mem_reg);
9457 %}
9458
9459 //----------PEEPHOLE RULES-----------------------------------------------------
9460 // These must follow all instruction definitions as they use the names
9461 // defined in the instructions definitions.
9462 //
9463 // peepmatch ( root_instr_name [preceding_instruction]* );
9464 //
9465 // peepconstraint %{
9466 // (instruction_number.operand_name relational_op instruction_number.operand_name
9467 // [, ...] );
9468 // // instruction numbers are zero-based using left to right order in peepmatch
9469 //
9470 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
9471 // // provide an instruction_number.operand_name for each operand that appears
9472 // // in the replacement instruction's match rule
9473 //
9474 // ---------VM FLAGS---------------------------------------------------------
9475 //
9476 // All peephole optimizations can be turned off using -XX:-OptoPeephole
9477 //
9478 // Each peephole rule is given an identifying number starting with zero and
9479 // increasing by one in the order seen by the parser. An individual peephole
9480 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
9481 // on the command-line.
9482 //
9483 // ---------CURRENT LIMITATIONS----------------------------------------------
9484 //
9485 // Only match adjacent instructions in same basic block
9486 // Only equality constraints
9487 // Only constraints between operands, not (0.dest_reg == EAX_enc)
9488 // Only one replacement instruction
9489 //
9490 // ---------EXAMPLE----------------------------------------------------------
9491 //
9492 // // pertinent parts of existing instructions in architecture description
9493 // instruct movI(eRegI dst, eRegI src) %{
9494 // match(Set dst (CopyI src));
9495 // %}
9496 //
9497 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
9498 // match(Set dst (AddI dst src));
9499 // effect(KILL cr);
9500 // %}
9501 //
9502 // // Change (inc mov) to lea
9503 // peephole %{
9504 // // increment preceeded by register-register move
9505 // peepmatch ( incI_eReg movI );
9506 // // require that the destination register of the increment
9507 // // match the destination register of the move
9508 // peepconstraint ( 0.dst == 1.dst );
9509 // // construct a replacement instruction that sets
9510 // // the destination to ( move's source register + one )
9511 // peepreplace ( incI_eReg_immI1( 0.dst 1.src 0.src ) );
9512 // %}
9513 //
9514
9515 // // Change load of spilled value to only a spill
9516 // instruct storeI(memory mem, eRegI src) %{
9517 // match(Set mem (StoreI mem src));
9518 // %}
9519 //
9520 // instruct loadI(eRegI dst, memory mem) %{
9521 // match(Set dst (LoadI mem));
9522 // %}
9523 //
9524 // peephole %{
9525 // peepmatch ( loadI storeI );
9526 // peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
9527 // peepreplace ( storeI( 1.mem 1.mem 1.src ) );
9528 // %}
9529
9530 //----------SMARTSPILL RULES---------------------------------------------------
9531 // These must follow all instruction definitions as they use the names
9532 // defined in the instructions definitions.
9533 //
9534 // SPARC will probably not have any of these rules due to RISC instruction set.
9535
9536 //----------PIPELINE-----------------------------------------------------------
9537 // Rules which define the behavior of the target architectures pipeline.