*** old/src/cpu/x86/vm/assembler_x86.cpp	Mon May  4 21:36:23 2009
--- new/src/cpu/x86/vm/assembler_x86.cpp	Mon May  4 21:36:23 2009

*** 950,959 ****
--- 950,974 ----
    emit_byte(0x0F);
    emit_byte(0x54);
    emit_operand(dst, src);
  }
  
+ void Assembler::bsfl(Register dst, Register src) {
+   int encode = prefix_and_encode(dst->encoding(), src->encoding());
+   emit_byte(0x0F);
+   emit_byte(0xBC);
+   emit_byte(0xC0 | encode);
+ }
+ 
+ void Assembler::bsrl(Register dst, Register src) {
+   assert(!VM_Version::supports_lzcnt(), "encoding is treated as LZCNT");
+   int encode = prefix_and_encode(dst->encoding(), src->encoding());
+   emit_byte(0x0F);
+   emit_byte(0xBD);
+   emit_byte(0xC0 | encode);
+ }
+ 
  void Assembler::bswapl(Register reg) { // bswap
    int encode = prefix_and_encode(reg->encoding());
    emit_byte(0x0F);
    emit_byte(0xC8 | encode);
  }

*** 1436,1445 ****
--- 1451,1469 ----
    } else {
       emit_byte(0xF0);
    }
  }
  
+ void Assembler::lzcntl(Register dst, Register src) {
+   assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
+   emit_byte(0xF3);
+   int encode = prefix_and_encode(dst->encoding(), src->encoding());
+   emit_byte(0x0F);
+   emit_byte(0xBD);
+   emit_byte(0xC0 | encode);
+ }
+ 
  // Emit mfence instruction
  void Assembler::mfence() {
    NOT_LP64(assert(VM_Version::supports_sse2(), "unsupported");)
    emit_byte( 0x0F );
    emit_byte( 0xAE );

*** 3686,3695 ****
--- 3710,3734 ----
  void Assembler::andq(Register dst, Register src) {
    (int) prefixq_and_encode(dst->encoding(), src->encoding());
    emit_arith(0x23, 0xC0, dst, src);
  }
  
+ void Assembler::bsfq(Register dst, Register src) {
+   int encode = prefixq_and_encode(dst->encoding(), src->encoding());
+   emit_byte(0x0F);
+   emit_byte(0xBC);
+   emit_byte(0xC0 | encode);
+ }
+ 
+ void Assembler::bsrq(Register dst, Register src) {
+   assert(!VM_Version::supports_lzcnt(), "encoding is treated as LZCNT");
+   int encode = prefixq_and_encode(dst->encoding(), src->encoding());
+   emit_byte(0x0F);
+   emit_byte(0xBD);
+   emit_byte(0xC0 | encode);
+ }
+ 
  void Assembler::bswapq(Register reg) {
    int encode = prefixq_and_encode(reg->encoding());
    emit_byte(0x0F);
    emit_byte(0xC8 | encode);
  }

*** 3939,3948 ****
--- 3978,3996 ----
    emit_byte(0x81);
    emit_operand(rax, src1, 4);
    emit_data((int)imm32, rspec, narrow_oop_operand);
  }
  
+ void Assembler::lzcntq(Register dst, Register src) {
+   assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
+   emit_byte(0xF3);
+   int encode = prefixq_and_encode(dst->encoding(), src->encoding());
+   emit_byte(0x0F);
+   emit_byte(0xBD);
+   emit_byte(0xC0 | encode);
+ }
+ 
  void Assembler::movdq(XMMRegister dst, Register src) {
    // table D-1 says MMX/SSE2
    NOT_LP64(assert(VM_Version::supports_sse2() || VM_Version::supports_mmx(), ""));
    emit_byte(0x66);
    int encode = prefixq_and_encode(dst->encoding(), src->encoding());