1 /*
2 * Copyright 1997-2009 Sun Microsystems, Inc. All Rights Reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
20 * CA 95054 USA or visit www.sun.com if you need additional information or
21 * have any questions.
22 *
23 */
24
25 class BiasedLockingCounters;
26
27 // Contains all the definitions needed for x86 assembly code generation.
28
29 // Calling convention
30 class Argument VALUE_OBJ_CLASS_SPEC {
31 public:
32 enum {
33 #ifdef _LP64
34 #ifdef _WIN64
35 n_int_register_parameters_c = 4, // rcx, rdx, r8, r9 (c_rarg0, c_rarg1, ...)
36 n_float_register_parameters_c = 4, // xmm0 - xmm3 (c_farg0, c_farg1, ... )
37 #else
38 n_int_register_parameters_c = 6, // rdi, rsi, rdx, rcx, r8, r9 (c_rarg0, c_rarg1, ...)
39 n_float_register_parameters_c = 8, // xmm0 - xmm7 (c_farg0, c_farg1, ... )
40 #endif // _WIN64
41 n_int_register_parameters_j = 6, // j_rarg0, j_rarg1, ...
42 n_float_register_parameters_j = 8 // j_farg0, j_farg1, ...
43 #else
44 n_register_parameters = 0 // 0 registers used to pass arguments
45 #endif // _LP64
46 };
47 };
48
49
50 #ifdef _LP64
51 // Symbolically name the register arguments used by the c calling convention.
52 // Windows is different from linux/solaris. So much for standards...
53
54 #ifdef _WIN64
55
56 REGISTER_DECLARATION(Register, c_rarg0, rcx);
57 REGISTER_DECLARATION(Register, c_rarg1, rdx);
58 REGISTER_DECLARATION(Register, c_rarg2, r8);
59 REGISTER_DECLARATION(Register, c_rarg3, r9);
60
61 REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0);
62 REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1);
63 REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2);
64 REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3);
65
66 #else
67
68 REGISTER_DECLARATION(Register, c_rarg0, rdi);
69 REGISTER_DECLARATION(Register, c_rarg1, rsi);
70 REGISTER_DECLARATION(Register, c_rarg2, rdx);
71 REGISTER_DECLARATION(Register, c_rarg3, rcx);
72 REGISTER_DECLARATION(Register, c_rarg4, r8);
73 REGISTER_DECLARATION(Register, c_rarg5, r9);
74
75 REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0);
76 REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1);
77 REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2);
78 REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3);
79 REGISTER_DECLARATION(XMMRegister, c_farg4, xmm4);
80 REGISTER_DECLARATION(XMMRegister, c_farg5, xmm5);
81 REGISTER_DECLARATION(XMMRegister, c_farg6, xmm6);
82 REGISTER_DECLARATION(XMMRegister, c_farg7, xmm7);
83
84 #endif // _WIN64
85
86 // Symbolically name the register arguments used by the Java calling convention.
87 // We have control over the convention for java so we can do what we please.
88 // What pleases us is to offset the java calling convention so that when
89 // we call a suitable jni method the arguments are lined up and we don't
90 // have to do little shuffling. A suitable jni method is non-static and a
91 // small number of arguments (two fewer args on windows)
92 //
93 // |-------------------------------------------------------|
94 // | c_rarg0 c_rarg1 c_rarg2 c_rarg3 c_rarg4 c_rarg5 |
95 // |-------------------------------------------------------|
96 // | rcx rdx r8 r9 rdi* rsi* | windows (* not a c_rarg)
97 // | rdi rsi rdx rcx r8 r9 | solaris/linux
98 // |-------------------------------------------------------|
99 // | j_rarg5 j_rarg0 j_rarg1 j_rarg2 j_rarg3 j_rarg4 |
100 // |-------------------------------------------------------|
101
102 REGISTER_DECLARATION(Register, j_rarg0, c_rarg1);
103 REGISTER_DECLARATION(Register, j_rarg1, c_rarg2);
104 REGISTER_DECLARATION(Register, j_rarg2, c_rarg3);
105 // Windows runs out of register args here
106 #ifdef _WIN64
107 REGISTER_DECLARATION(Register, j_rarg3, rdi);
108 REGISTER_DECLARATION(Register, j_rarg4, rsi);
109 #else
110 REGISTER_DECLARATION(Register, j_rarg3, c_rarg4);
111 REGISTER_DECLARATION(Register, j_rarg4, c_rarg5);
112 #endif /* _WIN64 */
113 REGISTER_DECLARATION(Register, j_rarg5, c_rarg0);
114
115 REGISTER_DECLARATION(XMMRegister, j_farg0, xmm0);
116 REGISTER_DECLARATION(XMMRegister, j_farg1, xmm1);
117 REGISTER_DECLARATION(XMMRegister, j_farg2, xmm2);
118 REGISTER_DECLARATION(XMMRegister, j_farg3, xmm3);
119 REGISTER_DECLARATION(XMMRegister, j_farg4, xmm4);
120 REGISTER_DECLARATION(XMMRegister, j_farg5, xmm5);
121 REGISTER_DECLARATION(XMMRegister, j_farg6, xmm6);
122 REGISTER_DECLARATION(XMMRegister, j_farg7, xmm7);
123
124 REGISTER_DECLARATION(Register, rscratch1, r10); // volatile
125 REGISTER_DECLARATION(Register, rscratch2, r11); // volatile
126
127 REGISTER_DECLARATION(Register, r12_heapbase, r12); // callee-saved
128 REGISTER_DECLARATION(Register, r15_thread, r15); // callee-saved
129
130 #else
131 // rscratch1 will apear in 32bit code that is dead but of course must compile
132 // Using noreg ensures if the dead code is incorrectly live and executed it
133 // will cause an assertion failure
134 #define rscratch1 noreg
135
136 #endif // _LP64
137
138 // Address is an abstraction used to represent a memory location
139 // using any of the amd64 addressing modes with one object.
140 //
141 // Note: A register location is represented via a Register, not
142 // via an address for efficiency & simplicity reasons.
143
144 class ArrayAddress;
145
146 class Address VALUE_OBJ_CLASS_SPEC {
147 public:
148 enum ScaleFactor {
149 no_scale = -1,
150 times_1 = 0,
151 times_2 = 1,
152 times_4 = 2,
153 times_8 = 3,
154 times_ptr = LP64_ONLY(times_8) NOT_LP64(times_4)
155 };
156 static ScaleFactor times(int size) {
157 assert(size >= 1 && size <= 8 && is_power_of_2(size), "bad scale size");
158 if (size == 8) return times_8;
159 if (size == 4) return times_4;
160 if (size == 2) return times_2;
161 return times_1;
162 }
163 static int scale_size(ScaleFactor scale) {
164 assert(scale != no_scale, "");
165 assert(((1 << (int)times_1) == 1 &&
166 (1 << (int)times_2) == 2 &&
167 (1 << (int)times_4) == 4 &&
168 (1 << (int)times_8) == 8), "");
169 return (1 << (int)scale);
170 }
171
172 private:
173 Register _base;
174 Register _index;
175 ScaleFactor _scale;
176 int _disp;
177 RelocationHolder _rspec;
178
179 // Easily misused constructors make them private
180 // %%% can we make these go away?
181 NOT_LP64(Address(address loc, RelocationHolder spec);)
182 Address(int disp, address loc, relocInfo::relocType rtype);
183 Address(int disp, address loc, RelocationHolder spec);
184
185 public:
186
187 int disp() { return _disp; }
188 // creation
189 Address()
190 : _base(noreg),
191 _index(noreg),
192 _scale(no_scale),
193 _disp(0) {
194 }
195
196 // No default displacement otherwise Register can be implicitly
197 // converted to 0(Register) which is quite a different animal.
198
199 Address(Register base, int disp)
200 : _base(base),
201 _index(noreg),
202 _scale(no_scale),
203 _disp(disp) {
204 }
205
206 Address(Register base, Register index, ScaleFactor scale, int disp = 0)
207 : _base (base),
208 _index(index),
209 _scale(scale),
210 _disp (disp) {
211 assert(!index->is_valid() == (scale == Address::no_scale),
212 "inconsistent address");
213 }
214
215 Address(Register base, RegisterOrConstant index, ScaleFactor scale = times_1, int disp = 0)
216 : _base (base),
217 _index(index.register_or_noreg()),
218 _scale(scale),
219 _disp (disp + (index.constant_or_zero() * scale_size(scale))) {
220 if (!index.is_register()) scale = Address::no_scale;
221 assert(!_index->is_valid() == (scale == Address::no_scale),
222 "inconsistent address");
223 }
224
225 Address plus_disp(int disp) const {
226 Address a = (*this);
227 a._disp += disp;
228 return a;
229 }
230
231 // The following two overloads are used in connection with the
232 // ByteSize type (see sizes.hpp). They simplify the use of
233 // ByteSize'd arguments in assembly code. Note that their equivalent
234 // for the optimized build are the member functions with int disp
235 // argument since ByteSize is mapped to an int type in that case.
236 //
237 // Note: DO NOT introduce similar overloaded functions for WordSize
238 // arguments as in the optimized mode, both ByteSize and WordSize
239 // are mapped to the same type and thus the compiler cannot make a
240 // distinction anymore (=> compiler errors).
241
242 #ifdef ASSERT
243 Address(Register base, ByteSize disp)
244 : _base(base),
245 _index(noreg),
246 _scale(no_scale),
247 _disp(in_bytes(disp)) {
248 }
249
250 Address(Register base, Register index, ScaleFactor scale, ByteSize disp)
251 : _base(base),
252 _index(index),
253 _scale(scale),
254 _disp(in_bytes(disp)) {
255 assert(!index->is_valid() == (scale == Address::no_scale),
256 "inconsistent address");
257 }
258
259 Address(Register base, RegisterOrConstant index, ScaleFactor scale, ByteSize disp)
260 : _base (base),
261 _index(index.register_or_noreg()),
262 _scale(scale),
263 _disp (in_bytes(disp) + (index.constant_or_zero() * scale_size(scale))) {
264 if (!index.is_register()) scale = Address::no_scale;
265 assert(!_index->is_valid() == (scale == Address::no_scale),
266 "inconsistent address");
267 }
268
269 #endif // ASSERT
270
271 // accessors
272 bool uses(Register reg) const { return _base == reg || _index == reg; }
273 Register base() const { return _base; }
274 Register index() const { return _index; }
275 ScaleFactor scale() const { return _scale; }
276 int disp() const { return _disp; }
277
278 // Convert the raw encoding form into the form expected by the constructor for
279 // Address. An index of 4 (rsp) corresponds to having no index, so convert
280 // that to noreg for the Address constructor.
281 static Address make_raw(int base, int index, int scale, int disp, bool disp_is_oop);
282
283 static Address make_array(ArrayAddress);
284
285 private:
286 bool base_needs_rex() const {
287 return _base != noreg && _base->encoding() >= 8;
288 }
289
290 bool index_needs_rex() const {
291 return _index != noreg &&_index->encoding() >= 8;
292 }
293
294 relocInfo::relocType reloc() const { return _rspec.type(); }
295
296 friend class Assembler;
297 friend class MacroAssembler;
298 friend class LIR_Assembler; // base/index/scale/disp
299 };
300
301 //
302 // AddressLiteral has been split out from Address because operands of this type
303 // need to be treated specially on 32bit vs. 64bit platforms. By splitting it out
304 // the few instructions that need to deal with address literals are unique and the
305 // MacroAssembler does not have to implement every instruction in the Assembler
306 // in order to search for address literals that may need special handling depending
307 // on the instruction and the platform. As small step on the way to merging i486/amd64
308 // directories.
309 //
310 class AddressLiteral VALUE_OBJ_CLASS_SPEC {
311 friend class ArrayAddress;
312 RelocationHolder _rspec;
313 // Typically we use AddressLiterals we want to use their rval
314 // However in some situations we want the lval (effect address) of the item.
315 // We provide a special factory for making those lvals.
316 bool _is_lval;
317
318 // If the target is far we'll need to load the ea of this to
319 // a register to reach it. Otherwise if near we can do rip
320 // relative addressing.
321
322 address _target;
323
324 protected:
325 // creation
326 AddressLiteral()
327 : _is_lval(false),
328 _target(NULL)
329 {}
330
331 public:
332
333
334 AddressLiteral(address target, relocInfo::relocType rtype);
335
336 AddressLiteral(address target, RelocationHolder const& rspec)
337 : _rspec(rspec),
338 _is_lval(false),
339 _target(target)
340 {}
341
342 AddressLiteral addr() {
343 AddressLiteral ret = *this;
344 ret._is_lval = true;
345 return ret;
346 }
347
348
349 private:
350
351 address target() { return _target; }
352 bool is_lval() { return _is_lval; }
353
354 relocInfo::relocType reloc() const { return _rspec.type(); }
355 const RelocationHolder& rspec() const { return _rspec; }
356
357 friend class Assembler;
358 friend class MacroAssembler;
359 friend class Address;
360 friend class LIR_Assembler;
361 };
362
363 // Convience classes
364 class RuntimeAddress: public AddressLiteral {
365
366 public:
367
368 RuntimeAddress(address target) : AddressLiteral(target, relocInfo::runtime_call_type) {}
369
370 };
371
372 class OopAddress: public AddressLiteral {
373
374 public:
375
376 OopAddress(address target) : AddressLiteral(target, relocInfo::oop_type){}
377
378 };
379
380 class ExternalAddress: public AddressLiteral {
381
382 public:
383
384 ExternalAddress(address target) : AddressLiteral(target, relocInfo::external_word_type){}
385
386 };
387
388 class InternalAddress: public AddressLiteral {
389
390 public:
391
392 InternalAddress(address target) : AddressLiteral(target, relocInfo::internal_word_type) {}
393
394 };
395
396 // x86 can do array addressing as a single operation since disp can be an absolute
397 // address amd64 can't. We create a class that expresses the concept but does extra
398 // magic on amd64 to get the final result
399
400 class ArrayAddress VALUE_OBJ_CLASS_SPEC {
401 private:
402
403 AddressLiteral _base;
404 Address _index;
405
406 public:
407
408 ArrayAddress() {};
409 ArrayAddress(AddressLiteral base, Address index): _base(base), _index(index) {};
410 AddressLiteral base() { return _base; }
411 Address index() { return _index; }
412
413 };
414
415 const int FPUStateSizeInWords = NOT_LP64(27) LP64_ONLY( 512 / wordSize);
416
417 // The Intel x86/Amd64 Assembler: Pure assembler doing NO optimizations on the instruction
418 // level (e.g. mov rax, 0 is not translated into xor rax, rax!); i.e., what you write
419 // is what you get. The Assembler is generating code into a CodeBuffer.
420
421 class Assembler : public AbstractAssembler {
422 friend class AbstractAssembler; // for the non-virtual hack
423 friend class LIR_Assembler; // as_Address()
424 friend class StubGenerator;
425
426 public:
427 enum Condition { // The x86 condition codes used for conditional jumps/moves.
428 zero = 0x4,
429 notZero = 0x5,
430 equal = 0x4,
431 notEqual = 0x5,
432 less = 0xc,
433 lessEqual = 0xe,
434 greater = 0xf,
435 greaterEqual = 0xd,
436 below = 0x2,
437 belowEqual = 0x6,
438 above = 0x7,
439 aboveEqual = 0x3,
440 overflow = 0x0,
441 noOverflow = 0x1,
442 carrySet = 0x2,
443 carryClear = 0x3,
444 negative = 0x8,
445 positive = 0x9,
446 parity = 0xa,
447 noParity = 0xb
448 };
449
450 enum Prefix {
451 // segment overrides
452 CS_segment = 0x2e,
453 SS_segment = 0x36,
454 DS_segment = 0x3e,
455 ES_segment = 0x26,
456 FS_segment = 0x64,
457 GS_segment = 0x65,
458
459 REX = 0x40,
460
461 REX_B = 0x41,
462 REX_X = 0x42,
463 REX_XB = 0x43,
464 REX_R = 0x44,
465 REX_RB = 0x45,
466 REX_RX = 0x46,
467 REX_RXB = 0x47,
468
469 REX_W = 0x48,
470
471 REX_WB = 0x49,
472 REX_WX = 0x4A,
473 REX_WXB = 0x4B,
474 REX_WR = 0x4C,
475 REX_WRB = 0x4D,
476 REX_WRX = 0x4E,
477 REX_WRXB = 0x4F
478 };
479
480 enum WhichOperand {
481 // input to locate_operand, and format code for relocations
482 imm_operand = 0, // embedded 32-bit|64-bit immediate operand
483 disp32_operand = 1, // embedded 32-bit displacement or address
484 call32_operand = 2, // embedded 32-bit self-relative displacement
485 #ifndef _LP64
486 _WhichOperand_limit = 3
487 #else
488 narrow_oop_operand = 3, // embedded 32-bit immediate narrow oop
489 _WhichOperand_limit = 4
490 #endif
491 };
492
493
494
495 // NOTE: The general philopsophy of the declarations here is that 64bit versions
496 // of instructions are freely declared without the need for wrapping them an ifdef.
497 // (Some dangerous instructions are ifdef's out of inappropriate jvm's.)
498 // In the .cpp file the implementations are wrapped so that they are dropped out
499 // of the resulting jvm. This is done mostly to keep the footprint of KERNEL
500 // to the size it was prior to merging up the 32bit and 64bit assemblers.
501 //
502 // This does mean you'll get a linker/runtime error if you use a 64bit only instruction
503 // in a 32bit vm. This is somewhat unfortunate but keeps the ifdef noise down.
504
505 private:
506
507
508 // 64bit prefixes
509 int prefix_and_encode(int reg_enc, bool byteinst = false);
510 int prefixq_and_encode(int reg_enc);
511
512 int prefix_and_encode(int dst_enc, int src_enc, bool byteinst = false);
513 int prefixq_and_encode(int dst_enc, int src_enc);
514
515 void prefix(Register reg);
516 void prefix(Address adr);
517 void prefixq(Address adr);
518
519 void prefix(Address adr, Register reg, bool byteinst = false);
520 void prefixq(Address adr, Register reg);
521
522 void prefix(Address adr, XMMRegister reg);
523
524 void prefetch_prefix(Address src);
525
526 // Helper functions for groups of instructions
527 void emit_arith_b(int op1, int op2, Register dst, int imm8);
528
529 void emit_arith(int op1, int op2, Register dst, int32_t imm32);
530 // only 32bit??
531 void emit_arith(int op1, int op2, Register dst, jobject obj);
532 void emit_arith(int op1, int op2, Register dst, Register src);
533
534 void emit_operand(Register reg,
535 Register base, Register index, Address::ScaleFactor scale,
536 int disp,
537 RelocationHolder const& rspec,
538 int rip_relative_correction = 0);
539
540 void emit_operand(Register reg, Address adr, int rip_relative_correction = 0);
541
542 // operands that only take the original 32bit registers
543 void emit_operand32(Register reg, Address adr);
544
545 void emit_operand(XMMRegister reg,
546 Register base, Register index, Address::ScaleFactor scale,
547 int disp,
548 RelocationHolder const& rspec);
549
550 void emit_operand(XMMRegister reg, Address adr);
551
552 void emit_operand(MMXRegister reg, Address adr);
553
554 // workaround gcc (3.2.1-7) bug
555 void emit_operand(Address adr, MMXRegister reg);
556
557
558 // Immediate-to-memory forms
559 void emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32);
560
561 void emit_farith(int b1, int b2, int i);
562
563
564 protected:
565 #ifdef ASSERT
566 void check_relocation(RelocationHolder const& rspec, int format);
567 #endif
568
569 inline void emit_long64(jlong x);
570
571 void emit_data(jint data, relocInfo::relocType rtype, int format);
572 void emit_data(jint data, RelocationHolder const& rspec, int format);
573 void emit_data64(jlong data, relocInfo::relocType rtype, int format = 0);
574 void emit_data64(jlong data, RelocationHolder const& rspec, int format = 0);
575
576
577 bool reachable(AddressLiteral adr) NOT_LP64({ return true;});
578
579 // These are all easily abused and hence protected
580
581 // 32BIT ONLY SECTION
582 #ifndef _LP64
583 // Make these disappear in 64bit mode since they would never be correct
584 void cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
585 void cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
586
587 void mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
588 void mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
589
590 void push_literal32(int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
591 #else
592 // 64BIT ONLY SECTION
593 void mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec); // 64BIT ONLY
594
595 void cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec);
596 void cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec);
597
598 void mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec);
599 void mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec);
600 #endif // _LP64
601
602 // These are unique in that we are ensured by the caller that the 32bit
603 // relative in these instructions will always be able to reach the potentially
604 // 64bit address described by entry. Since they can take a 64bit address they
605 // don't have the 32 suffix like the other instructions in this class.
606
607 void call_literal(address entry, RelocationHolder const& rspec);
608 void jmp_literal(address entry, RelocationHolder const& rspec);
609
610 // Avoid using directly section
611 // Instructions in this section are actually usable by anyone without danger
612 // of failure but have performance issues that are addressed my enhanced
613 // instructions which will do the proper thing base on the particular cpu.
614 // We protect them because we don't trust you...
615
616 // Don't use next inc() and dec() methods directly. INC & DEC instructions
617 // could cause a partial flag stall since they don't set CF flag.
618 // Use MacroAssembler::decrement() & MacroAssembler::increment() methods
619 // which call inc() & dec() or add() & sub() in accordance with
620 // the product flag UseIncDec value.
621
622 void decl(Register dst);
623 void decl(Address dst);
624 void decq(Register dst);
625 void decq(Address dst);
626
627 void incl(Register dst);
628 void incl(Address dst);
629 void incq(Register dst);
630 void incq(Address dst);
631
632 // New cpus require use of movsd and movss to avoid partial register stall
633 // when loading from memory. But for old Opteron use movlpd instead of movsd.
634 // The selection is done in MacroAssembler::movdbl() and movflt().
635
636 // Move Scalar Single-Precision Floating-Point Values
637 void movss(XMMRegister dst, Address src);
638 void movss(XMMRegister dst, XMMRegister src);
639 void movss(Address dst, XMMRegister src);
640
641 // Move Scalar Double-Precision Floating-Point Values
642 void movsd(XMMRegister dst, Address src);
643 void movsd(XMMRegister dst, XMMRegister src);
644 void movsd(Address dst, XMMRegister src);
645 void movlpd(XMMRegister dst, Address src);
646
647 // New cpus require use of movaps and movapd to avoid partial register stall
648 // when moving between registers.
649 void movaps(XMMRegister dst, XMMRegister src);
650 void movapd(XMMRegister dst, XMMRegister src);
651
652 // End avoid using directly
653
654
655 // Instruction prefixes
656 void prefix(Prefix p);
657
658 public:
659
660 // Creation
661 Assembler(CodeBuffer* code) : AbstractAssembler(code) {}
662
663 // Decoding
664 static address locate_operand(address inst, WhichOperand which);
665 static address locate_next_instruction(address inst);
666
667 // Utilities
668
669 #ifdef _LP64
670 static bool is_simm(int64_t x, int nbits) { return -( CONST64(1) << (nbits-1) ) <= x && x < ( CONST64(1) << (nbits-1) ); }
671 static bool is_simm32(int64_t x) { return x == (int64_t)(int32_t)x; }
672 #else
673 static bool is_simm(int32_t x, int nbits) { return -( 1 << (nbits-1) ) <= x && x < ( 1 << (nbits-1) ); }
674 static bool is_simm32(int32_t x) { return true; }
675 #endif // LP64
676
677 // Generic instructions
678 // Does 32bit or 64bit as needed for the platform. In some sense these
679 // belong in macro assembler but there is no need for both varieties to exist
680
681 void lea(Register dst, Address src);
682
683 void mov(Register dst, Register src);
684
685 void pusha();
686 void popa();
687
688 void pushf();
689 void popf();
690
691 void push(int32_t imm32);
692
693 void push(Register src);
694
695 void pop(Register dst);
696
697 // These are dummies to prevent surprise implicit conversions to Register
698 void push(void* v);
699 void pop(void* v);
700
701
702 // These do register sized moves/scans
703 void rep_mov();
704 void rep_set();
705 void repne_scan();
706 #ifdef _LP64
707 void repne_scanl();
708 #endif
709
710 // Vanilla instructions in lexical order
711
712 void adcl(Register dst, int32_t imm32);
713 void adcl(Register dst, Address src);
714 void adcl(Register dst, Register src);
715
716 void adcq(Register dst, int32_t imm32);
717 void adcq(Register dst, Address src);
718 void adcq(Register dst, Register src);
719
720
721 void addl(Address dst, int32_t imm32);
722 void addl(Address dst, Register src);
723 void addl(Register dst, int32_t imm32);
724 void addl(Register dst, Address src);
725 void addl(Register dst, Register src);
726
727 void addq(Address dst, int32_t imm32);
728 void addq(Address dst, Register src);
729 void addq(Register dst, int32_t imm32);
730 void addq(Register dst, Address src);
731 void addq(Register dst, Register src);
732
733
734 void addr_nop_4();
735 void addr_nop_5();
736 void addr_nop_7();
737 void addr_nop_8();
738
739 // Add Scalar Double-Precision Floating-Point Values
740 void addsd(XMMRegister dst, Address src);
741 void addsd(XMMRegister dst, XMMRegister src);
742
743 // Add Scalar Single-Precision Floating-Point Values
744 void addss(XMMRegister dst, Address src);
745 void addss(XMMRegister dst, XMMRegister src);
746
747 void andl(Register dst, int32_t imm32);
748 void andl(Register dst, Address src);
749 void andl(Register dst, Register src);
750
751 void andq(Register dst, int32_t imm32);
752 void andq(Register dst, Address src);
753 void andq(Register dst, Register src);
754
755
756 // Bitwise Logical AND of Packed Double-Precision Floating-Point Values
757 void andpd(XMMRegister dst, Address src);
758 void andpd(XMMRegister dst, XMMRegister src);
759
760 void bswapl(Register reg);
761
762 void bswapq(Register reg);
763
764 void call(Label& L, relocInfo::relocType rtype);
765 void call(Register reg); // push pc; pc <- reg
766 void call(Address adr); // push pc; pc <- adr
767
768 void cdql();
769
770 void cdqq();
771
772 void cld() { emit_byte(0xfc); }
773
774 void clflush(Address adr);
775
776 void cmovl(Condition cc, Register dst, Register src);
777 void cmovl(Condition cc, Register dst, Address src);
778
779 void cmovq(Condition cc, Register dst, Register src);
780 void cmovq(Condition cc, Register dst, Address src);
781
782
783 void cmpb(Address dst, int imm8);
784
785 void cmpl(Address dst, int32_t imm32);
786
787 void cmpl(Register dst, int32_t imm32);
788 void cmpl(Register dst, Register src);
789 void cmpl(Register dst, Address src);
790
791 void cmpq(Address dst, int32_t imm32);
792 void cmpq(Address dst, Register src);
793
794 void cmpq(Register dst, int32_t imm32);
795 void cmpq(Register dst, Register src);
796 void cmpq(Register dst, Address src);
797
798 // these are dummies used to catch attempting to convert NULL to Register
799 void cmpl(Register dst, void* junk); // dummy
800 void cmpq(Register dst, void* junk); // dummy
801
802 void cmpw(Address dst, int imm16);
803
804 void cmpxchg8 (Address adr);
805
806 void cmpxchgl(Register reg, Address adr);
807
808 void cmpxchgq(Register reg, Address adr);
809
810 // Ordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS
811 void comisd(XMMRegister dst, Address src);
812
813 // Ordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS
814 void comiss(XMMRegister dst, Address src);
815
816 // Identify processor type and features
817 void cpuid() {
818 emit_byte(0x0F);
819 emit_byte(0xA2);
820 }
821
822 // Convert Scalar Double-Precision Floating-Point Value to Scalar Single-Precision Floating-Point Value
823 void cvtsd2ss(XMMRegister dst, XMMRegister src);
824
825 // Convert Doubleword Integer to Scalar Double-Precision Floating-Point Value
826 void cvtsi2sdl(XMMRegister dst, Register src);
827 void cvtsi2sdq(XMMRegister dst, Register src);
828
829 // Convert Doubleword Integer to Scalar Single-Precision Floating-Point Value
830 void cvtsi2ssl(XMMRegister dst, Register src);
831 void cvtsi2ssq(XMMRegister dst, Register src);
832
833 // Convert Packed Signed Doubleword Integers to Packed Double-Precision Floating-Point Value
834 void cvtdq2pd(XMMRegister dst, XMMRegister src);
835
836 // Convert Packed Signed Doubleword Integers to Packed Single-Precision Floating-Point Value
837 void cvtdq2ps(XMMRegister dst, XMMRegister src);
838
839 // Convert Scalar Single-Precision Floating-Point Value to Scalar Double-Precision Floating-Point Value
840 void cvtss2sd(XMMRegister dst, XMMRegister src);
841
842 // Convert with Truncation Scalar Double-Precision Floating-Point Value to Doubleword Integer
843 void cvttsd2sil(Register dst, Address src);
844 void cvttsd2sil(Register dst, XMMRegister src);
845 void cvttsd2siq(Register dst, XMMRegister src);
846
847 // Convert with Truncation Scalar Single-Precision Floating-Point Value to Doubleword Integer
848 void cvttss2sil(Register dst, XMMRegister src);
849 void cvttss2siq(Register dst, XMMRegister src);
850
851 // Divide Scalar Double-Precision Floating-Point Values
852 void divsd(XMMRegister dst, Address src);
853 void divsd(XMMRegister dst, XMMRegister src);
854
855 // Divide Scalar Single-Precision Floating-Point Values
856 void divss(XMMRegister dst, Address src);
857 void divss(XMMRegister dst, XMMRegister src);
858
859 void emms();
860
861 void fabs();
862
863 void fadd(int i);
864
865 void fadd_d(Address src);
866 void fadd_s(Address src);
867
868 // "Alternate" versions of x87 instructions place result down in FPU
869 // stack instead of on TOS
870
871 void fadda(int i); // "alternate" fadd
872 void faddp(int i = 1);
873
874 void fchs();
875
876 void fcom(int i);
877
878 void fcomp(int i = 1);
879 void fcomp_d(Address src);
880 void fcomp_s(Address src);
881
882 void fcompp();
883
884 void fcos();
885
886 void fdecstp();
887
888 void fdiv(int i);
889 void fdiv_d(Address src);
890 void fdivr_s(Address src);
891 void fdiva(int i); // "alternate" fdiv
892 void fdivp(int i = 1);
893
894 void fdivr(int i);
895 void fdivr_d(Address src);
896 void fdiv_s(Address src);
897
898 void fdivra(int i); // "alternate" reversed fdiv
899
900 void fdivrp(int i = 1);
901
902 void ffree(int i = 0);
903
904 void fild_d(Address adr);
905 void fild_s(Address adr);
906
907 void fincstp();
908
909 void finit();
910
911 void fist_s (Address adr);
912 void fistp_d(Address adr);
913 void fistp_s(Address adr);
914
915 void fld1();
916
917 void fld_d(Address adr);
918 void fld_s(Address adr);
919 void fld_s(int index);
920 void fld_x(Address adr); // extended-precision (80-bit) format
921
922 void fldcw(Address src);
923
924 void fldenv(Address src);
925
926 void fldlg2();
927
928 void fldln2();
929
930 void fldz();
931
932 void flog();
933 void flog10();
934
935 void fmul(int i);
936
937 void fmul_d(Address src);
938 void fmul_s(Address src);
939
940 void fmula(int i); // "alternate" fmul
941
942 void fmulp(int i = 1);
943
944 void fnsave(Address dst);
945
946 void fnstcw(Address src);
947
948 void fnstsw_ax();
949
950 void fprem();
951 void fprem1();
952
953 void frstor(Address src);
954
955 void fsin();
956
957 void fsqrt();
958
959 void fst_d(Address adr);
960 void fst_s(Address adr);
961
962 void fstp_d(Address adr);
963 void fstp_d(int index);
964 void fstp_s(Address adr);
965 void fstp_x(Address adr); // extended-precision (80-bit) format
966
967 void fsub(int i);
968 void fsub_d(Address src);
969 void fsub_s(Address src);
970
971 void fsuba(int i); // "alternate" fsub
972
973 void fsubp(int i = 1);
974
975 void fsubr(int i);
976 void fsubr_d(Address src);
977 void fsubr_s(Address src);
978
979 void fsubra(int i); // "alternate" reversed fsub
980
981 void fsubrp(int i = 1);
982
983 void ftan();
984
985 void ftst();
986
987 void fucomi(int i = 1);
988 void fucomip(int i = 1);
989
990 void fwait();
991
992 void fxch(int i = 1);
993
994 void fxrstor(Address src);
995
996 void fxsave(Address dst);
997
998 void fyl2x();
999
1000 void hlt();
1001
1002 void idivl(Register src);
1003
1004 void idivq(Register src);
1005
1006 void imull(Register dst, Register src);
1007 void imull(Register dst, Register src, int value);
1008
1009 void imulq(Register dst, Register src);
1010 void imulq(Register dst, Register src, int value);
1011
1012
1013 // jcc is the generic conditional branch generator to run-
1014 // time routines, jcc is used for branches to labels. jcc
1015 // takes a branch opcode (cc) and a label (L) and generates
1016 // either a backward branch or a forward branch and links it
1017 // to the label fixup chain. Usage:
1018 //
1019 // Label L; // unbound label
1020 // jcc(cc, L); // forward branch to unbound label
1021 // bind(L); // bind label to the current pc
1022 // jcc(cc, L); // backward branch to bound label
1023 // bind(L); // illegal: a label may be bound only once
1024 //
1025 // Note: The same Label can be used for forward and backward branches
1026 // but it may be bound only once.
1027
1028 void jcc(Condition cc, Label& L,
1029 relocInfo::relocType rtype = relocInfo::none);
1030
1031 // Conditional jump to a 8-bit offset to L.
1032 // WARNING: be very careful using this for forward jumps. If the label is
1033 // not bound within an 8-bit offset of this instruction, a run-time error
1034 // will occur.
1035 void jccb(Condition cc, Label& L);
1036
1037 void jmp(Address entry); // pc <- entry
1038
1039 // Label operations & relative jumps (PPUM Appendix D)
1040 void jmp(Label& L, relocInfo::relocType rtype = relocInfo::none); // unconditional jump to L
1041
1042 void jmp(Register entry); // pc <- entry
1043
1044 // Unconditional 8-bit offset jump to L.
1045 // WARNING: be very careful using this for forward jumps. If the label is
1046 // not bound within an 8-bit offset of this instruction, a run-time error
1047 // will occur.
1048 void jmpb(Label& L);
1049
1050 void ldmxcsr( Address src );
1051
1052 void leal(Register dst, Address src);
1053
1054 void leaq(Register dst, Address src);
1055
1056 void lfence() {
1057 emit_byte(0x0F);
1058 emit_byte(0xAE);
1059 emit_byte(0xE8);
1060 }
1061
1062 void lock();
1063
1064 enum Membar_mask_bits {
1065 StoreStore = 1 << 3,
1066 LoadStore = 1 << 2,
1067 StoreLoad = 1 << 1,
1068 LoadLoad = 1 << 0
1069 };
1070
1071 // Serializes memory and blows flags
1072 void membar(Membar_mask_bits order_constraint) {
1073 if (os::is_MP()) {
1074 // We only have to handle StoreLoad
1075 if (order_constraint & StoreLoad) {
1076 // All usable chips support "locked" instructions which suffice
1077 // as barriers, and are much faster than the alternative of
1078 // using cpuid instruction. We use here a locked add [esp],0.
1079 // This is conveniently otherwise a no-op except for blowing
1080 // flags.
1081 // Any change to this code may need to revisit other places in
1082 // the code where this idiom is used, in particular the
1083 // orderAccess code.
1084 lock();
1085 addl(Address(rsp, 0), 0);// Assert the lock# signal here
1086 }
1087 }
1088 }
1089
1090 void mfence();
1091
1092 // Moves
1093
1094 void mov64(Register dst, int64_t imm64);
1095
1096 void movb(Address dst, Register src);
1097 void movb(Address dst, int imm8);
1098 void movb(Register dst, Address src);
1099
1100 void movdl(XMMRegister dst, Register src);
1101 void movdl(Register dst, XMMRegister src);
1102
1103 // Move Double Quadword
1104 void movdq(XMMRegister dst, Register src);
1105 void movdq(Register dst, XMMRegister src);
1106
1107 // Move Aligned Double Quadword
1108 void movdqa(Address dst, XMMRegister src);
1109 void movdqa(XMMRegister dst, Address src);
1110 void movdqa(XMMRegister dst, XMMRegister src);
1111
1112 // Move Unaligned Double Quadword
1113 void movdqu(Address dst, XMMRegister src);
1114 void movdqu(XMMRegister dst, Address src);
1115 void movdqu(XMMRegister dst, XMMRegister src);
1116
1117 void movl(Register dst, int32_t imm32);
1118 void movl(Address dst, int32_t imm32);
1119 void movl(Register dst, Register src);
1120 void movl(Register dst, Address src);
1121 void movl(Address dst, Register src);
1122
1123 // These dummies prevent using movl from converting a zero (like NULL) into Register
1124 // by giving the compiler two choices it can't resolve
1125
1126 void movl(Address dst, void* junk);
1127 void movl(Register dst, void* junk);
1128
1129 #ifdef _LP64
1130 void movq(Register dst, Register src);
1131 void movq(Register dst, Address src);
1132 void movq(Address dst, Register src);
1133 #endif
1134
1135 void movq(Address dst, MMXRegister src );
1136 void movq(MMXRegister dst, Address src );
1137
1138 #ifdef _LP64
1139 // These dummies prevent using movq from converting a zero (like NULL) into Register
1140 // by giving the compiler two choices it can't resolve
1141
1142 void movq(Address dst, void* dummy);
1143 void movq(Register dst, void* dummy);
1144 #endif
1145
1146 // Move Quadword
1147 void movq(Address dst, XMMRegister src);
1148 void movq(XMMRegister dst, Address src);
1149
1150 void movsbl(Register dst, Address src);
1151 void movsbl(Register dst, Register src);
1152
1153 #ifdef _LP64
1154 void movsbq(Register dst, Address src);
1155 void movsbq(Register dst, Register src);
1156
1157 // Move signed 32bit immediate to 64bit extending sign
1158 void movslq(Address dst, int32_t imm64);
1159 void movslq(Register dst, int32_t imm64);
1160
1161 void movslq(Register dst, Address src);
1162 void movslq(Register dst, Register src);
1163 void movslq(Register dst, void* src); // Dummy declaration to cause NULL to be ambiguous
1164 #endif
1165
1166 void movswl(Register dst, Address src);
1167 void movswl(Register dst, Register src);
1168
1169 #ifdef _LP64
1170 void movswq(Register dst, Address src);
1171 void movswq(Register dst, Register src);
1172 #endif
1173
1174 void movw(Address dst, int imm16);
1175 void movw(Register dst, Address src);
1176 void movw(Address dst, Register src);
1177
1178 void movzbl(Register dst, Address src);
1179 void movzbl(Register dst, Register src);
1180
1181 #ifdef _LP64
1182 void movzbq(Register dst, Address src);
1183 void movzbq(Register dst, Register src);
1184 #endif
1185
1186 void movzwl(Register dst, Address src);
1187 void movzwl(Register dst, Register src);
1188
1189 #ifdef _LP64
1190 void movzwq(Register dst, Address src);
1191 void movzwq(Register dst, Register src);
1192 #endif
1193
1194 void mull(Address src);
1195 void mull(Register src);
1196
1197 // Multiply Scalar Double-Precision Floating-Point Values
1198 void mulsd(XMMRegister dst, Address src);
1199 void mulsd(XMMRegister dst, XMMRegister src);
1200
1201 // Multiply Scalar Single-Precision Floating-Point Values
1202 void mulss(XMMRegister dst, Address src);
1203 void mulss(XMMRegister dst, XMMRegister src);
1204
1205 void negl(Register dst);
1206
1207 #ifdef _LP64
1208 void negq(Register dst);
1209 #endif
1210
1211 void nop(int i = 1);
1212
1213 void notl(Register dst);
1214
1215 #ifdef _LP64
1216 void notq(Register dst);
1217 #endif
1218
1219 void orl(Address dst, int32_t imm32);
1220 void orl(Register dst, int32_t imm32);
1221 void orl(Register dst, Address src);
1222 void orl(Register dst, Register src);
1223
1224 void orq(Address dst, int32_t imm32);
1225 void orq(Register dst, int32_t imm32);
1226 void orq(Register dst, Address src);
1227 void orq(Register dst, Register src);
1228
1229 // SSE4.2 string instructions
1230 void pcmpestri(XMMRegister xmm1, XMMRegister xmm2, int imm8);
1231 void pcmpestri(XMMRegister xmm1, Address src, int imm8);
1232
1233 void popl(Address dst);
1234
1235 #ifdef _LP64
1236 void popq(Address dst);
1237 #endif
1238
1239 void popcntl(Register dst, Address src);
1240 void popcntl(Register dst, Register src);
1241
1242 #ifdef _LP64
1243 void popcntq(Register dst, Address src);
1244 void popcntq(Register dst, Register src);
1245 #endif
1246
1247 // Prefetches (SSE, SSE2, 3DNOW only)
1248
1249 void prefetchnta(Address src);
1250 void prefetchr(Address src);
1251 void prefetcht0(Address src);
1252 void prefetcht1(Address src);
1253 void prefetcht2(Address src);
1254 void prefetchw(Address src);
1255
1256 // Shuffle Packed Doublewords
1257 void pshufd(XMMRegister dst, XMMRegister src, int mode);
1258 void pshufd(XMMRegister dst, Address src, int mode);
1259
1260 // Shuffle Packed Low Words
1261 void pshuflw(XMMRegister dst, XMMRegister src, int mode);
1262 void pshuflw(XMMRegister dst, Address src, int mode);
1263
1264 // Shift Right Logical Quadword Immediate
1265 void psrlq(XMMRegister dst, int shift);
1266
1267 // Logical Compare Double Quadword
1268 void ptest(XMMRegister dst, XMMRegister src);
1269 void ptest(XMMRegister dst, Address src);
1270
1271 // Interleave Low Bytes
1272 void punpcklbw(XMMRegister dst, XMMRegister src);
1273
1274 void pushl(Address src);
1275
1276 void pushq(Address src);
1277
1278 // Xor Packed Byte Integer Values
1279 void pxor(XMMRegister dst, Address src);
1280 void pxor(XMMRegister dst, XMMRegister src);
1281
1282 void rcll(Register dst, int imm8);
1283
1284 void rclq(Register dst, int imm8);
1285
1286 void ret(int imm16);
1287
1288 void sahf();
1289
1290 void sarl(Register dst, int imm8);
1291 void sarl(Register dst);
1292
1293 void sarq(Register dst, int imm8);
1294 void sarq(Register dst);
1295
1296 void sbbl(Address dst, int32_t imm32);
1297 void sbbl(Register dst, int32_t imm32);
1298 void sbbl(Register dst, Address src);
1299 void sbbl(Register dst, Register src);
1300
1301 void sbbq(Address dst, int32_t imm32);
1302 void sbbq(Register dst, int32_t imm32);
1303 void sbbq(Register dst, Address src);
1304 void sbbq(Register dst, Register src);
1305
1306 void setb(Condition cc, Register dst);
1307
1308 void shldl(Register dst, Register src);
1309
1310 void shll(Register dst, int imm8);
1311 void shll(Register dst);
1312
1313 void shlq(Register dst, int imm8);
1314 void shlq(Register dst);
1315
1316 void shrdl(Register dst, Register src);
1317
1318 void shrl(Register dst, int imm8);
1319 void shrl(Register dst);
1320
1321 void shrq(Register dst, int imm8);
1322 void shrq(Register dst);
1323
1324 void smovl(); // QQQ generic?
1325
1326 // Compute Square Root of Scalar Double-Precision Floating-Point Value
1327 void sqrtsd(XMMRegister dst, Address src);
1328 void sqrtsd(XMMRegister dst, XMMRegister src);
1329
1330 void std() { emit_byte(0xfd); }
1331
1332 void stmxcsr( Address dst );
1333
1334 void subl(Address dst, int32_t imm32);
1335 void subl(Address dst, Register src);
1336 void subl(Register dst, int32_t imm32);
1337 void subl(Register dst, Address src);
1338 void subl(Register dst, Register src);
1339
1340 void subq(Address dst, int32_t imm32);
1341 void subq(Address dst, Register src);
1342 void subq(Register dst, int32_t imm32);
1343 void subq(Register dst, Address src);
1344 void subq(Register dst, Register src);
1345
1346
1347 // Subtract Scalar Double-Precision Floating-Point Values
1348 void subsd(XMMRegister dst, Address src);
1349 void subsd(XMMRegister dst, XMMRegister src);
1350
1351 // Subtract Scalar Single-Precision Floating-Point Values
1352 void subss(XMMRegister dst, Address src);
1353 void subss(XMMRegister dst, XMMRegister src);
1354
1355 void testb(Register dst, int imm8);
1356
1357 void testl(Register dst, int32_t imm32);
1358 void testl(Register dst, Register src);
1359 void testl(Register dst, Address src);
1360
1361 void testq(Register dst, int32_t imm32);
1362 void testq(Register dst, Register src);
1363
1364
1365 // Unordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS
1366 void ucomisd(XMMRegister dst, Address src);
1367 void ucomisd(XMMRegister dst, XMMRegister src);
1368
1369 // Unordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS
1370 void ucomiss(XMMRegister dst, Address src);
1371 void ucomiss(XMMRegister dst, XMMRegister src);
1372
1373 void xaddl(Address dst, Register src);
1374
1375 void xaddq(Address dst, Register src);
1376
1377 void xchgl(Register reg, Address adr);
1378 void xchgl(Register dst, Register src);
1379
1380 void xchgq(Register reg, Address adr);
1381 void xchgq(Register dst, Register src);
1382
1383 void xorl(Register dst, int32_t imm32);
1384 void xorl(Register dst, Address src);
1385 void xorl(Register dst, Register src);
1386
1387 void xorq(Register dst, Address src);
1388 void xorq(Register dst, Register src);
1389
1390 // Bitwise Logical XOR of Packed Double-Precision Floating-Point Values
1391 void xorpd(XMMRegister dst, Address src);
1392 void xorpd(XMMRegister dst, XMMRegister src);
1393
1394 // Bitwise Logical XOR of Packed Single-Precision Floating-Point Values
1395 void xorps(XMMRegister dst, Address src);
1396 void xorps(XMMRegister dst, XMMRegister src);
1397
1398 void set_byte_if_not_zero(Register dst); // sets reg to 1 if not zero, otherwise 0
1399 };
1400
1401
1402 // MacroAssembler extends Assembler by frequently used macros.
1403 //
1404 // Instructions for which a 'better' code sequence exists depending
1405 // on arguments should also go in here.
1406
1407 class MacroAssembler: public Assembler {
1408 friend class LIR_Assembler;
1409 friend class Runtime1; // as_Address()
1410 protected:
1411
1412 Address as_Address(AddressLiteral adr);
1413 Address as_Address(ArrayAddress adr);
1414
1415 // Support for VM calls
1416 //
1417 // This is the base routine called by the different versions of call_VM_leaf. The interpreter
1418 // may customize this version by overriding it for its purposes (e.g., to save/restore
1419 // additional registers when doing a VM call).
1420 #ifdef CC_INTERP
1421 // c++ interpreter never wants to use interp_masm version of call_VM
1422 #define VIRTUAL
1423 #else
1424 #define VIRTUAL virtual
1425 #endif
1426
1427 VIRTUAL void call_VM_leaf_base(
1428 address entry_point, // the entry point
1429 int number_of_arguments // the number of arguments to pop after the call
1430 );
1431
1432 // This is the base routine called by the different versions of call_VM. The interpreter
1433 // may customize this version by overriding it for its purposes (e.g., to save/restore
1434 // additional registers when doing a VM call).
1435 //
1436 // If no java_thread register is specified (noreg) than rdi will be used instead. call_VM_base
1437 // returns the register which contains the thread upon return. If a thread register has been
1438 // specified, the return value will correspond to that register. If no last_java_sp is specified
1439 // (noreg) than rsp will be used instead.
1440 VIRTUAL void call_VM_base( // returns the register containing the thread upon return
1441 Register oop_result, // where an oop-result ends up if any; use noreg otherwise
1442 Register java_thread, // the thread if computed before ; use noreg otherwise
1443 Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise
1444 address entry_point, // the entry point
1445 int number_of_arguments, // the number of arguments (w/o thread) to pop after the call
1446 bool check_exceptions // whether to check for pending exceptions after return
1447 );
1448
1449 // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
1450 // The implementation is only non-empty for the InterpreterMacroAssembler,
1451 // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
1452 virtual void check_and_handle_popframe(Register java_thread);
1453 virtual void check_and_handle_earlyret(Register java_thread);
1454
1455 void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true);
1456
1457 // helpers for FPU flag access
1458 // tmp is a temporary register, if none is available use noreg
1459 void save_rax (Register tmp);
1460 void restore_rax(Register tmp);
1461
1462 public:
1463 MacroAssembler(CodeBuffer* code) : Assembler(code) {}
1464
1465 // Support for NULL-checks
1466 //
1467 // Generates code that causes a NULL OS exception if the content of reg is NULL.
1468 // If the accessed location is M[reg + offset] and the offset is known, provide the
1469 // offset. No explicit code generation is needed if the offset is within a certain
1470 // range (0 <= offset <= page_size).
1471
1472 void null_check(Register reg, int offset = -1);
1473 static bool needs_explicit_null_check(intptr_t offset);
1474
1475 // Required platform-specific helpers for Label::patch_instructions.
1476 // They _shadow_ the declarations in AbstractAssembler, which are undefined.
1477 void pd_patch_instruction(address branch, address target);
1478 #ifndef PRODUCT
1479 static void pd_print_patched_instruction(address branch);
1480 #endif
1481
1482 // The following 4 methods return the offset of the appropriate move instruction
1483
1484 // Support for fast byte/short loading with zero extension (depending on particular CPU)
1485 int load_unsigned_byte(Register dst, Address src);
1486 int load_unsigned_short(Register dst, Address src);
1487
1488 // Support for fast byte/short loading with sign extension (depending on particular CPU)
1489 int load_signed_byte(Register dst, Address src);
1490 int load_signed_short(Register dst, Address src);
1491
1492 // Support for sign-extension (hi:lo = extend_sign(lo))
1493 void extend_sign(Register hi, Register lo);
1494
1495 // Loading values by size and signed-ness
1496 void load_sized_value(Register dst, Address src, int size_in_bytes, bool is_signed);
1497
1498 // Support for inc/dec with optimal instruction selection depending on value
1499
1500 void increment(Register reg, int value = 1) { LP64_ONLY(incrementq(reg, value)) NOT_LP64(incrementl(reg, value)) ; }
1501 void decrement(Register reg, int value = 1) { LP64_ONLY(decrementq(reg, value)) NOT_LP64(decrementl(reg, value)) ; }
1502
1503 void decrementl(Address dst, int value = 1);
1504 void decrementl(Register reg, int value = 1);
1505
1506 void decrementq(Register reg, int value = 1);
1507 void decrementq(Address dst, int value = 1);
1508
1509 void incrementl(Address dst, int value = 1);
1510 void incrementl(Register reg, int value = 1);
1511
1512 void incrementq(Register reg, int value = 1);
1513 void incrementq(Address dst, int value = 1);
1514
1515
1516 // Support optimal SSE move instructions.
1517 void movflt(XMMRegister dst, XMMRegister src) {
1518 if (UseXmmRegToRegMoveAll) { movaps(dst, src); return; }
1519 else { movss (dst, src); return; }
1520 }
1521 void movflt(XMMRegister dst, Address src) { movss(dst, src); }
1522 void movflt(XMMRegister dst, AddressLiteral src);
1523 void movflt(Address dst, XMMRegister src) { movss(dst, src); }
1524
1525 void movdbl(XMMRegister dst, XMMRegister src) {
1526 if (UseXmmRegToRegMoveAll) { movapd(dst, src); return; }
1527 else { movsd (dst, src); return; }
1528 }
1529
1530 void movdbl(XMMRegister dst, AddressLiteral src);
1531
1532 void movdbl(XMMRegister dst, Address src) {
1533 if (UseXmmLoadAndClearUpper) { movsd (dst, src); return; }
1534 else { movlpd(dst, src); return; }
1535 }
1536 void movdbl(Address dst, XMMRegister src) { movsd(dst, src); }
1537
1538 void incrementl(AddressLiteral dst);
1539 void incrementl(ArrayAddress dst);
1540
1541 // Alignment
1542 void align(int modulus);
1543
1544 // Misc
1545 void fat_nop(); // 5 byte nop
1546
1547 // Stack frame creation/removal
1548 void enter();
1549 void leave();
1550
1551 // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information)
1552 // The pointer will be loaded into the thread register.
1553 void get_thread(Register thread);
1554
1555
1556 // Support for VM calls
1557 //
1558 // It is imperative that all calls into the VM are handled via the call_VM macros.
1559 // They make sure that the stack linkage is setup correctly. call_VM's correspond
1560 // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
1561
1562
1563 void call_VM(Register oop_result,
1564 address entry_point,
1565 bool check_exceptions = true);
1566 void call_VM(Register oop_result,
1567 address entry_point,
1568 Register arg_1,
1569 bool check_exceptions = true);
1570 void call_VM(Register oop_result,
1571 address entry_point,
1572 Register arg_1, Register arg_2,
1573 bool check_exceptions = true);
1574 void call_VM(Register oop_result,
1575 address entry_point,
1576 Register arg_1, Register arg_2, Register arg_3,
1577 bool check_exceptions = true);
1578
1579 // Overloadings with last_Java_sp
1580 void call_VM(Register oop_result,
1581 Register last_java_sp,
1582 address entry_point,
1583 int number_of_arguments = 0,
1584 bool check_exceptions = true);
1585 void call_VM(Register oop_result,
1586 Register last_java_sp,
1587 address entry_point,
1588 Register arg_1, bool
1589 check_exceptions = true);
1590 void call_VM(Register oop_result,
1591 Register last_java_sp,
1592 address entry_point,
1593 Register arg_1, Register arg_2,
1594 bool check_exceptions = true);
1595 void call_VM(Register oop_result,
1596 Register last_java_sp,
1597 address entry_point,
1598 Register arg_1, Register arg_2, Register arg_3,
1599 bool check_exceptions = true);
1600
1601 void call_VM_leaf(address entry_point,
1602 int number_of_arguments = 0);
1603 void call_VM_leaf(address entry_point,
1604 Register arg_1);
1605 void call_VM_leaf(address entry_point,
1606 Register arg_1, Register arg_2);
1607 void call_VM_leaf(address entry_point,
1608 Register arg_1, Register arg_2, Register arg_3);
1609
1610 // last Java Frame (fills frame anchor)
1611 void set_last_Java_frame(Register thread,
1612 Register last_java_sp,
1613 Register last_java_fp,
1614 address last_java_pc);
1615
1616 // thread in the default location (r15_thread on 64bit)
1617 void set_last_Java_frame(Register last_java_sp,
1618 Register last_java_fp,
1619 address last_java_pc);
1620
1621 void reset_last_Java_frame(Register thread, bool clear_fp, bool clear_pc);
1622
1623 // thread in the default location (r15_thread on 64bit)
1624 void reset_last_Java_frame(bool clear_fp, bool clear_pc);
1625
1626 // Stores
1627 void store_check(Register obj); // store check for obj - register is destroyed afterwards
1628 void store_check(Register obj, Address dst); // same as above, dst is exact store location (reg. is destroyed)
1629
1630 void g1_write_barrier_pre(Register obj,
1631 #ifndef _LP64
1632 Register thread,
1633 #endif
1634 Register tmp,
1635 Register tmp2,
1636 bool tosca_live);
1637 void g1_write_barrier_post(Register store_addr,
1638 Register new_val,
1639 #ifndef _LP64
1640 Register thread,
1641 #endif
1642 Register tmp,
1643 Register tmp2);
1644
1645
1646 // split store_check(Register obj) to enhance instruction interleaving
1647 void store_check_part_1(Register obj);
1648 void store_check_part_2(Register obj);
1649
1650 // C 'boolean' to Java boolean: x == 0 ? 0 : 1
1651 void c2bool(Register x);
1652
1653 // C++ bool manipulation
1654
1655 void movbool(Register dst, Address src);
1656 void movbool(Address dst, bool boolconst);
1657 void movbool(Address dst, Register src);
1658 void testbool(Register dst);
1659
1660 // oop manipulations
1661 void load_klass(Register dst, Register src);
1662 void store_klass(Register dst, Register src);
1663
1664 void load_prototype_header(Register dst, Register src);
1665
1666 #ifdef _LP64
1667 void store_klass_gap(Register dst, Register src);
1668
1669 void load_heap_oop(Register dst, Address src);
1670 void store_heap_oop(Address dst, Register src);
1671 void encode_heap_oop(Register r);
1672 void decode_heap_oop(Register r);
1673 void encode_heap_oop_not_null(Register r);
1674 void decode_heap_oop_not_null(Register r);
1675 void encode_heap_oop_not_null(Register dst, Register src);
1676 void decode_heap_oop_not_null(Register dst, Register src);
1677
1678 void set_narrow_oop(Register dst, jobject obj);
1679 void set_narrow_oop(Address dst, jobject obj);
1680 void cmp_narrow_oop(Register dst, jobject obj);
1681 void cmp_narrow_oop(Address dst, jobject obj);
1682
1683 // if heap base register is used - reinit it with the correct value
1684 void reinit_heapbase();
1685 #endif // _LP64
1686
1687 // Int division/remainder for Java
1688 // (as idivl, but checks for special case as described in JVM spec.)
1689 // returns idivl instruction offset for implicit exception handling
1690 int corrected_idivl(Register reg);
1691
1692 // Long division/remainder for Java
1693 // (as idivq, but checks for special case as described in JVM spec.)
1694 // returns idivq instruction offset for implicit exception handling
1695 int corrected_idivq(Register reg);
1696
1697 void int3();
1698
1699 // Long operation macros for a 32bit cpu
1700 // Long negation for Java
1701 void lneg(Register hi, Register lo);
1702
1703 // Long multiplication for Java
1704 // (destroys contents of eax, ebx, ecx and edx)
1705 void lmul(int x_rsp_offset, int y_rsp_offset); // rdx:rax = x * y
1706
1707 // Long shifts for Java
1708 // (semantics as described in JVM spec.)
1709 void lshl(Register hi, Register lo); // hi:lo << (rcx & 0x3f)
1710 void lshr(Register hi, Register lo, bool sign_extension = false); // hi:lo >> (rcx & 0x3f)
1711
1712 // Long compare for Java
1713 // (semantics as described in JVM spec.)
1714 void lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo); // x_hi = lcmp(x, y)
1715
1716
1717 // misc
1718
1719 // Sign extension
1720 void sign_extend_short(Register reg);
1721 void sign_extend_byte(Register reg);
1722
1723 // Division by power of 2, rounding towards 0
1724 void division_with_shift(Register reg, int shift_value);
1725
1726 // Compares the top-most stack entries on the FPU stack and sets the eflags as follows:
1727 //
1728 // CF (corresponds to C0) if x < y
1729 // PF (corresponds to C2) if unordered
1730 // ZF (corresponds to C3) if x = y
1731 //
1732 // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
1733 // tmp is a temporary register, if none is available use noreg (only matters for non-P6 code)
1734 void fcmp(Register tmp);
1735 // Variant of the above which allows y to be further down the stack
1736 // and which only pops x and y if specified. If pop_right is
1737 // specified then pop_left must also be specified.
1738 void fcmp(Register tmp, int index, bool pop_left, bool pop_right);
1739
1740 // Floating-point comparison for Java
1741 // Compares the top-most stack entries on the FPU stack and stores the result in dst.
1742 // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
1743 // (semantics as described in JVM spec.)
1744 void fcmp2int(Register dst, bool unordered_is_less);
1745 // Variant of the above which allows y to be further down the stack
1746 // and which only pops x and y if specified. If pop_right is
1747 // specified then pop_left must also be specified.
1748 void fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right);
1749
1750 // Floating-point remainder for Java (ST0 = ST0 fremr ST1, ST1 is empty afterwards)
1751 // tmp is a temporary register, if none is available use noreg
1752 void fremr(Register tmp);
1753
1754
1755 // same as fcmp2int, but using SSE2
1756 void cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
1757 void cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
1758
1759 // Inlined sin/cos generator for Java; must not use CPU instruction
1760 // directly on Intel as it does not have high enough precision
1761 // outside of the range [-pi/4, pi/4]. Extra argument indicate the
1762 // number of FPU stack slots in use; all but the topmost will
1763 // require saving if a slow case is necessary. Assumes argument is
1764 // on FP TOS; result is on FP TOS. No cpu registers are changed by
1765 // this code.
1766 void trigfunc(char trig, int num_fpu_regs_in_use = 1);
1767
1768 // branch to L if FPU flag C2 is set/not set
1769 // tmp is a temporary register, if none is available use noreg
1770 void jC2 (Register tmp, Label& L);
1771 void jnC2(Register tmp, Label& L);
1772
1773 // Pop ST (ffree & fincstp combined)
1774 void fpop();
1775
1776 // pushes double TOS element of FPU stack on CPU stack; pops from FPU stack
1777 void push_fTOS();
1778
1779 // pops double TOS element from CPU stack and pushes on FPU stack
1780 void pop_fTOS();
1781
1782 void empty_FPU_stack();
1783
1784 void push_IU_state();
1785 void pop_IU_state();
1786
1787 void push_FPU_state();
1788 void pop_FPU_state();
1789
1790 void push_CPU_state();
1791 void pop_CPU_state();
1792
1793 // Round up to a power of two
1794 void round_to(Register reg, int modulus);
1795
1796 // Callee saved registers handling
1797 void push_callee_saved_registers();
1798 void pop_callee_saved_registers();
1799
1800 // allocation
1801 void eden_allocate(
1802 Register obj, // result: pointer to object after successful allocation
1803 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
1804 int con_size_in_bytes, // object size in bytes if known at compile time
1805 Register t1, // temp register
1806 Label& slow_case // continuation point if fast allocation fails
1807 );
1808 void tlab_allocate(
1809 Register obj, // result: pointer to object after successful allocation
1810 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
1811 int con_size_in_bytes, // object size in bytes if known at compile time
1812 Register t1, // temp register
1813 Register t2, // temp register
1814 Label& slow_case // continuation point if fast allocation fails
1815 );
1816 void tlab_refill(Label& retry_tlab, Label& try_eden, Label& slow_case);
1817
1818 // interface method calling
1819 void lookup_interface_method(Register recv_klass,
1820 Register intf_klass,
1821 RegisterOrConstant itable_index,
1822 Register method_result,
1823 Register scan_temp,
1824 Label& no_such_interface);
1825
1826 // Test sub_klass against super_klass, with fast and slow paths.
1827
1828 // The fast path produces a tri-state answer: yes / no / maybe-slow.
1829 // One of the three labels can be NULL, meaning take the fall-through.
1830 // If super_check_offset is -1, the value is loaded up from super_klass.
1831 // No registers are killed, except temp_reg.
1832 void check_klass_subtype_fast_path(Register sub_klass,
1833 Register super_klass,
1834 Register temp_reg,
1835 Label* L_success,
1836 Label* L_failure,
1837 Label* L_slow_path,
1838 RegisterOrConstant super_check_offset = RegisterOrConstant(-1));
1839
1840 // The rest of the type check; must be wired to a corresponding fast path.
1841 // It does not repeat the fast path logic, so don't use it standalone.
1842 // The temp_reg and temp2_reg can be noreg, if no temps are available.
1843 // Updates the sub's secondary super cache as necessary.
1844 // If set_cond_codes, condition codes will be Z on success, NZ on failure.
1845 void check_klass_subtype_slow_path(Register sub_klass,
1846 Register super_klass,
1847 Register temp_reg,
1848 Register temp2_reg,
1849 Label* L_success,
1850 Label* L_failure,
1851 bool set_cond_codes = false);
1852
1853 // Simplified, combined version, good for typical uses.
1854 // Falls through on failure.
1855 void check_klass_subtype(Register sub_klass,
1856 Register super_klass,
1857 Register temp_reg,
1858 Label& L_success);
1859
1860 // method handles (JSR 292)
1861 void check_method_handle_type(Register mtype_reg, Register mh_reg,
1862 Register temp_reg,
1863 Label& wrong_method_type);
1864 void load_method_handle_vmslots(Register vmslots_reg, Register mh_reg,
1865 Register temp_reg);
1866 void jump_to_method_handle_entry(Register mh_reg, Register temp_reg);
1867 Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0);
1868
1869
1870 //----
1871 void set_word_if_not_zero(Register reg); // sets reg to 1 if not zero, otherwise 0
1872
1873 // Debugging
1874
1875 // only if +VerifyOops
1876 void verify_oop(Register reg, const char* s = "broken oop");
1877 void verify_oop_addr(Address addr, const char * s = "broken oop addr");
1878
1879 // only if +VerifyFPU
1880 void verify_FPU(int stack_depth, const char* s = "illegal FPU state");
1881
1882 // prints msg, dumps registers and stops execution
1883 void stop(const char* msg);
1884
1885 // prints msg and continues
1886 void warn(const char* msg);
1887
1888 static void debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg);
1889 static void debug64(char* msg, int64_t pc, int64_t regs[]);
1890
1891 void os_breakpoint();
1892
1893 void untested() { stop("untested"); }
1894
1895 void unimplemented(const char* what = "") { char* b = new char[1024]; jio_snprintf(b, sizeof(b), "unimplemented: %s", what); stop(b); }
1896
1897 void should_not_reach_here() { stop("should not reach here"); }
1898
1899 void print_CPU_state();
1900
1901 // Stack overflow checking
1902 void bang_stack_with_offset(int offset) {
1903 // stack grows down, caller passes positive offset
1904 assert(offset > 0, "must bang with negative offset");
1905 movl(Address(rsp, (-offset)), rax);
1906 }
1907
1908 // Writes to stack successive pages until offset reached to check for
1909 // stack overflow + shadow pages. Also, clobbers tmp
1910 void bang_stack_size(Register size, Register tmp);
1911
1912 virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr,
1913 Register tmp,
1914 int offset);
1915
1916 // Support for serializing memory accesses between threads
1917 void serialize_memory(Register thread, Register tmp);
1918
1919 void verify_tlab();
1920
1921 // Biased locking support
1922 // lock_reg and obj_reg must be loaded up with the appropriate values.
1923 // swap_reg must be rax, and is killed.
1924 // tmp_reg is optional. If it is supplied (i.e., != noreg) it will
1925 // be killed; if not supplied, push/pop will be used internally to
1926 // allocate a temporary (inefficient, avoid if possible).
1927 // Optional slow case is for implementations (interpreter and C1) which branch to
1928 // slow case directly. Leaves condition codes set for C2's Fast_Lock node.
1929 // Returns offset of first potentially-faulting instruction for null
1930 // check info (currently consumed only by C1). If
1931 // swap_reg_contains_mark is true then returns -1 as it is assumed
1932 // the calling code has already passed any potential faults.
1933 int biased_locking_enter(Register lock_reg, Register obj_reg,
1934 Register swap_reg, Register tmp_reg,
1935 bool swap_reg_contains_mark,
1936 Label& done, Label* slow_case = NULL,
1937 BiasedLockingCounters* counters = NULL);
1938 void biased_locking_exit (Register obj_reg, Register temp_reg, Label& done);
1939
1940
1941 Condition negate_condition(Condition cond);
1942
1943 // Instructions that use AddressLiteral operands. These instruction can handle 32bit/64bit
1944 // operands. In general the names are modified to avoid hiding the instruction in Assembler
1945 // so that we don't need to implement all the varieties in the Assembler with trivial wrappers
1946 // here in MacroAssembler. The major exception to this rule is call
1947
1948 // Arithmetics
1949
1950
1951 void addptr(Address dst, int32_t src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)) ; }
1952 void addptr(Address dst, Register src);
1953
1954 void addptr(Register dst, Address src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); }
1955 void addptr(Register dst, int32_t src);
1956 void addptr(Register dst, Register src);
1957
1958 void andptr(Register dst, int32_t src);
1959 void andptr(Register src1, Register src2) { LP64_ONLY(andq(src1, src2)) NOT_LP64(andl(src1, src2)) ; }
1960
1961 void cmp8(AddressLiteral src1, int imm);
1962
1963 // renamed to drag out the casting of address to int32_t/intptr_t
1964 void cmp32(Register src1, int32_t imm);
1965
1966 void cmp32(AddressLiteral src1, int32_t imm);
1967 // compare reg - mem, or reg - &mem
1968 void cmp32(Register src1, AddressLiteral src2);
1969
1970 void cmp32(Register src1, Address src2);
1971
1972 #ifndef _LP64
1973 void cmpoop(Address dst, jobject obj);
1974 void cmpoop(Register dst, jobject obj);
1975 #endif // _LP64
1976
1977 // NOTE src2 must be the lval. This is NOT an mem-mem compare
1978 void cmpptr(Address src1, AddressLiteral src2);
1979
1980 void cmpptr(Register src1, AddressLiteral src2);
1981
1982 void cmpptr(Register src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
1983 void cmpptr(Register src1, Address src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
1984 // void cmpptr(Address src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
1985
1986 void cmpptr(Register src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
1987 void cmpptr(Address src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
1988
1989 // cmp64 to avoild hiding cmpq
1990 void cmp64(Register src1, AddressLiteral src);
1991
1992 void cmpxchgptr(Register reg, Address adr);
1993
1994 void locked_cmpxchgptr(Register reg, AddressLiteral adr);
1995
1996
1997 void imulptr(Register dst, Register src) { LP64_ONLY(imulq(dst, src)) NOT_LP64(imull(dst, src)); }
1998
1999
2000 void negptr(Register dst) { LP64_ONLY(negq(dst)) NOT_LP64(negl(dst)); }
2001
2002 void notptr(Register dst) { LP64_ONLY(notq(dst)) NOT_LP64(notl(dst)); }
2003
2004 void shlptr(Register dst, int32_t shift);
2005 void shlptr(Register dst) { LP64_ONLY(shlq(dst)) NOT_LP64(shll(dst)); }
2006
2007 void shrptr(Register dst, int32_t shift);
2008 void shrptr(Register dst) { LP64_ONLY(shrq(dst)) NOT_LP64(shrl(dst)); }
2009
2010 void sarptr(Register dst) { LP64_ONLY(sarq(dst)) NOT_LP64(sarl(dst)); }
2011 void sarptr(Register dst, int32_t src) { LP64_ONLY(sarq(dst, src)) NOT_LP64(sarl(dst, src)); }
2012
2013 void subptr(Address dst, int32_t src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
2014
2015 void subptr(Register dst, Address src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
2016 void subptr(Register dst, int32_t src);
2017 void subptr(Register dst, Register src);
2018
2019
2020 void sbbptr(Address dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
2021 void sbbptr(Register dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
2022
2023 void xchgptr(Register src1, Register src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
2024 void xchgptr(Register src1, Address src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
2025
2026 void xaddptr(Address src1, Register src2) { LP64_ONLY(xaddq(src1, src2)) NOT_LP64(xaddl(src1, src2)) ; }
2027
2028
2029
2030 // Helper functions for statistics gathering.
2031 // Conditionally (atomically, on MPs) increments passed counter address, preserving condition codes.
2032 void cond_inc32(Condition cond, AddressLiteral counter_addr);
2033 // Unconditional atomic increment.
2034 void atomic_incl(AddressLiteral counter_addr);
2035
2036 void lea(Register dst, AddressLiteral adr);
2037 void lea(Address dst, AddressLiteral adr);
2038 void lea(Register dst, Address adr) { Assembler::lea(dst, adr); }
2039
2040 void leal32(Register dst, Address src) { leal(dst, src); }
2041
2042 void test32(Register src1, AddressLiteral src2);
2043
2044 void orptr(Register dst, Address src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
2045 void orptr(Register dst, Register src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
2046 void orptr(Register dst, int32_t src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
2047
2048 void testptr(Register src, int32_t imm32) { LP64_ONLY(testq(src, imm32)) NOT_LP64(testl(src, imm32)); }
2049 void testptr(Register src1, Register src2);
2050
2051 void xorptr(Register dst, Register src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
2052 void xorptr(Register dst, Address src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
2053
2054 // Calls
2055
2056 void call(Label& L, relocInfo::relocType rtype);
2057 void call(Register entry);
2058
2059 // NOTE: this call tranfers to the effective address of entry NOT
2060 // the address contained by entry. This is because this is more natural
2061 // for jumps/calls.
2062 void call(AddressLiteral entry);
2063
2064 // Jumps
2065
2066 // NOTE: these jumps tranfer to the effective address of dst NOT
2067 // the address contained by dst. This is because this is more natural
2068 // for jumps/calls.
2069 void jump(AddressLiteral dst);
2070 void jump_cc(Condition cc, AddressLiteral dst);
2071
2072 // 32bit can do a case table jump in one instruction but we no longer allow the base
2073 // to be installed in the Address class. This jump will tranfers to the address
2074 // contained in the location described by entry (not the address of entry)
2075 void jump(ArrayAddress entry);
2076
2077 // Floating
2078
2079 void andpd(XMMRegister dst, Address src) { Assembler::andpd(dst, src); }
2080 void andpd(XMMRegister dst, AddressLiteral src);
2081
2082 void comiss(XMMRegister dst, Address src) { Assembler::comiss(dst, src); }
2083 void comiss(XMMRegister dst, AddressLiteral src);
2084
2085 void comisd(XMMRegister dst, Address src) { Assembler::comisd(dst, src); }
2086 void comisd(XMMRegister dst, AddressLiteral src);
2087
2088 void fldcw(Address src) { Assembler::fldcw(src); }
2089 void fldcw(AddressLiteral src);
2090
2091 void fld_s(int index) { Assembler::fld_s(index); }
2092 void fld_s(Address src) { Assembler::fld_s(src); }
2093 void fld_s(AddressLiteral src);
2094
2095 void fld_d(Address src) { Assembler::fld_d(src); }
2096 void fld_d(AddressLiteral src);
2097
2098 void fld_x(Address src) { Assembler::fld_x(src); }
2099 void fld_x(AddressLiteral src);
2100
2101 void ldmxcsr(Address src) { Assembler::ldmxcsr(src); }
2102 void ldmxcsr(AddressLiteral src);
2103
2104 private:
2105 // these are private because users should be doing movflt/movdbl
2106
2107 void movss(Address dst, XMMRegister src) { Assembler::movss(dst, src); }
2108 void movss(XMMRegister dst, XMMRegister src) { Assembler::movss(dst, src); }
2109 void movss(XMMRegister dst, Address src) { Assembler::movss(dst, src); }
2110 void movss(XMMRegister dst, AddressLiteral src);
2111
2112 void movlpd(XMMRegister dst, Address src) {Assembler::movlpd(dst, src); }
2113 void movlpd(XMMRegister dst, AddressLiteral src);
2114
2115 public:
2116
2117 void movsd(XMMRegister dst, XMMRegister src) { Assembler::movsd(dst, src); }
2118 void movsd(Address dst, XMMRegister src) { Assembler::movsd(dst, src); }
2119 void movsd(XMMRegister dst, Address src) { Assembler::movsd(dst, src); }
2120 void movsd(XMMRegister dst, AddressLiteral src);
2121
2122 void ucomiss(XMMRegister dst, XMMRegister src) { Assembler::ucomiss(dst, src); }
2123 void ucomiss(XMMRegister dst, Address src) { Assembler::ucomiss(dst, src); }
2124 void ucomiss(XMMRegister dst, AddressLiteral src);
2125
2126 void ucomisd(XMMRegister dst, XMMRegister src) { Assembler::ucomisd(dst, src); }
2127 void ucomisd(XMMRegister dst, Address src) { Assembler::ucomisd(dst, src); }
2128 void ucomisd(XMMRegister dst, AddressLiteral src);
2129
2130 // Bitwise Logical XOR of Packed Double-Precision Floating-Point Values
2131 void xorpd(XMMRegister dst, XMMRegister src) { Assembler::xorpd(dst, src); }
2132 void xorpd(XMMRegister dst, Address src) { Assembler::xorpd(dst, src); }
2133 void xorpd(XMMRegister dst, AddressLiteral src);
2134
2135 // Bitwise Logical XOR of Packed Single-Precision Floating-Point Values
2136 void xorps(XMMRegister dst, XMMRegister src) { Assembler::xorps(dst, src); }
2137 void xorps(XMMRegister dst, Address src) { Assembler::xorps(dst, src); }
2138 void xorps(XMMRegister dst, AddressLiteral src);
2139
2140 // Data
2141
2142 void cmov(Condition cc, Register dst, Register src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmovl(cc, dst, src)); }
2143
2144 void cmovptr(Condition cc, Register dst, Address src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmovl(cc, dst, src)); }
2145 void cmovptr(Condition cc, Register dst, Register src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmovl(cc, dst, src)); }
2146
2147 void movoop(Register dst, jobject obj);
2148 void movoop(Address dst, jobject obj);
2149
2150 void movptr(ArrayAddress dst, Register src);
2151 // can this do an lea?
2152 void movptr(Register dst, ArrayAddress src);
2153
2154 void movptr(Register dst, Address src);
2155
2156 void movptr(Register dst, AddressLiteral src);
2157
2158 void movptr(Register dst, intptr_t src);
2159 void movptr(Register dst, Register src);
2160 void movptr(Address dst, intptr_t src);
2161
2162 void movptr(Address dst, Register src);
2163
2164 #ifdef _LP64
2165 // Generally the next two are only used for moving NULL
2166 // Although there are situations in initializing the mark word where
2167 // they could be used. They are dangerous.
2168
2169 // They only exist on LP64 so that int32_t and intptr_t are not the same
2170 // and we have ambiguous declarations.
2171
2172 void movptr(Address dst, int32_t imm32);
2173 void movptr(Register dst, int32_t imm32);
2174 #endif // _LP64
2175
2176 // to avoid hiding movl
2177 void mov32(AddressLiteral dst, Register src);
2178 void mov32(Register dst, AddressLiteral src);
2179
2180 // to avoid hiding movb
2181 void movbyte(ArrayAddress dst, int src);
2182
2183 // Can push value or effective address
2184 void pushptr(AddressLiteral src);
2185
2186 void pushptr(Address src) { LP64_ONLY(pushq(src)) NOT_LP64(pushl(src)); }
2187 void popptr(Address src) { LP64_ONLY(popq(src)) NOT_LP64(popl(src)); }
2188
2189 void pushoop(jobject obj);
2190
2191 // sign extend as need a l to ptr sized element
2192 void movl2ptr(Register dst, Address src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(movl(dst, src)); }
2193 void movl2ptr(Register dst, Register src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(if (dst != src) movl(dst, src)); }
2194
2195
2196 #undef VIRTUAL
2197
2198 };
2199
2200 /**
2201 * class SkipIfEqual:
2202 *
2203 * Instantiating this class will result in assembly code being output that will
2204 * jump around any code emitted between the creation of the instance and it's
2205 * automatic destruction at the end of a scope block, depending on the value of
2206 * the flag passed to the constructor, which will be checked at run-time.
2207 */
2208 class SkipIfEqual {
2209 private:
2210 MacroAssembler* _masm;
2211 Label _label;
2212
2213 public:
2214 SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value);
2215 ~SkipIfEqual();
2216 };
2217
2218 #ifdef ASSERT
2219 inline bool AbstractAssembler::pd_check_instruction_mark() { return true; }
2220 #endif