1 /*
2 * Copyright 1997-2009 Sun Microsystems, Inc. All Rights Reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
20 * CA 95054 USA or visit www.sun.com if you need additional information or
21 * have any questions.
22 *
23 */
24
25 class VM_Version : public Abstract_VM_Version {
26 public:
27 // cpuid result register layouts. These are all unions of a uint32_t
28 // (in case anyone wants access to the register as a whole) and a bitfield.
29
30 union StdCpuid1Eax {
31 uint32_t value;
32 struct {
33 uint32_t stepping : 4,
34 model : 4,
35 family : 4,
36 proc_type : 2,
37 : 2,
38 ext_model : 4,
39 ext_family : 8,
40 : 4;
41 } bits;
42 };
43
44 union StdCpuid1Ebx { // example, unused
45 uint32_t value;
46 struct {
47 uint32_t brand_id : 8,
48 clflush_size : 8,
49 threads_per_cpu : 8,
50 apic_id : 8;
51 } bits;
52 };
53
54 union StdCpuid1Ecx {
55 uint32_t value;
56 struct {
57 uint32_t sse3 : 1,
58 : 2,
59 monitor : 1,
60 : 1,
61 vmx : 1,
62 : 1,
63 est : 1,
64 : 1,
65 ssse3 : 1,
66 cid : 1,
67 : 2,
68 cmpxchg16: 1,
69 : 4,
70 dca : 1,
71 sse4_1 : 1,
72 sse4_2 : 1,
73 : 2,
74 popcnt : 1,
75 : 8;
76 } bits;
77 };
78
79 union StdCpuid1Edx {
80 uint32_t value;
81 struct {
82 uint32_t : 4,
83 tsc : 1,
84 : 3,
85 cmpxchg8 : 1,
86 : 6,
87 cmov : 1,
88 : 7,
89 mmx : 1,
90 fxsr : 1,
91 sse : 1,
92 sse2 : 1,
93 : 1,
94 ht : 1,
95 : 3;
96 } bits;
97 };
98
99 union DcpCpuid4Eax {
100 uint32_t value;
101 struct {
102 uint32_t cache_type : 5,
103 : 21,
104 cores_per_cpu : 6;
105 } bits;
106 };
107
108 union DcpCpuid4Ebx {
109 uint32_t value;
110 struct {
111 uint32_t L1_line_size : 12,
112 partitions : 10,
113 associativity : 10;
114 } bits;
115 };
116
117 union ExtCpuid1Ecx {
118 uint32_t value;
119 struct {
120 uint32_t LahfSahf : 1,
121 CmpLegacy : 1,
122 : 4,
123 abm : 1,
124 sse4a : 1,
125 misalignsse : 1,
126 prefetchw : 1,
127 : 22;
128 } bits;
129 };
130
131 union ExtCpuid1Edx {
132 uint32_t value;
133 struct {
134 uint32_t : 22,
135 mmx_amd : 1,
136 mmx : 1,
137 fxsr : 1,
138 : 4,
139 long_mode : 1,
140 tdnow2 : 1,
141 tdnow : 1;
142 } bits;
143 };
144
145 union ExtCpuid5Ex {
146 uint32_t value;
147 struct {
148 uint32_t L1_line_size : 8,
149 L1_tag_lines : 8,
150 L1_assoc : 8,
151 L1_size : 8;
152 } bits;
153 };
154
155 union ExtCpuid8Ecx {
156 uint32_t value;
157 struct {
158 uint32_t cores_per_cpu : 8,
159 : 24;
160 } bits;
161 };
162
163 protected:
164 static int _cpu;
165 static int _model;
166 static int _stepping;
167 static int _cpuFeatures; // features returned by the "cpuid" instruction
168 // 0 if this instruction is not available
169 static const char* _features_str;
170
171 enum {
172 CPU_CX8 = (1 << 0), // next bits are from cpuid 1 (EDX)
173 CPU_CMOV = (1 << 1),
174 CPU_FXSR = (1 << 2),
175 CPU_HT = (1 << 3),
176 CPU_MMX = (1 << 4),
177 CPU_3DNOW = (1 << 5), // 3DNow comes from cpuid 0x80000001 (EDX)
178 CPU_SSE = (1 << 6),
179 CPU_SSE2 = (1 << 7),
180 CPU_SSE3 = (1 << 8), // SSE3 comes from cpuid 1 (ECX)
181 CPU_SSSE3 = (1 << 9),
182 CPU_SSE4A = (1 << 10),
183 CPU_SSE4_1 = (1 << 11),
184 CPU_SSE4_2 = (1 << 12),
185 CPU_POPCNT = (1 << 13)
186 } cpuFeatureFlags;
187
188 // cpuid information block. All info derived from executing cpuid with
189 // various function numbers is stored here. Intel and AMD info is
190 // merged in this block: accessor methods disentangle it.
191 //
192 // The info block is laid out in subblocks of 4 dwords corresponding to
193 // eax, ebx, ecx and edx, whether or not they contain anything useful.
194 struct CpuidInfo {
195 // cpuid function 0
196 uint32_t std_max_function;
197 uint32_t std_vendor_name_0;
198 uint32_t std_vendor_name_1;
199 uint32_t std_vendor_name_2;
200
201 // cpuid function 1
202 StdCpuid1Eax std_cpuid1_eax;
203 StdCpuid1Ebx std_cpuid1_ebx;
204 StdCpuid1Ecx std_cpuid1_ecx;
205 StdCpuid1Edx std_cpuid1_edx;
206
207 // cpuid function 4 (deterministic cache parameters)
208 DcpCpuid4Eax dcp_cpuid4_eax;
209 DcpCpuid4Ebx dcp_cpuid4_ebx;
210 uint32_t dcp_cpuid4_ecx; // unused currently
211 uint32_t dcp_cpuid4_edx; // unused currently
212
213 // cpuid function 0x80000000 // example, unused
214 uint32_t ext_max_function;
215 uint32_t ext_vendor_name_0;
216 uint32_t ext_vendor_name_1;
217 uint32_t ext_vendor_name_2;
218
219 // cpuid function 0x80000001
220 uint32_t ext_cpuid1_eax; // reserved
221 uint32_t ext_cpuid1_ebx; // reserved
222 ExtCpuid1Ecx ext_cpuid1_ecx;
223 ExtCpuid1Edx ext_cpuid1_edx;
224
225 // cpuid functions 0x80000002 thru 0x80000004: example, unused
226 uint32_t proc_name_0, proc_name_1, proc_name_2, proc_name_3;
227 uint32_t proc_name_4, proc_name_5, proc_name_6, proc_name_7;
228 uint32_t proc_name_8, proc_name_9, proc_name_10,proc_name_11;
229
230 // cpuid function 0x80000005 //AMD L1, Intel reserved
231 uint32_t ext_cpuid5_eax; // unused currently
232 uint32_t ext_cpuid5_ebx; // reserved
233 ExtCpuid5Ex ext_cpuid5_ecx; // L1 data cache info (AMD)
234 ExtCpuid5Ex ext_cpuid5_edx; // L1 instruction cache info (AMD)
235
236 // cpuid function 0x80000008
237 uint32_t ext_cpuid8_eax; // unused currently
238 uint32_t ext_cpuid8_ebx; // reserved
239 ExtCpuid8Ecx ext_cpuid8_ecx;
240 uint32_t ext_cpuid8_edx; // reserved
241 };
242
243 // The actual cpuid info block
244 static CpuidInfo _cpuid_info;
245
246 // Extractors and predicates
247 static uint32_t extended_cpu_family() {
248 uint32_t result = _cpuid_info.std_cpuid1_eax.bits.family;
249 result += _cpuid_info.std_cpuid1_eax.bits.ext_family;
250 return result;
251 }
252 static uint32_t extended_cpu_model() {
253 uint32_t result = _cpuid_info.std_cpuid1_eax.bits.model;
254 result |= _cpuid_info.std_cpuid1_eax.bits.ext_model << 4;
255 return result;
256 }
257 static uint32_t cpu_stepping() {
258 uint32_t result = _cpuid_info.std_cpuid1_eax.bits.stepping;
259 return result;
260 }
261 static uint logical_processor_count() {
262 uint result = threads_per_core();
263 return result;
264 }
265 static uint32_t feature_flags() {
266 uint32_t result = 0;
267 if (_cpuid_info.std_cpuid1_edx.bits.cmpxchg8 != 0)
268 result |= CPU_CX8;
269 if (_cpuid_info.std_cpuid1_edx.bits.cmov != 0)
270 result |= CPU_CMOV;
271 if (_cpuid_info.std_cpuid1_edx.bits.fxsr != 0 || is_amd() &&
272 _cpuid_info.ext_cpuid1_edx.bits.fxsr != 0)
273 result |= CPU_FXSR;
274 // HT flag is set for multi-core processors also.
275 if (threads_per_core() > 1)
276 result |= CPU_HT;
277 if (_cpuid_info.std_cpuid1_edx.bits.mmx != 0 || is_amd() &&
278 _cpuid_info.ext_cpuid1_edx.bits.mmx != 0)
279 result |= CPU_MMX;
280 if (is_amd() && _cpuid_info.ext_cpuid1_edx.bits.tdnow != 0)
281 result |= CPU_3DNOW;
282 if (_cpuid_info.std_cpuid1_edx.bits.sse != 0)
283 result |= CPU_SSE;
284 if (_cpuid_info.std_cpuid1_edx.bits.sse2 != 0)
285 result |= CPU_SSE2;
286 if (_cpuid_info.std_cpuid1_ecx.bits.sse3 != 0)
287 result |= CPU_SSE3;
288 if (_cpuid_info.std_cpuid1_ecx.bits.ssse3 != 0)
289 result |= CPU_SSSE3;
290 if (is_amd() && _cpuid_info.ext_cpuid1_ecx.bits.sse4a != 0)
291 result |= CPU_SSE4A;
292 if (_cpuid_info.std_cpuid1_ecx.bits.sse4_1 != 0)
293 result |= CPU_SSE4_1;
294 if (_cpuid_info.std_cpuid1_ecx.bits.sse4_2 != 0)
295 result |= CPU_SSE4_2;
296 if (_cpuid_info.std_cpuid1_ecx.bits.popcnt != 0)
297 result |= CPU_POPCNT;
298 return result;
299 }
300
301 static void get_processor_features();
302
303 public:
304 // Offsets for cpuid asm stub
305 static ByteSize std_cpuid0_offset() { return byte_offset_of(CpuidInfo, std_max_function); }
306 static ByteSize std_cpuid1_offset() { return byte_offset_of(CpuidInfo, std_cpuid1_eax); }
307 static ByteSize dcp_cpuid4_offset() { return byte_offset_of(CpuidInfo, dcp_cpuid4_eax); }
308 static ByteSize ext_cpuid1_offset() { return byte_offset_of(CpuidInfo, ext_cpuid1_eax); }
309 static ByteSize ext_cpuid5_offset() { return byte_offset_of(CpuidInfo, ext_cpuid5_eax); }
310 static ByteSize ext_cpuid8_offset() { return byte_offset_of(CpuidInfo, ext_cpuid8_eax); }
311
312 // Initialization
313 static void initialize();
314
315 // Asserts
316 static void assert_is_initialized() {
317 assert(_cpuid_info.std_cpuid1_eax.bits.family != 0, "VM_Version not initialized");
318 }
319
320 //
321 // Processor family:
322 // 3 - 386
323 // 4 - 486
324 // 5 - Pentium
325 // 6 - PentiumPro, Pentium II, Celeron, Xeon, Pentium III, Athlon,
326 // Pentium M, Core Solo, Core Duo, Core2 Duo
327 // family 6 model: 9, 13, 14, 15
328 // 0x0f - Pentium 4, Opteron
329 //
330 // Note: The cpu family should be used to select between
331 // instruction sequences which are valid on all Intel
332 // processors. Use the feature test functions below to
333 // determine whether a particular instruction is supported.
334 //
335 static int cpu_family() { return _cpu;}
336 static bool is_P6() { return cpu_family() >= 6; }
337
338 static bool is_amd() { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x68747541; } // 'htuA'
339 static bool is_intel() { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x756e6547; } // 'uneG'
340
341 static uint cores_per_cpu() {
342 uint result = 1;
343 if (is_intel()) {
344 result = (_cpuid_info.dcp_cpuid4_eax.bits.cores_per_cpu + 1);
345 } else if (is_amd()) {
346 result = (_cpuid_info.ext_cpuid8_ecx.bits.cores_per_cpu + 1);
347 }
348 return result;
349 }
350
351 static uint threads_per_core() {
352 uint result = 1;
353 if (_cpuid_info.std_cpuid1_edx.bits.ht != 0) {
354 result = _cpuid_info.std_cpuid1_ebx.bits.threads_per_cpu /
355 cores_per_cpu();
356 }
357 return result;
358 }
359
360 static intx L1_data_cache_line_size() {
361 intx result = 0;
362 if (is_intel()) {
363 result = (_cpuid_info.dcp_cpuid4_ebx.bits.L1_line_size + 1);
364 } else if (is_amd()) {
365 result = _cpuid_info.ext_cpuid5_ecx.bits.L1_line_size;
366 }
367 if (result < 32) // not defined ?
368 result = 32; // 32 bytes by default on x86 and other x64
369 return result;
370 }
371
372 //
373 // Feature identification
374 //
375 static bool supports_cpuid() { return _cpuFeatures != 0; }
376 static bool supports_cmpxchg8() { return (_cpuFeatures & CPU_CX8) != 0; }
377 static bool supports_cmov() { return (_cpuFeatures & CPU_CMOV) != 0; }
378 static bool supports_fxsr() { return (_cpuFeatures & CPU_FXSR) != 0; }
379 static bool supports_ht() { return (_cpuFeatures & CPU_HT) != 0; }
380 static bool supports_mmx() { return (_cpuFeatures & CPU_MMX) != 0; }
381 static bool supports_sse() { return (_cpuFeatures & CPU_SSE) != 0; }
382 static bool supports_sse2() { return (_cpuFeatures & CPU_SSE2) != 0; }
383 static bool supports_sse3() { return (_cpuFeatures & CPU_SSE3) != 0; }
384 static bool supports_ssse3() { return (_cpuFeatures & CPU_SSSE3)!= 0; }
385 static bool supports_sse4_1() { return (_cpuFeatures & CPU_SSE4_1) != 0; }
386 static bool supports_sse4_2() { return (_cpuFeatures & CPU_SSE4_2) != 0; }
387 static bool supports_popcnt() { return (_cpuFeatures & CPU_POPCNT) != 0; }
388 //
389 // AMD features
390 //
391 static bool supports_3dnow() { return (_cpuFeatures & CPU_3DNOW) != 0; }
392 static bool supports_mmx_ext() { return is_amd() && _cpuid_info.ext_cpuid1_edx.bits.mmx_amd != 0; }
393 static bool supports_3dnow2() { return is_amd() && _cpuid_info.ext_cpuid1_edx.bits.tdnow2 != 0; }
394 static bool supports_sse4a() { return (_cpuFeatures & CPU_SSE4A) != 0; }
395
396 static bool supports_compare_and_exchange() { return true; }
397
398 static const char* cpu_features() { return _features_str; }
399
400 static intx allocate_prefetch_distance() {
401 // This method should be called before allocate_prefetch_style().
402 //
403 // Hardware prefetching (distance/size in bytes):
404 // Pentium 3 - 64 / 32
405 // Pentium 4 - 256 / 128
406 // Athlon - 64 / 32 ????
407 // Opteron - 128 / 64 only when 2 sequential cache lines accessed
408 // Core - 128 / 64
409 //
410 // Software prefetching (distance in bytes / instruction with best score):
411 // Pentium 3 - 128 / prefetchnta
412 // Pentium 4 - 512 / prefetchnta
413 // Athlon - 128 / prefetchnta
414 // Opteron - 256 / prefetchnta
415 // Core - 256 / prefetchnta
416 // It will be used only when AllocatePrefetchStyle > 0
417
418 intx count = AllocatePrefetchDistance;
419 if (count < 0) { // default ?
420 if (is_amd()) { // AMD
421 if (supports_sse2())
422 count = 256; // Opteron
423 else
424 count = 128; // Athlon
425 } else { // Intel
426 if (supports_sse2())
427 if (cpu_family() == 6) {
428 count = 256; // Pentium M, Core, Core2
429 } else {
430 count = 512; // Pentium 4
431 }
432 else
433 count = 128; // Pentium 3 (and all other old CPUs)
434 }
435 }
436 return count;
437 }
438 static intx allocate_prefetch_style() {
439 assert(AllocatePrefetchStyle >= 0, "AllocatePrefetchStyle should be positive");
440 // Return 0 if AllocatePrefetchDistance was not defined.
441 return AllocatePrefetchDistance > 0 ? AllocatePrefetchStyle : 0;
442 }
443
444 // Prefetch interval for gc copy/scan == 9 dcache lines. Derived from
445 // 50-warehouse specjbb runs on a 2-way 1.8ghz opteron using a 4gb heap.
446 // Tested intervals from 128 to 2048 in increments of 64 == one cache line.
447 // 256 bytes (4 dcache lines) was the nearest runner-up to 576.
448
449 // gc copy/scan is disabled if prefetchw isn't supported, because
450 // Prefetch::write emits an inlined prefetchw on Linux.
451 // Do not use the 3dnow prefetchw instruction. It isn't supported on em64t.
452 // The used prefetcht0 instruction works for both amd64 and em64t.
453 static intx prefetch_copy_interval_in_bytes() {
454 intx interval = PrefetchCopyIntervalInBytes;
455 return interval >= 0 ? interval : 576;
456 }
457 static intx prefetch_scan_interval_in_bytes() {
458 intx interval = PrefetchScanIntervalInBytes;
459 return interval >= 0 ? interval : 576;
460 }
461 static intx prefetch_fields_ahead() {
462 intx count = PrefetchFieldsAhead;
463 return count >= 0 ? count : 1;
464 }
465 };