1 //
2 // Copyright 1997-2009 Sun Microsystems, Inc. All Rights Reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
9 // This code is distributed in the hope that it will be useful, but WITHOUT
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
15 // You should have received a copy of the GNU General Public License version
16 // 2 along with this work; if not, write to the Free Software Foundation,
17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 //
19 // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
20 // CA 95054 USA or visit www.sun.com if you need additional information or
21 // have any questions.
22 //
23 //
24
25 // X86 Architecture Description File
26
27 //----------REGISTER DEFINITION BLOCK------------------------------------------
28 // This information is used by the matcher and the register allocator to
29 // describe individual registers and classes of registers within the target
30 // archtecture.
31
32 register %{
33 //----------Architecture Description Register Definitions----------------------
34 // General Registers
35 // "reg_def" name ( register save type, C convention save type,
36 // ideal register type, encoding );
37 // Register Save Types:
38 //
39 // NS = No-Save: The register allocator assumes that these registers
40 // can be used without saving upon entry to the method, &
41 // that they do not need to be saved at call sites.
42 //
43 // SOC = Save-On-Call: The register allocator assumes that these registers
44 // can be used without saving upon entry to the method,
45 // but that they must be saved at call sites.
46 //
47 // SOE = Save-On-Entry: The register allocator assumes that these registers
48 // must be saved before using them upon entry to the
49 // method, but they do not need to be saved at call
50 // sites.
51 //
52 // AS = Always-Save: The register allocator assumes that these registers
53 // must be saved before using them upon entry to the
54 // method, & that they must be saved at call sites.
55 //
56 // Ideal Register Type is used to determine how to save & restore a
57 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
58 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
59 //
60 // The encoding number is the actual bit-pattern placed into the opcodes.
61
62 // General Registers
63 // Previously set EBX, ESI, and EDI as save-on-entry for java code
64 // Turn off SOE in java-code due to frequent use of uncommon-traps.
65 // Now that allocator is better, turn on ESI and EDI as SOE registers.
66
67 reg_def EBX(SOC, SOE, Op_RegI, 3, rbx->as_VMReg());
68 reg_def ECX(SOC, SOC, Op_RegI, 1, rcx->as_VMReg());
69 reg_def ESI(SOC, SOE, Op_RegI, 6, rsi->as_VMReg());
70 reg_def EDI(SOC, SOE, Op_RegI, 7, rdi->as_VMReg());
71 // now that adapter frames are gone EBP is always saved and restored by the prolog/epilog code
72 reg_def EBP(NS, SOE, Op_RegI, 5, rbp->as_VMReg());
73 reg_def EDX(SOC, SOC, Op_RegI, 2, rdx->as_VMReg());
74 reg_def EAX(SOC, SOC, Op_RegI, 0, rax->as_VMReg());
75 reg_def ESP( NS, NS, Op_RegI, 4, rsp->as_VMReg());
76
77 // Special Registers
78 reg_def EFLAGS(SOC, SOC, 0, 8, VMRegImpl::Bad());
79
80 // Float registers. We treat TOS/FPR0 special. It is invisible to the
81 // allocator, and only shows up in the encodings.
82 reg_def FPR0L( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad());
83 reg_def FPR0H( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad());
84 // Ok so here's the trick FPR1 is really st(0) except in the midst
85 // of emission of assembly for a machnode. During the emission the fpu stack
86 // is pushed making FPR1 == st(1) temporarily. However at any safepoint
87 // the stack will not have this element so FPR1 == st(0) from the
88 // oopMap viewpoint. This same weirdness with numbering causes
89 // instruction encoding to have to play games with the register
90 // encode to correct for this 0/1 issue. See MachSpillCopyNode::implementation
91 // where it does flt->flt moves to see an example
92 //
93 reg_def FPR1L( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg());
94 reg_def FPR1H( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg()->next());
95 reg_def FPR2L( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg());
96 reg_def FPR2H( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg()->next());
97 reg_def FPR3L( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg());
98 reg_def FPR3H( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg()->next());
99 reg_def FPR4L( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg());
100 reg_def FPR4H( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg()->next());
101 reg_def FPR5L( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg());
102 reg_def FPR5H( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg()->next());
103 reg_def FPR6L( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg());
104 reg_def FPR6H( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg()->next());
105 reg_def FPR7L( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg());
106 reg_def FPR7H( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg()->next());
107
108 // XMM registers. 128-bit registers or 4 words each, labeled a-d.
109 // Word a in each register holds a Float, words ab hold a Double.
110 // We currently do not use the SIMD capabilities, so registers cd
111 // are unused at the moment.
112 reg_def XMM0a( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg());
113 reg_def XMM0b( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()->next());
114 reg_def XMM1a( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg());
115 reg_def XMM1b( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()->next());
116 reg_def XMM2a( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg());
117 reg_def XMM2b( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()->next());
118 reg_def XMM3a( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg());
119 reg_def XMM3b( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()->next());
120 reg_def XMM4a( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg());
121 reg_def XMM4b( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()->next());
122 reg_def XMM5a( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg());
123 reg_def XMM5b( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()->next());
124 reg_def XMM6a( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg());
125 reg_def XMM6b( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()->next());
126 reg_def XMM7a( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg());
127 reg_def XMM7b( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()->next());
128
129 // Specify priority of register selection within phases of register
130 // allocation. Highest priority is first. A useful heuristic is to
131 // give registers a low priority when they are required by machine
132 // instructions, like EAX and EDX. Registers which are used as
133 // pairs must fall on an even boundary (witness the FPR#L's in this list).
134 // For the Intel integer registers, the equivalent Long pairs are
135 // EDX:EAX, EBX:ECX, and EDI:EBP.
136 alloc_class chunk0( ECX, EBX, EBP, EDI, EAX, EDX, ESI, ESP,
137 FPR0L, FPR0H, FPR1L, FPR1H, FPR2L, FPR2H,
138 FPR3L, FPR3H, FPR4L, FPR4H, FPR5L, FPR5H,
139 FPR6L, FPR6H, FPR7L, FPR7H );
140
141 alloc_class chunk1( XMM0a, XMM0b,
142 XMM1a, XMM1b,
143 XMM2a, XMM2b,
144 XMM3a, XMM3b,
145 XMM4a, XMM4b,
146 XMM5a, XMM5b,
147 XMM6a, XMM6b,
148 XMM7a, XMM7b, EFLAGS);
149
150
151 //----------Architecture Description Register Classes--------------------------
152 // Several register classes are automatically defined based upon information in
153 // this architecture description.
154 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ )
155 // 2) reg_class compiler_method_oop_reg ( /* as def'd in frame section */ )
156 // 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ )
157 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
158 //
159 // Class for all registers
160 reg_class any_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX, ESP);
161 // Class for general registers
162 reg_class e_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX);
163 // Class for general registers which may be used for implicit null checks on win95
164 // Also safe for use by tailjump. We don't want to allocate in rbp,
165 reg_class e_reg_no_rbp(EAX, EDX, EDI, ESI, ECX, EBX);
166 // Class of "X" registers
167 reg_class x_reg(EBX, ECX, EDX, EAX);
168 // Class of registers that can appear in an address with no offset.
169 // EBP and ESP require an extra instruction byte for zero offset.
170 // Used in fast-unlock
171 reg_class p_reg(EDX, EDI, ESI, EBX);
172 // Class for general registers not including ECX
173 reg_class ncx_reg(EAX, EDX, EBP, EDI, ESI, EBX);
174 // Class for general registers not including EAX
175 reg_class nax_reg(EDX, EDI, ESI, ECX, EBX);
176 // Class for general registers not including EAX or EBX.
177 reg_class nabx_reg(EDX, EDI, ESI, ECX, EBP);
178 // Class of EAX (for multiply and divide operations)
179 reg_class eax_reg(EAX);
180 // Class of EBX (for atomic add)
181 reg_class ebx_reg(EBX);
182 // Class of ECX (for shift and JCXZ operations and cmpLTMask)
183 reg_class ecx_reg(ECX);
184 // Class of EDX (for multiply and divide operations)
185 reg_class edx_reg(EDX);
186 // Class of EDI (for synchronization)
187 reg_class edi_reg(EDI);
188 // Class of ESI (for synchronization)
189 reg_class esi_reg(ESI);
190 // Singleton class for interpreter's stack pointer
191 reg_class ebp_reg(EBP);
192 // Singleton class for stack pointer
193 reg_class sp_reg(ESP);
194 // Singleton class for instruction pointer
195 // reg_class ip_reg(EIP);
196 // Singleton class for condition codes
197 reg_class int_flags(EFLAGS);
198 // Class of integer register pairs
199 reg_class long_reg( EAX,EDX, ECX,EBX, EBP,EDI );
200 // Class of integer register pairs that aligns with calling convention
201 reg_class eadx_reg( EAX,EDX );
202 reg_class ebcx_reg( ECX,EBX );
203 // Not AX or DX, used in divides
204 reg_class nadx_reg( EBX,ECX,ESI,EDI,EBP );
205
206 // Floating point registers. Notice FPR0 is not a choice.
207 // FPR0 is not ever allocated; we use clever encodings to fake
208 // a 2-address instructions out of Intels FP stack.
209 reg_class flt_reg( FPR1L,FPR2L,FPR3L,FPR4L,FPR5L,FPR6L,FPR7L );
210
211 // make a register class for SSE registers
212 reg_class xmm_reg(XMM0a, XMM1a, XMM2a, XMM3a, XMM4a, XMM5a, XMM6a, XMM7a);
213
214 // make a double register class for SSE2 registers
215 reg_class xdb_reg(XMM0a,XMM0b, XMM1a,XMM1b, XMM2a,XMM2b, XMM3a,XMM3b,
216 XMM4a,XMM4b, XMM5a,XMM5b, XMM6a,XMM6b, XMM7a,XMM7b );
217
218 reg_class dbl_reg( FPR1L,FPR1H, FPR2L,FPR2H, FPR3L,FPR3H,
219 FPR4L,FPR4H, FPR5L,FPR5H, FPR6L,FPR6H,
220 FPR7L,FPR7H );
221
222 reg_class flt_reg0( FPR1L );
223 reg_class dbl_reg0( FPR1L,FPR1H );
224 reg_class dbl_reg1( FPR2L,FPR2H );
225 reg_class dbl_notreg0( FPR2L,FPR2H, FPR3L,FPR3H, FPR4L,FPR4H,
226 FPR5L,FPR5H, FPR6L,FPR6H, FPR7L,FPR7H );
227
228 // XMM6 and XMM7 could be used as temporary registers for long, float and
229 // double values for SSE2.
230 reg_class xdb_reg6( XMM6a,XMM6b );
231 reg_class xdb_reg7( XMM7a,XMM7b );
232 %}
233
234
235 //----------SOURCE BLOCK-------------------------------------------------------
236 // This is a block of C++ code which provides values, functions, and
237 // definitions necessary in the rest of the architecture description
238 source %{
239 #define RELOC_IMM32 Assembler::imm_operand
240 #define RELOC_DISP32 Assembler::disp32_operand
241
242 #define __ _masm.
243
244 // How to find the high register of a Long pair, given the low register
245 #define HIGH_FROM_LOW(x) ((x)+2)
246
247 // These masks are used to provide 128-bit aligned bitmasks to the XMM
248 // instructions, to allow sign-masking or sign-bit flipping. They allow
249 // fast versions of NegF/NegD and AbsF/AbsD.
250
251 // Note: 'double' and 'long long' have 32-bits alignment on x86.
252 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) {
253 // Use the expression (adr)&(~0xF) to provide 128-bits aligned address
254 // of 128-bits operands for SSE instructions.
255 jlong *operand = (jlong*)(((uintptr_t)adr)&((uintptr_t)(~0xF)));
256 // Store the value to a 128-bits operand.
257 operand[0] = lo;
258 operand[1] = hi;
259 return operand;
260 }
261
262 // Buffer for 128-bits masks used by SSE instructions.
263 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment)
264
265 // Static initialization during VM startup.
266 static jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF));
267 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF));
268 static jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], CONST64(0x8000000080000000), CONST64(0x8000000080000000));
269 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], CONST64(0x8000000000000000), CONST64(0x8000000000000000));
270
271 // !!!!! Special hack to get all type of calls to specify the byte offset
272 // from the start of the call to the point where the return address
273 // will point.
274 int MachCallStaticJavaNode::ret_addr_offset() {
275 return 5 + (Compile::current()->in_24_bit_fp_mode() ? 6 : 0); // 5 bytes from start of call to where return address points
276 }
277
278 int MachCallDynamicJavaNode::ret_addr_offset() {
279 return 10 + (Compile::current()->in_24_bit_fp_mode() ? 6 : 0); // 10 bytes from start of call to where return address points
280 }
281
282 static int sizeof_FFree_Float_Stack_All = -1;
283
284 int MachCallRuntimeNode::ret_addr_offset() {
285 assert(sizeof_FFree_Float_Stack_All != -1, "must have been emitted already");
286 return sizeof_FFree_Float_Stack_All + 5 + (Compile::current()->in_24_bit_fp_mode() ? 6 : 0);
287 }
288
289 // Indicate if the safepoint node needs the polling page as an input.
290 // Since x86 does have absolute addressing, it doesn't.
291 bool SafePointNode::needs_polling_address_input() {
292 return false;
293 }
294
295 //
296 // Compute padding required for nodes which need alignment
297 //
298
299 // The address of the call instruction needs to be 4-byte aligned to
300 // ensure that it does not span a cache line so that it can be patched.
301 int CallStaticJavaDirectNode::compute_padding(int current_offset) const {
302 if (Compile::current()->in_24_bit_fp_mode())
303 current_offset += 6; // skip fldcw in pre_call_FPU, if any
304 current_offset += 1; // skip call opcode byte
305 return round_to(current_offset, alignment_required()) - current_offset;
306 }
307
308 // The address of the call instruction needs to be 4-byte aligned to
309 // ensure that it does not span a cache line so that it can be patched.
310 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const {
311 if (Compile::current()->in_24_bit_fp_mode())
312 current_offset += 6; // skip fldcw in pre_call_FPU, if any
313 current_offset += 5; // skip MOV instruction
314 current_offset += 1; // skip call opcode byte
315 return round_to(current_offset, alignment_required()) - current_offset;
316 }
317
318 #ifndef PRODUCT
319 void MachBreakpointNode::format( PhaseRegAlloc *, outputStream* st ) const {
320 st->print("INT3");
321 }
322 #endif
323
324 // EMIT_RM()
325 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) {
326 unsigned char c = (unsigned char)((f1 << 6) | (f2 << 3) | f3);
327 *(cbuf.code_end()) = c;
328 cbuf.set_code_end(cbuf.code_end() + 1);
329 }
330
331 // EMIT_CC()
332 void emit_cc(CodeBuffer &cbuf, int f1, int f2) {
333 unsigned char c = (unsigned char)( f1 | f2 );
334 *(cbuf.code_end()) = c;
335 cbuf.set_code_end(cbuf.code_end() + 1);
336 }
337
338 // EMIT_OPCODE()
339 void emit_opcode(CodeBuffer &cbuf, int code) {
340 *(cbuf.code_end()) = (unsigned char)code;
341 cbuf.set_code_end(cbuf.code_end() + 1);
342 }
343
344 // EMIT_OPCODE() w/ relocation information
345 void emit_opcode(CodeBuffer &cbuf, int code, relocInfo::relocType reloc, int offset = 0) {
346 cbuf.relocate(cbuf.inst_mark() + offset, reloc);
347 emit_opcode(cbuf, code);
348 }
349
350 // EMIT_D8()
351 void emit_d8(CodeBuffer &cbuf, int d8) {
352 *(cbuf.code_end()) = (unsigned char)d8;
353 cbuf.set_code_end(cbuf.code_end() + 1);
354 }
355
356 // EMIT_D16()
357 void emit_d16(CodeBuffer &cbuf, int d16) {
358 *((short *)(cbuf.code_end())) = d16;
359 cbuf.set_code_end(cbuf.code_end() + 2);
360 }
361
362 // EMIT_D32()
363 void emit_d32(CodeBuffer &cbuf, int d32) {
364 *((int *)(cbuf.code_end())) = d32;
365 cbuf.set_code_end(cbuf.code_end() + 4);
366 }
367
368 // emit 32 bit value and construct relocation entry from relocInfo::relocType
369 void emit_d32_reloc(CodeBuffer &cbuf, int d32, relocInfo::relocType reloc,
370 int format) {
371 cbuf.relocate(cbuf.inst_mark(), reloc, format);
372
373 *((int *)(cbuf.code_end())) = d32;
374 cbuf.set_code_end(cbuf.code_end() + 4);
375 }
376
377 // emit 32 bit value and construct relocation entry from RelocationHolder
378 void emit_d32_reloc(CodeBuffer &cbuf, int d32, RelocationHolder const& rspec,
379 int format) {
380 #ifdef ASSERT
381 if (rspec.reloc()->type() == relocInfo::oop_type && d32 != 0 && d32 != (int)Universe::non_oop_word()) {
382 assert(oop(d32)->is_oop() && oop(d32)->is_perm(), "cannot embed non-perm oops in code");
383 }
384 #endif
385 cbuf.relocate(cbuf.inst_mark(), rspec, format);
386
387 *((int *)(cbuf.code_end())) = d32;
388 cbuf.set_code_end(cbuf.code_end() + 4);
389 }
390
391 // Access stack slot for load or store
392 void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp) {
393 emit_opcode( cbuf, opcode ); // (e.g., FILD [ESP+src])
394 if( -128 <= disp && disp <= 127 ) {
395 emit_rm( cbuf, 0x01, rm_field, ESP_enc ); // R/M byte
396 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
397 emit_d8 (cbuf, disp); // Displacement // R/M byte
398 } else {
399 emit_rm( cbuf, 0x02, rm_field, ESP_enc ); // R/M byte
400 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
401 emit_d32(cbuf, disp); // Displacement // R/M byte
402 }
403 }
404
405 // eRegI ereg, memory mem) %{ // emit_reg_mem
406 void encode_RegMem( CodeBuffer &cbuf, int reg_encoding, int base, int index, int scale, int displace, bool displace_is_oop ) {
407 // There is no index & no scale, use form without SIB byte
408 if ((index == 0x4) &&
409 (scale == 0) && (base != ESP_enc)) {
410 // If no displacement, mode is 0x0; unless base is [EBP]
411 if ( (displace == 0) && (base != EBP_enc) ) {
412 emit_rm(cbuf, 0x0, reg_encoding, base);
413 }
414 else { // If 8-bit displacement, mode 0x1
415 if ((displace >= -128) && (displace <= 127)
416 && !(displace_is_oop) ) {
417 emit_rm(cbuf, 0x1, reg_encoding, base);
418 emit_d8(cbuf, displace);
419 }
420 else { // If 32-bit displacement
421 if (base == -1) { // Special flag for absolute address
422 emit_rm(cbuf, 0x0, reg_encoding, 0x5);
423 // (manual lies; no SIB needed here)
424 if ( displace_is_oop ) {
425 emit_d32_reloc(cbuf, displace, relocInfo::oop_type, 1);
426 } else {
427 emit_d32 (cbuf, displace);
428 }
429 }
430 else { // Normal base + offset
431 emit_rm(cbuf, 0x2, reg_encoding, base);
432 if ( displace_is_oop ) {
433 emit_d32_reloc(cbuf, displace, relocInfo::oop_type, 1);
434 } else {
435 emit_d32 (cbuf, displace);
436 }
437 }
438 }
439 }
440 }
441 else { // Else, encode with the SIB byte
442 // If no displacement, mode is 0x0; unless base is [EBP]
443 if (displace == 0 && (base != EBP_enc)) { // If no displacement
444 emit_rm(cbuf, 0x0, reg_encoding, 0x4);
445 emit_rm(cbuf, scale, index, base);
446 }
447 else { // If 8-bit displacement, mode 0x1
448 if ((displace >= -128) && (displace <= 127)
449 && !(displace_is_oop) ) {
450 emit_rm(cbuf, 0x1, reg_encoding, 0x4);
451 emit_rm(cbuf, scale, index, base);
452 emit_d8(cbuf, displace);
453 }
454 else { // If 32-bit displacement
455 if (base == 0x04 ) {
456 emit_rm(cbuf, 0x2, reg_encoding, 0x4);
457 emit_rm(cbuf, scale, index, 0x04);
458 } else {
459 emit_rm(cbuf, 0x2, reg_encoding, 0x4);
460 emit_rm(cbuf, scale, index, base);
461 }
462 if ( displace_is_oop ) {
463 emit_d32_reloc(cbuf, displace, relocInfo::oop_type, 1);
464 } else {
465 emit_d32 (cbuf, displace);
466 }
467 }
468 }
469 }
470 }
471
472
473 void encode_Copy( CodeBuffer &cbuf, int dst_encoding, int src_encoding ) {
474 if( dst_encoding == src_encoding ) {
475 // reg-reg copy, use an empty encoding
476 } else {
477 emit_opcode( cbuf, 0x8B );
478 emit_rm(cbuf, 0x3, dst_encoding, src_encoding );
479 }
480 }
481
482 void encode_CopyXD( CodeBuffer &cbuf, int dst_encoding, int src_encoding ) {
483 if( dst_encoding == src_encoding ) {
484 // reg-reg copy, use an empty encoding
485 } else {
486 MacroAssembler _masm(&cbuf);
487
488 __ movdqa(as_XMMRegister(dst_encoding), as_XMMRegister(src_encoding));
489 }
490 }
491
492
493 //=============================================================================
494 #ifndef PRODUCT
495 void MachPrologNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
496 Compile* C = ra_->C;
497 if( C->in_24_bit_fp_mode() ) {
498 st->print("FLDCW 24 bit fpu control word");
499 st->print_cr(""); st->print("\t");
500 }
501
502 int framesize = C->frame_slots() << LogBytesPerInt;
503 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
504 // Remove two words for return addr and rbp,
505 framesize -= 2*wordSize;
506
507 // Calls to C2R adapters often do not accept exceptional returns.
508 // We require that their callers must bang for them. But be careful, because
509 // some VM calls (such as call site linkage) can use several kilobytes of
510 // stack. But the stack safety zone should account for that.
511 // See bugs 4446381, 4468289, 4497237.
512 if (C->need_stack_bang(framesize)) {
513 st->print_cr("# stack bang"); st->print("\t");
514 }
515 st->print_cr("PUSHL EBP"); st->print("\t");
516
517 if( VerifyStackAtCalls ) { // Majik cookie to verify stack depth
518 st->print("PUSH 0xBADB100D\t# Majik cookie for stack depth check");
519 st->print_cr(""); st->print("\t");
520 framesize -= wordSize;
521 }
522
523 if ((C->in_24_bit_fp_mode() || VerifyStackAtCalls ) && framesize < 128 ) {
524 if (framesize) {
525 st->print("SUB ESP,%d\t# Create frame",framesize);
526 }
527 } else {
528 st->print("SUB ESP,%d\t# Create frame",framesize);
529 }
530 }
531 #endif
532
533
534 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
535 Compile* C = ra_->C;
536
537 if (UseSSE >= 2 && VerifyFPU) {
538 MacroAssembler masm(&cbuf);
539 masm.verify_FPU(0, "FPU stack must be clean on entry");
540 }
541
542 // WARNING: Initial instruction MUST be 5 bytes or longer so that
543 // NativeJump::patch_verified_entry will be able to patch out the entry
544 // code safely. The fldcw is ok at 6 bytes, the push to verify stack
545 // depth is ok at 5 bytes, the frame allocation can be either 3 or
546 // 6 bytes. So if we don't do the fldcw or the push then we must
547 // use the 6 byte frame allocation even if we have no frame. :-(
548 // If method sets FPU control word do it now
549 if( C->in_24_bit_fp_mode() ) {
550 MacroAssembler masm(&cbuf);
551 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
552 }
553
554 int framesize = C->frame_slots() << LogBytesPerInt;
555 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
556 // Remove two words for return addr and rbp,
557 framesize -= 2*wordSize;
558
559 // Calls to C2R adapters often do not accept exceptional returns.
560 // We require that their callers must bang for them. But be careful, because
561 // some VM calls (such as call site linkage) can use several kilobytes of
562 // stack. But the stack safety zone should account for that.
563 // See bugs 4446381, 4468289, 4497237.
564 if (C->need_stack_bang(framesize)) {
565 MacroAssembler masm(&cbuf);
566 masm.generate_stack_overflow_check(framesize);
567 }
568
569 // We always push rbp, so that on return to interpreter rbp, will be
570 // restored correctly and we can correct the stack.
571 emit_opcode(cbuf, 0x50 | EBP_enc);
572
573 if( VerifyStackAtCalls ) { // Majik cookie to verify stack depth
574 emit_opcode(cbuf, 0x68); // push 0xbadb100d
575 emit_d32(cbuf, 0xbadb100d);
576 framesize -= wordSize;
577 }
578
579 if ((C->in_24_bit_fp_mode() || VerifyStackAtCalls ) && framesize < 128 ) {
580 if (framesize) {
581 emit_opcode(cbuf, 0x83); // sub SP,#framesize
582 emit_rm(cbuf, 0x3, 0x05, ESP_enc);
583 emit_d8(cbuf, framesize);
584 }
585 } else {
586 emit_opcode(cbuf, 0x81); // sub SP,#framesize
587 emit_rm(cbuf, 0x3, 0x05, ESP_enc);
588 emit_d32(cbuf, framesize);
589 }
590 C->set_frame_complete(cbuf.code_end() - cbuf.code_begin());
591
592 #ifdef ASSERT
593 if (VerifyStackAtCalls) {
594 Label L;
595 MacroAssembler masm(&cbuf);
596 masm.push(rax);
597 masm.mov(rax, rsp);
598 masm.andptr(rax, StackAlignmentInBytes-1);
599 masm.cmpptr(rax, StackAlignmentInBytes-wordSize);
600 masm.pop(rax);
601 masm.jcc(Assembler::equal, L);
602 masm.stop("Stack is not properly aligned!");
603 masm.bind(L);
604 }
605 #endif
606
607 }
608
609 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
610 return MachNode::size(ra_); // too many variables; just compute it the hard way
611 }
612
613 int MachPrologNode::reloc() const {
614 return 0; // a large enough number
615 }
616
617 //=============================================================================
618 #ifndef PRODUCT
619 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
620 Compile *C = ra_->C;
621 int framesize = C->frame_slots() << LogBytesPerInt;
622 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
623 // Remove two words for return addr and rbp,
624 framesize -= 2*wordSize;
625
626 if( C->in_24_bit_fp_mode() ) {
627 st->print("FLDCW standard control word");
628 st->cr(); st->print("\t");
629 }
630 if( framesize ) {
631 st->print("ADD ESP,%d\t# Destroy frame",framesize);
632 st->cr(); st->print("\t");
633 }
634 st->print_cr("POPL EBP"); st->print("\t");
635 if( do_polling() && C->is_method_compilation() ) {
636 st->print("TEST PollPage,EAX\t! Poll Safepoint");
637 st->cr(); st->print("\t");
638 }
639 }
640 #endif
641
642 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
643 Compile *C = ra_->C;
644
645 // If method set FPU control word, restore to standard control word
646 if( C->in_24_bit_fp_mode() ) {
647 MacroAssembler masm(&cbuf);
648 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
649 }
650
651 int framesize = C->frame_slots() << LogBytesPerInt;
652 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
653 // Remove two words for return addr and rbp,
654 framesize -= 2*wordSize;
655
656 // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here
657
658 if( framesize >= 128 ) {
659 emit_opcode(cbuf, 0x81); // add SP, #framesize
660 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
661 emit_d32(cbuf, framesize);
662 }
663 else if( framesize ) {
664 emit_opcode(cbuf, 0x83); // add SP, #framesize
665 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
666 emit_d8(cbuf, framesize);
667 }
668
669 emit_opcode(cbuf, 0x58 | EBP_enc);
670
671 if( do_polling() && C->is_method_compilation() ) {
672 cbuf.relocate(cbuf.code_end(), relocInfo::poll_return_type, 0);
673 emit_opcode(cbuf,0x85);
674 emit_rm(cbuf, 0x0, EAX_enc, 0x5); // EAX
675 emit_d32(cbuf, (intptr_t)os::get_polling_page());
676 }
677 }
678
679 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
680 Compile *C = ra_->C;
681 // If method set FPU control word, restore to standard control word
682 int size = C->in_24_bit_fp_mode() ? 6 : 0;
683 if( do_polling() && C->is_method_compilation() ) size += 6;
684
685 int framesize = C->frame_slots() << LogBytesPerInt;
686 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
687 // Remove two words for return addr and rbp,
688 framesize -= 2*wordSize;
689
690 size++; // popl rbp,
691
692 if( framesize >= 128 ) {
693 size += 6;
694 } else {
695 size += framesize ? 3 : 0;
696 }
697 return size;
698 }
699
700 int MachEpilogNode::reloc() const {
701 return 0; // a large enough number
702 }
703
704 const Pipeline * MachEpilogNode::pipeline() const {
705 return MachNode::pipeline_class();
706 }
707
708 int MachEpilogNode::safepoint_offset() const { return 0; }
709
710 //=============================================================================
711
712 enum RC { rc_bad, rc_int, rc_float, rc_xmm, rc_stack };
713 static enum RC rc_class( OptoReg::Name reg ) {
714
715 if( !OptoReg::is_valid(reg) ) return rc_bad;
716 if (OptoReg::is_stack(reg)) return rc_stack;
717
718 VMReg r = OptoReg::as_VMReg(reg);
719 if (r->is_Register()) return rc_int;
720 if (r->is_FloatRegister()) {
721 assert(UseSSE < 2, "shouldn't be used in SSE2+ mode");
722 return rc_float;
723 }
724 assert(r->is_XMMRegister(), "must be");
725 return rc_xmm;
726 }
727
728 static int impl_helper( CodeBuffer *cbuf, bool do_size, bool is_load, int offset, int reg,
729 int opcode, const char *op_str, int size, outputStream* st ) {
730 if( cbuf ) {
731 emit_opcode (*cbuf, opcode );
732 encode_RegMem(*cbuf, Matcher::_regEncode[reg], ESP_enc, 0x4, 0, offset, false);
733 #ifndef PRODUCT
734 } else if( !do_size ) {
735 if( size != 0 ) st->print("\n\t");
736 if( opcode == 0x8B || opcode == 0x89 ) { // MOV
737 if( is_load ) st->print("%s %s,[ESP + #%d]",op_str,Matcher::regName[reg],offset);
738 else st->print("%s [ESP + #%d],%s",op_str,offset,Matcher::regName[reg]);
739 } else { // FLD, FST, PUSH, POP
740 st->print("%s [ESP + #%d]",op_str,offset);
741 }
742 #endif
743 }
744 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
745 return size+3+offset_size;
746 }
747
748 // Helper for XMM registers. Extra opcode bits, limited syntax.
749 static int impl_x_helper( CodeBuffer *cbuf, bool do_size, bool is_load,
750 int offset, int reg_lo, int reg_hi, int size, outputStream* st ) {
751 if( cbuf ) {
752 if( reg_lo+1 == reg_hi ) { // double move?
753 if( is_load && !UseXmmLoadAndClearUpper )
754 emit_opcode(*cbuf, 0x66 ); // use 'movlpd' for load
755 else
756 emit_opcode(*cbuf, 0xF2 ); // use 'movsd' otherwise
757 } else {
758 emit_opcode(*cbuf, 0xF3 );
759 }
760 emit_opcode(*cbuf, 0x0F );
761 if( reg_lo+1 == reg_hi && is_load && !UseXmmLoadAndClearUpper )
762 emit_opcode(*cbuf, 0x12 ); // use 'movlpd' for load
763 else
764 emit_opcode(*cbuf, is_load ? 0x10 : 0x11 );
765 encode_RegMem(*cbuf, Matcher::_regEncode[reg_lo], ESP_enc, 0x4, 0, offset, false);
766 #ifndef PRODUCT
767 } else if( !do_size ) {
768 if( size != 0 ) st->print("\n\t");
769 if( reg_lo+1 == reg_hi ) { // double move?
770 if( is_load ) st->print("%s %s,[ESP + #%d]",
771 UseXmmLoadAndClearUpper ? "MOVSD " : "MOVLPD",
772 Matcher::regName[reg_lo], offset);
773 else st->print("MOVSD [ESP + #%d],%s",
774 offset, Matcher::regName[reg_lo]);
775 } else {
776 if( is_load ) st->print("MOVSS %s,[ESP + #%d]",
777 Matcher::regName[reg_lo], offset);
778 else st->print("MOVSS [ESP + #%d],%s",
779 offset, Matcher::regName[reg_lo]);
780 }
781 #endif
782 }
783 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
784 return size+5+offset_size;
785 }
786
787
788 static int impl_movx_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
789 int src_hi, int dst_hi, int size, outputStream* st ) {
790 if( UseXmmRegToRegMoveAll ) {//Use movaps,movapd to move between xmm registers
791 if( cbuf ) {
792 if( (src_lo+1 == src_hi && dst_lo+1 == dst_hi) ) {
793 emit_opcode(*cbuf, 0x66 );
794 }
795 emit_opcode(*cbuf, 0x0F );
796 emit_opcode(*cbuf, 0x28 );
797 emit_rm (*cbuf, 0x3, Matcher::_regEncode[dst_lo], Matcher::_regEncode[src_lo] );
798 #ifndef PRODUCT
799 } else if( !do_size ) {
800 if( size != 0 ) st->print("\n\t");
801 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double move?
802 st->print("MOVAPD %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
803 } else {
804 st->print("MOVAPS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
805 }
806 #endif
807 }
808 return size + ((src_lo+1 == src_hi && dst_lo+1 == dst_hi) ? 4 : 3);
809 } else {
810 if( cbuf ) {
811 emit_opcode(*cbuf, (src_lo+1 == src_hi && dst_lo+1 == dst_hi) ? 0xF2 : 0xF3 );
812 emit_opcode(*cbuf, 0x0F );
813 emit_opcode(*cbuf, 0x10 );
814 emit_rm (*cbuf, 0x3, Matcher::_regEncode[dst_lo], Matcher::_regEncode[src_lo] );
815 #ifndef PRODUCT
816 } else if( !do_size ) {
817 if( size != 0 ) st->print("\n\t");
818 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double move?
819 st->print("MOVSD %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
820 } else {
821 st->print("MOVSS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
822 }
823 #endif
824 }
825 return size+4;
826 }
827 }
828
829 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int size, outputStream* st ) {
830 if( cbuf ) {
831 emit_opcode(*cbuf, 0x8B );
832 emit_rm (*cbuf, 0x3, Matcher::_regEncode[dst], Matcher::_regEncode[src] );
833 #ifndef PRODUCT
834 } else if( !do_size ) {
835 if( size != 0 ) st->print("\n\t");
836 st->print("MOV %s,%s",Matcher::regName[dst],Matcher::regName[src]);
837 #endif
838 }
839 return size+2;
840 }
841
842 static int impl_fp_store_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int src_hi, int dst_lo, int dst_hi,
843 int offset, int size, outputStream* st ) {
844 if( src_lo != FPR1L_num ) { // Move value to top of FP stack, if not already there
845 if( cbuf ) {
846 emit_opcode( *cbuf, 0xD9 ); // FLD (i.e., push it)
847 emit_d8( *cbuf, 0xC0-1+Matcher::_regEncode[src_lo] );
848 #ifndef PRODUCT
849 } else if( !do_size ) {
850 if( size != 0 ) st->print("\n\t");
851 st->print("FLD %s",Matcher::regName[src_lo]);
852 #endif
853 }
854 size += 2;
855 }
856
857 int st_op = (src_lo != FPR1L_num) ? EBX_num /*store & pop*/ : EDX_num /*store no pop*/;
858 const char *op_str;
859 int op;
860 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double store?
861 op_str = (src_lo != FPR1L_num) ? "FSTP_D" : "FST_D ";
862 op = 0xDD;
863 } else { // 32-bit store
864 op_str = (src_lo != FPR1L_num) ? "FSTP_S" : "FST_S ";
865 op = 0xD9;
866 assert( !OptoReg::is_valid(src_hi) && !OptoReg::is_valid(dst_hi), "no non-adjacent float-stores" );
867 }
868
869 return impl_helper(cbuf,do_size,false,offset,st_op,op,op_str,size, st);
870 }
871
872 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream* st ) const {
873 // Get registers to move
874 OptoReg::Name src_second = ra_->get_reg_second(in(1));
875 OptoReg::Name src_first = ra_->get_reg_first(in(1));
876 OptoReg::Name dst_second = ra_->get_reg_second(this );
877 OptoReg::Name dst_first = ra_->get_reg_first(this );
878
879 enum RC src_second_rc = rc_class(src_second);
880 enum RC src_first_rc = rc_class(src_first);
881 enum RC dst_second_rc = rc_class(dst_second);
882 enum RC dst_first_rc = rc_class(dst_first);
883
884 assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" );
885
886 // Generate spill code!
887 int size = 0;
888
889 if( src_first == dst_first && src_second == dst_second )
890 return size; // Self copy, no move
891
892 // --------------------------------------
893 // Check for mem-mem move. push/pop to move.
894 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
895 if( src_second == dst_first ) { // overlapping stack copy ranges
896 assert( src_second_rc == rc_stack && dst_second_rc == rc_stack, "we only expect a stk-stk copy here" );
897 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH ",size, st);
898 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP ",size, st);
899 src_second_rc = dst_second_rc = rc_bad; // flag as already moved the second bits
900 }
901 // move low bits
902 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),ESI_num,0xFF,"PUSH ",size, st);
903 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),EAX_num,0x8F,"POP ",size, st);
904 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) { // mov second bits
905 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH ",size, st);
906 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP ",size, st);
907 }
908 return size;
909 }
910
911 // --------------------------------------
912 // Check for integer reg-reg copy
913 if( src_first_rc == rc_int && dst_first_rc == rc_int )
914 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,size, st);
915
916 // Check for integer store
917 if( src_first_rc == rc_int && dst_first_rc == rc_stack )
918 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first,0x89,"MOV ",size, st);
919
920 // Check for integer load
921 if( dst_first_rc == rc_int && src_first_rc == rc_stack )
922 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first,0x8B,"MOV ",size, st);
923
924 // --------------------------------------
925 // Check for float reg-reg copy
926 if( src_first_rc == rc_float && dst_first_rc == rc_float ) {
927 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) ||
928 (src_first+1 == src_second && dst_first+1 == dst_second), "no non-adjacent float-moves" );
929 if( cbuf ) {
930
931 // Note the mucking with the register encode to compensate for the 0/1
932 // indexing issue mentioned in a comment in the reg_def sections
933 // for FPR registers many lines above here.
934
935 if( src_first != FPR1L_num ) {
936 emit_opcode (*cbuf, 0xD9 ); // FLD ST(i)
937 emit_d8 (*cbuf, 0xC0+Matcher::_regEncode[src_first]-1 );
938 emit_opcode (*cbuf, 0xDD ); // FSTP ST(i)
939 emit_d8 (*cbuf, 0xD8+Matcher::_regEncode[dst_first] );
940 } else {
941 emit_opcode (*cbuf, 0xDD ); // FST ST(i)
942 emit_d8 (*cbuf, 0xD0+Matcher::_regEncode[dst_first]-1 );
943 }
944 #ifndef PRODUCT
945 } else if( !do_size ) {
946 if( size != 0 ) st->print("\n\t");
947 if( src_first != FPR1L_num ) st->print("FLD %s\n\tFSTP %s",Matcher::regName[src_first],Matcher::regName[dst_first]);
948 else st->print( "FST %s", Matcher::regName[dst_first]);
949 #endif
950 }
951 return size + ((src_first != FPR1L_num) ? 2+2 : 2);
952 }
953
954 // Check for float store
955 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) {
956 return impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,ra_->reg2offset(dst_first),size, st);
957 }
958
959 // Check for float load
960 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) {
961 int offset = ra_->reg2offset(src_first);
962 const char *op_str;
963 int op;
964 if( src_first+1 == src_second && dst_first+1 == dst_second ) { // double load?
965 op_str = "FLD_D";
966 op = 0xDD;
967 } else { // 32-bit load
968 op_str = "FLD_S";
969 op = 0xD9;
970 assert( src_second_rc == rc_bad && dst_second_rc == rc_bad, "no non-adjacent float-loads" );
971 }
972 if( cbuf ) {
973 emit_opcode (*cbuf, op );
974 encode_RegMem(*cbuf, 0x0, ESP_enc, 0x4, 0, offset, false);
975 emit_opcode (*cbuf, 0xDD ); // FSTP ST(i)
976 emit_d8 (*cbuf, 0xD8+Matcher::_regEncode[dst_first] );
977 #ifndef PRODUCT
978 } else if( !do_size ) {
979 if( size != 0 ) st->print("\n\t");
980 st->print("%s ST,[ESP + #%d]\n\tFSTP %s",op_str, offset,Matcher::regName[dst_first]);
981 #endif
982 }
983 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
984 return size + 3+offset_size+2;
985 }
986
987 // Check for xmm reg-reg copy
988 if( src_first_rc == rc_xmm && dst_first_rc == rc_xmm ) {
989 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) ||
990 (src_first+1 == src_second && dst_first+1 == dst_second),
991 "no non-adjacent float-moves" );
992 return impl_movx_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st);
993 }
994
995 // Check for xmm store
996 if( src_first_rc == rc_xmm && dst_first_rc == rc_stack ) {
997 return impl_x_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first, src_second, size, st);
998 }
999
1000 // Check for float xmm load
1001 if( dst_first_rc == rc_xmm && src_first_rc == rc_stack ) {
1002 return impl_x_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first, dst_second, size, st);
1003 }
1004
1005 // Copy from float reg to xmm reg
1006 if( dst_first_rc == rc_xmm && src_first_rc == rc_float ) {
1007 // copy to the top of stack from floating point reg
1008 // and use LEA to preserve flags
1009 if( cbuf ) {
1010 emit_opcode(*cbuf,0x8D); // LEA ESP,[ESP-8]
1011 emit_rm(*cbuf, 0x1, ESP_enc, 0x04);
1012 emit_rm(*cbuf, 0x0, 0x04, ESP_enc);
1013 emit_d8(*cbuf,0xF8);
1014 #ifndef PRODUCT
1015 } else if( !do_size ) {
1016 if( size != 0 ) st->print("\n\t");
1017 st->print("LEA ESP,[ESP-8]");
1018 #endif
1019 }
1020 size += 4;
1021
1022 size = impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,0,size, st);
1023
1024 // Copy from the temp memory to the xmm reg.
1025 size = impl_x_helper(cbuf,do_size,true ,0,dst_first, dst_second, size, st);
1026
1027 if( cbuf ) {
1028 emit_opcode(*cbuf,0x8D); // LEA ESP,[ESP+8]
1029 emit_rm(*cbuf, 0x1, ESP_enc, 0x04);
1030 emit_rm(*cbuf, 0x0, 0x04, ESP_enc);
1031 emit_d8(*cbuf,0x08);
1032 #ifndef PRODUCT
1033 } else if( !do_size ) {
1034 if( size != 0 ) st->print("\n\t");
1035 st->print("LEA ESP,[ESP+8]");
1036 #endif
1037 }
1038 size += 4;
1039 return size;
1040 }
1041
1042 assert( size > 0, "missed a case" );
1043
1044 // --------------------------------------------------------------------
1045 // Check for second bits still needing moving.
1046 if( src_second == dst_second )
1047 return size; // Self copy; no move
1048 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" );
1049
1050 // Check for second word int-int move
1051 if( src_second_rc == rc_int && dst_second_rc == rc_int )
1052 return impl_mov_helper(cbuf,do_size,src_second,dst_second,size, st);
1053
1054 // Check for second word integer store
1055 if( src_second_rc == rc_int && dst_second_rc == rc_stack )
1056 return impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),src_second,0x89,"MOV ",size, st);
1057
1058 // Check for second word integer load
1059 if( dst_second_rc == rc_int && src_second_rc == rc_stack )
1060 return impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),dst_second,0x8B,"MOV ",size, st);
1061
1062
1063 Unimplemented();
1064 }
1065
1066 #ifndef PRODUCT
1067 void MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1068 implementation( NULL, ra_, false, st );
1069 }
1070 #endif
1071
1072 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1073 implementation( &cbuf, ra_, false, NULL );
1074 }
1075
1076 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1077 return implementation( NULL, ra_, true, NULL );
1078 }
1079
1080 //=============================================================================
1081 #ifndef PRODUCT
1082 void MachNopNode::format( PhaseRegAlloc *, outputStream* st ) const {
1083 st->print("NOP \t# %d bytes pad for loops and calls", _count);
1084 }
1085 #endif
1086
1087 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc * ) const {
1088 MacroAssembler _masm(&cbuf);
1089 __ nop(_count);
1090 }
1091
1092 uint MachNopNode::size(PhaseRegAlloc *) const {
1093 return _count;
1094 }
1095
1096
1097 //=============================================================================
1098 #ifndef PRODUCT
1099 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1100 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1101 int reg = ra_->get_reg_first(this);
1102 st->print("LEA %s,[ESP + #%d]",Matcher::regName[reg],offset);
1103 }
1104 #endif
1105
1106 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1107 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1108 int reg = ra_->get_encode(this);
1109 if( offset >= 128 ) {
1110 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1111 emit_rm(cbuf, 0x2, reg, 0x04);
1112 emit_rm(cbuf, 0x0, 0x04, ESP_enc);
1113 emit_d32(cbuf, offset);
1114 }
1115 else {
1116 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1117 emit_rm(cbuf, 0x1, reg, 0x04);
1118 emit_rm(cbuf, 0x0, 0x04, ESP_enc);
1119 emit_d8(cbuf, offset);
1120 }
1121 }
1122
1123 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1124 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1125 if( offset >= 128 ) {
1126 return 7;
1127 }
1128 else {
1129 return 4;
1130 }
1131 }
1132
1133 //=============================================================================
1134
1135 // emit call stub, compiled java to interpreter
1136 void emit_java_to_interp(CodeBuffer &cbuf ) {
1137 // Stub is fixed up when the corresponding call is converted from calling
1138 // compiled code to calling interpreted code.
1139 // mov rbx,0
1140 // jmp -1
1141
1142 address mark = cbuf.inst_mark(); // get mark within main instrs section
1143
1144 // Note that the code buffer's inst_mark is always relative to insts.
1145 // That's why we must use the macroassembler to generate a stub.
1146 MacroAssembler _masm(&cbuf);
1147
1148 address base =
1149 __ start_a_stub(Compile::MAX_stubs_size);
1150 if (base == NULL) return; // CodeBuffer::expand failed
1151 // static stub relocation stores the instruction address of the call
1152 __ relocate(static_stub_Relocation::spec(mark), RELOC_IMM32);
1153 // static stub relocation also tags the methodOop in the code-stream.
1154 __ movoop(rbx, (jobject)NULL); // method is zapped till fixup time
1155 // This is recognized as unresolved by relocs/nativeInst/ic code
1156 __ jump(RuntimeAddress(__ pc()));
1157
1158 __ end_a_stub();
1159 // Update current stubs pointer and restore code_end.
1160 }
1161 // size of call stub, compiled java to interpretor
1162 uint size_java_to_interp() {
1163 return 10; // movl; jmp
1164 }
1165 // relocation entries for call stub, compiled java to interpretor
1166 uint reloc_java_to_interp() {
1167 return 4; // 3 in emit_java_to_interp + 1 in Java_Static_Call
1168 }
1169
1170 //=============================================================================
1171 #ifndef PRODUCT
1172 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1173 st->print_cr( "CMP EAX,[ECX+4]\t# Inline cache check");
1174 st->print_cr("\tJNE SharedRuntime::handle_ic_miss_stub");
1175 st->print_cr("\tNOP");
1176 st->print_cr("\tNOP");
1177 if( !OptoBreakpoint )
1178 st->print_cr("\tNOP");
1179 }
1180 #endif
1181
1182 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1183 MacroAssembler masm(&cbuf);
1184 #ifdef ASSERT
1185 uint code_size = cbuf.code_size();
1186 #endif
1187 masm.cmpptr(rax, Address(rcx, oopDesc::klass_offset_in_bytes()));
1188 masm.jump_cc(Assembler::notEqual,
1189 RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1190 /* WARNING these NOPs are critical so that verified entry point is properly
1191 aligned for patching by NativeJump::patch_verified_entry() */
1192 int nops_cnt = 2;
1193 if( !OptoBreakpoint ) // Leave space for int3
1194 nops_cnt += 1;
1195 masm.nop(nops_cnt);
1196
1197 assert(cbuf.code_size() - code_size == size(ra_), "checking code size of inline cache node");
1198 }
1199
1200 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
1201 return OptoBreakpoint ? 11 : 12;
1202 }
1203
1204
1205 //=============================================================================
1206 uint size_exception_handler() {
1207 // NativeCall instruction size is the same as NativeJump.
1208 // exception handler starts out as jump and can be patched to
1209 // a call be deoptimization. (4932387)
1210 // Note that this value is also credited (in output.cpp) to
1211 // the size of the code section.
1212 return NativeJump::instruction_size;
1213 }
1214
1215 // Emit exception handler code. Stuff framesize into a register
1216 // and call a VM stub routine.
1217 int emit_exception_handler(CodeBuffer& cbuf) {
1218
1219 // Note that the code buffer's inst_mark is always relative to insts.
1220 // That's why we must use the macroassembler to generate a handler.
1221 MacroAssembler _masm(&cbuf);
1222 address base =
1223 __ start_a_stub(size_exception_handler());
1224 if (base == NULL) return 0; // CodeBuffer::expand failed
1225 int offset = __ offset();
1226 __ jump(RuntimeAddress(OptoRuntime::exception_blob()->instructions_begin()));
1227 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
1228 __ end_a_stub();
1229 return offset;
1230 }
1231
1232 uint size_deopt_handler() {
1233 // NativeCall instruction size is the same as NativeJump.
1234 // exception handler starts out as jump and can be patched to
1235 // a call be deoptimization. (4932387)
1236 // Note that this value is also credited (in output.cpp) to
1237 // the size of the code section.
1238 return 5 + NativeJump::instruction_size; // pushl(); jmp;
1239 }
1240
1241 // Emit deopt handler code.
1242 int emit_deopt_handler(CodeBuffer& cbuf) {
1243
1244 // Note that the code buffer's inst_mark is always relative to insts.
1245 // That's why we must use the macroassembler to generate a handler.
1246 MacroAssembler _masm(&cbuf);
1247 address base =
1248 __ start_a_stub(size_exception_handler());
1249 if (base == NULL) return 0; // CodeBuffer::expand failed
1250 int offset = __ offset();
1251 InternalAddress here(__ pc());
1252 __ pushptr(here.addr());
1253
1254 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
1255 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
1256 __ end_a_stub();
1257 return offset;
1258 }
1259
1260
1261 static void emit_double_constant(CodeBuffer& cbuf, double x) {
1262 int mark = cbuf.insts()->mark_off();
1263 MacroAssembler _masm(&cbuf);
1264 address double_address = __ double_constant(x);
1265 cbuf.insts()->set_mark_off(mark); // preserve mark across masm shift
1266 emit_d32_reloc(cbuf,
1267 (int)double_address,
1268 internal_word_Relocation::spec(double_address),
1269 RELOC_DISP32);
1270 }
1271
1272 static void emit_float_constant(CodeBuffer& cbuf, float x) {
1273 int mark = cbuf.insts()->mark_off();
1274 MacroAssembler _masm(&cbuf);
1275 address float_address = __ float_constant(x);
1276 cbuf.insts()->set_mark_off(mark); // preserve mark across masm shift
1277 emit_d32_reloc(cbuf,
1278 (int)float_address,
1279 internal_word_Relocation::spec(float_address),
1280 RELOC_DISP32);
1281 }
1282
1283
1284 const bool Matcher::match_rule_supported(int opcode) {
1285 if (!has_match_rule(opcode))
1286 return false;
1287
1288 return true; // Per default match rules are supported.
1289 }
1290
1291 int Matcher::regnum_to_fpu_offset(int regnum) {
1292 return regnum - 32; // The FP registers are in the second chunk
1293 }
1294
1295 bool is_positive_zero_float(jfloat f) {
1296 return jint_cast(f) == jint_cast(0.0F);
1297 }
1298
1299 bool is_positive_one_float(jfloat f) {
1300 return jint_cast(f) == jint_cast(1.0F);
1301 }
1302
1303 bool is_positive_zero_double(jdouble d) {
1304 return jlong_cast(d) == jlong_cast(0.0);
1305 }
1306
1307 bool is_positive_one_double(jdouble d) {
1308 return jlong_cast(d) == jlong_cast(1.0);
1309 }
1310
1311 // This is UltraSparc specific, true just means we have fast l2f conversion
1312 const bool Matcher::convL2FSupported(void) {
1313 return true;
1314 }
1315
1316 // Vector width in bytes
1317 const uint Matcher::vector_width_in_bytes(void) {
1318 return UseSSE >= 2 ? 8 : 0;
1319 }
1320
1321 // Vector ideal reg
1322 const uint Matcher::vector_ideal_reg(void) {
1323 return Op_RegD;
1324 }
1325
1326 // Is this branch offset short enough that a short branch can be used?
1327 //
1328 // NOTE: If the platform does not provide any short branch variants, then
1329 // this method should return false for offset 0.
1330 bool Matcher::is_short_branch_offset(int rule, int offset) {
1331 // the short version of jmpConUCF2 contains multiple branches,
1332 // making the reach slightly less
1333 if (rule == jmpConUCF2_rule)
1334 return (-126 <= offset && offset <= 125);
1335 return (-128 <= offset && offset <= 127);
1336 }
1337
1338 const bool Matcher::isSimpleConstant64(jlong value) {
1339 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1340 return false;
1341 }
1342
1343 // The ecx parameter to rep stos for the ClearArray node is in dwords.
1344 const bool Matcher::init_array_count_is_in_bytes = false;
1345
1346 // Threshold size for cleararray.
1347 const int Matcher::init_array_short_size = 8 * BytesPerLong;
1348
1349 // Should the Matcher clone shifts on addressing modes, expecting them to
1350 // be subsumed into complex addressing expressions or compute them into
1351 // registers? True for Intel but false for most RISCs
1352 const bool Matcher::clone_shift_expressions = true;
1353
1354 // Is it better to copy float constants, or load them directly from memory?
1355 // Intel can load a float constant from a direct address, requiring no
1356 // extra registers. Most RISCs will have to materialize an address into a
1357 // register first, so they would do better to copy the constant from stack.
1358 const bool Matcher::rematerialize_float_constants = true;
1359
1360 // If CPU can load and store mis-aligned doubles directly then no fixup is
1361 // needed. Else we split the double into 2 integer pieces and move it
1362 // piece-by-piece. Only happens when passing doubles into C code as the
1363 // Java calling convention forces doubles to be aligned.
1364 const bool Matcher::misaligned_doubles_ok = true;
1365
1366
1367 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
1368 // Get the memory operand from the node
1369 uint numopnds = node->num_opnds(); // Virtual call for number of operands
1370 uint skipped = node->oper_input_base(); // Sum of leaves skipped so far
1371 assert( idx >= skipped, "idx too low in pd_implicit_null_fixup" );
1372 uint opcnt = 1; // First operand
1373 uint num_edges = node->_opnds[1]->num_edges(); // leaves for first operand
1374 while( idx >= skipped+num_edges ) {
1375 skipped += num_edges;
1376 opcnt++; // Bump operand count
1377 assert( opcnt < numopnds, "Accessing non-existent operand" );
1378 num_edges = node->_opnds[opcnt]->num_edges(); // leaves for next operand
1379 }
1380
1381 MachOper *memory = node->_opnds[opcnt];
1382 MachOper *new_memory = NULL;
1383 switch (memory->opcode()) {
1384 case DIRECT:
1385 case INDOFFSET32X:
1386 // No transformation necessary.
1387 return;
1388 case INDIRECT:
1389 new_memory = new (C) indirect_win95_safeOper( );
1390 break;
1391 case INDOFFSET8:
1392 new_memory = new (C) indOffset8_win95_safeOper(memory->disp(NULL, NULL, 0));
1393 break;
1394 case INDOFFSET32:
1395 new_memory = new (C) indOffset32_win95_safeOper(memory->disp(NULL, NULL, 0));
1396 break;
1397 case INDINDEXOFFSET:
1398 new_memory = new (C) indIndexOffset_win95_safeOper(memory->disp(NULL, NULL, 0));
1399 break;
1400 case INDINDEXSCALE:
1401 new_memory = new (C) indIndexScale_win95_safeOper(memory->scale());
1402 break;
1403 case INDINDEXSCALEOFFSET:
1404 new_memory = new (C) indIndexScaleOffset_win95_safeOper(memory->scale(), memory->disp(NULL, NULL, 0));
1405 break;
1406 case LOAD_LONG_INDIRECT:
1407 case LOAD_LONG_INDOFFSET32:
1408 // Does not use EBP as address register, use { EDX, EBX, EDI, ESI}
1409 return;
1410 default:
1411 assert(false, "unexpected memory operand in pd_implicit_null_fixup()");
1412 return;
1413 }
1414 node->_opnds[opcnt] = new_memory;
1415 }
1416
1417 // Advertise here if the CPU requires explicit rounding operations
1418 // to implement the UseStrictFP mode.
1419 const bool Matcher::strict_fp_requires_explicit_rounding = true;
1420
1421 // Do floats take an entire double register or just half?
1422 const bool Matcher::float_in_double = true;
1423 // Do ints take an entire long register or just half?
1424 const bool Matcher::int_in_long = false;
1425
1426 // Return whether or not this register is ever used as an argument. This
1427 // function is used on startup to build the trampoline stubs in generateOptoStub.
1428 // Registers not mentioned will be killed by the VM call in the trampoline, and
1429 // arguments in those registers not be available to the callee.
1430 bool Matcher::can_be_java_arg( int reg ) {
1431 if( reg == ECX_num || reg == EDX_num ) return true;
1432 if( (reg == XMM0a_num || reg == XMM1a_num) && UseSSE>=1 ) return true;
1433 if( (reg == XMM0b_num || reg == XMM1b_num) && UseSSE>=2 ) return true;
1434 return false;
1435 }
1436
1437 bool Matcher::is_spillable_arg( int reg ) {
1438 return can_be_java_arg(reg);
1439 }
1440
1441 // Register for DIVI projection of divmodI
1442 RegMask Matcher::divI_proj_mask() {
1443 return EAX_REG_mask;
1444 }
1445
1446 // Register for MODI projection of divmodI
1447 RegMask Matcher::modI_proj_mask() {
1448 return EDX_REG_mask;
1449 }
1450
1451 // Register for DIVL projection of divmodL
1452 RegMask Matcher::divL_proj_mask() {
1453 ShouldNotReachHere();
1454 return RegMask();
1455 }
1456
1457 // Register for MODL projection of divmodL
1458 RegMask Matcher::modL_proj_mask() {
1459 ShouldNotReachHere();
1460 return RegMask();
1461 }
1462
1463 %}
1464
1465 //----------ENCODING BLOCK-----------------------------------------------------
1466 // This block specifies the encoding classes used by the compiler to output
1467 // byte streams. Encoding classes generate functions which are called by
1468 // Machine Instruction Nodes in order to generate the bit encoding of the
1469 // instruction. Operands specify their base encoding interface with the
1470 // interface keyword. There are currently supported four interfaces,
1471 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
1472 // operand to generate a function which returns its register number when
1473 // queried. CONST_INTER causes an operand to generate a function which
1474 // returns the value of the constant when queried. MEMORY_INTER causes an
1475 // operand to generate four functions which return the Base Register, the
1476 // Index Register, the Scale Value, and the Offset Value of the operand when
1477 // queried. COND_INTER causes an operand to generate six functions which
1478 // return the encoding code (ie - encoding bits for the instruction)
1479 // associated with each basic boolean condition for a conditional instruction.
1480 // Instructions specify two basic values for encoding. They use the
1481 // ins_encode keyword to specify their encoding class (which must be one of
1482 // the class names specified in the encoding block), and they use the
1483 // opcode keyword to specify, in order, their primary, secondary, and
1484 // tertiary opcode. Only the opcode sections which a particular instruction
1485 // needs for encoding need to be specified.
1486 encode %{
1487 // Build emit functions for each basic byte or larger field in the intel
1488 // encoding scheme (opcode, rm, sib, immediate), and call them from C++
1489 // code in the enc_class source block. Emit functions will live in the
1490 // main source block for now. In future, we can generalize this by
1491 // adding a syntax that specifies the sizes of fields in an order,
1492 // so that the adlc can build the emit functions automagically
1493
1494 // Emit primary opcode
1495 enc_class OpcP %{
1496 emit_opcode(cbuf, $primary);
1497 %}
1498
1499 // Emit secondary opcode
1500 enc_class OpcS %{
1501 emit_opcode(cbuf, $secondary);
1502 %}
1503
1504 // Emit opcode directly
1505 enc_class Opcode(immI d8) %{
1506 emit_opcode(cbuf, $d8$$constant);
1507 %}
1508
1509 enc_class SizePrefix %{
1510 emit_opcode(cbuf,0x66);
1511 %}
1512
1513 enc_class RegReg (eRegI dst, eRegI src) %{ // RegReg(Many)
1514 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1515 %}
1516
1517 enc_class OpcRegReg (immI opcode, eRegI dst, eRegI src) %{ // OpcRegReg(Many)
1518 emit_opcode(cbuf,$opcode$$constant);
1519 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1520 %}
1521
1522 enc_class mov_r32_imm0( eRegI dst ) %{
1523 emit_opcode( cbuf, 0xB8 + $dst$$reg ); // 0xB8+ rd -- MOV r32 ,imm32
1524 emit_d32 ( cbuf, 0x0 ); // imm32==0x0
1525 %}
1526
1527 enc_class cdq_enc %{
1528 // Full implementation of Java idiv and irem; checks for
1529 // special case as described in JVM spec., p.243 & p.271.
1530 //
1531 // normal case special case
1532 //
1533 // input : rax,: dividend min_int
1534 // reg: divisor -1
1535 //
1536 // output: rax,: quotient (= rax, idiv reg) min_int
1537 // rdx: remainder (= rax, irem reg) 0
1538 //
1539 // Code sequnce:
1540 //
1541 // 81 F8 00 00 00 80 cmp rax,80000000h
1542 // 0F 85 0B 00 00 00 jne normal_case
1543 // 33 D2 xor rdx,edx
1544 // 83 F9 FF cmp rcx,0FFh
1545 // 0F 84 03 00 00 00 je done
1546 // normal_case:
1547 // 99 cdq
1548 // F7 F9 idiv rax,ecx
1549 // done:
1550 //
1551 emit_opcode(cbuf,0x81); emit_d8(cbuf,0xF8);
1552 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00);
1553 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x80); // cmp rax,80000000h
1554 emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x85);
1555 emit_opcode(cbuf,0x0B); emit_d8(cbuf,0x00);
1556 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); // jne normal_case
1557 emit_opcode(cbuf,0x33); emit_d8(cbuf,0xD2); // xor rdx,edx
1558 emit_opcode(cbuf,0x83); emit_d8(cbuf,0xF9); emit_d8(cbuf,0xFF); // cmp rcx,0FFh
1559 emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x84);
1560 emit_opcode(cbuf,0x03); emit_d8(cbuf,0x00);
1561 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); // je done
1562 // normal_case:
1563 emit_opcode(cbuf,0x99); // cdq
1564 // idiv (note: must be emitted by the user of this rule)
1565 // normal:
1566 %}
1567
1568 // Dense encoding for older common ops
1569 enc_class Opc_plus(immI opcode, eRegI reg) %{
1570 emit_opcode(cbuf, $opcode$$constant + $reg$$reg);
1571 %}
1572
1573
1574 // Opcde enc_class for 8/32 bit immediate instructions with sign-extension
1575 enc_class OpcSE (immI imm) %{ // Emit primary opcode and set sign-extend bit
1576 // Check for 8-bit immediate, and set sign extend bit in opcode
1577 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1578 emit_opcode(cbuf, $primary | 0x02);
1579 }
1580 else { // If 32-bit immediate
1581 emit_opcode(cbuf, $primary);
1582 }
1583 %}
1584
1585 enc_class OpcSErm (eRegI dst, immI imm) %{ // OpcSEr/m
1586 // Emit primary opcode and set sign-extend bit
1587 // Check for 8-bit immediate, and set sign extend bit in opcode
1588 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1589 emit_opcode(cbuf, $primary | 0x02); }
1590 else { // If 32-bit immediate
1591 emit_opcode(cbuf, $primary);
1592 }
1593 // Emit r/m byte with secondary opcode, after primary opcode.
1594 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1595 %}
1596
1597 enc_class Con8or32 (immI imm) %{ // Con8or32(storeImmI), 8 or 32 bits
1598 // Check for 8-bit immediate, and set sign extend bit in opcode
1599 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1600 $$$emit8$imm$$constant;
1601 }
1602 else { // If 32-bit immediate
1603 // Output immediate
1604 $$$emit32$imm$$constant;
1605 }
1606 %}
1607
1608 enc_class Long_OpcSErm_Lo(eRegL dst, immL imm) %{
1609 // Emit primary opcode and set sign-extend bit
1610 // Check for 8-bit immediate, and set sign extend bit in opcode
1611 int con = (int)$imm$$constant; // Throw away top bits
1612 emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary);
1613 // Emit r/m byte with secondary opcode, after primary opcode.
1614 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1615 if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con);
1616 else emit_d32(cbuf,con);
1617 %}
1618
1619 enc_class Long_OpcSErm_Hi(eRegL dst, immL imm) %{
1620 // Emit primary opcode and set sign-extend bit
1621 // Check for 8-bit immediate, and set sign extend bit in opcode
1622 int con = (int)($imm$$constant >> 32); // Throw away bottom bits
1623 emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary);
1624 // Emit r/m byte with tertiary opcode, after primary opcode.
1625 emit_rm(cbuf, 0x3, $tertiary, HIGH_FROM_LOW($dst$$reg));
1626 if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con);
1627 else emit_d32(cbuf,con);
1628 %}
1629
1630 enc_class Lbl (label labl) %{ // JMP, CALL
1631 Label *l = $labl$$label;
1632 emit_d32(cbuf, l ? (l->loc_pos() - (cbuf.code_size()+4)) : 0);
1633 %}
1634
1635 enc_class LblShort (label labl) %{ // JMP, CALL
1636 Label *l = $labl$$label;
1637 int disp = l ? (l->loc_pos() - (cbuf.code_size()+1)) : 0;
1638 assert(-128 <= disp && disp <= 127, "Displacement too large for short jmp");
1639 emit_d8(cbuf, disp);
1640 %}
1641
1642 enc_class OpcSReg (eRegI dst) %{ // BSWAP
1643 emit_cc(cbuf, $secondary, $dst$$reg );
1644 %}
1645
1646 enc_class bswap_long_bytes(eRegL dst) %{ // BSWAP
1647 int destlo = $dst$$reg;
1648 int desthi = HIGH_FROM_LOW(destlo);
1649 // bswap lo
1650 emit_opcode(cbuf, 0x0F);
1651 emit_cc(cbuf, 0xC8, destlo);
1652 // bswap hi
1653 emit_opcode(cbuf, 0x0F);
1654 emit_cc(cbuf, 0xC8, desthi);
1655 // xchg lo and hi
1656 emit_opcode(cbuf, 0x87);
1657 emit_rm(cbuf, 0x3, destlo, desthi);
1658 %}
1659
1660 enc_class RegOpc (eRegI div) %{ // IDIV, IMOD, JMP indirect, ...
1661 emit_rm(cbuf, 0x3, $secondary, $div$$reg );
1662 %}
1663
1664 enc_class Jcc (cmpOp cop, label labl) %{ // JCC
1665 Label *l = $labl$$label;
1666 $$$emit8$primary;
1667 emit_cc(cbuf, $secondary, $cop$$cmpcode);
1668 emit_d32(cbuf, l ? (l->loc_pos() - (cbuf.code_size()+4)) : 0);
1669 %}
1670
1671 enc_class JccShort (cmpOp cop, label labl) %{ // JCC
1672 Label *l = $labl$$label;
1673 emit_cc(cbuf, $primary, $cop$$cmpcode);
1674 int disp = l ? (l->loc_pos() - (cbuf.code_size()+1)) : 0;
1675 assert(-128 <= disp && disp <= 127, "Displacement too large for short jmp");
1676 emit_d8(cbuf, disp);
1677 %}
1678
1679 enc_class enc_cmov(cmpOp cop ) %{ // CMOV
1680 $$$emit8$primary;
1681 emit_cc(cbuf, $secondary, $cop$$cmpcode);
1682 %}
1683
1684 enc_class enc_cmov_d(cmpOp cop, regD src ) %{ // CMOV
1685 int op = 0xDA00 + $cop$$cmpcode + ($src$$reg-1);
1686 emit_d8(cbuf, op >> 8 );
1687 emit_d8(cbuf, op & 255);
1688 %}
1689
1690 // emulate a CMOV with a conditional branch around a MOV
1691 enc_class enc_cmov_branch( cmpOp cop, immI brOffs ) %{ // CMOV
1692 // Invert sense of branch from sense of CMOV
1693 emit_cc( cbuf, 0x70, ($cop$$cmpcode^1) );
1694 emit_d8( cbuf, $brOffs$$constant );
1695 %}
1696
1697 enc_class enc_PartialSubtypeCheck( ) %{
1698 Register Redi = as_Register(EDI_enc); // result register
1699 Register Reax = as_Register(EAX_enc); // super class
1700 Register Recx = as_Register(ECX_enc); // killed
1701 Register Resi = as_Register(ESI_enc); // sub class
1702 Label miss;
1703
1704 MacroAssembler _masm(&cbuf);
1705 __ check_klass_subtype_slow_path(Resi, Reax, Recx, Redi,
1706 NULL, &miss,
1707 /*set_cond_codes:*/ true);
1708 if ($primary) {
1709 __ xorptr(Redi, Redi);
1710 }
1711 __ bind(miss);
1712 %}
1713
1714 enc_class FFree_Float_Stack_All %{ // Free_Float_Stack_All
1715 MacroAssembler masm(&cbuf);
1716 int start = masm.offset();
1717 if (UseSSE >= 2) {
1718 if (VerifyFPU) {
1719 masm.verify_FPU(0, "must be empty in SSE2+ mode");
1720 }
1721 } else {
1722 // External c_calling_convention expects the FPU stack to be 'clean'.
1723 // Compiled code leaves it dirty. Do cleanup now.
1724 masm.empty_FPU_stack();
1725 }
1726 if (sizeof_FFree_Float_Stack_All == -1) {
1727 sizeof_FFree_Float_Stack_All = masm.offset() - start;
1728 } else {
1729 assert(masm.offset() - start == sizeof_FFree_Float_Stack_All, "wrong size");
1730 }
1731 %}
1732
1733 enc_class Verify_FPU_For_Leaf %{
1734 if( VerifyFPU ) {
1735 MacroAssembler masm(&cbuf);
1736 masm.verify_FPU( -3, "Returning from Runtime Leaf call");
1737 }
1738 %}
1739
1740 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime, Java_To_Runtime_Leaf
1741 // This is the instruction starting address for relocation info.
1742 cbuf.set_inst_mark();
1743 $$$emit8$primary;
1744 // CALL directly to the runtime
1745 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.code_end()) - 4),
1746 runtime_call_Relocation::spec(), RELOC_IMM32 );
1747
1748 if (UseSSE >= 2) {
1749 MacroAssembler _masm(&cbuf);
1750 BasicType rt = tf()->return_type();
1751
1752 if ((rt == T_FLOAT || rt == T_DOUBLE) && !return_value_is_used()) {
1753 // A C runtime call where the return value is unused. In SSE2+
1754 // mode the result needs to be removed from the FPU stack. It's
1755 // likely that this function call could be removed by the
1756 // optimizer if the C function is a pure function.
1757 __ ffree(0);
1758 } else if (rt == T_FLOAT) {
1759 __ lea(rsp, Address(rsp, -4));
1760 __ fstp_s(Address(rsp, 0));
1761 __ movflt(xmm0, Address(rsp, 0));
1762 __ lea(rsp, Address(rsp, 4));
1763 } else if (rt == T_DOUBLE) {
1764 __ lea(rsp, Address(rsp, -8));
1765 __ fstp_d(Address(rsp, 0));
1766 __ movdbl(xmm0, Address(rsp, 0));
1767 __ lea(rsp, Address(rsp, 8));
1768 }
1769 }
1770 %}
1771
1772
1773 enc_class pre_call_FPU %{
1774 // If method sets FPU control word restore it here
1775 if( Compile::current()->in_24_bit_fp_mode() ) {
1776 MacroAssembler masm(&cbuf);
1777 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
1778 }
1779 %}
1780
1781 enc_class post_call_FPU %{
1782 // If method sets FPU control word do it here also
1783 if( Compile::current()->in_24_bit_fp_mode() ) {
1784 MacroAssembler masm(&cbuf);
1785 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
1786 }
1787 %}
1788
1789 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL
1790 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
1791 // who we intended to call.
1792 cbuf.set_inst_mark();
1793 $$$emit8$primary;
1794 if ( !_method ) {
1795 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.code_end()) - 4),
1796 runtime_call_Relocation::spec(), RELOC_IMM32 );
1797 } else if(_optimized_virtual) {
1798 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.code_end()) - 4),
1799 opt_virtual_call_Relocation::spec(), RELOC_IMM32 );
1800 } else {
1801 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.code_end()) - 4),
1802 static_call_Relocation::spec(), RELOC_IMM32 );
1803 }
1804 if( _method ) { // Emit stub for static call
1805 emit_java_to_interp(cbuf);
1806 }
1807 %}
1808
1809 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL
1810 // !!!!!
1811 // Generate "Mov EAX,0x00", placeholder instruction to load oop-info
1812 // emit_call_dynamic_prologue( cbuf );
1813 cbuf.set_inst_mark();
1814 emit_opcode(cbuf, 0xB8 + EAX_enc); // mov EAX,-1
1815 emit_d32_reloc(cbuf, (int)Universe::non_oop_word(), oop_Relocation::spec_for_immediate(), RELOC_IMM32);
1816 address virtual_call_oop_addr = cbuf.inst_mark();
1817 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
1818 // who we intended to call.
1819 cbuf.set_inst_mark();
1820 $$$emit8$primary;
1821 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.code_end()) - 4),
1822 virtual_call_Relocation::spec(virtual_call_oop_addr), RELOC_IMM32 );
1823 %}
1824
1825 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL
1826 int disp = in_bytes(methodOopDesc::from_compiled_offset());
1827 assert( -128 <= disp && disp <= 127, "compiled_code_offset isn't small");
1828
1829 // CALL *[EAX+in_bytes(methodOopDesc::from_compiled_code_entry_point_offset())]
1830 cbuf.set_inst_mark();
1831 $$$emit8$primary;
1832 emit_rm(cbuf, 0x01, $secondary, EAX_enc ); // R/M byte
1833 emit_d8(cbuf, disp); // Displacement
1834
1835 %}
1836
1837 enc_class Xor_Reg (eRegI dst) %{
1838 emit_opcode(cbuf, 0x33);
1839 emit_rm(cbuf, 0x3, $dst$$reg, $dst$$reg);
1840 %}
1841
1842 // Following encoding is no longer used, but may be restored if calling
1843 // convention changes significantly.
1844 // Became: Xor_Reg(EBP), Java_To_Runtime( labl )
1845 //
1846 // enc_class Java_Interpreter_Call (label labl) %{ // JAVA INTERPRETER CALL
1847 // // int ic_reg = Matcher::inline_cache_reg();
1848 // // int ic_encode = Matcher::_regEncode[ic_reg];
1849 // // int imo_reg = Matcher::interpreter_method_oop_reg();
1850 // // int imo_encode = Matcher::_regEncode[imo_reg];
1851 //
1852 // // // Interpreter expects method_oop in EBX, currently a callee-saved register,
1853 // // // so we load it immediately before the call
1854 // // emit_opcode(cbuf, 0x8B); // MOV imo_reg,ic_reg # method_oop
1855 // // emit_rm(cbuf, 0x03, imo_encode, ic_encode ); // R/M byte
1856 //
1857 // // xor rbp,ebp
1858 // emit_opcode(cbuf, 0x33);
1859 // emit_rm(cbuf, 0x3, EBP_enc, EBP_enc);
1860 //
1861 // // CALL to interpreter.
1862 // cbuf.set_inst_mark();
1863 // $$$emit8$primary;
1864 // emit_d32_reloc(cbuf, ($labl$$label - (int)(cbuf.code_end()) - 4),
1865 // runtime_call_Relocation::spec(), RELOC_IMM32 );
1866 // %}
1867
1868 enc_class RegOpcImm (eRegI dst, immI8 shift) %{ // SHL, SAR, SHR
1869 $$$emit8$primary;
1870 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1871 $$$emit8$shift$$constant;
1872 %}
1873
1874 enc_class LdImmI (eRegI dst, immI src) %{ // Load Immediate
1875 // Load immediate does not have a zero or sign extended version
1876 // for 8-bit immediates
1877 emit_opcode(cbuf, 0xB8 + $dst$$reg);
1878 $$$emit32$src$$constant;
1879 %}
1880
1881 enc_class LdImmP (eRegI dst, immI src) %{ // Load Immediate
1882 // Load immediate does not have a zero or sign extended version
1883 // for 8-bit immediates
1884 emit_opcode(cbuf, $primary + $dst$$reg);
1885 $$$emit32$src$$constant;
1886 %}
1887
1888 enc_class LdImmL_Lo( eRegL dst, immL src) %{ // Load Immediate
1889 // Load immediate does not have a zero or sign extended version
1890 // for 8-bit immediates
1891 int dst_enc = $dst$$reg;
1892 int src_con = $src$$constant & 0x0FFFFFFFFL;
1893 if (src_con == 0) {
1894 // xor dst, dst
1895 emit_opcode(cbuf, 0x33);
1896 emit_rm(cbuf, 0x3, dst_enc, dst_enc);
1897 } else {
1898 emit_opcode(cbuf, $primary + dst_enc);
1899 emit_d32(cbuf, src_con);
1900 }
1901 %}
1902
1903 enc_class LdImmL_Hi( eRegL dst, immL src) %{ // Load Immediate
1904 // Load immediate does not have a zero or sign extended version
1905 // for 8-bit immediates
1906 int dst_enc = $dst$$reg + 2;
1907 int src_con = ((julong)($src$$constant)) >> 32;
1908 if (src_con == 0) {
1909 // xor dst, dst
1910 emit_opcode(cbuf, 0x33);
1911 emit_rm(cbuf, 0x3, dst_enc, dst_enc);
1912 } else {
1913 emit_opcode(cbuf, $primary + dst_enc);
1914 emit_d32(cbuf, src_con);
1915 }
1916 %}
1917
1918
1919 enc_class LdImmD (immD src) %{ // Load Immediate
1920 if( is_positive_zero_double($src$$constant)) {
1921 // FLDZ
1922 emit_opcode(cbuf,0xD9);
1923 emit_opcode(cbuf,0xEE);
1924 } else if( is_positive_one_double($src$$constant)) {
1925 // FLD1
1926 emit_opcode(cbuf,0xD9);
1927 emit_opcode(cbuf,0xE8);
1928 } else {
1929 emit_opcode(cbuf,0xDD);
1930 emit_rm(cbuf, 0x0, 0x0, 0x5);
1931 emit_double_constant(cbuf, $src$$constant);
1932 }
1933 %}
1934
1935
1936 enc_class LdImmF (immF src) %{ // Load Immediate
1937 if( is_positive_zero_float($src$$constant)) {
1938 emit_opcode(cbuf,0xD9);
1939 emit_opcode(cbuf,0xEE);
1940 } else if( is_positive_one_float($src$$constant)) {
1941 emit_opcode(cbuf,0xD9);
1942 emit_opcode(cbuf,0xE8);
1943 } else {
1944 $$$emit8$primary;
1945 // Load immediate does not have a zero or sign extended version
1946 // for 8-bit immediates
1947 // First load to TOS, then move to dst
1948 emit_rm(cbuf, 0x0, 0x0, 0x5);
1949 emit_float_constant(cbuf, $src$$constant);
1950 }
1951 %}
1952
1953 enc_class LdImmX (regX dst, immXF con) %{ // Load Immediate
1954 emit_rm(cbuf, 0x0, $dst$$reg, 0x5);
1955 emit_float_constant(cbuf, $con$$constant);
1956 %}
1957
1958 enc_class LdImmXD (regXD dst, immXD con) %{ // Load Immediate
1959 emit_rm(cbuf, 0x0, $dst$$reg, 0x5);
1960 emit_double_constant(cbuf, $con$$constant);
1961 %}
1962
1963 enc_class load_conXD (regXD dst, immXD con) %{ // Load double constant
1964 // UseXmmLoadAndClearUpper ? movsd(dst, con) : movlpd(dst, con)
1965 emit_opcode(cbuf, UseXmmLoadAndClearUpper ? 0xF2 : 0x66);
1966 emit_opcode(cbuf, 0x0F);
1967 emit_opcode(cbuf, UseXmmLoadAndClearUpper ? 0x10 : 0x12);
1968 emit_rm(cbuf, 0x0, $dst$$reg, 0x5);
1969 emit_double_constant(cbuf, $con$$constant);
1970 %}
1971
1972 enc_class Opc_MemImm_F(immF src) %{
1973 cbuf.set_inst_mark();
1974 $$$emit8$primary;
1975 emit_rm(cbuf, 0x0, $secondary, 0x5);
1976 emit_float_constant(cbuf, $src$$constant);
1977 %}
1978
1979
1980 enc_class MovI2X_reg(regX dst, eRegI src) %{
1981 emit_opcode(cbuf, 0x66 ); // MOVD dst,src
1982 emit_opcode(cbuf, 0x0F );
1983 emit_opcode(cbuf, 0x6E );
1984 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1985 %}
1986
1987 enc_class MovX2I_reg(eRegI dst, regX src) %{
1988 emit_opcode(cbuf, 0x66 ); // MOVD dst,src
1989 emit_opcode(cbuf, 0x0F );
1990 emit_opcode(cbuf, 0x7E );
1991 emit_rm(cbuf, 0x3, $src$$reg, $dst$$reg);
1992 %}
1993
1994 enc_class MovL2XD_reg(regXD dst, eRegL src, regXD tmp) %{
1995 { // MOVD $dst,$src.lo
1996 emit_opcode(cbuf,0x66);
1997 emit_opcode(cbuf,0x0F);
1998 emit_opcode(cbuf,0x6E);
1999 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2000 }
2001 { // MOVD $tmp,$src.hi
2002 emit_opcode(cbuf,0x66);
2003 emit_opcode(cbuf,0x0F);
2004 emit_opcode(cbuf,0x6E);
2005 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg));
2006 }
2007 { // PUNPCKLDQ $dst,$tmp
2008 emit_opcode(cbuf,0x66);
2009 emit_opcode(cbuf,0x0F);
2010 emit_opcode(cbuf,0x62);
2011 emit_rm(cbuf, 0x3, $dst$$reg, $tmp$$reg);
2012 }
2013 %}
2014
2015 enc_class MovXD2L_reg(eRegL dst, regXD src, regXD tmp) %{
2016 { // MOVD $dst.lo,$src
2017 emit_opcode(cbuf,0x66);
2018 emit_opcode(cbuf,0x0F);
2019 emit_opcode(cbuf,0x7E);
2020 emit_rm(cbuf, 0x3, $src$$reg, $dst$$reg);
2021 }
2022 { // PSHUFLW $tmp,$src,0x4E (01001110b)
2023 emit_opcode(cbuf,0xF2);
2024 emit_opcode(cbuf,0x0F);
2025 emit_opcode(cbuf,0x70);
2026 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg);
2027 emit_d8(cbuf, 0x4E);
2028 }
2029 { // MOVD $dst.hi,$tmp
2030 emit_opcode(cbuf,0x66);
2031 emit_opcode(cbuf,0x0F);
2032 emit_opcode(cbuf,0x7E);
2033 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg));
2034 }
2035 %}
2036
2037
2038 // Encode a reg-reg copy. If it is useless, then empty encoding.
2039 enc_class enc_Copy( eRegI dst, eRegI src ) %{
2040 encode_Copy( cbuf, $dst$$reg, $src$$reg );
2041 %}
2042
2043 enc_class enc_CopyL_Lo( eRegI dst, eRegL src ) %{
2044 encode_Copy( cbuf, $dst$$reg, $src$$reg );
2045 %}
2046
2047 // Encode xmm reg-reg copy. If it is useless, then empty encoding.
2048 enc_class enc_CopyXD( RegXD dst, RegXD src ) %{
2049 encode_CopyXD( cbuf, $dst$$reg, $src$$reg );
2050 %}
2051
2052 enc_class RegReg (eRegI dst, eRegI src) %{ // RegReg(Many)
2053 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2054 %}
2055
2056 enc_class RegReg_Lo(eRegL dst, eRegL src) %{ // RegReg(Many)
2057 $$$emit8$primary;
2058 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2059 %}
2060
2061 enc_class RegReg_Hi(eRegL dst, eRegL src) %{ // RegReg(Many)
2062 $$$emit8$secondary;
2063 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg));
2064 %}
2065
2066 enc_class RegReg_Lo2(eRegL dst, eRegL src) %{ // RegReg(Many)
2067 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2068 %}
2069
2070 enc_class RegReg_Hi2(eRegL dst, eRegL src) %{ // RegReg(Many)
2071 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg));
2072 %}
2073
2074 enc_class RegReg_HiLo( eRegL src, eRegI dst ) %{
2075 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($src$$reg));
2076 %}
2077
2078 enc_class Con32 (immI src) %{ // Con32(storeImmI)
2079 // Output immediate
2080 $$$emit32$src$$constant;
2081 %}
2082
2083 enc_class Con32F_as_bits(immF src) %{ // storeF_imm
2084 // Output Float immediate bits
2085 jfloat jf = $src$$constant;
2086 int jf_as_bits = jint_cast( jf );
2087 emit_d32(cbuf, jf_as_bits);
2088 %}
2089
2090 enc_class Con32XF_as_bits(immXF src) %{ // storeX_imm
2091 // Output Float immediate bits
2092 jfloat jf = $src$$constant;
2093 int jf_as_bits = jint_cast( jf );
2094 emit_d32(cbuf, jf_as_bits);
2095 %}
2096
2097 enc_class Con16 (immI src) %{ // Con16(storeImmI)
2098 // Output immediate
2099 $$$emit16$src$$constant;
2100 %}
2101
2102 enc_class Con_d32(immI src) %{
2103 emit_d32(cbuf,$src$$constant);
2104 %}
2105
2106 enc_class conmemref (eRegP t1) %{ // Con32(storeImmI)
2107 // Output immediate memory reference
2108 emit_rm(cbuf, 0x00, $t1$$reg, 0x05 );
2109 emit_d32(cbuf, 0x00);
2110 %}
2111
2112 enc_class lock_prefix( ) %{
2113 if( os::is_MP() )
2114 emit_opcode(cbuf,0xF0); // [Lock]
2115 %}
2116
2117 // Cmp-xchg long value.
2118 // Note: we need to swap rbx, and rcx before and after the
2119 // cmpxchg8 instruction because the instruction uses
2120 // rcx as the high order word of the new value to store but
2121 // our register encoding uses rbx,.
2122 enc_class enc_cmpxchg8(eSIRegP mem_ptr) %{
2123
2124 // XCHG rbx,ecx
2125 emit_opcode(cbuf,0x87);
2126 emit_opcode(cbuf,0xD9);
2127 // [Lock]
2128 if( os::is_MP() )
2129 emit_opcode(cbuf,0xF0);
2130 // CMPXCHG8 [Eptr]
2131 emit_opcode(cbuf,0x0F);
2132 emit_opcode(cbuf,0xC7);
2133 emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg );
2134 // XCHG rbx,ecx
2135 emit_opcode(cbuf,0x87);
2136 emit_opcode(cbuf,0xD9);
2137 %}
2138
2139 enc_class enc_cmpxchg(eSIRegP mem_ptr) %{
2140 // [Lock]
2141 if( os::is_MP() )
2142 emit_opcode(cbuf,0xF0);
2143
2144 // CMPXCHG [Eptr]
2145 emit_opcode(cbuf,0x0F);
2146 emit_opcode(cbuf,0xB1);
2147 emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg );
2148 %}
2149
2150 enc_class enc_flags_ne_to_boolean( iRegI res ) %{
2151 int res_encoding = $res$$reg;
2152
2153 // MOV res,0
2154 emit_opcode( cbuf, 0xB8 + res_encoding);
2155 emit_d32( cbuf, 0 );
2156 // JNE,s fail
2157 emit_opcode(cbuf,0x75);
2158 emit_d8(cbuf, 5 );
2159 // MOV res,1
2160 emit_opcode( cbuf, 0xB8 + res_encoding);
2161 emit_d32( cbuf, 1 );
2162 // fail:
2163 %}
2164
2165 enc_class set_instruction_start( ) %{
2166 cbuf.set_inst_mark(); // Mark start of opcode for reloc info in mem operand
2167 %}
2168
2169 enc_class RegMem (eRegI ereg, memory mem) %{ // emit_reg_mem
2170 int reg_encoding = $ereg$$reg;
2171 int base = $mem$$base;
2172 int index = $mem$$index;
2173 int scale = $mem$$scale;
2174 int displace = $mem$$disp;
2175 bool disp_is_oop = $mem->disp_is_oop();
2176 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2177 %}
2178
2179 enc_class RegMem_Hi(eRegL ereg, memory mem) %{ // emit_reg_mem
2180 int reg_encoding = HIGH_FROM_LOW($ereg$$reg); // Hi register of pair, computed from lo
2181 int base = $mem$$base;
2182 int index = $mem$$index;
2183 int scale = $mem$$scale;
2184 int displace = $mem$$disp + 4; // Offset is 4 further in memory
2185 assert( !$mem->disp_is_oop(), "Cannot add 4 to oop" );
2186 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, false/*disp_is_oop*/);
2187 %}
2188
2189 enc_class move_long_small_shift( eRegL dst, immI_1_31 cnt ) %{
2190 int r1, r2;
2191 if( $tertiary == 0xA4 ) { r1 = $dst$$reg; r2 = HIGH_FROM_LOW($dst$$reg); }
2192 else { r2 = $dst$$reg; r1 = HIGH_FROM_LOW($dst$$reg); }
2193 emit_opcode(cbuf,0x0F);
2194 emit_opcode(cbuf,$tertiary);
2195 emit_rm(cbuf, 0x3, r1, r2);
2196 emit_d8(cbuf,$cnt$$constant);
2197 emit_d8(cbuf,$primary);
2198 emit_rm(cbuf, 0x3, $secondary, r1);
2199 emit_d8(cbuf,$cnt$$constant);
2200 %}
2201
2202 enc_class move_long_big_shift_sign( eRegL dst, immI_32_63 cnt ) %{
2203 emit_opcode( cbuf, 0x8B ); // Move
2204 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg));
2205 emit_d8(cbuf,$primary);
2206 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
2207 emit_d8(cbuf,$cnt$$constant-32);
2208 emit_d8(cbuf,$primary);
2209 emit_rm(cbuf, 0x3, $secondary, HIGH_FROM_LOW($dst$$reg));
2210 emit_d8(cbuf,31);
2211 %}
2212
2213 enc_class move_long_big_shift_clr( eRegL dst, immI_32_63 cnt ) %{
2214 int r1, r2;
2215 if( $secondary == 0x5 ) { r1 = $dst$$reg; r2 = HIGH_FROM_LOW($dst$$reg); }
2216 else { r2 = $dst$$reg; r1 = HIGH_FROM_LOW($dst$$reg); }
2217
2218 emit_opcode( cbuf, 0x8B ); // Move r1,r2
2219 emit_rm(cbuf, 0x3, r1, r2);
2220 if( $cnt$$constant > 32 ) { // Shift, if not by zero
2221 emit_opcode(cbuf,$primary);
2222 emit_rm(cbuf, 0x3, $secondary, r1);
2223 emit_d8(cbuf,$cnt$$constant-32);
2224 }
2225 emit_opcode(cbuf,0x33); // XOR r2,r2
2226 emit_rm(cbuf, 0x3, r2, r2);
2227 %}
2228
2229 // Clone of RegMem but accepts an extra parameter to access each
2230 // half of a double in memory; it never needs relocation info.
2231 enc_class Mov_MemD_half_to_Reg (immI opcode, memory mem, immI disp_for_half, eRegI rm_reg) %{
2232 emit_opcode(cbuf,$opcode$$constant);
2233 int reg_encoding = $rm_reg$$reg;
2234 int base = $mem$$base;
2235 int index = $mem$$index;
2236 int scale = $mem$$scale;
2237 int displace = $mem$$disp + $disp_for_half$$constant;
2238 bool disp_is_oop = false;
2239 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2240 %}
2241
2242 // !!!!! Special Custom Code used by MemMove, and stack access instructions !!!!!
2243 //
2244 // Clone of RegMem except the RM-byte's reg/opcode field is an ADLC-time constant
2245 // and it never needs relocation information.
2246 // Frequently used to move data between FPU's Stack Top and memory.
2247 enc_class RMopc_Mem_no_oop (immI rm_opcode, memory mem) %{
2248 int rm_byte_opcode = $rm_opcode$$constant;
2249 int base = $mem$$base;
2250 int index = $mem$$index;
2251 int scale = $mem$$scale;
2252 int displace = $mem$$disp;
2253 assert( !$mem->disp_is_oop(), "No oops here because no relo info allowed" );
2254 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, false);
2255 %}
2256
2257 enc_class RMopc_Mem (immI rm_opcode, memory mem) %{
2258 int rm_byte_opcode = $rm_opcode$$constant;
2259 int base = $mem$$base;
2260 int index = $mem$$index;
2261 int scale = $mem$$scale;
2262 int displace = $mem$$disp;
2263 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
2264 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_is_oop);
2265 %}
2266
2267 enc_class RegLea (eRegI dst, eRegI src0, immI src1 ) %{ // emit_reg_lea
2268 int reg_encoding = $dst$$reg;
2269 int base = $src0$$reg; // 0xFFFFFFFF indicates no base
2270 int index = 0x04; // 0x04 indicates no index
2271 int scale = 0x00; // 0x00 indicates no scale
2272 int displace = $src1$$constant; // 0x00 indicates no displacement
2273 bool disp_is_oop = false;
2274 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2275 %}
2276
2277 enc_class min_enc (eRegI dst, eRegI src) %{ // MIN
2278 // Compare dst,src
2279 emit_opcode(cbuf,0x3B);
2280 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2281 // jmp dst < src around move
2282 emit_opcode(cbuf,0x7C);
2283 emit_d8(cbuf,2);
2284 // move dst,src
2285 emit_opcode(cbuf,0x8B);
2286 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2287 %}
2288
2289 enc_class max_enc (eRegI dst, eRegI src) %{ // MAX
2290 // Compare dst,src
2291 emit_opcode(cbuf,0x3B);
2292 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2293 // jmp dst > src around move
2294 emit_opcode(cbuf,0x7F);
2295 emit_d8(cbuf,2);
2296 // move dst,src
2297 emit_opcode(cbuf,0x8B);
2298 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2299 %}
2300
2301 enc_class enc_FP_store(memory mem, regD src) %{
2302 // If src is FPR1, we can just FST to store it.
2303 // Else we need to FLD it to FPR1, then FSTP to store/pop it.
2304 int reg_encoding = 0x2; // Just store
2305 int base = $mem$$base;
2306 int index = $mem$$index;
2307 int scale = $mem$$scale;
2308 int displace = $mem$$disp;
2309 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
2310 if( $src$$reg != FPR1L_enc ) {
2311 reg_encoding = 0x3; // Store & pop
2312 emit_opcode( cbuf, 0xD9 ); // FLD (i.e., push it)
2313 emit_d8( cbuf, 0xC0-1+$src$$reg );
2314 }
2315 cbuf.set_inst_mark(); // Mark start of opcode for reloc info in mem operand
2316 emit_opcode(cbuf,$primary);
2317 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2318 %}
2319
2320 enc_class neg_reg(eRegI dst) %{
2321 // NEG $dst
2322 emit_opcode(cbuf,0xF7);
2323 emit_rm(cbuf, 0x3, 0x03, $dst$$reg );
2324 %}
2325
2326 enc_class setLT_reg(eCXRegI dst) %{
2327 // SETLT $dst
2328 emit_opcode(cbuf,0x0F);
2329 emit_opcode(cbuf,0x9C);
2330 emit_rm( cbuf, 0x3, 0x4, $dst$$reg );
2331 %}
2332
2333 enc_class enc_cmpLTP(ncxRegI p, ncxRegI q, ncxRegI y, eCXRegI tmp) %{ // cadd_cmpLT
2334 int tmpReg = $tmp$$reg;
2335
2336 // SUB $p,$q
2337 emit_opcode(cbuf,0x2B);
2338 emit_rm(cbuf, 0x3, $p$$reg, $q$$reg);
2339 // SBB $tmp,$tmp
2340 emit_opcode(cbuf,0x1B);
2341 emit_rm(cbuf, 0x3, tmpReg, tmpReg);
2342 // AND $tmp,$y
2343 emit_opcode(cbuf,0x23);
2344 emit_rm(cbuf, 0x3, tmpReg, $y$$reg);
2345 // ADD $p,$tmp
2346 emit_opcode(cbuf,0x03);
2347 emit_rm(cbuf, 0x3, $p$$reg, tmpReg);
2348 %}
2349
2350 enc_class enc_cmpLTP_mem(eRegI p, eRegI q, memory mem, eCXRegI tmp) %{ // cadd_cmpLT
2351 int tmpReg = $tmp$$reg;
2352
2353 // SUB $p,$q
2354 emit_opcode(cbuf,0x2B);
2355 emit_rm(cbuf, 0x3, $p$$reg, $q$$reg);
2356 // SBB $tmp,$tmp
2357 emit_opcode(cbuf,0x1B);
2358 emit_rm(cbuf, 0x3, tmpReg, tmpReg);
2359 // AND $tmp,$y
2360 cbuf.set_inst_mark(); // Mark start of opcode for reloc info in mem operand
2361 emit_opcode(cbuf,0x23);
2362 int reg_encoding = tmpReg;
2363 int base = $mem$$base;
2364 int index = $mem$$index;
2365 int scale = $mem$$scale;
2366 int displace = $mem$$disp;
2367 bool disp_is_oop = $mem->disp_is_oop();
2368 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2369 // ADD $p,$tmp
2370 emit_opcode(cbuf,0x03);
2371 emit_rm(cbuf, 0x3, $p$$reg, tmpReg);
2372 %}
2373
2374 enc_class shift_left_long( eRegL dst, eCXRegI shift ) %{
2375 // TEST shift,32
2376 emit_opcode(cbuf,0xF7);
2377 emit_rm(cbuf, 0x3, 0, ECX_enc);
2378 emit_d32(cbuf,0x20);
2379 // JEQ,s small
2380 emit_opcode(cbuf, 0x74);
2381 emit_d8(cbuf, 0x04);
2382 // MOV $dst.hi,$dst.lo
2383 emit_opcode( cbuf, 0x8B );
2384 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg );
2385 // CLR $dst.lo
2386 emit_opcode(cbuf, 0x33);
2387 emit_rm(cbuf, 0x3, $dst$$reg, $dst$$reg);
2388 // small:
2389 // SHLD $dst.hi,$dst.lo,$shift
2390 emit_opcode(cbuf,0x0F);
2391 emit_opcode(cbuf,0xA5);
2392 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg));
2393 // SHL $dst.lo,$shift"
2394 emit_opcode(cbuf,0xD3);
2395 emit_rm(cbuf, 0x3, 0x4, $dst$$reg );
2396 %}
2397
2398 enc_class shift_right_long( eRegL dst, eCXRegI shift ) %{
2399 // TEST shift,32
2400 emit_opcode(cbuf,0xF7);
2401 emit_rm(cbuf, 0x3, 0, ECX_enc);
2402 emit_d32(cbuf,0x20);
2403 // JEQ,s small
2404 emit_opcode(cbuf, 0x74);
2405 emit_d8(cbuf, 0x04);
2406 // MOV $dst.lo,$dst.hi
2407 emit_opcode( cbuf, 0x8B );
2408 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) );
2409 // CLR $dst.hi
2410 emit_opcode(cbuf, 0x33);
2411 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($dst$$reg));
2412 // small:
2413 // SHRD $dst.lo,$dst.hi,$shift
2414 emit_opcode(cbuf,0x0F);
2415 emit_opcode(cbuf,0xAD);
2416 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg);
2417 // SHR $dst.hi,$shift"
2418 emit_opcode(cbuf,0xD3);
2419 emit_rm(cbuf, 0x3, 0x5, HIGH_FROM_LOW($dst$$reg) );
2420 %}
2421
2422 enc_class shift_right_arith_long( eRegL dst, eCXRegI shift ) %{
2423 // TEST shift,32
2424 emit_opcode(cbuf,0xF7);
2425 emit_rm(cbuf, 0x3, 0, ECX_enc);
2426 emit_d32(cbuf,0x20);
2427 // JEQ,s small
2428 emit_opcode(cbuf, 0x74);
2429 emit_d8(cbuf, 0x05);
2430 // MOV $dst.lo,$dst.hi
2431 emit_opcode( cbuf, 0x8B );
2432 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) );
2433 // SAR $dst.hi,31
2434 emit_opcode(cbuf, 0xC1);
2435 emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW($dst$$reg) );
2436 emit_d8(cbuf, 0x1F );
2437 // small:
2438 // SHRD $dst.lo,$dst.hi,$shift
2439 emit_opcode(cbuf,0x0F);
2440 emit_opcode(cbuf,0xAD);
2441 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg);
2442 // SAR $dst.hi,$shift"
2443 emit_opcode(cbuf,0xD3);
2444 emit_rm(cbuf, 0x3, 0x7, HIGH_FROM_LOW($dst$$reg) );
2445 %}
2446
2447
2448 // ----------------- Encodings for floating point unit -----------------
2449 // May leave result in FPU-TOS or FPU reg depending on opcodes
2450 enc_class OpcReg_F (regF src) %{ // FMUL, FDIV
2451 $$$emit8$primary;
2452 emit_rm(cbuf, 0x3, $secondary, $src$$reg );
2453 %}
2454
2455 // Pop argument in FPR0 with FSTP ST(0)
2456 enc_class PopFPU() %{
2457 emit_opcode( cbuf, 0xDD );
2458 emit_d8( cbuf, 0xD8 );
2459 %}
2460
2461 // !!!!! equivalent to Pop_Reg_F
2462 enc_class Pop_Reg_D( regD dst ) %{
2463 emit_opcode( cbuf, 0xDD ); // FSTP ST(i)
2464 emit_d8( cbuf, 0xD8+$dst$$reg );
2465 %}
2466
2467 enc_class Push_Reg_D( regD dst ) %{
2468 emit_opcode( cbuf, 0xD9 );
2469 emit_d8( cbuf, 0xC0-1+$dst$$reg ); // FLD ST(i-1)
2470 %}
2471
2472 enc_class strictfp_bias1( regD dst ) %{
2473 emit_opcode( cbuf, 0xDB ); // FLD m80real
2474 emit_opcode( cbuf, 0x2D );
2475 emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias1() );
2476 emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0
2477 emit_opcode( cbuf, 0xC8+$dst$$reg );
2478 %}
2479
2480 enc_class strictfp_bias2( regD dst ) %{
2481 emit_opcode( cbuf, 0xDB ); // FLD m80real
2482 emit_opcode( cbuf, 0x2D );
2483 emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias2() );
2484 emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0
2485 emit_opcode( cbuf, 0xC8+$dst$$reg );
2486 %}
2487
2488 // Special case for moving an integer register to a stack slot.
2489 enc_class OpcPRegSS( stackSlotI dst, eRegI src ) %{ // RegSS
2490 store_to_stackslot( cbuf, $primary, $src$$reg, $dst$$disp );
2491 %}
2492
2493 // Special case for moving a register to a stack slot.
2494 enc_class RegSS( stackSlotI dst, eRegI src ) %{ // RegSS
2495 // Opcode already emitted
2496 emit_rm( cbuf, 0x02, $src$$reg, ESP_enc ); // R/M byte
2497 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
2498 emit_d32(cbuf, $dst$$disp); // Displacement
2499 %}
2500
2501 // Push the integer in stackSlot 'src' onto FP-stack
2502 enc_class Push_Mem_I( memory src ) %{ // FILD [ESP+src]
2503 store_to_stackslot( cbuf, $primary, $secondary, $src$$disp );
2504 %}
2505
2506 // Push the float in stackSlot 'src' onto FP-stack
2507 enc_class Push_Mem_F( memory src ) %{ // FLD_S [ESP+src]
2508 store_to_stackslot( cbuf, 0xD9, 0x00, $src$$disp );
2509 %}
2510
2511 // Push the double in stackSlot 'src' onto FP-stack
2512 enc_class Push_Mem_D( memory src ) %{ // FLD_D [ESP+src]
2513 store_to_stackslot( cbuf, 0xDD, 0x00, $src$$disp );
2514 %}
2515
2516 // Push FPU's TOS float to a stack-slot, and pop FPU-stack
2517 enc_class Pop_Mem_F( stackSlotF dst ) %{ // FSTP_S [ESP+dst]
2518 store_to_stackslot( cbuf, 0xD9, 0x03, $dst$$disp );
2519 %}
2520
2521 // Same as Pop_Mem_F except for opcode
2522 // Push FPU's TOS double to a stack-slot, and pop FPU-stack
2523 enc_class Pop_Mem_D( stackSlotD dst ) %{ // FSTP_D [ESP+dst]
2524 store_to_stackslot( cbuf, 0xDD, 0x03, $dst$$disp );
2525 %}
2526
2527 enc_class Pop_Reg_F( regF dst ) %{
2528 emit_opcode( cbuf, 0xDD ); // FSTP ST(i)
2529 emit_d8( cbuf, 0xD8+$dst$$reg );
2530 %}
2531
2532 enc_class Push_Reg_F( regF dst ) %{
2533 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2534 emit_d8( cbuf, 0xC0-1+$dst$$reg );
2535 %}
2536
2537 // Push FPU's float to a stack-slot, and pop FPU-stack
2538 enc_class Pop_Mem_Reg_F( stackSlotF dst, regF src ) %{
2539 int pop = 0x02;
2540 if ($src$$reg != FPR1L_enc) {
2541 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2542 emit_d8( cbuf, 0xC0-1+$src$$reg );
2543 pop = 0x03;
2544 }
2545 store_to_stackslot( cbuf, 0xD9, pop, $dst$$disp ); // FST<P>_S [ESP+dst]
2546 %}
2547
2548 // Push FPU's double to a stack-slot, and pop FPU-stack
2549 enc_class Pop_Mem_Reg_D( stackSlotD dst, regD src ) %{
2550 int pop = 0x02;
2551 if ($src$$reg != FPR1L_enc) {
2552 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2553 emit_d8( cbuf, 0xC0-1+$src$$reg );
2554 pop = 0x03;
2555 }
2556 store_to_stackslot( cbuf, 0xDD, pop, $dst$$disp ); // FST<P>_D [ESP+dst]
2557 %}
2558
2559 // Push FPU's double to a FPU-stack-slot, and pop FPU-stack
2560 enc_class Pop_Reg_Reg_D( regD dst, regF src ) %{
2561 int pop = 0xD0 - 1; // -1 since we skip FLD
2562 if ($src$$reg != FPR1L_enc) {
2563 emit_opcode( cbuf, 0xD9 ); // FLD ST(src-1)
2564 emit_d8( cbuf, 0xC0-1+$src$$reg );
2565 pop = 0xD8;
2566 }
2567 emit_opcode( cbuf, 0xDD );
2568 emit_d8( cbuf, pop+$dst$$reg ); // FST<P> ST(i)
2569 %}
2570
2571
2572 enc_class Mul_Add_F( regF dst, regF src, regF src1, regF src2 ) %{
2573 MacroAssembler masm(&cbuf);
2574 masm.fld_s( $src1$$reg-1); // nothing at TOS, load TOS from src1.reg
2575 masm.fmul( $src2$$reg+0); // value at TOS
2576 masm.fadd( $src$$reg+0); // value at TOS
2577 masm.fstp_d( $dst$$reg+0); // value at TOS, popped off after store
2578 %}
2579
2580
2581 enc_class Push_Reg_Mod_D( regD dst, regD src) %{
2582 // load dst in FPR0
2583 emit_opcode( cbuf, 0xD9 );
2584 emit_d8( cbuf, 0xC0-1+$dst$$reg );
2585 if ($src$$reg != FPR1L_enc) {
2586 // fincstp
2587 emit_opcode (cbuf, 0xD9);
2588 emit_opcode (cbuf, 0xF7);
2589 // swap src with FPR1:
2590 // FXCH FPR1 with src
2591 emit_opcode(cbuf, 0xD9);
2592 emit_d8(cbuf, 0xC8-1+$src$$reg );
2593 // fdecstp
2594 emit_opcode (cbuf, 0xD9);
2595 emit_opcode (cbuf, 0xF6);
2596 }
2597 %}
2598
2599 enc_class Push_ModD_encoding( regXD src0, regXD src1) %{
2600 // Allocate a word
2601 emit_opcode(cbuf,0x83); // SUB ESP,8
2602 emit_opcode(cbuf,0xEC);
2603 emit_d8(cbuf,0x08);
2604
2605 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], src1
2606 emit_opcode (cbuf, 0x0F );
2607 emit_opcode (cbuf, 0x11 );
2608 encode_RegMem(cbuf, $src1$$reg, ESP_enc, 0x4, 0, 0, false);
2609
2610 emit_opcode(cbuf,0xDD ); // FLD_D [ESP]
2611 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
2612
2613 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], src0
2614 emit_opcode (cbuf, 0x0F );
2615 emit_opcode (cbuf, 0x11 );
2616 encode_RegMem(cbuf, $src0$$reg, ESP_enc, 0x4, 0, 0, false);
2617
2618 emit_opcode(cbuf,0xDD ); // FLD_D [ESP]
2619 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
2620
2621 %}
2622
2623 enc_class Push_ModX_encoding( regX src0, regX src1) %{
2624 // Allocate a word
2625 emit_opcode(cbuf,0x83); // SUB ESP,4
2626 emit_opcode(cbuf,0xEC);
2627 emit_d8(cbuf,0x04);
2628
2629 emit_opcode (cbuf, 0xF3 ); // MOVSS [ESP], src1
2630 emit_opcode (cbuf, 0x0F );
2631 emit_opcode (cbuf, 0x11 );
2632 encode_RegMem(cbuf, $src1$$reg, ESP_enc, 0x4, 0, 0, false);
2633
2634 emit_opcode(cbuf,0xD9 ); // FLD [ESP]
2635 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
2636
2637 emit_opcode (cbuf, 0xF3 ); // MOVSS [ESP], src0
2638 emit_opcode (cbuf, 0x0F );
2639 emit_opcode (cbuf, 0x11 );
2640 encode_RegMem(cbuf, $src0$$reg, ESP_enc, 0x4, 0, 0, false);
2641
2642 emit_opcode(cbuf,0xD9 ); // FLD [ESP]
2643 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
2644
2645 %}
2646
2647 enc_class Push_ResultXD(regXD dst) %{
2648 store_to_stackslot( cbuf, 0xDD, 0x03, 0 ); //FSTP [ESP]
2649
2650 // UseXmmLoadAndClearUpper ? movsd dst,[esp] : movlpd dst,[esp]
2651 emit_opcode (cbuf, UseXmmLoadAndClearUpper ? 0xF2 : 0x66);
2652 emit_opcode (cbuf, 0x0F );
2653 emit_opcode (cbuf, UseXmmLoadAndClearUpper ? 0x10 : 0x12);
2654 encode_RegMem(cbuf, $dst$$reg, ESP_enc, 0x4, 0, 0, false);
2655
2656 emit_opcode(cbuf,0x83); // ADD ESP,8
2657 emit_opcode(cbuf,0xC4);
2658 emit_d8(cbuf,0x08);
2659 %}
2660
2661 enc_class Push_ResultX(regX dst, immI d8) %{
2662 store_to_stackslot( cbuf, 0xD9, 0x03, 0 ); //FSTP_S [ESP]
2663
2664 emit_opcode (cbuf, 0xF3 ); // MOVSS dst(xmm), [ESP]
2665 emit_opcode (cbuf, 0x0F );
2666 emit_opcode (cbuf, 0x10 );
2667 encode_RegMem(cbuf, $dst$$reg, ESP_enc, 0x4, 0, 0, false);
2668
2669 emit_opcode(cbuf,0x83); // ADD ESP,d8 (4 or 8)
2670 emit_opcode(cbuf,0xC4);
2671 emit_d8(cbuf,$d8$$constant);
2672 %}
2673
2674 enc_class Push_SrcXD(regXD src) %{
2675 // Allocate a word
2676 emit_opcode(cbuf,0x83); // SUB ESP,8
2677 emit_opcode(cbuf,0xEC);
2678 emit_d8(cbuf,0x08);
2679
2680 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], src
2681 emit_opcode (cbuf, 0x0F );
2682 emit_opcode (cbuf, 0x11 );
2683 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false);
2684
2685 emit_opcode(cbuf,0xDD ); // FLD_D [ESP]
2686 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
2687 %}
2688
2689 enc_class push_stack_temp_qword() %{
2690 emit_opcode(cbuf,0x83); // SUB ESP,8
2691 emit_opcode(cbuf,0xEC);
2692 emit_d8 (cbuf,0x08);
2693 %}
2694
2695 enc_class pop_stack_temp_qword() %{
2696 emit_opcode(cbuf,0x83); // ADD ESP,8
2697 emit_opcode(cbuf,0xC4);
2698 emit_d8 (cbuf,0x08);
2699 %}
2700
2701 enc_class push_xmm_to_fpr1( regXD xmm_src ) %{
2702 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], xmm_src
2703 emit_opcode (cbuf, 0x0F );
2704 emit_opcode (cbuf, 0x11 );
2705 encode_RegMem(cbuf, $xmm_src$$reg, ESP_enc, 0x4, 0, 0, false);
2706
2707 emit_opcode(cbuf,0xDD ); // FLD_D [ESP]
2708 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
2709 %}
2710
2711 // Compute X^Y using Intel's fast hardware instructions, if possible.
2712 // Otherwise return a NaN.
2713 enc_class pow_exp_core_encoding %{
2714 // FPR1 holds Y*ln2(X). Compute FPR1 = 2^(Y*ln2(X))
2715 emit_opcode(cbuf,0xD9); emit_opcode(cbuf,0xC0); // fdup = fld st(0) Q Q
2716 emit_opcode(cbuf,0xD9); emit_opcode(cbuf,0xFC); // frndint int(Q) Q
2717 emit_opcode(cbuf,0xDC); emit_opcode(cbuf,0xE9); // fsub st(1) -= st(0); int(Q) frac(Q)
2718 emit_opcode(cbuf,0xDB); // FISTP [ESP] frac(Q)
2719 emit_opcode(cbuf,0x1C);
2720 emit_d8(cbuf,0x24);
2721 emit_opcode(cbuf,0xD9); emit_opcode(cbuf,0xF0); // f2xm1 2^frac(Q)-1
2722 emit_opcode(cbuf,0xD9); emit_opcode(cbuf,0xE8); // fld1 1 2^frac(Q)-1
2723 emit_opcode(cbuf,0xDE); emit_opcode(cbuf,0xC1); // faddp 2^frac(Q)
2724 emit_opcode(cbuf,0x8B); // mov rax,[esp+0]=int(Q)
2725 encode_RegMem(cbuf, EAX_enc, ESP_enc, 0x4, 0, 0, false);
2726 emit_opcode(cbuf,0xC7); // mov rcx,0xFFFFF800 - overflow mask
2727 emit_rm(cbuf, 0x3, 0x0, ECX_enc);
2728 emit_d32(cbuf,0xFFFFF800);
2729 emit_opcode(cbuf,0x81); // add rax,1023 - the double exponent bias
2730 emit_rm(cbuf, 0x3, 0x0, EAX_enc);
2731 emit_d32(cbuf,1023);
2732 emit_opcode(cbuf,0x8B); // mov rbx,eax
2733 emit_rm(cbuf, 0x3, EBX_enc, EAX_enc);
2734 emit_opcode(cbuf,0xC1); // shl rax,20 - Slide to exponent position
2735 emit_rm(cbuf,0x3,0x4,EAX_enc);
2736 emit_d8(cbuf,20);
2737 emit_opcode(cbuf,0x85); // test rbx,ecx - check for overflow
2738 emit_rm(cbuf, 0x3, EBX_enc, ECX_enc);
2739 emit_opcode(cbuf,0x0F); emit_opcode(cbuf,0x45); // CMOVne rax,ecx - overflow; stuff NAN into EAX
2740 emit_rm(cbuf, 0x3, EAX_enc, ECX_enc);
2741 emit_opcode(cbuf,0x89); // mov [esp+4],eax - Store as part of double word
2742 encode_RegMem(cbuf, EAX_enc, ESP_enc, 0x4, 0, 4, false);
2743 emit_opcode(cbuf,0xC7); // mov [esp+0],0 - [ESP] = (double)(1<<int(Q)) = 2^int(Q)
2744 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
2745 emit_d32(cbuf,0);
2746 emit_opcode(cbuf,0xDC); // fmul dword st(0),[esp+0]; FPR1 = 2^int(Q)*2^frac(Q) = 2^Q
2747 encode_RegMem(cbuf, 0x1, ESP_enc, 0x4, 0, 0, false);
2748 %}
2749
2750 // enc_class Pop_Reg_Mod_D( regD dst, regD src)
2751 // was replaced by Push_Result_Mod_D followed by Pop_Reg_X() or Pop_Mem_X()
2752
2753 enc_class Push_Result_Mod_D( regD src) %{
2754 if ($src$$reg != FPR1L_enc) {
2755 // fincstp
2756 emit_opcode (cbuf, 0xD9);
2757 emit_opcode (cbuf, 0xF7);
2758 // FXCH FPR1 with src
2759 emit_opcode(cbuf, 0xD9);
2760 emit_d8(cbuf, 0xC8-1+$src$$reg );
2761 // fdecstp
2762 emit_opcode (cbuf, 0xD9);
2763 emit_opcode (cbuf, 0xF6);
2764 }
2765 // // following asm replaced with Pop_Reg_F or Pop_Mem_F
2766 // // FSTP FPR$dst$$reg
2767 // emit_opcode( cbuf, 0xDD );
2768 // emit_d8( cbuf, 0xD8+$dst$$reg );
2769 %}
2770
2771 enc_class fnstsw_sahf_skip_parity() %{
2772 // fnstsw ax
2773 emit_opcode( cbuf, 0xDF );
2774 emit_opcode( cbuf, 0xE0 );
2775 // sahf
2776 emit_opcode( cbuf, 0x9E );
2777 // jnp ::skip
2778 emit_opcode( cbuf, 0x7B );
2779 emit_opcode( cbuf, 0x05 );
2780 %}
2781
2782 enc_class emitModD() %{
2783 // fprem must be iterative
2784 // :: loop
2785 // fprem
2786 emit_opcode( cbuf, 0xD9 );
2787 emit_opcode( cbuf, 0xF8 );
2788 // wait
2789 emit_opcode( cbuf, 0x9b );
2790 // fnstsw ax
2791 emit_opcode( cbuf, 0xDF );
2792 emit_opcode( cbuf, 0xE0 );
2793 // sahf
2794 emit_opcode( cbuf, 0x9E );
2795 // jp ::loop
2796 emit_opcode( cbuf, 0x0F );
2797 emit_opcode( cbuf, 0x8A );
2798 emit_opcode( cbuf, 0xF4 );
2799 emit_opcode( cbuf, 0xFF );
2800 emit_opcode( cbuf, 0xFF );
2801 emit_opcode( cbuf, 0xFF );
2802 %}
2803
2804 enc_class fpu_flags() %{
2805 // fnstsw_ax
2806 emit_opcode( cbuf, 0xDF);
2807 emit_opcode( cbuf, 0xE0);
2808 // test ax,0x0400
2809 emit_opcode( cbuf, 0x66 ); // operand-size prefix for 16-bit immediate
2810 emit_opcode( cbuf, 0xA9 );
2811 emit_d16 ( cbuf, 0x0400 );
2812 // // // This sequence works, but stalls for 12-16 cycles on PPro
2813 // // test rax,0x0400
2814 // emit_opcode( cbuf, 0xA9 );
2815 // emit_d32 ( cbuf, 0x00000400 );
2816 //
2817 // jz exit (no unordered comparison)
2818 emit_opcode( cbuf, 0x74 );
2819 emit_d8 ( cbuf, 0x02 );
2820 // mov ah,1 - treat as LT case (set carry flag)
2821 emit_opcode( cbuf, 0xB4 );
2822 emit_d8 ( cbuf, 0x01 );
2823 // sahf
2824 emit_opcode( cbuf, 0x9E);
2825 %}
2826
2827 enc_class cmpF_P6_fixup() %{
2828 // Fixup the integer flags in case comparison involved a NaN
2829 //
2830 // JNP exit (no unordered comparison, P-flag is set by NaN)
2831 emit_opcode( cbuf, 0x7B );
2832 emit_d8 ( cbuf, 0x03 );
2833 // MOV AH,1 - treat as LT case (set carry flag)
2834 emit_opcode( cbuf, 0xB4 );
2835 emit_d8 ( cbuf, 0x01 );
2836 // SAHF
2837 emit_opcode( cbuf, 0x9E);
2838 // NOP // target for branch to avoid branch to branch
2839 emit_opcode( cbuf, 0x90);
2840 %}
2841
2842 // fnstsw_ax();
2843 // sahf();
2844 // movl(dst, nan_result);
2845 // jcc(Assembler::parity, exit);
2846 // movl(dst, less_result);
2847 // jcc(Assembler::below, exit);
2848 // movl(dst, equal_result);
2849 // jcc(Assembler::equal, exit);
2850 // movl(dst, greater_result);
2851
2852 // less_result = 1;
2853 // greater_result = -1;
2854 // equal_result = 0;
2855 // nan_result = -1;
2856
2857 enc_class CmpF_Result(eRegI dst) %{
2858 // fnstsw_ax();
2859 emit_opcode( cbuf, 0xDF);
2860 emit_opcode( cbuf, 0xE0);
2861 // sahf
2862 emit_opcode( cbuf, 0x9E);
2863 // movl(dst, nan_result);
2864 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2865 emit_d32( cbuf, -1 );
2866 // jcc(Assembler::parity, exit);
2867 emit_opcode( cbuf, 0x7A );
2868 emit_d8 ( cbuf, 0x13 );
2869 // movl(dst, less_result);
2870 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2871 emit_d32( cbuf, -1 );
2872 // jcc(Assembler::below, exit);
2873 emit_opcode( cbuf, 0x72 );
2874 emit_d8 ( cbuf, 0x0C );
2875 // movl(dst, equal_result);
2876 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2877 emit_d32( cbuf, 0 );
2878 // jcc(Assembler::equal, exit);
2879 emit_opcode( cbuf, 0x74 );
2880 emit_d8 ( cbuf, 0x05 );
2881 // movl(dst, greater_result);
2882 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2883 emit_d32( cbuf, 1 );
2884 %}
2885
2886
2887 // XMM version of CmpF_Result. Because the XMM compare
2888 // instructions set the EFLAGS directly. It becomes simpler than
2889 // the float version above.
2890 enc_class CmpX_Result(eRegI dst) %{
2891 MacroAssembler _masm(&cbuf);
2892 Label nan, inc, done;
2893
2894 __ jccb(Assembler::parity, nan);
2895 __ jccb(Assembler::equal, done);
2896 __ jccb(Assembler::above, inc);
2897 __ bind(nan);
2898 __ decrement(as_Register($dst$$reg)); // NO L qqq
2899 __ jmpb(done);
2900 __ bind(inc);
2901 __ increment(as_Register($dst$$reg)); // NO L qqq
2902 __ bind(done);
2903 %}
2904
2905 // Compare the longs and set flags
2906 // BROKEN! Do Not use as-is
2907 enc_class cmpl_test( eRegL src1, eRegL src2 ) %{
2908 // CMP $src1.hi,$src2.hi
2909 emit_opcode( cbuf, 0x3B );
2910 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) );
2911 // JNE,s done
2912 emit_opcode(cbuf,0x75);
2913 emit_d8(cbuf, 2 );
2914 // CMP $src1.lo,$src2.lo
2915 emit_opcode( cbuf, 0x3B );
2916 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
2917 // done:
2918 %}
2919
2920 enc_class convert_int_long( regL dst, eRegI src ) %{
2921 // mov $dst.lo,$src
2922 int dst_encoding = $dst$$reg;
2923 int src_encoding = $src$$reg;
2924 encode_Copy( cbuf, dst_encoding , src_encoding );
2925 // mov $dst.hi,$src
2926 encode_Copy( cbuf, HIGH_FROM_LOW(dst_encoding), src_encoding );
2927 // sar $dst.hi,31
2928 emit_opcode( cbuf, 0xC1 );
2929 emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW(dst_encoding) );
2930 emit_d8(cbuf, 0x1F );
2931 %}
2932
2933 enc_class convert_long_double( eRegL src ) %{
2934 // push $src.hi
2935 emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg));
2936 // push $src.lo
2937 emit_opcode(cbuf, 0x50+$src$$reg );
2938 // fild 64-bits at [SP]
2939 emit_opcode(cbuf,0xdf);
2940 emit_d8(cbuf, 0x6C);
2941 emit_d8(cbuf, 0x24);
2942 emit_d8(cbuf, 0x00);
2943 // pop stack
2944 emit_opcode(cbuf, 0x83); // add SP, #8
2945 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
2946 emit_d8(cbuf, 0x8);
2947 %}
2948
2949 enc_class multiply_con_and_shift_high( eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr ) %{
2950 // IMUL EDX:EAX,$src1
2951 emit_opcode( cbuf, 0xF7 );
2952 emit_rm( cbuf, 0x3, 0x5, $src1$$reg );
2953 // SAR EDX,$cnt-32
2954 int shift_count = ((int)$cnt$$constant) - 32;
2955 if (shift_count > 0) {
2956 emit_opcode(cbuf, 0xC1);
2957 emit_rm(cbuf, 0x3, 7, $dst$$reg );
2958 emit_d8(cbuf, shift_count);
2959 }
2960 %}
2961
2962 // this version doesn't have add sp, 8
2963 enc_class convert_long_double2( eRegL src ) %{
2964 // push $src.hi
2965 emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg));
2966 // push $src.lo
2967 emit_opcode(cbuf, 0x50+$src$$reg );
2968 // fild 64-bits at [SP]
2969 emit_opcode(cbuf,0xdf);
2970 emit_d8(cbuf, 0x6C);
2971 emit_d8(cbuf, 0x24);
2972 emit_d8(cbuf, 0x00);
2973 %}
2974
2975 enc_class long_int_multiply( eADXRegL dst, nadxRegI src) %{
2976 // Basic idea: long = (long)int * (long)int
2977 // IMUL EDX:EAX, src
2978 emit_opcode( cbuf, 0xF7 );
2979 emit_rm( cbuf, 0x3, 0x5, $src$$reg);
2980 %}
2981
2982 enc_class long_uint_multiply( eADXRegL dst, nadxRegI src) %{
2983 // Basic Idea: long = (int & 0xffffffffL) * (int & 0xffffffffL)
2984 // MUL EDX:EAX, src
2985 emit_opcode( cbuf, 0xF7 );
2986 emit_rm( cbuf, 0x3, 0x4, $src$$reg);
2987 %}
2988
2989 enc_class long_multiply( eADXRegL dst, eRegL src, eRegI tmp ) %{
2990 // Basic idea: lo(result) = lo(x_lo * y_lo)
2991 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
2992 // MOV $tmp,$src.lo
2993 encode_Copy( cbuf, $tmp$$reg, $src$$reg );
2994 // IMUL $tmp,EDX
2995 emit_opcode( cbuf, 0x0F );
2996 emit_opcode( cbuf, 0xAF );
2997 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
2998 // MOV EDX,$src.hi
2999 encode_Copy( cbuf, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg) );
3000 // IMUL EDX,EAX
3001 emit_opcode( cbuf, 0x0F );
3002 emit_opcode( cbuf, 0xAF );
3003 emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg );
3004 // ADD $tmp,EDX
3005 emit_opcode( cbuf, 0x03 );
3006 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
3007 // MUL EDX:EAX,$src.lo
3008 emit_opcode( cbuf, 0xF7 );
3009 emit_rm( cbuf, 0x3, 0x4, $src$$reg );
3010 // ADD EDX,ESI
3011 emit_opcode( cbuf, 0x03 );
3012 emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $tmp$$reg );
3013 %}
3014
3015 enc_class long_multiply_con( eADXRegL dst, immL_127 src, eRegI tmp ) %{
3016 // Basic idea: lo(result) = lo(src * y_lo)
3017 // hi(result) = hi(src * y_lo) + lo(src * y_hi)
3018 // IMUL $tmp,EDX,$src
3019 emit_opcode( cbuf, 0x6B );
3020 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
3021 emit_d8( cbuf, (int)$src$$constant );
3022 // MOV EDX,$src
3023 emit_opcode(cbuf, 0xB8 + EDX_enc);
3024 emit_d32( cbuf, (int)$src$$constant );
3025 // MUL EDX:EAX,EDX
3026 emit_opcode( cbuf, 0xF7 );
3027 emit_rm( cbuf, 0x3, 0x4, EDX_enc );
3028 // ADD EDX,ESI
3029 emit_opcode( cbuf, 0x03 );
3030 emit_rm( cbuf, 0x3, EDX_enc, $tmp$$reg );
3031 %}
3032
3033 enc_class long_div( eRegL src1, eRegL src2 ) %{
3034 // PUSH src1.hi
3035 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) );
3036 // PUSH src1.lo
3037 emit_opcode(cbuf, 0x50+$src1$$reg );
3038 // PUSH src2.hi
3039 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) );
3040 // PUSH src2.lo
3041 emit_opcode(cbuf, 0x50+$src2$$reg );
3042 // CALL directly to the runtime
3043 cbuf.set_inst_mark();
3044 emit_opcode(cbuf,0xE8); // Call into runtime
3045 emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::ldiv) - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
3046 // Restore stack
3047 emit_opcode(cbuf, 0x83); // add SP, #framesize
3048 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
3049 emit_d8(cbuf, 4*4);
3050 %}
3051
3052 enc_class long_mod( eRegL src1, eRegL src2 ) %{
3053 // PUSH src1.hi
3054 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) );
3055 // PUSH src1.lo
3056 emit_opcode(cbuf, 0x50+$src1$$reg );
3057 // PUSH src2.hi
3058 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) );
3059 // PUSH src2.lo
3060 emit_opcode(cbuf, 0x50+$src2$$reg );
3061 // CALL directly to the runtime
3062 cbuf.set_inst_mark();
3063 emit_opcode(cbuf,0xE8); // Call into runtime
3064 emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::lrem ) - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
3065 // Restore stack
3066 emit_opcode(cbuf, 0x83); // add SP, #framesize
3067 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
3068 emit_d8(cbuf, 4*4);
3069 %}
3070
3071 enc_class long_cmp_flags0( eRegL src, eRegI tmp ) %{
3072 // MOV $tmp,$src.lo
3073 emit_opcode(cbuf, 0x8B);
3074 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg);
3075 // OR $tmp,$src.hi
3076 emit_opcode(cbuf, 0x0B);
3077 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg));
3078 %}
3079
3080 enc_class long_cmp_flags1( eRegL src1, eRegL src2 ) %{
3081 // CMP $src1.lo,$src2.lo
3082 emit_opcode( cbuf, 0x3B );
3083 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
3084 // JNE,s skip
3085 emit_cc(cbuf, 0x70, 0x5);
3086 emit_d8(cbuf,2);
3087 // CMP $src1.hi,$src2.hi
3088 emit_opcode( cbuf, 0x3B );
3089 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) );
3090 %}
3091
3092 enc_class long_cmp_flags2( eRegL src1, eRegL src2, eRegI tmp ) %{
3093 // CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits
3094 emit_opcode( cbuf, 0x3B );
3095 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
3096 // MOV $tmp,$src1.hi
3097 emit_opcode( cbuf, 0x8B );
3098 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src1$$reg) );
3099 // SBB $tmp,$src2.hi\t! Compute flags for long compare
3100 emit_opcode( cbuf, 0x1B );
3101 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src2$$reg) );
3102 %}
3103
3104 enc_class long_cmp_flags3( eRegL src, eRegI tmp ) %{
3105 // XOR $tmp,$tmp
3106 emit_opcode(cbuf,0x33); // XOR
3107 emit_rm(cbuf,0x3, $tmp$$reg, $tmp$$reg);
3108 // CMP $tmp,$src.lo
3109 emit_opcode( cbuf, 0x3B );
3110 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg );
3111 // SBB $tmp,$src.hi
3112 emit_opcode( cbuf, 0x1B );
3113 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg) );
3114 %}
3115
3116 // Sniff, sniff... smells like Gnu Superoptimizer
3117 enc_class neg_long( eRegL dst ) %{
3118 emit_opcode(cbuf,0xF7); // NEG hi
3119 emit_rm (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg));
3120 emit_opcode(cbuf,0xF7); // NEG lo
3121 emit_rm (cbuf,0x3, 0x3, $dst$$reg );
3122 emit_opcode(cbuf,0x83); // SBB hi,0
3123 emit_rm (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg));
3124 emit_d8 (cbuf,0 );
3125 %}
3126
3127 enc_class movq_ld(regXD dst, memory mem) %{
3128 MacroAssembler _masm(&cbuf);
3129 __ movq($dst$$XMMRegister, $mem$$Address);
3130 %}
3131
3132 enc_class movq_st(memory mem, regXD src) %{
3133 MacroAssembler _masm(&cbuf);
3134 __ movq($mem$$Address, $src$$XMMRegister);
3135 %}
3136
3137 enc_class pshufd_8x8(regX dst, regX src) %{
3138 MacroAssembler _masm(&cbuf);
3139
3140 encode_CopyXD(cbuf, $dst$$reg, $src$$reg);
3141 __ punpcklbw(as_XMMRegister($dst$$reg), as_XMMRegister($dst$$reg));
3142 __ pshuflw(as_XMMRegister($dst$$reg), as_XMMRegister($dst$$reg), 0x00);
3143 %}
3144
3145 enc_class pshufd_4x16(regX dst, regX src) %{
3146 MacroAssembler _masm(&cbuf);
3147
3148 __ pshuflw(as_XMMRegister($dst$$reg), as_XMMRegister($src$$reg), 0x00);
3149 %}
3150
3151 enc_class pshufd(regXD dst, regXD src, int mode) %{
3152 MacroAssembler _masm(&cbuf);
3153
3154 __ pshufd(as_XMMRegister($dst$$reg), as_XMMRegister($src$$reg), $mode);
3155 %}
3156
3157 enc_class pxor(regXD dst, regXD src) %{
3158 MacroAssembler _masm(&cbuf);
3159
3160 __ pxor(as_XMMRegister($dst$$reg), as_XMMRegister($src$$reg));
3161 %}
3162
3163 enc_class mov_i2x(regXD dst, eRegI src) %{
3164 MacroAssembler _masm(&cbuf);
3165
3166 __ movdl(as_XMMRegister($dst$$reg), as_Register($src$$reg));
3167 %}
3168
3169
3170 // Because the transitions from emitted code to the runtime
3171 // monitorenter/exit helper stubs are so slow it's critical that
3172 // we inline both the stack-locking fast-path and the inflated fast path.
3173 //
3174 // See also: cmpFastLock and cmpFastUnlock.
3175 //
3176 // What follows is a specialized inline transliteration of the code
3177 // in slow_enter() and slow_exit(). If we're concerned about I$ bloat
3178 // another option would be to emit TrySlowEnter and TrySlowExit methods
3179 // at startup-time. These methods would accept arguments as
3180 // (rax,=Obj, rbx=Self, rcx=box, rdx=Scratch) and return success-failure
3181 // indications in the icc.ZFlag. Fast_Lock and Fast_Unlock would simply
3182 // marshal the arguments and emit calls to TrySlowEnter and TrySlowExit.
3183 // In practice, however, the # of lock sites is bounded and is usually small.
3184 // Besides the call overhead, TrySlowEnter and TrySlowExit might suffer
3185 // if the processor uses simple bimodal branch predictors keyed by EIP
3186 // Since the helper routines would be called from multiple synchronization
3187 // sites.
3188 //
3189 // An even better approach would be write "MonitorEnter()" and "MonitorExit()"
3190 // in java - using j.u.c and unsafe - and just bind the lock and unlock sites
3191 // to those specialized methods. That'd give us a mostly platform-independent
3192 // implementation that the JITs could optimize and inline at their pleasure.
3193 // Done correctly, the only time we'd need to cross to native could would be
3194 // to park() or unpark() threads. We'd also need a few more unsafe operators
3195 // to (a) prevent compiler-JIT reordering of non-volatile accesses, and
3196 // (b) explicit barriers or fence operations.
3197 //
3198 // TODO:
3199 //
3200 // * Arrange for C2 to pass "Self" into Fast_Lock and Fast_Unlock in one of the registers (scr).
3201 // This avoids manifesting the Self pointer in the Fast_Lock and Fast_Unlock terminals.
3202 // Given TLAB allocation, Self is usually manifested in a register, so passing it into
3203 // the lock operators would typically be faster than reifying Self.
3204 //
3205 // * Ideally I'd define the primitives as:
3206 // fast_lock (nax Obj, nax box, EAX tmp, nax scr) where box, tmp and scr are KILLED.
3207 // fast_unlock (nax Obj, EAX box, nax tmp) where box and tmp are KILLED
3208 // Unfortunately ADLC bugs prevent us from expressing the ideal form.
3209 // Instead, we're stuck with a rather awkward and brittle register assignments below.
3210 // Furthermore the register assignments are overconstrained, possibly resulting in
3211 // sub-optimal code near the synchronization site.
3212 //
3213 // * Eliminate the sp-proximity tests and just use "== Self" tests instead.
3214 // Alternately, use a better sp-proximity test.
3215 //
3216 // * Currently ObjectMonitor._Owner can hold either an sp value or a (THREAD *) value.
3217 // Either one is sufficient to uniquely identify a thread.
3218 // TODO: eliminate use of sp in _owner and use get_thread(tr) instead.
3219 //
3220 // * Intrinsify notify() and notifyAll() for the common cases where the
3221 // object is locked by the calling thread but the waitlist is empty.
3222 // avoid the expensive JNI call to JVM_Notify() and JVM_NotifyAll().
3223 //
3224 // * use jccb and jmpb instead of jcc and jmp to improve code density.
3225 // But beware of excessive branch density on AMD Opterons.
3226 //
3227 // * Both Fast_Lock and Fast_Unlock set the ICC.ZF to indicate success
3228 // or failure of the fast-path. If the fast-path fails then we pass
3229 // control to the slow-path, typically in C. In Fast_Lock and
3230 // Fast_Unlock we often branch to DONE_LABEL, just to find that C2
3231 // will emit a conditional branch immediately after the node.
3232 // So we have branches to branches and lots of ICC.ZF games.
3233 // Instead, it might be better to have C2 pass a "FailureLabel"
3234 // into Fast_Lock and Fast_Unlock. In the case of success, control
3235 // will drop through the node. ICC.ZF is undefined at exit.
3236 // In the case of failure, the node will branch directly to the
3237 // FailureLabel
3238
3239
3240 // obj: object to lock
3241 // box: on-stack box address (displaced header location) - KILLED
3242 // rax,: tmp -- KILLED
3243 // scr: tmp -- KILLED
3244 enc_class Fast_Lock( eRegP obj, eRegP box, eAXRegI tmp, eRegP scr ) %{
3245
3246 Register objReg = as_Register($obj$$reg);
3247 Register boxReg = as_Register($box$$reg);
3248 Register tmpReg = as_Register($tmp$$reg);
3249 Register scrReg = as_Register($scr$$reg);
3250
3251 // Ensure the register assignents are disjoint
3252 guarantee (objReg != boxReg, "") ;
3253 guarantee (objReg != tmpReg, "") ;
3254 guarantee (objReg != scrReg, "") ;
3255 guarantee (boxReg != tmpReg, "") ;
3256 guarantee (boxReg != scrReg, "") ;
3257 guarantee (tmpReg == as_Register(EAX_enc), "") ;
3258
3259 MacroAssembler masm(&cbuf);
3260
3261 if (_counters != NULL) {
3262 masm.atomic_incl(ExternalAddress((address) _counters->total_entry_count_addr()));
3263 }
3264 if (EmitSync & 1) {
3265 // set box->dhw = unused_mark (3)
3266 // Force all sync thru slow-path: slow_enter() and slow_exit()
3267 masm.movptr (Address(boxReg, 0), int32_t(markOopDesc::unused_mark())) ;
3268 masm.cmpptr (rsp, (int32_t)0) ;
3269 } else
3270 if (EmitSync & 2) {
3271 Label DONE_LABEL ;
3272 if (UseBiasedLocking) {
3273 // Note: tmpReg maps to the swap_reg argument and scrReg to the tmp_reg argument.
3274 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters);
3275 }
3276
3277 masm.movptr(tmpReg, Address(objReg, 0)) ; // fetch markword
3278 masm.orptr (tmpReg, 0x1);
3279 masm.movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS
3280 if (os::is_MP()) { masm.lock(); }
3281 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
3282 masm.jcc(Assembler::equal, DONE_LABEL);
3283 // Recursive locking
3284 masm.subptr(tmpReg, rsp);
3285 masm.andptr(tmpReg, (int32_t) 0xFFFFF003 );
3286 masm.movptr(Address(boxReg, 0), tmpReg);
3287 masm.bind(DONE_LABEL) ;
3288 } else {
3289 // Possible cases that we'll encounter in fast_lock
3290 // ------------------------------------------------
3291 // * Inflated
3292 // -- unlocked
3293 // -- Locked
3294 // = by self
3295 // = by other
3296 // * biased
3297 // -- by Self
3298 // -- by other
3299 // * neutral
3300 // * stack-locked
3301 // -- by self
3302 // = sp-proximity test hits
3303 // = sp-proximity test generates false-negative
3304 // -- by other
3305 //
3306
3307 Label IsInflated, DONE_LABEL, PopDone ;
3308
3309 // TODO: optimize away redundant LDs of obj->mark and improve the markword triage
3310 // order to reduce the number of conditional branches in the most common cases.
3311 // Beware -- there's a subtle invariant that fetch of the markword
3312 // at [FETCH], below, will never observe a biased encoding (*101b).
3313 // If this invariant is not held we risk exclusion (safety) failure.
3314 if (UseBiasedLocking && !UseOptoBiasInlining) {
3315 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters);
3316 }
3317
3318 masm.movptr(tmpReg, Address(objReg, 0)) ; // [FETCH]
3319 masm.testptr(tmpReg, 0x02) ; // Inflated v (Stack-locked or neutral)
3320 masm.jccb (Assembler::notZero, IsInflated) ;
3321
3322 // Attempt stack-locking ...
3323 masm.orptr (tmpReg, 0x1);
3324 masm.movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS
3325 if (os::is_MP()) { masm.lock(); }
3326 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
3327 if (_counters != NULL) {
3328 masm.cond_inc32(Assembler::equal,
3329 ExternalAddress((address)_counters->fast_path_entry_count_addr()));
3330 }
3331 masm.jccb (Assembler::equal, DONE_LABEL);
3332
3333 // Recursive locking
3334 masm.subptr(tmpReg, rsp);
3335 masm.andptr(tmpReg, 0xFFFFF003 );
3336 masm.movptr(Address(boxReg, 0), tmpReg);
3337 if (_counters != NULL) {
3338 masm.cond_inc32(Assembler::equal,
3339 ExternalAddress((address)_counters->fast_path_entry_count_addr()));
3340 }
3341 masm.jmp (DONE_LABEL) ;
3342
3343 masm.bind (IsInflated) ;
3344
3345 // The object is inflated.
3346 //
3347 // TODO-FIXME: eliminate the ugly use of manifest constants:
3348 // Use markOopDesc::monitor_value instead of "2".
3349 // use markOop::unused_mark() instead of "3".
3350 // The tmpReg value is an objectMonitor reference ORed with
3351 // markOopDesc::monitor_value (2). We can either convert tmpReg to an
3352 // objectmonitor pointer by masking off the "2" bit or we can just
3353 // use tmpReg as an objectmonitor pointer but bias the objectmonitor
3354 // field offsets with "-2" to compensate for and annul the low-order tag bit.
3355 //
3356 // I use the latter as it avoids AGI stalls.
3357 // As such, we write "mov r, [tmpReg+OFFSETOF(Owner)-2]"
3358 // instead of "mov r, [tmpReg+OFFSETOF(Owner)]".
3359 //
3360 #define OFFSET_SKEWED(f) ((ObjectMonitor::f ## _offset_in_bytes())-2)
3361
3362 // boxReg refers to the on-stack BasicLock in the current frame.
3363 // We'd like to write:
3364 // set box->_displaced_header = markOop::unused_mark(). Any non-0 value suffices.
3365 // This is convenient but results a ST-before-CAS penalty. The following CAS suffers
3366 // additional latency as we have another ST in the store buffer that must drain.
3367
3368 if (EmitSync & 8192) {
3369 masm.movptr(Address(boxReg, 0), 3) ; // results in ST-before-CAS penalty
3370 masm.get_thread (scrReg) ;
3371 masm.movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
3372 masm.movptr(tmpReg, NULL_WORD); // consider: xor vs mov
3373 if (os::is_MP()) { masm.lock(); }
3374 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3375 } else
3376 if ((EmitSync & 128) == 0) { // avoid ST-before-CAS
3377 masm.movptr(scrReg, boxReg) ;
3378 masm.movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
3379
3380 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
3381 if ((EmitSync & 2048) && VM_Version::supports_3dnow() && os::is_MP()) {
3382 // prefetchw [eax + Offset(_owner)-2]
3383 masm.prefetchw(Address(rax, ObjectMonitor::owner_offset_in_bytes()-2));
3384 }
3385
3386 if ((EmitSync & 64) == 0) {
3387 // Optimistic form: consider XORL tmpReg,tmpReg
3388 masm.movptr(tmpReg, NULL_WORD) ;
3389 } else {
3390 // Can suffer RTS->RTO upgrades on shared or cold $ lines
3391 // Test-And-CAS instead of CAS
3392 masm.movptr(tmpReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; // rax, = m->_owner
3393 masm.testptr(tmpReg, tmpReg) ; // Locked ?
3394 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3395 }
3396
3397 // Appears unlocked - try to swing _owner from null to non-null.
3398 // Ideally, I'd manifest "Self" with get_thread and then attempt
3399 // to CAS the register containing Self into m->Owner.
3400 // But we don't have enough registers, so instead we can either try to CAS
3401 // rsp or the address of the box (in scr) into &m->owner. If the CAS succeeds
3402 // we later store "Self" into m->Owner. Transiently storing a stack address
3403 // (rsp or the address of the box) into m->owner is harmless.
3404 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
3405 if (os::is_MP()) { masm.lock(); }
3406 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3407 masm.movptr(Address(scrReg, 0), 3) ; // box->_displaced_header = 3
3408 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3409 masm.get_thread (scrReg) ; // beware: clobbers ICCs
3410 masm.movptr(Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2), scrReg) ;
3411 masm.xorptr(boxReg, boxReg) ; // set icc.ZFlag = 1 to indicate success
3412
3413 // If the CAS fails we can either retry or pass control to the slow-path.
3414 // We use the latter tactic.
3415 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
3416 // If the CAS was successful ...
3417 // Self has acquired the lock
3418 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
3419 // Intentional fall-through into DONE_LABEL ...
3420 } else {
3421 masm.movptr(Address(boxReg, 0), 3) ; // results in ST-before-CAS penalty
3422 masm.movptr(boxReg, tmpReg) ;
3423
3424 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
3425 if ((EmitSync & 2048) && VM_Version::supports_3dnow() && os::is_MP()) {
3426 // prefetchw [eax + Offset(_owner)-2]
3427 masm.prefetchw(Address(rax, ObjectMonitor::owner_offset_in_bytes()-2));
3428 }
3429
3430 if ((EmitSync & 64) == 0) {
3431 // Optimistic form
3432 masm.xorptr (tmpReg, tmpReg) ;
3433 } else {
3434 // Can suffer RTS->RTO upgrades on shared or cold $ lines
3435 masm.movptr(tmpReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; // rax, = m->_owner
3436 masm.testptr(tmpReg, tmpReg) ; // Locked ?
3437 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3438 }
3439
3440 // Appears unlocked - try to swing _owner from null to non-null.
3441 // Use either "Self" (in scr) or rsp as thread identity in _owner.
3442 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
3443 masm.get_thread (scrReg) ;
3444 if (os::is_MP()) { masm.lock(); }
3445 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3446
3447 // If the CAS fails we can either retry or pass control to the slow-path.
3448 // We use the latter tactic.
3449 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
3450 // If the CAS was successful ...
3451 // Self has acquired the lock
3452 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
3453 // Intentional fall-through into DONE_LABEL ...
3454 }
3455
3456 // DONE_LABEL is a hot target - we'd really like to place it at the
3457 // start of cache line by padding with NOPs.
3458 // See the AMD and Intel software optimization manuals for the
3459 // most efficient "long" NOP encodings.
3460 // Unfortunately none of our alignment mechanisms suffice.
3461 masm.bind(DONE_LABEL);
3462
3463 // Avoid branch-to-branch on AMD processors
3464 // This appears to be superstition.
3465 if (EmitSync & 32) masm.nop() ;
3466
3467
3468 // At DONE_LABEL the icc ZFlag is set as follows ...
3469 // Fast_Unlock uses the same protocol.
3470 // ZFlag == 1 -> Success
3471 // ZFlag == 0 -> Failure - force control through the slow-path
3472 }
3473 %}
3474
3475 // obj: object to unlock
3476 // box: box address (displaced header location), killed. Must be EAX.
3477 // rbx,: killed tmp; cannot be obj nor box.
3478 //
3479 // Some commentary on balanced locking:
3480 //
3481 // Fast_Lock and Fast_Unlock are emitted only for provably balanced lock sites.
3482 // Methods that don't have provably balanced locking are forced to run in the
3483 // interpreter - such methods won't be compiled to use fast_lock and fast_unlock.
3484 // The interpreter provides two properties:
3485 // I1: At return-time the interpreter automatically and quietly unlocks any
3486 // objects acquired the current activation (frame). Recall that the
3487 // interpreter maintains an on-stack list of locks currently held by
3488 // a frame.
3489 // I2: If a method attempts to unlock an object that is not held by the
3490 // the frame the interpreter throws IMSX.
3491 //
3492 // Lets say A(), which has provably balanced locking, acquires O and then calls B().
3493 // B() doesn't have provably balanced locking so it runs in the interpreter.
3494 // Control returns to A() and A() unlocks O. By I1 and I2, above, we know that O
3495 // is still locked by A().
3496 //
3497 // The only other source of unbalanced locking would be JNI. The "Java Native Interface:
3498 // Programmer's Guide and Specification" claims that an object locked by jni_monitorenter
3499 // should not be unlocked by "normal" java-level locking and vice-versa. The specification
3500 // doesn't specify what will occur if a program engages in such mixed-mode locking, however.
3501
3502 enc_class Fast_Unlock( nabxRegP obj, eAXRegP box, eRegP tmp) %{
3503
3504 Register objReg = as_Register($obj$$reg);
3505 Register boxReg = as_Register($box$$reg);
3506 Register tmpReg = as_Register($tmp$$reg);
3507
3508 guarantee (objReg != boxReg, "") ;
3509 guarantee (objReg != tmpReg, "") ;
3510 guarantee (boxReg != tmpReg, "") ;
3511 guarantee (boxReg == as_Register(EAX_enc), "") ;
3512 MacroAssembler masm(&cbuf);
3513
3514 if (EmitSync & 4) {
3515 // Disable - inhibit all inlining. Force control through the slow-path
3516 masm.cmpptr (rsp, 0) ;
3517 } else
3518 if (EmitSync & 8) {
3519 Label DONE_LABEL ;
3520 if (UseBiasedLocking) {
3521 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL);
3522 }
3523 // classic stack-locking code ...
3524 masm.movptr(tmpReg, Address(boxReg, 0)) ;
3525 masm.testptr(tmpReg, tmpReg) ;
3526 masm.jcc (Assembler::zero, DONE_LABEL) ;
3527 if (os::is_MP()) { masm.lock(); }
3528 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses EAX which is box
3529 masm.bind(DONE_LABEL);
3530 } else {
3531 Label DONE_LABEL, Stacked, CheckSucc, Inflated ;
3532
3533 // Critically, the biased locking test must have precedence over
3534 // and appear before the (box->dhw == 0) recursive stack-lock test.
3535 if (UseBiasedLocking && !UseOptoBiasInlining) {
3536 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL);
3537 }
3538
3539 masm.cmpptr(Address(boxReg, 0), 0) ; // Examine the displaced header
3540 masm.movptr(tmpReg, Address(objReg, 0)) ; // Examine the object's markword
3541 masm.jccb (Assembler::zero, DONE_LABEL) ; // 0 indicates recursive stack-lock
3542
3543 masm.testptr(tmpReg, 0x02) ; // Inflated?
3544 masm.jccb (Assembler::zero, Stacked) ;
3545
3546 masm.bind (Inflated) ;
3547 // It's inflated.
3548 // Despite our balanced locking property we still check that m->_owner == Self
3549 // as java routines or native JNI code called by this thread might
3550 // have released the lock.
3551 // Refer to the comments in synchronizer.cpp for how we might encode extra
3552 // state in _succ so we can avoid fetching EntryList|cxq.
3553 //
3554 // I'd like to add more cases in fast_lock() and fast_unlock() --
3555 // such as recursive enter and exit -- but we have to be wary of
3556 // I$ bloat, T$ effects and BP$ effects.
3557 //
3558 // If there's no contention try a 1-0 exit. That is, exit without
3559 // a costly MEMBAR or CAS. See synchronizer.cpp for details on how
3560 // we detect and recover from the race that the 1-0 exit admits.
3561 //
3562 // Conceptually Fast_Unlock() must execute a STST|LDST "release" barrier
3563 // before it STs null into _owner, releasing the lock. Updates
3564 // to data protected by the critical section must be visible before
3565 // we drop the lock (and thus before any other thread could acquire
3566 // the lock and observe the fields protected by the lock).
3567 // IA32's memory-model is SPO, so STs are ordered with respect to
3568 // each other and there's no need for an explicit barrier (fence).
3569 // See also http://gee.cs.oswego.edu/dl/jmm/cookbook.html.
3570
3571 masm.get_thread (boxReg) ;
3572 if ((EmitSync & 4096) && VM_Version::supports_3dnow() && os::is_MP()) {
3573 // prefetchw [ebx + Offset(_owner)-2]
3574 masm.prefetchw(Address(rbx, ObjectMonitor::owner_offset_in_bytes()-2));
3575 }
3576
3577 // Note that we could employ various encoding schemes to reduce
3578 // the number of loads below (currently 4) to just 2 or 3.
3579 // Refer to the comments in synchronizer.cpp.
3580 // In practice the chain of fetches doesn't seem to impact performance, however.
3581 if ((EmitSync & 65536) == 0 && (EmitSync & 256)) {
3582 // Attempt to reduce branch density - AMD's branch predictor.
3583 masm.xorptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3584 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ;
3585 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ;
3586 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ;
3587 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3588 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ;
3589 masm.jmpb (DONE_LABEL) ;
3590 } else {
3591 masm.xorptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3592 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ;
3593 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3594 masm.movptr(boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ;
3595 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ;
3596 masm.jccb (Assembler::notZero, CheckSucc) ;
3597 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ;
3598 masm.jmpb (DONE_LABEL) ;
3599 }
3600
3601 // The Following code fragment (EmitSync & 65536) improves the performance of
3602 // contended applications and contended synchronization microbenchmarks.
3603 // Unfortunately the emission of the code - even though not executed - causes regressions
3604 // in scimark and jetstream, evidently because of $ effects. Replacing the code
3605 // with an equal number of never-executed NOPs results in the same regression.
3606 // We leave it off by default.
3607
3608 if ((EmitSync & 65536) != 0) {
3609 Label LSuccess, LGoSlowPath ;
3610
3611 masm.bind (CheckSucc) ;
3612
3613 // Optional pre-test ... it's safe to elide this
3614 if ((EmitSync & 16) == 0) {
3615 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), 0) ;
3616 masm.jccb (Assembler::zero, LGoSlowPath) ;
3617 }
3618
3619 // We have a classic Dekker-style idiom:
3620 // ST m->_owner = 0 ; MEMBAR; LD m->_succ
3621 // There are a number of ways to implement the barrier:
3622 // (1) lock:andl &m->_owner, 0
3623 // is fast, but mask doesn't currently support the "ANDL M,IMM32" form.
3624 // LOCK: ANDL [ebx+Offset(_Owner)-2], 0
3625 // Encodes as 81 31 OFF32 IMM32 or 83 63 OFF8 IMM8
3626 // (2) If supported, an explicit MFENCE is appealing.
3627 // In older IA32 processors MFENCE is slower than lock:add or xchg
3628 // particularly if the write-buffer is full as might be the case if
3629 // if stores closely precede the fence or fence-equivalent instruction.
3630 // In more modern implementations MFENCE appears faster, however.
3631 // (3) In lieu of an explicit fence, use lock:addl to the top-of-stack
3632 // The $lines underlying the top-of-stack should be in M-state.
3633 // The locked add instruction is serializing, of course.
3634 // (4) Use xchg, which is serializing
3635 // mov boxReg, 0; xchgl boxReg, [tmpReg + Offset(_owner)-2] also works
3636 // (5) ST m->_owner = 0 and then execute lock:orl &m->_succ, 0.
3637 // The integer condition codes will tell us if succ was 0.
3638 // Since _succ and _owner should reside in the same $line and
3639 // we just stored into _owner, it's likely that the $line
3640 // remains in M-state for the lock:orl.
3641 //
3642 // We currently use (3), although it's likely that switching to (2)
3643 // is correct for the future.
3644
3645 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ;
3646 if (os::is_MP()) {
3647 if (VM_Version::supports_sse2() && 1 == FenceInstruction) {
3648 masm.mfence();
3649 } else {
3650 masm.lock () ; masm.addptr(Address(rsp, 0), 0) ;
3651 }
3652 }
3653 // Ratify _succ remains non-null
3654 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), 0) ;
3655 masm.jccb (Assembler::notZero, LSuccess) ;
3656
3657 masm.xorptr(boxReg, boxReg) ; // box is really EAX
3658 if (os::is_MP()) { masm.lock(); }
3659 masm.cmpxchgptr(rsp, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2));
3660 masm.jccb (Assembler::notEqual, LSuccess) ;
3661 // Since we're low on registers we installed rsp as a placeholding in _owner.
3662 // Now install Self over rsp. This is safe as we're transitioning from
3663 // non-null to non=null
3664 masm.get_thread (boxReg) ;
3665 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), boxReg) ;
3666 // Intentional fall-through into LGoSlowPath ...
3667
3668 masm.bind (LGoSlowPath) ;
3669 masm.orptr(boxReg, 1) ; // set ICC.ZF=0 to indicate failure
3670 masm.jmpb (DONE_LABEL) ;
3671
3672 masm.bind (LSuccess) ;
3673 masm.xorptr(boxReg, boxReg) ; // set ICC.ZF=1 to indicate success
3674 masm.jmpb (DONE_LABEL) ;
3675 }
3676
3677 masm.bind (Stacked) ;
3678 // It's not inflated and it's not recursively stack-locked and it's not biased.
3679 // It must be stack-locked.
3680 // Try to reset the header to displaced header.
3681 // The "box" value on the stack is stable, so we can reload
3682 // and be assured we observe the same value as above.
3683 masm.movptr(tmpReg, Address(boxReg, 0)) ;
3684 if (os::is_MP()) { masm.lock(); }
3685 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses EAX which is box
3686 // Intention fall-thru into DONE_LABEL
3687
3688
3689 // DONE_LABEL is a hot target - we'd really like to place it at the
3690 // start of cache line by padding with NOPs.
3691 // See the AMD and Intel software optimization manuals for the
3692 // most efficient "long" NOP encodings.
3693 // Unfortunately none of our alignment mechanisms suffice.
3694 if ((EmitSync & 65536) == 0) {
3695 masm.bind (CheckSucc) ;
3696 }
3697 masm.bind(DONE_LABEL);
3698
3699 // Avoid branch to branch on AMD processors
3700 if (EmitSync & 32768) { masm.nop() ; }
3701 }
3702 %}
3703
3704 enc_class enc_String_Compare(eDIRegP str1, eSIRegP str2, regXD tmp1, regXD tmp2,
3705 eAXRegI tmp3, eBXRegI tmp4, eCXRegI result) %{
3706 Label ECX_GOOD_LABEL, LENGTH_DIFF_LABEL,
3707 POP_LABEL, DONE_LABEL, CONT_LABEL,
3708 WHILE_HEAD_LABEL;
3709 MacroAssembler masm(&cbuf);
3710
3711 XMMRegister tmp1Reg = as_XMMRegister($tmp1$$reg);
3712 XMMRegister tmp2Reg = as_XMMRegister($tmp2$$reg);
3713
3714 // Get the first character position in both strings
3715 // [8] char array, [12] offset, [16] count
3716 int value_offset = java_lang_String::value_offset_in_bytes();
3717 int offset_offset = java_lang_String::offset_offset_in_bytes();
3718 int count_offset = java_lang_String::count_offset_in_bytes();
3719 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR);
3720
3721 masm.movptr(rax, Address(rsi, value_offset));
3722 masm.movl(rcx, Address(rsi, offset_offset));
3723 masm.lea(rax, Address(rax, rcx, Address::times_2, base_offset));
3724 masm.movptr(rbx, Address(rdi, value_offset));
3725 masm.movl(rcx, Address(rdi, offset_offset));
3726 masm.lea(rbx, Address(rbx, rcx, Address::times_2, base_offset));
3727
3728 // Compute the minimum of the string lengths(rsi) and the
3729 // difference of the string lengths (stack)
3730
3731 if (VM_Version::supports_cmov()) {
3732 masm.movl(rdi, Address(rdi, count_offset));
3733 masm.movl(rsi, Address(rsi, count_offset));
3734 masm.movl(rcx, rdi);
3735 masm.subl(rdi, rsi);
3736 masm.push(rdi);
3737 masm.cmovl(Assembler::lessEqual, rsi, rcx);
3738 } else {
3739 masm.movl(rdi, Address(rdi, count_offset));
3740 masm.movl(rcx, Address(rsi, count_offset));
3741 masm.movl(rsi, rdi);
3742 masm.subl(rdi, rcx);
3743 masm.push(rdi);
3744 masm.jccb(Assembler::lessEqual, ECX_GOOD_LABEL);
3745 masm.movl(rsi, rcx);
3746 // rsi holds min, rcx is unused
3747 }
3748
3749 // Is the minimum length zero?
3750 masm.bind(ECX_GOOD_LABEL);
3751 masm.testl(rsi, rsi);
3752 masm.jcc(Assembler::zero, LENGTH_DIFF_LABEL);
3753
3754 // Load first characters
3755 masm.load_unsigned_short(rcx, Address(rbx, 0));
3756 masm.load_unsigned_short(rdi, Address(rax, 0));
3757
3758 // Compare first characters
3759 masm.subl(rcx, rdi);
3760 masm.jcc(Assembler::notZero, POP_LABEL);
3761 masm.decrementl(rsi);
3762 masm.jcc(Assembler::zero, LENGTH_DIFF_LABEL);
3763
3764 {
3765 // Check after comparing first character to see if strings are equivalent
3766 Label LSkip2;
3767 // Check if the strings start at same location
3768 masm.cmpptr(rbx,rax);
3769 masm.jccb(Assembler::notEqual, LSkip2);
3770
3771 // Check if the length difference is zero (from stack)
3772 masm.cmpl(Address(rsp, 0), 0x0);
3773 masm.jcc(Assembler::equal, LENGTH_DIFF_LABEL);
3774
3775 // Strings might not be equivalent
3776 masm.bind(LSkip2);
3777 }
3778
3779 // Advance to next character
3780 masm.addptr(rax, 2);
3781 masm.addptr(rbx, 2);
3782
3783 if (UseSSE42Intrinsics) {
3784 // With SSE4.2, use double quad vector compare
3785 Label COMPARE_VECTORS, VECTOR_NOT_EQUAL, COMPARE_TAIL;
3786 // Setup to compare 16-byte vectors
3787 masm.movl(rdi, rsi);
3788 masm.andl(rsi, 0xfffffff8); // rsi holds the vector count
3789 masm.andl(rdi, 0x00000007); // rdi holds the tail count
3790 masm.testl(rsi, rsi);
3791 masm.jccb(Assembler::zero, COMPARE_TAIL);
3792
3793 masm.lea(rax, Address(rax, rsi, Address::times_2));
3794 masm.lea(rbx, Address(rbx, rsi, Address::times_2));
3795 masm.negl(rsi);
3796
3797 masm.bind(COMPARE_VECTORS);
3798 masm.movdqu(tmp1Reg, Address(rax, rsi, Address::times_2));
3799 masm.movdqu(tmp2Reg, Address(rbx, rsi, Address::times_2));
3800 masm.pxor(tmp1Reg, tmp2Reg);
3801 masm.ptest(tmp1Reg, tmp1Reg);
3802 masm.jccb(Assembler::notZero, VECTOR_NOT_EQUAL);
3803 masm.addl(rsi, 8);
3804 masm.jcc(Assembler::notZero, COMPARE_VECTORS);
3805 masm.jmpb(COMPARE_TAIL);
3806
3807 // Mismatched characters in the vectors
3808 masm.bind(VECTOR_NOT_EQUAL);
3809 masm.lea(rax, Address(rax, rsi, Address::times_2));
3810 masm.lea(rbx, Address(rbx, rsi, Address::times_2));
3811 masm.movl(rdi, 8);
3812
3813 // Compare tail (< 8 chars), or rescan last vectors to
3814 // find 1st mismatched characters
3815 masm.bind(COMPARE_TAIL);
3816 masm.testl(rdi, rdi);
3817 masm.jccb(Assembler::zero, LENGTH_DIFF_LABEL);
3818 masm.movl(rsi, rdi);
3819 // Fallthru to tail compare
3820 }
3821
3822 //Shift rax, and rbx, to the end of the arrays, negate min
3823 masm.lea(rax, Address(rax, rsi, Address::times_2, 0));
3824 masm.lea(rbx, Address(rbx, rsi, Address::times_2, 0));
3825 masm.negl(rsi);
3826
3827 // Compare the rest of the characters
3828 masm.bind(WHILE_HEAD_LABEL);
3829 masm.load_unsigned_short(rcx, Address(rbx, rsi, Address::times_2, 0));
3830 masm.load_unsigned_short(rdi, Address(rax, rsi, Address::times_2, 0));
3831 masm.subl(rcx, rdi);
3832 masm.jccb(Assembler::notZero, POP_LABEL);
3833 masm.incrementl(rsi);
3834 masm.jcc(Assembler::notZero, WHILE_HEAD_LABEL);
3835
3836 // Strings are equal up to min length. Return the length difference.
3837 masm.bind(LENGTH_DIFF_LABEL);
3838 masm.pop(rcx);
3839 masm.jmpb(DONE_LABEL);
3840
3841 // Discard the stored length difference
3842 masm.bind(POP_LABEL);
3843 masm.addptr(rsp, 4);
3844
3845 // That's it
3846 masm.bind(DONE_LABEL);
3847 %}
3848
3849 enc_class enc_String_Equals(eDIRegP str1, eSIRegP str2, regXD tmp1, regXD tmp2,
3850 eBXRegI tmp3, eCXRegI tmp4, eAXRegI result) %{
3851 Label RET_TRUE, RET_FALSE, DONE, COMPARE_VECTORS, COMPARE_CHAR;
3852 MacroAssembler masm(&cbuf);
3853
3854 XMMRegister tmp1Reg = as_XMMRegister($tmp1$$reg);
3855 XMMRegister tmp2Reg = as_XMMRegister($tmp2$$reg);
3856
3857 int value_offset = java_lang_String::value_offset_in_bytes();
3858 int offset_offset = java_lang_String::offset_offset_in_bytes();
3859 int count_offset = java_lang_String::count_offset_in_bytes();
3860 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR);
3861
3862 // does source == target string?
3863 masm.cmpptr(rdi, rsi);
3864 masm.jcc(Assembler::equal, RET_TRUE);
3865
3866 // get and compare counts
3867 masm.movl(rcx, Address(rdi, count_offset));
3868 masm.movl(rax, Address(rsi, count_offset));
3869 masm.cmpl(rcx, rax);
3870 masm.jcc(Assembler::notEqual, RET_FALSE);
3871 masm.testl(rax, rax);
3872 masm.jcc(Assembler::zero, RET_TRUE);
3873
3874 // get source string offset and value
3875 masm.movptr(rbx, Address(rsi, value_offset));
3876 masm.movl(rax, Address(rsi, offset_offset));
3877 masm.leal(rsi, Address(rbx, rax, Address::times_2, base_offset));
3878
3879 // get compare string offset and value
3880 masm.movptr(rbx, Address(rdi, value_offset));
3881 masm.movl(rax, Address(rdi, offset_offset));
3882 masm.leal(rdi, Address(rbx, rax, Address::times_2, base_offset));
3883
3884 // Set byte count
3885 masm.shll(rcx, 1);
3886 masm.movl(rax, rcx);
3887
3888 if (UseSSE42Intrinsics) {
3889 // With SSE4.2, use double quad vector compare
3890 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
3891 // Compare 16-byte vectors
3892 masm.andl(rcx, 0xfffffff0); // vector count (in bytes)
3893 masm.andl(rax, 0x0000000e); // tail count (in bytes)
3894 masm.testl(rcx, rcx);
3895 masm.jccb(Assembler::zero, COMPARE_TAIL);
3896 masm.lea(rdi, Address(rdi, rcx, Address::times_1));
3897 masm.lea(rsi, Address(rsi, rcx, Address::times_1));
3898 masm.negl(rcx);
3899
3900 masm.bind(COMPARE_WIDE_VECTORS);
3901 masm.movdqu(tmp1Reg, Address(rdi, rcx, Address::times_1));
3902 masm.movdqu(tmp2Reg, Address(rsi, rcx, Address::times_1));
3903 masm.pxor(tmp1Reg, tmp2Reg);
3904 masm.ptest(tmp1Reg, tmp1Reg);
3905 masm.jccb(Assembler::notZero, RET_FALSE);
3906 masm.addl(rcx, 16);
3907 masm.jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
3908 masm.bind(COMPARE_TAIL);
3909 masm.movl(rcx, rax);
3910 // Fallthru to tail compare
3911 }
3912
3913 // Compare 4-byte vectors
3914 masm.andl(rcx, 0xfffffffc); // vector count (in bytes)
3915 masm.andl(rax, 0x00000002); // tail char (in bytes)
3916 masm.testl(rcx, rcx);
3917 masm.jccb(Assembler::zero, COMPARE_CHAR);
3918 masm.lea(rdi, Address(rdi, rcx, Address::times_1));
3919 masm.lea(rsi, Address(rsi, rcx, Address::times_1));
3920 masm.negl(rcx);
3921
3922 masm.bind(COMPARE_VECTORS);
3923 masm.movl(rbx, Address(rdi, rcx, Address::times_1));
3924 masm.cmpl(rbx, Address(rsi, rcx, Address::times_1));
3925 masm.jccb(Assembler::notEqual, RET_FALSE);
3926 masm.addl(rcx, 4);
3927 masm.jcc(Assembler::notZero, COMPARE_VECTORS);
3928
3929 // Compare trailing char (final 2 bytes), if any
3930 masm.bind(COMPARE_CHAR);
3931 masm.testl(rax, rax);
3932 masm.jccb(Assembler::zero, RET_TRUE);
3933 masm.load_unsigned_short(rbx, Address(rdi, 0));
3934 masm.load_unsigned_short(rcx, Address(rsi, 0));
3935 masm.cmpl(rbx, rcx);
3936 masm.jccb(Assembler::notEqual, RET_FALSE);
3937
3938 masm.bind(RET_TRUE);
3939 masm.movl(rax, 1); // return true
3940 masm.jmpb(DONE);
3941
3942 masm.bind(RET_FALSE);
3943 masm.xorl(rax, rax); // return false
3944
3945 masm.bind(DONE);
3946 %}
3947
3948 enc_class enc_String_IndexOf(eSIRegP str1, eDIRegP str2, regXD tmp1, eAXRegI tmp2,
3949 eCXRegI tmp3, eDXRegI tmp4, eBXRegI result) %{
3950 // SSE4.2 version
3951 Label LOAD_SUBSTR, PREP_FOR_SCAN, SCAN_TO_SUBSTR,
3952 SCAN_SUBSTR, RET_NEG_ONE, RET_NOT_FOUND, CLEANUP, DONE;
3953 MacroAssembler masm(&cbuf);
3954
3955 XMMRegister tmp1Reg = as_XMMRegister($tmp1$$reg);
3956
3957 // Get the first character position in both strings
3958 // [8] char array, [12] offset, [16] count
3959 int value_offset = java_lang_String::value_offset_in_bytes();
3960 int offset_offset = java_lang_String::offset_offset_in_bytes();
3961 int count_offset = java_lang_String::count_offset_in_bytes();
3962 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR);
3963
3964 // Get counts for string and substr
3965 masm.movl(rdx, Address(rsi, count_offset));
3966 masm.movl(rax, Address(rdi, count_offset));
3967 // Check for substr count > string count
3968 masm.cmpl(rax, rdx);
3969 masm.jcc(Assembler::greater, RET_NEG_ONE);
3970
3971 // Start the indexOf operation
3972 // Get start addr of string
3973 masm.movptr(rbx, Address(rsi, value_offset));
3974 masm.movl(rcx, Address(rsi, offset_offset));
3975 masm.lea(rsi, Address(rbx, rcx, Address::times_2, base_offset));
3976 masm.push(rsi);
3977
3978 // Get start addr of substr
3979 masm.movptr(rbx, Address(rdi, value_offset));
3980 masm.movl(rcx, Address(rdi, offset_offset));
3981 masm.lea(rdi, Address(rbx, rcx, Address::times_2, base_offset));
3982 masm.push(rdi);
3983 masm.push(rax);
3984 masm.jmpb(PREP_FOR_SCAN);
3985
3986 // Substr count saved at sp
3987 // Substr saved at sp+4
3988 // String saved at sp+8
3989
3990 // Prep to load substr for scan
3991 masm.bind(LOAD_SUBSTR);
3992 masm.movptr(rdi, Address(rsp, 4));
3993 masm.movl(rax, Address(rsp, 0));
3994
3995 // Load substr
3996 masm.bind(PREP_FOR_SCAN);
3997 masm.movdqu(tmp1Reg, Address(rdi, 0));
3998 masm.addl(rdx, 8); // prime the loop
3999 masm.subptr(rsi, 16);
4000
4001 // Scan string for substr in 16-byte vectors
4002 masm.bind(SCAN_TO_SUBSTR);
4003 masm.subl(rdx, 8);
4004 masm.addptr(rsi, 16);
4005 masm.pcmpestri(tmp1Reg, Address(rsi, 0), 0x0d);
4006 masm.jcc(Assembler::above, SCAN_TO_SUBSTR); // CF == 0 && ZF == 0
4007 masm.jccb(Assembler::aboveEqual, RET_NOT_FOUND); // CF == 0
4008
4009 // Fallthru: found a potential substr
4010
4011 // Make sure string is still long enough
4012 masm.subl(rdx, rcx);
4013 masm.cmpl(rdx, rax);
4014 masm.jccb(Assembler::negative, RET_NOT_FOUND);
4015 // Compute start addr of substr
4016 masm.lea(rsi, Address(rsi, rcx, Address::times_2));
4017 masm.movptr(rbx, rsi);
4018
4019 // Compare potential substr
4020 masm.addl(rdx, 8); // prime the loop
4021 masm.addl(rax, 8);
4022 masm.subptr(rsi, 16);
4023 masm.subptr(rdi, 16);
4024
4025 // Scan 16-byte vectors of string and substr
4026 masm.bind(SCAN_SUBSTR);
4027 masm.subl(rax, 8);
4028 masm.subl(rdx, 8);
4029 masm.addptr(rsi, 16);
4030 masm.addptr(rdi, 16);
4031 masm.movdqu(tmp1Reg, Address(rdi, 0));
4032 masm.pcmpestri(tmp1Reg, Address(rsi, 0), 0x0d);
4033 masm.jcc(Assembler::noOverflow, LOAD_SUBSTR); // OF == 0
4034 masm.jcc(Assembler::positive, SCAN_SUBSTR); // SF == 0
4035
4036 // Compute substr offset
4037 masm.movptr(rsi, Address(rsp, 8));
4038 masm.subptr(rbx, rsi);
4039 masm.shrl(rbx, 1);
4040 masm.jmpb(CLEANUP);
4041
4042 masm.bind(RET_NEG_ONE);
4043 masm.movl(rbx, -1);
4044 masm.jmpb(DONE);
4045
4046 masm.bind(RET_NOT_FOUND);
4047 masm.movl(rbx, -1);
4048
4049 masm.bind(CLEANUP);
4050 masm.addptr(rsp, 12);
4051
4052 masm.bind(DONE);
4053 %}
4054
4055 enc_class enc_Array_Equals(eDIRegP ary1, eSIRegP ary2, regXD tmp1, regXD tmp2,
4056 eBXRegI tmp3, eDXRegI tmp4, eAXRegI result) %{
4057 Label TRUE_LABEL, FALSE_LABEL, DONE, COMPARE_VECTORS, COMPARE_CHAR;
4058 MacroAssembler masm(&cbuf);
4059
4060 XMMRegister tmp1Reg = as_XMMRegister($tmp1$$reg);
4061 XMMRegister tmp2Reg = as_XMMRegister($tmp2$$reg);
4062 Register ary1Reg = as_Register($ary1$$reg);
4063 Register ary2Reg = as_Register($ary2$$reg);
4064 Register tmp3Reg = as_Register($tmp3$$reg);
4065 Register tmp4Reg = as_Register($tmp4$$reg);
4066 Register resultReg = as_Register($result$$reg);
4067
4068 int length_offset = arrayOopDesc::length_offset_in_bytes();
4069 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR);
4070
4071 // Check the input args
4072 masm.cmpptr(ary1Reg, ary2Reg);
4073 masm.jcc(Assembler::equal, TRUE_LABEL);
4074 masm.testptr(ary1Reg, ary1Reg);
4075 masm.jcc(Assembler::zero, FALSE_LABEL);
4076 masm.testptr(ary2Reg, ary2Reg);
4077 masm.jcc(Assembler::zero, FALSE_LABEL);
4078
4079 // Check the lengths
4080 masm.movl(tmp4Reg, Address(ary1Reg, length_offset));
4081 masm.movl(resultReg, Address(ary2Reg, length_offset));
4082 masm.cmpl(tmp4Reg, resultReg);
4083 masm.jcc(Assembler::notEqual, FALSE_LABEL);
4084 masm.testl(resultReg, resultReg);
4085 masm.jcc(Assembler::zero, TRUE_LABEL);
4086
4087 // Load array addrs
4088 masm.lea(ary1Reg, Address(ary1Reg, base_offset));
4089 masm.lea(ary2Reg, Address(ary2Reg, base_offset));
4090
4091 // Set byte count
4092 masm.shll(tmp4Reg, 1);
4093 masm.movl(resultReg, tmp4Reg);
4094
4095 if (UseSSE42Intrinsics) {
4096 // With SSE4.2, use double quad vector compare
4097 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
4098 // Compare 16-byte vectors
4099 masm.andl(tmp4Reg, 0xfffffff0); // vector count (in bytes)
4100 masm.andl(resultReg, 0x0000000e); // tail count (in bytes)
4101 masm.testl(tmp4Reg, tmp4Reg);
4102 masm.jccb(Assembler::zero, COMPARE_TAIL);
4103 masm.lea(ary1Reg, Address(ary1Reg, tmp4Reg, Address::times_1));
4104 masm.lea(ary2Reg, Address(ary2Reg, tmp4Reg, Address::times_1));
4105 masm.negl(tmp4Reg);
4106
4107 masm.bind(COMPARE_WIDE_VECTORS);
4108 masm.movdqu(tmp1Reg, Address(ary1Reg, tmp4Reg, Address::times_1));
4109 masm.movdqu(tmp2Reg, Address(ary2Reg, tmp4Reg, Address::times_1));
4110 masm.pxor(tmp1Reg, tmp2Reg);
4111 masm.ptest(tmp1Reg, tmp1Reg);
4112
4113 masm.jccb(Assembler::notZero, FALSE_LABEL);
4114 masm.addl(tmp4Reg, 16);
4115 masm.jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
4116 masm.bind(COMPARE_TAIL);
4117 masm.movl(tmp4Reg, resultReg);
4118 // Fallthru to tail compare
4119 }
4120
4121 // Compare 4-byte vectors
4122 masm.andl(tmp4Reg, 0xfffffffc); // vector count (in bytes)
4123 masm.andl(resultReg, 0x00000002); // tail char (in bytes)
4124 masm.testl(tmp4Reg, tmp4Reg);
4125 masm.jccb(Assembler::zero, COMPARE_CHAR);
4126 masm.lea(ary1Reg, Address(ary1Reg, tmp4Reg, Address::times_1));
4127 masm.lea(ary2Reg, Address(ary2Reg, tmp4Reg, Address::times_1));
4128 masm.negl(tmp4Reg);
4129
4130 masm.bind(COMPARE_VECTORS);
4131 masm.movl(tmp3Reg, Address(ary1Reg, tmp4Reg, Address::times_1));
4132 masm.cmpl(tmp3Reg, Address(ary2Reg, tmp4Reg, Address::times_1));
4133 masm.jccb(Assembler::notEqual, FALSE_LABEL);
4134 masm.addl(tmp4Reg, 4);
4135 masm.jcc(Assembler::notZero, COMPARE_VECTORS);
4136
4137 // Compare trailing char (final 2 bytes), if any
4138 masm.bind(COMPARE_CHAR);
4139 masm.testl(resultReg, resultReg);
4140 masm.jccb(Assembler::zero, TRUE_LABEL);
4141 masm.load_unsigned_short(tmp3Reg, Address(ary1Reg, 0));
4142 masm.load_unsigned_short(tmp4Reg, Address(ary2Reg, 0));
4143 masm.cmpl(tmp3Reg, tmp4Reg);
4144 masm.jccb(Assembler::notEqual, FALSE_LABEL);
4145
4146 masm.bind(TRUE_LABEL);
4147 masm.movl(resultReg, 1); // return true
4148 masm.jmpb(DONE);
4149
4150 masm.bind(FALSE_LABEL);
4151 masm.xorl(resultReg, resultReg); // return false
4152
4153 // That's it
4154 masm.bind(DONE);
4155 %}
4156
4157 enc_class enc_pop_rdx() %{
4158 emit_opcode(cbuf,0x5A);
4159 %}
4160
4161 enc_class enc_rethrow() %{
4162 cbuf.set_inst_mark();
4163 emit_opcode(cbuf, 0xE9); // jmp entry
4164 emit_d32_reloc(cbuf, (int)OptoRuntime::rethrow_stub() - ((int)cbuf.code_end())-4,
4165 runtime_call_Relocation::spec(), RELOC_IMM32 );
4166 %}
4167
4168
4169 // Convert a double to an int. Java semantics require we do complex
4170 // manglelations in the corner cases. So we set the rounding mode to
4171 // 'zero', store the darned double down as an int, and reset the
4172 // rounding mode to 'nearest'. The hardware throws an exception which
4173 // patches up the correct value directly to the stack.
4174 enc_class D2I_encoding( regD src ) %{
4175 // Flip to round-to-zero mode. We attempted to allow invalid-op
4176 // exceptions here, so that a NAN or other corner-case value will
4177 // thrown an exception (but normal values get converted at full speed).
4178 // However, I2C adapters and other float-stack manglers leave pending
4179 // invalid-op exceptions hanging. We would have to clear them before
4180 // enabling them and that is more expensive than just testing for the
4181 // invalid value Intel stores down in the corner cases.
4182 emit_opcode(cbuf,0xD9); // FLDCW trunc
4183 emit_opcode(cbuf,0x2D);
4184 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
4185 // Allocate a word
4186 emit_opcode(cbuf,0x83); // SUB ESP,4
4187 emit_opcode(cbuf,0xEC);
4188 emit_d8(cbuf,0x04);
4189 // Encoding assumes a double has been pushed into FPR0.
4190 // Store down the double as an int, popping the FPU stack
4191 emit_opcode(cbuf,0xDB); // FISTP [ESP]
4192 emit_opcode(cbuf,0x1C);
4193 emit_d8(cbuf,0x24);
4194 // Restore the rounding mode; mask the exception
4195 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode
4196 emit_opcode(cbuf,0x2D);
4197 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
4198 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
4199 : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
4200
4201 // Load the converted int; adjust CPU stack
4202 emit_opcode(cbuf,0x58); // POP EAX
4203 emit_opcode(cbuf,0x3D); // CMP EAX,imm
4204 emit_d32 (cbuf,0x80000000); // 0x80000000
4205 emit_opcode(cbuf,0x75); // JNE around_slow_call
4206 emit_d8 (cbuf,0x07); // Size of slow_call
4207 // Push src onto stack slow-path
4208 emit_opcode(cbuf,0xD9 ); // FLD ST(i)
4209 emit_d8 (cbuf,0xC0-1+$src$$reg );
4210 // CALL directly to the runtime
4211 cbuf.set_inst_mark();
4212 emit_opcode(cbuf,0xE8); // Call into runtime
4213 emit_d32_reloc(cbuf, (StubRoutines::d2i_wrapper() - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
4214 // Carry on here...
4215 %}
4216
4217 enc_class D2L_encoding( regD src ) %{
4218 emit_opcode(cbuf,0xD9); // FLDCW trunc
4219 emit_opcode(cbuf,0x2D);
4220 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
4221 // Allocate a word
4222 emit_opcode(cbuf,0x83); // SUB ESP,8
4223 emit_opcode(cbuf,0xEC);
4224 emit_d8(cbuf,0x08);
4225 // Encoding assumes a double has been pushed into FPR0.
4226 // Store down the double as a long, popping the FPU stack
4227 emit_opcode(cbuf,0xDF); // FISTP [ESP]
4228 emit_opcode(cbuf,0x3C);
4229 emit_d8(cbuf,0x24);
4230 // Restore the rounding mode; mask the exception
4231 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode
4232 emit_opcode(cbuf,0x2D);
4233 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
4234 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
4235 : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
4236
4237 // Load the converted int; adjust CPU stack
4238 emit_opcode(cbuf,0x58); // POP EAX
4239 emit_opcode(cbuf,0x5A); // POP EDX
4240 emit_opcode(cbuf,0x81); // CMP EDX,imm
4241 emit_d8 (cbuf,0xFA); // rdx
4242 emit_d32 (cbuf,0x80000000); // 0x80000000
4243 emit_opcode(cbuf,0x75); // JNE around_slow_call
4244 emit_d8 (cbuf,0x07+4); // Size of slow_call
4245 emit_opcode(cbuf,0x85); // TEST EAX,EAX
4246 emit_opcode(cbuf,0xC0); // 2/rax,/rax,
4247 emit_opcode(cbuf,0x75); // JNE around_slow_call
4248 emit_d8 (cbuf,0x07); // Size of slow_call
4249 // Push src onto stack slow-path
4250 emit_opcode(cbuf,0xD9 ); // FLD ST(i)
4251 emit_d8 (cbuf,0xC0-1+$src$$reg );
4252 // CALL directly to the runtime
4253 cbuf.set_inst_mark();
4254 emit_opcode(cbuf,0xE8); // Call into runtime
4255 emit_d32_reloc(cbuf, (StubRoutines::d2l_wrapper() - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
4256 // Carry on here...
4257 %}
4258
4259 enc_class X2L_encoding( regX src ) %{
4260 // Allocate a word
4261 emit_opcode(cbuf,0x83); // SUB ESP,8
4262 emit_opcode(cbuf,0xEC);
4263 emit_d8(cbuf,0x08);
4264
4265 emit_opcode (cbuf, 0xF3 ); // MOVSS [ESP], src
4266 emit_opcode (cbuf, 0x0F );
4267 emit_opcode (cbuf, 0x11 );
4268 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false);
4269
4270 emit_opcode(cbuf,0xD9 ); // FLD_S [ESP]
4271 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
4272
4273 emit_opcode(cbuf,0xD9); // FLDCW trunc
4274 emit_opcode(cbuf,0x2D);
4275 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
4276
4277 // Encoding assumes a double has been pushed into FPR0.
4278 // Store down the double as a long, popping the FPU stack
4279 emit_opcode(cbuf,0xDF); // FISTP [ESP]
4280 emit_opcode(cbuf,0x3C);
4281 emit_d8(cbuf,0x24);
4282
4283 // Restore the rounding mode; mask the exception
4284 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode
4285 emit_opcode(cbuf,0x2D);
4286 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
4287 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
4288 : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
4289
4290 // Load the converted int; adjust CPU stack
4291 emit_opcode(cbuf,0x58); // POP EAX
4292
4293 emit_opcode(cbuf,0x5A); // POP EDX
4294
4295 emit_opcode(cbuf,0x81); // CMP EDX,imm
4296 emit_d8 (cbuf,0xFA); // rdx
4297 emit_d32 (cbuf,0x80000000);// 0x80000000
4298
4299 emit_opcode(cbuf,0x75); // JNE around_slow_call
4300 emit_d8 (cbuf,0x13+4); // Size of slow_call
4301
4302 emit_opcode(cbuf,0x85); // TEST EAX,EAX
4303 emit_opcode(cbuf,0xC0); // 2/rax,/rax,
4304
4305 emit_opcode(cbuf,0x75); // JNE around_slow_call
4306 emit_d8 (cbuf,0x13); // Size of slow_call
4307
4308 // Allocate a word
4309 emit_opcode(cbuf,0x83); // SUB ESP,4
4310 emit_opcode(cbuf,0xEC);
4311 emit_d8(cbuf,0x04);
4312
4313 emit_opcode (cbuf, 0xF3 ); // MOVSS [ESP], src
4314 emit_opcode (cbuf, 0x0F );
4315 emit_opcode (cbuf, 0x11 );
4316 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false);
4317
4318 emit_opcode(cbuf,0xD9 ); // FLD_S [ESP]
4319 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
4320
4321 emit_opcode(cbuf,0x83); // ADD ESP,4
4322 emit_opcode(cbuf,0xC4);
4323 emit_d8(cbuf,0x04);
4324
4325 // CALL directly to the runtime
4326 cbuf.set_inst_mark();
4327 emit_opcode(cbuf,0xE8); // Call into runtime
4328 emit_d32_reloc(cbuf, (StubRoutines::d2l_wrapper() - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
4329 // Carry on here...
4330 %}
4331
4332 enc_class XD2L_encoding( regXD src ) %{
4333 // Allocate a word
4334 emit_opcode(cbuf,0x83); // SUB ESP,8
4335 emit_opcode(cbuf,0xEC);
4336 emit_d8(cbuf,0x08);
4337
4338 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], src
4339 emit_opcode (cbuf, 0x0F );
4340 emit_opcode (cbuf, 0x11 );
4341 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false);
4342
4343 emit_opcode(cbuf,0xDD ); // FLD_D [ESP]
4344 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
4345
4346 emit_opcode(cbuf,0xD9); // FLDCW trunc
4347 emit_opcode(cbuf,0x2D);
4348 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
4349
4350 // Encoding assumes a double has been pushed into FPR0.
4351 // Store down the double as a long, popping the FPU stack
4352 emit_opcode(cbuf,0xDF); // FISTP [ESP]
4353 emit_opcode(cbuf,0x3C);
4354 emit_d8(cbuf,0x24);
4355
4356 // Restore the rounding mode; mask the exception
4357 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode
4358 emit_opcode(cbuf,0x2D);
4359 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
4360 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
4361 : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
4362
4363 // Load the converted int; adjust CPU stack
4364 emit_opcode(cbuf,0x58); // POP EAX
4365
4366 emit_opcode(cbuf,0x5A); // POP EDX
4367
4368 emit_opcode(cbuf,0x81); // CMP EDX,imm
4369 emit_d8 (cbuf,0xFA); // rdx
4370 emit_d32 (cbuf,0x80000000); // 0x80000000
4371
4372 emit_opcode(cbuf,0x75); // JNE around_slow_call
4373 emit_d8 (cbuf,0x13+4); // Size of slow_call
4374
4375 emit_opcode(cbuf,0x85); // TEST EAX,EAX
4376 emit_opcode(cbuf,0xC0); // 2/rax,/rax,
4377
4378 emit_opcode(cbuf,0x75); // JNE around_slow_call
4379 emit_d8 (cbuf,0x13); // Size of slow_call
4380
4381 // Push src onto stack slow-path
4382 // Allocate a word
4383 emit_opcode(cbuf,0x83); // SUB ESP,8
4384 emit_opcode(cbuf,0xEC);
4385 emit_d8(cbuf,0x08);
4386
4387 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], src
4388 emit_opcode (cbuf, 0x0F );
4389 emit_opcode (cbuf, 0x11 );
4390 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false);
4391
4392 emit_opcode(cbuf,0xDD ); // FLD_D [ESP]
4393 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
4394
4395 emit_opcode(cbuf,0x83); // ADD ESP,8
4396 emit_opcode(cbuf,0xC4);
4397 emit_d8(cbuf,0x08);
4398
4399 // CALL directly to the runtime
4400 cbuf.set_inst_mark();
4401 emit_opcode(cbuf,0xE8); // Call into runtime
4402 emit_d32_reloc(cbuf, (StubRoutines::d2l_wrapper() - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
4403 // Carry on here...
4404 %}
4405
4406 enc_class D2X_encoding( regX dst, regD src ) %{
4407 // Allocate a word
4408 emit_opcode(cbuf,0x83); // SUB ESP,4
4409 emit_opcode(cbuf,0xEC);
4410 emit_d8(cbuf,0x04);
4411 int pop = 0x02;
4412 if ($src$$reg != FPR1L_enc) {
4413 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
4414 emit_d8( cbuf, 0xC0-1+$src$$reg );
4415 pop = 0x03;
4416 }
4417 store_to_stackslot( cbuf, 0xD9, pop, 0 ); // FST<P>_S [ESP]
4418
4419 emit_opcode (cbuf, 0xF3 ); // MOVSS dst(xmm), [ESP]
4420 emit_opcode (cbuf, 0x0F );
4421 emit_opcode (cbuf, 0x10 );
4422 encode_RegMem(cbuf, $dst$$reg, ESP_enc, 0x4, 0, 0, false);
4423
4424 emit_opcode(cbuf,0x83); // ADD ESP,4
4425 emit_opcode(cbuf,0xC4);
4426 emit_d8(cbuf,0x04);
4427 // Carry on here...
4428 %}
4429
4430 enc_class FX2I_encoding( regX src, eRegI dst ) %{
4431 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
4432
4433 // Compare the result to see if we need to go to the slow path
4434 emit_opcode(cbuf,0x81); // CMP dst,imm
4435 emit_rm (cbuf,0x3,0x7,$dst$$reg);
4436 emit_d32 (cbuf,0x80000000); // 0x80000000
4437
4438 emit_opcode(cbuf,0x75); // JNE around_slow_call
4439 emit_d8 (cbuf,0x13); // Size of slow_call
4440 // Store xmm to a temp memory
4441 // location and push it onto stack.
4442
4443 emit_opcode(cbuf,0x83); // SUB ESP,4
4444 emit_opcode(cbuf,0xEC);
4445 emit_d8(cbuf, $primary ? 0x8 : 0x4);
4446
4447 emit_opcode (cbuf, $primary ? 0xF2 : 0xF3 ); // MOVSS [ESP], xmm
4448 emit_opcode (cbuf, 0x0F );
4449 emit_opcode (cbuf, 0x11 );
4450 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false);
4451
4452 emit_opcode(cbuf, $primary ? 0xDD : 0xD9 ); // FLD [ESP]
4453 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
4454
4455 emit_opcode(cbuf,0x83); // ADD ESP,4
4456 emit_opcode(cbuf,0xC4);
4457 emit_d8(cbuf, $primary ? 0x8 : 0x4);
4458
4459 // CALL directly to the runtime
4460 cbuf.set_inst_mark();
4461 emit_opcode(cbuf,0xE8); // Call into runtime
4462 emit_d32_reloc(cbuf, (StubRoutines::d2i_wrapper() - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
4463
4464 // Carry on here...
4465 %}
4466
4467 enc_class X2D_encoding( regD dst, regX src ) %{
4468 // Allocate a word
4469 emit_opcode(cbuf,0x83); // SUB ESP,4
4470 emit_opcode(cbuf,0xEC);
4471 emit_d8(cbuf,0x04);
4472
4473 emit_opcode (cbuf, 0xF3 ); // MOVSS [ESP], xmm
4474 emit_opcode (cbuf, 0x0F );
4475 emit_opcode (cbuf, 0x11 );
4476 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false);
4477
4478 emit_opcode(cbuf,0xD9 ); // FLD_S [ESP]
4479 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
4480
4481 emit_opcode(cbuf,0x83); // ADD ESP,4
4482 emit_opcode(cbuf,0xC4);
4483 emit_d8(cbuf,0x04);
4484
4485 // Carry on here...
4486 %}
4487
4488 enc_class AbsXF_encoding(regX dst) %{
4489 address signmask_address=(address)float_signmask_pool;
4490 // andpd:\tANDPS $dst,[signconst]
4491 emit_opcode(cbuf, 0x0F);
4492 emit_opcode(cbuf, 0x54);
4493 emit_rm(cbuf, 0x0, $dst$$reg, 0x5);
4494 emit_d32(cbuf, (int)signmask_address);
4495 %}
4496
4497 enc_class AbsXD_encoding(regXD dst) %{
4498 address signmask_address=(address)double_signmask_pool;
4499 // andpd:\tANDPD $dst,[signconst]
4500 emit_opcode(cbuf, 0x66);
4501 emit_opcode(cbuf, 0x0F);
4502 emit_opcode(cbuf, 0x54);
4503 emit_rm(cbuf, 0x0, $dst$$reg, 0x5);
4504 emit_d32(cbuf, (int)signmask_address);
4505 %}
4506
4507 enc_class NegXF_encoding(regX dst) %{
4508 address signmask_address=(address)float_signflip_pool;
4509 // andpd:\tXORPS $dst,[signconst]
4510 emit_opcode(cbuf, 0x0F);
4511 emit_opcode(cbuf, 0x57);
4512 emit_rm(cbuf, 0x0, $dst$$reg, 0x5);
4513 emit_d32(cbuf, (int)signmask_address);
4514 %}
4515
4516 enc_class NegXD_encoding(regXD dst) %{
4517 address signmask_address=(address)double_signflip_pool;
4518 // andpd:\tXORPD $dst,[signconst]
4519 emit_opcode(cbuf, 0x66);
4520 emit_opcode(cbuf, 0x0F);
4521 emit_opcode(cbuf, 0x57);
4522 emit_rm(cbuf, 0x0, $dst$$reg, 0x5);
4523 emit_d32(cbuf, (int)signmask_address);
4524 %}
4525
4526 enc_class FMul_ST_reg( eRegF src1 ) %{
4527 // Operand was loaded from memory into fp ST (stack top)
4528 // FMUL ST,$src /* D8 C8+i */
4529 emit_opcode(cbuf, 0xD8);
4530 emit_opcode(cbuf, 0xC8 + $src1$$reg);
4531 %}
4532
4533 enc_class FAdd_ST_reg( eRegF src2 ) %{
4534 // FADDP ST,src2 /* D8 C0+i */
4535 emit_opcode(cbuf, 0xD8);
4536 emit_opcode(cbuf, 0xC0 + $src2$$reg);
4537 //could use FADDP src2,fpST /* DE C0+i */
4538 %}
4539
4540 enc_class FAddP_reg_ST( eRegF src2 ) %{
4541 // FADDP src2,ST /* DE C0+i */
4542 emit_opcode(cbuf, 0xDE);
4543 emit_opcode(cbuf, 0xC0 + $src2$$reg);
4544 %}
4545
4546 enc_class subF_divF_encode( eRegF src1, eRegF src2) %{
4547 // Operand has been loaded into fp ST (stack top)
4548 // FSUB ST,$src1
4549 emit_opcode(cbuf, 0xD8);
4550 emit_opcode(cbuf, 0xE0 + $src1$$reg);
4551
4552 // FDIV
4553 emit_opcode(cbuf, 0xD8);
4554 emit_opcode(cbuf, 0xF0 + $src2$$reg);
4555 %}
4556
4557 enc_class MulFAddF (eRegF src1, eRegF src2) %{
4558 // Operand was loaded from memory into fp ST (stack top)
4559 // FADD ST,$src /* D8 C0+i */
4560 emit_opcode(cbuf, 0xD8);
4561 emit_opcode(cbuf, 0xC0 + $src1$$reg);
4562
4563 // FMUL ST,src2 /* D8 C*+i */
4564 emit_opcode(cbuf, 0xD8);
4565 emit_opcode(cbuf, 0xC8 + $src2$$reg);
4566 %}
4567
4568
4569 enc_class MulFAddFreverse (eRegF src1, eRegF src2) %{
4570 // Operand was loaded from memory into fp ST (stack top)
4571 // FADD ST,$src /* D8 C0+i */
4572 emit_opcode(cbuf, 0xD8);
4573 emit_opcode(cbuf, 0xC0 + $src1$$reg);
4574
4575 // FMULP src2,ST /* DE C8+i */
4576 emit_opcode(cbuf, 0xDE);
4577 emit_opcode(cbuf, 0xC8 + $src2$$reg);
4578 %}
4579
4580 // Atomically load the volatile long
4581 enc_class enc_loadL_volatile( memory mem, stackSlotL dst ) %{
4582 emit_opcode(cbuf,0xDF);
4583 int rm_byte_opcode = 0x05;
4584 int base = $mem$$base;
4585 int index = $mem$$index;
4586 int scale = $mem$$scale;
4587 int displace = $mem$$disp;
4588 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
4589 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_is_oop);
4590 store_to_stackslot( cbuf, 0x0DF, 0x07, $dst$$disp );
4591 %}
4592
4593 enc_class enc_loadLX_volatile( memory mem, stackSlotL dst, regXD tmp ) %{
4594 { // Atomic long load
4595 // UseXmmLoadAndClearUpper ? movsd $tmp,$mem : movlpd $tmp,$mem
4596 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0xF2 : 0x66);
4597 emit_opcode(cbuf,0x0F);
4598 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0x10 : 0x12);
4599 int base = $mem$$base;
4600 int index = $mem$$index;
4601 int scale = $mem$$scale;
4602 int displace = $mem$$disp;
4603 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
4604 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop);
4605 }
4606 { // MOVSD $dst,$tmp ! atomic long store
4607 emit_opcode(cbuf,0xF2);
4608 emit_opcode(cbuf,0x0F);
4609 emit_opcode(cbuf,0x11);
4610 int base = $dst$$base;
4611 int index = $dst$$index;
4612 int scale = $dst$$scale;
4613 int displace = $dst$$disp;
4614 bool disp_is_oop = $dst->disp_is_oop(); // disp-as-oop when working with static globals
4615 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop);
4616 }
4617 %}
4618
4619 enc_class enc_loadLX_reg_volatile( memory mem, eRegL dst, regXD tmp ) %{
4620 { // Atomic long load
4621 // UseXmmLoadAndClearUpper ? movsd $tmp,$mem : movlpd $tmp,$mem
4622 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0xF2 : 0x66);
4623 emit_opcode(cbuf,0x0F);
4624 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0x10 : 0x12);
4625 int base = $mem$$base;
4626 int index = $mem$$index;
4627 int scale = $mem$$scale;
4628 int displace = $mem$$disp;
4629 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
4630 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop);
4631 }
4632 { // MOVD $dst.lo,$tmp
4633 emit_opcode(cbuf,0x66);
4634 emit_opcode(cbuf,0x0F);
4635 emit_opcode(cbuf,0x7E);
4636 emit_rm(cbuf, 0x3, $tmp$$reg, $dst$$reg);
4637 }
4638 { // PSRLQ $tmp,32
4639 emit_opcode(cbuf,0x66);
4640 emit_opcode(cbuf,0x0F);
4641 emit_opcode(cbuf,0x73);
4642 emit_rm(cbuf, 0x3, 0x02, $tmp$$reg);
4643 emit_d8(cbuf, 0x20);
4644 }
4645 { // MOVD $dst.hi,$tmp
4646 emit_opcode(cbuf,0x66);
4647 emit_opcode(cbuf,0x0F);
4648 emit_opcode(cbuf,0x7E);
4649 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg));
4650 }
4651 %}
4652
4653 // Volatile Store Long. Must be atomic, so move it into
4654 // the FP TOS and then do a 64-bit FIST. Has to probe the
4655 // target address before the store (for null-ptr checks)
4656 // so the memory operand is used twice in the encoding.
4657 enc_class enc_storeL_volatile( memory mem, stackSlotL src ) %{
4658 store_to_stackslot( cbuf, 0x0DF, 0x05, $src$$disp );
4659 cbuf.set_inst_mark(); // Mark start of FIST in case $mem has an oop
4660 emit_opcode(cbuf,0xDF);
4661 int rm_byte_opcode = 0x07;
4662 int base = $mem$$base;
4663 int index = $mem$$index;
4664 int scale = $mem$$scale;
4665 int displace = $mem$$disp;
4666 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
4667 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_is_oop);
4668 %}
4669
4670 enc_class enc_storeLX_volatile( memory mem, stackSlotL src, regXD tmp) %{
4671 { // Atomic long load
4672 // UseXmmLoadAndClearUpper ? movsd $tmp,[$src] : movlpd $tmp,[$src]
4673 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0xF2 : 0x66);
4674 emit_opcode(cbuf,0x0F);
4675 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0x10 : 0x12);
4676 int base = $src$$base;
4677 int index = $src$$index;
4678 int scale = $src$$scale;
4679 int displace = $src$$disp;
4680 bool disp_is_oop = $src->disp_is_oop(); // disp-as-oop when working with static globals
4681 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop);
4682 }
4683 cbuf.set_inst_mark(); // Mark start of MOVSD in case $mem has an oop
4684 { // MOVSD $mem,$tmp ! atomic long store
4685 emit_opcode(cbuf,0xF2);
4686 emit_opcode(cbuf,0x0F);
4687 emit_opcode(cbuf,0x11);
4688 int base = $mem$$base;
4689 int index = $mem$$index;
4690 int scale = $mem$$scale;
4691 int displace = $mem$$disp;
4692 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
4693 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop);
4694 }
4695 %}
4696
4697 enc_class enc_storeLX_reg_volatile( memory mem, eRegL src, regXD tmp, regXD tmp2) %{
4698 { // MOVD $tmp,$src.lo
4699 emit_opcode(cbuf,0x66);
4700 emit_opcode(cbuf,0x0F);
4701 emit_opcode(cbuf,0x6E);
4702 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg);
4703 }
4704 { // MOVD $tmp2,$src.hi
4705 emit_opcode(cbuf,0x66);
4706 emit_opcode(cbuf,0x0F);
4707 emit_opcode(cbuf,0x6E);
4708 emit_rm(cbuf, 0x3, $tmp2$$reg, HIGH_FROM_LOW($src$$reg));
4709 }
4710 { // PUNPCKLDQ $tmp,$tmp2
4711 emit_opcode(cbuf,0x66);
4712 emit_opcode(cbuf,0x0F);
4713 emit_opcode(cbuf,0x62);
4714 emit_rm(cbuf, 0x3, $tmp$$reg, $tmp2$$reg);
4715 }
4716 cbuf.set_inst_mark(); // Mark start of MOVSD in case $mem has an oop
4717 { // MOVSD $mem,$tmp ! atomic long store
4718 emit_opcode(cbuf,0xF2);
4719 emit_opcode(cbuf,0x0F);
4720 emit_opcode(cbuf,0x11);
4721 int base = $mem$$base;
4722 int index = $mem$$index;
4723 int scale = $mem$$scale;
4724 int displace = $mem$$disp;
4725 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
4726 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop);
4727 }
4728 %}
4729
4730 // Safepoint Poll. This polls the safepoint page, and causes an
4731 // exception if it is not readable. Unfortunately, it kills the condition code
4732 // in the process
4733 // We current use TESTL [spp],EDI
4734 // A better choice might be TESTB [spp + pagesize() - CacheLineSize()],0
4735
4736 enc_class Safepoint_Poll() %{
4737 cbuf.relocate(cbuf.inst_mark(), relocInfo::poll_type, 0);
4738 emit_opcode(cbuf,0x85);
4739 emit_rm (cbuf, 0x0, 0x7, 0x5);
4740 emit_d32(cbuf, (intptr_t)os::get_polling_page());
4741 %}
4742 %}
4743
4744
4745 //----------FRAME--------------------------------------------------------------
4746 // Definition of frame structure and management information.
4747 //
4748 // S T A C K L A Y O U T Allocators stack-slot number
4749 // | (to get allocators register number
4750 // G Owned by | | v add OptoReg::stack0())
4751 // r CALLER | |
4752 // o | +--------+ pad to even-align allocators stack-slot
4753 // w V | pad0 | numbers; owned by CALLER
4754 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
4755 // h ^ | in | 5
4756 // | | args | 4 Holes in incoming args owned by SELF
4757 // | | | | 3
4758 // | | +--------+
4759 // V | | old out| Empty on Intel, window on Sparc
4760 // | old |preserve| Must be even aligned.
4761 // | SP-+--------+----> Matcher::_old_SP, even aligned
4762 // | | in | 3 area for Intel ret address
4763 // Owned by |preserve| Empty on Sparc.
4764 // SELF +--------+
4765 // | | pad2 | 2 pad to align old SP
4766 // | +--------+ 1
4767 // | | locks | 0
4768 // | +--------+----> OptoReg::stack0(), even aligned
4769 // | | pad1 | 11 pad to align new SP
4770 // | +--------+
4771 // | | | 10
4772 // | | spills | 9 spills
4773 // V | | 8 (pad0 slot for callee)
4774 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
4775 // ^ | out | 7
4776 // | | args | 6 Holes in outgoing args owned by CALLEE
4777 // Owned by +--------+
4778 // CALLEE | new out| 6 Empty on Intel, window on Sparc
4779 // | new |preserve| Must be even-aligned.
4780 // | SP-+--------+----> Matcher::_new_SP, even aligned
4781 // | | |
4782 //
4783 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
4784 // known from SELF's arguments and the Java calling convention.
4785 // Region 6-7 is determined per call site.
4786 // Note 2: If the calling convention leaves holes in the incoming argument
4787 // area, those holes are owned by SELF. Holes in the outgoing area
4788 // are owned by the CALLEE. Holes should not be nessecary in the
4789 // incoming area, as the Java calling convention is completely under
4790 // the control of the AD file. Doubles can be sorted and packed to
4791 // avoid holes. Holes in the outgoing arguments may be nessecary for
4792 // varargs C calling conventions.
4793 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
4794 // even aligned with pad0 as needed.
4795 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
4796 // region 6-11 is even aligned; it may be padded out more so that
4797 // the region from SP to FP meets the minimum stack alignment.
4798
4799 frame %{
4800 // What direction does stack grow in (assumed to be same for C & Java)
4801 stack_direction(TOWARDS_LOW);
4802
4803 // These three registers define part of the calling convention
4804 // between compiled code and the interpreter.
4805 inline_cache_reg(EAX); // Inline Cache Register
4806 interpreter_method_oop_reg(EBX); // Method Oop Register when calling interpreter
4807
4808 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
4809 cisc_spilling_operand_name(indOffset32);
4810
4811 // Number of stack slots consumed by locking an object
4812 sync_stack_slots(1);
4813
4814 // Compiled code's Frame Pointer
4815 frame_pointer(ESP);
4816 // Interpreter stores its frame pointer in a register which is
4817 // stored to the stack by I2CAdaptors.
4818 // I2CAdaptors convert from interpreted java to compiled java.
4819 interpreter_frame_pointer(EBP);
4820
4821 // Stack alignment requirement
4822 // Alignment size in bytes (128-bit -> 16 bytes)
4823 stack_alignment(StackAlignmentInBytes);
4824
4825 // Number of stack slots between incoming argument block and the start of
4826 // a new frame. The PROLOG must add this many slots to the stack. The
4827 // EPILOG must remove this many slots. Intel needs one slot for
4828 // return address and one for rbp, (must save rbp)
4829 in_preserve_stack_slots(2+VerifyStackAtCalls);
4830
4831 // Number of outgoing stack slots killed above the out_preserve_stack_slots
4832 // for calls to C. Supports the var-args backing area for register parms.
4833 varargs_C_out_slots_killed(0);
4834
4835 // The after-PROLOG location of the return address. Location of
4836 // return address specifies a type (REG or STACK) and a number
4837 // representing the register number (i.e. - use a register name) or
4838 // stack slot.
4839 // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
4840 // Otherwise, it is above the locks and verification slot and alignment word
4841 return_addr(STACK - 1 +
4842 round_to(1+VerifyStackAtCalls+
4843 Compile::current()->fixed_slots(),
4844 (StackAlignmentInBytes/wordSize)));
4845
4846 // Body of function which returns an integer array locating
4847 // arguments either in registers or in stack slots. Passed an array
4848 // of ideal registers called "sig" and a "length" count. Stack-slot
4849 // offsets are based on outgoing arguments, i.e. a CALLER setting up
4850 // arguments for a CALLEE. Incoming stack arguments are
4851 // automatically biased by the preserve_stack_slots field above.
4852 calling_convention %{
4853 // No difference between ingoing/outgoing just pass false
4854 SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
4855 %}
4856
4857
4858 // Body of function which returns an integer array locating
4859 // arguments either in registers or in stack slots. Passed an array
4860 // of ideal registers called "sig" and a "length" count. Stack-slot
4861 // offsets are based on outgoing arguments, i.e. a CALLER setting up
4862 // arguments for a CALLEE. Incoming stack arguments are
4863 // automatically biased by the preserve_stack_slots field above.
4864 c_calling_convention %{
4865 // This is obviously always outgoing
4866 (void) SharedRuntime::c_calling_convention(sig_bt, regs, length);
4867 %}
4868
4869 // Location of C & interpreter return values
4870 c_return_value %{
4871 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
4872 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num };
4873 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num };
4874
4875 // in SSE2+ mode we want to keep the FPU stack clean so pretend
4876 // that C functions return float and double results in XMM0.
4877 if( ideal_reg == Op_RegD && UseSSE>=2 )
4878 return OptoRegPair(XMM0b_num,XMM0a_num);
4879 if( ideal_reg == Op_RegF && UseSSE>=2 )
4880 return OptoRegPair(OptoReg::Bad,XMM0a_num);
4881
4882 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]);
4883 %}
4884
4885 // Location of return values
4886 return_value %{
4887 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
4888 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num };
4889 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num };
4890 if( ideal_reg == Op_RegD && UseSSE>=2 )
4891 return OptoRegPair(XMM0b_num,XMM0a_num);
4892 if( ideal_reg == Op_RegF && UseSSE>=1 )
4893 return OptoRegPair(OptoReg::Bad,XMM0a_num);
4894 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]);
4895 %}
4896
4897 %}
4898
4899 //----------ATTRIBUTES---------------------------------------------------------
4900 //----------Operand Attributes-------------------------------------------------
4901 op_attrib op_cost(0); // Required cost attribute
4902
4903 //----------Instruction Attributes---------------------------------------------
4904 ins_attrib ins_cost(100); // Required cost attribute
4905 ins_attrib ins_size(8); // Required size attribute (in bits)
4906 ins_attrib ins_pc_relative(0); // Required PC Relative flag
4907 ins_attrib ins_short_branch(0); // Required flag: is this instruction a
4908 // non-matching short branch variant of some
4909 // long branch?
4910 ins_attrib ins_alignment(1); // Required alignment attribute (must be a power of 2)
4911 // specifies the alignment that some part of the instruction (not
4912 // necessarily the start) requires. If > 1, a compute_padding()
4913 // function must be provided for the instruction
4914
4915 //----------OPERANDS-----------------------------------------------------------
4916 // Operand definitions must precede instruction definitions for correct parsing
4917 // in the ADLC because operands constitute user defined types which are used in
4918 // instruction definitions.
4919
4920 //----------Simple Operands----------------------------------------------------
4921 // Immediate Operands
4922 // Integer Immediate
4923 operand immI() %{
4924 match(ConI);
4925
4926 op_cost(10);
4927 format %{ %}
4928 interface(CONST_INTER);
4929 %}
4930
4931 // Constant for test vs zero
4932 operand immI0() %{
4933 predicate(n->get_int() == 0);
4934 match(ConI);
4935
4936 op_cost(0);
4937 format %{ %}
4938 interface(CONST_INTER);
4939 %}
4940
4941 // Constant for increment
4942 operand immI1() %{
4943 predicate(n->get_int() == 1);
4944 match(ConI);
4945
4946 op_cost(0);
4947 format %{ %}
4948 interface(CONST_INTER);
4949 %}
4950
4951 // Constant for decrement
4952 operand immI_M1() %{
4953 predicate(n->get_int() == -1);
4954 match(ConI);
4955
4956 op_cost(0);
4957 format %{ %}
4958 interface(CONST_INTER);
4959 %}
4960
4961 // Valid scale values for addressing modes
4962 operand immI2() %{
4963 predicate(0 <= n->get_int() && (n->get_int() <= 3));
4964 match(ConI);
4965
4966 format %{ %}
4967 interface(CONST_INTER);
4968 %}
4969
4970 operand immI8() %{
4971 predicate((-128 <= n->get_int()) && (n->get_int() <= 127));
4972 match(ConI);
4973
4974 op_cost(5);
4975 format %{ %}
4976 interface(CONST_INTER);
4977 %}
4978
4979 operand immI16() %{
4980 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767));
4981 match(ConI);
4982
4983 op_cost(10);
4984 format %{ %}
4985 interface(CONST_INTER);
4986 %}
4987
4988 // Constant for long shifts
4989 operand immI_32() %{
4990 predicate( n->get_int() == 32 );
4991 match(ConI);
4992
4993 op_cost(0);
4994 format %{ %}
4995 interface(CONST_INTER);
4996 %}
4997
4998 operand immI_1_31() %{
4999 predicate( n->get_int() >= 1 && n->get_int() <= 31 );
5000 match(ConI);
5001
5002 op_cost(0);
5003 format %{ %}
5004 interface(CONST_INTER);
5005 %}
5006
5007 operand immI_32_63() %{
5008 predicate( n->get_int() >= 32 && n->get_int() <= 63 );
5009 match(ConI);
5010 op_cost(0);
5011
5012 format %{ %}
5013 interface(CONST_INTER);
5014 %}
5015
5016 operand immI_1() %{
5017 predicate( n->get_int() == 1 );
5018 match(ConI);
5019
5020 op_cost(0);
5021 format %{ %}
5022 interface(CONST_INTER);
5023 %}
5024
5025 operand immI_2() %{
5026 predicate( n->get_int() == 2 );
5027 match(ConI);
5028
5029 op_cost(0);
5030 format %{ %}
5031 interface(CONST_INTER);
5032 %}
5033
5034 operand immI_3() %{
5035 predicate( n->get_int() == 3 );
5036 match(ConI);
5037
5038 op_cost(0);
5039 format %{ %}
5040 interface(CONST_INTER);
5041 %}
5042
5043 // Pointer Immediate
5044 operand immP() %{
5045 match(ConP);
5046
5047 op_cost(10);
5048 format %{ %}
5049 interface(CONST_INTER);
5050 %}
5051
5052 // NULL Pointer Immediate
5053 operand immP0() %{
5054 predicate( n->get_ptr() == 0 );
5055 match(ConP);
5056 op_cost(0);
5057
5058 format %{ %}
5059 interface(CONST_INTER);
5060 %}
5061
5062 // Long Immediate
5063 operand immL() %{
5064 match(ConL);
5065
5066 op_cost(20);
5067 format %{ %}
5068 interface(CONST_INTER);
5069 %}
5070
5071 // Long Immediate zero
5072 operand immL0() %{
5073 predicate( n->get_long() == 0L );
5074 match(ConL);
5075 op_cost(0);
5076
5077 format %{ %}
5078 interface(CONST_INTER);
5079 %}
5080
5081 // Long Immediate zero
5082 operand immL_M1() %{
5083 predicate( n->get_long() == -1L );
5084 match(ConL);
5085 op_cost(0);
5086
5087 format %{ %}
5088 interface(CONST_INTER);
5089 %}
5090
5091 // Long immediate from 0 to 127.
5092 // Used for a shorter form of long mul by 10.
5093 operand immL_127() %{
5094 predicate((0 <= n->get_long()) && (n->get_long() <= 127));
5095 match(ConL);
5096 op_cost(0);
5097
5098 format %{ %}
5099 interface(CONST_INTER);
5100 %}
5101
5102 // Long Immediate: low 32-bit mask
5103 operand immL_32bits() %{
5104 predicate(n->get_long() == 0xFFFFFFFFL);
5105 match(ConL);
5106 op_cost(0);
5107
5108 format %{ %}
5109 interface(CONST_INTER);
5110 %}
5111
5112 // Long Immediate: low 32-bit mask
5113 operand immL32() %{
5114 predicate(n->get_long() == (int)(n->get_long()));
5115 match(ConL);
5116 op_cost(20);
5117
5118 format %{ %}
5119 interface(CONST_INTER);
5120 %}
5121
5122 //Double Immediate zero
5123 operand immD0() %{
5124 // Do additional (and counter-intuitive) test against NaN to work around VC++
5125 // bug that generates code such that NaNs compare equal to 0.0
5126 predicate( UseSSE<=1 && n->getd() == 0.0 && !g_isnan(n->getd()) );
5127 match(ConD);
5128
5129 op_cost(5);
5130 format %{ %}
5131 interface(CONST_INTER);
5132 %}
5133
5134 // Double Immediate
5135 operand immD1() %{
5136 predicate( UseSSE<=1 && n->getd() == 1.0 );
5137 match(ConD);
5138
5139 op_cost(5);
5140 format %{ %}
5141 interface(CONST_INTER);
5142 %}
5143
5144 // Double Immediate
5145 operand immD() %{
5146 predicate(UseSSE<=1);
5147 match(ConD);
5148
5149 op_cost(5);
5150 format %{ %}
5151 interface(CONST_INTER);
5152 %}
5153
5154 operand immXD() %{
5155 predicate(UseSSE>=2);
5156 match(ConD);
5157
5158 op_cost(5);
5159 format %{ %}
5160 interface(CONST_INTER);
5161 %}
5162
5163 // Double Immediate zero
5164 operand immXD0() %{
5165 // Do additional (and counter-intuitive) test against NaN to work around VC++
5166 // bug that generates code such that NaNs compare equal to 0.0 AND do not
5167 // compare equal to -0.0.
5168 predicate( UseSSE>=2 && jlong_cast(n->getd()) == 0 );
5169 match(ConD);
5170
5171 format %{ %}
5172 interface(CONST_INTER);
5173 %}
5174
5175 // Float Immediate zero
5176 operand immF0() %{
5177 predicate( UseSSE == 0 && n->getf() == 0.0 );
5178 match(ConF);
5179
5180 op_cost(5);
5181 format %{ %}
5182 interface(CONST_INTER);
5183 %}
5184
5185 // Float Immediate
5186 operand immF() %{
5187 predicate( UseSSE == 0 );
5188 match(ConF);
5189
5190 op_cost(5);
5191 format %{ %}
5192 interface(CONST_INTER);
5193 %}
5194
5195 // Float Immediate
5196 operand immXF() %{
5197 predicate(UseSSE >= 1);
5198 match(ConF);
5199
5200 op_cost(5);
5201 format %{ %}
5202 interface(CONST_INTER);
5203 %}
5204
5205 // Float Immediate zero. Zero and not -0.0
5206 operand immXF0() %{
5207 predicate( UseSSE >= 1 && jint_cast(n->getf()) == 0 );
5208 match(ConF);
5209
5210 op_cost(5);
5211 format %{ %}
5212 interface(CONST_INTER);
5213 %}
5214
5215 // Immediates for special shifts (sign extend)
5216
5217 // Constants for increment
5218 operand immI_16() %{
5219 predicate( n->get_int() == 16 );
5220 match(ConI);
5221
5222 format %{ %}
5223 interface(CONST_INTER);
5224 %}
5225
5226 operand immI_24() %{
5227 predicate( n->get_int() == 24 );
5228 match(ConI);
5229
5230 format %{ %}
5231 interface(CONST_INTER);
5232 %}
5233
5234 // Constant for byte-wide masking
5235 operand immI_255() %{
5236 predicate( n->get_int() == 255 );
5237 match(ConI);
5238
5239 format %{ %}
5240 interface(CONST_INTER);
5241 %}
5242
5243 // Register Operands
5244 // Integer Register
5245 operand eRegI() %{
5246 constraint(ALLOC_IN_RC(e_reg));
5247 match(RegI);
5248 match(xRegI);
5249 match(eAXRegI);
5250 match(eBXRegI);
5251 match(eCXRegI);
5252 match(eDXRegI);
5253 match(eDIRegI);
5254 match(eSIRegI);
5255
5256 format %{ %}
5257 interface(REG_INTER);
5258 %}
5259
5260 // Subset of Integer Register
5261 operand xRegI(eRegI reg) %{
5262 constraint(ALLOC_IN_RC(x_reg));
5263 match(reg);
5264 match(eAXRegI);
5265 match(eBXRegI);
5266 match(eCXRegI);
5267 match(eDXRegI);
5268
5269 format %{ %}
5270 interface(REG_INTER);
5271 %}
5272
5273 // Special Registers
5274 operand eAXRegI(xRegI reg) %{
5275 constraint(ALLOC_IN_RC(eax_reg));
5276 match(reg);
5277 match(eRegI);
5278
5279 format %{ "EAX" %}
5280 interface(REG_INTER);
5281 %}
5282
5283 // Special Registers
5284 operand eBXRegI(xRegI reg) %{
5285 constraint(ALLOC_IN_RC(ebx_reg));
5286 match(reg);
5287 match(eRegI);
5288
5289 format %{ "EBX" %}
5290 interface(REG_INTER);
5291 %}
5292
5293 operand eCXRegI(xRegI reg) %{
5294 constraint(ALLOC_IN_RC(ecx_reg));
5295 match(reg);
5296 match(eRegI);
5297
5298 format %{ "ECX" %}
5299 interface(REG_INTER);
5300 %}
5301
5302 operand eDXRegI(xRegI reg) %{
5303 constraint(ALLOC_IN_RC(edx_reg));
5304 match(reg);
5305 match(eRegI);
5306
5307 format %{ "EDX" %}
5308 interface(REG_INTER);
5309 %}
5310
5311 operand eDIRegI(xRegI reg) %{
5312 constraint(ALLOC_IN_RC(edi_reg));
5313 match(reg);
5314 match(eRegI);
5315
5316 format %{ "EDI" %}
5317 interface(REG_INTER);
5318 %}
5319
5320 operand naxRegI() %{
5321 constraint(ALLOC_IN_RC(nax_reg));
5322 match(RegI);
5323 match(eCXRegI);
5324 match(eDXRegI);
5325 match(eSIRegI);
5326 match(eDIRegI);
5327
5328 format %{ %}
5329 interface(REG_INTER);
5330 %}
5331
5332 operand nadxRegI() %{
5333 constraint(ALLOC_IN_RC(nadx_reg));
5334 match(RegI);
5335 match(eBXRegI);
5336 match(eCXRegI);
5337 match(eSIRegI);
5338 match(eDIRegI);
5339
5340 format %{ %}
5341 interface(REG_INTER);
5342 %}
5343
5344 operand ncxRegI() %{
5345 constraint(ALLOC_IN_RC(ncx_reg));
5346 match(RegI);
5347 match(eAXRegI);
5348 match(eDXRegI);
5349 match(eSIRegI);
5350 match(eDIRegI);
5351
5352 format %{ %}
5353 interface(REG_INTER);
5354 %}
5355
5356 // // This operand was used by cmpFastUnlock, but conflicted with 'object' reg
5357 // //
5358 operand eSIRegI(xRegI reg) %{
5359 constraint(ALLOC_IN_RC(esi_reg));
5360 match(reg);
5361 match(eRegI);
5362
5363 format %{ "ESI" %}
5364 interface(REG_INTER);
5365 %}
5366
5367 // Pointer Register
5368 operand anyRegP() %{
5369 constraint(ALLOC_IN_RC(any_reg));
5370 match(RegP);
5371 match(eAXRegP);
5372 match(eBXRegP);
5373 match(eCXRegP);
5374 match(eDIRegP);
5375 match(eRegP);
5376
5377 format %{ %}
5378 interface(REG_INTER);
5379 %}
5380
5381 operand eRegP() %{
5382 constraint(ALLOC_IN_RC(e_reg));
5383 match(RegP);
5384 match(eAXRegP);
5385 match(eBXRegP);
5386 match(eCXRegP);
5387 match(eDIRegP);
5388
5389 format %{ %}
5390 interface(REG_INTER);
5391 %}
5392
5393 // On windows95, EBP is not safe to use for implicit null tests.
5394 operand eRegP_no_EBP() %{
5395 constraint(ALLOC_IN_RC(e_reg_no_rbp));
5396 match(RegP);
5397 match(eAXRegP);
5398 match(eBXRegP);
5399 match(eCXRegP);
5400 match(eDIRegP);
5401
5402 op_cost(100);
5403 format %{ %}
5404 interface(REG_INTER);
5405 %}
5406
5407 operand naxRegP() %{
5408 constraint(ALLOC_IN_RC(nax_reg));
5409 match(RegP);
5410 match(eBXRegP);
5411 match(eDXRegP);
5412 match(eCXRegP);
5413 match(eSIRegP);
5414 match(eDIRegP);
5415
5416 format %{ %}
5417 interface(REG_INTER);
5418 %}
5419
5420 operand nabxRegP() %{
5421 constraint(ALLOC_IN_RC(nabx_reg));
5422 match(RegP);
5423 match(eCXRegP);
5424 match(eDXRegP);
5425 match(eSIRegP);
5426 match(eDIRegP);
5427
5428 format %{ %}
5429 interface(REG_INTER);
5430 %}
5431
5432 operand pRegP() %{
5433 constraint(ALLOC_IN_RC(p_reg));
5434 match(RegP);
5435 match(eBXRegP);
5436 match(eDXRegP);
5437 match(eSIRegP);
5438 match(eDIRegP);
5439
5440 format %{ %}
5441 interface(REG_INTER);
5442 %}
5443
5444 // Special Registers
5445 // Return a pointer value
5446 operand eAXRegP(eRegP reg) %{
5447 constraint(ALLOC_IN_RC(eax_reg));
5448 match(reg);
5449 format %{ "EAX" %}
5450 interface(REG_INTER);
5451 %}
5452
5453 // Used in AtomicAdd
5454 operand eBXRegP(eRegP reg) %{
5455 constraint(ALLOC_IN_RC(ebx_reg));
5456 match(reg);
5457 format %{ "EBX" %}
5458 interface(REG_INTER);
5459 %}
5460
5461 // Tail-call (interprocedural jump) to interpreter
5462 operand eCXRegP(eRegP reg) %{
5463 constraint(ALLOC_IN_RC(ecx_reg));
5464 match(reg);
5465 format %{ "ECX" %}
5466 interface(REG_INTER);
5467 %}
5468
5469 operand eSIRegP(eRegP reg) %{
5470 constraint(ALLOC_IN_RC(esi_reg));
5471 match(reg);
5472 format %{ "ESI" %}
5473 interface(REG_INTER);
5474 %}
5475
5476 // Used in rep stosw
5477 operand eDIRegP(eRegP reg) %{
5478 constraint(ALLOC_IN_RC(edi_reg));
5479 match(reg);
5480 format %{ "EDI" %}
5481 interface(REG_INTER);
5482 %}
5483
5484 operand eBPRegP() %{
5485 constraint(ALLOC_IN_RC(ebp_reg));
5486 match(RegP);
5487 format %{ "EBP" %}
5488 interface(REG_INTER);
5489 %}
5490
5491 operand eRegL() %{
5492 constraint(ALLOC_IN_RC(long_reg));
5493 match(RegL);
5494 match(eADXRegL);
5495
5496 format %{ %}
5497 interface(REG_INTER);
5498 %}
5499
5500 operand eADXRegL( eRegL reg ) %{
5501 constraint(ALLOC_IN_RC(eadx_reg));
5502 match(reg);
5503
5504 format %{ "EDX:EAX" %}
5505 interface(REG_INTER);
5506 %}
5507
5508 operand eBCXRegL( eRegL reg ) %{
5509 constraint(ALLOC_IN_RC(ebcx_reg));
5510 match(reg);
5511
5512 format %{ "EBX:ECX" %}
5513 interface(REG_INTER);
5514 %}
5515
5516 // Special case for integer high multiply
5517 operand eADXRegL_low_only() %{
5518 constraint(ALLOC_IN_RC(eadx_reg));
5519 match(RegL);
5520
5521 format %{ "EAX" %}
5522 interface(REG_INTER);
5523 %}
5524
5525 // Flags register, used as output of compare instructions
5526 operand eFlagsReg() %{
5527 constraint(ALLOC_IN_RC(int_flags));
5528 match(RegFlags);
5529
5530 format %{ "EFLAGS" %}
5531 interface(REG_INTER);
5532 %}
5533
5534 // Flags register, used as output of FLOATING POINT compare instructions
5535 operand eFlagsRegU() %{
5536 constraint(ALLOC_IN_RC(int_flags));
5537 match(RegFlags);
5538
5539 format %{ "EFLAGS_U" %}
5540 interface(REG_INTER);
5541 %}
5542
5543 operand eFlagsRegUCF() %{
5544 constraint(ALLOC_IN_RC(int_flags));
5545 match(RegFlags);
5546 predicate(false);
5547
5548 format %{ "EFLAGS_U_CF" %}
5549 interface(REG_INTER);
5550 %}
5551
5552 // Condition Code Register used by long compare
5553 operand flagsReg_long_LTGE() %{
5554 constraint(ALLOC_IN_RC(int_flags));
5555 match(RegFlags);
5556 format %{ "FLAGS_LTGE" %}
5557 interface(REG_INTER);
5558 %}
5559 operand flagsReg_long_EQNE() %{
5560 constraint(ALLOC_IN_RC(int_flags));
5561 match(RegFlags);
5562 format %{ "FLAGS_EQNE" %}
5563 interface(REG_INTER);
5564 %}
5565 operand flagsReg_long_LEGT() %{
5566 constraint(ALLOC_IN_RC(int_flags));
5567 match(RegFlags);
5568 format %{ "FLAGS_LEGT" %}
5569 interface(REG_INTER);
5570 %}
5571
5572 // Float register operands
5573 operand regD() %{
5574 predicate( UseSSE < 2 );
5575 constraint(ALLOC_IN_RC(dbl_reg));
5576 match(RegD);
5577 match(regDPR1);
5578 match(regDPR2);
5579 format %{ %}
5580 interface(REG_INTER);
5581 %}
5582
5583 operand regDPR1(regD reg) %{
5584 predicate( UseSSE < 2 );
5585 constraint(ALLOC_IN_RC(dbl_reg0));
5586 match(reg);
5587 format %{ "FPR1" %}
5588 interface(REG_INTER);
5589 %}
5590
5591 operand regDPR2(regD reg) %{
5592 predicate( UseSSE < 2 );
5593 constraint(ALLOC_IN_RC(dbl_reg1));
5594 match(reg);
5595 format %{ "FPR2" %}
5596 interface(REG_INTER);
5597 %}
5598
5599 operand regnotDPR1(regD reg) %{
5600 predicate( UseSSE < 2 );
5601 constraint(ALLOC_IN_RC(dbl_notreg0));
5602 match(reg);
5603 format %{ %}
5604 interface(REG_INTER);
5605 %}
5606
5607 // XMM Double register operands
5608 operand regXD() %{
5609 predicate( UseSSE>=2 );
5610 constraint(ALLOC_IN_RC(xdb_reg));
5611 match(RegD);
5612 match(regXD6);
5613 match(regXD7);
5614 format %{ %}
5615 interface(REG_INTER);
5616 %}
5617
5618 // XMM6 double register operands
5619 operand regXD6(regXD reg) %{
5620 predicate( UseSSE>=2 );
5621 constraint(ALLOC_IN_RC(xdb_reg6));
5622 match(reg);
5623 format %{ "XMM6" %}
5624 interface(REG_INTER);
5625 %}
5626
5627 // XMM7 double register operands
5628 operand regXD7(regXD reg) %{
5629 predicate( UseSSE>=2 );
5630 constraint(ALLOC_IN_RC(xdb_reg7));
5631 match(reg);
5632 format %{ "XMM7" %}
5633 interface(REG_INTER);
5634 %}
5635
5636 // Float register operands
5637 operand regF() %{
5638 predicate( UseSSE < 2 );
5639 constraint(ALLOC_IN_RC(flt_reg));
5640 match(RegF);
5641 match(regFPR1);
5642 format %{ %}
5643 interface(REG_INTER);
5644 %}
5645
5646 // Float register operands
5647 operand regFPR1(regF reg) %{
5648 predicate( UseSSE < 2 );
5649 constraint(ALLOC_IN_RC(flt_reg0));
5650 match(reg);
5651 format %{ "FPR1" %}
5652 interface(REG_INTER);
5653 %}
5654
5655 // XMM register operands
5656 operand regX() %{
5657 predicate( UseSSE>=1 );
5658 constraint(ALLOC_IN_RC(xmm_reg));
5659 match(RegF);
5660 format %{ %}
5661 interface(REG_INTER);
5662 %}
5663
5664
5665 //----------Memory Operands----------------------------------------------------
5666 // Direct Memory Operand
5667 operand direct(immP addr) %{
5668 match(addr);
5669
5670 format %{ "[$addr]" %}
5671 interface(MEMORY_INTER) %{
5672 base(0xFFFFFFFF);
5673 index(0x4);
5674 scale(0x0);
5675 disp($addr);
5676 %}
5677 %}
5678
5679 // Indirect Memory Operand
5680 operand indirect(eRegP reg) %{
5681 constraint(ALLOC_IN_RC(e_reg));
5682 match(reg);
5683
5684 format %{ "[$reg]" %}
5685 interface(MEMORY_INTER) %{
5686 base($reg);
5687 index(0x4);
5688 scale(0x0);
5689 disp(0x0);
5690 %}
5691 %}
5692
5693 // Indirect Memory Plus Short Offset Operand
5694 operand indOffset8(eRegP reg, immI8 off) %{
5695 match(AddP reg off);
5696
5697 format %{ "[$reg + $off]" %}
5698 interface(MEMORY_INTER) %{
5699 base($reg);
5700 index(0x4);
5701 scale(0x0);
5702 disp($off);
5703 %}
5704 %}
5705
5706 // Indirect Memory Plus Long Offset Operand
5707 operand indOffset32(eRegP reg, immI off) %{
5708 match(AddP reg off);
5709
5710 format %{ "[$reg + $off]" %}
5711 interface(MEMORY_INTER) %{
5712 base($reg);
5713 index(0x4);
5714 scale(0x0);
5715 disp($off);
5716 %}
5717 %}
5718
5719 // Indirect Memory Plus Long Offset Operand
5720 operand indOffset32X(eRegI reg, immP off) %{
5721 match(AddP off reg);
5722
5723 format %{ "[$reg + $off]" %}
5724 interface(MEMORY_INTER) %{
5725 base($reg);
5726 index(0x4);
5727 scale(0x0);
5728 disp($off);
5729 %}
5730 %}
5731
5732 // Indirect Memory Plus Index Register Plus Offset Operand
5733 operand indIndexOffset(eRegP reg, eRegI ireg, immI off) %{
5734 match(AddP (AddP reg ireg) off);
5735
5736 op_cost(10);
5737 format %{"[$reg + $off + $ireg]" %}
5738 interface(MEMORY_INTER) %{
5739 base($reg);
5740 index($ireg);
5741 scale(0x0);
5742 disp($off);
5743 %}
5744 %}
5745
5746 // Indirect Memory Plus Index Register Plus Offset Operand
5747 operand indIndex(eRegP reg, eRegI ireg) %{
5748 match(AddP reg ireg);
5749
5750 op_cost(10);
5751 format %{"[$reg + $ireg]" %}
5752 interface(MEMORY_INTER) %{
5753 base($reg);
5754 index($ireg);
5755 scale(0x0);
5756 disp(0x0);
5757 %}
5758 %}
5759
5760 // // -------------------------------------------------------------------------
5761 // // 486 architecture doesn't support "scale * index + offset" with out a base
5762 // // -------------------------------------------------------------------------
5763 // // Scaled Memory Operands
5764 // // Indirect Memory Times Scale Plus Offset Operand
5765 // operand indScaleOffset(immP off, eRegI ireg, immI2 scale) %{
5766 // match(AddP off (LShiftI ireg scale));
5767 //
5768 // op_cost(10);
5769 // format %{"[$off + $ireg << $scale]" %}
5770 // interface(MEMORY_INTER) %{
5771 // base(0x4);
5772 // index($ireg);
5773 // scale($scale);
5774 // disp($off);
5775 // %}
5776 // %}
5777
5778 // Indirect Memory Times Scale Plus Index Register
5779 operand indIndexScale(eRegP reg, eRegI ireg, immI2 scale) %{
5780 match(AddP reg (LShiftI ireg scale));
5781
5782 op_cost(10);
5783 format %{"[$reg + $ireg << $scale]" %}
5784 interface(MEMORY_INTER) %{
5785 base($reg);
5786 index($ireg);
5787 scale($scale);
5788 disp(0x0);
5789 %}
5790 %}
5791
5792 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
5793 operand indIndexScaleOffset(eRegP reg, immI off, eRegI ireg, immI2 scale) %{
5794 match(AddP (AddP reg (LShiftI ireg scale)) off);
5795
5796 op_cost(10);
5797 format %{"[$reg + $off + $ireg << $scale]" %}
5798 interface(MEMORY_INTER) %{
5799 base($reg);
5800 index($ireg);
5801 scale($scale);
5802 disp($off);
5803 %}
5804 %}
5805
5806 //----------Load Long Memory Operands------------------------------------------
5807 // The load-long idiom will use it's address expression again after loading
5808 // the first word of the long. If the load-long destination overlaps with
5809 // registers used in the addressing expression, the 2nd half will be loaded
5810 // from a clobbered address. Fix this by requiring that load-long use
5811 // address registers that do not overlap with the load-long target.
5812
5813 // load-long support
5814 operand load_long_RegP() %{
5815 constraint(ALLOC_IN_RC(esi_reg));
5816 match(RegP);
5817 match(eSIRegP);
5818 op_cost(100);
5819 format %{ %}
5820 interface(REG_INTER);
5821 %}
5822
5823 // Indirect Memory Operand Long
5824 operand load_long_indirect(load_long_RegP reg) %{
5825 constraint(ALLOC_IN_RC(esi_reg));
5826 match(reg);
5827
5828 format %{ "[$reg]" %}
5829 interface(MEMORY_INTER) %{
5830 base($reg);
5831 index(0x4);
5832 scale(0x0);
5833 disp(0x0);
5834 %}
5835 %}
5836
5837 // Indirect Memory Plus Long Offset Operand
5838 operand load_long_indOffset32(load_long_RegP reg, immI off) %{
5839 match(AddP reg off);
5840
5841 format %{ "[$reg + $off]" %}
5842 interface(MEMORY_INTER) %{
5843 base($reg);
5844 index(0x4);
5845 scale(0x0);
5846 disp($off);
5847 %}
5848 %}
5849
5850 opclass load_long_memory(load_long_indirect, load_long_indOffset32);
5851
5852
5853 //----------Special Memory Operands--------------------------------------------
5854 // Stack Slot Operand - This operand is used for loading and storing temporary
5855 // values on the stack where a match requires a value to
5856 // flow through memory.
5857 operand stackSlotP(sRegP reg) %{
5858 constraint(ALLOC_IN_RC(stack_slots));
5859 // No match rule because this operand is only generated in matching
5860 format %{ "[$reg]" %}
5861 interface(MEMORY_INTER) %{
5862 base(0x4); // ESP
5863 index(0x4); // No Index
5864 scale(0x0); // No Scale
5865 disp($reg); // Stack Offset
5866 %}
5867 %}
5868
5869 operand stackSlotI(sRegI reg) %{
5870 constraint(ALLOC_IN_RC(stack_slots));
5871 // No match rule because this operand is only generated in matching
5872 format %{ "[$reg]" %}
5873 interface(MEMORY_INTER) %{
5874 base(0x4); // ESP
5875 index(0x4); // No Index
5876 scale(0x0); // No Scale
5877 disp($reg); // Stack Offset
5878 %}
5879 %}
5880
5881 operand stackSlotF(sRegF reg) %{
5882 constraint(ALLOC_IN_RC(stack_slots));
5883 // No match rule because this operand is only generated in matching
5884 format %{ "[$reg]" %}
5885 interface(MEMORY_INTER) %{
5886 base(0x4); // ESP
5887 index(0x4); // No Index
5888 scale(0x0); // No Scale
5889 disp($reg); // Stack Offset
5890 %}
5891 %}
5892
5893 operand stackSlotD(sRegD reg) %{
5894 constraint(ALLOC_IN_RC(stack_slots));
5895 // No match rule because this operand is only generated in matching
5896 format %{ "[$reg]" %}
5897 interface(MEMORY_INTER) %{
5898 base(0x4); // ESP
5899 index(0x4); // No Index
5900 scale(0x0); // No Scale
5901 disp($reg); // Stack Offset
5902 %}
5903 %}
5904
5905 operand stackSlotL(sRegL reg) %{
5906 constraint(ALLOC_IN_RC(stack_slots));
5907 // No match rule because this operand is only generated in matching
5908 format %{ "[$reg]" %}
5909 interface(MEMORY_INTER) %{
5910 base(0x4); // ESP
5911 index(0x4); // No Index
5912 scale(0x0); // No Scale
5913 disp($reg); // Stack Offset
5914 %}
5915 %}
5916
5917 //----------Memory Operands - Win95 Implicit Null Variants----------------
5918 // Indirect Memory Operand
5919 operand indirect_win95_safe(eRegP_no_EBP reg)
5920 %{
5921 constraint(ALLOC_IN_RC(e_reg));
5922 match(reg);
5923
5924 op_cost(100);
5925 format %{ "[$reg]" %}
5926 interface(MEMORY_INTER) %{
5927 base($reg);
5928 index(0x4);
5929 scale(0x0);
5930 disp(0x0);
5931 %}
5932 %}
5933
5934 // Indirect Memory Plus Short Offset Operand
5935 operand indOffset8_win95_safe(eRegP_no_EBP reg, immI8 off)
5936 %{
5937 match(AddP reg off);
5938
5939 op_cost(100);
5940 format %{ "[$reg + $off]" %}
5941 interface(MEMORY_INTER) %{
5942 base($reg);
5943 index(0x4);
5944 scale(0x0);
5945 disp($off);
5946 %}
5947 %}
5948
5949 // Indirect Memory Plus Long Offset Operand
5950 operand indOffset32_win95_safe(eRegP_no_EBP reg, immI off)
5951 %{
5952 match(AddP reg off);
5953
5954 op_cost(100);
5955 format %{ "[$reg + $off]" %}
5956 interface(MEMORY_INTER) %{
5957 base($reg);
5958 index(0x4);
5959 scale(0x0);
5960 disp($off);
5961 %}
5962 %}
5963
5964 // Indirect Memory Plus Index Register Plus Offset Operand
5965 operand indIndexOffset_win95_safe(eRegP_no_EBP reg, eRegI ireg, immI off)
5966 %{
5967 match(AddP (AddP reg ireg) off);
5968
5969 op_cost(100);
5970 format %{"[$reg + $off + $ireg]" %}
5971 interface(MEMORY_INTER) %{
5972 base($reg);
5973 index($ireg);
5974 scale(0x0);
5975 disp($off);
5976 %}
5977 %}
5978
5979 // Indirect Memory Times Scale Plus Index Register
5980 operand indIndexScale_win95_safe(eRegP_no_EBP reg, eRegI ireg, immI2 scale)
5981 %{
5982 match(AddP reg (LShiftI ireg scale));
5983
5984 op_cost(100);
5985 format %{"[$reg + $ireg << $scale]" %}
5986 interface(MEMORY_INTER) %{
5987 base($reg);
5988 index($ireg);
5989 scale($scale);
5990 disp(0x0);
5991 %}
5992 %}
5993
5994 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
5995 operand indIndexScaleOffset_win95_safe(eRegP_no_EBP reg, immI off, eRegI ireg, immI2 scale)
5996 %{
5997 match(AddP (AddP reg (LShiftI ireg scale)) off);
5998
5999 op_cost(100);
6000 format %{"[$reg + $off + $ireg << $scale]" %}
6001 interface(MEMORY_INTER) %{
6002 base($reg);
6003 index($ireg);
6004 scale($scale);
6005 disp($off);
6006 %}
6007 %}
6008
6009 //----------Conditional Branch Operands----------------------------------------
6010 // Comparison Op - This is the operation of the comparison, and is limited to
6011 // the following set of codes:
6012 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
6013 //
6014 // Other attributes of the comparison, such as unsignedness, are specified
6015 // by the comparison instruction that sets a condition code flags register.
6016 // That result is represented by a flags operand whose subtype is appropriate
6017 // to the unsignedness (etc.) of the comparison.
6018 //
6019 // Later, the instruction which matches both the Comparison Op (a Bool) and
6020 // the flags (produced by the Cmp) specifies the coding of the comparison op
6021 // by matching a specific subtype of Bool operand below, such as cmpOpU.
6022
6023 // Comparision Code
6024 operand cmpOp() %{
6025 match(Bool);
6026
6027 format %{ "" %}
6028 interface(COND_INTER) %{
6029 equal(0x4, "e");
6030 not_equal(0x5, "ne");
6031 less(0xC, "l");
6032 greater_equal(0xD, "ge");
6033 less_equal(0xE, "le");
6034 greater(0xF, "g");
6035 %}
6036 %}
6037
6038 // Comparison Code, unsigned compare. Used by FP also, with
6039 // C2 (unordered) turned into GT or LT already. The other bits
6040 // C0 and C3 are turned into Carry & Zero flags.
6041 operand cmpOpU() %{
6042 match(Bool);
6043
6044 format %{ "" %}
6045 interface(COND_INTER) %{
6046 equal(0x4, "e");
6047 not_equal(0x5, "ne");
6048 less(0x2, "b");
6049 greater_equal(0x3, "nb");
6050 less_equal(0x6, "be");
6051 greater(0x7, "nbe");
6052 %}
6053 %}
6054
6055 // Floating comparisons that don't require any fixup for the unordered case
6056 operand cmpOpUCF() %{
6057 match(Bool);
6058 predicate(n->as_Bool()->_test._test == BoolTest::lt ||
6059 n->as_Bool()->_test._test == BoolTest::ge ||
6060 n->as_Bool()->_test._test == BoolTest::le ||
6061 n->as_Bool()->_test._test == BoolTest::gt);
6062 format %{ "" %}
6063 interface(COND_INTER) %{
6064 equal(0x4, "e");
6065 not_equal(0x5, "ne");
6066 less(0x2, "b");
6067 greater_equal(0x3, "nb");
6068 less_equal(0x6, "be");
6069 greater(0x7, "nbe");
6070 %}
6071 %}
6072
6073
6074 // Floating comparisons that can be fixed up with extra conditional jumps
6075 operand cmpOpUCF2() %{
6076 match(Bool);
6077 predicate(n->as_Bool()->_test._test == BoolTest::ne ||
6078 n->as_Bool()->_test._test == BoolTest::eq);
6079 format %{ "" %}
6080 interface(COND_INTER) %{
6081 equal(0x4, "e");
6082 not_equal(0x5, "ne");
6083 less(0x2, "b");
6084 greater_equal(0x3, "nb");
6085 less_equal(0x6, "be");
6086 greater(0x7, "nbe");
6087 %}
6088 %}
6089
6090 // Comparison Code for FP conditional move
6091 operand cmpOp_fcmov() %{
6092 match(Bool);
6093
6094 format %{ "" %}
6095 interface(COND_INTER) %{
6096 equal (0x0C8);
6097 not_equal (0x1C8);
6098 less (0x0C0);
6099 greater_equal(0x1C0);
6100 less_equal (0x0D0);
6101 greater (0x1D0);
6102 %}
6103 %}
6104
6105 // Comparision Code used in long compares
6106 operand cmpOp_commute() %{
6107 match(Bool);
6108
6109 format %{ "" %}
6110 interface(COND_INTER) %{
6111 equal(0x4, "e");
6112 not_equal(0x5, "ne");
6113 less(0xF, "g");
6114 greater_equal(0xE, "le");
6115 less_equal(0xD, "ge");
6116 greater(0xC, "l");
6117 %}
6118 %}
6119
6120 //----------OPERAND CLASSES----------------------------------------------------
6121 // Operand Classes are groups of operands that are used as to simplify
6122 // instruction definitions by not requiring the AD writer to specify separate
6123 // instructions for every form of operand when the instruction accepts
6124 // multiple operand types with the same basic encoding and format. The classic
6125 // case of this is memory operands.
6126
6127 opclass memory(direct, indirect, indOffset8, indOffset32, indOffset32X, indIndexOffset,
6128 indIndex, indIndexScale, indIndexScaleOffset);
6129
6130 // Long memory operations are encoded in 2 instructions and a +4 offset.
6131 // This means some kind of offset is always required and you cannot use
6132 // an oop as the offset (done when working on static globals).
6133 opclass long_memory(direct, indirect, indOffset8, indOffset32, indIndexOffset,
6134 indIndex, indIndexScale, indIndexScaleOffset);
6135
6136
6137 //----------PIPELINE-----------------------------------------------------------
6138 // Rules which define the behavior of the target architectures pipeline.
6139 pipeline %{
6140
6141 //----------ATTRIBUTES---------------------------------------------------------
6142 attributes %{
6143 variable_size_instructions; // Fixed size instructions
6144 max_instructions_per_bundle = 3; // Up to 3 instructions per bundle
6145 instruction_unit_size = 1; // An instruction is 1 bytes long
6146 instruction_fetch_unit_size = 16; // The processor fetches one line
6147 instruction_fetch_units = 1; // of 16 bytes
6148
6149 // List of nop instructions
6150 nops( MachNop );
6151 %}
6152
6153 //----------RESOURCES----------------------------------------------------------
6154 // Resources are the functional units available to the machine
6155
6156 // Generic P2/P3 pipeline
6157 // 3 decoders, only D0 handles big operands; a "bundle" is the limit of
6158 // 3 instructions decoded per cycle.
6159 // 2 load/store ops per cycle, 1 branch, 1 FPU,
6160 // 2 ALU op, only ALU0 handles mul/div instructions.
6161 resources( D0, D1, D2, DECODE = D0 | D1 | D2,
6162 MS0, MS1, MEM = MS0 | MS1,
6163 BR, FPU,
6164 ALU0, ALU1, ALU = ALU0 | ALU1 );
6165
6166 //----------PIPELINE DESCRIPTION-----------------------------------------------
6167 // Pipeline Description specifies the stages in the machine's pipeline
6168
6169 // Generic P2/P3 pipeline
6170 pipe_desc(S0, S1, S2, S3, S4, S5);
6171
6172 //----------PIPELINE CLASSES---------------------------------------------------
6173 // Pipeline Classes describe the stages in which input and output are
6174 // referenced by the hardware pipeline.
6175
6176 // Naming convention: ialu or fpu
6177 // Then: _reg
6178 // Then: _reg if there is a 2nd register
6179 // Then: _long if it's a pair of instructions implementing a long
6180 // Then: _fat if it requires the big decoder
6181 // Or: _mem if it requires the big decoder and a memory unit.
6182
6183 // Integer ALU reg operation
6184 pipe_class ialu_reg(eRegI dst) %{
6185 single_instruction;
6186 dst : S4(write);
6187 dst : S3(read);
6188 DECODE : S0; // any decoder
6189 ALU : S3; // any alu
6190 %}
6191
6192 // Long ALU reg operation
6193 pipe_class ialu_reg_long(eRegL dst) %{
6194 instruction_count(2);
6195 dst : S4(write);
6196 dst : S3(read);
6197 DECODE : S0(2); // any 2 decoders
6198 ALU : S3(2); // both alus
6199 %}
6200
6201 // Integer ALU reg operation using big decoder
6202 pipe_class ialu_reg_fat(eRegI dst) %{
6203 single_instruction;
6204 dst : S4(write);
6205 dst : S3(read);
6206 D0 : S0; // big decoder only
6207 ALU : S3; // any alu
6208 %}
6209
6210 // Long ALU reg operation using big decoder
6211 pipe_class ialu_reg_long_fat(eRegL dst) %{
6212 instruction_count(2);
6213 dst : S4(write);
6214 dst : S3(read);
6215 D0 : S0(2); // big decoder only; twice
6216 ALU : S3(2); // any 2 alus
6217 %}
6218
6219 // Integer ALU reg-reg operation
6220 pipe_class ialu_reg_reg(eRegI dst, eRegI src) %{
6221 single_instruction;
6222 dst : S4(write);
6223 src : S3(read);
6224 DECODE : S0; // any decoder
6225 ALU : S3; // any alu
6226 %}
6227
6228 // Long ALU reg-reg operation
6229 pipe_class ialu_reg_reg_long(eRegL dst, eRegL src) %{
6230 instruction_count(2);
6231 dst : S4(write);
6232 src : S3(read);
6233 DECODE : S0(2); // any 2 decoders
6234 ALU : S3(2); // both alus
6235 %}
6236
6237 // Integer ALU reg-reg operation
6238 pipe_class ialu_reg_reg_fat(eRegI dst, memory src) %{
6239 single_instruction;
6240 dst : S4(write);
6241 src : S3(read);
6242 D0 : S0; // big decoder only
6243 ALU : S3; // any alu
6244 %}
6245
6246 // Long ALU reg-reg operation
6247 pipe_class ialu_reg_reg_long_fat(eRegL dst, eRegL src) %{
6248 instruction_count(2);
6249 dst : S4(write);
6250 src : S3(read);
6251 D0 : S0(2); // big decoder only; twice
6252 ALU : S3(2); // both alus
6253 %}
6254
6255 // Integer ALU reg-mem operation
6256 pipe_class ialu_reg_mem(eRegI dst, memory mem) %{
6257 single_instruction;
6258 dst : S5(write);
6259 mem : S3(read);
6260 D0 : S0; // big decoder only
6261 ALU : S4; // any alu
6262 MEM : S3; // any mem
6263 %}
6264
6265 // Long ALU reg-mem operation
6266 pipe_class ialu_reg_long_mem(eRegL dst, load_long_memory mem) %{
6267 instruction_count(2);
6268 dst : S5(write);
6269 mem : S3(read);
6270 D0 : S0(2); // big decoder only; twice
6271 ALU : S4(2); // any 2 alus
6272 MEM : S3(2); // both mems
6273 %}
6274
6275 // Integer mem operation (prefetch)
6276 pipe_class ialu_mem(memory mem)
6277 %{
6278 single_instruction;
6279 mem : S3(read);
6280 D0 : S0; // big decoder only
6281 MEM : S3; // any mem
6282 %}
6283
6284 // Integer Store to Memory
6285 pipe_class ialu_mem_reg(memory mem, eRegI src) %{
6286 single_instruction;
6287 mem : S3(read);
6288 src : S5(read);
6289 D0 : S0; // big decoder only
6290 ALU : S4; // any alu
6291 MEM : S3;
6292 %}
6293
6294 // Long Store to Memory
6295 pipe_class ialu_mem_long_reg(memory mem, eRegL src) %{
6296 instruction_count(2);
6297 mem : S3(read);
6298 src : S5(read);
6299 D0 : S0(2); // big decoder only; twice
6300 ALU : S4(2); // any 2 alus
6301 MEM : S3(2); // Both mems
6302 %}
6303
6304 // Integer Store to Memory
6305 pipe_class ialu_mem_imm(memory mem) %{
6306 single_instruction;
6307 mem : S3(read);
6308 D0 : S0; // big decoder only
6309 ALU : S4; // any alu
6310 MEM : S3;
6311 %}
6312
6313 // Integer ALU0 reg-reg operation
6314 pipe_class ialu_reg_reg_alu0(eRegI dst, eRegI src) %{
6315 single_instruction;
6316 dst : S4(write);
6317 src : S3(read);
6318 D0 : S0; // Big decoder only
6319 ALU0 : S3; // only alu0
6320 %}
6321
6322 // Integer ALU0 reg-mem operation
6323 pipe_class ialu_reg_mem_alu0(eRegI dst, memory mem) %{
6324 single_instruction;
6325 dst : S5(write);
6326 mem : S3(read);
6327 D0 : S0; // big decoder only
6328 ALU0 : S4; // ALU0 only
6329 MEM : S3; // any mem
6330 %}
6331
6332 // Integer ALU reg-reg operation
6333 pipe_class ialu_cr_reg_reg(eFlagsReg cr, eRegI src1, eRegI src2) %{
6334 single_instruction;
6335 cr : S4(write);
6336 src1 : S3(read);
6337 src2 : S3(read);
6338 DECODE : S0; // any decoder
6339 ALU : S3; // any alu
6340 %}
6341
6342 // Integer ALU reg-imm operation
6343 pipe_class ialu_cr_reg_imm(eFlagsReg cr, eRegI src1) %{
6344 single_instruction;
6345 cr : S4(write);
6346 src1 : S3(read);
6347 DECODE : S0; // any decoder
6348 ALU : S3; // any alu
6349 %}
6350
6351 // Integer ALU reg-mem operation
6352 pipe_class ialu_cr_reg_mem(eFlagsReg cr, eRegI src1, memory src2) %{
6353 single_instruction;
6354 cr : S4(write);
6355 src1 : S3(read);
6356 src2 : S3(read);
6357 D0 : S0; // big decoder only
6358 ALU : S4; // any alu
6359 MEM : S3;
6360 %}
6361
6362 // Conditional move reg-reg
6363 pipe_class pipe_cmplt( eRegI p, eRegI q, eRegI y ) %{
6364 instruction_count(4);
6365 y : S4(read);
6366 q : S3(read);
6367 p : S3(read);
6368 DECODE : S0(4); // any decoder
6369 %}
6370
6371 // Conditional move reg-reg
6372 pipe_class pipe_cmov_reg( eRegI dst, eRegI src, eFlagsReg cr ) %{
6373 single_instruction;
6374 dst : S4(write);
6375 src : S3(read);
6376 cr : S3(read);
6377 DECODE : S0; // any decoder
6378 %}
6379
6380 // Conditional move reg-mem
6381 pipe_class pipe_cmov_mem( eFlagsReg cr, eRegI dst, memory src) %{
6382 single_instruction;
6383 dst : S4(write);
6384 src : S3(read);
6385 cr : S3(read);
6386 DECODE : S0; // any decoder
6387 MEM : S3;
6388 %}
6389
6390 // Conditional move reg-reg long
6391 pipe_class pipe_cmov_reg_long( eFlagsReg cr, eRegL dst, eRegL src) %{
6392 single_instruction;
6393 dst : S4(write);
6394 src : S3(read);
6395 cr : S3(read);
6396 DECODE : S0(2); // any 2 decoders
6397 %}
6398
6399 // Conditional move double reg-reg
6400 pipe_class pipe_cmovD_reg( eFlagsReg cr, regDPR1 dst, regD src) %{
6401 single_instruction;
6402 dst : S4(write);
6403 src : S3(read);
6404 cr : S3(read);
6405 DECODE : S0; // any decoder
6406 %}
6407
6408 // Float reg-reg operation
6409 pipe_class fpu_reg(regD dst) %{
6410 instruction_count(2);
6411 dst : S3(read);
6412 DECODE : S0(2); // any 2 decoders
6413 FPU : S3;
6414 %}
6415
6416 // Float reg-reg operation
6417 pipe_class fpu_reg_reg(regD dst, regD src) %{
6418 instruction_count(2);
6419 dst : S4(write);
6420 src : S3(read);
6421 DECODE : S0(2); // any 2 decoders
6422 FPU : S3;
6423 %}
6424
6425 // Float reg-reg operation
6426 pipe_class fpu_reg_reg_reg(regD dst, regD src1, regD src2) %{
6427 instruction_count(3);
6428 dst : S4(write);
6429 src1 : S3(read);
6430 src2 : S3(read);
6431 DECODE : S0(3); // any 3 decoders
6432 FPU : S3(2);
6433 %}
6434
6435 // Float reg-reg operation
6436 pipe_class fpu_reg_reg_reg_reg(regD dst, regD src1, regD src2, regD src3) %{
6437 instruction_count(4);
6438 dst : S4(write);
6439 src1 : S3(read);
6440 src2 : S3(read);
6441 src3 : S3(read);
6442 DECODE : S0(4); // any 3 decoders
6443 FPU : S3(2);
6444 %}
6445
6446 // Float reg-reg operation
6447 pipe_class fpu_reg_mem_reg_reg(regD dst, memory src1, regD src2, regD src3) %{
6448 instruction_count(4);
6449 dst : S4(write);
6450 src1 : S3(read);
6451 src2 : S3(read);
6452 src3 : S3(read);
6453 DECODE : S1(3); // any 3 decoders
6454 D0 : S0; // Big decoder only
6455 FPU : S3(2);
6456 MEM : S3;
6457 %}
6458
6459 // Float reg-mem operation
6460 pipe_class fpu_reg_mem(regD dst, memory mem) %{
6461 instruction_count(2);
6462 dst : S5(write);
6463 mem : S3(read);
6464 D0 : S0; // big decoder only
6465 DECODE : S1; // any decoder for FPU POP
6466 FPU : S4;
6467 MEM : S3; // any mem
6468 %}
6469
6470 // Float reg-mem operation
6471 pipe_class fpu_reg_reg_mem(regD dst, regD src1, memory mem) %{
6472 instruction_count(3);
6473 dst : S5(write);
6474 src1 : S3(read);
6475 mem : S3(read);
6476 D0 : S0; // big decoder only
6477 DECODE : S1(2); // any decoder for FPU POP
6478 FPU : S4;
6479 MEM : S3; // any mem
6480 %}
6481
6482 // Float mem-reg operation
6483 pipe_class fpu_mem_reg(memory mem, regD src) %{
6484 instruction_count(2);
6485 src : S5(read);
6486 mem : S3(read);
6487 DECODE : S0; // any decoder for FPU PUSH
6488 D0 : S1; // big decoder only
6489 FPU : S4;
6490 MEM : S3; // any mem
6491 %}
6492
6493 pipe_class fpu_mem_reg_reg(memory mem, regD src1, regD src2) %{
6494 instruction_count(3);
6495 src1 : S3(read);
6496 src2 : S3(read);
6497 mem : S3(read);
6498 DECODE : S0(2); // any decoder for FPU PUSH
6499 D0 : S1; // big decoder only
6500 FPU : S4;
6501 MEM : S3; // any mem
6502 %}
6503
6504 pipe_class fpu_mem_reg_mem(memory mem, regD src1, memory src2) %{
6505 instruction_count(3);
6506 src1 : S3(read);
6507 src2 : S3(read);
6508 mem : S4(read);
6509 DECODE : S0; // any decoder for FPU PUSH
6510 D0 : S0(2); // big decoder only
6511 FPU : S4;
6512 MEM : S3(2); // any mem
6513 %}
6514
6515 pipe_class fpu_mem_mem(memory dst, memory src1) %{
6516 instruction_count(2);
6517 src1 : S3(read);
6518 dst : S4(read);
6519 D0 : S0(2); // big decoder only
6520 MEM : S3(2); // any mem
6521 %}
6522
6523 pipe_class fpu_mem_mem_mem(memory dst, memory src1, memory src2) %{
6524 instruction_count(3);
6525 src1 : S3(read);
6526 src2 : S3(read);
6527 dst : S4(read);
6528 D0 : S0(3); // big decoder only
6529 FPU : S4;
6530 MEM : S3(3); // any mem
6531 %}
6532
6533 pipe_class fpu_mem_reg_con(memory mem, regD src1) %{
6534 instruction_count(3);
6535 src1 : S4(read);
6536 mem : S4(read);
6537 DECODE : S0; // any decoder for FPU PUSH
6538 D0 : S0(2); // big decoder only
6539 FPU : S4;
6540 MEM : S3(2); // any mem
6541 %}
6542
6543 // Float load constant
6544 pipe_class fpu_reg_con(regD dst) %{
6545 instruction_count(2);
6546 dst : S5(write);
6547 D0 : S0; // big decoder only for the load
6548 DECODE : S1; // any decoder for FPU POP
6549 FPU : S4;
6550 MEM : S3; // any mem
6551 %}
6552
6553 // Float load constant
6554 pipe_class fpu_reg_reg_con(regD dst, regD src) %{
6555 instruction_count(3);
6556 dst : S5(write);
6557 src : S3(read);
6558 D0 : S0; // big decoder only for the load
6559 DECODE : S1(2); // any decoder for FPU POP
6560 FPU : S4;
6561 MEM : S3; // any mem
6562 %}
6563
6564 // UnConditional branch
6565 pipe_class pipe_jmp( label labl ) %{
6566 single_instruction;
6567 BR : S3;
6568 %}
6569
6570 // Conditional branch
6571 pipe_class pipe_jcc( cmpOp cmp, eFlagsReg cr, label labl ) %{
6572 single_instruction;
6573 cr : S1(read);
6574 BR : S3;
6575 %}
6576
6577 // Allocation idiom
6578 pipe_class pipe_cmpxchg( eRegP dst, eRegP heap_ptr ) %{
6579 instruction_count(1); force_serialization;
6580 fixed_latency(6);
6581 heap_ptr : S3(read);
6582 DECODE : S0(3);
6583 D0 : S2;
6584 MEM : S3;
6585 ALU : S3(2);
6586 dst : S5(write);
6587 BR : S5;
6588 %}
6589
6590 // Generic big/slow expanded idiom
6591 pipe_class pipe_slow( ) %{
6592 instruction_count(10); multiple_bundles; force_serialization;
6593 fixed_latency(100);
6594 D0 : S0(2);
6595 MEM : S3(2);
6596 %}
6597
6598 // The real do-nothing guy
6599 pipe_class empty( ) %{
6600 instruction_count(0);
6601 %}
6602
6603 // Define the class for the Nop node
6604 define %{
6605 MachNop = empty;
6606 %}
6607
6608 %}
6609
6610 //----------INSTRUCTIONS-------------------------------------------------------
6611 //
6612 // match -- States which machine-independent subtree may be replaced
6613 // by this instruction.
6614 // ins_cost -- The estimated cost of this instruction is used by instruction
6615 // selection to identify a minimum cost tree of machine
6616 // instructions that matches a tree of machine-independent
6617 // instructions.
6618 // format -- A string providing the disassembly for this instruction.
6619 // The value of an instruction's operand may be inserted
6620 // by referring to it with a '$' prefix.
6621 // opcode -- Three instruction opcodes may be provided. These are referred
6622 // to within an encode class as $primary, $secondary, and $tertiary
6623 // respectively. The primary opcode is commonly used to
6624 // indicate the type of machine instruction, while secondary
6625 // and tertiary are often used for prefix options or addressing
6626 // modes.
6627 // ins_encode -- A list of encode classes with parameters. The encode class
6628 // name must have been defined in an 'enc_class' specification
6629 // in the encode section of the architecture description.
6630
6631 //----------BSWAP-Instruction--------------------------------------------------
6632 instruct bytes_reverse_int(eRegI dst) %{
6633 match(Set dst (ReverseBytesI dst));
6634
6635 format %{ "BSWAP $dst" %}
6636 opcode(0x0F, 0xC8);
6637 ins_encode( OpcP, OpcSReg(dst) );
6638 ins_pipe( ialu_reg );
6639 %}
6640
6641 instruct bytes_reverse_long(eRegL dst) %{
6642 match(Set dst (ReverseBytesL dst));
6643
6644 format %{ "BSWAP $dst.lo\n\t"
6645 "BSWAP $dst.hi\n\t"
6646 "XCHG $dst.lo $dst.hi" %}
6647
6648 ins_cost(125);
6649 ins_encode( bswap_long_bytes(dst) );
6650 ins_pipe( ialu_reg_reg);
6651 %}
6652
6653
6654 //---------- Zeros Count Instructions ------------------------------------------
6655
6656 instruct countLeadingZerosI(eRegI dst, eRegI src, eFlagsReg cr) %{
6657 predicate(UseCountLeadingZerosInstruction);
6658 match(Set dst (CountLeadingZerosI src));
6659 effect(KILL cr);
6660
6661 format %{ "LZCNT $dst, $src\t# count leading zeros (int)" %}
6662 ins_encode %{
6663 __ lzcntl($dst$$Register, $src$$Register);
6664 %}
6665 ins_pipe(ialu_reg);
6666 %}
6667
6668 instruct countLeadingZerosI_bsr(eRegI dst, eRegI src, eFlagsReg cr) %{
6669 predicate(!UseCountLeadingZerosInstruction);
6670 match(Set dst (CountLeadingZerosI src));
6671 effect(KILL cr);
6672
6673 format %{ "BSR $dst, $src\t# count leading zeros (int)\n\t"
6674 "JNZ skip\n\t"
6675 "MOV $dst, -1\n"
6676 "skip:\n\t"
6677 "NEG $dst\n\t"
6678 "ADD $dst, 31" %}
6679 ins_encode %{
6680 Register Rdst = $dst$$Register;
6681 Register Rsrc = $src$$Register;
6682 Label skip;
6683 __ bsrl(Rdst, Rsrc);
6684 __ jccb(Assembler::notZero, skip);
6685 __ movl(Rdst, -1);
6686 __ bind(skip);
6687 __ negl(Rdst);
6688 __ addl(Rdst, BitsPerInt - 1);
6689 %}
6690 ins_pipe(ialu_reg);
6691 %}
6692
6693 instruct countLeadingZerosL(eRegI dst, eRegL src, eFlagsReg cr) %{
6694 predicate(UseCountLeadingZerosInstruction);
6695 match(Set dst (CountLeadingZerosL src));
6696 effect(TEMP dst, KILL cr);
6697
6698 format %{ "LZCNT $dst, $src.hi\t# count leading zeros (long)\n\t"
6699 "JNC done\n\t"
6700 "LZCNT $dst, $src.lo\n\t"
6701 "ADD $dst, 32\n"
6702 "done:" %}
6703 ins_encode %{
6704 Register Rdst = $dst$$Register;
6705 Register Rsrc = $src$$Register;
6706 Label done;
6707 __ lzcntl(Rdst, HIGH_FROM_LOW(Rsrc));
6708 __ jccb(Assembler::carryClear, done);
6709 __ lzcntl(Rdst, Rsrc);
6710 __ addl(Rdst, BitsPerInt);
6711 __ bind(done);
6712 %}
6713 ins_pipe(ialu_reg);
6714 %}
6715
6716 instruct countLeadingZerosL_bsr(eRegI dst, eRegL src, eFlagsReg cr) %{
6717 predicate(!UseCountLeadingZerosInstruction);
6718 match(Set dst (CountLeadingZerosL src));
6719 effect(TEMP dst, KILL cr);
6720
6721 format %{ "BSR $dst, $src.hi\t# count leading zeros (long)\n\t"
6722 "JZ msw_is_zero\n\t"
6723 "ADD $dst, 32\n\t"
6724 "JMP not_zero\n"
6725 "msw_is_zero:\n\t"
6726 "BSR $dst, $src.lo\n\t"
6727 "JNZ not_zero\n\t"
6728 "MOV $dst, -1\n"
6729 "not_zero:\n\t"
6730 "NEG $dst\n\t"
6731 "ADD $dst, 63\n" %}
6732 ins_encode %{
6733 Register Rdst = $dst$$Register;
6734 Register Rsrc = $src$$Register;
6735 Label msw_is_zero;
6736 Label not_zero;
6737 __ bsrl(Rdst, HIGH_FROM_LOW(Rsrc));
6738 __ jccb(Assembler::zero, msw_is_zero);
6739 __ addl(Rdst, BitsPerInt);
6740 __ jmpb(not_zero);
6741 __ bind(msw_is_zero);
6742 __ bsrl(Rdst, Rsrc);
6743 __ jccb(Assembler::notZero, not_zero);
6744 __ movl(Rdst, -1);
6745 __ bind(not_zero);
6746 __ negl(Rdst);
6747 __ addl(Rdst, BitsPerLong - 1);
6748 %}
6749 ins_pipe(ialu_reg);
6750 %}
6751
6752 instruct countTrailingZerosI(eRegI dst, eRegI src, eFlagsReg cr) %{
6753 match(Set dst (CountTrailingZerosI src));
6754 effect(KILL cr);
6755
6756 format %{ "BSF $dst, $src\t# count trailing zeros (int)\n\t"
6757 "JNZ done\n\t"
6758 "MOV $dst, 32\n"
6759 "done:" %}
6760 ins_encode %{
6761 Register Rdst = $dst$$Register;
6762 Label done;
6763 __ bsfl(Rdst, $src$$Register);
6764 __ jccb(Assembler::notZero, done);
6765 __ movl(Rdst, BitsPerInt);
6766 __ bind(done);
6767 %}
6768 ins_pipe(ialu_reg);
6769 %}
6770
6771 instruct countTrailingZerosL(eRegI dst, eRegL src, eFlagsReg cr) %{
6772 match(Set dst (CountTrailingZerosL src));
6773 effect(TEMP dst, KILL cr);
6774
6775 format %{ "BSF $dst, $src.lo\t# count trailing zeros (long)\n\t"
6776 "JNZ done\n\t"
6777 "BSF $dst, $src.hi\n\t"
6778 "JNZ msw_not_zero\n\t"
6779 "MOV $dst, 32\n"
6780 "msw_not_zero:\n\t"
6781 "ADD $dst, 32\n"
6782 "done:" %}
6783 ins_encode %{
6784 Register Rdst = $dst$$Register;
6785 Register Rsrc = $src$$Register;
6786 Label msw_not_zero;
6787 Label done;
6788 __ bsfl(Rdst, Rsrc);
6789 __ jccb(Assembler::notZero, done);
6790 __ bsfl(Rdst, HIGH_FROM_LOW(Rsrc));
6791 __ jccb(Assembler::notZero, msw_not_zero);
6792 __ movl(Rdst, BitsPerInt);
6793 __ bind(msw_not_zero);
6794 __ addl(Rdst, BitsPerInt);
6795 __ bind(done);
6796 %}
6797 ins_pipe(ialu_reg);
6798 %}
6799
6800
6801 //---------- Population Count Instructions -------------------------------------
6802
6803 instruct popCountI(eRegI dst, eRegI src) %{
6804 predicate(UsePopCountInstruction);
6805 match(Set dst (PopCountI src));
6806
6807 format %{ "POPCNT $dst, $src" %}
6808 ins_encode %{
6809 __ popcntl($dst$$Register, $src$$Register);
6810 %}
6811 ins_pipe(ialu_reg);
6812 %}
6813
6814 instruct popCountI_mem(eRegI dst, memory mem) %{
6815 predicate(UsePopCountInstruction);
6816 match(Set dst (PopCountI (LoadI mem)));
6817
6818 format %{ "POPCNT $dst, $mem" %}
6819 ins_encode %{
6820 __ popcntl($dst$$Register, $mem$$Address);
6821 %}
6822 ins_pipe(ialu_reg);
6823 %}
6824
6825 // Note: Long.bitCount(long) returns an int.
6826 instruct popCountL(eRegI dst, eRegL src, eRegI tmp, eFlagsReg cr) %{
6827 predicate(UsePopCountInstruction);
6828 match(Set dst (PopCountL src));
6829 effect(KILL cr, TEMP tmp, TEMP dst);
6830
6831 format %{ "POPCNT $dst, $src.lo\n\t"
6832 "POPCNT $tmp, $src.hi\n\t"
6833 "ADD $dst, $tmp" %}
6834 ins_encode %{
6835 __ popcntl($dst$$Register, $src$$Register);
6836 __ popcntl($tmp$$Register, HIGH_FROM_LOW($src$$Register));
6837 __ addl($dst$$Register, $tmp$$Register);
6838 %}
6839 ins_pipe(ialu_reg);
6840 %}
6841
6842 // Note: Long.bitCount(long) returns an int.
6843 instruct popCountL_mem(eRegI dst, memory mem, eRegI tmp, eFlagsReg cr) %{
6844 predicate(UsePopCountInstruction);
6845 match(Set dst (PopCountL (LoadL mem)));
6846 effect(KILL cr, TEMP tmp, TEMP dst);
6847
6848 format %{ "POPCNT $dst, $mem\n\t"
6849 "POPCNT $tmp, $mem+4\n\t"
6850 "ADD $dst, $tmp" %}
6851 ins_encode %{
6852 //__ popcntl($dst$$Register, $mem$$Address$$first);
6853 //__ popcntl($tmp$$Register, $mem$$Address$$second);
6854 __ popcntl($dst$$Register, Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp, false));
6855 __ popcntl($tmp$$Register, Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp + 4, false));
6856 __ addl($dst$$Register, $tmp$$Register);
6857 %}
6858 ins_pipe(ialu_reg);
6859 %}
6860
6861
6862 //----------Load/Store/Move Instructions---------------------------------------
6863 //----------Load Instructions--------------------------------------------------
6864 // Load Byte (8bit signed)
6865 instruct loadB(xRegI dst, memory mem) %{
6866 match(Set dst (LoadB mem));
6867
6868 ins_cost(125);
6869 format %{ "MOVSX8 $dst,$mem\t# byte" %}
6870
6871 ins_encode %{
6872 __ movsbl($dst$$Register, $mem$$Address);
6873 %}
6874
6875 ins_pipe(ialu_reg_mem);
6876 %}
6877
6878 // Load Byte (8bit signed) into Long Register
6879 instruct loadB2L(eRegL dst, memory mem) %{
6880 match(Set dst (ConvI2L (LoadB mem)));
6881
6882 ins_cost(375);
6883 format %{ "MOVSX8 $dst.lo,$mem\t# byte -> long\n\t"
6884 "MOV $dst.hi,$dst.lo\n\t"
6885 "SAR $dst.hi,7" %}
6886
6887 ins_encode %{
6888 __ movsbl($dst$$Register, $mem$$Address);
6889 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
6890 __ sarl(HIGH_FROM_LOW($dst$$Register), 7); // 24+1 MSB are already signed extended.
6891 %}
6892
6893 ins_pipe(ialu_reg_mem);
6894 %}
6895
6896 // Load Unsigned Byte (8bit UNsigned)
6897 instruct loadUB(xRegI dst, memory mem) %{
6898 match(Set dst (LoadUB mem));
6899
6900 ins_cost(125);
6901 format %{ "MOVZX8 $dst,$mem\t# ubyte -> int" %}
6902
6903 ins_encode %{
6904 __ movzbl($dst$$Register, $mem$$Address);
6905 %}
6906
6907 ins_pipe(ialu_reg_mem);
6908 %}
6909
6910 // Load Unsigned Byte (8 bit UNsigned) into Long Register
6911 instruct loadUB2L(eRegL dst, memory mem)
6912 %{
6913 match(Set dst (ConvI2L (LoadUB mem)));
6914
6915 ins_cost(250);
6916 format %{ "MOVZX8 $dst.lo,$mem\t# ubyte -> long\n\t"
6917 "XOR $dst.hi,$dst.hi" %}
6918
6919 ins_encode %{
6920 __ movzbl($dst$$Register, $mem$$Address);
6921 __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register));
6922 %}
6923
6924 ins_pipe(ialu_reg_mem);
6925 %}
6926
6927 // Load Short (16bit signed)
6928 instruct loadS(eRegI dst, memory mem) %{
6929 match(Set dst (LoadS mem));
6930
6931 ins_cost(125);
6932 format %{ "MOVSX $dst,$mem\t# short" %}
6933
6934 ins_encode %{
6935 __ movswl($dst$$Register, $mem$$Address);
6936 %}
6937
6938 ins_pipe(ialu_reg_mem);
6939 %}
6940
6941 // Load Short (16bit signed) into Long Register
6942 instruct loadS2L(eRegL dst, memory mem) %{
6943 match(Set dst (ConvI2L (LoadS mem)));
6944
6945 ins_cost(375);
6946 format %{ "MOVSX $dst.lo,$mem\t# short -> long\n\t"
6947 "MOV $dst.hi,$dst.lo\n\t"
6948 "SAR $dst.hi,15" %}
6949
6950 ins_encode %{
6951 __ movswl($dst$$Register, $mem$$Address);
6952 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
6953 __ sarl(HIGH_FROM_LOW($dst$$Register), 15); // 16+1 MSB are already signed extended.
6954 %}
6955
6956 ins_pipe(ialu_reg_mem);
6957 %}
6958
6959 // Load Unsigned Short/Char (16bit unsigned)
6960 instruct loadUS(eRegI dst, memory mem) %{
6961 match(Set dst (LoadUS mem));
6962
6963 ins_cost(125);
6964 format %{ "MOVZX $dst,$mem\t# ushort/char -> int" %}
6965
6966 ins_encode %{
6967 __ movzwl($dst$$Register, $mem$$Address);
6968 %}
6969
6970 ins_pipe(ialu_reg_mem);
6971 %}
6972
6973 // Load Unsigned Short/Char (16 bit UNsigned) into Long Register
6974 instruct loadUS2L(eRegL dst, memory mem)
6975 %{
6976 match(Set dst (ConvI2L (LoadUS mem)));
6977
6978 ins_cost(250);
6979 format %{ "MOVZX $dst.lo,$mem\t# ushort/char -> long\n\t"
6980 "XOR $dst.hi,$dst.hi" %}
6981
6982 ins_encode %{
6983 __ movzwl($dst$$Register, $mem$$Address);
6984 __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register));
6985 %}
6986
6987 ins_pipe(ialu_reg_mem);
6988 %}
6989
6990 // Load Integer
6991 instruct loadI(eRegI dst, memory mem) %{
6992 match(Set dst (LoadI mem));
6993
6994 ins_cost(125);
6995 format %{ "MOV $dst,$mem\t# int" %}
6996
6997 ins_encode %{
6998 __ movl($dst$$Register, $mem$$Address);
6999 %}
7000
7001 ins_pipe(ialu_reg_mem);
7002 %}
7003
7004 // Load Integer into Long Register
7005 instruct loadI2L(eRegL dst, memory mem) %{
7006 match(Set dst (ConvI2L (LoadI mem)));
7007
7008 ins_cost(375);
7009 format %{ "MOV $dst.lo,$mem\t# int -> long\n\t"
7010 "MOV $dst.hi,$dst.lo\n\t"
7011 "SAR $dst.hi,31" %}
7012
7013 ins_encode %{
7014 __ movl($dst$$Register, $mem$$Address);
7015 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
7016 __ sarl(HIGH_FROM_LOW($dst$$Register), 31);
7017 %}
7018
7019 ins_pipe(ialu_reg_mem);
7020 %}
7021
7022 // Load Unsigned Integer into Long Register
7023 instruct loadUI2L(eRegL dst, memory mem) %{
7024 match(Set dst (LoadUI2L mem));
7025
7026 ins_cost(250);
7027 format %{ "MOV $dst.lo,$mem\t# uint -> long\n\t"
7028 "XOR $dst.hi,$dst.hi" %}
7029
7030 ins_encode %{
7031 __ movl($dst$$Register, $mem$$Address);
7032 __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register));
7033 %}
7034
7035 ins_pipe(ialu_reg_mem);
7036 %}
7037
7038 // Load Long. Cannot clobber address while loading, so restrict address
7039 // register to ESI
7040 instruct loadL(eRegL dst, load_long_memory mem) %{
7041 predicate(!((LoadLNode*)n)->require_atomic_access());
7042 match(Set dst (LoadL mem));
7043
7044 ins_cost(250);
7045 format %{ "MOV $dst.lo,$mem\t# long\n\t"
7046 "MOV $dst.hi,$mem+4" %}
7047
7048 ins_encode %{
7049 Address Amemlo = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp, false);
7050 Address Amemhi = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp + 4, false);
7051 __ movl($dst$$Register, Amemlo);
7052 __ movl(HIGH_FROM_LOW($dst$$Register), Amemhi);
7053 %}
7054
7055 ins_pipe(ialu_reg_long_mem);
7056 %}
7057
7058 // Volatile Load Long. Must be atomic, so do 64-bit FILD
7059 // then store it down to the stack and reload on the int
7060 // side.
7061 instruct loadL_volatile(stackSlotL dst, memory mem) %{
7062 predicate(UseSSE<=1 && ((LoadLNode*)n)->require_atomic_access());
7063 match(Set dst (LoadL mem));
7064
7065 ins_cost(200);
7066 format %{ "FILD $mem\t# Atomic volatile long load\n\t"
7067 "FISTp $dst" %}
7068 ins_encode(enc_loadL_volatile(mem,dst));
7069 ins_pipe( fpu_reg_mem );
7070 %}
7071
7072 instruct loadLX_volatile(stackSlotL dst, memory mem, regXD tmp) %{
7073 predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access());
7074 match(Set dst (LoadL mem));
7075 effect(TEMP tmp);
7076 ins_cost(180);
7077 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
7078 "MOVSD $dst,$tmp" %}
7079 ins_encode(enc_loadLX_volatile(mem, dst, tmp));
7080 ins_pipe( pipe_slow );
7081 %}
7082
7083 instruct loadLX_reg_volatile(eRegL dst, memory mem, regXD tmp) %{
7084 predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access());
7085 match(Set dst (LoadL mem));
7086 effect(TEMP tmp);
7087 ins_cost(160);
7088 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
7089 "MOVD $dst.lo,$tmp\n\t"
7090 "PSRLQ $tmp,32\n\t"
7091 "MOVD $dst.hi,$tmp" %}
7092 ins_encode(enc_loadLX_reg_volatile(mem, dst, tmp));
7093 ins_pipe( pipe_slow );
7094 %}
7095
7096 // Load Range
7097 instruct loadRange(eRegI dst, memory mem) %{
7098 match(Set dst (LoadRange mem));
7099
7100 ins_cost(125);
7101 format %{ "MOV $dst,$mem" %}
7102 opcode(0x8B);
7103 ins_encode( OpcP, RegMem(dst,mem));
7104 ins_pipe( ialu_reg_mem );
7105 %}
7106
7107
7108 // Load Pointer
7109 instruct loadP(eRegP dst, memory mem) %{
7110 match(Set dst (LoadP mem));
7111
7112 ins_cost(125);
7113 format %{ "MOV $dst,$mem" %}
7114 opcode(0x8B);
7115 ins_encode( OpcP, RegMem(dst,mem));
7116 ins_pipe( ialu_reg_mem );
7117 %}
7118
7119 // Load Klass Pointer
7120 instruct loadKlass(eRegP dst, memory mem) %{
7121 match(Set dst (LoadKlass mem));
7122
7123 ins_cost(125);
7124 format %{ "MOV $dst,$mem" %}
7125 opcode(0x8B);
7126 ins_encode( OpcP, RegMem(dst,mem));
7127 ins_pipe( ialu_reg_mem );
7128 %}
7129
7130 // Load Double
7131 instruct loadD(regD dst, memory mem) %{
7132 predicate(UseSSE<=1);
7133 match(Set dst (LoadD mem));
7134
7135 ins_cost(150);
7136 format %{ "FLD_D ST,$mem\n\t"
7137 "FSTP $dst" %}
7138 opcode(0xDD); /* DD /0 */
7139 ins_encode( OpcP, RMopc_Mem(0x00,mem),
7140 Pop_Reg_D(dst) );
7141 ins_pipe( fpu_reg_mem );
7142 %}
7143
7144 // Load Double to XMM
7145 instruct loadXD(regXD dst, memory mem) %{
7146 predicate(UseSSE>=2 && UseXmmLoadAndClearUpper);
7147 match(Set dst (LoadD mem));
7148 ins_cost(145);
7149 format %{ "MOVSD $dst,$mem" %}
7150 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x10), RegMem(dst,mem));
7151 ins_pipe( pipe_slow );
7152 %}
7153
7154 instruct loadXD_partial(regXD dst, memory mem) %{
7155 predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper);
7156 match(Set dst (LoadD mem));
7157 ins_cost(145);
7158 format %{ "MOVLPD $dst,$mem" %}
7159 ins_encode( Opcode(0x66), Opcode(0x0F), Opcode(0x12), RegMem(dst,mem));
7160 ins_pipe( pipe_slow );
7161 %}
7162
7163 // Load to XMM register (single-precision floating point)
7164 // MOVSS instruction
7165 instruct loadX(regX dst, memory mem) %{
7166 predicate(UseSSE>=1);
7167 match(Set dst (LoadF mem));
7168 ins_cost(145);
7169 format %{ "MOVSS $dst,$mem" %}
7170 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x10), RegMem(dst,mem));
7171 ins_pipe( pipe_slow );
7172 %}
7173
7174 // Load Float
7175 instruct loadF(regF dst, memory mem) %{
7176 predicate(UseSSE==0);
7177 match(Set dst (LoadF mem));
7178
7179 ins_cost(150);
7180 format %{ "FLD_S ST,$mem\n\t"
7181 "FSTP $dst" %}
7182 opcode(0xD9); /* D9 /0 */
7183 ins_encode( OpcP, RMopc_Mem(0x00,mem),
7184 Pop_Reg_F(dst) );
7185 ins_pipe( fpu_reg_mem );
7186 %}
7187
7188 // Load Aligned Packed Byte to XMM register
7189 instruct loadA8B(regXD dst, memory mem) %{
7190 predicate(UseSSE>=1);
7191 match(Set dst (Load8B mem));
7192 ins_cost(125);
7193 format %{ "MOVQ $dst,$mem\t! packed8B" %}
7194 ins_encode( movq_ld(dst, mem));
7195 ins_pipe( pipe_slow );
7196 %}
7197
7198 // Load Aligned Packed Short to XMM register
7199 instruct loadA4S(regXD dst, memory mem) %{
7200 predicate(UseSSE>=1);
7201 match(Set dst (Load4S mem));
7202 ins_cost(125);
7203 format %{ "MOVQ $dst,$mem\t! packed4S" %}
7204 ins_encode( movq_ld(dst, mem));
7205 ins_pipe( pipe_slow );
7206 %}
7207
7208 // Load Aligned Packed Char to XMM register
7209 instruct loadA4C(regXD dst, memory mem) %{
7210 predicate(UseSSE>=1);
7211 match(Set dst (Load4C mem));
7212 ins_cost(125);
7213 format %{ "MOVQ $dst,$mem\t! packed4C" %}
7214 ins_encode( movq_ld(dst, mem));
7215 ins_pipe( pipe_slow );
7216 %}
7217
7218 // Load Aligned Packed Integer to XMM register
7219 instruct load2IU(regXD dst, memory mem) %{
7220 predicate(UseSSE>=1);
7221 match(Set dst (Load2I mem));
7222 ins_cost(125);
7223 format %{ "MOVQ $dst,$mem\t! packed2I" %}
7224 ins_encode( movq_ld(dst, mem));
7225 ins_pipe( pipe_slow );
7226 %}
7227
7228 // Load Aligned Packed Single to XMM
7229 instruct loadA2F(regXD dst, memory mem) %{
7230 predicate(UseSSE>=1);
7231 match(Set dst (Load2F mem));
7232 ins_cost(145);
7233 format %{ "MOVQ $dst,$mem\t! packed2F" %}
7234 ins_encode( movq_ld(dst, mem));
7235 ins_pipe( pipe_slow );
7236 %}
7237
7238 // Load Effective Address
7239 instruct leaP8(eRegP dst, indOffset8 mem) %{
7240 match(Set dst mem);
7241
7242 ins_cost(110);
7243 format %{ "LEA $dst,$mem" %}
7244 opcode(0x8D);
7245 ins_encode( OpcP, RegMem(dst,mem));
7246 ins_pipe( ialu_reg_reg_fat );
7247 %}
7248
7249 instruct leaP32(eRegP dst, indOffset32 mem) %{
7250 match(Set dst mem);
7251
7252 ins_cost(110);
7253 format %{ "LEA $dst,$mem" %}
7254 opcode(0x8D);
7255 ins_encode( OpcP, RegMem(dst,mem));
7256 ins_pipe( ialu_reg_reg_fat );
7257 %}
7258
7259 instruct leaPIdxOff(eRegP dst, indIndexOffset mem) %{
7260 match(Set dst mem);
7261
7262 ins_cost(110);
7263 format %{ "LEA $dst,$mem" %}
7264 opcode(0x8D);
7265 ins_encode( OpcP, RegMem(dst,mem));
7266 ins_pipe( ialu_reg_reg_fat );
7267 %}
7268
7269 instruct leaPIdxScale(eRegP dst, indIndexScale mem) %{
7270 match(Set dst mem);
7271
7272 ins_cost(110);
7273 format %{ "LEA $dst,$mem" %}
7274 opcode(0x8D);
7275 ins_encode( OpcP, RegMem(dst,mem));
7276 ins_pipe( ialu_reg_reg_fat );
7277 %}
7278
7279 instruct leaPIdxScaleOff(eRegP dst, indIndexScaleOffset mem) %{
7280 match(Set dst mem);
7281
7282 ins_cost(110);
7283 format %{ "LEA $dst,$mem" %}
7284 opcode(0x8D);
7285 ins_encode( OpcP, RegMem(dst,mem));
7286 ins_pipe( ialu_reg_reg_fat );
7287 %}
7288
7289 // Load Constant
7290 instruct loadConI(eRegI dst, immI src) %{
7291 match(Set dst src);
7292
7293 format %{ "MOV $dst,$src" %}
7294 ins_encode( LdImmI(dst, src) );
7295 ins_pipe( ialu_reg_fat );
7296 %}
7297
7298 // Load Constant zero
7299 instruct loadConI0(eRegI dst, immI0 src, eFlagsReg cr) %{
7300 match(Set dst src);
7301 effect(KILL cr);
7302
7303 ins_cost(50);
7304 format %{ "XOR $dst,$dst" %}
7305 opcode(0x33); /* + rd */
7306 ins_encode( OpcP, RegReg( dst, dst ) );
7307 ins_pipe( ialu_reg );
7308 %}
7309
7310 instruct loadConP(eRegP dst, immP src) %{
7311 match(Set dst src);
7312
7313 format %{ "MOV $dst,$src" %}
7314 opcode(0xB8); /* + rd */
7315 ins_encode( LdImmP(dst, src) );
7316 ins_pipe( ialu_reg_fat );
7317 %}
7318
7319 instruct loadConL(eRegL dst, immL src, eFlagsReg cr) %{
7320 match(Set dst src);
7321 effect(KILL cr);
7322 ins_cost(200);
7323 format %{ "MOV $dst.lo,$src.lo\n\t"
7324 "MOV $dst.hi,$src.hi" %}
7325 opcode(0xB8);
7326 ins_encode( LdImmL_Lo(dst, src), LdImmL_Hi(dst, src) );
7327 ins_pipe( ialu_reg_long_fat );
7328 %}
7329
7330 instruct loadConL0(eRegL dst, immL0 src, eFlagsReg cr) %{
7331 match(Set dst src);
7332 effect(KILL cr);
7333 ins_cost(150);
7334 format %{ "XOR $dst.lo,$dst.lo\n\t"
7335 "XOR $dst.hi,$dst.hi" %}
7336 opcode(0x33,0x33);
7337 ins_encode( RegReg_Lo(dst,dst), RegReg_Hi(dst, dst) );
7338 ins_pipe( ialu_reg_long );
7339 %}
7340
7341 // The instruction usage is guarded by predicate in operand immF().
7342 instruct loadConF(regF dst, immF src) %{
7343 match(Set dst src);
7344 ins_cost(125);
7345
7346 format %{ "FLD_S ST,$src\n\t"
7347 "FSTP $dst" %}
7348 opcode(0xD9, 0x00); /* D9 /0 */
7349 ins_encode(LdImmF(src), Pop_Reg_F(dst) );
7350 ins_pipe( fpu_reg_con );
7351 %}
7352
7353 // The instruction usage is guarded by predicate in operand immXF().
7354 instruct loadConX(regX dst, immXF con) %{
7355 match(Set dst con);
7356 ins_cost(125);
7357 format %{ "MOVSS $dst,[$con]" %}
7358 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x10), LdImmX(dst, con));
7359 ins_pipe( pipe_slow );
7360 %}
7361
7362 // The instruction usage is guarded by predicate in operand immXF0().
7363 instruct loadConX0(regX dst, immXF0 src) %{
7364 match(Set dst src);
7365 ins_cost(100);
7366 format %{ "XORPS $dst,$dst\t# float 0.0" %}
7367 ins_encode( Opcode(0x0F), Opcode(0x57), RegReg(dst,dst));
7368 ins_pipe( pipe_slow );
7369 %}
7370
7371 // The instruction usage is guarded by predicate in operand immD().
7372 instruct loadConD(regD dst, immD src) %{
7373 match(Set dst src);
7374 ins_cost(125);
7375
7376 format %{ "FLD_D ST,$src\n\t"
7377 "FSTP $dst" %}
7378 ins_encode(LdImmD(src), Pop_Reg_D(dst) );
7379 ins_pipe( fpu_reg_con );
7380 %}
7381
7382 // The instruction usage is guarded by predicate in operand immXD().
7383 instruct loadConXD(regXD dst, immXD con) %{
7384 match(Set dst con);
7385 ins_cost(125);
7386 format %{ "MOVSD $dst,[$con]" %}
7387 ins_encode(load_conXD(dst, con));
7388 ins_pipe( pipe_slow );
7389 %}
7390
7391 // The instruction usage is guarded by predicate in operand immXD0().
7392 instruct loadConXD0(regXD dst, immXD0 src) %{
7393 match(Set dst src);
7394 ins_cost(100);
7395 format %{ "XORPD $dst,$dst\t# double 0.0" %}
7396 ins_encode( Opcode(0x66), Opcode(0x0F), Opcode(0x57), RegReg(dst,dst));
7397 ins_pipe( pipe_slow );
7398 %}
7399
7400 // Load Stack Slot
7401 instruct loadSSI(eRegI dst, stackSlotI src) %{
7402 match(Set dst src);
7403 ins_cost(125);
7404
7405 format %{ "MOV $dst,$src" %}
7406 opcode(0x8B);
7407 ins_encode( OpcP, RegMem(dst,src));
7408 ins_pipe( ialu_reg_mem );
7409 %}
7410
7411 instruct loadSSL(eRegL dst, stackSlotL src) %{
7412 match(Set dst src);
7413
7414 ins_cost(200);
7415 format %{ "MOV $dst,$src.lo\n\t"
7416 "MOV $dst+4,$src.hi" %}
7417 opcode(0x8B, 0x8B);
7418 ins_encode( OpcP, RegMem( dst, src ), OpcS, RegMem_Hi( dst, src ) );
7419 ins_pipe( ialu_mem_long_reg );
7420 %}
7421
7422 // Load Stack Slot
7423 instruct loadSSP(eRegP dst, stackSlotP src) %{
7424 match(Set dst src);
7425 ins_cost(125);
7426
7427 format %{ "MOV $dst,$src" %}
7428 opcode(0x8B);
7429 ins_encode( OpcP, RegMem(dst,src));
7430 ins_pipe( ialu_reg_mem );
7431 %}
7432
7433 // Load Stack Slot
7434 instruct loadSSF(regF dst, stackSlotF src) %{
7435 match(Set dst src);
7436 ins_cost(125);
7437
7438 format %{ "FLD_S $src\n\t"
7439 "FSTP $dst" %}
7440 opcode(0xD9); /* D9 /0, FLD m32real */
7441 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
7442 Pop_Reg_F(dst) );
7443 ins_pipe( fpu_reg_mem );
7444 %}
7445
7446 // Load Stack Slot
7447 instruct loadSSD(regD dst, stackSlotD src) %{
7448 match(Set dst src);
7449 ins_cost(125);
7450
7451 format %{ "FLD_D $src\n\t"
7452 "FSTP $dst" %}
7453 opcode(0xDD); /* DD /0, FLD m64real */
7454 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
7455 Pop_Reg_D(dst) );
7456 ins_pipe( fpu_reg_mem );
7457 %}
7458
7459 // Prefetch instructions.
7460 // Must be safe to execute with invalid address (cannot fault).
7461
7462 instruct prefetchr0( memory mem ) %{
7463 predicate(UseSSE==0 && !VM_Version::supports_3dnow());
7464 match(PrefetchRead mem);
7465 ins_cost(0);
7466 size(0);
7467 format %{ "PREFETCHR (non-SSE is empty encoding)" %}
7468 ins_encode();
7469 ins_pipe(empty);
7470 %}
7471
7472 instruct prefetchr( memory mem ) %{
7473 predicate(UseSSE==0 && VM_Version::supports_3dnow() || ReadPrefetchInstr==3);
7474 match(PrefetchRead mem);
7475 ins_cost(100);
7476
7477 format %{ "PREFETCHR $mem\t! Prefetch into level 1 cache for read" %}
7478 opcode(0x0F, 0x0d); /* Opcode 0F 0d /0 */
7479 ins_encode(OpcP, OpcS, RMopc_Mem(0x00,mem));
7480 ins_pipe(ialu_mem);
7481 %}
7482
7483 instruct prefetchrNTA( memory mem ) %{
7484 predicate(UseSSE>=1 && ReadPrefetchInstr==0);
7485 match(PrefetchRead mem);
7486 ins_cost(100);
7487
7488 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for read" %}
7489 opcode(0x0F, 0x18); /* Opcode 0F 18 /0 */
7490 ins_encode(OpcP, OpcS, RMopc_Mem(0x00,mem));
7491 ins_pipe(ialu_mem);
7492 %}
7493
7494 instruct prefetchrT0( memory mem ) %{
7495 predicate(UseSSE>=1 && ReadPrefetchInstr==1);
7496 match(PrefetchRead mem);
7497 ins_cost(100);
7498
7499 format %{ "PREFETCHT0 $mem\t! Prefetch into L1 and L2 caches for read" %}
7500 opcode(0x0F, 0x18); /* Opcode 0F 18 /1 */
7501 ins_encode(OpcP, OpcS, RMopc_Mem(0x01,mem));
7502 ins_pipe(ialu_mem);
7503 %}
7504
7505 instruct prefetchrT2( memory mem ) %{
7506 predicate(UseSSE>=1 && ReadPrefetchInstr==2);
7507 match(PrefetchRead mem);
7508 ins_cost(100);
7509
7510 format %{ "PREFETCHT2 $mem\t! Prefetch into L2 cache for read" %}
7511 opcode(0x0F, 0x18); /* Opcode 0F 18 /3 */
7512 ins_encode(OpcP, OpcS, RMopc_Mem(0x03,mem));
7513 ins_pipe(ialu_mem);
7514 %}
7515
7516 instruct prefetchw0( memory mem ) %{
7517 predicate(UseSSE==0 && !VM_Version::supports_3dnow());
7518 match(PrefetchWrite mem);
7519 ins_cost(0);
7520 size(0);
7521 format %{ "Prefetch (non-SSE is empty encoding)" %}
7522 ins_encode();
7523 ins_pipe(empty);
7524 %}
7525
7526 instruct prefetchw( memory mem ) %{
7527 predicate(UseSSE==0 && VM_Version::supports_3dnow() || AllocatePrefetchInstr==3);
7528 match( PrefetchWrite mem );
7529 ins_cost(100);
7530
7531 format %{ "PREFETCHW $mem\t! Prefetch into L1 cache and mark modified" %}
7532 opcode(0x0F, 0x0D); /* Opcode 0F 0D /1 */
7533 ins_encode(OpcP, OpcS, RMopc_Mem(0x01,mem));
7534 ins_pipe(ialu_mem);
7535 %}
7536
7537 instruct prefetchwNTA( memory mem ) %{
7538 predicate(UseSSE>=1 && AllocatePrefetchInstr==0);
7539 match(PrefetchWrite mem);
7540 ins_cost(100);
7541
7542 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for write" %}
7543 opcode(0x0F, 0x18); /* Opcode 0F 18 /0 */
7544 ins_encode(OpcP, OpcS, RMopc_Mem(0x00,mem));
7545 ins_pipe(ialu_mem);
7546 %}
7547
7548 instruct prefetchwT0( memory mem ) %{
7549 predicate(UseSSE>=1 && AllocatePrefetchInstr==1);
7550 match(PrefetchWrite mem);
7551 ins_cost(100);
7552
7553 format %{ "PREFETCHT0 $mem\t! Prefetch into L1 and L2 caches for write" %}
7554 opcode(0x0F, 0x18); /* Opcode 0F 18 /1 */
7555 ins_encode(OpcP, OpcS, RMopc_Mem(0x01,mem));
7556 ins_pipe(ialu_mem);
7557 %}
7558
7559 instruct prefetchwT2( memory mem ) %{
7560 predicate(UseSSE>=1 && AllocatePrefetchInstr==2);
7561 match(PrefetchWrite mem);
7562 ins_cost(100);
7563
7564 format %{ "PREFETCHT2 $mem\t! Prefetch into L2 cache for write" %}
7565 opcode(0x0F, 0x18); /* Opcode 0F 18 /3 */
7566 ins_encode(OpcP, OpcS, RMopc_Mem(0x03,mem));
7567 ins_pipe(ialu_mem);
7568 %}
7569
7570 //----------Store Instructions-------------------------------------------------
7571
7572 // Store Byte
7573 instruct storeB(memory mem, xRegI src) %{
7574 match(Set mem (StoreB mem src));
7575
7576 ins_cost(125);
7577 format %{ "MOV8 $mem,$src" %}
7578 opcode(0x88);
7579 ins_encode( OpcP, RegMem( src, mem ) );
7580 ins_pipe( ialu_mem_reg );
7581 %}
7582
7583 // Store Char/Short
7584 instruct storeC(memory mem, eRegI src) %{
7585 match(Set mem (StoreC mem src));
7586
7587 ins_cost(125);
7588 format %{ "MOV16 $mem,$src" %}
7589 opcode(0x89, 0x66);
7590 ins_encode( OpcS, OpcP, RegMem( src, mem ) );
7591 ins_pipe( ialu_mem_reg );
7592 %}
7593
7594 // Store Integer
7595 instruct storeI(memory mem, eRegI src) %{
7596 match(Set mem (StoreI mem src));
7597
7598 ins_cost(125);
7599 format %{ "MOV $mem,$src" %}
7600 opcode(0x89);
7601 ins_encode( OpcP, RegMem( src, mem ) );
7602 ins_pipe( ialu_mem_reg );
7603 %}
7604
7605 // Store Long
7606 instruct storeL(long_memory mem, eRegL src) %{
7607 predicate(!((StoreLNode*)n)->require_atomic_access());
7608 match(Set mem (StoreL mem src));
7609
7610 ins_cost(200);
7611 format %{ "MOV $mem,$src.lo\n\t"
7612 "MOV $mem+4,$src.hi" %}
7613 opcode(0x89, 0x89);
7614 ins_encode( OpcP, RegMem( src, mem ), OpcS, RegMem_Hi( src, mem ) );
7615 ins_pipe( ialu_mem_long_reg );
7616 %}
7617
7618 // Volatile Store Long. Must be atomic, so move it into
7619 // the FP TOS and then do a 64-bit FIST. Has to probe the
7620 // target address before the store (for null-ptr checks)
7621 // so the memory operand is used twice in the encoding.
7622 instruct storeL_volatile(memory mem, stackSlotL src, eFlagsReg cr ) %{
7623 predicate(UseSSE<=1 && ((StoreLNode*)n)->require_atomic_access());
7624 match(Set mem (StoreL mem src));
7625 effect( KILL cr );
7626 ins_cost(400);
7627 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
7628 "FILD $src\n\t"
7629 "FISTp $mem\t # 64-bit atomic volatile long store" %}
7630 opcode(0x3B);
7631 ins_encode( OpcP, RegMem( EAX, mem ), enc_storeL_volatile(mem,src));
7632 ins_pipe( fpu_reg_mem );
7633 %}
7634
7635 instruct storeLX_volatile(memory mem, stackSlotL src, regXD tmp, eFlagsReg cr) %{
7636 predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access());
7637 match(Set mem (StoreL mem src));
7638 effect( TEMP tmp, KILL cr );
7639 ins_cost(380);
7640 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
7641 "MOVSD $tmp,$src\n\t"
7642 "MOVSD $mem,$tmp\t # 64-bit atomic volatile long store" %}
7643 opcode(0x3B);
7644 ins_encode( OpcP, RegMem( EAX, mem ), enc_storeLX_volatile(mem, src, tmp));
7645 ins_pipe( pipe_slow );
7646 %}
7647
7648 instruct storeLX_reg_volatile(memory mem, eRegL src, regXD tmp2, regXD tmp, eFlagsReg cr) %{
7649 predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access());
7650 match(Set mem (StoreL mem src));
7651 effect( TEMP tmp2 , TEMP tmp, KILL cr );
7652 ins_cost(360);
7653 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
7654 "MOVD $tmp,$src.lo\n\t"
7655 "MOVD $tmp2,$src.hi\n\t"
7656 "PUNPCKLDQ $tmp,$tmp2\n\t"
7657 "MOVSD $mem,$tmp\t # 64-bit atomic volatile long store" %}
7658 opcode(0x3B);
7659 ins_encode( OpcP, RegMem( EAX, mem ), enc_storeLX_reg_volatile(mem, src, tmp, tmp2));
7660 ins_pipe( pipe_slow );
7661 %}
7662
7663 // Store Pointer; for storing unknown oops and raw pointers
7664 instruct storeP(memory mem, anyRegP src) %{
7665 match(Set mem (StoreP mem src));
7666
7667 ins_cost(125);
7668 format %{ "MOV $mem,$src" %}
7669 opcode(0x89);
7670 ins_encode( OpcP, RegMem( src, mem ) );
7671 ins_pipe( ialu_mem_reg );
7672 %}
7673
7674 // Store Integer Immediate
7675 instruct storeImmI(memory mem, immI src) %{
7676 match(Set mem (StoreI mem src));
7677
7678 ins_cost(150);
7679 format %{ "MOV $mem,$src" %}
7680 opcode(0xC7); /* C7 /0 */
7681 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32( src ));
7682 ins_pipe( ialu_mem_imm );
7683 %}
7684
7685 // Store Short/Char Immediate
7686 instruct storeImmI16(memory mem, immI16 src) %{
7687 predicate(UseStoreImmI16);
7688 match(Set mem (StoreC mem src));
7689
7690 ins_cost(150);
7691 format %{ "MOV16 $mem,$src" %}
7692 opcode(0xC7); /* C7 /0 Same as 32 store immediate with prefix */
7693 ins_encode( SizePrefix, OpcP, RMopc_Mem(0x00,mem), Con16( src ));
7694 ins_pipe( ialu_mem_imm );
7695 %}
7696
7697 // Store Pointer Immediate; null pointers or constant oops that do not
7698 // need card-mark barriers.
7699 instruct storeImmP(memory mem, immP src) %{
7700 match(Set mem (StoreP mem src));
7701
7702 ins_cost(150);
7703 format %{ "MOV $mem,$src" %}
7704 opcode(0xC7); /* C7 /0 */
7705 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32( src ));
7706 ins_pipe( ialu_mem_imm );
7707 %}
7708
7709 // Store Byte Immediate
7710 instruct storeImmB(memory mem, immI8 src) %{
7711 match(Set mem (StoreB mem src));
7712
7713 ins_cost(150);
7714 format %{ "MOV8 $mem,$src" %}
7715 opcode(0xC6); /* C6 /0 */
7716 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con8or32( src ));
7717 ins_pipe( ialu_mem_imm );
7718 %}
7719
7720 // Store Aligned Packed Byte XMM register to memory
7721 instruct storeA8B(memory mem, regXD src) %{
7722 predicate(UseSSE>=1);
7723 match(Set mem (Store8B mem src));
7724 ins_cost(145);
7725 format %{ "MOVQ $mem,$src\t! packed8B" %}
7726 ins_encode( movq_st(mem, src));
7727 ins_pipe( pipe_slow );
7728 %}
7729
7730 // Store Aligned Packed Char/Short XMM register to memory
7731 instruct storeA4C(memory mem, regXD src) %{
7732 predicate(UseSSE>=1);
7733 match(Set mem (Store4C mem src));
7734 ins_cost(145);
7735 format %{ "MOVQ $mem,$src\t! packed4C" %}
7736 ins_encode( movq_st(mem, src));
7737 ins_pipe( pipe_slow );
7738 %}
7739
7740 // Store Aligned Packed Integer XMM register to memory
7741 instruct storeA2I(memory mem, regXD src) %{
7742 predicate(UseSSE>=1);
7743 match(Set mem (Store2I mem src));
7744 ins_cost(145);
7745 format %{ "MOVQ $mem,$src\t! packed2I" %}
7746 ins_encode( movq_st(mem, src));
7747 ins_pipe( pipe_slow );
7748 %}
7749
7750 // Store CMS card-mark Immediate
7751 instruct storeImmCM(memory mem, immI8 src) %{
7752 match(Set mem (StoreCM mem src));
7753
7754 ins_cost(150);
7755 format %{ "MOV8 $mem,$src\t! CMS card-mark imm0" %}
7756 opcode(0xC6); /* C6 /0 */
7757 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con8or32( src ));
7758 ins_pipe( ialu_mem_imm );
7759 %}
7760
7761 // Store Double
7762 instruct storeD( memory mem, regDPR1 src) %{
7763 predicate(UseSSE<=1);
7764 match(Set mem (StoreD mem src));
7765
7766 ins_cost(100);
7767 format %{ "FST_D $mem,$src" %}
7768 opcode(0xDD); /* DD /2 */
7769 ins_encode( enc_FP_store(mem,src) );
7770 ins_pipe( fpu_mem_reg );
7771 %}
7772
7773 // Store double does rounding on x86
7774 instruct storeD_rounded( memory mem, regDPR1 src) %{
7775 predicate(UseSSE<=1);
7776 match(Set mem (StoreD mem (RoundDouble src)));
7777
7778 ins_cost(100);
7779 format %{ "FST_D $mem,$src\t# round" %}
7780 opcode(0xDD); /* DD /2 */
7781 ins_encode( enc_FP_store(mem,src) );
7782 ins_pipe( fpu_mem_reg );
7783 %}
7784
7785 // Store XMM register to memory (double-precision floating points)
7786 // MOVSD instruction
7787 instruct storeXD(memory mem, regXD src) %{
7788 predicate(UseSSE>=2);
7789 match(Set mem (StoreD mem src));
7790 ins_cost(95);
7791 format %{ "MOVSD $mem,$src" %}
7792 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x11), RegMem(src, mem));
7793 ins_pipe( pipe_slow );
7794 %}
7795
7796 // Store XMM register to memory (single-precision floating point)
7797 // MOVSS instruction
7798 instruct storeX(memory mem, regX src) %{
7799 predicate(UseSSE>=1);
7800 match(Set mem (StoreF mem src));
7801 ins_cost(95);
7802 format %{ "MOVSS $mem,$src" %}
7803 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x11), RegMem(src, mem));
7804 ins_pipe( pipe_slow );
7805 %}
7806
7807 // Store Aligned Packed Single Float XMM register to memory
7808 instruct storeA2F(memory mem, regXD src) %{
7809 predicate(UseSSE>=1);
7810 match(Set mem (Store2F mem src));
7811 ins_cost(145);
7812 format %{ "MOVQ $mem,$src\t! packed2F" %}
7813 ins_encode( movq_st(mem, src));
7814 ins_pipe( pipe_slow );
7815 %}
7816
7817 // Store Float
7818 instruct storeF( memory mem, regFPR1 src) %{
7819 predicate(UseSSE==0);
7820 match(Set mem (StoreF mem src));
7821
7822 ins_cost(100);
7823 format %{ "FST_S $mem,$src" %}
7824 opcode(0xD9); /* D9 /2 */
7825 ins_encode( enc_FP_store(mem,src) );
7826 ins_pipe( fpu_mem_reg );
7827 %}
7828
7829 // Store Float does rounding on x86
7830 instruct storeF_rounded( memory mem, regFPR1 src) %{
7831 predicate(UseSSE==0);
7832 match(Set mem (StoreF mem (RoundFloat src)));
7833
7834 ins_cost(100);
7835 format %{ "FST_S $mem,$src\t# round" %}
7836 opcode(0xD9); /* D9 /2 */
7837 ins_encode( enc_FP_store(mem,src) );
7838 ins_pipe( fpu_mem_reg );
7839 %}
7840
7841 // Store Float does rounding on x86
7842 instruct storeF_Drounded( memory mem, regDPR1 src) %{
7843 predicate(UseSSE<=1);
7844 match(Set mem (StoreF mem (ConvD2F src)));
7845
7846 ins_cost(100);
7847 format %{ "FST_S $mem,$src\t# D-round" %}
7848 opcode(0xD9); /* D9 /2 */
7849 ins_encode( enc_FP_store(mem,src) );
7850 ins_pipe( fpu_mem_reg );
7851 %}
7852
7853 // Store immediate Float value (it is faster than store from FPU register)
7854 // The instruction usage is guarded by predicate in operand immF().
7855 instruct storeF_imm( memory mem, immF src) %{
7856 match(Set mem (StoreF mem src));
7857
7858 ins_cost(50);
7859 format %{ "MOV $mem,$src\t# store float" %}
7860 opcode(0xC7); /* C7 /0 */
7861 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32F_as_bits( src ));
7862 ins_pipe( ialu_mem_imm );
7863 %}
7864
7865 // Store immediate Float value (it is faster than store from XMM register)
7866 // The instruction usage is guarded by predicate in operand immXF().
7867 instruct storeX_imm( memory mem, immXF src) %{
7868 match(Set mem (StoreF mem src));
7869
7870 ins_cost(50);
7871 format %{ "MOV $mem,$src\t# store float" %}
7872 opcode(0xC7); /* C7 /0 */
7873 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32XF_as_bits( src ));
7874 ins_pipe( ialu_mem_imm );
7875 %}
7876
7877 // Store Integer to stack slot
7878 instruct storeSSI(stackSlotI dst, eRegI src) %{
7879 match(Set dst src);
7880
7881 ins_cost(100);
7882 format %{ "MOV $dst,$src" %}
7883 opcode(0x89);
7884 ins_encode( OpcPRegSS( dst, src ) );
7885 ins_pipe( ialu_mem_reg );
7886 %}
7887
7888 // Store Integer to stack slot
7889 instruct storeSSP(stackSlotP dst, eRegP src) %{
7890 match(Set dst src);
7891
7892 ins_cost(100);
7893 format %{ "MOV $dst,$src" %}
7894 opcode(0x89);
7895 ins_encode( OpcPRegSS( dst, src ) );
7896 ins_pipe( ialu_mem_reg );
7897 %}
7898
7899 // Store Long to stack slot
7900 instruct storeSSL(stackSlotL dst, eRegL src) %{
7901 match(Set dst src);
7902
7903 ins_cost(200);
7904 format %{ "MOV $dst,$src.lo\n\t"
7905 "MOV $dst+4,$src.hi" %}
7906 opcode(0x89, 0x89);
7907 ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) );
7908 ins_pipe( ialu_mem_long_reg );
7909 %}
7910
7911 //----------MemBar Instructions-----------------------------------------------
7912 // Memory barrier flavors
7913
7914 instruct membar_acquire() %{
7915 match(MemBarAcquire);
7916 ins_cost(400);
7917
7918 size(0);
7919 format %{ "MEMBAR-acquire ! (empty encoding)" %}
7920 ins_encode();
7921 ins_pipe(empty);
7922 %}
7923
7924 instruct membar_acquire_lock() %{
7925 match(MemBarAcquire);
7926 predicate(Matcher::prior_fast_lock(n));
7927 ins_cost(0);
7928
7929 size(0);
7930 format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)" %}
7931 ins_encode( );
7932 ins_pipe(empty);
7933 %}
7934
7935 instruct membar_release() %{
7936 match(MemBarRelease);
7937 ins_cost(400);
7938
7939 size(0);
7940 format %{ "MEMBAR-release ! (empty encoding)" %}
7941 ins_encode( );
7942 ins_pipe(empty);
7943 %}
7944
7945 instruct membar_release_lock() %{
7946 match(MemBarRelease);
7947 predicate(Matcher::post_fast_unlock(n));
7948 ins_cost(0);
7949
7950 size(0);
7951 format %{ "MEMBAR-release (a FastUnlock follows so empty encoding)" %}
7952 ins_encode( );
7953 ins_pipe(empty);
7954 %}
7955
7956 instruct membar_volatile(eFlagsReg cr) %{
7957 match(MemBarVolatile);
7958 effect(KILL cr);
7959 ins_cost(400);
7960
7961 format %{
7962 $$template
7963 if (os::is_MP()) {
7964 $$emit$$"LOCK ADDL [ESP + #0], 0\t! membar_volatile"
7965 } else {
7966 $$emit$$"MEMBAR-volatile ! (empty encoding)"
7967 }
7968 %}
7969 ins_encode %{
7970 __ membar(Assembler::StoreLoad);
7971 %}
7972 ins_pipe(pipe_slow);
7973 %}
7974
7975 instruct unnecessary_membar_volatile() %{
7976 match(MemBarVolatile);
7977 predicate(Matcher::post_store_load_barrier(n));
7978 ins_cost(0);
7979
7980 size(0);
7981 format %{ "MEMBAR-volatile (unnecessary so empty encoding)" %}
7982 ins_encode( );
7983 ins_pipe(empty);
7984 %}
7985
7986 //----------Move Instructions--------------------------------------------------
7987 instruct castX2P(eAXRegP dst, eAXRegI src) %{
7988 match(Set dst (CastX2P src));
7989 format %{ "# X2P $dst, $src" %}
7990 ins_encode( /*empty encoding*/ );
7991 ins_cost(0);
7992 ins_pipe(empty);
7993 %}
7994
7995 instruct castP2X(eRegI dst, eRegP src ) %{
7996 match(Set dst (CastP2X src));
7997 ins_cost(50);
7998 format %{ "MOV $dst, $src\t# CastP2X" %}
7999 ins_encode( enc_Copy( dst, src) );
8000 ins_pipe( ialu_reg_reg );
8001 %}
8002
8003 //----------Conditional Move---------------------------------------------------
8004 // Conditional move
8005 instruct cmovI_reg(eRegI dst, eRegI src, eFlagsReg cr, cmpOp cop ) %{
8006 predicate(VM_Version::supports_cmov() );
8007 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
8008 ins_cost(200);
8009 format %{ "CMOV$cop $dst,$src" %}
8010 opcode(0x0F,0x40);
8011 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
8012 ins_pipe( pipe_cmov_reg );
8013 %}
8014
8015 instruct cmovI_regU( cmpOpU cop, eFlagsRegU cr, eRegI dst, eRegI src ) %{
8016 predicate(VM_Version::supports_cmov() );
8017 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
8018 ins_cost(200);
8019 format %{ "CMOV$cop $dst,$src" %}
8020 opcode(0x0F,0x40);
8021 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
8022 ins_pipe( pipe_cmov_reg );
8023 %}
8024
8025 instruct cmovI_regUCF( cmpOpUCF cop, eFlagsRegUCF cr, eRegI dst, eRegI src ) %{
8026 predicate(VM_Version::supports_cmov() );
8027 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
8028 ins_cost(200);
8029 expand %{
8030 cmovI_regU(cop, cr, dst, src);
8031 %}
8032 %}
8033
8034 // Conditional move
8035 instruct cmovI_mem(cmpOp cop, eFlagsReg cr, eRegI dst, memory src) %{
8036 predicate(VM_Version::supports_cmov() );
8037 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
8038 ins_cost(250);
8039 format %{ "CMOV$cop $dst,$src" %}
8040 opcode(0x0F,0x40);
8041 ins_encode( enc_cmov(cop), RegMem( dst, src ) );
8042 ins_pipe( pipe_cmov_mem );
8043 %}
8044
8045 // Conditional move
8046 instruct cmovI_memU(cmpOpU cop, eFlagsRegU cr, eRegI dst, memory src) %{
8047 predicate(VM_Version::supports_cmov() );
8048 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
8049 ins_cost(250);
8050 format %{ "CMOV$cop $dst,$src" %}
8051 opcode(0x0F,0x40);
8052 ins_encode( enc_cmov(cop), RegMem( dst, src ) );
8053 ins_pipe( pipe_cmov_mem );
8054 %}
8055
8056 instruct cmovI_memUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegI dst, memory src) %{
8057 predicate(VM_Version::supports_cmov() );
8058 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
8059 ins_cost(250);
8060 expand %{
8061 cmovI_memU(cop, cr, dst, src);
8062 %}
8063 %}
8064
8065 // Conditional move
8066 instruct cmovP_reg(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{
8067 predicate(VM_Version::supports_cmov() );
8068 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
8069 ins_cost(200);
8070 format %{ "CMOV$cop $dst,$src\t# ptr" %}
8071 opcode(0x0F,0x40);
8072 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
8073 ins_pipe( pipe_cmov_reg );
8074 %}
8075
8076 // Conditional move (non-P6 version)
8077 // Note: a CMoveP is generated for stubs and native wrappers
8078 // regardless of whether we are on a P6, so we
8079 // emulate a cmov here
8080 instruct cmovP_reg_nonP6(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{
8081 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
8082 ins_cost(300);
8083 format %{ "Jn$cop skip\n\t"
8084 "MOV $dst,$src\t# pointer\n"
8085 "skip:" %}
8086 opcode(0x8b);
8087 ins_encode( enc_cmov_branch(cop, 0x2), OpcP, RegReg(dst, src));
8088 ins_pipe( pipe_cmov_reg );
8089 %}
8090
8091 // Conditional move
8092 instruct cmovP_regU(cmpOpU cop, eFlagsRegU cr, eRegP dst, eRegP src ) %{
8093 predicate(VM_Version::supports_cmov() );
8094 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
8095 ins_cost(200);
8096 format %{ "CMOV$cop $dst,$src\t# ptr" %}
8097 opcode(0x0F,0x40);
8098 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
8099 ins_pipe( pipe_cmov_reg );
8100 %}
8101
8102 instruct cmovP_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegP dst, eRegP src ) %{
8103 predicate(VM_Version::supports_cmov() );
8104 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
8105 ins_cost(200);
8106 expand %{
8107 cmovP_regU(cop, cr, dst, src);
8108 %}
8109 %}
8110
8111 // DISABLED: Requires the ADLC to emit a bottom_type call that
8112 // correctly meets the two pointer arguments; one is an incoming
8113 // register but the other is a memory operand. ALSO appears to
8114 // be buggy with implicit null checks.
8115 //
8116 //// Conditional move
8117 //instruct cmovP_mem(cmpOp cop, eFlagsReg cr, eRegP dst, memory src) %{
8118 // predicate(VM_Version::supports_cmov() );
8119 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
8120 // ins_cost(250);
8121 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
8122 // opcode(0x0F,0x40);
8123 // ins_encode( enc_cmov(cop), RegMem( dst, src ) );
8124 // ins_pipe( pipe_cmov_mem );
8125 //%}
8126 //
8127 //// Conditional move
8128 //instruct cmovP_memU(cmpOpU cop, eFlagsRegU cr, eRegP dst, memory src) %{
8129 // predicate(VM_Version::supports_cmov() );
8130 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
8131 // ins_cost(250);
8132 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
8133 // opcode(0x0F,0x40);
8134 // ins_encode( enc_cmov(cop), RegMem( dst, src ) );
8135 // ins_pipe( pipe_cmov_mem );
8136 //%}
8137
8138 // Conditional move
8139 instruct fcmovD_regU(cmpOp_fcmov cop, eFlagsRegU cr, regDPR1 dst, regD src) %{
8140 predicate(UseSSE<=1);
8141 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
8142 ins_cost(200);
8143 format %{ "FCMOV$cop $dst,$src\t# double" %}
8144 opcode(0xDA);
8145 ins_encode( enc_cmov_d(cop,src) );
8146 ins_pipe( pipe_cmovD_reg );
8147 %}
8148
8149 // Conditional move
8150 instruct fcmovF_regU(cmpOp_fcmov cop, eFlagsRegU cr, regFPR1 dst, regF src) %{
8151 predicate(UseSSE==0);
8152 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
8153 ins_cost(200);
8154 format %{ "FCMOV$cop $dst,$src\t# float" %}
8155 opcode(0xDA);
8156 ins_encode( enc_cmov_d(cop,src) );
8157 ins_pipe( pipe_cmovD_reg );
8158 %}
8159
8160 // Float CMOV on Intel doesn't handle *signed* compares, only unsigned.
8161 instruct fcmovD_regS(cmpOp cop, eFlagsReg cr, regD dst, regD src) %{
8162 predicate(UseSSE<=1);
8163 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
8164 ins_cost(200);
8165 format %{ "Jn$cop skip\n\t"
8166 "MOV $dst,$src\t# double\n"
8167 "skip:" %}
8168 opcode (0xdd, 0x3); /* DD D8+i or DD /3 */
8169 ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_D(src), OpcP, RegOpc(dst) );
8170 ins_pipe( pipe_cmovD_reg );
8171 %}
8172
8173 // Float CMOV on Intel doesn't handle *signed* compares, only unsigned.
8174 instruct fcmovF_regS(cmpOp cop, eFlagsReg cr, regF dst, regF src) %{
8175 predicate(UseSSE==0);
8176 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
8177 ins_cost(200);
8178 format %{ "Jn$cop skip\n\t"
8179 "MOV $dst,$src\t# float\n"
8180 "skip:" %}
8181 opcode (0xdd, 0x3); /* DD D8+i or DD /3 */
8182 ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_F(src), OpcP, RegOpc(dst) );
8183 ins_pipe( pipe_cmovD_reg );
8184 %}
8185
8186 // No CMOVE with SSE/SSE2
8187 instruct fcmovX_regS(cmpOp cop, eFlagsReg cr, regX dst, regX src) %{
8188 predicate (UseSSE>=1);
8189 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
8190 ins_cost(200);
8191 format %{ "Jn$cop skip\n\t"
8192 "MOVSS $dst,$src\t# float\n"
8193 "skip:" %}
8194 ins_encode %{
8195 Label skip;
8196 // Invert sense of branch from sense of CMOV
8197 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
8198 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
8199 __ bind(skip);
8200 %}
8201 ins_pipe( pipe_slow );
8202 %}
8203
8204 // No CMOVE with SSE/SSE2
8205 instruct fcmovXD_regS(cmpOp cop, eFlagsReg cr, regXD dst, regXD src) %{
8206 predicate (UseSSE>=2);
8207 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
8208 ins_cost(200);
8209 format %{ "Jn$cop skip\n\t"
8210 "MOVSD $dst,$src\t# float\n"
8211 "skip:" %}
8212 ins_encode %{
8213 Label skip;
8214 // Invert sense of branch from sense of CMOV
8215 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
8216 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
8217 __ bind(skip);
8218 %}
8219 ins_pipe( pipe_slow );
8220 %}
8221
8222 // unsigned version
8223 instruct fcmovX_regU(cmpOpU cop, eFlagsRegU cr, regX dst, regX src) %{
8224 predicate (UseSSE>=1);
8225 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
8226 ins_cost(200);
8227 format %{ "Jn$cop skip\n\t"
8228 "MOVSS $dst,$src\t# float\n"
8229 "skip:" %}
8230 ins_encode %{
8231 Label skip;
8232 // Invert sense of branch from sense of CMOV
8233 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
8234 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
8235 __ bind(skip);
8236 %}
8237 ins_pipe( pipe_slow );
8238 %}
8239
8240 instruct fcmovX_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, regX dst, regX src) %{
8241 predicate (UseSSE>=1);
8242 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
8243 ins_cost(200);
8244 expand %{
8245 fcmovX_regU(cop, cr, dst, src);
8246 %}
8247 %}
8248
8249 // unsigned version
8250 instruct fcmovXD_regU(cmpOpU cop, eFlagsRegU cr, regXD dst, regXD src) %{
8251 predicate (UseSSE>=2);
8252 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
8253 ins_cost(200);
8254 format %{ "Jn$cop skip\n\t"
8255 "MOVSD $dst,$src\t# float\n"
8256 "skip:" %}
8257 ins_encode %{
8258 Label skip;
8259 // Invert sense of branch from sense of CMOV
8260 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
8261 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
8262 __ bind(skip);
8263 %}
8264 ins_pipe( pipe_slow );
8265 %}
8266
8267 instruct fcmovXD_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, regXD dst, regXD src) %{
8268 predicate (UseSSE>=2);
8269 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
8270 ins_cost(200);
8271 expand %{
8272 fcmovXD_regU(cop, cr, dst, src);
8273 %}
8274 %}
8275
8276 instruct cmovL_reg(cmpOp cop, eFlagsReg cr, eRegL dst, eRegL src) %{
8277 predicate(VM_Version::supports_cmov() );
8278 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
8279 ins_cost(200);
8280 format %{ "CMOV$cop $dst.lo,$src.lo\n\t"
8281 "CMOV$cop $dst.hi,$src.hi" %}
8282 opcode(0x0F,0x40);
8283 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) );
8284 ins_pipe( pipe_cmov_reg_long );
8285 %}
8286
8287 instruct cmovL_regU(cmpOpU cop, eFlagsRegU cr, eRegL dst, eRegL src) %{
8288 predicate(VM_Version::supports_cmov() );
8289 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
8290 ins_cost(200);
8291 format %{ "CMOV$cop $dst.lo,$src.lo\n\t"
8292 "CMOV$cop $dst.hi,$src.hi" %}
8293 opcode(0x0F,0x40);
8294 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) );
8295 ins_pipe( pipe_cmov_reg_long );
8296 %}
8297
8298 instruct cmovL_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegL dst, eRegL src) %{
8299 predicate(VM_Version::supports_cmov() );
8300 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
8301 ins_cost(200);
8302 expand %{
8303 cmovL_regU(cop, cr, dst, src);
8304 %}
8305 %}
8306
8307 //----------Arithmetic Instructions--------------------------------------------
8308 //----------Addition Instructions----------------------------------------------
8309 // Integer Addition Instructions
8310 instruct addI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
8311 match(Set dst (AddI dst src));
8312 effect(KILL cr);
8313
8314 size(2);
8315 format %{ "ADD $dst,$src" %}
8316 opcode(0x03);
8317 ins_encode( OpcP, RegReg( dst, src) );
8318 ins_pipe( ialu_reg_reg );
8319 %}
8320
8321 instruct addI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{
8322 match(Set dst (AddI dst src));
8323 effect(KILL cr);
8324
8325 format %{ "ADD $dst,$src" %}
8326 opcode(0x81, 0x00); /* /0 id */
8327 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8328 ins_pipe( ialu_reg );
8329 %}
8330
8331 instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
8332 predicate(UseIncDec);
8333 match(Set dst (AddI dst src));
8334 effect(KILL cr);
8335
8336 size(1);
8337 format %{ "INC $dst" %}
8338 opcode(0x40); /* */
8339 ins_encode( Opc_plus( primary, dst ) );
8340 ins_pipe( ialu_reg );
8341 %}
8342
8343 instruct leaI_eReg_immI(eRegI dst, eRegI src0, immI src1) %{
8344 match(Set dst (AddI src0 src1));
8345 ins_cost(110);
8346
8347 format %{ "LEA $dst,[$src0 + $src1]" %}
8348 opcode(0x8D); /* 0x8D /r */
8349 ins_encode( OpcP, RegLea( dst, src0, src1 ) );
8350 ins_pipe( ialu_reg_reg );
8351 %}
8352
8353 instruct leaP_eReg_immI(eRegP dst, eRegP src0, immI src1) %{
8354 match(Set dst (AddP src0 src1));
8355 ins_cost(110);
8356
8357 format %{ "LEA $dst,[$src0 + $src1]\t# ptr" %}
8358 opcode(0x8D); /* 0x8D /r */
8359 ins_encode( OpcP, RegLea( dst, src0, src1 ) );
8360 ins_pipe( ialu_reg_reg );
8361 %}
8362
8363 instruct decI_eReg(eRegI dst, immI_M1 src, eFlagsReg cr) %{
8364 predicate(UseIncDec);
8365 match(Set dst (AddI dst src));
8366 effect(KILL cr);
8367
8368 size(1);
8369 format %{ "DEC $dst" %}
8370 opcode(0x48); /* */
8371 ins_encode( Opc_plus( primary, dst ) );
8372 ins_pipe( ialu_reg );
8373 %}
8374
8375 instruct addP_eReg(eRegP dst, eRegI src, eFlagsReg cr) %{
8376 match(Set dst (AddP dst src));
8377 effect(KILL cr);
8378
8379 size(2);
8380 format %{ "ADD $dst,$src" %}
8381 opcode(0x03);
8382 ins_encode( OpcP, RegReg( dst, src) );
8383 ins_pipe( ialu_reg_reg );
8384 %}
8385
8386 instruct addP_eReg_imm(eRegP dst, immI src, eFlagsReg cr) %{
8387 match(Set dst (AddP dst src));
8388 effect(KILL cr);
8389
8390 format %{ "ADD $dst,$src" %}
8391 opcode(0x81,0x00); /* Opcode 81 /0 id */
8392 // ins_encode( RegImm( dst, src) );
8393 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8394 ins_pipe( ialu_reg );
8395 %}
8396
8397 instruct addI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{
8398 match(Set dst (AddI dst (LoadI src)));
8399 effect(KILL cr);
8400
8401 ins_cost(125);
8402 format %{ "ADD $dst,$src" %}
8403 opcode(0x03);
8404 ins_encode( OpcP, RegMem( dst, src) );
8405 ins_pipe( ialu_reg_mem );
8406 %}
8407
8408 instruct addI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{
8409 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
8410 effect(KILL cr);
8411
8412 ins_cost(150);
8413 format %{ "ADD $dst,$src" %}
8414 opcode(0x01); /* Opcode 01 /r */
8415 ins_encode( OpcP, RegMem( src, dst ) );
8416 ins_pipe( ialu_mem_reg );
8417 %}
8418
8419 // Add Memory with Immediate
8420 instruct addI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
8421 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
8422 effect(KILL cr);
8423
8424 ins_cost(125);
8425 format %{ "ADD $dst,$src" %}
8426 opcode(0x81); /* Opcode 81 /0 id */
8427 ins_encode( OpcSE( src ), RMopc_Mem(0x00,dst), Con8or32( src ) );
8428 ins_pipe( ialu_mem_imm );
8429 %}
8430
8431 instruct incI_mem(memory dst, immI1 src, eFlagsReg cr) %{
8432 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
8433 effect(KILL cr);
8434
8435 ins_cost(125);
8436 format %{ "INC $dst" %}
8437 opcode(0xFF); /* Opcode FF /0 */
8438 ins_encode( OpcP, RMopc_Mem(0x00,dst));
8439 ins_pipe( ialu_mem_imm );
8440 %}
8441
8442 instruct decI_mem(memory dst, immI_M1 src, eFlagsReg cr) %{
8443 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
8444 effect(KILL cr);
8445
8446 ins_cost(125);
8447 format %{ "DEC $dst" %}
8448 opcode(0xFF); /* Opcode FF /1 */
8449 ins_encode( OpcP, RMopc_Mem(0x01,dst));
8450 ins_pipe( ialu_mem_imm );
8451 %}
8452
8453
8454 instruct checkCastPP( eRegP dst ) %{
8455 match(Set dst (CheckCastPP dst));
8456
8457 size(0);
8458 format %{ "#checkcastPP of $dst" %}
8459 ins_encode( /*empty encoding*/ );
8460 ins_pipe( empty );
8461 %}
8462
8463 instruct castPP( eRegP dst ) %{
8464 match(Set dst (CastPP dst));
8465 format %{ "#castPP of $dst" %}
8466 ins_encode( /*empty encoding*/ );
8467 ins_pipe( empty );
8468 %}
8469
8470 instruct castII( eRegI dst ) %{
8471 match(Set dst (CastII dst));
8472 format %{ "#castII of $dst" %}
8473 ins_encode( /*empty encoding*/ );
8474 ins_cost(0);
8475 ins_pipe( empty );
8476 %}
8477
8478
8479 // Load-locked - same as a regular pointer load when used with compare-swap
8480 instruct loadPLocked(eRegP dst, memory mem) %{
8481 match(Set dst (LoadPLocked mem));
8482
8483 ins_cost(125);
8484 format %{ "MOV $dst,$mem\t# Load ptr. locked" %}
8485 opcode(0x8B);
8486 ins_encode( OpcP, RegMem(dst,mem));
8487 ins_pipe( ialu_reg_mem );
8488 %}
8489
8490 // LoadLong-locked - same as a volatile long load when used with compare-swap
8491 instruct loadLLocked(stackSlotL dst, load_long_memory mem) %{
8492 predicate(UseSSE<=1);
8493 match(Set dst (LoadLLocked mem));
8494
8495 ins_cost(200);
8496 format %{ "FILD $mem\t# Atomic volatile long load\n\t"
8497 "FISTp $dst" %}
8498 ins_encode(enc_loadL_volatile(mem,dst));
8499 ins_pipe( fpu_reg_mem );
8500 %}
8501
8502 instruct loadLX_Locked(stackSlotL dst, load_long_memory mem, regXD tmp) %{
8503 predicate(UseSSE>=2);
8504 match(Set dst (LoadLLocked mem));
8505 effect(TEMP tmp);
8506 ins_cost(180);
8507 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
8508 "MOVSD $dst,$tmp" %}
8509 ins_encode(enc_loadLX_volatile(mem, dst, tmp));
8510 ins_pipe( pipe_slow );
8511 %}
8512
8513 instruct loadLX_reg_Locked(eRegL dst, load_long_memory mem, regXD tmp) %{
8514 predicate(UseSSE>=2);
8515 match(Set dst (LoadLLocked mem));
8516 effect(TEMP tmp);
8517 ins_cost(160);
8518 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
8519 "MOVD $dst.lo,$tmp\n\t"
8520 "PSRLQ $tmp,32\n\t"
8521 "MOVD $dst.hi,$tmp" %}
8522 ins_encode(enc_loadLX_reg_volatile(mem, dst, tmp));
8523 ins_pipe( pipe_slow );
8524 %}
8525
8526 // Conditional-store of the updated heap-top.
8527 // Used during allocation of the shared heap.
8528 // Sets flags (EQ) on success. Implemented with a CMPXCHG on Intel.
8529 instruct storePConditional( memory heap_top_ptr, eAXRegP oldval, eRegP newval, eFlagsReg cr ) %{
8530 match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval)));
8531 // EAX is killed if there is contention, but then it's also unused.
8532 // In the common case of no contention, EAX holds the new oop address.
8533 format %{ "CMPXCHG $heap_top_ptr,$newval\t# If EAX==$heap_top_ptr Then store $newval into $heap_top_ptr" %}
8534 ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval,heap_top_ptr) );
8535 ins_pipe( pipe_cmpxchg );
8536 %}
8537
8538 // Conditional-store of an int value.
8539 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG on Intel.
8540 instruct storeIConditional( memory mem, eAXRegI oldval, eRegI newval, eFlagsReg cr ) %{
8541 match(Set cr (StoreIConditional mem (Binary oldval newval)));
8542 effect(KILL oldval);
8543 format %{ "CMPXCHG $mem,$newval\t# If EAX==$mem Then store $newval into $mem" %}
8544 ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval, mem) );
8545 ins_pipe( pipe_cmpxchg );
8546 %}
8547
8548 // Conditional-store of a long value.
8549 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG8 on Intel.
8550 instruct storeLConditional( memory mem, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{
8551 match(Set cr (StoreLConditional mem (Binary oldval newval)));
8552 effect(KILL oldval);
8553 format %{ "XCHG EBX,ECX\t# correct order for CMPXCHG8 instruction\n\t"
8554 "CMPXCHG8 $mem,ECX:EBX\t# If EDX:EAX==$mem Then store ECX:EBX into $mem\n\t"
8555 "XCHG EBX,ECX"
8556 %}
8557 ins_encode %{
8558 // Note: we need to swap rbx, and rcx before and after the
8559 // cmpxchg8 instruction because the instruction uses
8560 // rcx as the high order word of the new value to store but
8561 // our register encoding uses rbx.
8562 __ xchgl(as_Register(EBX_enc), as_Register(ECX_enc));
8563 if( os::is_MP() )
8564 __ lock();
8565 __ cmpxchg8($mem$$Address);
8566 __ xchgl(as_Register(EBX_enc), as_Register(ECX_enc));
8567 %}
8568 ins_pipe( pipe_cmpxchg );
8569 %}
8570
8571 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
8572
8573 instruct compareAndSwapL( eRegI res, eSIRegP mem_ptr, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{
8574 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
8575 effect(KILL cr, KILL oldval);
8576 format %{ "CMPXCHG8 [$mem_ptr],$newval\t# If EDX:EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
8577 "MOV $res,0\n\t"
8578 "JNE,s fail\n\t"
8579 "MOV $res,1\n"
8580 "fail:" %}
8581 ins_encode( enc_cmpxchg8(mem_ptr),
8582 enc_flags_ne_to_boolean(res) );
8583 ins_pipe( pipe_cmpxchg );
8584 %}
8585
8586 instruct compareAndSwapP( eRegI res, pRegP mem_ptr, eAXRegP oldval, eCXRegP newval, eFlagsReg cr) %{
8587 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
8588 effect(KILL cr, KILL oldval);
8589 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
8590 "MOV $res,0\n\t"
8591 "JNE,s fail\n\t"
8592 "MOV $res,1\n"
8593 "fail:" %}
8594 ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) );
8595 ins_pipe( pipe_cmpxchg );
8596 %}
8597
8598 instruct compareAndSwapI( eRegI res, pRegP mem_ptr, eAXRegI oldval, eCXRegI newval, eFlagsReg cr) %{
8599 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
8600 effect(KILL cr, KILL oldval);
8601 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
8602 "MOV $res,0\n\t"
8603 "JNE,s fail\n\t"
8604 "MOV $res,1\n"
8605 "fail:" %}
8606 ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) );
8607 ins_pipe( pipe_cmpxchg );
8608 %}
8609
8610 //----------Subtraction Instructions-------------------------------------------
8611 // Integer Subtraction Instructions
8612 instruct subI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
8613 match(Set dst (SubI dst src));
8614 effect(KILL cr);
8615
8616 size(2);
8617 format %{ "SUB $dst,$src" %}
8618 opcode(0x2B);
8619 ins_encode( OpcP, RegReg( dst, src) );
8620 ins_pipe( ialu_reg_reg );
8621 %}
8622
8623 instruct subI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{
8624 match(Set dst (SubI dst src));
8625 effect(KILL cr);
8626
8627 format %{ "SUB $dst,$src" %}
8628 opcode(0x81,0x05); /* Opcode 81 /5 */
8629 // ins_encode( RegImm( dst, src) );
8630 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8631 ins_pipe( ialu_reg );
8632 %}
8633
8634 instruct subI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{
8635 match(Set dst (SubI dst (LoadI src)));
8636 effect(KILL cr);
8637
8638 ins_cost(125);
8639 format %{ "SUB $dst,$src" %}
8640 opcode(0x2B);
8641 ins_encode( OpcP, RegMem( dst, src) );
8642 ins_pipe( ialu_reg_mem );
8643 %}
8644
8645 instruct subI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{
8646 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
8647 effect(KILL cr);
8648
8649 ins_cost(150);
8650 format %{ "SUB $dst,$src" %}
8651 opcode(0x29); /* Opcode 29 /r */
8652 ins_encode( OpcP, RegMem( src, dst ) );
8653 ins_pipe( ialu_mem_reg );
8654 %}
8655
8656 // Subtract from a pointer
8657 instruct subP_eReg(eRegP dst, eRegI src, immI0 zero, eFlagsReg cr) %{
8658 match(Set dst (AddP dst (SubI zero src)));
8659 effect(KILL cr);
8660
8661 size(2);
8662 format %{ "SUB $dst,$src" %}
8663 opcode(0x2B);
8664 ins_encode( OpcP, RegReg( dst, src) );
8665 ins_pipe( ialu_reg_reg );
8666 %}
8667
8668 instruct negI_eReg(eRegI dst, immI0 zero, eFlagsReg cr) %{
8669 match(Set dst (SubI zero dst));
8670 effect(KILL cr);
8671
8672 size(2);
8673 format %{ "NEG $dst" %}
8674 opcode(0xF7,0x03); // Opcode F7 /3
8675 ins_encode( OpcP, RegOpc( dst ) );
8676 ins_pipe( ialu_reg );
8677 %}
8678
8679
8680 //----------Multiplication/Division Instructions-------------------------------
8681 // Integer Multiplication Instructions
8682 // Multiply Register
8683 instruct mulI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
8684 match(Set dst (MulI dst src));
8685 effect(KILL cr);
8686
8687 size(3);
8688 ins_cost(300);
8689 format %{ "IMUL $dst,$src" %}
8690 opcode(0xAF, 0x0F);
8691 ins_encode( OpcS, OpcP, RegReg( dst, src) );
8692 ins_pipe( ialu_reg_reg_alu0 );
8693 %}
8694
8695 // Multiply 32-bit Immediate
8696 instruct mulI_eReg_imm(eRegI dst, eRegI src, immI imm, eFlagsReg cr) %{
8697 match(Set dst (MulI src imm));
8698 effect(KILL cr);
8699
8700 ins_cost(300);
8701 format %{ "IMUL $dst,$src,$imm" %}
8702 opcode(0x69); /* 69 /r id */
8703 ins_encode( OpcSE(imm), RegReg( dst, src ), Con8or32( imm ) );
8704 ins_pipe( ialu_reg_reg_alu0 );
8705 %}
8706
8707 instruct loadConL_low_only(eADXRegL_low_only dst, immL32 src, eFlagsReg cr) %{
8708 match(Set dst src);
8709 effect(KILL cr);
8710
8711 // Note that this is artificially increased to make it more expensive than loadConL
8712 ins_cost(250);
8713 format %{ "MOV EAX,$src\t// low word only" %}
8714 opcode(0xB8);
8715 ins_encode( LdImmL_Lo(dst, src) );
8716 ins_pipe( ialu_reg_fat );
8717 %}
8718
8719 // Multiply by 32-bit Immediate, taking the shifted high order results
8720 // (special case for shift by 32)
8721 instruct mulI_imm_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32 cnt, eFlagsReg cr) %{
8722 match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt)));
8723 predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL &&
8724 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint &&
8725 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint );
8726 effect(USE src1, KILL cr);
8727
8728 // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only
8729 ins_cost(0*100 + 1*400 - 150);
8730 format %{ "IMUL EDX:EAX,$src1" %}
8731 ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) );
8732 ins_pipe( pipe_slow );
8733 %}
8734
8735 // Multiply by 32-bit Immediate, taking the shifted high order results
8736 instruct mulI_imm_RShift_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr) %{
8737 match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt)));
8738 predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL &&
8739 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint &&
8740 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint );
8741 effect(USE src1, KILL cr);
8742
8743 // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only
8744 ins_cost(1*100 + 1*400 - 150);
8745 format %{ "IMUL EDX:EAX,$src1\n\t"
8746 "SAR EDX,$cnt-32" %}
8747 ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) );
8748 ins_pipe( pipe_slow );
8749 %}
8750
8751 // Multiply Memory 32-bit Immediate
8752 instruct mulI_mem_imm(eRegI dst, memory src, immI imm, eFlagsReg cr) %{
8753 match(Set dst (MulI (LoadI src) imm));
8754 effect(KILL cr);
8755
8756 ins_cost(300);
8757 format %{ "IMUL $dst,$src,$imm" %}
8758 opcode(0x69); /* 69 /r id */
8759 ins_encode( OpcSE(imm), RegMem( dst, src ), Con8or32( imm ) );
8760 ins_pipe( ialu_reg_mem_alu0 );
8761 %}
8762
8763 // Multiply Memory
8764 instruct mulI(eRegI dst, memory src, eFlagsReg cr) %{
8765 match(Set dst (MulI dst (LoadI src)));
8766 effect(KILL cr);
8767
8768 ins_cost(350);
8769 format %{ "IMUL $dst,$src" %}
8770 opcode(0xAF, 0x0F);
8771 ins_encode( OpcS, OpcP, RegMem( dst, src) );
8772 ins_pipe( ialu_reg_mem_alu0 );
8773 %}
8774
8775 // Multiply Register Int to Long
8776 instruct mulI2L(eADXRegL dst, eAXRegI src, nadxRegI src1, eFlagsReg flags) %{
8777 // Basic Idea: long = (long)int * (long)int
8778 match(Set dst (MulL (ConvI2L src) (ConvI2L src1)));
8779 effect(DEF dst, USE src, USE src1, KILL flags);
8780
8781 ins_cost(300);
8782 format %{ "IMUL $dst,$src1" %}
8783
8784 ins_encode( long_int_multiply( dst, src1 ) );
8785 ins_pipe( ialu_reg_reg_alu0 );
8786 %}
8787
8788 instruct mulIS_eReg(eADXRegL dst, immL_32bits mask, eFlagsReg flags, eAXRegI src, nadxRegI src1) %{
8789 // Basic Idea: long = (int & 0xffffffffL) * (int & 0xffffffffL)
8790 match(Set dst (MulL (AndL (ConvI2L src) mask) (AndL (ConvI2L src1) mask)));
8791 effect(KILL flags);
8792
8793 ins_cost(300);
8794 format %{ "MUL $dst,$src1" %}
8795
8796 ins_encode( long_uint_multiply(dst, src1) );
8797 ins_pipe( ialu_reg_reg_alu0 );
8798 %}
8799
8800 // Multiply Register Long
8801 instruct mulL_eReg(eADXRegL dst, eRegL src, eRegI tmp, eFlagsReg cr) %{
8802 match(Set dst (MulL dst src));
8803 effect(KILL cr, TEMP tmp);
8804 ins_cost(4*100+3*400);
8805 // Basic idea: lo(result) = lo(x_lo * y_lo)
8806 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
8807 format %{ "MOV $tmp,$src.lo\n\t"
8808 "IMUL $tmp,EDX\n\t"
8809 "MOV EDX,$src.hi\n\t"
8810 "IMUL EDX,EAX\n\t"
8811 "ADD $tmp,EDX\n\t"
8812 "MUL EDX:EAX,$src.lo\n\t"
8813 "ADD EDX,$tmp" %}
8814 ins_encode( long_multiply( dst, src, tmp ) );
8815 ins_pipe( pipe_slow );
8816 %}
8817
8818 // Multiply Register Long by small constant
8819 instruct mulL_eReg_con(eADXRegL dst, immL_127 src, eRegI tmp, eFlagsReg cr) %{
8820 match(Set dst (MulL dst src));
8821 effect(KILL cr, TEMP tmp);
8822 ins_cost(2*100+2*400);
8823 size(12);
8824 // Basic idea: lo(result) = lo(src * EAX)
8825 // hi(result) = hi(src * EAX) + lo(src * EDX)
8826 format %{ "IMUL $tmp,EDX,$src\n\t"
8827 "MOV EDX,$src\n\t"
8828 "MUL EDX\t# EDX*EAX -> EDX:EAX\n\t"
8829 "ADD EDX,$tmp" %}
8830 ins_encode( long_multiply_con( dst, src, tmp ) );
8831 ins_pipe( pipe_slow );
8832 %}
8833
8834 // Integer DIV with Register
8835 instruct divI_eReg(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{
8836 match(Set rax (DivI rax div));
8837 effect(KILL rdx, KILL cr);
8838 size(26);
8839 ins_cost(30*100+10*100);
8840 format %{ "CMP EAX,0x80000000\n\t"
8841 "JNE,s normal\n\t"
8842 "XOR EDX,EDX\n\t"
8843 "CMP ECX,-1\n\t"
8844 "JE,s done\n"
8845 "normal: CDQ\n\t"
8846 "IDIV $div\n\t"
8847 "done:" %}
8848 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8849 ins_encode( cdq_enc, OpcP, RegOpc(div) );
8850 ins_pipe( ialu_reg_reg_alu0 );
8851 %}
8852
8853 // Divide Register Long
8854 instruct divL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{
8855 match(Set dst (DivL src1 src2));
8856 effect( KILL cr, KILL cx, KILL bx );
8857 ins_cost(10000);
8858 format %{ "PUSH $src1.hi\n\t"
8859 "PUSH $src1.lo\n\t"
8860 "PUSH $src2.hi\n\t"
8861 "PUSH $src2.lo\n\t"
8862 "CALL SharedRuntime::ldiv\n\t"
8863 "ADD ESP,16" %}
8864 ins_encode( long_div(src1,src2) );
8865 ins_pipe( pipe_slow );
8866 %}
8867
8868 // Integer DIVMOD with Register, both quotient and mod results
8869 instruct divModI_eReg_divmod(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{
8870 match(DivModI rax div);
8871 effect(KILL cr);
8872 size(26);
8873 ins_cost(30*100+10*100);
8874 format %{ "CMP EAX,0x80000000\n\t"
8875 "JNE,s normal\n\t"
8876 "XOR EDX,EDX\n\t"
8877 "CMP ECX,-1\n\t"
8878 "JE,s done\n"
8879 "normal: CDQ\n\t"
8880 "IDIV $div\n\t"
8881 "done:" %}
8882 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8883 ins_encode( cdq_enc, OpcP, RegOpc(div) );
8884 ins_pipe( pipe_slow );
8885 %}
8886
8887 // Integer MOD with Register
8888 instruct modI_eReg(eDXRegI rdx, eAXRegI rax, eCXRegI div, eFlagsReg cr) %{
8889 match(Set rdx (ModI rax div));
8890 effect(KILL rax, KILL cr);
8891
8892 size(26);
8893 ins_cost(300);
8894 format %{ "CDQ\n\t"
8895 "IDIV $div" %}
8896 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8897 ins_encode( cdq_enc, OpcP, RegOpc(div) );
8898 ins_pipe( ialu_reg_reg_alu0 );
8899 %}
8900
8901 // Remainder Register Long
8902 instruct modL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{
8903 match(Set dst (ModL src1 src2));
8904 effect( KILL cr, KILL cx, KILL bx );
8905 ins_cost(10000);
8906 format %{ "PUSH $src1.hi\n\t"
8907 "PUSH $src1.lo\n\t"
8908 "PUSH $src2.hi\n\t"
8909 "PUSH $src2.lo\n\t"
8910 "CALL SharedRuntime::lrem\n\t"
8911 "ADD ESP,16" %}
8912 ins_encode( long_mod(src1,src2) );
8913 ins_pipe( pipe_slow );
8914 %}
8915
8916 // Integer Shift Instructions
8917 // Shift Left by one
8918 instruct shlI_eReg_1(eRegI dst, immI1 shift, eFlagsReg cr) %{
8919 match(Set dst (LShiftI dst shift));
8920 effect(KILL cr);
8921
8922 size(2);
8923 format %{ "SHL $dst,$shift" %}
8924 opcode(0xD1, 0x4); /* D1 /4 */
8925 ins_encode( OpcP, RegOpc( dst ) );
8926 ins_pipe( ialu_reg );
8927 %}
8928
8929 // Shift Left by 8-bit immediate
8930 instruct salI_eReg_imm(eRegI dst, immI8 shift, eFlagsReg cr) %{
8931 match(Set dst (LShiftI dst shift));
8932 effect(KILL cr);
8933
8934 size(3);
8935 format %{ "SHL $dst,$shift" %}
8936 opcode(0xC1, 0x4); /* C1 /4 ib */
8937 ins_encode( RegOpcImm( dst, shift) );
8938 ins_pipe( ialu_reg );
8939 %}
8940
8941 // Shift Left by variable
8942 instruct salI_eReg_CL(eRegI dst, eCXRegI shift, eFlagsReg cr) %{
8943 match(Set dst (LShiftI dst shift));
8944 effect(KILL cr);
8945
8946 size(2);
8947 format %{ "SHL $dst,$shift" %}
8948 opcode(0xD3, 0x4); /* D3 /4 */
8949 ins_encode( OpcP, RegOpc( dst ) );
8950 ins_pipe( ialu_reg_reg );
8951 %}
8952
8953 // Arithmetic shift right by one
8954 instruct sarI_eReg_1(eRegI dst, immI1 shift, eFlagsReg cr) %{
8955 match(Set dst (RShiftI dst shift));
8956 effect(KILL cr);
8957
8958 size(2);
8959 format %{ "SAR $dst,$shift" %}
8960 opcode(0xD1, 0x7); /* D1 /7 */
8961 ins_encode( OpcP, RegOpc( dst ) );
8962 ins_pipe( ialu_reg );
8963 %}
8964
8965 // Arithmetic shift right by one
8966 instruct sarI_mem_1(memory dst, immI1 shift, eFlagsReg cr) %{
8967 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8968 effect(KILL cr);
8969 format %{ "SAR $dst,$shift" %}
8970 opcode(0xD1, 0x7); /* D1 /7 */
8971 ins_encode( OpcP, RMopc_Mem(secondary,dst) );
8972 ins_pipe( ialu_mem_imm );
8973 %}
8974
8975 // Arithmetic Shift Right by 8-bit immediate
8976 instruct sarI_eReg_imm(eRegI dst, immI8 shift, eFlagsReg cr) %{
8977 match(Set dst (RShiftI dst shift));
8978 effect(KILL cr);
8979
8980 size(3);
8981 format %{ "SAR $dst,$shift" %}
8982 opcode(0xC1, 0x7); /* C1 /7 ib */
8983 ins_encode( RegOpcImm( dst, shift ) );
8984 ins_pipe( ialu_mem_imm );
8985 %}
8986
8987 // Arithmetic Shift Right by 8-bit immediate
8988 instruct sarI_mem_imm(memory dst, immI8 shift, eFlagsReg cr) %{
8989 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8990 effect(KILL cr);
8991
8992 format %{ "SAR $dst,$shift" %}
8993 opcode(0xC1, 0x7); /* C1 /7 ib */
8994 ins_encode( OpcP, RMopc_Mem(secondary, dst ), Con8or32( shift ) );
8995 ins_pipe( ialu_mem_imm );
8996 %}
8997
8998 // Arithmetic Shift Right by variable
8999 instruct sarI_eReg_CL(eRegI dst, eCXRegI shift, eFlagsReg cr) %{
9000 match(Set dst (RShiftI dst shift));
9001 effect(KILL cr);
9002
9003 size(2);
9004 format %{ "SAR $dst,$shift" %}
9005 opcode(0xD3, 0x7); /* D3 /7 */
9006 ins_encode( OpcP, RegOpc( dst ) );
9007 ins_pipe( ialu_reg_reg );
9008 %}
9009
9010 // Logical shift right by one
9011 instruct shrI_eReg_1(eRegI dst, immI1 shift, eFlagsReg cr) %{
9012 match(Set dst (URShiftI dst shift));
9013 effect(KILL cr);
9014
9015 size(2);
9016 format %{ "SHR $dst,$shift" %}
9017 opcode(0xD1, 0x5); /* D1 /5 */
9018 ins_encode( OpcP, RegOpc( dst ) );
9019 ins_pipe( ialu_reg );
9020 %}
9021
9022 // Logical Shift Right by 8-bit immediate
9023 instruct shrI_eReg_imm(eRegI dst, immI8 shift, eFlagsReg cr) %{
9024 match(Set dst (URShiftI dst shift));
9025 effect(KILL cr);
9026
9027 size(3);
9028 format %{ "SHR $dst,$shift" %}
9029 opcode(0xC1, 0x5); /* C1 /5 ib */
9030 ins_encode( RegOpcImm( dst, shift) );
9031 ins_pipe( ialu_reg );
9032 %}
9033
9034
9035 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24.
9036 // This idiom is used by the compiler for the i2b bytecode.
9037 instruct i2b(eRegI dst, xRegI src, immI_24 twentyfour, eFlagsReg cr) %{
9038 match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour));
9039 effect(KILL cr);
9040
9041 size(3);
9042 format %{ "MOVSX $dst,$src :8" %}
9043 opcode(0xBE, 0x0F);
9044 ins_encode( OpcS, OpcP, RegReg( dst, src));
9045 ins_pipe( ialu_reg_reg );
9046 %}
9047
9048 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16.
9049 // This idiom is used by the compiler the i2s bytecode.
9050 instruct i2s(eRegI dst, xRegI src, immI_16 sixteen, eFlagsReg cr) %{
9051 match(Set dst (RShiftI (LShiftI src sixteen) sixteen));
9052 effect(KILL cr);
9053
9054 size(3);
9055 format %{ "MOVSX $dst,$src :16" %}
9056 opcode(0xBF, 0x0F);
9057 ins_encode( OpcS, OpcP, RegReg( dst, src));
9058 ins_pipe( ialu_reg_reg );
9059 %}
9060
9061
9062 // Logical Shift Right by variable
9063 instruct shrI_eReg_CL(eRegI dst, eCXRegI shift, eFlagsReg cr) %{
9064 match(Set dst (URShiftI dst shift));
9065 effect(KILL cr);
9066
9067 size(2);
9068 format %{ "SHR $dst,$shift" %}
9069 opcode(0xD3, 0x5); /* D3 /5 */
9070 ins_encode( OpcP, RegOpc( dst ) );
9071 ins_pipe( ialu_reg_reg );
9072 %}
9073
9074
9075 //----------Logical Instructions-----------------------------------------------
9076 //----------Integer Logical Instructions---------------------------------------
9077 // And Instructions
9078 // And Register with Register
9079 instruct andI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
9080 match(Set dst (AndI dst src));
9081 effect(KILL cr);
9082
9083 size(2);
9084 format %{ "AND $dst,$src" %}
9085 opcode(0x23);
9086 ins_encode( OpcP, RegReg( dst, src) );
9087 ins_pipe( ialu_reg_reg );
9088 %}
9089
9090 // And Register with Immediate
9091 instruct andI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{
9092 match(Set dst (AndI dst src));
9093 effect(KILL cr);
9094
9095 format %{ "AND $dst,$src" %}
9096 opcode(0x81,0x04); /* Opcode 81 /4 */
9097 // ins_encode( RegImm( dst, src) );
9098 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
9099 ins_pipe( ialu_reg );
9100 %}
9101
9102 // And Register with Memory
9103 instruct andI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{
9104 match(Set dst (AndI dst (LoadI src)));
9105 effect(KILL cr);
9106
9107 ins_cost(125);
9108 format %{ "AND $dst,$src" %}
9109 opcode(0x23);
9110 ins_encode( OpcP, RegMem( dst, src) );
9111 ins_pipe( ialu_reg_mem );
9112 %}
9113
9114 // And Memory with Register
9115 instruct andI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{
9116 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
9117 effect(KILL cr);
9118
9119 ins_cost(150);
9120 format %{ "AND $dst,$src" %}
9121 opcode(0x21); /* Opcode 21 /r */
9122 ins_encode( OpcP, RegMem( src, dst ) );
9123 ins_pipe( ialu_mem_reg );
9124 %}
9125
9126 // And Memory with Immediate
9127 instruct andI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
9128 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
9129 effect(KILL cr);
9130
9131 ins_cost(125);
9132 format %{ "AND $dst,$src" %}
9133 opcode(0x81, 0x4); /* Opcode 81 /4 id */
9134 // ins_encode( MemImm( dst, src) );
9135 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
9136 ins_pipe( ialu_mem_imm );
9137 %}
9138
9139 // Or Instructions
9140 // Or Register with Register
9141 instruct orI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
9142 match(Set dst (OrI dst src));
9143 effect(KILL cr);
9144
9145 size(2);
9146 format %{ "OR $dst,$src" %}
9147 opcode(0x0B);
9148 ins_encode( OpcP, RegReg( dst, src) );
9149 ins_pipe( ialu_reg_reg );
9150 %}
9151
9152 instruct orI_eReg_castP2X(eRegI dst, eRegP src, eFlagsReg cr) %{
9153 match(Set dst (OrI dst (CastP2X src)));
9154 effect(KILL cr);
9155
9156 size(2);
9157 format %{ "OR $dst,$src" %}
9158 opcode(0x0B);
9159 ins_encode( OpcP, RegReg( dst, src) );
9160 ins_pipe( ialu_reg_reg );
9161 %}
9162
9163
9164 // Or Register with Immediate
9165 instruct orI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{
9166 match(Set dst (OrI dst src));
9167 effect(KILL cr);
9168
9169 format %{ "OR $dst,$src" %}
9170 opcode(0x81,0x01); /* Opcode 81 /1 id */
9171 // ins_encode( RegImm( dst, src) );
9172 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
9173 ins_pipe( ialu_reg );
9174 %}
9175
9176 // Or Register with Memory
9177 instruct orI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{
9178 match(Set dst (OrI dst (LoadI src)));
9179 effect(KILL cr);
9180
9181 ins_cost(125);
9182 format %{ "OR $dst,$src" %}
9183 opcode(0x0B);
9184 ins_encode( OpcP, RegMem( dst, src) );
9185 ins_pipe( ialu_reg_mem );
9186 %}
9187
9188 // Or Memory with Register
9189 instruct orI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{
9190 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
9191 effect(KILL cr);
9192
9193 ins_cost(150);
9194 format %{ "OR $dst,$src" %}
9195 opcode(0x09); /* Opcode 09 /r */
9196 ins_encode( OpcP, RegMem( src, dst ) );
9197 ins_pipe( ialu_mem_reg );
9198 %}
9199
9200 // Or Memory with Immediate
9201 instruct orI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
9202 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
9203 effect(KILL cr);
9204
9205 ins_cost(125);
9206 format %{ "OR $dst,$src" %}
9207 opcode(0x81,0x1); /* Opcode 81 /1 id */
9208 // ins_encode( MemImm( dst, src) );
9209 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
9210 ins_pipe( ialu_mem_imm );
9211 %}
9212
9213 // ROL/ROR
9214 // ROL expand
9215 instruct rolI_eReg_imm1(eRegI dst, immI1 shift, eFlagsReg cr) %{
9216 effect(USE_DEF dst, USE shift, KILL cr);
9217
9218 format %{ "ROL $dst, $shift" %}
9219 opcode(0xD1, 0x0); /* Opcode D1 /0 */
9220 ins_encode( OpcP, RegOpc( dst ));
9221 ins_pipe( ialu_reg );
9222 %}
9223
9224 instruct rolI_eReg_imm8(eRegI dst, immI8 shift, eFlagsReg cr) %{
9225 effect(USE_DEF dst, USE shift, KILL cr);
9226
9227 format %{ "ROL $dst, $shift" %}
9228 opcode(0xC1, 0x0); /*Opcode /C1 /0 */
9229 ins_encode( RegOpcImm(dst, shift) );
9230 ins_pipe(ialu_reg);
9231 %}
9232
9233 instruct rolI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr) %{
9234 effect(USE_DEF dst, USE shift, KILL cr);
9235
9236 format %{ "ROL $dst, $shift" %}
9237 opcode(0xD3, 0x0); /* Opcode D3 /0 */
9238 ins_encode(OpcP, RegOpc(dst));
9239 ins_pipe( ialu_reg_reg );
9240 %}
9241 // end of ROL expand
9242
9243 // ROL 32bit by one once
9244 instruct rolI_eReg_i1(eRegI dst, immI1 lshift, immI_M1 rshift, eFlagsReg cr) %{
9245 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift)));
9246
9247 expand %{
9248 rolI_eReg_imm1(dst, lshift, cr);
9249 %}
9250 %}
9251
9252 // ROL 32bit var by imm8 once
9253 instruct rolI_eReg_i8(eRegI dst, immI8 lshift, immI8 rshift, eFlagsReg cr) %{
9254 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
9255 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift)));
9256
9257 expand %{
9258 rolI_eReg_imm8(dst, lshift, cr);
9259 %}
9260 %}
9261
9262 // ROL 32bit var by var once
9263 instruct rolI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{
9264 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI zero shift))));
9265
9266 expand %{
9267 rolI_eReg_CL(dst, shift, cr);
9268 %}
9269 %}
9270
9271 // ROL 32bit var by var once
9272 instruct rolI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{
9273 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI c32 shift))));
9274
9275 expand %{
9276 rolI_eReg_CL(dst, shift, cr);
9277 %}
9278 %}
9279
9280 // ROR expand
9281 instruct rorI_eReg_imm1(eRegI dst, immI1 shift, eFlagsReg cr) %{
9282 effect(USE_DEF dst, USE shift, KILL cr);
9283
9284 format %{ "ROR $dst, $shift" %}
9285 opcode(0xD1,0x1); /* Opcode D1 /1 */
9286 ins_encode( OpcP, RegOpc( dst ) );
9287 ins_pipe( ialu_reg );
9288 %}
9289
9290 instruct rorI_eReg_imm8(eRegI dst, immI8 shift, eFlagsReg cr) %{
9291 effect (USE_DEF dst, USE shift, KILL cr);
9292
9293 format %{ "ROR $dst, $shift" %}
9294 opcode(0xC1, 0x1); /* Opcode /C1 /1 ib */
9295 ins_encode( RegOpcImm(dst, shift) );
9296 ins_pipe( ialu_reg );
9297 %}
9298
9299 instruct rorI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr)%{
9300 effect(USE_DEF dst, USE shift, KILL cr);
9301
9302 format %{ "ROR $dst, $shift" %}
9303 opcode(0xD3, 0x1); /* Opcode D3 /1 */
9304 ins_encode(OpcP, RegOpc(dst));
9305 ins_pipe( ialu_reg_reg );
9306 %}
9307 // end of ROR expand
9308
9309 // ROR right once
9310 instruct rorI_eReg_i1(eRegI dst, immI1 rshift, immI_M1 lshift, eFlagsReg cr) %{
9311 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift)));
9312
9313 expand %{
9314 rorI_eReg_imm1(dst, rshift, cr);
9315 %}
9316 %}
9317
9318 // ROR 32bit by immI8 once
9319 instruct rorI_eReg_i8(eRegI dst, immI8 rshift, immI8 lshift, eFlagsReg cr) %{
9320 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
9321 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift)));
9322
9323 expand %{
9324 rorI_eReg_imm8(dst, rshift, cr);
9325 %}
9326 %}
9327
9328 // ROR 32bit var by var once
9329 instruct rorI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{
9330 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI zero shift))));
9331
9332 expand %{
9333 rorI_eReg_CL(dst, shift, cr);
9334 %}
9335 %}
9336
9337 // ROR 32bit var by var once
9338 instruct rorI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{
9339 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI c32 shift))));
9340
9341 expand %{
9342 rorI_eReg_CL(dst, shift, cr);
9343 %}
9344 %}
9345
9346 // Xor Instructions
9347 // Xor Register with Register
9348 instruct xorI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
9349 match(Set dst (XorI dst src));
9350 effect(KILL cr);
9351
9352 size(2);
9353 format %{ "XOR $dst,$src" %}
9354 opcode(0x33);
9355 ins_encode( OpcP, RegReg( dst, src) );
9356 ins_pipe( ialu_reg_reg );
9357 %}
9358
9359 // Xor Register with Immediate -1
9360 instruct xorI_eReg_im1(eRegI dst, immI_M1 imm) %{
9361 match(Set dst (XorI dst imm));
9362
9363 size(2);
9364 format %{ "NOT $dst" %}
9365 ins_encode %{
9366 __ notl($dst$$Register);
9367 %}
9368 ins_pipe( ialu_reg );
9369 %}
9370
9371 // Xor Register with Immediate
9372 instruct xorI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{
9373 match(Set dst (XorI dst src));
9374 effect(KILL cr);
9375
9376 format %{ "XOR $dst,$src" %}
9377 opcode(0x81,0x06); /* Opcode 81 /6 id */
9378 // ins_encode( RegImm( dst, src) );
9379 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
9380 ins_pipe( ialu_reg );
9381 %}
9382
9383 // Xor Register with Memory
9384 instruct xorI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{
9385 match(Set dst (XorI dst (LoadI src)));
9386 effect(KILL cr);
9387
9388 ins_cost(125);
9389 format %{ "XOR $dst,$src" %}
9390 opcode(0x33);
9391 ins_encode( OpcP, RegMem(dst, src) );
9392 ins_pipe( ialu_reg_mem );
9393 %}
9394
9395 // Xor Memory with Register
9396 instruct xorI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{
9397 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
9398 effect(KILL cr);
9399
9400 ins_cost(150);
9401 format %{ "XOR $dst,$src" %}
9402 opcode(0x31); /* Opcode 31 /r */
9403 ins_encode( OpcP, RegMem( src, dst ) );
9404 ins_pipe( ialu_mem_reg );
9405 %}
9406
9407 // Xor Memory with Immediate
9408 instruct xorI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
9409 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
9410 effect(KILL cr);
9411
9412 ins_cost(125);
9413 format %{ "XOR $dst,$src" %}
9414 opcode(0x81,0x6); /* Opcode 81 /6 id */
9415 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
9416 ins_pipe( ialu_mem_imm );
9417 %}
9418
9419 //----------Convert Int to Boolean---------------------------------------------
9420
9421 instruct movI_nocopy(eRegI dst, eRegI src) %{
9422 effect( DEF dst, USE src );
9423 format %{ "MOV $dst,$src" %}
9424 ins_encode( enc_Copy( dst, src) );
9425 ins_pipe( ialu_reg_reg );
9426 %}
9427
9428 instruct ci2b( eRegI dst, eRegI src, eFlagsReg cr ) %{
9429 effect( USE_DEF dst, USE src, KILL cr );
9430
9431 size(4);
9432 format %{ "NEG $dst\n\t"
9433 "ADC $dst,$src" %}
9434 ins_encode( neg_reg(dst),
9435 OpcRegReg(0x13,dst,src) );
9436 ins_pipe( ialu_reg_reg_long );
9437 %}
9438
9439 instruct convI2B( eRegI dst, eRegI src, eFlagsReg cr ) %{
9440 match(Set dst (Conv2B src));
9441
9442 expand %{
9443 movI_nocopy(dst,src);
9444 ci2b(dst,src,cr);
9445 %}
9446 %}
9447
9448 instruct movP_nocopy(eRegI dst, eRegP src) %{
9449 effect( DEF dst, USE src );
9450 format %{ "MOV $dst,$src" %}
9451 ins_encode( enc_Copy( dst, src) );
9452 ins_pipe( ialu_reg_reg );
9453 %}
9454
9455 instruct cp2b( eRegI dst, eRegP src, eFlagsReg cr ) %{
9456 effect( USE_DEF dst, USE src, KILL cr );
9457 format %{ "NEG $dst\n\t"
9458 "ADC $dst,$src" %}
9459 ins_encode( neg_reg(dst),
9460 OpcRegReg(0x13,dst,src) );
9461 ins_pipe( ialu_reg_reg_long );
9462 %}
9463
9464 instruct convP2B( eRegI dst, eRegP src, eFlagsReg cr ) %{
9465 match(Set dst (Conv2B src));
9466
9467 expand %{
9468 movP_nocopy(dst,src);
9469 cp2b(dst,src,cr);
9470 %}
9471 %}
9472
9473 instruct cmpLTMask( eCXRegI dst, ncxRegI p, ncxRegI q, eFlagsReg cr ) %{
9474 match(Set dst (CmpLTMask p q));
9475 effect( KILL cr );
9476 ins_cost(400);
9477
9478 // SETlt can only use low byte of EAX,EBX, ECX, or EDX as destination
9479 format %{ "XOR $dst,$dst\n\t"
9480 "CMP $p,$q\n\t"
9481 "SETlt $dst\n\t"
9482 "NEG $dst" %}
9483 ins_encode( OpcRegReg(0x33,dst,dst),
9484 OpcRegReg(0x3B,p,q),
9485 setLT_reg(dst), neg_reg(dst) );
9486 ins_pipe( pipe_slow );
9487 %}
9488
9489 instruct cmpLTMask0( eRegI dst, immI0 zero, eFlagsReg cr ) %{
9490 match(Set dst (CmpLTMask dst zero));
9491 effect( DEF dst, KILL cr );
9492 ins_cost(100);
9493
9494 format %{ "SAR $dst,31" %}
9495 opcode(0xC1, 0x7); /* C1 /7 ib */
9496 ins_encode( RegOpcImm( dst, 0x1F ) );
9497 ins_pipe( ialu_reg );
9498 %}
9499
9500
9501 instruct cadd_cmpLTMask( ncxRegI p, ncxRegI q, ncxRegI y, eCXRegI tmp, eFlagsReg cr ) %{
9502 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
9503 effect( KILL tmp, KILL cr );
9504 ins_cost(400);
9505 // annoyingly, $tmp has no edges so you cant ask for it in
9506 // any format or encoding
9507 format %{ "SUB $p,$q\n\t"
9508 "SBB ECX,ECX\n\t"
9509 "AND ECX,$y\n\t"
9510 "ADD $p,ECX" %}
9511 ins_encode( enc_cmpLTP(p,q,y,tmp) );
9512 ins_pipe( pipe_cmplt );
9513 %}
9514
9515 /* If I enable this, I encourage spilling in the inner loop of compress.
9516 instruct cadd_cmpLTMask_mem( ncxRegI p, ncxRegI q, memory y, eCXRegI tmp, eFlagsReg cr ) %{
9517 match(Set p (AddI (AndI (CmpLTMask p q) (LoadI y)) (SubI p q)));
9518 effect( USE_KILL tmp, KILL cr );
9519 ins_cost(400);
9520
9521 format %{ "SUB $p,$q\n\t"
9522 "SBB ECX,ECX\n\t"
9523 "AND ECX,$y\n\t"
9524 "ADD $p,ECX" %}
9525 ins_encode( enc_cmpLTP_mem(p,q,y,tmp) );
9526 %}
9527 */
9528
9529 //----------Long Instructions------------------------------------------------
9530 // Add Long Register with Register
9531 instruct addL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9532 match(Set dst (AddL dst src));
9533 effect(KILL cr);
9534 ins_cost(200);
9535 format %{ "ADD $dst.lo,$src.lo\n\t"
9536 "ADC $dst.hi,$src.hi" %}
9537 opcode(0x03, 0x13);
9538 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) );
9539 ins_pipe( ialu_reg_reg_long );
9540 %}
9541
9542 // Add Long Register with Immediate
9543 instruct addL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9544 match(Set dst (AddL dst src));
9545 effect(KILL cr);
9546 format %{ "ADD $dst.lo,$src.lo\n\t"
9547 "ADC $dst.hi,$src.hi" %}
9548 opcode(0x81,0x00,0x02); /* Opcode 81 /0, 81 /2 */
9549 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9550 ins_pipe( ialu_reg_long );
9551 %}
9552
9553 // Add Long Register with Memory
9554 instruct addL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9555 match(Set dst (AddL dst (LoadL mem)));
9556 effect(KILL cr);
9557 ins_cost(125);
9558 format %{ "ADD $dst.lo,$mem\n\t"
9559 "ADC $dst.hi,$mem+4" %}
9560 opcode(0x03, 0x13);
9561 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9562 ins_pipe( ialu_reg_long_mem );
9563 %}
9564
9565 // Subtract Long Register with Register.
9566 instruct subL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9567 match(Set dst (SubL dst src));
9568 effect(KILL cr);
9569 ins_cost(200);
9570 format %{ "SUB $dst.lo,$src.lo\n\t"
9571 "SBB $dst.hi,$src.hi" %}
9572 opcode(0x2B, 0x1B);
9573 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) );
9574 ins_pipe( ialu_reg_reg_long );
9575 %}
9576
9577 // Subtract Long Register with Immediate
9578 instruct subL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9579 match(Set dst (SubL dst src));
9580 effect(KILL cr);
9581 format %{ "SUB $dst.lo,$src.lo\n\t"
9582 "SBB $dst.hi,$src.hi" %}
9583 opcode(0x81,0x05,0x03); /* Opcode 81 /5, 81 /3 */
9584 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9585 ins_pipe( ialu_reg_long );
9586 %}
9587
9588 // Subtract Long Register with Memory
9589 instruct subL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9590 match(Set dst (SubL dst (LoadL mem)));
9591 effect(KILL cr);
9592 ins_cost(125);
9593 format %{ "SUB $dst.lo,$mem\n\t"
9594 "SBB $dst.hi,$mem+4" %}
9595 opcode(0x2B, 0x1B);
9596 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9597 ins_pipe( ialu_reg_long_mem );
9598 %}
9599
9600 instruct negL_eReg(eRegL dst, immL0 zero, eFlagsReg cr) %{
9601 match(Set dst (SubL zero dst));
9602 effect(KILL cr);
9603 ins_cost(300);
9604 format %{ "NEG $dst.hi\n\tNEG $dst.lo\n\tSBB $dst.hi,0" %}
9605 ins_encode( neg_long(dst) );
9606 ins_pipe( ialu_reg_reg_long );
9607 %}
9608
9609 // And Long Register with Register
9610 instruct andL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9611 match(Set dst (AndL dst src));
9612 effect(KILL cr);
9613 format %{ "AND $dst.lo,$src.lo\n\t"
9614 "AND $dst.hi,$src.hi" %}
9615 opcode(0x23,0x23);
9616 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
9617 ins_pipe( ialu_reg_reg_long );
9618 %}
9619
9620 // And Long Register with Immediate
9621 instruct andL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9622 match(Set dst (AndL dst src));
9623 effect(KILL cr);
9624 format %{ "AND $dst.lo,$src.lo\n\t"
9625 "AND $dst.hi,$src.hi" %}
9626 opcode(0x81,0x04,0x04); /* Opcode 81 /4, 81 /4 */
9627 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9628 ins_pipe( ialu_reg_long );
9629 %}
9630
9631 // And Long Register with Memory
9632 instruct andL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9633 match(Set dst (AndL dst (LoadL mem)));
9634 effect(KILL cr);
9635 ins_cost(125);
9636 format %{ "AND $dst.lo,$mem\n\t"
9637 "AND $dst.hi,$mem+4" %}
9638 opcode(0x23, 0x23);
9639 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9640 ins_pipe( ialu_reg_long_mem );
9641 %}
9642
9643 // Or Long Register with Register
9644 instruct orl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9645 match(Set dst (OrL dst src));
9646 effect(KILL cr);
9647 format %{ "OR $dst.lo,$src.lo\n\t"
9648 "OR $dst.hi,$src.hi" %}
9649 opcode(0x0B,0x0B);
9650 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
9651 ins_pipe( ialu_reg_reg_long );
9652 %}
9653
9654 // Or Long Register with Immediate
9655 instruct orl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9656 match(Set dst (OrL dst src));
9657 effect(KILL cr);
9658 format %{ "OR $dst.lo,$src.lo\n\t"
9659 "OR $dst.hi,$src.hi" %}
9660 opcode(0x81,0x01,0x01); /* Opcode 81 /1, 81 /1 */
9661 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9662 ins_pipe( ialu_reg_long );
9663 %}
9664
9665 // Or Long Register with Memory
9666 instruct orl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9667 match(Set dst (OrL dst (LoadL mem)));
9668 effect(KILL cr);
9669 ins_cost(125);
9670 format %{ "OR $dst.lo,$mem\n\t"
9671 "OR $dst.hi,$mem+4" %}
9672 opcode(0x0B,0x0B);
9673 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9674 ins_pipe( ialu_reg_long_mem );
9675 %}
9676
9677 // Xor Long Register with Register
9678 instruct xorl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9679 match(Set dst (XorL dst src));
9680 effect(KILL cr);
9681 format %{ "XOR $dst.lo,$src.lo\n\t"
9682 "XOR $dst.hi,$src.hi" %}
9683 opcode(0x33,0x33);
9684 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
9685 ins_pipe( ialu_reg_reg_long );
9686 %}
9687
9688 // Xor Long Register with Immediate -1
9689 instruct xorl_eReg_im1(eRegL dst, immL_M1 imm) %{
9690 match(Set dst (XorL dst imm));
9691 format %{ "NOT $dst.lo\n\t"
9692 "NOT $dst.hi" %}
9693 ins_encode %{
9694 __ notl($dst$$Register);
9695 __ notl(HIGH_FROM_LOW($dst$$Register));
9696 %}
9697 ins_pipe( ialu_reg_long );
9698 %}
9699
9700 // Xor Long Register with Immediate
9701 instruct xorl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9702 match(Set dst (XorL dst src));
9703 effect(KILL cr);
9704 format %{ "XOR $dst.lo,$src.lo\n\t"
9705 "XOR $dst.hi,$src.hi" %}
9706 opcode(0x81,0x06,0x06); /* Opcode 81 /6, 81 /6 */
9707 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9708 ins_pipe( ialu_reg_long );
9709 %}
9710
9711 // Xor Long Register with Memory
9712 instruct xorl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9713 match(Set dst (XorL dst (LoadL mem)));
9714 effect(KILL cr);
9715 ins_cost(125);
9716 format %{ "XOR $dst.lo,$mem\n\t"
9717 "XOR $dst.hi,$mem+4" %}
9718 opcode(0x33,0x33);
9719 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9720 ins_pipe( ialu_reg_long_mem );
9721 %}
9722
9723 // Shift Left Long by 1
9724 instruct shlL_eReg_1(eRegL dst, immI_1 cnt, eFlagsReg cr) %{
9725 predicate(UseNewLongLShift);
9726 match(Set dst (LShiftL dst cnt));
9727 effect(KILL cr);
9728 ins_cost(100);
9729 format %{ "ADD $dst.lo,$dst.lo\n\t"
9730 "ADC $dst.hi,$dst.hi" %}
9731 ins_encode %{
9732 __ addl($dst$$Register,$dst$$Register);
9733 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9734 %}
9735 ins_pipe( ialu_reg_long );
9736 %}
9737
9738 // Shift Left Long by 2
9739 instruct shlL_eReg_2(eRegL dst, immI_2 cnt, eFlagsReg cr) %{
9740 predicate(UseNewLongLShift);
9741 match(Set dst (LShiftL dst cnt));
9742 effect(KILL cr);
9743 ins_cost(100);
9744 format %{ "ADD $dst.lo,$dst.lo\n\t"
9745 "ADC $dst.hi,$dst.hi\n\t"
9746 "ADD $dst.lo,$dst.lo\n\t"
9747 "ADC $dst.hi,$dst.hi" %}
9748 ins_encode %{
9749 __ addl($dst$$Register,$dst$$Register);
9750 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9751 __ addl($dst$$Register,$dst$$Register);
9752 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9753 %}
9754 ins_pipe( ialu_reg_long );
9755 %}
9756
9757 // Shift Left Long by 3
9758 instruct shlL_eReg_3(eRegL dst, immI_3 cnt, eFlagsReg cr) %{
9759 predicate(UseNewLongLShift);
9760 match(Set dst (LShiftL dst cnt));
9761 effect(KILL cr);
9762 ins_cost(100);
9763 format %{ "ADD $dst.lo,$dst.lo\n\t"
9764 "ADC $dst.hi,$dst.hi\n\t"
9765 "ADD $dst.lo,$dst.lo\n\t"
9766 "ADC $dst.hi,$dst.hi\n\t"
9767 "ADD $dst.lo,$dst.lo\n\t"
9768 "ADC $dst.hi,$dst.hi" %}
9769 ins_encode %{
9770 __ addl($dst$$Register,$dst$$Register);
9771 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9772 __ addl($dst$$Register,$dst$$Register);
9773 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9774 __ addl($dst$$Register,$dst$$Register);
9775 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9776 %}
9777 ins_pipe( ialu_reg_long );
9778 %}
9779
9780 // Shift Left Long by 1-31
9781 instruct shlL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9782 match(Set dst (LShiftL dst cnt));
9783 effect(KILL cr);
9784 ins_cost(200);
9785 format %{ "SHLD $dst.hi,$dst.lo,$cnt\n\t"
9786 "SHL $dst.lo,$cnt" %}
9787 opcode(0xC1, 0x4, 0xA4); /* 0F/A4, then C1 /4 ib */
9788 ins_encode( move_long_small_shift(dst,cnt) );
9789 ins_pipe( ialu_reg_long );
9790 %}
9791
9792 // Shift Left Long by 32-63
9793 instruct shlL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9794 match(Set dst (LShiftL dst cnt));
9795 effect(KILL cr);
9796 ins_cost(300);
9797 format %{ "MOV $dst.hi,$dst.lo\n"
9798 "\tSHL $dst.hi,$cnt-32\n"
9799 "\tXOR $dst.lo,$dst.lo" %}
9800 opcode(0xC1, 0x4); /* C1 /4 ib */
9801 ins_encode( move_long_big_shift_clr(dst,cnt) );
9802 ins_pipe( ialu_reg_long );
9803 %}
9804
9805 // Shift Left Long by variable
9806 instruct salL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9807 match(Set dst (LShiftL dst shift));
9808 effect(KILL cr);
9809 ins_cost(500+200);
9810 size(17);
9811 format %{ "TEST $shift,32\n\t"
9812 "JEQ,s small\n\t"
9813 "MOV $dst.hi,$dst.lo\n\t"
9814 "XOR $dst.lo,$dst.lo\n"
9815 "small:\tSHLD $dst.hi,$dst.lo,$shift\n\t"
9816 "SHL $dst.lo,$shift" %}
9817 ins_encode( shift_left_long( dst, shift ) );
9818 ins_pipe( pipe_slow );
9819 %}
9820
9821 // Shift Right Long by 1-31
9822 instruct shrL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9823 match(Set dst (URShiftL dst cnt));
9824 effect(KILL cr);
9825 ins_cost(200);
9826 format %{ "SHRD $dst.lo,$dst.hi,$cnt\n\t"
9827 "SHR $dst.hi,$cnt" %}
9828 opcode(0xC1, 0x5, 0xAC); /* 0F/AC, then C1 /5 ib */
9829 ins_encode( move_long_small_shift(dst,cnt) );
9830 ins_pipe( ialu_reg_long );
9831 %}
9832
9833 // Shift Right Long by 32-63
9834 instruct shrL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9835 match(Set dst (URShiftL dst cnt));
9836 effect(KILL cr);
9837 ins_cost(300);
9838 format %{ "MOV $dst.lo,$dst.hi\n"
9839 "\tSHR $dst.lo,$cnt-32\n"
9840 "\tXOR $dst.hi,$dst.hi" %}
9841 opcode(0xC1, 0x5); /* C1 /5 ib */
9842 ins_encode( move_long_big_shift_clr(dst,cnt) );
9843 ins_pipe( ialu_reg_long );
9844 %}
9845
9846 // Shift Right Long by variable
9847 instruct shrL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9848 match(Set dst (URShiftL dst shift));
9849 effect(KILL cr);
9850 ins_cost(600);
9851 size(17);
9852 format %{ "TEST $shift,32\n\t"
9853 "JEQ,s small\n\t"
9854 "MOV $dst.lo,$dst.hi\n\t"
9855 "XOR $dst.hi,$dst.hi\n"
9856 "small:\tSHRD $dst.lo,$dst.hi,$shift\n\t"
9857 "SHR $dst.hi,$shift" %}
9858 ins_encode( shift_right_long( dst, shift ) );
9859 ins_pipe( pipe_slow );
9860 %}
9861
9862 // Shift Right Long by 1-31
9863 instruct sarL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9864 match(Set dst (RShiftL dst cnt));
9865 effect(KILL cr);
9866 ins_cost(200);
9867 format %{ "SHRD $dst.lo,$dst.hi,$cnt\n\t"
9868 "SAR $dst.hi,$cnt" %}
9869 opcode(0xC1, 0x7, 0xAC); /* 0F/AC, then C1 /7 ib */
9870 ins_encode( move_long_small_shift(dst,cnt) );
9871 ins_pipe( ialu_reg_long );
9872 %}
9873
9874 // Shift Right Long by 32-63
9875 instruct sarL_eReg_32_63( eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9876 match(Set dst (RShiftL dst cnt));
9877 effect(KILL cr);
9878 ins_cost(300);
9879 format %{ "MOV $dst.lo,$dst.hi\n"
9880 "\tSAR $dst.lo,$cnt-32\n"
9881 "\tSAR $dst.hi,31" %}
9882 opcode(0xC1, 0x7); /* C1 /7 ib */
9883 ins_encode( move_long_big_shift_sign(dst,cnt) );
9884 ins_pipe( ialu_reg_long );
9885 %}
9886
9887 // Shift Right arithmetic Long by variable
9888 instruct sarL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9889 match(Set dst (RShiftL dst shift));
9890 effect(KILL cr);
9891 ins_cost(600);
9892 size(18);
9893 format %{ "TEST $shift,32\n\t"
9894 "JEQ,s small\n\t"
9895 "MOV $dst.lo,$dst.hi\n\t"
9896 "SAR $dst.hi,31\n"
9897 "small:\tSHRD $dst.lo,$dst.hi,$shift\n\t"
9898 "SAR $dst.hi,$shift" %}
9899 ins_encode( shift_right_arith_long( dst, shift ) );
9900 ins_pipe( pipe_slow );
9901 %}
9902
9903
9904 //----------Double Instructions------------------------------------------------
9905 // Double Math
9906
9907 // Compare & branch
9908
9909 // P6 version of float compare, sets condition codes in EFLAGS
9910 instruct cmpD_cc_P6(eFlagsRegU cr, regD src1, regD src2, eAXRegI rax) %{
9911 predicate(VM_Version::supports_cmov() && UseSSE <=1);
9912 match(Set cr (CmpD src1 src2));
9913 effect(KILL rax);
9914 ins_cost(150);
9915 format %{ "FLD $src1\n\t"
9916 "FUCOMIP ST,$src2 // P6 instruction\n\t"
9917 "JNP exit\n\t"
9918 "MOV ah,1 // saw a NaN, set CF\n\t"
9919 "SAHF\n"
9920 "exit:\tNOP // avoid branch to branch" %}
9921 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
9922 ins_encode( Push_Reg_D(src1),
9923 OpcP, RegOpc(src2),
9924 cmpF_P6_fixup );
9925 ins_pipe( pipe_slow );
9926 %}
9927
9928 instruct cmpD_cc_P6CF(eFlagsRegUCF cr, regD src1, regD src2) %{
9929 predicate(VM_Version::supports_cmov() && UseSSE <=1);
9930 match(Set cr (CmpD src1 src2));
9931 ins_cost(150);
9932 format %{ "FLD $src1\n\t"
9933 "FUCOMIP ST,$src2 // P6 instruction" %}
9934 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
9935 ins_encode( Push_Reg_D(src1),
9936 OpcP, RegOpc(src2));
9937 ins_pipe( pipe_slow );
9938 %}
9939
9940 // Compare & branch
9941 instruct cmpD_cc(eFlagsRegU cr, regD src1, regD src2, eAXRegI rax) %{
9942 predicate(UseSSE<=1);
9943 match(Set cr (CmpD src1 src2));
9944 effect(KILL rax);
9945 ins_cost(200);
9946 format %{ "FLD $src1\n\t"
9947 "FCOMp $src2\n\t"
9948 "FNSTSW AX\n\t"
9949 "TEST AX,0x400\n\t"
9950 "JZ,s flags\n\t"
9951 "MOV AH,1\t# unordered treat as LT\n"
9952 "flags:\tSAHF" %}
9953 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
9954 ins_encode( Push_Reg_D(src1),
9955 OpcP, RegOpc(src2),
9956 fpu_flags);
9957 ins_pipe( pipe_slow );
9958 %}
9959
9960 // Compare vs zero into -1,0,1
9961 instruct cmpD_0(eRegI dst, regD src1, immD0 zero, eAXRegI rax, eFlagsReg cr) %{
9962 predicate(UseSSE<=1);
9963 match(Set dst (CmpD3 src1 zero));
9964 effect(KILL cr, KILL rax);
9965 ins_cost(280);
9966 format %{ "FTSTD $dst,$src1" %}
9967 opcode(0xE4, 0xD9);
9968 ins_encode( Push_Reg_D(src1),
9969 OpcS, OpcP, PopFPU,
9970 CmpF_Result(dst));
9971 ins_pipe( pipe_slow );
9972 %}
9973
9974 // Compare into -1,0,1
9975 instruct cmpD_reg(eRegI dst, regD src1, regD src2, eAXRegI rax, eFlagsReg cr) %{
9976 predicate(UseSSE<=1);
9977 match(Set dst (CmpD3 src1 src2));
9978 effect(KILL cr, KILL rax);
9979 ins_cost(300);
9980 format %{ "FCMPD $dst,$src1,$src2" %}
9981 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
9982 ins_encode( Push_Reg_D(src1),
9983 OpcP, RegOpc(src2),
9984 CmpF_Result(dst));
9985 ins_pipe( pipe_slow );
9986 %}
9987
9988 // float compare and set condition codes in EFLAGS by XMM regs
9989 instruct cmpXD_cc(eFlagsRegU cr, regXD dst, regXD src, eAXRegI rax) %{
9990 predicate(UseSSE>=2);
9991 match(Set cr (CmpD dst src));
9992 effect(KILL rax);
9993 ins_cost(125);
9994 format %{ "COMISD $dst,$src\n"
9995 "\tJNP exit\n"
9996 "\tMOV ah,1 // saw a NaN, set CF\n"
9997 "\tSAHF\n"
9998 "exit:\tNOP // avoid branch to branch" %}
9999 opcode(0x66, 0x0F, 0x2F);
10000 ins_encode(OpcP, OpcS, Opcode(tertiary), RegReg(dst, src), cmpF_P6_fixup);
10001 ins_pipe( pipe_slow );
10002 %}
10003
10004 instruct cmpXD_ccCF(eFlagsRegUCF cr, regXD dst, regXD src) %{
10005 predicate(UseSSE>=2);
10006 match(Set cr (CmpD dst src));
10007 ins_cost(100);
10008 format %{ "COMISD $dst,$src" %}
10009 opcode(0x66, 0x0F, 0x2F);
10010 ins_encode(OpcP, OpcS, Opcode(tertiary), RegReg(dst, src));
10011 ins_pipe( pipe_slow );
10012 %}
10013
10014 // float compare and set condition codes in EFLAGS by XMM regs
10015 instruct cmpXD_ccmem(eFlagsRegU cr, regXD dst, memory src, eAXRegI rax) %{
10016 predicate(UseSSE>=2);
10017 match(Set cr (CmpD dst (LoadD src)));
10018 effect(KILL rax);
10019 ins_cost(145);
10020 format %{ "COMISD $dst,$src\n"
10021 "\tJNP exit\n"
10022 "\tMOV ah,1 // saw a NaN, set CF\n"
10023 "\tSAHF\n"
10024 "exit:\tNOP // avoid branch to branch" %}
10025 opcode(0x66, 0x0F, 0x2F);
10026 ins_encode(OpcP, OpcS, Opcode(tertiary), RegMem(dst, src), cmpF_P6_fixup);
10027 ins_pipe( pipe_slow );
10028 %}
10029
10030 instruct cmpXD_ccmemCF(eFlagsRegUCF cr, regXD dst, memory src) %{
10031 predicate(UseSSE>=2);
10032 match(Set cr (CmpD dst (LoadD src)));
10033 ins_cost(100);
10034 format %{ "COMISD $dst,$src" %}
10035 opcode(0x66, 0x0F, 0x2F);
10036 ins_encode(OpcP, OpcS, Opcode(tertiary), RegMem(dst, src));
10037 ins_pipe( pipe_slow );
10038 %}
10039
10040 // Compare into -1,0,1 in XMM
10041 instruct cmpXD_reg(eRegI dst, regXD src1, regXD src2, eFlagsReg cr) %{
10042 predicate(UseSSE>=2);
10043 match(Set dst (CmpD3 src1 src2));
10044 effect(KILL cr);
10045 ins_cost(255);
10046 format %{ "XOR $dst,$dst\n"
10047 "\tCOMISD $src1,$src2\n"
10048 "\tJP,s nan\n"
10049 "\tJEQ,s exit\n"
10050 "\tJA,s inc\n"
10051 "nan:\tDEC $dst\n"
10052 "\tJMP,s exit\n"
10053 "inc:\tINC $dst\n"
10054 "exit:"
10055 %}
10056 opcode(0x66, 0x0F, 0x2F);
10057 ins_encode(Xor_Reg(dst), OpcP, OpcS, Opcode(tertiary), RegReg(src1, src2),
10058 CmpX_Result(dst));
10059 ins_pipe( pipe_slow );
10060 %}
10061
10062 // Compare into -1,0,1 in XMM and memory
10063 instruct cmpXD_regmem(eRegI dst, regXD src1, memory mem, eFlagsReg cr) %{
10064 predicate(UseSSE>=2);
10065 match(Set dst (CmpD3 src1 (LoadD mem)));
10066 effect(KILL cr);
10067 ins_cost(275);
10068 format %{ "COMISD $src1,$mem\n"
10069 "\tMOV $dst,0\t\t# do not blow flags\n"
10070 "\tJP,s nan\n"
10071 "\tJEQ,s exit\n"
10072 "\tJA,s inc\n"
10073 "nan:\tDEC $dst\n"
10074 "\tJMP,s exit\n"
10075 "inc:\tINC $dst\n"
10076 "exit:"
10077 %}
10078 opcode(0x66, 0x0F, 0x2F);
10079 ins_encode(OpcP, OpcS, Opcode(tertiary), RegMem(src1, mem),
10080 LdImmI(dst,0x0), CmpX_Result(dst));
10081 ins_pipe( pipe_slow );
10082 %}
10083
10084
10085 instruct subD_reg(regD dst, regD src) %{
10086 predicate (UseSSE <=1);
10087 match(Set dst (SubD dst src));
10088
10089 format %{ "FLD $src\n\t"
10090 "DSUBp $dst,ST" %}
10091 opcode(0xDE, 0x5); /* DE E8+i or DE /5 */
10092 ins_cost(150);
10093 ins_encode( Push_Reg_D(src),
10094 OpcP, RegOpc(dst) );
10095 ins_pipe( fpu_reg_reg );
10096 %}
10097
10098 instruct subD_reg_round(stackSlotD dst, regD src1, regD src2) %{
10099 predicate (UseSSE <=1);
10100 match(Set dst (RoundDouble (SubD src1 src2)));
10101 ins_cost(250);
10102
10103 format %{ "FLD $src2\n\t"
10104 "DSUB ST,$src1\n\t"
10105 "FSTP_D $dst\t# D-round" %}
10106 opcode(0xD8, 0x5);
10107 ins_encode( Push_Reg_D(src2),
10108 OpcP, RegOpc(src1), Pop_Mem_D(dst) );
10109 ins_pipe( fpu_mem_reg_reg );
10110 %}
10111
10112
10113 instruct subD_reg_mem(regD dst, memory src) %{
10114 predicate (UseSSE <=1);
10115 match(Set dst (SubD dst (LoadD src)));
10116 ins_cost(150);
10117
10118 format %{ "FLD $src\n\t"
10119 "DSUBp $dst,ST" %}
10120 opcode(0xDE, 0x5, 0xDD); /* DE C0+i */ /* LoadD DD /0 */
10121 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
10122 OpcP, RegOpc(dst) );
10123 ins_pipe( fpu_reg_mem );
10124 %}
10125
10126 instruct absD_reg(regDPR1 dst, regDPR1 src) %{
10127 predicate (UseSSE<=1);
10128 match(Set dst (AbsD src));
10129 ins_cost(100);
10130 format %{ "FABS" %}
10131 opcode(0xE1, 0xD9);
10132 ins_encode( OpcS, OpcP );
10133 ins_pipe( fpu_reg_reg );
10134 %}
10135
10136 instruct absXD_reg( regXD dst ) %{
10137 predicate(UseSSE>=2);
10138 match(Set dst (AbsD dst));
10139 format %{ "ANDPD $dst,[0x7FFFFFFFFFFFFFFF]\t# ABS D by sign masking" %}
10140 ins_encode( AbsXD_encoding(dst));
10141 ins_pipe( pipe_slow );
10142 %}
10143
10144 instruct negD_reg(regDPR1 dst, regDPR1 src) %{
10145 predicate(UseSSE<=1);
10146 match(Set dst (NegD src));
10147 ins_cost(100);
10148 format %{ "FCHS" %}
10149 opcode(0xE0, 0xD9);
10150 ins_encode( OpcS, OpcP );
10151 ins_pipe( fpu_reg_reg );
10152 %}
10153
10154 instruct negXD_reg( regXD dst ) %{
10155 predicate(UseSSE>=2);
10156 match(Set dst (NegD dst));
10157 format %{ "XORPD $dst,[0x8000000000000000]\t# CHS D by sign flipping" %}
10158 ins_encode %{
10159 __ xorpd($dst$$XMMRegister,
10160 ExternalAddress((address)double_signflip_pool));
10161 %}
10162 ins_pipe( pipe_slow );
10163 %}
10164
10165 instruct addD_reg(regD dst, regD src) %{
10166 predicate(UseSSE<=1);
10167 match(Set dst (AddD dst src));
10168 format %{ "FLD $src\n\t"
10169 "DADD $dst,ST" %}
10170 size(4);
10171 ins_cost(150);
10172 opcode(0xDE, 0x0); /* DE C0+i or DE /0*/
10173 ins_encode( Push_Reg_D(src),
10174 OpcP, RegOpc(dst) );
10175 ins_pipe( fpu_reg_reg );
10176 %}
10177
10178
10179 instruct addD_reg_round(stackSlotD dst, regD src1, regD src2) %{
10180 predicate(UseSSE<=1);
10181 match(Set dst (RoundDouble (AddD src1 src2)));
10182 ins_cost(250);
10183
10184 format %{ "FLD $src2\n\t"
10185 "DADD ST,$src1\n\t"
10186 "FSTP_D $dst\t# D-round" %}
10187 opcode(0xD8, 0x0); /* D8 C0+i or D8 /0*/
10188 ins_encode( Push_Reg_D(src2),
10189 OpcP, RegOpc(src1), Pop_Mem_D(dst) );
10190 ins_pipe( fpu_mem_reg_reg );
10191 %}
10192
10193
10194 instruct addD_reg_mem(regD dst, memory src) %{
10195 predicate(UseSSE<=1);
10196 match(Set dst (AddD dst (LoadD src)));
10197 ins_cost(150);
10198
10199 format %{ "FLD $src\n\t"
10200 "DADDp $dst,ST" %}
10201 opcode(0xDE, 0x0, 0xDD); /* DE C0+i */ /* LoadD DD /0 */
10202 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
10203 OpcP, RegOpc(dst) );
10204 ins_pipe( fpu_reg_mem );
10205 %}
10206
10207 // add-to-memory
10208 instruct addD_mem_reg(memory dst, regD src) %{
10209 predicate(UseSSE<=1);
10210 match(Set dst (StoreD dst (RoundDouble (AddD (LoadD dst) src))));
10211 ins_cost(150);
10212
10213 format %{ "FLD_D $dst\n\t"
10214 "DADD ST,$src\n\t"
10215 "FST_D $dst" %}
10216 opcode(0xDD, 0x0);
10217 ins_encode( Opcode(0xDD), RMopc_Mem(0x00,dst),
10218 Opcode(0xD8), RegOpc(src),
10219 set_instruction_start,
10220 Opcode(0xDD), RMopc_Mem(0x03,dst) );
10221 ins_pipe( fpu_reg_mem );
10222 %}
10223
10224 instruct addD_reg_imm1(regD dst, immD1 src) %{
10225 predicate(UseSSE<=1);
10226 match(Set dst (AddD dst src));
10227 ins_cost(125);
10228 format %{ "FLD1\n\t"
10229 "DADDp $dst,ST" %}
10230 opcode(0xDE, 0x00);
10231 ins_encode( LdImmD(src),
10232 OpcP, RegOpc(dst) );
10233 ins_pipe( fpu_reg );
10234 %}
10235
10236 instruct addD_reg_imm(regD dst, immD src) %{
10237 predicate(UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 );
10238 match(Set dst (AddD dst src));
10239 ins_cost(200);
10240 format %{ "FLD_D [$src]\n\t"
10241 "DADDp $dst,ST" %}
10242 opcode(0xDE, 0x00); /* DE /0 */
10243 ins_encode( LdImmD(src),
10244 OpcP, RegOpc(dst));
10245 ins_pipe( fpu_reg_mem );
10246 %}
10247
10248 instruct addD_reg_imm_round(stackSlotD dst, regD src, immD con) %{
10249 predicate(UseSSE<=1 && _kids[0]->_kids[1]->_leaf->getd() != 0.0 && _kids[0]->_kids[1]->_leaf->getd() != 1.0 );
10250 match(Set dst (RoundDouble (AddD src con)));
10251 ins_cost(200);
10252 format %{ "FLD_D [$con]\n\t"
10253 "DADD ST,$src\n\t"
10254 "FSTP_D $dst\t# D-round" %}
10255 opcode(0xD8, 0x00); /* D8 /0 */
10256 ins_encode( LdImmD(con),
10257 OpcP, RegOpc(src), Pop_Mem_D(dst));
10258 ins_pipe( fpu_mem_reg_con );
10259 %}
10260
10261 // Add two double precision floating point values in xmm
10262 instruct addXD_reg(regXD dst, regXD src) %{
10263 predicate(UseSSE>=2);
10264 match(Set dst (AddD dst src));
10265 format %{ "ADDSD $dst,$src" %}
10266 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x58), RegReg(dst, src));
10267 ins_pipe( pipe_slow );
10268 %}
10269
10270 instruct addXD_imm(regXD dst, immXD con) %{
10271 predicate(UseSSE>=2);
10272 match(Set dst (AddD dst con));
10273 format %{ "ADDSD $dst,[$con]" %}
10274 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x58), LdImmXD(dst, con) );
10275 ins_pipe( pipe_slow );
10276 %}
10277
10278 instruct addXD_mem(regXD dst, memory mem) %{
10279 predicate(UseSSE>=2);
10280 match(Set dst (AddD dst (LoadD mem)));
10281 format %{ "ADDSD $dst,$mem" %}
10282 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x58), RegMem(dst,mem));
10283 ins_pipe( pipe_slow );
10284 %}
10285
10286 // Sub two double precision floating point values in xmm
10287 instruct subXD_reg(regXD dst, regXD src) %{
10288 predicate(UseSSE>=2);
10289 match(Set dst (SubD dst src));
10290 format %{ "SUBSD $dst,$src" %}
10291 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5C), RegReg(dst, src));
10292 ins_pipe( pipe_slow );
10293 %}
10294
10295 instruct subXD_imm(regXD dst, immXD con) %{
10296 predicate(UseSSE>=2);
10297 match(Set dst (SubD dst con));
10298 format %{ "SUBSD $dst,[$con]" %}
10299 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5C), LdImmXD(dst, con) );
10300 ins_pipe( pipe_slow );
10301 %}
10302
10303 instruct subXD_mem(regXD dst, memory mem) %{
10304 predicate(UseSSE>=2);
10305 match(Set dst (SubD dst (LoadD mem)));
10306 format %{ "SUBSD $dst,$mem" %}
10307 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5C), RegMem(dst,mem));
10308 ins_pipe( pipe_slow );
10309 %}
10310
10311 // Mul two double precision floating point values in xmm
10312 instruct mulXD_reg(regXD dst, regXD src) %{
10313 predicate(UseSSE>=2);
10314 match(Set dst (MulD dst src));
10315 format %{ "MULSD $dst,$src" %}
10316 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x59), RegReg(dst, src));
10317 ins_pipe( pipe_slow );
10318 %}
10319
10320 instruct mulXD_imm(regXD dst, immXD con) %{
10321 predicate(UseSSE>=2);
10322 match(Set dst (MulD dst con));
10323 format %{ "MULSD $dst,[$con]" %}
10324 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x59), LdImmXD(dst, con) );
10325 ins_pipe( pipe_slow );
10326 %}
10327
10328 instruct mulXD_mem(regXD dst, memory mem) %{
10329 predicate(UseSSE>=2);
10330 match(Set dst (MulD dst (LoadD mem)));
10331 format %{ "MULSD $dst,$mem" %}
10332 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x59), RegMem(dst,mem));
10333 ins_pipe( pipe_slow );
10334 %}
10335
10336 // Div two double precision floating point values in xmm
10337 instruct divXD_reg(regXD dst, regXD src) %{
10338 predicate(UseSSE>=2);
10339 match(Set dst (DivD dst src));
10340 format %{ "DIVSD $dst,$src" %}
10341 opcode(0xF2, 0x0F, 0x5E);
10342 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5E), RegReg(dst, src));
10343 ins_pipe( pipe_slow );
10344 %}
10345
10346 instruct divXD_imm(regXD dst, immXD con) %{
10347 predicate(UseSSE>=2);
10348 match(Set dst (DivD dst con));
10349 format %{ "DIVSD $dst,[$con]" %}
10350 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5E), LdImmXD(dst, con));
10351 ins_pipe( pipe_slow );
10352 %}
10353
10354 instruct divXD_mem(regXD dst, memory mem) %{
10355 predicate(UseSSE>=2);
10356 match(Set dst (DivD dst (LoadD mem)));
10357 format %{ "DIVSD $dst,$mem" %}
10358 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5E), RegMem(dst,mem));
10359 ins_pipe( pipe_slow );
10360 %}
10361
10362
10363 instruct mulD_reg(regD dst, regD src) %{
10364 predicate(UseSSE<=1);
10365 match(Set dst (MulD dst src));
10366 format %{ "FLD $src\n\t"
10367 "DMULp $dst,ST" %}
10368 opcode(0xDE, 0x1); /* DE C8+i or DE /1*/
10369 ins_cost(150);
10370 ins_encode( Push_Reg_D(src),
10371 OpcP, RegOpc(dst) );
10372 ins_pipe( fpu_reg_reg );
10373 %}
10374
10375 // Strict FP instruction biases argument before multiply then
10376 // biases result to avoid double rounding of subnormals.
10377 //
10378 // scale arg1 by multiplying arg1 by 2^(-15360)
10379 // load arg2
10380 // multiply scaled arg1 by arg2
10381 // rescale product by 2^(15360)
10382 //
10383 instruct strictfp_mulD_reg(regDPR1 dst, regnotDPR1 src) %{
10384 predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() );
10385 match(Set dst (MulD dst src));
10386 ins_cost(1); // Select this instruction for all strict FP double multiplies
10387
10388 format %{ "FLD StubRoutines::_fpu_subnormal_bias1\n\t"
10389 "DMULp $dst,ST\n\t"
10390 "FLD $src\n\t"
10391 "DMULp $dst,ST\n\t"
10392 "FLD StubRoutines::_fpu_subnormal_bias2\n\t"
10393 "DMULp $dst,ST\n\t" %}
10394 opcode(0xDE, 0x1); /* DE C8+i or DE /1*/
10395 ins_encode( strictfp_bias1(dst),
10396 Push_Reg_D(src),
10397 OpcP, RegOpc(dst),
10398 strictfp_bias2(dst) );
10399 ins_pipe( fpu_reg_reg );
10400 %}
10401
10402 instruct mulD_reg_imm(regD dst, immD src) %{
10403 predicate( UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 );
10404 match(Set dst (MulD dst src));
10405 ins_cost(200);
10406 format %{ "FLD_D [$src]\n\t"
10407 "DMULp $dst,ST" %}
10408 opcode(0xDE, 0x1); /* DE /1 */
10409 ins_encode( LdImmD(src),
10410 OpcP, RegOpc(dst) );
10411 ins_pipe( fpu_reg_mem );
10412 %}
10413
10414
10415 instruct mulD_reg_mem(regD dst, memory src) %{
10416 predicate( UseSSE<=1 );
10417 match(Set dst (MulD dst (LoadD src)));
10418 ins_cost(200);
10419 format %{ "FLD_D $src\n\t"
10420 "DMULp $dst,ST" %}
10421 opcode(0xDE, 0x1, 0xDD); /* DE C8+i or DE /1*/ /* LoadD DD /0 */
10422 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
10423 OpcP, RegOpc(dst) );
10424 ins_pipe( fpu_reg_mem );
10425 %}
10426
10427 //
10428 // Cisc-alternate to reg-reg multiply
10429 instruct mulD_reg_mem_cisc(regD dst, regD src, memory mem) %{
10430 predicate( UseSSE<=1 );
10431 match(Set dst (MulD src (LoadD mem)));
10432 ins_cost(250);
10433 format %{ "FLD_D $mem\n\t"
10434 "DMUL ST,$src\n\t"
10435 "FSTP_D $dst" %}
10436 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */ /* LoadD D9 /0 */
10437 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem),
10438 OpcReg_F(src),
10439 Pop_Reg_D(dst) );
10440 ins_pipe( fpu_reg_reg_mem );
10441 %}
10442
10443
10444 // MACRO3 -- addD a mulD
10445 // This instruction is a '2-address' instruction in that the result goes
10446 // back to src2. This eliminates a move from the macro; possibly the
10447 // register allocator will have to add it back (and maybe not).
10448 instruct addD_mulD_reg(regD src2, regD src1, regD src0) %{
10449 predicate( UseSSE<=1 );
10450 match(Set src2 (AddD (MulD src0 src1) src2));
10451 format %{ "FLD $src0\t# ===MACRO3d===\n\t"
10452 "DMUL ST,$src1\n\t"
10453 "DADDp $src2,ST" %}
10454 ins_cost(250);
10455 opcode(0xDD); /* LoadD DD /0 */
10456 ins_encode( Push_Reg_F(src0),
10457 FMul_ST_reg(src1),
10458 FAddP_reg_ST(src2) );
10459 ins_pipe( fpu_reg_reg_reg );
10460 %}
10461
10462
10463 // MACRO3 -- subD a mulD
10464 instruct subD_mulD_reg(regD src2, regD src1, regD src0) %{
10465 predicate( UseSSE<=1 );
10466 match(Set src2 (SubD (MulD src0 src1) src2));
10467 format %{ "FLD $src0\t# ===MACRO3d===\n\t"
10468 "DMUL ST,$src1\n\t"
10469 "DSUBRp $src2,ST" %}
10470 ins_cost(250);
10471 ins_encode( Push_Reg_F(src0),
10472 FMul_ST_reg(src1),
10473 Opcode(0xDE), Opc_plus(0xE0,src2));
10474 ins_pipe( fpu_reg_reg_reg );
10475 %}
10476
10477
10478 instruct divD_reg(regD dst, regD src) %{
10479 predicate( UseSSE<=1 );
10480 match(Set dst (DivD dst src));
10481
10482 format %{ "FLD $src\n\t"
10483 "FDIVp $dst,ST" %}
10484 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
10485 ins_cost(150);
10486 ins_encode( Push_Reg_D(src),
10487 OpcP, RegOpc(dst) );
10488 ins_pipe( fpu_reg_reg );
10489 %}
10490
10491 // Strict FP instruction biases argument before division then
10492 // biases result, to avoid double rounding of subnormals.
10493 //
10494 // scale dividend by multiplying dividend by 2^(-15360)
10495 // load divisor
10496 // divide scaled dividend by divisor
10497 // rescale quotient by 2^(15360)
10498 //
10499 instruct strictfp_divD_reg(regDPR1 dst, regnotDPR1 src) %{
10500 predicate (UseSSE<=1);
10501 match(Set dst (DivD dst src));
10502 predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() );
10503 ins_cost(01);
10504
10505 format %{ "FLD StubRoutines::_fpu_subnormal_bias1\n\t"
10506 "DMULp $dst,ST\n\t"
10507 "FLD $src\n\t"
10508 "FDIVp $dst,ST\n\t"
10509 "FLD StubRoutines::_fpu_subnormal_bias2\n\t"
10510 "DMULp $dst,ST\n\t" %}
10511 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
10512 ins_encode( strictfp_bias1(dst),
10513 Push_Reg_D(src),
10514 OpcP, RegOpc(dst),
10515 strictfp_bias2(dst) );
10516 ins_pipe( fpu_reg_reg );
10517 %}
10518
10519 instruct divD_reg_round(stackSlotD dst, regD src1, regD src2) %{
10520 predicate( UseSSE<=1 && !(Compile::current()->has_method() && Compile::current()->method()->is_strict()) );
10521 match(Set dst (RoundDouble (DivD src1 src2)));
10522
10523 format %{ "FLD $src1\n\t"
10524 "FDIV ST,$src2\n\t"
10525 "FSTP_D $dst\t# D-round" %}
10526 opcode(0xD8, 0x6); /* D8 F0+i or D8 /6 */
10527 ins_encode( Push_Reg_D(src1),
10528 OpcP, RegOpc(src2), Pop_Mem_D(dst) );
10529 ins_pipe( fpu_mem_reg_reg );
10530 %}
10531
10532
10533 instruct modD_reg(regD dst, regD src, eAXRegI rax, eFlagsReg cr) %{
10534 predicate(UseSSE<=1);
10535 match(Set dst (ModD dst src));
10536 effect(KILL rax, KILL cr); // emitModD() uses EAX and EFLAGS
10537
10538 format %{ "DMOD $dst,$src" %}
10539 ins_cost(250);
10540 ins_encode(Push_Reg_Mod_D(dst, src),
10541 emitModD(),
10542 Push_Result_Mod_D(src),
10543 Pop_Reg_D(dst));
10544 ins_pipe( pipe_slow );
10545 %}
10546
10547 instruct modXD_reg(regXD dst, regXD src0, regXD src1, eAXRegI rax, eFlagsReg cr) %{
10548 predicate(UseSSE>=2);
10549 match(Set dst (ModD src0 src1));
10550 effect(KILL rax, KILL cr);
10551
10552 format %{ "SUB ESP,8\t # DMOD\n"
10553 "\tMOVSD [ESP+0],$src1\n"
10554 "\tFLD_D [ESP+0]\n"
10555 "\tMOVSD [ESP+0],$src0\n"
10556 "\tFLD_D [ESP+0]\n"
10557 "loop:\tFPREM\n"
10558 "\tFWAIT\n"
10559 "\tFNSTSW AX\n"
10560 "\tSAHF\n"
10561 "\tJP loop\n"
10562 "\tFSTP_D [ESP+0]\n"
10563 "\tMOVSD $dst,[ESP+0]\n"
10564 "\tADD ESP,8\n"
10565 "\tFSTP ST0\t # Restore FPU Stack"
10566 %}
10567 ins_cost(250);
10568 ins_encode( Push_ModD_encoding(src0, src1), emitModD(), Push_ResultXD(dst), PopFPU);
10569 ins_pipe( pipe_slow );
10570 %}
10571
10572 instruct sinD_reg(regDPR1 dst, regDPR1 src) %{
10573 predicate (UseSSE<=1);
10574 match(Set dst (SinD src));
10575 ins_cost(1800);
10576 format %{ "DSIN $dst" %}
10577 opcode(0xD9, 0xFE);
10578 ins_encode( OpcP, OpcS );
10579 ins_pipe( pipe_slow );
10580 %}
10581
10582 instruct sinXD_reg(regXD dst, eFlagsReg cr) %{
10583 predicate (UseSSE>=2);
10584 match(Set dst (SinD dst));
10585 effect(KILL cr); // Push_{Src|Result}XD() uses "{SUB|ADD} ESP,8"
10586 ins_cost(1800);
10587 format %{ "DSIN $dst" %}
10588 opcode(0xD9, 0xFE);
10589 ins_encode( Push_SrcXD(dst), OpcP, OpcS, Push_ResultXD(dst) );
10590 ins_pipe( pipe_slow );
10591 %}
10592
10593 instruct cosD_reg(regDPR1 dst, regDPR1 src) %{
10594 predicate (UseSSE<=1);
10595 match(Set dst (CosD src));
10596 ins_cost(1800);
10597 format %{ "DCOS $dst" %}
10598 opcode(0xD9, 0xFF);
10599 ins_encode( OpcP, OpcS );
10600 ins_pipe( pipe_slow );
10601 %}
10602
10603 instruct cosXD_reg(regXD dst, eFlagsReg cr) %{
10604 predicate (UseSSE>=2);
10605 match(Set dst (CosD dst));
10606 effect(KILL cr); // Push_{Src|Result}XD() uses "{SUB|ADD} ESP,8"
10607 ins_cost(1800);
10608 format %{ "DCOS $dst" %}
10609 opcode(0xD9, 0xFF);
10610 ins_encode( Push_SrcXD(dst), OpcP, OpcS, Push_ResultXD(dst) );
10611 ins_pipe( pipe_slow );
10612 %}
10613
10614 instruct tanD_reg(regDPR1 dst, regDPR1 src) %{
10615 predicate (UseSSE<=1);
10616 match(Set dst(TanD src));
10617 format %{ "DTAN $dst" %}
10618 ins_encode( Opcode(0xD9), Opcode(0xF2), // fptan
10619 Opcode(0xDD), Opcode(0xD8)); // fstp st
10620 ins_pipe( pipe_slow );
10621 %}
10622
10623 instruct tanXD_reg(regXD dst, eFlagsReg cr) %{
10624 predicate (UseSSE>=2);
10625 match(Set dst(TanD dst));
10626 effect(KILL cr); // Push_{Src|Result}XD() uses "{SUB|ADD} ESP,8"
10627 format %{ "DTAN $dst" %}
10628 ins_encode( Push_SrcXD(dst),
10629 Opcode(0xD9), Opcode(0xF2), // fptan
10630 Opcode(0xDD), Opcode(0xD8), // fstp st
10631 Push_ResultXD(dst) );
10632 ins_pipe( pipe_slow );
10633 %}
10634
10635 instruct atanD_reg(regD dst, regD src) %{
10636 predicate (UseSSE<=1);
10637 match(Set dst(AtanD dst src));
10638 format %{ "DATA $dst,$src" %}
10639 opcode(0xD9, 0xF3);
10640 ins_encode( Push_Reg_D(src),
10641 OpcP, OpcS, RegOpc(dst) );
10642 ins_pipe( pipe_slow );
10643 %}
10644
10645 instruct atanXD_reg(regXD dst, regXD src, eFlagsReg cr) %{
10646 predicate (UseSSE>=2);
10647 match(Set dst(AtanD dst src));
10648 effect(KILL cr); // Push_{Src|Result}XD() uses "{SUB|ADD} ESP,8"
10649 format %{ "DATA $dst,$src" %}
10650 opcode(0xD9, 0xF3);
10651 ins_encode( Push_SrcXD(src),
10652 OpcP, OpcS, Push_ResultXD(dst) );
10653 ins_pipe( pipe_slow );
10654 %}
10655
10656 instruct sqrtD_reg(regD dst, regD src) %{
10657 predicate (UseSSE<=1);
10658 match(Set dst (SqrtD src));
10659 format %{ "DSQRT $dst,$src" %}
10660 opcode(0xFA, 0xD9);
10661 ins_encode( Push_Reg_D(src),
10662 OpcS, OpcP, Pop_Reg_D(dst) );
10663 ins_pipe( pipe_slow );
10664 %}
10665
10666 instruct powD_reg(regD X, regDPR1 Y, eAXRegI rax, eBXRegI rbx, eCXRegI rcx) %{
10667 predicate (UseSSE<=1);
10668 match(Set Y (PowD X Y)); // Raise X to the Yth power
10669 effect(KILL rax, KILL rbx, KILL rcx);
10670 format %{ "SUB ESP,8\t\t# Fast-path POW encoding\n\t"
10671 "FLD_D $X\n\t"
10672 "FYL2X \t\t\t# Q=Y*ln2(X)\n\t"
10673
10674 "FDUP \t\t\t# Q Q\n\t"
10675 "FRNDINT\t\t\t# int(Q) Q\n\t"
10676 "FSUB ST(1),ST(0)\t# int(Q) frac(Q)\n\t"
10677 "FISTP dword [ESP]\n\t"
10678 "F2XM1 \t\t\t# 2^frac(Q)-1 int(Q)\n\t"
10679 "FLD1 \t\t\t# 1 2^frac(Q)-1 int(Q)\n\t"
10680 "FADDP \t\t\t# 2^frac(Q) int(Q)\n\t" // could use FADD [1.000] instead
10681 "MOV EAX,[ESP]\t# Pick up int(Q)\n\t"
10682 "MOV ECX,0xFFFFF800\t# Overflow mask\n\t"
10683 "ADD EAX,1023\t\t# Double exponent bias\n\t"
10684 "MOV EBX,EAX\t\t# Preshifted biased expo\n\t"
10685 "SHL EAX,20\t\t# Shift exponent into place\n\t"
10686 "TEST EBX,ECX\t\t# Check for overflow\n\t"
10687 "CMOVne EAX,ECX\t\t# If overflow, stuff NaN into EAX\n\t"
10688 "MOV [ESP+4],EAX\t# Marshal 64-bit scaling double\n\t"
10689 "MOV [ESP+0],0\n\t"
10690 "FMUL ST(0),[ESP+0]\t# Scale\n\t"
10691
10692 "ADD ESP,8"
10693 %}
10694 ins_encode( push_stack_temp_qword,
10695 Push_Reg_D(X),
10696 Opcode(0xD9), Opcode(0xF1), // fyl2x
10697 pow_exp_core_encoding,
10698 pop_stack_temp_qword);
10699 ins_pipe( pipe_slow );
10700 %}
10701
10702 instruct powXD_reg(regXD dst, regXD src0, regXD src1, regDPR1 tmp1, eAXRegI rax, eBXRegI rbx, eCXRegI rcx ) %{
10703 predicate (UseSSE>=2);
10704 match(Set dst (PowD src0 src1)); // Raise src0 to the src1'th power
10705 effect(KILL tmp1, KILL rax, KILL rbx, KILL rcx );
10706 format %{ "SUB ESP,8\t\t# Fast-path POW encoding\n\t"
10707 "MOVSD [ESP],$src1\n\t"
10708 "FLD FPR1,$src1\n\t"
10709 "MOVSD [ESP],$src0\n\t"
10710 "FLD FPR1,$src0\n\t"
10711 "FYL2X \t\t\t# Q=Y*ln2(X)\n\t"
10712
10713 "FDUP \t\t\t# Q Q\n\t"
10714 "FRNDINT\t\t\t# int(Q) Q\n\t"
10715 "FSUB ST(1),ST(0)\t# int(Q) frac(Q)\n\t"
10716 "FISTP dword [ESP]\n\t"
10717 "F2XM1 \t\t\t# 2^frac(Q)-1 int(Q)\n\t"
10718 "FLD1 \t\t\t# 1 2^frac(Q)-1 int(Q)\n\t"
10719 "FADDP \t\t\t# 2^frac(Q) int(Q)\n\t" // could use FADD [1.000] instead
10720 "MOV EAX,[ESP]\t# Pick up int(Q)\n\t"
10721 "MOV ECX,0xFFFFF800\t# Overflow mask\n\t"
10722 "ADD EAX,1023\t\t# Double exponent bias\n\t"
10723 "MOV EBX,EAX\t\t# Preshifted biased expo\n\t"
10724 "SHL EAX,20\t\t# Shift exponent into place\n\t"
10725 "TEST EBX,ECX\t\t# Check for overflow\n\t"
10726 "CMOVne EAX,ECX\t\t# If overflow, stuff NaN into EAX\n\t"
10727 "MOV [ESP+4],EAX\t# Marshal 64-bit scaling double\n\t"
10728 "MOV [ESP+0],0\n\t"
10729 "FMUL ST(0),[ESP+0]\t# Scale\n\t"
10730
10731 "FST_D [ESP]\n\t"
10732 "MOVSD $dst,[ESP]\n\t"
10733 "ADD ESP,8"
10734 %}
10735 ins_encode( push_stack_temp_qword,
10736 push_xmm_to_fpr1(src1),
10737 push_xmm_to_fpr1(src0),
10738 Opcode(0xD9), Opcode(0xF1), // fyl2x
10739 pow_exp_core_encoding,
10740 Push_ResultXD(dst) );
10741 ins_pipe( pipe_slow );
10742 %}
10743
10744
10745 instruct expD_reg(regDPR1 dpr1, eAXRegI rax, eBXRegI rbx, eCXRegI rcx) %{
10746 predicate (UseSSE<=1);
10747 match(Set dpr1 (ExpD dpr1));
10748 effect(KILL rax, KILL rbx, KILL rcx);
10749 format %{ "SUB ESP,8\t\t# Fast-path EXP encoding"
10750 "FLDL2E \t\t\t# Ld log2(e) X\n\t"
10751 "FMULP \t\t\t# Q=X*log2(e)\n\t"
10752
10753 "FDUP \t\t\t# Q Q\n\t"
10754 "FRNDINT\t\t\t# int(Q) Q\n\t"
10755 "FSUB ST(1),ST(0)\t# int(Q) frac(Q)\n\t"
10756 "FISTP dword [ESP]\n\t"
10757 "F2XM1 \t\t\t# 2^frac(Q)-1 int(Q)\n\t"
10758 "FLD1 \t\t\t# 1 2^frac(Q)-1 int(Q)\n\t"
10759 "FADDP \t\t\t# 2^frac(Q) int(Q)\n\t" // could use FADD [1.000] instead
10760 "MOV EAX,[ESP]\t# Pick up int(Q)\n\t"
10761 "MOV ECX,0xFFFFF800\t# Overflow mask\n\t"
10762 "ADD EAX,1023\t\t# Double exponent bias\n\t"
10763 "MOV EBX,EAX\t\t# Preshifted biased expo\n\t"
10764 "SHL EAX,20\t\t# Shift exponent into place\n\t"
10765 "TEST EBX,ECX\t\t# Check for overflow\n\t"
10766 "CMOVne EAX,ECX\t\t# If overflow, stuff NaN into EAX\n\t"
10767 "MOV [ESP+4],EAX\t# Marshal 64-bit scaling double\n\t"
10768 "MOV [ESP+0],0\n\t"
10769 "FMUL ST(0),[ESP+0]\t# Scale\n\t"
10770
10771 "ADD ESP,8"
10772 %}
10773 ins_encode( push_stack_temp_qword,
10774 Opcode(0xD9), Opcode(0xEA), // fldl2e
10775 Opcode(0xDE), Opcode(0xC9), // fmulp
10776 pow_exp_core_encoding,
10777 pop_stack_temp_qword);
10778 ins_pipe( pipe_slow );
10779 %}
10780
10781 instruct expXD_reg(regXD dst, regXD src, regDPR1 tmp1, eAXRegI rax, eBXRegI rbx, eCXRegI rcx) %{
10782 predicate (UseSSE>=2);
10783 match(Set dst (ExpD src));
10784 effect(KILL tmp1, KILL rax, KILL rbx, KILL rcx);
10785 format %{ "SUB ESP,8\t\t# Fast-path EXP encoding\n\t"
10786 "MOVSD [ESP],$src\n\t"
10787 "FLDL2E \t\t\t# Ld log2(e) X\n\t"
10788 "FMULP \t\t\t# Q=X*log2(e) X\n\t"
10789
10790 "FDUP \t\t\t# Q Q\n\t"
10791 "FRNDINT\t\t\t# int(Q) Q\n\t"
10792 "FSUB ST(1),ST(0)\t# int(Q) frac(Q)\n\t"
10793 "FISTP dword [ESP]\n\t"
10794 "F2XM1 \t\t\t# 2^frac(Q)-1 int(Q)\n\t"
10795 "FLD1 \t\t\t# 1 2^frac(Q)-1 int(Q)\n\t"
10796 "FADDP \t\t\t# 2^frac(Q) int(Q)\n\t" // could use FADD [1.000] instead
10797 "MOV EAX,[ESP]\t# Pick up int(Q)\n\t"
10798 "MOV ECX,0xFFFFF800\t# Overflow mask\n\t"
10799 "ADD EAX,1023\t\t# Double exponent bias\n\t"
10800 "MOV EBX,EAX\t\t# Preshifted biased expo\n\t"
10801 "SHL EAX,20\t\t# Shift exponent into place\n\t"
10802 "TEST EBX,ECX\t\t# Check for overflow\n\t"
10803 "CMOVne EAX,ECX\t\t# If overflow, stuff NaN into EAX\n\t"
10804 "MOV [ESP+4],EAX\t# Marshal 64-bit scaling double\n\t"
10805 "MOV [ESP+0],0\n\t"
10806 "FMUL ST(0),[ESP+0]\t# Scale\n\t"
10807
10808 "FST_D [ESP]\n\t"
10809 "MOVSD $dst,[ESP]\n\t"
10810 "ADD ESP,8"
10811 %}
10812 ins_encode( Push_SrcXD(src),
10813 Opcode(0xD9), Opcode(0xEA), // fldl2e
10814 Opcode(0xDE), Opcode(0xC9), // fmulp
10815 pow_exp_core_encoding,
10816 Push_ResultXD(dst) );
10817 ins_pipe( pipe_slow );
10818 %}
10819
10820
10821
10822 instruct log10D_reg(regDPR1 dst, regDPR1 src) %{
10823 predicate (UseSSE<=1);
10824 // The source Double operand on FPU stack
10825 match(Set dst (Log10D src));
10826 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number
10827 // fxch ; swap ST(0) with ST(1)
10828 // fyl2x ; compute log_10(2) * log_2(x)
10829 format %{ "FLDLG2 \t\t\t#Log10\n\t"
10830 "FXCH \n\t"
10831 "FYL2X \t\t\t# Q=Log10*Log_2(x)"
10832 %}
10833 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2
10834 Opcode(0xD9), Opcode(0xC9), // fxch
10835 Opcode(0xD9), Opcode(0xF1)); // fyl2x
10836
10837 ins_pipe( pipe_slow );
10838 %}
10839
10840 instruct log10XD_reg(regXD dst, regXD src, eFlagsReg cr) %{
10841 predicate (UseSSE>=2);
10842 effect(KILL cr);
10843 match(Set dst (Log10D src));
10844 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number
10845 // fyl2x ; compute log_10(2) * log_2(x)
10846 format %{ "FLDLG2 \t\t\t#Log10\n\t"
10847 "FYL2X \t\t\t# Q=Log10*Log_2(x)"
10848 %}
10849 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2
10850 Push_SrcXD(src),
10851 Opcode(0xD9), Opcode(0xF1), // fyl2x
10852 Push_ResultXD(dst));
10853
10854 ins_pipe( pipe_slow );
10855 %}
10856
10857 instruct logD_reg(regDPR1 dst, regDPR1 src) %{
10858 predicate (UseSSE<=1);
10859 // The source Double operand on FPU stack
10860 match(Set dst (LogD src));
10861 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number
10862 // fxch ; swap ST(0) with ST(1)
10863 // fyl2x ; compute log_e(2) * log_2(x)
10864 format %{ "FLDLN2 \t\t\t#Log_e\n\t"
10865 "FXCH \n\t"
10866 "FYL2X \t\t\t# Q=Log_e*Log_2(x)"
10867 %}
10868 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2
10869 Opcode(0xD9), Opcode(0xC9), // fxch
10870 Opcode(0xD9), Opcode(0xF1)); // fyl2x
10871
10872 ins_pipe( pipe_slow );
10873 %}
10874
10875 instruct logXD_reg(regXD dst, regXD src, eFlagsReg cr) %{
10876 predicate (UseSSE>=2);
10877 effect(KILL cr);
10878 // The source and result Double operands in XMM registers
10879 match(Set dst (LogD src));
10880 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number
10881 // fyl2x ; compute log_e(2) * log_2(x)
10882 format %{ "FLDLN2 \t\t\t#Log_e\n\t"
10883 "FYL2X \t\t\t# Q=Log_e*Log_2(x)"
10884 %}
10885 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2
10886 Push_SrcXD(src),
10887 Opcode(0xD9), Opcode(0xF1), // fyl2x
10888 Push_ResultXD(dst));
10889 ins_pipe( pipe_slow );
10890 %}
10891
10892 //-------------Float Instructions-------------------------------
10893 // Float Math
10894
10895 // Code for float compare:
10896 // fcompp();
10897 // fwait(); fnstsw_ax();
10898 // sahf();
10899 // movl(dst, unordered_result);
10900 // jcc(Assembler::parity, exit);
10901 // movl(dst, less_result);
10902 // jcc(Assembler::below, exit);
10903 // movl(dst, equal_result);
10904 // jcc(Assembler::equal, exit);
10905 // movl(dst, greater_result);
10906 // exit:
10907
10908 // P6 version of float compare, sets condition codes in EFLAGS
10909 instruct cmpF_cc_P6(eFlagsRegU cr, regF src1, regF src2, eAXRegI rax) %{
10910 predicate(VM_Version::supports_cmov() && UseSSE == 0);
10911 match(Set cr (CmpF src1 src2));
10912 effect(KILL rax);
10913 ins_cost(150);
10914 format %{ "FLD $src1\n\t"
10915 "FUCOMIP ST,$src2 // P6 instruction\n\t"
10916 "JNP exit\n\t"
10917 "MOV ah,1 // saw a NaN, set CF (treat as LT)\n\t"
10918 "SAHF\n"
10919 "exit:\tNOP // avoid branch to branch" %}
10920 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
10921 ins_encode( Push_Reg_D(src1),
10922 OpcP, RegOpc(src2),
10923 cmpF_P6_fixup );
10924 ins_pipe( pipe_slow );
10925 %}
10926
10927 instruct cmpF_cc_P6CF(eFlagsRegUCF cr, regF src1, regF src2) %{
10928 predicate(VM_Version::supports_cmov() && UseSSE == 0);
10929 match(Set cr (CmpF src1 src2));
10930 ins_cost(100);
10931 format %{ "FLD $src1\n\t"
10932 "FUCOMIP ST,$src2 // P6 instruction" %}
10933 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
10934 ins_encode( Push_Reg_D(src1),
10935 OpcP, RegOpc(src2));
10936 ins_pipe( pipe_slow );
10937 %}
10938
10939
10940 // Compare & branch
10941 instruct cmpF_cc(eFlagsRegU cr, regF src1, regF src2, eAXRegI rax) %{
10942 predicate(UseSSE == 0);
10943 match(Set cr (CmpF src1 src2));
10944 effect(KILL rax);
10945 ins_cost(200);
10946 format %{ "FLD $src1\n\t"
10947 "FCOMp $src2\n\t"
10948 "FNSTSW AX\n\t"
10949 "TEST AX,0x400\n\t"
10950 "JZ,s flags\n\t"
10951 "MOV AH,1\t# unordered treat as LT\n"
10952 "flags:\tSAHF" %}
10953 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
10954 ins_encode( Push_Reg_D(src1),
10955 OpcP, RegOpc(src2),
10956 fpu_flags);
10957 ins_pipe( pipe_slow );
10958 %}
10959
10960 // Compare vs zero into -1,0,1
10961 instruct cmpF_0(eRegI dst, regF src1, immF0 zero, eAXRegI rax, eFlagsReg cr) %{
10962 predicate(UseSSE == 0);
10963 match(Set dst (CmpF3 src1 zero));
10964 effect(KILL cr, KILL rax);
10965 ins_cost(280);
10966 format %{ "FTSTF $dst,$src1" %}
10967 opcode(0xE4, 0xD9);
10968 ins_encode( Push_Reg_D(src1),
10969 OpcS, OpcP, PopFPU,
10970 CmpF_Result(dst));
10971 ins_pipe( pipe_slow );
10972 %}
10973
10974 // Compare into -1,0,1
10975 instruct cmpF_reg(eRegI dst, regF src1, regF src2, eAXRegI rax, eFlagsReg cr) %{
10976 predicate(UseSSE == 0);
10977 match(Set dst (CmpF3 src1 src2));
10978 effect(KILL cr, KILL rax);
10979 ins_cost(300);
10980 format %{ "FCMPF $dst,$src1,$src2" %}
10981 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
10982 ins_encode( Push_Reg_D(src1),
10983 OpcP, RegOpc(src2),
10984 CmpF_Result(dst));
10985 ins_pipe( pipe_slow );
10986 %}
10987
10988 // float compare and set condition codes in EFLAGS by XMM regs
10989 instruct cmpX_cc(eFlagsRegU cr, regX dst, regX src, eAXRegI rax) %{
10990 predicate(UseSSE>=1);
10991 match(Set cr (CmpF dst src));
10992 effect(KILL rax);
10993 ins_cost(145);
10994 format %{ "COMISS $dst,$src\n"
10995 "\tJNP exit\n"
10996 "\tMOV ah,1 // saw a NaN, set CF\n"
10997 "\tSAHF\n"
10998 "exit:\tNOP // avoid branch to branch" %}
10999 opcode(0x0F, 0x2F);
11000 ins_encode(OpcP, OpcS, RegReg(dst, src), cmpF_P6_fixup);
11001 ins_pipe( pipe_slow );
11002 %}
11003
11004 instruct cmpX_ccCF(eFlagsRegUCF cr, regX dst, regX src) %{
11005 predicate(UseSSE>=1);
11006 match(Set cr (CmpF dst src));
11007 ins_cost(100);
11008 format %{ "COMISS $dst,$src" %}
11009 opcode(0x0F, 0x2F);
11010 ins_encode(OpcP, OpcS, RegReg(dst, src));
11011 ins_pipe( pipe_slow );
11012 %}
11013
11014 // float compare and set condition codes in EFLAGS by XMM regs
11015 instruct cmpX_ccmem(eFlagsRegU cr, regX dst, memory src, eAXRegI rax) %{
11016 predicate(UseSSE>=1);
11017 match(Set cr (CmpF dst (LoadF src)));
11018 effect(KILL rax);
11019 ins_cost(165);
11020 format %{ "COMISS $dst,$src\n"
11021 "\tJNP exit\n"
11022 "\tMOV ah,1 // saw a NaN, set CF\n"
11023 "\tSAHF\n"
11024 "exit:\tNOP // avoid branch to branch" %}
11025 opcode(0x0F, 0x2F);
11026 ins_encode(OpcP, OpcS, RegMem(dst, src), cmpF_P6_fixup);
11027 ins_pipe( pipe_slow );
11028 %}
11029
11030 instruct cmpX_ccmemCF(eFlagsRegUCF cr, regX dst, memory src) %{
11031 predicate(UseSSE>=1);
11032 match(Set cr (CmpF dst (LoadF src)));
11033 ins_cost(100);
11034 format %{ "COMISS $dst,$src" %}
11035 opcode(0x0F, 0x2F);
11036 ins_encode(OpcP, OpcS, RegMem(dst, src));
11037 ins_pipe( pipe_slow );
11038 %}
11039
11040 // Compare into -1,0,1 in XMM
11041 instruct cmpX_reg(eRegI dst, regX src1, regX src2, eFlagsReg cr) %{
11042 predicate(UseSSE>=1);
11043 match(Set dst (CmpF3 src1 src2));
11044 effect(KILL cr);
11045 ins_cost(255);
11046 format %{ "XOR $dst,$dst\n"
11047 "\tCOMISS $src1,$src2\n"
11048 "\tJP,s nan\n"
11049 "\tJEQ,s exit\n"
11050 "\tJA,s inc\n"
11051 "nan:\tDEC $dst\n"
11052 "\tJMP,s exit\n"
11053 "inc:\tINC $dst\n"
11054 "exit:"
11055 %}
11056 opcode(0x0F, 0x2F);
11057 ins_encode(Xor_Reg(dst), OpcP, OpcS, RegReg(src1, src2), CmpX_Result(dst));
11058 ins_pipe( pipe_slow );
11059 %}
11060
11061 // Compare into -1,0,1 in XMM and memory
11062 instruct cmpX_regmem(eRegI dst, regX src1, memory mem, eFlagsReg cr) %{
11063 predicate(UseSSE>=1);
11064 match(Set dst (CmpF3 src1 (LoadF mem)));
11065 effect(KILL cr);
11066 ins_cost(275);
11067 format %{ "COMISS $src1,$mem\n"
11068 "\tMOV $dst,0\t\t# do not blow flags\n"
11069 "\tJP,s nan\n"
11070 "\tJEQ,s exit\n"
11071 "\tJA,s inc\n"
11072 "nan:\tDEC $dst\n"
11073 "\tJMP,s exit\n"
11074 "inc:\tINC $dst\n"
11075 "exit:"
11076 %}
11077 opcode(0x0F, 0x2F);
11078 ins_encode(OpcP, OpcS, RegMem(src1, mem), LdImmI(dst,0x0), CmpX_Result(dst));
11079 ins_pipe( pipe_slow );
11080 %}
11081
11082 // Spill to obtain 24-bit precision
11083 instruct subF24_reg(stackSlotF dst, regF src1, regF src2) %{
11084 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11085 match(Set dst (SubF src1 src2));
11086
11087 format %{ "FSUB $dst,$src1 - $src2" %}
11088 opcode(0xD8, 0x4); /* D8 E0+i or D8 /4 mod==0x3 ;; result in TOS */
11089 ins_encode( Push_Reg_F(src1),
11090 OpcReg_F(src2),
11091 Pop_Mem_F(dst) );
11092 ins_pipe( fpu_mem_reg_reg );
11093 %}
11094 //
11095 // This instruction does not round to 24-bits
11096 instruct subF_reg(regF dst, regF src) %{
11097 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11098 match(Set dst (SubF dst src));
11099
11100 format %{ "FSUB $dst,$src" %}
11101 opcode(0xDE, 0x5); /* DE E8+i or DE /5 */
11102 ins_encode( Push_Reg_F(src),
11103 OpcP, RegOpc(dst) );
11104 ins_pipe( fpu_reg_reg );
11105 %}
11106
11107 // Spill to obtain 24-bit precision
11108 instruct addF24_reg(stackSlotF dst, regF src1, regF src2) %{
11109 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11110 match(Set dst (AddF src1 src2));
11111
11112 format %{ "FADD $dst,$src1,$src2" %}
11113 opcode(0xD8, 0x0); /* D8 C0+i */
11114 ins_encode( Push_Reg_F(src2),
11115 OpcReg_F(src1),
11116 Pop_Mem_F(dst) );
11117 ins_pipe( fpu_mem_reg_reg );
11118 %}
11119 //
11120 // This instruction does not round to 24-bits
11121 instruct addF_reg(regF dst, regF src) %{
11122 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11123 match(Set dst (AddF dst src));
11124
11125 format %{ "FLD $src\n\t"
11126 "FADDp $dst,ST" %}
11127 opcode(0xDE, 0x0); /* DE C0+i or DE /0*/
11128 ins_encode( Push_Reg_F(src),
11129 OpcP, RegOpc(dst) );
11130 ins_pipe( fpu_reg_reg );
11131 %}
11132
11133 // Add two single precision floating point values in xmm
11134 instruct addX_reg(regX dst, regX src) %{
11135 predicate(UseSSE>=1);
11136 match(Set dst (AddF dst src));
11137 format %{ "ADDSS $dst,$src" %}
11138 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x58), RegReg(dst, src));
11139 ins_pipe( pipe_slow );
11140 %}
11141
11142 instruct addX_imm(regX dst, immXF con) %{
11143 predicate(UseSSE>=1);
11144 match(Set dst (AddF dst con));
11145 format %{ "ADDSS $dst,[$con]" %}
11146 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x58), LdImmX(dst, con) );
11147 ins_pipe( pipe_slow );
11148 %}
11149
11150 instruct addX_mem(regX dst, memory mem) %{
11151 predicate(UseSSE>=1);
11152 match(Set dst (AddF dst (LoadF mem)));
11153 format %{ "ADDSS $dst,$mem" %}
11154 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x58), RegMem(dst, mem));
11155 ins_pipe( pipe_slow );
11156 %}
11157
11158 // Subtract two single precision floating point values in xmm
11159 instruct subX_reg(regX dst, regX src) %{
11160 predicate(UseSSE>=1);
11161 match(Set dst (SubF dst src));
11162 format %{ "SUBSS $dst,$src" %}
11163 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5C), RegReg(dst, src));
11164 ins_pipe( pipe_slow );
11165 %}
11166
11167 instruct subX_imm(regX dst, immXF con) %{
11168 predicate(UseSSE>=1);
11169 match(Set dst (SubF dst con));
11170 format %{ "SUBSS $dst,[$con]" %}
11171 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5C), LdImmX(dst, con) );
11172 ins_pipe( pipe_slow );
11173 %}
11174
11175 instruct subX_mem(regX dst, memory mem) %{
11176 predicate(UseSSE>=1);
11177 match(Set dst (SubF dst (LoadF mem)));
11178 format %{ "SUBSS $dst,$mem" %}
11179 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5C), RegMem(dst,mem));
11180 ins_pipe( pipe_slow );
11181 %}
11182
11183 // Multiply two single precision floating point values in xmm
11184 instruct mulX_reg(regX dst, regX src) %{
11185 predicate(UseSSE>=1);
11186 match(Set dst (MulF dst src));
11187 format %{ "MULSS $dst,$src" %}
11188 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x59), RegReg(dst, src));
11189 ins_pipe( pipe_slow );
11190 %}
11191
11192 instruct mulX_imm(regX dst, immXF con) %{
11193 predicate(UseSSE>=1);
11194 match(Set dst (MulF dst con));
11195 format %{ "MULSS $dst,[$con]" %}
11196 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x59), LdImmX(dst, con) );
11197 ins_pipe( pipe_slow );
11198 %}
11199
11200 instruct mulX_mem(regX dst, memory mem) %{
11201 predicate(UseSSE>=1);
11202 match(Set dst (MulF dst (LoadF mem)));
11203 format %{ "MULSS $dst,$mem" %}
11204 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x59), RegMem(dst,mem));
11205 ins_pipe( pipe_slow );
11206 %}
11207
11208 // Divide two single precision floating point values in xmm
11209 instruct divX_reg(regX dst, regX src) %{
11210 predicate(UseSSE>=1);
11211 match(Set dst (DivF dst src));
11212 format %{ "DIVSS $dst,$src" %}
11213 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5E), RegReg(dst, src));
11214 ins_pipe( pipe_slow );
11215 %}
11216
11217 instruct divX_imm(regX dst, immXF con) %{
11218 predicate(UseSSE>=1);
11219 match(Set dst (DivF dst con));
11220 format %{ "DIVSS $dst,[$con]" %}
11221 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5E), LdImmX(dst, con) );
11222 ins_pipe( pipe_slow );
11223 %}
11224
11225 instruct divX_mem(regX dst, memory mem) %{
11226 predicate(UseSSE>=1);
11227 match(Set dst (DivF dst (LoadF mem)));
11228 format %{ "DIVSS $dst,$mem" %}
11229 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5E), RegMem(dst,mem));
11230 ins_pipe( pipe_slow );
11231 %}
11232
11233 // Get the square root of a single precision floating point values in xmm
11234 instruct sqrtX_reg(regX dst, regX src) %{
11235 predicate(UseSSE>=1);
11236 match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
11237 format %{ "SQRTSS $dst,$src" %}
11238 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x51), RegReg(dst, src));
11239 ins_pipe( pipe_slow );
11240 %}
11241
11242 instruct sqrtX_mem(regX dst, memory mem) %{
11243 predicate(UseSSE>=1);
11244 match(Set dst (ConvD2F (SqrtD (ConvF2D (LoadF mem)))));
11245 format %{ "SQRTSS $dst,$mem" %}
11246 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x51), RegMem(dst, mem));
11247 ins_pipe( pipe_slow );
11248 %}
11249
11250 // Get the square root of a double precision floating point values in xmm
11251 instruct sqrtXD_reg(regXD dst, regXD src) %{
11252 predicate(UseSSE>=2);
11253 match(Set dst (SqrtD src));
11254 format %{ "SQRTSD $dst,$src" %}
11255 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x51), RegReg(dst, src));
11256 ins_pipe( pipe_slow );
11257 %}
11258
11259 instruct sqrtXD_mem(regXD dst, memory mem) %{
11260 predicate(UseSSE>=2);
11261 match(Set dst (SqrtD (LoadD mem)));
11262 format %{ "SQRTSD $dst,$mem" %}
11263 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x51), RegMem(dst, mem));
11264 ins_pipe( pipe_slow );
11265 %}
11266
11267 instruct absF_reg(regFPR1 dst, regFPR1 src) %{
11268 predicate(UseSSE==0);
11269 match(Set dst (AbsF src));
11270 ins_cost(100);
11271 format %{ "FABS" %}
11272 opcode(0xE1, 0xD9);
11273 ins_encode( OpcS, OpcP );
11274 ins_pipe( fpu_reg_reg );
11275 %}
11276
11277 instruct absX_reg(regX dst ) %{
11278 predicate(UseSSE>=1);
11279 match(Set dst (AbsF dst));
11280 format %{ "ANDPS $dst,[0x7FFFFFFF]\t# ABS F by sign masking" %}
11281 ins_encode( AbsXF_encoding(dst));
11282 ins_pipe( pipe_slow );
11283 %}
11284
11285 instruct negF_reg(regFPR1 dst, regFPR1 src) %{
11286 predicate(UseSSE==0);
11287 match(Set dst (NegF src));
11288 ins_cost(100);
11289 format %{ "FCHS" %}
11290 opcode(0xE0, 0xD9);
11291 ins_encode( OpcS, OpcP );
11292 ins_pipe( fpu_reg_reg );
11293 %}
11294
11295 instruct negX_reg( regX dst ) %{
11296 predicate(UseSSE>=1);
11297 match(Set dst (NegF dst));
11298 format %{ "XORPS $dst,[0x80000000]\t# CHS F by sign flipping" %}
11299 ins_encode( NegXF_encoding(dst));
11300 ins_pipe( pipe_slow );
11301 %}
11302
11303 // Cisc-alternate to addF_reg
11304 // Spill to obtain 24-bit precision
11305 instruct addF24_reg_mem(stackSlotF dst, regF src1, memory src2) %{
11306 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11307 match(Set dst (AddF src1 (LoadF src2)));
11308
11309 format %{ "FLD $src2\n\t"
11310 "FADD ST,$src1\n\t"
11311 "FSTP_S $dst" %}
11312 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
11313 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
11314 OpcReg_F(src1),
11315 Pop_Mem_F(dst) );
11316 ins_pipe( fpu_mem_reg_mem );
11317 %}
11318 //
11319 // Cisc-alternate to addF_reg
11320 // This instruction does not round to 24-bits
11321 instruct addF_reg_mem(regF dst, memory src) %{
11322 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11323 match(Set dst (AddF dst (LoadF src)));
11324
11325 format %{ "FADD $dst,$src" %}
11326 opcode(0xDE, 0x0, 0xD9); /* DE C0+i or DE /0*/ /* LoadF D9 /0 */
11327 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
11328 OpcP, RegOpc(dst) );
11329 ins_pipe( fpu_reg_mem );
11330 %}
11331
11332 // // Following two instructions for _222_mpegaudio
11333 // Spill to obtain 24-bit precision
11334 instruct addF24_mem_reg(stackSlotF dst, regF src2, memory src1 ) %{
11335 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11336 match(Set dst (AddF src1 src2));
11337
11338 format %{ "FADD $dst,$src1,$src2" %}
11339 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
11340 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src1),
11341 OpcReg_F(src2),
11342 Pop_Mem_F(dst) );
11343 ins_pipe( fpu_mem_reg_mem );
11344 %}
11345
11346 // Cisc-spill variant
11347 // Spill to obtain 24-bit precision
11348 instruct addF24_mem_cisc(stackSlotF dst, memory src1, memory src2) %{
11349 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11350 match(Set dst (AddF src1 (LoadF src2)));
11351
11352 format %{ "FADD $dst,$src1,$src2 cisc" %}
11353 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
11354 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
11355 set_instruction_start,
11356 OpcP, RMopc_Mem(secondary,src1),
11357 Pop_Mem_F(dst) );
11358 ins_pipe( fpu_mem_mem_mem );
11359 %}
11360
11361 // Spill to obtain 24-bit precision
11362 instruct addF24_mem_mem(stackSlotF dst, memory src1, memory src2) %{
11363 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11364 match(Set dst (AddF src1 src2));
11365
11366 format %{ "FADD $dst,$src1,$src2" %}
11367 opcode(0xD8, 0x0, 0xD9); /* D8 /0 */ /* LoadF D9 /0 */
11368 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
11369 set_instruction_start,
11370 OpcP, RMopc_Mem(secondary,src1),
11371 Pop_Mem_F(dst) );
11372 ins_pipe( fpu_mem_mem_mem );
11373 %}
11374
11375
11376 // Spill to obtain 24-bit precision
11377 instruct addF24_reg_imm(stackSlotF dst, regF src1, immF src2) %{
11378 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11379 match(Set dst (AddF src1 src2));
11380 format %{ "FLD $src1\n\t"
11381 "FADD $src2\n\t"
11382 "FSTP_S $dst" %}
11383 opcode(0xD8, 0x00); /* D8 /0 */
11384 ins_encode( Push_Reg_F(src1),
11385 Opc_MemImm_F(src2),
11386 Pop_Mem_F(dst));
11387 ins_pipe( fpu_mem_reg_con );
11388 %}
11389 //
11390 // This instruction does not round to 24-bits
11391 instruct addF_reg_imm(regF dst, regF src1, immF src2) %{
11392 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11393 match(Set dst (AddF src1 src2));
11394 format %{ "FLD $src1\n\t"
11395 "FADD $src2\n\t"
11396 "FSTP_S $dst" %}
11397 opcode(0xD8, 0x00); /* D8 /0 */
11398 ins_encode( Push_Reg_F(src1),
11399 Opc_MemImm_F(src2),
11400 Pop_Reg_F(dst));
11401 ins_pipe( fpu_reg_reg_con );
11402 %}
11403
11404 // Spill to obtain 24-bit precision
11405 instruct mulF24_reg(stackSlotF dst, regF src1, regF src2) %{
11406 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11407 match(Set dst (MulF src1 src2));
11408
11409 format %{ "FLD $src1\n\t"
11410 "FMUL $src2\n\t"
11411 "FSTP_S $dst" %}
11412 opcode(0xD8, 0x1); /* D8 C8+i or D8 /1 ;; result in TOS */
11413 ins_encode( Push_Reg_F(src1),
11414 OpcReg_F(src2),
11415 Pop_Mem_F(dst) );
11416 ins_pipe( fpu_mem_reg_reg );
11417 %}
11418 //
11419 // This instruction does not round to 24-bits
11420 instruct mulF_reg(regF dst, regF src1, regF src2) %{
11421 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11422 match(Set dst (MulF src1 src2));
11423
11424 format %{ "FLD $src1\n\t"
11425 "FMUL $src2\n\t"
11426 "FSTP_S $dst" %}
11427 opcode(0xD8, 0x1); /* D8 C8+i */
11428 ins_encode( Push_Reg_F(src2),
11429 OpcReg_F(src1),
11430 Pop_Reg_F(dst) );
11431 ins_pipe( fpu_reg_reg_reg );
11432 %}
11433
11434
11435 // Spill to obtain 24-bit precision
11436 // Cisc-alternate to reg-reg multiply
11437 instruct mulF24_reg_mem(stackSlotF dst, regF src1, memory src2) %{
11438 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11439 match(Set dst (MulF src1 (LoadF src2)));
11440
11441 format %{ "FLD_S $src2\n\t"
11442 "FMUL $src1\n\t"
11443 "FSTP_S $dst" %}
11444 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or DE /1*/ /* LoadF D9 /0 */
11445 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
11446 OpcReg_F(src1),
11447 Pop_Mem_F(dst) );
11448 ins_pipe( fpu_mem_reg_mem );
11449 %}
11450 //
11451 // This instruction does not round to 24-bits
11452 // Cisc-alternate to reg-reg multiply
11453 instruct mulF_reg_mem(regF dst, regF src1, memory src2) %{
11454 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11455 match(Set dst (MulF src1 (LoadF src2)));
11456
11457 format %{ "FMUL $dst,$src1,$src2" %}
11458 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */ /* LoadF D9 /0 */
11459 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
11460 OpcReg_F(src1),
11461 Pop_Reg_F(dst) );
11462 ins_pipe( fpu_reg_reg_mem );
11463 %}
11464
11465 // Spill to obtain 24-bit precision
11466 instruct mulF24_mem_mem(stackSlotF dst, memory src1, memory src2) %{
11467 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11468 match(Set dst (MulF src1 src2));
11469
11470 format %{ "FMUL $dst,$src1,$src2" %}
11471 opcode(0xD8, 0x1, 0xD9); /* D8 /1 */ /* LoadF D9 /0 */
11472 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
11473 set_instruction_start,
11474 OpcP, RMopc_Mem(secondary,src1),
11475 Pop_Mem_F(dst) );
11476 ins_pipe( fpu_mem_mem_mem );
11477 %}
11478
11479 // Spill to obtain 24-bit precision
11480 instruct mulF24_reg_imm(stackSlotF dst, regF src1, immF src2) %{
11481 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11482 match(Set dst (MulF src1 src2));
11483
11484 format %{ "FMULc $dst,$src1,$src2" %}
11485 opcode(0xD8, 0x1); /* D8 /1*/
11486 ins_encode( Push_Reg_F(src1),
11487 Opc_MemImm_F(src2),
11488 Pop_Mem_F(dst));
11489 ins_pipe( fpu_mem_reg_con );
11490 %}
11491 //
11492 // This instruction does not round to 24-bits
11493 instruct mulF_reg_imm(regF dst, regF src1, immF src2) %{
11494 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11495 match(Set dst (MulF src1 src2));
11496
11497 format %{ "FMULc $dst. $src1, $src2" %}
11498 opcode(0xD8, 0x1); /* D8 /1*/
11499 ins_encode( Push_Reg_F(src1),
11500 Opc_MemImm_F(src2),
11501 Pop_Reg_F(dst));
11502 ins_pipe( fpu_reg_reg_con );
11503 %}
11504
11505
11506 //
11507 // MACRO1 -- subsume unshared load into mulF
11508 // This instruction does not round to 24-bits
11509 instruct mulF_reg_load1(regF dst, regF src, memory mem1 ) %{
11510 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11511 match(Set dst (MulF (LoadF mem1) src));
11512
11513 format %{ "FLD $mem1 ===MACRO1===\n\t"
11514 "FMUL ST,$src\n\t"
11515 "FSTP $dst" %}
11516 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or D8 /1 */ /* LoadF D9 /0 */
11517 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem1),
11518 OpcReg_F(src),
11519 Pop_Reg_F(dst) );
11520 ins_pipe( fpu_reg_reg_mem );
11521 %}
11522 //
11523 // MACRO2 -- addF a mulF which subsumed an unshared load
11524 // This instruction does not round to 24-bits
11525 instruct addF_mulF_reg_load1(regF dst, memory mem1, regF src1, regF src2) %{
11526 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11527 match(Set dst (AddF (MulF (LoadF mem1) src1) src2));
11528 ins_cost(95);
11529
11530 format %{ "FLD $mem1 ===MACRO2===\n\t"
11531 "FMUL ST,$src1 subsume mulF left load\n\t"
11532 "FADD ST,$src2\n\t"
11533 "FSTP $dst" %}
11534 opcode(0xD9); /* LoadF D9 /0 */
11535 ins_encode( OpcP, RMopc_Mem(0x00,mem1),
11536 FMul_ST_reg(src1),
11537 FAdd_ST_reg(src2),
11538 Pop_Reg_F(dst) );
11539 ins_pipe( fpu_reg_mem_reg_reg );
11540 %}
11541
11542 // MACRO3 -- addF a mulF
11543 // This instruction does not round to 24-bits. It is a '2-address'
11544 // instruction in that the result goes back to src2. This eliminates
11545 // a move from the macro; possibly the register allocator will have
11546 // to add it back (and maybe not).
11547 instruct addF_mulF_reg(regF src2, regF src1, regF src0) %{
11548 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11549 match(Set src2 (AddF (MulF src0 src1) src2));
11550
11551 format %{ "FLD $src0 ===MACRO3===\n\t"
11552 "FMUL ST,$src1\n\t"
11553 "FADDP $src2,ST" %}
11554 opcode(0xD9); /* LoadF D9 /0 */
11555 ins_encode( Push_Reg_F(src0),
11556 FMul_ST_reg(src1),
11557 FAddP_reg_ST(src2) );
11558 ins_pipe( fpu_reg_reg_reg );
11559 %}
11560
11561 // MACRO4 -- divF subF
11562 // This instruction does not round to 24-bits
11563 instruct subF_divF_reg(regF dst, regF src1, regF src2, regF src3) %{
11564 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11565 match(Set dst (DivF (SubF src2 src1) src3));
11566
11567 format %{ "FLD $src2 ===MACRO4===\n\t"
11568 "FSUB ST,$src1\n\t"
11569 "FDIV ST,$src3\n\t"
11570 "FSTP $dst" %}
11571 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
11572 ins_encode( Push_Reg_F(src2),
11573 subF_divF_encode(src1,src3),
11574 Pop_Reg_F(dst) );
11575 ins_pipe( fpu_reg_reg_reg_reg );
11576 %}
11577
11578 // Spill to obtain 24-bit precision
11579 instruct divF24_reg(stackSlotF dst, regF src1, regF src2) %{
11580 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11581 match(Set dst (DivF src1 src2));
11582
11583 format %{ "FDIV $dst,$src1,$src2" %}
11584 opcode(0xD8, 0x6); /* D8 F0+i or DE /6*/
11585 ins_encode( Push_Reg_F(src1),
11586 OpcReg_F(src2),
11587 Pop_Mem_F(dst) );
11588 ins_pipe( fpu_mem_reg_reg );
11589 %}
11590 //
11591 // This instruction does not round to 24-bits
11592 instruct divF_reg(regF dst, regF src) %{
11593 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11594 match(Set dst (DivF dst src));
11595
11596 format %{ "FDIV $dst,$src" %}
11597 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
11598 ins_encode( Push_Reg_F(src),
11599 OpcP, RegOpc(dst) );
11600 ins_pipe( fpu_reg_reg );
11601 %}
11602
11603
11604 // Spill to obtain 24-bit precision
11605 instruct modF24_reg(stackSlotF dst, regF src1, regF src2, eAXRegI rax, eFlagsReg cr) %{
11606 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
11607 match(Set dst (ModF src1 src2));
11608 effect(KILL rax, KILL cr); // emitModD() uses EAX and EFLAGS
11609
11610 format %{ "FMOD $dst,$src1,$src2" %}
11611 ins_encode( Push_Reg_Mod_D(src1, src2),
11612 emitModD(),
11613 Push_Result_Mod_D(src2),
11614 Pop_Mem_F(dst));
11615 ins_pipe( pipe_slow );
11616 %}
11617 //
11618 // This instruction does not round to 24-bits
11619 instruct modF_reg(regF dst, regF src, eAXRegI rax, eFlagsReg cr) %{
11620 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
11621 match(Set dst (ModF dst src));
11622 effect(KILL rax, KILL cr); // emitModD() uses EAX and EFLAGS
11623
11624 format %{ "FMOD $dst,$src" %}
11625 ins_encode(Push_Reg_Mod_D(dst, src),
11626 emitModD(),
11627 Push_Result_Mod_D(src),
11628 Pop_Reg_F(dst));
11629 ins_pipe( pipe_slow );
11630 %}
11631
11632 instruct modX_reg(regX dst, regX src0, regX src1, eAXRegI rax, eFlagsReg cr) %{
11633 predicate(UseSSE>=1);
11634 match(Set dst (ModF src0 src1));
11635 effect(KILL rax, KILL cr);
11636 format %{ "SUB ESP,4\t # FMOD\n"
11637 "\tMOVSS [ESP+0],$src1\n"
11638 "\tFLD_S [ESP+0]\n"
11639 "\tMOVSS [ESP+0],$src0\n"
11640 "\tFLD_S [ESP+0]\n"
11641 "loop:\tFPREM\n"
11642 "\tFWAIT\n"
11643 "\tFNSTSW AX\n"
11644 "\tSAHF\n"
11645 "\tJP loop\n"
11646 "\tFSTP_S [ESP+0]\n"
11647 "\tMOVSS $dst,[ESP+0]\n"
11648 "\tADD ESP,4\n"
11649 "\tFSTP ST0\t # Restore FPU Stack"
11650 %}
11651 ins_cost(250);
11652 ins_encode( Push_ModX_encoding(src0, src1), emitModD(), Push_ResultX(dst,0x4), PopFPU);
11653 ins_pipe( pipe_slow );
11654 %}
11655
11656
11657 //----------Arithmetic Conversion Instructions---------------------------------
11658 // The conversions operations are all Alpha sorted. Please keep it that way!
11659
11660 instruct roundFloat_mem_reg(stackSlotF dst, regF src) %{
11661 predicate(UseSSE==0);
11662 match(Set dst (RoundFloat src));
11663 ins_cost(125);
11664 format %{ "FST_S $dst,$src\t# F-round" %}
11665 ins_encode( Pop_Mem_Reg_F(dst, src) );
11666 ins_pipe( fpu_mem_reg );
11667 %}
11668
11669 instruct roundDouble_mem_reg(stackSlotD dst, regD src) %{
11670 predicate(UseSSE<=1);
11671 match(Set dst (RoundDouble src));
11672 ins_cost(125);
11673 format %{ "FST_D $dst,$src\t# D-round" %}
11674 ins_encode( Pop_Mem_Reg_D(dst, src) );
11675 ins_pipe( fpu_mem_reg );
11676 %}
11677
11678 // Force rounding to 24-bit precision and 6-bit exponent
11679 instruct convD2F_reg(stackSlotF dst, regD src) %{
11680 predicate(UseSSE==0);
11681 match(Set dst (ConvD2F src));
11682 format %{ "FST_S $dst,$src\t# F-round" %}
11683 expand %{
11684 roundFloat_mem_reg(dst,src);
11685 %}
11686 %}
11687
11688 // Force rounding to 24-bit precision and 6-bit exponent
11689 instruct convD2X_reg(regX dst, regD src, eFlagsReg cr) %{
11690 predicate(UseSSE==1);
11691 match(Set dst (ConvD2F src));
11692 effect( KILL cr );
11693 format %{ "SUB ESP,4\n\t"
11694 "FST_S [ESP],$src\t# F-round\n\t"
11695 "MOVSS $dst,[ESP]\n\t"
11696 "ADD ESP,4" %}
11697 ins_encode( D2X_encoding(dst, src) );
11698 ins_pipe( pipe_slow );
11699 %}
11700
11701 // Force rounding double precision to single precision
11702 instruct convXD2X_reg(regX dst, regXD src) %{
11703 predicate(UseSSE>=2);
11704 match(Set dst (ConvD2F src));
11705 format %{ "CVTSD2SS $dst,$src\t# F-round" %}
11706 opcode(0xF2, 0x0F, 0x5A);
11707 ins_encode( OpcP, OpcS, Opcode(tertiary), RegReg(dst, src));
11708 ins_pipe( pipe_slow );
11709 %}
11710
11711 instruct convF2D_reg_reg(regD dst, regF src) %{
11712 predicate(UseSSE==0);
11713 match(Set dst (ConvF2D src));
11714 format %{ "FST_S $dst,$src\t# D-round" %}
11715 ins_encode( Pop_Reg_Reg_D(dst, src));
11716 ins_pipe( fpu_reg_reg );
11717 %}
11718
11719 instruct convF2D_reg(stackSlotD dst, regF src) %{
11720 predicate(UseSSE==1);
11721 match(Set dst (ConvF2D src));
11722 format %{ "FST_D $dst,$src\t# D-round" %}
11723 expand %{
11724 roundDouble_mem_reg(dst,src);
11725 %}
11726 %}
11727
11728 instruct convX2D_reg(regD dst, regX src, eFlagsReg cr) %{
11729 predicate(UseSSE==1);
11730 match(Set dst (ConvF2D src));
11731 effect( KILL cr );
11732 format %{ "SUB ESP,4\n\t"
11733 "MOVSS [ESP] $src\n\t"
11734 "FLD_S [ESP]\n\t"
11735 "ADD ESP,4\n\t"
11736 "FSTP $dst\t# D-round" %}
11737 ins_encode( X2D_encoding(dst, src), Pop_Reg_D(dst));
11738 ins_pipe( pipe_slow );
11739 %}
11740
11741 instruct convX2XD_reg(regXD dst, regX src) %{
11742 predicate(UseSSE>=2);
11743 match(Set dst (ConvF2D src));
11744 format %{ "CVTSS2SD $dst,$src\t# D-round" %}
11745 opcode(0xF3, 0x0F, 0x5A);
11746 ins_encode( OpcP, OpcS, Opcode(tertiary), RegReg(dst, src));
11747 ins_pipe( pipe_slow );
11748 %}
11749
11750 // Convert a double to an int. If the double is a NAN, stuff a zero in instead.
11751 instruct convD2I_reg_reg( eAXRegI dst, eDXRegI tmp, regD src, eFlagsReg cr ) %{
11752 predicate(UseSSE<=1);
11753 match(Set dst (ConvD2I src));
11754 effect( KILL tmp, KILL cr );
11755 format %{ "FLD $src\t# Convert double to int \n\t"
11756 "FLDCW trunc mode\n\t"
11757 "SUB ESP,4\n\t"
11758 "FISTp [ESP + #0]\n\t"
11759 "FLDCW std/24-bit mode\n\t"
11760 "POP EAX\n\t"
11761 "CMP EAX,0x80000000\n\t"
11762 "JNE,s fast\n\t"
11763 "FLD_D $src\n\t"
11764 "CALL d2i_wrapper\n"
11765 "fast:" %}
11766 ins_encode( Push_Reg_D(src), D2I_encoding(src) );
11767 ins_pipe( pipe_slow );
11768 %}
11769
11770 // Convert a double to an int. If the double is a NAN, stuff a zero in instead.
11771 instruct convXD2I_reg_reg( eAXRegI dst, eDXRegI tmp, regXD src, eFlagsReg cr ) %{
11772 predicate(UseSSE>=2);
11773 match(Set dst (ConvD2I src));
11774 effect( KILL tmp, KILL cr );
11775 format %{ "CVTTSD2SI $dst, $src\n\t"
11776 "CMP $dst,0x80000000\n\t"
11777 "JNE,s fast\n\t"
11778 "SUB ESP, 8\n\t"
11779 "MOVSD [ESP], $src\n\t"
11780 "FLD_D [ESP]\n\t"
11781 "ADD ESP, 8\n\t"
11782 "CALL d2i_wrapper\n"
11783 "fast:" %}
11784 opcode(0x1); // double-precision conversion
11785 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x2C), FX2I_encoding(src,dst));
11786 ins_pipe( pipe_slow );
11787 %}
11788
11789 instruct convD2L_reg_reg( eADXRegL dst, regD src, eFlagsReg cr ) %{
11790 predicate(UseSSE<=1);
11791 match(Set dst (ConvD2L src));
11792 effect( KILL cr );
11793 format %{ "FLD $src\t# Convert double to long\n\t"
11794 "FLDCW trunc mode\n\t"
11795 "SUB ESP,8\n\t"
11796 "FISTp [ESP + #0]\n\t"
11797 "FLDCW std/24-bit mode\n\t"
11798 "POP EAX\n\t"
11799 "POP EDX\n\t"
11800 "CMP EDX,0x80000000\n\t"
11801 "JNE,s fast\n\t"
11802 "TEST EAX,EAX\n\t"
11803 "JNE,s fast\n\t"
11804 "FLD $src\n\t"
11805 "CALL d2l_wrapper\n"
11806 "fast:" %}
11807 ins_encode( Push_Reg_D(src), D2L_encoding(src) );
11808 ins_pipe( pipe_slow );
11809 %}
11810
11811 // XMM lacks a float/double->long conversion, so use the old FPU stack.
11812 instruct convXD2L_reg_reg( eADXRegL dst, regXD src, eFlagsReg cr ) %{
11813 predicate (UseSSE>=2);
11814 match(Set dst (ConvD2L src));
11815 effect( KILL cr );
11816 format %{ "SUB ESP,8\t# Convert double to long\n\t"
11817 "MOVSD [ESP],$src\n\t"
11818 "FLD_D [ESP]\n\t"
11819 "FLDCW trunc mode\n\t"
11820 "FISTp [ESP + #0]\n\t"
11821 "FLDCW std/24-bit mode\n\t"
11822 "POP EAX\n\t"
11823 "POP EDX\n\t"
11824 "CMP EDX,0x80000000\n\t"
11825 "JNE,s fast\n\t"
11826 "TEST EAX,EAX\n\t"
11827 "JNE,s fast\n\t"
11828 "SUB ESP,8\n\t"
11829 "MOVSD [ESP],$src\n\t"
11830 "FLD_D [ESP]\n\t"
11831 "CALL d2l_wrapper\n"
11832 "fast:" %}
11833 ins_encode( XD2L_encoding(src) );
11834 ins_pipe( pipe_slow );
11835 %}
11836
11837 // Convert a double to an int. Java semantics require we do complex
11838 // manglations in the corner cases. So we set the rounding mode to
11839 // 'zero', store the darned double down as an int, and reset the
11840 // rounding mode to 'nearest'. The hardware stores a flag value down
11841 // if we would overflow or converted a NAN; we check for this and
11842 // and go the slow path if needed.
11843 instruct convF2I_reg_reg(eAXRegI dst, eDXRegI tmp, regF src, eFlagsReg cr ) %{
11844 predicate(UseSSE==0);
11845 match(Set dst (ConvF2I src));
11846 effect( KILL tmp, KILL cr );
11847 format %{ "FLD $src\t# Convert float to int \n\t"
11848 "FLDCW trunc mode\n\t"
11849 "SUB ESP,4\n\t"
11850 "FISTp [ESP + #0]\n\t"
11851 "FLDCW std/24-bit mode\n\t"
11852 "POP EAX\n\t"
11853 "CMP EAX,0x80000000\n\t"
11854 "JNE,s fast\n\t"
11855 "FLD $src\n\t"
11856 "CALL d2i_wrapper\n"
11857 "fast:" %}
11858 // D2I_encoding works for F2I
11859 ins_encode( Push_Reg_F(src), D2I_encoding(src) );
11860 ins_pipe( pipe_slow );
11861 %}
11862
11863 // Convert a float in xmm to an int reg.
11864 instruct convX2I_reg(eAXRegI dst, eDXRegI tmp, regX src, eFlagsReg cr ) %{
11865 predicate(UseSSE>=1);
11866 match(Set dst (ConvF2I src));
11867 effect( KILL tmp, KILL cr );
11868 format %{ "CVTTSS2SI $dst, $src\n\t"
11869 "CMP $dst,0x80000000\n\t"
11870 "JNE,s fast\n\t"
11871 "SUB ESP, 4\n\t"
11872 "MOVSS [ESP], $src\n\t"
11873 "FLD [ESP]\n\t"
11874 "ADD ESP, 4\n\t"
11875 "CALL d2i_wrapper\n"
11876 "fast:" %}
11877 opcode(0x0); // single-precision conversion
11878 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x2C), FX2I_encoding(src,dst));
11879 ins_pipe( pipe_slow );
11880 %}
11881
11882 instruct convF2L_reg_reg( eADXRegL dst, regF src, eFlagsReg cr ) %{
11883 predicate(UseSSE==0);
11884 match(Set dst (ConvF2L src));
11885 effect( KILL cr );
11886 format %{ "FLD $src\t# Convert float to long\n\t"
11887 "FLDCW trunc mode\n\t"
11888 "SUB ESP,8\n\t"
11889 "FISTp [ESP + #0]\n\t"
11890 "FLDCW std/24-bit mode\n\t"
11891 "POP EAX\n\t"
11892 "POP EDX\n\t"
11893 "CMP EDX,0x80000000\n\t"
11894 "JNE,s fast\n\t"
11895 "TEST EAX,EAX\n\t"
11896 "JNE,s fast\n\t"
11897 "FLD $src\n\t"
11898 "CALL d2l_wrapper\n"
11899 "fast:" %}
11900 // D2L_encoding works for F2L
11901 ins_encode( Push_Reg_F(src), D2L_encoding(src) );
11902 ins_pipe( pipe_slow );
11903 %}
11904
11905 // XMM lacks a float/double->long conversion, so use the old FPU stack.
11906 instruct convX2L_reg_reg( eADXRegL dst, regX src, eFlagsReg cr ) %{
11907 predicate (UseSSE>=1);
11908 match(Set dst (ConvF2L src));
11909 effect( KILL cr );
11910 format %{ "SUB ESP,8\t# Convert float to long\n\t"
11911 "MOVSS [ESP],$src\n\t"
11912 "FLD_S [ESP]\n\t"
11913 "FLDCW trunc mode\n\t"
11914 "FISTp [ESP + #0]\n\t"
11915 "FLDCW std/24-bit mode\n\t"
11916 "POP EAX\n\t"
11917 "POP EDX\n\t"
11918 "CMP EDX,0x80000000\n\t"
11919 "JNE,s fast\n\t"
11920 "TEST EAX,EAX\n\t"
11921 "JNE,s fast\n\t"
11922 "SUB ESP,4\t# Convert float to long\n\t"
11923 "MOVSS [ESP],$src\n\t"
11924 "FLD_S [ESP]\n\t"
11925 "ADD ESP,4\n\t"
11926 "CALL d2l_wrapper\n"
11927 "fast:" %}
11928 ins_encode( X2L_encoding(src) );
11929 ins_pipe( pipe_slow );
11930 %}
11931
11932 instruct convI2D_reg(regD dst, stackSlotI src) %{
11933 predicate( UseSSE<=1 );
11934 match(Set dst (ConvI2D src));
11935 format %{ "FILD $src\n\t"
11936 "FSTP $dst" %}
11937 opcode(0xDB, 0x0); /* DB /0 */
11938 ins_encode(Push_Mem_I(src), Pop_Reg_D(dst));
11939 ins_pipe( fpu_reg_mem );
11940 %}
11941
11942 instruct convI2XD_reg(regXD dst, eRegI src) %{
11943 predicate( UseSSE>=2 && !UseXmmI2D );
11944 match(Set dst (ConvI2D src));
11945 format %{ "CVTSI2SD $dst,$src" %}
11946 opcode(0xF2, 0x0F, 0x2A);
11947 ins_encode( OpcP, OpcS, Opcode(tertiary), RegReg(dst, src));
11948 ins_pipe( pipe_slow );
11949 %}
11950
11951 instruct convI2XD_mem(regXD dst, memory mem) %{
11952 predicate( UseSSE>=2 );
11953 match(Set dst (ConvI2D (LoadI mem)));
11954 format %{ "CVTSI2SD $dst,$mem" %}
11955 opcode(0xF2, 0x0F, 0x2A);
11956 ins_encode( OpcP, OpcS, Opcode(tertiary), RegMem(dst, mem));
11957 ins_pipe( pipe_slow );
11958 %}
11959
11960 instruct convXI2XD_reg(regXD dst, eRegI src)
11961 %{
11962 predicate( UseSSE>=2 && UseXmmI2D );
11963 match(Set dst (ConvI2D src));
11964
11965 format %{ "MOVD $dst,$src\n\t"
11966 "CVTDQ2PD $dst,$dst\t# i2d" %}
11967 ins_encode %{
11968 __ movdl($dst$$XMMRegister, $src$$Register);
11969 __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister);
11970 %}
11971 ins_pipe(pipe_slow); // XXX
11972 %}
11973
11974 instruct convI2D_mem(regD dst, memory mem) %{
11975 predicate( UseSSE<=1 && !Compile::current()->select_24_bit_instr());
11976 match(Set dst (ConvI2D (LoadI mem)));
11977 format %{ "FILD $mem\n\t"
11978 "FSTP $dst" %}
11979 opcode(0xDB); /* DB /0 */
11980 ins_encode( OpcP, RMopc_Mem(0x00,mem),
11981 Pop_Reg_D(dst));
11982 ins_pipe( fpu_reg_mem );
11983 %}
11984
11985 // Convert a byte to a float; no rounding step needed.
11986 instruct conv24I2F_reg(regF dst, stackSlotI src) %{
11987 predicate( UseSSE==0 && n->in(1)->Opcode() == Op_AndI && n->in(1)->in(2)->is_Con() && n->in(1)->in(2)->get_int() == 255 );
11988 match(Set dst (ConvI2F src));
11989 format %{ "FILD $src\n\t"
11990 "FSTP $dst" %}
11991
11992 opcode(0xDB, 0x0); /* DB /0 */
11993 ins_encode(Push_Mem_I(src), Pop_Reg_F(dst));
11994 ins_pipe( fpu_reg_mem );
11995 %}
11996
11997 // In 24-bit mode, force exponent rounding by storing back out
11998 instruct convI2F_SSF(stackSlotF dst, stackSlotI src) %{
11999 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
12000 match(Set dst (ConvI2F src));
12001 ins_cost(200);
12002 format %{ "FILD $src\n\t"
12003 "FSTP_S $dst" %}
12004 opcode(0xDB, 0x0); /* DB /0 */
12005 ins_encode( Push_Mem_I(src),
12006 Pop_Mem_F(dst));
12007 ins_pipe( fpu_mem_mem );
12008 %}
12009
12010 // In 24-bit mode, force exponent rounding by storing back out
12011 instruct convI2F_SSF_mem(stackSlotF dst, memory mem) %{
12012 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
12013 match(Set dst (ConvI2F (LoadI mem)));
12014 ins_cost(200);
12015 format %{ "FILD $mem\n\t"
12016 "FSTP_S $dst" %}
12017 opcode(0xDB); /* DB /0 */
12018 ins_encode( OpcP, RMopc_Mem(0x00,mem),
12019 Pop_Mem_F(dst));
12020 ins_pipe( fpu_mem_mem );
12021 %}
12022
12023 // This instruction does not round to 24-bits
12024 instruct convI2F_reg(regF dst, stackSlotI src) %{
12025 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
12026 match(Set dst (ConvI2F src));
12027 format %{ "FILD $src\n\t"
12028 "FSTP $dst" %}
12029 opcode(0xDB, 0x0); /* DB /0 */
12030 ins_encode( Push_Mem_I(src),
12031 Pop_Reg_F(dst));
12032 ins_pipe( fpu_reg_mem );
12033 %}
12034
12035 // This instruction does not round to 24-bits
12036 instruct convI2F_mem(regF dst, memory mem) %{
12037 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
12038 match(Set dst (ConvI2F (LoadI mem)));
12039 format %{ "FILD $mem\n\t"
12040 "FSTP $dst" %}
12041 opcode(0xDB); /* DB /0 */
12042 ins_encode( OpcP, RMopc_Mem(0x00,mem),
12043 Pop_Reg_F(dst));
12044 ins_pipe( fpu_reg_mem );
12045 %}
12046
12047 // Convert an int to a float in xmm; no rounding step needed.
12048 instruct convI2X_reg(regX dst, eRegI src) %{
12049 predicate( UseSSE==1 || UseSSE>=2 && !UseXmmI2F );
12050 match(Set dst (ConvI2F src));
12051 format %{ "CVTSI2SS $dst, $src" %}
12052
12053 opcode(0xF3, 0x0F, 0x2A); /* F3 0F 2A /r */
12054 ins_encode( OpcP, OpcS, Opcode(tertiary), RegReg(dst, src));
12055 ins_pipe( pipe_slow );
12056 %}
12057
12058 instruct convXI2X_reg(regX dst, eRegI src)
12059 %{
12060 predicate( UseSSE>=2 && UseXmmI2F );
12061 match(Set dst (ConvI2F src));
12062
12063 format %{ "MOVD $dst,$src\n\t"
12064 "CVTDQ2PS $dst,$dst\t# i2f" %}
12065 ins_encode %{
12066 __ movdl($dst$$XMMRegister, $src$$Register);
12067 __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister);
12068 %}
12069 ins_pipe(pipe_slow); // XXX
12070 %}
12071
12072 instruct convI2L_reg( eRegL dst, eRegI src, eFlagsReg cr) %{
12073 match(Set dst (ConvI2L src));
12074 effect(KILL cr);
12075 ins_cost(375);
12076 format %{ "MOV $dst.lo,$src\n\t"
12077 "MOV $dst.hi,$src\n\t"
12078 "SAR $dst.hi,31" %}
12079 ins_encode(convert_int_long(dst,src));
12080 ins_pipe( ialu_reg_reg_long );
12081 %}
12082
12083 // Zero-extend convert int to long
12084 instruct convI2L_reg_zex(eRegL dst, eRegI src, immL_32bits mask, eFlagsReg flags ) %{
12085 match(Set dst (AndL (ConvI2L src) mask) );
12086 effect( KILL flags );
12087 ins_cost(250);
12088 format %{ "MOV $dst.lo,$src\n\t"
12089 "XOR $dst.hi,$dst.hi" %}
12090 opcode(0x33); // XOR
12091 ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) );
12092 ins_pipe( ialu_reg_reg_long );
12093 %}
12094
12095 // Zero-extend long
12096 instruct zerox_long(eRegL dst, eRegL src, immL_32bits mask, eFlagsReg flags ) %{
12097 match(Set dst (AndL src mask) );
12098 effect( KILL flags );
12099 ins_cost(250);
12100 format %{ "MOV $dst.lo,$src.lo\n\t"
12101 "XOR $dst.hi,$dst.hi\n\t" %}
12102 opcode(0x33); // XOR
12103 ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) );
12104 ins_pipe( ialu_reg_reg_long );
12105 %}
12106
12107 instruct convL2D_reg( stackSlotD dst, eRegL src, eFlagsReg cr) %{
12108 predicate (UseSSE<=1);
12109 match(Set dst (ConvL2D src));
12110 effect( KILL cr );
12111 format %{ "PUSH $src.hi\t# Convert long to double\n\t"
12112 "PUSH $src.lo\n\t"
12113 "FILD ST,[ESP + #0]\n\t"
12114 "ADD ESP,8\n\t"
12115 "FSTP_D $dst\t# D-round" %}
12116 opcode(0xDF, 0x5); /* DF /5 */
12117 ins_encode(convert_long_double(src), Pop_Mem_D(dst));
12118 ins_pipe( pipe_slow );
12119 %}
12120
12121 instruct convL2XD_reg( regXD dst, eRegL src, eFlagsReg cr) %{
12122 predicate (UseSSE>=2);
12123 match(Set dst (ConvL2D src));
12124 effect( KILL cr );
12125 format %{ "PUSH $src.hi\t# Convert long to double\n\t"
12126 "PUSH $src.lo\n\t"
12127 "FILD_D [ESP]\n\t"
12128 "FSTP_D [ESP]\n\t"
12129 "MOVSD $dst,[ESP]\n\t"
12130 "ADD ESP,8" %}
12131 opcode(0xDF, 0x5); /* DF /5 */
12132 ins_encode(convert_long_double2(src), Push_ResultXD(dst));
12133 ins_pipe( pipe_slow );
12134 %}
12135
12136 instruct convL2X_reg( regX dst, eRegL src, eFlagsReg cr) %{
12137 predicate (UseSSE>=1);
12138 match(Set dst (ConvL2F src));
12139 effect( KILL cr );
12140 format %{ "PUSH $src.hi\t# Convert long to single float\n\t"
12141 "PUSH $src.lo\n\t"
12142 "FILD_D [ESP]\n\t"
12143 "FSTP_S [ESP]\n\t"
12144 "MOVSS $dst,[ESP]\n\t"
12145 "ADD ESP,8" %}
12146 opcode(0xDF, 0x5); /* DF /5 */
12147 ins_encode(convert_long_double2(src), Push_ResultX(dst,0x8));
12148 ins_pipe( pipe_slow );
12149 %}
12150
12151 instruct convL2F_reg( stackSlotF dst, eRegL src, eFlagsReg cr) %{
12152 match(Set dst (ConvL2F src));
12153 effect( KILL cr );
12154 format %{ "PUSH $src.hi\t# Convert long to single float\n\t"
12155 "PUSH $src.lo\n\t"
12156 "FILD ST,[ESP + #0]\n\t"
12157 "ADD ESP,8\n\t"
12158 "FSTP_S $dst\t# F-round" %}
12159 opcode(0xDF, 0x5); /* DF /5 */
12160 ins_encode(convert_long_double(src), Pop_Mem_F(dst));
12161 ins_pipe( pipe_slow );
12162 %}
12163
12164 instruct convL2I_reg( eRegI dst, eRegL src ) %{
12165 match(Set dst (ConvL2I src));
12166 effect( DEF dst, USE src );
12167 format %{ "MOV $dst,$src.lo" %}
12168 ins_encode(enc_CopyL_Lo(dst,src));
12169 ins_pipe( ialu_reg_reg );
12170 %}
12171
12172
12173 instruct MoveF2I_stack_reg(eRegI dst, stackSlotF src) %{
12174 match(Set dst (MoveF2I src));
12175 effect( DEF dst, USE src );
12176 ins_cost(100);
12177 format %{ "MOV $dst,$src\t# MoveF2I_stack_reg" %}
12178 opcode(0x8B);
12179 ins_encode( OpcP, RegMem(dst,src));
12180 ins_pipe( ialu_reg_mem );
12181 %}
12182
12183 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{
12184 predicate(UseSSE==0);
12185 match(Set dst (MoveF2I src));
12186 effect( DEF dst, USE src );
12187
12188 ins_cost(125);
12189 format %{ "FST_S $dst,$src\t# MoveF2I_reg_stack" %}
12190 ins_encode( Pop_Mem_Reg_F(dst, src) );
12191 ins_pipe( fpu_mem_reg );
12192 %}
12193
12194 instruct MoveF2I_reg_stack_sse(stackSlotI dst, regX src) %{
12195 predicate(UseSSE>=1);
12196 match(Set dst (MoveF2I src));
12197 effect( DEF dst, USE src );
12198
12199 ins_cost(95);
12200 format %{ "MOVSS $dst,$src\t# MoveF2I_reg_stack_sse" %}
12201 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x11), RegMem(src, dst));
12202 ins_pipe( pipe_slow );
12203 %}
12204
12205 instruct MoveF2I_reg_reg_sse(eRegI dst, regX src) %{
12206 predicate(UseSSE>=2);
12207 match(Set dst (MoveF2I src));
12208 effect( DEF dst, USE src );
12209 ins_cost(85);
12210 format %{ "MOVD $dst,$src\t# MoveF2I_reg_reg_sse" %}
12211 ins_encode( MovX2I_reg(dst, src));
12212 ins_pipe( pipe_slow );
12213 %}
12214
12215 instruct MoveI2F_reg_stack(stackSlotF dst, eRegI src) %{
12216 match(Set dst (MoveI2F src));
12217 effect( DEF dst, USE src );
12218
12219 ins_cost(100);
12220 format %{ "MOV $dst,$src\t# MoveI2F_reg_stack" %}
12221 opcode(0x89);
12222 ins_encode( OpcPRegSS( dst, src ) );
12223 ins_pipe( ialu_mem_reg );
12224 %}
12225
12226
12227 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
12228 predicate(UseSSE==0);
12229 match(Set dst (MoveI2F src));
12230 effect(DEF dst, USE src);
12231
12232 ins_cost(125);
12233 format %{ "FLD_S $src\n\t"
12234 "FSTP $dst\t# MoveI2F_stack_reg" %}
12235 opcode(0xD9); /* D9 /0, FLD m32real */
12236 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
12237 Pop_Reg_F(dst) );
12238 ins_pipe( fpu_reg_mem );
12239 %}
12240
12241 instruct MoveI2F_stack_reg_sse(regX dst, stackSlotI src) %{
12242 predicate(UseSSE>=1);
12243 match(Set dst (MoveI2F src));
12244 effect( DEF dst, USE src );
12245
12246 ins_cost(95);
12247 format %{ "MOVSS $dst,$src\t# MoveI2F_stack_reg_sse" %}
12248 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x10), RegMem(dst,src));
12249 ins_pipe( pipe_slow );
12250 %}
12251
12252 instruct MoveI2F_reg_reg_sse(regX dst, eRegI src) %{
12253 predicate(UseSSE>=2);
12254 match(Set dst (MoveI2F src));
12255 effect( DEF dst, USE src );
12256
12257 ins_cost(85);
12258 format %{ "MOVD $dst,$src\t# MoveI2F_reg_reg_sse" %}
12259 ins_encode( MovI2X_reg(dst, src) );
12260 ins_pipe( pipe_slow );
12261 %}
12262
12263 instruct MoveD2L_stack_reg(eRegL dst, stackSlotD src) %{
12264 match(Set dst (MoveD2L src));
12265 effect(DEF dst, USE src);
12266
12267 ins_cost(250);
12268 format %{ "MOV $dst.lo,$src\n\t"
12269 "MOV $dst.hi,$src+4\t# MoveD2L_stack_reg" %}
12270 opcode(0x8B, 0x8B);
12271 ins_encode( OpcP, RegMem(dst,src), OpcS, RegMem_Hi(dst,src));
12272 ins_pipe( ialu_mem_long_reg );
12273 %}
12274
12275 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
12276 predicate(UseSSE<=1);
12277 match(Set dst (MoveD2L src));
12278 effect(DEF dst, USE src);
12279
12280 ins_cost(125);
12281 format %{ "FST_D $dst,$src\t# MoveD2L_reg_stack" %}
12282 ins_encode( Pop_Mem_Reg_D(dst, src) );
12283 ins_pipe( fpu_mem_reg );
12284 %}
12285
12286 instruct MoveD2L_reg_stack_sse(stackSlotL dst, regXD src) %{
12287 predicate(UseSSE>=2);
12288 match(Set dst (MoveD2L src));
12289 effect(DEF dst, USE src);
12290 ins_cost(95);
12291
12292 format %{ "MOVSD $dst,$src\t# MoveD2L_reg_stack_sse" %}
12293 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x11), RegMem(src,dst));
12294 ins_pipe( pipe_slow );
12295 %}
12296
12297 instruct MoveD2L_reg_reg_sse(eRegL dst, regXD src, regXD tmp) %{
12298 predicate(UseSSE>=2);
12299 match(Set dst (MoveD2L src));
12300 effect(DEF dst, USE src, TEMP tmp);
12301 ins_cost(85);
12302 format %{ "MOVD $dst.lo,$src\n\t"
12303 "PSHUFLW $tmp,$src,0x4E\n\t"
12304 "MOVD $dst.hi,$tmp\t# MoveD2L_reg_reg_sse" %}
12305 ins_encode( MovXD2L_reg(dst, src, tmp) );
12306 ins_pipe( pipe_slow );
12307 %}
12308
12309 instruct MoveL2D_reg_stack(stackSlotD dst, eRegL src) %{
12310 match(Set dst (MoveL2D src));
12311 effect(DEF dst, USE src);
12312
12313 ins_cost(200);
12314 format %{ "MOV $dst,$src.lo\n\t"
12315 "MOV $dst+4,$src.hi\t# MoveL2D_reg_stack" %}
12316 opcode(0x89, 0x89);
12317 ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) );
12318 ins_pipe( ialu_mem_long_reg );
12319 %}
12320
12321
12322 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
12323 predicate(UseSSE<=1);
12324 match(Set dst (MoveL2D src));
12325 effect(DEF dst, USE src);
12326 ins_cost(125);
12327
12328 format %{ "FLD_D $src\n\t"
12329 "FSTP $dst\t# MoveL2D_stack_reg" %}
12330 opcode(0xDD); /* DD /0, FLD m64real */
12331 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
12332 Pop_Reg_D(dst) );
12333 ins_pipe( fpu_reg_mem );
12334 %}
12335
12336
12337 instruct MoveL2D_stack_reg_sse(regXD dst, stackSlotL src) %{
12338 predicate(UseSSE>=2 && UseXmmLoadAndClearUpper);
12339 match(Set dst (MoveL2D src));
12340 effect(DEF dst, USE src);
12341
12342 ins_cost(95);
12343 format %{ "MOVSD $dst,$src\t# MoveL2D_stack_reg_sse" %}
12344 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x10), RegMem(dst,src));
12345 ins_pipe( pipe_slow );
12346 %}
12347
12348 instruct MoveL2D_stack_reg_sse_partial(regXD dst, stackSlotL src) %{
12349 predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper);
12350 match(Set dst (MoveL2D src));
12351 effect(DEF dst, USE src);
12352
12353 ins_cost(95);
12354 format %{ "MOVLPD $dst,$src\t# MoveL2D_stack_reg_sse" %}
12355 ins_encode( Opcode(0x66), Opcode(0x0F), Opcode(0x12), RegMem(dst,src));
12356 ins_pipe( pipe_slow );
12357 %}
12358
12359 instruct MoveL2D_reg_reg_sse(regXD dst, eRegL src, regXD tmp) %{
12360 predicate(UseSSE>=2);
12361 match(Set dst (MoveL2D src));
12362 effect(TEMP dst, USE src, TEMP tmp);
12363 ins_cost(85);
12364 format %{ "MOVD $dst,$src.lo\n\t"
12365 "MOVD $tmp,$src.hi\n\t"
12366 "PUNPCKLDQ $dst,$tmp\t# MoveL2D_reg_reg_sse" %}
12367 ins_encode( MovL2XD_reg(dst, src, tmp) );
12368 ins_pipe( pipe_slow );
12369 %}
12370
12371 // Replicate scalar to packed byte (1 byte) values in xmm
12372 instruct Repl8B_reg(regXD dst, regXD src) %{
12373 predicate(UseSSE>=2);
12374 match(Set dst (Replicate8B src));
12375 format %{ "MOVDQA $dst,$src\n\t"
12376 "PUNPCKLBW $dst,$dst\n\t"
12377 "PSHUFLW $dst,$dst,0x00\t! replicate8B" %}
12378 ins_encode( pshufd_8x8(dst, src));
12379 ins_pipe( pipe_slow );
12380 %}
12381
12382 // Replicate scalar to packed byte (1 byte) values in xmm
12383 instruct Repl8B_eRegI(regXD dst, eRegI src) %{
12384 predicate(UseSSE>=2);
12385 match(Set dst (Replicate8B src));
12386 format %{ "MOVD $dst,$src\n\t"
12387 "PUNPCKLBW $dst,$dst\n\t"
12388 "PSHUFLW $dst,$dst,0x00\t! replicate8B" %}
12389 ins_encode( mov_i2x(dst, src), pshufd_8x8(dst, dst));
12390 ins_pipe( pipe_slow );
12391 %}
12392
12393 // Replicate scalar zero to packed byte (1 byte) values in xmm
12394 instruct Repl8B_immI0(regXD dst, immI0 zero) %{
12395 predicate(UseSSE>=2);
12396 match(Set dst (Replicate8B zero));
12397 format %{ "PXOR $dst,$dst\t! replicate8B" %}
12398 ins_encode( pxor(dst, dst));
12399 ins_pipe( fpu_reg_reg );
12400 %}
12401
12402 // Replicate scalar to packed shore (2 byte) values in xmm
12403 instruct Repl4S_reg(regXD dst, regXD src) %{
12404 predicate(UseSSE>=2);
12405 match(Set dst (Replicate4S src));
12406 format %{ "PSHUFLW $dst,$src,0x00\t! replicate4S" %}
12407 ins_encode( pshufd_4x16(dst, src));
12408 ins_pipe( fpu_reg_reg );
12409 %}
12410
12411 // Replicate scalar to packed shore (2 byte) values in xmm
12412 instruct Repl4S_eRegI(regXD dst, eRegI src) %{
12413 predicate(UseSSE>=2);
12414 match(Set dst (Replicate4S src));
12415 format %{ "MOVD $dst,$src\n\t"
12416 "PSHUFLW $dst,$dst,0x00\t! replicate4S" %}
12417 ins_encode( mov_i2x(dst, src), pshufd_4x16(dst, dst));
12418 ins_pipe( fpu_reg_reg );
12419 %}
12420
12421 // Replicate scalar zero to packed short (2 byte) values in xmm
12422 instruct Repl4S_immI0(regXD dst, immI0 zero) %{
12423 predicate(UseSSE>=2);
12424 match(Set dst (Replicate4S zero));
12425 format %{ "PXOR $dst,$dst\t! replicate4S" %}
12426 ins_encode( pxor(dst, dst));
12427 ins_pipe( fpu_reg_reg );
12428 %}
12429
12430 // Replicate scalar to packed char (2 byte) values in xmm
12431 instruct Repl4C_reg(regXD dst, regXD src) %{
12432 predicate(UseSSE>=2);
12433 match(Set dst (Replicate4C src));
12434 format %{ "PSHUFLW $dst,$src,0x00\t! replicate4C" %}
12435 ins_encode( pshufd_4x16(dst, src));
12436 ins_pipe( fpu_reg_reg );
12437 %}
12438
12439 // Replicate scalar to packed char (2 byte) values in xmm
12440 instruct Repl4C_eRegI(regXD dst, eRegI src) %{
12441 predicate(UseSSE>=2);
12442 match(Set dst (Replicate4C src));
12443 format %{ "MOVD $dst,$src\n\t"
12444 "PSHUFLW $dst,$dst,0x00\t! replicate4C" %}
12445 ins_encode( mov_i2x(dst, src), pshufd_4x16(dst, dst));
12446 ins_pipe( fpu_reg_reg );
12447 %}
12448
12449 // Replicate scalar zero to packed char (2 byte) values in xmm
12450 instruct Repl4C_immI0(regXD dst, immI0 zero) %{
12451 predicate(UseSSE>=2);
12452 match(Set dst (Replicate4C zero));
12453 format %{ "PXOR $dst,$dst\t! replicate4C" %}
12454 ins_encode( pxor(dst, dst));
12455 ins_pipe( fpu_reg_reg );
12456 %}
12457
12458 // Replicate scalar to packed integer (4 byte) values in xmm
12459 instruct Repl2I_reg(regXD dst, regXD src) %{
12460 predicate(UseSSE>=2);
12461 match(Set dst (Replicate2I src));
12462 format %{ "PSHUFD $dst,$src,0x00\t! replicate2I" %}
12463 ins_encode( pshufd(dst, src, 0x00));
12464 ins_pipe( fpu_reg_reg );
12465 %}
12466
12467 // Replicate scalar to packed integer (4 byte) values in xmm
12468 instruct Repl2I_eRegI(regXD dst, eRegI src) %{
12469 predicate(UseSSE>=2);
12470 match(Set dst (Replicate2I src));
12471 format %{ "MOVD $dst,$src\n\t"
12472 "PSHUFD $dst,$dst,0x00\t! replicate2I" %}
12473 ins_encode( mov_i2x(dst, src), pshufd(dst, dst, 0x00));
12474 ins_pipe( fpu_reg_reg );
12475 %}
12476
12477 // Replicate scalar zero to packed integer (2 byte) values in xmm
12478 instruct Repl2I_immI0(regXD dst, immI0 zero) %{
12479 predicate(UseSSE>=2);
12480 match(Set dst (Replicate2I zero));
12481 format %{ "PXOR $dst,$dst\t! replicate2I" %}
12482 ins_encode( pxor(dst, dst));
12483 ins_pipe( fpu_reg_reg );
12484 %}
12485
12486 // Replicate scalar to packed single precision floating point values in xmm
12487 instruct Repl2F_reg(regXD dst, regXD src) %{
12488 predicate(UseSSE>=2);
12489 match(Set dst (Replicate2F src));
12490 format %{ "PSHUFD $dst,$src,0xe0\t! replicate2F" %}
12491 ins_encode( pshufd(dst, src, 0xe0));
12492 ins_pipe( fpu_reg_reg );
12493 %}
12494
12495 // Replicate scalar to packed single precision floating point values in xmm
12496 instruct Repl2F_regX(regXD dst, regX src) %{
12497 predicate(UseSSE>=2);
12498 match(Set dst (Replicate2F src));
12499 format %{ "PSHUFD $dst,$src,0xe0\t! replicate2F" %}
12500 ins_encode( pshufd(dst, src, 0xe0));
12501 ins_pipe( fpu_reg_reg );
12502 %}
12503
12504 // Replicate scalar to packed single precision floating point values in xmm
12505 instruct Repl2F_immXF0(regXD dst, immXF0 zero) %{
12506 predicate(UseSSE>=2);
12507 match(Set dst (Replicate2F zero));
12508 format %{ "PXOR $dst,$dst\t! replicate2F" %}
12509 ins_encode( pxor(dst, dst));
12510 ins_pipe( fpu_reg_reg );
12511 %}
12512
12513 // =======================================================================
12514 // fast clearing of an array
12515 instruct rep_stos(eCXRegI cnt, eDIRegP base, eAXRegI zero, Universe dummy, eFlagsReg cr) %{
12516 match(Set dummy (ClearArray cnt base));
12517 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr);
12518 format %{ "SHL ECX,1\t# Convert doublewords to words\n\t"
12519 "XOR EAX,EAX\n\t"
12520 "REP STOS\t# store EAX into [EDI++] while ECX--" %}
12521 opcode(0,0x4);
12522 ins_encode( Opcode(0xD1), RegOpc(ECX),
12523 OpcRegReg(0x33,EAX,EAX),
12524 Opcode(0xF3), Opcode(0xAB) );
12525 ins_pipe( pipe_slow );
12526 %}
12527
12528 instruct string_compare(eDIRegP str1, eSIRegP str2, regXD tmp1, regXD tmp2,
12529 eAXRegI tmp3, eBXRegI tmp4, eCXRegI result, eFlagsReg cr) %{
12530 match(Set result (StrComp str1 str2));
12531 effect(TEMP tmp1, TEMP tmp2, USE_KILL str1, USE_KILL str2, KILL tmp3, KILL tmp4, KILL cr);
12532 //ins_cost(300);
12533
12534 format %{ "String Compare $str1,$str2 -> $result // KILL EAX, EBX" %}
12535 ins_encode( enc_String_Compare(str1, str2, tmp1, tmp2, tmp3, tmp4, result) );
12536 ins_pipe( pipe_slow );
12537 %}
12538
12539 // fast string equals
12540 instruct string_equals(eDIRegP str1, eSIRegP str2, regXD tmp1, regXD tmp2,
12541 eBXRegI tmp3, eCXRegI tmp4, eAXRegI result, eFlagsReg cr) %{
12542 match(Set result (StrEquals str1 str2));
12543 effect(TEMP tmp1, TEMP tmp2, USE_KILL str1, USE_KILL str2, KILL tmp3, KILL tmp4, KILL cr);
12544
12545 format %{ "String Equals $str1,$str2 -> $result // KILL EBX, ECX" %}
12546 ins_encode( enc_String_Equals(tmp1, tmp2, str1, str2, tmp3, tmp4, result) );
12547 ins_pipe( pipe_slow );
12548 %}
12549
12550 instruct string_indexof(eSIRegP str1, eDIRegP str2, regXD tmp1, eAXRegI tmp2,
12551 eCXRegI tmp3, eDXRegI tmp4, eBXRegI result, eFlagsReg cr) %{
12552 predicate(UseSSE42Intrinsics);
12553 match(Set result (StrIndexOf str1 str2));
12554 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, KILL tmp2, KILL tmp3, KILL tmp4, KILL cr);
12555
12556 format %{ "String IndexOf $str1,$str2 -> $result // KILL EAX, ECX, EDX" %}
12557 ins_encode( enc_String_IndexOf(str1, str2, tmp1, tmp2, tmp3, tmp4, result) );
12558 ins_pipe( pipe_slow );
12559 %}
12560
12561 // fast array equals
12562 instruct array_equals(eDIRegP ary1, eSIRegP ary2, regXD tmp1, regXD tmp2, eBXRegI tmp3,
12563 eDXRegI tmp4, eAXRegI result, eFlagsReg cr) %{
12564 match(Set result (AryEq ary1 ary2));
12565 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
12566 //ins_cost(300);
12567
12568 format %{ "Array Equals $ary1,$ary2 -> $result // KILL EBX, EDX" %}
12569 ins_encode( enc_Array_Equals(ary1, ary2, tmp1, tmp2, tmp3, tmp4, result) );
12570 ins_pipe( pipe_slow );
12571 %}
12572
12573 //----------Control Flow Instructions------------------------------------------
12574 // Signed compare Instructions
12575 instruct compI_eReg(eFlagsReg cr, eRegI op1, eRegI op2) %{
12576 match(Set cr (CmpI op1 op2));
12577 effect( DEF cr, USE op1, USE op2 );
12578 format %{ "CMP $op1,$op2" %}
12579 opcode(0x3B); /* Opcode 3B /r */
12580 ins_encode( OpcP, RegReg( op1, op2) );
12581 ins_pipe( ialu_cr_reg_reg );
12582 %}
12583
12584 instruct compI_eReg_imm(eFlagsReg cr, eRegI op1, immI op2) %{
12585 match(Set cr (CmpI op1 op2));
12586 effect( DEF cr, USE op1 );
12587 format %{ "CMP $op1,$op2" %}
12588 opcode(0x81,0x07); /* Opcode 81 /7 */
12589 // ins_encode( RegImm( op1, op2) ); /* Was CmpImm */
12590 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
12591 ins_pipe( ialu_cr_reg_imm );
12592 %}
12593
12594 // Cisc-spilled version of cmpI_eReg
12595 instruct compI_eReg_mem(eFlagsReg cr, eRegI op1, memory op2) %{
12596 match(Set cr (CmpI op1 (LoadI op2)));
12597
12598 format %{ "CMP $op1,$op2" %}
12599 ins_cost(500);
12600 opcode(0x3B); /* Opcode 3B /r */
12601 ins_encode( OpcP, RegMem( op1, op2) );
12602 ins_pipe( ialu_cr_reg_mem );
12603 %}
12604
12605 instruct testI_reg( eFlagsReg cr, eRegI src, immI0 zero ) %{
12606 match(Set cr (CmpI src zero));
12607 effect( DEF cr, USE src );
12608
12609 format %{ "TEST $src,$src" %}
12610 opcode(0x85);
12611 ins_encode( OpcP, RegReg( src, src ) );
12612 ins_pipe( ialu_cr_reg_imm );
12613 %}
12614
12615 instruct testI_reg_imm( eFlagsReg cr, eRegI src, immI con, immI0 zero ) %{
12616 match(Set cr (CmpI (AndI src con) zero));
12617
12618 format %{ "TEST $src,$con" %}
12619 opcode(0xF7,0x00);
12620 ins_encode( OpcP, RegOpc(src), Con32(con) );
12621 ins_pipe( ialu_cr_reg_imm );
12622 %}
12623
12624 instruct testI_reg_mem( eFlagsReg cr, eRegI src, memory mem, immI0 zero ) %{
12625 match(Set cr (CmpI (AndI src mem) zero));
12626
12627 format %{ "TEST $src,$mem" %}
12628 opcode(0x85);
12629 ins_encode( OpcP, RegMem( src, mem ) );
12630 ins_pipe( ialu_cr_reg_mem );
12631 %}
12632
12633 // Unsigned compare Instructions; really, same as signed except they
12634 // produce an eFlagsRegU instead of eFlagsReg.
12635 instruct compU_eReg(eFlagsRegU cr, eRegI op1, eRegI op2) %{
12636 match(Set cr (CmpU op1 op2));
12637
12638 format %{ "CMPu $op1,$op2" %}
12639 opcode(0x3B); /* Opcode 3B /r */
12640 ins_encode( OpcP, RegReg( op1, op2) );
12641 ins_pipe( ialu_cr_reg_reg );
12642 %}
12643
12644 instruct compU_eReg_imm(eFlagsRegU cr, eRegI op1, immI op2) %{
12645 match(Set cr (CmpU op1 op2));
12646
12647 format %{ "CMPu $op1,$op2" %}
12648 opcode(0x81,0x07); /* Opcode 81 /7 */
12649 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
12650 ins_pipe( ialu_cr_reg_imm );
12651 %}
12652
12653 // // Cisc-spilled version of cmpU_eReg
12654 instruct compU_eReg_mem(eFlagsRegU cr, eRegI op1, memory op2) %{
12655 match(Set cr (CmpU op1 (LoadI op2)));
12656
12657 format %{ "CMPu $op1,$op2" %}
12658 ins_cost(500);
12659 opcode(0x3B); /* Opcode 3B /r */
12660 ins_encode( OpcP, RegMem( op1, op2) );
12661 ins_pipe( ialu_cr_reg_mem );
12662 %}
12663
12664 // // Cisc-spilled version of cmpU_eReg
12665 //instruct compU_mem_eReg(eFlagsRegU cr, memory op1, eRegI op2) %{
12666 // match(Set cr (CmpU (LoadI op1) op2));
12667 //
12668 // format %{ "CMPu $op1,$op2" %}
12669 // ins_cost(500);
12670 // opcode(0x39); /* Opcode 39 /r */
12671 // ins_encode( OpcP, RegMem( op1, op2) );
12672 //%}
12673
12674 instruct testU_reg( eFlagsRegU cr, eRegI src, immI0 zero ) %{
12675 match(Set cr (CmpU src zero));
12676
12677 format %{ "TESTu $src,$src" %}
12678 opcode(0x85);
12679 ins_encode( OpcP, RegReg( src, src ) );
12680 ins_pipe( ialu_cr_reg_imm );
12681 %}
12682
12683 // Unsigned pointer compare Instructions
12684 instruct compP_eReg(eFlagsRegU cr, eRegP op1, eRegP op2) %{
12685 match(Set cr (CmpP op1 op2));
12686
12687 format %{ "CMPu $op1,$op2" %}
12688 opcode(0x3B); /* Opcode 3B /r */
12689 ins_encode( OpcP, RegReg( op1, op2) );
12690 ins_pipe( ialu_cr_reg_reg );
12691 %}
12692
12693 instruct compP_eReg_imm(eFlagsRegU cr, eRegP op1, immP op2) %{
12694 match(Set cr (CmpP op1 op2));
12695
12696 format %{ "CMPu $op1,$op2" %}
12697 opcode(0x81,0x07); /* Opcode 81 /7 */
12698 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
12699 ins_pipe( ialu_cr_reg_imm );
12700 %}
12701
12702 // // Cisc-spilled version of cmpP_eReg
12703 instruct compP_eReg_mem(eFlagsRegU cr, eRegP op1, memory op2) %{
12704 match(Set cr (CmpP op1 (LoadP op2)));
12705
12706 format %{ "CMPu $op1,$op2" %}
12707 ins_cost(500);
12708 opcode(0x3B); /* Opcode 3B /r */
12709 ins_encode( OpcP, RegMem( op1, op2) );
12710 ins_pipe( ialu_cr_reg_mem );
12711 %}
12712
12713 // // Cisc-spilled version of cmpP_eReg
12714 //instruct compP_mem_eReg(eFlagsRegU cr, memory op1, eRegP op2) %{
12715 // match(Set cr (CmpP (LoadP op1) op2));
12716 //
12717 // format %{ "CMPu $op1,$op2" %}
12718 // ins_cost(500);
12719 // opcode(0x39); /* Opcode 39 /r */
12720 // ins_encode( OpcP, RegMem( op1, op2) );
12721 //%}
12722
12723 // Compare raw pointer (used in out-of-heap check).
12724 // Only works because non-oop pointers must be raw pointers
12725 // and raw pointers have no anti-dependencies.
12726 instruct compP_mem_eReg( eFlagsRegU cr, eRegP op1, memory op2 ) %{
12727 predicate( !n->in(2)->in(2)->bottom_type()->isa_oop_ptr() );
12728 match(Set cr (CmpP op1 (LoadP op2)));
12729
12730 format %{ "CMPu $op1,$op2" %}
12731 opcode(0x3B); /* Opcode 3B /r */
12732 ins_encode( OpcP, RegMem( op1, op2) );
12733 ins_pipe( ialu_cr_reg_mem );
12734 %}
12735
12736 //
12737 // This will generate a signed flags result. This should be ok
12738 // since any compare to a zero should be eq/neq.
12739 instruct testP_reg( eFlagsReg cr, eRegP src, immP0 zero ) %{
12740 match(Set cr (CmpP src zero));
12741
12742 format %{ "TEST $src,$src" %}
12743 opcode(0x85);
12744 ins_encode( OpcP, RegReg( src, src ) );
12745 ins_pipe( ialu_cr_reg_imm );
12746 %}
12747
12748 // Cisc-spilled version of testP_reg
12749 // This will generate a signed flags result. This should be ok
12750 // since any compare to a zero should be eq/neq.
12751 instruct testP_Reg_mem( eFlagsReg cr, memory op, immI0 zero ) %{
12752 match(Set cr (CmpP (LoadP op) zero));
12753
12754 format %{ "TEST $op,0xFFFFFFFF" %}
12755 ins_cost(500);
12756 opcode(0xF7); /* Opcode F7 /0 */
12757 ins_encode( OpcP, RMopc_Mem(0x00,op), Con_d32(0xFFFFFFFF) );
12758 ins_pipe( ialu_cr_reg_imm );
12759 %}
12760
12761 // Yanked all unsigned pointer compare operations.
12762 // Pointer compares are done with CmpP which is already unsigned.
12763
12764 //----------Max and Min--------------------------------------------------------
12765 // Min Instructions
12766 ////
12767 // *** Min and Max using the conditional move are slower than the
12768 // *** branch version on a Pentium III.
12769 // // Conditional move for min
12770 //instruct cmovI_reg_lt( eRegI op2, eRegI op1, eFlagsReg cr ) %{
12771 // effect( USE_DEF op2, USE op1, USE cr );
12772 // format %{ "CMOVlt $op2,$op1\t! min" %}
12773 // opcode(0x4C,0x0F);
12774 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) );
12775 // ins_pipe( pipe_cmov_reg );
12776 //%}
12777 //
12778 //// Min Register with Register (P6 version)
12779 //instruct minI_eReg_p6( eRegI op1, eRegI op2 ) %{
12780 // predicate(VM_Version::supports_cmov() );
12781 // match(Set op2 (MinI op1 op2));
12782 // ins_cost(200);
12783 // expand %{
12784 // eFlagsReg cr;
12785 // compI_eReg(cr,op1,op2);
12786 // cmovI_reg_lt(op2,op1,cr);
12787 // %}
12788 //%}
12789
12790 // Min Register with Register (generic version)
12791 instruct minI_eReg(eRegI dst, eRegI src, eFlagsReg flags) %{
12792 match(Set dst (MinI dst src));
12793 effect(KILL flags);
12794 ins_cost(300);
12795
12796 format %{ "MIN $dst,$src" %}
12797 opcode(0xCC);
12798 ins_encode( min_enc(dst,src) );
12799 ins_pipe( pipe_slow );
12800 %}
12801
12802 // Max Register with Register
12803 // *** Min and Max using the conditional move are slower than the
12804 // *** branch version on a Pentium III.
12805 // // Conditional move for max
12806 //instruct cmovI_reg_gt( eRegI op2, eRegI op1, eFlagsReg cr ) %{
12807 // effect( USE_DEF op2, USE op1, USE cr );
12808 // format %{ "CMOVgt $op2,$op1\t! max" %}
12809 // opcode(0x4F,0x0F);
12810 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) );
12811 // ins_pipe( pipe_cmov_reg );
12812 //%}
12813 //
12814 // // Max Register with Register (P6 version)
12815 //instruct maxI_eReg_p6( eRegI op1, eRegI op2 ) %{
12816 // predicate(VM_Version::supports_cmov() );
12817 // match(Set op2 (MaxI op1 op2));
12818 // ins_cost(200);
12819 // expand %{
12820 // eFlagsReg cr;
12821 // compI_eReg(cr,op1,op2);
12822 // cmovI_reg_gt(op2,op1,cr);
12823 // %}
12824 //%}
12825
12826 // Max Register with Register (generic version)
12827 instruct maxI_eReg(eRegI dst, eRegI src, eFlagsReg flags) %{
12828 match(Set dst (MaxI dst src));
12829 effect(KILL flags);
12830 ins_cost(300);
12831
12832 format %{ "MAX $dst,$src" %}
12833 opcode(0xCC);
12834 ins_encode( max_enc(dst,src) );
12835 ins_pipe( pipe_slow );
12836 %}
12837
12838 // ============================================================================
12839 // Branch Instructions
12840 // Jump Table
12841 instruct jumpXtnd(eRegI switch_val) %{
12842 match(Jump switch_val);
12843 ins_cost(350);
12844
12845 format %{ "JMP [table_base](,$switch_val,1)\n\t" %}
12846
12847 ins_encode %{
12848 address table_base = __ address_table_constant(_index2label);
12849
12850 // Jump to Address(table_base + switch_reg)
12851 InternalAddress table(table_base);
12852 Address index(noreg, $switch_val$$Register, Address::times_1);
12853 __ jump(ArrayAddress(table, index));
12854 %}
12855 ins_pc_relative(1);
12856 ins_pipe(pipe_jmp);
12857 %}
12858
12859 // Jump Direct - Label defines a relative address from JMP+1
12860 instruct jmpDir(label labl) %{
12861 match(Goto);
12862 effect(USE labl);
12863
12864 ins_cost(300);
12865 format %{ "JMP $labl" %}
12866 size(5);
12867 opcode(0xE9);
12868 ins_encode( OpcP, Lbl( labl ) );
12869 ins_pipe( pipe_jmp );
12870 ins_pc_relative(1);
12871 %}
12872
12873 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12874 instruct jmpCon(cmpOp cop, eFlagsReg cr, label labl) %{
12875 match(If cop cr);
12876 effect(USE labl);
12877
12878 ins_cost(300);
12879 format %{ "J$cop $labl" %}
12880 size(6);
12881 opcode(0x0F, 0x80);
12882 ins_encode( Jcc( cop, labl) );
12883 ins_pipe( pipe_jcc );
12884 ins_pc_relative(1);
12885 %}
12886
12887 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12888 instruct jmpLoopEnd(cmpOp cop, eFlagsReg cr, label labl) %{
12889 match(CountedLoopEnd cop cr);
12890 effect(USE labl);
12891
12892 ins_cost(300);
12893 format %{ "J$cop $labl\t# Loop end" %}
12894 size(6);
12895 opcode(0x0F, 0x80);
12896 ins_encode( Jcc( cop, labl) );
12897 ins_pipe( pipe_jcc );
12898 ins_pc_relative(1);
12899 %}
12900
12901 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12902 instruct jmpLoopEndU(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12903 match(CountedLoopEnd cop cmp);
12904 effect(USE labl);
12905
12906 ins_cost(300);
12907 format %{ "J$cop,u $labl\t# Loop end" %}
12908 size(6);
12909 opcode(0x0F, 0x80);
12910 ins_encode( Jcc( cop, labl) );
12911 ins_pipe( pipe_jcc );
12912 ins_pc_relative(1);
12913 %}
12914
12915 instruct jmpLoopEndUCF(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12916 match(CountedLoopEnd cop cmp);
12917 effect(USE labl);
12918
12919 ins_cost(200);
12920 format %{ "J$cop,u $labl\t# Loop end" %}
12921 size(6);
12922 opcode(0x0F, 0x80);
12923 ins_encode( Jcc( cop, labl) );
12924 ins_pipe( pipe_jcc );
12925 ins_pc_relative(1);
12926 %}
12927
12928 // Jump Direct Conditional - using unsigned comparison
12929 instruct jmpConU(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12930 match(If cop cmp);
12931 effect(USE labl);
12932
12933 ins_cost(300);
12934 format %{ "J$cop,u $labl" %}
12935 size(6);
12936 opcode(0x0F, 0x80);
12937 ins_encode(Jcc(cop, labl));
12938 ins_pipe(pipe_jcc);
12939 ins_pc_relative(1);
12940 %}
12941
12942 instruct jmpConUCF(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12943 match(If cop cmp);
12944 effect(USE labl);
12945
12946 ins_cost(200);
12947 format %{ "J$cop,u $labl" %}
12948 size(6);
12949 opcode(0x0F, 0x80);
12950 ins_encode(Jcc(cop, labl));
12951 ins_pipe(pipe_jcc);
12952 ins_pc_relative(1);
12953 %}
12954
12955 instruct jmpConUCF2(cmpOpUCF2 cop, eFlagsRegUCF cmp, label labl) %{
12956 match(If cop cmp);
12957 effect(USE labl);
12958
12959 ins_cost(200);
12960 format %{ $$template
12961 if ($cop$$cmpcode == Assembler::notEqual) {
12962 $$emit$$"JP,u $labl\n\t"
12963 $$emit$$"J$cop,u $labl"
12964 } else {
12965 $$emit$$"JP,u done\n\t"
12966 $$emit$$"J$cop,u $labl\n\t"
12967 $$emit$$"done:"
12968 }
12969 %}
12970 size(12);
12971 opcode(0x0F, 0x80);
12972 ins_encode %{
12973 Label* l = $labl$$label;
12974 $$$emit8$primary;
12975 emit_cc(cbuf, $secondary, Assembler::parity);
12976 int parity_disp = -1;
12977 bool ok = false;
12978 if ($cop$$cmpcode == Assembler::notEqual) {
12979 // the two jumps 6 bytes apart so the jump distances are too
12980 parity_disp = l ? (l->loc_pos() - (cbuf.code_size() + 4)) : 0;
12981 } else if ($cop$$cmpcode == Assembler::equal) {
12982 parity_disp = 6;
12983 ok = true;
12984 } else {
12985 ShouldNotReachHere();
12986 }
12987 emit_d32(cbuf, parity_disp);
12988 $$$emit8$primary;
12989 emit_cc(cbuf, $secondary, $cop$$cmpcode);
12990 int disp = l ? (l->loc_pos() - (cbuf.code_size() + 4)) : 0;
12991 emit_d32(cbuf, disp);
12992 %}
12993 ins_pipe(pipe_jcc);
12994 ins_pc_relative(1);
12995 %}
12996
12997 // ============================================================================
12998 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
12999 // array for an instance of the superklass. Set a hidden internal cache on a
13000 // hit (cache is checked with exposed code in gen_subtype_check()). Return
13001 // NZ for a miss or zero for a hit. The encoding ALSO sets flags.
13002 instruct partialSubtypeCheck( eDIRegP result, eSIRegP sub, eAXRegP super, eCXRegI rcx, eFlagsReg cr ) %{
13003 match(Set result (PartialSubtypeCheck sub super));
13004 effect( KILL rcx, KILL cr );
13005
13006 ins_cost(1100); // slightly larger than the next version
13007 format %{ "MOV EDI,[$sub+Klass::secondary_supers]\n\t"
13008 "MOV ECX,[EDI+arrayKlass::length]\t# length to scan\n\t"
13009 "ADD EDI,arrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t"
13010 "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t"
13011 "JNE,s miss\t\t# Missed: EDI not-zero\n\t"
13012 "MOV [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache\n\t"
13013 "XOR $result,$result\t\t Hit: EDI zero\n\t"
13014 "miss:\t" %}
13015
13016 opcode(0x1); // Force a XOR of EDI
13017 ins_encode( enc_PartialSubtypeCheck() );
13018 ins_pipe( pipe_slow );
13019 %}
13020
13021 instruct partialSubtypeCheck_vs_Zero( eFlagsReg cr, eSIRegP sub, eAXRegP super, eCXRegI rcx, eDIRegP result, immP0 zero ) %{
13022 match(Set cr (CmpP (PartialSubtypeCheck sub super) zero));
13023 effect( KILL rcx, KILL result );
13024
13025 ins_cost(1000);
13026 format %{ "MOV EDI,[$sub+Klass::secondary_supers]\n\t"
13027 "MOV ECX,[EDI+arrayKlass::length]\t# length to scan\n\t"
13028 "ADD EDI,arrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t"
13029 "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t"
13030 "JNE,s miss\t\t# Missed: flags NZ\n\t"
13031 "MOV [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache, flags Z\n\t"
13032 "miss:\t" %}
13033
13034 opcode(0x0); // No need to XOR EDI
13035 ins_encode( enc_PartialSubtypeCheck() );
13036 ins_pipe( pipe_slow );
13037 %}
13038
13039 // ============================================================================
13040 // Branch Instructions -- short offset versions
13041 //
13042 // These instructions are used to replace jumps of a long offset (the default
13043 // match) with jumps of a shorter offset. These instructions are all tagged
13044 // with the ins_short_branch attribute, which causes the ADLC to suppress the
13045 // match rules in general matching. Instead, the ADLC generates a conversion
13046 // method in the MachNode which can be used to do in-place replacement of the
13047 // long variant with the shorter variant. The compiler will determine if a
13048 // branch can be taken by the is_short_branch_offset() predicate in the machine
13049 // specific code section of the file.
13050
13051 // Jump Direct - Label defines a relative address from JMP+1
13052 instruct jmpDir_short(label labl) %{
13053 match(Goto);
13054 effect(USE labl);
13055
13056 ins_cost(300);
13057 format %{ "JMP,s $labl" %}
13058 size(2);
13059 opcode(0xEB);
13060 ins_encode( OpcP, LblShort( labl ) );
13061 ins_pipe( pipe_jmp );
13062 ins_pc_relative(1);
13063 ins_short_branch(1);
13064 %}
13065
13066 // Jump Direct Conditional - Label defines a relative address from Jcc+1
13067 instruct jmpCon_short(cmpOp cop, eFlagsReg cr, label labl) %{
13068 match(If cop cr);
13069 effect(USE labl);
13070
13071 ins_cost(300);
13072 format %{ "J$cop,s $labl" %}
13073 size(2);
13074 opcode(0x70);
13075 ins_encode( JccShort( cop, labl) );
13076 ins_pipe( pipe_jcc );
13077 ins_pc_relative(1);
13078 ins_short_branch(1);
13079 %}
13080
13081 // Jump Direct Conditional - Label defines a relative address from Jcc+1
13082 instruct jmpLoopEnd_short(cmpOp cop, eFlagsReg cr, label labl) %{
13083 match(CountedLoopEnd cop cr);
13084 effect(USE labl);
13085
13086 ins_cost(300);
13087 format %{ "J$cop,s $labl\t# Loop end" %}
13088 size(2);
13089 opcode(0x70);
13090 ins_encode( JccShort( cop, labl) );
13091 ins_pipe( pipe_jcc );
13092 ins_pc_relative(1);
13093 ins_short_branch(1);
13094 %}
13095
13096 // Jump Direct Conditional - Label defines a relative address from Jcc+1
13097 instruct jmpLoopEndU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{
13098 match(CountedLoopEnd cop cmp);
13099 effect(USE labl);
13100
13101 ins_cost(300);
13102 format %{ "J$cop,us $labl\t# Loop end" %}
13103 size(2);
13104 opcode(0x70);
13105 ins_encode( JccShort( cop, labl) );
13106 ins_pipe( pipe_jcc );
13107 ins_pc_relative(1);
13108 ins_short_branch(1);
13109 %}
13110
13111 instruct jmpLoopEndUCF_short(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
13112 match(CountedLoopEnd cop cmp);
13113 effect(USE labl);
13114
13115 ins_cost(300);
13116 format %{ "J$cop,us $labl\t# Loop end" %}
13117 size(2);
13118 opcode(0x70);
13119 ins_encode( JccShort( cop, labl) );
13120 ins_pipe( pipe_jcc );
13121 ins_pc_relative(1);
13122 ins_short_branch(1);
13123 %}
13124
13125 // Jump Direct Conditional - using unsigned comparison
13126 instruct jmpConU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{
13127 match(If cop cmp);
13128 effect(USE labl);
13129
13130 ins_cost(300);
13131 format %{ "J$cop,us $labl" %}
13132 size(2);
13133 opcode(0x70);
13134 ins_encode( JccShort( cop, labl) );
13135 ins_pipe( pipe_jcc );
13136 ins_pc_relative(1);
13137 ins_short_branch(1);
13138 %}
13139
13140 instruct jmpConUCF_short(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
13141 match(If cop cmp);
13142 effect(USE labl);
13143
13144 ins_cost(300);
13145 format %{ "J$cop,us $labl" %}
13146 size(2);
13147 opcode(0x70);
13148 ins_encode( JccShort( cop, labl) );
13149 ins_pipe( pipe_jcc );
13150 ins_pc_relative(1);
13151 ins_short_branch(1);
13152 %}
13153
13154 instruct jmpConUCF2_short(cmpOpUCF2 cop, eFlagsRegUCF cmp, label labl) %{
13155 match(If cop cmp);
13156 effect(USE labl);
13157
13158 ins_cost(300);
13159 format %{ $$template
13160 if ($cop$$cmpcode == Assembler::notEqual) {
13161 $$emit$$"JP,u,s $labl\n\t"
13162 $$emit$$"J$cop,u,s $labl"
13163 } else {
13164 $$emit$$"JP,u,s done\n\t"
13165 $$emit$$"J$cop,u,s $labl\n\t"
13166 $$emit$$"done:"
13167 }
13168 %}
13169 size(4);
13170 opcode(0x70);
13171 ins_encode %{
13172 Label* l = $labl$$label;
13173 emit_cc(cbuf, $primary, Assembler::parity);
13174 int parity_disp = -1;
13175 if ($cop$$cmpcode == Assembler::notEqual) {
13176 parity_disp = l ? (l->loc_pos() - (cbuf.code_size() + 1)) : 0;
13177 } else if ($cop$$cmpcode == Assembler::equal) {
13178 parity_disp = 2;
13179 } else {
13180 ShouldNotReachHere();
13181 }
13182 emit_d8(cbuf, parity_disp);
13183 emit_cc(cbuf, $primary, $cop$$cmpcode);
13184 int disp = l ? (l->loc_pos() - (cbuf.code_size() + 1)) : 0;
13185 emit_d8(cbuf, disp);
13186 assert(-128 <= disp && disp <= 127, "Displacement too large for short jmp");
13187 assert(-128 <= parity_disp && parity_disp <= 127, "Displacement too large for short jmp");
13188 %}
13189 ins_pipe(pipe_jcc);
13190 ins_pc_relative(1);
13191 ins_short_branch(1);
13192 %}
13193
13194 // ============================================================================
13195 // Long Compare
13196 //
13197 // Currently we hold longs in 2 registers. Comparing such values efficiently
13198 // is tricky. The flavor of compare used depends on whether we are testing
13199 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit.
13200 // The GE test is the negated LT test. The LE test can be had by commuting
13201 // the operands (yielding a GE test) and then negating; negate again for the
13202 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the
13203 // NE test is negated from that.
13204
13205 // Due to a shortcoming in the ADLC, it mixes up expressions like:
13206 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the
13207 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections
13208 // are collapsed internally in the ADLC's dfa-gen code. The match for
13209 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the
13210 // foo match ends up with the wrong leaf. One fix is to not match both
13211 // reg-reg and reg-zero forms of long-compare. This is unfortunate because
13212 // both forms beat the trinary form of long-compare and both are very useful
13213 // on Intel which has so few registers.
13214
13215 // Manifest a CmpL result in an integer register. Very painful.
13216 // This is the test to avoid.
13217 instruct cmpL3_reg_reg(eSIRegI dst, eRegL src1, eRegL src2, eFlagsReg flags ) %{
13218 match(Set dst (CmpL3 src1 src2));
13219 effect( KILL flags );
13220 ins_cost(1000);
13221 format %{ "XOR $dst,$dst\n\t"
13222 "CMP $src1.hi,$src2.hi\n\t"
13223 "JLT,s m_one\n\t"
13224 "JGT,s p_one\n\t"
13225 "CMP $src1.lo,$src2.lo\n\t"
13226 "JB,s m_one\n\t"
13227 "JEQ,s done\n"
13228 "p_one:\tINC $dst\n\t"
13229 "JMP,s done\n"
13230 "m_one:\tDEC $dst\n"
13231 "done:" %}
13232 ins_encode %{
13233 Label p_one, m_one, done;
13234 __ xorptr($dst$$Register, $dst$$Register);
13235 __ cmpl(HIGH_FROM_LOW($src1$$Register), HIGH_FROM_LOW($src2$$Register));
13236 __ jccb(Assembler::less, m_one);
13237 __ jccb(Assembler::greater, p_one);
13238 __ cmpl($src1$$Register, $src2$$Register);
13239 __ jccb(Assembler::below, m_one);
13240 __ jccb(Assembler::equal, done);
13241 __ bind(p_one);
13242 __ incrementl($dst$$Register);
13243 __ jmpb(done);
13244 __ bind(m_one);
13245 __ decrementl($dst$$Register);
13246 __ bind(done);
13247 %}
13248 ins_pipe( pipe_slow );
13249 %}
13250
13251 //======
13252 // Manifest a CmpL result in the normal flags. Only good for LT or GE
13253 // compares. Can be used for LE or GT compares by reversing arguments.
13254 // NOT GOOD FOR EQ/NE tests.
13255 instruct cmpL_zero_flags_LTGE( flagsReg_long_LTGE flags, eRegL src, immL0 zero ) %{
13256 match( Set flags (CmpL src zero ));
13257 ins_cost(100);
13258 format %{ "TEST $src.hi,$src.hi" %}
13259 opcode(0x85);
13260 ins_encode( OpcP, RegReg_Hi2( src, src ) );
13261 ins_pipe( ialu_cr_reg_reg );
13262 %}
13263
13264 // Manifest a CmpL result in the normal flags. Only good for LT or GE
13265 // compares. Can be used for LE or GT compares by reversing arguments.
13266 // NOT GOOD FOR EQ/NE tests.
13267 instruct cmpL_reg_flags_LTGE( flagsReg_long_LTGE flags, eRegL src1, eRegL src2, eRegI tmp ) %{
13268 match( Set flags (CmpL src1 src2 ));
13269 effect( TEMP tmp );
13270 ins_cost(300);
13271 format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t"
13272 "MOV $tmp,$src1.hi\n\t"
13273 "SBB $tmp,$src2.hi\t! Compute flags for long compare" %}
13274 ins_encode( long_cmp_flags2( src1, src2, tmp ) );
13275 ins_pipe( ialu_cr_reg_reg );
13276 %}
13277
13278 // Long compares reg < zero/req OR reg >= zero/req.
13279 // Just a wrapper for a normal branch, plus the predicate test.
13280 instruct cmpL_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, label labl) %{
13281 match(If cmp flags);
13282 effect(USE labl);
13283 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
13284 expand %{
13285 jmpCon(cmp,flags,labl); // JLT or JGE...
13286 %}
13287 %}
13288
13289 // Compare 2 longs and CMOVE longs.
13290 instruct cmovLL_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, eRegL src) %{
13291 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
13292 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
13293 ins_cost(400);
13294 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
13295 "CMOV$cmp $dst.hi,$src.hi" %}
13296 opcode(0x0F,0x40);
13297 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
13298 ins_pipe( pipe_cmov_reg_long );
13299 %}
13300
13301 instruct cmovLL_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, load_long_memory src) %{
13302 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
13303 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
13304 ins_cost(500);
13305 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
13306 "CMOV$cmp $dst.hi,$src.hi" %}
13307 opcode(0x0F,0x40);
13308 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
13309 ins_pipe( pipe_cmov_reg_long );
13310 %}
13311
13312 // Compare 2 longs and CMOVE ints.
13313 instruct cmovII_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegI dst, eRegI src) %{
13314 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
13315 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
13316 ins_cost(200);
13317 format %{ "CMOV$cmp $dst,$src" %}
13318 opcode(0x0F,0x40);
13319 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
13320 ins_pipe( pipe_cmov_reg );
13321 %}
13322
13323 instruct cmovII_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegI dst, memory src) %{
13324 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
13325 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
13326 ins_cost(250);
13327 format %{ "CMOV$cmp $dst,$src" %}
13328 opcode(0x0F,0x40);
13329 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
13330 ins_pipe( pipe_cmov_mem );
13331 %}
13332
13333 // Compare 2 longs and CMOVE ints.
13334 instruct cmovPP_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegP dst, eRegP src) %{
13335 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
13336 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
13337 ins_cost(200);
13338 format %{ "CMOV$cmp $dst,$src" %}
13339 opcode(0x0F,0x40);
13340 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
13341 ins_pipe( pipe_cmov_reg );
13342 %}
13343
13344 // Compare 2 longs and CMOVE doubles
13345 instruct cmovDD_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regD dst, regD src) %{
13346 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
13347 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
13348 ins_cost(200);
13349 expand %{
13350 fcmovD_regS(cmp,flags,dst,src);
13351 %}
13352 %}
13353
13354 // Compare 2 longs and CMOVE doubles
13355 instruct cmovXDD_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regXD dst, regXD src) %{
13356 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
13357 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
13358 ins_cost(200);
13359 expand %{
13360 fcmovXD_regS(cmp,flags,dst,src);
13361 %}
13362 %}
13363
13364 instruct cmovFF_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regF dst, regF src) %{
13365 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
13366 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
13367 ins_cost(200);
13368 expand %{
13369 fcmovF_regS(cmp,flags,dst,src);
13370 %}
13371 %}
13372
13373 instruct cmovXX_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regX dst, regX src) %{
13374 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
13375 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
13376 ins_cost(200);
13377 expand %{
13378 fcmovX_regS(cmp,flags,dst,src);
13379 %}
13380 %}
13381
13382 //======
13383 // Manifest a CmpL result in the normal flags. Only good for EQ/NE compares.
13384 instruct cmpL_zero_flags_EQNE( flagsReg_long_EQNE flags, eRegL src, immL0 zero, eRegI tmp ) %{
13385 match( Set flags (CmpL src zero ));
13386 effect(TEMP tmp);
13387 ins_cost(200);
13388 format %{ "MOV $tmp,$src.lo\n\t"
13389 "OR $tmp,$src.hi\t! Long is EQ/NE 0?" %}
13390 ins_encode( long_cmp_flags0( src, tmp ) );
13391 ins_pipe( ialu_reg_reg_long );
13392 %}
13393
13394 // Manifest a CmpL result in the normal flags. Only good for EQ/NE compares.
13395 instruct cmpL_reg_flags_EQNE( flagsReg_long_EQNE flags, eRegL src1, eRegL src2 ) %{
13396 match( Set flags (CmpL src1 src2 ));
13397 ins_cost(200+300);
13398 format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t"
13399 "JNE,s skip\n\t"
13400 "CMP $src1.hi,$src2.hi\n\t"
13401 "skip:\t" %}
13402 ins_encode( long_cmp_flags1( src1, src2 ) );
13403 ins_pipe( ialu_cr_reg_reg );
13404 %}
13405
13406 // Long compare reg == zero/reg OR reg != zero/reg
13407 // Just a wrapper for a normal branch, plus the predicate test.
13408 instruct cmpL_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, label labl) %{
13409 match(If cmp flags);
13410 effect(USE labl);
13411 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
13412 expand %{
13413 jmpCon(cmp,flags,labl); // JEQ or JNE...
13414 %}
13415 %}
13416
13417 // Compare 2 longs and CMOVE longs.
13418 instruct cmovLL_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, eRegL src) %{
13419 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
13420 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
13421 ins_cost(400);
13422 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
13423 "CMOV$cmp $dst.hi,$src.hi" %}
13424 opcode(0x0F,0x40);
13425 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
13426 ins_pipe( pipe_cmov_reg_long );
13427 %}
13428
13429 instruct cmovLL_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, load_long_memory src) %{
13430 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
13431 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
13432 ins_cost(500);
13433 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
13434 "CMOV$cmp $dst.hi,$src.hi" %}
13435 opcode(0x0F,0x40);
13436 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
13437 ins_pipe( pipe_cmov_reg_long );
13438 %}
13439
13440 // Compare 2 longs and CMOVE ints.
13441 instruct cmovII_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegI dst, eRegI src) %{
13442 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
13443 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
13444 ins_cost(200);
13445 format %{ "CMOV$cmp $dst,$src" %}
13446 opcode(0x0F,0x40);
13447 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
13448 ins_pipe( pipe_cmov_reg );
13449 %}
13450
13451 instruct cmovII_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegI dst, memory src) %{
13452 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
13453 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
13454 ins_cost(250);
13455 format %{ "CMOV$cmp $dst,$src" %}
13456 opcode(0x0F,0x40);
13457 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
13458 ins_pipe( pipe_cmov_mem );
13459 %}
13460
13461 // Compare 2 longs and CMOVE ints.
13462 instruct cmovPP_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegP dst, eRegP src) %{
13463 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
13464 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
13465 ins_cost(200);
13466 format %{ "CMOV$cmp $dst,$src" %}
13467 opcode(0x0F,0x40);
13468 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
13469 ins_pipe( pipe_cmov_reg );
13470 %}
13471
13472 // Compare 2 longs and CMOVE doubles
13473 instruct cmovDD_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regD dst, regD src) %{
13474 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
13475 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
13476 ins_cost(200);
13477 expand %{
13478 fcmovD_regS(cmp,flags,dst,src);
13479 %}
13480 %}
13481
13482 // Compare 2 longs and CMOVE doubles
13483 instruct cmovXDD_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regXD dst, regXD src) %{
13484 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
13485 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
13486 ins_cost(200);
13487 expand %{
13488 fcmovXD_regS(cmp,flags,dst,src);
13489 %}
13490 %}
13491
13492 instruct cmovFF_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regF dst, regF src) %{
13493 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
13494 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
13495 ins_cost(200);
13496 expand %{
13497 fcmovF_regS(cmp,flags,dst,src);
13498 %}
13499 %}
13500
13501 instruct cmovXX_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regX dst, regX src) %{
13502 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
13503 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
13504 ins_cost(200);
13505 expand %{
13506 fcmovX_regS(cmp,flags,dst,src);
13507 %}
13508 %}
13509
13510 //======
13511 // Manifest a CmpL result in the normal flags. Only good for LE or GT compares.
13512 // Same as cmpL_reg_flags_LEGT except must negate src
13513 instruct cmpL_zero_flags_LEGT( flagsReg_long_LEGT flags, eRegL src, immL0 zero, eRegI tmp ) %{
13514 match( Set flags (CmpL src zero ));
13515 effect( TEMP tmp );
13516 ins_cost(300);
13517 format %{ "XOR $tmp,$tmp\t# Long compare for -$src < 0, use commuted test\n\t"
13518 "CMP $tmp,$src.lo\n\t"
13519 "SBB $tmp,$src.hi\n\t" %}
13520 ins_encode( long_cmp_flags3(src, tmp) );
13521 ins_pipe( ialu_reg_reg_long );
13522 %}
13523
13524 // Manifest a CmpL result in the normal flags. Only good for LE or GT compares.
13525 // Same as cmpL_reg_flags_LTGE except operands swapped. Swapping operands
13526 // requires a commuted test to get the same result.
13527 instruct cmpL_reg_flags_LEGT( flagsReg_long_LEGT flags, eRegL src1, eRegL src2, eRegI tmp ) %{
13528 match( Set flags (CmpL src1 src2 ));
13529 effect( TEMP tmp );
13530 ins_cost(300);
13531 format %{ "CMP $src2.lo,$src1.lo\t! Long compare, swapped operands, use with commuted test\n\t"
13532 "MOV $tmp,$src2.hi\n\t"
13533 "SBB $tmp,$src1.hi\t! Compute flags for long compare" %}
13534 ins_encode( long_cmp_flags2( src2, src1, tmp ) );
13535 ins_pipe( ialu_cr_reg_reg );
13536 %}
13537
13538 // Long compares reg < zero/req OR reg >= zero/req.
13539 // Just a wrapper for a normal branch, plus the predicate test
13540 instruct cmpL_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, label labl) %{
13541 match(If cmp flags);
13542 effect(USE labl);
13543 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le );
13544 ins_cost(300);
13545 expand %{
13546 jmpCon(cmp,flags,labl); // JGT or JLE...
13547 %}
13548 %}
13549
13550 // Compare 2 longs and CMOVE longs.
13551 instruct cmovLL_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, eRegL src) %{
13552 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
13553 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
13554 ins_cost(400);
13555 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
13556 "CMOV$cmp $dst.hi,$src.hi" %}
13557 opcode(0x0F,0x40);
13558 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
13559 ins_pipe( pipe_cmov_reg_long );
13560 %}
13561
13562 instruct cmovLL_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, load_long_memory src) %{
13563 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
13564 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
13565 ins_cost(500);
13566 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
13567 "CMOV$cmp $dst.hi,$src.hi+4" %}
13568 opcode(0x0F,0x40);
13569 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
13570 ins_pipe( pipe_cmov_reg_long );
13571 %}
13572
13573 // Compare 2 longs and CMOVE ints.
13574 instruct cmovII_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegI dst, eRegI src) %{
13575 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
13576 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
13577 ins_cost(200);
13578 format %{ "CMOV$cmp $dst,$src" %}
13579 opcode(0x0F,0x40);
13580 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
13581 ins_pipe( pipe_cmov_reg );
13582 %}
13583
13584 instruct cmovII_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegI dst, memory src) %{
13585 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
13586 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
13587 ins_cost(250);
13588 format %{ "CMOV$cmp $dst,$src" %}
13589 opcode(0x0F,0x40);
13590 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
13591 ins_pipe( pipe_cmov_mem );
13592 %}
13593
13594 // Compare 2 longs and CMOVE ptrs.
13595 instruct cmovPP_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegP dst, eRegP src) %{
13596 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
13597 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
13598 ins_cost(200);
13599 format %{ "CMOV$cmp $dst,$src" %}
13600 opcode(0x0F,0x40);
13601 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
13602 ins_pipe( pipe_cmov_reg );
13603 %}
13604
13605 // Compare 2 longs and CMOVE doubles
13606 instruct cmovDD_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regD dst, regD src) %{
13607 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
13608 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
13609 ins_cost(200);
13610 expand %{
13611 fcmovD_regS(cmp,flags,dst,src);
13612 %}
13613 %}
13614
13615 // Compare 2 longs and CMOVE doubles
13616 instruct cmovXDD_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regXD dst, regXD src) %{
13617 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
13618 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
13619 ins_cost(200);
13620 expand %{
13621 fcmovXD_regS(cmp,flags,dst,src);
13622 %}
13623 %}
13624
13625 instruct cmovFF_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regF dst, regF src) %{
13626 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
13627 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
13628 ins_cost(200);
13629 expand %{
13630 fcmovF_regS(cmp,flags,dst,src);
13631 %}
13632 %}
13633
13634
13635 instruct cmovXX_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regX dst, regX src) %{
13636 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
13637 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
13638 ins_cost(200);
13639 expand %{
13640 fcmovX_regS(cmp,flags,dst,src);
13641 %}
13642 %}
13643
13644
13645 // ============================================================================
13646 // Procedure Call/Return Instructions
13647 // Call Java Static Instruction
13648 // Note: If this code changes, the corresponding ret_addr_offset() and
13649 // compute_padding() functions will have to be adjusted.
13650 instruct CallStaticJavaDirect(method meth) %{
13651 match(CallStaticJava);
13652 effect(USE meth);
13653
13654 ins_cost(300);
13655 format %{ "CALL,static " %}
13656 opcode(0xE8); /* E8 cd */
13657 ins_encode( pre_call_FPU,
13658 Java_Static_Call( meth ),
13659 call_epilog,
13660 post_call_FPU );
13661 ins_pipe( pipe_slow );
13662 ins_pc_relative(1);
13663 ins_alignment(4);
13664 %}
13665
13666 // Call Java Dynamic Instruction
13667 // Note: If this code changes, the corresponding ret_addr_offset() and
13668 // compute_padding() functions will have to be adjusted.
13669 instruct CallDynamicJavaDirect(method meth) %{
13670 match(CallDynamicJava);
13671 effect(USE meth);
13672
13673 ins_cost(300);
13674 format %{ "MOV EAX,(oop)-1\n\t"
13675 "CALL,dynamic" %}
13676 opcode(0xE8); /* E8 cd */
13677 ins_encode( pre_call_FPU,
13678 Java_Dynamic_Call( meth ),
13679 call_epilog,
13680 post_call_FPU );
13681 ins_pipe( pipe_slow );
13682 ins_pc_relative(1);
13683 ins_alignment(4);
13684 %}
13685
13686 // Call Runtime Instruction
13687 instruct CallRuntimeDirect(method meth) %{
13688 match(CallRuntime );
13689 effect(USE meth);
13690
13691 ins_cost(300);
13692 format %{ "CALL,runtime " %}
13693 opcode(0xE8); /* E8 cd */
13694 // Use FFREEs to clear entries in float stack
13695 ins_encode( pre_call_FPU,
13696 FFree_Float_Stack_All,
13697 Java_To_Runtime( meth ),
13698 post_call_FPU );
13699 ins_pipe( pipe_slow );
13700 ins_pc_relative(1);
13701 %}
13702
13703 // Call runtime without safepoint
13704 instruct CallLeafDirect(method meth) %{
13705 match(CallLeaf);
13706 effect(USE meth);
13707
13708 ins_cost(300);
13709 format %{ "CALL_LEAF,runtime " %}
13710 opcode(0xE8); /* E8 cd */
13711 ins_encode( pre_call_FPU,
13712 FFree_Float_Stack_All,
13713 Java_To_Runtime( meth ),
13714 Verify_FPU_For_Leaf, post_call_FPU );
13715 ins_pipe( pipe_slow );
13716 ins_pc_relative(1);
13717 %}
13718
13719 instruct CallLeafNoFPDirect(method meth) %{
13720 match(CallLeafNoFP);
13721 effect(USE meth);
13722
13723 ins_cost(300);
13724 format %{ "CALL_LEAF_NOFP,runtime " %}
13725 opcode(0xE8); /* E8 cd */
13726 ins_encode(Java_To_Runtime(meth));
13727 ins_pipe( pipe_slow );
13728 ins_pc_relative(1);
13729 %}
13730
13731
13732 // Return Instruction
13733 // Remove the return address & jump to it.
13734 instruct Ret() %{
13735 match(Return);
13736 format %{ "RET" %}
13737 opcode(0xC3);
13738 ins_encode(OpcP);
13739 ins_pipe( pipe_jmp );
13740 %}
13741
13742 // Tail Call; Jump from runtime stub to Java code.
13743 // Also known as an 'interprocedural jump'.
13744 // Target of jump will eventually return to caller.
13745 // TailJump below removes the return address.
13746 instruct TailCalljmpInd(eRegP_no_EBP jump_target, eBXRegP method_oop) %{
13747 match(TailCall jump_target method_oop );
13748 ins_cost(300);
13749 format %{ "JMP $jump_target \t# EBX holds method oop" %}
13750 opcode(0xFF, 0x4); /* Opcode FF /4 */
13751 ins_encode( OpcP, RegOpc(jump_target) );
13752 ins_pipe( pipe_jmp );
13753 %}
13754
13755
13756 // Tail Jump; remove the return address; jump to target.
13757 // TailCall above leaves the return address around.
13758 instruct tailjmpInd(eRegP_no_EBP jump_target, eAXRegP ex_oop) %{
13759 match( TailJump jump_target ex_oop );
13760 ins_cost(300);
13761 format %{ "POP EDX\t# pop return address into dummy\n\t"
13762 "JMP $jump_target " %}
13763 opcode(0xFF, 0x4); /* Opcode FF /4 */
13764 ins_encode( enc_pop_rdx,
13765 OpcP, RegOpc(jump_target) );
13766 ins_pipe( pipe_jmp );
13767 %}
13768
13769 // Create exception oop: created by stack-crawling runtime code.
13770 // Created exception is now available to this handler, and is setup
13771 // just prior to jumping to this handler. No code emitted.
13772 instruct CreateException( eAXRegP ex_oop )
13773 %{
13774 match(Set ex_oop (CreateEx));
13775
13776 size(0);
13777 // use the following format syntax
13778 format %{ "# exception oop is in EAX; no code emitted" %}
13779 ins_encode();
13780 ins_pipe( empty );
13781 %}
13782
13783
13784 // Rethrow exception:
13785 // The exception oop will come in the first argument position.
13786 // Then JUMP (not call) to the rethrow stub code.
13787 instruct RethrowException()
13788 %{
13789 match(Rethrow);
13790
13791 // use the following format syntax
13792 format %{ "JMP rethrow_stub" %}
13793 ins_encode(enc_rethrow);
13794 ins_pipe( pipe_jmp );
13795 %}
13796
13797 // inlined locking and unlocking
13798
13799
13800 instruct cmpFastLock( eFlagsReg cr, eRegP object, eRegP box, eAXRegI tmp, eRegP scr) %{
13801 match( Set cr (FastLock object box) );
13802 effect( TEMP tmp, TEMP scr );
13803 ins_cost(300);
13804 format %{ "FASTLOCK $object, $box KILLS $tmp,$scr" %}
13805 ins_encode( Fast_Lock(object,box,tmp,scr) );
13806 ins_pipe( pipe_slow );
13807 ins_pc_relative(1);
13808 %}
13809
13810 instruct cmpFastUnlock( eFlagsReg cr, eRegP object, eAXRegP box, eRegP tmp ) %{
13811 match( Set cr (FastUnlock object box) );
13812 effect( TEMP tmp );
13813 ins_cost(300);
13814 format %{ "FASTUNLOCK $object, $box, $tmp" %}
13815 ins_encode( Fast_Unlock(object,box,tmp) );
13816 ins_pipe( pipe_slow );
13817 ins_pc_relative(1);
13818 %}
13819
13820
13821
13822 // ============================================================================
13823 // Safepoint Instruction
13824 instruct safePoint_poll(eFlagsReg cr) %{
13825 match(SafePoint);
13826 effect(KILL cr);
13827
13828 // TODO-FIXME: we currently poll at offset 0 of the safepoint polling page.
13829 // On SPARC that might be acceptable as we can generate the address with
13830 // just a sethi, saving an or. By polling at offset 0 we can end up
13831 // putting additional pressure on the index-0 in the D$. Because of
13832 // alignment (just like the situation at hand) the lower indices tend
13833 // to see more traffic. It'd be better to change the polling address
13834 // to offset 0 of the last $line in the polling page.
13835
13836 format %{ "TSTL #polladdr,EAX\t! Safepoint: poll for GC" %}
13837 ins_cost(125);
13838 size(6) ;
13839 ins_encode( Safepoint_Poll() );
13840 ins_pipe( ialu_reg_mem );
13841 %}
13842
13843 //----------PEEPHOLE RULES-----------------------------------------------------
13844 // These must follow all instruction definitions as they use the names
13845 // defined in the instructions definitions.
13846 //
13847 // peepmatch ( root_instr_name [preceding_instruction]* );
13848 //
13849 // peepconstraint %{
13850 // (instruction_number.operand_name relational_op instruction_number.operand_name
13851 // [, ...] );
13852 // // instruction numbers are zero-based using left to right order in peepmatch
13853 //
13854 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
13855 // // provide an instruction_number.operand_name for each operand that appears
13856 // // in the replacement instruction's match rule
13857 //
13858 // ---------VM FLAGS---------------------------------------------------------
13859 //
13860 // All peephole optimizations can be turned off using -XX:-OptoPeephole
13861 //
13862 // Each peephole rule is given an identifying number starting with zero and
13863 // increasing by one in the order seen by the parser. An individual peephole
13864 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
13865 // on the command-line.
13866 //
13867 // ---------CURRENT LIMITATIONS----------------------------------------------
13868 //
13869 // Only match adjacent instructions in same basic block
13870 // Only equality constraints
13871 // Only constraints between operands, not (0.dest_reg == EAX_enc)
13872 // Only one replacement instruction
13873 //
13874 // ---------EXAMPLE----------------------------------------------------------
13875 //
13876 // // pertinent parts of existing instructions in architecture description
13877 // instruct movI(eRegI dst, eRegI src) %{
13878 // match(Set dst (CopyI src));
13879 // %}
13880 //
13881 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
13882 // match(Set dst (AddI dst src));
13883 // effect(KILL cr);
13884 // %}
13885 //
13886 // // Change (inc mov) to lea
13887 // peephole %{
13888 // // increment preceeded by register-register move
13889 // peepmatch ( incI_eReg movI );
13890 // // require that the destination register of the increment
13891 // // match the destination register of the move
13892 // peepconstraint ( 0.dst == 1.dst );
13893 // // construct a replacement instruction that sets
13894 // // the destination to ( move's source register + one )
13895 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13896 // %}
13897 //
13898 // Implementation no longer uses movX instructions since
13899 // machine-independent system no longer uses CopyX nodes.
13900 //
13901 // peephole %{
13902 // peepmatch ( incI_eReg movI );
13903 // peepconstraint ( 0.dst == 1.dst );
13904 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13905 // %}
13906 //
13907 // peephole %{
13908 // peepmatch ( decI_eReg movI );
13909 // peepconstraint ( 0.dst == 1.dst );
13910 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13911 // %}
13912 //
13913 // peephole %{
13914 // peepmatch ( addI_eReg_imm movI );
13915 // peepconstraint ( 0.dst == 1.dst );
13916 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13917 // %}
13918 //
13919 // peephole %{
13920 // peepmatch ( addP_eReg_imm movP );
13921 // peepconstraint ( 0.dst == 1.dst );
13922 // peepreplace ( leaP_eReg_immI( 0.dst 1.src 0.src ) );
13923 // %}
13924
13925 // // Change load of spilled value to only a spill
13926 // instruct storeI(memory mem, eRegI src) %{
13927 // match(Set mem (StoreI mem src));
13928 // %}
13929 //
13930 // instruct loadI(eRegI dst, memory mem) %{
13931 // match(Set dst (LoadI mem));
13932 // %}
13933 //
13934 peephole %{
13935 peepmatch ( loadI storeI );
13936 peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
13937 peepreplace ( storeI( 1.mem 1.mem 1.src ) );
13938 %}
13939
13940 //----------SMARTSPILL RULES---------------------------------------------------
13941 // These must follow all instruction definitions as they use the names
13942 // defined in the instructions definitions.