1264 address double_address = __ double_constant(x);
1265 cbuf.insts()->set_mark_off(mark); // preserve mark across masm shift
1266 emit_d32_reloc(cbuf,
1267 (int)double_address,
1268 internal_word_Relocation::spec(double_address),
1269 RELOC_DISP32);
1270 }
1271
1272 static void emit_float_constant(CodeBuffer& cbuf, float x) {
1273 int mark = cbuf.insts()->mark_off();
1274 MacroAssembler _masm(&cbuf);
1275 address float_address = __ float_constant(x);
1276 cbuf.insts()->set_mark_off(mark); // preserve mark across masm shift
1277 emit_d32_reloc(cbuf,
1278 (int)float_address,
1279 internal_word_Relocation::spec(float_address),
1280 RELOC_DISP32);
1281 }
1282
1283
1284 int Matcher::regnum_to_fpu_offset(int regnum) {
1285 return regnum - 32; // The FP registers are in the second chunk
1286 }
1287
1288 bool is_positive_zero_float(jfloat f) {
1289 return jint_cast(f) == jint_cast(0.0F);
1290 }
1291
1292 bool is_positive_one_float(jfloat f) {
1293 return jint_cast(f) == jint_cast(1.0F);
1294 }
1295
1296 bool is_positive_zero_double(jdouble d) {
1297 return jlong_cast(d) == jlong_cast(0.0);
1298 }
1299
1300 bool is_positive_one_double(jdouble d) {
1301 return jlong_cast(d) == jlong_cast(1.0);
1302 }
1303
6627
6628 format %{ "BSWAP $dst" %}
6629 opcode(0x0F, 0xC8);
6630 ins_encode( OpcP, OpcSReg(dst) );
6631 ins_pipe( ialu_reg );
6632 %}
6633
6634 instruct bytes_reverse_long(eRegL dst) %{
6635 match(Set dst (ReverseBytesL dst));
6636
6637 format %{ "BSWAP $dst.lo\n\t"
6638 "BSWAP $dst.hi\n\t"
6639 "XCHG $dst.lo $dst.hi" %}
6640
6641 ins_cost(125);
6642 ins_encode( bswap_long_bytes(dst) );
6643 ins_pipe( ialu_reg_reg);
6644 %}
6645
6646
6647 //---------- Population Count Instructions -------------------------------------
6648
6649 instruct popCountI(eRegI dst, eRegI src) %{
6650 predicate(UsePopCountInstruction);
6651 match(Set dst (PopCountI src));
6652
6653 format %{ "POPCNT $dst, $src" %}
6654 ins_encode %{
6655 __ popcntl($dst$$Register, $src$$Register);
6656 %}
6657 ins_pipe(ialu_reg);
6658 %}
6659
6660 instruct popCountI_mem(eRegI dst, memory mem) %{
6661 predicate(UsePopCountInstruction);
6662 match(Set dst (PopCountI (LoadI mem)));
6663
6664 format %{ "POPCNT $dst, $mem" %}
6665 ins_encode %{
6666 __ popcntl($dst$$Register, $mem$$Address);
|
1264 address double_address = __ double_constant(x);
1265 cbuf.insts()->set_mark_off(mark); // preserve mark across masm shift
1266 emit_d32_reloc(cbuf,
1267 (int)double_address,
1268 internal_word_Relocation::spec(double_address),
1269 RELOC_DISP32);
1270 }
1271
1272 static void emit_float_constant(CodeBuffer& cbuf, float x) {
1273 int mark = cbuf.insts()->mark_off();
1274 MacroAssembler _masm(&cbuf);
1275 address float_address = __ float_constant(x);
1276 cbuf.insts()->set_mark_off(mark); // preserve mark across masm shift
1277 emit_d32_reloc(cbuf,
1278 (int)float_address,
1279 internal_word_Relocation::spec(float_address),
1280 RELOC_DISP32);
1281 }
1282
1283
1284 const bool Matcher::match_rule_supported(int opcode) {
1285 if (!has_match_rule(opcode))
1286 return false;
1287
1288 return true; // Per default match rules are supported.
1289 }
1290
1291 int Matcher::regnum_to_fpu_offset(int regnum) {
1292 return regnum - 32; // The FP registers are in the second chunk
1293 }
1294
1295 bool is_positive_zero_float(jfloat f) {
1296 return jint_cast(f) == jint_cast(0.0F);
1297 }
1298
1299 bool is_positive_one_float(jfloat f) {
1300 return jint_cast(f) == jint_cast(1.0F);
1301 }
1302
1303 bool is_positive_zero_double(jdouble d) {
1304 return jlong_cast(d) == jlong_cast(0.0);
1305 }
1306
1307 bool is_positive_one_double(jdouble d) {
1308 return jlong_cast(d) == jlong_cast(1.0);
1309 }
1310
6634
6635 format %{ "BSWAP $dst" %}
6636 opcode(0x0F, 0xC8);
6637 ins_encode( OpcP, OpcSReg(dst) );
6638 ins_pipe( ialu_reg );
6639 %}
6640
6641 instruct bytes_reverse_long(eRegL dst) %{
6642 match(Set dst (ReverseBytesL dst));
6643
6644 format %{ "BSWAP $dst.lo\n\t"
6645 "BSWAP $dst.hi\n\t"
6646 "XCHG $dst.lo $dst.hi" %}
6647
6648 ins_cost(125);
6649 ins_encode( bswap_long_bytes(dst) );
6650 ins_pipe( ialu_reg_reg);
6651 %}
6652
6653
6654 //---------- Zeros Count Instructions ------------------------------------------
6655
6656 instruct countLeadingZerosI(eRegI dst, eRegI src, eFlagsReg cr) %{
6657 predicate(UseCountLeadingZerosInstruction);
6658 match(Set dst (CountLeadingZerosI src));
6659 effect(KILL cr);
6660
6661 format %{ "LZCNT $dst, $src\t# count leading zeros (int)" %}
6662 ins_encode %{
6663 __ lzcntl($dst$$Register, $src$$Register);
6664 %}
6665 ins_pipe(ialu_reg);
6666 %}
6667
6668 instruct countLeadingZerosI_bsr(eRegI dst, eRegI src, eFlagsReg cr) %{
6669 predicate(!UseCountLeadingZerosInstruction);
6670 match(Set dst (CountLeadingZerosI src));
6671 effect(KILL cr);
6672
6673 format %{ "BSR $dst, $src\t# count leading zeros (int)\n\t"
6674 "JNZ skip\n\t"
6675 "MOV $dst, -1\n"
6676 "skip:\n\t"
6677 "NEG $dst\n\t"
6678 "ADD $dst, 31" %}
6679 ins_encode %{
6680 Register Rdst = $dst$$Register;
6681 Register Rsrc = $src$$Register;
6682 Label skip;
6683 __ bsrl(Rdst, Rsrc);
6684 __ jccb(Assembler::notZero, skip);
6685 __ movl(Rdst, -1);
6686 __ bind(skip);
6687 __ negl(Rdst);
6688 __ addl(Rdst, BitsPerInt - 1);
6689 %}
6690 ins_pipe(ialu_reg);
6691 %}
6692
6693 instruct countLeadingZerosL(eRegI dst, eRegL src, eFlagsReg cr) %{
6694 predicate(UseCountLeadingZerosInstruction);
6695 match(Set dst (CountLeadingZerosL src));
6696 effect(TEMP dst, KILL cr);
6697
6698 format %{ "LZCNT $dst, $src.hi\t# count leading zeros (long)\n\t"
6699 "JNC done\n\t"
6700 "LZCNT $dst, $src.lo\n\t"
6701 "ADD $dst, 32\n"
6702 "done:" %}
6703 ins_encode %{
6704 Register Rdst = $dst$$Register;
6705 Register Rsrc = $src$$Register;
6706 Label done;
6707 __ lzcntl(Rdst, HIGH_FROM_LOW(Rsrc));
6708 __ jccb(Assembler::carryClear, done);
6709 __ lzcntl(Rdst, Rsrc);
6710 __ addl(Rdst, BitsPerInt);
6711 __ bind(done);
6712 %}
6713 ins_pipe(ialu_reg);
6714 %}
6715
6716 instruct countLeadingZerosL_bsr(eRegI dst, eRegL src, eFlagsReg cr) %{
6717 predicate(!UseCountLeadingZerosInstruction);
6718 match(Set dst (CountLeadingZerosL src));
6719 effect(TEMP dst, KILL cr);
6720
6721 format %{ "BSR $dst, $src.hi\t# count leading zeros (long)\n\t"
6722 "JZ msw_is_zero\n\t"
6723 "ADD $dst, 32\n\t"
6724 "JMP not_zero\n"
6725 "msw_is_zero:\n\t"
6726 "BSR $dst, $src.lo\n\t"
6727 "JNZ not_zero\n\t"
6728 "MOV $dst, -1\n"
6729 "not_zero:\n\t"
6730 "NEG $dst\n\t"
6731 "ADD $dst, 63\n" %}
6732 ins_encode %{
6733 Register Rdst = $dst$$Register;
6734 Register Rsrc = $src$$Register;
6735 Label msw_is_zero;
6736 Label not_zero;
6737 __ bsrl(Rdst, HIGH_FROM_LOW(Rsrc));
6738 __ jccb(Assembler::zero, msw_is_zero);
6739 __ addl(Rdst, BitsPerInt);
6740 __ jmpb(not_zero);
6741 __ bind(msw_is_zero);
6742 __ bsrl(Rdst, Rsrc);
6743 __ jccb(Assembler::notZero, not_zero);
6744 __ movl(Rdst, -1);
6745 __ bind(not_zero);
6746 __ negl(Rdst);
6747 __ addl(Rdst, BitsPerLong - 1);
6748 %}
6749 ins_pipe(ialu_reg);
6750 %}
6751
6752 instruct countTrailingZerosI(eRegI dst, eRegI src, eFlagsReg cr) %{
6753 match(Set dst (CountTrailingZerosI src));
6754 effect(KILL cr);
6755
6756 format %{ "BSF $dst, $src\t# count trailing zeros (int)\n\t"
6757 "JNZ done\n\t"
6758 "MOV $dst, 32\n"
6759 "done:" %}
6760 ins_encode %{
6761 Register Rdst = $dst$$Register;
6762 Label done;
6763 __ bsfl(Rdst, $src$$Register);
6764 __ jccb(Assembler::notZero, done);
6765 __ movl(Rdst, BitsPerInt);
6766 __ bind(done);
6767 %}
6768 ins_pipe(ialu_reg);
6769 %}
6770
6771 instruct countTrailingZerosL(eRegI dst, eRegL src, eFlagsReg cr) %{
6772 match(Set dst (CountTrailingZerosL src));
6773 effect(TEMP dst, KILL cr);
6774
6775 format %{ "BSF $dst, $src.lo\t# count trailing zeros (long)\n\t"
6776 "JNZ done\n\t"
6777 "BSF $dst, $src.hi\n\t"
6778 "JNZ msw_not_zero\n\t"
6779 "MOV $dst, 32\n"
6780 "msw_not_zero:\n\t"
6781 "ADD $dst, 32\n"
6782 "done:" %}
6783 ins_encode %{
6784 Register Rdst = $dst$$Register;
6785 Register Rsrc = $src$$Register;
6786 Label msw_not_zero;
6787 Label done;
6788 __ bsfl(Rdst, Rsrc);
6789 __ jccb(Assembler::notZero, done);
6790 __ bsfl(Rdst, HIGH_FROM_LOW(Rsrc));
6791 __ jccb(Assembler::notZero, msw_not_zero);
6792 __ movl(Rdst, BitsPerInt);
6793 __ bind(msw_not_zero);
6794 __ addl(Rdst, BitsPerInt);
6795 __ bind(done);
6796 %}
6797 ins_pipe(ialu_reg);
6798 %}
6799
6800
6801 //---------- Population Count Instructions -------------------------------------
6802
6803 instruct popCountI(eRegI dst, eRegI src) %{
6804 predicate(UsePopCountInstruction);
6805 match(Set dst (PopCountI src));
6806
6807 format %{ "POPCNT $dst, $src" %}
6808 ins_encode %{
6809 __ popcntl($dst$$Register, $src$$Register);
6810 %}
6811 ins_pipe(ialu_reg);
6812 %}
6813
6814 instruct popCountI_mem(eRegI dst, memory mem) %{
6815 predicate(UsePopCountInstruction);
6816 match(Set dst (PopCountI (LoadI mem)));
6817
6818 format %{ "POPCNT $dst, $mem" %}
6819 ins_encode %{
6820 __ popcntl($dst$$Register, $mem$$Address);
|