1 /*
2 * Copyright 1997-2008 Sun Microsystems, Inc. All Rights Reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
20 * CA 95054 USA or visit www.sun.com if you need additional information or
21 * have any questions.
22 *
23 */
24
25 class Compile;
26 class Node;
27 class MachNode;
28 class MachTypeNode;
29 class MachOper;
30
31 //---------------------------Matcher-------------------------------------------
32 class Matcher : public PhaseTransform {
33 friend class VMStructs;
34 // Private arena of State objects
35 ResourceArea _states_arena;
36
37 VectorSet _visited; // Visit bits
38
39 // Used to control the Label pass
40 VectorSet _shared; // Shared Ideal Node
41 VectorSet _dontcare; // Nothing the matcher cares about
42
43 // Private methods which perform the actual matching and reduction
44 // Walks the label tree, generating machine nodes
45 MachNode *ReduceInst( State *s, int rule, Node *&mem);
46 void ReduceInst_Chain_Rule( State *s, int rule, Node *&mem, MachNode *mach);
47 uint ReduceInst_Interior(State *s, int rule, Node *&mem, MachNode *mach, uint num_opnds);
48 void ReduceOper( State *s, int newrule, Node *&mem, MachNode *mach );
49
50 // If this node already matched using "rule", return the MachNode for it.
51 MachNode* find_shared_node(Node* n, uint rule);
52
53 // Convert a dense opcode number to an expanded rule number
54 const int *_reduceOp;
55 const int *_leftOp;
56 const int *_rightOp;
57
58 // Map dense opcode number to info on when rule is swallowed constant.
59 const bool *_swallowed;
60
61 // Map dense rule number to determine if this is an instruction chain rule
62 const uint _begin_inst_chain_rule;
63 const uint _end_inst_chain_rule;
64
65 // We want to clone constants and possible CmpI-variants.
66 // If we do not clone CmpI, then we can have many instances of
67 // condition codes alive at once. This is OK on some chips and
68 // bad on others. Hence the machine-dependent table lookup.
69 const char *_must_clone;
70
71 // Find shared Nodes, or Nodes that otherwise are Matcher roots
72 void find_shared( Node *n );
73
74 // Debug and profile information for nodes in old space:
75 GrowableArray<Node_Notes*>* _old_node_note_array;
76
77 // Node labeling iterator for instruction selection
78 Node *Label_Root( const Node *n, State *svec, Node *control, const Node *mem );
79
80 Node *transform( Node *dummy );
81
82 Node_List &_proj_list; // For Machine nodes killing many values
83
84 Node_Array _shared_nodes;
85
86 debug_only(Node_Array _old2new_map;) // Map roots of ideal-trees to machine-roots
87 debug_only(Node_Array _new2old_map;) // Maps machine nodes back to ideal
88
89 // Accessors for the inherited field PhaseTransform::_nodes:
90 void grow_new_node_array(uint idx_limit) {
91 _nodes.map(idx_limit-1, NULL);
92 }
93 bool has_new_node(const Node* n) const {
94 return _nodes.at(n->_idx) != NULL;
95 }
96 Node* new_node(const Node* n) const {
97 assert(has_new_node(n), "set before get");
98 return _nodes.at(n->_idx);
99 }
100 void set_new_node(const Node* n, Node *nn) {
101 assert(!has_new_node(n), "set only once");
102 _nodes.map(n->_idx, nn);
103 }
104
105 #ifdef ASSERT
106 // Make sure only new nodes are reachable from this node
107 void verify_new_nodes_only(Node* root);
108
109 Node* _mem_node; // Ideal memory node consumed by mach node
110 #endif
111
112 // Mach node for ConP #NULL
113 MachNode* _mach_null;
114
115 public:
116 int LabelRootDepth;
117 static const int base2reg[]; // Map Types to machine register types
118 // Convert ideal machine register to a register mask for spill-loads
119 static const RegMask *idealreg2regmask[];
120 RegMask *idealreg2spillmask[_last_machine_leaf];
121 RegMask *idealreg2debugmask[_last_machine_leaf];
122 void init_spill_mask( Node *ret );
123 // Convert machine register number to register mask
124 static uint mreg2regmask_max;
125 static RegMask mreg2regmask[];
126 static RegMask STACK_ONLY_mask;
127
128 MachNode* mach_null() const { return _mach_null; }
129
130 bool is_shared( Node *n ) { return _shared.test(n->_idx) != 0; }
131 void set_shared( Node *n ) { _shared.set(n->_idx); }
132 bool is_visited( Node *n ) { return _visited.test(n->_idx) != 0; }
133 void set_visited( Node *n ) { _visited.set(n->_idx); }
134 bool is_dontcare( Node *n ) { return _dontcare.test(n->_idx) != 0; }
135 void set_dontcare( Node *n ) { _dontcare.set(n->_idx); }
136
137 // Mode bit to tell DFA and expand rules whether we are running after
138 // (or during) register selection. Usually, the matcher runs before,
139 // but it will also get called to generate post-allocation spill code.
140 // In this situation, it is a deadly error to attempt to allocate more
141 // temporary registers.
142 bool _allocation_started;
143
144 // Machine register names
145 static const char *regName[];
146 // Machine register encodings
147 static const unsigned char _regEncode[];
148 // Machine Node names
149 const char **_ruleName;
150 // Rules that are cheaper to rematerialize than to spill
151 static const uint _begin_rematerialize;
152 static const uint _end_rematerialize;
153
154 // An array of chars, from 0 to _last_Mach_Reg.
155 // No Save = 'N' (for register windows)
156 // Save on Entry = 'E'
157 // Save on Call = 'C'
158 // Always Save = 'A' (same as SOE + SOC)
159 const char *_register_save_policy;
160 const char *_c_reg_save_policy;
161 // Convert a machine register to a machine register type, so-as to
162 // properly match spill code.
163 const int *_register_save_type;
164 // Maps from machine register to boolean; true if machine register can
165 // be holding a call argument in some signature.
166 static bool can_be_java_arg( int reg );
167 // Maps from machine register to boolean; true if machine register holds
168 // a spillable argument.
169 static bool is_spillable_arg( int reg );
170
171 // List of IfFalse or IfTrue Nodes that indicate a taken null test.
172 // List is valid in the post-matching space.
173 Node_List _null_check_tests;
174 void collect_null_checks( Node *proj, Node *orig_proj );
175 void validate_null_checks( );
176
177 Matcher( Node_List &proj_list );
178
179 // Select instructions for entire method
180 void match( );
181 // Helper for match
182 OptoReg::Name warp_incoming_stk_arg( VMReg reg );
183
184 // Transform, then walk. Does implicit DCE while walking.
185 // Name changed from "transform" to avoid it being virtual.
186 Node *xform( Node *old_space_node, int Nodes );
187
188 // Match a single Ideal Node - turn it into a 1-Node tree; Label & Reduce.
189 MachNode *match_tree( const Node *n );
190 MachNode *match_sfpt( SafePointNode *sfpt );
191 // Helper for match_sfpt
192 OptoReg::Name warp_outgoing_stk_arg( VMReg reg, OptoReg::Name begin_out_arg_area, OptoReg::Name &out_arg_limit_per_call );
193
194 // Initialize first stack mask and related masks.
195 void init_first_stack_mask();
196
197 // If we should save-on-entry this register
198 bool is_save_on_entry( int reg );
199
200 // Fixup the save-on-entry registers
201 void Fixup_Save_On_Entry( );
202
203 // --- Frame handling ---
204
205 // Register number of the stack slot corresponding to the incoming SP.
206 // Per the Big Picture in the AD file, it is:
207 // SharedInfo::stack0 + locks + in_preserve_stack_slots + pad2.
208 OptoReg::Name _old_SP;
209
210 // Register number of the stack slot corresponding to the highest incoming
211 // argument on the stack. Per the Big Picture in the AD file, it is:
212 // _old_SP + out_preserve_stack_slots + incoming argument size.
213 OptoReg::Name _in_arg_limit;
214
215 // Register number of the stack slot corresponding to the new SP.
216 // Per the Big Picture in the AD file, it is:
217 // _in_arg_limit + pad0
218 OptoReg::Name _new_SP;
219
220 // Register number of the stack slot corresponding to the highest outgoing
221 // argument on the stack. Per the Big Picture in the AD file, it is:
222 // _new_SP + max outgoing arguments of all calls
223 OptoReg::Name _out_arg_limit;
224
225 OptoRegPair *_parm_regs; // Array of machine registers per argument
226 RegMask *_calling_convention_mask; // Array of RegMasks per argument
227
228 // Does matcher have a match rule for this ideal node?
229 static const bool has_match_rule(int opcode);
230 static const bool _hasMatchRule[_last_opcode];
231
232 // Does matcher have a match rule for this ideal node and is the
233 // predicate (if there is one) true?
234 // NOTE: If this function is used more commonly in the future, ADLC
235 // should generate this one.
236 static const bool match_rule_supported(int opcode);
237
238 // Used to determine if we have fast l2f conversion
239 // USII has it, USIII doesn't
240 static const bool convL2FSupported(void);
241
242 // Vector width in bytes
243 static const uint vector_width_in_bytes(void);
244
245 // Vector ideal reg
246 static const uint vector_ideal_reg(void);
247
248 // Used to determine a "low complexity" 64-bit constant. (Zero is simple.)
249 // The standard of comparison is one (StoreL ConL) vs. two (StoreI ConI).
250 // Depends on the details of 64-bit constant generation on the CPU.
251 static const bool isSimpleConstant64(jlong con);
252
253 // These calls are all generated by the ADLC
254
255 // TRUE - grows up, FALSE - grows down (Intel)
256 virtual bool stack_direction() const;
257
258 // Java-Java calling convention
259 // (what you use when Java calls Java)
260
261 // Alignment of stack in bytes, standard Intel word alignment is 4.
262 // Sparc probably wants at least double-word (8).
263 static uint stack_alignment_in_bytes();
264 // Alignment of stack, measured in stack slots.
265 // The size of stack slots is defined by VMRegImpl::stack_slot_size.
266 static uint stack_alignment_in_slots() {
267 return stack_alignment_in_bytes() / (VMRegImpl::stack_slot_size);
268 }
269
270 // Array mapping arguments to registers. Argument 0 is usually the 'this'
271 // pointer. Registers can include stack-slots and regular registers.
272 static void calling_convention( BasicType *, VMRegPair *, uint len, bool is_outgoing );
273
274 // Convert a sig into a calling convention register layout
275 // and find interesting things about it.
276 static OptoReg::Name find_receiver( bool is_outgoing );
277 // Return address register. On Intel it is a stack-slot. On PowerPC
278 // it is the Link register. On Sparc it is r31?
279 virtual OptoReg::Name return_addr() const;
280 RegMask _return_addr_mask;
281 // Return value register. On Intel it is EAX. On Sparc i0/o0.
282 static OptoRegPair return_value(int ideal_reg, bool is_outgoing);
283 static OptoRegPair c_return_value(int ideal_reg, bool is_outgoing);
284 RegMask _return_value_mask;
285 // Inline Cache Register
286 static OptoReg::Name inline_cache_reg();
287 static const RegMask &inline_cache_reg_mask();
288 static int inline_cache_reg_encode();
289
290 // Register for DIVI projection of divmodI
291 static RegMask divI_proj_mask();
292 // Register for MODI projection of divmodI
293 static RegMask modI_proj_mask();
294
295 // Register for DIVL projection of divmodL
296 static RegMask divL_proj_mask();
297 // Register for MODL projection of divmodL
298 static RegMask modL_proj_mask();
299
300 // Java-Interpreter calling convention
301 // (what you use when calling between compiled-Java and Interpreted-Java
302
303 // Number of callee-save + always-save registers
304 // Ignores frame pointer and "special" registers
305 static int number_of_saved_registers();
306
307 // The Method-klass-holder may be passed in the inline_cache_reg
308 // and then expanded into the inline_cache_reg and a method_oop register
309
310 static OptoReg::Name interpreter_method_oop_reg();
311 static const RegMask &interpreter_method_oop_reg_mask();
312 static int interpreter_method_oop_reg_encode();
313
314 static OptoReg::Name compiler_method_oop_reg();
315 static const RegMask &compiler_method_oop_reg_mask();
316 static int compiler_method_oop_reg_encode();
317
318 // Interpreter's Frame Pointer Register
319 static OptoReg::Name interpreter_frame_pointer_reg();
320 static const RegMask &interpreter_frame_pointer_reg_mask();
321
322 // Java-Native calling convention
323 // (what you use when intercalling between Java and C++ code)
324
325 // Array mapping arguments to registers. Argument 0 is usually the 'this'
326 // pointer. Registers can include stack-slots and regular registers.
327 static void c_calling_convention( BasicType*, VMRegPair *, uint );
328 // Frame pointer. The frame pointer is kept at the base of the stack
329 // and so is probably the stack pointer for most machines. On Intel
330 // it is ESP. On the PowerPC it is R1. On Sparc it is SP.
331 OptoReg::Name c_frame_pointer() const;
332 static RegMask c_frame_ptr_mask;
333
334 // !!!!! Special stuff for building ScopeDescs
335 virtual int regnum_to_fpu_offset(int regnum);
336
337 // Is this branch offset small enough to be addressed by a short branch?
338 bool is_short_branch_offset(int rule, int offset);
339
340 // Optional scaling for the parameter to the ClearArray/CopyArray node.
341 static const bool init_array_count_is_in_bytes;
342
343 // Threshold small size (in bytes) for a ClearArray/CopyArray node.
344 // Anything this size or smaller may get converted to discrete scalar stores.
345 static const int init_array_short_size;
346
347 // Should the Matcher clone shifts on addressing modes, expecting them to
348 // be subsumed into complex addressing expressions or compute them into
349 // registers? True for Intel but false for most RISCs
350 static const bool clone_shift_expressions;
351
352 // Is it better to copy float constants, or load them directly from memory?
353 // Intel can load a float constant from a direct address, requiring no
354 // extra registers. Most RISCs will have to materialize an address into a
355 // register first, so they may as well materialize the constant immediately.
356 static const bool rematerialize_float_constants;
357
358 // If CPU can load and store mis-aligned doubles directly then no fixup is
359 // needed. Else we split the double into 2 integer pieces and move it
360 // piece-by-piece. Only happens when passing doubles into C code or when
361 // calling i2c adapters as the Java calling convention forces doubles to be
362 // aligned.
363 static const bool misaligned_doubles_ok;
364
365 // Perform a platform dependent implicit null fixup. This is needed
366 // on windows95 to take care of some unusual register constraints.
367 void pd_implicit_null_fixup(MachNode *load, uint idx);
368
369 // Advertise here if the CPU requires explicit rounding operations
370 // to implement the UseStrictFP mode.
371 static const bool strict_fp_requires_explicit_rounding;
372
373 // Do floats take an entire double register or just half?
374 static const bool float_in_double;
375 // Do ints take an entire long register or just half?
376 static const bool int_in_long;
377
378 // This routine is run whenever a graph fails to match.
379 // If it returns, the compiler should bailout to interpreter without error.
380 // In non-product mode, SoftMatchFailure is false to detect non-canonical
381 // graphs. Print a message and exit.
382 static void soft_match_failure() {
383 if( SoftMatchFailure ) return;
384 else { fatal("SoftMatchFailure is not allowed except in product"); }
385 }
386
387 // Used by the DFA in dfa_sparc.cpp. Check for a prior FastLock
388 // acting as an Acquire and thus we don't need an Acquire here. We
389 // retain the Node to act as a compiler ordering barrier.
390 static bool prior_fast_lock( const Node *acq );
391
392 // Used by the DFA in dfa_sparc.cpp. Check for a following
393 // FastUnLock acting as a Release and thus we don't need a Release
394 // here. We retain the Node to act as a compiler ordering barrier.
395 static bool post_fast_unlock( const Node *rel );
396
397 // Check for a following volatile memory barrier without an
398 // intervening load and thus we don't need a barrier here. We
399 // retain the Node to act as a compiler ordering barrier.
400 static bool post_store_load_barrier(const Node* mb);
401
402
403 #ifdef ASSERT
404 void dump_old2new_map(); // machine-independent to machine-dependent
405
406 Node* find_old_node(Node* new_node) {
407 return _new2old_map[new_node->_idx];
408 }
409 #endif
410 };