1 //
2 // Copyright 1997-2009 Sun Microsystems, Inc. All Rights Reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
9 // This code is distributed in the hope that it will be useful, but WITHOUT
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
15 // You should have received a copy of the GNU General Public License version
16 // 2 along with this work; if not, write to the Free Software Foundation,
17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 //
19 // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
20 // CA 95054 USA or visit www.sun.com if you need additional information or
21 // have any questions.
22 //
23 //
24
25 // X86 Architecture Description File
26
27 //----------REGISTER DEFINITION BLOCK------------------------------------------
28 // This information is used by the matcher and the register allocator to
29 // describe individual registers and classes of registers within the target
30 // archtecture.
31
32 register %{
33 //----------Architecture Description Register Definitions----------------------
34 // General Registers
35 // "reg_def" name ( register save type, C convention save type,
36 // ideal register type, encoding );
37 // Register Save Types:
38 //
39 // NS = No-Save: The register allocator assumes that these registers
40 // can be used without saving upon entry to the method, &
41 // that they do not need to be saved at call sites.
42 //
43 // SOC = Save-On-Call: The register allocator assumes that these registers
44 // can be used without saving upon entry to the method,
45 // but that they must be saved at call sites.
46 //
47 // SOE = Save-On-Entry: The register allocator assumes that these registers
48 // must be saved before using them upon entry to the
49 // method, but they do not need to be saved at call
50 // sites.
51 //
52 // AS = Always-Save: The register allocator assumes that these registers
53 // must be saved before using them upon entry to the
54 // method, & that they must be saved at call sites.
55 //
56 // Ideal Register Type is used to determine how to save & restore a
57 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
58 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
59 //
60 // The encoding number is the actual bit-pattern placed into the opcodes.
61
62 // General Registers
63 // Previously set EBX, ESI, and EDI as save-on-entry for java code
64 // Turn off SOE in java-code due to frequent use of uncommon-traps.
65 // Now that allocator is better, turn on ESI and EDI as SOE registers.
66
67 reg_def EBX(SOC, SOE, Op_RegI, 3, rbx->as_VMReg());
68 reg_def ECX(SOC, SOC, Op_RegI, 1, rcx->as_VMReg());
69 reg_def ESI(SOC, SOE, Op_RegI, 6, rsi->as_VMReg());
70 reg_def EDI(SOC, SOE, Op_RegI, 7, rdi->as_VMReg());
71 // now that adapter frames are gone EBP is always saved and restored by the prolog/epilog code
72 reg_def EBP(NS, SOE, Op_RegI, 5, rbp->as_VMReg());
73 reg_def EDX(SOC, SOC, Op_RegI, 2, rdx->as_VMReg());
74 reg_def EAX(SOC, SOC, Op_RegI, 0, rax->as_VMReg());
75 reg_def ESP( NS, NS, Op_RegI, 4, rsp->as_VMReg());
76
77 // Special Registers
78 reg_def EFLAGS(SOC, SOC, 0, 8, VMRegImpl::Bad());
79
80 // Float registers. We treat TOS/FPR0 special. It is invisible to the
81 // allocator, and only shows up in the encodings.
82 reg_def FPR0L( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad());
83 reg_def FPR0H( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad());
84 // Ok so here's the trick FPR1 is really st(0) except in the midst
85 // of emission of assembly for a machnode. During the emission the fpu stack
86 // is pushed making FPR1 == st(1) temporarily. However at any safepoint
87 // the stack will not have this element so FPR1 == st(0) from the
88 // oopMap viewpoint. This same weirdness with numbering causes
89 // instruction encoding to have to play games with the register
90 // encode to correct for this 0/1 issue. See MachSpillCopyNode::implementation
91 // where it does flt->flt moves to see an example
92 //
93 reg_def FPR1L( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg());
94 reg_def FPR1H( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg()->next());
95 reg_def FPR2L( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg());
96 reg_def FPR2H( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg()->next());
97 reg_def FPR3L( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg());
98 reg_def FPR3H( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg()->next());
99 reg_def FPR4L( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg());
100 reg_def FPR4H( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg()->next());
101 reg_def FPR5L( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg());
102 reg_def FPR5H( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg()->next());
103 reg_def FPR6L( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg());
104 reg_def FPR6H( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg()->next());
105 reg_def FPR7L( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg());
106 reg_def FPR7H( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg()->next());
107
108 // XMM registers. 128-bit registers or 4 words each, labeled a-d.
109 // Word a in each register holds a Float, words ab hold a Double.
110 // We currently do not use the SIMD capabilities, so registers cd
111 // are unused at the moment.
112 reg_def XMM0a( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg());
113 reg_def XMM0b( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()->next());
114 reg_def XMM1a( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg());
115 reg_def XMM1b( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()->next());
116 reg_def XMM2a( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg());
117 reg_def XMM2b( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()->next());
118 reg_def XMM3a( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg());
119 reg_def XMM3b( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()->next());
120 reg_def XMM4a( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg());
121 reg_def XMM4b( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()->next());
122 reg_def XMM5a( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg());
123 reg_def XMM5b( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()->next());
124 reg_def XMM6a( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg());
125 reg_def XMM6b( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()->next());
126 reg_def XMM7a( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg());
127 reg_def XMM7b( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()->next());
128
129 // Specify priority of register selection within phases of register
130 // allocation. Highest priority is first. A useful heuristic is to
131 // give registers a low priority when they are required by machine
132 // instructions, like EAX and EDX. Registers which are used as
133 // pairs must fall on an even boundary (witness the FPR#L's in this list).
134 // For the Intel integer registers, the equivalent Long pairs are
135 // EDX:EAX, EBX:ECX, and EDI:EBP.
136 alloc_class chunk0( ECX, EBX, EBP, EDI, EAX, EDX, ESI, ESP,
137 FPR0L, FPR0H, FPR1L, FPR1H, FPR2L, FPR2H,
138 FPR3L, FPR3H, FPR4L, FPR4H, FPR5L, FPR5H,
139 FPR6L, FPR6H, FPR7L, FPR7H );
140
141 alloc_class chunk1( XMM0a, XMM0b,
142 XMM1a, XMM1b,
143 XMM2a, XMM2b,
144 XMM3a, XMM3b,
145 XMM4a, XMM4b,
146 XMM5a, XMM5b,
147 XMM6a, XMM6b,
148 XMM7a, XMM7b, EFLAGS);
149
150
151 //----------Architecture Description Register Classes--------------------------
152 // Several register classes are automatically defined based upon information in
153 // this architecture description.
154 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ )
155 // 2) reg_class compiler_method_oop_reg ( /* as def'd in frame section */ )
156 // 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ )
157 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
158 //
159 // Class for all registers
160 reg_class any_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX, ESP);
161 // Class for general registers
162 reg_class e_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX);
163 // Class for general registers which may be used for implicit null checks on win95
164 // Also safe for use by tailjump. We don't want to allocate in rbp,
165 reg_class e_reg_no_rbp(EAX, EDX, EDI, ESI, ECX, EBX);
166 // Class of "X" registers
167 reg_class x_reg(EBX, ECX, EDX, EAX);
168 // Class of registers that can appear in an address with no offset.
169 // EBP and ESP require an extra instruction byte for zero offset.
170 // Used in fast-unlock
171 reg_class p_reg(EDX, EDI, ESI, EBX);
172 // Class for general registers not including ECX
173 reg_class ncx_reg(EAX, EDX, EBP, EDI, ESI, EBX);
174 // Class for general registers not including EAX
175 reg_class nax_reg(EDX, EDI, ESI, ECX, EBX);
176 // Class for general registers not including EAX or EBX.
177 reg_class nabx_reg(EDX, EDI, ESI, ECX, EBP);
178 // Class of EAX (for multiply and divide operations)
179 reg_class eax_reg(EAX);
180 // Class of EBX (for atomic add)
181 reg_class ebx_reg(EBX);
182 // Class of ECX (for shift and JCXZ operations and cmpLTMask)
183 reg_class ecx_reg(ECX);
184 // Class of EDX (for multiply and divide operations)
185 reg_class edx_reg(EDX);
186 // Class of EDI (for synchronization)
187 reg_class edi_reg(EDI);
188 // Class of ESI (for synchronization)
189 reg_class esi_reg(ESI);
190 // Singleton class for interpreter's stack pointer
191 reg_class ebp_reg(EBP);
192 // Singleton class for stack pointer
193 reg_class sp_reg(ESP);
194 // Singleton class for instruction pointer
195 // reg_class ip_reg(EIP);
196 // Singleton class for condition codes
197 reg_class int_flags(EFLAGS);
198 // Class of integer register pairs
199 reg_class long_reg( EAX,EDX, ECX,EBX, EBP,EDI );
200 // Class of integer register pairs that aligns with calling convention
201 reg_class eadx_reg( EAX,EDX );
202 reg_class ebcx_reg( ECX,EBX );
203 // Not AX or DX, used in divides
204 reg_class nadx_reg( EBX,ECX,ESI,EDI,EBP );
205
206 // Floating point registers. Notice FPR0 is not a choice.
207 // FPR0 is not ever allocated; we use clever encodings to fake
208 // a 2-address instructions out of Intels FP stack.
209 reg_class flt_reg( FPR1L,FPR2L,FPR3L,FPR4L,FPR5L,FPR6L,FPR7L );
210
211 // make a register class for SSE registers
212 reg_class xmm_reg(XMM0a, XMM1a, XMM2a, XMM3a, XMM4a, XMM5a, XMM6a, XMM7a);
213
214 // make a double register class for SSE2 registers
215 reg_class xdb_reg(XMM0a,XMM0b, XMM1a,XMM1b, XMM2a,XMM2b, XMM3a,XMM3b,
216 XMM4a,XMM4b, XMM5a,XMM5b, XMM6a,XMM6b, XMM7a,XMM7b );
217
218 reg_class dbl_reg( FPR1L,FPR1H, FPR2L,FPR2H, FPR3L,FPR3H,
219 FPR4L,FPR4H, FPR5L,FPR5H, FPR6L,FPR6H,
220 FPR7L,FPR7H );
221
222 reg_class flt_reg0( FPR1L );
223 reg_class dbl_reg0( FPR1L,FPR1H );
224 reg_class dbl_reg1( FPR2L,FPR2H );
225 reg_class dbl_notreg0( FPR2L,FPR2H, FPR3L,FPR3H, FPR4L,FPR4H,
226 FPR5L,FPR5H, FPR6L,FPR6H, FPR7L,FPR7H );
227
228 // XMM6 and XMM7 could be used as temporary registers for long, float and
229 // double values for SSE2.
230 reg_class xdb_reg6( XMM6a,XMM6b );
231 reg_class xdb_reg7( XMM7a,XMM7b );
232 %}
233
234
235 //----------SOURCE BLOCK-------------------------------------------------------
236 // This is a block of C++ code which provides values, functions, and
237 // definitions necessary in the rest of the architecture description
238 source %{
239 #define RELOC_IMM32 Assembler::imm_operand
240 #define RELOC_DISP32 Assembler::disp32_operand
241
242 #define __ _masm.
243
244 // How to find the high register of a Long pair, given the low register
245 #define HIGH_FROM_LOW(x) ((x)+2)
246
247 // These masks are used to provide 128-bit aligned bitmasks to the XMM
248 // instructions, to allow sign-masking or sign-bit flipping. They allow
249 // fast versions of NegF/NegD and AbsF/AbsD.
250
251 // Note: 'double' and 'long long' have 32-bits alignment on x86.
252 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) {
253 // Use the expression (adr)&(~0xF) to provide 128-bits aligned address
254 // of 128-bits operands for SSE instructions.
255 jlong *operand = (jlong*)(((uintptr_t)adr)&((uintptr_t)(~0xF)));
256 // Store the value to a 128-bits operand.
257 operand[0] = lo;
258 operand[1] = hi;
259 return operand;
260 }
261
262 // Buffer for 128-bits masks used by SSE instructions.
263 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment)
264
265 // Static initialization during VM startup.
266 static jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF));
267 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF));
268 static jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], CONST64(0x8000000080000000), CONST64(0x8000000080000000));
269 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], CONST64(0x8000000000000000), CONST64(0x8000000000000000));
270
271 // !!!!! Special hack to get all type of calls to specify the byte offset
272 // from the start of the call to the point where the return address
273 // will point.
274 int MachCallStaticJavaNode::ret_addr_offset() {
275 return 5 + (Compile::current()->in_24_bit_fp_mode() ? 6 : 0); // 5 bytes from start of call to where return address points
276 }
277
278 int MachCallDynamicJavaNode::ret_addr_offset() {
279 return 10 + (Compile::current()->in_24_bit_fp_mode() ? 6 : 0); // 10 bytes from start of call to where return address points
280 }
281
282 static int sizeof_FFree_Float_Stack_All = -1;
283
284 int MachCallRuntimeNode::ret_addr_offset() {
285 assert(sizeof_FFree_Float_Stack_All != -1, "must have been emitted already");
286 return sizeof_FFree_Float_Stack_All + 5 + (Compile::current()->in_24_bit_fp_mode() ? 6 : 0);
287 }
288
289 // Indicate if the safepoint node needs the polling page as an input.
290 // Since x86 does have absolute addressing, it doesn't.
291 bool SafePointNode::needs_polling_address_input() {
292 return false;
293 }
294
295 //
296 // Compute padding required for nodes which need alignment
297 //
298
299 // The address of the call instruction needs to be 4-byte aligned to
300 // ensure that it does not span a cache line so that it can be patched.
301 int CallStaticJavaDirectNode::compute_padding(int current_offset) const {
302 if (Compile::current()->in_24_bit_fp_mode())
303 current_offset += 6; // skip fldcw in pre_call_FPU, if any
304 current_offset += 1; // skip call opcode byte
305 return round_to(current_offset, alignment_required()) - current_offset;
306 }
307
308 // The address of the call instruction needs to be 4-byte aligned to
309 // ensure that it does not span a cache line so that it can be patched.
310 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const {
311 if (Compile::current()->in_24_bit_fp_mode())
312 current_offset += 6; // skip fldcw in pre_call_FPU, if any
313 current_offset += 5; // skip MOV instruction
314 current_offset += 1; // skip call opcode byte
315 return round_to(current_offset, alignment_required()) - current_offset;
316 }
317
318 #ifndef PRODUCT
319 void MachBreakpointNode::format( PhaseRegAlloc *, outputStream* st ) const {
320 st->print("INT3");
321 }
322 #endif
323
324 // EMIT_RM()
325 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) {
326 unsigned char c = (unsigned char)((f1 << 6) | (f2 << 3) | f3);
327 *(cbuf.code_end()) = c;
328 cbuf.set_code_end(cbuf.code_end() + 1);
329 }
330
331 // EMIT_CC()
332 void emit_cc(CodeBuffer &cbuf, int f1, int f2) {
333 unsigned char c = (unsigned char)( f1 | f2 );
334 *(cbuf.code_end()) = c;
335 cbuf.set_code_end(cbuf.code_end() + 1);
336 }
337
338 // EMIT_OPCODE()
339 void emit_opcode(CodeBuffer &cbuf, int code) {
340 *(cbuf.code_end()) = (unsigned char)code;
341 cbuf.set_code_end(cbuf.code_end() + 1);
342 }
343
344 // EMIT_OPCODE() w/ relocation information
345 void emit_opcode(CodeBuffer &cbuf, int code, relocInfo::relocType reloc, int offset = 0) {
346 cbuf.relocate(cbuf.inst_mark() + offset, reloc);
347 emit_opcode(cbuf, code);
348 }
349
350 // EMIT_D8()
351 void emit_d8(CodeBuffer &cbuf, int d8) {
352 *(cbuf.code_end()) = (unsigned char)d8;
353 cbuf.set_code_end(cbuf.code_end() + 1);
354 }
355
356 // EMIT_D16()
357 void emit_d16(CodeBuffer &cbuf, int d16) {
358 *((short *)(cbuf.code_end())) = d16;
359 cbuf.set_code_end(cbuf.code_end() + 2);
360 }
361
362 // EMIT_D32()
363 void emit_d32(CodeBuffer &cbuf, int d32) {
364 *((int *)(cbuf.code_end())) = d32;
365 cbuf.set_code_end(cbuf.code_end() + 4);
366 }
367
368 // emit 32 bit value and construct relocation entry from relocInfo::relocType
369 void emit_d32_reloc(CodeBuffer &cbuf, int d32, relocInfo::relocType reloc,
370 int format) {
371 cbuf.relocate(cbuf.inst_mark(), reloc, format);
372
373 *((int *)(cbuf.code_end())) = d32;
374 cbuf.set_code_end(cbuf.code_end() + 4);
375 }
376
377 // emit 32 bit value and construct relocation entry from RelocationHolder
378 void emit_d32_reloc(CodeBuffer &cbuf, int d32, RelocationHolder const& rspec,
379 int format) {
380 #ifdef ASSERT
381 if (rspec.reloc()->type() == relocInfo::oop_type && d32 != 0 && d32 != (int)Universe::non_oop_word()) {
382 assert(oop(d32)->is_oop() && (ScavengeRootsInCode || !oop(d32)->is_scavengable()), "cannot embed scavengable oops in code");
383 }
384 #endif
385 cbuf.relocate(cbuf.inst_mark(), rspec, format);
386
387 *((int *)(cbuf.code_end())) = d32;
388 cbuf.set_code_end(cbuf.code_end() + 4);
389 }
390
391 // Access stack slot for load or store
392 void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp) {
393 emit_opcode( cbuf, opcode ); // (e.g., FILD [ESP+src])
394 if( -128 <= disp && disp <= 127 ) {
395 emit_rm( cbuf, 0x01, rm_field, ESP_enc ); // R/M byte
396 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
397 emit_d8 (cbuf, disp); // Displacement // R/M byte
398 } else {
399 emit_rm( cbuf, 0x02, rm_field, ESP_enc ); // R/M byte
400 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
401 emit_d32(cbuf, disp); // Displacement // R/M byte
402 }
403 }
404
405 // eRegI ereg, memory mem) %{ // emit_reg_mem
406 void encode_RegMem( CodeBuffer &cbuf, int reg_encoding, int base, int index, int scale, int displace, bool displace_is_oop ) {
407 // There is no index & no scale, use form without SIB byte
408 if ((index == 0x4) &&
409 (scale == 0) && (base != ESP_enc)) {
410 // If no displacement, mode is 0x0; unless base is [EBP]
411 if ( (displace == 0) && (base != EBP_enc) ) {
412 emit_rm(cbuf, 0x0, reg_encoding, base);
413 }
414 else { // If 8-bit displacement, mode 0x1
415 if ((displace >= -128) && (displace <= 127)
416 && !(displace_is_oop) ) {
417 emit_rm(cbuf, 0x1, reg_encoding, base);
418 emit_d8(cbuf, displace);
419 }
420 else { // If 32-bit displacement
421 if (base == -1) { // Special flag for absolute address
422 emit_rm(cbuf, 0x0, reg_encoding, 0x5);
423 // (manual lies; no SIB needed here)
424 if ( displace_is_oop ) {
425 emit_d32_reloc(cbuf, displace, relocInfo::oop_type, 1);
426 } else {
427 emit_d32 (cbuf, displace);
428 }
429 }
430 else { // Normal base + offset
431 emit_rm(cbuf, 0x2, reg_encoding, base);
432 if ( displace_is_oop ) {
433 emit_d32_reloc(cbuf, displace, relocInfo::oop_type, 1);
434 } else {
435 emit_d32 (cbuf, displace);
436 }
437 }
438 }
439 }
440 }
441 else { // Else, encode with the SIB byte
442 // If no displacement, mode is 0x0; unless base is [EBP]
443 if (displace == 0 && (base != EBP_enc)) { // If no displacement
444 emit_rm(cbuf, 0x0, reg_encoding, 0x4);
445 emit_rm(cbuf, scale, index, base);
446 }
447 else { // If 8-bit displacement, mode 0x1
448 if ((displace >= -128) && (displace <= 127)
449 && !(displace_is_oop) ) {
450 emit_rm(cbuf, 0x1, reg_encoding, 0x4);
451 emit_rm(cbuf, scale, index, base);
452 emit_d8(cbuf, displace);
453 }
454 else { // If 32-bit displacement
455 if (base == 0x04 ) {
456 emit_rm(cbuf, 0x2, reg_encoding, 0x4);
457 emit_rm(cbuf, scale, index, 0x04);
458 } else {
459 emit_rm(cbuf, 0x2, reg_encoding, 0x4);
460 emit_rm(cbuf, scale, index, base);
461 }
462 if ( displace_is_oop ) {
463 emit_d32_reloc(cbuf, displace, relocInfo::oop_type, 1);
464 } else {
465 emit_d32 (cbuf, displace);
466 }
467 }
468 }
469 }
470 }
471
472
473 void encode_Copy( CodeBuffer &cbuf, int dst_encoding, int src_encoding ) {
474 if( dst_encoding == src_encoding ) {
475 // reg-reg copy, use an empty encoding
476 } else {
477 emit_opcode( cbuf, 0x8B );
478 emit_rm(cbuf, 0x3, dst_encoding, src_encoding );
479 }
480 }
481
482 void encode_CopyXD( CodeBuffer &cbuf, int dst_encoding, int src_encoding ) {
483 if( dst_encoding == src_encoding ) {
484 // reg-reg copy, use an empty encoding
485 } else {
486 MacroAssembler _masm(&cbuf);
487
488 __ movdqa(as_XMMRegister(dst_encoding), as_XMMRegister(src_encoding));
489 }
490 }
491
492
493 //=============================================================================
494 #ifndef PRODUCT
495 void MachPrologNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
496 Compile* C = ra_->C;
497 if( C->in_24_bit_fp_mode() ) {
498 st->print("FLDCW 24 bit fpu control word");
499 st->print_cr(""); st->print("\t");
500 }
501
502 int framesize = C->frame_slots() << LogBytesPerInt;
503 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
504 // Remove two words for return addr and rbp,
505 framesize -= 2*wordSize;
506
507 // Calls to C2R adapters often do not accept exceptional returns.
508 // We require that their callers must bang for them. But be careful, because
509 // some VM calls (such as call site linkage) can use several kilobytes of
510 // stack. But the stack safety zone should account for that.
511 // See bugs 4446381, 4468289, 4497237.
512 if (C->need_stack_bang(framesize)) {
513 st->print_cr("# stack bang"); st->print("\t");
514 }
515 st->print_cr("PUSHL EBP"); st->print("\t");
516
517 if( VerifyStackAtCalls ) { // Majik cookie to verify stack depth
518 st->print("PUSH 0xBADB100D\t# Majik cookie for stack depth check");
519 st->print_cr(""); st->print("\t");
520 framesize -= wordSize;
521 }
522
523 if ((C->in_24_bit_fp_mode() || VerifyStackAtCalls ) && framesize < 128 ) {
524 if (framesize) {
525 st->print("SUB ESP,%d\t# Create frame",framesize);
526 }
527 } else {
528 st->print("SUB ESP,%d\t# Create frame",framesize);
529 }
530 }
531 #endif
532
533
534 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
535 Compile* C = ra_->C;
536
537 if (UseSSE >= 2 && VerifyFPU) {
538 MacroAssembler masm(&cbuf);
539 masm.verify_FPU(0, "FPU stack must be clean on entry");
540 }
541
542 // WARNING: Initial instruction MUST be 5 bytes or longer so that
543 // NativeJump::patch_verified_entry will be able to patch out the entry
544 // code safely. The fldcw is ok at 6 bytes, the push to verify stack
545 // depth is ok at 5 bytes, the frame allocation can be either 3 or
546 // 6 bytes. So if we don't do the fldcw or the push then we must
547 // use the 6 byte frame allocation even if we have no frame. :-(
548 // If method sets FPU control word do it now
549 if( C->in_24_bit_fp_mode() ) {
550 MacroAssembler masm(&cbuf);
551 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
552 }
553
554 int framesize = C->frame_slots() << LogBytesPerInt;
555 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
556 // Remove two words for return addr and rbp,
557 framesize -= 2*wordSize;
558
559 // Calls to C2R adapters often do not accept exceptional returns.
560 // We require that their callers must bang for them. But be careful, because
561 // some VM calls (such as call site linkage) can use several kilobytes of
562 // stack. But the stack safety zone should account for that.
563 // See bugs 4446381, 4468289, 4497237.
564 if (C->need_stack_bang(framesize)) {
565 MacroAssembler masm(&cbuf);
566 masm.generate_stack_overflow_check(framesize);
567 }
568
569 // We always push rbp, so that on return to interpreter rbp, will be
570 // restored correctly and we can correct the stack.
571 emit_opcode(cbuf, 0x50 | EBP_enc);
572
573 if( VerifyStackAtCalls ) { // Majik cookie to verify stack depth
574 emit_opcode(cbuf, 0x68); // push 0xbadb100d
575 emit_d32(cbuf, 0xbadb100d);
576 framesize -= wordSize;
577 }
578
579 if ((C->in_24_bit_fp_mode() || VerifyStackAtCalls ) && framesize < 128 ) {
580 if (framesize) {
581 emit_opcode(cbuf, 0x83); // sub SP,#framesize
582 emit_rm(cbuf, 0x3, 0x05, ESP_enc);
583 emit_d8(cbuf, framesize);
584 }
585 } else {
586 emit_opcode(cbuf, 0x81); // sub SP,#framesize
587 emit_rm(cbuf, 0x3, 0x05, ESP_enc);
588 emit_d32(cbuf, framesize);
589 }
590 C->set_frame_complete(cbuf.code_end() - cbuf.code_begin());
591
592 #ifdef ASSERT
593 if (VerifyStackAtCalls) {
594 Label L;
595 MacroAssembler masm(&cbuf);
596 masm.push(rax);
597 masm.mov(rax, rsp);
598 masm.andptr(rax, StackAlignmentInBytes-1);
599 masm.cmpptr(rax, StackAlignmentInBytes-wordSize);
600 masm.pop(rax);
601 masm.jcc(Assembler::equal, L);
602 masm.stop("Stack is not properly aligned!");
603 masm.bind(L);
604 }
605 #endif
606
607 }
608
609 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
610 return MachNode::size(ra_); // too many variables; just compute it the hard way
611 }
612
613 int MachPrologNode::reloc() const {
614 return 0; // a large enough number
615 }
616
617 //=============================================================================
618 #ifndef PRODUCT
619 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
620 Compile *C = ra_->C;
621 int framesize = C->frame_slots() << LogBytesPerInt;
622 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
623 // Remove two words for return addr and rbp,
624 framesize -= 2*wordSize;
625
626 if( C->in_24_bit_fp_mode() ) {
627 st->print("FLDCW standard control word");
628 st->cr(); st->print("\t");
629 }
630 if( framesize ) {
631 st->print("ADD ESP,%d\t# Destroy frame",framesize);
632 st->cr(); st->print("\t");
633 }
634 st->print_cr("POPL EBP"); st->print("\t");
635 if( do_polling() && C->is_method_compilation() ) {
636 st->print("TEST PollPage,EAX\t! Poll Safepoint");
637 st->cr(); st->print("\t");
638 }
639 }
640 #endif
641
642 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
643 Compile *C = ra_->C;
644
645 // If method set FPU control word, restore to standard control word
646 if( C->in_24_bit_fp_mode() ) {
647 MacroAssembler masm(&cbuf);
648 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
649 }
650
651 int framesize = C->frame_slots() << LogBytesPerInt;
652 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
653 // Remove two words for return addr and rbp,
654 framesize -= 2*wordSize;
655
656 // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here
657
658 if( framesize >= 128 ) {
659 emit_opcode(cbuf, 0x81); // add SP, #framesize
660 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
661 emit_d32(cbuf, framesize);
662 }
663 else if( framesize ) {
664 emit_opcode(cbuf, 0x83); // add SP, #framesize
665 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
666 emit_d8(cbuf, framesize);
667 }
668
669 emit_opcode(cbuf, 0x58 | EBP_enc);
670
671 if( do_polling() && C->is_method_compilation() ) {
672 cbuf.relocate(cbuf.code_end(), relocInfo::poll_return_type, 0);
673 emit_opcode(cbuf,0x85);
674 emit_rm(cbuf, 0x0, EAX_enc, 0x5); // EAX
675 emit_d32(cbuf, (intptr_t)os::get_polling_page());
676 }
677 }
678
679 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
680 Compile *C = ra_->C;
681 // If method set FPU control word, restore to standard control word
682 int size = C->in_24_bit_fp_mode() ? 6 : 0;
683 if( do_polling() && C->is_method_compilation() ) size += 6;
684
685 int framesize = C->frame_slots() << LogBytesPerInt;
686 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
687 // Remove two words for return addr and rbp,
688 framesize -= 2*wordSize;
689
690 size++; // popl rbp,
691
692 if( framesize >= 128 ) {
693 size += 6;
694 } else {
695 size += framesize ? 3 : 0;
696 }
697 return size;
698 }
699
700 int MachEpilogNode::reloc() const {
701 return 0; // a large enough number
702 }
703
704 const Pipeline * MachEpilogNode::pipeline() const {
705 return MachNode::pipeline_class();
706 }
707
708 int MachEpilogNode::safepoint_offset() const { return 0; }
709
710 //=============================================================================
711
712 enum RC { rc_bad, rc_int, rc_float, rc_xmm, rc_stack };
713 static enum RC rc_class( OptoReg::Name reg ) {
714
715 if( !OptoReg::is_valid(reg) ) return rc_bad;
716 if (OptoReg::is_stack(reg)) return rc_stack;
717
718 VMReg r = OptoReg::as_VMReg(reg);
719 if (r->is_Register()) return rc_int;
720 if (r->is_FloatRegister()) {
721 assert(UseSSE < 2, "shouldn't be used in SSE2+ mode");
722 return rc_float;
723 }
724 assert(r->is_XMMRegister(), "must be");
725 return rc_xmm;
726 }
727
728 static int impl_helper( CodeBuffer *cbuf, bool do_size, bool is_load, int offset, int reg,
729 int opcode, const char *op_str, int size, outputStream* st ) {
730 if( cbuf ) {
731 emit_opcode (*cbuf, opcode );
732 encode_RegMem(*cbuf, Matcher::_regEncode[reg], ESP_enc, 0x4, 0, offset, false);
733 #ifndef PRODUCT
734 } else if( !do_size ) {
735 if( size != 0 ) st->print("\n\t");
736 if( opcode == 0x8B || opcode == 0x89 ) { // MOV
737 if( is_load ) st->print("%s %s,[ESP + #%d]",op_str,Matcher::regName[reg],offset);
738 else st->print("%s [ESP + #%d],%s",op_str,offset,Matcher::regName[reg]);
739 } else { // FLD, FST, PUSH, POP
740 st->print("%s [ESP + #%d]",op_str,offset);
741 }
742 #endif
743 }
744 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
745 return size+3+offset_size;
746 }
747
748 // Helper for XMM registers. Extra opcode bits, limited syntax.
749 static int impl_x_helper( CodeBuffer *cbuf, bool do_size, bool is_load,
750 int offset, int reg_lo, int reg_hi, int size, outputStream* st ) {
751 if( cbuf ) {
752 if( reg_lo+1 == reg_hi ) { // double move?
753 if( is_load && !UseXmmLoadAndClearUpper )
754 emit_opcode(*cbuf, 0x66 ); // use 'movlpd' for load
755 else
756 emit_opcode(*cbuf, 0xF2 ); // use 'movsd' otherwise
757 } else {
758 emit_opcode(*cbuf, 0xF3 );
759 }
760 emit_opcode(*cbuf, 0x0F );
761 if( reg_lo+1 == reg_hi && is_load && !UseXmmLoadAndClearUpper )
762 emit_opcode(*cbuf, 0x12 ); // use 'movlpd' for load
763 else
764 emit_opcode(*cbuf, is_load ? 0x10 : 0x11 );
765 encode_RegMem(*cbuf, Matcher::_regEncode[reg_lo], ESP_enc, 0x4, 0, offset, false);
766 #ifndef PRODUCT
767 } else if( !do_size ) {
768 if( size != 0 ) st->print("\n\t");
769 if( reg_lo+1 == reg_hi ) { // double move?
770 if( is_load ) st->print("%s %s,[ESP + #%d]",
771 UseXmmLoadAndClearUpper ? "MOVSD " : "MOVLPD",
772 Matcher::regName[reg_lo], offset);
773 else st->print("MOVSD [ESP + #%d],%s",
774 offset, Matcher::regName[reg_lo]);
775 } else {
776 if( is_load ) st->print("MOVSS %s,[ESP + #%d]",
777 Matcher::regName[reg_lo], offset);
778 else st->print("MOVSS [ESP + #%d],%s",
779 offset, Matcher::regName[reg_lo]);
780 }
781 #endif
782 }
783 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
784 return size+5+offset_size;
785 }
786
787
788 static int impl_movx_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
789 int src_hi, int dst_hi, int size, outputStream* st ) {
790 if( UseXmmRegToRegMoveAll ) {//Use movaps,movapd to move between xmm registers
791 if( cbuf ) {
792 if( (src_lo+1 == src_hi && dst_lo+1 == dst_hi) ) {
793 emit_opcode(*cbuf, 0x66 );
794 }
795 emit_opcode(*cbuf, 0x0F );
796 emit_opcode(*cbuf, 0x28 );
797 emit_rm (*cbuf, 0x3, Matcher::_regEncode[dst_lo], Matcher::_regEncode[src_lo] );
798 #ifndef PRODUCT
799 } else if( !do_size ) {
800 if( size != 0 ) st->print("\n\t");
801 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double move?
802 st->print("MOVAPD %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
803 } else {
804 st->print("MOVAPS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
805 }
806 #endif
807 }
808 return size + ((src_lo+1 == src_hi && dst_lo+1 == dst_hi) ? 4 : 3);
809 } else {
810 if( cbuf ) {
811 emit_opcode(*cbuf, (src_lo+1 == src_hi && dst_lo+1 == dst_hi) ? 0xF2 : 0xF3 );
812 emit_opcode(*cbuf, 0x0F );
813 emit_opcode(*cbuf, 0x10 );
814 emit_rm (*cbuf, 0x3, Matcher::_regEncode[dst_lo], Matcher::_regEncode[src_lo] );
815 #ifndef PRODUCT
816 } else if( !do_size ) {
817 if( size != 0 ) st->print("\n\t");
818 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double move?
819 st->print("MOVSD %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
820 } else {
821 st->print("MOVSS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
822 }
823 #endif
824 }
825 return size+4;
826 }
827 }
828
829 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int size, outputStream* st ) {
830 if( cbuf ) {
831 emit_opcode(*cbuf, 0x8B );
832 emit_rm (*cbuf, 0x3, Matcher::_regEncode[dst], Matcher::_regEncode[src] );
833 #ifndef PRODUCT
834 } else if( !do_size ) {
835 if( size != 0 ) st->print("\n\t");
836 st->print("MOV %s,%s",Matcher::regName[dst],Matcher::regName[src]);
837 #endif
838 }
839 return size+2;
840 }
841
842 static int impl_fp_store_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int src_hi, int dst_lo, int dst_hi,
843 int offset, int size, outputStream* st ) {
844 if( src_lo != FPR1L_num ) { // Move value to top of FP stack, if not already there
845 if( cbuf ) {
846 emit_opcode( *cbuf, 0xD9 ); // FLD (i.e., push it)
847 emit_d8( *cbuf, 0xC0-1+Matcher::_regEncode[src_lo] );
848 #ifndef PRODUCT
849 } else if( !do_size ) {
850 if( size != 0 ) st->print("\n\t");
851 st->print("FLD %s",Matcher::regName[src_lo]);
852 #endif
853 }
854 size += 2;
855 }
856
857 int st_op = (src_lo != FPR1L_num) ? EBX_num /*store & pop*/ : EDX_num /*store no pop*/;
858 const char *op_str;
859 int op;
860 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double store?
861 op_str = (src_lo != FPR1L_num) ? "FSTP_D" : "FST_D ";
862 op = 0xDD;
863 } else { // 32-bit store
864 op_str = (src_lo != FPR1L_num) ? "FSTP_S" : "FST_S ";
865 op = 0xD9;
866 assert( !OptoReg::is_valid(src_hi) && !OptoReg::is_valid(dst_hi), "no non-adjacent float-stores" );
867 }
868
869 return impl_helper(cbuf,do_size,false,offset,st_op,op,op_str,size, st);
870 }
871
872 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream* st ) const {
873 // Get registers to move
874 OptoReg::Name src_second = ra_->get_reg_second(in(1));
875 OptoReg::Name src_first = ra_->get_reg_first(in(1));
876 OptoReg::Name dst_second = ra_->get_reg_second(this );
877 OptoReg::Name dst_first = ra_->get_reg_first(this );
878
879 enum RC src_second_rc = rc_class(src_second);
880 enum RC src_first_rc = rc_class(src_first);
881 enum RC dst_second_rc = rc_class(dst_second);
882 enum RC dst_first_rc = rc_class(dst_first);
883
884 assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" );
885
886 // Generate spill code!
887 int size = 0;
888
889 if( src_first == dst_first && src_second == dst_second )
890 return size; // Self copy, no move
891
892 // --------------------------------------
893 // Check for mem-mem move. push/pop to move.
894 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
895 if( src_second == dst_first ) { // overlapping stack copy ranges
896 assert( src_second_rc == rc_stack && dst_second_rc == rc_stack, "we only expect a stk-stk copy here" );
897 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH ",size, st);
898 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP ",size, st);
899 src_second_rc = dst_second_rc = rc_bad; // flag as already moved the second bits
900 }
901 // move low bits
902 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),ESI_num,0xFF,"PUSH ",size, st);
903 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),EAX_num,0x8F,"POP ",size, st);
904 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) { // mov second bits
905 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH ",size, st);
906 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP ",size, st);
907 }
908 return size;
909 }
910
911 // --------------------------------------
912 // Check for integer reg-reg copy
913 if( src_first_rc == rc_int && dst_first_rc == rc_int )
914 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,size, st);
915
916 // Check for integer store
917 if( src_first_rc == rc_int && dst_first_rc == rc_stack )
918 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first,0x89,"MOV ",size, st);
919
920 // Check for integer load
921 if( dst_first_rc == rc_int && src_first_rc == rc_stack )
922 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first,0x8B,"MOV ",size, st);
923
924 // --------------------------------------
925 // Check for float reg-reg copy
926 if( src_first_rc == rc_float && dst_first_rc == rc_float ) {
927 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) ||
928 (src_first+1 == src_second && dst_first+1 == dst_second), "no non-adjacent float-moves" );
929 if( cbuf ) {
930
931 // Note the mucking with the register encode to compensate for the 0/1
932 // indexing issue mentioned in a comment in the reg_def sections
933 // for FPR registers many lines above here.
934
935 if( src_first != FPR1L_num ) {
936 emit_opcode (*cbuf, 0xD9 ); // FLD ST(i)
937 emit_d8 (*cbuf, 0xC0+Matcher::_regEncode[src_first]-1 );
938 emit_opcode (*cbuf, 0xDD ); // FSTP ST(i)
939 emit_d8 (*cbuf, 0xD8+Matcher::_regEncode[dst_first] );
940 } else {
941 emit_opcode (*cbuf, 0xDD ); // FST ST(i)
942 emit_d8 (*cbuf, 0xD0+Matcher::_regEncode[dst_first]-1 );
943 }
944 #ifndef PRODUCT
945 } else if( !do_size ) {
946 if( size != 0 ) st->print("\n\t");
947 if( src_first != FPR1L_num ) st->print("FLD %s\n\tFSTP %s",Matcher::regName[src_first],Matcher::regName[dst_first]);
948 else st->print( "FST %s", Matcher::regName[dst_first]);
949 #endif
950 }
951 return size + ((src_first != FPR1L_num) ? 2+2 : 2);
952 }
953
954 // Check for float store
955 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) {
956 return impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,ra_->reg2offset(dst_first),size, st);
957 }
958
959 // Check for float load
960 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) {
961 int offset = ra_->reg2offset(src_first);
962 const char *op_str;
963 int op;
964 if( src_first+1 == src_second && dst_first+1 == dst_second ) { // double load?
965 op_str = "FLD_D";
966 op = 0xDD;
967 } else { // 32-bit load
968 op_str = "FLD_S";
969 op = 0xD9;
970 assert( src_second_rc == rc_bad && dst_second_rc == rc_bad, "no non-adjacent float-loads" );
971 }
972 if( cbuf ) {
973 emit_opcode (*cbuf, op );
974 encode_RegMem(*cbuf, 0x0, ESP_enc, 0x4, 0, offset, false);
975 emit_opcode (*cbuf, 0xDD ); // FSTP ST(i)
976 emit_d8 (*cbuf, 0xD8+Matcher::_regEncode[dst_first] );
977 #ifndef PRODUCT
978 } else if( !do_size ) {
979 if( size != 0 ) st->print("\n\t");
980 st->print("%s ST,[ESP + #%d]\n\tFSTP %s",op_str, offset,Matcher::regName[dst_first]);
981 #endif
982 }
983 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
984 return size + 3+offset_size+2;
985 }
986
987 // Check for xmm reg-reg copy
988 if( src_first_rc == rc_xmm && dst_first_rc == rc_xmm ) {
989 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) ||
990 (src_first+1 == src_second && dst_first+1 == dst_second),
991 "no non-adjacent float-moves" );
992 return impl_movx_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st);
993 }
994
995 // Check for xmm store
996 if( src_first_rc == rc_xmm && dst_first_rc == rc_stack ) {
997 return impl_x_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first, src_second, size, st);
998 }
999
1000 // Check for float xmm load
1001 if( dst_first_rc == rc_xmm && src_first_rc == rc_stack ) {
1002 return impl_x_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first, dst_second, size, st);
1003 }
1004
1005 // Copy from float reg to xmm reg
1006 if( dst_first_rc == rc_xmm && src_first_rc == rc_float ) {
1007 // copy to the top of stack from floating point reg
1008 // and use LEA to preserve flags
1009 if( cbuf ) {
1010 emit_opcode(*cbuf,0x8D); // LEA ESP,[ESP-8]
1011 emit_rm(*cbuf, 0x1, ESP_enc, 0x04);
1012 emit_rm(*cbuf, 0x0, 0x04, ESP_enc);
1013 emit_d8(*cbuf,0xF8);
1014 #ifndef PRODUCT
1015 } else if( !do_size ) {
1016 if( size != 0 ) st->print("\n\t");
1017 st->print("LEA ESP,[ESP-8]");
1018 #endif
1019 }
1020 size += 4;
1021
1022 size = impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,0,size, st);
1023
1024 // Copy from the temp memory to the xmm reg.
1025 size = impl_x_helper(cbuf,do_size,true ,0,dst_first, dst_second, size, st);
1026
1027 if( cbuf ) {
1028 emit_opcode(*cbuf,0x8D); // LEA ESP,[ESP+8]
1029 emit_rm(*cbuf, 0x1, ESP_enc, 0x04);
1030 emit_rm(*cbuf, 0x0, 0x04, ESP_enc);
1031 emit_d8(*cbuf,0x08);
1032 #ifndef PRODUCT
1033 } else if( !do_size ) {
1034 if( size != 0 ) st->print("\n\t");
1035 st->print("LEA ESP,[ESP+8]");
1036 #endif
1037 }
1038 size += 4;
1039 return size;
1040 }
1041
1042 assert( size > 0, "missed a case" );
1043
1044 // --------------------------------------------------------------------
1045 // Check for second bits still needing moving.
1046 if( src_second == dst_second )
1047 return size; // Self copy; no move
1048 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" );
1049
1050 // Check for second word int-int move
1051 if( src_second_rc == rc_int && dst_second_rc == rc_int )
1052 return impl_mov_helper(cbuf,do_size,src_second,dst_second,size, st);
1053
1054 // Check for second word integer store
1055 if( src_second_rc == rc_int && dst_second_rc == rc_stack )
1056 return impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),src_second,0x89,"MOV ",size, st);
1057
1058 // Check for second word integer load
1059 if( dst_second_rc == rc_int && src_second_rc == rc_stack )
1060 return impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),dst_second,0x8B,"MOV ",size, st);
1061
1062
1063 Unimplemented();
1064 }
1065
1066 #ifndef PRODUCT
1067 void MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1068 implementation( NULL, ra_, false, st );
1069 }
1070 #endif
1071
1072 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1073 implementation( &cbuf, ra_, false, NULL );
1074 }
1075
1076 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1077 return implementation( NULL, ra_, true, NULL );
1078 }
1079
1080 //=============================================================================
1081 #ifndef PRODUCT
1082 void MachNopNode::format( PhaseRegAlloc *, outputStream* st ) const {
1083 st->print("NOP \t# %d bytes pad for loops and calls", _count);
1084 }
1085 #endif
1086
1087 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc * ) const {
1088 MacroAssembler _masm(&cbuf);
1089 __ nop(_count);
1090 }
1091
1092 uint MachNopNode::size(PhaseRegAlloc *) const {
1093 return _count;
1094 }
1095
1096
1097 //=============================================================================
1098 #ifndef PRODUCT
1099 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1100 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1101 int reg = ra_->get_reg_first(this);
1102 st->print("LEA %s,[ESP + #%d]",Matcher::regName[reg],offset);
1103 }
1104 #endif
1105
1106 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1107 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1108 int reg = ra_->get_encode(this);
1109 if( offset >= 128 ) {
1110 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1111 emit_rm(cbuf, 0x2, reg, 0x04);
1112 emit_rm(cbuf, 0x0, 0x04, ESP_enc);
1113 emit_d32(cbuf, offset);
1114 }
1115 else {
1116 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1117 emit_rm(cbuf, 0x1, reg, 0x04);
1118 emit_rm(cbuf, 0x0, 0x04, ESP_enc);
1119 emit_d8(cbuf, offset);
1120 }
1121 }
1122
1123 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1124 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1125 if( offset >= 128 ) {
1126 return 7;
1127 }
1128 else {
1129 return 4;
1130 }
1131 }
1132
1133 //=============================================================================
1134
1135 // emit call stub, compiled java to interpreter
1136 void emit_java_to_interp(CodeBuffer &cbuf ) {
1137 // Stub is fixed up when the corresponding call is converted from calling
1138 // compiled code to calling interpreted code.
1139 // mov rbx,0
1140 // jmp -1
1141
1142 address mark = cbuf.inst_mark(); // get mark within main instrs section
1143
1144 // Note that the code buffer's inst_mark is always relative to insts.
1145 // That's why we must use the macroassembler to generate a stub.
1146 MacroAssembler _masm(&cbuf);
1147
1148 address base =
1149 __ start_a_stub(Compile::MAX_stubs_size);
1150 if (base == NULL) return; // CodeBuffer::expand failed
1151 // static stub relocation stores the instruction address of the call
1152 __ relocate(static_stub_Relocation::spec(mark), RELOC_IMM32);
1153 // static stub relocation also tags the methodOop in the code-stream.
1154 __ movoop(rbx, (jobject)NULL); // method is zapped till fixup time
1155 // This is recognized as unresolved by relocs/nativeInst/ic code
1156 __ jump(RuntimeAddress(__ pc()));
1157
1158 __ end_a_stub();
1159 // Update current stubs pointer and restore code_end.
1160 }
1161 // size of call stub, compiled java to interpretor
1162 uint size_java_to_interp() {
1163 return 10; // movl; jmp
1164 }
1165 // relocation entries for call stub, compiled java to interpretor
1166 uint reloc_java_to_interp() {
1167 return 4; // 3 in emit_java_to_interp + 1 in Java_Static_Call
1168 }
1169
1170 //=============================================================================
1171 #ifndef PRODUCT
1172 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1173 st->print_cr( "CMP EAX,[ECX+4]\t# Inline cache check");
1174 st->print_cr("\tJNE SharedRuntime::handle_ic_miss_stub");
1175 st->print_cr("\tNOP");
1176 st->print_cr("\tNOP");
1177 if( !OptoBreakpoint )
1178 st->print_cr("\tNOP");
1179 }
1180 #endif
1181
1182 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1183 MacroAssembler masm(&cbuf);
1184 #ifdef ASSERT
1185 uint code_size = cbuf.code_size();
1186 #endif
1187 masm.cmpptr(rax, Address(rcx, oopDesc::klass_offset_in_bytes()));
1188 masm.jump_cc(Assembler::notEqual,
1189 RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1190 /* WARNING these NOPs are critical so that verified entry point is properly
1191 aligned for patching by NativeJump::patch_verified_entry() */
1192 int nops_cnt = 2;
1193 if( !OptoBreakpoint ) // Leave space for int3
1194 nops_cnt += 1;
1195 masm.nop(nops_cnt);
1196
1197 assert(cbuf.code_size() - code_size == size(ra_), "checking code size of inline cache node");
1198 }
1199
1200 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
1201 return OptoBreakpoint ? 11 : 12;
1202 }
1203
1204
1205 //=============================================================================
1206 uint size_exception_handler() {
1207 // NativeCall instruction size is the same as NativeJump.
1208 // exception handler starts out as jump and can be patched to
1209 // a call be deoptimization. (4932387)
1210 // Note that this value is also credited (in output.cpp) to
1211 // the size of the code section.
1212 return NativeJump::instruction_size;
1213 }
1214
1215 // Emit exception handler code. Stuff framesize into a register
1216 // and call a VM stub routine.
1217 int emit_exception_handler(CodeBuffer& cbuf) {
1218
1219 // Note that the code buffer's inst_mark is always relative to insts.
1220 // That's why we must use the macroassembler to generate a handler.
1221 MacroAssembler _masm(&cbuf);
1222 address base =
1223 __ start_a_stub(size_exception_handler());
1224 if (base == NULL) return 0; // CodeBuffer::expand failed
1225 int offset = __ offset();
1226 __ jump(RuntimeAddress(OptoRuntime::exception_blob()->instructions_begin()));
1227 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
1228 __ end_a_stub();
1229 return offset;
1230 }
1231
1232 uint size_deopt_handler() {
1233 // NativeCall instruction size is the same as NativeJump.
1234 // exception handler starts out as jump and can be patched to
1235 // a call be deoptimization. (4932387)
1236 // Note that this value is also credited (in output.cpp) to
1237 // the size of the code section.
1238 return 5 + NativeJump::instruction_size; // pushl(); jmp;
1239 }
1240
1241 // Emit deopt handler code.
1242 int emit_deopt_handler(CodeBuffer& cbuf) {
1243
1244 // Note that the code buffer's inst_mark is always relative to insts.
1245 // That's why we must use the macroassembler to generate a handler.
1246 MacroAssembler _masm(&cbuf);
1247 address base =
1248 __ start_a_stub(size_exception_handler());
1249 if (base == NULL) return 0; // CodeBuffer::expand failed
1250 int offset = __ offset();
1251 InternalAddress here(__ pc());
1252 __ pushptr(here.addr());
1253
1254 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
1255 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
1256 __ end_a_stub();
1257 return offset;
1258 }
1259
1260
1261 static void emit_double_constant(CodeBuffer& cbuf, double x) {
1262 int mark = cbuf.insts()->mark_off();
1263 MacroAssembler _masm(&cbuf);
1264 address double_address = __ double_constant(x);
1265 cbuf.insts()->set_mark_off(mark); // preserve mark across masm shift
1266 emit_d32_reloc(cbuf,
1267 (int)double_address,
1268 internal_word_Relocation::spec(double_address),
1269 RELOC_DISP32);
1270 }
1271
1272 static void emit_float_constant(CodeBuffer& cbuf, float x) {
1273 int mark = cbuf.insts()->mark_off();
1274 MacroAssembler _masm(&cbuf);
1275 address float_address = __ float_constant(x);
1276 cbuf.insts()->set_mark_off(mark); // preserve mark across masm shift
1277 emit_d32_reloc(cbuf,
1278 (int)float_address,
1279 internal_word_Relocation::spec(float_address),
1280 RELOC_DISP32);
1281 }
1282
1283
1284 const bool Matcher::match_rule_supported(int opcode) {
1285 if (!has_match_rule(opcode))
1286 return false;
1287
1288 return true; // Per default match rules are supported.
1289 }
1290
1291 int Matcher::regnum_to_fpu_offset(int regnum) {
1292 return regnum - 32; // The FP registers are in the second chunk
1293 }
1294
1295 bool is_positive_zero_float(jfloat f) {
1296 return jint_cast(f) == jint_cast(0.0F);
1297 }
1298
1299 bool is_positive_one_float(jfloat f) {
1300 return jint_cast(f) == jint_cast(1.0F);
1301 }
1302
1303 bool is_positive_zero_double(jdouble d) {
1304 return jlong_cast(d) == jlong_cast(0.0);
1305 }
1306
1307 bool is_positive_one_double(jdouble d) {
1308 return jlong_cast(d) == jlong_cast(1.0);
1309 }
1310
1311 // This is UltraSparc specific, true just means we have fast l2f conversion
1312 const bool Matcher::convL2FSupported(void) {
1313 return true;
1314 }
1315
1316 // Vector width in bytes
1317 const uint Matcher::vector_width_in_bytes(void) {
1318 return UseSSE >= 2 ? 8 : 0;
1319 }
1320
1321 // Vector ideal reg
1322 const uint Matcher::vector_ideal_reg(void) {
1323 return Op_RegD;
1324 }
1325
1326 // Is this branch offset short enough that a short branch can be used?
1327 //
1328 // NOTE: If the platform does not provide any short branch variants, then
1329 // this method should return false for offset 0.
1330 bool Matcher::is_short_branch_offset(int rule, int offset) {
1331 // the short version of jmpConUCF2 contains multiple branches,
1332 // making the reach slightly less
1333 if (rule == jmpConUCF2_rule)
1334 return (-126 <= offset && offset <= 125);
1335 return (-128 <= offset && offset <= 127);
1336 }
1337
1338 const bool Matcher::isSimpleConstant64(jlong value) {
1339 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1340 return false;
1341 }
1342
1343 // The ecx parameter to rep stos for the ClearArray node is in dwords.
1344 const bool Matcher::init_array_count_is_in_bytes = false;
1345
1346 // Threshold size for cleararray.
1347 const int Matcher::init_array_short_size = 8 * BytesPerLong;
1348
1349 // Should the Matcher clone shifts on addressing modes, expecting them to
1350 // be subsumed into complex addressing expressions or compute them into
1351 // registers? True for Intel but false for most RISCs
1352 const bool Matcher::clone_shift_expressions = true;
1353
1354 // Is it better to copy float constants, or load them directly from memory?
1355 // Intel can load a float constant from a direct address, requiring no
1356 // extra registers. Most RISCs will have to materialize an address into a
1357 // register first, so they would do better to copy the constant from stack.
1358 const bool Matcher::rematerialize_float_constants = true;
1359
1360 // If CPU can load and store mis-aligned doubles directly then no fixup is
1361 // needed. Else we split the double into 2 integer pieces and move it
1362 // piece-by-piece. Only happens when passing doubles into C code as the
1363 // Java calling convention forces doubles to be aligned.
1364 const bool Matcher::misaligned_doubles_ok = true;
1365
1366
1367 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
1368 // Get the memory operand from the node
1369 uint numopnds = node->num_opnds(); // Virtual call for number of operands
1370 uint skipped = node->oper_input_base(); // Sum of leaves skipped so far
1371 assert( idx >= skipped, "idx too low in pd_implicit_null_fixup" );
1372 uint opcnt = 1; // First operand
1373 uint num_edges = node->_opnds[1]->num_edges(); // leaves for first operand
1374 while( idx >= skipped+num_edges ) {
1375 skipped += num_edges;
1376 opcnt++; // Bump operand count
1377 assert( opcnt < numopnds, "Accessing non-existent operand" );
1378 num_edges = node->_opnds[opcnt]->num_edges(); // leaves for next operand
1379 }
1380
1381 MachOper *memory = node->_opnds[opcnt];
1382 MachOper *new_memory = NULL;
1383 switch (memory->opcode()) {
1384 case DIRECT:
1385 case INDOFFSET32X:
1386 // No transformation necessary.
1387 return;
1388 case INDIRECT:
1389 new_memory = new (C) indirect_win95_safeOper( );
1390 break;
1391 case INDOFFSET8:
1392 new_memory = new (C) indOffset8_win95_safeOper(memory->disp(NULL, NULL, 0));
1393 break;
1394 case INDOFFSET32:
1395 new_memory = new (C) indOffset32_win95_safeOper(memory->disp(NULL, NULL, 0));
1396 break;
1397 case INDINDEXOFFSET:
1398 new_memory = new (C) indIndexOffset_win95_safeOper(memory->disp(NULL, NULL, 0));
1399 break;
1400 case INDINDEXSCALE:
1401 new_memory = new (C) indIndexScale_win95_safeOper(memory->scale());
1402 break;
1403 case INDINDEXSCALEOFFSET:
1404 new_memory = new (C) indIndexScaleOffset_win95_safeOper(memory->scale(), memory->disp(NULL, NULL, 0));
1405 break;
1406 case LOAD_LONG_INDIRECT:
1407 case LOAD_LONG_INDOFFSET32:
1408 // Does not use EBP as address register, use { EDX, EBX, EDI, ESI}
1409 return;
1410 default:
1411 assert(false, "unexpected memory operand in pd_implicit_null_fixup()");
1412 return;
1413 }
1414 node->_opnds[opcnt] = new_memory;
1415 }
1416
1417 // Advertise here if the CPU requires explicit rounding operations
1418 // to implement the UseStrictFP mode.
1419 const bool Matcher::strict_fp_requires_explicit_rounding = true;
1420
1421 // Do floats take an entire double register or just half?
1422 const bool Matcher::float_in_double = true;
1423 // Do ints take an entire long register or just half?
1424 const bool Matcher::int_in_long = false;
1425
1426 // Return whether or not this register is ever used as an argument. This
1427 // function is used on startup to build the trampoline stubs in generateOptoStub.
1428 // Registers not mentioned will be killed by the VM call in the trampoline, and
1429 // arguments in those registers not be available to the callee.
1430 bool Matcher::can_be_java_arg( int reg ) {
1431 if( reg == ECX_num || reg == EDX_num ) return true;
1432 if( (reg == XMM0a_num || reg == XMM1a_num) && UseSSE>=1 ) return true;
1433 if( (reg == XMM0b_num || reg == XMM1b_num) && UseSSE>=2 ) return true;
1434 return false;
1435 }
1436
1437 bool Matcher::is_spillable_arg( int reg ) {
1438 return can_be_java_arg(reg);
1439 }
1440
1441 // Register for DIVI projection of divmodI
1442 RegMask Matcher::divI_proj_mask() {
1443 return EAX_REG_mask;
1444 }
1445
1446 // Register for MODI projection of divmodI
1447 RegMask Matcher::modI_proj_mask() {
1448 return EDX_REG_mask;
1449 }
1450
1451 // Register for DIVL projection of divmodL
1452 RegMask Matcher::divL_proj_mask() {
1453 ShouldNotReachHere();
1454 return RegMask();
1455 }
1456
1457 // Register for MODL projection of divmodL
1458 RegMask Matcher::modL_proj_mask() {
1459 ShouldNotReachHere();
1460 return RegMask();
1461 }
1462
1463 %}
1464
1465 //----------ENCODING BLOCK-----------------------------------------------------
1466 // This block specifies the encoding classes used by the compiler to output
1467 // byte streams. Encoding classes generate functions which are called by
1468 // Machine Instruction Nodes in order to generate the bit encoding of the
1469 // instruction. Operands specify their base encoding interface with the
1470 // interface keyword. There are currently supported four interfaces,
1471 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
1472 // operand to generate a function which returns its register number when
1473 // queried. CONST_INTER causes an operand to generate a function which
1474 // returns the value of the constant when queried. MEMORY_INTER causes an
1475 // operand to generate four functions which return the Base Register, the
1476 // Index Register, the Scale Value, and the Offset Value of the operand when
1477 // queried. COND_INTER causes an operand to generate six functions which
1478 // return the encoding code (ie - encoding bits for the instruction)
1479 // associated with each basic boolean condition for a conditional instruction.
1480 // Instructions specify two basic values for encoding. They use the
1481 // ins_encode keyword to specify their encoding class (which must be one of
1482 // the class names specified in the encoding block), and they use the
1483 // opcode keyword to specify, in order, their primary, secondary, and
1484 // tertiary opcode. Only the opcode sections which a particular instruction
1485 // needs for encoding need to be specified.
1486 encode %{
1487 // Build emit functions for each basic byte or larger field in the intel
1488 // encoding scheme (opcode, rm, sib, immediate), and call them from C++
1489 // code in the enc_class source block. Emit functions will live in the
1490 // main source block for now. In future, we can generalize this by
1491 // adding a syntax that specifies the sizes of fields in an order,
1492 // so that the adlc can build the emit functions automagically
1493
1494 // Emit primary opcode
1495 enc_class OpcP %{
1496 emit_opcode(cbuf, $primary);
1497 %}
1498
1499 // Emit secondary opcode
1500 enc_class OpcS %{
1501 emit_opcode(cbuf, $secondary);
1502 %}
1503
1504 // Emit opcode directly
1505 enc_class Opcode(immI d8) %{
1506 emit_opcode(cbuf, $d8$$constant);
1507 %}
1508
1509 enc_class SizePrefix %{
1510 emit_opcode(cbuf,0x66);
1511 %}
1512
1513 enc_class RegReg (eRegI dst, eRegI src) %{ // RegReg(Many)
1514 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1515 %}
1516
1517 enc_class OpcRegReg (immI opcode, eRegI dst, eRegI src) %{ // OpcRegReg(Many)
1518 emit_opcode(cbuf,$opcode$$constant);
1519 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1520 %}
1521
1522 enc_class mov_r32_imm0( eRegI dst ) %{
1523 emit_opcode( cbuf, 0xB8 + $dst$$reg ); // 0xB8+ rd -- MOV r32 ,imm32
1524 emit_d32 ( cbuf, 0x0 ); // imm32==0x0
1525 %}
1526
1527 enc_class cdq_enc %{
1528 // Full implementation of Java idiv and irem; checks for
1529 // special case as described in JVM spec., p.243 & p.271.
1530 //
1531 // normal case special case
1532 //
1533 // input : rax,: dividend min_int
1534 // reg: divisor -1
1535 //
1536 // output: rax,: quotient (= rax, idiv reg) min_int
1537 // rdx: remainder (= rax, irem reg) 0
1538 //
1539 // Code sequnce:
1540 //
1541 // 81 F8 00 00 00 80 cmp rax,80000000h
1542 // 0F 85 0B 00 00 00 jne normal_case
1543 // 33 D2 xor rdx,edx
1544 // 83 F9 FF cmp rcx,0FFh
1545 // 0F 84 03 00 00 00 je done
1546 // normal_case:
1547 // 99 cdq
1548 // F7 F9 idiv rax,ecx
1549 // done:
1550 //
1551 emit_opcode(cbuf,0x81); emit_d8(cbuf,0xF8);
1552 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00);
1553 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x80); // cmp rax,80000000h
1554 emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x85);
1555 emit_opcode(cbuf,0x0B); emit_d8(cbuf,0x00);
1556 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); // jne normal_case
1557 emit_opcode(cbuf,0x33); emit_d8(cbuf,0xD2); // xor rdx,edx
1558 emit_opcode(cbuf,0x83); emit_d8(cbuf,0xF9); emit_d8(cbuf,0xFF); // cmp rcx,0FFh
1559 emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x84);
1560 emit_opcode(cbuf,0x03); emit_d8(cbuf,0x00);
1561 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); // je done
1562 // normal_case:
1563 emit_opcode(cbuf,0x99); // cdq
1564 // idiv (note: must be emitted by the user of this rule)
1565 // normal:
1566 %}
1567
1568 // Dense encoding for older common ops
1569 enc_class Opc_plus(immI opcode, eRegI reg) %{
1570 emit_opcode(cbuf, $opcode$$constant + $reg$$reg);
1571 %}
1572
1573
1574 // Opcde enc_class for 8/32 bit immediate instructions with sign-extension
1575 enc_class OpcSE (immI imm) %{ // Emit primary opcode and set sign-extend bit
1576 // Check for 8-bit immediate, and set sign extend bit in opcode
1577 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1578 emit_opcode(cbuf, $primary | 0x02);
1579 }
1580 else { // If 32-bit immediate
1581 emit_opcode(cbuf, $primary);
1582 }
1583 %}
1584
1585 enc_class OpcSErm (eRegI dst, immI imm) %{ // OpcSEr/m
1586 // Emit primary opcode and set sign-extend bit
1587 // Check for 8-bit immediate, and set sign extend bit in opcode
1588 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1589 emit_opcode(cbuf, $primary | 0x02); }
1590 else { // If 32-bit immediate
1591 emit_opcode(cbuf, $primary);
1592 }
1593 // Emit r/m byte with secondary opcode, after primary opcode.
1594 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1595 %}
1596
1597 enc_class Con8or32 (immI imm) %{ // Con8or32(storeImmI), 8 or 32 bits
1598 // Check for 8-bit immediate, and set sign extend bit in opcode
1599 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1600 $$$emit8$imm$$constant;
1601 }
1602 else { // If 32-bit immediate
1603 // Output immediate
1604 $$$emit32$imm$$constant;
1605 }
1606 %}
1607
1608 enc_class Long_OpcSErm_Lo(eRegL dst, immL imm) %{
1609 // Emit primary opcode and set sign-extend bit
1610 // Check for 8-bit immediate, and set sign extend bit in opcode
1611 int con = (int)$imm$$constant; // Throw away top bits
1612 emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary);
1613 // Emit r/m byte with secondary opcode, after primary opcode.
1614 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1615 if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con);
1616 else emit_d32(cbuf,con);
1617 %}
1618
1619 enc_class Long_OpcSErm_Hi(eRegL dst, immL imm) %{
1620 // Emit primary opcode and set sign-extend bit
1621 // Check for 8-bit immediate, and set sign extend bit in opcode
1622 int con = (int)($imm$$constant >> 32); // Throw away bottom bits
1623 emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary);
1624 // Emit r/m byte with tertiary opcode, after primary opcode.
1625 emit_rm(cbuf, 0x3, $tertiary, HIGH_FROM_LOW($dst$$reg));
1626 if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con);
1627 else emit_d32(cbuf,con);
1628 %}
1629
1630 enc_class Lbl (label labl) %{ // JMP, CALL
1631 Label *l = $labl$$label;
1632 emit_d32(cbuf, l ? (l->loc_pos() - (cbuf.code_size()+4)) : 0);
1633 %}
1634
1635 enc_class LblShort (label labl) %{ // JMP, CALL
1636 Label *l = $labl$$label;
1637 int disp = l ? (l->loc_pos() - (cbuf.code_size()+1)) : 0;
1638 assert(-128 <= disp && disp <= 127, "Displacement too large for short jmp");
1639 emit_d8(cbuf, disp);
1640 %}
1641
1642 enc_class OpcSReg (eRegI dst) %{ // BSWAP
1643 emit_cc(cbuf, $secondary, $dst$$reg );
1644 %}
1645
1646 enc_class bswap_long_bytes(eRegL dst) %{ // BSWAP
1647 int destlo = $dst$$reg;
1648 int desthi = HIGH_FROM_LOW(destlo);
1649 // bswap lo
1650 emit_opcode(cbuf, 0x0F);
1651 emit_cc(cbuf, 0xC8, destlo);
1652 // bswap hi
1653 emit_opcode(cbuf, 0x0F);
1654 emit_cc(cbuf, 0xC8, desthi);
1655 // xchg lo and hi
1656 emit_opcode(cbuf, 0x87);
1657 emit_rm(cbuf, 0x3, destlo, desthi);
1658 %}
1659
1660 enc_class RegOpc (eRegI div) %{ // IDIV, IMOD, JMP indirect, ...
1661 emit_rm(cbuf, 0x3, $secondary, $div$$reg );
1662 %}
1663
1664 enc_class Jcc (cmpOp cop, label labl) %{ // JCC
1665 Label *l = $labl$$label;
1666 $$$emit8$primary;
1667 emit_cc(cbuf, $secondary, $cop$$cmpcode);
1668 emit_d32(cbuf, l ? (l->loc_pos() - (cbuf.code_size()+4)) : 0);
1669 %}
1670
1671 enc_class JccShort (cmpOp cop, label labl) %{ // JCC
1672 Label *l = $labl$$label;
1673 emit_cc(cbuf, $primary, $cop$$cmpcode);
1674 int disp = l ? (l->loc_pos() - (cbuf.code_size()+1)) : 0;
1675 assert(-128 <= disp && disp <= 127, "Displacement too large for short jmp");
1676 emit_d8(cbuf, disp);
1677 %}
1678
1679 enc_class enc_cmov(cmpOp cop ) %{ // CMOV
1680 $$$emit8$primary;
1681 emit_cc(cbuf, $secondary, $cop$$cmpcode);
1682 %}
1683
1684 enc_class enc_cmov_d(cmpOp cop, regD src ) %{ // CMOV
1685 int op = 0xDA00 + $cop$$cmpcode + ($src$$reg-1);
1686 emit_d8(cbuf, op >> 8 );
1687 emit_d8(cbuf, op & 255);
1688 %}
1689
1690 // emulate a CMOV with a conditional branch around a MOV
1691 enc_class enc_cmov_branch( cmpOp cop, immI brOffs ) %{ // CMOV
1692 // Invert sense of branch from sense of CMOV
1693 emit_cc( cbuf, 0x70, ($cop$$cmpcode^1) );
1694 emit_d8( cbuf, $brOffs$$constant );
1695 %}
1696
1697 enc_class enc_PartialSubtypeCheck( ) %{
1698 Register Redi = as_Register(EDI_enc); // result register
1699 Register Reax = as_Register(EAX_enc); // super class
1700 Register Recx = as_Register(ECX_enc); // killed
1701 Register Resi = as_Register(ESI_enc); // sub class
1702 Label miss;
1703
1704 MacroAssembler _masm(&cbuf);
1705 __ check_klass_subtype_slow_path(Resi, Reax, Recx, Redi,
1706 NULL, &miss,
1707 /*set_cond_codes:*/ true);
1708 if ($primary) {
1709 __ xorptr(Redi, Redi);
1710 }
1711 __ bind(miss);
1712 %}
1713
1714 enc_class FFree_Float_Stack_All %{ // Free_Float_Stack_All
1715 MacroAssembler masm(&cbuf);
1716 int start = masm.offset();
1717 if (UseSSE >= 2) {
1718 if (VerifyFPU) {
1719 masm.verify_FPU(0, "must be empty in SSE2+ mode");
1720 }
1721 } else {
1722 // External c_calling_convention expects the FPU stack to be 'clean'.
1723 // Compiled code leaves it dirty. Do cleanup now.
1724 masm.empty_FPU_stack();
1725 }
1726 if (sizeof_FFree_Float_Stack_All == -1) {
1727 sizeof_FFree_Float_Stack_All = masm.offset() - start;
1728 } else {
1729 assert(masm.offset() - start == sizeof_FFree_Float_Stack_All, "wrong size");
1730 }
1731 %}
1732
1733 enc_class Verify_FPU_For_Leaf %{
1734 if( VerifyFPU ) {
1735 MacroAssembler masm(&cbuf);
1736 masm.verify_FPU( -3, "Returning from Runtime Leaf call");
1737 }
1738 %}
1739
1740 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime, Java_To_Runtime_Leaf
1741 // This is the instruction starting address for relocation info.
1742 cbuf.set_inst_mark();
1743 $$$emit8$primary;
1744 // CALL directly to the runtime
1745 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.code_end()) - 4),
1746 runtime_call_Relocation::spec(), RELOC_IMM32 );
1747
1748 if (UseSSE >= 2) {
1749 MacroAssembler _masm(&cbuf);
1750 BasicType rt = tf()->return_type();
1751
1752 if ((rt == T_FLOAT || rt == T_DOUBLE) && !return_value_is_used()) {
1753 // A C runtime call where the return value is unused. In SSE2+
1754 // mode the result needs to be removed from the FPU stack. It's
1755 // likely that this function call could be removed by the
1756 // optimizer if the C function is a pure function.
1757 __ ffree(0);
1758 } else if (rt == T_FLOAT) {
1759 __ lea(rsp, Address(rsp, -4));
1760 __ fstp_s(Address(rsp, 0));
1761 __ movflt(xmm0, Address(rsp, 0));
1762 __ lea(rsp, Address(rsp, 4));
1763 } else if (rt == T_DOUBLE) {
1764 __ lea(rsp, Address(rsp, -8));
1765 __ fstp_d(Address(rsp, 0));
1766 __ movdbl(xmm0, Address(rsp, 0));
1767 __ lea(rsp, Address(rsp, 8));
1768 }
1769 }
1770 %}
1771
1772
1773 enc_class pre_call_FPU %{
1774 // If method sets FPU control word restore it here
1775 if( Compile::current()->in_24_bit_fp_mode() ) {
1776 MacroAssembler masm(&cbuf);
1777 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
1778 }
1779 %}
1780
1781 enc_class post_call_FPU %{
1782 // If method sets FPU control word do it here also
1783 if( Compile::current()->in_24_bit_fp_mode() ) {
1784 MacroAssembler masm(&cbuf);
1785 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
1786 }
1787 %}
1788
1789 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL
1790 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
1791 // who we intended to call.
1792 cbuf.set_inst_mark();
1793 $$$emit8$primary;
1794 if ( !_method ) {
1795 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.code_end()) - 4),
1796 runtime_call_Relocation::spec(), RELOC_IMM32 );
1797 } else if(_optimized_virtual) {
1798 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.code_end()) - 4),
1799 opt_virtual_call_Relocation::spec(), RELOC_IMM32 );
1800 } else {
1801 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.code_end()) - 4),
1802 static_call_Relocation::spec(), RELOC_IMM32 );
1803 }
1804 if( _method ) { // Emit stub for static call
1805 emit_java_to_interp(cbuf);
1806 }
1807 %}
1808
1809 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL
1810 // !!!!!
1811 // Generate "Mov EAX,0x00", placeholder instruction to load oop-info
1812 // emit_call_dynamic_prologue( cbuf );
1813 cbuf.set_inst_mark();
1814 emit_opcode(cbuf, 0xB8 + EAX_enc); // mov EAX,-1
1815 emit_d32_reloc(cbuf, (int)Universe::non_oop_word(), oop_Relocation::spec_for_immediate(), RELOC_IMM32);
1816 address virtual_call_oop_addr = cbuf.inst_mark();
1817 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
1818 // who we intended to call.
1819 cbuf.set_inst_mark();
1820 $$$emit8$primary;
1821 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.code_end()) - 4),
1822 virtual_call_Relocation::spec(virtual_call_oop_addr), RELOC_IMM32 );
1823 %}
1824
1825 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL
1826 int disp = in_bytes(methodOopDesc::from_compiled_offset());
1827 assert( -128 <= disp && disp <= 127, "compiled_code_offset isn't small");
1828
1829 // CALL *[EAX+in_bytes(methodOopDesc::from_compiled_code_entry_point_offset())]
1830 cbuf.set_inst_mark();
1831 $$$emit8$primary;
1832 emit_rm(cbuf, 0x01, $secondary, EAX_enc ); // R/M byte
1833 emit_d8(cbuf, disp); // Displacement
1834
1835 %}
1836
1837 enc_class Xor_Reg (eRegI dst) %{
1838 emit_opcode(cbuf, 0x33);
1839 emit_rm(cbuf, 0x3, $dst$$reg, $dst$$reg);
1840 %}
1841
1842 // Following encoding is no longer used, but may be restored if calling
1843 // convention changes significantly.
1844 // Became: Xor_Reg(EBP), Java_To_Runtime( labl )
1845 //
1846 // enc_class Java_Interpreter_Call (label labl) %{ // JAVA INTERPRETER CALL
1847 // // int ic_reg = Matcher::inline_cache_reg();
1848 // // int ic_encode = Matcher::_regEncode[ic_reg];
1849 // // int imo_reg = Matcher::interpreter_method_oop_reg();
1850 // // int imo_encode = Matcher::_regEncode[imo_reg];
1851 //
1852 // // // Interpreter expects method_oop in EBX, currently a callee-saved register,
1853 // // // so we load it immediately before the call
1854 // // emit_opcode(cbuf, 0x8B); // MOV imo_reg,ic_reg # method_oop
1855 // // emit_rm(cbuf, 0x03, imo_encode, ic_encode ); // R/M byte
1856 //
1857 // // xor rbp,ebp
1858 // emit_opcode(cbuf, 0x33);
1859 // emit_rm(cbuf, 0x3, EBP_enc, EBP_enc);
1860 //
1861 // // CALL to interpreter.
1862 // cbuf.set_inst_mark();
1863 // $$$emit8$primary;
1864 // emit_d32_reloc(cbuf, ($labl$$label - (int)(cbuf.code_end()) - 4),
1865 // runtime_call_Relocation::spec(), RELOC_IMM32 );
1866 // %}
1867
1868 enc_class RegOpcImm (eRegI dst, immI8 shift) %{ // SHL, SAR, SHR
1869 $$$emit8$primary;
1870 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1871 $$$emit8$shift$$constant;
1872 %}
1873
1874 enc_class LdImmI (eRegI dst, immI src) %{ // Load Immediate
1875 // Load immediate does not have a zero or sign extended version
1876 // for 8-bit immediates
1877 emit_opcode(cbuf, 0xB8 + $dst$$reg);
1878 $$$emit32$src$$constant;
1879 %}
1880
1881 enc_class LdImmP (eRegI dst, immI src) %{ // Load Immediate
1882 // Load immediate does not have a zero or sign extended version
1883 // for 8-bit immediates
1884 emit_opcode(cbuf, $primary + $dst$$reg);
1885 $$$emit32$src$$constant;
1886 %}
1887
1888 enc_class LdImmL_Lo( eRegL dst, immL src) %{ // Load Immediate
1889 // Load immediate does not have a zero or sign extended version
1890 // for 8-bit immediates
1891 int dst_enc = $dst$$reg;
1892 int src_con = $src$$constant & 0x0FFFFFFFFL;
1893 if (src_con == 0) {
1894 // xor dst, dst
1895 emit_opcode(cbuf, 0x33);
1896 emit_rm(cbuf, 0x3, dst_enc, dst_enc);
1897 } else {
1898 emit_opcode(cbuf, $primary + dst_enc);
1899 emit_d32(cbuf, src_con);
1900 }
1901 %}
1902
1903 enc_class LdImmL_Hi( eRegL dst, immL src) %{ // Load Immediate
1904 // Load immediate does not have a zero or sign extended version
1905 // for 8-bit immediates
1906 int dst_enc = $dst$$reg + 2;
1907 int src_con = ((julong)($src$$constant)) >> 32;
1908 if (src_con == 0) {
1909 // xor dst, dst
1910 emit_opcode(cbuf, 0x33);
1911 emit_rm(cbuf, 0x3, dst_enc, dst_enc);
1912 } else {
1913 emit_opcode(cbuf, $primary + dst_enc);
1914 emit_d32(cbuf, src_con);
1915 }
1916 %}
1917
1918
1919 enc_class LdImmD (immD src) %{ // Load Immediate
1920 if( is_positive_zero_double($src$$constant)) {
1921 // FLDZ
1922 emit_opcode(cbuf,0xD9);
1923 emit_opcode(cbuf,0xEE);
1924 } else if( is_positive_one_double($src$$constant)) {
1925 // FLD1
1926 emit_opcode(cbuf,0xD9);
1927 emit_opcode(cbuf,0xE8);
1928 } else {
1929 emit_opcode(cbuf,0xDD);
1930 emit_rm(cbuf, 0x0, 0x0, 0x5);
1931 emit_double_constant(cbuf, $src$$constant);
1932 }
1933 %}
1934
1935
1936 enc_class LdImmF (immF src) %{ // Load Immediate
1937 if( is_positive_zero_float($src$$constant)) {
1938 emit_opcode(cbuf,0xD9);
1939 emit_opcode(cbuf,0xEE);
1940 } else if( is_positive_one_float($src$$constant)) {
1941 emit_opcode(cbuf,0xD9);
1942 emit_opcode(cbuf,0xE8);
1943 } else {
1944 $$$emit8$primary;
1945 // Load immediate does not have a zero or sign extended version
1946 // for 8-bit immediates
1947 // First load to TOS, then move to dst
1948 emit_rm(cbuf, 0x0, 0x0, 0x5);
1949 emit_float_constant(cbuf, $src$$constant);
1950 }
1951 %}
1952
1953 enc_class LdImmX (regX dst, immXF con) %{ // Load Immediate
1954 emit_rm(cbuf, 0x0, $dst$$reg, 0x5);
1955 emit_float_constant(cbuf, $con$$constant);
1956 %}
1957
1958 enc_class LdImmXD (regXD dst, immXD con) %{ // Load Immediate
1959 emit_rm(cbuf, 0x0, $dst$$reg, 0x5);
1960 emit_double_constant(cbuf, $con$$constant);
1961 %}
1962
1963 enc_class load_conXD (regXD dst, immXD con) %{ // Load double constant
1964 // UseXmmLoadAndClearUpper ? movsd(dst, con) : movlpd(dst, con)
1965 emit_opcode(cbuf, UseXmmLoadAndClearUpper ? 0xF2 : 0x66);
1966 emit_opcode(cbuf, 0x0F);
1967 emit_opcode(cbuf, UseXmmLoadAndClearUpper ? 0x10 : 0x12);
1968 emit_rm(cbuf, 0x0, $dst$$reg, 0x5);
1969 emit_double_constant(cbuf, $con$$constant);
1970 %}
1971
1972 enc_class Opc_MemImm_F(immF src) %{
1973 cbuf.set_inst_mark();
1974 $$$emit8$primary;
1975 emit_rm(cbuf, 0x0, $secondary, 0x5);
1976 emit_float_constant(cbuf, $src$$constant);
1977 %}
1978
1979
1980 enc_class MovI2X_reg(regX dst, eRegI src) %{
1981 emit_opcode(cbuf, 0x66 ); // MOVD dst,src
1982 emit_opcode(cbuf, 0x0F );
1983 emit_opcode(cbuf, 0x6E );
1984 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1985 %}
1986
1987 enc_class MovX2I_reg(eRegI dst, regX src) %{
1988 emit_opcode(cbuf, 0x66 ); // MOVD dst,src
1989 emit_opcode(cbuf, 0x0F );
1990 emit_opcode(cbuf, 0x7E );
1991 emit_rm(cbuf, 0x3, $src$$reg, $dst$$reg);
1992 %}
1993
1994 enc_class MovL2XD_reg(regXD dst, eRegL src, regXD tmp) %{
1995 { // MOVD $dst,$src.lo
1996 emit_opcode(cbuf,0x66);
1997 emit_opcode(cbuf,0x0F);
1998 emit_opcode(cbuf,0x6E);
1999 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2000 }
2001 { // MOVD $tmp,$src.hi
2002 emit_opcode(cbuf,0x66);
2003 emit_opcode(cbuf,0x0F);
2004 emit_opcode(cbuf,0x6E);
2005 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg));
2006 }
2007 { // PUNPCKLDQ $dst,$tmp
2008 emit_opcode(cbuf,0x66);
2009 emit_opcode(cbuf,0x0F);
2010 emit_opcode(cbuf,0x62);
2011 emit_rm(cbuf, 0x3, $dst$$reg, $tmp$$reg);
2012 }
2013 %}
2014
2015 enc_class MovXD2L_reg(eRegL dst, regXD src, regXD tmp) %{
2016 { // MOVD $dst.lo,$src
2017 emit_opcode(cbuf,0x66);
2018 emit_opcode(cbuf,0x0F);
2019 emit_opcode(cbuf,0x7E);
2020 emit_rm(cbuf, 0x3, $src$$reg, $dst$$reg);
2021 }
2022 { // PSHUFLW $tmp,$src,0x4E (01001110b)
2023 emit_opcode(cbuf,0xF2);
2024 emit_opcode(cbuf,0x0F);
2025 emit_opcode(cbuf,0x70);
2026 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg);
2027 emit_d8(cbuf, 0x4E);
2028 }
2029 { // MOVD $dst.hi,$tmp
2030 emit_opcode(cbuf,0x66);
2031 emit_opcode(cbuf,0x0F);
2032 emit_opcode(cbuf,0x7E);
2033 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg));
2034 }
2035 %}
2036
2037
2038 // Encode a reg-reg copy. If it is useless, then empty encoding.
2039 enc_class enc_Copy( eRegI dst, eRegI src ) %{
2040 encode_Copy( cbuf, $dst$$reg, $src$$reg );
2041 %}
2042
2043 enc_class enc_CopyL_Lo( eRegI dst, eRegL src ) %{
2044 encode_Copy( cbuf, $dst$$reg, $src$$reg );
2045 %}
2046
2047 // Encode xmm reg-reg copy. If it is useless, then empty encoding.
2048 enc_class enc_CopyXD( RegXD dst, RegXD src ) %{
2049 encode_CopyXD( cbuf, $dst$$reg, $src$$reg );
2050 %}
2051
2052 enc_class RegReg (eRegI dst, eRegI src) %{ // RegReg(Many)
2053 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2054 %}
2055
2056 enc_class RegReg_Lo(eRegL dst, eRegL src) %{ // RegReg(Many)
2057 $$$emit8$primary;
2058 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2059 %}
2060
2061 enc_class RegReg_Hi(eRegL dst, eRegL src) %{ // RegReg(Many)
2062 $$$emit8$secondary;
2063 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg));
2064 %}
2065
2066 enc_class RegReg_Lo2(eRegL dst, eRegL src) %{ // RegReg(Many)
2067 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2068 %}
2069
2070 enc_class RegReg_Hi2(eRegL dst, eRegL src) %{ // RegReg(Many)
2071 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg));
2072 %}
2073
2074 enc_class RegReg_HiLo( eRegL src, eRegI dst ) %{
2075 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($src$$reg));
2076 %}
2077
2078 enc_class Con32 (immI src) %{ // Con32(storeImmI)
2079 // Output immediate
2080 $$$emit32$src$$constant;
2081 %}
2082
2083 enc_class Con32F_as_bits(immF src) %{ // storeF_imm
2084 // Output Float immediate bits
2085 jfloat jf = $src$$constant;
2086 int jf_as_bits = jint_cast( jf );
2087 emit_d32(cbuf, jf_as_bits);
2088 %}
2089
2090 enc_class Con32XF_as_bits(immXF src) %{ // storeX_imm
2091 // Output Float immediate bits
2092 jfloat jf = $src$$constant;
2093 int jf_as_bits = jint_cast( jf );
2094 emit_d32(cbuf, jf_as_bits);
2095 %}
2096
2097 enc_class Con16 (immI src) %{ // Con16(storeImmI)
2098 // Output immediate
2099 $$$emit16$src$$constant;
2100 %}
2101
2102 enc_class Con_d32(immI src) %{
2103 emit_d32(cbuf,$src$$constant);
2104 %}
2105
2106 enc_class conmemref (eRegP t1) %{ // Con32(storeImmI)
2107 // Output immediate memory reference
2108 emit_rm(cbuf, 0x00, $t1$$reg, 0x05 );
2109 emit_d32(cbuf, 0x00);
2110 %}
2111
2112 enc_class lock_prefix( ) %{
2113 if( os::is_MP() )
2114 emit_opcode(cbuf,0xF0); // [Lock]
2115 %}
2116
2117 // Cmp-xchg long value.
2118 // Note: we need to swap rbx, and rcx before and after the
2119 // cmpxchg8 instruction because the instruction uses
2120 // rcx as the high order word of the new value to store but
2121 // our register encoding uses rbx,.
2122 enc_class enc_cmpxchg8(eSIRegP mem_ptr) %{
2123
2124 // XCHG rbx,ecx
2125 emit_opcode(cbuf,0x87);
2126 emit_opcode(cbuf,0xD9);
2127 // [Lock]
2128 if( os::is_MP() )
2129 emit_opcode(cbuf,0xF0);
2130 // CMPXCHG8 [Eptr]
2131 emit_opcode(cbuf,0x0F);
2132 emit_opcode(cbuf,0xC7);
2133 emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg );
2134 // XCHG rbx,ecx
2135 emit_opcode(cbuf,0x87);
2136 emit_opcode(cbuf,0xD9);
2137 %}
2138
2139 enc_class enc_cmpxchg(eSIRegP mem_ptr) %{
2140 // [Lock]
2141 if( os::is_MP() )
2142 emit_opcode(cbuf,0xF0);
2143
2144 // CMPXCHG [Eptr]
2145 emit_opcode(cbuf,0x0F);
2146 emit_opcode(cbuf,0xB1);
2147 emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg );
2148 %}
2149
2150 enc_class enc_flags_ne_to_boolean( iRegI res ) %{
2151 int res_encoding = $res$$reg;
2152
2153 // MOV res,0
2154 emit_opcode( cbuf, 0xB8 + res_encoding);
2155 emit_d32( cbuf, 0 );
2156 // JNE,s fail
2157 emit_opcode(cbuf,0x75);
2158 emit_d8(cbuf, 5 );
2159 // MOV res,1
2160 emit_opcode( cbuf, 0xB8 + res_encoding);
2161 emit_d32( cbuf, 1 );
2162 // fail:
2163 %}
2164
2165 enc_class set_instruction_start( ) %{
2166 cbuf.set_inst_mark(); // Mark start of opcode for reloc info in mem operand
2167 %}
2168
2169 enc_class RegMem (eRegI ereg, memory mem) %{ // emit_reg_mem
2170 int reg_encoding = $ereg$$reg;
2171 int base = $mem$$base;
2172 int index = $mem$$index;
2173 int scale = $mem$$scale;
2174 int displace = $mem$$disp;
2175 bool disp_is_oop = $mem->disp_is_oop();
2176 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2177 %}
2178
2179 enc_class RegMem_Hi(eRegL ereg, memory mem) %{ // emit_reg_mem
2180 int reg_encoding = HIGH_FROM_LOW($ereg$$reg); // Hi register of pair, computed from lo
2181 int base = $mem$$base;
2182 int index = $mem$$index;
2183 int scale = $mem$$scale;
2184 int displace = $mem$$disp + 4; // Offset is 4 further in memory
2185 assert( !$mem->disp_is_oop(), "Cannot add 4 to oop" );
2186 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, false/*disp_is_oop*/);
2187 %}
2188
2189 enc_class move_long_small_shift( eRegL dst, immI_1_31 cnt ) %{
2190 int r1, r2;
2191 if( $tertiary == 0xA4 ) { r1 = $dst$$reg; r2 = HIGH_FROM_LOW($dst$$reg); }
2192 else { r2 = $dst$$reg; r1 = HIGH_FROM_LOW($dst$$reg); }
2193 emit_opcode(cbuf,0x0F);
2194 emit_opcode(cbuf,$tertiary);
2195 emit_rm(cbuf, 0x3, r1, r2);
2196 emit_d8(cbuf,$cnt$$constant);
2197 emit_d8(cbuf,$primary);
2198 emit_rm(cbuf, 0x3, $secondary, r1);
2199 emit_d8(cbuf,$cnt$$constant);
2200 %}
2201
2202 enc_class move_long_big_shift_sign( eRegL dst, immI_32_63 cnt ) %{
2203 emit_opcode( cbuf, 0x8B ); // Move
2204 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg));
2205 emit_d8(cbuf,$primary);
2206 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
2207 emit_d8(cbuf,$cnt$$constant-32);
2208 emit_d8(cbuf,$primary);
2209 emit_rm(cbuf, 0x3, $secondary, HIGH_FROM_LOW($dst$$reg));
2210 emit_d8(cbuf,31);
2211 %}
2212
2213 enc_class move_long_big_shift_clr( eRegL dst, immI_32_63 cnt ) %{
2214 int r1, r2;
2215 if( $secondary == 0x5 ) { r1 = $dst$$reg; r2 = HIGH_FROM_LOW($dst$$reg); }
2216 else { r2 = $dst$$reg; r1 = HIGH_FROM_LOW($dst$$reg); }
2217
2218 emit_opcode( cbuf, 0x8B ); // Move r1,r2
2219 emit_rm(cbuf, 0x3, r1, r2);
2220 if( $cnt$$constant > 32 ) { // Shift, if not by zero
2221 emit_opcode(cbuf,$primary);
2222 emit_rm(cbuf, 0x3, $secondary, r1);
2223 emit_d8(cbuf,$cnt$$constant-32);
2224 }
2225 emit_opcode(cbuf,0x33); // XOR r2,r2
2226 emit_rm(cbuf, 0x3, r2, r2);
2227 %}
2228
2229 // Clone of RegMem but accepts an extra parameter to access each
2230 // half of a double in memory; it never needs relocation info.
2231 enc_class Mov_MemD_half_to_Reg (immI opcode, memory mem, immI disp_for_half, eRegI rm_reg) %{
2232 emit_opcode(cbuf,$opcode$$constant);
2233 int reg_encoding = $rm_reg$$reg;
2234 int base = $mem$$base;
2235 int index = $mem$$index;
2236 int scale = $mem$$scale;
2237 int displace = $mem$$disp + $disp_for_half$$constant;
2238 bool disp_is_oop = false;
2239 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2240 %}
2241
2242 // !!!!! Special Custom Code used by MemMove, and stack access instructions !!!!!
2243 //
2244 // Clone of RegMem except the RM-byte's reg/opcode field is an ADLC-time constant
2245 // and it never needs relocation information.
2246 // Frequently used to move data between FPU's Stack Top and memory.
2247 enc_class RMopc_Mem_no_oop (immI rm_opcode, memory mem) %{
2248 int rm_byte_opcode = $rm_opcode$$constant;
2249 int base = $mem$$base;
2250 int index = $mem$$index;
2251 int scale = $mem$$scale;
2252 int displace = $mem$$disp;
2253 assert( !$mem->disp_is_oop(), "No oops here because no relo info allowed" );
2254 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, false);
2255 %}
2256
2257 enc_class RMopc_Mem (immI rm_opcode, memory mem) %{
2258 int rm_byte_opcode = $rm_opcode$$constant;
2259 int base = $mem$$base;
2260 int index = $mem$$index;
2261 int scale = $mem$$scale;
2262 int displace = $mem$$disp;
2263 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
2264 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_is_oop);
2265 %}
2266
2267 enc_class RegLea (eRegI dst, eRegI src0, immI src1 ) %{ // emit_reg_lea
2268 int reg_encoding = $dst$$reg;
2269 int base = $src0$$reg; // 0xFFFFFFFF indicates no base
2270 int index = 0x04; // 0x04 indicates no index
2271 int scale = 0x00; // 0x00 indicates no scale
2272 int displace = $src1$$constant; // 0x00 indicates no displacement
2273 bool disp_is_oop = false;
2274 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2275 %}
2276
2277 enc_class min_enc (eRegI dst, eRegI src) %{ // MIN
2278 // Compare dst,src
2279 emit_opcode(cbuf,0x3B);
2280 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2281 // jmp dst < src around move
2282 emit_opcode(cbuf,0x7C);
2283 emit_d8(cbuf,2);
2284 // move dst,src
2285 emit_opcode(cbuf,0x8B);
2286 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2287 %}
2288
2289 enc_class max_enc (eRegI dst, eRegI src) %{ // MAX
2290 // Compare dst,src
2291 emit_opcode(cbuf,0x3B);
2292 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2293 // jmp dst > src around move
2294 emit_opcode(cbuf,0x7F);
2295 emit_d8(cbuf,2);
2296 // move dst,src
2297 emit_opcode(cbuf,0x8B);
2298 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2299 %}
2300
2301 enc_class enc_FP_store(memory mem, regD src) %{
2302 // If src is FPR1, we can just FST to store it.
2303 // Else we need to FLD it to FPR1, then FSTP to store/pop it.
2304 int reg_encoding = 0x2; // Just store
2305 int base = $mem$$base;
2306 int index = $mem$$index;
2307 int scale = $mem$$scale;
2308 int displace = $mem$$disp;
2309 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
2310 if( $src$$reg != FPR1L_enc ) {
2311 reg_encoding = 0x3; // Store & pop
2312 emit_opcode( cbuf, 0xD9 ); // FLD (i.e., push it)
2313 emit_d8( cbuf, 0xC0-1+$src$$reg );
2314 }
2315 cbuf.set_inst_mark(); // Mark start of opcode for reloc info in mem operand
2316 emit_opcode(cbuf,$primary);
2317 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2318 %}
2319
2320 enc_class neg_reg(eRegI dst) %{
2321 // NEG $dst
2322 emit_opcode(cbuf,0xF7);
2323 emit_rm(cbuf, 0x3, 0x03, $dst$$reg );
2324 %}
2325
2326 enc_class setLT_reg(eCXRegI dst) %{
2327 // SETLT $dst
2328 emit_opcode(cbuf,0x0F);
2329 emit_opcode(cbuf,0x9C);
2330 emit_rm( cbuf, 0x3, 0x4, $dst$$reg );
2331 %}
2332
2333 enc_class enc_cmpLTP(ncxRegI p, ncxRegI q, ncxRegI y, eCXRegI tmp) %{ // cadd_cmpLT
2334 int tmpReg = $tmp$$reg;
2335
2336 // SUB $p,$q
2337 emit_opcode(cbuf,0x2B);
2338 emit_rm(cbuf, 0x3, $p$$reg, $q$$reg);
2339 // SBB $tmp,$tmp
2340 emit_opcode(cbuf,0x1B);
2341 emit_rm(cbuf, 0x3, tmpReg, tmpReg);
2342 // AND $tmp,$y
2343 emit_opcode(cbuf,0x23);
2344 emit_rm(cbuf, 0x3, tmpReg, $y$$reg);
2345 // ADD $p,$tmp
2346 emit_opcode(cbuf,0x03);
2347 emit_rm(cbuf, 0x3, $p$$reg, tmpReg);
2348 %}
2349
2350 enc_class enc_cmpLTP_mem(eRegI p, eRegI q, memory mem, eCXRegI tmp) %{ // cadd_cmpLT
2351 int tmpReg = $tmp$$reg;
2352
2353 // SUB $p,$q
2354 emit_opcode(cbuf,0x2B);
2355 emit_rm(cbuf, 0x3, $p$$reg, $q$$reg);
2356 // SBB $tmp,$tmp
2357 emit_opcode(cbuf,0x1B);
2358 emit_rm(cbuf, 0x3, tmpReg, tmpReg);
2359 // AND $tmp,$y
2360 cbuf.set_inst_mark(); // Mark start of opcode for reloc info in mem operand
2361 emit_opcode(cbuf,0x23);
2362 int reg_encoding = tmpReg;
2363 int base = $mem$$base;
2364 int index = $mem$$index;
2365 int scale = $mem$$scale;
2366 int displace = $mem$$disp;
2367 bool disp_is_oop = $mem->disp_is_oop();
2368 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2369 // ADD $p,$tmp
2370 emit_opcode(cbuf,0x03);
2371 emit_rm(cbuf, 0x3, $p$$reg, tmpReg);
2372 %}
2373
2374 enc_class shift_left_long( eRegL dst, eCXRegI shift ) %{
2375 // TEST shift,32
2376 emit_opcode(cbuf,0xF7);
2377 emit_rm(cbuf, 0x3, 0, ECX_enc);
2378 emit_d32(cbuf,0x20);
2379 // JEQ,s small
2380 emit_opcode(cbuf, 0x74);
2381 emit_d8(cbuf, 0x04);
2382 // MOV $dst.hi,$dst.lo
2383 emit_opcode( cbuf, 0x8B );
2384 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg );
2385 // CLR $dst.lo
2386 emit_opcode(cbuf, 0x33);
2387 emit_rm(cbuf, 0x3, $dst$$reg, $dst$$reg);
2388 // small:
2389 // SHLD $dst.hi,$dst.lo,$shift
2390 emit_opcode(cbuf,0x0F);
2391 emit_opcode(cbuf,0xA5);
2392 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg));
2393 // SHL $dst.lo,$shift"
2394 emit_opcode(cbuf,0xD3);
2395 emit_rm(cbuf, 0x3, 0x4, $dst$$reg );
2396 %}
2397
2398 enc_class shift_right_long( eRegL dst, eCXRegI shift ) %{
2399 // TEST shift,32
2400 emit_opcode(cbuf,0xF7);
2401 emit_rm(cbuf, 0x3, 0, ECX_enc);
2402 emit_d32(cbuf,0x20);
2403 // JEQ,s small
2404 emit_opcode(cbuf, 0x74);
2405 emit_d8(cbuf, 0x04);
2406 // MOV $dst.lo,$dst.hi
2407 emit_opcode( cbuf, 0x8B );
2408 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) );
2409 // CLR $dst.hi
2410 emit_opcode(cbuf, 0x33);
2411 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($dst$$reg));
2412 // small:
2413 // SHRD $dst.lo,$dst.hi,$shift
2414 emit_opcode(cbuf,0x0F);
2415 emit_opcode(cbuf,0xAD);
2416 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg);
2417 // SHR $dst.hi,$shift"
2418 emit_opcode(cbuf,0xD3);
2419 emit_rm(cbuf, 0x3, 0x5, HIGH_FROM_LOW($dst$$reg) );
2420 %}
2421
2422 enc_class shift_right_arith_long( eRegL dst, eCXRegI shift ) %{
2423 // TEST shift,32
2424 emit_opcode(cbuf,0xF7);
2425 emit_rm(cbuf, 0x3, 0, ECX_enc);
2426 emit_d32(cbuf,0x20);
2427 // JEQ,s small
2428 emit_opcode(cbuf, 0x74);
2429 emit_d8(cbuf, 0x05);
2430 // MOV $dst.lo,$dst.hi
2431 emit_opcode( cbuf, 0x8B );
2432 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) );
2433 // SAR $dst.hi,31
2434 emit_opcode(cbuf, 0xC1);
2435 emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW($dst$$reg) );
2436 emit_d8(cbuf, 0x1F );
2437 // small:
2438 // SHRD $dst.lo,$dst.hi,$shift
2439 emit_opcode(cbuf,0x0F);
2440 emit_opcode(cbuf,0xAD);
2441 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg);
2442 // SAR $dst.hi,$shift"
2443 emit_opcode(cbuf,0xD3);
2444 emit_rm(cbuf, 0x3, 0x7, HIGH_FROM_LOW($dst$$reg) );
2445 %}
2446
2447
2448 // ----------------- Encodings for floating point unit -----------------
2449 // May leave result in FPU-TOS or FPU reg depending on opcodes
2450 enc_class OpcReg_F (regF src) %{ // FMUL, FDIV
2451 $$$emit8$primary;
2452 emit_rm(cbuf, 0x3, $secondary, $src$$reg );
2453 %}
2454
2455 // Pop argument in FPR0 with FSTP ST(0)
2456 enc_class PopFPU() %{
2457 emit_opcode( cbuf, 0xDD );
2458 emit_d8( cbuf, 0xD8 );
2459 %}
2460
2461 // !!!!! equivalent to Pop_Reg_F
2462 enc_class Pop_Reg_D( regD dst ) %{
2463 emit_opcode( cbuf, 0xDD ); // FSTP ST(i)
2464 emit_d8( cbuf, 0xD8+$dst$$reg );
2465 %}
2466
2467 enc_class Push_Reg_D( regD dst ) %{
2468 emit_opcode( cbuf, 0xD9 );
2469 emit_d8( cbuf, 0xC0-1+$dst$$reg ); // FLD ST(i-1)
2470 %}
2471
2472 enc_class strictfp_bias1( regD dst ) %{
2473 emit_opcode( cbuf, 0xDB ); // FLD m80real
2474 emit_opcode( cbuf, 0x2D );
2475 emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias1() );
2476 emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0
2477 emit_opcode( cbuf, 0xC8+$dst$$reg );
2478 %}
2479
2480 enc_class strictfp_bias2( regD dst ) %{
2481 emit_opcode( cbuf, 0xDB ); // FLD m80real
2482 emit_opcode( cbuf, 0x2D );
2483 emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias2() );
2484 emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0
2485 emit_opcode( cbuf, 0xC8+$dst$$reg );
2486 %}
2487
2488 // Special case for moving an integer register to a stack slot.
2489 enc_class OpcPRegSS( stackSlotI dst, eRegI src ) %{ // RegSS
2490 store_to_stackslot( cbuf, $primary, $src$$reg, $dst$$disp );
2491 %}
2492
2493 // Special case for moving a register to a stack slot.
2494 enc_class RegSS( stackSlotI dst, eRegI src ) %{ // RegSS
2495 // Opcode already emitted
2496 emit_rm( cbuf, 0x02, $src$$reg, ESP_enc ); // R/M byte
2497 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
2498 emit_d32(cbuf, $dst$$disp); // Displacement
2499 %}
2500
2501 // Push the integer in stackSlot 'src' onto FP-stack
2502 enc_class Push_Mem_I( memory src ) %{ // FILD [ESP+src]
2503 store_to_stackslot( cbuf, $primary, $secondary, $src$$disp );
2504 %}
2505
2506 // Push the float in stackSlot 'src' onto FP-stack
2507 enc_class Push_Mem_F( memory src ) %{ // FLD_S [ESP+src]
2508 store_to_stackslot( cbuf, 0xD9, 0x00, $src$$disp );
2509 %}
2510
2511 // Push the double in stackSlot 'src' onto FP-stack
2512 enc_class Push_Mem_D( memory src ) %{ // FLD_D [ESP+src]
2513 store_to_stackslot( cbuf, 0xDD, 0x00, $src$$disp );
2514 %}
2515
2516 // Push FPU's TOS float to a stack-slot, and pop FPU-stack
2517 enc_class Pop_Mem_F( stackSlotF dst ) %{ // FSTP_S [ESP+dst]
2518 store_to_stackslot( cbuf, 0xD9, 0x03, $dst$$disp );
2519 %}
2520
2521 // Same as Pop_Mem_F except for opcode
2522 // Push FPU's TOS double to a stack-slot, and pop FPU-stack
2523 enc_class Pop_Mem_D( stackSlotD dst ) %{ // FSTP_D [ESP+dst]
2524 store_to_stackslot( cbuf, 0xDD, 0x03, $dst$$disp );
2525 %}
2526
2527 enc_class Pop_Reg_F( regF dst ) %{
2528 emit_opcode( cbuf, 0xDD ); // FSTP ST(i)
2529 emit_d8( cbuf, 0xD8+$dst$$reg );
2530 %}
2531
2532 enc_class Push_Reg_F( regF dst ) %{
2533 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2534 emit_d8( cbuf, 0xC0-1+$dst$$reg );
2535 %}
2536
2537 // Push FPU's float to a stack-slot, and pop FPU-stack
2538 enc_class Pop_Mem_Reg_F( stackSlotF dst, regF src ) %{
2539 int pop = 0x02;
2540 if ($src$$reg != FPR1L_enc) {
2541 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2542 emit_d8( cbuf, 0xC0-1+$src$$reg );
2543 pop = 0x03;
2544 }
2545 store_to_stackslot( cbuf, 0xD9, pop, $dst$$disp ); // FST<P>_S [ESP+dst]
2546 %}
2547
2548 // Push FPU's double to a stack-slot, and pop FPU-stack
2549 enc_class Pop_Mem_Reg_D( stackSlotD dst, regD src ) %{
2550 int pop = 0x02;
2551 if ($src$$reg != FPR1L_enc) {
2552 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2553 emit_d8( cbuf, 0xC0-1+$src$$reg );
2554 pop = 0x03;
2555 }
2556 store_to_stackslot( cbuf, 0xDD, pop, $dst$$disp ); // FST<P>_D [ESP+dst]
2557 %}
2558
2559 // Push FPU's double to a FPU-stack-slot, and pop FPU-stack
2560 enc_class Pop_Reg_Reg_D( regD dst, regF src ) %{
2561 int pop = 0xD0 - 1; // -1 since we skip FLD
2562 if ($src$$reg != FPR1L_enc) {
2563 emit_opcode( cbuf, 0xD9 ); // FLD ST(src-1)
2564 emit_d8( cbuf, 0xC0-1+$src$$reg );
2565 pop = 0xD8;
2566 }
2567 emit_opcode( cbuf, 0xDD );
2568 emit_d8( cbuf, pop+$dst$$reg ); // FST<P> ST(i)
2569 %}
2570
2571
2572 enc_class Mul_Add_F( regF dst, regF src, regF src1, regF src2 ) %{
2573 MacroAssembler masm(&cbuf);
2574 masm.fld_s( $src1$$reg-1); // nothing at TOS, load TOS from src1.reg
2575 masm.fmul( $src2$$reg+0); // value at TOS
2576 masm.fadd( $src$$reg+0); // value at TOS
2577 masm.fstp_d( $dst$$reg+0); // value at TOS, popped off after store
2578 %}
2579
2580
2581 enc_class Push_Reg_Mod_D( regD dst, regD src) %{
2582 // load dst in FPR0
2583 emit_opcode( cbuf, 0xD9 );
2584 emit_d8( cbuf, 0xC0-1+$dst$$reg );
2585 if ($src$$reg != FPR1L_enc) {
2586 // fincstp
2587 emit_opcode (cbuf, 0xD9);
2588 emit_opcode (cbuf, 0xF7);
2589 // swap src with FPR1:
2590 // FXCH FPR1 with src
2591 emit_opcode(cbuf, 0xD9);
2592 emit_d8(cbuf, 0xC8-1+$src$$reg );
2593 // fdecstp
2594 emit_opcode (cbuf, 0xD9);
2595 emit_opcode (cbuf, 0xF6);
2596 }
2597 %}
2598
2599 enc_class Push_ModD_encoding( regXD src0, regXD src1) %{
2600 // Allocate a word
2601 emit_opcode(cbuf,0x83); // SUB ESP,8
2602 emit_opcode(cbuf,0xEC);
2603 emit_d8(cbuf,0x08);
2604
2605 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], src1
2606 emit_opcode (cbuf, 0x0F );
2607 emit_opcode (cbuf, 0x11 );
2608 encode_RegMem(cbuf, $src1$$reg, ESP_enc, 0x4, 0, 0, false);
2609
2610 emit_opcode(cbuf,0xDD ); // FLD_D [ESP]
2611 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
2612
2613 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], src0
2614 emit_opcode (cbuf, 0x0F );
2615 emit_opcode (cbuf, 0x11 );
2616 encode_RegMem(cbuf, $src0$$reg, ESP_enc, 0x4, 0, 0, false);
2617
2618 emit_opcode(cbuf,0xDD ); // FLD_D [ESP]
2619 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
2620
2621 %}
2622
2623 enc_class Push_ModX_encoding( regX src0, regX src1) %{
2624 // Allocate a word
2625 emit_opcode(cbuf,0x83); // SUB ESP,4
2626 emit_opcode(cbuf,0xEC);
2627 emit_d8(cbuf,0x04);
2628
2629 emit_opcode (cbuf, 0xF3 ); // MOVSS [ESP], src1
2630 emit_opcode (cbuf, 0x0F );
2631 emit_opcode (cbuf, 0x11 );
2632 encode_RegMem(cbuf, $src1$$reg, ESP_enc, 0x4, 0, 0, false);
2633
2634 emit_opcode(cbuf,0xD9 ); // FLD [ESP]
2635 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
2636
2637 emit_opcode (cbuf, 0xF3 ); // MOVSS [ESP], src0
2638 emit_opcode (cbuf, 0x0F );
2639 emit_opcode (cbuf, 0x11 );
2640 encode_RegMem(cbuf, $src0$$reg, ESP_enc, 0x4, 0, 0, false);
2641
2642 emit_opcode(cbuf,0xD9 ); // FLD [ESP]
2643 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
2644
2645 %}
2646
2647 enc_class Push_ResultXD(regXD dst) %{
2648 store_to_stackslot( cbuf, 0xDD, 0x03, 0 ); //FSTP [ESP]
2649
2650 // UseXmmLoadAndClearUpper ? movsd dst,[esp] : movlpd dst,[esp]
2651 emit_opcode (cbuf, UseXmmLoadAndClearUpper ? 0xF2 : 0x66);
2652 emit_opcode (cbuf, 0x0F );
2653 emit_opcode (cbuf, UseXmmLoadAndClearUpper ? 0x10 : 0x12);
2654 encode_RegMem(cbuf, $dst$$reg, ESP_enc, 0x4, 0, 0, false);
2655
2656 emit_opcode(cbuf,0x83); // ADD ESP,8
2657 emit_opcode(cbuf,0xC4);
2658 emit_d8(cbuf,0x08);
2659 %}
2660
2661 enc_class Push_ResultX(regX dst, immI d8) %{
2662 store_to_stackslot( cbuf, 0xD9, 0x03, 0 ); //FSTP_S [ESP]
2663
2664 emit_opcode (cbuf, 0xF3 ); // MOVSS dst(xmm), [ESP]
2665 emit_opcode (cbuf, 0x0F );
2666 emit_opcode (cbuf, 0x10 );
2667 encode_RegMem(cbuf, $dst$$reg, ESP_enc, 0x4, 0, 0, false);
2668
2669 emit_opcode(cbuf,0x83); // ADD ESP,d8 (4 or 8)
2670 emit_opcode(cbuf,0xC4);
2671 emit_d8(cbuf,$d8$$constant);
2672 %}
2673
2674 enc_class Push_SrcXD(regXD src) %{
2675 // Allocate a word
2676 emit_opcode(cbuf,0x83); // SUB ESP,8
2677 emit_opcode(cbuf,0xEC);
2678 emit_d8(cbuf,0x08);
2679
2680 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], src
2681 emit_opcode (cbuf, 0x0F );
2682 emit_opcode (cbuf, 0x11 );
2683 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false);
2684
2685 emit_opcode(cbuf,0xDD ); // FLD_D [ESP]
2686 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
2687 %}
2688
2689 enc_class push_stack_temp_qword() %{
2690 emit_opcode(cbuf,0x83); // SUB ESP,8
2691 emit_opcode(cbuf,0xEC);
2692 emit_d8 (cbuf,0x08);
2693 %}
2694
2695 enc_class pop_stack_temp_qword() %{
2696 emit_opcode(cbuf,0x83); // ADD ESP,8
2697 emit_opcode(cbuf,0xC4);
2698 emit_d8 (cbuf,0x08);
2699 %}
2700
2701 enc_class push_xmm_to_fpr1( regXD xmm_src ) %{
2702 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], xmm_src
2703 emit_opcode (cbuf, 0x0F );
2704 emit_opcode (cbuf, 0x11 );
2705 encode_RegMem(cbuf, $xmm_src$$reg, ESP_enc, 0x4, 0, 0, false);
2706
2707 emit_opcode(cbuf,0xDD ); // FLD_D [ESP]
2708 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
2709 %}
2710
2711 // Compute X^Y using Intel's fast hardware instructions, if possible.
2712 // Otherwise return a NaN.
2713 enc_class pow_exp_core_encoding %{
2714 // FPR1 holds Y*ln2(X). Compute FPR1 = 2^(Y*ln2(X))
2715 emit_opcode(cbuf,0xD9); emit_opcode(cbuf,0xC0); // fdup = fld st(0) Q Q
2716 emit_opcode(cbuf,0xD9); emit_opcode(cbuf,0xFC); // frndint int(Q) Q
2717 emit_opcode(cbuf,0xDC); emit_opcode(cbuf,0xE9); // fsub st(1) -= st(0); int(Q) frac(Q)
2718 emit_opcode(cbuf,0xDB); // FISTP [ESP] frac(Q)
2719 emit_opcode(cbuf,0x1C);
2720 emit_d8(cbuf,0x24);
2721 emit_opcode(cbuf,0xD9); emit_opcode(cbuf,0xF0); // f2xm1 2^frac(Q)-1
2722 emit_opcode(cbuf,0xD9); emit_opcode(cbuf,0xE8); // fld1 1 2^frac(Q)-1
2723 emit_opcode(cbuf,0xDE); emit_opcode(cbuf,0xC1); // faddp 2^frac(Q)
2724 emit_opcode(cbuf,0x8B); // mov rax,[esp+0]=int(Q)
2725 encode_RegMem(cbuf, EAX_enc, ESP_enc, 0x4, 0, 0, false);
2726 emit_opcode(cbuf,0xC7); // mov rcx,0xFFFFF800 - overflow mask
2727 emit_rm(cbuf, 0x3, 0x0, ECX_enc);
2728 emit_d32(cbuf,0xFFFFF800);
2729 emit_opcode(cbuf,0x81); // add rax,1023 - the double exponent bias
2730 emit_rm(cbuf, 0x3, 0x0, EAX_enc);
2731 emit_d32(cbuf,1023);
2732 emit_opcode(cbuf,0x8B); // mov rbx,eax
2733 emit_rm(cbuf, 0x3, EBX_enc, EAX_enc);
2734 emit_opcode(cbuf,0xC1); // shl rax,20 - Slide to exponent position
2735 emit_rm(cbuf,0x3,0x4,EAX_enc);
2736 emit_d8(cbuf,20);
2737 emit_opcode(cbuf,0x85); // test rbx,ecx - check for overflow
2738 emit_rm(cbuf, 0x3, EBX_enc, ECX_enc);
2739 emit_opcode(cbuf,0x0F); emit_opcode(cbuf,0x45); // CMOVne rax,ecx - overflow; stuff NAN into EAX
2740 emit_rm(cbuf, 0x3, EAX_enc, ECX_enc);
2741 emit_opcode(cbuf,0x89); // mov [esp+4],eax - Store as part of double word
2742 encode_RegMem(cbuf, EAX_enc, ESP_enc, 0x4, 0, 4, false);
2743 emit_opcode(cbuf,0xC7); // mov [esp+0],0 - [ESP] = (double)(1<<int(Q)) = 2^int(Q)
2744 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
2745 emit_d32(cbuf,0);
2746 emit_opcode(cbuf,0xDC); // fmul dword st(0),[esp+0]; FPR1 = 2^int(Q)*2^frac(Q) = 2^Q
2747 encode_RegMem(cbuf, 0x1, ESP_enc, 0x4, 0, 0, false);
2748 %}
2749
2750 // enc_class Pop_Reg_Mod_D( regD dst, regD src)
2751 // was replaced by Push_Result_Mod_D followed by Pop_Reg_X() or Pop_Mem_X()
2752
2753 enc_class Push_Result_Mod_D( regD src) %{
2754 if ($src$$reg != FPR1L_enc) {
2755 // fincstp
2756 emit_opcode (cbuf, 0xD9);
2757 emit_opcode (cbuf, 0xF7);
2758 // FXCH FPR1 with src
2759 emit_opcode(cbuf, 0xD9);
2760 emit_d8(cbuf, 0xC8-1+$src$$reg );
2761 // fdecstp
2762 emit_opcode (cbuf, 0xD9);
2763 emit_opcode (cbuf, 0xF6);
2764 }
2765 // // following asm replaced with Pop_Reg_F or Pop_Mem_F
2766 // // FSTP FPR$dst$$reg
2767 // emit_opcode( cbuf, 0xDD );
2768 // emit_d8( cbuf, 0xD8+$dst$$reg );
2769 %}
2770
2771 enc_class fnstsw_sahf_skip_parity() %{
2772 // fnstsw ax
2773 emit_opcode( cbuf, 0xDF );
2774 emit_opcode( cbuf, 0xE0 );
2775 // sahf
2776 emit_opcode( cbuf, 0x9E );
2777 // jnp ::skip
2778 emit_opcode( cbuf, 0x7B );
2779 emit_opcode( cbuf, 0x05 );
2780 %}
2781
2782 enc_class emitModD() %{
2783 // fprem must be iterative
2784 // :: loop
2785 // fprem
2786 emit_opcode( cbuf, 0xD9 );
2787 emit_opcode( cbuf, 0xF8 );
2788 // wait
2789 emit_opcode( cbuf, 0x9b );
2790 // fnstsw ax
2791 emit_opcode( cbuf, 0xDF );
2792 emit_opcode( cbuf, 0xE0 );
2793 // sahf
2794 emit_opcode( cbuf, 0x9E );
2795 // jp ::loop
2796 emit_opcode( cbuf, 0x0F );
2797 emit_opcode( cbuf, 0x8A );
2798 emit_opcode( cbuf, 0xF4 );
2799 emit_opcode( cbuf, 0xFF );
2800 emit_opcode( cbuf, 0xFF );
2801 emit_opcode( cbuf, 0xFF );
2802 %}
2803
2804 enc_class fpu_flags() %{
2805 // fnstsw_ax
2806 emit_opcode( cbuf, 0xDF);
2807 emit_opcode( cbuf, 0xE0);
2808 // test ax,0x0400
2809 emit_opcode( cbuf, 0x66 ); // operand-size prefix for 16-bit immediate
2810 emit_opcode( cbuf, 0xA9 );
2811 emit_d16 ( cbuf, 0x0400 );
2812 // // // This sequence works, but stalls for 12-16 cycles on PPro
2813 // // test rax,0x0400
2814 // emit_opcode( cbuf, 0xA9 );
2815 // emit_d32 ( cbuf, 0x00000400 );
2816 //
2817 // jz exit (no unordered comparison)
2818 emit_opcode( cbuf, 0x74 );
2819 emit_d8 ( cbuf, 0x02 );
2820 // mov ah,1 - treat as LT case (set carry flag)
2821 emit_opcode( cbuf, 0xB4 );
2822 emit_d8 ( cbuf, 0x01 );
2823 // sahf
2824 emit_opcode( cbuf, 0x9E);
2825 %}
2826
2827 enc_class cmpF_P6_fixup() %{
2828 // Fixup the integer flags in case comparison involved a NaN
2829 //
2830 // JNP exit (no unordered comparison, P-flag is set by NaN)
2831 emit_opcode( cbuf, 0x7B );
2832 emit_d8 ( cbuf, 0x03 );
2833 // MOV AH,1 - treat as LT case (set carry flag)
2834 emit_opcode( cbuf, 0xB4 );
2835 emit_d8 ( cbuf, 0x01 );
2836 // SAHF
2837 emit_opcode( cbuf, 0x9E);
2838 // NOP // target for branch to avoid branch to branch
2839 emit_opcode( cbuf, 0x90);
2840 %}
2841
2842 // fnstsw_ax();
2843 // sahf();
2844 // movl(dst, nan_result);
2845 // jcc(Assembler::parity, exit);
2846 // movl(dst, less_result);
2847 // jcc(Assembler::below, exit);
2848 // movl(dst, equal_result);
2849 // jcc(Assembler::equal, exit);
2850 // movl(dst, greater_result);
2851
2852 // less_result = 1;
2853 // greater_result = -1;
2854 // equal_result = 0;
2855 // nan_result = -1;
2856
2857 enc_class CmpF_Result(eRegI dst) %{
2858 // fnstsw_ax();
2859 emit_opcode( cbuf, 0xDF);
2860 emit_opcode( cbuf, 0xE0);
2861 // sahf
2862 emit_opcode( cbuf, 0x9E);
2863 // movl(dst, nan_result);
2864 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2865 emit_d32( cbuf, -1 );
2866 // jcc(Assembler::parity, exit);
2867 emit_opcode( cbuf, 0x7A );
2868 emit_d8 ( cbuf, 0x13 );
2869 // movl(dst, less_result);
2870 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2871 emit_d32( cbuf, -1 );
2872 // jcc(Assembler::below, exit);
2873 emit_opcode( cbuf, 0x72 );
2874 emit_d8 ( cbuf, 0x0C );
2875 // movl(dst, equal_result);
2876 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2877 emit_d32( cbuf, 0 );
2878 // jcc(Assembler::equal, exit);
2879 emit_opcode( cbuf, 0x74 );
2880 emit_d8 ( cbuf, 0x05 );
2881 // movl(dst, greater_result);
2882 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2883 emit_d32( cbuf, 1 );
2884 %}
2885
2886
2887 // XMM version of CmpF_Result. Because the XMM compare
2888 // instructions set the EFLAGS directly. It becomes simpler than
2889 // the float version above.
2890 enc_class CmpX_Result(eRegI dst) %{
2891 MacroAssembler _masm(&cbuf);
2892 Label nan, inc, done;
2893
2894 __ jccb(Assembler::parity, nan);
2895 __ jccb(Assembler::equal, done);
2896 __ jccb(Assembler::above, inc);
2897 __ bind(nan);
2898 __ decrement(as_Register($dst$$reg)); // NO L qqq
2899 __ jmpb(done);
2900 __ bind(inc);
2901 __ increment(as_Register($dst$$reg)); // NO L qqq
2902 __ bind(done);
2903 %}
2904
2905 // Compare the longs and set flags
2906 // BROKEN! Do Not use as-is
2907 enc_class cmpl_test( eRegL src1, eRegL src2 ) %{
2908 // CMP $src1.hi,$src2.hi
2909 emit_opcode( cbuf, 0x3B );
2910 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) );
2911 // JNE,s done
2912 emit_opcode(cbuf,0x75);
2913 emit_d8(cbuf, 2 );
2914 // CMP $src1.lo,$src2.lo
2915 emit_opcode( cbuf, 0x3B );
2916 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
2917 // done:
2918 %}
2919
2920 enc_class convert_int_long( regL dst, eRegI src ) %{
2921 // mov $dst.lo,$src
2922 int dst_encoding = $dst$$reg;
2923 int src_encoding = $src$$reg;
2924 encode_Copy( cbuf, dst_encoding , src_encoding );
2925 // mov $dst.hi,$src
2926 encode_Copy( cbuf, HIGH_FROM_LOW(dst_encoding), src_encoding );
2927 // sar $dst.hi,31
2928 emit_opcode( cbuf, 0xC1 );
2929 emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW(dst_encoding) );
2930 emit_d8(cbuf, 0x1F );
2931 %}
2932
2933 enc_class convert_long_double( eRegL src ) %{
2934 // push $src.hi
2935 emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg));
2936 // push $src.lo
2937 emit_opcode(cbuf, 0x50+$src$$reg );
2938 // fild 64-bits at [SP]
2939 emit_opcode(cbuf,0xdf);
2940 emit_d8(cbuf, 0x6C);
2941 emit_d8(cbuf, 0x24);
2942 emit_d8(cbuf, 0x00);
2943 // pop stack
2944 emit_opcode(cbuf, 0x83); // add SP, #8
2945 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
2946 emit_d8(cbuf, 0x8);
2947 %}
2948
2949 enc_class multiply_con_and_shift_high( eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr ) %{
2950 // IMUL EDX:EAX,$src1
2951 emit_opcode( cbuf, 0xF7 );
2952 emit_rm( cbuf, 0x3, 0x5, $src1$$reg );
2953 // SAR EDX,$cnt-32
2954 int shift_count = ((int)$cnt$$constant) - 32;
2955 if (shift_count > 0) {
2956 emit_opcode(cbuf, 0xC1);
2957 emit_rm(cbuf, 0x3, 7, $dst$$reg );
2958 emit_d8(cbuf, shift_count);
2959 }
2960 %}
2961
2962 // this version doesn't have add sp, 8
2963 enc_class convert_long_double2( eRegL src ) %{
2964 // push $src.hi
2965 emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg));
2966 // push $src.lo
2967 emit_opcode(cbuf, 0x50+$src$$reg );
2968 // fild 64-bits at [SP]
2969 emit_opcode(cbuf,0xdf);
2970 emit_d8(cbuf, 0x6C);
2971 emit_d8(cbuf, 0x24);
2972 emit_d8(cbuf, 0x00);
2973 %}
2974
2975 enc_class long_int_multiply( eADXRegL dst, nadxRegI src) %{
2976 // Basic idea: long = (long)int * (long)int
2977 // IMUL EDX:EAX, src
2978 emit_opcode( cbuf, 0xF7 );
2979 emit_rm( cbuf, 0x3, 0x5, $src$$reg);
2980 %}
2981
2982 enc_class long_uint_multiply( eADXRegL dst, nadxRegI src) %{
2983 // Basic Idea: long = (int & 0xffffffffL) * (int & 0xffffffffL)
2984 // MUL EDX:EAX, src
2985 emit_opcode( cbuf, 0xF7 );
2986 emit_rm( cbuf, 0x3, 0x4, $src$$reg);
2987 %}
2988
2989 enc_class long_multiply( eADXRegL dst, eRegL src, eRegI tmp ) %{
2990 // Basic idea: lo(result) = lo(x_lo * y_lo)
2991 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
2992 // MOV $tmp,$src.lo
2993 encode_Copy( cbuf, $tmp$$reg, $src$$reg );
2994 // IMUL $tmp,EDX
2995 emit_opcode( cbuf, 0x0F );
2996 emit_opcode( cbuf, 0xAF );
2997 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
2998 // MOV EDX,$src.hi
2999 encode_Copy( cbuf, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg) );
3000 // IMUL EDX,EAX
3001 emit_opcode( cbuf, 0x0F );
3002 emit_opcode( cbuf, 0xAF );
3003 emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg );
3004 // ADD $tmp,EDX
3005 emit_opcode( cbuf, 0x03 );
3006 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
3007 // MUL EDX:EAX,$src.lo
3008 emit_opcode( cbuf, 0xF7 );
3009 emit_rm( cbuf, 0x3, 0x4, $src$$reg );
3010 // ADD EDX,ESI
3011 emit_opcode( cbuf, 0x03 );
3012 emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $tmp$$reg );
3013 %}
3014
3015 enc_class long_multiply_con( eADXRegL dst, immL_127 src, eRegI tmp ) %{
3016 // Basic idea: lo(result) = lo(src * y_lo)
3017 // hi(result) = hi(src * y_lo) + lo(src * y_hi)
3018 // IMUL $tmp,EDX,$src
3019 emit_opcode( cbuf, 0x6B );
3020 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
3021 emit_d8( cbuf, (int)$src$$constant );
3022 // MOV EDX,$src
3023 emit_opcode(cbuf, 0xB8 + EDX_enc);
3024 emit_d32( cbuf, (int)$src$$constant );
3025 // MUL EDX:EAX,EDX
3026 emit_opcode( cbuf, 0xF7 );
3027 emit_rm( cbuf, 0x3, 0x4, EDX_enc );
3028 // ADD EDX,ESI
3029 emit_opcode( cbuf, 0x03 );
3030 emit_rm( cbuf, 0x3, EDX_enc, $tmp$$reg );
3031 %}
3032
3033 enc_class long_div( eRegL src1, eRegL src2 ) %{
3034 // PUSH src1.hi
3035 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) );
3036 // PUSH src1.lo
3037 emit_opcode(cbuf, 0x50+$src1$$reg );
3038 // PUSH src2.hi
3039 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) );
3040 // PUSH src2.lo
3041 emit_opcode(cbuf, 0x50+$src2$$reg );
3042 // CALL directly to the runtime
3043 cbuf.set_inst_mark();
3044 emit_opcode(cbuf,0xE8); // Call into runtime
3045 emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::ldiv) - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
3046 // Restore stack
3047 emit_opcode(cbuf, 0x83); // add SP, #framesize
3048 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
3049 emit_d8(cbuf, 4*4);
3050 %}
3051
3052 enc_class long_mod( eRegL src1, eRegL src2 ) %{
3053 // PUSH src1.hi
3054 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) );
3055 // PUSH src1.lo
3056 emit_opcode(cbuf, 0x50+$src1$$reg );
3057 // PUSH src2.hi
3058 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) );
3059 // PUSH src2.lo
3060 emit_opcode(cbuf, 0x50+$src2$$reg );
3061 // CALL directly to the runtime
3062 cbuf.set_inst_mark();
3063 emit_opcode(cbuf,0xE8); // Call into runtime
3064 emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::lrem ) - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
3065 // Restore stack
3066 emit_opcode(cbuf, 0x83); // add SP, #framesize
3067 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
3068 emit_d8(cbuf, 4*4);
3069 %}
3070
3071 enc_class long_cmp_flags0( eRegL src, eRegI tmp ) %{
3072 // MOV $tmp,$src.lo
3073 emit_opcode(cbuf, 0x8B);
3074 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg);
3075 // OR $tmp,$src.hi
3076 emit_opcode(cbuf, 0x0B);
3077 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg));
3078 %}
3079
3080 enc_class long_cmp_flags1( eRegL src1, eRegL src2 ) %{
3081 // CMP $src1.lo,$src2.lo
3082 emit_opcode( cbuf, 0x3B );
3083 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
3084 // JNE,s skip
3085 emit_cc(cbuf, 0x70, 0x5);
3086 emit_d8(cbuf,2);
3087 // CMP $src1.hi,$src2.hi
3088 emit_opcode( cbuf, 0x3B );
3089 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) );
3090 %}
3091
3092 enc_class long_cmp_flags2( eRegL src1, eRegL src2, eRegI tmp ) %{
3093 // CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits
3094 emit_opcode( cbuf, 0x3B );
3095 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
3096 // MOV $tmp,$src1.hi
3097 emit_opcode( cbuf, 0x8B );
3098 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src1$$reg) );
3099 // SBB $tmp,$src2.hi\t! Compute flags for long compare
3100 emit_opcode( cbuf, 0x1B );
3101 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src2$$reg) );
3102 %}
3103
3104 enc_class long_cmp_flags3( eRegL src, eRegI tmp ) %{
3105 // XOR $tmp,$tmp
3106 emit_opcode(cbuf,0x33); // XOR
3107 emit_rm(cbuf,0x3, $tmp$$reg, $tmp$$reg);
3108 // CMP $tmp,$src.lo
3109 emit_opcode( cbuf, 0x3B );
3110 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg );
3111 // SBB $tmp,$src.hi
3112 emit_opcode( cbuf, 0x1B );
3113 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg) );
3114 %}
3115
3116 // Sniff, sniff... smells like Gnu Superoptimizer
3117 enc_class neg_long( eRegL dst ) %{
3118 emit_opcode(cbuf,0xF7); // NEG hi
3119 emit_rm (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg));
3120 emit_opcode(cbuf,0xF7); // NEG lo
3121 emit_rm (cbuf,0x3, 0x3, $dst$$reg );
3122 emit_opcode(cbuf,0x83); // SBB hi,0
3123 emit_rm (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg));
3124 emit_d8 (cbuf,0 );
3125 %}
3126
3127 enc_class movq_ld(regXD dst, memory mem) %{
3128 MacroAssembler _masm(&cbuf);
3129 __ movq($dst$$XMMRegister, $mem$$Address);
3130 %}
3131
3132 enc_class movq_st(memory mem, regXD src) %{
3133 MacroAssembler _masm(&cbuf);
3134 __ movq($mem$$Address, $src$$XMMRegister);
3135 %}
3136
3137 enc_class pshufd_8x8(regX dst, regX src) %{
3138 MacroAssembler _masm(&cbuf);
3139
3140 encode_CopyXD(cbuf, $dst$$reg, $src$$reg);
3141 __ punpcklbw(as_XMMRegister($dst$$reg), as_XMMRegister($dst$$reg));
3142 __ pshuflw(as_XMMRegister($dst$$reg), as_XMMRegister($dst$$reg), 0x00);
3143 %}
3144
3145 enc_class pshufd_4x16(regX dst, regX src) %{
3146 MacroAssembler _masm(&cbuf);
3147
3148 __ pshuflw(as_XMMRegister($dst$$reg), as_XMMRegister($src$$reg), 0x00);
3149 %}
3150
3151 enc_class pshufd(regXD dst, regXD src, int mode) %{
3152 MacroAssembler _masm(&cbuf);
3153
3154 __ pshufd(as_XMMRegister($dst$$reg), as_XMMRegister($src$$reg), $mode);
3155 %}
3156
3157 enc_class pxor(regXD dst, regXD src) %{
3158 MacroAssembler _masm(&cbuf);
3159
3160 __ pxor(as_XMMRegister($dst$$reg), as_XMMRegister($src$$reg));
3161 %}
3162
3163 enc_class mov_i2x(regXD dst, eRegI src) %{
3164 MacroAssembler _masm(&cbuf);
3165
3166 __ movdl(as_XMMRegister($dst$$reg), as_Register($src$$reg));
3167 %}
3168
3169
3170 // Because the transitions from emitted code to the runtime
3171 // monitorenter/exit helper stubs are so slow it's critical that
3172 // we inline both the stack-locking fast-path and the inflated fast path.
3173 //
3174 // See also: cmpFastLock and cmpFastUnlock.
3175 //
3176 // What follows is a specialized inline transliteration of the code
3177 // in slow_enter() and slow_exit(). If we're concerned about I$ bloat
3178 // another option would be to emit TrySlowEnter and TrySlowExit methods
3179 // at startup-time. These methods would accept arguments as
3180 // (rax,=Obj, rbx=Self, rcx=box, rdx=Scratch) and return success-failure
3181 // indications in the icc.ZFlag. Fast_Lock and Fast_Unlock would simply
3182 // marshal the arguments and emit calls to TrySlowEnter and TrySlowExit.
3183 // In practice, however, the # of lock sites is bounded and is usually small.
3184 // Besides the call overhead, TrySlowEnter and TrySlowExit might suffer
3185 // if the processor uses simple bimodal branch predictors keyed by EIP
3186 // Since the helper routines would be called from multiple synchronization
3187 // sites.
3188 //
3189 // An even better approach would be write "MonitorEnter()" and "MonitorExit()"
3190 // in java - using j.u.c and unsafe - and just bind the lock and unlock sites
3191 // to those specialized methods. That'd give us a mostly platform-independent
3192 // implementation that the JITs could optimize and inline at their pleasure.
3193 // Done correctly, the only time we'd need to cross to native could would be
3194 // to park() or unpark() threads. We'd also need a few more unsafe operators
3195 // to (a) prevent compiler-JIT reordering of non-volatile accesses, and
3196 // (b) explicit barriers or fence operations.
3197 //
3198 // TODO:
3199 //
3200 // * Arrange for C2 to pass "Self" into Fast_Lock and Fast_Unlock in one of the registers (scr).
3201 // This avoids manifesting the Self pointer in the Fast_Lock and Fast_Unlock terminals.
3202 // Given TLAB allocation, Self is usually manifested in a register, so passing it into
3203 // the lock operators would typically be faster than reifying Self.
3204 //
3205 // * Ideally I'd define the primitives as:
3206 // fast_lock (nax Obj, nax box, EAX tmp, nax scr) where box, tmp and scr are KILLED.
3207 // fast_unlock (nax Obj, EAX box, nax tmp) where box and tmp are KILLED
3208 // Unfortunately ADLC bugs prevent us from expressing the ideal form.
3209 // Instead, we're stuck with a rather awkward and brittle register assignments below.
3210 // Furthermore the register assignments are overconstrained, possibly resulting in
3211 // sub-optimal code near the synchronization site.
3212 //
3213 // * Eliminate the sp-proximity tests and just use "== Self" tests instead.
3214 // Alternately, use a better sp-proximity test.
3215 //
3216 // * Currently ObjectMonitor._Owner can hold either an sp value or a (THREAD *) value.
3217 // Either one is sufficient to uniquely identify a thread.
3218 // TODO: eliminate use of sp in _owner and use get_thread(tr) instead.
3219 //
3220 // * Intrinsify notify() and notifyAll() for the common cases where the
3221 // object is locked by the calling thread but the waitlist is empty.
3222 // avoid the expensive JNI call to JVM_Notify() and JVM_NotifyAll().
3223 //
3224 // * use jccb and jmpb instead of jcc and jmp to improve code density.
3225 // But beware of excessive branch density on AMD Opterons.
3226 //
3227 // * Both Fast_Lock and Fast_Unlock set the ICC.ZF to indicate success
3228 // or failure of the fast-path. If the fast-path fails then we pass
3229 // control to the slow-path, typically in C. In Fast_Lock and
3230 // Fast_Unlock we often branch to DONE_LABEL, just to find that C2
3231 // will emit a conditional branch immediately after the node.
3232 // So we have branches to branches and lots of ICC.ZF games.
3233 // Instead, it might be better to have C2 pass a "FailureLabel"
3234 // into Fast_Lock and Fast_Unlock. In the case of success, control
3235 // will drop through the node. ICC.ZF is undefined at exit.
3236 // In the case of failure, the node will branch directly to the
3237 // FailureLabel
3238
3239
3240 // obj: object to lock
3241 // box: on-stack box address (displaced header location) - KILLED
3242 // rax,: tmp -- KILLED
3243 // scr: tmp -- KILLED
3244 enc_class Fast_Lock( eRegP obj, eRegP box, eAXRegI tmp, eRegP scr ) %{
3245
3246 Register objReg = as_Register($obj$$reg);
3247 Register boxReg = as_Register($box$$reg);
3248 Register tmpReg = as_Register($tmp$$reg);
3249 Register scrReg = as_Register($scr$$reg);
3250
3251 // Ensure the register assignents are disjoint
3252 guarantee (objReg != boxReg, "") ;
3253 guarantee (objReg != tmpReg, "") ;
3254 guarantee (objReg != scrReg, "") ;
3255 guarantee (boxReg != tmpReg, "") ;
3256 guarantee (boxReg != scrReg, "") ;
3257 guarantee (tmpReg == as_Register(EAX_enc), "") ;
3258
3259 MacroAssembler masm(&cbuf);
3260
3261 if (_counters != NULL) {
3262 masm.atomic_incl(ExternalAddress((address) _counters->total_entry_count_addr()));
3263 }
3264 if (EmitSync & 1) {
3265 // set box->dhw = unused_mark (3)
3266 // Force all sync thru slow-path: slow_enter() and slow_exit()
3267 masm.movptr (Address(boxReg, 0), int32_t(markOopDesc::unused_mark())) ;
3268 masm.cmpptr (rsp, (int32_t)0) ;
3269 } else
3270 if (EmitSync & 2) {
3271 Label DONE_LABEL ;
3272 if (UseBiasedLocking) {
3273 // Note: tmpReg maps to the swap_reg argument and scrReg to the tmp_reg argument.
3274 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters);
3275 }
3276
3277 masm.movptr(tmpReg, Address(objReg, 0)) ; // fetch markword
3278 masm.orptr (tmpReg, 0x1);
3279 masm.movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS
3280 if (os::is_MP()) { masm.lock(); }
3281 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
3282 masm.jcc(Assembler::equal, DONE_LABEL);
3283 // Recursive locking
3284 masm.subptr(tmpReg, rsp);
3285 masm.andptr(tmpReg, (int32_t) 0xFFFFF003 );
3286 masm.movptr(Address(boxReg, 0), tmpReg);
3287 masm.bind(DONE_LABEL) ;
3288 } else {
3289 // Possible cases that we'll encounter in fast_lock
3290 // ------------------------------------------------
3291 // * Inflated
3292 // -- unlocked
3293 // -- Locked
3294 // = by self
3295 // = by other
3296 // * biased
3297 // -- by Self
3298 // -- by other
3299 // * neutral
3300 // * stack-locked
3301 // -- by self
3302 // = sp-proximity test hits
3303 // = sp-proximity test generates false-negative
3304 // -- by other
3305 //
3306
3307 Label IsInflated, DONE_LABEL, PopDone ;
3308
3309 // TODO: optimize away redundant LDs of obj->mark and improve the markword triage
3310 // order to reduce the number of conditional branches in the most common cases.
3311 // Beware -- there's a subtle invariant that fetch of the markword
3312 // at [FETCH], below, will never observe a biased encoding (*101b).
3313 // If this invariant is not held we risk exclusion (safety) failure.
3314 if (UseBiasedLocking && !UseOptoBiasInlining) {
3315 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters);
3316 }
3317
3318 masm.movptr(tmpReg, Address(objReg, 0)) ; // [FETCH]
3319 masm.testptr(tmpReg, 0x02) ; // Inflated v (Stack-locked or neutral)
3320 masm.jccb (Assembler::notZero, IsInflated) ;
3321
3322 // Attempt stack-locking ...
3323 masm.orptr (tmpReg, 0x1);
3324 masm.movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS
3325 if (os::is_MP()) { masm.lock(); }
3326 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
3327 if (_counters != NULL) {
3328 masm.cond_inc32(Assembler::equal,
3329 ExternalAddress((address)_counters->fast_path_entry_count_addr()));
3330 }
3331 masm.jccb (Assembler::equal, DONE_LABEL);
3332
3333 // Recursive locking
3334 masm.subptr(tmpReg, rsp);
3335 masm.andptr(tmpReg, 0xFFFFF003 );
3336 masm.movptr(Address(boxReg, 0), tmpReg);
3337 if (_counters != NULL) {
3338 masm.cond_inc32(Assembler::equal,
3339 ExternalAddress((address)_counters->fast_path_entry_count_addr()));
3340 }
3341 masm.jmp (DONE_LABEL) ;
3342
3343 masm.bind (IsInflated) ;
3344
3345 // The object is inflated.
3346 //
3347 // TODO-FIXME: eliminate the ugly use of manifest constants:
3348 // Use markOopDesc::monitor_value instead of "2".
3349 // use markOop::unused_mark() instead of "3".
3350 // The tmpReg value is an objectMonitor reference ORed with
3351 // markOopDesc::monitor_value (2). We can either convert tmpReg to an
3352 // objectmonitor pointer by masking off the "2" bit or we can just
3353 // use tmpReg as an objectmonitor pointer but bias the objectmonitor
3354 // field offsets with "-2" to compensate for and annul the low-order tag bit.
3355 //
3356 // I use the latter as it avoids AGI stalls.
3357 // As such, we write "mov r, [tmpReg+OFFSETOF(Owner)-2]"
3358 // instead of "mov r, [tmpReg+OFFSETOF(Owner)]".
3359 //
3360 #define OFFSET_SKEWED(f) ((ObjectMonitor::f ## _offset_in_bytes())-2)
3361
3362 // boxReg refers to the on-stack BasicLock in the current frame.
3363 // We'd like to write:
3364 // set box->_displaced_header = markOop::unused_mark(). Any non-0 value suffices.
3365 // This is convenient but results a ST-before-CAS penalty. The following CAS suffers
3366 // additional latency as we have another ST in the store buffer that must drain.
3367
3368 if (EmitSync & 8192) {
3369 masm.movptr(Address(boxReg, 0), 3) ; // results in ST-before-CAS penalty
3370 masm.get_thread (scrReg) ;
3371 masm.movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
3372 masm.movptr(tmpReg, NULL_WORD); // consider: xor vs mov
3373 if (os::is_MP()) { masm.lock(); }
3374 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3375 } else
3376 if ((EmitSync & 128) == 0) { // avoid ST-before-CAS
3377 masm.movptr(scrReg, boxReg) ;
3378 masm.movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
3379
3380 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
3381 if ((EmitSync & 2048) && VM_Version::supports_3dnow() && os::is_MP()) {
3382 // prefetchw [eax + Offset(_owner)-2]
3383 masm.prefetchw(Address(rax, ObjectMonitor::owner_offset_in_bytes()-2));
3384 }
3385
3386 if ((EmitSync & 64) == 0) {
3387 // Optimistic form: consider XORL tmpReg,tmpReg
3388 masm.movptr(tmpReg, NULL_WORD) ;
3389 } else {
3390 // Can suffer RTS->RTO upgrades on shared or cold $ lines
3391 // Test-And-CAS instead of CAS
3392 masm.movptr(tmpReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; // rax, = m->_owner
3393 masm.testptr(tmpReg, tmpReg) ; // Locked ?
3394 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3395 }
3396
3397 // Appears unlocked - try to swing _owner from null to non-null.
3398 // Ideally, I'd manifest "Self" with get_thread and then attempt
3399 // to CAS the register containing Self into m->Owner.
3400 // But we don't have enough registers, so instead we can either try to CAS
3401 // rsp or the address of the box (in scr) into &m->owner. If the CAS succeeds
3402 // we later store "Self" into m->Owner. Transiently storing a stack address
3403 // (rsp or the address of the box) into m->owner is harmless.
3404 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
3405 if (os::is_MP()) { masm.lock(); }
3406 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3407 masm.movptr(Address(scrReg, 0), 3) ; // box->_displaced_header = 3
3408 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3409 masm.get_thread (scrReg) ; // beware: clobbers ICCs
3410 masm.movptr(Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2), scrReg) ;
3411 masm.xorptr(boxReg, boxReg) ; // set icc.ZFlag = 1 to indicate success
3412
3413 // If the CAS fails we can either retry or pass control to the slow-path.
3414 // We use the latter tactic.
3415 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
3416 // If the CAS was successful ...
3417 // Self has acquired the lock
3418 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
3419 // Intentional fall-through into DONE_LABEL ...
3420 } else {
3421 masm.movptr(Address(boxReg, 0), 3) ; // results in ST-before-CAS penalty
3422 masm.movptr(boxReg, tmpReg) ;
3423
3424 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
3425 if ((EmitSync & 2048) && VM_Version::supports_3dnow() && os::is_MP()) {
3426 // prefetchw [eax + Offset(_owner)-2]
3427 masm.prefetchw(Address(rax, ObjectMonitor::owner_offset_in_bytes()-2));
3428 }
3429
3430 if ((EmitSync & 64) == 0) {
3431 // Optimistic form
3432 masm.xorptr (tmpReg, tmpReg) ;
3433 } else {
3434 // Can suffer RTS->RTO upgrades on shared or cold $ lines
3435 masm.movptr(tmpReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; // rax, = m->_owner
3436 masm.testptr(tmpReg, tmpReg) ; // Locked ?
3437 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3438 }
3439
3440 // Appears unlocked - try to swing _owner from null to non-null.
3441 // Use either "Self" (in scr) or rsp as thread identity in _owner.
3442 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
3443 masm.get_thread (scrReg) ;
3444 if (os::is_MP()) { masm.lock(); }
3445 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3446
3447 // If the CAS fails we can either retry or pass control to the slow-path.
3448 // We use the latter tactic.
3449 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
3450 // If the CAS was successful ...
3451 // Self has acquired the lock
3452 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
3453 // Intentional fall-through into DONE_LABEL ...
3454 }
3455
3456 // DONE_LABEL is a hot target - we'd really like to place it at the
3457 // start of cache line by padding with NOPs.
3458 // See the AMD and Intel software optimization manuals for the
3459 // most efficient "long" NOP encodings.
3460 // Unfortunately none of our alignment mechanisms suffice.
3461 masm.bind(DONE_LABEL);
3462
3463 // Avoid branch-to-branch on AMD processors
3464 // This appears to be superstition.
3465 if (EmitSync & 32) masm.nop() ;
3466
3467
3468 // At DONE_LABEL the icc ZFlag is set as follows ...
3469 // Fast_Unlock uses the same protocol.
3470 // ZFlag == 1 -> Success
3471 // ZFlag == 0 -> Failure - force control through the slow-path
3472 }
3473 %}
3474
3475 // obj: object to unlock
3476 // box: box address (displaced header location), killed. Must be EAX.
3477 // rbx,: killed tmp; cannot be obj nor box.
3478 //
3479 // Some commentary on balanced locking:
3480 //
3481 // Fast_Lock and Fast_Unlock are emitted only for provably balanced lock sites.
3482 // Methods that don't have provably balanced locking are forced to run in the
3483 // interpreter - such methods won't be compiled to use fast_lock and fast_unlock.
3484 // The interpreter provides two properties:
3485 // I1: At return-time the interpreter automatically and quietly unlocks any
3486 // objects acquired the current activation (frame). Recall that the
3487 // interpreter maintains an on-stack list of locks currently held by
3488 // a frame.
3489 // I2: If a method attempts to unlock an object that is not held by the
3490 // the frame the interpreter throws IMSX.
3491 //
3492 // Lets say A(), which has provably balanced locking, acquires O and then calls B().
3493 // B() doesn't have provably balanced locking so it runs in the interpreter.
3494 // Control returns to A() and A() unlocks O. By I1 and I2, above, we know that O
3495 // is still locked by A().
3496 //
3497 // The only other source of unbalanced locking would be JNI. The "Java Native Interface:
3498 // Programmer's Guide and Specification" claims that an object locked by jni_monitorenter
3499 // should not be unlocked by "normal" java-level locking and vice-versa. The specification
3500 // doesn't specify what will occur if a program engages in such mixed-mode locking, however.
3501
3502 enc_class Fast_Unlock( nabxRegP obj, eAXRegP box, eRegP tmp) %{
3503
3504 Register objReg = as_Register($obj$$reg);
3505 Register boxReg = as_Register($box$$reg);
3506 Register tmpReg = as_Register($tmp$$reg);
3507
3508 guarantee (objReg != boxReg, "") ;
3509 guarantee (objReg != tmpReg, "") ;
3510 guarantee (boxReg != tmpReg, "") ;
3511 guarantee (boxReg == as_Register(EAX_enc), "") ;
3512 MacroAssembler masm(&cbuf);
3513
3514 if (EmitSync & 4) {
3515 // Disable - inhibit all inlining. Force control through the slow-path
3516 masm.cmpptr (rsp, 0) ;
3517 } else
3518 if (EmitSync & 8) {
3519 Label DONE_LABEL ;
3520 if (UseBiasedLocking) {
3521 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL);
3522 }
3523 // classic stack-locking code ...
3524 masm.movptr(tmpReg, Address(boxReg, 0)) ;
3525 masm.testptr(tmpReg, tmpReg) ;
3526 masm.jcc (Assembler::zero, DONE_LABEL) ;
3527 if (os::is_MP()) { masm.lock(); }
3528 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses EAX which is box
3529 masm.bind(DONE_LABEL);
3530 } else {
3531 Label DONE_LABEL, Stacked, CheckSucc, Inflated ;
3532
3533 // Critically, the biased locking test must have precedence over
3534 // and appear before the (box->dhw == 0) recursive stack-lock test.
3535 if (UseBiasedLocking && !UseOptoBiasInlining) {
3536 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL);
3537 }
3538
3539 masm.cmpptr(Address(boxReg, 0), 0) ; // Examine the displaced header
3540 masm.movptr(tmpReg, Address(objReg, 0)) ; // Examine the object's markword
3541 masm.jccb (Assembler::zero, DONE_LABEL) ; // 0 indicates recursive stack-lock
3542
3543 masm.testptr(tmpReg, 0x02) ; // Inflated?
3544 masm.jccb (Assembler::zero, Stacked) ;
3545
3546 masm.bind (Inflated) ;
3547 // It's inflated.
3548 // Despite our balanced locking property we still check that m->_owner == Self
3549 // as java routines or native JNI code called by this thread might
3550 // have released the lock.
3551 // Refer to the comments in synchronizer.cpp for how we might encode extra
3552 // state in _succ so we can avoid fetching EntryList|cxq.
3553 //
3554 // I'd like to add more cases in fast_lock() and fast_unlock() --
3555 // such as recursive enter and exit -- but we have to be wary of
3556 // I$ bloat, T$ effects and BP$ effects.
3557 //
3558 // If there's no contention try a 1-0 exit. That is, exit without
3559 // a costly MEMBAR or CAS. See synchronizer.cpp for details on how
3560 // we detect and recover from the race that the 1-0 exit admits.
3561 //
3562 // Conceptually Fast_Unlock() must execute a STST|LDST "release" barrier
3563 // before it STs null into _owner, releasing the lock. Updates
3564 // to data protected by the critical section must be visible before
3565 // we drop the lock (and thus before any other thread could acquire
3566 // the lock and observe the fields protected by the lock).
3567 // IA32's memory-model is SPO, so STs are ordered with respect to
3568 // each other and there's no need for an explicit barrier (fence).
3569 // See also http://gee.cs.oswego.edu/dl/jmm/cookbook.html.
3570
3571 masm.get_thread (boxReg) ;
3572 if ((EmitSync & 4096) && VM_Version::supports_3dnow() && os::is_MP()) {
3573 // prefetchw [ebx + Offset(_owner)-2]
3574 masm.prefetchw(Address(rbx, ObjectMonitor::owner_offset_in_bytes()-2));
3575 }
3576
3577 // Note that we could employ various encoding schemes to reduce
3578 // the number of loads below (currently 4) to just 2 or 3.
3579 // Refer to the comments in synchronizer.cpp.
3580 // In practice the chain of fetches doesn't seem to impact performance, however.
3581 if ((EmitSync & 65536) == 0 && (EmitSync & 256)) {
3582 // Attempt to reduce branch density - AMD's branch predictor.
3583 masm.xorptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3584 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ;
3585 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ;
3586 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ;
3587 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3588 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ;
3589 masm.jmpb (DONE_LABEL) ;
3590 } else {
3591 masm.xorptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3592 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ;
3593 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3594 masm.movptr(boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ;
3595 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ;
3596 masm.jccb (Assembler::notZero, CheckSucc) ;
3597 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ;
3598 masm.jmpb (DONE_LABEL) ;
3599 }
3600
3601 // The Following code fragment (EmitSync & 65536) improves the performance of
3602 // contended applications and contended synchronization microbenchmarks.
3603 // Unfortunately the emission of the code - even though not executed - causes regressions
3604 // in scimark and jetstream, evidently because of $ effects. Replacing the code
3605 // with an equal number of never-executed NOPs results in the same regression.
3606 // We leave it off by default.
3607
3608 if ((EmitSync & 65536) != 0) {
3609 Label LSuccess, LGoSlowPath ;
3610
3611 masm.bind (CheckSucc) ;
3612
3613 // Optional pre-test ... it's safe to elide this
3614 if ((EmitSync & 16) == 0) {
3615 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), 0) ;
3616 masm.jccb (Assembler::zero, LGoSlowPath) ;
3617 }
3618
3619 // We have a classic Dekker-style idiom:
3620 // ST m->_owner = 0 ; MEMBAR; LD m->_succ
3621 // There are a number of ways to implement the barrier:
3622 // (1) lock:andl &m->_owner, 0
3623 // is fast, but mask doesn't currently support the "ANDL M,IMM32" form.
3624 // LOCK: ANDL [ebx+Offset(_Owner)-2], 0
3625 // Encodes as 81 31 OFF32 IMM32 or 83 63 OFF8 IMM8
3626 // (2) If supported, an explicit MFENCE is appealing.
3627 // In older IA32 processors MFENCE is slower than lock:add or xchg
3628 // particularly if the write-buffer is full as might be the case if
3629 // if stores closely precede the fence or fence-equivalent instruction.
3630 // In more modern implementations MFENCE appears faster, however.
3631 // (3) In lieu of an explicit fence, use lock:addl to the top-of-stack
3632 // The $lines underlying the top-of-stack should be in M-state.
3633 // The locked add instruction is serializing, of course.
3634 // (4) Use xchg, which is serializing
3635 // mov boxReg, 0; xchgl boxReg, [tmpReg + Offset(_owner)-2] also works
3636 // (5) ST m->_owner = 0 and then execute lock:orl &m->_succ, 0.
3637 // The integer condition codes will tell us if succ was 0.
3638 // Since _succ and _owner should reside in the same $line and
3639 // we just stored into _owner, it's likely that the $line
3640 // remains in M-state for the lock:orl.
3641 //
3642 // We currently use (3), although it's likely that switching to (2)
3643 // is correct for the future.
3644
3645 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ;
3646 if (os::is_MP()) {
3647 if (VM_Version::supports_sse2() && 1 == FenceInstruction) {
3648 masm.mfence();
3649 } else {
3650 masm.lock () ; masm.addptr(Address(rsp, 0), 0) ;
3651 }
3652 }
3653 // Ratify _succ remains non-null
3654 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), 0) ;
3655 masm.jccb (Assembler::notZero, LSuccess) ;
3656
3657 masm.xorptr(boxReg, boxReg) ; // box is really EAX
3658 if (os::is_MP()) { masm.lock(); }
3659 masm.cmpxchgptr(rsp, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2));
3660 masm.jccb (Assembler::notEqual, LSuccess) ;
3661 // Since we're low on registers we installed rsp as a placeholding in _owner.
3662 // Now install Self over rsp. This is safe as we're transitioning from
3663 // non-null to non=null
3664 masm.get_thread (boxReg) ;
3665 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), boxReg) ;
3666 // Intentional fall-through into LGoSlowPath ...
3667
3668 masm.bind (LGoSlowPath) ;
3669 masm.orptr(boxReg, 1) ; // set ICC.ZF=0 to indicate failure
3670 masm.jmpb (DONE_LABEL) ;
3671
3672 masm.bind (LSuccess) ;
3673 masm.xorptr(boxReg, boxReg) ; // set ICC.ZF=1 to indicate success
3674 masm.jmpb (DONE_LABEL) ;
3675 }
3676
3677 masm.bind (Stacked) ;
3678 // It's not inflated and it's not recursively stack-locked and it's not biased.
3679 // It must be stack-locked.
3680 // Try to reset the header to displaced header.
3681 // The "box" value on the stack is stable, so we can reload
3682 // and be assured we observe the same value as above.
3683 masm.movptr(tmpReg, Address(boxReg, 0)) ;
3684 if (os::is_MP()) { masm.lock(); }
3685 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses EAX which is box
3686 // Intention fall-thru into DONE_LABEL
3687
3688
3689 // DONE_LABEL is a hot target - we'd really like to place it at the
3690 // start of cache line by padding with NOPs.
3691 // See the AMD and Intel software optimization manuals for the
3692 // most efficient "long" NOP encodings.
3693 // Unfortunately none of our alignment mechanisms suffice.
3694 if ((EmitSync & 65536) == 0) {
3695 masm.bind (CheckSucc) ;
3696 }
3697 masm.bind(DONE_LABEL);
3698
3699 // Avoid branch to branch on AMD processors
3700 if (EmitSync & 32768) { masm.nop() ; }
3701 }
3702 %}
3703
3704
3705 enc_class enc_pop_rdx() %{
3706 emit_opcode(cbuf,0x5A);
3707 %}
3708
3709 enc_class enc_rethrow() %{
3710 cbuf.set_inst_mark();
3711 emit_opcode(cbuf, 0xE9); // jmp entry
3712 emit_d32_reloc(cbuf, (int)OptoRuntime::rethrow_stub() - ((int)cbuf.code_end())-4,
3713 runtime_call_Relocation::spec(), RELOC_IMM32 );
3714 %}
3715
3716
3717 // Convert a double to an int. Java semantics require we do complex
3718 // manglelations in the corner cases. So we set the rounding mode to
3719 // 'zero', store the darned double down as an int, and reset the
3720 // rounding mode to 'nearest'. The hardware throws an exception which
3721 // patches up the correct value directly to the stack.
3722 enc_class D2I_encoding( regD src ) %{
3723 // Flip to round-to-zero mode. We attempted to allow invalid-op
3724 // exceptions here, so that a NAN or other corner-case value will
3725 // thrown an exception (but normal values get converted at full speed).
3726 // However, I2C adapters and other float-stack manglers leave pending
3727 // invalid-op exceptions hanging. We would have to clear them before
3728 // enabling them and that is more expensive than just testing for the
3729 // invalid value Intel stores down in the corner cases.
3730 emit_opcode(cbuf,0xD9); // FLDCW trunc
3731 emit_opcode(cbuf,0x2D);
3732 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
3733 // Allocate a word
3734 emit_opcode(cbuf,0x83); // SUB ESP,4
3735 emit_opcode(cbuf,0xEC);
3736 emit_d8(cbuf,0x04);
3737 // Encoding assumes a double has been pushed into FPR0.
3738 // Store down the double as an int, popping the FPU stack
3739 emit_opcode(cbuf,0xDB); // FISTP [ESP]
3740 emit_opcode(cbuf,0x1C);
3741 emit_d8(cbuf,0x24);
3742 // Restore the rounding mode; mask the exception
3743 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode
3744 emit_opcode(cbuf,0x2D);
3745 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
3746 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
3747 : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
3748
3749 // Load the converted int; adjust CPU stack
3750 emit_opcode(cbuf,0x58); // POP EAX
3751 emit_opcode(cbuf,0x3D); // CMP EAX,imm
3752 emit_d32 (cbuf,0x80000000); // 0x80000000
3753 emit_opcode(cbuf,0x75); // JNE around_slow_call
3754 emit_d8 (cbuf,0x07); // Size of slow_call
3755 // Push src onto stack slow-path
3756 emit_opcode(cbuf,0xD9 ); // FLD ST(i)
3757 emit_d8 (cbuf,0xC0-1+$src$$reg );
3758 // CALL directly to the runtime
3759 cbuf.set_inst_mark();
3760 emit_opcode(cbuf,0xE8); // Call into runtime
3761 emit_d32_reloc(cbuf, (StubRoutines::d2i_wrapper() - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
3762 // Carry on here...
3763 %}
3764
3765 enc_class D2L_encoding( regD src ) %{
3766 emit_opcode(cbuf,0xD9); // FLDCW trunc
3767 emit_opcode(cbuf,0x2D);
3768 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
3769 // Allocate a word
3770 emit_opcode(cbuf,0x83); // SUB ESP,8
3771 emit_opcode(cbuf,0xEC);
3772 emit_d8(cbuf,0x08);
3773 // Encoding assumes a double has been pushed into FPR0.
3774 // Store down the double as a long, popping the FPU stack
3775 emit_opcode(cbuf,0xDF); // FISTP [ESP]
3776 emit_opcode(cbuf,0x3C);
3777 emit_d8(cbuf,0x24);
3778 // Restore the rounding mode; mask the exception
3779 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode
3780 emit_opcode(cbuf,0x2D);
3781 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
3782 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
3783 : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
3784
3785 // Load the converted int; adjust CPU stack
3786 emit_opcode(cbuf,0x58); // POP EAX
3787 emit_opcode(cbuf,0x5A); // POP EDX
3788 emit_opcode(cbuf,0x81); // CMP EDX,imm
3789 emit_d8 (cbuf,0xFA); // rdx
3790 emit_d32 (cbuf,0x80000000); // 0x80000000
3791 emit_opcode(cbuf,0x75); // JNE around_slow_call
3792 emit_d8 (cbuf,0x07+4); // Size of slow_call
3793 emit_opcode(cbuf,0x85); // TEST EAX,EAX
3794 emit_opcode(cbuf,0xC0); // 2/rax,/rax,
3795 emit_opcode(cbuf,0x75); // JNE around_slow_call
3796 emit_d8 (cbuf,0x07); // Size of slow_call
3797 // Push src onto stack slow-path
3798 emit_opcode(cbuf,0xD9 ); // FLD ST(i)
3799 emit_d8 (cbuf,0xC0-1+$src$$reg );
3800 // CALL directly to the runtime
3801 cbuf.set_inst_mark();
3802 emit_opcode(cbuf,0xE8); // Call into runtime
3803 emit_d32_reloc(cbuf, (StubRoutines::d2l_wrapper() - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
3804 // Carry on here...
3805 %}
3806
3807 enc_class X2L_encoding( regX src ) %{
3808 // Allocate a word
3809 emit_opcode(cbuf,0x83); // SUB ESP,8
3810 emit_opcode(cbuf,0xEC);
3811 emit_d8(cbuf,0x08);
3812
3813 emit_opcode (cbuf, 0xF3 ); // MOVSS [ESP], src
3814 emit_opcode (cbuf, 0x0F );
3815 emit_opcode (cbuf, 0x11 );
3816 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false);
3817
3818 emit_opcode(cbuf,0xD9 ); // FLD_S [ESP]
3819 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
3820
3821 emit_opcode(cbuf,0xD9); // FLDCW trunc
3822 emit_opcode(cbuf,0x2D);
3823 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
3824
3825 // Encoding assumes a double has been pushed into FPR0.
3826 // Store down the double as a long, popping the FPU stack
3827 emit_opcode(cbuf,0xDF); // FISTP [ESP]
3828 emit_opcode(cbuf,0x3C);
3829 emit_d8(cbuf,0x24);
3830
3831 // Restore the rounding mode; mask the exception
3832 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode
3833 emit_opcode(cbuf,0x2D);
3834 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
3835 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
3836 : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
3837
3838 // Load the converted int; adjust CPU stack
3839 emit_opcode(cbuf,0x58); // POP EAX
3840
3841 emit_opcode(cbuf,0x5A); // POP EDX
3842
3843 emit_opcode(cbuf,0x81); // CMP EDX,imm
3844 emit_d8 (cbuf,0xFA); // rdx
3845 emit_d32 (cbuf,0x80000000);// 0x80000000
3846
3847 emit_opcode(cbuf,0x75); // JNE around_slow_call
3848 emit_d8 (cbuf,0x13+4); // Size of slow_call
3849
3850 emit_opcode(cbuf,0x85); // TEST EAX,EAX
3851 emit_opcode(cbuf,0xC0); // 2/rax,/rax,
3852
3853 emit_opcode(cbuf,0x75); // JNE around_slow_call
3854 emit_d8 (cbuf,0x13); // Size of slow_call
3855
3856 // Allocate a word
3857 emit_opcode(cbuf,0x83); // SUB ESP,4
3858 emit_opcode(cbuf,0xEC);
3859 emit_d8(cbuf,0x04);
3860
3861 emit_opcode (cbuf, 0xF3 ); // MOVSS [ESP], src
3862 emit_opcode (cbuf, 0x0F );
3863 emit_opcode (cbuf, 0x11 );
3864 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false);
3865
3866 emit_opcode(cbuf,0xD9 ); // FLD_S [ESP]
3867 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
3868
3869 emit_opcode(cbuf,0x83); // ADD ESP,4
3870 emit_opcode(cbuf,0xC4);
3871 emit_d8(cbuf,0x04);
3872
3873 // CALL directly to the runtime
3874 cbuf.set_inst_mark();
3875 emit_opcode(cbuf,0xE8); // Call into runtime
3876 emit_d32_reloc(cbuf, (StubRoutines::d2l_wrapper() - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
3877 // Carry on here...
3878 %}
3879
3880 enc_class XD2L_encoding( regXD src ) %{
3881 // Allocate a word
3882 emit_opcode(cbuf,0x83); // SUB ESP,8
3883 emit_opcode(cbuf,0xEC);
3884 emit_d8(cbuf,0x08);
3885
3886 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], src
3887 emit_opcode (cbuf, 0x0F );
3888 emit_opcode (cbuf, 0x11 );
3889 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false);
3890
3891 emit_opcode(cbuf,0xDD ); // FLD_D [ESP]
3892 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
3893
3894 emit_opcode(cbuf,0xD9); // FLDCW trunc
3895 emit_opcode(cbuf,0x2D);
3896 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
3897
3898 // Encoding assumes a double has been pushed into FPR0.
3899 // Store down the double as a long, popping the FPU stack
3900 emit_opcode(cbuf,0xDF); // FISTP [ESP]
3901 emit_opcode(cbuf,0x3C);
3902 emit_d8(cbuf,0x24);
3903
3904 // Restore the rounding mode; mask the exception
3905 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode
3906 emit_opcode(cbuf,0x2D);
3907 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
3908 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
3909 : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
3910
3911 // Load the converted int; adjust CPU stack
3912 emit_opcode(cbuf,0x58); // POP EAX
3913
3914 emit_opcode(cbuf,0x5A); // POP EDX
3915
3916 emit_opcode(cbuf,0x81); // CMP EDX,imm
3917 emit_d8 (cbuf,0xFA); // rdx
3918 emit_d32 (cbuf,0x80000000); // 0x80000000
3919
3920 emit_opcode(cbuf,0x75); // JNE around_slow_call
3921 emit_d8 (cbuf,0x13+4); // Size of slow_call
3922
3923 emit_opcode(cbuf,0x85); // TEST EAX,EAX
3924 emit_opcode(cbuf,0xC0); // 2/rax,/rax,
3925
3926 emit_opcode(cbuf,0x75); // JNE around_slow_call
3927 emit_d8 (cbuf,0x13); // Size of slow_call
3928
3929 // Push src onto stack slow-path
3930 // Allocate a word
3931 emit_opcode(cbuf,0x83); // SUB ESP,8
3932 emit_opcode(cbuf,0xEC);
3933 emit_d8(cbuf,0x08);
3934
3935 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], src
3936 emit_opcode (cbuf, 0x0F );
3937 emit_opcode (cbuf, 0x11 );
3938 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false);
3939
3940 emit_opcode(cbuf,0xDD ); // FLD_D [ESP]
3941 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
3942
3943 emit_opcode(cbuf,0x83); // ADD ESP,8
3944 emit_opcode(cbuf,0xC4);
3945 emit_d8(cbuf,0x08);
3946
3947 // CALL directly to the runtime
3948 cbuf.set_inst_mark();
3949 emit_opcode(cbuf,0xE8); // Call into runtime
3950 emit_d32_reloc(cbuf, (StubRoutines::d2l_wrapper() - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
3951 // Carry on here...
3952 %}
3953
3954 enc_class D2X_encoding( regX dst, regD src ) %{
3955 // Allocate a word
3956 emit_opcode(cbuf,0x83); // SUB ESP,4
3957 emit_opcode(cbuf,0xEC);
3958 emit_d8(cbuf,0x04);
3959 int pop = 0x02;
3960 if ($src$$reg != FPR1L_enc) {
3961 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
3962 emit_d8( cbuf, 0xC0-1+$src$$reg );
3963 pop = 0x03;
3964 }
3965 store_to_stackslot( cbuf, 0xD9, pop, 0 ); // FST<P>_S [ESP]
3966
3967 emit_opcode (cbuf, 0xF3 ); // MOVSS dst(xmm), [ESP]
3968 emit_opcode (cbuf, 0x0F );
3969 emit_opcode (cbuf, 0x10 );
3970 encode_RegMem(cbuf, $dst$$reg, ESP_enc, 0x4, 0, 0, false);
3971
3972 emit_opcode(cbuf,0x83); // ADD ESP,4
3973 emit_opcode(cbuf,0xC4);
3974 emit_d8(cbuf,0x04);
3975 // Carry on here...
3976 %}
3977
3978 enc_class FX2I_encoding( regX src, eRegI dst ) %{
3979 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
3980
3981 // Compare the result to see if we need to go to the slow path
3982 emit_opcode(cbuf,0x81); // CMP dst,imm
3983 emit_rm (cbuf,0x3,0x7,$dst$$reg);
3984 emit_d32 (cbuf,0x80000000); // 0x80000000
3985
3986 emit_opcode(cbuf,0x75); // JNE around_slow_call
3987 emit_d8 (cbuf,0x13); // Size of slow_call
3988 // Store xmm to a temp memory
3989 // location and push it onto stack.
3990
3991 emit_opcode(cbuf,0x83); // SUB ESP,4
3992 emit_opcode(cbuf,0xEC);
3993 emit_d8(cbuf, $primary ? 0x8 : 0x4);
3994
3995 emit_opcode (cbuf, $primary ? 0xF2 : 0xF3 ); // MOVSS [ESP], xmm
3996 emit_opcode (cbuf, 0x0F );
3997 emit_opcode (cbuf, 0x11 );
3998 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false);
3999
4000 emit_opcode(cbuf, $primary ? 0xDD : 0xD9 ); // FLD [ESP]
4001 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
4002
4003 emit_opcode(cbuf,0x83); // ADD ESP,4
4004 emit_opcode(cbuf,0xC4);
4005 emit_d8(cbuf, $primary ? 0x8 : 0x4);
4006
4007 // CALL directly to the runtime
4008 cbuf.set_inst_mark();
4009 emit_opcode(cbuf,0xE8); // Call into runtime
4010 emit_d32_reloc(cbuf, (StubRoutines::d2i_wrapper() - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
4011
4012 // Carry on here...
4013 %}
4014
4015 enc_class X2D_encoding( regD dst, regX src ) %{
4016 // Allocate a word
4017 emit_opcode(cbuf,0x83); // SUB ESP,4
4018 emit_opcode(cbuf,0xEC);
4019 emit_d8(cbuf,0x04);
4020
4021 emit_opcode (cbuf, 0xF3 ); // MOVSS [ESP], xmm
4022 emit_opcode (cbuf, 0x0F );
4023 emit_opcode (cbuf, 0x11 );
4024 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false);
4025
4026 emit_opcode(cbuf,0xD9 ); // FLD_S [ESP]
4027 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
4028
4029 emit_opcode(cbuf,0x83); // ADD ESP,4
4030 emit_opcode(cbuf,0xC4);
4031 emit_d8(cbuf,0x04);
4032
4033 // Carry on here...
4034 %}
4035
4036 enc_class AbsXF_encoding(regX dst) %{
4037 address signmask_address=(address)float_signmask_pool;
4038 // andpd:\tANDPS $dst,[signconst]
4039 emit_opcode(cbuf, 0x0F);
4040 emit_opcode(cbuf, 0x54);
4041 emit_rm(cbuf, 0x0, $dst$$reg, 0x5);
4042 emit_d32(cbuf, (int)signmask_address);
4043 %}
4044
4045 enc_class AbsXD_encoding(regXD dst) %{
4046 address signmask_address=(address)double_signmask_pool;
4047 // andpd:\tANDPD $dst,[signconst]
4048 emit_opcode(cbuf, 0x66);
4049 emit_opcode(cbuf, 0x0F);
4050 emit_opcode(cbuf, 0x54);
4051 emit_rm(cbuf, 0x0, $dst$$reg, 0x5);
4052 emit_d32(cbuf, (int)signmask_address);
4053 %}
4054
4055 enc_class NegXF_encoding(regX dst) %{
4056 address signmask_address=(address)float_signflip_pool;
4057 // andpd:\tXORPS $dst,[signconst]
4058 emit_opcode(cbuf, 0x0F);
4059 emit_opcode(cbuf, 0x57);
4060 emit_rm(cbuf, 0x0, $dst$$reg, 0x5);
4061 emit_d32(cbuf, (int)signmask_address);
4062 %}
4063
4064 enc_class NegXD_encoding(regXD dst) %{
4065 address signmask_address=(address)double_signflip_pool;
4066 // andpd:\tXORPD $dst,[signconst]
4067 emit_opcode(cbuf, 0x66);
4068 emit_opcode(cbuf, 0x0F);
4069 emit_opcode(cbuf, 0x57);
4070 emit_rm(cbuf, 0x0, $dst$$reg, 0x5);
4071 emit_d32(cbuf, (int)signmask_address);
4072 %}
4073
4074 enc_class FMul_ST_reg( eRegF src1 ) %{
4075 // Operand was loaded from memory into fp ST (stack top)
4076 // FMUL ST,$src /* D8 C8+i */
4077 emit_opcode(cbuf, 0xD8);
4078 emit_opcode(cbuf, 0xC8 + $src1$$reg);
4079 %}
4080
4081 enc_class FAdd_ST_reg( eRegF src2 ) %{
4082 // FADDP ST,src2 /* D8 C0+i */
4083 emit_opcode(cbuf, 0xD8);
4084 emit_opcode(cbuf, 0xC0 + $src2$$reg);
4085 //could use FADDP src2,fpST /* DE C0+i */
4086 %}
4087
4088 enc_class FAddP_reg_ST( eRegF src2 ) %{
4089 // FADDP src2,ST /* DE C0+i */
4090 emit_opcode(cbuf, 0xDE);
4091 emit_opcode(cbuf, 0xC0 + $src2$$reg);
4092 %}
4093
4094 enc_class subF_divF_encode( eRegF src1, eRegF src2) %{
4095 // Operand has been loaded into fp ST (stack top)
4096 // FSUB ST,$src1
4097 emit_opcode(cbuf, 0xD8);
4098 emit_opcode(cbuf, 0xE0 + $src1$$reg);
4099
4100 // FDIV
4101 emit_opcode(cbuf, 0xD8);
4102 emit_opcode(cbuf, 0xF0 + $src2$$reg);
4103 %}
4104
4105 enc_class MulFAddF (eRegF src1, eRegF src2) %{
4106 // Operand was loaded from memory into fp ST (stack top)
4107 // FADD ST,$src /* D8 C0+i */
4108 emit_opcode(cbuf, 0xD8);
4109 emit_opcode(cbuf, 0xC0 + $src1$$reg);
4110
4111 // FMUL ST,src2 /* D8 C*+i */
4112 emit_opcode(cbuf, 0xD8);
4113 emit_opcode(cbuf, 0xC8 + $src2$$reg);
4114 %}
4115
4116
4117 enc_class MulFAddFreverse (eRegF src1, eRegF src2) %{
4118 // Operand was loaded from memory into fp ST (stack top)
4119 // FADD ST,$src /* D8 C0+i */
4120 emit_opcode(cbuf, 0xD8);
4121 emit_opcode(cbuf, 0xC0 + $src1$$reg);
4122
4123 // FMULP src2,ST /* DE C8+i */
4124 emit_opcode(cbuf, 0xDE);
4125 emit_opcode(cbuf, 0xC8 + $src2$$reg);
4126 %}
4127
4128 // Atomically load the volatile long
4129 enc_class enc_loadL_volatile( memory mem, stackSlotL dst ) %{
4130 emit_opcode(cbuf,0xDF);
4131 int rm_byte_opcode = 0x05;
4132 int base = $mem$$base;
4133 int index = $mem$$index;
4134 int scale = $mem$$scale;
4135 int displace = $mem$$disp;
4136 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
4137 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_is_oop);
4138 store_to_stackslot( cbuf, 0x0DF, 0x07, $dst$$disp );
4139 %}
4140
4141 enc_class enc_loadLX_volatile( memory mem, stackSlotL dst, regXD tmp ) %{
4142 { // Atomic long load
4143 // UseXmmLoadAndClearUpper ? movsd $tmp,$mem : movlpd $tmp,$mem
4144 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0xF2 : 0x66);
4145 emit_opcode(cbuf,0x0F);
4146 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0x10 : 0x12);
4147 int base = $mem$$base;
4148 int index = $mem$$index;
4149 int scale = $mem$$scale;
4150 int displace = $mem$$disp;
4151 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
4152 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop);
4153 }
4154 { // MOVSD $dst,$tmp ! atomic long store
4155 emit_opcode(cbuf,0xF2);
4156 emit_opcode(cbuf,0x0F);
4157 emit_opcode(cbuf,0x11);
4158 int base = $dst$$base;
4159 int index = $dst$$index;
4160 int scale = $dst$$scale;
4161 int displace = $dst$$disp;
4162 bool disp_is_oop = $dst->disp_is_oop(); // disp-as-oop when working with static globals
4163 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop);
4164 }
4165 %}
4166
4167 enc_class enc_loadLX_reg_volatile( memory mem, eRegL dst, regXD tmp ) %{
4168 { // Atomic long load
4169 // UseXmmLoadAndClearUpper ? movsd $tmp,$mem : movlpd $tmp,$mem
4170 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0xF2 : 0x66);
4171 emit_opcode(cbuf,0x0F);
4172 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0x10 : 0x12);
4173 int base = $mem$$base;
4174 int index = $mem$$index;
4175 int scale = $mem$$scale;
4176 int displace = $mem$$disp;
4177 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
4178 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop);
4179 }
4180 { // MOVD $dst.lo,$tmp
4181 emit_opcode(cbuf,0x66);
4182 emit_opcode(cbuf,0x0F);
4183 emit_opcode(cbuf,0x7E);
4184 emit_rm(cbuf, 0x3, $tmp$$reg, $dst$$reg);
4185 }
4186 { // PSRLQ $tmp,32
4187 emit_opcode(cbuf,0x66);
4188 emit_opcode(cbuf,0x0F);
4189 emit_opcode(cbuf,0x73);
4190 emit_rm(cbuf, 0x3, 0x02, $tmp$$reg);
4191 emit_d8(cbuf, 0x20);
4192 }
4193 { // MOVD $dst.hi,$tmp
4194 emit_opcode(cbuf,0x66);
4195 emit_opcode(cbuf,0x0F);
4196 emit_opcode(cbuf,0x7E);
4197 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg));
4198 }
4199 %}
4200
4201 // Volatile Store Long. Must be atomic, so move it into
4202 // the FP TOS and then do a 64-bit FIST. Has to probe the
4203 // target address before the store (for null-ptr checks)
4204 // so the memory operand is used twice in the encoding.
4205 enc_class enc_storeL_volatile( memory mem, stackSlotL src ) %{
4206 store_to_stackslot( cbuf, 0x0DF, 0x05, $src$$disp );
4207 cbuf.set_inst_mark(); // Mark start of FIST in case $mem has an oop
4208 emit_opcode(cbuf,0xDF);
4209 int rm_byte_opcode = 0x07;
4210 int base = $mem$$base;
4211 int index = $mem$$index;
4212 int scale = $mem$$scale;
4213 int displace = $mem$$disp;
4214 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
4215 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_is_oop);
4216 %}
4217
4218 enc_class enc_storeLX_volatile( memory mem, stackSlotL src, regXD tmp) %{
4219 { // Atomic long load
4220 // UseXmmLoadAndClearUpper ? movsd $tmp,[$src] : movlpd $tmp,[$src]
4221 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0xF2 : 0x66);
4222 emit_opcode(cbuf,0x0F);
4223 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0x10 : 0x12);
4224 int base = $src$$base;
4225 int index = $src$$index;
4226 int scale = $src$$scale;
4227 int displace = $src$$disp;
4228 bool disp_is_oop = $src->disp_is_oop(); // disp-as-oop when working with static globals
4229 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop);
4230 }
4231 cbuf.set_inst_mark(); // Mark start of MOVSD in case $mem has an oop
4232 { // MOVSD $mem,$tmp ! atomic long store
4233 emit_opcode(cbuf,0xF2);
4234 emit_opcode(cbuf,0x0F);
4235 emit_opcode(cbuf,0x11);
4236 int base = $mem$$base;
4237 int index = $mem$$index;
4238 int scale = $mem$$scale;
4239 int displace = $mem$$disp;
4240 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
4241 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop);
4242 }
4243 %}
4244
4245 enc_class enc_storeLX_reg_volatile( memory mem, eRegL src, regXD tmp, regXD tmp2) %{
4246 { // MOVD $tmp,$src.lo
4247 emit_opcode(cbuf,0x66);
4248 emit_opcode(cbuf,0x0F);
4249 emit_opcode(cbuf,0x6E);
4250 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg);
4251 }
4252 { // MOVD $tmp2,$src.hi
4253 emit_opcode(cbuf,0x66);
4254 emit_opcode(cbuf,0x0F);
4255 emit_opcode(cbuf,0x6E);
4256 emit_rm(cbuf, 0x3, $tmp2$$reg, HIGH_FROM_LOW($src$$reg));
4257 }
4258 { // PUNPCKLDQ $tmp,$tmp2
4259 emit_opcode(cbuf,0x66);
4260 emit_opcode(cbuf,0x0F);
4261 emit_opcode(cbuf,0x62);
4262 emit_rm(cbuf, 0x3, $tmp$$reg, $tmp2$$reg);
4263 }
4264 cbuf.set_inst_mark(); // Mark start of MOVSD in case $mem has an oop
4265 { // MOVSD $mem,$tmp ! atomic long store
4266 emit_opcode(cbuf,0xF2);
4267 emit_opcode(cbuf,0x0F);
4268 emit_opcode(cbuf,0x11);
4269 int base = $mem$$base;
4270 int index = $mem$$index;
4271 int scale = $mem$$scale;
4272 int displace = $mem$$disp;
4273 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
4274 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop);
4275 }
4276 %}
4277
4278 // Safepoint Poll. This polls the safepoint page, and causes an
4279 // exception if it is not readable. Unfortunately, it kills the condition code
4280 // in the process
4281 // We current use TESTL [spp],EDI
4282 // A better choice might be TESTB [spp + pagesize() - CacheLineSize()],0
4283
4284 enc_class Safepoint_Poll() %{
4285 cbuf.relocate(cbuf.inst_mark(), relocInfo::poll_type, 0);
4286 emit_opcode(cbuf,0x85);
4287 emit_rm (cbuf, 0x0, 0x7, 0x5);
4288 emit_d32(cbuf, (intptr_t)os::get_polling_page());
4289 %}
4290 %}
4291
4292
4293 //----------FRAME--------------------------------------------------------------
4294 // Definition of frame structure and management information.
4295 //
4296 // S T A C K L A Y O U T Allocators stack-slot number
4297 // | (to get allocators register number
4298 // G Owned by | | v add OptoReg::stack0())
4299 // r CALLER | |
4300 // o | +--------+ pad to even-align allocators stack-slot
4301 // w V | pad0 | numbers; owned by CALLER
4302 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
4303 // h ^ | in | 5
4304 // | | args | 4 Holes in incoming args owned by SELF
4305 // | | | | 3
4306 // | | +--------+
4307 // V | | old out| Empty on Intel, window on Sparc
4308 // | old |preserve| Must be even aligned.
4309 // | SP-+--------+----> Matcher::_old_SP, even aligned
4310 // | | in | 3 area for Intel ret address
4311 // Owned by |preserve| Empty on Sparc.
4312 // SELF +--------+
4313 // | | pad2 | 2 pad to align old SP
4314 // | +--------+ 1
4315 // | | locks | 0
4316 // | +--------+----> OptoReg::stack0(), even aligned
4317 // | | pad1 | 11 pad to align new SP
4318 // | +--------+
4319 // | | | 10
4320 // | | spills | 9 spills
4321 // V | | 8 (pad0 slot for callee)
4322 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
4323 // ^ | out | 7
4324 // | | args | 6 Holes in outgoing args owned by CALLEE
4325 // Owned by +--------+
4326 // CALLEE | new out| 6 Empty on Intel, window on Sparc
4327 // | new |preserve| Must be even-aligned.
4328 // | SP-+--------+----> Matcher::_new_SP, even aligned
4329 // | | |
4330 //
4331 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
4332 // known from SELF's arguments and the Java calling convention.
4333 // Region 6-7 is determined per call site.
4334 // Note 2: If the calling convention leaves holes in the incoming argument
4335 // area, those holes are owned by SELF. Holes in the outgoing area
4336 // are owned by the CALLEE. Holes should not be nessecary in the
4337 // incoming area, as the Java calling convention is completely under
4338 // the control of the AD file. Doubles can be sorted and packed to
4339 // avoid holes. Holes in the outgoing arguments may be nessecary for
4340 // varargs C calling conventions.
4341 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
4342 // even aligned with pad0 as needed.
4343 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
4344 // region 6-11 is even aligned; it may be padded out more so that
4345 // the region from SP to FP meets the minimum stack alignment.
4346
4347 frame %{
4348 // What direction does stack grow in (assumed to be same for C & Java)
4349 stack_direction(TOWARDS_LOW);
4350
4351 // These three registers define part of the calling convention
4352 // between compiled code and the interpreter.
4353 inline_cache_reg(EAX); // Inline Cache Register
4354 interpreter_method_oop_reg(EBX); // Method Oop Register when calling interpreter
4355
4356 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
4357 cisc_spilling_operand_name(indOffset32);
4358
4359 // Number of stack slots consumed by locking an object
4360 sync_stack_slots(1);
4361
4362 // Compiled code's Frame Pointer
4363 frame_pointer(ESP);
4364 // Interpreter stores its frame pointer in a register which is
4365 // stored to the stack by I2CAdaptors.
4366 // I2CAdaptors convert from interpreted java to compiled java.
4367 interpreter_frame_pointer(EBP);
4368
4369 // Stack alignment requirement
4370 // Alignment size in bytes (128-bit -> 16 bytes)
4371 stack_alignment(StackAlignmentInBytes);
4372
4373 // Number of stack slots between incoming argument block and the start of
4374 // a new frame. The PROLOG must add this many slots to the stack. The
4375 // EPILOG must remove this many slots. Intel needs one slot for
4376 // return address and one for rbp, (must save rbp)
4377 in_preserve_stack_slots(2+VerifyStackAtCalls);
4378
4379 // Number of outgoing stack slots killed above the out_preserve_stack_slots
4380 // for calls to C. Supports the var-args backing area for register parms.
4381 varargs_C_out_slots_killed(0);
4382
4383 // The after-PROLOG location of the return address. Location of
4384 // return address specifies a type (REG or STACK) and a number
4385 // representing the register number (i.e. - use a register name) or
4386 // stack slot.
4387 // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
4388 // Otherwise, it is above the locks and verification slot and alignment word
4389 return_addr(STACK - 1 +
4390 round_to(1+VerifyStackAtCalls+
4391 Compile::current()->fixed_slots(),
4392 (StackAlignmentInBytes/wordSize)));
4393
4394 // Body of function which returns an integer array locating
4395 // arguments either in registers or in stack slots. Passed an array
4396 // of ideal registers called "sig" and a "length" count. Stack-slot
4397 // offsets are based on outgoing arguments, i.e. a CALLER setting up
4398 // arguments for a CALLEE. Incoming stack arguments are
4399 // automatically biased by the preserve_stack_slots field above.
4400 calling_convention %{
4401 // No difference between ingoing/outgoing just pass false
4402 SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
4403 %}
4404
4405
4406 // Body of function which returns an integer array locating
4407 // arguments either in registers or in stack slots. Passed an array
4408 // of ideal registers called "sig" and a "length" count. Stack-slot
4409 // offsets are based on outgoing arguments, i.e. a CALLER setting up
4410 // arguments for a CALLEE. Incoming stack arguments are
4411 // automatically biased by the preserve_stack_slots field above.
4412 c_calling_convention %{
4413 // This is obviously always outgoing
4414 (void) SharedRuntime::c_calling_convention(sig_bt, regs, length);
4415 %}
4416
4417 // Location of C & interpreter return values
4418 c_return_value %{
4419 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
4420 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num };
4421 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num };
4422
4423 // in SSE2+ mode we want to keep the FPU stack clean so pretend
4424 // that C functions return float and double results in XMM0.
4425 if( ideal_reg == Op_RegD && UseSSE>=2 )
4426 return OptoRegPair(XMM0b_num,XMM0a_num);
4427 if( ideal_reg == Op_RegF && UseSSE>=2 )
4428 return OptoRegPair(OptoReg::Bad,XMM0a_num);
4429
4430 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]);
4431 %}
4432
4433 // Location of return values
4434 return_value %{
4435 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
4436 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num };
4437 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num };
4438 if( ideal_reg == Op_RegD && UseSSE>=2 )
4439 return OptoRegPair(XMM0b_num,XMM0a_num);
4440 if( ideal_reg == Op_RegF && UseSSE>=1 )
4441 return OptoRegPair(OptoReg::Bad,XMM0a_num);
4442 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]);
4443 %}
4444
4445 %}
4446
4447 //----------ATTRIBUTES---------------------------------------------------------
4448 //----------Operand Attributes-------------------------------------------------
4449 op_attrib op_cost(0); // Required cost attribute
4450
4451 //----------Instruction Attributes---------------------------------------------
4452 ins_attrib ins_cost(100); // Required cost attribute
4453 ins_attrib ins_size(8); // Required size attribute (in bits)
4454 ins_attrib ins_pc_relative(0); // Required PC Relative flag
4455 ins_attrib ins_short_branch(0); // Required flag: is this instruction a
4456 // non-matching short branch variant of some
4457 // long branch?
4458 ins_attrib ins_alignment(1); // Required alignment attribute (must be a power of 2)
4459 // specifies the alignment that some part of the instruction (not
4460 // necessarily the start) requires. If > 1, a compute_padding()
4461 // function must be provided for the instruction
4462
4463 //----------OPERANDS-----------------------------------------------------------
4464 // Operand definitions must precede instruction definitions for correct parsing
4465 // in the ADLC because operands constitute user defined types which are used in
4466 // instruction definitions.
4467
4468 //----------Simple Operands----------------------------------------------------
4469 // Immediate Operands
4470 // Integer Immediate
4471 operand immI() %{
4472 match(ConI);
4473
4474 op_cost(10);
4475 format %{ %}
4476 interface(CONST_INTER);
4477 %}
4478
4479 // Constant for test vs zero
4480 operand immI0() %{
4481 predicate(n->get_int() == 0);
4482 match(ConI);
4483
4484 op_cost(0);
4485 format %{ %}
4486 interface(CONST_INTER);
4487 %}
4488
4489 // Constant for increment
4490 operand immI1() %{
4491 predicate(n->get_int() == 1);
4492 match(ConI);
4493
4494 op_cost(0);
4495 format %{ %}
4496 interface(CONST_INTER);
4497 %}
4498
4499 // Constant for decrement
4500 operand immI_M1() %{
4501 predicate(n->get_int() == -1);
4502 match(ConI);
4503
4504 op_cost(0);
4505 format %{ %}
4506 interface(CONST_INTER);
4507 %}
4508
4509 // Valid scale values for addressing modes
4510 operand immI2() %{
4511 predicate(0 <= n->get_int() && (n->get_int() <= 3));
4512 match(ConI);
4513
4514 format %{ %}
4515 interface(CONST_INTER);
4516 %}
4517
4518 operand immI8() %{
4519 predicate((-128 <= n->get_int()) && (n->get_int() <= 127));
4520 match(ConI);
4521
4522 op_cost(5);
4523 format %{ %}
4524 interface(CONST_INTER);
4525 %}
4526
4527 operand immI16() %{
4528 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767));
4529 match(ConI);
4530
4531 op_cost(10);
4532 format %{ %}
4533 interface(CONST_INTER);
4534 %}
4535
4536 // Constant for long shifts
4537 operand immI_32() %{
4538 predicate( n->get_int() == 32 );
4539 match(ConI);
4540
4541 op_cost(0);
4542 format %{ %}
4543 interface(CONST_INTER);
4544 %}
4545
4546 operand immI_1_31() %{
4547 predicate( n->get_int() >= 1 && n->get_int() <= 31 );
4548 match(ConI);
4549
4550 op_cost(0);
4551 format %{ %}
4552 interface(CONST_INTER);
4553 %}
4554
4555 operand immI_32_63() %{
4556 predicate( n->get_int() >= 32 && n->get_int() <= 63 );
4557 match(ConI);
4558 op_cost(0);
4559
4560 format %{ %}
4561 interface(CONST_INTER);
4562 %}
4563
4564 operand immI_1() %{
4565 predicate( n->get_int() == 1 );
4566 match(ConI);
4567
4568 op_cost(0);
4569 format %{ %}
4570 interface(CONST_INTER);
4571 %}
4572
4573 operand immI_2() %{
4574 predicate( n->get_int() == 2 );
4575 match(ConI);
4576
4577 op_cost(0);
4578 format %{ %}
4579 interface(CONST_INTER);
4580 %}
4581
4582 operand immI_3() %{
4583 predicate( n->get_int() == 3 );
4584 match(ConI);
4585
4586 op_cost(0);
4587 format %{ %}
4588 interface(CONST_INTER);
4589 %}
4590
4591 // Pointer Immediate
4592 operand immP() %{
4593 match(ConP);
4594
4595 op_cost(10);
4596 format %{ %}
4597 interface(CONST_INTER);
4598 %}
4599
4600 // NULL Pointer Immediate
4601 operand immP0() %{
4602 predicate( n->get_ptr() == 0 );
4603 match(ConP);
4604 op_cost(0);
4605
4606 format %{ %}
4607 interface(CONST_INTER);
4608 %}
4609
4610 // Long Immediate
4611 operand immL() %{
4612 match(ConL);
4613
4614 op_cost(20);
4615 format %{ %}
4616 interface(CONST_INTER);
4617 %}
4618
4619 // Long Immediate zero
4620 operand immL0() %{
4621 predicate( n->get_long() == 0L );
4622 match(ConL);
4623 op_cost(0);
4624
4625 format %{ %}
4626 interface(CONST_INTER);
4627 %}
4628
4629 // Long Immediate zero
4630 operand immL_M1() %{
4631 predicate( n->get_long() == -1L );
4632 match(ConL);
4633 op_cost(0);
4634
4635 format %{ %}
4636 interface(CONST_INTER);
4637 %}
4638
4639 // Long immediate from 0 to 127.
4640 // Used for a shorter form of long mul by 10.
4641 operand immL_127() %{
4642 predicate((0 <= n->get_long()) && (n->get_long() <= 127));
4643 match(ConL);
4644 op_cost(0);
4645
4646 format %{ %}
4647 interface(CONST_INTER);
4648 %}
4649
4650 // Long Immediate: low 32-bit mask
4651 operand immL_32bits() %{
4652 predicate(n->get_long() == 0xFFFFFFFFL);
4653 match(ConL);
4654 op_cost(0);
4655
4656 format %{ %}
4657 interface(CONST_INTER);
4658 %}
4659
4660 // Long Immediate: low 32-bit mask
4661 operand immL32() %{
4662 predicate(n->get_long() == (int)(n->get_long()));
4663 match(ConL);
4664 op_cost(20);
4665
4666 format %{ %}
4667 interface(CONST_INTER);
4668 %}
4669
4670 //Double Immediate zero
4671 operand immD0() %{
4672 // Do additional (and counter-intuitive) test against NaN to work around VC++
4673 // bug that generates code such that NaNs compare equal to 0.0
4674 predicate( UseSSE<=1 && n->getd() == 0.0 && !g_isnan(n->getd()) );
4675 match(ConD);
4676
4677 op_cost(5);
4678 format %{ %}
4679 interface(CONST_INTER);
4680 %}
4681
4682 // Double Immediate
4683 operand immD1() %{
4684 predicate( UseSSE<=1 && n->getd() == 1.0 );
4685 match(ConD);
4686
4687 op_cost(5);
4688 format %{ %}
4689 interface(CONST_INTER);
4690 %}
4691
4692 // Double Immediate
4693 operand immD() %{
4694 predicate(UseSSE<=1);
4695 match(ConD);
4696
4697 op_cost(5);
4698 format %{ %}
4699 interface(CONST_INTER);
4700 %}
4701
4702 operand immXD() %{
4703 predicate(UseSSE>=2);
4704 match(ConD);
4705
4706 op_cost(5);
4707 format %{ %}
4708 interface(CONST_INTER);
4709 %}
4710
4711 // Double Immediate zero
4712 operand immXD0() %{
4713 // Do additional (and counter-intuitive) test against NaN to work around VC++
4714 // bug that generates code such that NaNs compare equal to 0.0 AND do not
4715 // compare equal to -0.0.
4716 predicate( UseSSE>=2 && jlong_cast(n->getd()) == 0 );
4717 match(ConD);
4718
4719 format %{ %}
4720 interface(CONST_INTER);
4721 %}
4722
4723 // Float Immediate zero
4724 operand immF0() %{
4725 predicate( UseSSE == 0 && n->getf() == 0.0 );
4726 match(ConF);
4727
4728 op_cost(5);
4729 format %{ %}
4730 interface(CONST_INTER);
4731 %}
4732
4733 // Float Immediate
4734 operand immF() %{
4735 predicate( UseSSE == 0 );
4736 match(ConF);
4737
4738 op_cost(5);
4739 format %{ %}
4740 interface(CONST_INTER);
4741 %}
4742
4743 // Float Immediate
4744 operand immXF() %{
4745 predicate(UseSSE >= 1);
4746 match(ConF);
4747
4748 op_cost(5);
4749 format %{ %}
4750 interface(CONST_INTER);
4751 %}
4752
4753 // Float Immediate zero. Zero and not -0.0
4754 operand immXF0() %{
4755 predicate( UseSSE >= 1 && jint_cast(n->getf()) == 0 );
4756 match(ConF);
4757
4758 op_cost(5);
4759 format %{ %}
4760 interface(CONST_INTER);
4761 %}
4762
4763 // Immediates for special shifts (sign extend)
4764
4765 // Constants for increment
4766 operand immI_16() %{
4767 predicate( n->get_int() == 16 );
4768 match(ConI);
4769
4770 format %{ %}
4771 interface(CONST_INTER);
4772 %}
4773
4774 operand immI_24() %{
4775 predicate( n->get_int() == 24 );
4776 match(ConI);
4777
4778 format %{ %}
4779 interface(CONST_INTER);
4780 %}
4781
4782 // Constant for byte-wide masking
4783 operand immI_255() %{
4784 predicate( n->get_int() == 255 );
4785 match(ConI);
4786
4787 format %{ %}
4788 interface(CONST_INTER);
4789 %}
4790
4791 // Constant for short-wide masking
4792 operand immI_65535() %{
4793 predicate(n->get_int() == 65535);
4794 match(ConI);
4795
4796 format %{ %}
4797 interface(CONST_INTER);
4798 %}
4799
4800 // Register Operands
4801 // Integer Register
4802 operand eRegI() %{
4803 constraint(ALLOC_IN_RC(e_reg));
4804 match(RegI);
4805 match(xRegI);
4806 match(eAXRegI);
4807 match(eBXRegI);
4808 match(eCXRegI);
4809 match(eDXRegI);
4810 match(eDIRegI);
4811 match(eSIRegI);
4812
4813 format %{ %}
4814 interface(REG_INTER);
4815 %}
4816
4817 // Subset of Integer Register
4818 operand xRegI(eRegI reg) %{
4819 constraint(ALLOC_IN_RC(x_reg));
4820 match(reg);
4821 match(eAXRegI);
4822 match(eBXRegI);
4823 match(eCXRegI);
4824 match(eDXRegI);
4825
4826 format %{ %}
4827 interface(REG_INTER);
4828 %}
4829
4830 // Special Registers
4831 operand eAXRegI(xRegI reg) %{
4832 constraint(ALLOC_IN_RC(eax_reg));
4833 match(reg);
4834 match(eRegI);
4835
4836 format %{ "EAX" %}
4837 interface(REG_INTER);
4838 %}
4839
4840 // Special Registers
4841 operand eBXRegI(xRegI reg) %{
4842 constraint(ALLOC_IN_RC(ebx_reg));
4843 match(reg);
4844 match(eRegI);
4845
4846 format %{ "EBX" %}
4847 interface(REG_INTER);
4848 %}
4849
4850 operand eCXRegI(xRegI reg) %{
4851 constraint(ALLOC_IN_RC(ecx_reg));
4852 match(reg);
4853 match(eRegI);
4854
4855 format %{ "ECX" %}
4856 interface(REG_INTER);
4857 %}
4858
4859 operand eDXRegI(xRegI reg) %{
4860 constraint(ALLOC_IN_RC(edx_reg));
4861 match(reg);
4862 match(eRegI);
4863
4864 format %{ "EDX" %}
4865 interface(REG_INTER);
4866 %}
4867
4868 operand eDIRegI(xRegI reg) %{
4869 constraint(ALLOC_IN_RC(edi_reg));
4870 match(reg);
4871 match(eRegI);
4872
4873 format %{ "EDI" %}
4874 interface(REG_INTER);
4875 %}
4876
4877 operand naxRegI() %{
4878 constraint(ALLOC_IN_RC(nax_reg));
4879 match(RegI);
4880 match(eCXRegI);
4881 match(eDXRegI);
4882 match(eSIRegI);
4883 match(eDIRegI);
4884
4885 format %{ %}
4886 interface(REG_INTER);
4887 %}
4888
4889 operand nadxRegI() %{
4890 constraint(ALLOC_IN_RC(nadx_reg));
4891 match(RegI);
4892 match(eBXRegI);
4893 match(eCXRegI);
4894 match(eSIRegI);
4895 match(eDIRegI);
4896
4897 format %{ %}
4898 interface(REG_INTER);
4899 %}
4900
4901 operand ncxRegI() %{
4902 constraint(ALLOC_IN_RC(ncx_reg));
4903 match(RegI);
4904 match(eAXRegI);
4905 match(eDXRegI);
4906 match(eSIRegI);
4907 match(eDIRegI);
4908
4909 format %{ %}
4910 interface(REG_INTER);
4911 %}
4912
4913 // // This operand was used by cmpFastUnlock, but conflicted with 'object' reg
4914 // //
4915 operand eSIRegI(xRegI reg) %{
4916 constraint(ALLOC_IN_RC(esi_reg));
4917 match(reg);
4918 match(eRegI);
4919
4920 format %{ "ESI" %}
4921 interface(REG_INTER);
4922 %}
4923
4924 // Pointer Register
4925 operand anyRegP() %{
4926 constraint(ALLOC_IN_RC(any_reg));
4927 match(RegP);
4928 match(eAXRegP);
4929 match(eBXRegP);
4930 match(eCXRegP);
4931 match(eDIRegP);
4932 match(eRegP);
4933
4934 format %{ %}
4935 interface(REG_INTER);
4936 %}
4937
4938 operand eRegP() %{
4939 constraint(ALLOC_IN_RC(e_reg));
4940 match(RegP);
4941 match(eAXRegP);
4942 match(eBXRegP);
4943 match(eCXRegP);
4944 match(eDIRegP);
4945
4946 format %{ %}
4947 interface(REG_INTER);
4948 %}
4949
4950 // On windows95, EBP is not safe to use for implicit null tests.
4951 operand eRegP_no_EBP() %{
4952 constraint(ALLOC_IN_RC(e_reg_no_rbp));
4953 match(RegP);
4954 match(eAXRegP);
4955 match(eBXRegP);
4956 match(eCXRegP);
4957 match(eDIRegP);
4958
4959 op_cost(100);
4960 format %{ %}
4961 interface(REG_INTER);
4962 %}
4963
4964 operand naxRegP() %{
4965 constraint(ALLOC_IN_RC(nax_reg));
4966 match(RegP);
4967 match(eBXRegP);
4968 match(eDXRegP);
4969 match(eCXRegP);
4970 match(eSIRegP);
4971 match(eDIRegP);
4972
4973 format %{ %}
4974 interface(REG_INTER);
4975 %}
4976
4977 operand nabxRegP() %{
4978 constraint(ALLOC_IN_RC(nabx_reg));
4979 match(RegP);
4980 match(eCXRegP);
4981 match(eDXRegP);
4982 match(eSIRegP);
4983 match(eDIRegP);
4984
4985 format %{ %}
4986 interface(REG_INTER);
4987 %}
4988
4989 operand pRegP() %{
4990 constraint(ALLOC_IN_RC(p_reg));
4991 match(RegP);
4992 match(eBXRegP);
4993 match(eDXRegP);
4994 match(eSIRegP);
4995 match(eDIRegP);
4996
4997 format %{ %}
4998 interface(REG_INTER);
4999 %}
5000
5001 // Special Registers
5002 // Return a pointer value
5003 operand eAXRegP(eRegP reg) %{
5004 constraint(ALLOC_IN_RC(eax_reg));
5005 match(reg);
5006 format %{ "EAX" %}
5007 interface(REG_INTER);
5008 %}
5009
5010 // Used in AtomicAdd
5011 operand eBXRegP(eRegP reg) %{
5012 constraint(ALLOC_IN_RC(ebx_reg));
5013 match(reg);
5014 format %{ "EBX" %}
5015 interface(REG_INTER);
5016 %}
5017
5018 // Tail-call (interprocedural jump) to interpreter
5019 operand eCXRegP(eRegP reg) %{
5020 constraint(ALLOC_IN_RC(ecx_reg));
5021 match(reg);
5022 format %{ "ECX" %}
5023 interface(REG_INTER);
5024 %}
5025
5026 operand eSIRegP(eRegP reg) %{
5027 constraint(ALLOC_IN_RC(esi_reg));
5028 match(reg);
5029 format %{ "ESI" %}
5030 interface(REG_INTER);
5031 %}
5032
5033 // Used in rep stosw
5034 operand eDIRegP(eRegP reg) %{
5035 constraint(ALLOC_IN_RC(edi_reg));
5036 match(reg);
5037 format %{ "EDI" %}
5038 interface(REG_INTER);
5039 %}
5040
5041 operand eBPRegP() %{
5042 constraint(ALLOC_IN_RC(ebp_reg));
5043 match(RegP);
5044 format %{ "EBP" %}
5045 interface(REG_INTER);
5046 %}
5047
5048 operand eRegL() %{
5049 constraint(ALLOC_IN_RC(long_reg));
5050 match(RegL);
5051 match(eADXRegL);
5052
5053 format %{ %}
5054 interface(REG_INTER);
5055 %}
5056
5057 operand eADXRegL( eRegL reg ) %{
5058 constraint(ALLOC_IN_RC(eadx_reg));
5059 match(reg);
5060
5061 format %{ "EDX:EAX" %}
5062 interface(REG_INTER);
5063 %}
5064
5065 operand eBCXRegL( eRegL reg ) %{
5066 constraint(ALLOC_IN_RC(ebcx_reg));
5067 match(reg);
5068
5069 format %{ "EBX:ECX" %}
5070 interface(REG_INTER);
5071 %}
5072
5073 // Special case for integer high multiply
5074 operand eADXRegL_low_only() %{
5075 constraint(ALLOC_IN_RC(eadx_reg));
5076 match(RegL);
5077
5078 format %{ "EAX" %}
5079 interface(REG_INTER);
5080 %}
5081
5082 // Flags register, used as output of compare instructions
5083 operand eFlagsReg() %{
5084 constraint(ALLOC_IN_RC(int_flags));
5085 match(RegFlags);
5086
5087 format %{ "EFLAGS" %}
5088 interface(REG_INTER);
5089 %}
5090
5091 // Flags register, used as output of FLOATING POINT compare instructions
5092 operand eFlagsRegU() %{
5093 constraint(ALLOC_IN_RC(int_flags));
5094 match(RegFlags);
5095
5096 format %{ "EFLAGS_U" %}
5097 interface(REG_INTER);
5098 %}
5099
5100 operand eFlagsRegUCF() %{
5101 constraint(ALLOC_IN_RC(int_flags));
5102 match(RegFlags);
5103 predicate(false);
5104
5105 format %{ "EFLAGS_U_CF" %}
5106 interface(REG_INTER);
5107 %}
5108
5109 // Condition Code Register used by long compare
5110 operand flagsReg_long_LTGE() %{
5111 constraint(ALLOC_IN_RC(int_flags));
5112 match(RegFlags);
5113 format %{ "FLAGS_LTGE" %}
5114 interface(REG_INTER);
5115 %}
5116 operand flagsReg_long_EQNE() %{
5117 constraint(ALLOC_IN_RC(int_flags));
5118 match(RegFlags);
5119 format %{ "FLAGS_EQNE" %}
5120 interface(REG_INTER);
5121 %}
5122 operand flagsReg_long_LEGT() %{
5123 constraint(ALLOC_IN_RC(int_flags));
5124 match(RegFlags);
5125 format %{ "FLAGS_LEGT" %}
5126 interface(REG_INTER);
5127 %}
5128
5129 // Float register operands
5130 operand regD() %{
5131 predicate( UseSSE < 2 );
5132 constraint(ALLOC_IN_RC(dbl_reg));
5133 match(RegD);
5134 match(regDPR1);
5135 match(regDPR2);
5136 format %{ %}
5137 interface(REG_INTER);
5138 %}
5139
5140 operand regDPR1(regD reg) %{
5141 predicate( UseSSE < 2 );
5142 constraint(ALLOC_IN_RC(dbl_reg0));
5143 match(reg);
5144 format %{ "FPR1" %}
5145 interface(REG_INTER);
5146 %}
5147
5148 operand regDPR2(regD reg) %{
5149 predicate( UseSSE < 2 );
5150 constraint(ALLOC_IN_RC(dbl_reg1));
5151 match(reg);
5152 format %{ "FPR2" %}
5153 interface(REG_INTER);
5154 %}
5155
5156 operand regnotDPR1(regD reg) %{
5157 predicate( UseSSE < 2 );
5158 constraint(ALLOC_IN_RC(dbl_notreg0));
5159 match(reg);
5160 format %{ %}
5161 interface(REG_INTER);
5162 %}
5163
5164 // XMM Double register operands
5165 operand regXD() %{
5166 predicate( UseSSE>=2 );
5167 constraint(ALLOC_IN_RC(xdb_reg));
5168 match(RegD);
5169 match(regXD6);
5170 match(regXD7);
5171 format %{ %}
5172 interface(REG_INTER);
5173 %}
5174
5175 // XMM6 double register operands
5176 operand regXD6(regXD reg) %{
5177 predicate( UseSSE>=2 );
5178 constraint(ALLOC_IN_RC(xdb_reg6));
5179 match(reg);
5180 format %{ "XMM6" %}
5181 interface(REG_INTER);
5182 %}
5183
5184 // XMM7 double register operands
5185 operand regXD7(regXD reg) %{
5186 predicate( UseSSE>=2 );
5187 constraint(ALLOC_IN_RC(xdb_reg7));
5188 match(reg);
5189 format %{ "XMM7" %}
5190 interface(REG_INTER);
5191 %}
5192
5193 // Float register operands
5194 operand regF() %{
5195 predicate( UseSSE < 2 );
5196 constraint(ALLOC_IN_RC(flt_reg));
5197 match(RegF);
5198 match(regFPR1);
5199 format %{ %}
5200 interface(REG_INTER);
5201 %}
5202
5203 // Float register operands
5204 operand regFPR1(regF reg) %{
5205 predicate( UseSSE < 2 );
5206 constraint(ALLOC_IN_RC(flt_reg0));
5207 match(reg);
5208 format %{ "FPR1" %}
5209 interface(REG_INTER);
5210 %}
5211
5212 // XMM register operands
5213 operand regX() %{
5214 predicate( UseSSE>=1 );
5215 constraint(ALLOC_IN_RC(xmm_reg));
5216 match(RegF);
5217 format %{ %}
5218 interface(REG_INTER);
5219 %}
5220
5221
5222 //----------Memory Operands----------------------------------------------------
5223 // Direct Memory Operand
5224 operand direct(immP addr) %{
5225 match(addr);
5226
5227 format %{ "[$addr]" %}
5228 interface(MEMORY_INTER) %{
5229 base(0xFFFFFFFF);
5230 index(0x4);
5231 scale(0x0);
5232 disp($addr);
5233 %}
5234 %}
5235
5236 // Indirect Memory Operand
5237 operand indirect(eRegP reg) %{
5238 constraint(ALLOC_IN_RC(e_reg));
5239 match(reg);
5240
5241 format %{ "[$reg]" %}
5242 interface(MEMORY_INTER) %{
5243 base($reg);
5244 index(0x4);
5245 scale(0x0);
5246 disp(0x0);
5247 %}
5248 %}
5249
5250 // Indirect Memory Plus Short Offset Operand
5251 operand indOffset8(eRegP reg, immI8 off) %{
5252 match(AddP reg off);
5253
5254 format %{ "[$reg + $off]" %}
5255 interface(MEMORY_INTER) %{
5256 base($reg);
5257 index(0x4);
5258 scale(0x0);
5259 disp($off);
5260 %}
5261 %}
5262
5263 // Indirect Memory Plus Long Offset Operand
5264 operand indOffset32(eRegP reg, immI off) %{
5265 match(AddP reg off);
5266
5267 format %{ "[$reg + $off]" %}
5268 interface(MEMORY_INTER) %{
5269 base($reg);
5270 index(0x4);
5271 scale(0x0);
5272 disp($off);
5273 %}
5274 %}
5275
5276 // Indirect Memory Plus Long Offset Operand
5277 operand indOffset32X(eRegI reg, immP off) %{
5278 match(AddP off reg);
5279
5280 format %{ "[$reg + $off]" %}
5281 interface(MEMORY_INTER) %{
5282 base($reg);
5283 index(0x4);
5284 scale(0x0);
5285 disp($off);
5286 %}
5287 %}
5288
5289 // Indirect Memory Plus Index Register Plus Offset Operand
5290 operand indIndexOffset(eRegP reg, eRegI ireg, immI off) %{
5291 match(AddP (AddP reg ireg) off);
5292
5293 op_cost(10);
5294 format %{"[$reg + $off + $ireg]" %}
5295 interface(MEMORY_INTER) %{
5296 base($reg);
5297 index($ireg);
5298 scale(0x0);
5299 disp($off);
5300 %}
5301 %}
5302
5303 // Indirect Memory Plus Index Register Plus Offset Operand
5304 operand indIndex(eRegP reg, eRegI ireg) %{
5305 match(AddP reg ireg);
5306
5307 op_cost(10);
5308 format %{"[$reg + $ireg]" %}
5309 interface(MEMORY_INTER) %{
5310 base($reg);
5311 index($ireg);
5312 scale(0x0);
5313 disp(0x0);
5314 %}
5315 %}
5316
5317 // // -------------------------------------------------------------------------
5318 // // 486 architecture doesn't support "scale * index + offset" with out a base
5319 // // -------------------------------------------------------------------------
5320 // // Scaled Memory Operands
5321 // // Indirect Memory Times Scale Plus Offset Operand
5322 // operand indScaleOffset(immP off, eRegI ireg, immI2 scale) %{
5323 // match(AddP off (LShiftI ireg scale));
5324 //
5325 // op_cost(10);
5326 // format %{"[$off + $ireg << $scale]" %}
5327 // interface(MEMORY_INTER) %{
5328 // base(0x4);
5329 // index($ireg);
5330 // scale($scale);
5331 // disp($off);
5332 // %}
5333 // %}
5334
5335 // Indirect Memory Times Scale Plus Index Register
5336 operand indIndexScale(eRegP reg, eRegI ireg, immI2 scale) %{
5337 match(AddP reg (LShiftI ireg scale));
5338
5339 op_cost(10);
5340 format %{"[$reg + $ireg << $scale]" %}
5341 interface(MEMORY_INTER) %{
5342 base($reg);
5343 index($ireg);
5344 scale($scale);
5345 disp(0x0);
5346 %}
5347 %}
5348
5349 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
5350 operand indIndexScaleOffset(eRegP reg, immI off, eRegI ireg, immI2 scale) %{
5351 match(AddP (AddP reg (LShiftI ireg scale)) off);
5352
5353 op_cost(10);
5354 format %{"[$reg + $off + $ireg << $scale]" %}
5355 interface(MEMORY_INTER) %{
5356 base($reg);
5357 index($ireg);
5358 scale($scale);
5359 disp($off);
5360 %}
5361 %}
5362
5363 //----------Load Long Memory Operands------------------------------------------
5364 // The load-long idiom will use it's address expression again after loading
5365 // the first word of the long. If the load-long destination overlaps with
5366 // registers used in the addressing expression, the 2nd half will be loaded
5367 // from a clobbered address. Fix this by requiring that load-long use
5368 // address registers that do not overlap with the load-long target.
5369
5370 // load-long support
5371 operand load_long_RegP() %{
5372 constraint(ALLOC_IN_RC(esi_reg));
5373 match(RegP);
5374 match(eSIRegP);
5375 op_cost(100);
5376 format %{ %}
5377 interface(REG_INTER);
5378 %}
5379
5380 // Indirect Memory Operand Long
5381 operand load_long_indirect(load_long_RegP reg) %{
5382 constraint(ALLOC_IN_RC(esi_reg));
5383 match(reg);
5384
5385 format %{ "[$reg]" %}
5386 interface(MEMORY_INTER) %{
5387 base($reg);
5388 index(0x4);
5389 scale(0x0);
5390 disp(0x0);
5391 %}
5392 %}
5393
5394 // Indirect Memory Plus Long Offset Operand
5395 operand load_long_indOffset32(load_long_RegP reg, immI off) %{
5396 match(AddP reg off);
5397
5398 format %{ "[$reg + $off]" %}
5399 interface(MEMORY_INTER) %{
5400 base($reg);
5401 index(0x4);
5402 scale(0x0);
5403 disp($off);
5404 %}
5405 %}
5406
5407 opclass load_long_memory(load_long_indirect, load_long_indOffset32);
5408
5409
5410 //----------Special Memory Operands--------------------------------------------
5411 // Stack Slot Operand - This operand is used for loading and storing temporary
5412 // values on the stack where a match requires a value to
5413 // flow through memory.
5414 operand stackSlotP(sRegP reg) %{
5415 constraint(ALLOC_IN_RC(stack_slots));
5416 // No match rule because this operand is only generated in matching
5417 format %{ "[$reg]" %}
5418 interface(MEMORY_INTER) %{
5419 base(0x4); // ESP
5420 index(0x4); // No Index
5421 scale(0x0); // No Scale
5422 disp($reg); // Stack Offset
5423 %}
5424 %}
5425
5426 operand stackSlotI(sRegI reg) %{
5427 constraint(ALLOC_IN_RC(stack_slots));
5428 // No match rule because this operand is only generated in matching
5429 format %{ "[$reg]" %}
5430 interface(MEMORY_INTER) %{
5431 base(0x4); // ESP
5432 index(0x4); // No Index
5433 scale(0x0); // No Scale
5434 disp($reg); // Stack Offset
5435 %}
5436 %}
5437
5438 operand stackSlotF(sRegF reg) %{
5439 constraint(ALLOC_IN_RC(stack_slots));
5440 // No match rule because this operand is only generated in matching
5441 format %{ "[$reg]" %}
5442 interface(MEMORY_INTER) %{
5443 base(0x4); // ESP
5444 index(0x4); // No Index
5445 scale(0x0); // No Scale
5446 disp($reg); // Stack Offset
5447 %}
5448 %}
5449
5450 operand stackSlotD(sRegD reg) %{
5451 constraint(ALLOC_IN_RC(stack_slots));
5452 // No match rule because this operand is only generated in matching
5453 format %{ "[$reg]" %}
5454 interface(MEMORY_INTER) %{
5455 base(0x4); // ESP
5456 index(0x4); // No Index
5457 scale(0x0); // No Scale
5458 disp($reg); // Stack Offset
5459 %}
5460 %}
5461
5462 operand stackSlotL(sRegL reg) %{
5463 constraint(ALLOC_IN_RC(stack_slots));
5464 // No match rule because this operand is only generated in matching
5465 format %{ "[$reg]" %}
5466 interface(MEMORY_INTER) %{
5467 base(0x4); // ESP
5468 index(0x4); // No Index
5469 scale(0x0); // No Scale
5470 disp($reg); // Stack Offset
5471 %}
5472 %}
5473
5474 //----------Memory Operands - Win95 Implicit Null Variants----------------
5475 // Indirect Memory Operand
5476 operand indirect_win95_safe(eRegP_no_EBP reg)
5477 %{
5478 constraint(ALLOC_IN_RC(e_reg));
5479 match(reg);
5480
5481 op_cost(100);
5482 format %{ "[$reg]" %}
5483 interface(MEMORY_INTER) %{
5484 base($reg);
5485 index(0x4);
5486 scale(0x0);
5487 disp(0x0);
5488 %}
5489 %}
5490
5491 // Indirect Memory Plus Short Offset Operand
5492 operand indOffset8_win95_safe(eRegP_no_EBP reg, immI8 off)
5493 %{
5494 match(AddP reg off);
5495
5496 op_cost(100);
5497 format %{ "[$reg + $off]" %}
5498 interface(MEMORY_INTER) %{
5499 base($reg);
5500 index(0x4);
5501 scale(0x0);
5502 disp($off);
5503 %}
5504 %}
5505
5506 // Indirect Memory Plus Long Offset Operand
5507 operand indOffset32_win95_safe(eRegP_no_EBP reg, immI off)
5508 %{
5509 match(AddP reg off);
5510
5511 op_cost(100);
5512 format %{ "[$reg + $off]" %}
5513 interface(MEMORY_INTER) %{
5514 base($reg);
5515 index(0x4);
5516 scale(0x0);
5517 disp($off);
5518 %}
5519 %}
5520
5521 // Indirect Memory Plus Index Register Plus Offset Operand
5522 operand indIndexOffset_win95_safe(eRegP_no_EBP reg, eRegI ireg, immI off)
5523 %{
5524 match(AddP (AddP reg ireg) off);
5525
5526 op_cost(100);
5527 format %{"[$reg + $off + $ireg]" %}
5528 interface(MEMORY_INTER) %{
5529 base($reg);
5530 index($ireg);
5531 scale(0x0);
5532 disp($off);
5533 %}
5534 %}
5535
5536 // Indirect Memory Times Scale Plus Index Register
5537 operand indIndexScale_win95_safe(eRegP_no_EBP reg, eRegI ireg, immI2 scale)
5538 %{
5539 match(AddP reg (LShiftI ireg scale));
5540
5541 op_cost(100);
5542 format %{"[$reg + $ireg << $scale]" %}
5543 interface(MEMORY_INTER) %{
5544 base($reg);
5545 index($ireg);
5546 scale($scale);
5547 disp(0x0);
5548 %}
5549 %}
5550
5551 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
5552 operand indIndexScaleOffset_win95_safe(eRegP_no_EBP reg, immI off, eRegI ireg, immI2 scale)
5553 %{
5554 match(AddP (AddP reg (LShiftI ireg scale)) off);
5555
5556 op_cost(100);
5557 format %{"[$reg + $off + $ireg << $scale]" %}
5558 interface(MEMORY_INTER) %{
5559 base($reg);
5560 index($ireg);
5561 scale($scale);
5562 disp($off);
5563 %}
5564 %}
5565
5566 //----------Conditional Branch Operands----------------------------------------
5567 // Comparison Op - This is the operation of the comparison, and is limited to
5568 // the following set of codes:
5569 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
5570 //
5571 // Other attributes of the comparison, such as unsignedness, are specified
5572 // by the comparison instruction that sets a condition code flags register.
5573 // That result is represented by a flags operand whose subtype is appropriate
5574 // to the unsignedness (etc.) of the comparison.
5575 //
5576 // Later, the instruction which matches both the Comparison Op (a Bool) and
5577 // the flags (produced by the Cmp) specifies the coding of the comparison op
5578 // by matching a specific subtype of Bool operand below, such as cmpOpU.
5579
5580 // Comparision Code
5581 operand cmpOp() %{
5582 match(Bool);
5583
5584 format %{ "" %}
5585 interface(COND_INTER) %{
5586 equal(0x4, "e");
5587 not_equal(0x5, "ne");
5588 less(0xC, "l");
5589 greater_equal(0xD, "ge");
5590 less_equal(0xE, "le");
5591 greater(0xF, "g");
5592 %}
5593 %}
5594
5595 // Comparison Code, unsigned compare. Used by FP also, with
5596 // C2 (unordered) turned into GT or LT already. The other bits
5597 // C0 and C3 are turned into Carry & Zero flags.
5598 operand cmpOpU() %{
5599 match(Bool);
5600
5601 format %{ "" %}
5602 interface(COND_INTER) %{
5603 equal(0x4, "e");
5604 not_equal(0x5, "ne");
5605 less(0x2, "b");
5606 greater_equal(0x3, "nb");
5607 less_equal(0x6, "be");
5608 greater(0x7, "nbe");
5609 %}
5610 %}
5611
5612 // Floating comparisons that don't require any fixup for the unordered case
5613 operand cmpOpUCF() %{
5614 match(Bool);
5615 predicate(n->as_Bool()->_test._test == BoolTest::lt ||
5616 n->as_Bool()->_test._test == BoolTest::ge ||
5617 n->as_Bool()->_test._test == BoolTest::le ||
5618 n->as_Bool()->_test._test == BoolTest::gt);
5619 format %{ "" %}
5620 interface(COND_INTER) %{
5621 equal(0x4, "e");
5622 not_equal(0x5, "ne");
5623 less(0x2, "b");
5624 greater_equal(0x3, "nb");
5625 less_equal(0x6, "be");
5626 greater(0x7, "nbe");
5627 %}
5628 %}
5629
5630
5631 // Floating comparisons that can be fixed up with extra conditional jumps
5632 operand cmpOpUCF2() %{
5633 match(Bool);
5634 predicate(n->as_Bool()->_test._test == BoolTest::ne ||
5635 n->as_Bool()->_test._test == BoolTest::eq);
5636 format %{ "" %}
5637 interface(COND_INTER) %{
5638 equal(0x4, "e");
5639 not_equal(0x5, "ne");
5640 less(0x2, "b");
5641 greater_equal(0x3, "nb");
5642 less_equal(0x6, "be");
5643 greater(0x7, "nbe");
5644 %}
5645 %}
5646
5647 // Comparison Code for FP conditional move
5648 operand cmpOp_fcmov() %{
5649 match(Bool);
5650
5651 format %{ "" %}
5652 interface(COND_INTER) %{
5653 equal (0x0C8);
5654 not_equal (0x1C8);
5655 less (0x0C0);
5656 greater_equal(0x1C0);
5657 less_equal (0x0D0);
5658 greater (0x1D0);
5659 %}
5660 %}
5661
5662 // Comparision Code used in long compares
5663 operand cmpOp_commute() %{
5664 match(Bool);
5665
5666 format %{ "" %}
5667 interface(COND_INTER) %{
5668 equal(0x4, "e");
5669 not_equal(0x5, "ne");
5670 less(0xF, "g");
5671 greater_equal(0xE, "le");
5672 less_equal(0xD, "ge");
5673 greater(0xC, "l");
5674 %}
5675 %}
5676
5677 //----------OPERAND CLASSES----------------------------------------------------
5678 // Operand Classes are groups of operands that are used as to simplify
5679 // instruction definitions by not requiring the AD writer to specify separate
5680 // instructions for every form of operand when the instruction accepts
5681 // multiple operand types with the same basic encoding and format. The classic
5682 // case of this is memory operands.
5683
5684 opclass memory(direct, indirect, indOffset8, indOffset32, indOffset32X, indIndexOffset,
5685 indIndex, indIndexScale, indIndexScaleOffset);
5686
5687 // Long memory operations are encoded in 2 instructions and a +4 offset.
5688 // This means some kind of offset is always required and you cannot use
5689 // an oop as the offset (done when working on static globals).
5690 opclass long_memory(direct, indirect, indOffset8, indOffset32, indIndexOffset,
5691 indIndex, indIndexScale, indIndexScaleOffset);
5692
5693
5694 //----------PIPELINE-----------------------------------------------------------
5695 // Rules which define the behavior of the target architectures pipeline.
5696 pipeline %{
5697
5698 //----------ATTRIBUTES---------------------------------------------------------
5699 attributes %{
5700 variable_size_instructions; // Fixed size instructions
5701 max_instructions_per_bundle = 3; // Up to 3 instructions per bundle
5702 instruction_unit_size = 1; // An instruction is 1 bytes long
5703 instruction_fetch_unit_size = 16; // The processor fetches one line
5704 instruction_fetch_units = 1; // of 16 bytes
5705
5706 // List of nop instructions
5707 nops( MachNop );
5708 %}
5709
5710 //----------RESOURCES----------------------------------------------------------
5711 // Resources are the functional units available to the machine
5712
5713 // Generic P2/P3 pipeline
5714 // 3 decoders, only D0 handles big operands; a "bundle" is the limit of
5715 // 3 instructions decoded per cycle.
5716 // 2 load/store ops per cycle, 1 branch, 1 FPU,
5717 // 2 ALU op, only ALU0 handles mul/div instructions.
5718 resources( D0, D1, D2, DECODE = D0 | D1 | D2,
5719 MS0, MS1, MEM = MS0 | MS1,
5720 BR, FPU,
5721 ALU0, ALU1, ALU = ALU0 | ALU1 );
5722
5723 //----------PIPELINE DESCRIPTION-----------------------------------------------
5724 // Pipeline Description specifies the stages in the machine's pipeline
5725
5726 // Generic P2/P3 pipeline
5727 pipe_desc(S0, S1, S2, S3, S4, S5);
5728
5729 //----------PIPELINE CLASSES---------------------------------------------------
5730 // Pipeline Classes describe the stages in which input and output are
5731 // referenced by the hardware pipeline.
5732
5733 // Naming convention: ialu or fpu
5734 // Then: _reg
5735 // Then: _reg if there is a 2nd register
5736 // Then: _long if it's a pair of instructions implementing a long
5737 // Then: _fat if it requires the big decoder
5738 // Or: _mem if it requires the big decoder and a memory unit.
5739
5740 // Integer ALU reg operation
5741 pipe_class ialu_reg(eRegI dst) %{
5742 single_instruction;
5743 dst : S4(write);
5744 dst : S3(read);
5745 DECODE : S0; // any decoder
5746 ALU : S3; // any alu
5747 %}
5748
5749 // Long ALU reg operation
5750 pipe_class ialu_reg_long(eRegL dst) %{
5751 instruction_count(2);
5752 dst : S4(write);
5753 dst : S3(read);
5754 DECODE : S0(2); // any 2 decoders
5755 ALU : S3(2); // both alus
5756 %}
5757
5758 // Integer ALU reg operation using big decoder
5759 pipe_class ialu_reg_fat(eRegI dst) %{
5760 single_instruction;
5761 dst : S4(write);
5762 dst : S3(read);
5763 D0 : S0; // big decoder only
5764 ALU : S3; // any alu
5765 %}
5766
5767 // Long ALU reg operation using big decoder
5768 pipe_class ialu_reg_long_fat(eRegL dst) %{
5769 instruction_count(2);
5770 dst : S4(write);
5771 dst : S3(read);
5772 D0 : S0(2); // big decoder only; twice
5773 ALU : S3(2); // any 2 alus
5774 %}
5775
5776 // Integer ALU reg-reg operation
5777 pipe_class ialu_reg_reg(eRegI dst, eRegI src) %{
5778 single_instruction;
5779 dst : S4(write);
5780 src : S3(read);
5781 DECODE : S0; // any decoder
5782 ALU : S3; // any alu
5783 %}
5784
5785 // Long ALU reg-reg operation
5786 pipe_class ialu_reg_reg_long(eRegL dst, eRegL src) %{
5787 instruction_count(2);
5788 dst : S4(write);
5789 src : S3(read);
5790 DECODE : S0(2); // any 2 decoders
5791 ALU : S3(2); // both alus
5792 %}
5793
5794 // Integer ALU reg-reg operation
5795 pipe_class ialu_reg_reg_fat(eRegI dst, memory src) %{
5796 single_instruction;
5797 dst : S4(write);
5798 src : S3(read);
5799 D0 : S0; // big decoder only
5800 ALU : S3; // any alu
5801 %}
5802
5803 // Long ALU reg-reg operation
5804 pipe_class ialu_reg_reg_long_fat(eRegL dst, eRegL src) %{
5805 instruction_count(2);
5806 dst : S4(write);
5807 src : S3(read);
5808 D0 : S0(2); // big decoder only; twice
5809 ALU : S3(2); // both alus
5810 %}
5811
5812 // Integer ALU reg-mem operation
5813 pipe_class ialu_reg_mem(eRegI dst, memory mem) %{
5814 single_instruction;
5815 dst : S5(write);
5816 mem : S3(read);
5817 D0 : S0; // big decoder only
5818 ALU : S4; // any alu
5819 MEM : S3; // any mem
5820 %}
5821
5822 // Long ALU reg-mem operation
5823 pipe_class ialu_reg_long_mem(eRegL dst, load_long_memory mem) %{
5824 instruction_count(2);
5825 dst : S5(write);
5826 mem : S3(read);
5827 D0 : S0(2); // big decoder only; twice
5828 ALU : S4(2); // any 2 alus
5829 MEM : S3(2); // both mems
5830 %}
5831
5832 // Integer mem operation (prefetch)
5833 pipe_class ialu_mem(memory mem)
5834 %{
5835 single_instruction;
5836 mem : S3(read);
5837 D0 : S0; // big decoder only
5838 MEM : S3; // any mem
5839 %}
5840
5841 // Integer Store to Memory
5842 pipe_class ialu_mem_reg(memory mem, eRegI src) %{
5843 single_instruction;
5844 mem : S3(read);
5845 src : S5(read);
5846 D0 : S0; // big decoder only
5847 ALU : S4; // any alu
5848 MEM : S3;
5849 %}
5850
5851 // Long Store to Memory
5852 pipe_class ialu_mem_long_reg(memory mem, eRegL src) %{
5853 instruction_count(2);
5854 mem : S3(read);
5855 src : S5(read);
5856 D0 : S0(2); // big decoder only; twice
5857 ALU : S4(2); // any 2 alus
5858 MEM : S3(2); // Both mems
5859 %}
5860
5861 // Integer Store to Memory
5862 pipe_class ialu_mem_imm(memory mem) %{
5863 single_instruction;
5864 mem : S3(read);
5865 D0 : S0; // big decoder only
5866 ALU : S4; // any alu
5867 MEM : S3;
5868 %}
5869
5870 // Integer ALU0 reg-reg operation
5871 pipe_class ialu_reg_reg_alu0(eRegI dst, eRegI src) %{
5872 single_instruction;
5873 dst : S4(write);
5874 src : S3(read);
5875 D0 : S0; // Big decoder only
5876 ALU0 : S3; // only alu0
5877 %}
5878
5879 // Integer ALU0 reg-mem operation
5880 pipe_class ialu_reg_mem_alu0(eRegI dst, memory mem) %{
5881 single_instruction;
5882 dst : S5(write);
5883 mem : S3(read);
5884 D0 : S0; // big decoder only
5885 ALU0 : S4; // ALU0 only
5886 MEM : S3; // any mem
5887 %}
5888
5889 // Integer ALU reg-reg operation
5890 pipe_class ialu_cr_reg_reg(eFlagsReg cr, eRegI src1, eRegI src2) %{
5891 single_instruction;
5892 cr : S4(write);
5893 src1 : S3(read);
5894 src2 : S3(read);
5895 DECODE : S0; // any decoder
5896 ALU : S3; // any alu
5897 %}
5898
5899 // Integer ALU reg-imm operation
5900 pipe_class ialu_cr_reg_imm(eFlagsReg cr, eRegI src1) %{
5901 single_instruction;
5902 cr : S4(write);
5903 src1 : S3(read);
5904 DECODE : S0; // any decoder
5905 ALU : S3; // any alu
5906 %}
5907
5908 // Integer ALU reg-mem operation
5909 pipe_class ialu_cr_reg_mem(eFlagsReg cr, eRegI src1, memory src2) %{
5910 single_instruction;
5911 cr : S4(write);
5912 src1 : S3(read);
5913 src2 : S3(read);
5914 D0 : S0; // big decoder only
5915 ALU : S4; // any alu
5916 MEM : S3;
5917 %}
5918
5919 // Conditional move reg-reg
5920 pipe_class pipe_cmplt( eRegI p, eRegI q, eRegI y ) %{
5921 instruction_count(4);
5922 y : S4(read);
5923 q : S3(read);
5924 p : S3(read);
5925 DECODE : S0(4); // any decoder
5926 %}
5927
5928 // Conditional move reg-reg
5929 pipe_class pipe_cmov_reg( eRegI dst, eRegI src, eFlagsReg cr ) %{
5930 single_instruction;
5931 dst : S4(write);
5932 src : S3(read);
5933 cr : S3(read);
5934 DECODE : S0; // any decoder
5935 %}
5936
5937 // Conditional move reg-mem
5938 pipe_class pipe_cmov_mem( eFlagsReg cr, eRegI dst, memory src) %{
5939 single_instruction;
5940 dst : S4(write);
5941 src : S3(read);
5942 cr : S3(read);
5943 DECODE : S0; // any decoder
5944 MEM : S3;
5945 %}
5946
5947 // Conditional move reg-reg long
5948 pipe_class pipe_cmov_reg_long( eFlagsReg cr, eRegL dst, eRegL src) %{
5949 single_instruction;
5950 dst : S4(write);
5951 src : S3(read);
5952 cr : S3(read);
5953 DECODE : S0(2); // any 2 decoders
5954 %}
5955
5956 // Conditional move double reg-reg
5957 pipe_class pipe_cmovD_reg( eFlagsReg cr, regDPR1 dst, regD src) %{
5958 single_instruction;
5959 dst : S4(write);
5960 src : S3(read);
5961 cr : S3(read);
5962 DECODE : S0; // any decoder
5963 %}
5964
5965 // Float reg-reg operation
5966 pipe_class fpu_reg(regD dst) %{
5967 instruction_count(2);
5968 dst : S3(read);
5969 DECODE : S0(2); // any 2 decoders
5970 FPU : S3;
5971 %}
5972
5973 // Float reg-reg operation
5974 pipe_class fpu_reg_reg(regD dst, regD src) %{
5975 instruction_count(2);
5976 dst : S4(write);
5977 src : S3(read);
5978 DECODE : S0(2); // any 2 decoders
5979 FPU : S3;
5980 %}
5981
5982 // Float reg-reg operation
5983 pipe_class fpu_reg_reg_reg(regD dst, regD src1, regD src2) %{
5984 instruction_count(3);
5985 dst : S4(write);
5986 src1 : S3(read);
5987 src2 : S3(read);
5988 DECODE : S0(3); // any 3 decoders
5989 FPU : S3(2);
5990 %}
5991
5992 // Float reg-reg operation
5993 pipe_class fpu_reg_reg_reg_reg(regD dst, regD src1, regD src2, regD src3) %{
5994 instruction_count(4);
5995 dst : S4(write);
5996 src1 : S3(read);
5997 src2 : S3(read);
5998 src3 : S3(read);
5999 DECODE : S0(4); // any 3 decoders
6000 FPU : S3(2);
6001 %}
6002
6003 // Float reg-reg operation
6004 pipe_class fpu_reg_mem_reg_reg(regD dst, memory src1, regD src2, regD src3) %{
6005 instruction_count(4);
6006 dst : S4(write);
6007 src1 : S3(read);
6008 src2 : S3(read);
6009 src3 : S3(read);
6010 DECODE : S1(3); // any 3 decoders
6011 D0 : S0; // Big decoder only
6012 FPU : S3(2);
6013 MEM : S3;
6014 %}
6015
6016 // Float reg-mem operation
6017 pipe_class fpu_reg_mem(regD dst, memory mem) %{
6018 instruction_count(2);
6019 dst : S5(write);
6020 mem : S3(read);
6021 D0 : S0; // big decoder only
6022 DECODE : S1; // any decoder for FPU POP
6023 FPU : S4;
6024 MEM : S3; // any mem
6025 %}
6026
6027 // Float reg-mem operation
6028 pipe_class fpu_reg_reg_mem(regD dst, regD src1, memory mem) %{
6029 instruction_count(3);
6030 dst : S5(write);
6031 src1 : S3(read);
6032 mem : S3(read);
6033 D0 : S0; // big decoder only
6034 DECODE : S1(2); // any decoder for FPU POP
6035 FPU : S4;
6036 MEM : S3; // any mem
6037 %}
6038
6039 // Float mem-reg operation
6040 pipe_class fpu_mem_reg(memory mem, regD src) %{
6041 instruction_count(2);
6042 src : S5(read);
6043 mem : S3(read);
6044 DECODE : S0; // any decoder for FPU PUSH
6045 D0 : S1; // big decoder only
6046 FPU : S4;
6047 MEM : S3; // any mem
6048 %}
6049
6050 pipe_class fpu_mem_reg_reg(memory mem, regD src1, regD src2) %{
6051 instruction_count(3);
6052 src1 : S3(read);
6053 src2 : S3(read);
6054 mem : S3(read);
6055 DECODE : S0(2); // any decoder for FPU PUSH
6056 D0 : S1; // big decoder only
6057 FPU : S4;
6058 MEM : S3; // any mem
6059 %}
6060
6061 pipe_class fpu_mem_reg_mem(memory mem, regD src1, memory src2) %{
6062 instruction_count(3);
6063 src1 : S3(read);
6064 src2 : S3(read);
6065 mem : S4(read);
6066 DECODE : S0; // any decoder for FPU PUSH
6067 D0 : S0(2); // big decoder only
6068 FPU : S4;
6069 MEM : S3(2); // any mem
6070 %}
6071
6072 pipe_class fpu_mem_mem(memory dst, memory src1) %{
6073 instruction_count(2);
6074 src1 : S3(read);
6075 dst : S4(read);
6076 D0 : S0(2); // big decoder only
6077 MEM : S3(2); // any mem
6078 %}
6079
6080 pipe_class fpu_mem_mem_mem(memory dst, memory src1, memory src2) %{
6081 instruction_count(3);
6082 src1 : S3(read);
6083 src2 : S3(read);
6084 dst : S4(read);
6085 D0 : S0(3); // big decoder only
6086 FPU : S4;
6087 MEM : S3(3); // any mem
6088 %}
6089
6090 pipe_class fpu_mem_reg_con(memory mem, regD src1) %{
6091 instruction_count(3);
6092 src1 : S4(read);
6093 mem : S4(read);
6094 DECODE : S0; // any decoder for FPU PUSH
6095 D0 : S0(2); // big decoder only
6096 FPU : S4;
6097 MEM : S3(2); // any mem
6098 %}
6099
6100 // Float load constant
6101 pipe_class fpu_reg_con(regD dst) %{
6102 instruction_count(2);
6103 dst : S5(write);
6104 D0 : S0; // big decoder only for the load
6105 DECODE : S1; // any decoder for FPU POP
6106 FPU : S4;
6107 MEM : S3; // any mem
6108 %}
6109
6110 // Float load constant
6111 pipe_class fpu_reg_reg_con(regD dst, regD src) %{
6112 instruction_count(3);
6113 dst : S5(write);
6114 src : S3(read);
6115 D0 : S0; // big decoder only for the load
6116 DECODE : S1(2); // any decoder for FPU POP
6117 FPU : S4;
6118 MEM : S3; // any mem
6119 %}
6120
6121 // UnConditional branch
6122 pipe_class pipe_jmp( label labl ) %{
6123 single_instruction;
6124 BR : S3;
6125 %}
6126
6127 // Conditional branch
6128 pipe_class pipe_jcc( cmpOp cmp, eFlagsReg cr, label labl ) %{
6129 single_instruction;
6130 cr : S1(read);
6131 BR : S3;
6132 %}
6133
6134 // Allocation idiom
6135 pipe_class pipe_cmpxchg( eRegP dst, eRegP heap_ptr ) %{
6136 instruction_count(1); force_serialization;
6137 fixed_latency(6);
6138 heap_ptr : S3(read);
6139 DECODE : S0(3);
6140 D0 : S2;
6141 MEM : S3;
6142 ALU : S3(2);
6143 dst : S5(write);
6144 BR : S5;
6145 %}
6146
6147 // Generic big/slow expanded idiom
6148 pipe_class pipe_slow( ) %{
6149 instruction_count(10); multiple_bundles; force_serialization;
6150 fixed_latency(100);
6151 D0 : S0(2);
6152 MEM : S3(2);
6153 %}
6154
6155 // The real do-nothing guy
6156 pipe_class empty( ) %{
6157 instruction_count(0);
6158 %}
6159
6160 // Define the class for the Nop node
6161 define %{
6162 MachNop = empty;
6163 %}
6164
6165 %}
6166
6167 //----------INSTRUCTIONS-------------------------------------------------------
6168 //
6169 // match -- States which machine-independent subtree may be replaced
6170 // by this instruction.
6171 // ins_cost -- The estimated cost of this instruction is used by instruction
6172 // selection to identify a minimum cost tree of machine
6173 // instructions that matches a tree of machine-independent
6174 // instructions.
6175 // format -- A string providing the disassembly for this instruction.
6176 // The value of an instruction's operand may be inserted
6177 // by referring to it with a '$' prefix.
6178 // opcode -- Three instruction opcodes may be provided. These are referred
6179 // to within an encode class as $primary, $secondary, and $tertiary
6180 // respectively. The primary opcode is commonly used to
6181 // indicate the type of machine instruction, while secondary
6182 // and tertiary are often used for prefix options or addressing
6183 // modes.
6184 // ins_encode -- A list of encode classes with parameters. The encode class
6185 // name must have been defined in an 'enc_class' specification
6186 // in the encode section of the architecture description.
6187
6188 //----------BSWAP-Instruction--------------------------------------------------
6189 instruct bytes_reverse_int(eRegI dst) %{
6190 match(Set dst (ReverseBytesI dst));
6191
6192 format %{ "BSWAP $dst" %}
6193 opcode(0x0F, 0xC8);
6194 ins_encode( OpcP, OpcSReg(dst) );
6195 ins_pipe( ialu_reg );
6196 %}
6197
6198 instruct bytes_reverse_long(eRegL dst) %{
6199 match(Set dst (ReverseBytesL dst));
6200
6201 format %{ "BSWAP $dst.lo\n\t"
6202 "BSWAP $dst.hi\n\t"
6203 "XCHG $dst.lo $dst.hi" %}
6204
6205 ins_cost(125);
6206 ins_encode( bswap_long_bytes(dst) );
6207 ins_pipe( ialu_reg_reg);
6208 %}
6209
6210
6211 //---------- Zeros Count Instructions ------------------------------------------
6212
6213 instruct countLeadingZerosI(eRegI dst, eRegI src, eFlagsReg cr) %{
6214 predicate(UseCountLeadingZerosInstruction);
6215 match(Set dst (CountLeadingZerosI src));
6216 effect(KILL cr);
6217
6218 format %{ "LZCNT $dst, $src\t# count leading zeros (int)" %}
6219 ins_encode %{
6220 __ lzcntl($dst$$Register, $src$$Register);
6221 %}
6222 ins_pipe(ialu_reg);
6223 %}
6224
6225 instruct countLeadingZerosI_bsr(eRegI dst, eRegI src, eFlagsReg cr) %{
6226 predicate(!UseCountLeadingZerosInstruction);
6227 match(Set dst (CountLeadingZerosI src));
6228 effect(KILL cr);
6229
6230 format %{ "BSR $dst, $src\t# count leading zeros (int)\n\t"
6231 "JNZ skip\n\t"
6232 "MOV $dst, -1\n"
6233 "skip:\n\t"
6234 "NEG $dst\n\t"
6235 "ADD $dst, 31" %}
6236 ins_encode %{
6237 Register Rdst = $dst$$Register;
6238 Register Rsrc = $src$$Register;
6239 Label skip;
6240 __ bsrl(Rdst, Rsrc);
6241 __ jccb(Assembler::notZero, skip);
6242 __ movl(Rdst, -1);
6243 __ bind(skip);
6244 __ negl(Rdst);
6245 __ addl(Rdst, BitsPerInt - 1);
6246 %}
6247 ins_pipe(ialu_reg);
6248 %}
6249
6250 instruct countLeadingZerosL(eRegI dst, eRegL src, eFlagsReg cr) %{
6251 predicate(UseCountLeadingZerosInstruction);
6252 match(Set dst (CountLeadingZerosL src));
6253 effect(TEMP dst, KILL cr);
6254
6255 format %{ "LZCNT $dst, $src.hi\t# count leading zeros (long)\n\t"
6256 "JNC done\n\t"
6257 "LZCNT $dst, $src.lo\n\t"
6258 "ADD $dst, 32\n"
6259 "done:" %}
6260 ins_encode %{
6261 Register Rdst = $dst$$Register;
6262 Register Rsrc = $src$$Register;
6263 Label done;
6264 __ lzcntl(Rdst, HIGH_FROM_LOW(Rsrc));
6265 __ jccb(Assembler::carryClear, done);
6266 __ lzcntl(Rdst, Rsrc);
6267 __ addl(Rdst, BitsPerInt);
6268 __ bind(done);
6269 %}
6270 ins_pipe(ialu_reg);
6271 %}
6272
6273 instruct countLeadingZerosL_bsr(eRegI dst, eRegL src, eFlagsReg cr) %{
6274 predicate(!UseCountLeadingZerosInstruction);
6275 match(Set dst (CountLeadingZerosL src));
6276 effect(TEMP dst, KILL cr);
6277
6278 format %{ "BSR $dst, $src.hi\t# count leading zeros (long)\n\t"
6279 "JZ msw_is_zero\n\t"
6280 "ADD $dst, 32\n\t"
6281 "JMP not_zero\n"
6282 "msw_is_zero:\n\t"
6283 "BSR $dst, $src.lo\n\t"
6284 "JNZ not_zero\n\t"
6285 "MOV $dst, -1\n"
6286 "not_zero:\n\t"
6287 "NEG $dst\n\t"
6288 "ADD $dst, 63\n" %}
6289 ins_encode %{
6290 Register Rdst = $dst$$Register;
6291 Register Rsrc = $src$$Register;
6292 Label msw_is_zero;
6293 Label not_zero;
6294 __ bsrl(Rdst, HIGH_FROM_LOW(Rsrc));
6295 __ jccb(Assembler::zero, msw_is_zero);
6296 __ addl(Rdst, BitsPerInt);
6297 __ jmpb(not_zero);
6298 __ bind(msw_is_zero);
6299 __ bsrl(Rdst, Rsrc);
6300 __ jccb(Assembler::notZero, not_zero);
6301 __ movl(Rdst, -1);
6302 __ bind(not_zero);
6303 __ negl(Rdst);
6304 __ addl(Rdst, BitsPerLong - 1);
6305 %}
6306 ins_pipe(ialu_reg);
6307 %}
6308
6309 instruct countTrailingZerosI(eRegI dst, eRegI src, eFlagsReg cr) %{
6310 match(Set dst (CountTrailingZerosI src));
6311 effect(KILL cr);
6312
6313 format %{ "BSF $dst, $src\t# count trailing zeros (int)\n\t"
6314 "JNZ done\n\t"
6315 "MOV $dst, 32\n"
6316 "done:" %}
6317 ins_encode %{
6318 Register Rdst = $dst$$Register;
6319 Label done;
6320 __ bsfl(Rdst, $src$$Register);
6321 __ jccb(Assembler::notZero, done);
6322 __ movl(Rdst, BitsPerInt);
6323 __ bind(done);
6324 %}
6325 ins_pipe(ialu_reg);
6326 %}
6327
6328 instruct countTrailingZerosL(eRegI dst, eRegL src, eFlagsReg cr) %{
6329 match(Set dst (CountTrailingZerosL src));
6330 effect(TEMP dst, KILL cr);
6331
6332 format %{ "BSF $dst, $src.lo\t# count trailing zeros (long)\n\t"
6333 "JNZ done\n\t"
6334 "BSF $dst, $src.hi\n\t"
6335 "JNZ msw_not_zero\n\t"
6336 "MOV $dst, 32\n"
6337 "msw_not_zero:\n\t"
6338 "ADD $dst, 32\n"
6339 "done:" %}
6340 ins_encode %{
6341 Register Rdst = $dst$$Register;
6342 Register Rsrc = $src$$Register;
6343 Label msw_not_zero;
6344 Label done;
6345 __ bsfl(Rdst, Rsrc);
6346 __ jccb(Assembler::notZero, done);
6347 __ bsfl(Rdst, HIGH_FROM_LOW(Rsrc));
6348 __ jccb(Assembler::notZero, msw_not_zero);
6349 __ movl(Rdst, BitsPerInt);
6350 __ bind(msw_not_zero);
6351 __ addl(Rdst, BitsPerInt);
6352 __ bind(done);
6353 %}
6354 ins_pipe(ialu_reg);
6355 %}
6356
6357
6358 //---------- Population Count Instructions -------------------------------------
6359
6360 instruct popCountI(eRegI dst, eRegI src) %{
6361 predicate(UsePopCountInstruction);
6362 match(Set dst (PopCountI src));
6363
6364 format %{ "POPCNT $dst, $src" %}
6365 ins_encode %{
6366 __ popcntl($dst$$Register, $src$$Register);
6367 %}
6368 ins_pipe(ialu_reg);
6369 %}
6370
6371 instruct popCountI_mem(eRegI dst, memory mem) %{
6372 predicate(UsePopCountInstruction);
6373 match(Set dst (PopCountI (LoadI mem)));
6374
6375 format %{ "POPCNT $dst, $mem" %}
6376 ins_encode %{
6377 __ popcntl($dst$$Register, $mem$$Address);
6378 %}
6379 ins_pipe(ialu_reg);
6380 %}
6381
6382 // Note: Long.bitCount(long) returns an int.
6383 instruct popCountL(eRegI dst, eRegL src, eRegI tmp, eFlagsReg cr) %{
6384 predicate(UsePopCountInstruction);
6385 match(Set dst (PopCountL src));
6386 effect(KILL cr, TEMP tmp, TEMP dst);
6387
6388 format %{ "POPCNT $dst, $src.lo\n\t"
6389 "POPCNT $tmp, $src.hi\n\t"
6390 "ADD $dst, $tmp" %}
6391 ins_encode %{
6392 __ popcntl($dst$$Register, $src$$Register);
6393 __ popcntl($tmp$$Register, HIGH_FROM_LOW($src$$Register));
6394 __ addl($dst$$Register, $tmp$$Register);
6395 %}
6396 ins_pipe(ialu_reg);
6397 %}
6398
6399 // Note: Long.bitCount(long) returns an int.
6400 instruct popCountL_mem(eRegI dst, memory mem, eRegI tmp, eFlagsReg cr) %{
6401 predicate(UsePopCountInstruction);
6402 match(Set dst (PopCountL (LoadL mem)));
6403 effect(KILL cr, TEMP tmp, TEMP dst);
6404
6405 format %{ "POPCNT $dst, $mem\n\t"
6406 "POPCNT $tmp, $mem+4\n\t"
6407 "ADD $dst, $tmp" %}
6408 ins_encode %{
6409 //__ popcntl($dst$$Register, $mem$$Address$$first);
6410 //__ popcntl($tmp$$Register, $mem$$Address$$second);
6411 __ popcntl($dst$$Register, Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp, false));
6412 __ popcntl($tmp$$Register, Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp + 4, false));
6413 __ addl($dst$$Register, $tmp$$Register);
6414 %}
6415 ins_pipe(ialu_reg);
6416 %}
6417
6418
6419 //----------Load/Store/Move Instructions---------------------------------------
6420 //----------Load Instructions--------------------------------------------------
6421 // Load Byte (8bit signed)
6422 instruct loadB(xRegI dst, memory mem) %{
6423 match(Set dst (LoadB mem));
6424
6425 ins_cost(125);
6426 format %{ "MOVSX8 $dst,$mem\t# byte" %}
6427
6428 ins_encode %{
6429 __ movsbl($dst$$Register, $mem$$Address);
6430 %}
6431
6432 ins_pipe(ialu_reg_mem);
6433 %}
6434
6435 // Load Byte (8bit signed) into Long Register
6436 instruct loadB2L(eRegL dst, memory mem, eFlagsReg cr) %{
6437 match(Set dst (ConvI2L (LoadB mem)));
6438 effect(KILL cr);
6439
6440 ins_cost(375);
6441 format %{ "MOVSX8 $dst.lo,$mem\t# byte -> long\n\t"
6442 "MOV $dst.hi,$dst.lo\n\t"
6443 "SAR $dst.hi,7" %}
6444
6445 ins_encode %{
6446 __ movsbl($dst$$Register, $mem$$Address);
6447 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
6448 __ sarl(HIGH_FROM_LOW($dst$$Register), 7); // 24+1 MSB are already signed extended.
6449 %}
6450
6451 ins_pipe(ialu_reg_mem);
6452 %}
6453
6454 // Load Unsigned Byte (8bit UNsigned)
6455 instruct loadUB(xRegI dst, memory mem) %{
6456 match(Set dst (LoadUB mem));
6457
6458 ins_cost(125);
6459 format %{ "MOVZX8 $dst,$mem\t# ubyte -> int" %}
6460
6461 ins_encode %{
6462 __ movzbl($dst$$Register, $mem$$Address);
6463 %}
6464
6465 ins_pipe(ialu_reg_mem);
6466 %}
6467
6468 // Load Unsigned Byte (8 bit UNsigned) into Long Register
6469 instruct loadUB2L(eRegL dst, memory mem, eFlagsReg cr) %{
6470 match(Set dst (ConvI2L (LoadUB mem)));
6471 effect(KILL cr);
6472
6473 ins_cost(250);
6474 format %{ "MOVZX8 $dst.lo,$mem\t# ubyte -> long\n\t"
6475 "XOR $dst.hi,$dst.hi" %}
6476
6477 ins_encode %{
6478 Register Rdst = $dst$$Register;
6479 __ movzbl(Rdst, $mem$$Address);
6480 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6481 %}
6482
6483 ins_pipe(ialu_reg_mem);
6484 %}
6485
6486 // Load Unsigned Byte (8 bit UNsigned) with mask into Long Register
6487 instruct loadUB2L_immI8(eRegL dst, memory mem, immI8 mask, eFlagsReg cr) %{
6488 match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
6489 effect(KILL cr);
6490
6491 format %{ "MOVZX8 $dst.lo,$mem\t# ubyte & 8-bit mask -> long\n\t"
6492 "XOR $dst.hi,$dst.hi\n\t"
6493 "AND $dst.lo,$mask" %}
6494 ins_encode %{
6495 Register Rdst = $dst$$Register;
6496 __ movzbl(Rdst, $mem$$Address);
6497 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6498 __ andl(Rdst, $mask$$constant);
6499 %}
6500 ins_pipe(ialu_reg_mem);
6501 %}
6502
6503 // Load Short (16bit signed)
6504 instruct loadS(eRegI dst, memory mem) %{
6505 match(Set dst (LoadS mem));
6506
6507 ins_cost(125);
6508 format %{ "MOVSX $dst,$mem\t# short" %}
6509
6510 ins_encode %{
6511 __ movswl($dst$$Register, $mem$$Address);
6512 %}
6513
6514 ins_pipe(ialu_reg_mem);
6515 %}
6516
6517 // Load Short (16 bit signed) to Byte (8 bit signed)
6518 instruct loadS2B(eRegI dst, memory mem, immI_24 twentyfour) %{
6519 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
6520
6521 ins_cost(125);
6522 format %{ "MOVSX $dst, $mem\t# short -> byte" %}
6523 ins_encode %{
6524 __ movsbl($dst$$Register, $mem$$Address);
6525 %}
6526 ins_pipe(ialu_reg_mem);
6527 %}
6528
6529 // Load Short (16bit signed) into Long Register
6530 instruct loadS2L(eRegL dst, memory mem, eFlagsReg cr) %{
6531 match(Set dst (ConvI2L (LoadS mem)));
6532 effect(KILL cr);
6533
6534 ins_cost(375);
6535 format %{ "MOVSX $dst.lo,$mem\t# short -> long\n\t"
6536 "MOV $dst.hi,$dst.lo\n\t"
6537 "SAR $dst.hi,15" %}
6538
6539 ins_encode %{
6540 __ movswl($dst$$Register, $mem$$Address);
6541 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
6542 __ sarl(HIGH_FROM_LOW($dst$$Register), 15); // 16+1 MSB are already signed extended.
6543 %}
6544
6545 ins_pipe(ialu_reg_mem);
6546 %}
6547
6548 // Load Unsigned Short/Char (16bit unsigned)
6549 instruct loadUS(eRegI dst, memory mem) %{
6550 match(Set dst (LoadUS mem));
6551
6552 ins_cost(125);
6553 format %{ "MOVZX $dst,$mem\t# ushort/char -> int" %}
6554
6555 ins_encode %{
6556 __ movzwl($dst$$Register, $mem$$Address);
6557 %}
6558
6559 ins_pipe(ialu_reg_mem);
6560 %}
6561
6562 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
6563 instruct loadUS2B(eRegI dst, memory mem, immI_24 twentyfour) %{
6564 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
6565
6566 ins_cost(125);
6567 format %{ "MOVSX $dst, $mem\t# ushort -> byte" %}
6568 ins_encode %{
6569 __ movsbl($dst$$Register, $mem$$Address);
6570 %}
6571 ins_pipe(ialu_reg_mem);
6572 %}
6573
6574 // Load Unsigned Short/Char (16 bit UNsigned) into Long Register
6575 instruct loadUS2L(eRegL dst, memory mem, eFlagsReg cr) %{
6576 match(Set dst (ConvI2L (LoadUS mem)));
6577 effect(KILL cr);
6578
6579 ins_cost(250);
6580 format %{ "MOVZX $dst.lo,$mem\t# ushort/char -> long\n\t"
6581 "XOR $dst.hi,$dst.hi" %}
6582
6583 ins_encode %{
6584 __ movzwl($dst$$Register, $mem$$Address);
6585 __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register));
6586 %}
6587
6588 ins_pipe(ialu_reg_mem);
6589 %}
6590
6591 // Load Unsigned Short/Char (16 bit UNsigned) with mask 0xFF into Long Register
6592 instruct loadUS2L_immI_255(eRegL dst, memory mem, immI_255 mask, eFlagsReg cr) %{
6593 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
6594 effect(KILL cr);
6595
6596 format %{ "MOVZX8 $dst.lo,$mem\t# ushort/char & 0xFF -> long\n\t"
6597 "XOR $dst.hi,$dst.hi" %}
6598 ins_encode %{
6599 Register Rdst = $dst$$Register;
6600 __ movzbl(Rdst, $mem$$Address);
6601 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6602 %}
6603 ins_pipe(ialu_reg_mem);
6604 %}
6605
6606 // Load Unsigned Short/Char (16 bit UNsigned) with a 16-bit mask into Long Register
6607 instruct loadUS2L_immI16(eRegL dst, memory mem, immI16 mask, eFlagsReg cr) %{
6608 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
6609 effect(KILL cr);
6610
6611 format %{ "MOVZX $dst.lo, $mem\t# ushort/char & 16-bit mask -> long\n\t"
6612 "XOR $dst.hi,$dst.hi\n\t"
6613 "AND $dst.lo,$mask" %}
6614 ins_encode %{
6615 Register Rdst = $dst$$Register;
6616 __ movzwl(Rdst, $mem$$Address);
6617 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6618 __ andl(Rdst, $mask$$constant);
6619 %}
6620 ins_pipe(ialu_reg_mem);
6621 %}
6622
6623 // Load Integer
6624 instruct loadI(eRegI dst, memory mem) %{
6625 match(Set dst (LoadI mem));
6626
6627 ins_cost(125);
6628 format %{ "MOV $dst,$mem\t# int" %}
6629
6630 ins_encode %{
6631 __ movl($dst$$Register, $mem$$Address);
6632 %}
6633
6634 ins_pipe(ialu_reg_mem);
6635 %}
6636
6637 // Load Integer (32 bit signed) to Byte (8 bit signed)
6638 instruct loadI2B(eRegI dst, memory mem, immI_24 twentyfour) %{
6639 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
6640
6641 ins_cost(125);
6642 format %{ "MOVSX $dst, $mem\t# int -> byte" %}
6643 ins_encode %{
6644 __ movsbl($dst$$Register, $mem$$Address);
6645 %}
6646 ins_pipe(ialu_reg_mem);
6647 %}
6648
6649 // Load Integer (32 bit signed) to Unsigned Byte (8 bit UNsigned)
6650 instruct loadI2UB(eRegI dst, memory mem, immI_255 mask) %{
6651 match(Set dst (AndI (LoadI mem) mask));
6652
6653 ins_cost(125);
6654 format %{ "MOVZX $dst, $mem\t# int -> ubyte" %}
6655 ins_encode %{
6656 __ movzbl($dst$$Register, $mem$$Address);
6657 %}
6658 ins_pipe(ialu_reg_mem);
6659 %}
6660
6661 // Load Integer (32 bit signed) to Short (16 bit signed)
6662 instruct loadI2S(eRegI dst, memory mem, immI_16 sixteen) %{
6663 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
6664
6665 ins_cost(125);
6666 format %{ "MOVSX $dst, $mem\t# int -> short" %}
6667 ins_encode %{
6668 __ movswl($dst$$Register, $mem$$Address);
6669 %}
6670 ins_pipe(ialu_reg_mem);
6671 %}
6672
6673 // Load Integer (32 bit signed) to Unsigned Short/Char (16 bit UNsigned)
6674 instruct loadI2US(eRegI dst, memory mem, immI_65535 mask) %{
6675 match(Set dst (AndI (LoadI mem) mask));
6676
6677 ins_cost(125);
6678 format %{ "MOVZX $dst, $mem\t# int -> ushort/char" %}
6679 ins_encode %{
6680 __ movzwl($dst$$Register, $mem$$Address);
6681 %}
6682 ins_pipe(ialu_reg_mem);
6683 %}
6684
6685 // Load Integer into Long Register
6686 instruct loadI2L(eRegL dst, memory mem, eFlagsReg cr) %{
6687 match(Set dst (ConvI2L (LoadI mem)));
6688 effect(KILL cr);
6689
6690 ins_cost(375);
6691 format %{ "MOV $dst.lo,$mem\t# int -> long\n\t"
6692 "MOV $dst.hi,$dst.lo\n\t"
6693 "SAR $dst.hi,31" %}
6694
6695 ins_encode %{
6696 __ movl($dst$$Register, $mem$$Address);
6697 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
6698 __ sarl(HIGH_FROM_LOW($dst$$Register), 31);
6699 %}
6700
6701 ins_pipe(ialu_reg_mem);
6702 %}
6703
6704 // Load Integer with mask 0xFF into Long Register
6705 instruct loadI2L_immI_255(eRegL dst, memory mem, immI_255 mask, eFlagsReg cr) %{
6706 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
6707 effect(KILL cr);
6708
6709 format %{ "MOVZX8 $dst.lo,$mem\t# int & 0xFF -> long\n\t"
6710 "XOR $dst.hi,$dst.hi" %}
6711 ins_encode %{
6712 Register Rdst = $dst$$Register;
6713 __ movzbl(Rdst, $mem$$Address);
6714 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6715 %}
6716 ins_pipe(ialu_reg_mem);
6717 %}
6718
6719 // Load Integer with mask 0xFFFF into Long Register
6720 instruct loadI2L_immI_65535(eRegL dst, memory mem, immI_65535 mask, eFlagsReg cr) %{
6721 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
6722 effect(KILL cr);
6723
6724 format %{ "MOVZX $dst.lo,$mem\t# int & 0xFFFF -> long\n\t"
6725 "XOR $dst.hi,$dst.hi" %}
6726 ins_encode %{
6727 Register Rdst = $dst$$Register;
6728 __ movzwl(Rdst, $mem$$Address);
6729 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6730 %}
6731 ins_pipe(ialu_reg_mem);
6732 %}
6733
6734 // Load Integer with 32-bit mask into Long Register
6735 instruct loadI2L_immI(eRegL dst, memory mem, immI mask, eFlagsReg cr) %{
6736 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
6737 effect(KILL cr);
6738
6739 format %{ "MOV $dst.lo,$mem\t# int & 32-bit mask -> long\n\t"
6740 "XOR $dst.hi,$dst.hi\n\t"
6741 "AND $dst.lo,$mask" %}
6742 ins_encode %{
6743 Register Rdst = $dst$$Register;
6744 __ movl(Rdst, $mem$$Address);
6745 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6746 __ andl(Rdst, $mask$$constant);
6747 %}
6748 ins_pipe(ialu_reg_mem);
6749 %}
6750
6751 // Load Unsigned Integer into Long Register
6752 instruct loadUI2L(eRegL dst, memory mem, eFlagsReg cr) %{
6753 match(Set dst (LoadUI2L mem));
6754 effect(KILL cr);
6755
6756 ins_cost(250);
6757 format %{ "MOV $dst.lo,$mem\t# uint -> long\n\t"
6758 "XOR $dst.hi,$dst.hi" %}
6759
6760 ins_encode %{
6761 __ movl($dst$$Register, $mem$$Address);
6762 __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register));
6763 %}
6764
6765 ins_pipe(ialu_reg_mem);
6766 %}
6767
6768 // Load Long. Cannot clobber address while loading, so restrict address
6769 // register to ESI
6770 instruct loadL(eRegL dst, load_long_memory mem) %{
6771 predicate(!((LoadLNode*)n)->require_atomic_access());
6772 match(Set dst (LoadL mem));
6773
6774 ins_cost(250);
6775 format %{ "MOV $dst.lo,$mem\t# long\n\t"
6776 "MOV $dst.hi,$mem+4" %}
6777
6778 ins_encode %{
6779 Address Amemlo = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp, false);
6780 Address Amemhi = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp + 4, false);
6781 __ movl($dst$$Register, Amemlo);
6782 __ movl(HIGH_FROM_LOW($dst$$Register), Amemhi);
6783 %}
6784
6785 ins_pipe(ialu_reg_long_mem);
6786 %}
6787
6788 // Volatile Load Long. Must be atomic, so do 64-bit FILD
6789 // then store it down to the stack and reload on the int
6790 // side.
6791 instruct loadL_volatile(stackSlotL dst, memory mem) %{
6792 predicate(UseSSE<=1 && ((LoadLNode*)n)->require_atomic_access());
6793 match(Set dst (LoadL mem));
6794
6795 ins_cost(200);
6796 format %{ "FILD $mem\t# Atomic volatile long load\n\t"
6797 "FISTp $dst" %}
6798 ins_encode(enc_loadL_volatile(mem,dst));
6799 ins_pipe( fpu_reg_mem );
6800 %}
6801
6802 instruct loadLX_volatile(stackSlotL dst, memory mem, regXD tmp) %{
6803 predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access());
6804 match(Set dst (LoadL mem));
6805 effect(TEMP tmp);
6806 ins_cost(180);
6807 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
6808 "MOVSD $dst,$tmp" %}
6809 ins_encode(enc_loadLX_volatile(mem, dst, tmp));
6810 ins_pipe( pipe_slow );
6811 %}
6812
6813 instruct loadLX_reg_volatile(eRegL dst, memory mem, regXD tmp) %{
6814 predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access());
6815 match(Set dst (LoadL mem));
6816 effect(TEMP tmp);
6817 ins_cost(160);
6818 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
6819 "MOVD $dst.lo,$tmp\n\t"
6820 "PSRLQ $tmp,32\n\t"
6821 "MOVD $dst.hi,$tmp" %}
6822 ins_encode(enc_loadLX_reg_volatile(mem, dst, tmp));
6823 ins_pipe( pipe_slow );
6824 %}
6825
6826 // Load Range
6827 instruct loadRange(eRegI dst, memory mem) %{
6828 match(Set dst (LoadRange mem));
6829
6830 ins_cost(125);
6831 format %{ "MOV $dst,$mem" %}
6832 opcode(0x8B);
6833 ins_encode( OpcP, RegMem(dst,mem));
6834 ins_pipe( ialu_reg_mem );
6835 %}
6836
6837
6838 // Load Pointer
6839 instruct loadP(eRegP dst, memory mem) %{
6840 match(Set dst (LoadP mem));
6841
6842 ins_cost(125);
6843 format %{ "MOV $dst,$mem" %}
6844 opcode(0x8B);
6845 ins_encode( OpcP, RegMem(dst,mem));
6846 ins_pipe( ialu_reg_mem );
6847 %}
6848
6849 // Load Klass Pointer
6850 instruct loadKlass(eRegP dst, memory mem) %{
6851 match(Set dst (LoadKlass mem));
6852
6853 ins_cost(125);
6854 format %{ "MOV $dst,$mem" %}
6855 opcode(0x8B);
6856 ins_encode( OpcP, RegMem(dst,mem));
6857 ins_pipe( ialu_reg_mem );
6858 %}
6859
6860 // Load Double
6861 instruct loadD(regD dst, memory mem) %{
6862 predicate(UseSSE<=1);
6863 match(Set dst (LoadD mem));
6864
6865 ins_cost(150);
6866 format %{ "FLD_D ST,$mem\n\t"
6867 "FSTP $dst" %}
6868 opcode(0xDD); /* DD /0 */
6869 ins_encode( OpcP, RMopc_Mem(0x00,mem),
6870 Pop_Reg_D(dst) );
6871 ins_pipe( fpu_reg_mem );
6872 %}
6873
6874 // Load Double to XMM
6875 instruct loadXD(regXD dst, memory mem) %{
6876 predicate(UseSSE>=2 && UseXmmLoadAndClearUpper);
6877 match(Set dst (LoadD mem));
6878 ins_cost(145);
6879 format %{ "MOVSD $dst,$mem" %}
6880 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x10), RegMem(dst,mem));
6881 ins_pipe( pipe_slow );
6882 %}
6883
6884 instruct loadXD_partial(regXD dst, memory mem) %{
6885 predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper);
6886 match(Set dst (LoadD mem));
6887 ins_cost(145);
6888 format %{ "MOVLPD $dst,$mem" %}
6889 ins_encode( Opcode(0x66), Opcode(0x0F), Opcode(0x12), RegMem(dst,mem));
6890 ins_pipe( pipe_slow );
6891 %}
6892
6893 // Load to XMM register (single-precision floating point)
6894 // MOVSS instruction
6895 instruct loadX(regX dst, memory mem) %{
6896 predicate(UseSSE>=1);
6897 match(Set dst (LoadF mem));
6898 ins_cost(145);
6899 format %{ "MOVSS $dst,$mem" %}
6900 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x10), RegMem(dst,mem));
6901 ins_pipe( pipe_slow );
6902 %}
6903
6904 // Load Float
6905 instruct loadF(regF dst, memory mem) %{
6906 predicate(UseSSE==0);
6907 match(Set dst (LoadF mem));
6908
6909 ins_cost(150);
6910 format %{ "FLD_S ST,$mem\n\t"
6911 "FSTP $dst" %}
6912 opcode(0xD9); /* D9 /0 */
6913 ins_encode( OpcP, RMopc_Mem(0x00,mem),
6914 Pop_Reg_F(dst) );
6915 ins_pipe( fpu_reg_mem );
6916 %}
6917
6918 // Load Aligned Packed Byte to XMM register
6919 instruct loadA8B(regXD dst, memory mem) %{
6920 predicate(UseSSE>=1);
6921 match(Set dst (Load8B mem));
6922 ins_cost(125);
6923 format %{ "MOVQ $dst,$mem\t! packed8B" %}
6924 ins_encode( movq_ld(dst, mem));
6925 ins_pipe( pipe_slow );
6926 %}
6927
6928 // Load Aligned Packed Short to XMM register
6929 instruct loadA4S(regXD dst, memory mem) %{
6930 predicate(UseSSE>=1);
6931 match(Set dst (Load4S mem));
6932 ins_cost(125);
6933 format %{ "MOVQ $dst,$mem\t! packed4S" %}
6934 ins_encode( movq_ld(dst, mem));
6935 ins_pipe( pipe_slow );
6936 %}
6937
6938 // Load Aligned Packed Char to XMM register
6939 instruct loadA4C(regXD dst, memory mem) %{
6940 predicate(UseSSE>=1);
6941 match(Set dst (Load4C mem));
6942 ins_cost(125);
6943 format %{ "MOVQ $dst,$mem\t! packed4C" %}
6944 ins_encode( movq_ld(dst, mem));
6945 ins_pipe( pipe_slow );
6946 %}
6947
6948 // Load Aligned Packed Integer to XMM register
6949 instruct load2IU(regXD dst, memory mem) %{
6950 predicate(UseSSE>=1);
6951 match(Set dst (Load2I mem));
6952 ins_cost(125);
6953 format %{ "MOVQ $dst,$mem\t! packed2I" %}
6954 ins_encode( movq_ld(dst, mem));
6955 ins_pipe( pipe_slow );
6956 %}
6957
6958 // Load Aligned Packed Single to XMM
6959 instruct loadA2F(regXD dst, memory mem) %{
6960 predicate(UseSSE>=1);
6961 match(Set dst (Load2F mem));
6962 ins_cost(145);
6963 format %{ "MOVQ $dst,$mem\t! packed2F" %}
6964 ins_encode( movq_ld(dst, mem));
6965 ins_pipe( pipe_slow );
6966 %}
6967
6968 // Load Effective Address
6969 instruct leaP8(eRegP dst, indOffset8 mem) %{
6970 match(Set dst mem);
6971
6972 ins_cost(110);
6973 format %{ "LEA $dst,$mem" %}
6974 opcode(0x8D);
6975 ins_encode( OpcP, RegMem(dst,mem));
6976 ins_pipe( ialu_reg_reg_fat );
6977 %}
6978
6979 instruct leaP32(eRegP dst, indOffset32 mem) %{
6980 match(Set dst mem);
6981
6982 ins_cost(110);
6983 format %{ "LEA $dst,$mem" %}
6984 opcode(0x8D);
6985 ins_encode( OpcP, RegMem(dst,mem));
6986 ins_pipe( ialu_reg_reg_fat );
6987 %}
6988
6989 instruct leaPIdxOff(eRegP dst, indIndexOffset mem) %{
6990 match(Set dst mem);
6991
6992 ins_cost(110);
6993 format %{ "LEA $dst,$mem" %}
6994 opcode(0x8D);
6995 ins_encode( OpcP, RegMem(dst,mem));
6996 ins_pipe( ialu_reg_reg_fat );
6997 %}
6998
6999 instruct leaPIdxScale(eRegP dst, indIndexScale mem) %{
7000 match(Set dst mem);
7001
7002 ins_cost(110);
7003 format %{ "LEA $dst,$mem" %}
7004 opcode(0x8D);
7005 ins_encode( OpcP, RegMem(dst,mem));
7006 ins_pipe( ialu_reg_reg_fat );
7007 %}
7008
7009 instruct leaPIdxScaleOff(eRegP dst, indIndexScaleOffset mem) %{
7010 match(Set dst mem);
7011
7012 ins_cost(110);
7013 format %{ "LEA $dst,$mem" %}
7014 opcode(0x8D);
7015 ins_encode( OpcP, RegMem(dst,mem));
7016 ins_pipe( ialu_reg_reg_fat );
7017 %}
7018
7019 // Load Constant
7020 instruct loadConI(eRegI dst, immI src) %{
7021 match(Set dst src);
7022
7023 format %{ "MOV $dst,$src" %}
7024 ins_encode( LdImmI(dst, src) );
7025 ins_pipe( ialu_reg_fat );
7026 %}
7027
7028 // Load Constant zero
7029 instruct loadConI0(eRegI dst, immI0 src, eFlagsReg cr) %{
7030 match(Set dst src);
7031 effect(KILL cr);
7032
7033 ins_cost(50);
7034 format %{ "XOR $dst,$dst" %}
7035 opcode(0x33); /* + rd */
7036 ins_encode( OpcP, RegReg( dst, dst ) );
7037 ins_pipe( ialu_reg );
7038 %}
7039
7040 instruct loadConP(eRegP dst, immP src) %{
7041 match(Set dst src);
7042
7043 format %{ "MOV $dst,$src" %}
7044 opcode(0xB8); /* + rd */
7045 ins_encode( LdImmP(dst, src) );
7046 ins_pipe( ialu_reg_fat );
7047 %}
7048
7049 instruct loadConL(eRegL dst, immL src, eFlagsReg cr) %{
7050 match(Set dst src);
7051 effect(KILL cr);
7052 ins_cost(200);
7053 format %{ "MOV $dst.lo,$src.lo\n\t"
7054 "MOV $dst.hi,$src.hi" %}
7055 opcode(0xB8);
7056 ins_encode( LdImmL_Lo(dst, src), LdImmL_Hi(dst, src) );
7057 ins_pipe( ialu_reg_long_fat );
7058 %}
7059
7060 instruct loadConL0(eRegL dst, immL0 src, eFlagsReg cr) %{
7061 match(Set dst src);
7062 effect(KILL cr);
7063 ins_cost(150);
7064 format %{ "XOR $dst.lo,$dst.lo\n\t"
7065 "XOR $dst.hi,$dst.hi" %}
7066 opcode(0x33,0x33);
7067 ins_encode( RegReg_Lo(dst,dst), RegReg_Hi(dst, dst) );
7068 ins_pipe( ialu_reg_long );
7069 %}
7070
7071 // The instruction usage is guarded by predicate in operand immF().
7072 instruct loadConF(regF dst, immF src) %{
7073 match(Set dst src);
7074 ins_cost(125);
7075
7076 format %{ "FLD_S ST,$src\n\t"
7077 "FSTP $dst" %}
7078 opcode(0xD9, 0x00); /* D9 /0 */
7079 ins_encode(LdImmF(src), Pop_Reg_F(dst) );
7080 ins_pipe( fpu_reg_con );
7081 %}
7082
7083 // The instruction usage is guarded by predicate in operand immXF().
7084 instruct loadConX(regX dst, immXF con) %{
7085 match(Set dst con);
7086 ins_cost(125);
7087 format %{ "MOVSS $dst,[$con]" %}
7088 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x10), LdImmX(dst, con));
7089 ins_pipe( pipe_slow );
7090 %}
7091
7092 // The instruction usage is guarded by predicate in operand immXF0().
7093 instruct loadConX0(regX dst, immXF0 src) %{
7094 match(Set dst src);
7095 ins_cost(100);
7096 format %{ "XORPS $dst,$dst\t# float 0.0" %}
7097 ins_encode( Opcode(0x0F), Opcode(0x57), RegReg(dst,dst));
7098 ins_pipe( pipe_slow );
7099 %}
7100
7101 // The instruction usage is guarded by predicate in operand immD().
7102 instruct loadConD(regD dst, immD src) %{
7103 match(Set dst src);
7104 ins_cost(125);
7105
7106 format %{ "FLD_D ST,$src\n\t"
7107 "FSTP $dst" %}
7108 ins_encode(LdImmD(src), Pop_Reg_D(dst) );
7109 ins_pipe( fpu_reg_con );
7110 %}
7111
7112 // The instruction usage is guarded by predicate in operand immXD().
7113 instruct loadConXD(regXD dst, immXD con) %{
7114 match(Set dst con);
7115 ins_cost(125);
7116 format %{ "MOVSD $dst,[$con]" %}
7117 ins_encode(load_conXD(dst, con));
7118 ins_pipe( pipe_slow );
7119 %}
7120
7121 // The instruction usage is guarded by predicate in operand immXD0().
7122 instruct loadConXD0(regXD dst, immXD0 src) %{
7123 match(Set dst src);
7124 ins_cost(100);
7125 format %{ "XORPD $dst,$dst\t# double 0.0" %}
7126 ins_encode( Opcode(0x66), Opcode(0x0F), Opcode(0x57), RegReg(dst,dst));
7127 ins_pipe( pipe_slow );
7128 %}
7129
7130 // Load Stack Slot
7131 instruct loadSSI(eRegI dst, stackSlotI src) %{
7132 match(Set dst src);
7133 ins_cost(125);
7134
7135 format %{ "MOV $dst,$src" %}
7136 opcode(0x8B);
7137 ins_encode( OpcP, RegMem(dst,src));
7138 ins_pipe( ialu_reg_mem );
7139 %}
7140
7141 instruct loadSSL(eRegL dst, stackSlotL src) %{
7142 match(Set dst src);
7143
7144 ins_cost(200);
7145 format %{ "MOV $dst,$src.lo\n\t"
7146 "MOV $dst+4,$src.hi" %}
7147 opcode(0x8B, 0x8B);
7148 ins_encode( OpcP, RegMem( dst, src ), OpcS, RegMem_Hi( dst, src ) );
7149 ins_pipe( ialu_mem_long_reg );
7150 %}
7151
7152 // Load Stack Slot
7153 instruct loadSSP(eRegP dst, stackSlotP src) %{
7154 match(Set dst src);
7155 ins_cost(125);
7156
7157 format %{ "MOV $dst,$src" %}
7158 opcode(0x8B);
7159 ins_encode( OpcP, RegMem(dst,src));
7160 ins_pipe( ialu_reg_mem );
7161 %}
7162
7163 // Load Stack Slot
7164 instruct loadSSF(regF dst, stackSlotF src) %{
7165 match(Set dst src);
7166 ins_cost(125);
7167
7168 format %{ "FLD_S $src\n\t"
7169 "FSTP $dst" %}
7170 opcode(0xD9); /* D9 /0, FLD m32real */
7171 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
7172 Pop_Reg_F(dst) );
7173 ins_pipe( fpu_reg_mem );
7174 %}
7175
7176 // Load Stack Slot
7177 instruct loadSSD(regD dst, stackSlotD src) %{
7178 match(Set dst src);
7179 ins_cost(125);
7180
7181 format %{ "FLD_D $src\n\t"
7182 "FSTP $dst" %}
7183 opcode(0xDD); /* DD /0, FLD m64real */
7184 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
7185 Pop_Reg_D(dst) );
7186 ins_pipe( fpu_reg_mem );
7187 %}
7188
7189 // Prefetch instructions.
7190 // Must be safe to execute with invalid address (cannot fault).
7191
7192 instruct prefetchr0( memory mem ) %{
7193 predicate(UseSSE==0 && !VM_Version::supports_3dnow());
7194 match(PrefetchRead mem);
7195 ins_cost(0);
7196 size(0);
7197 format %{ "PREFETCHR (non-SSE is empty encoding)" %}
7198 ins_encode();
7199 ins_pipe(empty);
7200 %}
7201
7202 instruct prefetchr( memory mem ) %{
7203 predicate(UseSSE==0 && VM_Version::supports_3dnow() || ReadPrefetchInstr==3);
7204 match(PrefetchRead mem);
7205 ins_cost(100);
7206
7207 format %{ "PREFETCHR $mem\t! Prefetch into level 1 cache for read" %}
7208 opcode(0x0F, 0x0d); /* Opcode 0F 0d /0 */
7209 ins_encode(OpcP, OpcS, RMopc_Mem(0x00,mem));
7210 ins_pipe(ialu_mem);
7211 %}
7212
7213 instruct prefetchrNTA( memory mem ) %{
7214 predicate(UseSSE>=1 && ReadPrefetchInstr==0);
7215 match(PrefetchRead mem);
7216 ins_cost(100);
7217
7218 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for read" %}
7219 opcode(0x0F, 0x18); /* Opcode 0F 18 /0 */
7220 ins_encode(OpcP, OpcS, RMopc_Mem(0x00,mem));
7221 ins_pipe(ialu_mem);
7222 %}
7223
7224 instruct prefetchrT0( memory mem ) %{
7225 predicate(UseSSE>=1 && ReadPrefetchInstr==1);
7226 match(PrefetchRead mem);
7227 ins_cost(100);
7228
7229 format %{ "PREFETCHT0 $mem\t! Prefetch into L1 and L2 caches for read" %}
7230 opcode(0x0F, 0x18); /* Opcode 0F 18 /1 */
7231 ins_encode(OpcP, OpcS, RMopc_Mem(0x01,mem));
7232 ins_pipe(ialu_mem);
7233 %}
7234
7235 instruct prefetchrT2( memory mem ) %{
7236 predicate(UseSSE>=1 && ReadPrefetchInstr==2);
7237 match(PrefetchRead mem);
7238 ins_cost(100);
7239
7240 format %{ "PREFETCHT2 $mem\t! Prefetch into L2 cache for read" %}
7241 opcode(0x0F, 0x18); /* Opcode 0F 18 /3 */
7242 ins_encode(OpcP, OpcS, RMopc_Mem(0x03,mem));
7243 ins_pipe(ialu_mem);
7244 %}
7245
7246 instruct prefetchw0( memory mem ) %{
7247 predicate(UseSSE==0 && !VM_Version::supports_3dnow());
7248 match(PrefetchWrite mem);
7249 ins_cost(0);
7250 size(0);
7251 format %{ "Prefetch (non-SSE is empty encoding)" %}
7252 ins_encode();
7253 ins_pipe(empty);
7254 %}
7255
7256 instruct prefetchw( memory mem ) %{
7257 predicate(UseSSE==0 && VM_Version::supports_3dnow() || AllocatePrefetchInstr==3);
7258 match( PrefetchWrite mem );
7259 ins_cost(100);
7260
7261 format %{ "PREFETCHW $mem\t! Prefetch into L1 cache and mark modified" %}
7262 opcode(0x0F, 0x0D); /* Opcode 0F 0D /1 */
7263 ins_encode(OpcP, OpcS, RMopc_Mem(0x01,mem));
7264 ins_pipe(ialu_mem);
7265 %}
7266
7267 instruct prefetchwNTA( memory mem ) %{
7268 predicate(UseSSE>=1 && AllocatePrefetchInstr==0);
7269 match(PrefetchWrite mem);
7270 ins_cost(100);
7271
7272 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for write" %}
7273 opcode(0x0F, 0x18); /* Opcode 0F 18 /0 */
7274 ins_encode(OpcP, OpcS, RMopc_Mem(0x00,mem));
7275 ins_pipe(ialu_mem);
7276 %}
7277
7278 instruct prefetchwT0( memory mem ) %{
7279 predicate(UseSSE>=1 && AllocatePrefetchInstr==1);
7280 match(PrefetchWrite mem);
7281 ins_cost(100);
7282
7283 format %{ "PREFETCHT0 $mem\t! Prefetch into L1 and L2 caches for write" %}
7284 opcode(0x0F, 0x18); /* Opcode 0F 18 /1 */
7285 ins_encode(OpcP, OpcS, RMopc_Mem(0x01,mem));
7286 ins_pipe(ialu_mem);
7287 %}
7288
7289 instruct prefetchwT2( memory mem ) %{
7290 predicate(UseSSE>=1 && AllocatePrefetchInstr==2);
7291 match(PrefetchWrite mem);
7292 ins_cost(100);
7293
7294 format %{ "PREFETCHT2 $mem\t! Prefetch into L2 cache for write" %}
7295 opcode(0x0F, 0x18); /* Opcode 0F 18 /3 */
7296 ins_encode(OpcP, OpcS, RMopc_Mem(0x03,mem));
7297 ins_pipe(ialu_mem);
7298 %}
7299
7300 //----------Store Instructions-------------------------------------------------
7301
7302 // Store Byte
7303 instruct storeB(memory mem, xRegI src) %{
7304 match(Set mem (StoreB mem src));
7305
7306 ins_cost(125);
7307 format %{ "MOV8 $mem,$src" %}
7308 opcode(0x88);
7309 ins_encode( OpcP, RegMem( src, mem ) );
7310 ins_pipe( ialu_mem_reg );
7311 %}
7312
7313 // Store Char/Short
7314 instruct storeC(memory mem, eRegI src) %{
7315 match(Set mem (StoreC mem src));
7316
7317 ins_cost(125);
7318 format %{ "MOV16 $mem,$src" %}
7319 opcode(0x89, 0x66);
7320 ins_encode( OpcS, OpcP, RegMem( src, mem ) );
7321 ins_pipe( ialu_mem_reg );
7322 %}
7323
7324 // Store Integer
7325 instruct storeI(memory mem, eRegI src) %{
7326 match(Set mem (StoreI mem src));
7327
7328 ins_cost(125);
7329 format %{ "MOV $mem,$src" %}
7330 opcode(0x89);
7331 ins_encode( OpcP, RegMem( src, mem ) );
7332 ins_pipe( ialu_mem_reg );
7333 %}
7334
7335 // Store Long
7336 instruct storeL(long_memory mem, eRegL src) %{
7337 predicate(!((StoreLNode*)n)->require_atomic_access());
7338 match(Set mem (StoreL mem src));
7339
7340 ins_cost(200);
7341 format %{ "MOV $mem,$src.lo\n\t"
7342 "MOV $mem+4,$src.hi" %}
7343 opcode(0x89, 0x89);
7344 ins_encode( OpcP, RegMem( src, mem ), OpcS, RegMem_Hi( src, mem ) );
7345 ins_pipe( ialu_mem_long_reg );
7346 %}
7347
7348 // Store Long to Integer
7349 instruct storeL2I(memory mem, eRegL src) %{
7350 match(Set mem (StoreI mem (ConvL2I src)));
7351
7352 format %{ "MOV $mem,$src.lo\t# long -> int" %}
7353 ins_encode %{
7354 __ movl($mem$$Address, $src$$Register);
7355 %}
7356 ins_pipe(ialu_mem_reg);
7357 %}
7358
7359 // Volatile Store Long. Must be atomic, so move it into
7360 // the FP TOS and then do a 64-bit FIST. Has to probe the
7361 // target address before the store (for null-ptr checks)
7362 // so the memory operand is used twice in the encoding.
7363 instruct storeL_volatile(memory mem, stackSlotL src, eFlagsReg cr ) %{
7364 predicate(UseSSE<=1 && ((StoreLNode*)n)->require_atomic_access());
7365 match(Set mem (StoreL mem src));
7366 effect( KILL cr );
7367 ins_cost(400);
7368 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
7369 "FILD $src\n\t"
7370 "FISTp $mem\t # 64-bit atomic volatile long store" %}
7371 opcode(0x3B);
7372 ins_encode( OpcP, RegMem( EAX, mem ), enc_storeL_volatile(mem,src));
7373 ins_pipe( fpu_reg_mem );
7374 %}
7375
7376 instruct storeLX_volatile(memory mem, stackSlotL src, regXD tmp, eFlagsReg cr) %{
7377 predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access());
7378 match(Set mem (StoreL mem src));
7379 effect( TEMP tmp, KILL cr );
7380 ins_cost(380);
7381 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
7382 "MOVSD $tmp,$src\n\t"
7383 "MOVSD $mem,$tmp\t # 64-bit atomic volatile long store" %}
7384 opcode(0x3B);
7385 ins_encode( OpcP, RegMem( EAX, mem ), enc_storeLX_volatile(mem, src, tmp));
7386 ins_pipe( pipe_slow );
7387 %}
7388
7389 instruct storeLX_reg_volatile(memory mem, eRegL src, regXD tmp2, regXD tmp, eFlagsReg cr) %{
7390 predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access());
7391 match(Set mem (StoreL mem src));
7392 effect( TEMP tmp2 , TEMP tmp, KILL cr );
7393 ins_cost(360);
7394 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
7395 "MOVD $tmp,$src.lo\n\t"
7396 "MOVD $tmp2,$src.hi\n\t"
7397 "PUNPCKLDQ $tmp,$tmp2\n\t"
7398 "MOVSD $mem,$tmp\t # 64-bit atomic volatile long store" %}
7399 opcode(0x3B);
7400 ins_encode( OpcP, RegMem( EAX, mem ), enc_storeLX_reg_volatile(mem, src, tmp, tmp2));
7401 ins_pipe( pipe_slow );
7402 %}
7403
7404 // Store Pointer; for storing unknown oops and raw pointers
7405 instruct storeP(memory mem, anyRegP src) %{
7406 match(Set mem (StoreP mem src));
7407
7408 ins_cost(125);
7409 format %{ "MOV $mem,$src" %}
7410 opcode(0x89);
7411 ins_encode( OpcP, RegMem( src, mem ) );
7412 ins_pipe( ialu_mem_reg );
7413 %}
7414
7415 // Store Integer Immediate
7416 instruct storeImmI(memory mem, immI src) %{
7417 match(Set mem (StoreI mem src));
7418
7419 ins_cost(150);
7420 format %{ "MOV $mem,$src" %}
7421 opcode(0xC7); /* C7 /0 */
7422 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32( src ));
7423 ins_pipe( ialu_mem_imm );
7424 %}
7425
7426 // Store Short/Char Immediate
7427 instruct storeImmI16(memory mem, immI16 src) %{
7428 predicate(UseStoreImmI16);
7429 match(Set mem (StoreC mem src));
7430
7431 ins_cost(150);
7432 format %{ "MOV16 $mem,$src" %}
7433 opcode(0xC7); /* C7 /0 Same as 32 store immediate with prefix */
7434 ins_encode( SizePrefix, OpcP, RMopc_Mem(0x00,mem), Con16( src ));
7435 ins_pipe( ialu_mem_imm );
7436 %}
7437
7438 // Store Pointer Immediate; null pointers or constant oops that do not
7439 // need card-mark barriers.
7440 instruct storeImmP(memory mem, immP src) %{
7441 match(Set mem (StoreP mem src));
7442
7443 ins_cost(150);
7444 format %{ "MOV $mem,$src" %}
7445 opcode(0xC7); /* C7 /0 */
7446 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32( src ));
7447 ins_pipe( ialu_mem_imm );
7448 %}
7449
7450 // Store Byte Immediate
7451 instruct storeImmB(memory mem, immI8 src) %{
7452 match(Set mem (StoreB mem src));
7453
7454 ins_cost(150);
7455 format %{ "MOV8 $mem,$src" %}
7456 opcode(0xC6); /* C6 /0 */
7457 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con8or32( src ));
7458 ins_pipe( ialu_mem_imm );
7459 %}
7460
7461 // Store Aligned Packed Byte XMM register to memory
7462 instruct storeA8B(memory mem, regXD src) %{
7463 predicate(UseSSE>=1);
7464 match(Set mem (Store8B mem src));
7465 ins_cost(145);
7466 format %{ "MOVQ $mem,$src\t! packed8B" %}
7467 ins_encode( movq_st(mem, src));
7468 ins_pipe( pipe_slow );
7469 %}
7470
7471 // Store Aligned Packed Char/Short XMM register to memory
7472 instruct storeA4C(memory mem, regXD src) %{
7473 predicate(UseSSE>=1);
7474 match(Set mem (Store4C mem src));
7475 ins_cost(145);
7476 format %{ "MOVQ $mem,$src\t! packed4C" %}
7477 ins_encode( movq_st(mem, src));
7478 ins_pipe( pipe_slow );
7479 %}
7480
7481 // Store Aligned Packed Integer XMM register to memory
7482 instruct storeA2I(memory mem, regXD src) %{
7483 predicate(UseSSE>=1);
7484 match(Set mem (Store2I mem src));
7485 ins_cost(145);
7486 format %{ "MOVQ $mem,$src\t! packed2I" %}
7487 ins_encode( movq_st(mem, src));
7488 ins_pipe( pipe_slow );
7489 %}
7490
7491 // Store CMS card-mark Immediate
7492 instruct storeImmCM(memory mem, immI8 src) %{
7493 match(Set mem (StoreCM mem src));
7494
7495 ins_cost(150);
7496 format %{ "MOV8 $mem,$src\t! CMS card-mark imm0" %}
7497 opcode(0xC6); /* C6 /0 */
7498 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con8or32( src ));
7499 ins_pipe( ialu_mem_imm );
7500 %}
7501
7502 // Store Double
7503 instruct storeD( memory mem, regDPR1 src) %{
7504 predicate(UseSSE<=1);
7505 match(Set mem (StoreD mem src));
7506
7507 ins_cost(100);
7508 format %{ "FST_D $mem,$src" %}
7509 opcode(0xDD); /* DD /2 */
7510 ins_encode( enc_FP_store(mem,src) );
7511 ins_pipe( fpu_mem_reg );
7512 %}
7513
7514 // Store double does rounding on x86
7515 instruct storeD_rounded( memory mem, regDPR1 src) %{
7516 predicate(UseSSE<=1);
7517 match(Set mem (StoreD mem (RoundDouble src)));
7518
7519 ins_cost(100);
7520 format %{ "FST_D $mem,$src\t# round" %}
7521 opcode(0xDD); /* DD /2 */
7522 ins_encode( enc_FP_store(mem,src) );
7523 ins_pipe( fpu_mem_reg );
7524 %}
7525
7526 // Store XMM register to memory (double-precision floating points)
7527 // MOVSD instruction
7528 instruct storeXD(memory mem, regXD src) %{
7529 predicate(UseSSE>=2);
7530 match(Set mem (StoreD mem src));
7531 ins_cost(95);
7532 format %{ "MOVSD $mem,$src" %}
7533 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x11), RegMem(src, mem));
7534 ins_pipe( pipe_slow );
7535 %}
7536
7537 // Store XMM register to memory (single-precision floating point)
7538 // MOVSS instruction
7539 instruct storeX(memory mem, regX src) %{
7540 predicate(UseSSE>=1);
7541 match(Set mem (StoreF mem src));
7542 ins_cost(95);
7543 format %{ "MOVSS $mem,$src" %}
7544 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x11), RegMem(src, mem));
7545 ins_pipe( pipe_slow );
7546 %}
7547
7548 // Store Aligned Packed Single Float XMM register to memory
7549 instruct storeA2F(memory mem, regXD src) %{
7550 predicate(UseSSE>=1);
7551 match(Set mem (Store2F mem src));
7552 ins_cost(145);
7553 format %{ "MOVQ $mem,$src\t! packed2F" %}
7554 ins_encode( movq_st(mem, src));
7555 ins_pipe( pipe_slow );
7556 %}
7557
7558 // Store Float
7559 instruct storeF( memory mem, regFPR1 src) %{
7560 predicate(UseSSE==0);
7561 match(Set mem (StoreF mem src));
7562
7563 ins_cost(100);
7564 format %{ "FST_S $mem,$src" %}
7565 opcode(0xD9); /* D9 /2 */
7566 ins_encode( enc_FP_store(mem,src) );
7567 ins_pipe( fpu_mem_reg );
7568 %}
7569
7570 // Store Float does rounding on x86
7571 instruct storeF_rounded( memory mem, regFPR1 src) %{
7572 predicate(UseSSE==0);
7573 match(Set mem (StoreF mem (RoundFloat src)));
7574
7575 ins_cost(100);
7576 format %{ "FST_S $mem,$src\t# round" %}
7577 opcode(0xD9); /* D9 /2 */
7578 ins_encode( enc_FP_store(mem,src) );
7579 ins_pipe( fpu_mem_reg );
7580 %}
7581
7582 // Store Float does rounding on x86
7583 instruct storeF_Drounded( memory mem, regDPR1 src) %{
7584 predicate(UseSSE<=1);
7585 match(Set mem (StoreF mem (ConvD2F src)));
7586
7587 ins_cost(100);
7588 format %{ "FST_S $mem,$src\t# D-round" %}
7589 opcode(0xD9); /* D9 /2 */
7590 ins_encode( enc_FP_store(mem,src) );
7591 ins_pipe( fpu_mem_reg );
7592 %}
7593
7594 // Store immediate Float value (it is faster than store from FPU register)
7595 // The instruction usage is guarded by predicate in operand immF().
7596 instruct storeF_imm( memory mem, immF src) %{
7597 match(Set mem (StoreF mem src));
7598
7599 ins_cost(50);
7600 format %{ "MOV $mem,$src\t# store float" %}
7601 opcode(0xC7); /* C7 /0 */
7602 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32F_as_bits( src ));
7603 ins_pipe( ialu_mem_imm );
7604 %}
7605
7606 // Store immediate Float value (it is faster than store from XMM register)
7607 // The instruction usage is guarded by predicate in operand immXF().
7608 instruct storeX_imm( memory mem, immXF src) %{
7609 match(Set mem (StoreF mem src));
7610
7611 ins_cost(50);
7612 format %{ "MOV $mem,$src\t# store float" %}
7613 opcode(0xC7); /* C7 /0 */
7614 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32XF_as_bits( src ));
7615 ins_pipe( ialu_mem_imm );
7616 %}
7617
7618 // Store Integer to stack slot
7619 instruct storeSSI(stackSlotI dst, eRegI src) %{
7620 match(Set dst src);
7621
7622 ins_cost(100);
7623 format %{ "MOV $dst,$src" %}
7624 opcode(0x89);
7625 ins_encode( OpcPRegSS( dst, src ) );
7626 ins_pipe( ialu_mem_reg );
7627 %}
7628
7629 // Store Integer to stack slot
7630 instruct storeSSP(stackSlotP dst, eRegP src) %{
7631 match(Set dst src);
7632
7633 ins_cost(100);
7634 format %{ "MOV $dst,$src" %}
7635 opcode(0x89);
7636 ins_encode( OpcPRegSS( dst, src ) );
7637 ins_pipe( ialu_mem_reg );
7638 %}
7639
7640 // Store Long to stack slot
7641 instruct storeSSL(stackSlotL dst, eRegL src) %{
7642 match(Set dst src);
7643
7644 ins_cost(200);
7645 format %{ "MOV $dst,$src.lo\n\t"
7646 "MOV $dst+4,$src.hi" %}
7647 opcode(0x89, 0x89);
7648 ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) );
7649 ins_pipe( ialu_mem_long_reg );
7650 %}
7651
7652 //----------MemBar Instructions-----------------------------------------------
7653 // Memory barrier flavors
7654
7655 instruct membar_acquire() %{
7656 match(MemBarAcquire);
7657 ins_cost(400);
7658
7659 size(0);
7660 format %{ "MEMBAR-acquire ! (empty encoding)" %}
7661 ins_encode();
7662 ins_pipe(empty);
7663 %}
7664
7665 instruct membar_acquire_lock() %{
7666 match(MemBarAcquire);
7667 predicate(Matcher::prior_fast_lock(n));
7668 ins_cost(0);
7669
7670 size(0);
7671 format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)" %}
7672 ins_encode( );
7673 ins_pipe(empty);
7674 %}
7675
7676 instruct membar_release() %{
7677 match(MemBarRelease);
7678 ins_cost(400);
7679
7680 size(0);
7681 format %{ "MEMBAR-release ! (empty encoding)" %}
7682 ins_encode( );
7683 ins_pipe(empty);
7684 %}
7685
7686 instruct membar_release_lock() %{
7687 match(MemBarRelease);
7688 predicate(Matcher::post_fast_unlock(n));
7689 ins_cost(0);
7690
7691 size(0);
7692 format %{ "MEMBAR-release (a FastUnlock follows so empty encoding)" %}
7693 ins_encode( );
7694 ins_pipe(empty);
7695 %}
7696
7697 instruct membar_volatile(eFlagsReg cr) %{
7698 match(MemBarVolatile);
7699 effect(KILL cr);
7700 ins_cost(400);
7701
7702 format %{
7703 $$template
7704 if (os::is_MP()) {
7705 $$emit$$"LOCK ADDL [ESP + #0], 0\t! membar_volatile"
7706 } else {
7707 $$emit$$"MEMBAR-volatile ! (empty encoding)"
7708 }
7709 %}
7710 ins_encode %{
7711 __ membar(Assembler::StoreLoad);
7712 %}
7713 ins_pipe(pipe_slow);
7714 %}
7715
7716 instruct unnecessary_membar_volatile() %{
7717 match(MemBarVolatile);
7718 predicate(Matcher::post_store_load_barrier(n));
7719 ins_cost(0);
7720
7721 size(0);
7722 format %{ "MEMBAR-volatile (unnecessary so empty encoding)" %}
7723 ins_encode( );
7724 ins_pipe(empty);
7725 %}
7726
7727 //----------Move Instructions--------------------------------------------------
7728 instruct castX2P(eAXRegP dst, eAXRegI src) %{
7729 match(Set dst (CastX2P src));
7730 format %{ "# X2P $dst, $src" %}
7731 ins_encode( /*empty encoding*/ );
7732 ins_cost(0);
7733 ins_pipe(empty);
7734 %}
7735
7736 instruct castP2X(eRegI dst, eRegP src ) %{
7737 match(Set dst (CastP2X src));
7738 ins_cost(50);
7739 format %{ "MOV $dst, $src\t# CastP2X" %}
7740 ins_encode( enc_Copy( dst, src) );
7741 ins_pipe( ialu_reg_reg );
7742 %}
7743
7744 //----------Conditional Move---------------------------------------------------
7745 // Conditional move
7746 instruct cmovI_reg(eRegI dst, eRegI src, eFlagsReg cr, cmpOp cop ) %{
7747 predicate(VM_Version::supports_cmov() );
7748 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7749 ins_cost(200);
7750 format %{ "CMOV$cop $dst,$src" %}
7751 opcode(0x0F,0x40);
7752 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7753 ins_pipe( pipe_cmov_reg );
7754 %}
7755
7756 instruct cmovI_regU( cmpOpU cop, eFlagsRegU cr, eRegI dst, eRegI src ) %{
7757 predicate(VM_Version::supports_cmov() );
7758 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7759 ins_cost(200);
7760 format %{ "CMOV$cop $dst,$src" %}
7761 opcode(0x0F,0x40);
7762 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7763 ins_pipe( pipe_cmov_reg );
7764 %}
7765
7766 instruct cmovI_regUCF( cmpOpUCF cop, eFlagsRegUCF cr, eRegI dst, eRegI src ) %{
7767 predicate(VM_Version::supports_cmov() );
7768 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7769 ins_cost(200);
7770 expand %{
7771 cmovI_regU(cop, cr, dst, src);
7772 %}
7773 %}
7774
7775 // Conditional move
7776 instruct cmovI_mem(cmpOp cop, eFlagsReg cr, eRegI dst, memory src) %{
7777 predicate(VM_Version::supports_cmov() );
7778 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7779 ins_cost(250);
7780 format %{ "CMOV$cop $dst,$src" %}
7781 opcode(0x0F,0x40);
7782 ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7783 ins_pipe( pipe_cmov_mem );
7784 %}
7785
7786 // Conditional move
7787 instruct cmovI_memU(cmpOpU cop, eFlagsRegU cr, eRegI dst, memory src) %{
7788 predicate(VM_Version::supports_cmov() );
7789 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7790 ins_cost(250);
7791 format %{ "CMOV$cop $dst,$src" %}
7792 opcode(0x0F,0x40);
7793 ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7794 ins_pipe( pipe_cmov_mem );
7795 %}
7796
7797 instruct cmovI_memUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegI dst, memory src) %{
7798 predicate(VM_Version::supports_cmov() );
7799 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7800 ins_cost(250);
7801 expand %{
7802 cmovI_memU(cop, cr, dst, src);
7803 %}
7804 %}
7805
7806 // Conditional move
7807 instruct cmovP_reg(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{
7808 predicate(VM_Version::supports_cmov() );
7809 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7810 ins_cost(200);
7811 format %{ "CMOV$cop $dst,$src\t# ptr" %}
7812 opcode(0x0F,0x40);
7813 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7814 ins_pipe( pipe_cmov_reg );
7815 %}
7816
7817 // Conditional move (non-P6 version)
7818 // Note: a CMoveP is generated for stubs and native wrappers
7819 // regardless of whether we are on a P6, so we
7820 // emulate a cmov here
7821 instruct cmovP_reg_nonP6(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{
7822 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7823 ins_cost(300);
7824 format %{ "Jn$cop skip\n\t"
7825 "MOV $dst,$src\t# pointer\n"
7826 "skip:" %}
7827 opcode(0x8b);
7828 ins_encode( enc_cmov_branch(cop, 0x2), OpcP, RegReg(dst, src));
7829 ins_pipe( pipe_cmov_reg );
7830 %}
7831
7832 // Conditional move
7833 instruct cmovP_regU(cmpOpU cop, eFlagsRegU cr, eRegP dst, eRegP src ) %{
7834 predicate(VM_Version::supports_cmov() );
7835 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7836 ins_cost(200);
7837 format %{ "CMOV$cop $dst,$src\t# ptr" %}
7838 opcode(0x0F,0x40);
7839 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7840 ins_pipe( pipe_cmov_reg );
7841 %}
7842
7843 instruct cmovP_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegP dst, eRegP src ) %{
7844 predicate(VM_Version::supports_cmov() );
7845 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7846 ins_cost(200);
7847 expand %{
7848 cmovP_regU(cop, cr, dst, src);
7849 %}
7850 %}
7851
7852 // DISABLED: Requires the ADLC to emit a bottom_type call that
7853 // correctly meets the two pointer arguments; one is an incoming
7854 // register but the other is a memory operand. ALSO appears to
7855 // be buggy with implicit null checks.
7856 //
7857 //// Conditional move
7858 //instruct cmovP_mem(cmpOp cop, eFlagsReg cr, eRegP dst, memory src) %{
7859 // predicate(VM_Version::supports_cmov() );
7860 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
7861 // ins_cost(250);
7862 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
7863 // opcode(0x0F,0x40);
7864 // ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7865 // ins_pipe( pipe_cmov_mem );
7866 //%}
7867 //
7868 //// Conditional move
7869 //instruct cmovP_memU(cmpOpU cop, eFlagsRegU cr, eRegP dst, memory src) %{
7870 // predicate(VM_Version::supports_cmov() );
7871 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
7872 // ins_cost(250);
7873 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
7874 // opcode(0x0F,0x40);
7875 // ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7876 // ins_pipe( pipe_cmov_mem );
7877 //%}
7878
7879 // Conditional move
7880 instruct fcmovD_regU(cmpOp_fcmov cop, eFlagsRegU cr, regDPR1 dst, regD src) %{
7881 predicate(UseSSE<=1);
7882 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7883 ins_cost(200);
7884 format %{ "FCMOV$cop $dst,$src\t# double" %}
7885 opcode(0xDA);
7886 ins_encode( enc_cmov_d(cop,src) );
7887 ins_pipe( pipe_cmovD_reg );
7888 %}
7889
7890 // Conditional move
7891 instruct fcmovF_regU(cmpOp_fcmov cop, eFlagsRegU cr, regFPR1 dst, regF src) %{
7892 predicate(UseSSE==0);
7893 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7894 ins_cost(200);
7895 format %{ "FCMOV$cop $dst,$src\t# float" %}
7896 opcode(0xDA);
7897 ins_encode( enc_cmov_d(cop,src) );
7898 ins_pipe( pipe_cmovD_reg );
7899 %}
7900
7901 // Float CMOV on Intel doesn't handle *signed* compares, only unsigned.
7902 instruct fcmovD_regS(cmpOp cop, eFlagsReg cr, regD dst, regD src) %{
7903 predicate(UseSSE<=1);
7904 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7905 ins_cost(200);
7906 format %{ "Jn$cop skip\n\t"
7907 "MOV $dst,$src\t# double\n"
7908 "skip:" %}
7909 opcode (0xdd, 0x3); /* DD D8+i or DD /3 */
7910 ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_D(src), OpcP, RegOpc(dst) );
7911 ins_pipe( pipe_cmovD_reg );
7912 %}
7913
7914 // Float CMOV on Intel doesn't handle *signed* compares, only unsigned.
7915 instruct fcmovF_regS(cmpOp cop, eFlagsReg cr, regF dst, regF src) %{
7916 predicate(UseSSE==0);
7917 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7918 ins_cost(200);
7919 format %{ "Jn$cop skip\n\t"
7920 "MOV $dst,$src\t# float\n"
7921 "skip:" %}
7922 opcode (0xdd, 0x3); /* DD D8+i or DD /3 */
7923 ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_F(src), OpcP, RegOpc(dst) );
7924 ins_pipe( pipe_cmovD_reg );
7925 %}
7926
7927 // No CMOVE with SSE/SSE2
7928 instruct fcmovX_regS(cmpOp cop, eFlagsReg cr, regX dst, regX src) %{
7929 predicate (UseSSE>=1);
7930 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7931 ins_cost(200);
7932 format %{ "Jn$cop skip\n\t"
7933 "MOVSS $dst,$src\t# float\n"
7934 "skip:" %}
7935 ins_encode %{
7936 Label skip;
7937 // Invert sense of branch from sense of CMOV
7938 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
7939 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
7940 __ bind(skip);
7941 %}
7942 ins_pipe( pipe_slow );
7943 %}
7944
7945 // No CMOVE with SSE/SSE2
7946 instruct fcmovXD_regS(cmpOp cop, eFlagsReg cr, regXD dst, regXD src) %{
7947 predicate (UseSSE>=2);
7948 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7949 ins_cost(200);
7950 format %{ "Jn$cop skip\n\t"
7951 "MOVSD $dst,$src\t# float\n"
7952 "skip:" %}
7953 ins_encode %{
7954 Label skip;
7955 // Invert sense of branch from sense of CMOV
7956 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
7957 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
7958 __ bind(skip);
7959 %}
7960 ins_pipe( pipe_slow );
7961 %}
7962
7963 // unsigned version
7964 instruct fcmovX_regU(cmpOpU cop, eFlagsRegU cr, regX dst, regX src) %{
7965 predicate (UseSSE>=1);
7966 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7967 ins_cost(200);
7968 format %{ "Jn$cop skip\n\t"
7969 "MOVSS $dst,$src\t# float\n"
7970 "skip:" %}
7971 ins_encode %{
7972 Label skip;
7973 // Invert sense of branch from sense of CMOV
7974 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
7975 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
7976 __ bind(skip);
7977 %}
7978 ins_pipe( pipe_slow );
7979 %}
7980
7981 instruct fcmovX_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, regX dst, regX src) %{
7982 predicate (UseSSE>=1);
7983 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7984 ins_cost(200);
7985 expand %{
7986 fcmovX_regU(cop, cr, dst, src);
7987 %}
7988 %}
7989
7990 // unsigned version
7991 instruct fcmovXD_regU(cmpOpU cop, eFlagsRegU cr, regXD dst, regXD src) %{
7992 predicate (UseSSE>=2);
7993 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7994 ins_cost(200);
7995 format %{ "Jn$cop skip\n\t"
7996 "MOVSD $dst,$src\t# float\n"
7997 "skip:" %}
7998 ins_encode %{
7999 Label skip;
8000 // Invert sense of branch from sense of CMOV
8001 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
8002 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
8003 __ bind(skip);
8004 %}
8005 ins_pipe( pipe_slow );
8006 %}
8007
8008 instruct fcmovXD_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, regXD dst, regXD src) %{
8009 predicate (UseSSE>=2);
8010 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
8011 ins_cost(200);
8012 expand %{
8013 fcmovXD_regU(cop, cr, dst, src);
8014 %}
8015 %}
8016
8017 instruct cmovL_reg(cmpOp cop, eFlagsReg cr, eRegL dst, eRegL src) %{
8018 predicate(VM_Version::supports_cmov() );
8019 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
8020 ins_cost(200);
8021 format %{ "CMOV$cop $dst.lo,$src.lo\n\t"
8022 "CMOV$cop $dst.hi,$src.hi" %}
8023 opcode(0x0F,0x40);
8024 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) );
8025 ins_pipe( pipe_cmov_reg_long );
8026 %}
8027
8028 instruct cmovL_regU(cmpOpU cop, eFlagsRegU cr, eRegL dst, eRegL src) %{
8029 predicate(VM_Version::supports_cmov() );
8030 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
8031 ins_cost(200);
8032 format %{ "CMOV$cop $dst.lo,$src.lo\n\t"
8033 "CMOV$cop $dst.hi,$src.hi" %}
8034 opcode(0x0F,0x40);
8035 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) );
8036 ins_pipe( pipe_cmov_reg_long );
8037 %}
8038
8039 instruct cmovL_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegL dst, eRegL src) %{
8040 predicate(VM_Version::supports_cmov() );
8041 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
8042 ins_cost(200);
8043 expand %{
8044 cmovL_regU(cop, cr, dst, src);
8045 %}
8046 %}
8047
8048 //----------Arithmetic Instructions--------------------------------------------
8049 //----------Addition Instructions----------------------------------------------
8050 // Integer Addition Instructions
8051 instruct addI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
8052 match(Set dst (AddI dst src));
8053 effect(KILL cr);
8054
8055 size(2);
8056 format %{ "ADD $dst,$src" %}
8057 opcode(0x03);
8058 ins_encode( OpcP, RegReg( dst, src) );
8059 ins_pipe( ialu_reg_reg );
8060 %}
8061
8062 instruct addI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{
8063 match(Set dst (AddI dst src));
8064 effect(KILL cr);
8065
8066 format %{ "ADD $dst,$src" %}
8067 opcode(0x81, 0x00); /* /0 id */
8068 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8069 ins_pipe( ialu_reg );
8070 %}
8071
8072 instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
8073 predicate(UseIncDec);
8074 match(Set dst (AddI dst src));
8075 effect(KILL cr);
8076
8077 size(1);
8078 format %{ "INC $dst" %}
8079 opcode(0x40); /* */
8080 ins_encode( Opc_plus( primary, dst ) );
8081 ins_pipe( ialu_reg );
8082 %}
8083
8084 instruct leaI_eReg_immI(eRegI dst, eRegI src0, immI src1) %{
8085 match(Set dst (AddI src0 src1));
8086 ins_cost(110);
8087
8088 format %{ "LEA $dst,[$src0 + $src1]" %}
8089 opcode(0x8D); /* 0x8D /r */
8090 ins_encode( OpcP, RegLea( dst, src0, src1 ) );
8091 ins_pipe( ialu_reg_reg );
8092 %}
8093
8094 instruct leaP_eReg_immI(eRegP dst, eRegP src0, immI src1) %{
8095 match(Set dst (AddP src0 src1));
8096 ins_cost(110);
8097
8098 format %{ "LEA $dst,[$src0 + $src1]\t# ptr" %}
8099 opcode(0x8D); /* 0x8D /r */
8100 ins_encode( OpcP, RegLea( dst, src0, src1 ) );
8101 ins_pipe( ialu_reg_reg );
8102 %}
8103
8104 instruct decI_eReg(eRegI dst, immI_M1 src, eFlagsReg cr) %{
8105 predicate(UseIncDec);
8106 match(Set dst (AddI dst src));
8107 effect(KILL cr);
8108
8109 size(1);
8110 format %{ "DEC $dst" %}
8111 opcode(0x48); /* */
8112 ins_encode( Opc_plus( primary, dst ) );
8113 ins_pipe( ialu_reg );
8114 %}
8115
8116 instruct addP_eReg(eRegP dst, eRegI src, eFlagsReg cr) %{
8117 match(Set dst (AddP dst src));
8118 effect(KILL cr);
8119
8120 size(2);
8121 format %{ "ADD $dst,$src" %}
8122 opcode(0x03);
8123 ins_encode( OpcP, RegReg( dst, src) );
8124 ins_pipe( ialu_reg_reg );
8125 %}
8126
8127 instruct addP_eReg_imm(eRegP dst, immI src, eFlagsReg cr) %{
8128 match(Set dst (AddP dst src));
8129 effect(KILL cr);
8130
8131 format %{ "ADD $dst,$src" %}
8132 opcode(0x81,0x00); /* Opcode 81 /0 id */
8133 // ins_encode( RegImm( dst, src) );
8134 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8135 ins_pipe( ialu_reg );
8136 %}
8137
8138 instruct addI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{
8139 match(Set dst (AddI dst (LoadI src)));
8140 effect(KILL cr);
8141
8142 ins_cost(125);
8143 format %{ "ADD $dst,$src" %}
8144 opcode(0x03);
8145 ins_encode( OpcP, RegMem( dst, src) );
8146 ins_pipe( ialu_reg_mem );
8147 %}
8148
8149 instruct addI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{
8150 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
8151 effect(KILL cr);
8152
8153 ins_cost(150);
8154 format %{ "ADD $dst,$src" %}
8155 opcode(0x01); /* Opcode 01 /r */
8156 ins_encode( OpcP, RegMem( src, dst ) );
8157 ins_pipe( ialu_mem_reg );
8158 %}
8159
8160 // Add Memory with Immediate
8161 instruct addI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
8162 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
8163 effect(KILL cr);
8164
8165 ins_cost(125);
8166 format %{ "ADD $dst,$src" %}
8167 opcode(0x81); /* Opcode 81 /0 id */
8168 ins_encode( OpcSE( src ), RMopc_Mem(0x00,dst), Con8or32( src ) );
8169 ins_pipe( ialu_mem_imm );
8170 %}
8171
8172 instruct incI_mem(memory dst, immI1 src, eFlagsReg cr) %{
8173 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
8174 effect(KILL cr);
8175
8176 ins_cost(125);
8177 format %{ "INC $dst" %}
8178 opcode(0xFF); /* Opcode FF /0 */
8179 ins_encode( OpcP, RMopc_Mem(0x00,dst));
8180 ins_pipe( ialu_mem_imm );
8181 %}
8182
8183 instruct decI_mem(memory dst, immI_M1 src, eFlagsReg cr) %{
8184 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
8185 effect(KILL cr);
8186
8187 ins_cost(125);
8188 format %{ "DEC $dst" %}
8189 opcode(0xFF); /* Opcode FF /1 */
8190 ins_encode( OpcP, RMopc_Mem(0x01,dst));
8191 ins_pipe( ialu_mem_imm );
8192 %}
8193
8194
8195 instruct checkCastPP( eRegP dst ) %{
8196 match(Set dst (CheckCastPP dst));
8197
8198 size(0);
8199 format %{ "#checkcastPP of $dst" %}
8200 ins_encode( /*empty encoding*/ );
8201 ins_pipe( empty );
8202 %}
8203
8204 instruct castPP( eRegP dst ) %{
8205 match(Set dst (CastPP dst));
8206 format %{ "#castPP of $dst" %}
8207 ins_encode( /*empty encoding*/ );
8208 ins_pipe( empty );
8209 %}
8210
8211 instruct castII( eRegI dst ) %{
8212 match(Set dst (CastII dst));
8213 format %{ "#castII of $dst" %}
8214 ins_encode( /*empty encoding*/ );
8215 ins_cost(0);
8216 ins_pipe( empty );
8217 %}
8218
8219
8220 // Load-locked - same as a regular pointer load when used with compare-swap
8221 instruct loadPLocked(eRegP dst, memory mem) %{
8222 match(Set dst (LoadPLocked mem));
8223
8224 ins_cost(125);
8225 format %{ "MOV $dst,$mem\t# Load ptr. locked" %}
8226 opcode(0x8B);
8227 ins_encode( OpcP, RegMem(dst,mem));
8228 ins_pipe( ialu_reg_mem );
8229 %}
8230
8231 // LoadLong-locked - same as a volatile long load when used with compare-swap
8232 instruct loadLLocked(stackSlotL dst, load_long_memory mem) %{
8233 predicate(UseSSE<=1);
8234 match(Set dst (LoadLLocked mem));
8235
8236 ins_cost(200);
8237 format %{ "FILD $mem\t# Atomic volatile long load\n\t"
8238 "FISTp $dst" %}
8239 ins_encode(enc_loadL_volatile(mem,dst));
8240 ins_pipe( fpu_reg_mem );
8241 %}
8242
8243 instruct loadLX_Locked(stackSlotL dst, load_long_memory mem, regXD tmp) %{
8244 predicate(UseSSE>=2);
8245 match(Set dst (LoadLLocked mem));
8246 effect(TEMP tmp);
8247 ins_cost(180);
8248 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
8249 "MOVSD $dst,$tmp" %}
8250 ins_encode(enc_loadLX_volatile(mem, dst, tmp));
8251 ins_pipe( pipe_slow );
8252 %}
8253
8254 instruct loadLX_reg_Locked(eRegL dst, load_long_memory mem, regXD tmp) %{
8255 predicate(UseSSE>=2);
8256 match(Set dst (LoadLLocked mem));
8257 effect(TEMP tmp);
8258 ins_cost(160);
8259 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
8260 "MOVD $dst.lo,$tmp\n\t"
8261 "PSRLQ $tmp,32\n\t"
8262 "MOVD $dst.hi,$tmp" %}
8263 ins_encode(enc_loadLX_reg_volatile(mem, dst, tmp));
8264 ins_pipe( pipe_slow );
8265 %}
8266
8267 // Conditional-store of the updated heap-top.
8268 // Used during allocation of the shared heap.
8269 // Sets flags (EQ) on success. Implemented with a CMPXCHG on Intel.
8270 instruct storePConditional( memory heap_top_ptr, eAXRegP oldval, eRegP newval, eFlagsReg cr ) %{
8271 match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval)));
8272 // EAX is killed if there is contention, but then it's also unused.
8273 // In the common case of no contention, EAX holds the new oop address.
8274 format %{ "CMPXCHG $heap_top_ptr,$newval\t# If EAX==$heap_top_ptr Then store $newval into $heap_top_ptr" %}
8275 ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval,heap_top_ptr) );
8276 ins_pipe( pipe_cmpxchg );
8277 %}
8278
8279 // Conditional-store of an int value.
8280 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG on Intel.
8281 instruct storeIConditional( memory mem, eAXRegI oldval, eRegI newval, eFlagsReg cr ) %{
8282 match(Set cr (StoreIConditional mem (Binary oldval newval)));
8283 effect(KILL oldval);
8284 format %{ "CMPXCHG $mem,$newval\t# If EAX==$mem Then store $newval into $mem" %}
8285 ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval, mem) );
8286 ins_pipe( pipe_cmpxchg );
8287 %}
8288
8289 // Conditional-store of a long value.
8290 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG8 on Intel.
8291 instruct storeLConditional( memory mem, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{
8292 match(Set cr (StoreLConditional mem (Binary oldval newval)));
8293 effect(KILL oldval);
8294 format %{ "XCHG EBX,ECX\t# correct order for CMPXCHG8 instruction\n\t"
8295 "CMPXCHG8 $mem,ECX:EBX\t# If EDX:EAX==$mem Then store ECX:EBX into $mem\n\t"
8296 "XCHG EBX,ECX"
8297 %}
8298 ins_encode %{
8299 // Note: we need to swap rbx, and rcx before and after the
8300 // cmpxchg8 instruction because the instruction uses
8301 // rcx as the high order word of the new value to store but
8302 // our register encoding uses rbx.
8303 __ xchgl(as_Register(EBX_enc), as_Register(ECX_enc));
8304 if( os::is_MP() )
8305 __ lock();
8306 __ cmpxchg8($mem$$Address);
8307 __ xchgl(as_Register(EBX_enc), as_Register(ECX_enc));
8308 %}
8309 ins_pipe( pipe_cmpxchg );
8310 %}
8311
8312 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
8313
8314 instruct compareAndSwapL( eRegI res, eSIRegP mem_ptr, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{
8315 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
8316 effect(KILL cr, KILL oldval);
8317 format %{ "CMPXCHG8 [$mem_ptr],$newval\t# If EDX:EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
8318 "MOV $res,0\n\t"
8319 "JNE,s fail\n\t"
8320 "MOV $res,1\n"
8321 "fail:" %}
8322 ins_encode( enc_cmpxchg8(mem_ptr),
8323 enc_flags_ne_to_boolean(res) );
8324 ins_pipe( pipe_cmpxchg );
8325 %}
8326
8327 instruct compareAndSwapP( eRegI res, pRegP mem_ptr, eAXRegP oldval, eCXRegP newval, eFlagsReg cr) %{
8328 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
8329 effect(KILL cr, KILL oldval);
8330 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
8331 "MOV $res,0\n\t"
8332 "JNE,s fail\n\t"
8333 "MOV $res,1\n"
8334 "fail:" %}
8335 ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) );
8336 ins_pipe( pipe_cmpxchg );
8337 %}
8338
8339 instruct compareAndSwapI( eRegI res, pRegP mem_ptr, eAXRegI oldval, eCXRegI newval, eFlagsReg cr) %{
8340 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
8341 effect(KILL cr, KILL oldval);
8342 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
8343 "MOV $res,0\n\t"
8344 "JNE,s fail\n\t"
8345 "MOV $res,1\n"
8346 "fail:" %}
8347 ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) );
8348 ins_pipe( pipe_cmpxchg );
8349 %}
8350
8351 //----------Subtraction Instructions-------------------------------------------
8352 // Integer Subtraction Instructions
8353 instruct subI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
8354 match(Set dst (SubI dst src));
8355 effect(KILL cr);
8356
8357 size(2);
8358 format %{ "SUB $dst,$src" %}
8359 opcode(0x2B);
8360 ins_encode( OpcP, RegReg( dst, src) );
8361 ins_pipe( ialu_reg_reg );
8362 %}
8363
8364 instruct subI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{
8365 match(Set dst (SubI dst src));
8366 effect(KILL cr);
8367
8368 format %{ "SUB $dst,$src" %}
8369 opcode(0x81,0x05); /* Opcode 81 /5 */
8370 // ins_encode( RegImm( dst, src) );
8371 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8372 ins_pipe( ialu_reg );
8373 %}
8374
8375 instruct subI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{
8376 match(Set dst (SubI dst (LoadI src)));
8377 effect(KILL cr);
8378
8379 ins_cost(125);
8380 format %{ "SUB $dst,$src" %}
8381 opcode(0x2B);
8382 ins_encode( OpcP, RegMem( dst, src) );
8383 ins_pipe( ialu_reg_mem );
8384 %}
8385
8386 instruct subI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{
8387 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
8388 effect(KILL cr);
8389
8390 ins_cost(150);
8391 format %{ "SUB $dst,$src" %}
8392 opcode(0x29); /* Opcode 29 /r */
8393 ins_encode( OpcP, RegMem( src, dst ) );
8394 ins_pipe( ialu_mem_reg );
8395 %}
8396
8397 // Subtract from a pointer
8398 instruct subP_eReg(eRegP dst, eRegI src, immI0 zero, eFlagsReg cr) %{
8399 match(Set dst (AddP dst (SubI zero src)));
8400 effect(KILL cr);
8401
8402 size(2);
8403 format %{ "SUB $dst,$src" %}
8404 opcode(0x2B);
8405 ins_encode( OpcP, RegReg( dst, src) );
8406 ins_pipe( ialu_reg_reg );
8407 %}
8408
8409 instruct negI_eReg(eRegI dst, immI0 zero, eFlagsReg cr) %{
8410 match(Set dst (SubI zero dst));
8411 effect(KILL cr);
8412
8413 size(2);
8414 format %{ "NEG $dst" %}
8415 opcode(0xF7,0x03); // Opcode F7 /3
8416 ins_encode( OpcP, RegOpc( dst ) );
8417 ins_pipe( ialu_reg );
8418 %}
8419
8420
8421 //----------Multiplication/Division Instructions-------------------------------
8422 // Integer Multiplication Instructions
8423 // Multiply Register
8424 instruct mulI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
8425 match(Set dst (MulI dst src));
8426 effect(KILL cr);
8427
8428 size(3);
8429 ins_cost(300);
8430 format %{ "IMUL $dst,$src" %}
8431 opcode(0xAF, 0x0F);
8432 ins_encode( OpcS, OpcP, RegReg( dst, src) );
8433 ins_pipe( ialu_reg_reg_alu0 );
8434 %}
8435
8436 // Multiply 32-bit Immediate
8437 instruct mulI_eReg_imm(eRegI dst, eRegI src, immI imm, eFlagsReg cr) %{
8438 match(Set dst (MulI src imm));
8439 effect(KILL cr);
8440
8441 ins_cost(300);
8442 format %{ "IMUL $dst,$src,$imm" %}
8443 opcode(0x69); /* 69 /r id */
8444 ins_encode( OpcSE(imm), RegReg( dst, src ), Con8or32( imm ) );
8445 ins_pipe( ialu_reg_reg_alu0 );
8446 %}
8447
8448 instruct loadConL_low_only(eADXRegL_low_only dst, immL32 src, eFlagsReg cr) %{
8449 match(Set dst src);
8450 effect(KILL cr);
8451
8452 // Note that this is artificially increased to make it more expensive than loadConL
8453 ins_cost(250);
8454 format %{ "MOV EAX,$src\t// low word only" %}
8455 opcode(0xB8);
8456 ins_encode( LdImmL_Lo(dst, src) );
8457 ins_pipe( ialu_reg_fat );
8458 %}
8459
8460 // Multiply by 32-bit Immediate, taking the shifted high order results
8461 // (special case for shift by 32)
8462 instruct mulI_imm_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32 cnt, eFlagsReg cr) %{
8463 match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt)));
8464 predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL &&
8465 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint &&
8466 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint );
8467 effect(USE src1, KILL cr);
8468
8469 // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only
8470 ins_cost(0*100 + 1*400 - 150);
8471 format %{ "IMUL EDX:EAX,$src1" %}
8472 ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) );
8473 ins_pipe( pipe_slow );
8474 %}
8475
8476 // Multiply by 32-bit Immediate, taking the shifted high order results
8477 instruct mulI_imm_RShift_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr) %{
8478 match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt)));
8479 predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL &&
8480 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint &&
8481 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint );
8482 effect(USE src1, KILL cr);
8483
8484 // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only
8485 ins_cost(1*100 + 1*400 - 150);
8486 format %{ "IMUL EDX:EAX,$src1\n\t"
8487 "SAR EDX,$cnt-32" %}
8488 ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) );
8489 ins_pipe( pipe_slow );
8490 %}
8491
8492 // Multiply Memory 32-bit Immediate
8493 instruct mulI_mem_imm(eRegI dst, memory src, immI imm, eFlagsReg cr) %{
8494 match(Set dst (MulI (LoadI src) imm));
8495 effect(KILL cr);
8496
8497 ins_cost(300);
8498 format %{ "IMUL $dst,$src,$imm" %}
8499 opcode(0x69); /* 69 /r id */
8500 ins_encode( OpcSE(imm), RegMem( dst, src ), Con8or32( imm ) );
8501 ins_pipe( ialu_reg_mem_alu0 );
8502 %}
8503
8504 // Multiply Memory
8505 instruct mulI(eRegI dst, memory src, eFlagsReg cr) %{
8506 match(Set dst (MulI dst (LoadI src)));
8507 effect(KILL cr);
8508
8509 ins_cost(350);
8510 format %{ "IMUL $dst,$src" %}
8511 opcode(0xAF, 0x0F);
8512 ins_encode( OpcS, OpcP, RegMem( dst, src) );
8513 ins_pipe( ialu_reg_mem_alu0 );
8514 %}
8515
8516 // Multiply Register Int to Long
8517 instruct mulI2L(eADXRegL dst, eAXRegI src, nadxRegI src1, eFlagsReg flags) %{
8518 // Basic Idea: long = (long)int * (long)int
8519 match(Set dst (MulL (ConvI2L src) (ConvI2L src1)));
8520 effect(DEF dst, USE src, USE src1, KILL flags);
8521
8522 ins_cost(300);
8523 format %{ "IMUL $dst,$src1" %}
8524
8525 ins_encode( long_int_multiply( dst, src1 ) );
8526 ins_pipe( ialu_reg_reg_alu0 );
8527 %}
8528
8529 instruct mulIS_eReg(eADXRegL dst, immL_32bits mask, eFlagsReg flags, eAXRegI src, nadxRegI src1) %{
8530 // Basic Idea: long = (int & 0xffffffffL) * (int & 0xffffffffL)
8531 match(Set dst (MulL (AndL (ConvI2L src) mask) (AndL (ConvI2L src1) mask)));
8532 effect(KILL flags);
8533
8534 ins_cost(300);
8535 format %{ "MUL $dst,$src1" %}
8536
8537 ins_encode( long_uint_multiply(dst, src1) );
8538 ins_pipe( ialu_reg_reg_alu0 );
8539 %}
8540
8541 // Multiply Register Long
8542 instruct mulL_eReg(eADXRegL dst, eRegL src, eRegI tmp, eFlagsReg cr) %{
8543 match(Set dst (MulL dst src));
8544 effect(KILL cr, TEMP tmp);
8545 ins_cost(4*100+3*400);
8546 // Basic idea: lo(result) = lo(x_lo * y_lo)
8547 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
8548 format %{ "MOV $tmp,$src.lo\n\t"
8549 "IMUL $tmp,EDX\n\t"
8550 "MOV EDX,$src.hi\n\t"
8551 "IMUL EDX,EAX\n\t"
8552 "ADD $tmp,EDX\n\t"
8553 "MUL EDX:EAX,$src.lo\n\t"
8554 "ADD EDX,$tmp" %}
8555 ins_encode( long_multiply( dst, src, tmp ) );
8556 ins_pipe( pipe_slow );
8557 %}
8558
8559 // Multiply Register Long by small constant
8560 instruct mulL_eReg_con(eADXRegL dst, immL_127 src, eRegI tmp, eFlagsReg cr) %{
8561 match(Set dst (MulL dst src));
8562 effect(KILL cr, TEMP tmp);
8563 ins_cost(2*100+2*400);
8564 size(12);
8565 // Basic idea: lo(result) = lo(src * EAX)
8566 // hi(result) = hi(src * EAX) + lo(src * EDX)
8567 format %{ "IMUL $tmp,EDX,$src\n\t"
8568 "MOV EDX,$src\n\t"
8569 "MUL EDX\t# EDX*EAX -> EDX:EAX\n\t"
8570 "ADD EDX,$tmp" %}
8571 ins_encode( long_multiply_con( dst, src, tmp ) );
8572 ins_pipe( pipe_slow );
8573 %}
8574
8575 // Integer DIV with Register
8576 instruct divI_eReg(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{
8577 match(Set rax (DivI rax div));
8578 effect(KILL rdx, KILL cr);
8579 size(26);
8580 ins_cost(30*100+10*100);
8581 format %{ "CMP EAX,0x80000000\n\t"
8582 "JNE,s normal\n\t"
8583 "XOR EDX,EDX\n\t"
8584 "CMP ECX,-1\n\t"
8585 "JE,s done\n"
8586 "normal: CDQ\n\t"
8587 "IDIV $div\n\t"
8588 "done:" %}
8589 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8590 ins_encode( cdq_enc, OpcP, RegOpc(div) );
8591 ins_pipe( ialu_reg_reg_alu0 );
8592 %}
8593
8594 // Divide Register Long
8595 instruct divL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{
8596 match(Set dst (DivL src1 src2));
8597 effect( KILL cr, KILL cx, KILL bx );
8598 ins_cost(10000);
8599 format %{ "PUSH $src1.hi\n\t"
8600 "PUSH $src1.lo\n\t"
8601 "PUSH $src2.hi\n\t"
8602 "PUSH $src2.lo\n\t"
8603 "CALL SharedRuntime::ldiv\n\t"
8604 "ADD ESP,16" %}
8605 ins_encode( long_div(src1,src2) );
8606 ins_pipe( pipe_slow );
8607 %}
8608
8609 // Integer DIVMOD with Register, both quotient and mod results
8610 instruct divModI_eReg_divmod(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{
8611 match(DivModI rax div);
8612 effect(KILL cr);
8613 size(26);
8614 ins_cost(30*100+10*100);
8615 format %{ "CMP EAX,0x80000000\n\t"
8616 "JNE,s normal\n\t"
8617 "XOR EDX,EDX\n\t"
8618 "CMP ECX,-1\n\t"
8619 "JE,s done\n"
8620 "normal: CDQ\n\t"
8621 "IDIV $div\n\t"
8622 "done:" %}
8623 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8624 ins_encode( cdq_enc, OpcP, RegOpc(div) );
8625 ins_pipe( pipe_slow );
8626 %}
8627
8628 // Integer MOD with Register
8629 instruct modI_eReg(eDXRegI rdx, eAXRegI rax, eCXRegI div, eFlagsReg cr) %{
8630 match(Set rdx (ModI rax div));
8631 effect(KILL rax, KILL cr);
8632
8633 size(26);
8634 ins_cost(300);
8635 format %{ "CDQ\n\t"
8636 "IDIV $div" %}
8637 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8638 ins_encode( cdq_enc, OpcP, RegOpc(div) );
8639 ins_pipe( ialu_reg_reg_alu0 );
8640 %}
8641
8642 // Remainder Register Long
8643 instruct modL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{
8644 match(Set dst (ModL src1 src2));
8645 effect( KILL cr, KILL cx, KILL bx );
8646 ins_cost(10000);
8647 format %{ "PUSH $src1.hi\n\t"
8648 "PUSH $src1.lo\n\t"
8649 "PUSH $src2.hi\n\t"
8650 "PUSH $src2.lo\n\t"
8651 "CALL SharedRuntime::lrem\n\t"
8652 "ADD ESP,16" %}
8653 ins_encode( long_mod(src1,src2) );
8654 ins_pipe( pipe_slow );
8655 %}
8656
8657 // Integer Shift Instructions
8658 // Shift Left by one
8659 instruct shlI_eReg_1(eRegI dst, immI1 shift, eFlagsReg cr) %{
8660 match(Set dst (LShiftI dst shift));
8661 effect(KILL cr);
8662
8663 size(2);
8664 format %{ "SHL $dst,$shift" %}
8665 opcode(0xD1, 0x4); /* D1 /4 */
8666 ins_encode( OpcP, RegOpc( dst ) );
8667 ins_pipe( ialu_reg );
8668 %}
8669
8670 // Shift Left by 8-bit immediate
8671 instruct salI_eReg_imm(eRegI dst, immI8 shift, eFlagsReg cr) %{
8672 match(Set dst (LShiftI dst shift));
8673 effect(KILL cr);
8674
8675 size(3);
8676 format %{ "SHL $dst,$shift" %}
8677 opcode(0xC1, 0x4); /* C1 /4 ib */
8678 ins_encode( RegOpcImm( dst, shift) );
8679 ins_pipe( ialu_reg );
8680 %}
8681
8682 // Shift Left by variable
8683 instruct salI_eReg_CL(eRegI dst, eCXRegI shift, eFlagsReg cr) %{
8684 match(Set dst (LShiftI dst shift));
8685 effect(KILL cr);
8686
8687 size(2);
8688 format %{ "SHL $dst,$shift" %}
8689 opcode(0xD3, 0x4); /* D3 /4 */
8690 ins_encode( OpcP, RegOpc( dst ) );
8691 ins_pipe( ialu_reg_reg );
8692 %}
8693
8694 // Arithmetic shift right by one
8695 instruct sarI_eReg_1(eRegI dst, immI1 shift, eFlagsReg cr) %{
8696 match(Set dst (RShiftI dst shift));
8697 effect(KILL cr);
8698
8699 size(2);
8700 format %{ "SAR $dst,$shift" %}
8701 opcode(0xD1, 0x7); /* D1 /7 */
8702 ins_encode( OpcP, RegOpc( dst ) );
8703 ins_pipe( ialu_reg );
8704 %}
8705
8706 // Arithmetic shift right by one
8707 instruct sarI_mem_1(memory dst, immI1 shift, eFlagsReg cr) %{
8708 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8709 effect(KILL cr);
8710 format %{ "SAR $dst,$shift" %}
8711 opcode(0xD1, 0x7); /* D1 /7 */
8712 ins_encode( OpcP, RMopc_Mem(secondary,dst) );
8713 ins_pipe( ialu_mem_imm );
8714 %}
8715
8716 // Arithmetic Shift Right by 8-bit immediate
8717 instruct sarI_eReg_imm(eRegI dst, immI8 shift, eFlagsReg cr) %{
8718 match(Set dst (RShiftI dst shift));
8719 effect(KILL cr);
8720
8721 size(3);
8722 format %{ "SAR $dst,$shift" %}
8723 opcode(0xC1, 0x7); /* C1 /7 ib */
8724 ins_encode( RegOpcImm( dst, shift ) );
8725 ins_pipe( ialu_mem_imm );
8726 %}
8727
8728 // Arithmetic Shift Right by 8-bit immediate
8729 instruct sarI_mem_imm(memory dst, immI8 shift, eFlagsReg cr) %{
8730 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8731 effect(KILL cr);
8732
8733 format %{ "SAR $dst,$shift" %}
8734 opcode(0xC1, 0x7); /* C1 /7 ib */
8735 ins_encode( OpcP, RMopc_Mem(secondary, dst ), Con8or32( shift ) );
8736 ins_pipe( ialu_mem_imm );
8737 %}
8738
8739 // Arithmetic Shift Right by variable
8740 instruct sarI_eReg_CL(eRegI dst, eCXRegI shift, eFlagsReg cr) %{
8741 match(Set dst (RShiftI dst shift));
8742 effect(KILL cr);
8743
8744 size(2);
8745 format %{ "SAR $dst,$shift" %}
8746 opcode(0xD3, 0x7); /* D3 /7 */
8747 ins_encode( OpcP, RegOpc( dst ) );
8748 ins_pipe( ialu_reg_reg );
8749 %}
8750
8751 // Logical shift right by one
8752 instruct shrI_eReg_1(eRegI dst, immI1 shift, eFlagsReg cr) %{
8753 match(Set dst (URShiftI dst shift));
8754 effect(KILL cr);
8755
8756 size(2);
8757 format %{ "SHR $dst,$shift" %}
8758 opcode(0xD1, 0x5); /* D1 /5 */
8759 ins_encode( OpcP, RegOpc( dst ) );
8760 ins_pipe( ialu_reg );
8761 %}
8762
8763 // Logical Shift Right by 8-bit immediate
8764 instruct shrI_eReg_imm(eRegI dst, immI8 shift, eFlagsReg cr) %{
8765 match(Set dst (URShiftI dst shift));
8766 effect(KILL cr);
8767
8768 size(3);
8769 format %{ "SHR $dst,$shift" %}
8770 opcode(0xC1, 0x5); /* C1 /5 ib */
8771 ins_encode( RegOpcImm( dst, shift) );
8772 ins_pipe( ialu_reg );
8773 %}
8774
8775
8776 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24.
8777 // This idiom is used by the compiler for the i2b bytecode.
8778 instruct i2b(eRegI dst, xRegI src, immI_24 twentyfour) %{
8779 match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour));
8780
8781 size(3);
8782 format %{ "MOVSX $dst,$src :8" %}
8783 ins_encode %{
8784 __ movsbl($dst$$Register, $src$$Register);
8785 %}
8786 ins_pipe(ialu_reg_reg);
8787 %}
8788
8789 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16.
8790 // This idiom is used by the compiler the i2s bytecode.
8791 instruct i2s(eRegI dst, xRegI src, immI_16 sixteen) %{
8792 match(Set dst (RShiftI (LShiftI src sixteen) sixteen));
8793
8794 size(3);
8795 format %{ "MOVSX $dst,$src :16" %}
8796 ins_encode %{
8797 __ movswl($dst$$Register, $src$$Register);
8798 %}
8799 ins_pipe(ialu_reg_reg);
8800 %}
8801
8802
8803 // Logical Shift Right by variable
8804 instruct shrI_eReg_CL(eRegI dst, eCXRegI shift, eFlagsReg cr) %{
8805 match(Set dst (URShiftI dst shift));
8806 effect(KILL cr);
8807
8808 size(2);
8809 format %{ "SHR $dst,$shift" %}
8810 opcode(0xD3, 0x5); /* D3 /5 */
8811 ins_encode( OpcP, RegOpc( dst ) );
8812 ins_pipe( ialu_reg_reg );
8813 %}
8814
8815
8816 //----------Logical Instructions-----------------------------------------------
8817 //----------Integer Logical Instructions---------------------------------------
8818 // And Instructions
8819 // And Register with Register
8820 instruct andI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
8821 match(Set dst (AndI dst src));
8822 effect(KILL cr);
8823
8824 size(2);
8825 format %{ "AND $dst,$src" %}
8826 opcode(0x23);
8827 ins_encode( OpcP, RegReg( dst, src) );
8828 ins_pipe( ialu_reg_reg );
8829 %}
8830
8831 // And Register with Immediate
8832 instruct andI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{
8833 match(Set dst (AndI dst src));
8834 effect(KILL cr);
8835
8836 format %{ "AND $dst,$src" %}
8837 opcode(0x81,0x04); /* Opcode 81 /4 */
8838 // ins_encode( RegImm( dst, src) );
8839 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8840 ins_pipe( ialu_reg );
8841 %}
8842
8843 // And Register with Memory
8844 instruct andI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{
8845 match(Set dst (AndI dst (LoadI src)));
8846 effect(KILL cr);
8847
8848 ins_cost(125);
8849 format %{ "AND $dst,$src" %}
8850 opcode(0x23);
8851 ins_encode( OpcP, RegMem( dst, src) );
8852 ins_pipe( ialu_reg_mem );
8853 %}
8854
8855 // And Memory with Register
8856 instruct andI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{
8857 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
8858 effect(KILL cr);
8859
8860 ins_cost(150);
8861 format %{ "AND $dst,$src" %}
8862 opcode(0x21); /* Opcode 21 /r */
8863 ins_encode( OpcP, RegMem( src, dst ) );
8864 ins_pipe( ialu_mem_reg );
8865 %}
8866
8867 // And Memory with Immediate
8868 instruct andI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
8869 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
8870 effect(KILL cr);
8871
8872 ins_cost(125);
8873 format %{ "AND $dst,$src" %}
8874 opcode(0x81, 0x4); /* Opcode 81 /4 id */
8875 // ins_encode( MemImm( dst, src) );
8876 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
8877 ins_pipe( ialu_mem_imm );
8878 %}
8879
8880 // Or Instructions
8881 // Or Register with Register
8882 instruct orI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
8883 match(Set dst (OrI dst src));
8884 effect(KILL cr);
8885
8886 size(2);
8887 format %{ "OR $dst,$src" %}
8888 opcode(0x0B);
8889 ins_encode( OpcP, RegReg( dst, src) );
8890 ins_pipe( ialu_reg_reg );
8891 %}
8892
8893 instruct orI_eReg_castP2X(eRegI dst, eRegP src, eFlagsReg cr) %{
8894 match(Set dst (OrI dst (CastP2X src)));
8895 effect(KILL cr);
8896
8897 size(2);
8898 format %{ "OR $dst,$src" %}
8899 opcode(0x0B);
8900 ins_encode( OpcP, RegReg( dst, src) );
8901 ins_pipe( ialu_reg_reg );
8902 %}
8903
8904
8905 // Or Register with Immediate
8906 instruct orI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{
8907 match(Set dst (OrI dst src));
8908 effect(KILL cr);
8909
8910 format %{ "OR $dst,$src" %}
8911 opcode(0x81,0x01); /* Opcode 81 /1 id */
8912 // ins_encode( RegImm( dst, src) );
8913 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8914 ins_pipe( ialu_reg );
8915 %}
8916
8917 // Or Register with Memory
8918 instruct orI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{
8919 match(Set dst (OrI dst (LoadI src)));
8920 effect(KILL cr);
8921
8922 ins_cost(125);
8923 format %{ "OR $dst,$src" %}
8924 opcode(0x0B);
8925 ins_encode( OpcP, RegMem( dst, src) );
8926 ins_pipe( ialu_reg_mem );
8927 %}
8928
8929 // Or Memory with Register
8930 instruct orI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{
8931 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
8932 effect(KILL cr);
8933
8934 ins_cost(150);
8935 format %{ "OR $dst,$src" %}
8936 opcode(0x09); /* Opcode 09 /r */
8937 ins_encode( OpcP, RegMem( src, dst ) );
8938 ins_pipe( ialu_mem_reg );
8939 %}
8940
8941 // Or Memory with Immediate
8942 instruct orI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
8943 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
8944 effect(KILL cr);
8945
8946 ins_cost(125);
8947 format %{ "OR $dst,$src" %}
8948 opcode(0x81,0x1); /* Opcode 81 /1 id */
8949 // ins_encode( MemImm( dst, src) );
8950 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
8951 ins_pipe( ialu_mem_imm );
8952 %}
8953
8954 // ROL/ROR
8955 // ROL expand
8956 instruct rolI_eReg_imm1(eRegI dst, immI1 shift, eFlagsReg cr) %{
8957 effect(USE_DEF dst, USE shift, KILL cr);
8958
8959 format %{ "ROL $dst, $shift" %}
8960 opcode(0xD1, 0x0); /* Opcode D1 /0 */
8961 ins_encode( OpcP, RegOpc( dst ));
8962 ins_pipe( ialu_reg );
8963 %}
8964
8965 instruct rolI_eReg_imm8(eRegI dst, immI8 shift, eFlagsReg cr) %{
8966 effect(USE_DEF dst, USE shift, KILL cr);
8967
8968 format %{ "ROL $dst, $shift" %}
8969 opcode(0xC1, 0x0); /*Opcode /C1 /0 */
8970 ins_encode( RegOpcImm(dst, shift) );
8971 ins_pipe(ialu_reg);
8972 %}
8973
8974 instruct rolI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr) %{
8975 effect(USE_DEF dst, USE shift, KILL cr);
8976
8977 format %{ "ROL $dst, $shift" %}
8978 opcode(0xD3, 0x0); /* Opcode D3 /0 */
8979 ins_encode(OpcP, RegOpc(dst));
8980 ins_pipe( ialu_reg_reg );
8981 %}
8982 // end of ROL expand
8983
8984 // ROL 32bit by one once
8985 instruct rolI_eReg_i1(eRegI dst, immI1 lshift, immI_M1 rshift, eFlagsReg cr) %{
8986 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift)));
8987
8988 expand %{
8989 rolI_eReg_imm1(dst, lshift, cr);
8990 %}
8991 %}
8992
8993 // ROL 32bit var by imm8 once
8994 instruct rolI_eReg_i8(eRegI dst, immI8 lshift, immI8 rshift, eFlagsReg cr) %{
8995 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8996 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift)));
8997
8998 expand %{
8999 rolI_eReg_imm8(dst, lshift, cr);
9000 %}
9001 %}
9002
9003 // ROL 32bit var by var once
9004 instruct rolI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{
9005 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI zero shift))));
9006
9007 expand %{
9008 rolI_eReg_CL(dst, shift, cr);
9009 %}
9010 %}
9011
9012 // ROL 32bit var by var once
9013 instruct rolI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{
9014 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI c32 shift))));
9015
9016 expand %{
9017 rolI_eReg_CL(dst, shift, cr);
9018 %}
9019 %}
9020
9021 // ROR expand
9022 instruct rorI_eReg_imm1(eRegI dst, immI1 shift, eFlagsReg cr) %{
9023 effect(USE_DEF dst, USE shift, KILL cr);
9024
9025 format %{ "ROR $dst, $shift" %}
9026 opcode(0xD1,0x1); /* Opcode D1 /1 */
9027 ins_encode( OpcP, RegOpc( dst ) );
9028 ins_pipe( ialu_reg );
9029 %}
9030
9031 instruct rorI_eReg_imm8(eRegI dst, immI8 shift, eFlagsReg cr) %{
9032 effect (USE_DEF dst, USE shift, KILL cr);
9033
9034 format %{ "ROR $dst, $shift" %}
9035 opcode(0xC1, 0x1); /* Opcode /C1 /1 ib */
9036 ins_encode( RegOpcImm(dst, shift) );
9037 ins_pipe( ialu_reg );
9038 %}
9039
9040 instruct rorI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr)%{
9041 effect(USE_DEF dst, USE shift, KILL cr);
9042
9043 format %{ "ROR $dst, $shift" %}
9044 opcode(0xD3, 0x1); /* Opcode D3 /1 */
9045 ins_encode(OpcP, RegOpc(dst));
9046 ins_pipe( ialu_reg_reg );
9047 %}
9048 // end of ROR expand
9049
9050 // ROR right once
9051 instruct rorI_eReg_i1(eRegI dst, immI1 rshift, immI_M1 lshift, eFlagsReg cr) %{
9052 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift)));
9053
9054 expand %{
9055 rorI_eReg_imm1(dst, rshift, cr);
9056 %}
9057 %}
9058
9059 // ROR 32bit by immI8 once
9060 instruct rorI_eReg_i8(eRegI dst, immI8 rshift, immI8 lshift, eFlagsReg cr) %{
9061 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
9062 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift)));
9063
9064 expand %{
9065 rorI_eReg_imm8(dst, rshift, cr);
9066 %}
9067 %}
9068
9069 // ROR 32bit var by var once
9070 instruct rorI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{
9071 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI zero shift))));
9072
9073 expand %{
9074 rorI_eReg_CL(dst, shift, cr);
9075 %}
9076 %}
9077
9078 // ROR 32bit var by var once
9079 instruct rorI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{
9080 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI c32 shift))));
9081
9082 expand %{
9083 rorI_eReg_CL(dst, shift, cr);
9084 %}
9085 %}
9086
9087 // Xor Instructions
9088 // Xor Register with Register
9089 instruct xorI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
9090 match(Set dst (XorI dst src));
9091 effect(KILL cr);
9092
9093 size(2);
9094 format %{ "XOR $dst,$src" %}
9095 opcode(0x33);
9096 ins_encode( OpcP, RegReg( dst, src) );
9097 ins_pipe( ialu_reg_reg );
9098 %}
9099
9100 // Xor Register with Immediate -1
9101 instruct xorI_eReg_im1(eRegI dst, immI_M1 imm) %{
9102 match(Set dst (XorI dst imm));
9103
9104 size(2);
9105 format %{ "NOT $dst" %}
9106 ins_encode %{
9107 __ notl($dst$$Register);
9108 %}
9109 ins_pipe( ialu_reg );
9110 %}
9111
9112 // Xor Register with Immediate
9113 instruct xorI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{
9114 match(Set dst (XorI dst src));
9115 effect(KILL cr);
9116
9117 format %{ "XOR $dst,$src" %}
9118 opcode(0x81,0x06); /* Opcode 81 /6 id */
9119 // ins_encode( RegImm( dst, src) );
9120 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
9121 ins_pipe( ialu_reg );
9122 %}
9123
9124 // Xor Register with Memory
9125 instruct xorI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{
9126 match(Set dst (XorI dst (LoadI src)));
9127 effect(KILL cr);
9128
9129 ins_cost(125);
9130 format %{ "XOR $dst,$src" %}
9131 opcode(0x33);
9132 ins_encode( OpcP, RegMem(dst, src) );
9133 ins_pipe( ialu_reg_mem );
9134 %}
9135
9136 // Xor Memory with Register
9137 instruct xorI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{
9138 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
9139 effect(KILL cr);
9140
9141 ins_cost(150);
9142 format %{ "XOR $dst,$src" %}
9143 opcode(0x31); /* Opcode 31 /r */
9144 ins_encode( OpcP, RegMem( src, dst ) );
9145 ins_pipe( ialu_mem_reg );
9146 %}
9147
9148 // Xor Memory with Immediate
9149 instruct xorI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
9150 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
9151 effect(KILL cr);
9152
9153 ins_cost(125);
9154 format %{ "XOR $dst,$src" %}
9155 opcode(0x81,0x6); /* Opcode 81 /6 id */
9156 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
9157 ins_pipe( ialu_mem_imm );
9158 %}
9159
9160 //----------Convert Int to Boolean---------------------------------------------
9161
9162 instruct movI_nocopy(eRegI dst, eRegI src) %{
9163 effect( DEF dst, USE src );
9164 format %{ "MOV $dst,$src" %}
9165 ins_encode( enc_Copy( dst, src) );
9166 ins_pipe( ialu_reg_reg );
9167 %}
9168
9169 instruct ci2b( eRegI dst, eRegI src, eFlagsReg cr ) %{
9170 effect( USE_DEF dst, USE src, KILL cr );
9171
9172 size(4);
9173 format %{ "NEG $dst\n\t"
9174 "ADC $dst,$src" %}
9175 ins_encode( neg_reg(dst),
9176 OpcRegReg(0x13,dst,src) );
9177 ins_pipe( ialu_reg_reg_long );
9178 %}
9179
9180 instruct convI2B( eRegI dst, eRegI src, eFlagsReg cr ) %{
9181 match(Set dst (Conv2B src));
9182
9183 expand %{
9184 movI_nocopy(dst,src);
9185 ci2b(dst,src,cr);
9186 %}
9187 %}
9188
9189 instruct movP_nocopy(eRegI dst, eRegP src) %{
9190 effect( DEF dst, USE src );
9191 format %{ "MOV $dst,$src" %}
9192 ins_encode( enc_Copy( dst, src) );
9193 ins_pipe( ialu_reg_reg );
9194 %}
9195
9196 instruct cp2b( eRegI dst, eRegP src, eFlagsReg cr ) %{
9197 effect( USE_DEF dst, USE src, KILL cr );
9198 format %{ "NEG $dst\n\t"
9199 "ADC $dst,$src" %}
9200 ins_encode( neg_reg(dst),
9201 OpcRegReg(0x13,dst,src) );
9202 ins_pipe( ialu_reg_reg_long );
9203 %}
9204
9205 instruct convP2B( eRegI dst, eRegP src, eFlagsReg cr ) %{
9206 match(Set dst (Conv2B src));
9207
9208 expand %{
9209 movP_nocopy(dst,src);
9210 cp2b(dst,src,cr);
9211 %}
9212 %}
9213
9214 instruct cmpLTMask( eCXRegI dst, ncxRegI p, ncxRegI q, eFlagsReg cr ) %{
9215 match(Set dst (CmpLTMask p q));
9216 effect( KILL cr );
9217 ins_cost(400);
9218
9219 // SETlt can only use low byte of EAX,EBX, ECX, or EDX as destination
9220 format %{ "XOR $dst,$dst\n\t"
9221 "CMP $p,$q\n\t"
9222 "SETlt $dst\n\t"
9223 "NEG $dst" %}
9224 ins_encode( OpcRegReg(0x33,dst,dst),
9225 OpcRegReg(0x3B,p,q),
9226 setLT_reg(dst), neg_reg(dst) );
9227 ins_pipe( pipe_slow );
9228 %}
9229
9230 instruct cmpLTMask0( eRegI dst, immI0 zero, eFlagsReg cr ) %{
9231 match(Set dst (CmpLTMask dst zero));
9232 effect( DEF dst, KILL cr );
9233 ins_cost(100);
9234
9235 format %{ "SAR $dst,31" %}
9236 opcode(0xC1, 0x7); /* C1 /7 ib */
9237 ins_encode( RegOpcImm( dst, 0x1F ) );
9238 ins_pipe( ialu_reg );
9239 %}
9240
9241
9242 instruct cadd_cmpLTMask( ncxRegI p, ncxRegI q, ncxRegI y, eCXRegI tmp, eFlagsReg cr ) %{
9243 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
9244 effect( KILL tmp, KILL cr );
9245 ins_cost(400);
9246 // annoyingly, $tmp has no edges so you cant ask for it in
9247 // any format or encoding
9248 format %{ "SUB $p,$q\n\t"
9249 "SBB ECX,ECX\n\t"
9250 "AND ECX,$y\n\t"
9251 "ADD $p,ECX" %}
9252 ins_encode( enc_cmpLTP(p,q,y,tmp) );
9253 ins_pipe( pipe_cmplt );
9254 %}
9255
9256 /* If I enable this, I encourage spilling in the inner loop of compress.
9257 instruct cadd_cmpLTMask_mem( ncxRegI p, ncxRegI q, memory y, eCXRegI tmp, eFlagsReg cr ) %{
9258 match(Set p (AddI (AndI (CmpLTMask p q) (LoadI y)) (SubI p q)));
9259 effect( USE_KILL tmp, KILL cr );
9260 ins_cost(400);
9261
9262 format %{ "SUB $p,$q\n\t"
9263 "SBB ECX,ECX\n\t"
9264 "AND ECX,$y\n\t"
9265 "ADD $p,ECX" %}
9266 ins_encode( enc_cmpLTP_mem(p,q,y,tmp) );
9267 %}
9268 */
9269
9270 //----------Long Instructions------------------------------------------------
9271 // Add Long Register with Register
9272 instruct addL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9273 match(Set dst (AddL dst src));
9274 effect(KILL cr);
9275 ins_cost(200);
9276 format %{ "ADD $dst.lo,$src.lo\n\t"
9277 "ADC $dst.hi,$src.hi" %}
9278 opcode(0x03, 0x13);
9279 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) );
9280 ins_pipe( ialu_reg_reg_long );
9281 %}
9282
9283 // Add Long Register with Immediate
9284 instruct addL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9285 match(Set dst (AddL dst src));
9286 effect(KILL cr);
9287 format %{ "ADD $dst.lo,$src.lo\n\t"
9288 "ADC $dst.hi,$src.hi" %}
9289 opcode(0x81,0x00,0x02); /* Opcode 81 /0, 81 /2 */
9290 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9291 ins_pipe( ialu_reg_long );
9292 %}
9293
9294 // Add Long Register with Memory
9295 instruct addL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9296 match(Set dst (AddL dst (LoadL mem)));
9297 effect(KILL cr);
9298 ins_cost(125);
9299 format %{ "ADD $dst.lo,$mem\n\t"
9300 "ADC $dst.hi,$mem+4" %}
9301 opcode(0x03, 0x13);
9302 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9303 ins_pipe( ialu_reg_long_mem );
9304 %}
9305
9306 // Subtract Long Register with Register.
9307 instruct subL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9308 match(Set dst (SubL dst src));
9309 effect(KILL cr);
9310 ins_cost(200);
9311 format %{ "SUB $dst.lo,$src.lo\n\t"
9312 "SBB $dst.hi,$src.hi" %}
9313 opcode(0x2B, 0x1B);
9314 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) );
9315 ins_pipe( ialu_reg_reg_long );
9316 %}
9317
9318 // Subtract Long Register with Immediate
9319 instruct subL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9320 match(Set dst (SubL dst src));
9321 effect(KILL cr);
9322 format %{ "SUB $dst.lo,$src.lo\n\t"
9323 "SBB $dst.hi,$src.hi" %}
9324 opcode(0x81,0x05,0x03); /* Opcode 81 /5, 81 /3 */
9325 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9326 ins_pipe( ialu_reg_long );
9327 %}
9328
9329 // Subtract Long Register with Memory
9330 instruct subL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9331 match(Set dst (SubL dst (LoadL mem)));
9332 effect(KILL cr);
9333 ins_cost(125);
9334 format %{ "SUB $dst.lo,$mem\n\t"
9335 "SBB $dst.hi,$mem+4" %}
9336 opcode(0x2B, 0x1B);
9337 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9338 ins_pipe( ialu_reg_long_mem );
9339 %}
9340
9341 instruct negL_eReg(eRegL dst, immL0 zero, eFlagsReg cr) %{
9342 match(Set dst (SubL zero dst));
9343 effect(KILL cr);
9344 ins_cost(300);
9345 format %{ "NEG $dst.hi\n\tNEG $dst.lo\n\tSBB $dst.hi,0" %}
9346 ins_encode( neg_long(dst) );
9347 ins_pipe( ialu_reg_reg_long );
9348 %}
9349
9350 // And Long Register with Register
9351 instruct andL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9352 match(Set dst (AndL dst src));
9353 effect(KILL cr);
9354 format %{ "AND $dst.lo,$src.lo\n\t"
9355 "AND $dst.hi,$src.hi" %}
9356 opcode(0x23,0x23);
9357 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
9358 ins_pipe( ialu_reg_reg_long );
9359 %}
9360
9361 // And Long Register with Immediate
9362 instruct andL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9363 match(Set dst (AndL dst src));
9364 effect(KILL cr);
9365 format %{ "AND $dst.lo,$src.lo\n\t"
9366 "AND $dst.hi,$src.hi" %}
9367 opcode(0x81,0x04,0x04); /* Opcode 81 /4, 81 /4 */
9368 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9369 ins_pipe( ialu_reg_long );
9370 %}
9371
9372 // And Long Register with Memory
9373 instruct andL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9374 match(Set dst (AndL dst (LoadL mem)));
9375 effect(KILL cr);
9376 ins_cost(125);
9377 format %{ "AND $dst.lo,$mem\n\t"
9378 "AND $dst.hi,$mem+4" %}
9379 opcode(0x23, 0x23);
9380 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9381 ins_pipe( ialu_reg_long_mem );
9382 %}
9383
9384 // Or Long Register with Register
9385 instruct orl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9386 match(Set dst (OrL dst src));
9387 effect(KILL cr);
9388 format %{ "OR $dst.lo,$src.lo\n\t"
9389 "OR $dst.hi,$src.hi" %}
9390 opcode(0x0B,0x0B);
9391 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
9392 ins_pipe( ialu_reg_reg_long );
9393 %}
9394
9395 // Or Long Register with Immediate
9396 instruct orl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9397 match(Set dst (OrL dst src));
9398 effect(KILL cr);
9399 format %{ "OR $dst.lo,$src.lo\n\t"
9400 "OR $dst.hi,$src.hi" %}
9401 opcode(0x81,0x01,0x01); /* Opcode 81 /1, 81 /1 */
9402 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9403 ins_pipe( ialu_reg_long );
9404 %}
9405
9406 // Or Long Register with Memory
9407 instruct orl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9408 match(Set dst (OrL dst (LoadL mem)));
9409 effect(KILL cr);
9410 ins_cost(125);
9411 format %{ "OR $dst.lo,$mem\n\t"
9412 "OR $dst.hi,$mem+4" %}
9413 opcode(0x0B,0x0B);
9414 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9415 ins_pipe( ialu_reg_long_mem );
9416 %}
9417
9418 // Xor Long Register with Register
9419 instruct xorl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9420 match(Set dst (XorL dst src));
9421 effect(KILL cr);
9422 format %{ "XOR $dst.lo,$src.lo\n\t"
9423 "XOR $dst.hi,$src.hi" %}
9424 opcode(0x33,0x33);
9425 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
9426 ins_pipe( ialu_reg_reg_long );
9427 %}
9428
9429 // Xor Long Register with Immediate -1
9430 instruct xorl_eReg_im1(eRegL dst, immL_M1 imm) %{
9431 match(Set dst (XorL dst imm));
9432 format %{ "NOT $dst.lo\n\t"
9433 "NOT $dst.hi" %}
9434 ins_encode %{
9435 __ notl($dst$$Register);
9436 __ notl(HIGH_FROM_LOW($dst$$Register));
9437 %}
9438 ins_pipe( ialu_reg_long );
9439 %}
9440
9441 // Xor Long Register with Immediate
9442 instruct xorl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9443 match(Set dst (XorL dst src));
9444 effect(KILL cr);
9445 format %{ "XOR $dst.lo,$src.lo\n\t"
9446 "XOR $dst.hi,$src.hi" %}
9447 opcode(0x81,0x06,0x06); /* Opcode 81 /6, 81 /6 */
9448 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9449 ins_pipe( ialu_reg_long );
9450 %}
9451
9452 // Xor Long Register with Memory
9453 instruct xorl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9454 match(Set dst (XorL dst (LoadL mem)));
9455 effect(KILL cr);
9456 ins_cost(125);
9457 format %{ "XOR $dst.lo,$mem\n\t"
9458 "XOR $dst.hi,$mem+4" %}
9459 opcode(0x33,0x33);
9460 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9461 ins_pipe( ialu_reg_long_mem );
9462 %}
9463
9464 // Shift Left Long by 1
9465 instruct shlL_eReg_1(eRegL dst, immI_1 cnt, eFlagsReg cr) %{
9466 predicate(UseNewLongLShift);
9467 match(Set dst (LShiftL dst cnt));
9468 effect(KILL cr);
9469 ins_cost(100);
9470 format %{ "ADD $dst.lo,$dst.lo\n\t"
9471 "ADC $dst.hi,$dst.hi" %}
9472 ins_encode %{
9473 __ addl($dst$$Register,$dst$$Register);
9474 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9475 %}
9476 ins_pipe( ialu_reg_long );
9477 %}
9478
9479 // Shift Left Long by 2
9480 instruct shlL_eReg_2(eRegL dst, immI_2 cnt, eFlagsReg cr) %{
9481 predicate(UseNewLongLShift);
9482 match(Set dst (LShiftL dst cnt));
9483 effect(KILL cr);
9484 ins_cost(100);
9485 format %{ "ADD $dst.lo,$dst.lo\n\t"
9486 "ADC $dst.hi,$dst.hi\n\t"
9487 "ADD $dst.lo,$dst.lo\n\t"
9488 "ADC $dst.hi,$dst.hi" %}
9489 ins_encode %{
9490 __ addl($dst$$Register,$dst$$Register);
9491 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9492 __ addl($dst$$Register,$dst$$Register);
9493 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9494 %}
9495 ins_pipe( ialu_reg_long );
9496 %}
9497
9498 // Shift Left Long by 3
9499 instruct shlL_eReg_3(eRegL dst, immI_3 cnt, eFlagsReg cr) %{
9500 predicate(UseNewLongLShift);
9501 match(Set dst (LShiftL dst cnt));
9502 effect(KILL cr);
9503 ins_cost(100);
9504 format %{ "ADD $dst.lo,$dst.lo\n\t"
9505 "ADC $dst.hi,$dst.hi\n\t"
9506 "ADD $dst.lo,$dst.lo\n\t"
9507 "ADC $dst.hi,$dst.hi\n\t"
9508 "ADD $dst.lo,$dst.lo\n\t"
9509 "ADC $dst.hi,$dst.hi" %}
9510 ins_encode %{
9511 __ addl($dst$$Register,$dst$$Register);
9512 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9513 __ addl($dst$$Register,$dst$$Register);
9514 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9515 __ addl($dst$$Register,$dst$$Register);
9516 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9517 %}
9518 ins_pipe( ialu_reg_long );
9519 %}
9520
9521 // Shift Left Long by 1-31
9522 instruct shlL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9523 match(Set dst (LShiftL dst cnt));
9524 effect(KILL cr);
9525 ins_cost(200);
9526 format %{ "SHLD $dst.hi,$dst.lo,$cnt\n\t"
9527 "SHL $dst.lo,$cnt" %}
9528 opcode(0xC1, 0x4, 0xA4); /* 0F/A4, then C1 /4 ib */
9529 ins_encode( move_long_small_shift(dst,cnt) );
9530 ins_pipe( ialu_reg_long );
9531 %}
9532
9533 // Shift Left Long by 32-63
9534 instruct shlL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9535 match(Set dst (LShiftL dst cnt));
9536 effect(KILL cr);
9537 ins_cost(300);
9538 format %{ "MOV $dst.hi,$dst.lo\n"
9539 "\tSHL $dst.hi,$cnt-32\n"
9540 "\tXOR $dst.lo,$dst.lo" %}
9541 opcode(0xC1, 0x4); /* C1 /4 ib */
9542 ins_encode( move_long_big_shift_clr(dst,cnt) );
9543 ins_pipe( ialu_reg_long );
9544 %}
9545
9546 // Shift Left Long by variable
9547 instruct salL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9548 match(Set dst (LShiftL dst shift));
9549 effect(KILL cr);
9550 ins_cost(500+200);
9551 size(17);
9552 format %{ "TEST $shift,32\n\t"
9553 "JEQ,s small\n\t"
9554 "MOV $dst.hi,$dst.lo\n\t"
9555 "XOR $dst.lo,$dst.lo\n"
9556 "small:\tSHLD $dst.hi,$dst.lo,$shift\n\t"
9557 "SHL $dst.lo,$shift" %}
9558 ins_encode( shift_left_long( dst, shift ) );
9559 ins_pipe( pipe_slow );
9560 %}
9561
9562 // Shift Right Long by 1-31
9563 instruct shrL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9564 match(Set dst (URShiftL dst cnt));
9565 effect(KILL cr);
9566 ins_cost(200);
9567 format %{ "SHRD $dst.lo,$dst.hi,$cnt\n\t"
9568 "SHR $dst.hi,$cnt" %}
9569 opcode(0xC1, 0x5, 0xAC); /* 0F/AC, then C1 /5 ib */
9570 ins_encode( move_long_small_shift(dst,cnt) );
9571 ins_pipe( ialu_reg_long );
9572 %}
9573
9574 // Shift Right Long by 32-63
9575 instruct shrL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9576 match(Set dst (URShiftL dst cnt));
9577 effect(KILL cr);
9578 ins_cost(300);
9579 format %{ "MOV $dst.lo,$dst.hi\n"
9580 "\tSHR $dst.lo,$cnt-32\n"
9581 "\tXOR $dst.hi,$dst.hi" %}
9582 opcode(0xC1, 0x5); /* C1 /5 ib */
9583 ins_encode( move_long_big_shift_clr(dst,cnt) );
9584 ins_pipe( ialu_reg_long );
9585 %}
9586
9587 // Shift Right Long by variable
9588 instruct shrL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9589 match(Set dst (URShiftL dst shift));
9590 effect(KILL cr);
9591 ins_cost(600);
9592 size(17);
9593 format %{ "TEST $shift,32\n\t"
9594 "JEQ,s small\n\t"
9595 "MOV $dst.lo,$dst.hi\n\t"
9596 "XOR $dst.hi,$dst.hi\n"
9597 "small:\tSHRD $dst.lo,$dst.hi,$shift\n\t"
9598 "SHR $dst.hi,$shift" %}
9599 ins_encode( shift_right_long( dst, shift ) );
9600 ins_pipe( pipe_slow );
9601 %}
9602
9603 // Shift Right Long by 1-31
9604 instruct sarL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9605 match(Set dst (RShiftL dst cnt));
9606 effect(KILL cr);
9607 ins_cost(200);
9608 format %{ "SHRD $dst.lo,$dst.hi,$cnt\n\t"
9609 "SAR $dst.hi,$cnt" %}
9610 opcode(0xC1, 0x7, 0xAC); /* 0F/AC, then C1 /7 ib */
9611 ins_encode( move_long_small_shift(dst,cnt) );
9612 ins_pipe( ialu_reg_long );
9613 %}
9614
9615 // Shift Right Long by 32-63
9616 instruct sarL_eReg_32_63( eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9617 match(Set dst (RShiftL dst cnt));
9618 effect(KILL cr);
9619 ins_cost(300);
9620 format %{ "MOV $dst.lo,$dst.hi\n"
9621 "\tSAR $dst.lo,$cnt-32\n"
9622 "\tSAR $dst.hi,31" %}
9623 opcode(0xC1, 0x7); /* C1 /7 ib */
9624 ins_encode( move_long_big_shift_sign(dst,cnt) );
9625 ins_pipe( ialu_reg_long );
9626 %}
9627
9628 // Shift Right arithmetic Long by variable
9629 instruct sarL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9630 match(Set dst (RShiftL dst shift));
9631 effect(KILL cr);
9632 ins_cost(600);
9633 size(18);
9634 format %{ "TEST $shift,32\n\t"
9635 "JEQ,s small\n\t"
9636 "MOV $dst.lo,$dst.hi\n\t"
9637 "SAR $dst.hi,31\n"
9638 "small:\tSHRD $dst.lo,$dst.hi,$shift\n\t"
9639 "SAR $dst.hi,$shift" %}
9640 ins_encode( shift_right_arith_long( dst, shift ) );
9641 ins_pipe( pipe_slow );
9642 %}
9643
9644
9645 //----------Double Instructions------------------------------------------------
9646 // Double Math
9647
9648 // Compare & branch
9649
9650 // P6 version of float compare, sets condition codes in EFLAGS
9651 instruct cmpD_cc_P6(eFlagsRegU cr, regD src1, regD src2, eAXRegI rax) %{
9652 predicate(VM_Version::supports_cmov() && UseSSE <=1);
9653 match(Set cr (CmpD src1 src2));
9654 effect(KILL rax);
9655 ins_cost(150);
9656 format %{ "FLD $src1\n\t"
9657 "FUCOMIP ST,$src2 // P6 instruction\n\t"
9658 "JNP exit\n\t"
9659 "MOV ah,1 // saw a NaN, set CF\n\t"
9660 "SAHF\n"
9661 "exit:\tNOP // avoid branch to branch" %}
9662 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
9663 ins_encode( Push_Reg_D(src1),
9664 OpcP, RegOpc(src2),
9665 cmpF_P6_fixup );
9666 ins_pipe( pipe_slow );
9667 %}
9668
9669 instruct cmpD_cc_P6CF(eFlagsRegUCF cr, regD src1, regD src2) %{
9670 predicate(VM_Version::supports_cmov() && UseSSE <=1);
9671 match(Set cr (CmpD src1 src2));
9672 ins_cost(150);
9673 format %{ "FLD $src1\n\t"
9674 "FUCOMIP ST,$src2 // P6 instruction" %}
9675 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
9676 ins_encode( Push_Reg_D(src1),
9677 OpcP, RegOpc(src2));
9678 ins_pipe( pipe_slow );
9679 %}
9680
9681 // Compare & branch
9682 instruct cmpD_cc(eFlagsRegU cr, regD src1, regD src2, eAXRegI rax) %{
9683 predicate(UseSSE<=1);
9684 match(Set cr (CmpD src1 src2));
9685 effect(KILL rax);
9686 ins_cost(200);
9687 format %{ "FLD $src1\n\t"
9688 "FCOMp $src2\n\t"
9689 "FNSTSW AX\n\t"
9690 "TEST AX,0x400\n\t"
9691 "JZ,s flags\n\t"
9692 "MOV AH,1\t# unordered treat as LT\n"
9693 "flags:\tSAHF" %}
9694 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
9695 ins_encode( Push_Reg_D(src1),
9696 OpcP, RegOpc(src2),
9697 fpu_flags);
9698 ins_pipe( pipe_slow );
9699 %}
9700
9701 // Compare vs zero into -1,0,1
9702 instruct cmpD_0(eRegI dst, regD src1, immD0 zero, eAXRegI rax, eFlagsReg cr) %{
9703 predicate(UseSSE<=1);
9704 match(Set dst (CmpD3 src1 zero));
9705 effect(KILL cr, KILL rax);
9706 ins_cost(280);
9707 format %{ "FTSTD $dst,$src1" %}
9708 opcode(0xE4, 0xD9);
9709 ins_encode( Push_Reg_D(src1),
9710 OpcS, OpcP, PopFPU,
9711 CmpF_Result(dst));
9712 ins_pipe( pipe_slow );
9713 %}
9714
9715 // Compare into -1,0,1
9716 instruct cmpD_reg(eRegI dst, regD src1, regD src2, eAXRegI rax, eFlagsReg cr) %{
9717 predicate(UseSSE<=1);
9718 match(Set dst (CmpD3 src1 src2));
9719 effect(KILL cr, KILL rax);
9720 ins_cost(300);
9721 format %{ "FCMPD $dst,$src1,$src2" %}
9722 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
9723 ins_encode( Push_Reg_D(src1),
9724 OpcP, RegOpc(src2),
9725 CmpF_Result(dst));
9726 ins_pipe( pipe_slow );
9727 %}
9728
9729 // float compare and set condition codes in EFLAGS by XMM regs
9730 instruct cmpXD_cc(eFlagsRegU cr, regXD dst, regXD src, eAXRegI rax) %{
9731 predicate(UseSSE>=2);
9732 match(Set cr (CmpD dst src));
9733 effect(KILL rax);
9734 ins_cost(125);
9735 format %{ "COMISD $dst,$src\n"
9736 "\tJNP exit\n"
9737 "\tMOV ah,1 // saw a NaN, set CF\n"
9738 "\tSAHF\n"
9739 "exit:\tNOP // avoid branch to branch" %}
9740 opcode(0x66, 0x0F, 0x2F);
9741 ins_encode(OpcP, OpcS, Opcode(tertiary), RegReg(dst, src), cmpF_P6_fixup);
9742 ins_pipe( pipe_slow );
9743 %}
9744
9745 instruct cmpXD_ccCF(eFlagsRegUCF cr, regXD dst, regXD src) %{
9746 predicate(UseSSE>=2);
9747 match(Set cr (CmpD dst src));
9748 ins_cost(100);
9749 format %{ "COMISD $dst,$src" %}
9750 opcode(0x66, 0x0F, 0x2F);
9751 ins_encode(OpcP, OpcS, Opcode(tertiary), RegReg(dst, src));
9752 ins_pipe( pipe_slow );
9753 %}
9754
9755 // float compare and set condition codes in EFLAGS by XMM regs
9756 instruct cmpXD_ccmem(eFlagsRegU cr, regXD dst, memory src, eAXRegI rax) %{
9757 predicate(UseSSE>=2);
9758 match(Set cr (CmpD dst (LoadD src)));
9759 effect(KILL rax);
9760 ins_cost(145);
9761 format %{ "COMISD $dst,$src\n"
9762 "\tJNP exit\n"
9763 "\tMOV ah,1 // saw a NaN, set CF\n"
9764 "\tSAHF\n"
9765 "exit:\tNOP // avoid branch to branch" %}
9766 opcode(0x66, 0x0F, 0x2F);
9767 ins_encode(OpcP, OpcS, Opcode(tertiary), RegMem(dst, src), cmpF_P6_fixup);
9768 ins_pipe( pipe_slow );
9769 %}
9770
9771 instruct cmpXD_ccmemCF(eFlagsRegUCF cr, regXD dst, memory src) %{
9772 predicate(UseSSE>=2);
9773 match(Set cr (CmpD dst (LoadD src)));
9774 ins_cost(100);
9775 format %{ "COMISD $dst,$src" %}
9776 opcode(0x66, 0x0F, 0x2F);
9777 ins_encode(OpcP, OpcS, Opcode(tertiary), RegMem(dst, src));
9778 ins_pipe( pipe_slow );
9779 %}
9780
9781 // Compare into -1,0,1 in XMM
9782 instruct cmpXD_reg(eRegI dst, regXD src1, regXD src2, eFlagsReg cr) %{
9783 predicate(UseSSE>=2);
9784 match(Set dst (CmpD3 src1 src2));
9785 effect(KILL cr);
9786 ins_cost(255);
9787 format %{ "XOR $dst,$dst\n"
9788 "\tCOMISD $src1,$src2\n"
9789 "\tJP,s nan\n"
9790 "\tJEQ,s exit\n"
9791 "\tJA,s inc\n"
9792 "nan:\tDEC $dst\n"
9793 "\tJMP,s exit\n"
9794 "inc:\tINC $dst\n"
9795 "exit:"
9796 %}
9797 opcode(0x66, 0x0F, 0x2F);
9798 ins_encode(Xor_Reg(dst), OpcP, OpcS, Opcode(tertiary), RegReg(src1, src2),
9799 CmpX_Result(dst));
9800 ins_pipe( pipe_slow );
9801 %}
9802
9803 // Compare into -1,0,1 in XMM and memory
9804 instruct cmpXD_regmem(eRegI dst, regXD src1, memory mem, eFlagsReg cr) %{
9805 predicate(UseSSE>=2);
9806 match(Set dst (CmpD3 src1 (LoadD mem)));
9807 effect(KILL cr);
9808 ins_cost(275);
9809 format %{ "COMISD $src1,$mem\n"
9810 "\tMOV $dst,0\t\t# do not blow flags\n"
9811 "\tJP,s nan\n"
9812 "\tJEQ,s exit\n"
9813 "\tJA,s inc\n"
9814 "nan:\tDEC $dst\n"
9815 "\tJMP,s exit\n"
9816 "inc:\tINC $dst\n"
9817 "exit:"
9818 %}
9819 opcode(0x66, 0x0F, 0x2F);
9820 ins_encode(OpcP, OpcS, Opcode(tertiary), RegMem(src1, mem),
9821 LdImmI(dst,0x0), CmpX_Result(dst));
9822 ins_pipe( pipe_slow );
9823 %}
9824
9825
9826 instruct subD_reg(regD dst, regD src) %{
9827 predicate (UseSSE <=1);
9828 match(Set dst (SubD dst src));
9829
9830 format %{ "FLD $src\n\t"
9831 "DSUBp $dst,ST" %}
9832 opcode(0xDE, 0x5); /* DE E8+i or DE /5 */
9833 ins_cost(150);
9834 ins_encode( Push_Reg_D(src),
9835 OpcP, RegOpc(dst) );
9836 ins_pipe( fpu_reg_reg );
9837 %}
9838
9839 instruct subD_reg_round(stackSlotD dst, regD src1, regD src2) %{
9840 predicate (UseSSE <=1);
9841 match(Set dst (RoundDouble (SubD src1 src2)));
9842 ins_cost(250);
9843
9844 format %{ "FLD $src2\n\t"
9845 "DSUB ST,$src1\n\t"
9846 "FSTP_D $dst\t# D-round" %}
9847 opcode(0xD8, 0x5);
9848 ins_encode( Push_Reg_D(src2),
9849 OpcP, RegOpc(src1), Pop_Mem_D(dst) );
9850 ins_pipe( fpu_mem_reg_reg );
9851 %}
9852
9853
9854 instruct subD_reg_mem(regD dst, memory src) %{
9855 predicate (UseSSE <=1);
9856 match(Set dst (SubD dst (LoadD src)));
9857 ins_cost(150);
9858
9859 format %{ "FLD $src\n\t"
9860 "DSUBp $dst,ST" %}
9861 opcode(0xDE, 0x5, 0xDD); /* DE C0+i */ /* LoadD DD /0 */
9862 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
9863 OpcP, RegOpc(dst) );
9864 ins_pipe( fpu_reg_mem );
9865 %}
9866
9867 instruct absD_reg(regDPR1 dst, regDPR1 src) %{
9868 predicate (UseSSE<=1);
9869 match(Set dst (AbsD src));
9870 ins_cost(100);
9871 format %{ "FABS" %}
9872 opcode(0xE1, 0xD9);
9873 ins_encode( OpcS, OpcP );
9874 ins_pipe( fpu_reg_reg );
9875 %}
9876
9877 instruct absXD_reg( regXD dst ) %{
9878 predicate(UseSSE>=2);
9879 match(Set dst (AbsD dst));
9880 format %{ "ANDPD $dst,[0x7FFFFFFFFFFFFFFF]\t# ABS D by sign masking" %}
9881 ins_encode( AbsXD_encoding(dst));
9882 ins_pipe( pipe_slow );
9883 %}
9884
9885 instruct negD_reg(regDPR1 dst, regDPR1 src) %{
9886 predicate(UseSSE<=1);
9887 match(Set dst (NegD src));
9888 ins_cost(100);
9889 format %{ "FCHS" %}
9890 opcode(0xE0, 0xD9);
9891 ins_encode( OpcS, OpcP );
9892 ins_pipe( fpu_reg_reg );
9893 %}
9894
9895 instruct negXD_reg( regXD dst ) %{
9896 predicate(UseSSE>=2);
9897 match(Set dst (NegD dst));
9898 format %{ "XORPD $dst,[0x8000000000000000]\t# CHS D by sign flipping" %}
9899 ins_encode %{
9900 __ xorpd($dst$$XMMRegister,
9901 ExternalAddress((address)double_signflip_pool));
9902 %}
9903 ins_pipe( pipe_slow );
9904 %}
9905
9906 instruct addD_reg(regD dst, regD src) %{
9907 predicate(UseSSE<=1);
9908 match(Set dst (AddD dst src));
9909 format %{ "FLD $src\n\t"
9910 "DADD $dst,ST" %}
9911 size(4);
9912 ins_cost(150);
9913 opcode(0xDE, 0x0); /* DE C0+i or DE /0*/
9914 ins_encode( Push_Reg_D(src),
9915 OpcP, RegOpc(dst) );
9916 ins_pipe( fpu_reg_reg );
9917 %}
9918
9919
9920 instruct addD_reg_round(stackSlotD dst, regD src1, regD src2) %{
9921 predicate(UseSSE<=1);
9922 match(Set dst (RoundDouble (AddD src1 src2)));
9923 ins_cost(250);
9924
9925 format %{ "FLD $src2\n\t"
9926 "DADD ST,$src1\n\t"
9927 "FSTP_D $dst\t# D-round" %}
9928 opcode(0xD8, 0x0); /* D8 C0+i or D8 /0*/
9929 ins_encode( Push_Reg_D(src2),
9930 OpcP, RegOpc(src1), Pop_Mem_D(dst) );
9931 ins_pipe( fpu_mem_reg_reg );
9932 %}
9933
9934
9935 instruct addD_reg_mem(regD dst, memory src) %{
9936 predicate(UseSSE<=1);
9937 match(Set dst (AddD dst (LoadD src)));
9938 ins_cost(150);
9939
9940 format %{ "FLD $src\n\t"
9941 "DADDp $dst,ST" %}
9942 opcode(0xDE, 0x0, 0xDD); /* DE C0+i */ /* LoadD DD /0 */
9943 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
9944 OpcP, RegOpc(dst) );
9945 ins_pipe( fpu_reg_mem );
9946 %}
9947
9948 // add-to-memory
9949 instruct addD_mem_reg(memory dst, regD src) %{
9950 predicate(UseSSE<=1);
9951 match(Set dst (StoreD dst (RoundDouble (AddD (LoadD dst) src))));
9952 ins_cost(150);
9953
9954 format %{ "FLD_D $dst\n\t"
9955 "DADD ST,$src\n\t"
9956 "FST_D $dst" %}
9957 opcode(0xDD, 0x0);
9958 ins_encode( Opcode(0xDD), RMopc_Mem(0x00,dst),
9959 Opcode(0xD8), RegOpc(src),
9960 set_instruction_start,
9961 Opcode(0xDD), RMopc_Mem(0x03,dst) );
9962 ins_pipe( fpu_reg_mem );
9963 %}
9964
9965 instruct addD_reg_imm1(regD dst, immD1 src) %{
9966 predicate(UseSSE<=1);
9967 match(Set dst (AddD dst src));
9968 ins_cost(125);
9969 format %{ "FLD1\n\t"
9970 "DADDp $dst,ST" %}
9971 opcode(0xDE, 0x00);
9972 ins_encode( LdImmD(src),
9973 OpcP, RegOpc(dst) );
9974 ins_pipe( fpu_reg );
9975 %}
9976
9977 instruct addD_reg_imm(regD dst, immD src) %{
9978 predicate(UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 );
9979 match(Set dst (AddD dst src));
9980 ins_cost(200);
9981 format %{ "FLD_D [$src]\n\t"
9982 "DADDp $dst,ST" %}
9983 opcode(0xDE, 0x00); /* DE /0 */
9984 ins_encode( LdImmD(src),
9985 OpcP, RegOpc(dst));
9986 ins_pipe( fpu_reg_mem );
9987 %}
9988
9989 instruct addD_reg_imm_round(stackSlotD dst, regD src, immD con) %{
9990 predicate(UseSSE<=1 && _kids[0]->_kids[1]->_leaf->getd() != 0.0 && _kids[0]->_kids[1]->_leaf->getd() != 1.0 );
9991 match(Set dst (RoundDouble (AddD src con)));
9992 ins_cost(200);
9993 format %{ "FLD_D [$con]\n\t"
9994 "DADD ST,$src\n\t"
9995 "FSTP_D $dst\t# D-round" %}
9996 opcode(0xD8, 0x00); /* D8 /0 */
9997 ins_encode( LdImmD(con),
9998 OpcP, RegOpc(src), Pop_Mem_D(dst));
9999 ins_pipe( fpu_mem_reg_con );
10000 %}
10001
10002 // Add two double precision floating point values in xmm
10003 instruct addXD_reg(regXD dst, regXD src) %{
10004 predicate(UseSSE>=2);
10005 match(Set dst (AddD dst src));
10006 format %{ "ADDSD $dst,$src" %}
10007 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x58), RegReg(dst, src));
10008 ins_pipe( pipe_slow );
10009 %}
10010
10011 instruct addXD_imm(regXD dst, immXD con) %{
10012 predicate(UseSSE>=2);
10013 match(Set dst (AddD dst con));
10014 format %{ "ADDSD $dst,[$con]" %}
10015 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x58), LdImmXD(dst, con) );
10016 ins_pipe( pipe_slow );
10017 %}
10018
10019 instruct addXD_mem(regXD dst, memory mem) %{
10020 predicate(UseSSE>=2);
10021 match(Set dst (AddD dst (LoadD mem)));
10022 format %{ "ADDSD $dst,$mem" %}
10023 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x58), RegMem(dst,mem));
10024 ins_pipe( pipe_slow );
10025 %}
10026
10027 // Sub two double precision floating point values in xmm
10028 instruct subXD_reg(regXD dst, regXD src) %{
10029 predicate(UseSSE>=2);
10030 match(Set dst (SubD dst src));
10031 format %{ "SUBSD $dst,$src" %}
10032 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5C), RegReg(dst, src));
10033 ins_pipe( pipe_slow );
10034 %}
10035
10036 instruct subXD_imm(regXD dst, immXD con) %{
10037 predicate(UseSSE>=2);
10038 match(Set dst (SubD dst con));
10039 format %{ "SUBSD $dst,[$con]" %}
10040 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5C), LdImmXD(dst, con) );
10041 ins_pipe( pipe_slow );
10042 %}
10043
10044 instruct subXD_mem(regXD dst, memory mem) %{
10045 predicate(UseSSE>=2);
10046 match(Set dst (SubD dst (LoadD mem)));
10047 format %{ "SUBSD $dst,$mem" %}
10048 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5C), RegMem(dst,mem));
10049 ins_pipe( pipe_slow );
10050 %}
10051
10052 // Mul two double precision floating point values in xmm
10053 instruct mulXD_reg(regXD dst, regXD src) %{
10054 predicate(UseSSE>=2);
10055 match(Set dst (MulD dst src));
10056 format %{ "MULSD $dst,$src" %}
10057 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x59), RegReg(dst, src));
10058 ins_pipe( pipe_slow );
10059 %}
10060
10061 instruct mulXD_imm(regXD dst, immXD con) %{
10062 predicate(UseSSE>=2);
10063 match(Set dst (MulD dst con));
10064 format %{ "MULSD $dst,[$con]" %}
10065 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x59), LdImmXD(dst, con) );
10066 ins_pipe( pipe_slow );
10067 %}
10068
10069 instruct mulXD_mem(regXD dst, memory mem) %{
10070 predicate(UseSSE>=2);
10071 match(Set dst (MulD dst (LoadD mem)));
10072 format %{ "MULSD $dst,$mem" %}
10073 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x59), RegMem(dst,mem));
10074 ins_pipe( pipe_slow );
10075 %}
10076
10077 // Div two double precision floating point values in xmm
10078 instruct divXD_reg(regXD dst, regXD src) %{
10079 predicate(UseSSE>=2);
10080 match(Set dst (DivD dst src));
10081 format %{ "DIVSD $dst,$src" %}
10082 opcode(0xF2, 0x0F, 0x5E);
10083 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5E), RegReg(dst, src));
10084 ins_pipe( pipe_slow );
10085 %}
10086
10087 instruct divXD_imm(regXD dst, immXD con) %{
10088 predicate(UseSSE>=2);
10089 match(Set dst (DivD dst con));
10090 format %{ "DIVSD $dst,[$con]" %}
10091 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5E), LdImmXD(dst, con));
10092 ins_pipe( pipe_slow );
10093 %}
10094
10095 instruct divXD_mem(regXD dst, memory mem) %{
10096 predicate(UseSSE>=2);
10097 match(Set dst (DivD dst (LoadD mem)));
10098 format %{ "DIVSD $dst,$mem" %}
10099 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5E), RegMem(dst,mem));
10100 ins_pipe( pipe_slow );
10101 %}
10102
10103
10104 instruct mulD_reg(regD dst, regD src) %{
10105 predicate(UseSSE<=1);
10106 match(Set dst (MulD dst src));
10107 format %{ "FLD $src\n\t"
10108 "DMULp $dst,ST" %}
10109 opcode(0xDE, 0x1); /* DE C8+i or DE /1*/
10110 ins_cost(150);
10111 ins_encode( Push_Reg_D(src),
10112 OpcP, RegOpc(dst) );
10113 ins_pipe( fpu_reg_reg );
10114 %}
10115
10116 // Strict FP instruction biases argument before multiply then
10117 // biases result to avoid double rounding of subnormals.
10118 //
10119 // scale arg1 by multiplying arg1 by 2^(-15360)
10120 // load arg2
10121 // multiply scaled arg1 by arg2
10122 // rescale product by 2^(15360)
10123 //
10124 instruct strictfp_mulD_reg(regDPR1 dst, regnotDPR1 src) %{
10125 predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() );
10126 match(Set dst (MulD dst src));
10127 ins_cost(1); // Select this instruction for all strict FP double multiplies
10128
10129 format %{ "FLD StubRoutines::_fpu_subnormal_bias1\n\t"
10130 "DMULp $dst,ST\n\t"
10131 "FLD $src\n\t"
10132 "DMULp $dst,ST\n\t"
10133 "FLD StubRoutines::_fpu_subnormal_bias2\n\t"
10134 "DMULp $dst,ST\n\t" %}
10135 opcode(0xDE, 0x1); /* DE C8+i or DE /1*/
10136 ins_encode( strictfp_bias1(dst),
10137 Push_Reg_D(src),
10138 OpcP, RegOpc(dst),
10139 strictfp_bias2(dst) );
10140 ins_pipe( fpu_reg_reg );
10141 %}
10142
10143 instruct mulD_reg_imm(regD dst, immD src) %{
10144 predicate( UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 );
10145 match(Set dst (MulD dst src));
10146 ins_cost(200);
10147 format %{ "FLD_D [$src]\n\t"
10148 "DMULp $dst,ST" %}
10149 opcode(0xDE, 0x1); /* DE /1 */
10150 ins_encode( LdImmD(src),
10151 OpcP, RegOpc(dst) );
10152 ins_pipe( fpu_reg_mem );
10153 %}
10154
10155
10156 instruct mulD_reg_mem(regD dst, memory src) %{
10157 predicate( UseSSE<=1 );
10158 match(Set dst (MulD dst (LoadD src)));
10159 ins_cost(200);
10160 format %{ "FLD_D $src\n\t"
10161 "DMULp $dst,ST" %}
10162 opcode(0xDE, 0x1, 0xDD); /* DE C8+i or DE /1*/ /* LoadD DD /0 */
10163 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
10164 OpcP, RegOpc(dst) );
10165 ins_pipe( fpu_reg_mem );
10166 %}
10167
10168 //
10169 // Cisc-alternate to reg-reg multiply
10170 instruct mulD_reg_mem_cisc(regD dst, regD src, memory mem) %{
10171 predicate( UseSSE<=1 );
10172 match(Set dst (MulD src (LoadD mem)));
10173 ins_cost(250);
10174 format %{ "FLD_D $mem\n\t"
10175 "DMUL ST,$src\n\t"
10176 "FSTP_D $dst" %}
10177 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */ /* LoadD D9 /0 */
10178 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem),
10179 OpcReg_F(src),
10180 Pop_Reg_D(dst) );
10181 ins_pipe( fpu_reg_reg_mem );
10182 %}
10183
10184
10185 // MACRO3 -- addD a mulD
10186 // This instruction is a '2-address' instruction in that the result goes
10187 // back to src2. This eliminates a move from the macro; possibly the
10188 // register allocator will have to add it back (and maybe not).
10189 instruct addD_mulD_reg(regD src2, regD src1, regD src0) %{
10190 predicate( UseSSE<=1 );
10191 match(Set src2 (AddD (MulD src0 src1) src2));
10192 format %{ "FLD $src0\t# ===MACRO3d===\n\t"
10193 "DMUL ST,$src1\n\t"
10194 "DADDp $src2,ST" %}
10195 ins_cost(250);
10196 opcode(0xDD); /* LoadD DD /0 */
10197 ins_encode( Push_Reg_F(src0),
10198 FMul_ST_reg(src1),
10199 FAddP_reg_ST(src2) );
10200 ins_pipe( fpu_reg_reg_reg );
10201 %}
10202
10203
10204 // MACRO3 -- subD a mulD
10205 instruct subD_mulD_reg(regD src2, regD src1, regD src0) %{
10206 predicate( UseSSE<=1 );
10207 match(Set src2 (SubD (MulD src0 src1) src2));
10208 format %{ "FLD $src0\t# ===MACRO3d===\n\t"
10209 "DMUL ST,$src1\n\t"
10210 "DSUBRp $src2,ST" %}
10211 ins_cost(250);
10212 ins_encode( Push_Reg_F(src0),
10213 FMul_ST_reg(src1),
10214 Opcode(0xDE), Opc_plus(0xE0,src2));
10215 ins_pipe( fpu_reg_reg_reg );
10216 %}
10217
10218
10219 instruct divD_reg(regD dst, regD src) %{
10220 predicate( UseSSE<=1 );
10221 match(Set dst (DivD dst src));
10222
10223 format %{ "FLD $src\n\t"
10224 "FDIVp $dst,ST" %}
10225 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
10226 ins_cost(150);
10227 ins_encode( Push_Reg_D(src),
10228 OpcP, RegOpc(dst) );
10229 ins_pipe( fpu_reg_reg );
10230 %}
10231
10232 // Strict FP instruction biases argument before division then
10233 // biases result, to avoid double rounding of subnormals.
10234 //
10235 // scale dividend by multiplying dividend by 2^(-15360)
10236 // load divisor
10237 // divide scaled dividend by divisor
10238 // rescale quotient by 2^(15360)
10239 //
10240 instruct strictfp_divD_reg(regDPR1 dst, regnotDPR1 src) %{
10241 predicate (UseSSE<=1);
10242 match(Set dst (DivD dst src));
10243 predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() );
10244 ins_cost(01);
10245
10246 format %{ "FLD StubRoutines::_fpu_subnormal_bias1\n\t"
10247 "DMULp $dst,ST\n\t"
10248 "FLD $src\n\t"
10249 "FDIVp $dst,ST\n\t"
10250 "FLD StubRoutines::_fpu_subnormal_bias2\n\t"
10251 "DMULp $dst,ST\n\t" %}
10252 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
10253 ins_encode( strictfp_bias1(dst),
10254 Push_Reg_D(src),
10255 OpcP, RegOpc(dst),
10256 strictfp_bias2(dst) );
10257 ins_pipe( fpu_reg_reg );
10258 %}
10259
10260 instruct divD_reg_round(stackSlotD dst, regD src1, regD src2) %{
10261 predicate( UseSSE<=1 && !(Compile::current()->has_method() && Compile::current()->method()->is_strict()) );
10262 match(Set dst (RoundDouble (DivD src1 src2)));
10263
10264 format %{ "FLD $src1\n\t"
10265 "FDIV ST,$src2\n\t"
10266 "FSTP_D $dst\t# D-round" %}
10267 opcode(0xD8, 0x6); /* D8 F0+i or D8 /6 */
10268 ins_encode( Push_Reg_D(src1),
10269 OpcP, RegOpc(src2), Pop_Mem_D(dst) );
10270 ins_pipe( fpu_mem_reg_reg );
10271 %}
10272
10273
10274 instruct modD_reg(regD dst, regD src, eAXRegI rax, eFlagsReg cr) %{
10275 predicate(UseSSE<=1);
10276 match(Set dst (ModD dst src));
10277 effect(KILL rax, KILL cr); // emitModD() uses EAX and EFLAGS
10278
10279 format %{ "DMOD $dst,$src" %}
10280 ins_cost(250);
10281 ins_encode(Push_Reg_Mod_D(dst, src),
10282 emitModD(),
10283 Push_Result_Mod_D(src),
10284 Pop_Reg_D(dst));
10285 ins_pipe( pipe_slow );
10286 %}
10287
10288 instruct modXD_reg(regXD dst, regXD src0, regXD src1, eAXRegI rax, eFlagsReg cr) %{
10289 predicate(UseSSE>=2);
10290 match(Set dst (ModD src0 src1));
10291 effect(KILL rax, KILL cr);
10292
10293 format %{ "SUB ESP,8\t # DMOD\n"
10294 "\tMOVSD [ESP+0],$src1\n"
10295 "\tFLD_D [ESP+0]\n"
10296 "\tMOVSD [ESP+0],$src0\n"
10297 "\tFLD_D [ESP+0]\n"
10298 "loop:\tFPREM\n"
10299 "\tFWAIT\n"
10300 "\tFNSTSW AX\n"
10301 "\tSAHF\n"
10302 "\tJP loop\n"
10303 "\tFSTP_D [ESP+0]\n"
10304 "\tMOVSD $dst,[ESP+0]\n"
10305 "\tADD ESP,8\n"
10306 "\tFSTP ST0\t # Restore FPU Stack"
10307 %}
10308 ins_cost(250);
10309 ins_encode( Push_ModD_encoding(src0, src1), emitModD(), Push_ResultXD(dst), PopFPU);
10310 ins_pipe( pipe_slow );
10311 %}
10312
10313 instruct sinD_reg(regDPR1 dst, regDPR1 src) %{
10314 predicate (UseSSE<=1);
10315 match(Set dst (SinD src));
10316 ins_cost(1800);
10317 format %{ "DSIN $dst" %}
10318 opcode(0xD9, 0xFE);
10319 ins_encode( OpcP, OpcS );
10320 ins_pipe( pipe_slow );
10321 %}
10322
10323 instruct sinXD_reg(regXD dst, eFlagsReg cr) %{
10324 predicate (UseSSE>=2);
10325 match(Set dst (SinD dst));
10326 effect(KILL cr); // Push_{Src|Result}XD() uses "{SUB|ADD} ESP,8"
10327 ins_cost(1800);
10328 format %{ "DSIN $dst" %}
10329 opcode(0xD9, 0xFE);
10330 ins_encode( Push_SrcXD(dst), OpcP, OpcS, Push_ResultXD(dst) );
10331 ins_pipe( pipe_slow );
10332 %}
10333
10334 instruct cosD_reg(regDPR1 dst, regDPR1 src) %{
10335 predicate (UseSSE<=1);
10336 match(Set dst (CosD src));
10337 ins_cost(1800);
10338 format %{ "DCOS $dst" %}
10339 opcode(0xD9, 0xFF);
10340 ins_encode( OpcP, OpcS );
10341 ins_pipe( pipe_slow );
10342 %}
10343
10344 instruct cosXD_reg(regXD dst, eFlagsReg cr) %{
10345 predicate (UseSSE>=2);
10346 match(Set dst (CosD dst));
10347 effect(KILL cr); // Push_{Src|Result}XD() uses "{SUB|ADD} ESP,8"
10348 ins_cost(1800);
10349 format %{ "DCOS $dst" %}
10350 opcode(0xD9, 0xFF);
10351 ins_encode( Push_SrcXD(dst), OpcP, OpcS, Push_ResultXD(dst) );
10352 ins_pipe( pipe_slow );
10353 %}
10354
10355 instruct tanD_reg(regDPR1 dst, regDPR1 src) %{
10356 predicate (UseSSE<=1);
10357 match(Set dst(TanD src));
10358 format %{ "DTAN $dst" %}
10359 ins_encode( Opcode(0xD9), Opcode(0xF2), // fptan
10360 Opcode(0xDD), Opcode(0xD8)); // fstp st
10361 ins_pipe( pipe_slow );
10362 %}
10363
10364 instruct tanXD_reg(regXD dst, eFlagsReg cr) %{
10365 predicate (UseSSE>=2);
10366 match(Set dst(TanD dst));
10367 effect(KILL cr); // Push_{Src|Result}XD() uses "{SUB|ADD} ESP,8"
10368 format %{ "DTAN $dst" %}
10369 ins_encode( Push_SrcXD(dst),
10370 Opcode(0xD9), Opcode(0xF2), // fptan
10371 Opcode(0xDD), Opcode(0xD8), // fstp st
10372 Push_ResultXD(dst) );
10373 ins_pipe( pipe_slow );
10374 %}
10375
10376 instruct atanD_reg(regD dst, regD src) %{
10377 predicate (UseSSE<=1);
10378 match(Set dst(AtanD dst src));
10379 format %{ "DATA $dst,$src" %}
10380 opcode(0xD9, 0xF3);
10381 ins_encode( Push_Reg_D(src),
10382 OpcP, OpcS, RegOpc(dst) );
10383 ins_pipe( pipe_slow );
10384 %}
10385
10386 instruct atanXD_reg(regXD dst, regXD src, eFlagsReg cr) %{
10387 predicate (UseSSE>=2);
10388 match(Set dst(AtanD dst src));
10389 effect(KILL cr); // Push_{Src|Result}XD() uses "{SUB|ADD} ESP,8"
10390 format %{ "DATA $dst,$src" %}
10391 opcode(0xD9, 0xF3);
10392 ins_encode( Push_SrcXD(src),
10393 OpcP, OpcS, Push_ResultXD(dst) );
10394 ins_pipe( pipe_slow );
10395 %}
10396
10397 instruct sqrtD_reg(regD dst, regD src) %{
10398 predicate (UseSSE<=1);
10399 match(Set dst (SqrtD src));
10400 format %{ "DSQRT $dst,$src" %}
10401 opcode(0xFA, 0xD9);
10402 ins_encode( Push_Reg_D(src),
10403 OpcS, OpcP, Pop_Reg_D(dst) );
10404 ins_pipe( pipe_slow );
10405 %}
10406
10407 instruct powD_reg(regD X, regDPR1 Y, eAXRegI rax, eBXRegI rbx, eCXRegI rcx) %{
10408 predicate (UseSSE<=1);
10409 match(Set Y (PowD X Y)); // Raise X to the Yth power
10410 effect(KILL rax, KILL rbx, KILL rcx);
10411 format %{ "SUB ESP,8\t\t# Fast-path POW encoding\n\t"
10412 "FLD_D $X\n\t"
10413 "FYL2X \t\t\t# Q=Y*ln2(X)\n\t"
10414
10415 "FDUP \t\t\t# Q Q\n\t"
10416 "FRNDINT\t\t\t# int(Q) Q\n\t"
10417 "FSUB ST(1),ST(0)\t# int(Q) frac(Q)\n\t"
10418 "FISTP dword [ESP]\n\t"
10419 "F2XM1 \t\t\t# 2^frac(Q)-1 int(Q)\n\t"
10420 "FLD1 \t\t\t# 1 2^frac(Q)-1 int(Q)\n\t"
10421 "FADDP \t\t\t# 2^frac(Q) int(Q)\n\t" // could use FADD [1.000] instead
10422 "MOV EAX,[ESP]\t# Pick up int(Q)\n\t"
10423 "MOV ECX,0xFFFFF800\t# Overflow mask\n\t"
10424 "ADD EAX,1023\t\t# Double exponent bias\n\t"
10425 "MOV EBX,EAX\t\t# Preshifted biased expo\n\t"
10426 "SHL EAX,20\t\t# Shift exponent into place\n\t"
10427 "TEST EBX,ECX\t\t# Check for overflow\n\t"
10428 "CMOVne EAX,ECX\t\t# If overflow, stuff NaN into EAX\n\t"
10429 "MOV [ESP+4],EAX\t# Marshal 64-bit scaling double\n\t"
10430 "MOV [ESP+0],0\n\t"
10431 "FMUL ST(0),[ESP+0]\t# Scale\n\t"
10432
10433 "ADD ESP,8"
10434 %}
10435 ins_encode( push_stack_temp_qword,
10436 Push_Reg_D(X),
10437 Opcode(0xD9), Opcode(0xF1), // fyl2x
10438 pow_exp_core_encoding,
10439 pop_stack_temp_qword);
10440 ins_pipe( pipe_slow );
10441 %}
10442
10443 instruct powXD_reg(regXD dst, regXD src0, regXD src1, regDPR1 tmp1, eAXRegI rax, eBXRegI rbx, eCXRegI rcx ) %{
10444 predicate (UseSSE>=2);
10445 match(Set dst (PowD src0 src1)); // Raise src0 to the src1'th power
10446 effect(KILL tmp1, KILL rax, KILL rbx, KILL rcx );
10447 format %{ "SUB ESP,8\t\t# Fast-path POW encoding\n\t"
10448 "MOVSD [ESP],$src1\n\t"
10449 "FLD FPR1,$src1\n\t"
10450 "MOVSD [ESP],$src0\n\t"
10451 "FLD FPR1,$src0\n\t"
10452 "FYL2X \t\t\t# Q=Y*ln2(X)\n\t"
10453
10454 "FDUP \t\t\t# Q Q\n\t"
10455 "FRNDINT\t\t\t# int(Q) Q\n\t"
10456 "FSUB ST(1),ST(0)\t# int(Q) frac(Q)\n\t"
10457 "FISTP dword [ESP]\n\t"
10458 "F2XM1 \t\t\t# 2^frac(Q)-1 int(Q)\n\t"
10459 "FLD1 \t\t\t# 1 2^frac(Q)-1 int(Q)\n\t"
10460 "FADDP \t\t\t# 2^frac(Q) int(Q)\n\t" // could use FADD [1.000] instead
10461 "MOV EAX,[ESP]\t# Pick up int(Q)\n\t"
10462 "MOV ECX,0xFFFFF800\t# Overflow mask\n\t"
10463 "ADD EAX,1023\t\t# Double exponent bias\n\t"
10464 "MOV EBX,EAX\t\t# Preshifted biased expo\n\t"
10465 "SHL EAX,20\t\t# Shift exponent into place\n\t"
10466 "TEST EBX,ECX\t\t# Check for overflow\n\t"
10467 "CMOVne EAX,ECX\t\t# If overflow, stuff NaN into EAX\n\t"
10468 "MOV [ESP+4],EAX\t# Marshal 64-bit scaling double\n\t"
10469 "MOV [ESP+0],0\n\t"
10470 "FMUL ST(0),[ESP+0]\t# Scale\n\t"
10471
10472 "FST_D [ESP]\n\t"
10473 "MOVSD $dst,[ESP]\n\t"
10474 "ADD ESP,8"
10475 %}
10476 ins_encode( push_stack_temp_qword,
10477 push_xmm_to_fpr1(src1),
10478 push_xmm_to_fpr1(src0),
10479 Opcode(0xD9), Opcode(0xF1), // fyl2x
10480 pow_exp_core_encoding,
10481 Push_ResultXD(dst) );
10482 ins_pipe( pipe_slow );
10483 %}
10484
10485
10486 instruct expD_reg(regDPR1 dpr1, eAXRegI rax, eBXRegI rbx, eCXRegI rcx) %{
10487 predicate (UseSSE<=1);
10488 match(Set dpr1 (ExpD dpr1));
10489 effect(KILL rax, KILL rbx, KILL rcx);
10490 format %{ "SUB ESP,8\t\t# Fast-path EXP encoding"
10491 "FLDL2E \t\t\t# Ld log2(e) X\n\t"
10492 "FMULP \t\t\t# Q=X*log2(e)\n\t"
10493
10494 "FDUP \t\t\t# Q Q\n\t"
10495 "FRNDINT\t\t\t# int(Q) Q\n\t"
10496 "FSUB ST(1),ST(0)\t# int(Q) frac(Q)\n\t"
10497 "FISTP dword [ESP]\n\t"
10498 "F2XM1 \t\t\t# 2^frac(Q)-1 int(Q)\n\t"
10499 "FLD1 \t\t\t# 1 2^frac(Q)-1 int(Q)\n\t"
10500 "FADDP \t\t\t# 2^frac(Q) int(Q)\n\t" // could use FADD [1.000] instead
10501 "MOV EAX,[ESP]\t# Pick up int(Q)\n\t"
10502 "MOV ECX,0xFFFFF800\t# Overflow mask\n\t"
10503 "ADD EAX,1023\t\t# Double exponent bias\n\t"
10504 "MOV EBX,EAX\t\t# Preshifted biased expo\n\t"
10505 "SHL EAX,20\t\t# Shift exponent into place\n\t"
10506 "TEST EBX,ECX\t\t# Check for overflow\n\t"
10507 "CMOVne EAX,ECX\t\t# If overflow, stuff NaN into EAX\n\t"
10508 "MOV [ESP+4],EAX\t# Marshal 64-bit scaling double\n\t"
10509 "MOV [ESP+0],0\n\t"
10510 "FMUL ST(0),[ESP+0]\t# Scale\n\t"
10511
10512 "ADD ESP,8"
10513 %}
10514 ins_encode( push_stack_temp_qword,
10515 Opcode(0xD9), Opcode(0xEA), // fldl2e
10516 Opcode(0xDE), Opcode(0xC9), // fmulp
10517 pow_exp_core_encoding,
10518 pop_stack_temp_qword);
10519 ins_pipe( pipe_slow );
10520 %}
10521
10522 instruct expXD_reg(regXD dst, regXD src, regDPR1 tmp1, eAXRegI rax, eBXRegI rbx, eCXRegI rcx) %{
10523 predicate (UseSSE>=2);
10524 match(Set dst (ExpD src));
10525 effect(KILL tmp1, KILL rax, KILL rbx, KILL rcx);
10526 format %{ "SUB ESP,8\t\t# Fast-path EXP encoding\n\t"
10527 "MOVSD [ESP],$src\n\t"
10528 "FLDL2E \t\t\t# Ld log2(e) X\n\t"
10529 "FMULP \t\t\t# Q=X*log2(e) X\n\t"
10530
10531 "FDUP \t\t\t# Q Q\n\t"
10532 "FRNDINT\t\t\t# int(Q) Q\n\t"
10533 "FSUB ST(1),ST(0)\t# int(Q) frac(Q)\n\t"
10534 "FISTP dword [ESP]\n\t"
10535 "F2XM1 \t\t\t# 2^frac(Q)-1 int(Q)\n\t"
10536 "FLD1 \t\t\t# 1 2^frac(Q)-1 int(Q)\n\t"
10537 "FADDP \t\t\t# 2^frac(Q) int(Q)\n\t" // could use FADD [1.000] instead
10538 "MOV EAX,[ESP]\t# Pick up int(Q)\n\t"
10539 "MOV ECX,0xFFFFF800\t# Overflow mask\n\t"
10540 "ADD EAX,1023\t\t# Double exponent bias\n\t"
10541 "MOV EBX,EAX\t\t# Preshifted biased expo\n\t"
10542 "SHL EAX,20\t\t# Shift exponent into place\n\t"
10543 "TEST EBX,ECX\t\t# Check for overflow\n\t"
10544 "CMOVne EAX,ECX\t\t# If overflow, stuff NaN into EAX\n\t"
10545 "MOV [ESP+4],EAX\t# Marshal 64-bit scaling double\n\t"
10546 "MOV [ESP+0],0\n\t"
10547 "FMUL ST(0),[ESP+0]\t# Scale\n\t"
10548
10549 "FST_D [ESP]\n\t"
10550 "MOVSD $dst,[ESP]\n\t"
10551 "ADD ESP,8"
10552 %}
10553 ins_encode( Push_SrcXD(src),
10554 Opcode(0xD9), Opcode(0xEA), // fldl2e
10555 Opcode(0xDE), Opcode(0xC9), // fmulp
10556 pow_exp_core_encoding,
10557 Push_ResultXD(dst) );
10558 ins_pipe( pipe_slow );
10559 %}
10560
10561
10562
10563 instruct log10D_reg(regDPR1 dst, regDPR1 src) %{
10564 predicate (UseSSE<=1);
10565 // The source Double operand on FPU stack
10566 match(Set dst (Log10D src));
10567 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number
10568 // fxch ; swap ST(0) with ST(1)
10569 // fyl2x ; compute log_10(2) * log_2(x)
10570 format %{ "FLDLG2 \t\t\t#Log10\n\t"
10571 "FXCH \n\t"
10572 "FYL2X \t\t\t# Q=Log10*Log_2(x)"
10573 %}
10574 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2
10575 Opcode(0xD9), Opcode(0xC9), // fxch
10576 Opcode(0xD9), Opcode(0xF1)); // fyl2x
10577
10578 ins_pipe( pipe_slow );
10579 %}
10580
10581 instruct log10XD_reg(regXD dst, regXD src, eFlagsReg cr) %{
10582 predicate (UseSSE>=2);
10583 effect(KILL cr);
10584 match(Set dst (Log10D src));
10585 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number
10586 // fyl2x ; compute log_10(2) * log_2(x)
10587 format %{ "FLDLG2 \t\t\t#Log10\n\t"
10588 "FYL2X \t\t\t# Q=Log10*Log_2(x)"
10589 %}
10590 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2
10591 Push_SrcXD(src),
10592 Opcode(0xD9), Opcode(0xF1), // fyl2x
10593 Push_ResultXD(dst));
10594
10595 ins_pipe( pipe_slow );
10596 %}
10597
10598 instruct logD_reg(regDPR1 dst, regDPR1 src) %{
10599 predicate (UseSSE<=1);
10600 // The source Double operand on FPU stack
10601 match(Set dst (LogD src));
10602 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number
10603 // fxch ; swap ST(0) with ST(1)
10604 // fyl2x ; compute log_e(2) * log_2(x)
10605 format %{ "FLDLN2 \t\t\t#Log_e\n\t"
10606 "FXCH \n\t"
10607 "FYL2X \t\t\t# Q=Log_e*Log_2(x)"
10608 %}
10609 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2
10610 Opcode(0xD9), Opcode(0xC9), // fxch
10611 Opcode(0xD9), Opcode(0xF1)); // fyl2x
10612
10613 ins_pipe( pipe_slow );
10614 %}
10615
10616 instruct logXD_reg(regXD dst, regXD src, eFlagsReg cr) %{
10617 predicate (UseSSE>=2);
10618 effect(KILL cr);
10619 // The source and result Double operands in XMM registers
10620 match(Set dst (LogD src));
10621 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number
10622 // fyl2x ; compute log_e(2) * log_2(x)
10623 format %{ "FLDLN2 \t\t\t#Log_e\n\t"
10624 "FYL2X \t\t\t# Q=Log_e*Log_2(x)"
10625 %}
10626 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2
10627 Push_SrcXD(src),
10628 Opcode(0xD9), Opcode(0xF1), // fyl2x
10629 Push_ResultXD(dst));
10630 ins_pipe( pipe_slow );
10631 %}
10632
10633 //-------------Float Instructions-------------------------------
10634 // Float Math
10635
10636 // Code for float compare:
10637 // fcompp();
10638 // fwait(); fnstsw_ax();
10639 // sahf();
10640 // movl(dst, unordered_result);
10641 // jcc(Assembler::parity, exit);
10642 // movl(dst, less_result);
10643 // jcc(Assembler::below, exit);
10644 // movl(dst, equal_result);
10645 // jcc(Assembler::equal, exit);
10646 // movl(dst, greater_result);
10647 // exit:
10648
10649 // P6 version of float compare, sets condition codes in EFLAGS
10650 instruct cmpF_cc_P6(eFlagsRegU cr, regF src1, regF src2, eAXRegI rax) %{
10651 predicate(VM_Version::supports_cmov() && UseSSE == 0);
10652 match(Set cr (CmpF src1 src2));
10653 effect(KILL rax);
10654 ins_cost(150);
10655 format %{ "FLD $src1\n\t"
10656 "FUCOMIP ST,$src2 // P6 instruction\n\t"
10657 "JNP exit\n\t"
10658 "MOV ah,1 // saw a NaN, set CF (treat as LT)\n\t"
10659 "SAHF\n"
10660 "exit:\tNOP // avoid branch to branch" %}
10661 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
10662 ins_encode( Push_Reg_D(src1),
10663 OpcP, RegOpc(src2),
10664 cmpF_P6_fixup );
10665 ins_pipe( pipe_slow );
10666 %}
10667
10668 instruct cmpF_cc_P6CF(eFlagsRegUCF cr, regF src1, regF src2) %{
10669 predicate(VM_Version::supports_cmov() && UseSSE == 0);
10670 match(Set cr (CmpF src1 src2));
10671 ins_cost(100);
10672 format %{ "FLD $src1\n\t"
10673 "FUCOMIP ST,$src2 // P6 instruction" %}
10674 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
10675 ins_encode( Push_Reg_D(src1),
10676 OpcP, RegOpc(src2));
10677 ins_pipe( pipe_slow );
10678 %}
10679
10680
10681 // Compare & branch
10682 instruct cmpF_cc(eFlagsRegU cr, regF src1, regF src2, eAXRegI rax) %{
10683 predicate(UseSSE == 0);
10684 match(Set cr (CmpF src1 src2));
10685 effect(KILL rax);
10686 ins_cost(200);
10687 format %{ "FLD $src1\n\t"
10688 "FCOMp $src2\n\t"
10689 "FNSTSW AX\n\t"
10690 "TEST AX,0x400\n\t"
10691 "JZ,s flags\n\t"
10692 "MOV AH,1\t# unordered treat as LT\n"
10693 "flags:\tSAHF" %}
10694 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
10695 ins_encode( Push_Reg_D(src1),
10696 OpcP, RegOpc(src2),
10697 fpu_flags);
10698 ins_pipe( pipe_slow );
10699 %}
10700
10701 // Compare vs zero into -1,0,1
10702 instruct cmpF_0(eRegI dst, regF src1, immF0 zero, eAXRegI rax, eFlagsReg cr) %{
10703 predicate(UseSSE == 0);
10704 match(Set dst (CmpF3 src1 zero));
10705 effect(KILL cr, KILL rax);
10706 ins_cost(280);
10707 format %{ "FTSTF $dst,$src1" %}
10708 opcode(0xE4, 0xD9);
10709 ins_encode( Push_Reg_D(src1),
10710 OpcS, OpcP, PopFPU,
10711 CmpF_Result(dst));
10712 ins_pipe( pipe_slow );
10713 %}
10714
10715 // Compare into -1,0,1
10716 instruct cmpF_reg(eRegI dst, regF src1, regF src2, eAXRegI rax, eFlagsReg cr) %{
10717 predicate(UseSSE == 0);
10718 match(Set dst (CmpF3 src1 src2));
10719 effect(KILL cr, KILL rax);
10720 ins_cost(300);
10721 format %{ "FCMPF $dst,$src1,$src2" %}
10722 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
10723 ins_encode( Push_Reg_D(src1),
10724 OpcP, RegOpc(src2),
10725 CmpF_Result(dst));
10726 ins_pipe( pipe_slow );
10727 %}
10728
10729 // float compare and set condition codes in EFLAGS by XMM regs
10730 instruct cmpX_cc(eFlagsRegU cr, regX dst, regX src, eAXRegI rax) %{
10731 predicate(UseSSE>=1);
10732 match(Set cr (CmpF dst src));
10733 effect(KILL rax);
10734 ins_cost(145);
10735 format %{ "COMISS $dst,$src\n"
10736 "\tJNP exit\n"
10737 "\tMOV ah,1 // saw a NaN, set CF\n"
10738 "\tSAHF\n"
10739 "exit:\tNOP // avoid branch to branch" %}
10740 opcode(0x0F, 0x2F);
10741 ins_encode(OpcP, OpcS, RegReg(dst, src), cmpF_P6_fixup);
10742 ins_pipe( pipe_slow );
10743 %}
10744
10745 instruct cmpX_ccCF(eFlagsRegUCF cr, regX dst, regX src) %{
10746 predicate(UseSSE>=1);
10747 match(Set cr (CmpF dst src));
10748 ins_cost(100);
10749 format %{ "COMISS $dst,$src" %}
10750 opcode(0x0F, 0x2F);
10751 ins_encode(OpcP, OpcS, RegReg(dst, src));
10752 ins_pipe( pipe_slow );
10753 %}
10754
10755 // float compare and set condition codes in EFLAGS by XMM regs
10756 instruct cmpX_ccmem(eFlagsRegU cr, regX dst, memory src, eAXRegI rax) %{
10757 predicate(UseSSE>=1);
10758 match(Set cr (CmpF dst (LoadF src)));
10759 effect(KILL rax);
10760 ins_cost(165);
10761 format %{ "COMISS $dst,$src\n"
10762 "\tJNP exit\n"
10763 "\tMOV ah,1 // saw a NaN, set CF\n"
10764 "\tSAHF\n"
10765 "exit:\tNOP // avoid branch to branch" %}
10766 opcode(0x0F, 0x2F);
10767 ins_encode(OpcP, OpcS, RegMem(dst, src), cmpF_P6_fixup);
10768 ins_pipe( pipe_slow );
10769 %}
10770
10771 instruct cmpX_ccmemCF(eFlagsRegUCF cr, regX dst, memory src) %{
10772 predicate(UseSSE>=1);
10773 match(Set cr (CmpF dst (LoadF src)));
10774 ins_cost(100);
10775 format %{ "COMISS $dst,$src" %}
10776 opcode(0x0F, 0x2F);
10777 ins_encode(OpcP, OpcS, RegMem(dst, src));
10778 ins_pipe( pipe_slow );
10779 %}
10780
10781 // Compare into -1,0,1 in XMM
10782 instruct cmpX_reg(eRegI dst, regX src1, regX src2, eFlagsReg cr) %{
10783 predicate(UseSSE>=1);
10784 match(Set dst (CmpF3 src1 src2));
10785 effect(KILL cr);
10786 ins_cost(255);
10787 format %{ "XOR $dst,$dst\n"
10788 "\tCOMISS $src1,$src2\n"
10789 "\tJP,s nan\n"
10790 "\tJEQ,s exit\n"
10791 "\tJA,s inc\n"
10792 "nan:\tDEC $dst\n"
10793 "\tJMP,s exit\n"
10794 "inc:\tINC $dst\n"
10795 "exit:"
10796 %}
10797 opcode(0x0F, 0x2F);
10798 ins_encode(Xor_Reg(dst), OpcP, OpcS, RegReg(src1, src2), CmpX_Result(dst));
10799 ins_pipe( pipe_slow );
10800 %}
10801
10802 // Compare into -1,0,1 in XMM and memory
10803 instruct cmpX_regmem(eRegI dst, regX src1, memory mem, eFlagsReg cr) %{
10804 predicate(UseSSE>=1);
10805 match(Set dst (CmpF3 src1 (LoadF mem)));
10806 effect(KILL cr);
10807 ins_cost(275);
10808 format %{ "COMISS $src1,$mem\n"
10809 "\tMOV $dst,0\t\t# do not blow flags\n"
10810 "\tJP,s nan\n"
10811 "\tJEQ,s exit\n"
10812 "\tJA,s inc\n"
10813 "nan:\tDEC $dst\n"
10814 "\tJMP,s exit\n"
10815 "inc:\tINC $dst\n"
10816 "exit:"
10817 %}
10818 opcode(0x0F, 0x2F);
10819 ins_encode(OpcP, OpcS, RegMem(src1, mem), LdImmI(dst,0x0), CmpX_Result(dst));
10820 ins_pipe( pipe_slow );
10821 %}
10822
10823 // Spill to obtain 24-bit precision
10824 instruct subF24_reg(stackSlotF dst, regF src1, regF src2) %{
10825 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10826 match(Set dst (SubF src1 src2));
10827
10828 format %{ "FSUB $dst,$src1 - $src2" %}
10829 opcode(0xD8, 0x4); /* D8 E0+i or D8 /4 mod==0x3 ;; result in TOS */
10830 ins_encode( Push_Reg_F(src1),
10831 OpcReg_F(src2),
10832 Pop_Mem_F(dst) );
10833 ins_pipe( fpu_mem_reg_reg );
10834 %}
10835 //
10836 // This instruction does not round to 24-bits
10837 instruct subF_reg(regF dst, regF src) %{
10838 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10839 match(Set dst (SubF dst src));
10840
10841 format %{ "FSUB $dst,$src" %}
10842 opcode(0xDE, 0x5); /* DE E8+i or DE /5 */
10843 ins_encode( Push_Reg_F(src),
10844 OpcP, RegOpc(dst) );
10845 ins_pipe( fpu_reg_reg );
10846 %}
10847
10848 // Spill to obtain 24-bit precision
10849 instruct addF24_reg(stackSlotF dst, regF src1, regF src2) %{
10850 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10851 match(Set dst (AddF src1 src2));
10852
10853 format %{ "FADD $dst,$src1,$src2" %}
10854 opcode(0xD8, 0x0); /* D8 C0+i */
10855 ins_encode( Push_Reg_F(src2),
10856 OpcReg_F(src1),
10857 Pop_Mem_F(dst) );
10858 ins_pipe( fpu_mem_reg_reg );
10859 %}
10860 //
10861 // This instruction does not round to 24-bits
10862 instruct addF_reg(regF dst, regF src) %{
10863 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10864 match(Set dst (AddF dst src));
10865
10866 format %{ "FLD $src\n\t"
10867 "FADDp $dst,ST" %}
10868 opcode(0xDE, 0x0); /* DE C0+i or DE /0*/
10869 ins_encode( Push_Reg_F(src),
10870 OpcP, RegOpc(dst) );
10871 ins_pipe( fpu_reg_reg );
10872 %}
10873
10874 // Add two single precision floating point values in xmm
10875 instruct addX_reg(regX dst, regX src) %{
10876 predicate(UseSSE>=1);
10877 match(Set dst (AddF dst src));
10878 format %{ "ADDSS $dst,$src" %}
10879 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x58), RegReg(dst, src));
10880 ins_pipe( pipe_slow );
10881 %}
10882
10883 instruct addX_imm(regX dst, immXF con) %{
10884 predicate(UseSSE>=1);
10885 match(Set dst (AddF dst con));
10886 format %{ "ADDSS $dst,[$con]" %}
10887 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x58), LdImmX(dst, con) );
10888 ins_pipe( pipe_slow );
10889 %}
10890
10891 instruct addX_mem(regX dst, memory mem) %{
10892 predicate(UseSSE>=1);
10893 match(Set dst (AddF dst (LoadF mem)));
10894 format %{ "ADDSS $dst,$mem" %}
10895 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x58), RegMem(dst, mem));
10896 ins_pipe( pipe_slow );
10897 %}
10898
10899 // Subtract two single precision floating point values in xmm
10900 instruct subX_reg(regX dst, regX src) %{
10901 predicate(UseSSE>=1);
10902 match(Set dst (SubF dst src));
10903 format %{ "SUBSS $dst,$src" %}
10904 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5C), RegReg(dst, src));
10905 ins_pipe( pipe_slow );
10906 %}
10907
10908 instruct subX_imm(regX dst, immXF con) %{
10909 predicate(UseSSE>=1);
10910 match(Set dst (SubF dst con));
10911 format %{ "SUBSS $dst,[$con]" %}
10912 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5C), LdImmX(dst, con) );
10913 ins_pipe( pipe_slow );
10914 %}
10915
10916 instruct subX_mem(regX dst, memory mem) %{
10917 predicate(UseSSE>=1);
10918 match(Set dst (SubF dst (LoadF mem)));
10919 format %{ "SUBSS $dst,$mem" %}
10920 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5C), RegMem(dst,mem));
10921 ins_pipe( pipe_slow );
10922 %}
10923
10924 // Multiply two single precision floating point values in xmm
10925 instruct mulX_reg(regX dst, regX src) %{
10926 predicate(UseSSE>=1);
10927 match(Set dst (MulF dst src));
10928 format %{ "MULSS $dst,$src" %}
10929 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x59), RegReg(dst, src));
10930 ins_pipe( pipe_slow );
10931 %}
10932
10933 instruct mulX_imm(regX dst, immXF con) %{
10934 predicate(UseSSE>=1);
10935 match(Set dst (MulF dst con));
10936 format %{ "MULSS $dst,[$con]" %}
10937 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x59), LdImmX(dst, con) );
10938 ins_pipe( pipe_slow );
10939 %}
10940
10941 instruct mulX_mem(regX dst, memory mem) %{
10942 predicate(UseSSE>=1);
10943 match(Set dst (MulF dst (LoadF mem)));
10944 format %{ "MULSS $dst,$mem" %}
10945 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x59), RegMem(dst,mem));
10946 ins_pipe( pipe_slow );
10947 %}
10948
10949 // Divide two single precision floating point values in xmm
10950 instruct divX_reg(regX dst, regX src) %{
10951 predicate(UseSSE>=1);
10952 match(Set dst (DivF dst src));
10953 format %{ "DIVSS $dst,$src" %}
10954 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5E), RegReg(dst, src));
10955 ins_pipe( pipe_slow );
10956 %}
10957
10958 instruct divX_imm(regX dst, immXF con) %{
10959 predicate(UseSSE>=1);
10960 match(Set dst (DivF dst con));
10961 format %{ "DIVSS $dst,[$con]" %}
10962 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5E), LdImmX(dst, con) );
10963 ins_pipe( pipe_slow );
10964 %}
10965
10966 instruct divX_mem(regX dst, memory mem) %{
10967 predicate(UseSSE>=1);
10968 match(Set dst (DivF dst (LoadF mem)));
10969 format %{ "DIVSS $dst,$mem" %}
10970 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5E), RegMem(dst,mem));
10971 ins_pipe( pipe_slow );
10972 %}
10973
10974 // Get the square root of a single precision floating point values in xmm
10975 instruct sqrtX_reg(regX dst, regX src) %{
10976 predicate(UseSSE>=1);
10977 match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
10978 format %{ "SQRTSS $dst,$src" %}
10979 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x51), RegReg(dst, src));
10980 ins_pipe( pipe_slow );
10981 %}
10982
10983 instruct sqrtX_mem(regX dst, memory mem) %{
10984 predicate(UseSSE>=1);
10985 match(Set dst (ConvD2F (SqrtD (ConvF2D (LoadF mem)))));
10986 format %{ "SQRTSS $dst,$mem" %}
10987 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x51), RegMem(dst, mem));
10988 ins_pipe( pipe_slow );
10989 %}
10990
10991 // Get the square root of a double precision floating point values in xmm
10992 instruct sqrtXD_reg(regXD dst, regXD src) %{
10993 predicate(UseSSE>=2);
10994 match(Set dst (SqrtD src));
10995 format %{ "SQRTSD $dst,$src" %}
10996 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x51), RegReg(dst, src));
10997 ins_pipe( pipe_slow );
10998 %}
10999
11000 instruct sqrtXD_mem(regXD dst, memory mem) %{
11001 predicate(UseSSE>=2);
11002 match(Set dst (SqrtD (LoadD mem)));
11003 format %{ "SQRTSD $dst,$mem" %}
11004 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x51), RegMem(dst, mem));
11005 ins_pipe( pipe_slow );
11006 %}
11007
11008 instruct absF_reg(regFPR1 dst, regFPR1 src) %{
11009 predicate(UseSSE==0);
11010 match(Set dst (AbsF src));
11011 ins_cost(100);
11012 format %{ "FABS" %}
11013 opcode(0xE1, 0xD9);
11014 ins_encode( OpcS, OpcP );
11015 ins_pipe( fpu_reg_reg );
11016 %}
11017
11018 instruct absX_reg(regX dst ) %{
11019 predicate(UseSSE>=1);
11020 match(Set dst (AbsF dst));
11021 format %{ "ANDPS $dst,[0x7FFFFFFF]\t# ABS F by sign masking" %}
11022 ins_encode( AbsXF_encoding(dst));
11023 ins_pipe( pipe_slow );
11024 %}
11025
11026 instruct negF_reg(regFPR1 dst, regFPR1 src) %{
11027 predicate(UseSSE==0);
11028 match(Set dst (NegF src));
11029 ins_cost(100);
11030 format %{ "FCHS" %}
11031 opcode(0xE0, 0xD9);
11032 ins_encode( OpcS, OpcP );
11033 ins_pipe( fpu_reg_reg );
11034 %}
11035
11036 instruct negX_reg( regX dst ) %{
11037 predicate(UseSSE>=1);
11038 match(Set dst (NegF dst));
11039 format %{ "XORPS $dst,[0x80000000]\t# CHS F by sign flipping" %}
11040 ins_encode( NegXF_encoding(dst));
11041 ins_pipe( pipe_slow );
11042 %}
11043
11044 // Cisc-alternate to addF_reg
11045 // Spill to obtain 24-bit precision
11046 instruct addF24_reg_mem(stackSlotF dst, regF src1, memory src2) %{
11047 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11048 match(Set dst (AddF src1 (LoadF src2)));
11049
11050 format %{ "FLD $src2\n\t"
11051 "FADD ST,$src1\n\t"
11052 "FSTP_S $dst" %}
11053 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
11054 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
11055 OpcReg_F(src1),
11056 Pop_Mem_F(dst) );
11057 ins_pipe( fpu_mem_reg_mem );
11058 %}
11059 //
11060 // Cisc-alternate to addF_reg
11061 // This instruction does not round to 24-bits
11062 instruct addF_reg_mem(regF dst, memory src) %{
11063 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11064 match(Set dst (AddF dst (LoadF src)));
11065
11066 format %{ "FADD $dst,$src" %}
11067 opcode(0xDE, 0x0, 0xD9); /* DE C0+i or DE /0*/ /* LoadF D9 /0 */
11068 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
11069 OpcP, RegOpc(dst) );
11070 ins_pipe( fpu_reg_mem );
11071 %}
11072
11073 // // Following two instructions for _222_mpegaudio
11074 // Spill to obtain 24-bit precision
11075 instruct addF24_mem_reg(stackSlotF dst, regF src2, memory src1 ) %{
11076 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11077 match(Set dst (AddF src1 src2));
11078
11079 format %{ "FADD $dst,$src1,$src2" %}
11080 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
11081 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src1),
11082 OpcReg_F(src2),
11083 Pop_Mem_F(dst) );
11084 ins_pipe( fpu_mem_reg_mem );
11085 %}
11086
11087 // Cisc-spill variant
11088 // Spill to obtain 24-bit precision
11089 instruct addF24_mem_cisc(stackSlotF dst, memory src1, memory src2) %{
11090 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11091 match(Set dst (AddF src1 (LoadF src2)));
11092
11093 format %{ "FADD $dst,$src1,$src2 cisc" %}
11094 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
11095 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
11096 set_instruction_start,
11097 OpcP, RMopc_Mem(secondary,src1),
11098 Pop_Mem_F(dst) );
11099 ins_pipe( fpu_mem_mem_mem );
11100 %}
11101
11102 // Spill to obtain 24-bit precision
11103 instruct addF24_mem_mem(stackSlotF dst, memory src1, memory src2) %{
11104 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11105 match(Set dst (AddF src1 src2));
11106
11107 format %{ "FADD $dst,$src1,$src2" %}
11108 opcode(0xD8, 0x0, 0xD9); /* D8 /0 */ /* LoadF D9 /0 */
11109 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
11110 set_instruction_start,
11111 OpcP, RMopc_Mem(secondary,src1),
11112 Pop_Mem_F(dst) );
11113 ins_pipe( fpu_mem_mem_mem );
11114 %}
11115
11116
11117 // Spill to obtain 24-bit precision
11118 instruct addF24_reg_imm(stackSlotF dst, regF src1, immF src2) %{
11119 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11120 match(Set dst (AddF src1 src2));
11121 format %{ "FLD $src1\n\t"
11122 "FADD $src2\n\t"
11123 "FSTP_S $dst" %}
11124 opcode(0xD8, 0x00); /* D8 /0 */
11125 ins_encode( Push_Reg_F(src1),
11126 Opc_MemImm_F(src2),
11127 Pop_Mem_F(dst));
11128 ins_pipe( fpu_mem_reg_con );
11129 %}
11130 //
11131 // This instruction does not round to 24-bits
11132 instruct addF_reg_imm(regF dst, regF src1, immF src2) %{
11133 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11134 match(Set dst (AddF src1 src2));
11135 format %{ "FLD $src1\n\t"
11136 "FADD $src2\n\t"
11137 "FSTP_S $dst" %}
11138 opcode(0xD8, 0x00); /* D8 /0 */
11139 ins_encode( Push_Reg_F(src1),
11140 Opc_MemImm_F(src2),
11141 Pop_Reg_F(dst));
11142 ins_pipe( fpu_reg_reg_con );
11143 %}
11144
11145 // Spill to obtain 24-bit precision
11146 instruct mulF24_reg(stackSlotF dst, regF src1, regF src2) %{
11147 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11148 match(Set dst (MulF src1 src2));
11149
11150 format %{ "FLD $src1\n\t"
11151 "FMUL $src2\n\t"
11152 "FSTP_S $dst" %}
11153 opcode(0xD8, 0x1); /* D8 C8+i or D8 /1 ;; result in TOS */
11154 ins_encode( Push_Reg_F(src1),
11155 OpcReg_F(src2),
11156 Pop_Mem_F(dst) );
11157 ins_pipe( fpu_mem_reg_reg );
11158 %}
11159 //
11160 // This instruction does not round to 24-bits
11161 instruct mulF_reg(regF dst, regF src1, regF src2) %{
11162 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11163 match(Set dst (MulF src1 src2));
11164
11165 format %{ "FLD $src1\n\t"
11166 "FMUL $src2\n\t"
11167 "FSTP_S $dst" %}
11168 opcode(0xD8, 0x1); /* D8 C8+i */
11169 ins_encode( Push_Reg_F(src2),
11170 OpcReg_F(src1),
11171 Pop_Reg_F(dst) );
11172 ins_pipe( fpu_reg_reg_reg );
11173 %}
11174
11175
11176 // Spill to obtain 24-bit precision
11177 // Cisc-alternate to reg-reg multiply
11178 instruct mulF24_reg_mem(stackSlotF dst, regF src1, memory src2) %{
11179 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11180 match(Set dst (MulF src1 (LoadF src2)));
11181
11182 format %{ "FLD_S $src2\n\t"
11183 "FMUL $src1\n\t"
11184 "FSTP_S $dst" %}
11185 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or DE /1*/ /* LoadF D9 /0 */
11186 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
11187 OpcReg_F(src1),
11188 Pop_Mem_F(dst) );
11189 ins_pipe( fpu_mem_reg_mem );
11190 %}
11191 //
11192 // This instruction does not round to 24-bits
11193 // Cisc-alternate to reg-reg multiply
11194 instruct mulF_reg_mem(regF dst, regF src1, memory src2) %{
11195 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11196 match(Set dst (MulF src1 (LoadF src2)));
11197
11198 format %{ "FMUL $dst,$src1,$src2" %}
11199 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */ /* LoadF D9 /0 */
11200 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
11201 OpcReg_F(src1),
11202 Pop_Reg_F(dst) );
11203 ins_pipe( fpu_reg_reg_mem );
11204 %}
11205
11206 // Spill to obtain 24-bit precision
11207 instruct mulF24_mem_mem(stackSlotF dst, memory src1, memory src2) %{
11208 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11209 match(Set dst (MulF src1 src2));
11210
11211 format %{ "FMUL $dst,$src1,$src2" %}
11212 opcode(0xD8, 0x1, 0xD9); /* D8 /1 */ /* LoadF D9 /0 */
11213 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
11214 set_instruction_start,
11215 OpcP, RMopc_Mem(secondary,src1),
11216 Pop_Mem_F(dst) );
11217 ins_pipe( fpu_mem_mem_mem );
11218 %}
11219
11220 // Spill to obtain 24-bit precision
11221 instruct mulF24_reg_imm(stackSlotF dst, regF src1, immF src2) %{
11222 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11223 match(Set dst (MulF src1 src2));
11224
11225 format %{ "FMULc $dst,$src1,$src2" %}
11226 opcode(0xD8, 0x1); /* D8 /1*/
11227 ins_encode( Push_Reg_F(src1),
11228 Opc_MemImm_F(src2),
11229 Pop_Mem_F(dst));
11230 ins_pipe( fpu_mem_reg_con );
11231 %}
11232 //
11233 // This instruction does not round to 24-bits
11234 instruct mulF_reg_imm(regF dst, regF src1, immF src2) %{
11235 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11236 match(Set dst (MulF src1 src2));
11237
11238 format %{ "FMULc $dst. $src1, $src2" %}
11239 opcode(0xD8, 0x1); /* D8 /1*/
11240 ins_encode( Push_Reg_F(src1),
11241 Opc_MemImm_F(src2),
11242 Pop_Reg_F(dst));
11243 ins_pipe( fpu_reg_reg_con );
11244 %}
11245
11246
11247 //
11248 // MACRO1 -- subsume unshared load into mulF
11249 // This instruction does not round to 24-bits
11250 instruct mulF_reg_load1(regF dst, regF src, memory mem1 ) %{
11251 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11252 match(Set dst (MulF (LoadF mem1) src));
11253
11254 format %{ "FLD $mem1 ===MACRO1===\n\t"
11255 "FMUL ST,$src\n\t"
11256 "FSTP $dst" %}
11257 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or D8 /1 */ /* LoadF D9 /0 */
11258 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem1),
11259 OpcReg_F(src),
11260 Pop_Reg_F(dst) );
11261 ins_pipe( fpu_reg_reg_mem );
11262 %}
11263 //
11264 // MACRO2 -- addF a mulF which subsumed an unshared load
11265 // This instruction does not round to 24-bits
11266 instruct addF_mulF_reg_load1(regF dst, memory mem1, regF src1, regF src2) %{
11267 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11268 match(Set dst (AddF (MulF (LoadF mem1) src1) src2));
11269 ins_cost(95);
11270
11271 format %{ "FLD $mem1 ===MACRO2===\n\t"
11272 "FMUL ST,$src1 subsume mulF left load\n\t"
11273 "FADD ST,$src2\n\t"
11274 "FSTP $dst" %}
11275 opcode(0xD9); /* LoadF D9 /0 */
11276 ins_encode( OpcP, RMopc_Mem(0x00,mem1),
11277 FMul_ST_reg(src1),
11278 FAdd_ST_reg(src2),
11279 Pop_Reg_F(dst) );
11280 ins_pipe( fpu_reg_mem_reg_reg );
11281 %}
11282
11283 // MACRO3 -- addF a mulF
11284 // This instruction does not round to 24-bits. It is a '2-address'
11285 // instruction in that the result goes back to src2. This eliminates
11286 // a move from the macro; possibly the register allocator will have
11287 // to add it back (and maybe not).
11288 instruct addF_mulF_reg(regF src2, regF src1, regF src0) %{
11289 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11290 match(Set src2 (AddF (MulF src0 src1) src2));
11291
11292 format %{ "FLD $src0 ===MACRO3===\n\t"
11293 "FMUL ST,$src1\n\t"
11294 "FADDP $src2,ST" %}
11295 opcode(0xD9); /* LoadF D9 /0 */
11296 ins_encode( Push_Reg_F(src0),
11297 FMul_ST_reg(src1),
11298 FAddP_reg_ST(src2) );
11299 ins_pipe( fpu_reg_reg_reg );
11300 %}
11301
11302 // MACRO4 -- divF subF
11303 // This instruction does not round to 24-bits
11304 instruct subF_divF_reg(regF dst, regF src1, regF src2, regF src3) %{
11305 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11306 match(Set dst (DivF (SubF src2 src1) src3));
11307
11308 format %{ "FLD $src2 ===MACRO4===\n\t"
11309 "FSUB ST,$src1\n\t"
11310 "FDIV ST,$src3\n\t"
11311 "FSTP $dst" %}
11312 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
11313 ins_encode( Push_Reg_F(src2),
11314 subF_divF_encode(src1,src3),
11315 Pop_Reg_F(dst) );
11316 ins_pipe( fpu_reg_reg_reg_reg );
11317 %}
11318
11319 // Spill to obtain 24-bit precision
11320 instruct divF24_reg(stackSlotF dst, regF src1, regF src2) %{
11321 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11322 match(Set dst (DivF src1 src2));
11323
11324 format %{ "FDIV $dst,$src1,$src2" %}
11325 opcode(0xD8, 0x6); /* D8 F0+i or DE /6*/
11326 ins_encode( Push_Reg_F(src1),
11327 OpcReg_F(src2),
11328 Pop_Mem_F(dst) );
11329 ins_pipe( fpu_mem_reg_reg );
11330 %}
11331 //
11332 // This instruction does not round to 24-bits
11333 instruct divF_reg(regF dst, regF src) %{
11334 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11335 match(Set dst (DivF dst src));
11336
11337 format %{ "FDIV $dst,$src" %}
11338 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
11339 ins_encode( Push_Reg_F(src),
11340 OpcP, RegOpc(dst) );
11341 ins_pipe( fpu_reg_reg );
11342 %}
11343
11344
11345 // Spill to obtain 24-bit precision
11346 instruct modF24_reg(stackSlotF dst, regF src1, regF src2, eAXRegI rax, eFlagsReg cr) %{
11347 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
11348 match(Set dst (ModF src1 src2));
11349 effect(KILL rax, KILL cr); // emitModD() uses EAX and EFLAGS
11350
11351 format %{ "FMOD $dst,$src1,$src2" %}
11352 ins_encode( Push_Reg_Mod_D(src1, src2),
11353 emitModD(),
11354 Push_Result_Mod_D(src2),
11355 Pop_Mem_F(dst));
11356 ins_pipe( pipe_slow );
11357 %}
11358 //
11359 // This instruction does not round to 24-bits
11360 instruct modF_reg(regF dst, regF src, eAXRegI rax, eFlagsReg cr) %{
11361 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
11362 match(Set dst (ModF dst src));
11363 effect(KILL rax, KILL cr); // emitModD() uses EAX and EFLAGS
11364
11365 format %{ "FMOD $dst,$src" %}
11366 ins_encode(Push_Reg_Mod_D(dst, src),
11367 emitModD(),
11368 Push_Result_Mod_D(src),
11369 Pop_Reg_F(dst));
11370 ins_pipe( pipe_slow );
11371 %}
11372
11373 instruct modX_reg(regX dst, regX src0, regX src1, eAXRegI rax, eFlagsReg cr) %{
11374 predicate(UseSSE>=1);
11375 match(Set dst (ModF src0 src1));
11376 effect(KILL rax, KILL cr);
11377 format %{ "SUB ESP,4\t # FMOD\n"
11378 "\tMOVSS [ESP+0],$src1\n"
11379 "\tFLD_S [ESP+0]\n"
11380 "\tMOVSS [ESP+0],$src0\n"
11381 "\tFLD_S [ESP+0]\n"
11382 "loop:\tFPREM\n"
11383 "\tFWAIT\n"
11384 "\tFNSTSW AX\n"
11385 "\tSAHF\n"
11386 "\tJP loop\n"
11387 "\tFSTP_S [ESP+0]\n"
11388 "\tMOVSS $dst,[ESP+0]\n"
11389 "\tADD ESP,4\n"
11390 "\tFSTP ST0\t # Restore FPU Stack"
11391 %}
11392 ins_cost(250);
11393 ins_encode( Push_ModX_encoding(src0, src1), emitModD(), Push_ResultX(dst,0x4), PopFPU);
11394 ins_pipe( pipe_slow );
11395 %}
11396
11397
11398 //----------Arithmetic Conversion Instructions---------------------------------
11399 // The conversions operations are all Alpha sorted. Please keep it that way!
11400
11401 instruct roundFloat_mem_reg(stackSlotF dst, regF src) %{
11402 predicate(UseSSE==0);
11403 match(Set dst (RoundFloat src));
11404 ins_cost(125);
11405 format %{ "FST_S $dst,$src\t# F-round" %}
11406 ins_encode( Pop_Mem_Reg_F(dst, src) );
11407 ins_pipe( fpu_mem_reg );
11408 %}
11409
11410 instruct roundDouble_mem_reg(stackSlotD dst, regD src) %{
11411 predicate(UseSSE<=1);
11412 match(Set dst (RoundDouble src));
11413 ins_cost(125);
11414 format %{ "FST_D $dst,$src\t# D-round" %}
11415 ins_encode( Pop_Mem_Reg_D(dst, src) );
11416 ins_pipe( fpu_mem_reg );
11417 %}
11418
11419 // Force rounding to 24-bit precision and 6-bit exponent
11420 instruct convD2F_reg(stackSlotF dst, regD src) %{
11421 predicate(UseSSE==0);
11422 match(Set dst (ConvD2F src));
11423 format %{ "FST_S $dst,$src\t# F-round" %}
11424 expand %{
11425 roundFloat_mem_reg(dst,src);
11426 %}
11427 %}
11428
11429 // Force rounding to 24-bit precision and 6-bit exponent
11430 instruct convD2X_reg(regX dst, regD src, eFlagsReg cr) %{
11431 predicate(UseSSE==1);
11432 match(Set dst (ConvD2F src));
11433 effect( KILL cr );
11434 format %{ "SUB ESP,4\n\t"
11435 "FST_S [ESP],$src\t# F-round\n\t"
11436 "MOVSS $dst,[ESP]\n\t"
11437 "ADD ESP,4" %}
11438 ins_encode( D2X_encoding(dst, src) );
11439 ins_pipe( pipe_slow );
11440 %}
11441
11442 // Force rounding double precision to single precision
11443 instruct convXD2X_reg(regX dst, regXD src) %{
11444 predicate(UseSSE>=2);
11445 match(Set dst (ConvD2F src));
11446 format %{ "CVTSD2SS $dst,$src\t# F-round" %}
11447 opcode(0xF2, 0x0F, 0x5A);
11448 ins_encode( OpcP, OpcS, Opcode(tertiary), RegReg(dst, src));
11449 ins_pipe( pipe_slow );
11450 %}
11451
11452 instruct convF2D_reg_reg(regD dst, regF src) %{
11453 predicate(UseSSE==0);
11454 match(Set dst (ConvF2D src));
11455 format %{ "FST_S $dst,$src\t# D-round" %}
11456 ins_encode( Pop_Reg_Reg_D(dst, src));
11457 ins_pipe( fpu_reg_reg );
11458 %}
11459
11460 instruct convF2D_reg(stackSlotD dst, regF src) %{
11461 predicate(UseSSE==1);
11462 match(Set dst (ConvF2D src));
11463 format %{ "FST_D $dst,$src\t# D-round" %}
11464 expand %{
11465 roundDouble_mem_reg(dst,src);
11466 %}
11467 %}
11468
11469 instruct convX2D_reg(regD dst, regX src, eFlagsReg cr) %{
11470 predicate(UseSSE==1);
11471 match(Set dst (ConvF2D src));
11472 effect( KILL cr );
11473 format %{ "SUB ESP,4\n\t"
11474 "MOVSS [ESP] $src\n\t"
11475 "FLD_S [ESP]\n\t"
11476 "ADD ESP,4\n\t"
11477 "FSTP $dst\t# D-round" %}
11478 ins_encode( X2D_encoding(dst, src), Pop_Reg_D(dst));
11479 ins_pipe( pipe_slow );
11480 %}
11481
11482 instruct convX2XD_reg(regXD dst, regX src) %{
11483 predicate(UseSSE>=2);
11484 match(Set dst (ConvF2D src));
11485 format %{ "CVTSS2SD $dst,$src\t# D-round" %}
11486 opcode(0xF3, 0x0F, 0x5A);
11487 ins_encode( OpcP, OpcS, Opcode(tertiary), RegReg(dst, src));
11488 ins_pipe( pipe_slow );
11489 %}
11490
11491 // Convert a double to an int. If the double is a NAN, stuff a zero in instead.
11492 instruct convD2I_reg_reg( eAXRegI dst, eDXRegI tmp, regD src, eFlagsReg cr ) %{
11493 predicate(UseSSE<=1);
11494 match(Set dst (ConvD2I src));
11495 effect( KILL tmp, KILL cr );
11496 format %{ "FLD $src\t# Convert double to int \n\t"
11497 "FLDCW trunc mode\n\t"
11498 "SUB ESP,4\n\t"
11499 "FISTp [ESP + #0]\n\t"
11500 "FLDCW std/24-bit mode\n\t"
11501 "POP EAX\n\t"
11502 "CMP EAX,0x80000000\n\t"
11503 "JNE,s fast\n\t"
11504 "FLD_D $src\n\t"
11505 "CALL d2i_wrapper\n"
11506 "fast:" %}
11507 ins_encode( Push_Reg_D(src), D2I_encoding(src) );
11508 ins_pipe( pipe_slow );
11509 %}
11510
11511 // Convert a double to an int. If the double is a NAN, stuff a zero in instead.
11512 instruct convXD2I_reg_reg( eAXRegI dst, eDXRegI tmp, regXD src, eFlagsReg cr ) %{
11513 predicate(UseSSE>=2);
11514 match(Set dst (ConvD2I src));
11515 effect( KILL tmp, KILL cr );
11516 format %{ "CVTTSD2SI $dst, $src\n\t"
11517 "CMP $dst,0x80000000\n\t"
11518 "JNE,s fast\n\t"
11519 "SUB ESP, 8\n\t"
11520 "MOVSD [ESP], $src\n\t"
11521 "FLD_D [ESP]\n\t"
11522 "ADD ESP, 8\n\t"
11523 "CALL d2i_wrapper\n"
11524 "fast:" %}
11525 opcode(0x1); // double-precision conversion
11526 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x2C), FX2I_encoding(src,dst));
11527 ins_pipe( pipe_slow );
11528 %}
11529
11530 instruct convD2L_reg_reg( eADXRegL dst, regD src, eFlagsReg cr ) %{
11531 predicate(UseSSE<=1);
11532 match(Set dst (ConvD2L src));
11533 effect( KILL cr );
11534 format %{ "FLD $src\t# Convert double to long\n\t"
11535 "FLDCW trunc mode\n\t"
11536 "SUB ESP,8\n\t"
11537 "FISTp [ESP + #0]\n\t"
11538 "FLDCW std/24-bit mode\n\t"
11539 "POP EAX\n\t"
11540 "POP EDX\n\t"
11541 "CMP EDX,0x80000000\n\t"
11542 "JNE,s fast\n\t"
11543 "TEST EAX,EAX\n\t"
11544 "JNE,s fast\n\t"
11545 "FLD $src\n\t"
11546 "CALL d2l_wrapper\n"
11547 "fast:" %}
11548 ins_encode( Push_Reg_D(src), D2L_encoding(src) );
11549 ins_pipe( pipe_slow );
11550 %}
11551
11552 // XMM lacks a float/double->long conversion, so use the old FPU stack.
11553 instruct convXD2L_reg_reg( eADXRegL dst, regXD src, eFlagsReg cr ) %{
11554 predicate (UseSSE>=2);
11555 match(Set dst (ConvD2L src));
11556 effect( KILL cr );
11557 format %{ "SUB ESP,8\t# Convert double to long\n\t"
11558 "MOVSD [ESP],$src\n\t"
11559 "FLD_D [ESP]\n\t"
11560 "FLDCW trunc mode\n\t"
11561 "FISTp [ESP + #0]\n\t"
11562 "FLDCW std/24-bit mode\n\t"
11563 "POP EAX\n\t"
11564 "POP EDX\n\t"
11565 "CMP EDX,0x80000000\n\t"
11566 "JNE,s fast\n\t"
11567 "TEST EAX,EAX\n\t"
11568 "JNE,s fast\n\t"
11569 "SUB ESP,8\n\t"
11570 "MOVSD [ESP],$src\n\t"
11571 "FLD_D [ESP]\n\t"
11572 "CALL d2l_wrapper\n"
11573 "fast:" %}
11574 ins_encode( XD2L_encoding(src) );
11575 ins_pipe( pipe_slow );
11576 %}
11577
11578 // Convert a double to an int. Java semantics require we do complex
11579 // manglations in the corner cases. So we set the rounding mode to
11580 // 'zero', store the darned double down as an int, and reset the
11581 // rounding mode to 'nearest'. The hardware stores a flag value down
11582 // if we would overflow or converted a NAN; we check for this and
11583 // and go the slow path if needed.
11584 instruct convF2I_reg_reg(eAXRegI dst, eDXRegI tmp, regF src, eFlagsReg cr ) %{
11585 predicate(UseSSE==0);
11586 match(Set dst (ConvF2I src));
11587 effect( KILL tmp, KILL cr );
11588 format %{ "FLD $src\t# Convert float to int \n\t"
11589 "FLDCW trunc mode\n\t"
11590 "SUB ESP,4\n\t"
11591 "FISTp [ESP + #0]\n\t"
11592 "FLDCW std/24-bit mode\n\t"
11593 "POP EAX\n\t"
11594 "CMP EAX,0x80000000\n\t"
11595 "JNE,s fast\n\t"
11596 "FLD $src\n\t"
11597 "CALL d2i_wrapper\n"
11598 "fast:" %}
11599 // D2I_encoding works for F2I
11600 ins_encode( Push_Reg_F(src), D2I_encoding(src) );
11601 ins_pipe( pipe_slow );
11602 %}
11603
11604 // Convert a float in xmm to an int reg.
11605 instruct convX2I_reg(eAXRegI dst, eDXRegI tmp, regX src, eFlagsReg cr ) %{
11606 predicate(UseSSE>=1);
11607 match(Set dst (ConvF2I src));
11608 effect( KILL tmp, KILL cr );
11609 format %{ "CVTTSS2SI $dst, $src\n\t"
11610 "CMP $dst,0x80000000\n\t"
11611 "JNE,s fast\n\t"
11612 "SUB ESP, 4\n\t"
11613 "MOVSS [ESP], $src\n\t"
11614 "FLD [ESP]\n\t"
11615 "ADD ESP, 4\n\t"
11616 "CALL d2i_wrapper\n"
11617 "fast:" %}
11618 opcode(0x0); // single-precision conversion
11619 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x2C), FX2I_encoding(src,dst));
11620 ins_pipe( pipe_slow );
11621 %}
11622
11623 instruct convF2L_reg_reg( eADXRegL dst, regF src, eFlagsReg cr ) %{
11624 predicate(UseSSE==0);
11625 match(Set dst (ConvF2L src));
11626 effect( KILL cr );
11627 format %{ "FLD $src\t# Convert float to long\n\t"
11628 "FLDCW trunc mode\n\t"
11629 "SUB ESP,8\n\t"
11630 "FISTp [ESP + #0]\n\t"
11631 "FLDCW std/24-bit mode\n\t"
11632 "POP EAX\n\t"
11633 "POP EDX\n\t"
11634 "CMP EDX,0x80000000\n\t"
11635 "JNE,s fast\n\t"
11636 "TEST EAX,EAX\n\t"
11637 "JNE,s fast\n\t"
11638 "FLD $src\n\t"
11639 "CALL d2l_wrapper\n"
11640 "fast:" %}
11641 // D2L_encoding works for F2L
11642 ins_encode( Push_Reg_F(src), D2L_encoding(src) );
11643 ins_pipe( pipe_slow );
11644 %}
11645
11646 // XMM lacks a float/double->long conversion, so use the old FPU stack.
11647 instruct convX2L_reg_reg( eADXRegL dst, regX src, eFlagsReg cr ) %{
11648 predicate (UseSSE>=1);
11649 match(Set dst (ConvF2L src));
11650 effect( KILL cr );
11651 format %{ "SUB ESP,8\t# Convert float to long\n\t"
11652 "MOVSS [ESP],$src\n\t"
11653 "FLD_S [ESP]\n\t"
11654 "FLDCW trunc mode\n\t"
11655 "FISTp [ESP + #0]\n\t"
11656 "FLDCW std/24-bit mode\n\t"
11657 "POP EAX\n\t"
11658 "POP EDX\n\t"
11659 "CMP EDX,0x80000000\n\t"
11660 "JNE,s fast\n\t"
11661 "TEST EAX,EAX\n\t"
11662 "JNE,s fast\n\t"
11663 "SUB ESP,4\t# Convert float to long\n\t"
11664 "MOVSS [ESP],$src\n\t"
11665 "FLD_S [ESP]\n\t"
11666 "ADD ESP,4\n\t"
11667 "CALL d2l_wrapper\n"
11668 "fast:" %}
11669 ins_encode( X2L_encoding(src) );
11670 ins_pipe( pipe_slow );
11671 %}
11672
11673 instruct convI2D_reg(regD dst, stackSlotI src) %{
11674 predicate( UseSSE<=1 );
11675 match(Set dst (ConvI2D src));
11676 format %{ "FILD $src\n\t"
11677 "FSTP $dst" %}
11678 opcode(0xDB, 0x0); /* DB /0 */
11679 ins_encode(Push_Mem_I(src), Pop_Reg_D(dst));
11680 ins_pipe( fpu_reg_mem );
11681 %}
11682
11683 instruct convI2XD_reg(regXD dst, eRegI src) %{
11684 predicate( UseSSE>=2 && !UseXmmI2D );
11685 match(Set dst (ConvI2D src));
11686 format %{ "CVTSI2SD $dst,$src" %}
11687 opcode(0xF2, 0x0F, 0x2A);
11688 ins_encode( OpcP, OpcS, Opcode(tertiary), RegReg(dst, src));
11689 ins_pipe( pipe_slow );
11690 %}
11691
11692 instruct convI2XD_mem(regXD dst, memory mem) %{
11693 predicate( UseSSE>=2 );
11694 match(Set dst (ConvI2D (LoadI mem)));
11695 format %{ "CVTSI2SD $dst,$mem" %}
11696 opcode(0xF2, 0x0F, 0x2A);
11697 ins_encode( OpcP, OpcS, Opcode(tertiary), RegMem(dst, mem));
11698 ins_pipe( pipe_slow );
11699 %}
11700
11701 instruct convXI2XD_reg(regXD dst, eRegI src)
11702 %{
11703 predicate( UseSSE>=2 && UseXmmI2D );
11704 match(Set dst (ConvI2D src));
11705
11706 format %{ "MOVD $dst,$src\n\t"
11707 "CVTDQ2PD $dst,$dst\t# i2d" %}
11708 ins_encode %{
11709 __ movdl($dst$$XMMRegister, $src$$Register);
11710 __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister);
11711 %}
11712 ins_pipe(pipe_slow); // XXX
11713 %}
11714
11715 instruct convI2D_mem(regD dst, memory mem) %{
11716 predicate( UseSSE<=1 && !Compile::current()->select_24_bit_instr());
11717 match(Set dst (ConvI2D (LoadI mem)));
11718 format %{ "FILD $mem\n\t"
11719 "FSTP $dst" %}
11720 opcode(0xDB); /* DB /0 */
11721 ins_encode( OpcP, RMopc_Mem(0x00,mem),
11722 Pop_Reg_D(dst));
11723 ins_pipe( fpu_reg_mem );
11724 %}
11725
11726 // Convert a byte to a float; no rounding step needed.
11727 instruct conv24I2F_reg(regF dst, stackSlotI src) %{
11728 predicate( UseSSE==0 && n->in(1)->Opcode() == Op_AndI && n->in(1)->in(2)->is_Con() && n->in(1)->in(2)->get_int() == 255 );
11729 match(Set dst (ConvI2F src));
11730 format %{ "FILD $src\n\t"
11731 "FSTP $dst" %}
11732
11733 opcode(0xDB, 0x0); /* DB /0 */
11734 ins_encode(Push_Mem_I(src), Pop_Reg_F(dst));
11735 ins_pipe( fpu_reg_mem );
11736 %}
11737
11738 // In 24-bit mode, force exponent rounding by storing back out
11739 instruct convI2F_SSF(stackSlotF dst, stackSlotI src) %{
11740 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
11741 match(Set dst (ConvI2F src));
11742 ins_cost(200);
11743 format %{ "FILD $src\n\t"
11744 "FSTP_S $dst" %}
11745 opcode(0xDB, 0x0); /* DB /0 */
11746 ins_encode( Push_Mem_I(src),
11747 Pop_Mem_F(dst));
11748 ins_pipe( fpu_mem_mem );
11749 %}
11750
11751 // In 24-bit mode, force exponent rounding by storing back out
11752 instruct convI2F_SSF_mem(stackSlotF dst, memory mem) %{
11753 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
11754 match(Set dst (ConvI2F (LoadI mem)));
11755 ins_cost(200);
11756 format %{ "FILD $mem\n\t"
11757 "FSTP_S $dst" %}
11758 opcode(0xDB); /* DB /0 */
11759 ins_encode( OpcP, RMopc_Mem(0x00,mem),
11760 Pop_Mem_F(dst));
11761 ins_pipe( fpu_mem_mem );
11762 %}
11763
11764 // This instruction does not round to 24-bits
11765 instruct convI2F_reg(regF dst, stackSlotI src) %{
11766 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
11767 match(Set dst (ConvI2F src));
11768 format %{ "FILD $src\n\t"
11769 "FSTP $dst" %}
11770 opcode(0xDB, 0x0); /* DB /0 */
11771 ins_encode( Push_Mem_I(src),
11772 Pop_Reg_F(dst));
11773 ins_pipe( fpu_reg_mem );
11774 %}
11775
11776 // This instruction does not round to 24-bits
11777 instruct convI2F_mem(regF dst, memory mem) %{
11778 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
11779 match(Set dst (ConvI2F (LoadI mem)));
11780 format %{ "FILD $mem\n\t"
11781 "FSTP $dst" %}
11782 opcode(0xDB); /* DB /0 */
11783 ins_encode( OpcP, RMopc_Mem(0x00,mem),
11784 Pop_Reg_F(dst));
11785 ins_pipe( fpu_reg_mem );
11786 %}
11787
11788 // Convert an int to a float in xmm; no rounding step needed.
11789 instruct convI2X_reg(regX dst, eRegI src) %{
11790 predicate( UseSSE==1 || UseSSE>=2 && !UseXmmI2F );
11791 match(Set dst (ConvI2F src));
11792 format %{ "CVTSI2SS $dst, $src" %}
11793
11794 opcode(0xF3, 0x0F, 0x2A); /* F3 0F 2A /r */
11795 ins_encode( OpcP, OpcS, Opcode(tertiary), RegReg(dst, src));
11796 ins_pipe( pipe_slow );
11797 %}
11798
11799 instruct convXI2X_reg(regX dst, eRegI src)
11800 %{
11801 predicate( UseSSE>=2 && UseXmmI2F );
11802 match(Set dst (ConvI2F src));
11803
11804 format %{ "MOVD $dst,$src\n\t"
11805 "CVTDQ2PS $dst,$dst\t# i2f" %}
11806 ins_encode %{
11807 __ movdl($dst$$XMMRegister, $src$$Register);
11808 __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister);
11809 %}
11810 ins_pipe(pipe_slow); // XXX
11811 %}
11812
11813 instruct convI2L_reg( eRegL dst, eRegI src, eFlagsReg cr) %{
11814 match(Set dst (ConvI2L src));
11815 effect(KILL cr);
11816 ins_cost(375);
11817 format %{ "MOV $dst.lo,$src\n\t"
11818 "MOV $dst.hi,$src\n\t"
11819 "SAR $dst.hi,31" %}
11820 ins_encode(convert_int_long(dst,src));
11821 ins_pipe( ialu_reg_reg_long );
11822 %}
11823
11824 // Zero-extend convert int to long
11825 instruct convI2L_reg_zex(eRegL dst, eRegI src, immL_32bits mask, eFlagsReg flags ) %{
11826 match(Set dst (AndL (ConvI2L src) mask) );
11827 effect( KILL flags );
11828 ins_cost(250);
11829 format %{ "MOV $dst.lo,$src\n\t"
11830 "XOR $dst.hi,$dst.hi" %}
11831 opcode(0x33); // XOR
11832 ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) );
11833 ins_pipe( ialu_reg_reg_long );
11834 %}
11835
11836 // Zero-extend long
11837 instruct zerox_long(eRegL dst, eRegL src, immL_32bits mask, eFlagsReg flags ) %{
11838 match(Set dst (AndL src mask) );
11839 effect( KILL flags );
11840 ins_cost(250);
11841 format %{ "MOV $dst.lo,$src.lo\n\t"
11842 "XOR $dst.hi,$dst.hi\n\t" %}
11843 opcode(0x33); // XOR
11844 ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) );
11845 ins_pipe( ialu_reg_reg_long );
11846 %}
11847
11848 instruct convL2D_reg( stackSlotD dst, eRegL src, eFlagsReg cr) %{
11849 predicate (UseSSE<=1);
11850 match(Set dst (ConvL2D src));
11851 effect( KILL cr );
11852 format %{ "PUSH $src.hi\t# Convert long to double\n\t"
11853 "PUSH $src.lo\n\t"
11854 "FILD ST,[ESP + #0]\n\t"
11855 "ADD ESP,8\n\t"
11856 "FSTP_D $dst\t# D-round" %}
11857 opcode(0xDF, 0x5); /* DF /5 */
11858 ins_encode(convert_long_double(src), Pop_Mem_D(dst));
11859 ins_pipe( pipe_slow );
11860 %}
11861
11862 instruct convL2XD_reg( regXD dst, eRegL src, eFlagsReg cr) %{
11863 predicate (UseSSE>=2);
11864 match(Set dst (ConvL2D src));
11865 effect( KILL cr );
11866 format %{ "PUSH $src.hi\t# Convert long to double\n\t"
11867 "PUSH $src.lo\n\t"
11868 "FILD_D [ESP]\n\t"
11869 "FSTP_D [ESP]\n\t"
11870 "MOVSD $dst,[ESP]\n\t"
11871 "ADD ESP,8" %}
11872 opcode(0xDF, 0x5); /* DF /5 */
11873 ins_encode(convert_long_double2(src), Push_ResultXD(dst));
11874 ins_pipe( pipe_slow );
11875 %}
11876
11877 instruct convL2X_reg( regX dst, eRegL src, eFlagsReg cr) %{
11878 predicate (UseSSE>=1);
11879 match(Set dst (ConvL2F src));
11880 effect( KILL cr );
11881 format %{ "PUSH $src.hi\t# Convert long to single float\n\t"
11882 "PUSH $src.lo\n\t"
11883 "FILD_D [ESP]\n\t"
11884 "FSTP_S [ESP]\n\t"
11885 "MOVSS $dst,[ESP]\n\t"
11886 "ADD ESP,8" %}
11887 opcode(0xDF, 0x5); /* DF /5 */
11888 ins_encode(convert_long_double2(src), Push_ResultX(dst,0x8));
11889 ins_pipe( pipe_slow );
11890 %}
11891
11892 instruct convL2F_reg( stackSlotF dst, eRegL src, eFlagsReg cr) %{
11893 match(Set dst (ConvL2F src));
11894 effect( KILL cr );
11895 format %{ "PUSH $src.hi\t# Convert long to single float\n\t"
11896 "PUSH $src.lo\n\t"
11897 "FILD ST,[ESP + #0]\n\t"
11898 "ADD ESP,8\n\t"
11899 "FSTP_S $dst\t# F-round" %}
11900 opcode(0xDF, 0x5); /* DF /5 */
11901 ins_encode(convert_long_double(src), Pop_Mem_F(dst));
11902 ins_pipe( pipe_slow );
11903 %}
11904
11905 instruct convL2I_reg( eRegI dst, eRegL src ) %{
11906 match(Set dst (ConvL2I src));
11907 effect( DEF dst, USE src );
11908 format %{ "MOV $dst,$src.lo" %}
11909 ins_encode(enc_CopyL_Lo(dst,src));
11910 ins_pipe( ialu_reg_reg );
11911 %}
11912
11913
11914 instruct MoveF2I_stack_reg(eRegI dst, stackSlotF src) %{
11915 match(Set dst (MoveF2I src));
11916 effect( DEF dst, USE src );
11917 ins_cost(100);
11918 format %{ "MOV $dst,$src\t# MoveF2I_stack_reg" %}
11919 opcode(0x8B);
11920 ins_encode( OpcP, RegMem(dst,src));
11921 ins_pipe( ialu_reg_mem );
11922 %}
11923
11924 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{
11925 predicate(UseSSE==0);
11926 match(Set dst (MoveF2I src));
11927 effect( DEF dst, USE src );
11928
11929 ins_cost(125);
11930 format %{ "FST_S $dst,$src\t# MoveF2I_reg_stack" %}
11931 ins_encode( Pop_Mem_Reg_F(dst, src) );
11932 ins_pipe( fpu_mem_reg );
11933 %}
11934
11935 instruct MoveF2I_reg_stack_sse(stackSlotI dst, regX src) %{
11936 predicate(UseSSE>=1);
11937 match(Set dst (MoveF2I src));
11938 effect( DEF dst, USE src );
11939
11940 ins_cost(95);
11941 format %{ "MOVSS $dst,$src\t# MoveF2I_reg_stack_sse" %}
11942 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x11), RegMem(src, dst));
11943 ins_pipe( pipe_slow );
11944 %}
11945
11946 instruct MoveF2I_reg_reg_sse(eRegI dst, regX src) %{
11947 predicate(UseSSE>=2);
11948 match(Set dst (MoveF2I src));
11949 effect( DEF dst, USE src );
11950 ins_cost(85);
11951 format %{ "MOVD $dst,$src\t# MoveF2I_reg_reg_sse" %}
11952 ins_encode( MovX2I_reg(dst, src));
11953 ins_pipe( pipe_slow );
11954 %}
11955
11956 instruct MoveI2F_reg_stack(stackSlotF dst, eRegI src) %{
11957 match(Set dst (MoveI2F src));
11958 effect( DEF dst, USE src );
11959
11960 ins_cost(100);
11961 format %{ "MOV $dst,$src\t# MoveI2F_reg_stack" %}
11962 opcode(0x89);
11963 ins_encode( OpcPRegSS( dst, src ) );
11964 ins_pipe( ialu_mem_reg );
11965 %}
11966
11967
11968 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
11969 predicate(UseSSE==0);
11970 match(Set dst (MoveI2F src));
11971 effect(DEF dst, USE src);
11972
11973 ins_cost(125);
11974 format %{ "FLD_S $src\n\t"
11975 "FSTP $dst\t# MoveI2F_stack_reg" %}
11976 opcode(0xD9); /* D9 /0, FLD m32real */
11977 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
11978 Pop_Reg_F(dst) );
11979 ins_pipe( fpu_reg_mem );
11980 %}
11981
11982 instruct MoveI2F_stack_reg_sse(regX dst, stackSlotI src) %{
11983 predicate(UseSSE>=1);
11984 match(Set dst (MoveI2F src));
11985 effect( DEF dst, USE src );
11986
11987 ins_cost(95);
11988 format %{ "MOVSS $dst,$src\t# MoveI2F_stack_reg_sse" %}
11989 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x10), RegMem(dst,src));
11990 ins_pipe( pipe_slow );
11991 %}
11992
11993 instruct MoveI2F_reg_reg_sse(regX dst, eRegI src) %{
11994 predicate(UseSSE>=2);
11995 match(Set dst (MoveI2F src));
11996 effect( DEF dst, USE src );
11997
11998 ins_cost(85);
11999 format %{ "MOVD $dst,$src\t# MoveI2F_reg_reg_sse" %}
12000 ins_encode( MovI2X_reg(dst, src) );
12001 ins_pipe( pipe_slow );
12002 %}
12003
12004 instruct MoveD2L_stack_reg(eRegL dst, stackSlotD src) %{
12005 match(Set dst (MoveD2L src));
12006 effect(DEF dst, USE src);
12007
12008 ins_cost(250);
12009 format %{ "MOV $dst.lo,$src\n\t"
12010 "MOV $dst.hi,$src+4\t# MoveD2L_stack_reg" %}
12011 opcode(0x8B, 0x8B);
12012 ins_encode( OpcP, RegMem(dst,src), OpcS, RegMem_Hi(dst,src));
12013 ins_pipe( ialu_mem_long_reg );
12014 %}
12015
12016 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
12017 predicate(UseSSE<=1);
12018 match(Set dst (MoveD2L src));
12019 effect(DEF dst, USE src);
12020
12021 ins_cost(125);
12022 format %{ "FST_D $dst,$src\t# MoveD2L_reg_stack" %}
12023 ins_encode( Pop_Mem_Reg_D(dst, src) );
12024 ins_pipe( fpu_mem_reg );
12025 %}
12026
12027 instruct MoveD2L_reg_stack_sse(stackSlotL dst, regXD src) %{
12028 predicate(UseSSE>=2);
12029 match(Set dst (MoveD2L src));
12030 effect(DEF dst, USE src);
12031 ins_cost(95);
12032
12033 format %{ "MOVSD $dst,$src\t# MoveD2L_reg_stack_sse" %}
12034 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x11), RegMem(src,dst));
12035 ins_pipe( pipe_slow );
12036 %}
12037
12038 instruct MoveD2L_reg_reg_sse(eRegL dst, regXD src, regXD tmp) %{
12039 predicate(UseSSE>=2);
12040 match(Set dst (MoveD2L src));
12041 effect(DEF dst, USE src, TEMP tmp);
12042 ins_cost(85);
12043 format %{ "MOVD $dst.lo,$src\n\t"
12044 "PSHUFLW $tmp,$src,0x4E\n\t"
12045 "MOVD $dst.hi,$tmp\t# MoveD2L_reg_reg_sse" %}
12046 ins_encode( MovXD2L_reg(dst, src, tmp) );
12047 ins_pipe( pipe_slow );
12048 %}
12049
12050 instruct MoveL2D_reg_stack(stackSlotD dst, eRegL src) %{
12051 match(Set dst (MoveL2D src));
12052 effect(DEF dst, USE src);
12053
12054 ins_cost(200);
12055 format %{ "MOV $dst,$src.lo\n\t"
12056 "MOV $dst+4,$src.hi\t# MoveL2D_reg_stack" %}
12057 opcode(0x89, 0x89);
12058 ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) );
12059 ins_pipe( ialu_mem_long_reg );
12060 %}
12061
12062
12063 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
12064 predicate(UseSSE<=1);
12065 match(Set dst (MoveL2D src));
12066 effect(DEF dst, USE src);
12067 ins_cost(125);
12068
12069 format %{ "FLD_D $src\n\t"
12070 "FSTP $dst\t# MoveL2D_stack_reg" %}
12071 opcode(0xDD); /* DD /0, FLD m64real */
12072 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
12073 Pop_Reg_D(dst) );
12074 ins_pipe( fpu_reg_mem );
12075 %}
12076
12077
12078 instruct MoveL2D_stack_reg_sse(regXD dst, stackSlotL src) %{
12079 predicate(UseSSE>=2 && UseXmmLoadAndClearUpper);
12080 match(Set dst (MoveL2D src));
12081 effect(DEF dst, USE src);
12082
12083 ins_cost(95);
12084 format %{ "MOVSD $dst,$src\t# MoveL2D_stack_reg_sse" %}
12085 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x10), RegMem(dst,src));
12086 ins_pipe( pipe_slow );
12087 %}
12088
12089 instruct MoveL2D_stack_reg_sse_partial(regXD dst, stackSlotL src) %{
12090 predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper);
12091 match(Set dst (MoveL2D src));
12092 effect(DEF dst, USE src);
12093
12094 ins_cost(95);
12095 format %{ "MOVLPD $dst,$src\t# MoveL2D_stack_reg_sse" %}
12096 ins_encode( Opcode(0x66), Opcode(0x0F), Opcode(0x12), RegMem(dst,src));
12097 ins_pipe( pipe_slow );
12098 %}
12099
12100 instruct MoveL2D_reg_reg_sse(regXD dst, eRegL src, regXD tmp) %{
12101 predicate(UseSSE>=2);
12102 match(Set dst (MoveL2D src));
12103 effect(TEMP dst, USE src, TEMP tmp);
12104 ins_cost(85);
12105 format %{ "MOVD $dst,$src.lo\n\t"
12106 "MOVD $tmp,$src.hi\n\t"
12107 "PUNPCKLDQ $dst,$tmp\t# MoveL2D_reg_reg_sse" %}
12108 ins_encode( MovL2XD_reg(dst, src, tmp) );
12109 ins_pipe( pipe_slow );
12110 %}
12111
12112 // Replicate scalar to packed byte (1 byte) values in xmm
12113 instruct Repl8B_reg(regXD dst, regXD src) %{
12114 predicate(UseSSE>=2);
12115 match(Set dst (Replicate8B src));
12116 format %{ "MOVDQA $dst,$src\n\t"
12117 "PUNPCKLBW $dst,$dst\n\t"
12118 "PSHUFLW $dst,$dst,0x00\t! replicate8B" %}
12119 ins_encode( pshufd_8x8(dst, src));
12120 ins_pipe( pipe_slow );
12121 %}
12122
12123 // Replicate scalar to packed byte (1 byte) values in xmm
12124 instruct Repl8B_eRegI(regXD dst, eRegI src) %{
12125 predicate(UseSSE>=2);
12126 match(Set dst (Replicate8B src));
12127 format %{ "MOVD $dst,$src\n\t"
12128 "PUNPCKLBW $dst,$dst\n\t"
12129 "PSHUFLW $dst,$dst,0x00\t! replicate8B" %}
12130 ins_encode( mov_i2x(dst, src), pshufd_8x8(dst, dst));
12131 ins_pipe( pipe_slow );
12132 %}
12133
12134 // Replicate scalar zero to packed byte (1 byte) values in xmm
12135 instruct Repl8B_immI0(regXD dst, immI0 zero) %{
12136 predicate(UseSSE>=2);
12137 match(Set dst (Replicate8B zero));
12138 format %{ "PXOR $dst,$dst\t! replicate8B" %}
12139 ins_encode( pxor(dst, dst));
12140 ins_pipe( fpu_reg_reg );
12141 %}
12142
12143 // Replicate scalar to packed shore (2 byte) values in xmm
12144 instruct Repl4S_reg(regXD dst, regXD src) %{
12145 predicate(UseSSE>=2);
12146 match(Set dst (Replicate4S src));
12147 format %{ "PSHUFLW $dst,$src,0x00\t! replicate4S" %}
12148 ins_encode( pshufd_4x16(dst, src));
12149 ins_pipe( fpu_reg_reg );
12150 %}
12151
12152 // Replicate scalar to packed shore (2 byte) values in xmm
12153 instruct Repl4S_eRegI(regXD dst, eRegI src) %{
12154 predicate(UseSSE>=2);
12155 match(Set dst (Replicate4S src));
12156 format %{ "MOVD $dst,$src\n\t"
12157 "PSHUFLW $dst,$dst,0x00\t! replicate4S" %}
12158 ins_encode( mov_i2x(dst, src), pshufd_4x16(dst, dst));
12159 ins_pipe( fpu_reg_reg );
12160 %}
12161
12162 // Replicate scalar zero to packed short (2 byte) values in xmm
12163 instruct Repl4S_immI0(regXD dst, immI0 zero) %{
12164 predicate(UseSSE>=2);
12165 match(Set dst (Replicate4S zero));
12166 format %{ "PXOR $dst,$dst\t! replicate4S" %}
12167 ins_encode( pxor(dst, dst));
12168 ins_pipe( fpu_reg_reg );
12169 %}
12170
12171 // Replicate scalar to packed char (2 byte) values in xmm
12172 instruct Repl4C_reg(regXD dst, regXD src) %{
12173 predicate(UseSSE>=2);
12174 match(Set dst (Replicate4C src));
12175 format %{ "PSHUFLW $dst,$src,0x00\t! replicate4C" %}
12176 ins_encode( pshufd_4x16(dst, src));
12177 ins_pipe( fpu_reg_reg );
12178 %}
12179
12180 // Replicate scalar to packed char (2 byte) values in xmm
12181 instruct Repl4C_eRegI(regXD dst, eRegI src) %{
12182 predicate(UseSSE>=2);
12183 match(Set dst (Replicate4C src));
12184 format %{ "MOVD $dst,$src\n\t"
12185 "PSHUFLW $dst,$dst,0x00\t! replicate4C" %}
12186 ins_encode( mov_i2x(dst, src), pshufd_4x16(dst, dst));
12187 ins_pipe( fpu_reg_reg );
12188 %}
12189
12190 // Replicate scalar zero to packed char (2 byte) values in xmm
12191 instruct Repl4C_immI0(regXD dst, immI0 zero) %{
12192 predicate(UseSSE>=2);
12193 match(Set dst (Replicate4C zero));
12194 format %{ "PXOR $dst,$dst\t! replicate4C" %}
12195 ins_encode( pxor(dst, dst));
12196 ins_pipe( fpu_reg_reg );
12197 %}
12198
12199 // Replicate scalar to packed integer (4 byte) values in xmm
12200 instruct Repl2I_reg(regXD dst, regXD src) %{
12201 predicate(UseSSE>=2);
12202 match(Set dst (Replicate2I src));
12203 format %{ "PSHUFD $dst,$src,0x00\t! replicate2I" %}
12204 ins_encode( pshufd(dst, src, 0x00));
12205 ins_pipe( fpu_reg_reg );
12206 %}
12207
12208 // Replicate scalar to packed integer (4 byte) values in xmm
12209 instruct Repl2I_eRegI(regXD dst, eRegI src) %{
12210 predicate(UseSSE>=2);
12211 match(Set dst (Replicate2I src));
12212 format %{ "MOVD $dst,$src\n\t"
12213 "PSHUFD $dst,$dst,0x00\t! replicate2I" %}
12214 ins_encode( mov_i2x(dst, src), pshufd(dst, dst, 0x00));
12215 ins_pipe( fpu_reg_reg );
12216 %}
12217
12218 // Replicate scalar zero to packed integer (2 byte) values in xmm
12219 instruct Repl2I_immI0(regXD dst, immI0 zero) %{
12220 predicate(UseSSE>=2);
12221 match(Set dst (Replicate2I zero));
12222 format %{ "PXOR $dst,$dst\t! replicate2I" %}
12223 ins_encode( pxor(dst, dst));
12224 ins_pipe( fpu_reg_reg );
12225 %}
12226
12227 // Replicate scalar to packed single precision floating point values in xmm
12228 instruct Repl2F_reg(regXD dst, regXD src) %{
12229 predicate(UseSSE>=2);
12230 match(Set dst (Replicate2F src));
12231 format %{ "PSHUFD $dst,$src,0xe0\t! replicate2F" %}
12232 ins_encode( pshufd(dst, src, 0xe0));
12233 ins_pipe( fpu_reg_reg );
12234 %}
12235
12236 // Replicate scalar to packed single precision floating point values in xmm
12237 instruct Repl2F_regX(regXD dst, regX src) %{
12238 predicate(UseSSE>=2);
12239 match(Set dst (Replicate2F src));
12240 format %{ "PSHUFD $dst,$src,0xe0\t! replicate2F" %}
12241 ins_encode( pshufd(dst, src, 0xe0));
12242 ins_pipe( fpu_reg_reg );
12243 %}
12244
12245 // Replicate scalar to packed single precision floating point values in xmm
12246 instruct Repl2F_immXF0(regXD dst, immXF0 zero) %{
12247 predicate(UseSSE>=2);
12248 match(Set dst (Replicate2F zero));
12249 format %{ "PXOR $dst,$dst\t! replicate2F" %}
12250 ins_encode( pxor(dst, dst));
12251 ins_pipe( fpu_reg_reg );
12252 %}
12253
12254 // =======================================================================
12255 // fast clearing of an array
12256 instruct rep_stos(eCXRegI cnt, eDIRegP base, eAXRegI zero, Universe dummy, eFlagsReg cr) %{
12257 match(Set dummy (ClearArray cnt base));
12258 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr);
12259 format %{ "SHL ECX,1\t# Convert doublewords to words\n\t"
12260 "XOR EAX,EAX\n\t"
12261 "REP STOS\t# store EAX into [EDI++] while ECX--" %}
12262 opcode(0,0x4);
12263 ins_encode( Opcode(0xD1), RegOpc(ECX),
12264 OpcRegReg(0x33,EAX,EAX),
12265 Opcode(0xF3), Opcode(0xAB) );
12266 ins_pipe( pipe_slow );
12267 %}
12268
12269 instruct string_compare(eDIRegP str1, eCXRegI cnt1, eSIRegP str2, eBXRegI cnt2,
12270 eAXRegI result, regXD tmp1, regXD tmp2, eFlagsReg cr) %{
12271 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
12272 effect(TEMP tmp1, TEMP tmp2, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
12273
12274 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1, $tmp2" %}
12275 ins_encode %{
12276 __ string_compare($str1$$Register, $str2$$Register,
12277 $cnt1$$Register, $cnt2$$Register, $result$$Register,
12278 $tmp1$$XMMRegister, $tmp2$$XMMRegister);
12279 %}
12280 ins_pipe( pipe_slow );
12281 %}
12282
12283 // fast string equals
12284 instruct string_equals(eDIRegP str1, eSIRegP str2, eCXRegI cnt, eAXRegI result,
12285 regXD tmp1, regXD tmp2, eBXRegI tmp3, eFlagsReg cr) %{
12286 match(Set result (StrEquals (Binary str1 str2) cnt));
12287 effect(TEMP tmp1, TEMP tmp2, USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp3, KILL cr);
12288
12289 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp1, $tmp2, $tmp3" %}
12290 ins_encode %{
12291 __ char_arrays_equals(false, $str1$$Register, $str2$$Register,
12292 $cnt$$Register, $result$$Register, $tmp3$$Register,
12293 $tmp1$$XMMRegister, $tmp2$$XMMRegister);
12294 %}
12295 ins_pipe( pipe_slow );
12296 %}
12297
12298 instruct string_indexof(eDIRegP str1, eDXRegI cnt1, eSIRegP str2, eAXRegI cnt2,
12299 eBXRegI result, regXD tmp1, eCXRegI tmp2, eFlagsReg cr) %{
12300 predicate(UseSSE42Intrinsics);
12301 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
12302 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp2, KILL cr);
12303
12304 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp2, $tmp1" %}
12305 ins_encode %{
12306 __ string_indexof($str1$$Register, $str2$$Register,
12307 $cnt1$$Register, $cnt2$$Register, $result$$Register,
12308 $tmp1$$XMMRegister, $tmp2$$Register);
12309 %}
12310 ins_pipe( pipe_slow );
12311 %}
12312
12313 // fast array equals
12314 instruct array_equals(eDIRegP ary1, eSIRegP ary2, eAXRegI result,
12315 regXD tmp1, regXD tmp2, eCXRegI tmp3, eBXRegI tmp4, eFlagsReg cr)
12316 %{
12317 match(Set result (AryEq ary1 ary2));
12318 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
12319 //ins_cost(300);
12320
12321 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
12322 ins_encode %{
12323 __ char_arrays_equals(true, $ary1$$Register, $ary2$$Register,
12324 $tmp3$$Register, $result$$Register, $tmp4$$Register,
12325 $tmp1$$XMMRegister, $tmp2$$XMMRegister);
12326 %}
12327 ins_pipe( pipe_slow );
12328 %}
12329
12330 //----------Control Flow Instructions------------------------------------------
12331 // Signed compare Instructions
12332 instruct compI_eReg(eFlagsReg cr, eRegI op1, eRegI op2) %{
12333 match(Set cr (CmpI op1 op2));
12334 effect( DEF cr, USE op1, USE op2 );
12335 format %{ "CMP $op1,$op2" %}
12336 opcode(0x3B); /* Opcode 3B /r */
12337 ins_encode( OpcP, RegReg( op1, op2) );
12338 ins_pipe( ialu_cr_reg_reg );
12339 %}
12340
12341 instruct compI_eReg_imm(eFlagsReg cr, eRegI op1, immI op2) %{
12342 match(Set cr (CmpI op1 op2));
12343 effect( DEF cr, USE op1 );
12344 format %{ "CMP $op1,$op2" %}
12345 opcode(0x81,0x07); /* Opcode 81 /7 */
12346 // ins_encode( RegImm( op1, op2) ); /* Was CmpImm */
12347 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
12348 ins_pipe( ialu_cr_reg_imm );
12349 %}
12350
12351 // Cisc-spilled version of cmpI_eReg
12352 instruct compI_eReg_mem(eFlagsReg cr, eRegI op1, memory op2) %{
12353 match(Set cr (CmpI op1 (LoadI op2)));
12354
12355 format %{ "CMP $op1,$op2" %}
12356 ins_cost(500);
12357 opcode(0x3B); /* Opcode 3B /r */
12358 ins_encode( OpcP, RegMem( op1, op2) );
12359 ins_pipe( ialu_cr_reg_mem );
12360 %}
12361
12362 instruct testI_reg( eFlagsReg cr, eRegI src, immI0 zero ) %{
12363 match(Set cr (CmpI src zero));
12364 effect( DEF cr, USE src );
12365
12366 format %{ "TEST $src,$src" %}
12367 opcode(0x85);
12368 ins_encode( OpcP, RegReg( src, src ) );
12369 ins_pipe( ialu_cr_reg_imm );
12370 %}
12371
12372 instruct testI_reg_imm( eFlagsReg cr, eRegI src, immI con, immI0 zero ) %{
12373 match(Set cr (CmpI (AndI src con) zero));
12374
12375 format %{ "TEST $src,$con" %}
12376 opcode(0xF7,0x00);
12377 ins_encode( OpcP, RegOpc(src), Con32(con) );
12378 ins_pipe( ialu_cr_reg_imm );
12379 %}
12380
12381 instruct testI_reg_mem( eFlagsReg cr, eRegI src, memory mem, immI0 zero ) %{
12382 match(Set cr (CmpI (AndI src mem) zero));
12383
12384 format %{ "TEST $src,$mem" %}
12385 opcode(0x85);
12386 ins_encode( OpcP, RegMem( src, mem ) );
12387 ins_pipe( ialu_cr_reg_mem );
12388 %}
12389
12390 // Unsigned compare Instructions; really, same as signed except they
12391 // produce an eFlagsRegU instead of eFlagsReg.
12392 instruct compU_eReg(eFlagsRegU cr, eRegI op1, eRegI op2) %{
12393 match(Set cr (CmpU op1 op2));
12394
12395 format %{ "CMPu $op1,$op2" %}
12396 opcode(0x3B); /* Opcode 3B /r */
12397 ins_encode( OpcP, RegReg( op1, op2) );
12398 ins_pipe( ialu_cr_reg_reg );
12399 %}
12400
12401 instruct compU_eReg_imm(eFlagsRegU cr, eRegI op1, immI op2) %{
12402 match(Set cr (CmpU op1 op2));
12403
12404 format %{ "CMPu $op1,$op2" %}
12405 opcode(0x81,0x07); /* Opcode 81 /7 */
12406 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
12407 ins_pipe( ialu_cr_reg_imm );
12408 %}
12409
12410 // // Cisc-spilled version of cmpU_eReg
12411 instruct compU_eReg_mem(eFlagsRegU cr, eRegI op1, memory op2) %{
12412 match(Set cr (CmpU op1 (LoadI op2)));
12413
12414 format %{ "CMPu $op1,$op2" %}
12415 ins_cost(500);
12416 opcode(0x3B); /* Opcode 3B /r */
12417 ins_encode( OpcP, RegMem( op1, op2) );
12418 ins_pipe( ialu_cr_reg_mem );
12419 %}
12420
12421 // // Cisc-spilled version of cmpU_eReg
12422 //instruct compU_mem_eReg(eFlagsRegU cr, memory op1, eRegI op2) %{
12423 // match(Set cr (CmpU (LoadI op1) op2));
12424 //
12425 // format %{ "CMPu $op1,$op2" %}
12426 // ins_cost(500);
12427 // opcode(0x39); /* Opcode 39 /r */
12428 // ins_encode( OpcP, RegMem( op1, op2) );
12429 //%}
12430
12431 instruct testU_reg( eFlagsRegU cr, eRegI src, immI0 zero ) %{
12432 match(Set cr (CmpU src zero));
12433
12434 format %{ "TESTu $src,$src" %}
12435 opcode(0x85);
12436 ins_encode( OpcP, RegReg( src, src ) );
12437 ins_pipe( ialu_cr_reg_imm );
12438 %}
12439
12440 // Unsigned pointer compare Instructions
12441 instruct compP_eReg(eFlagsRegU cr, eRegP op1, eRegP op2) %{
12442 match(Set cr (CmpP op1 op2));
12443
12444 format %{ "CMPu $op1,$op2" %}
12445 opcode(0x3B); /* Opcode 3B /r */
12446 ins_encode( OpcP, RegReg( op1, op2) );
12447 ins_pipe( ialu_cr_reg_reg );
12448 %}
12449
12450 instruct compP_eReg_imm(eFlagsRegU cr, eRegP op1, immP op2) %{
12451 match(Set cr (CmpP op1 op2));
12452
12453 format %{ "CMPu $op1,$op2" %}
12454 opcode(0x81,0x07); /* Opcode 81 /7 */
12455 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
12456 ins_pipe( ialu_cr_reg_imm );
12457 %}
12458
12459 // // Cisc-spilled version of cmpP_eReg
12460 instruct compP_eReg_mem(eFlagsRegU cr, eRegP op1, memory op2) %{
12461 match(Set cr (CmpP op1 (LoadP op2)));
12462
12463 format %{ "CMPu $op1,$op2" %}
12464 ins_cost(500);
12465 opcode(0x3B); /* Opcode 3B /r */
12466 ins_encode( OpcP, RegMem( op1, op2) );
12467 ins_pipe( ialu_cr_reg_mem );
12468 %}
12469
12470 // // Cisc-spilled version of cmpP_eReg
12471 //instruct compP_mem_eReg(eFlagsRegU cr, memory op1, eRegP op2) %{
12472 // match(Set cr (CmpP (LoadP op1) op2));
12473 //
12474 // format %{ "CMPu $op1,$op2" %}
12475 // ins_cost(500);
12476 // opcode(0x39); /* Opcode 39 /r */
12477 // ins_encode( OpcP, RegMem( op1, op2) );
12478 //%}
12479
12480 // Compare raw pointer (used in out-of-heap check).
12481 // Only works because non-oop pointers must be raw pointers
12482 // and raw pointers have no anti-dependencies.
12483 instruct compP_mem_eReg( eFlagsRegU cr, eRegP op1, memory op2 ) %{
12484 predicate( !n->in(2)->in(2)->bottom_type()->isa_oop_ptr() );
12485 match(Set cr (CmpP op1 (LoadP op2)));
12486
12487 format %{ "CMPu $op1,$op2" %}
12488 opcode(0x3B); /* Opcode 3B /r */
12489 ins_encode( OpcP, RegMem( op1, op2) );
12490 ins_pipe( ialu_cr_reg_mem );
12491 %}
12492
12493 //
12494 // This will generate a signed flags result. This should be ok
12495 // since any compare to a zero should be eq/neq.
12496 instruct testP_reg( eFlagsReg cr, eRegP src, immP0 zero ) %{
12497 match(Set cr (CmpP src zero));
12498
12499 format %{ "TEST $src,$src" %}
12500 opcode(0x85);
12501 ins_encode( OpcP, RegReg( src, src ) );
12502 ins_pipe( ialu_cr_reg_imm );
12503 %}
12504
12505 // Cisc-spilled version of testP_reg
12506 // This will generate a signed flags result. This should be ok
12507 // since any compare to a zero should be eq/neq.
12508 instruct testP_Reg_mem( eFlagsReg cr, memory op, immI0 zero ) %{
12509 match(Set cr (CmpP (LoadP op) zero));
12510
12511 format %{ "TEST $op,0xFFFFFFFF" %}
12512 ins_cost(500);
12513 opcode(0xF7); /* Opcode F7 /0 */
12514 ins_encode( OpcP, RMopc_Mem(0x00,op), Con_d32(0xFFFFFFFF) );
12515 ins_pipe( ialu_cr_reg_imm );
12516 %}
12517
12518 // Yanked all unsigned pointer compare operations.
12519 // Pointer compares are done with CmpP which is already unsigned.
12520
12521 //----------Max and Min--------------------------------------------------------
12522 // Min Instructions
12523 ////
12524 // *** Min and Max using the conditional move are slower than the
12525 // *** branch version on a Pentium III.
12526 // // Conditional move for min
12527 //instruct cmovI_reg_lt( eRegI op2, eRegI op1, eFlagsReg cr ) %{
12528 // effect( USE_DEF op2, USE op1, USE cr );
12529 // format %{ "CMOVlt $op2,$op1\t! min" %}
12530 // opcode(0x4C,0x0F);
12531 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) );
12532 // ins_pipe( pipe_cmov_reg );
12533 //%}
12534 //
12535 //// Min Register with Register (P6 version)
12536 //instruct minI_eReg_p6( eRegI op1, eRegI op2 ) %{
12537 // predicate(VM_Version::supports_cmov() );
12538 // match(Set op2 (MinI op1 op2));
12539 // ins_cost(200);
12540 // expand %{
12541 // eFlagsReg cr;
12542 // compI_eReg(cr,op1,op2);
12543 // cmovI_reg_lt(op2,op1,cr);
12544 // %}
12545 //%}
12546
12547 // Min Register with Register (generic version)
12548 instruct minI_eReg(eRegI dst, eRegI src, eFlagsReg flags) %{
12549 match(Set dst (MinI dst src));
12550 effect(KILL flags);
12551 ins_cost(300);
12552
12553 format %{ "MIN $dst,$src" %}
12554 opcode(0xCC);
12555 ins_encode( min_enc(dst,src) );
12556 ins_pipe( pipe_slow );
12557 %}
12558
12559 // Max Register with Register
12560 // *** Min and Max using the conditional move are slower than the
12561 // *** branch version on a Pentium III.
12562 // // Conditional move for max
12563 //instruct cmovI_reg_gt( eRegI op2, eRegI op1, eFlagsReg cr ) %{
12564 // effect( USE_DEF op2, USE op1, USE cr );
12565 // format %{ "CMOVgt $op2,$op1\t! max" %}
12566 // opcode(0x4F,0x0F);
12567 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) );
12568 // ins_pipe( pipe_cmov_reg );
12569 //%}
12570 //
12571 // // Max Register with Register (P6 version)
12572 //instruct maxI_eReg_p6( eRegI op1, eRegI op2 ) %{
12573 // predicate(VM_Version::supports_cmov() );
12574 // match(Set op2 (MaxI op1 op2));
12575 // ins_cost(200);
12576 // expand %{
12577 // eFlagsReg cr;
12578 // compI_eReg(cr,op1,op2);
12579 // cmovI_reg_gt(op2,op1,cr);
12580 // %}
12581 //%}
12582
12583 // Max Register with Register (generic version)
12584 instruct maxI_eReg(eRegI dst, eRegI src, eFlagsReg flags) %{
12585 match(Set dst (MaxI dst src));
12586 effect(KILL flags);
12587 ins_cost(300);
12588
12589 format %{ "MAX $dst,$src" %}
12590 opcode(0xCC);
12591 ins_encode( max_enc(dst,src) );
12592 ins_pipe( pipe_slow );
12593 %}
12594
12595 // ============================================================================
12596 // Branch Instructions
12597 // Jump Table
12598 instruct jumpXtnd(eRegI switch_val) %{
12599 match(Jump switch_val);
12600 ins_cost(350);
12601
12602 format %{ "JMP [table_base](,$switch_val,1)\n\t" %}
12603
12604 ins_encode %{
12605 address table_base = __ address_table_constant(_index2label);
12606
12607 // Jump to Address(table_base + switch_reg)
12608 InternalAddress table(table_base);
12609 Address index(noreg, $switch_val$$Register, Address::times_1);
12610 __ jump(ArrayAddress(table, index));
12611 %}
12612 ins_pc_relative(1);
12613 ins_pipe(pipe_jmp);
12614 %}
12615
12616 // Jump Direct - Label defines a relative address from JMP+1
12617 instruct jmpDir(label labl) %{
12618 match(Goto);
12619 effect(USE labl);
12620
12621 ins_cost(300);
12622 format %{ "JMP $labl" %}
12623 size(5);
12624 opcode(0xE9);
12625 ins_encode( OpcP, Lbl( labl ) );
12626 ins_pipe( pipe_jmp );
12627 ins_pc_relative(1);
12628 %}
12629
12630 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12631 instruct jmpCon(cmpOp cop, eFlagsReg cr, label labl) %{
12632 match(If cop cr);
12633 effect(USE labl);
12634
12635 ins_cost(300);
12636 format %{ "J$cop $labl" %}
12637 size(6);
12638 opcode(0x0F, 0x80);
12639 ins_encode( Jcc( cop, labl) );
12640 ins_pipe( pipe_jcc );
12641 ins_pc_relative(1);
12642 %}
12643
12644 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12645 instruct jmpLoopEnd(cmpOp cop, eFlagsReg cr, label labl) %{
12646 match(CountedLoopEnd cop cr);
12647 effect(USE labl);
12648
12649 ins_cost(300);
12650 format %{ "J$cop $labl\t# Loop end" %}
12651 size(6);
12652 opcode(0x0F, 0x80);
12653 ins_encode( Jcc( cop, labl) );
12654 ins_pipe( pipe_jcc );
12655 ins_pc_relative(1);
12656 %}
12657
12658 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12659 instruct jmpLoopEndU(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12660 match(CountedLoopEnd cop cmp);
12661 effect(USE labl);
12662
12663 ins_cost(300);
12664 format %{ "J$cop,u $labl\t# Loop end" %}
12665 size(6);
12666 opcode(0x0F, 0x80);
12667 ins_encode( Jcc( cop, labl) );
12668 ins_pipe( pipe_jcc );
12669 ins_pc_relative(1);
12670 %}
12671
12672 instruct jmpLoopEndUCF(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12673 match(CountedLoopEnd cop cmp);
12674 effect(USE labl);
12675
12676 ins_cost(200);
12677 format %{ "J$cop,u $labl\t# Loop end" %}
12678 size(6);
12679 opcode(0x0F, 0x80);
12680 ins_encode( Jcc( cop, labl) );
12681 ins_pipe( pipe_jcc );
12682 ins_pc_relative(1);
12683 %}
12684
12685 // Jump Direct Conditional - using unsigned comparison
12686 instruct jmpConU(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12687 match(If cop cmp);
12688 effect(USE labl);
12689
12690 ins_cost(300);
12691 format %{ "J$cop,u $labl" %}
12692 size(6);
12693 opcode(0x0F, 0x80);
12694 ins_encode(Jcc(cop, labl));
12695 ins_pipe(pipe_jcc);
12696 ins_pc_relative(1);
12697 %}
12698
12699 instruct jmpConUCF(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12700 match(If cop cmp);
12701 effect(USE labl);
12702
12703 ins_cost(200);
12704 format %{ "J$cop,u $labl" %}
12705 size(6);
12706 opcode(0x0F, 0x80);
12707 ins_encode(Jcc(cop, labl));
12708 ins_pipe(pipe_jcc);
12709 ins_pc_relative(1);
12710 %}
12711
12712 instruct jmpConUCF2(cmpOpUCF2 cop, eFlagsRegUCF cmp, label labl) %{
12713 match(If cop cmp);
12714 effect(USE labl);
12715
12716 ins_cost(200);
12717 format %{ $$template
12718 if ($cop$$cmpcode == Assembler::notEqual) {
12719 $$emit$$"JP,u $labl\n\t"
12720 $$emit$$"J$cop,u $labl"
12721 } else {
12722 $$emit$$"JP,u done\n\t"
12723 $$emit$$"J$cop,u $labl\n\t"
12724 $$emit$$"done:"
12725 }
12726 %}
12727 size(12);
12728 opcode(0x0F, 0x80);
12729 ins_encode %{
12730 Label* l = $labl$$label;
12731 $$$emit8$primary;
12732 emit_cc(cbuf, $secondary, Assembler::parity);
12733 int parity_disp = -1;
12734 bool ok = false;
12735 if ($cop$$cmpcode == Assembler::notEqual) {
12736 // the two jumps 6 bytes apart so the jump distances are too
12737 parity_disp = l ? (l->loc_pos() - (cbuf.code_size() + 4)) : 0;
12738 } else if ($cop$$cmpcode == Assembler::equal) {
12739 parity_disp = 6;
12740 ok = true;
12741 } else {
12742 ShouldNotReachHere();
12743 }
12744 emit_d32(cbuf, parity_disp);
12745 $$$emit8$primary;
12746 emit_cc(cbuf, $secondary, $cop$$cmpcode);
12747 int disp = l ? (l->loc_pos() - (cbuf.code_size() + 4)) : 0;
12748 emit_d32(cbuf, disp);
12749 %}
12750 ins_pipe(pipe_jcc);
12751 ins_pc_relative(1);
12752 %}
12753
12754 // ============================================================================
12755 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
12756 // array for an instance of the superklass. Set a hidden internal cache on a
12757 // hit (cache is checked with exposed code in gen_subtype_check()). Return
12758 // NZ for a miss or zero for a hit. The encoding ALSO sets flags.
12759 instruct partialSubtypeCheck( eDIRegP result, eSIRegP sub, eAXRegP super, eCXRegI rcx, eFlagsReg cr ) %{
12760 match(Set result (PartialSubtypeCheck sub super));
12761 effect( KILL rcx, KILL cr );
12762
12763 ins_cost(1100); // slightly larger than the next version
12764 format %{ "MOV EDI,[$sub+Klass::secondary_supers]\n\t"
12765 "MOV ECX,[EDI+arrayKlass::length]\t# length to scan\n\t"
12766 "ADD EDI,arrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t"
12767 "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t"
12768 "JNE,s miss\t\t# Missed: EDI not-zero\n\t"
12769 "MOV [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache\n\t"
12770 "XOR $result,$result\t\t Hit: EDI zero\n\t"
12771 "miss:\t" %}
12772
12773 opcode(0x1); // Force a XOR of EDI
12774 ins_encode( enc_PartialSubtypeCheck() );
12775 ins_pipe( pipe_slow );
12776 %}
12777
12778 instruct partialSubtypeCheck_vs_Zero( eFlagsReg cr, eSIRegP sub, eAXRegP super, eCXRegI rcx, eDIRegP result, immP0 zero ) %{
12779 match(Set cr (CmpP (PartialSubtypeCheck sub super) zero));
12780 effect( KILL rcx, KILL result );
12781
12782 ins_cost(1000);
12783 format %{ "MOV EDI,[$sub+Klass::secondary_supers]\n\t"
12784 "MOV ECX,[EDI+arrayKlass::length]\t# length to scan\n\t"
12785 "ADD EDI,arrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t"
12786 "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t"
12787 "JNE,s miss\t\t# Missed: flags NZ\n\t"
12788 "MOV [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache, flags Z\n\t"
12789 "miss:\t" %}
12790
12791 opcode(0x0); // No need to XOR EDI
12792 ins_encode( enc_PartialSubtypeCheck() );
12793 ins_pipe( pipe_slow );
12794 %}
12795
12796 // ============================================================================
12797 // Branch Instructions -- short offset versions
12798 //
12799 // These instructions are used to replace jumps of a long offset (the default
12800 // match) with jumps of a shorter offset. These instructions are all tagged
12801 // with the ins_short_branch attribute, which causes the ADLC to suppress the
12802 // match rules in general matching. Instead, the ADLC generates a conversion
12803 // method in the MachNode which can be used to do in-place replacement of the
12804 // long variant with the shorter variant. The compiler will determine if a
12805 // branch can be taken by the is_short_branch_offset() predicate in the machine
12806 // specific code section of the file.
12807
12808 // Jump Direct - Label defines a relative address from JMP+1
12809 instruct jmpDir_short(label labl) %{
12810 match(Goto);
12811 effect(USE labl);
12812
12813 ins_cost(300);
12814 format %{ "JMP,s $labl" %}
12815 size(2);
12816 opcode(0xEB);
12817 ins_encode( OpcP, LblShort( labl ) );
12818 ins_pipe( pipe_jmp );
12819 ins_pc_relative(1);
12820 ins_short_branch(1);
12821 %}
12822
12823 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12824 instruct jmpCon_short(cmpOp cop, eFlagsReg cr, label labl) %{
12825 match(If cop cr);
12826 effect(USE labl);
12827
12828 ins_cost(300);
12829 format %{ "J$cop,s $labl" %}
12830 size(2);
12831 opcode(0x70);
12832 ins_encode( JccShort( cop, labl) );
12833 ins_pipe( pipe_jcc );
12834 ins_pc_relative(1);
12835 ins_short_branch(1);
12836 %}
12837
12838 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12839 instruct jmpLoopEnd_short(cmpOp cop, eFlagsReg cr, label labl) %{
12840 match(CountedLoopEnd cop cr);
12841 effect(USE labl);
12842
12843 ins_cost(300);
12844 format %{ "J$cop,s $labl\t# Loop end" %}
12845 size(2);
12846 opcode(0x70);
12847 ins_encode( JccShort( cop, labl) );
12848 ins_pipe( pipe_jcc );
12849 ins_pc_relative(1);
12850 ins_short_branch(1);
12851 %}
12852
12853 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12854 instruct jmpLoopEndU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12855 match(CountedLoopEnd cop cmp);
12856 effect(USE labl);
12857
12858 ins_cost(300);
12859 format %{ "J$cop,us $labl\t# Loop end" %}
12860 size(2);
12861 opcode(0x70);
12862 ins_encode( JccShort( cop, labl) );
12863 ins_pipe( pipe_jcc );
12864 ins_pc_relative(1);
12865 ins_short_branch(1);
12866 %}
12867
12868 instruct jmpLoopEndUCF_short(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12869 match(CountedLoopEnd cop cmp);
12870 effect(USE labl);
12871
12872 ins_cost(300);
12873 format %{ "J$cop,us $labl\t# Loop end" %}
12874 size(2);
12875 opcode(0x70);
12876 ins_encode( JccShort( cop, labl) );
12877 ins_pipe( pipe_jcc );
12878 ins_pc_relative(1);
12879 ins_short_branch(1);
12880 %}
12881
12882 // Jump Direct Conditional - using unsigned comparison
12883 instruct jmpConU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12884 match(If cop cmp);
12885 effect(USE labl);
12886
12887 ins_cost(300);
12888 format %{ "J$cop,us $labl" %}
12889 size(2);
12890 opcode(0x70);
12891 ins_encode( JccShort( cop, labl) );
12892 ins_pipe( pipe_jcc );
12893 ins_pc_relative(1);
12894 ins_short_branch(1);
12895 %}
12896
12897 instruct jmpConUCF_short(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12898 match(If cop cmp);
12899 effect(USE labl);
12900
12901 ins_cost(300);
12902 format %{ "J$cop,us $labl" %}
12903 size(2);
12904 opcode(0x70);
12905 ins_encode( JccShort( cop, labl) );
12906 ins_pipe( pipe_jcc );
12907 ins_pc_relative(1);
12908 ins_short_branch(1);
12909 %}
12910
12911 instruct jmpConUCF2_short(cmpOpUCF2 cop, eFlagsRegUCF cmp, label labl) %{
12912 match(If cop cmp);
12913 effect(USE labl);
12914
12915 ins_cost(300);
12916 format %{ $$template
12917 if ($cop$$cmpcode == Assembler::notEqual) {
12918 $$emit$$"JP,u,s $labl\n\t"
12919 $$emit$$"J$cop,u,s $labl"
12920 } else {
12921 $$emit$$"JP,u,s done\n\t"
12922 $$emit$$"J$cop,u,s $labl\n\t"
12923 $$emit$$"done:"
12924 }
12925 %}
12926 size(4);
12927 opcode(0x70);
12928 ins_encode %{
12929 Label* l = $labl$$label;
12930 emit_cc(cbuf, $primary, Assembler::parity);
12931 int parity_disp = -1;
12932 if ($cop$$cmpcode == Assembler::notEqual) {
12933 parity_disp = l ? (l->loc_pos() - (cbuf.code_size() + 1)) : 0;
12934 } else if ($cop$$cmpcode == Assembler::equal) {
12935 parity_disp = 2;
12936 } else {
12937 ShouldNotReachHere();
12938 }
12939 emit_d8(cbuf, parity_disp);
12940 emit_cc(cbuf, $primary, $cop$$cmpcode);
12941 int disp = l ? (l->loc_pos() - (cbuf.code_size() + 1)) : 0;
12942 emit_d8(cbuf, disp);
12943 assert(-128 <= disp && disp <= 127, "Displacement too large for short jmp");
12944 assert(-128 <= parity_disp && parity_disp <= 127, "Displacement too large for short jmp");
12945 %}
12946 ins_pipe(pipe_jcc);
12947 ins_pc_relative(1);
12948 ins_short_branch(1);
12949 %}
12950
12951 // ============================================================================
12952 // Long Compare
12953 //
12954 // Currently we hold longs in 2 registers. Comparing such values efficiently
12955 // is tricky. The flavor of compare used depends on whether we are testing
12956 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit.
12957 // The GE test is the negated LT test. The LE test can be had by commuting
12958 // the operands (yielding a GE test) and then negating; negate again for the
12959 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the
12960 // NE test is negated from that.
12961
12962 // Due to a shortcoming in the ADLC, it mixes up expressions like:
12963 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the
12964 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections
12965 // are collapsed internally in the ADLC's dfa-gen code. The match for
12966 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the
12967 // foo match ends up with the wrong leaf. One fix is to not match both
12968 // reg-reg and reg-zero forms of long-compare. This is unfortunate because
12969 // both forms beat the trinary form of long-compare and both are very useful
12970 // on Intel which has so few registers.
12971
12972 // Manifest a CmpL result in an integer register. Very painful.
12973 // This is the test to avoid.
12974 instruct cmpL3_reg_reg(eSIRegI dst, eRegL src1, eRegL src2, eFlagsReg flags ) %{
12975 match(Set dst (CmpL3 src1 src2));
12976 effect( KILL flags );
12977 ins_cost(1000);
12978 format %{ "XOR $dst,$dst\n\t"
12979 "CMP $src1.hi,$src2.hi\n\t"
12980 "JLT,s m_one\n\t"
12981 "JGT,s p_one\n\t"
12982 "CMP $src1.lo,$src2.lo\n\t"
12983 "JB,s m_one\n\t"
12984 "JEQ,s done\n"
12985 "p_one:\tINC $dst\n\t"
12986 "JMP,s done\n"
12987 "m_one:\tDEC $dst\n"
12988 "done:" %}
12989 ins_encode %{
12990 Label p_one, m_one, done;
12991 __ xorptr($dst$$Register, $dst$$Register);
12992 __ cmpl(HIGH_FROM_LOW($src1$$Register), HIGH_FROM_LOW($src2$$Register));
12993 __ jccb(Assembler::less, m_one);
12994 __ jccb(Assembler::greater, p_one);
12995 __ cmpl($src1$$Register, $src2$$Register);
12996 __ jccb(Assembler::below, m_one);
12997 __ jccb(Assembler::equal, done);
12998 __ bind(p_one);
12999 __ incrementl($dst$$Register);
13000 __ jmpb(done);
13001 __ bind(m_one);
13002 __ decrementl($dst$$Register);
13003 __ bind(done);
13004 %}
13005 ins_pipe( pipe_slow );
13006 %}
13007
13008 //======
13009 // Manifest a CmpL result in the normal flags. Only good for LT or GE
13010 // compares. Can be used for LE or GT compares by reversing arguments.
13011 // NOT GOOD FOR EQ/NE tests.
13012 instruct cmpL_zero_flags_LTGE( flagsReg_long_LTGE flags, eRegL src, immL0 zero ) %{
13013 match( Set flags (CmpL src zero ));
13014 ins_cost(100);
13015 format %{ "TEST $src.hi,$src.hi" %}
13016 opcode(0x85);
13017 ins_encode( OpcP, RegReg_Hi2( src, src ) );
13018 ins_pipe( ialu_cr_reg_reg );
13019 %}
13020
13021 // Manifest a CmpL result in the normal flags. Only good for LT or GE
13022 // compares. Can be used for LE or GT compares by reversing arguments.
13023 // NOT GOOD FOR EQ/NE tests.
13024 instruct cmpL_reg_flags_LTGE( flagsReg_long_LTGE flags, eRegL src1, eRegL src2, eRegI tmp ) %{
13025 match( Set flags (CmpL src1 src2 ));
13026 effect( TEMP tmp );
13027 ins_cost(300);
13028 format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t"
13029 "MOV $tmp,$src1.hi\n\t"
13030 "SBB $tmp,$src2.hi\t! Compute flags for long compare" %}
13031 ins_encode( long_cmp_flags2( src1, src2, tmp ) );
13032 ins_pipe( ialu_cr_reg_reg );
13033 %}
13034
13035 // Long compares reg < zero/req OR reg >= zero/req.
13036 // Just a wrapper for a normal branch, plus the predicate test.
13037 instruct cmpL_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, label labl) %{
13038 match(If cmp flags);
13039 effect(USE labl);
13040 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
13041 expand %{
13042 jmpCon(cmp,flags,labl); // JLT or JGE...
13043 %}
13044 %}
13045
13046 // Compare 2 longs and CMOVE longs.
13047 instruct cmovLL_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, eRegL src) %{
13048 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
13049 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
13050 ins_cost(400);
13051 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
13052 "CMOV$cmp $dst.hi,$src.hi" %}
13053 opcode(0x0F,0x40);
13054 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
13055 ins_pipe( pipe_cmov_reg_long );
13056 %}
13057
13058 instruct cmovLL_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, load_long_memory src) %{
13059 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
13060 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
13061 ins_cost(500);
13062 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
13063 "CMOV$cmp $dst.hi,$src.hi" %}
13064 opcode(0x0F,0x40);
13065 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
13066 ins_pipe( pipe_cmov_reg_long );
13067 %}
13068
13069 // Compare 2 longs and CMOVE ints.
13070 instruct cmovII_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegI dst, eRegI src) %{
13071 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
13072 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
13073 ins_cost(200);
13074 format %{ "CMOV$cmp $dst,$src" %}
13075 opcode(0x0F,0x40);
13076 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
13077 ins_pipe( pipe_cmov_reg );
13078 %}
13079
13080 instruct cmovII_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegI dst, memory src) %{
13081 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
13082 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
13083 ins_cost(250);
13084 format %{ "CMOV$cmp $dst,$src" %}
13085 opcode(0x0F,0x40);
13086 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
13087 ins_pipe( pipe_cmov_mem );
13088 %}
13089
13090 // Compare 2 longs and CMOVE ints.
13091 instruct cmovPP_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegP dst, eRegP src) %{
13092 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
13093 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
13094 ins_cost(200);
13095 format %{ "CMOV$cmp $dst,$src" %}
13096 opcode(0x0F,0x40);
13097 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
13098 ins_pipe( pipe_cmov_reg );
13099 %}
13100
13101 // Compare 2 longs and CMOVE doubles
13102 instruct cmovDD_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regD dst, regD src) %{
13103 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
13104 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
13105 ins_cost(200);
13106 expand %{
13107 fcmovD_regS(cmp,flags,dst,src);
13108 %}
13109 %}
13110
13111 // Compare 2 longs and CMOVE doubles
13112 instruct cmovXDD_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regXD dst, regXD src) %{
13113 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
13114 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
13115 ins_cost(200);
13116 expand %{
13117 fcmovXD_regS(cmp,flags,dst,src);
13118 %}
13119 %}
13120
13121 instruct cmovFF_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regF dst, regF src) %{
13122 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
13123 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
13124 ins_cost(200);
13125 expand %{
13126 fcmovF_regS(cmp,flags,dst,src);
13127 %}
13128 %}
13129
13130 instruct cmovXX_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regX dst, regX src) %{
13131 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
13132 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
13133 ins_cost(200);
13134 expand %{
13135 fcmovX_regS(cmp,flags,dst,src);
13136 %}
13137 %}
13138
13139 //======
13140 // Manifest a CmpL result in the normal flags. Only good for EQ/NE compares.
13141 instruct cmpL_zero_flags_EQNE( flagsReg_long_EQNE flags, eRegL src, immL0 zero, eRegI tmp ) %{
13142 match( Set flags (CmpL src zero ));
13143 effect(TEMP tmp);
13144 ins_cost(200);
13145 format %{ "MOV $tmp,$src.lo\n\t"
13146 "OR $tmp,$src.hi\t! Long is EQ/NE 0?" %}
13147 ins_encode( long_cmp_flags0( src, tmp ) );
13148 ins_pipe( ialu_reg_reg_long );
13149 %}
13150
13151 // Manifest a CmpL result in the normal flags. Only good for EQ/NE compares.
13152 instruct cmpL_reg_flags_EQNE( flagsReg_long_EQNE flags, eRegL src1, eRegL src2 ) %{
13153 match( Set flags (CmpL src1 src2 ));
13154 ins_cost(200+300);
13155 format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t"
13156 "JNE,s skip\n\t"
13157 "CMP $src1.hi,$src2.hi\n\t"
13158 "skip:\t" %}
13159 ins_encode( long_cmp_flags1( src1, src2 ) );
13160 ins_pipe( ialu_cr_reg_reg );
13161 %}
13162
13163 // Long compare reg == zero/reg OR reg != zero/reg
13164 // Just a wrapper for a normal branch, plus the predicate test.
13165 instruct cmpL_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, label labl) %{
13166 match(If cmp flags);
13167 effect(USE labl);
13168 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
13169 expand %{
13170 jmpCon(cmp,flags,labl); // JEQ or JNE...
13171 %}
13172 %}
13173
13174 // Compare 2 longs and CMOVE longs.
13175 instruct cmovLL_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, eRegL src) %{
13176 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
13177 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
13178 ins_cost(400);
13179 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
13180 "CMOV$cmp $dst.hi,$src.hi" %}
13181 opcode(0x0F,0x40);
13182 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
13183 ins_pipe( pipe_cmov_reg_long );
13184 %}
13185
13186 instruct cmovLL_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, load_long_memory src) %{
13187 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
13188 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
13189 ins_cost(500);
13190 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
13191 "CMOV$cmp $dst.hi,$src.hi" %}
13192 opcode(0x0F,0x40);
13193 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
13194 ins_pipe( pipe_cmov_reg_long );
13195 %}
13196
13197 // Compare 2 longs and CMOVE ints.
13198 instruct cmovII_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegI dst, eRegI src) %{
13199 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
13200 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
13201 ins_cost(200);
13202 format %{ "CMOV$cmp $dst,$src" %}
13203 opcode(0x0F,0x40);
13204 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
13205 ins_pipe( pipe_cmov_reg );
13206 %}
13207
13208 instruct cmovII_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegI dst, memory src) %{
13209 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
13210 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
13211 ins_cost(250);
13212 format %{ "CMOV$cmp $dst,$src" %}
13213 opcode(0x0F,0x40);
13214 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
13215 ins_pipe( pipe_cmov_mem );
13216 %}
13217
13218 // Compare 2 longs and CMOVE ints.
13219 instruct cmovPP_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegP dst, eRegP src) %{
13220 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
13221 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
13222 ins_cost(200);
13223 format %{ "CMOV$cmp $dst,$src" %}
13224 opcode(0x0F,0x40);
13225 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
13226 ins_pipe( pipe_cmov_reg );
13227 %}
13228
13229 // Compare 2 longs and CMOVE doubles
13230 instruct cmovDD_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regD dst, regD src) %{
13231 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
13232 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
13233 ins_cost(200);
13234 expand %{
13235 fcmovD_regS(cmp,flags,dst,src);
13236 %}
13237 %}
13238
13239 // Compare 2 longs and CMOVE doubles
13240 instruct cmovXDD_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regXD dst, regXD src) %{
13241 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
13242 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
13243 ins_cost(200);
13244 expand %{
13245 fcmovXD_regS(cmp,flags,dst,src);
13246 %}
13247 %}
13248
13249 instruct cmovFF_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regF dst, regF src) %{
13250 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
13251 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
13252 ins_cost(200);
13253 expand %{
13254 fcmovF_regS(cmp,flags,dst,src);
13255 %}
13256 %}
13257
13258 instruct cmovXX_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regX dst, regX src) %{
13259 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
13260 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
13261 ins_cost(200);
13262 expand %{
13263 fcmovX_regS(cmp,flags,dst,src);
13264 %}
13265 %}
13266
13267 //======
13268 // Manifest a CmpL result in the normal flags. Only good for LE or GT compares.
13269 // Same as cmpL_reg_flags_LEGT except must negate src
13270 instruct cmpL_zero_flags_LEGT( flagsReg_long_LEGT flags, eRegL src, immL0 zero, eRegI tmp ) %{
13271 match( Set flags (CmpL src zero ));
13272 effect( TEMP tmp );
13273 ins_cost(300);
13274 format %{ "XOR $tmp,$tmp\t# Long compare for -$src < 0, use commuted test\n\t"
13275 "CMP $tmp,$src.lo\n\t"
13276 "SBB $tmp,$src.hi\n\t" %}
13277 ins_encode( long_cmp_flags3(src, tmp) );
13278 ins_pipe( ialu_reg_reg_long );
13279 %}
13280
13281 // Manifest a CmpL result in the normal flags. Only good for LE or GT compares.
13282 // Same as cmpL_reg_flags_LTGE except operands swapped. Swapping operands
13283 // requires a commuted test to get the same result.
13284 instruct cmpL_reg_flags_LEGT( flagsReg_long_LEGT flags, eRegL src1, eRegL src2, eRegI tmp ) %{
13285 match( Set flags (CmpL src1 src2 ));
13286 effect( TEMP tmp );
13287 ins_cost(300);
13288 format %{ "CMP $src2.lo,$src1.lo\t! Long compare, swapped operands, use with commuted test\n\t"
13289 "MOV $tmp,$src2.hi\n\t"
13290 "SBB $tmp,$src1.hi\t! Compute flags for long compare" %}
13291 ins_encode( long_cmp_flags2( src2, src1, tmp ) );
13292 ins_pipe( ialu_cr_reg_reg );
13293 %}
13294
13295 // Long compares reg < zero/req OR reg >= zero/req.
13296 // Just a wrapper for a normal branch, plus the predicate test
13297 instruct cmpL_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, label labl) %{
13298 match(If cmp flags);
13299 effect(USE labl);
13300 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le );
13301 ins_cost(300);
13302 expand %{
13303 jmpCon(cmp,flags,labl); // JGT or JLE...
13304 %}
13305 %}
13306
13307 // Compare 2 longs and CMOVE longs.
13308 instruct cmovLL_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, eRegL src) %{
13309 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
13310 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
13311 ins_cost(400);
13312 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
13313 "CMOV$cmp $dst.hi,$src.hi" %}
13314 opcode(0x0F,0x40);
13315 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
13316 ins_pipe( pipe_cmov_reg_long );
13317 %}
13318
13319 instruct cmovLL_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, load_long_memory src) %{
13320 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
13321 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
13322 ins_cost(500);
13323 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
13324 "CMOV$cmp $dst.hi,$src.hi+4" %}
13325 opcode(0x0F,0x40);
13326 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
13327 ins_pipe( pipe_cmov_reg_long );
13328 %}
13329
13330 // Compare 2 longs and CMOVE ints.
13331 instruct cmovII_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegI dst, eRegI src) %{
13332 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
13333 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
13334 ins_cost(200);
13335 format %{ "CMOV$cmp $dst,$src" %}
13336 opcode(0x0F,0x40);
13337 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
13338 ins_pipe( pipe_cmov_reg );
13339 %}
13340
13341 instruct cmovII_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegI dst, memory src) %{
13342 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
13343 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
13344 ins_cost(250);
13345 format %{ "CMOV$cmp $dst,$src" %}
13346 opcode(0x0F,0x40);
13347 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
13348 ins_pipe( pipe_cmov_mem );
13349 %}
13350
13351 // Compare 2 longs and CMOVE ptrs.
13352 instruct cmovPP_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegP dst, eRegP src) %{
13353 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
13354 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
13355 ins_cost(200);
13356 format %{ "CMOV$cmp $dst,$src" %}
13357 opcode(0x0F,0x40);
13358 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
13359 ins_pipe( pipe_cmov_reg );
13360 %}
13361
13362 // Compare 2 longs and CMOVE doubles
13363 instruct cmovDD_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regD dst, regD src) %{
13364 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
13365 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
13366 ins_cost(200);
13367 expand %{
13368 fcmovD_regS(cmp,flags,dst,src);
13369 %}
13370 %}
13371
13372 // Compare 2 longs and CMOVE doubles
13373 instruct cmovXDD_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regXD dst, regXD src) %{
13374 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
13375 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
13376 ins_cost(200);
13377 expand %{
13378 fcmovXD_regS(cmp,flags,dst,src);
13379 %}
13380 %}
13381
13382 instruct cmovFF_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regF dst, regF src) %{
13383 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
13384 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
13385 ins_cost(200);
13386 expand %{
13387 fcmovF_regS(cmp,flags,dst,src);
13388 %}
13389 %}
13390
13391
13392 instruct cmovXX_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regX dst, regX src) %{
13393 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
13394 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
13395 ins_cost(200);
13396 expand %{
13397 fcmovX_regS(cmp,flags,dst,src);
13398 %}
13399 %}
13400
13401
13402 // ============================================================================
13403 // Procedure Call/Return Instructions
13404 // Call Java Static Instruction
13405 // Note: If this code changes, the corresponding ret_addr_offset() and
13406 // compute_padding() functions will have to be adjusted.
13407 instruct CallStaticJavaDirect(method meth) %{
13408 match(CallStaticJava);
13409 effect(USE meth);
13410
13411 ins_cost(300);
13412 format %{ "CALL,static " %}
13413 opcode(0xE8); /* E8 cd */
13414 ins_encode( pre_call_FPU,
13415 Java_Static_Call( meth ),
13416 call_epilog,
13417 post_call_FPU );
13418 ins_pipe( pipe_slow );
13419 ins_pc_relative(1);
13420 ins_alignment(4);
13421 %}
13422
13423 // Call Java Dynamic Instruction
13424 // Note: If this code changes, the corresponding ret_addr_offset() and
13425 // compute_padding() functions will have to be adjusted.
13426 instruct CallDynamicJavaDirect(method meth) %{
13427 match(CallDynamicJava);
13428 effect(USE meth);
13429
13430 ins_cost(300);
13431 format %{ "MOV EAX,(oop)-1\n\t"
13432 "CALL,dynamic" %}
13433 opcode(0xE8); /* E8 cd */
13434 ins_encode( pre_call_FPU,
13435 Java_Dynamic_Call( meth ),
13436 call_epilog,
13437 post_call_FPU );
13438 ins_pipe( pipe_slow );
13439 ins_pc_relative(1);
13440 ins_alignment(4);
13441 %}
13442
13443 // Call Runtime Instruction
13444 instruct CallRuntimeDirect(method meth) %{
13445 match(CallRuntime );
13446 effect(USE meth);
13447
13448 ins_cost(300);
13449 format %{ "CALL,runtime " %}
13450 opcode(0xE8); /* E8 cd */
13451 // Use FFREEs to clear entries in float stack
13452 ins_encode( pre_call_FPU,
13453 FFree_Float_Stack_All,
13454 Java_To_Runtime( meth ),
13455 post_call_FPU );
13456 ins_pipe( pipe_slow );
13457 ins_pc_relative(1);
13458 %}
13459
13460 // Call runtime without safepoint
13461 instruct CallLeafDirect(method meth) %{
13462 match(CallLeaf);
13463 effect(USE meth);
13464
13465 ins_cost(300);
13466 format %{ "CALL_LEAF,runtime " %}
13467 opcode(0xE8); /* E8 cd */
13468 ins_encode( pre_call_FPU,
13469 FFree_Float_Stack_All,
13470 Java_To_Runtime( meth ),
13471 Verify_FPU_For_Leaf, post_call_FPU );
13472 ins_pipe( pipe_slow );
13473 ins_pc_relative(1);
13474 %}
13475
13476 instruct CallLeafNoFPDirect(method meth) %{
13477 match(CallLeafNoFP);
13478 effect(USE meth);
13479
13480 ins_cost(300);
13481 format %{ "CALL_LEAF_NOFP,runtime " %}
13482 opcode(0xE8); /* E8 cd */
13483 ins_encode(Java_To_Runtime(meth));
13484 ins_pipe( pipe_slow );
13485 ins_pc_relative(1);
13486 %}
13487
13488
13489 // Return Instruction
13490 // Remove the return address & jump to it.
13491 instruct Ret() %{
13492 match(Return);
13493 format %{ "RET" %}
13494 opcode(0xC3);
13495 ins_encode(OpcP);
13496 ins_pipe( pipe_jmp );
13497 %}
13498
13499 // Tail Call; Jump from runtime stub to Java code.
13500 // Also known as an 'interprocedural jump'.
13501 // Target of jump will eventually return to caller.
13502 // TailJump below removes the return address.
13503 instruct TailCalljmpInd(eRegP_no_EBP jump_target, eBXRegP method_oop) %{
13504 match(TailCall jump_target method_oop );
13505 ins_cost(300);
13506 format %{ "JMP $jump_target \t# EBX holds method oop" %}
13507 opcode(0xFF, 0x4); /* Opcode FF /4 */
13508 ins_encode( OpcP, RegOpc(jump_target) );
13509 ins_pipe( pipe_jmp );
13510 %}
13511
13512
13513 // Tail Jump; remove the return address; jump to target.
13514 // TailCall above leaves the return address around.
13515 instruct tailjmpInd(eRegP_no_EBP jump_target, eAXRegP ex_oop) %{
13516 match( TailJump jump_target ex_oop );
13517 ins_cost(300);
13518 format %{ "POP EDX\t# pop return address into dummy\n\t"
13519 "JMP $jump_target " %}
13520 opcode(0xFF, 0x4); /* Opcode FF /4 */
13521 ins_encode( enc_pop_rdx,
13522 OpcP, RegOpc(jump_target) );
13523 ins_pipe( pipe_jmp );
13524 %}
13525
13526 // Create exception oop: created by stack-crawling runtime code.
13527 // Created exception is now available to this handler, and is setup
13528 // just prior to jumping to this handler. No code emitted.
13529 instruct CreateException( eAXRegP ex_oop )
13530 %{
13531 match(Set ex_oop (CreateEx));
13532
13533 size(0);
13534 // use the following format syntax
13535 format %{ "# exception oop is in EAX; no code emitted" %}
13536 ins_encode();
13537 ins_pipe( empty );
13538 %}
13539
13540
13541 // Rethrow exception:
13542 // The exception oop will come in the first argument position.
13543 // Then JUMP (not call) to the rethrow stub code.
13544 instruct RethrowException()
13545 %{
13546 match(Rethrow);
13547
13548 // use the following format syntax
13549 format %{ "JMP rethrow_stub" %}
13550 ins_encode(enc_rethrow);
13551 ins_pipe( pipe_jmp );
13552 %}
13553
13554 // inlined locking and unlocking
13555
13556
13557 instruct cmpFastLock( eFlagsReg cr, eRegP object, eRegP box, eAXRegI tmp, eRegP scr) %{
13558 match( Set cr (FastLock object box) );
13559 effect( TEMP tmp, TEMP scr );
13560 ins_cost(300);
13561 format %{ "FASTLOCK $object, $box KILLS $tmp,$scr" %}
13562 ins_encode( Fast_Lock(object,box,tmp,scr) );
13563 ins_pipe( pipe_slow );
13564 ins_pc_relative(1);
13565 %}
13566
13567 instruct cmpFastUnlock( eFlagsReg cr, eRegP object, eAXRegP box, eRegP tmp ) %{
13568 match( Set cr (FastUnlock object box) );
13569 effect( TEMP tmp );
13570 ins_cost(300);
13571 format %{ "FASTUNLOCK $object, $box, $tmp" %}
13572 ins_encode( Fast_Unlock(object,box,tmp) );
13573 ins_pipe( pipe_slow );
13574 ins_pc_relative(1);
13575 %}
13576
13577
13578
13579 // ============================================================================
13580 // Safepoint Instruction
13581 instruct safePoint_poll(eFlagsReg cr) %{
13582 match(SafePoint);
13583 effect(KILL cr);
13584
13585 // TODO-FIXME: we currently poll at offset 0 of the safepoint polling page.
13586 // On SPARC that might be acceptable as we can generate the address with
13587 // just a sethi, saving an or. By polling at offset 0 we can end up
13588 // putting additional pressure on the index-0 in the D$. Because of
13589 // alignment (just like the situation at hand) the lower indices tend
13590 // to see more traffic. It'd be better to change the polling address
13591 // to offset 0 of the last $line in the polling page.
13592
13593 format %{ "TSTL #polladdr,EAX\t! Safepoint: poll for GC" %}
13594 ins_cost(125);
13595 size(6) ;
13596 ins_encode( Safepoint_Poll() );
13597 ins_pipe( ialu_reg_mem );
13598 %}
13599
13600 //----------PEEPHOLE RULES-----------------------------------------------------
13601 // These must follow all instruction definitions as they use the names
13602 // defined in the instructions definitions.
13603 //
13604 // peepmatch ( root_instr_name [preceding_instruction]* );
13605 //
13606 // peepconstraint %{
13607 // (instruction_number.operand_name relational_op instruction_number.operand_name
13608 // [, ...] );
13609 // // instruction numbers are zero-based using left to right order in peepmatch
13610 //
13611 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
13612 // // provide an instruction_number.operand_name for each operand that appears
13613 // // in the replacement instruction's match rule
13614 //
13615 // ---------VM FLAGS---------------------------------------------------------
13616 //
13617 // All peephole optimizations can be turned off using -XX:-OptoPeephole
13618 //
13619 // Each peephole rule is given an identifying number starting with zero and
13620 // increasing by one in the order seen by the parser. An individual peephole
13621 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
13622 // on the command-line.
13623 //
13624 // ---------CURRENT LIMITATIONS----------------------------------------------
13625 //
13626 // Only match adjacent instructions in same basic block
13627 // Only equality constraints
13628 // Only constraints between operands, not (0.dest_reg == EAX_enc)
13629 // Only one replacement instruction
13630 //
13631 // ---------EXAMPLE----------------------------------------------------------
13632 //
13633 // // pertinent parts of existing instructions in architecture description
13634 // instruct movI(eRegI dst, eRegI src) %{
13635 // match(Set dst (CopyI src));
13636 // %}
13637 //
13638 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
13639 // match(Set dst (AddI dst src));
13640 // effect(KILL cr);
13641 // %}
13642 //
13643 // // Change (inc mov) to lea
13644 // peephole %{
13645 // // increment preceeded by register-register move
13646 // peepmatch ( incI_eReg movI );
13647 // // require that the destination register of the increment
13648 // // match the destination register of the move
13649 // peepconstraint ( 0.dst == 1.dst );
13650 // // construct a replacement instruction that sets
13651 // // the destination to ( move's source register + one )
13652 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13653 // %}
13654 //
13655 // Implementation no longer uses movX instructions since
13656 // machine-independent system no longer uses CopyX nodes.
13657 //
13658 // peephole %{
13659 // peepmatch ( incI_eReg movI );
13660 // peepconstraint ( 0.dst == 1.dst );
13661 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13662 // %}
13663 //
13664 // peephole %{
13665 // peepmatch ( decI_eReg movI );
13666 // peepconstraint ( 0.dst == 1.dst );
13667 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13668 // %}
13669 //
13670 // peephole %{
13671 // peepmatch ( addI_eReg_imm movI );
13672 // peepconstraint ( 0.dst == 1.dst );
13673 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13674 // %}
13675 //
13676 // peephole %{
13677 // peepmatch ( addP_eReg_imm movP );
13678 // peepconstraint ( 0.dst == 1.dst );
13679 // peepreplace ( leaP_eReg_immI( 0.dst 1.src 0.src ) );
13680 // %}
13681
13682 // // Change load of spilled value to only a spill
13683 // instruct storeI(memory mem, eRegI src) %{
13684 // match(Set mem (StoreI mem src));
13685 // %}
13686 //
13687 // instruct loadI(eRegI dst, memory mem) %{
13688 // match(Set dst (LoadI mem));
13689 // %}
13690 //
13691 peephole %{
13692 peepmatch ( loadI storeI );
13693 peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
13694 peepreplace ( storeI( 1.mem 1.mem 1.src ) );
13695 %}
13696
13697 //----------SMARTSPILL RULES---------------------------------------------------
13698 // These must follow all instruction definitions as they use the names
13699 // defined in the instructions definitions.