1 //
2 // Copyright 1997-2009 Sun Microsystems, Inc. All Rights Reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
9 // This code is distributed in the hope that it will be useful, but WITHOUT
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
15 // You should have received a copy of the GNU General Public License version
16 // 2 along with this work; if not, write to the Free Software Foundation,
17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 //
19 // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
20 // CA 95054 USA or visit www.sun.com if you need additional information or
21 // have any questions.
22 //
23 //
24
25 // X86 Architecture Description File
26
27 //----------REGISTER DEFINITION BLOCK------------------------------------------
28 // This information is used by the matcher and the register allocator to
29 // describe individual registers and classes of registers within the target
30 // archtecture.
31
32 register %{
33 //----------Architecture Description Register Definitions----------------------
34 // General Registers
35 // "reg_def" name ( register save type, C convention save type,
36 // ideal register type, encoding );
37 // Register Save Types:
38 //
39 // NS = No-Save: The register allocator assumes that these registers
40 // can be used without saving upon entry to the method, &
41 // that they do not need to be saved at call sites.
42 //
43 // SOC = Save-On-Call: The register allocator assumes that these registers
44 // can be used without saving upon entry to the method,
45 // but that they must be saved at call sites.
46 //
47 // SOE = Save-On-Entry: The register allocator assumes that these registers
48 // must be saved before using them upon entry to the
49 // method, but they do not need to be saved at call
50 // sites.
51 //
52 // AS = Always-Save: The register allocator assumes that these registers
53 // must be saved before using them upon entry to the
54 // method, & that they must be saved at call sites.
55 //
56 // Ideal Register Type is used to determine how to save & restore a
57 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
58 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
59 //
60 // The encoding number is the actual bit-pattern placed into the opcodes.
61
62 // General Registers
63 // Previously set EBX, ESI, and EDI as save-on-entry for java code
64 // Turn off SOE in java-code due to frequent use of uncommon-traps.
65 // Now that allocator is better, turn on ESI and EDI as SOE registers.
66
67 reg_def EBX(SOC, SOE, Op_RegI, 3, rbx->as_VMReg());
68 reg_def ECX(SOC, SOC, Op_RegI, 1, rcx->as_VMReg());
69 reg_def ESI(SOC, SOE, Op_RegI, 6, rsi->as_VMReg());
70 reg_def EDI(SOC, SOE, Op_RegI, 7, rdi->as_VMReg());
71 // now that adapter frames are gone EBP is always saved and restored by the prolog/epilog code
72 reg_def EBP(NS, SOE, Op_RegI, 5, rbp->as_VMReg());
73 reg_def EDX(SOC, SOC, Op_RegI, 2, rdx->as_VMReg());
74 reg_def EAX(SOC, SOC, Op_RegI, 0, rax->as_VMReg());
75 reg_def ESP( NS, NS, Op_RegI, 4, rsp->as_VMReg());
76
77 // Special Registers
78 reg_def EFLAGS(SOC, SOC, 0, 8, VMRegImpl::Bad());
79
80 // Float registers. We treat TOS/FPR0 special. It is invisible to the
81 // allocator, and only shows up in the encodings.
82 reg_def FPR0L( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad());
83 reg_def FPR0H( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad());
84 // Ok so here's the trick FPR1 is really st(0) except in the midst
85 // of emission of assembly for a machnode. During the emission the fpu stack
86 // is pushed making FPR1 == st(1) temporarily. However at any safepoint
87 // the stack will not have this element so FPR1 == st(0) from the
88 // oopMap viewpoint. This same weirdness with numbering causes
89 // instruction encoding to have to play games with the register
90 // encode to correct for this 0/1 issue. See MachSpillCopyNode::implementation
91 // where it does flt->flt moves to see an example
92 //
93 reg_def FPR1L( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg());
94 reg_def FPR1H( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg()->next());
95 reg_def FPR2L( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg());
96 reg_def FPR2H( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg()->next());
97 reg_def FPR3L( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg());
98 reg_def FPR3H( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg()->next());
99 reg_def FPR4L( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg());
100 reg_def FPR4H( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg()->next());
101 reg_def FPR5L( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg());
102 reg_def FPR5H( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg()->next());
103 reg_def FPR6L( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg());
104 reg_def FPR6H( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg()->next());
105 reg_def FPR7L( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg());
106 reg_def FPR7H( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg()->next());
107
108 // XMM registers. 128-bit registers or 4 words each, labeled a-d.
109 // Word a in each register holds a Float, words ab hold a Double.
110 // We currently do not use the SIMD capabilities, so registers cd
111 // are unused at the moment.
112 reg_def XMM0a( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg());
113 reg_def XMM0b( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()->next());
114 reg_def XMM1a( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg());
115 reg_def XMM1b( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()->next());
116 reg_def XMM2a( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg());
117 reg_def XMM2b( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()->next());
118 reg_def XMM3a( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg());
119 reg_def XMM3b( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()->next());
120 reg_def XMM4a( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg());
121 reg_def XMM4b( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()->next());
122 reg_def XMM5a( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg());
123 reg_def XMM5b( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()->next());
124 reg_def XMM6a( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg());
125 reg_def XMM6b( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()->next());
126 reg_def XMM7a( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg());
127 reg_def XMM7b( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()->next());
128
129 // Specify priority of register selection within phases of register
130 // allocation. Highest priority is first. A useful heuristic is to
131 // give registers a low priority when they are required by machine
132 // instructions, like EAX and EDX. Registers which are used as
133 // pairs must fall on an even boundary (witness the FPR#L's in this list).
134 // For the Intel integer registers, the equivalent Long pairs are
135 // EDX:EAX, EBX:ECX, and EDI:EBP.
136 alloc_class chunk0( ECX, EBX, EBP, EDI, EAX, EDX, ESI, ESP,
137 FPR0L, FPR0H, FPR1L, FPR1H, FPR2L, FPR2H,
138 FPR3L, FPR3H, FPR4L, FPR4H, FPR5L, FPR5H,
139 FPR6L, FPR6H, FPR7L, FPR7H );
140
141 alloc_class chunk1( XMM0a, XMM0b,
142 XMM1a, XMM1b,
143 XMM2a, XMM2b,
144 XMM3a, XMM3b,
145 XMM4a, XMM4b,
146 XMM5a, XMM5b,
147 XMM6a, XMM6b,
148 XMM7a, XMM7b, EFLAGS);
149
150
151 //----------Architecture Description Register Classes--------------------------
152 // Several register classes are automatically defined based upon information in
153 // this architecture description.
154 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ )
155 // 2) reg_class compiler_method_oop_reg ( /* as def'd in frame section */ )
156 // 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ )
157 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
158 //
159 // Class for all registers
160 reg_class any_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX, ESP);
161 // Class for general registers
162 reg_class e_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX);
163 // Class for general registers which may be used for implicit null checks on win95
164 // Also safe for use by tailjump. We don't want to allocate in rbp,
165 reg_class e_reg_no_rbp(EAX, EDX, EDI, ESI, ECX, EBX);
166 // Class of "X" registers
167 reg_class x_reg(EBX, ECX, EDX, EAX);
168 // Class of registers that can appear in an address with no offset.
169 // EBP and ESP require an extra instruction byte for zero offset.
170 // Used in fast-unlock
171 reg_class p_reg(EDX, EDI, ESI, EBX);
172 // Class for general registers not including ECX
173 reg_class ncx_reg(EAX, EDX, EBP, EDI, ESI, EBX);
174 // Class for general registers not including EAX
175 reg_class nax_reg(EDX, EDI, ESI, ECX, EBX);
176 // Class for general registers not including EAX or EBX.
177 reg_class nabx_reg(EDX, EDI, ESI, ECX, EBP);
178 // Class of EAX (for multiply and divide operations)
179 reg_class eax_reg(EAX);
180 // Class of EBX (for atomic add)
181 reg_class ebx_reg(EBX);
182 // Class of ECX (for shift and JCXZ operations and cmpLTMask)
183 reg_class ecx_reg(ECX);
184 // Class of EDX (for multiply and divide operations)
185 reg_class edx_reg(EDX);
186 // Class of EDI (for synchronization)
187 reg_class edi_reg(EDI);
188 // Class of ESI (for synchronization)
189 reg_class esi_reg(ESI);
190 // Singleton class for interpreter's stack pointer
191 reg_class ebp_reg(EBP);
192 // Singleton class for stack pointer
193 reg_class sp_reg(ESP);
194 // Singleton class for instruction pointer
195 // reg_class ip_reg(EIP);
196 // Singleton class for condition codes
197 reg_class int_flags(EFLAGS);
198 // Class of integer register pairs
199 reg_class long_reg( EAX,EDX, ECX,EBX, EBP,EDI );
200 // Class of integer register pairs that aligns with calling convention
201 reg_class eadx_reg( EAX,EDX );
202 reg_class ebcx_reg( ECX,EBX );
203 // Not AX or DX, used in divides
204 reg_class nadx_reg( EBX,ECX,ESI,EDI,EBP );
205
206 // Floating point registers. Notice FPR0 is not a choice.
207 // FPR0 is not ever allocated; we use clever encodings to fake
208 // a 2-address instructions out of Intels FP stack.
209 reg_class flt_reg( FPR1L,FPR2L,FPR3L,FPR4L,FPR5L,FPR6L,FPR7L );
210
211 // make a register class for SSE registers
212 reg_class xmm_reg(XMM0a, XMM1a, XMM2a, XMM3a, XMM4a, XMM5a, XMM6a, XMM7a);
213
214 // make a double register class for SSE2 registers
215 reg_class xdb_reg(XMM0a,XMM0b, XMM1a,XMM1b, XMM2a,XMM2b, XMM3a,XMM3b,
216 XMM4a,XMM4b, XMM5a,XMM5b, XMM6a,XMM6b, XMM7a,XMM7b );
217
218 reg_class dbl_reg( FPR1L,FPR1H, FPR2L,FPR2H, FPR3L,FPR3H,
219 FPR4L,FPR4H, FPR5L,FPR5H, FPR6L,FPR6H,
220 FPR7L,FPR7H );
221
222 reg_class flt_reg0( FPR1L );
223 reg_class dbl_reg0( FPR1L,FPR1H );
224 reg_class dbl_reg1( FPR2L,FPR2H );
225 reg_class dbl_notreg0( FPR2L,FPR2H, FPR3L,FPR3H, FPR4L,FPR4H,
226 FPR5L,FPR5H, FPR6L,FPR6H, FPR7L,FPR7H );
227
228 // XMM6 and XMM7 could be used as temporary registers for long, float and
229 // double values for SSE2.
230 reg_class xdb_reg6( XMM6a,XMM6b );
231 reg_class xdb_reg7( XMM7a,XMM7b );
232 %}
233
234
235 //----------SOURCE BLOCK-------------------------------------------------------
236 // This is a block of C++ code which provides values, functions, and
237 // definitions necessary in the rest of the architecture description
238 source %{
239 #define RELOC_IMM32 Assembler::imm_operand
240 #define RELOC_DISP32 Assembler::disp32_operand
241
242 #define __ _masm.
243
244 // How to find the high register of a Long pair, given the low register
245 #define HIGH_FROM_LOW(x) ((x)+2)
246
247 // These masks are used to provide 128-bit aligned bitmasks to the XMM
248 // instructions, to allow sign-masking or sign-bit flipping. They allow
249 // fast versions of NegF/NegD and AbsF/AbsD.
250
251 // Note: 'double' and 'long long' have 32-bits alignment on x86.
252 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) {
253 // Use the expression (adr)&(~0xF) to provide 128-bits aligned address
254 // of 128-bits operands for SSE instructions.
255 jlong *operand = (jlong*)(((uintptr_t)adr)&((uintptr_t)(~0xF)));
256 // Store the value to a 128-bits operand.
257 operand[0] = lo;
258 operand[1] = hi;
259 return operand;
260 }
261
262 // Buffer for 128-bits masks used by SSE instructions.
263 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment)
264
265 // Static initialization during VM startup.
266 static jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF));
267 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF));
268 static jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], CONST64(0x8000000080000000), CONST64(0x8000000080000000));
269 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], CONST64(0x8000000000000000), CONST64(0x8000000000000000));
270
271 // Offset hacking within calls.
272 static int pre_call_FPU_size() {
273 if (Compile::current()->in_24_bit_fp_mode())
274 return 6; // fldcw
275 return 0;
276 }
277
278 static int preserve_SP_size() {
279 return LP64_ONLY(1 +) 2; // [rex,] op, rm(reg/reg)
280 }
281
282 // !!!!! Special hack to get all type of calls to specify the byte offset
283 // from the start of the call to the point where the return address
284 // will point.
285 int MachCallStaticJavaNode::ret_addr_offset() {
286 int offset = 5 + pre_call_FPU_size(); // 5 bytes from start of call to where return address points
287 if (_method_handle_invoke)
288 offset += preserve_SP_size();
289 return offset;
290 }
291
292 int MachCallDynamicJavaNode::ret_addr_offset() {
293 return 10 + pre_call_FPU_size(); // 10 bytes from start of call to where return address points
294 }
295
296 static int sizeof_FFree_Float_Stack_All = -1;
297
298 int MachCallRuntimeNode::ret_addr_offset() {
299 assert(sizeof_FFree_Float_Stack_All != -1, "must have been emitted already");
300 return sizeof_FFree_Float_Stack_All + 5 + pre_call_FPU_size();
301 }
302
303 // Indicate if the safepoint node needs the polling page as an input.
304 // Since x86 does have absolute addressing, it doesn't.
305 bool SafePointNode::needs_polling_address_input() {
306 return false;
307 }
308
309 //
310 // Compute padding required for nodes which need alignment
311 //
312
313 // The address of the call instruction needs to be 4-byte aligned to
314 // ensure that it does not span a cache line so that it can be patched.
315 int CallStaticJavaDirectNode::compute_padding(int current_offset) const {
316 current_offset += pre_call_FPU_size(); // skip fldcw, if any
317 current_offset += 1; // skip call opcode byte
318 return round_to(current_offset, alignment_required()) - current_offset;
319 }
320
321 // The address of the call instruction needs to be 4-byte aligned to
322 // ensure that it does not span a cache line so that it can be patched.
323 int CallStaticJavaHandleNode::compute_padding(int current_offset) const {
324 current_offset += pre_call_FPU_size(); // skip fldcw, if any
325 current_offset += preserve_SP_size(); // skip mov rbp, rsp
326 current_offset += 1; // skip call opcode byte
327 return round_to(current_offset, alignment_required()) - current_offset;
328 }
329
330 // The address of the call instruction needs to be 4-byte aligned to
331 // ensure that it does not span a cache line so that it can be patched.
332 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const {
333 current_offset += pre_call_FPU_size(); // skip fldcw, if any
334 current_offset += 5; // skip MOV instruction
335 current_offset += 1; // skip call opcode byte
336 return round_to(current_offset, alignment_required()) - current_offset;
337 }
338
339 #ifndef PRODUCT
340 void MachBreakpointNode::format( PhaseRegAlloc *, outputStream* st ) const {
341 st->print("INT3");
342 }
343 #endif
344
345 // EMIT_RM()
346 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) {
347 unsigned char c = (unsigned char)((f1 << 6) | (f2 << 3) | f3);
348 *(cbuf.code_end()) = c;
349 cbuf.set_code_end(cbuf.code_end() + 1);
350 }
351
352 // EMIT_CC()
353 void emit_cc(CodeBuffer &cbuf, int f1, int f2) {
354 unsigned char c = (unsigned char)( f1 | f2 );
355 *(cbuf.code_end()) = c;
356 cbuf.set_code_end(cbuf.code_end() + 1);
357 }
358
359 // EMIT_OPCODE()
360 void emit_opcode(CodeBuffer &cbuf, int code) {
361 *(cbuf.code_end()) = (unsigned char)code;
362 cbuf.set_code_end(cbuf.code_end() + 1);
363 }
364
365 // EMIT_OPCODE() w/ relocation information
366 void emit_opcode(CodeBuffer &cbuf, int code, relocInfo::relocType reloc, int offset = 0) {
367 cbuf.relocate(cbuf.inst_mark() + offset, reloc);
368 emit_opcode(cbuf, code);
369 }
370
371 // EMIT_D8()
372 void emit_d8(CodeBuffer &cbuf, int d8) {
373 *(cbuf.code_end()) = (unsigned char)d8;
374 cbuf.set_code_end(cbuf.code_end() + 1);
375 }
376
377 // EMIT_D16()
378 void emit_d16(CodeBuffer &cbuf, int d16) {
379 *((short *)(cbuf.code_end())) = d16;
380 cbuf.set_code_end(cbuf.code_end() + 2);
381 }
382
383 // EMIT_D32()
384 void emit_d32(CodeBuffer &cbuf, int d32) {
385 *((int *)(cbuf.code_end())) = d32;
386 cbuf.set_code_end(cbuf.code_end() + 4);
387 }
388
389 // emit 32 bit value and construct relocation entry from relocInfo::relocType
390 void emit_d32_reloc(CodeBuffer &cbuf, int d32, relocInfo::relocType reloc,
391 int format) {
392 cbuf.relocate(cbuf.inst_mark(), reloc, format);
393
394 *((int *)(cbuf.code_end())) = d32;
395 cbuf.set_code_end(cbuf.code_end() + 4);
396 }
397
398 // emit 32 bit value and construct relocation entry from RelocationHolder
399 void emit_d32_reloc(CodeBuffer &cbuf, int d32, RelocationHolder const& rspec,
400 int format) {
401 #ifdef ASSERT
402 if (rspec.reloc()->type() == relocInfo::oop_type && d32 != 0 && d32 != (int)Universe::non_oop_word()) {
403 assert(oop(d32)->is_oop() && (ScavengeRootsInCode || !oop(d32)->is_scavengable()), "cannot embed scavengable oops in code");
404 }
405 #endif
406 cbuf.relocate(cbuf.inst_mark(), rspec, format);
407
408 *((int *)(cbuf.code_end())) = d32;
409 cbuf.set_code_end(cbuf.code_end() + 4);
410 }
411
412 // Access stack slot for load or store
413 void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp) {
414 emit_opcode( cbuf, opcode ); // (e.g., FILD [ESP+src])
415 if( -128 <= disp && disp <= 127 ) {
416 emit_rm( cbuf, 0x01, rm_field, ESP_enc ); // R/M byte
417 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
418 emit_d8 (cbuf, disp); // Displacement // R/M byte
419 } else {
420 emit_rm( cbuf, 0x02, rm_field, ESP_enc ); // R/M byte
421 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
422 emit_d32(cbuf, disp); // Displacement // R/M byte
423 }
424 }
425
426 // eRegI ereg, memory mem) %{ // emit_reg_mem
427 void encode_RegMem( CodeBuffer &cbuf, int reg_encoding, int base, int index, int scale, int displace, bool displace_is_oop ) {
428 // There is no index & no scale, use form without SIB byte
429 if ((index == 0x4) &&
430 (scale == 0) && (base != ESP_enc)) {
431 // If no displacement, mode is 0x0; unless base is [EBP]
432 if ( (displace == 0) && (base != EBP_enc) ) {
433 emit_rm(cbuf, 0x0, reg_encoding, base);
434 }
435 else { // If 8-bit displacement, mode 0x1
436 if ((displace >= -128) && (displace <= 127)
437 && !(displace_is_oop) ) {
438 emit_rm(cbuf, 0x1, reg_encoding, base);
439 emit_d8(cbuf, displace);
440 }
441 else { // If 32-bit displacement
442 if (base == -1) { // Special flag for absolute address
443 emit_rm(cbuf, 0x0, reg_encoding, 0x5);
444 // (manual lies; no SIB needed here)
445 if ( displace_is_oop ) {
446 emit_d32_reloc(cbuf, displace, relocInfo::oop_type, 1);
447 } else {
448 emit_d32 (cbuf, displace);
449 }
450 }
451 else { // Normal base + offset
452 emit_rm(cbuf, 0x2, reg_encoding, base);
453 if ( displace_is_oop ) {
454 emit_d32_reloc(cbuf, displace, relocInfo::oop_type, 1);
455 } else {
456 emit_d32 (cbuf, displace);
457 }
458 }
459 }
460 }
461 }
462 else { // Else, encode with the SIB byte
463 // If no displacement, mode is 0x0; unless base is [EBP]
464 if (displace == 0 && (base != EBP_enc)) { // If no displacement
465 emit_rm(cbuf, 0x0, reg_encoding, 0x4);
466 emit_rm(cbuf, scale, index, base);
467 }
468 else { // If 8-bit displacement, mode 0x1
469 if ((displace >= -128) && (displace <= 127)
470 && !(displace_is_oop) ) {
471 emit_rm(cbuf, 0x1, reg_encoding, 0x4);
472 emit_rm(cbuf, scale, index, base);
473 emit_d8(cbuf, displace);
474 }
475 else { // If 32-bit displacement
476 if (base == 0x04 ) {
477 emit_rm(cbuf, 0x2, reg_encoding, 0x4);
478 emit_rm(cbuf, scale, index, 0x04);
479 } else {
480 emit_rm(cbuf, 0x2, reg_encoding, 0x4);
481 emit_rm(cbuf, scale, index, base);
482 }
483 if ( displace_is_oop ) {
484 emit_d32_reloc(cbuf, displace, relocInfo::oop_type, 1);
485 } else {
486 emit_d32 (cbuf, displace);
487 }
488 }
489 }
490 }
491 }
492
493
494 void encode_Copy( CodeBuffer &cbuf, int dst_encoding, int src_encoding ) {
495 if( dst_encoding == src_encoding ) {
496 // reg-reg copy, use an empty encoding
497 } else {
498 emit_opcode( cbuf, 0x8B );
499 emit_rm(cbuf, 0x3, dst_encoding, src_encoding );
500 }
501 }
502
503 void encode_CopyXD( CodeBuffer &cbuf, int dst_encoding, int src_encoding ) {
504 if( dst_encoding == src_encoding ) {
505 // reg-reg copy, use an empty encoding
506 } else {
507 MacroAssembler _masm(&cbuf);
508
509 __ movdqa(as_XMMRegister(dst_encoding), as_XMMRegister(src_encoding));
510 }
511 }
512
513
514 //=============================================================================
515 #ifndef PRODUCT
516 void MachPrologNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
517 Compile* C = ra_->C;
518 if( C->in_24_bit_fp_mode() ) {
519 st->print("FLDCW 24 bit fpu control word");
520 st->print_cr(""); st->print("\t");
521 }
522
523 int framesize = C->frame_slots() << LogBytesPerInt;
524 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
525 // Remove two words for return addr and rbp,
526 framesize -= 2*wordSize;
527
528 // Calls to C2R adapters often do not accept exceptional returns.
529 // We require that their callers must bang for them. But be careful, because
530 // some VM calls (such as call site linkage) can use several kilobytes of
531 // stack. But the stack safety zone should account for that.
532 // See bugs 4446381, 4468289, 4497237.
533 if (C->need_stack_bang(framesize)) {
534 st->print_cr("# stack bang"); st->print("\t");
535 }
536 st->print_cr("PUSHL EBP"); st->print("\t");
537
538 if( VerifyStackAtCalls ) { // Majik cookie to verify stack depth
539 st->print("PUSH 0xBADB100D\t# Majik cookie for stack depth check");
540 st->print_cr(""); st->print("\t");
541 framesize -= wordSize;
542 }
543
544 if ((C->in_24_bit_fp_mode() || VerifyStackAtCalls ) && framesize < 128 ) {
545 if (framesize) {
546 st->print("SUB ESP,%d\t# Create frame",framesize);
547 }
548 } else {
549 st->print("SUB ESP,%d\t# Create frame",framesize);
550 }
551 }
552 #endif
553
554
555 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
556 Compile* C = ra_->C;
557
558 if (UseSSE >= 2 && VerifyFPU) {
559 MacroAssembler masm(&cbuf);
560 masm.verify_FPU(0, "FPU stack must be clean on entry");
561 }
562
563 // WARNING: Initial instruction MUST be 5 bytes or longer so that
564 // NativeJump::patch_verified_entry will be able to patch out the entry
565 // code safely. The fldcw is ok at 6 bytes, the push to verify stack
566 // depth is ok at 5 bytes, the frame allocation can be either 3 or
567 // 6 bytes. So if we don't do the fldcw or the push then we must
568 // use the 6 byte frame allocation even if we have no frame. :-(
569 // If method sets FPU control word do it now
570 if( C->in_24_bit_fp_mode() ) {
571 MacroAssembler masm(&cbuf);
572 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
573 }
574
575 int framesize = C->frame_slots() << LogBytesPerInt;
576 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
577 // Remove two words for return addr and rbp,
578 framesize -= 2*wordSize;
579
580 // Calls to C2R adapters often do not accept exceptional returns.
581 // We require that their callers must bang for them. But be careful, because
582 // some VM calls (such as call site linkage) can use several kilobytes of
583 // stack. But the stack safety zone should account for that.
584 // See bugs 4446381, 4468289, 4497237.
585 if (C->need_stack_bang(framesize)) {
586 MacroAssembler masm(&cbuf);
587 masm.generate_stack_overflow_check(framesize);
588 }
589
590 // We always push rbp, so that on return to interpreter rbp, will be
591 // restored correctly and we can correct the stack.
592 emit_opcode(cbuf, 0x50 | EBP_enc);
593
594 if( VerifyStackAtCalls ) { // Majik cookie to verify stack depth
595 emit_opcode(cbuf, 0x68); // push 0xbadb100d
596 emit_d32(cbuf, 0xbadb100d);
597 framesize -= wordSize;
598 }
599
600 if ((C->in_24_bit_fp_mode() || VerifyStackAtCalls ) && framesize < 128 ) {
601 if (framesize) {
602 emit_opcode(cbuf, 0x83); // sub SP,#framesize
603 emit_rm(cbuf, 0x3, 0x05, ESP_enc);
604 emit_d8(cbuf, framesize);
605 }
606 } else {
607 emit_opcode(cbuf, 0x81); // sub SP,#framesize
608 emit_rm(cbuf, 0x3, 0x05, ESP_enc);
609 emit_d32(cbuf, framesize);
610 }
611 C->set_frame_complete(cbuf.code_end() - cbuf.code_begin());
612
613 #ifdef ASSERT
614 if (VerifyStackAtCalls) {
615 Label L;
616 MacroAssembler masm(&cbuf);
617 masm.push(rax);
618 masm.mov(rax, rsp);
619 masm.andptr(rax, StackAlignmentInBytes-1);
620 masm.cmpptr(rax, StackAlignmentInBytes-wordSize);
621 masm.pop(rax);
622 masm.jcc(Assembler::equal, L);
623 masm.stop("Stack is not properly aligned!");
624 masm.bind(L);
625 }
626 #endif
627
628 }
629
630 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
631 return MachNode::size(ra_); // too many variables; just compute it the hard way
632 }
633
634 int MachPrologNode::reloc() const {
635 return 0; // a large enough number
636 }
637
638 //=============================================================================
639 #ifndef PRODUCT
640 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
641 Compile *C = ra_->C;
642 int framesize = C->frame_slots() << LogBytesPerInt;
643 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
644 // Remove two words for return addr and rbp,
645 framesize -= 2*wordSize;
646
647 if( C->in_24_bit_fp_mode() ) {
648 st->print("FLDCW standard control word");
649 st->cr(); st->print("\t");
650 }
651 if( framesize ) {
652 st->print("ADD ESP,%d\t# Destroy frame",framesize);
653 st->cr(); st->print("\t");
654 }
655 st->print_cr("POPL EBP"); st->print("\t");
656 if( do_polling() && C->is_method_compilation() ) {
657 st->print("TEST PollPage,EAX\t! Poll Safepoint");
658 st->cr(); st->print("\t");
659 }
660 }
661 #endif
662
663 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
664 Compile *C = ra_->C;
665
666 // If method set FPU control word, restore to standard control word
667 if( C->in_24_bit_fp_mode() ) {
668 MacroAssembler masm(&cbuf);
669 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
670 }
671
672 int framesize = C->frame_slots() << LogBytesPerInt;
673 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
674 // Remove two words for return addr and rbp,
675 framesize -= 2*wordSize;
676
677 // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here
678
679 if( framesize >= 128 ) {
680 emit_opcode(cbuf, 0x81); // add SP, #framesize
681 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
682 emit_d32(cbuf, framesize);
683 }
684 else if( framesize ) {
685 emit_opcode(cbuf, 0x83); // add SP, #framesize
686 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
687 emit_d8(cbuf, framesize);
688 }
689
690 emit_opcode(cbuf, 0x58 | EBP_enc);
691
692 if( do_polling() && C->is_method_compilation() ) {
693 cbuf.relocate(cbuf.code_end(), relocInfo::poll_return_type, 0);
694 emit_opcode(cbuf,0x85);
695 emit_rm(cbuf, 0x0, EAX_enc, 0x5); // EAX
696 emit_d32(cbuf, (intptr_t)os::get_polling_page());
697 }
698 }
699
700 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
701 Compile *C = ra_->C;
702 // If method set FPU control word, restore to standard control word
703 int size = C->in_24_bit_fp_mode() ? 6 : 0;
704 if( do_polling() && C->is_method_compilation() ) size += 6;
705
706 int framesize = C->frame_slots() << LogBytesPerInt;
707 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
708 // Remove two words for return addr and rbp,
709 framesize -= 2*wordSize;
710
711 size++; // popl rbp,
712
713 if( framesize >= 128 ) {
714 size += 6;
715 } else {
716 size += framesize ? 3 : 0;
717 }
718 return size;
719 }
720
721 int MachEpilogNode::reloc() const {
722 return 0; // a large enough number
723 }
724
725 const Pipeline * MachEpilogNode::pipeline() const {
726 return MachNode::pipeline_class();
727 }
728
729 int MachEpilogNode::safepoint_offset() const { return 0; }
730
731 //=============================================================================
732
733 enum RC { rc_bad, rc_int, rc_float, rc_xmm, rc_stack };
734 static enum RC rc_class( OptoReg::Name reg ) {
735
736 if( !OptoReg::is_valid(reg) ) return rc_bad;
737 if (OptoReg::is_stack(reg)) return rc_stack;
738
739 VMReg r = OptoReg::as_VMReg(reg);
740 if (r->is_Register()) return rc_int;
741 if (r->is_FloatRegister()) {
742 assert(UseSSE < 2, "shouldn't be used in SSE2+ mode");
743 return rc_float;
744 }
745 assert(r->is_XMMRegister(), "must be");
746 return rc_xmm;
747 }
748
749 static int impl_helper( CodeBuffer *cbuf, bool do_size, bool is_load, int offset, int reg,
750 int opcode, const char *op_str, int size, outputStream* st ) {
751 if( cbuf ) {
752 emit_opcode (*cbuf, opcode );
753 encode_RegMem(*cbuf, Matcher::_regEncode[reg], ESP_enc, 0x4, 0, offset, false);
754 #ifndef PRODUCT
755 } else if( !do_size ) {
756 if( size != 0 ) st->print("\n\t");
757 if( opcode == 0x8B || opcode == 0x89 ) { // MOV
758 if( is_load ) st->print("%s %s,[ESP + #%d]",op_str,Matcher::regName[reg],offset);
759 else st->print("%s [ESP + #%d],%s",op_str,offset,Matcher::regName[reg]);
760 } else { // FLD, FST, PUSH, POP
761 st->print("%s [ESP + #%d]",op_str,offset);
762 }
763 #endif
764 }
765 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
766 return size+3+offset_size;
767 }
768
769 // Helper for XMM registers. Extra opcode bits, limited syntax.
770 static int impl_x_helper( CodeBuffer *cbuf, bool do_size, bool is_load,
771 int offset, int reg_lo, int reg_hi, int size, outputStream* st ) {
772 if( cbuf ) {
773 if( reg_lo+1 == reg_hi ) { // double move?
774 if( is_load && !UseXmmLoadAndClearUpper )
775 emit_opcode(*cbuf, 0x66 ); // use 'movlpd' for load
776 else
777 emit_opcode(*cbuf, 0xF2 ); // use 'movsd' otherwise
778 } else {
779 emit_opcode(*cbuf, 0xF3 );
780 }
781 emit_opcode(*cbuf, 0x0F );
782 if( reg_lo+1 == reg_hi && is_load && !UseXmmLoadAndClearUpper )
783 emit_opcode(*cbuf, 0x12 ); // use 'movlpd' for load
784 else
785 emit_opcode(*cbuf, is_load ? 0x10 : 0x11 );
786 encode_RegMem(*cbuf, Matcher::_regEncode[reg_lo], ESP_enc, 0x4, 0, offset, false);
787 #ifndef PRODUCT
788 } else if( !do_size ) {
789 if( size != 0 ) st->print("\n\t");
790 if( reg_lo+1 == reg_hi ) { // double move?
791 if( is_load ) st->print("%s %s,[ESP + #%d]",
792 UseXmmLoadAndClearUpper ? "MOVSD " : "MOVLPD",
793 Matcher::regName[reg_lo], offset);
794 else st->print("MOVSD [ESP + #%d],%s",
795 offset, Matcher::regName[reg_lo]);
796 } else {
797 if( is_load ) st->print("MOVSS %s,[ESP + #%d]",
798 Matcher::regName[reg_lo], offset);
799 else st->print("MOVSS [ESP + #%d],%s",
800 offset, Matcher::regName[reg_lo]);
801 }
802 #endif
803 }
804 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
805 return size+5+offset_size;
806 }
807
808
809 static int impl_movx_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
810 int src_hi, int dst_hi, int size, outputStream* st ) {
811 if( UseXmmRegToRegMoveAll ) {//Use movaps,movapd to move between xmm registers
812 if( cbuf ) {
813 if( (src_lo+1 == src_hi && dst_lo+1 == dst_hi) ) {
814 emit_opcode(*cbuf, 0x66 );
815 }
816 emit_opcode(*cbuf, 0x0F );
817 emit_opcode(*cbuf, 0x28 );
818 emit_rm (*cbuf, 0x3, Matcher::_regEncode[dst_lo], Matcher::_regEncode[src_lo] );
819 #ifndef PRODUCT
820 } else if( !do_size ) {
821 if( size != 0 ) st->print("\n\t");
822 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double move?
823 st->print("MOVAPD %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
824 } else {
825 st->print("MOVAPS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
826 }
827 #endif
828 }
829 return size + ((src_lo+1 == src_hi && dst_lo+1 == dst_hi) ? 4 : 3);
830 } else {
831 if( cbuf ) {
832 emit_opcode(*cbuf, (src_lo+1 == src_hi && dst_lo+1 == dst_hi) ? 0xF2 : 0xF3 );
833 emit_opcode(*cbuf, 0x0F );
834 emit_opcode(*cbuf, 0x10 );
835 emit_rm (*cbuf, 0x3, Matcher::_regEncode[dst_lo], Matcher::_regEncode[src_lo] );
836 #ifndef PRODUCT
837 } else if( !do_size ) {
838 if( size != 0 ) st->print("\n\t");
839 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double move?
840 st->print("MOVSD %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
841 } else {
842 st->print("MOVSS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
843 }
844 #endif
845 }
846 return size+4;
847 }
848 }
849
850 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int size, outputStream* st ) {
851 if( cbuf ) {
852 emit_opcode(*cbuf, 0x8B );
853 emit_rm (*cbuf, 0x3, Matcher::_regEncode[dst], Matcher::_regEncode[src] );
854 #ifndef PRODUCT
855 } else if( !do_size ) {
856 if( size != 0 ) st->print("\n\t");
857 st->print("MOV %s,%s",Matcher::regName[dst],Matcher::regName[src]);
858 #endif
859 }
860 return size+2;
861 }
862
863 static int impl_fp_store_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int src_hi, int dst_lo, int dst_hi,
864 int offset, int size, outputStream* st ) {
865 if( src_lo != FPR1L_num ) { // Move value to top of FP stack, if not already there
866 if( cbuf ) {
867 emit_opcode( *cbuf, 0xD9 ); // FLD (i.e., push it)
868 emit_d8( *cbuf, 0xC0-1+Matcher::_regEncode[src_lo] );
869 #ifndef PRODUCT
870 } else if( !do_size ) {
871 if( size != 0 ) st->print("\n\t");
872 st->print("FLD %s",Matcher::regName[src_lo]);
873 #endif
874 }
875 size += 2;
876 }
877
878 int st_op = (src_lo != FPR1L_num) ? EBX_num /*store & pop*/ : EDX_num /*store no pop*/;
879 const char *op_str;
880 int op;
881 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double store?
882 op_str = (src_lo != FPR1L_num) ? "FSTP_D" : "FST_D ";
883 op = 0xDD;
884 } else { // 32-bit store
885 op_str = (src_lo != FPR1L_num) ? "FSTP_S" : "FST_S ";
886 op = 0xD9;
887 assert( !OptoReg::is_valid(src_hi) && !OptoReg::is_valid(dst_hi), "no non-adjacent float-stores" );
888 }
889
890 return impl_helper(cbuf,do_size,false,offset,st_op,op,op_str,size, st);
891 }
892
893 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream* st ) const {
894 // Get registers to move
895 OptoReg::Name src_second = ra_->get_reg_second(in(1));
896 OptoReg::Name src_first = ra_->get_reg_first(in(1));
897 OptoReg::Name dst_second = ra_->get_reg_second(this );
898 OptoReg::Name dst_first = ra_->get_reg_first(this );
899
900 enum RC src_second_rc = rc_class(src_second);
901 enum RC src_first_rc = rc_class(src_first);
902 enum RC dst_second_rc = rc_class(dst_second);
903 enum RC dst_first_rc = rc_class(dst_first);
904
905 assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" );
906
907 // Generate spill code!
908 int size = 0;
909
910 if( src_first == dst_first && src_second == dst_second )
911 return size; // Self copy, no move
912
913 // --------------------------------------
914 // Check for mem-mem move. push/pop to move.
915 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
916 if( src_second == dst_first ) { // overlapping stack copy ranges
917 assert( src_second_rc == rc_stack && dst_second_rc == rc_stack, "we only expect a stk-stk copy here" );
918 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH ",size, st);
919 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP ",size, st);
920 src_second_rc = dst_second_rc = rc_bad; // flag as already moved the second bits
921 }
922 // move low bits
923 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),ESI_num,0xFF,"PUSH ",size, st);
924 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),EAX_num,0x8F,"POP ",size, st);
925 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) { // mov second bits
926 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH ",size, st);
927 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP ",size, st);
928 }
929 return size;
930 }
931
932 // --------------------------------------
933 // Check for integer reg-reg copy
934 if( src_first_rc == rc_int && dst_first_rc == rc_int )
935 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,size, st);
936
937 // Check for integer store
938 if( src_first_rc == rc_int && dst_first_rc == rc_stack )
939 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first,0x89,"MOV ",size, st);
940
941 // Check for integer load
942 if( dst_first_rc == rc_int && src_first_rc == rc_stack )
943 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first,0x8B,"MOV ",size, st);
944
945 // --------------------------------------
946 // Check for float reg-reg copy
947 if( src_first_rc == rc_float && dst_first_rc == rc_float ) {
948 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) ||
949 (src_first+1 == src_second && dst_first+1 == dst_second), "no non-adjacent float-moves" );
950 if( cbuf ) {
951
952 // Note the mucking with the register encode to compensate for the 0/1
953 // indexing issue mentioned in a comment in the reg_def sections
954 // for FPR registers many lines above here.
955
956 if( src_first != FPR1L_num ) {
957 emit_opcode (*cbuf, 0xD9 ); // FLD ST(i)
958 emit_d8 (*cbuf, 0xC0+Matcher::_regEncode[src_first]-1 );
959 emit_opcode (*cbuf, 0xDD ); // FSTP ST(i)
960 emit_d8 (*cbuf, 0xD8+Matcher::_regEncode[dst_first] );
961 } else {
962 emit_opcode (*cbuf, 0xDD ); // FST ST(i)
963 emit_d8 (*cbuf, 0xD0+Matcher::_regEncode[dst_first]-1 );
964 }
965 #ifndef PRODUCT
966 } else if( !do_size ) {
967 if( size != 0 ) st->print("\n\t");
968 if( src_first != FPR1L_num ) st->print("FLD %s\n\tFSTP %s",Matcher::regName[src_first],Matcher::regName[dst_first]);
969 else st->print( "FST %s", Matcher::regName[dst_first]);
970 #endif
971 }
972 return size + ((src_first != FPR1L_num) ? 2+2 : 2);
973 }
974
975 // Check for float store
976 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) {
977 return impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,ra_->reg2offset(dst_first),size, st);
978 }
979
980 // Check for float load
981 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) {
982 int offset = ra_->reg2offset(src_first);
983 const char *op_str;
984 int op;
985 if( src_first+1 == src_second && dst_first+1 == dst_second ) { // double load?
986 op_str = "FLD_D";
987 op = 0xDD;
988 } else { // 32-bit load
989 op_str = "FLD_S";
990 op = 0xD9;
991 assert( src_second_rc == rc_bad && dst_second_rc == rc_bad, "no non-adjacent float-loads" );
992 }
993 if( cbuf ) {
994 emit_opcode (*cbuf, op );
995 encode_RegMem(*cbuf, 0x0, ESP_enc, 0x4, 0, offset, false);
996 emit_opcode (*cbuf, 0xDD ); // FSTP ST(i)
997 emit_d8 (*cbuf, 0xD8+Matcher::_regEncode[dst_first] );
998 #ifndef PRODUCT
999 } else if( !do_size ) {
1000 if( size != 0 ) st->print("\n\t");
1001 st->print("%s ST,[ESP + #%d]\n\tFSTP %s",op_str, offset,Matcher::regName[dst_first]);
1002 #endif
1003 }
1004 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
1005 return size + 3+offset_size+2;
1006 }
1007
1008 // Check for xmm reg-reg copy
1009 if( src_first_rc == rc_xmm && dst_first_rc == rc_xmm ) {
1010 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) ||
1011 (src_first+1 == src_second && dst_first+1 == dst_second),
1012 "no non-adjacent float-moves" );
1013 return impl_movx_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st);
1014 }
1015
1016 // Check for xmm store
1017 if( src_first_rc == rc_xmm && dst_first_rc == rc_stack ) {
1018 return impl_x_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first, src_second, size, st);
1019 }
1020
1021 // Check for float xmm load
1022 if( dst_first_rc == rc_xmm && src_first_rc == rc_stack ) {
1023 return impl_x_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first, dst_second, size, st);
1024 }
1025
1026 // Copy from float reg to xmm reg
1027 if( dst_first_rc == rc_xmm && src_first_rc == rc_float ) {
1028 // copy to the top of stack from floating point reg
1029 // and use LEA to preserve flags
1030 if( cbuf ) {
1031 emit_opcode(*cbuf,0x8D); // LEA ESP,[ESP-8]
1032 emit_rm(*cbuf, 0x1, ESP_enc, 0x04);
1033 emit_rm(*cbuf, 0x0, 0x04, ESP_enc);
1034 emit_d8(*cbuf,0xF8);
1035 #ifndef PRODUCT
1036 } else if( !do_size ) {
1037 if( size != 0 ) st->print("\n\t");
1038 st->print("LEA ESP,[ESP-8]");
1039 #endif
1040 }
1041 size += 4;
1042
1043 size = impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,0,size, st);
1044
1045 // Copy from the temp memory to the xmm reg.
1046 size = impl_x_helper(cbuf,do_size,true ,0,dst_first, dst_second, size, st);
1047
1048 if( cbuf ) {
1049 emit_opcode(*cbuf,0x8D); // LEA ESP,[ESP+8]
1050 emit_rm(*cbuf, 0x1, ESP_enc, 0x04);
1051 emit_rm(*cbuf, 0x0, 0x04, ESP_enc);
1052 emit_d8(*cbuf,0x08);
1053 #ifndef PRODUCT
1054 } else if( !do_size ) {
1055 if( size != 0 ) st->print("\n\t");
1056 st->print("LEA ESP,[ESP+8]");
1057 #endif
1058 }
1059 size += 4;
1060 return size;
1061 }
1062
1063 assert( size > 0, "missed a case" );
1064
1065 // --------------------------------------------------------------------
1066 // Check for second bits still needing moving.
1067 if( src_second == dst_second )
1068 return size; // Self copy; no move
1069 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" );
1070
1071 // Check for second word int-int move
1072 if( src_second_rc == rc_int && dst_second_rc == rc_int )
1073 return impl_mov_helper(cbuf,do_size,src_second,dst_second,size, st);
1074
1075 // Check for second word integer store
1076 if( src_second_rc == rc_int && dst_second_rc == rc_stack )
1077 return impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),src_second,0x89,"MOV ",size, st);
1078
1079 // Check for second word integer load
1080 if( dst_second_rc == rc_int && src_second_rc == rc_stack )
1081 return impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),dst_second,0x8B,"MOV ",size, st);
1082
1083
1084 Unimplemented();
1085 }
1086
1087 #ifndef PRODUCT
1088 void MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1089 implementation( NULL, ra_, false, st );
1090 }
1091 #endif
1092
1093 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1094 implementation( &cbuf, ra_, false, NULL );
1095 }
1096
1097 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1098 return implementation( NULL, ra_, true, NULL );
1099 }
1100
1101 //=============================================================================
1102 #ifndef PRODUCT
1103 void MachNopNode::format( PhaseRegAlloc *, outputStream* st ) const {
1104 st->print("NOP \t# %d bytes pad for loops and calls", _count);
1105 }
1106 #endif
1107
1108 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc * ) const {
1109 MacroAssembler _masm(&cbuf);
1110 __ nop(_count);
1111 }
1112
1113 uint MachNopNode::size(PhaseRegAlloc *) const {
1114 return _count;
1115 }
1116
1117
1118 //=============================================================================
1119 #ifndef PRODUCT
1120 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1121 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1122 int reg = ra_->get_reg_first(this);
1123 st->print("LEA %s,[ESP + #%d]",Matcher::regName[reg],offset);
1124 }
1125 #endif
1126
1127 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1128 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1129 int reg = ra_->get_encode(this);
1130 if( offset >= 128 ) {
1131 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1132 emit_rm(cbuf, 0x2, reg, 0x04);
1133 emit_rm(cbuf, 0x0, 0x04, ESP_enc);
1134 emit_d32(cbuf, offset);
1135 }
1136 else {
1137 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1138 emit_rm(cbuf, 0x1, reg, 0x04);
1139 emit_rm(cbuf, 0x0, 0x04, ESP_enc);
1140 emit_d8(cbuf, offset);
1141 }
1142 }
1143
1144 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1145 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1146 if( offset >= 128 ) {
1147 return 7;
1148 }
1149 else {
1150 return 4;
1151 }
1152 }
1153
1154 //=============================================================================
1155
1156 // emit call stub, compiled java to interpreter
1157 void emit_java_to_interp(CodeBuffer &cbuf ) {
1158 // Stub is fixed up when the corresponding call is converted from calling
1159 // compiled code to calling interpreted code.
1160 // mov rbx,0
1161 // jmp -1
1162
1163 address mark = cbuf.inst_mark(); // get mark within main instrs section
1164
1165 // Note that the code buffer's inst_mark is always relative to insts.
1166 // That's why we must use the macroassembler to generate a stub.
1167 MacroAssembler _masm(&cbuf);
1168
1169 address base =
1170 __ start_a_stub(Compile::MAX_stubs_size);
1171 if (base == NULL) return; // CodeBuffer::expand failed
1172 // static stub relocation stores the instruction address of the call
1173 __ relocate(static_stub_Relocation::spec(mark), RELOC_IMM32);
1174 // static stub relocation also tags the methodOop in the code-stream.
1175 __ movoop(rbx, (jobject)NULL); // method is zapped till fixup time
1176 // This is recognized as unresolved by relocs/nativeInst/ic code
1177 __ jump(RuntimeAddress(__ pc()));
1178
1179 __ end_a_stub();
1180 // Update current stubs pointer and restore code_end.
1181 }
1182 // size of call stub, compiled java to interpretor
1183 uint size_java_to_interp() {
1184 return 10; // movl; jmp
1185 }
1186 // relocation entries for call stub, compiled java to interpretor
1187 uint reloc_java_to_interp() {
1188 return 4; // 3 in emit_java_to_interp + 1 in Java_Static_Call
1189 }
1190
1191 //=============================================================================
1192 #ifndef PRODUCT
1193 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1194 st->print_cr( "CMP EAX,[ECX+4]\t# Inline cache check");
1195 st->print_cr("\tJNE SharedRuntime::handle_ic_miss_stub");
1196 st->print_cr("\tNOP");
1197 st->print_cr("\tNOP");
1198 if( !OptoBreakpoint )
1199 st->print_cr("\tNOP");
1200 }
1201 #endif
1202
1203 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1204 MacroAssembler masm(&cbuf);
1205 #ifdef ASSERT
1206 uint code_size = cbuf.code_size();
1207 #endif
1208 masm.cmpptr(rax, Address(rcx, oopDesc::klass_offset_in_bytes()));
1209 masm.jump_cc(Assembler::notEqual,
1210 RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1211 /* WARNING these NOPs are critical so that verified entry point is properly
1212 aligned for patching by NativeJump::patch_verified_entry() */
1213 int nops_cnt = 2;
1214 if( !OptoBreakpoint ) // Leave space for int3
1215 nops_cnt += 1;
1216 masm.nop(nops_cnt);
1217
1218 assert(cbuf.code_size() - code_size == size(ra_), "checking code size of inline cache node");
1219 }
1220
1221 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
1222 return OptoBreakpoint ? 11 : 12;
1223 }
1224
1225
1226 //=============================================================================
1227 uint size_exception_handler() {
1228 // NativeCall instruction size is the same as NativeJump.
1229 // exception handler starts out as jump and can be patched to
1230 // a call be deoptimization. (4932387)
1231 // Note that this value is also credited (in output.cpp) to
1232 // the size of the code section.
1233 return NativeJump::instruction_size;
1234 }
1235
1236 // Emit exception handler code. Stuff framesize into a register
1237 // and call a VM stub routine.
1238 int emit_exception_handler(CodeBuffer& cbuf) {
1239
1240 // Note that the code buffer's inst_mark is always relative to insts.
1241 // That's why we must use the macroassembler to generate a handler.
1242 MacroAssembler _masm(&cbuf);
1243 address base =
1244 __ start_a_stub(size_exception_handler());
1245 if (base == NULL) return 0; // CodeBuffer::expand failed
1246 int offset = __ offset();
1247 __ jump(RuntimeAddress(OptoRuntime::exception_blob()->instructions_begin()));
1248 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
1249 __ end_a_stub();
1250 return offset;
1251 }
1252
1253 uint size_deopt_handler() {
1254 // NativeCall instruction size is the same as NativeJump.
1255 // exception handler starts out as jump and can be patched to
1256 // a call be deoptimization. (4932387)
1257 // Note that this value is also credited (in output.cpp) to
1258 // the size of the code section.
1259 return 5 + NativeJump::instruction_size; // pushl(); jmp;
1260 }
1261
1262 // Emit deopt handler code.
1263 int emit_deopt_handler(CodeBuffer& cbuf) {
1264
1265 // Note that the code buffer's inst_mark is always relative to insts.
1266 // That's why we must use the macroassembler to generate a handler.
1267 MacroAssembler _masm(&cbuf);
1268 address base =
1269 __ start_a_stub(size_exception_handler());
1270 if (base == NULL) return 0; // CodeBuffer::expand failed
1271 int offset = __ offset();
1272 InternalAddress here(__ pc());
1273 __ pushptr(here.addr());
1274
1275 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
1276 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
1277 __ end_a_stub();
1278 return offset;
1279 }
1280
1281
1282 static void emit_double_constant(CodeBuffer& cbuf, double x) {
1283 int mark = cbuf.insts()->mark_off();
1284 MacroAssembler _masm(&cbuf);
1285 address double_address = __ double_constant(x);
1286 cbuf.insts()->set_mark_off(mark); // preserve mark across masm shift
1287 emit_d32_reloc(cbuf,
1288 (int)double_address,
1289 internal_word_Relocation::spec(double_address),
1290 RELOC_DISP32);
1291 }
1292
1293 static void emit_float_constant(CodeBuffer& cbuf, float x) {
1294 int mark = cbuf.insts()->mark_off();
1295 MacroAssembler _masm(&cbuf);
1296 address float_address = __ float_constant(x);
1297 cbuf.insts()->set_mark_off(mark); // preserve mark across masm shift
1298 emit_d32_reloc(cbuf,
1299 (int)float_address,
1300 internal_word_Relocation::spec(float_address),
1301 RELOC_DISP32);
1302 }
1303
1304
1305 const bool Matcher::match_rule_supported(int opcode) {
1306 if (!has_match_rule(opcode))
1307 return false;
1308
1309 return true; // Per default match rules are supported.
1310 }
1311
1312 int Matcher::regnum_to_fpu_offset(int regnum) {
1313 return regnum - 32; // The FP registers are in the second chunk
1314 }
1315
1316 bool is_positive_zero_float(jfloat f) {
1317 return jint_cast(f) == jint_cast(0.0F);
1318 }
1319
1320 bool is_positive_one_float(jfloat f) {
1321 return jint_cast(f) == jint_cast(1.0F);
1322 }
1323
1324 bool is_positive_zero_double(jdouble d) {
1325 return jlong_cast(d) == jlong_cast(0.0);
1326 }
1327
1328 bool is_positive_one_double(jdouble d) {
1329 return jlong_cast(d) == jlong_cast(1.0);
1330 }
1331
1332 // This is UltraSparc specific, true just means we have fast l2f conversion
1333 const bool Matcher::convL2FSupported(void) {
1334 return true;
1335 }
1336
1337 // Vector width in bytes
1338 const uint Matcher::vector_width_in_bytes(void) {
1339 return UseSSE >= 2 ? 8 : 0;
1340 }
1341
1342 // Vector ideal reg
1343 const uint Matcher::vector_ideal_reg(void) {
1344 return Op_RegD;
1345 }
1346
1347 // Is this branch offset short enough that a short branch can be used?
1348 //
1349 // NOTE: If the platform does not provide any short branch variants, then
1350 // this method should return false for offset 0.
1351 bool Matcher::is_short_branch_offset(int rule, int offset) {
1352 // the short version of jmpConUCF2 contains multiple branches,
1353 // making the reach slightly less
1354 if (rule == jmpConUCF2_rule)
1355 return (-126 <= offset && offset <= 125);
1356 return (-128 <= offset && offset <= 127);
1357 }
1358
1359 const bool Matcher::isSimpleConstant64(jlong value) {
1360 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1361 return false;
1362 }
1363
1364 // The ecx parameter to rep stos for the ClearArray node is in dwords.
1365 const bool Matcher::init_array_count_is_in_bytes = false;
1366
1367 // Threshold size for cleararray.
1368 const int Matcher::init_array_short_size = 8 * BytesPerLong;
1369
1370 // Should the Matcher clone shifts on addressing modes, expecting them to
1371 // be subsumed into complex addressing expressions or compute them into
1372 // registers? True for Intel but false for most RISCs
1373 const bool Matcher::clone_shift_expressions = true;
1374
1375 // Is it better to copy float constants, or load them directly from memory?
1376 // Intel can load a float constant from a direct address, requiring no
1377 // extra registers. Most RISCs will have to materialize an address into a
1378 // register first, so they would do better to copy the constant from stack.
1379 const bool Matcher::rematerialize_float_constants = true;
1380
1381 // If CPU can load and store mis-aligned doubles directly then no fixup is
1382 // needed. Else we split the double into 2 integer pieces and move it
1383 // piece-by-piece. Only happens when passing doubles into C code as the
1384 // Java calling convention forces doubles to be aligned.
1385 const bool Matcher::misaligned_doubles_ok = true;
1386
1387
1388 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
1389 // Get the memory operand from the node
1390 uint numopnds = node->num_opnds(); // Virtual call for number of operands
1391 uint skipped = node->oper_input_base(); // Sum of leaves skipped so far
1392 assert( idx >= skipped, "idx too low in pd_implicit_null_fixup" );
1393 uint opcnt = 1; // First operand
1394 uint num_edges = node->_opnds[1]->num_edges(); // leaves for first operand
1395 while( idx >= skipped+num_edges ) {
1396 skipped += num_edges;
1397 opcnt++; // Bump operand count
1398 assert( opcnt < numopnds, "Accessing non-existent operand" );
1399 num_edges = node->_opnds[opcnt]->num_edges(); // leaves for next operand
1400 }
1401
1402 MachOper *memory = node->_opnds[opcnt];
1403 MachOper *new_memory = NULL;
1404 switch (memory->opcode()) {
1405 case DIRECT:
1406 case INDOFFSET32X:
1407 // No transformation necessary.
1408 return;
1409 case INDIRECT:
1410 new_memory = new (C) indirect_win95_safeOper( );
1411 break;
1412 case INDOFFSET8:
1413 new_memory = new (C) indOffset8_win95_safeOper(memory->disp(NULL, NULL, 0));
1414 break;
1415 case INDOFFSET32:
1416 new_memory = new (C) indOffset32_win95_safeOper(memory->disp(NULL, NULL, 0));
1417 break;
1418 case INDINDEXOFFSET:
1419 new_memory = new (C) indIndexOffset_win95_safeOper(memory->disp(NULL, NULL, 0));
1420 break;
1421 case INDINDEXSCALE:
1422 new_memory = new (C) indIndexScale_win95_safeOper(memory->scale());
1423 break;
1424 case INDINDEXSCALEOFFSET:
1425 new_memory = new (C) indIndexScaleOffset_win95_safeOper(memory->scale(), memory->disp(NULL, NULL, 0));
1426 break;
1427 case LOAD_LONG_INDIRECT:
1428 case LOAD_LONG_INDOFFSET32:
1429 // Does not use EBP as address register, use { EDX, EBX, EDI, ESI}
1430 return;
1431 default:
1432 assert(false, "unexpected memory operand in pd_implicit_null_fixup()");
1433 return;
1434 }
1435 node->_opnds[opcnt] = new_memory;
1436 }
1437
1438 // Advertise here if the CPU requires explicit rounding operations
1439 // to implement the UseStrictFP mode.
1440 const bool Matcher::strict_fp_requires_explicit_rounding = true;
1441
1442 // Do floats take an entire double register or just half?
1443 const bool Matcher::float_in_double = true;
1444 // Do ints take an entire long register or just half?
1445 const bool Matcher::int_in_long = false;
1446
1447 // Return whether or not this register is ever used as an argument. This
1448 // function is used on startup to build the trampoline stubs in generateOptoStub.
1449 // Registers not mentioned will be killed by the VM call in the trampoline, and
1450 // arguments in those registers not be available to the callee.
1451 bool Matcher::can_be_java_arg( int reg ) {
1452 if( reg == ECX_num || reg == EDX_num ) return true;
1453 if( (reg == XMM0a_num || reg == XMM1a_num) && UseSSE>=1 ) return true;
1454 if( (reg == XMM0b_num || reg == XMM1b_num) && UseSSE>=2 ) return true;
1455 return false;
1456 }
1457
1458 bool Matcher::is_spillable_arg( int reg ) {
1459 return can_be_java_arg(reg);
1460 }
1461
1462 // Register for DIVI projection of divmodI
1463 RegMask Matcher::divI_proj_mask() {
1464 return EAX_REG_mask;
1465 }
1466
1467 // Register for MODI projection of divmodI
1468 RegMask Matcher::modI_proj_mask() {
1469 return EDX_REG_mask;
1470 }
1471
1472 // Register for DIVL projection of divmodL
1473 RegMask Matcher::divL_proj_mask() {
1474 ShouldNotReachHere();
1475 return RegMask();
1476 }
1477
1478 // Register for MODL projection of divmodL
1479 RegMask Matcher::modL_proj_mask() {
1480 ShouldNotReachHere();
1481 return RegMask();
1482 }
1483
1484 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
1485 return EBP_REG_mask;
1486 }
1487
1488 %}
1489
1490 //----------ENCODING BLOCK-----------------------------------------------------
1491 // This block specifies the encoding classes used by the compiler to output
1492 // byte streams. Encoding classes generate functions which are called by
1493 // Machine Instruction Nodes in order to generate the bit encoding of the
1494 // instruction. Operands specify their base encoding interface with the
1495 // interface keyword. There are currently supported four interfaces,
1496 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
1497 // operand to generate a function which returns its register number when
1498 // queried. CONST_INTER causes an operand to generate a function which
1499 // returns the value of the constant when queried. MEMORY_INTER causes an
1500 // operand to generate four functions which return the Base Register, the
1501 // Index Register, the Scale Value, and the Offset Value of the operand when
1502 // queried. COND_INTER causes an operand to generate six functions which
1503 // return the encoding code (ie - encoding bits for the instruction)
1504 // associated with each basic boolean condition for a conditional instruction.
1505 // Instructions specify two basic values for encoding. They use the
1506 // ins_encode keyword to specify their encoding class (which must be one of
1507 // the class names specified in the encoding block), and they use the
1508 // opcode keyword to specify, in order, their primary, secondary, and
1509 // tertiary opcode. Only the opcode sections which a particular instruction
1510 // needs for encoding need to be specified.
1511 encode %{
1512 // Build emit functions for each basic byte or larger field in the intel
1513 // encoding scheme (opcode, rm, sib, immediate), and call them from C++
1514 // code in the enc_class source block. Emit functions will live in the
1515 // main source block for now. In future, we can generalize this by
1516 // adding a syntax that specifies the sizes of fields in an order,
1517 // so that the adlc can build the emit functions automagically
1518
1519 // Emit primary opcode
1520 enc_class OpcP %{
1521 emit_opcode(cbuf, $primary);
1522 %}
1523
1524 // Emit secondary opcode
1525 enc_class OpcS %{
1526 emit_opcode(cbuf, $secondary);
1527 %}
1528
1529 // Emit opcode directly
1530 enc_class Opcode(immI d8) %{
1531 emit_opcode(cbuf, $d8$$constant);
1532 %}
1533
1534 enc_class SizePrefix %{
1535 emit_opcode(cbuf,0x66);
1536 %}
1537
1538 enc_class RegReg (eRegI dst, eRegI src) %{ // RegReg(Many)
1539 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1540 %}
1541
1542 enc_class OpcRegReg (immI opcode, eRegI dst, eRegI src) %{ // OpcRegReg(Many)
1543 emit_opcode(cbuf,$opcode$$constant);
1544 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1545 %}
1546
1547 enc_class mov_r32_imm0( eRegI dst ) %{
1548 emit_opcode( cbuf, 0xB8 + $dst$$reg ); // 0xB8+ rd -- MOV r32 ,imm32
1549 emit_d32 ( cbuf, 0x0 ); // imm32==0x0
1550 %}
1551
1552 enc_class cdq_enc %{
1553 // Full implementation of Java idiv and irem; checks for
1554 // special case as described in JVM spec., p.243 & p.271.
1555 //
1556 // normal case special case
1557 //
1558 // input : rax,: dividend min_int
1559 // reg: divisor -1
1560 //
1561 // output: rax,: quotient (= rax, idiv reg) min_int
1562 // rdx: remainder (= rax, irem reg) 0
1563 //
1564 // Code sequnce:
1565 //
1566 // 81 F8 00 00 00 80 cmp rax,80000000h
1567 // 0F 85 0B 00 00 00 jne normal_case
1568 // 33 D2 xor rdx,edx
1569 // 83 F9 FF cmp rcx,0FFh
1570 // 0F 84 03 00 00 00 je done
1571 // normal_case:
1572 // 99 cdq
1573 // F7 F9 idiv rax,ecx
1574 // done:
1575 //
1576 emit_opcode(cbuf,0x81); emit_d8(cbuf,0xF8);
1577 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00);
1578 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x80); // cmp rax,80000000h
1579 emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x85);
1580 emit_opcode(cbuf,0x0B); emit_d8(cbuf,0x00);
1581 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); // jne normal_case
1582 emit_opcode(cbuf,0x33); emit_d8(cbuf,0xD2); // xor rdx,edx
1583 emit_opcode(cbuf,0x83); emit_d8(cbuf,0xF9); emit_d8(cbuf,0xFF); // cmp rcx,0FFh
1584 emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x84);
1585 emit_opcode(cbuf,0x03); emit_d8(cbuf,0x00);
1586 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); // je done
1587 // normal_case:
1588 emit_opcode(cbuf,0x99); // cdq
1589 // idiv (note: must be emitted by the user of this rule)
1590 // normal:
1591 %}
1592
1593 // Dense encoding for older common ops
1594 enc_class Opc_plus(immI opcode, eRegI reg) %{
1595 emit_opcode(cbuf, $opcode$$constant + $reg$$reg);
1596 %}
1597
1598
1599 // Opcde enc_class for 8/32 bit immediate instructions with sign-extension
1600 enc_class OpcSE (immI imm) %{ // Emit primary opcode and set sign-extend bit
1601 // Check for 8-bit immediate, and set sign extend bit in opcode
1602 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1603 emit_opcode(cbuf, $primary | 0x02);
1604 }
1605 else { // If 32-bit immediate
1606 emit_opcode(cbuf, $primary);
1607 }
1608 %}
1609
1610 enc_class OpcSErm (eRegI dst, immI imm) %{ // OpcSEr/m
1611 // Emit primary opcode and set sign-extend bit
1612 // Check for 8-bit immediate, and set sign extend bit in opcode
1613 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1614 emit_opcode(cbuf, $primary | 0x02); }
1615 else { // If 32-bit immediate
1616 emit_opcode(cbuf, $primary);
1617 }
1618 // Emit r/m byte with secondary opcode, after primary opcode.
1619 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1620 %}
1621
1622 enc_class Con8or32 (immI imm) %{ // Con8or32(storeImmI), 8 or 32 bits
1623 // Check for 8-bit immediate, and set sign extend bit in opcode
1624 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1625 $$$emit8$imm$$constant;
1626 }
1627 else { // If 32-bit immediate
1628 // Output immediate
1629 $$$emit32$imm$$constant;
1630 }
1631 %}
1632
1633 enc_class Long_OpcSErm_Lo(eRegL dst, immL imm) %{
1634 // Emit primary opcode and set sign-extend bit
1635 // Check for 8-bit immediate, and set sign extend bit in opcode
1636 int con = (int)$imm$$constant; // Throw away top bits
1637 emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary);
1638 // Emit r/m byte with secondary opcode, after primary opcode.
1639 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1640 if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con);
1641 else emit_d32(cbuf,con);
1642 %}
1643
1644 enc_class Long_OpcSErm_Hi(eRegL dst, immL imm) %{
1645 // Emit primary opcode and set sign-extend bit
1646 // Check for 8-bit immediate, and set sign extend bit in opcode
1647 int con = (int)($imm$$constant >> 32); // Throw away bottom bits
1648 emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary);
1649 // Emit r/m byte with tertiary opcode, after primary opcode.
1650 emit_rm(cbuf, 0x3, $tertiary, HIGH_FROM_LOW($dst$$reg));
1651 if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con);
1652 else emit_d32(cbuf,con);
1653 %}
1654
1655 enc_class Lbl (label labl) %{ // JMP, CALL
1656 Label *l = $labl$$label;
1657 emit_d32(cbuf, l ? (l->loc_pos() - (cbuf.code_size()+4)) : 0);
1658 %}
1659
1660 enc_class LblShort (label labl) %{ // JMP, CALL
1661 Label *l = $labl$$label;
1662 int disp = l ? (l->loc_pos() - (cbuf.code_size()+1)) : 0;
1663 assert(-128 <= disp && disp <= 127, "Displacement too large for short jmp");
1664 emit_d8(cbuf, disp);
1665 %}
1666
1667 enc_class OpcSReg (eRegI dst) %{ // BSWAP
1668 emit_cc(cbuf, $secondary, $dst$$reg );
1669 %}
1670
1671 enc_class bswap_long_bytes(eRegL dst) %{ // BSWAP
1672 int destlo = $dst$$reg;
1673 int desthi = HIGH_FROM_LOW(destlo);
1674 // bswap lo
1675 emit_opcode(cbuf, 0x0F);
1676 emit_cc(cbuf, 0xC8, destlo);
1677 // bswap hi
1678 emit_opcode(cbuf, 0x0F);
1679 emit_cc(cbuf, 0xC8, desthi);
1680 // xchg lo and hi
1681 emit_opcode(cbuf, 0x87);
1682 emit_rm(cbuf, 0x3, destlo, desthi);
1683 %}
1684
1685 enc_class RegOpc (eRegI div) %{ // IDIV, IMOD, JMP indirect, ...
1686 emit_rm(cbuf, 0x3, $secondary, $div$$reg );
1687 %}
1688
1689 enc_class Jcc (cmpOp cop, label labl) %{ // JCC
1690 Label *l = $labl$$label;
1691 $$$emit8$primary;
1692 emit_cc(cbuf, $secondary, $cop$$cmpcode);
1693 emit_d32(cbuf, l ? (l->loc_pos() - (cbuf.code_size()+4)) : 0);
1694 %}
1695
1696 enc_class JccShort (cmpOp cop, label labl) %{ // JCC
1697 Label *l = $labl$$label;
1698 emit_cc(cbuf, $primary, $cop$$cmpcode);
1699 int disp = l ? (l->loc_pos() - (cbuf.code_size()+1)) : 0;
1700 assert(-128 <= disp && disp <= 127, "Displacement too large for short jmp");
1701 emit_d8(cbuf, disp);
1702 %}
1703
1704 enc_class enc_cmov(cmpOp cop ) %{ // CMOV
1705 $$$emit8$primary;
1706 emit_cc(cbuf, $secondary, $cop$$cmpcode);
1707 %}
1708
1709 enc_class enc_cmov_d(cmpOp cop, regD src ) %{ // CMOV
1710 int op = 0xDA00 + $cop$$cmpcode + ($src$$reg-1);
1711 emit_d8(cbuf, op >> 8 );
1712 emit_d8(cbuf, op & 255);
1713 %}
1714
1715 // emulate a CMOV with a conditional branch around a MOV
1716 enc_class enc_cmov_branch( cmpOp cop, immI brOffs ) %{ // CMOV
1717 // Invert sense of branch from sense of CMOV
1718 emit_cc( cbuf, 0x70, ($cop$$cmpcode^1) );
1719 emit_d8( cbuf, $brOffs$$constant );
1720 %}
1721
1722 enc_class enc_PartialSubtypeCheck( ) %{
1723 Register Redi = as_Register(EDI_enc); // result register
1724 Register Reax = as_Register(EAX_enc); // super class
1725 Register Recx = as_Register(ECX_enc); // killed
1726 Register Resi = as_Register(ESI_enc); // sub class
1727 Label miss;
1728
1729 MacroAssembler _masm(&cbuf);
1730 __ check_klass_subtype_slow_path(Resi, Reax, Recx, Redi,
1731 NULL, &miss,
1732 /*set_cond_codes:*/ true);
1733 if ($primary) {
1734 __ xorptr(Redi, Redi);
1735 }
1736 __ bind(miss);
1737 %}
1738
1739 enc_class FFree_Float_Stack_All %{ // Free_Float_Stack_All
1740 MacroAssembler masm(&cbuf);
1741 int start = masm.offset();
1742 if (UseSSE >= 2) {
1743 if (VerifyFPU) {
1744 masm.verify_FPU(0, "must be empty in SSE2+ mode");
1745 }
1746 } else {
1747 // External c_calling_convention expects the FPU stack to be 'clean'.
1748 // Compiled code leaves it dirty. Do cleanup now.
1749 masm.empty_FPU_stack();
1750 }
1751 if (sizeof_FFree_Float_Stack_All == -1) {
1752 sizeof_FFree_Float_Stack_All = masm.offset() - start;
1753 } else {
1754 assert(masm.offset() - start == sizeof_FFree_Float_Stack_All, "wrong size");
1755 }
1756 %}
1757
1758 enc_class Verify_FPU_For_Leaf %{
1759 if( VerifyFPU ) {
1760 MacroAssembler masm(&cbuf);
1761 masm.verify_FPU( -3, "Returning from Runtime Leaf call");
1762 }
1763 %}
1764
1765 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime, Java_To_Runtime_Leaf
1766 // This is the instruction starting address for relocation info.
1767 cbuf.set_inst_mark();
1768 $$$emit8$primary;
1769 // CALL directly to the runtime
1770 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.code_end()) - 4),
1771 runtime_call_Relocation::spec(), RELOC_IMM32 );
1772
1773 if (UseSSE >= 2) {
1774 MacroAssembler _masm(&cbuf);
1775 BasicType rt = tf()->return_type();
1776
1777 if ((rt == T_FLOAT || rt == T_DOUBLE) && !return_value_is_used()) {
1778 // A C runtime call where the return value is unused. In SSE2+
1779 // mode the result needs to be removed from the FPU stack. It's
1780 // likely that this function call could be removed by the
1781 // optimizer if the C function is a pure function.
1782 __ ffree(0);
1783 } else if (rt == T_FLOAT) {
1784 __ lea(rsp, Address(rsp, -4));
1785 __ fstp_s(Address(rsp, 0));
1786 __ movflt(xmm0, Address(rsp, 0));
1787 __ lea(rsp, Address(rsp, 4));
1788 } else if (rt == T_DOUBLE) {
1789 __ lea(rsp, Address(rsp, -8));
1790 __ fstp_d(Address(rsp, 0));
1791 __ movdbl(xmm0, Address(rsp, 0));
1792 __ lea(rsp, Address(rsp, 8));
1793 }
1794 }
1795 %}
1796
1797
1798 enc_class pre_call_FPU %{
1799 // If method sets FPU control word restore it here
1800 debug_only(int off0 = cbuf.code_size());
1801 if( Compile::current()->in_24_bit_fp_mode() ) {
1802 MacroAssembler masm(&cbuf);
1803 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
1804 }
1805 debug_only(int off1 = cbuf.code_size());
1806 assert(off1 - off0 == pre_call_FPU_size(), "correct size prediction");
1807 %}
1808
1809 enc_class post_call_FPU %{
1810 // If method sets FPU control word do it here also
1811 if( Compile::current()->in_24_bit_fp_mode() ) {
1812 MacroAssembler masm(&cbuf);
1813 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
1814 }
1815 %}
1816
1817 enc_class preserve_SP %{
1818 debug_only(int off0 = cbuf.code_size());
1819 MacroAssembler _masm(&cbuf);
1820 // RBP is preserved across all calls, even compiled calls.
1821 // Use it to preserve RSP in places where the callee might change the SP.
1822 __ movptr(rbp, rsp);
1823 debug_only(int off1 = cbuf.code_size());
1824 assert(off1 - off0 == preserve_SP_size(), "correct size prediction");
1825 %}
1826
1827 enc_class restore_SP %{
1828 MacroAssembler _masm(&cbuf);
1829 __ movptr(rsp, rbp);
1830 %}
1831
1832 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL
1833 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
1834 // who we intended to call.
1835 cbuf.set_inst_mark();
1836 $$$emit8$primary;
1837 if ( !_method ) {
1838 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.code_end()) - 4),
1839 runtime_call_Relocation::spec(), RELOC_IMM32 );
1840 } else if(_optimized_virtual) {
1841 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.code_end()) - 4),
1842 opt_virtual_call_Relocation::spec(), RELOC_IMM32 );
1843 } else {
1844 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.code_end()) - 4),
1845 static_call_Relocation::spec(), RELOC_IMM32 );
1846 }
1847 if( _method ) { // Emit stub for static call
1848 emit_java_to_interp(cbuf);
1849 }
1850 %}
1851
1852 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL
1853 // !!!!!
1854 // Generate "Mov EAX,0x00", placeholder instruction to load oop-info
1855 // emit_call_dynamic_prologue( cbuf );
1856 cbuf.set_inst_mark();
1857 emit_opcode(cbuf, 0xB8 + EAX_enc); // mov EAX,-1
1858 emit_d32_reloc(cbuf, (int)Universe::non_oop_word(), oop_Relocation::spec_for_immediate(), RELOC_IMM32);
1859 address virtual_call_oop_addr = cbuf.inst_mark();
1860 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
1861 // who we intended to call.
1862 cbuf.set_inst_mark();
1863 $$$emit8$primary;
1864 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.code_end()) - 4),
1865 virtual_call_Relocation::spec(virtual_call_oop_addr), RELOC_IMM32 );
1866 %}
1867
1868 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL
1869 int disp = in_bytes(methodOopDesc::from_compiled_offset());
1870 assert( -128 <= disp && disp <= 127, "compiled_code_offset isn't small");
1871
1872 // CALL *[EAX+in_bytes(methodOopDesc::from_compiled_code_entry_point_offset())]
1873 cbuf.set_inst_mark();
1874 $$$emit8$primary;
1875 emit_rm(cbuf, 0x01, $secondary, EAX_enc ); // R/M byte
1876 emit_d8(cbuf, disp); // Displacement
1877
1878 %}
1879
1880 enc_class Xor_Reg (eRegI dst) %{
1881 emit_opcode(cbuf, 0x33);
1882 emit_rm(cbuf, 0x3, $dst$$reg, $dst$$reg);
1883 %}
1884
1885 // Following encoding is no longer used, but may be restored if calling
1886 // convention changes significantly.
1887 // Became: Xor_Reg(EBP), Java_To_Runtime( labl )
1888 //
1889 // enc_class Java_Interpreter_Call (label labl) %{ // JAVA INTERPRETER CALL
1890 // // int ic_reg = Matcher::inline_cache_reg();
1891 // // int ic_encode = Matcher::_regEncode[ic_reg];
1892 // // int imo_reg = Matcher::interpreter_method_oop_reg();
1893 // // int imo_encode = Matcher::_regEncode[imo_reg];
1894 //
1895 // // // Interpreter expects method_oop in EBX, currently a callee-saved register,
1896 // // // so we load it immediately before the call
1897 // // emit_opcode(cbuf, 0x8B); // MOV imo_reg,ic_reg # method_oop
1898 // // emit_rm(cbuf, 0x03, imo_encode, ic_encode ); // R/M byte
1899 //
1900 // // xor rbp,ebp
1901 // emit_opcode(cbuf, 0x33);
1902 // emit_rm(cbuf, 0x3, EBP_enc, EBP_enc);
1903 //
1904 // // CALL to interpreter.
1905 // cbuf.set_inst_mark();
1906 // $$$emit8$primary;
1907 // emit_d32_reloc(cbuf, ($labl$$label - (int)(cbuf.code_end()) - 4),
1908 // runtime_call_Relocation::spec(), RELOC_IMM32 );
1909 // %}
1910
1911 enc_class RegOpcImm (eRegI dst, immI8 shift) %{ // SHL, SAR, SHR
1912 $$$emit8$primary;
1913 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1914 $$$emit8$shift$$constant;
1915 %}
1916
1917 enc_class LdImmI (eRegI dst, immI src) %{ // Load Immediate
1918 // Load immediate does not have a zero or sign extended version
1919 // for 8-bit immediates
1920 emit_opcode(cbuf, 0xB8 + $dst$$reg);
1921 $$$emit32$src$$constant;
1922 %}
1923
1924 enc_class LdImmP (eRegI dst, immI src) %{ // Load Immediate
1925 // Load immediate does not have a zero or sign extended version
1926 // for 8-bit immediates
1927 emit_opcode(cbuf, $primary + $dst$$reg);
1928 $$$emit32$src$$constant;
1929 %}
1930
1931 enc_class LdImmL_Lo( eRegL dst, immL src) %{ // Load Immediate
1932 // Load immediate does not have a zero or sign extended version
1933 // for 8-bit immediates
1934 int dst_enc = $dst$$reg;
1935 int src_con = $src$$constant & 0x0FFFFFFFFL;
1936 if (src_con == 0) {
1937 // xor dst, dst
1938 emit_opcode(cbuf, 0x33);
1939 emit_rm(cbuf, 0x3, dst_enc, dst_enc);
1940 } else {
1941 emit_opcode(cbuf, $primary + dst_enc);
1942 emit_d32(cbuf, src_con);
1943 }
1944 %}
1945
1946 enc_class LdImmL_Hi( eRegL dst, immL src) %{ // Load Immediate
1947 // Load immediate does not have a zero or sign extended version
1948 // for 8-bit immediates
1949 int dst_enc = $dst$$reg + 2;
1950 int src_con = ((julong)($src$$constant)) >> 32;
1951 if (src_con == 0) {
1952 // xor dst, dst
1953 emit_opcode(cbuf, 0x33);
1954 emit_rm(cbuf, 0x3, dst_enc, dst_enc);
1955 } else {
1956 emit_opcode(cbuf, $primary + dst_enc);
1957 emit_d32(cbuf, src_con);
1958 }
1959 %}
1960
1961
1962 enc_class LdImmD (immD src) %{ // Load Immediate
1963 if( is_positive_zero_double($src$$constant)) {
1964 // FLDZ
1965 emit_opcode(cbuf,0xD9);
1966 emit_opcode(cbuf,0xEE);
1967 } else if( is_positive_one_double($src$$constant)) {
1968 // FLD1
1969 emit_opcode(cbuf,0xD9);
1970 emit_opcode(cbuf,0xE8);
1971 } else {
1972 emit_opcode(cbuf,0xDD);
1973 emit_rm(cbuf, 0x0, 0x0, 0x5);
1974 emit_double_constant(cbuf, $src$$constant);
1975 }
1976 %}
1977
1978
1979 enc_class LdImmF (immF src) %{ // Load Immediate
1980 if( is_positive_zero_float($src$$constant)) {
1981 emit_opcode(cbuf,0xD9);
1982 emit_opcode(cbuf,0xEE);
1983 } else if( is_positive_one_float($src$$constant)) {
1984 emit_opcode(cbuf,0xD9);
1985 emit_opcode(cbuf,0xE8);
1986 } else {
1987 $$$emit8$primary;
1988 // Load immediate does not have a zero or sign extended version
1989 // for 8-bit immediates
1990 // First load to TOS, then move to dst
1991 emit_rm(cbuf, 0x0, 0x0, 0x5);
1992 emit_float_constant(cbuf, $src$$constant);
1993 }
1994 %}
1995
1996 enc_class LdImmX (regX dst, immXF con) %{ // Load Immediate
1997 emit_rm(cbuf, 0x0, $dst$$reg, 0x5);
1998 emit_float_constant(cbuf, $con$$constant);
1999 %}
2000
2001 enc_class LdImmXD (regXD dst, immXD con) %{ // Load Immediate
2002 emit_rm(cbuf, 0x0, $dst$$reg, 0x5);
2003 emit_double_constant(cbuf, $con$$constant);
2004 %}
2005
2006 enc_class load_conXD (regXD dst, immXD con) %{ // Load double constant
2007 // UseXmmLoadAndClearUpper ? movsd(dst, con) : movlpd(dst, con)
2008 emit_opcode(cbuf, UseXmmLoadAndClearUpper ? 0xF2 : 0x66);
2009 emit_opcode(cbuf, 0x0F);
2010 emit_opcode(cbuf, UseXmmLoadAndClearUpper ? 0x10 : 0x12);
2011 emit_rm(cbuf, 0x0, $dst$$reg, 0x5);
2012 emit_double_constant(cbuf, $con$$constant);
2013 %}
2014
2015 enc_class Opc_MemImm_F(immF src) %{
2016 cbuf.set_inst_mark();
2017 $$$emit8$primary;
2018 emit_rm(cbuf, 0x0, $secondary, 0x5);
2019 emit_float_constant(cbuf, $src$$constant);
2020 %}
2021
2022
2023 enc_class MovI2X_reg(regX dst, eRegI src) %{
2024 emit_opcode(cbuf, 0x66 ); // MOVD dst,src
2025 emit_opcode(cbuf, 0x0F );
2026 emit_opcode(cbuf, 0x6E );
2027 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2028 %}
2029
2030 enc_class MovX2I_reg(eRegI dst, regX src) %{
2031 emit_opcode(cbuf, 0x66 ); // MOVD dst,src
2032 emit_opcode(cbuf, 0x0F );
2033 emit_opcode(cbuf, 0x7E );
2034 emit_rm(cbuf, 0x3, $src$$reg, $dst$$reg);
2035 %}
2036
2037 enc_class MovL2XD_reg(regXD dst, eRegL src, regXD tmp) %{
2038 { // MOVD $dst,$src.lo
2039 emit_opcode(cbuf,0x66);
2040 emit_opcode(cbuf,0x0F);
2041 emit_opcode(cbuf,0x6E);
2042 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2043 }
2044 { // MOVD $tmp,$src.hi
2045 emit_opcode(cbuf,0x66);
2046 emit_opcode(cbuf,0x0F);
2047 emit_opcode(cbuf,0x6E);
2048 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg));
2049 }
2050 { // PUNPCKLDQ $dst,$tmp
2051 emit_opcode(cbuf,0x66);
2052 emit_opcode(cbuf,0x0F);
2053 emit_opcode(cbuf,0x62);
2054 emit_rm(cbuf, 0x3, $dst$$reg, $tmp$$reg);
2055 }
2056 %}
2057
2058 enc_class MovXD2L_reg(eRegL dst, regXD src, regXD tmp) %{
2059 { // MOVD $dst.lo,$src
2060 emit_opcode(cbuf,0x66);
2061 emit_opcode(cbuf,0x0F);
2062 emit_opcode(cbuf,0x7E);
2063 emit_rm(cbuf, 0x3, $src$$reg, $dst$$reg);
2064 }
2065 { // PSHUFLW $tmp,$src,0x4E (01001110b)
2066 emit_opcode(cbuf,0xF2);
2067 emit_opcode(cbuf,0x0F);
2068 emit_opcode(cbuf,0x70);
2069 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg);
2070 emit_d8(cbuf, 0x4E);
2071 }
2072 { // MOVD $dst.hi,$tmp
2073 emit_opcode(cbuf,0x66);
2074 emit_opcode(cbuf,0x0F);
2075 emit_opcode(cbuf,0x7E);
2076 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg));
2077 }
2078 %}
2079
2080
2081 // Encode a reg-reg copy. If it is useless, then empty encoding.
2082 enc_class enc_Copy( eRegI dst, eRegI src ) %{
2083 encode_Copy( cbuf, $dst$$reg, $src$$reg );
2084 %}
2085
2086 enc_class enc_CopyL_Lo( eRegI dst, eRegL src ) %{
2087 encode_Copy( cbuf, $dst$$reg, $src$$reg );
2088 %}
2089
2090 // Encode xmm reg-reg copy. If it is useless, then empty encoding.
2091 enc_class enc_CopyXD( RegXD dst, RegXD src ) %{
2092 encode_CopyXD( cbuf, $dst$$reg, $src$$reg );
2093 %}
2094
2095 enc_class RegReg (eRegI dst, eRegI src) %{ // RegReg(Many)
2096 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2097 %}
2098
2099 enc_class RegReg_Lo(eRegL dst, eRegL src) %{ // RegReg(Many)
2100 $$$emit8$primary;
2101 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2102 %}
2103
2104 enc_class RegReg_Hi(eRegL dst, eRegL src) %{ // RegReg(Many)
2105 $$$emit8$secondary;
2106 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg));
2107 %}
2108
2109 enc_class RegReg_Lo2(eRegL dst, eRegL src) %{ // RegReg(Many)
2110 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2111 %}
2112
2113 enc_class RegReg_Hi2(eRegL dst, eRegL src) %{ // RegReg(Many)
2114 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg));
2115 %}
2116
2117 enc_class RegReg_HiLo( eRegL src, eRegI dst ) %{
2118 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($src$$reg));
2119 %}
2120
2121 enc_class Con32 (immI src) %{ // Con32(storeImmI)
2122 // Output immediate
2123 $$$emit32$src$$constant;
2124 %}
2125
2126 enc_class Con32F_as_bits(immF src) %{ // storeF_imm
2127 // Output Float immediate bits
2128 jfloat jf = $src$$constant;
2129 int jf_as_bits = jint_cast( jf );
2130 emit_d32(cbuf, jf_as_bits);
2131 %}
2132
2133 enc_class Con32XF_as_bits(immXF src) %{ // storeX_imm
2134 // Output Float immediate bits
2135 jfloat jf = $src$$constant;
2136 int jf_as_bits = jint_cast( jf );
2137 emit_d32(cbuf, jf_as_bits);
2138 %}
2139
2140 enc_class Con16 (immI src) %{ // Con16(storeImmI)
2141 // Output immediate
2142 $$$emit16$src$$constant;
2143 %}
2144
2145 enc_class Con_d32(immI src) %{
2146 emit_d32(cbuf,$src$$constant);
2147 %}
2148
2149 enc_class conmemref (eRegP t1) %{ // Con32(storeImmI)
2150 // Output immediate memory reference
2151 emit_rm(cbuf, 0x00, $t1$$reg, 0x05 );
2152 emit_d32(cbuf, 0x00);
2153 %}
2154
2155 enc_class lock_prefix( ) %{
2156 if( os::is_MP() )
2157 emit_opcode(cbuf,0xF0); // [Lock]
2158 %}
2159
2160 // Cmp-xchg long value.
2161 // Note: we need to swap rbx, and rcx before and after the
2162 // cmpxchg8 instruction because the instruction uses
2163 // rcx as the high order word of the new value to store but
2164 // our register encoding uses rbx,.
2165 enc_class enc_cmpxchg8(eSIRegP mem_ptr) %{
2166
2167 // XCHG rbx,ecx
2168 emit_opcode(cbuf,0x87);
2169 emit_opcode(cbuf,0xD9);
2170 // [Lock]
2171 if( os::is_MP() )
2172 emit_opcode(cbuf,0xF0);
2173 // CMPXCHG8 [Eptr]
2174 emit_opcode(cbuf,0x0F);
2175 emit_opcode(cbuf,0xC7);
2176 emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg );
2177 // XCHG rbx,ecx
2178 emit_opcode(cbuf,0x87);
2179 emit_opcode(cbuf,0xD9);
2180 %}
2181
2182 enc_class enc_cmpxchg(eSIRegP mem_ptr) %{
2183 // [Lock]
2184 if( os::is_MP() )
2185 emit_opcode(cbuf,0xF0);
2186
2187 // CMPXCHG [Eptr]
2188 emit_opcode(cbuf,0x0F);
2189 emit_opcode(cbuf,0xB1);
2190 emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg );
2191 %}
2192
2193 enc_class enc_flags_ne_to_boolean( iRegI res ) %{
2194 int res_encoding = $res$$reg;
2195
2196 // MOV res,0
2197 emit_opcode( cbuf, 0xB8 + res_encoding);
2198 emit_d32( cbuf, 0 );
2199 // JNE,s fail
2200 emit_opcode(cbuf,0x75);
2201 emit_d8(cbuf, 5 );
2202 // MOV res,1
2203 emit_opcode( cbuf, 0xB8 + res_encoding);
2204 emit_d32( cbuf, 1 );
2205 // fail:
2206 %}
2207
2208 enc_class set_instruction_start( ) %{
2209 cbuf.set_inst_mark(); // Mark start of opcode for reloc info in mem operand
2210 %}
2211
2212 enc_class RegMem (eRegI ereg, memory mem) %{ // emit_reg_mem
2213 int reg_encoding = $ereg$$reg;
2214 int base = $mem$$base;
2215 int index = $mem$$index;
2216 int scale = $mem$$scale;
2217 int displace = $mem$$disp;
2218 bool disp_is_oop = $mem->disp_is_oop();
2219 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2220 %}
2221
2222 enc_class RegMem_Hi(eRegL ereg, memory mem) %{ // emit_reg_mem
2223 int reg_encoding = HIGH_FROM_LOW($ereg$$reg); // Hi register of pair, computed from lo
2224 int base = $mem$$base;
2225 int index = $mem$$index;
2226 int scale = $mem$$scale;
2227 int displace = $mem$$disp + 4; // Offset is 4 further in memory
2228 assert( !$mem->disp_is_oop(), "Cannot add 4 to oop" );
2229 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, false/*disp_is_oop*/);
2230 %}
2231
2232 enc_class move_long_small_shift( eRegL dst, immI_1_31 cnt ) %{
2233 int r1, r2;
2234 if( $tertiary == 0xA4 ) { r1 = $dst$$reg; r2 = HIGH_FROM_LOW($dst$$reg); }
2235 else { r2 = $dst$$reg; r1 = HIGH_FROM_LOW($dst$$reg); }
2236 emit_opcode(cbuf,0x0F);
2237 emit_opcode(cbuf,$tertiary);
2238 emit_rm(cbuf, 0x3, r1, r2);
2239 emit_d8(cbuf,$cnt$$constant);
2240 emit_d8(cbuf,$primary);
2241 emit_rm(cbuf, 0x3, $secondary, r1);
2242 emit_d8(cbuf,$cnt$$constant);
2243 %}
2244
2245 enc_class move_long_big_shift_sign( eRegL dst, immI_32_63 cnt ) %{
2246 emit_opcode( cbuf, 0x8B ); // Move
2247 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg));
2248 emit_d8(cbuf,$primary);
2249 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
2250 emit_d8(cbuf,$cnt$$constant-32);
2251 emit_d8(cbuf,$primary);
2252 emit_rm(cbuf, 0x3, $secondary, HIGH_FROM_LOW($dst$$reg));
2253 emit_d8(cbuf,31);
2254 %}
2255
2256 enc_class move_long_big_shift_clr( eRegL dst, immI_32_63 cnt ) %{
2257 int r1, r2;
2258 if( $secondary == 0x5 ) { r1 = $dst$$reg; r2 = HIGH_FROM_LOW($dst$$reg); }
2259 else { r2 = $dst$$reg; r1 = HIGH_FROM_LOW($dst$$reg); }
2260
2261 emit_opcode( cbuf, 0x8B ); // Move r1,r2
2262 emit_rm(cbuf, 0x3, r1, r2);
2263 if( $cnt$$constant > 32 ) { // Shift, if not by zero
2264 emit_opcode(cbuf,$primary);
2265 emit_rm(cbuf, 0x3, $secondary, r1);
2266 emit_d8(cbuf,$cnt$$constant-32);
2267 }
2268 emit_opcode(cbuf,0x33); // XOR r2,r2
2269 emit_rm(cbuf, 0x3, r2, r2);
2270 %}
2271
2272 // Clone of RegMem but accepts an extra parameter to access each
2273 // half of a double in memory; it never needs relocation info.
2274 enc_class Mov_MemD_half_to_Reg (immI opcode, memory mem, immI disp_for_half, eRegI rm_reg) %{
2275 emit_opcode(cbuf,$opcode$$constant);
2276 int reg_encoding = $rm_reg$$reg;
2277 int base = $mem$$base;
2278 int index = $mem$$index;
2279 int scale = $mem$$scale;
2280 int displace = $mem$$disp + $disp_for_half$$constant;
2281 bool disp_is_oop = false;
2282 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2283 %}
2284
2285 // !!!!! Special Custom Code used by MemMove, and stack access instructions !!!!!
2286 //
2287 // Clone of RegMem except the RM-byte's reg/opcode field is an ADLC-time constant
2288 // and it never needs relocation information.
2289 // Frequently used to move data between FPU's Stack Top and memory.
2290 enc_class RMopc_Mem_no_oop (immI rm_opcode, memory mem) %{
2291 int rm_byte_opcode = $rm_opcode$$constant;
2292 int base = $mem$$base;
2293 int index = $mem$$index;
2294 int scale = $mem$$scale;
2295 int displace = $mem$$disp;
2296 assert( !$mem->disp_is_oop(), "No oops here because no relo info allowed" );
2297 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, false);
2298 %}
2299
2300 enc_class RMopc_Mem (immI rm_opcode, memory mem) %{
2301 int rm_byte_opcode = $rm_opcode$$constant;
2302 int base = $mem$$base;
2303 int index = $mem$$index;
2304 int scale = $mem$$scale;
2305 int displace = $mem$$disp;
2306 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
2307 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_is_oop);
2308 %}
2309
2310 enc_class RegLea (eRegI dst, eRegI src0, immI src1 ) %{ // emit_reg_lea
2311 int reg_encoding = $dst$$reg;
2312 int base = $src0$$reg; // 0xFFFFFFFF indicates no base
2313 int index = 0x04; // 0x04 indicates no index
2314 int scale = 0x00; // 0x00 indicates no scale
2315 int displace = $src1$$constant; // 0x00 indicates no displacement
2316 bool disp_is_oop = false;
2317 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2318 %}
2319
2320 enc_class min_enc (eRegI dst, eRegI src) %{ // MIN
2321 // Compare dst,src
2322 emit_opcode(cbuf,0x3B);
2323 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2324 // jmp dst < src around move
2325 emit_opcode(cbuf,0x7C);
2326 emit_d8(cbuf,2);
2327 // move dst,src
2328 emit_opcode(cbuf,0x8B);
2329 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2330 %}
2331
2332 enc_class max_enc (eRegI dst, eRegI src) %{ // MAX
2333 // Compare dst,src
2334 emit_opcode(cbuf,0x3B);
2335 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2336 // jmp dst > src around move
2337 emit_opcode(cbuf,0x7F);
2338 emit_d8(cbuf,2);
2339 // move dst,src
2340 emit_opcode(cbuf,0x8B);
2341 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2342 %}
2343
2344 enc_class enc_FP_store(memory mem, regD src) %{
2345 // If src is FPR1, we can just FST to store it.
2346 // Else we need to FLD it to FPR1, then FSTP to store/pop it.
2347 int reg_encoding = 0x2; // Just store
2348 int base = $mem$$base;
2349 int index = $mem$$index;
2350 int scale = $mem$$scale;
2351 int displace = $mem$$disp;
2352 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
2353 if( $src$$reg != FPR1L_enc ) {
2354 reg_encoding = 0x3; // Store & pop
2355 emit_opcode( cbuf, 0xD9 ); // FLD (i.e., push it)
2356 emit_d8( cbuf, 0xC0-1+$src$$reg );
2357 }
2358 cbuf.set_inst_mark(); // Mark start of opcode for reloc info in mem operand
2359 emit_opcode(cbuf,$primary);
2360 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2361 %}
2362
2363 enc_class neg_reg(eRegI dst) %{
2364 // NEG $dst
2365 emit_opcode(cbuf,0xF7);
2366 emit_rm(cbuf, 0x3, 0x03, $dst$$reg );
2367 %}
2368
2369 enc_class setLT_reg(eCXRegI dst) %{
2370 // SETLT $dst
2371 emit_opcode(cbuf,0x0F);
2372 emit_opcode(cbuf,0x9C);
2373 emit_rm( cbuf, 0x3, 0x4, $dst$$reg );
2374 %}
2375
2376 enc_class enc_cmpLTP(ncxRegI p, ncxRegI q, ncxRegI y, eCXRegI tmp) %{ // cadd_cmpLT
2377 int tmpReg = $tmp$$reg;
2378
2379 // SUB $p,$q
2380 emit_opcode(cbuf,0x2B);
2381 emit_rm(cbuf, 0x3, $p$$reg, $q$$reg);
2382 // SBB $tmp,$tmp
2383 emit_opcode(cbuf,0x1B);
2384 emit_rm(cbuf, 0x3, tmpReg, tmpReg);
2385 // AND $tmp,$y
2386 emit_opcode(cbuf,0x23);
2387 emit_rm(cbuf, 0x3, tmpReg, $y$$reg);
2388 // ADD $p,$tmp
2389 emit_opcode(cbuf,0x03);
2390 emit_rm(cbuf, 0x3, $p$$reg, tmpReg);
2391 %}
2392
2393 enc_class enc_cmpLTP_mem(eRegI p, eRegI q, memory mem, eCXRegI tmp) %{ // cadd_cmpLT
2394 int tmpReg = $tmp$$reg;
2395
2396 // SUB $p,$q
2397 emit_opcode(cbuf,0x2B);
2398 emit_rm(cbuf, 0x3, $p$$reg, $q$$reg);
2399 // SBB $tmp,$tmp
2400 emit_opcode(cbuf,0x1B);
2401 emit_rm(cbuf, 0x3, tmpReg, tmpReg);
2402 // AND $tmp,$y
2403 cbuf.set_inst_mark(); // Mark start of opcode for reloc info in mem operand
2404 emit_opcode(cbuf,0x23);
2405 int reg_encoding = tmpReg;
2406 int base = $mem$$base;
2407 int index = $mem$$index;
2408 int scale = $mem$$scale;
2409 int displace = $mem$$disp;
2410 bool disp_is_oop = $mem->disp_is_oop();
2411 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2412 // ADD $p,$tmp
2413 emit_opcode(cbuf,0x03);
2414 emit_rm(cbuf, 0x3, $p$$reg, tmpReg);
2415 %}
2416
2417 enc_class shift_left_long( eRegL dst, eCXRegI shift ) %{
2418 // TEST shift,32
2419 emit_opcode(cbuf,0xF7);
2420 emit_rm(cbuf, 0x3, 0, ECX_enc);
2421 emit_d32(cbuf,0x20);
2422 // JEQ,s small
2423 emit_opcode(cbuf, 0x74);
2424 emit_d8(cbuf, 0x04);
2425 // MOV $dst.hi,$dst.lo
2426 emit_opcode( cbuf, 0x8B );
2427 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg );
2428 // CLR $dst.lo
2429 emit_opcode(cbuf, 0x33);
2430 emit_rm(cbuf, 0x3, $dst$$reg, $dst$$reg);
2431 // small:
2432 // SHLD $dst.hi,$dst.lo,$shift
2433 emit_opcode(cbuf,0x0F);
2434 emit_opcode(cbuf,0xA5);
2435 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg));
2436 // SHL $dst.lo,$shift"
2437 emit_opcode(cbuf,0xD3);
2438 emit_rm(cbuf, 0x3, 0x4, $dst$$reg );
2439 %}
2440
2441 enc_class shift_right_long( eRegL dst, eCXRegI shift ) %{
2442 // TEST shift,32
2443 emit_opcode(cbuf,0xF7);
2444 emit_rm(cbuf, 0x3, 0, ECX_enc);
2445 emit_d32(cbuf,0x20);
2446 // JEQ,s small
2447 emit_opcode(cbuf, 0x74);
2448 emit_d8(cbuf, 0x04);
2449 // MOV $dst.lo,$dst.hi
2450 emit_opcode( cbuf, 0x8B );
2451 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) );
2452 // CLR $dst.hi
2453 emit_opcode(cbuf, 0x33);
2454 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($dst$$reg));
2455 // small:
2456 // SHRD $dst.lo,$dst.hi,$shift
2457 emit_opcode(cbuf,0x0F);
2458 emit_opcode(cbuf,0xAD);
2459 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg);
2460 // SHR $dst.hi,$shift"
2461 emit_opcode(cbuf,0xD3);
2462 emit_rm(cbuf, 0x3, 0x5, HIGH_FROM_LOW($dst$$reg) );
2463 %}
2464
2465 enc_class shift_right_arith_long( eRegL dst, eCXRegI shift ) %{
2466 // TEST shift,32
2467 emit_opcode(cbuf,0xF7);
2468 emit_rm(cbuf, 0x3, 0, ECX_enc);
2469 emit_d32(cbuf,0x20);
2470 // JEQ,s small
2471 emit_opcode(cbuf, 0x74);
2472 emit_d8(cbuf, 0x05);
2473 // MOV $dst.lo,$dst.hi
2474 emit_opcode( cbuf, 0x8B );
2475 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) );
2476 // SAR $dst.hi,31
2477 emit_opcode(cbuf, 0xC1);
2478 emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW($dst$$reg) );
2479 emit_d8(cbuf, 0x1F );
2480 // small:
2481 // SHRD $dst.lo,$dst.hi,$shift
2482 emit_opcode(cbuf,0x0F);
2483 emit_opcode(cbuf,0xAD);
2484 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg);
2485 // SAR $dst.hi,$shift"
2486 emit_opcode(cbuf,0xD3);
2487 emit_rm(cbuf, 0x3, 0x7, HIGH_FROM_LOW($dst$$reg) );
2488 %}
2489
2490
2491 // ----------------- Encodings for floating point unit -----------------
2492 // May leave result in FPU-TOS or FPU reg depending on opcodes
2493 enc_class OpcReg_F (regF src) %{ // FMUL, FDIV
2494 $$$emit8$primary;
2495 emit_rm(cbuf, 0x3, $secondary, $src$$reg );
2496 %}
2497
2498 // Pop argument in FPR0 with FSTP ST(0)
2499 enc_class PopFPU() %{
2500 emit_opcode( cbuf, 0xDD );
2501 emit_d8( cbuf, 0xD8 );
2502 %}
2503
2504 // !!!!! equivalent to Pop_Reg_F
2505 enc_class Pop_Reg_D( regD dst ) %{
2506 emit_opcode( cbuf, 0xDD ); // FSTP ST(i)
2507 emit_d8( cbuf, 0xD8+$dst$$reg );
2508 %}
2509
2510 enc_class Push_Reg_D( regD dst ) %{
2511 emit_opcode( cbuf, 0xD9 );
2512 emit_d8( cbuf, 0xC0-1+$dst$$reg ); // FLD ST(i-1)
2513 %}
2514
2515 enc_class strictfp_bias1( regD dst ) %{
2516 emit_opcode( cbuf, 0xDB ); // FLD m80real
2517 emit_opcode( cbuf, 0x2D );
2518 emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias1() );
2519 emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0
2520 emit_opcode( cbuf, 0xC8+$dst$$reg );
2521 %}
2522
2523 enc_class strictfp_bias2( regD dst ) %{
2524 emit_opcode( cbuf, 0xDB ); // FLD m80real
2525 emit_opcode( cbuf, 0x2D );
2526 emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias2() );
2527 emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0
2528 emit_opcode( cbuf, 0xC8+$dst$$reg );
2529 %}
2530
2531 // Special case for moving an integer register to a stack slot.
2532 enc_class OpcPRegSS( stackSlotI dst, eRegI src ) %{ // RegSS
2533 store_to_stackslot( cbuf, $primary, $src$$reg, $dst$$disp );
2534 %}
2535
2536 // Special case for moving a register to a stack slot.
2537 enc_class RegSS( stackSlotI dst, eRegI src ) %{ // RegSS
2538 // Opcode already emitted
2539 emit_rm( cbuf, 0x02, $src$$reg, ESP_enc ); // R/M byte
2540 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
2541 emit_d32(cbuf, $dst$$disp); // Displacement
2542 %}
2543
2544 // Push the integer in stackSlot 'src' onto FP-stack
2545 enc_class Push_Mem_I( memory src ) %{ // FILD [ESP+src]
2546 store_to_stackslot( cbuf, $primary, $secondary, $src$$disp );
2547 %}
2548
2549 // Push the float in stackSlot 'src' onto FP-stack
2550 enc_class Push_Mem_F( memory src ) %{ // FLD_S [ESP+src]
2551 store_to_stackslot( cbuf, 0xD9, 0x00, $src$$disp );
2552 %}
2553
2554 // Push the double in stackSlot 'src' onto FP-stack
2555 enc_class Push_Mem_D( memory src ) %{ // FLD_D [ESP+src]
2556 store_to_stackslot( cbuf, 0xDD, 0x00, $src$$disp );
2557 %}
2558
2559 // Push FPU's TOS float to a stack-slot, and pop FPU-stack
2560 enc_class Pop_Mem_F( stackSlotF dst ) %{ // FSTP_S [ESP+dst]
2561 store_to_stackslot( cbuf, 0xD9, 0x03, $dst$$disp );
2562 %}
2563
2564 // Same as Pop_Mem_F except for opcode
2565 // Push FPU's TOS double to a stack-slot, and pop FPU-stack
2566 enc_class Pop_Mem_D( stackSlotD dst ) %{ // FSTP_D [ESP+dst]
2567 store_to_stackslot( cbuf, 0xDD, 0x03, $dst$$disp );
2568 %}
2569
2570 enc_class Pop_Reg_F( regF dst ) %{
2571 emit_opcode( cbuf, 0xDD ); // FSTP ST(i)
2572 emit_d8( cbuf, 0xD8+$dst$$reg );
2573 %}
2574
2575 enc_class Push_Reg_F( regF dst ) %{
2576 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2577 emit_d8( cbuf, 0xC0-1+$dst$$reg );
2578 %}
2579
2580 // Push FPU's float to a stack-slot, and pop FPU-stack
2581 enc_class Pop_Mem_Reg_F( stackSlotF dst, regF src ) %{
2582 int pop = 0x02;
2583 if ($src$$reg != FPR1L_enc) {
2584 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2585 emit_d8( cbuf, 0xC0-1+$src$$reg );
2586 pop = 0x03;
2587 }
2588 store_to_stackslot( cbuf, 0xD9, pop, $dst$$disp ); // FST<P>_S [ESP+dst]
2589 %}
2590
2591 // Push FPU's double to a stack-slot, and pop FPU-stack
2592 enc_class Pop_Mem_Reg_D( stackSlotD dst, regD src ) %{
2593 int pop = 0x02;
2594 if ($src$$reg != FPR1L_enc) {
2595 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2596 emit_d8( cbuf, 0xC0-1+$src$$reg );
2597 pop = 0x03;
2598 }
2599 store_to_stackslot( cbuf, 0xDD, pop, $dst$$disp ); // FST<P>_D [ESP+dst]
2600 %}
2601
2602 // Push FPU's double to a FPU-stack-slot, and pop FPU-stack
2603 enc_class Pop_Reg_Reg_D( regD dst, regF src ) %{
2604 int pop = 0xD0 - 1; // -1 since we skip FLD
2605 if ($src$$reg != FPR1L_enc) {
2606 emit_opcode( cbuf, 0xD9 ); // FLD ST(src-1)
2607 emit_d8( cbuf, 0xC0-1+$src$$reg );
2608 pop = 0xD8;
2609 }
2610 emit_opcode( cbuf, 0xDD );
2611 emit_d8( cbuf, pop+$dst$$reg ); // FST<P> ST(i)
2612 %}
2613
2614
2615 enc_class Mul_Add_F( regF dst, regF src, regF src1, regF src2 ) %{
2616 MacroAssembler masm(&cbuf);
2617 masm.fld_s( $src1$$reg-1); // nothing at TOS, load TOS from src1.reg
2618 masm.fmul( $src2$$reg+0); // value at TOS
2619 masm.fadd( $src$$reg+0); // value at TOS
2620 masm.fstp_d( $dst$$reg+0); // value at TOS, popped off after store
2621 %}
2622
2623
2624 enc_class Push_Reg_Mod_D( regD dst, regD src) %{
2625 // load dst in FPR0
2626 emit_opcode( cbuf, 0xD9 );
2627 emit_d8( cbuf, 0xC0-1+$dst$$reg );
2628 if ($src$$reg != FPR1L_enc) {
2629 // fincstp
2630 emit_opcode (cbuf, 0xD9);
2631 emit_opcode (cbuf, 0xF7);
2632 // swap src with FPR1:
2633 // FXCH FPR1 with src
2634 emit_opcode(cbuf, 0xD9);
2635 emit_d8(cbuf, 0xC8-1+$src$$reg );
2636 // fdecstp
2637 emit_opcode (cbuf, 0xD9);
2638 emit_opcode (cbuf, 0xF6);
2639 }
2640 %}
2641
2642 enc_class Push_ModD_encoding( regXD src0, regXD src1) %{
2643 // Allocate a word
2644 emit_opcode(cbuf,0x83); // SUB ESP,8
2645 emit_opcode(cbuf,0xEC);
2646 emit_d8(cbuf,0x08);
2647
2648 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], src1
2649 emit_opcode (cbuf, 0x0F );
2650 emit_opcode (cbuf, 0x11 );
2651 encode_RegMem(cbuf, $src1$$reg, ESP_enc, 0x4, 0, 0, false);
2652
2653 emit_opcode(cbuf,0xDD ); // FLD_D [ESP]
2654 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
2655
2656 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], src0
2657 emit_opcode (cbuf, 0x0F );
2658 emit_opcode (cbuf, 0x11 );
2659 encode_RegMem(cbuf, $src0$$reg, ESP_enc, 0x4, 0, 0, false);
2660
2661 emit_opcode(cbuf,0xDD ); // FLD_D [ESP]
2662 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
2663
2664 %}
2665
2666 enc_class Push_ModX_encoding( regX src0, regX src1) %{
2667 // Allocate a word
2668 emit_opcode(cbuf,0x83); // SUB ESP,4
2669 emit_opcode(cbuf,0xEC);
2670 emit_d8(cbuf,0x04);
2671
2672 emit_opcode (cbuf, 0xF3 ); // MOVSS [ESP], src1
2673 emit_opcode (cbuf, 0x0F );
2674 emit_opcode (cbuf, 0x11 );
2675 encode_RegMem(cbuf, $src1$$reg, ESP_enc, 0x4, 0, 0, false);
2676
2677 emit_opcode(cbuf,0xD9 ); // FLD [ESP]
2678 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
2679
2680 emit_opcode (cbuf, 0xF3 ); // MOVSS [ESP], src0
2681 emit_opcode (cbuf, 0x0F );
2682 emit_opcode (cbuf, 0x11 );
2683 encode_RegMem(cbuf, $src0$$reg, ESP_enc, 0x4, 0, 0, false);
2684
2685 emit_opcode(cbuf,0xD9 ); // FLD [ESP]
2686 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
2687
2688 %}
2689
2690 enc_class Push_ResultXD(regXD dst) %{
2691 store_to_stackslot( cbuf, 0xDD, 0x03, 0 ); //FSTP [ESP]
2692
2693 // UseXmmLoadAndClearUpper ? movsd dst,[esp] : movlpd dst,[esp]
2694 emit_opcode (cbuf, UseXmmLoadAndClearUpper ? 0xF2 : 0x66);
2695 emit_opcode (cbuf, 0x0F );
2696 emit_opcode (cbuf, UseXmmLoadAndClearUpper ? 0x10 : 0x12);
2697 encode_RegMem(cbuf, $dst$$reg, ESP_enc, 0x4, 0, 0, false);
2698
2699 emit_opcode(cbuf,0x83); // ADD ESP,8
2700 emit_opcode(cbuf,0xC4);
2701 emit_d8(cbuf,0x08);
2702 %}
2703
2704 enc_class Push_ResultX(regX dst, immI d8) %{
2705 store_to_stackslot( cbuf, 0xD9, 0x03, 0 ); //FSTP_S [ESP]
2706
2707 emit_opcode (cbuf, 0xF3 ); // MOVSS dst(xmm), [ESP]
2708 emit_opcode (cbuf, 0x0F );
2709 emit_opcode (cbuf, 0x10 );
2710 encode_RegMem(cbuf, $dst$$reg, ESP_enc, 0x4, 0, 0, false);
2711
2712 emit_opcode(cbuf,0x83); // ADD ESP,d8 (4 or 8)
2713 emit_opcode(cbuf,0xC4);
2714 emit_d8(cbuf,$d8$$constant);
2715 %}
2716
2717 enc_class Push_SrcXD(regXD src) %{
2718 // Allocate a word
2719 emit_opcode(cbuf,0x83); // SUB ESP,8
2720 emit_opcode(cbuf,0xEC);
2721 emit_d8(cbuf,0x08);
2722
2723 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], src
2724 emit_opcode (cbuf, 0x0F );
2725 emit_opcode (cbuf, 0x11 );
2726 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false);
2727
2728 emit_opcode(cbuf,0xDD ); // FLD_D [ESP]
2729 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
2730 %}
2731
2732 enc_class push_stack_temp_qword() %{
2733 emit_opcode(cbuf,0x83); // SUB ESP,8
2734 emit_opcode(cbuf,0xEC);
2735 emit_d8 (cbuf,0x08);
2736 %}
2737
2738 enc_class pop_stack_temp_qword() %{
2739 emit_opcode(cbuf,0x83); // ADD ESP,8
2740 emit_opcode(cbuf,0xC4);
2741 emit_d8 (cbuf,0x08);
2742 %}
2743
2744 enc_class push_xmm_to_fpr1( regXD xmm_src ) %{
2745 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], xmm_src
2746 emit_opcode (cbuf, 0x0F );
2747 emit_opcode (cbuf, 0x11 );
2748 encode_RegMem(cbuf, $xmm_src$$reg, ESP_enc, 0x4, 0, 0, false);
2749
2750 emit_opcode(cbuf,0xDD ); // FLD_D [ESP]
2751 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
2752 %}
2753
2754 // Compute X^Y using Intel's fast hardware instructions, if possible.
2755 // Otherwise return a NaN.
2756 enc_class pow_exp_core_encoding %{
2757 // FPR1 holds Y*ln2(X). Compute FPR1 = 2^(Y*ln2(X))
2758 emit_opcode(cbuf,0xD9); emit_opcode(cbuf,0xC0); // fdup = fld st(0) Q Q
2759 emit_opcode(cbuf,0xD9); emit_opcode(cbuf,0xFC); // frndint int(Q) Q
2760 emit_opcode(cbuf,0xDC); emit_opcode(cbuf,0xE9); // fsub st(1) -= st(0); int(Q) frac(Q)
2761 emit_opcode(cbuf,0xDB); // FISTP [ESP] frac(Q)
2762 emit_opcode(cbuf,0x1C);
2763 emit_d8(cbuf,0x24);
2764 emit_opcode(cbuf,0xD9); emit_opcode(cbuf,0xF0); // f2xm1 2^frac(Q)-1
2765 emit_opcode(cbuf,0xD9); emit_opcode(cbuf,0xE8); // fld1 1 2^frac(Q)-1
2766 emit_opcode(cbuf,0xDE); emit_opcode(cbuf,0xC1); // faddp 2^frac(Q)
2767 emit_opcode(cbuf,0x8B); // mov rax,[esp+0]=int(Q)
2768 encode_RegMem(cbuf, EAX_enc, ESP_enc, 0x4, 0, 0, false);
2769 emit_opcode(cbuf,0xC7); // mov rcx,0xFFFFF800 - overflow mask
2770 emit_rm(cbuf, 0x3, 0x0, ECX_enc);
2771 emit_d32(cbuf,0xFFFFF800);
2772 emit_opcode(cbuf,0x81); // add rax,1023 - the double exponent bias
2773 emit_rm(cbuf, 0x3, 0x0, EAX_enc);
2774 emit_d32(cbuf,1023);
2775 emit_opcode(cbuf,0x8B); // mov rbx,eax
2776 emit_rm(cbuf, 0x3, EBX_enc, EAX_enc);
2777 emit_opcode(cbuf,0xC1); // shl rax,20 - Slide to exponent position
2778 emit_rm(cbuf,0x3,0x4,EAX_enc);
2779 emit_d8(cbuf,20);
2780 emit_opcode(cbuf,0x85); // test rbx,ecx - check for overflow
2781 emit_rm(cbuf, 0x3, EBX_enc, ECX_enc);
2782 emit_opcode(cbuf,0x0F); emit_opcode(cbuf,0x45); // CMOVne rax,ecx - overflow; stuff NAN into EAX
2783 emit_rm(cbuf, 0x3, EAX_enc, ECX_enc);
2784 emit_opcode(cbuf,0x89); // mov [esp+4],eax - Store as part of double word
2785 encode_RegMem(cbuf, EAX_enc, ESP_enc, 0x4, 0, 4, false);
2786 emit_opcode(cbuf,0xC7); // mov [esp+0],0 - [ESP] = (double)(1<<int(Q)) = 2^int(Q)
2787 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
2788 emit_d32(cbuf,0);
2789 emit_opcode(cbuf,0xDC); // fmul dword st(0),[esp+0]; FPR1 = 2^int(Q)*2^frac(Q) = 2^Q
2790 encode_RegMem(cbuf, 0x1, ESP_enc, 0x4, 0, 0, false);
2791 %}
2792
2793 // enc_class Pop_Reg_Mod_D( regD dst, regD src)
2794 // was replaced by Push_Result_Mod_D followed by Pop_Reg_X() or Pop_Mem_X()
2795
2796 enc_class Push_Result_Mod_D( regD src) %{
2797 if ($src$$reg != FPR1L_enc) {
2798 // fincstp
2799 emit_opcode (cbuf, 0xD9);
2800 emit_opcode (cbuf, 0xF7);
2801 // FXCH FPR1 with src
2802 emit_opcode(cbuf, 0xD9);
2803 emit_d8(cbuf, 0xC8-1+$src$$reg );
2804 // fdecstp
2805 emit_opcode (cbuf, 0xD9);
2806 emit_opcode (cbuf, 0xF6);
2807 }
2808 // // following asm replaced with Pop_Reg_F or Pop_Mem_F
2809 // // FSTP FPR$dst$$reg
2810 // emit_opcode( cbuf, 0xDD );
2811 // emit_d8( cbuf, 0xD8+$dst$$reg );
2812 %}
2813
2814 enc_class fnstsw_sahf_skip_parity() %{
2815 // fnstsw ax
2816 emit_opcode( cbuf, 0xDF );
2817 emit_opcode( cbuf, 0xE0 );
2818 // sahf
2819 emit_opcode( cbuf, 0x9E );
2820 // jnp ::skip
2821 emit_opcode( cbuf, 0x7B );
2822 emit_opcode( cbuf, 0x05 );
2823 %}
2824
2825 enc_class emitModD() %{
2826 // fprem must be iterative
2827 // :: loop
2828 // fprem
2829 emit_opcode( cbuf, 0xD9 );
2830 emit_opcode( cbuf, 0xF8 );
2831 // wait
2832 emit_opcode( cbuf, 0x9b );
2833 // fnstsw ax
2834 emit_opcode( cbuf, 0xDF );
2835 emit_opcode( cbuf, 0xE0 );
2836 // sahf
2837 emit_opcode( cbuf, 0x9E );
2838 // jp ::loop
2839 emit_opcode( cbuf, 0x0F );
2840 emit_opcode( cbuf, 0x8A );
2841 emit_opcode( cbuf, 0xF4 );
2842 emit_opcode( cbuf, 0xFF );
2843 emit_opcode( cbuf, 0xFF );
2844 emit_opcode( cbuf, 0xFF );
2845 %}
2846
2847 enc_class fpu_flags() %{
2848 // fnstsw_ax
2849 emit_opcode( cbuf, 0xDF);
2850 emit_opcode( cbuf, 0xE0);
2851 // test ax,0x0400
2852 emit_opcode( cbuf, 0x66 ); // operand-size prefix for 16-bit immediate
2853 emit_opcode( cbuf, 0xA9 );
2854 emit_d16 ( cbuf, 0x0400 );
2855 // // // This sequence works, but stalls for 12-16 cycles on PPro
2856 // // test rax,0x0400
2857 // emit_opcode( cbuf, 0xA9 );
2858 // emit_d32 ( cbuf, 0x00000400 );
2859 //
2860 // jz exit (no unordered comparison)
2861 emit_opcode( cbuf, 0x74 );
2862 emit_d8 ( cbuf, 0x02 );
2863 // mov ah,1 - treat as LT case (set carry flag)
2864 emit_opcode( cbuf, 0xB4 );
2865 emit_d8 ( cbuf, 0x01 );
2866 // sahf
2867 emit_opcode( cbuf, 0x9E);
2868 %}
2869
2870 enc_class cmpF_P6_fixup() %{
2871 // Fixup the integer flags in case comparison involved a NaN
2872 //
2873 // JNP exit (no unordered comparison, P-flag is set by NaN)
2874 emit_opcode( cbuf, 0x7B );
2875 emit_d8 ( cbuf, 0x03 );
2876 // MOV AH,1 - treat as LT case (set carry flag)
2877 emit_opcode( cbuf, 0xB4 );
2878 emit_d8 ( cbuf, 0x01 );
2879 // SAHF
2880 emit_opcode( cbuf, 0x9E);
2881 // NOP // target for branch to avoid branch to branch
2882 emit_opcode( cbuf, 0x90);
2883 %}
2884
2885 // fnstsw_ax();
2886 // sahf();
2887 // movl(dst, nan_result);
2888 // jcc(Assembler::parity, exit);
2889 // movl(dst, less_result);
2890 // jcc(Assembler::below, exit);
2891 // movl(dst, equal_result);
2892 // jcc(Assembler::equal, exit);
2893 // movl(dst, greater_result);
2894
2895 // less_result = 1;
2896 // greater_result = -1;
2897 // equal_result = 0;
2898 // nan_result = -1;
2899
2900 enc_class CmpF_Result(eRegI dst) %{
2901 // fnstsw_ax();
2902 emit_opcode( cbuf, 0xDF);
2903 emit_opcode( cbuf, 0xE0);
2904 // sahf
2905 emit_opcode( cbuf, 0x9E);
2906 // movl(dst, nan_result);
2907 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2908 emit_d32( cbuf, -1 );
2909 // jcc(Assembler::parity, exit);
2910 emit_opcode( cbuf, 0x7A );
2911 emit_d8 ( cbuf, 0x13 );
2912 // movl(dst, less_result);
2913 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2914 emit_d32( cbuf, -1 );
2915 // jcc(Assembler::below, exit);
2916 emit_opcode( cbuf, 0x72 );
2917 emit_d8 ( cbuf, 0x0C );
2918 // movl(dst, equal_result);
2919 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2920 emit_d32( cbuf, 0 );
2921 // jcc(Assembler::equal, exit);
2922 emit_opcode( cbuf, 0x74 );
2923 emit_d8 ( cbuf, 0x05 );
2924 // movl(dst, greater_result);
2925 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2926 emit_d32( cbuf, 1 );
2927 %}
2928
2929
2930 // XMM version of CmpF_Result. Because the XMM compare
2931 // instructions set the EFLAGS directly. It becomes simpler than
2932 // the float version above.
2933 enc_class CmpX_Result(eRegI dst) %{
2934 MacroAssembler _masm(&cbuf);
2935 Label nan, inc, done;
2936
2937 __ jccb(Assembler::parity, nan);
2938 __ jccb(Assembler::equal, done);
2939 __ jccb(Assembler::above, inc);
2940 __ bind(nan);
2941 __ decrement(as_Register($dst$$reg)); // NO L qqq
2942 __ jmpb(done);
2943 __ bind(inc);
2944 __ increment(as_Register($dst$$reg)); // NO L qqq
2945 __ bind(done);
2946 %}
2947
2948 // Compare the longs and set flags
2949 // BROKEN! Do Not use as-is
2950 enc_class cmpl_test( eRegL src1, eRegL src2 ) %{
2951 // CMP $src1.hi,$src2.hi
2952 emit_opcode( cbuf, 0x3B );
2953 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) );
2954 // JNE,s done
2955 emit_opcode(cbuf,0x75);
2956 emit_d8(cbuf, 2 );
2957 // CMP $src1.lo,$src2.lo
2958 emit_opcode( cbuf, 0x3B );
2959 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
2960 // done:
2961 %}
2962
2963 enc_class convert_int_long( regL dst, eRegI src ) %{
2964 // mov $dst.lo,$src
2965 int dst_encoding = $dst$$reg;
2966 int src_encoding = $src$$reg;
2967 encode_Copy( cbuf, dst_encoding , src_encoding );
2968 // mov $dst.hi,$src
2969 encode_Copy( cbuf, HIGH_FROM_LOW(dst_encoding), src_encoding );
2970 // sar $dst.hi,31
2971 emit_opcode( cbuf, 0xC1 );
2972 emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW(dst_encoding) );
2973 emit_d8(cbuf, 0x1F );
2974 %}
2975
2976 enc_class convert_long_double( eRegL src ) %{
2977 // push $src.hi
2978 emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg));
2979 // push $src.lo
2980 emit_opcode(cbuf, 0x50+$src$$reg );
2981 // fild 64-bits at [SP]
2982 emit_opcode(cbuf,0xdf);
2983 emit_d8(cbuf, 0x6C);
2984 emit_d8(cbuf, 0x24);
2985 emit_d8(cbuf, 0x00);
2986 // pop stack
2987 emit_opcode(cbuf, 0x83); // add SP, #8
2988 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
2989 emit_d8(cbuf, 0x8);
2990 %}
2991
2992 enc_class multiply_con_and_shift_high( eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr ) %{
2993 // IMUL EDX:EAX,$src1
2994 emit_opcode( cbuf, 0xF7 );
2995 emit_rm( cbuf, 0x3, 0x5, $src1$$reg );
2996 // SAR EDX,$cnt-32
2997 int shift_count = ((int)$cnt$$constant) - 32;
2998 if (shift_count > 0) {
2999 emit_opcode(cbuf, 0xC1);
3000 emit_rm(cbuf, 0x3, 7, $dst$$reg );
3001 emit_d8(cbuf, shift_count);
3002 }
3003 %}
3004
3005 // this version doesn't have add sp, 8
3006 enc_class convert_long_double2( eRegL src ) %{
3007 // push $src.hi
3008 emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg));
3009 // push $src.lo
3010 emit_opcode(cbuf, 0x50+$src$$reg );
3011 // fild 64-bits at [SP]
3012 emit_opcode(cbuf,0xdf);
3013 emit_d8(cbuf, 0x6C);
3014 emit_d8(cbuf, 0x24);
3015 emit_d8(cbuf, 0x00);
3016 %}
3017
3018 enc_class long_int_multiply( eADXRegL dst, nadxRegI src) %{
3019 // Basic idea: long = (long)int * (long)int
3020 // IMUL EDX:EAX, src
3021 emit_opcode( cbuf, 0xF7 );
3022 emit_rm( cbuf, 0x3, 0x5, $src$$reg);
3023 %}
3024
3025 enc_class long_uint_multiply( eADXRegL dst, nadxRegI src) %{
3026 // Basic Idea: long = (int & 0xffffffffL) * (int & 0xffffffffL)
3027 // MUL EDX:EAX, src
3028 emit_opcode( cbuf, 0xF7 );
3029 emit_rm( cbuf, 0x3, 0x4, $src$$reg);
3030 %}
3031
3032 enc_class long_multiply( eADXRegL dst, eRegL src, eRegI tmp ) %{
3033 // Basic idea: lo(result) = lo(x_lo * y_lo)
3034 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
3035 // MOV $tmp,$src.lo
3036 encode_Copy( cbuf, $tmp$$reg, $src$$reg );
3037 // IMUL $tmp,EDX
3038 emit_opcode( cbuf, 0x0F );
3039 emit_opcode( cbuf, 0xAF );
3040 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
3041 // MOV EDX,$src.hi
3042 encode_Copy( cbuf, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg) );
3043 // IMUL EDX,EAX
3044 emit_opcode( cbuf, 0x0F );
3045 emit_opcode( cbuf, 0xAF );
3046 emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg );
3047 // ADD $tmp,EDX
3048 emit_opcode( cbuf, 0x03 );
3049 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
3050 // MUL EDX:EAX,$src.lo
3051 emit_opcode( cbuf, 0xF7 );
3052 emit_rm( cbuf, 0x3, 0x4, $src$$reg );
3053 // ADD EDX,ESI
3054 emit_opcode( cbuf, 0x03 );
3055 emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $tmp$$reg );
3056 %}
3057
3058 enc_class long_multiply_con( eADXRegL dst, immL_127 src, eRegI tmp ) %{
3059 // Basic idea: lo(result) = lo(src * y_lo)
3060 // hi(result) = hi(src * y_lo) + lo(src * y_hi)
3061 // IMUL $tmp,EDX,$src
3062 emit_opcode( cbuf, 0x6B );
3063 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
3064 emit_d8( cbuf, (int)$src$$constant );
3065 // MOV EDX,$src
3066 emit_opcode(cbuf, 0xB8 + EDX_enc);
3067 emit_d32( cbuf, (int)$src$$constant );
3068 // MUL EDX:EAX,EDX
3069 emit_opcode( cbuf, 0xF7 );
3070 emit_rm( cbuf, 0x3, 0x4, EDX_enc );
3071 // ADD EDX,ESI
3072 emit_opcode( cbuf, 0x03 );
3073 emit_rm( cbuf, 0x3, EDX_enc, $tmp$$reg );
3074 %}
3075
3076 enc_class long_div( eRegL src1, eRegL src2 ) %{
3077 // PUSH src1.hi
3078 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) );
3079 // PUSH src1.lo
3080 emit_opcode(cbuf, 0x50+$src1$$reg );
3081 // PUSH src2.hi
3082 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) );
3083 // PUSH src2.lo
3084 emit_opcode(cbuf, 0x50+$src2$$reg );
3085 // CALL directly to the runtime
3086 cbuf.set_inst_mark();
3087 emit_opcode(cbuf,0xE8); // Call into runtime
3088 emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::ldiv) - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
3089 // Restore stack
3090 emit_opcode(cbuf, 0x83); // add SP, #framesize
3091 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
3092 emit_d8(cbuf, 4*4);
3093 %}
3094
3095 enc_class long_mod( eRegL src1, eRegL src2 ) %{
3096 // PUSH src1.hi
3097 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) );
3098 // PUSH src1.lo
3099 emit_opcode(cbuf, 0x50+$src1$$reg );
3100 // PUSH src2.hi
3101 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) );
3102 // PUSH src2.lo
3103 emit_opcode(cbuf, 0x50+$src2$$reg );
3104 // CALL directly to the runtime
3105 cbuf.set_inst_mark();
3106 emit_opcode(cbuf,0xE8); // Call into runtime
3107 emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::lrem ) - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
3108 // Restore stack
3109 emit_opcode(cbuf, 0x83); // add SP, #framesize
3110 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
3111 emit_d8(cbuf, 4*4);
3112 %}
3113
3114 enc_class long_cmp_flags0( eRegL src, eRegI tmp ) %{
3115 // MOV $tmp,$src.lo
3116 emit_opcode(cbuf, 0x8B);
3117 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg);
3118 // OR $tmp,$src.hi
3119 emit_opcode(cbuf, 0x0B);
3120 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg));
3121 %}
3122
3123 enc_class long_cmp_flags1( eRegL src1, eRegL src2 ) %{
3124 // CMP $src1.lo,$src2.lo
3125 emit_opcode( cbuf, 0x3B );
3126 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
3127 // JNE,s skip
3128 emit_cc(cbuf, 0x70, 0x5);
3129 emit_d8(cbuf,2);
3130 // CMP $src1.hi,$src2.hi
3131 emit_opcode( cbuf, 0x3B );
3132 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) );
3133 %}
3134
3135 enc_class long_cmp_flags2( eRegL src1, eRegL src2, eRegI tmp ) %{
3136 // CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits
3137 emit_opcode( cbuf, 0x3B );
3138 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
3139 // MOV $tmp,$src1.hi
3140 emit_opcode( cbuf, 0x8B );
3141 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src1$$reg) );
3142 // SBB $tmp,$src2.hi\t! Compute flags for long compare
3143 emit_opcode( cbuf, 0x1B );
3144 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src2$$reg) );
3145 %}
3146
3147 enc_class long_cmp_flags3( eRegL src, eRegI tmp ) %{
3148 // XOR $tmp,$tmp
3149 emit_opcode(cbuf,0x33); // XOR
3150 emit_rm(cbuf,0x3, $tmp$$reg, $tmp$$reg);
3151 // CMP $tmp,$src.lo
3152 emit_opcode( cbuf, 0x3B );
3153 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg );
3154 // SBB $tmp,$src.hi
3155 emit_opcode( cbuf, 0x1B );
3156 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg) );
3157 %}
3158
3159 // Sniff, sniff... smells like Gnu Superoptimizer
3160 enc_class neg_long( eRegL dst ) %{
3161 emit_opcode(cbuf,0xF7); // NEG hi
3162 emit_rm (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg));
3163 emit_opcode(cbuf,0xF7); // NEG lo
3164 emit_rm (cbuf,0x3, 0x3, $dst$$reg );
3165 emit_opcode(cbuf,0x83); // SBB hi,0
3166 emit_rm (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg));
3167 emit_d8 (cbuf,0 );
3168 %}
3169
3170 enc_class movq_ld(regXD dst, memory mem) %{
3171 MacroAssembler _masm(&cbuf);
3172 __ movq($dst$$XMMRegister, $mem$$Address);
3173 %}
3174
3175 enc_class movq_st(memory mem, regXD src) %{
3176 MacroAssembler _masm(&cbuf);
3177 __ movq($mem$$Address, $src$$XMMRegister);
3178 %}
3179
3180 enc_class pshufd_8x8(regX dst, regX src) %{
3181 MacroAssembler _masm(&cbuf);
3182
3183 encode_CopyXD(cbuf, $dst$$reg, $src$$reg);
3184 __ punpcklbw(as_XMMRegister($dst$$reg), as_XMMRegister($dst$$reg));
3185 __ pshuflw(as_XMMRegister($dst$$reg), as_XMMRegister($dst$$reg), 0x00);
3186 %}
3187
3188 enc_class pshufd_4x16(regX dst, regX src) %{
3189 MacroAssembler _masm(&cbuf);
3190
3191 __ pshuflw(as_XMMRegister($dst$$reg), as_XMMRegister($src$$reg), 0x00);
3192 %}
3193
3194 enc_class pshufd(regXD dst, regXD src, int mode) %{
3195 MacroAssembler _masm(&cbuf);
3196
3197 __ pshufd(as_XMMRegister($dst$$reg), as_XMMRegister($src$$reg), $mode);
3198 %}
3199
3200 enc_class pxor(regXD dst, regXD src) %{
3201 MacroAssembler _masm(&cbuf);
3202
3203 __ pxor(as_XMMRegister($dst$$reg), as_XMMRegister($src$$reg));
3204 %}
3205
3206 enc_class mov_i2x(regXD dst, eRegI src) %{
3207 MacroAssembler _masm(&cbuf);
3208
3209 __ movdl(as_XMMRegister($dst$$reg), as_Register($src$$reg));
3210 %}
3211
3212
3213 // Because the transitions from emitted code to the runtime
3214 // monitorenter/exit helper stubs are so slow it's critical that
3215 // we inline both the stack-locking fast-path and the inflated fast path.
3216 //
3217 // See also: cmpFastLock and cmpFastUnlock.
3218 //
3219 // What follows is a specialized inline transliteration of the code
3220 // in slow_enter() and slow_exit(). If we're concerned about I$ bloat
3221 // another option would be to emit TrySlowEnter and TrySlowExit methods
3222 // at startup-time. These methods would accept arguments as
3223 // (rax,=Obj, rbx=Self, rcx=box, rdx=Scratch) and return success-failure
3224 // indications in the icc.ZFlag. Fast_Lock and Fast_Unlock would simply
3225 // marshal the arguments and emit calls to TrySlowEnter and TrySlowExit.
3226 // In practice, however, the # of lock sites is bounded and is usually small.
3227 // Besides the call overhead, TrySlowEnter and TrySlowExit might suffer
3228 // if the processor uses simple bimodal branch predictors keyed by EIP
3229 // Since the helper routines would be called from multiple synchronization
3230 // sites.
3231 //
3232 // An even better approach would be write "MonitorEnter()" and "MonitorExit()"
3233 // in java - using j.u.c and unsafe - and just bind the lock and unlock sites
3234 // to those specialized methods. That'd give us a mostly platform-independent
3235 // implementation that the JITs could optimize and inline at their pleasure.
3236 // Done correctly, the only time we'd need to cross to native could would be
3237 // to park() or unpark() threads. We'd also need a few more unsafe operators
3238 // to (a) prevent compiler-JIT reordering of non-volatile accesses, and
3239 // (b) explicit barriers or fence operations.
3240 //
3241 // TODO:
3242 //
3243 // * Arrange for C2 to pass "Self" into Fast_Lock and Fast_Unlock in one of the registers (scr).
3244 // This avoids manifesting the Self pointer in the Fast_Lock and Fast_Unlock terminals.
3245 // Given TLAB allocation, Self is usually manifested in a register, so passing it into
3246 // the lock operators would typically be faster than reifying Self.
3247 //
3248 // * Ideally I'd define the primitives as:
3249 // fast_lock (nax Obj, nax box, EAX tmp, nax scr) where box, tmp and scr are KILLED.
3250 // fast_unlock (nax Obj, EAX box, nax tmp) where box and tmp are KILLED
3251 // Unfortunately ADLC bugs prevent us from expressing the ideal form.
3252 // Instead, we're stuck with a rather awkward and brittle register assignments below.
3253 // Furthermore the register assignments are overconstrained, possibly resulting in
3254 // sub-optimal code near the synchronization site.
3255 //
3256 // * Eliminate the sp-proximity tests and just use "== Self" tests instead.
3257 // Alternately, use a better sp-proximity test.
3258 //
3259 // * Currently ObjectMonitor._Owner can hold either an sp value or a (THREAD *) value.
3260 // Either one is sufficient to uniquely identify a thread.
3261 // TODO: eliminate use of sp in _owner and use get_thread(tr) instead.
3262 //
3263 // * Intrinsify notify() and notifyAll() for the common cases where the
3264 // object is locked by the calling thread but the waitlist is empty.
3265 // avoid the expensive JNI call to JVM_Notify() and JVM_NotifyAll().
3266 //
3267 // * use jccb and jmpb instead of jcc and jmp to improve code density.
3268 // But beware of excessive branch density on AMD Opterons.
3269 //
3270 // * Both Fast_Lock and Fast_Unlock set the ICC.ZF to indicate success
3271 // or failure of the fast-path. If the fast-path fails then we pass
3272 // control to the slow-path, typically in C. In Fast_Lock and
3273 // Fast_Unlock we often branch to DONE_LABEL, just to find that C2
3274 // will emit a conditional branch immediately after the node.
3275 // So we have branches to branches and lots of ICC.ZF games.
3276 // Instead, it might be better to have C2 pass a "FailureLabel"
3277 // into Fast_Lock and Fast_Unlock. In the case of success, control
3278 // will drop through the node. ICC.ZF is undefined at exit.
3279 // In the case of failure, the node will branch directly to the
3280 // FailureLabel
3281
3282
3283 // obj: object to lock
3284 // box: on-stack box address (displaced header location) - KILLED
3285 // rax,: tmp -- KILLED
3286 // scr: tmp -- KILLED
3287 enc_class Fast_Lock( eRegP obj, eRegP box, eAXRegI tmp, eRegP scr ) %{
3288
3289 Register objReg = as_Register($obj$$reg);
3290 Register boxReg = as_Register($box$$reg);
3291 Register tmpReg = as_Register($tmp$$reg);
3292 Register scrReg = as_Register($scr$$reg);
3293
3294 // Ensure the register assignents are disjoint
3295 guarantee (objReg != boxReg, "") ;
3296 guarantee (objReg != tmpReg, "") ;
3297 guarantee (objReg != scrReg, "") ;
3298 guarantee (boxReg != tmpReg, "") ;
3299 guarantee (boxReg != scrReg, "") ;
3300 guarantee (tmpReg == as_Register(EAX_enc), "") ;
3301
3302 MacroAssembler masm(&cbuf);
3303
3304 if (_counters != NULL) {
3305 masm.atomic_incl(ExternalAddress((address) _counters->total_entry_count_addr()));
3306 }
3307 if (EmitSync & 1) {
3308 // set box->dhw = unused_mark (3)
3309 // Force all sync thru slow-path: slow_enter() and slow_exit()
3310 masm.movptr (Address(boxReg, 0), int32_t(markOopDesc::unused_mark())) ;
3311 masm.cmpptr (rsp, (int32_t)0) ;
3312 } else
3313 if (EmitSync & 2) {
3314 Label DONE_LABEL ;
3315 if (UseBiasedLocking) {
3316 // Note: tmpReg maps to the swap_reg argument and scrReg to the tmp_reg argument.
3317 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters);
3318 }
3319
3320 masm.movptr(tmpReg, Address(objReg, 0)) ; // fetch markword
3321 masm.orptr (tmpReg, 0x1);
3322 masm.movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS
3323 if (os::is_MP()) { masm.lock(); }
3324 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
3325 masm.jcc(Assembler::equal, DONE_LABEL);
3326 // Recursive locking
3327 masm.subptr(tmpReg, rsp);
3328 masm.andptr(tmpReg, (int32_t) 0xFFFFF003 );
3329 masm.movptr(Address(boxReg, 0), tmpReg);
3330 masm.bind(DONE_LABEL) ;
3331 } else {
3332 // Possible cases that we'll encounter in fast_lock
3333 // ------------------------------------------------
3334 // * Inflated
3335 // -- unlocked
3336 // -- Locked
3337 // = by self
3338 // = by other
3339 // * biased
3340 // -- by Self
3341 // -- by other
3342 // * neutral
3343 // * stack-locked
3344 // -- by self
3345 // = sp-proximity test hits
3346 // = sp-proximity test generates false-negative
3347 // -- by other
3348 //
3349
3350 Label IsInflated, DONE_LABEL, PopDone ;
3351
3352 // TODO: optimize away redundant LDs of obj->mark and improve the markword triage
3353 // order to reduce the number of conditional branches in the most common cases.
3354 // Beware -- there's a subtle invariant that fetch of the markword
3355 // at [FETCH], below, will never observe a biased encoding (*101b).
3356 // If this invariant is not held we risk exclusion (safety) failure.
3357 if (UseBiasedLocking && !UseOptoBiasInlining) {
3358 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters);
3359 }
3360
3361 masm.movptr(tmpReg, Address(objReg, 0)) ; // [FETCH]
3362 masm.testptr(tmpReg, 0x02) ; // Inflated v (Stack-locked or neutral)
3363 masm.jccb (Assembler::notZero, IsInflated) ;
3364
3365 // Attempt stack-locking ...
3366 masm.orptr (tmpReg, 0x1);
3367 masm.movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS
3368 if (os::is_MP()) { masm.lock(); }
3369 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
3370 if (_counters != NULL) {
3371 masm.cond_inc32(Assembler::equal,
3372 ExternalAddress((address)_counters->fast_path_entry_count_addr()));
3373 }
3374 masm.jccb (Assembler::equal, DONE_LABEL);
3375
3376 // Recursive locking
3377 masm.subptr(tmpReg, rsp);
3378 masm.andptr(tmpReg, 0xFFFFF003 );
3379 masm.movptr(Address(boxReg, 0), tmpReg);
3380 if (_counters != NULL) {
3381 masm.cond_inc32(Assembler::equal,
3382 ExternalAddress((address)_counters->fast_path_entry_count_addr()));
3383 }
3384 masm.jmp (DONE_LABEL) ;
3385
3386 masm.bind (IsInflated) ;
3387
3388 // The object is inflated.
3389 //
3390 // TODO-FIXME: eliminate the ugly use of manifest constants:
3391 // Use markOopDesc::monitor_value instead of "2".
3392 // use markOop::unused_mark() instead of "3".
3393 // The tmpReg value is an objectMonitor reference ORed with
3394 // markOopDesc::monitor_value (2). We can either convert tmpReg to an
3395 // objectmonitor pointer by masking off the "2" bit or we can just
3396 // use tmpReg as an objectmonitor pointer but bias the objectmonitor
3397 // field offsets with "-2" to compensate for and annul the low-order tag bit.
3398 //
3399 // I use the latter as it avoids AGI stalls.
3400 // As such, we write "mov r, [tmpReg+OFFSETOF(Owner)-2]"
3401 // instead of "mov r, [tmpReg+OFFSETOF(Owner)]".
3402 //
3403 #define OFFSET_SKEWED(f) ((ObjectMonitor::f ## _offset_in_bytes())-2)
3404
3405 // boxReg refers to the on-stack BasicLock in the current frame.
3406 // We'd like to write:
3407 // set box->_displaced_header = markOop::unused_mark(). Any non-0 value suffices.
3408 // This is convenient but results a ST-before-CAS penalty. The following CAS suffers
3409 // additional latency as we have another ST in the store buffer that must drain.
3410
3411 if (EmitSync & 8192) {
3412 masm.movptr(Address(boxReg, 0), 3) ; // results in ST-before-CAS penalty
3413 masm.get_thread (scrReg) ;
3414 masm.movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
3415 masm.movptr(tmpReg, NULL_WORD); // consider: xor vs mov
3416 if (os::is_MP()) { masm.lock(); }
3417 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3418 } else
3419 if ((EmitSync & 128) == 0) { // avoid ST-before-CAS
3420 masm.movptr(scrReg, boxReg) ;
3421 masm.movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
3422
3423 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
3424 if ((EmitSync & 2048) && VM_Version::supports_3dnow() && os::is_MP()) {
3425 // prefetchw [eax + Offset(_owner)-2]
3426 masm.prefetchw(Address(rax, ObjectMonitor::owner_offset_in_bytes()-2));
3427 }
3428
3429 if ((EmitSync & 64) == 0) {
3430 // Optimistic form: consider XORL tmpReg,tmpReg
3431 masm.movptr(tmpReg, NULL_WORD) ;
3432 } else {
3433 // Can suffer RTS->RTO upgrades on shared or cold $ lines
3434 // Test-And-CAS instead of CAS
3435 masm.movptr(tmpReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; // rax, = m->_owner
3436 masm.testptr(tmpReg, tmpReg) ; // Locked ?
3437 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3438 }
3439
3440 // Appears unlocked - try to swing _owner from null to non-null.
3441 // Ideally, I'd manifest "Self" with get_thread and then attempt
3442 // to CAS the register containing Self into m->Owner.
3443 // But we don't have enough registers, so instead we can either try to CAS
3444 // rsp or the address of the box (in scr) into &m->owner. If the CAS succeeds
3445 // we later store "Self" into m->Owner. Transiently storing a stack address
3446 // (rsp or the address of the box) into m->owner is harmless.
3447 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
3448 if (os::is_MP()) { masm.lock(); }
3449 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3450 masm.movptr(Address(scrReg, 0), 3) ; // box->_displaced_header = 3
3451 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3452 masm.get_thread (scrReg) ; // beware: clobbers ICCs
3453 masm.movptr(Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2), scrReg) ;
3454 masm.xorptr(boxReg, boxReg) ; // set icc.ZFlag = 1 to indicate success
3455
3456 // If the CAS fails we can either retry or pass control to the slow-path.
3457 // We use the latter tactic.
3458 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
3459 // If the CAS was successful ...
3460 // Self has acquired the lock
3461 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
3462 // Intentional fall-through into DONE_LABEL ...
3463 } else {
3464 masm.movptr(Address(boxReg, 0), 3) ; // results in ST-before-CAS penalty
3465 masm.movptr(boxReg, tmpReg) ;
3466
3467 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
3468 if ((EmitSync & 2048) && VM_Version::supports_3dnow() && os::is_MP()) {
3469 // prefetchw [eax + Offset(_owner)-2]
3470 masm.prefetchw(Address(rax, ObjectMonitor::owner_offset_in_bytes()-2));
3471 }
3472
3473 if ((EmitSync & 64) == 0) {
3474 // Optimistic form
3475 masm.xorptr (tmpReg, tmpReg) ;
3476 } else {
3477 // Can suffer RTS->RTO upgrades on shared or cold $ lines
3478 masm.movptr(tmpReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; // rax, = m->_owner
3479 masm.testptr(tmpReg, tmpReg) ; // Locked ?
3480 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3481 }
3482
3483 // Appears unlocked - try to swing _owner from null to non-null.
3484 // Use either "Self" (in scr) or rsp as thread identity in _owner.
3485 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
3486 masm.get_thread (scrReg) ;
3487 if (os::is_MP()) { masm.lock(); }
3488 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3489
3490 // If the CAS fails we can either retry or pass control to the slow-path.
3491 // We use the latter tactic.
3492 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
3493 // If the CAS was successful ...
3494 // Self has acquired the lock
3495 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
3496 // Intentional fall-through into DONE_LABEL ...
3497 }
3498
3499 // DONE_LABEL is a hot target - we'd really like to place it at the
3500 // start of cache line by padding with NOPs.
3501 // See the AMD and Intel software optimization manuals for the
3502 // most efficient "long" NOP encodings.
3503 // Unfortunately none of our alignment mechanisms suffice.
3504 masm.bind(DONE_LABEL);
3505
3506 // Avoid branch-to-branch on AMD processors
3507 // This appears to be superstition.
3508 if (EmitSync & 32) masm.nop() ;
3509
3510
3511 // At DONE_LABEL the icc ZFlag is set as follows ...
3512 // Fast_Unlock uses the same protocol.
3513 // ZFlag == 1 -> Success
3514 // ZFlag == 0 -> Failure - force control through the slow-path
3515 }
3516 %}
3517
3518 // obj: object to unlock
3519 // box: box address (displaced header location), killed. Must be EAX.
3520 // rbx,: killed tmp; cannot be obj nor box.
3521 //
3522 // Some commentary on balanced locking:
3523 //
3524 // Fast_Lock and Fast_Unlock are emitted only for provably balanced lock sites.
3525 // Methods that don't have provably balanced locking are forced to run in the
3526 // interpreter - such methods won't be compiled to use fast_lock and fast_unlock.
3527 // The interpreter provides two properties:
3528 // I1: At return-time the interpreter automatically and quietly unlocks any
3529 // objects acquired the current activation (frame). Recall that the
3530 // interpreter maintains an on-stack list of locks currently held by
3531 // a frame.
3532 // I2: If a method attempts to unlock an object that is not held by the
3533 // the frame the interpreter throws IMSX.
3534 //
3535 // Lets say A(), which has provably balanced locking, acquires O and then calls B().
3536 // B() doesn't have provably balanced locking so it runs in the interpreter.
3537 // Control returns to A() and A() unlocks O. By I1 and I2, above, we know that O
3538 // is still locked by A().
3539 //
3540 // The only other source of unbalanced locking would be JNI. The "Java Native Interface:
3541 // Programmer's Guide and Specification" claims that an object locked by jni_monitorenter
3542 // should not be unlocked by "normal" java-level locking and vice-versa. The specification
3543 // doesn't specify what will occur if a program engages in such mixed-mode locking, however.
3544
3545 enc_class Fast_Unlock( nabxRegP obj, eAXRegP box, eRegP tmp) %{
3546
3547 Register objReg = as_Register($obj$$reg);
3548 Register boxReg = as_Register($box$$reg);
3549 Register tmpReg = as_Register($tmp$$reg);
3550
3551 guarantee (objReg != boxReg, "") ;
3552 guarantee (objReg != tmpReg, "") ;
3553 guarantee (boxReg != tmpReg, "") ;
3554 guarantee (boxReg == as_Register(EAX_enc), "") ;
3555 MacroAssembler masm(&cbuf);
3556
3557 if (EmitSync & 4) {
3558 // Disable - inhibit all inlining. Force control through the slow-path
3559 masm.cmpptr (rsp, 0) ;
3560 } else
3561 if (EmitSync & 8) {
3562 Label DONE_LABEL ;
3563 if (UseBiasedLocking) {
3564 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL);
3565 }
3566 // classic stack-locking code ...
3567 masm.movptr(tmpReg, Address(boxReg, 0)) ;
3568 masm.testptr(tmpReg, tmpReg) ;
3569 masm.jcc (Assembler::zero, DONE_LABEL) ;
3570 if (os::is_MP()) { masm.lock(); }
3571 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses EAX which is box
3572 masm.bind(DONE_LABEL);
3573 } else {
3574 Label DONE_LABEL, Stacked, CheckSucc, Inflated ;
3575
3576 // Critically, the biased locking test must have precedence over
3577 // and appear before the (box->dhw == 0) recursive stack-lock test.
3578 if (UseBiasedLocking && !UseOptoBiasInlining) {
3579 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL);
3580 }
3581
3582 masm.cmpptr(Address(boxReg, 0), 0) ; // Examine the displaced header
3583 masm.movptr(tmpReg, Address(objReg, 0)) ; // Examine the object's markword
3584 masm.jccb (Assembler::zero, DONE_LABEL) ; // 0 indicates recursive stack-lock
3585
3586 masm.testptr(tmpReg, 0x02) ; // Inflated?
3587 masm.jccb (Assembler::zero, Stacked) ;
3588
3589 masm.bind (Inflated) ;
3590 // It's inflated.
3591 // Despite our balanced locking property we still check that m->_owner == Self
3592 // as java routines or native JNI code called by this thread might
3593 // have released the lock.
3594 // Refer to the comments in synchronizer.cpp for how we might encode extra
3595 // state in _succ so we can avoid fetching EntryList|cxq.
3596 //
3597 // I'd like to add more cases in fast_lock() and fast_unlock() --
3598 // such as recursive enter and exit -- but we have to be wary of
3599 // I$ bloat, T$ effects and BP$ effects.
3600 //
3601 // If there's no contention try a 1-0 exit. That is, exit without
3602 // a costly MEMBAR or CAS. See synchronizer.cpp for details on how
3603 // we detect and recover from the race that the 1-0 exit admits.
3604 //
3605 // Conceptually Fast_Unlock() must execute a STST|LDST "release" barrier
3606 // before it STs null into _owner, releasing the lock. Updates
3607 // to data protected by the critical section must be visible before
3608 // we drop the lock (and thus before any other thread could acquire
3609 // the lock and observe the fields protected by the lock).
3610 // IA32's memory-model is SPO, so STs are ordered with respect to
3611 // each other and there's no need for an explicit barrier (fence).
3612 // See also http://gee.cs.oswego.edu/dl/jmm/cookbook.html.
3613
3614 masm.get_thread (boxReg) ;
3615 if ((EmitSync & 4096) && VM_Version::supports_3dnow() && os::is_MP()) {
3616 // prefetchw [ebx + Offset(_owner)-2]
3617 masm.prefetchw(Address(rbx, ObjectMonitor::owner_offset_in_bytes()-2));
3618 }
3619
3620 // Note that we could employ various encoding schemes to reduce
3621 // the number of loads below (currently 4) to just 2 or 3.
3622 // Refer to the comments in synchronizer.cpp.
3623 // In practice the chain of fetches doesn't seem to impact performance, however.
3624 if ((EmitSync & 65536) == 0 && (EmitSync & 256)) {
3625 // Attempt to reduce branch density - AMD's branch predictor.
3626 masm.xorptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3627 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ;
3628 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ;
3629 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ;
3630 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3631 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ;
3632 masm.jmpb (DONE_LABEL) ;
3633 } else {
3634 masm.xorptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3635 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ;
3636 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3637 masm.movptr(boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ;
3638 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ;
3639 masm.jccb (Assembler::notZero, CheckSucc) ;
3640 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ;
3641 masm.jmpb (DONE_LABEL) ;
3642 }
3643
3644 // The Following code fragment (EmitSync & 65536) improves the performance of
3645 // contended applications and contended synchronization microbenchmarks.
3646 // Unfortunately the emission of the code - even though not executed - causes regressions
3647 // in scimark and jetstream, evidently because of $ effects. Replacing the code
3648 // with an equal number of never-executed NOPs results in the same regression.
3649 // We leave it off by default.
3650
3651 if ((EmitSync & 65536) != 0) {
3652 Label LSuccess, LGoSlowPath ;
3653
3654 masm.bind (CheckSucc) ;
3655
3656 // Optional pre-test ... it's safe to elide this
3657 if ((EmitSync & 16) == 0) {
3658 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), 0) ;
3659 masm.jccb (Assembler::zero, LGoSlowPath) ;
3660 }
3661
3662 // We have a classic Dekker-style idiom:
3663 // ST m->_owner = 0 ; MEMBAR; LD m->_succ
3664 // There are a number of ways to implement the barrier:
3665 // (1) lock:andl &m->_owner, 0
3666 // is fast, but mask doesn't currently support the "ANDL M,IMM32" form.
3667 // LOCK: ANDL [ebx+Offset(_Owner)-2], 0
3668 // Encodes as 81 31 OFF32 IMM32 or 83 63 OFF8 IMM8
3669 // (2) If supported, an explicit MFENCE is appealing.
3670 // In older IA32 processors MFENCE is slower than lock:add or xchg
3671 // particularly if the write-buffer is full as might be the case if
3672 // if stores closely precede the fence or fence-equivalent instruction.
3673 // In more modern implementations MFENCE appears faster, however.
3674 // (3) In lieu of an explicit fence, use lock:addl to the top-of-stack
3675 // The $lines underlying the top-of-stack should be in M-state.
3676 // The locked add instruction is serializing, of course.
3677 // (4) Use xchg, which is serializing
3678 // mov boxReg, 0; xchgl boxReg, [tmpReg + Offset(_owner)-2] also works
3679 // (5) ST m->_owner = 0 and then execute lock:orl &m->_succ, 0.
3680 // The integer condition codes will tell us if succ was 0.
3681 // Since _succ and _owner should reside in the same $line and
3682 // we just stored into _owner, it's likely that the $line
3683 // remains in M-state for the lock:orl.
3684 //
3685 // We currently use (3), although it's likely that switching to (2)
3686 // is correct for the future.
3687
3688 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ;
3689 if (os::is_MP()) {
3690 if (VM_Version::supports_sse2() && 1 == FenceInstruction) {
3691 masm.mfence();
3692 } else {
3693 masm.lock () ; masm.addptr(Address(rsp, 0), 0) ;
3694 }
3695 }
3696 // Ratify _succ remains non-null
3697 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), 0) ;
3698 masm.jccb (Assembler::notZero, LSuccess) ;
3699
3700 masm.xorptr(boxReg, boxReg) ; // box is really EAX
3701 if (os::is_MP()) { masm.lock(); }
3702 masm.cmpxchgptr(rsp, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2));
3703 masm.jccb (Assembler::notEqual, LSuccess) ;
3704 // Since we're low on registers we installed rsp as a placeholding in _owner.
3705 // Now install Self over rsp. This is safe as we're transitioning from
3706 // non-null to non=null
3707 masm.get_thread (boxReg) ;
3708 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), boxReg) ;
3709 // Intentional fall-through into LGoSlowPath ...
3710
3711 masm.bind (LGoSlowPath) ;
3712 masm.orptr(boxReg, 1) ; // set ICC.ZF=0 to indicate failure
3713 masm.jmpb (DONE_LABEL) ;
3714
3715 masm.bind (LSuccess) ;
3716 masm.xorptr(boxReg, boxReg) ; // set ICC.ZF=1 to indicate success
3717 masm.jmpb (DONE_LABEL) ;
3718 }
3719
3720 masm.bind (Stacked) ;
3721 // It's not inflated and it's not recursively stack-locked and it's not biased.
3722 // It must be stack-locked.
3723 // Try to reset the header to displaced header.
3724 // The "box" value on the stack is stable, so we can reload
3725 // and be assured we observe the same value as above.
3726 masm.movptr(tmpReg, Address(boxReg, 0)) ;
3727 if (os::is_MP()) { masm.lock(); }
3728 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses EAX which is box
3729 // Intention fall-thru into DONE_LABEL
3730
3731
3732 // DONE_LABEL is a hot target - we'd really like to place it at the
3733 // start of cache line by padding with NOPs.
3734 // See the AMD and Intel software optimization manuals for the
3735 // most efficient "long" NOP encodings.
3736 // Unfortunately none of our alignment mechanisms suffice.
3737 if ((EmitSync & 65536) == 0) {
3738 masm.bind (CheckSucc) ;
3739 }
3740 masm.bind(DONE_LABEL);
3741
3742 // Avoid branch to branch on AMD processors
3743 if (EmitSync & 32768) { masm.nop() ; }
3744 }
3745 %}
3746
3747
3748 enc_class enc_pop_rdx() %{
3749 emit_opcode(cbuf,0x5A);
3750 %}
3751
3752 enc_class enc_rethrow() %{
3753 cbuf.set_inst_mark();
3754 emit_opcode(cbuf, 0xE9); // jmp entry
3755 emit_d32_reloc(cbuf, (int)OptoRuntime::rethrow_stub() - ((int)cbuf.code_end())-4,
3756 runtime_call_Relocation::spec(), RELOC_IMM32 );
3757 %}
3758
3759
3760 // Convert a double to an int. Java semantics require we do complex
3761 // manglelations in the corner cases. So we set the rounding mode to
3762 // 'zero', store the darned double down as an int, and reset the
3763 // rounding mode to 'nearest'. The hardware throws an exception which
3764 // patches up the correct value directly to the stack.
3765 enc_class D2I_encoding( regD src ) %{
3766 // Flip to round-to-zero mode. We attempted to allow invalid-op
3767 // exceptions here, so that a NAN or other corner-case value will
3768 // thrown an exception (but normal values get converted at full speed).
3769 // However, I2C adapters and other float-stack manglers leave pending
3770 // invalid-op exceptions hanging. We would have to clear them before
3771 // enabling them and that is more expensive than just testing for the
3772 // invalid value Intel stores down in the corner cases.
3773 emit_opcode(cbuf,0xD9); // FLDCW trunc
3774 emit_opcode(cbuf,0x2D);
3775 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
3776 // Allocate a word
3777 emit_opcode(cbuf,0x83); // SUB ESP,4
3778 emit_opcode(cbuf,0xEC);
3779 emit_d8(cbuf,0x04);
3780 // Encoding assumes a double has been pushed into FPR0.
3781 // Store down the double as an int, popping the FPU stack
3782 emit_opcode(cbuf,0xDB); // FISTP [ESP]
3783 emit_opcode(cbuf,0x1C);
3784 emit_d8(cbuf,0x24);
3785 // Restore the rounding mode; mask the exception
3786 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode
3787 emit_opcode(cbuf,0x2D);
3788 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
3789 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
3790 : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
3791
3792 // Load the converted int; adjust CPU stack
3793 emit_opcode(cbuf,0x58); // POP EAX
3794 emit_opcode(cbuf,0x3D); // CMP EAX,imm
3795 emit_d32 (cbuf,0x80000000); // 0x80000000
3796 emit_opcode(cbuf,0x75); // JNE around_slow_call
3797 emit_d8 (cbuf,0x07); // Size of slow_call
3798 // Push src onto stack slow-path
3799 emit_opcode(cbuf,0xD9 ); // FLD ST(i)
3800 emit_d8 (cbuf,0xC0-1+$src$$reg );
3801 // CALL directly to the runtime
3802 cbuf.set_inst_mark();
3803 emit_opcode(cbuf,0xE8); // Call into runtime
3804 emit_d32_reloc(cbuf, (StubRoutines::d2i_wrapper() - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
3805 // Carry on here...
3806 %}
3807
3808 enc_class D2L_encoding( regD src ) %{
3809 emit_opcode(cbuf,0xD9); // FLDCW trunc
3810 emit_opcode(cbuf,0x2D);
3811 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
3812 // Allocate a word
3813 emit_opcode(cbuf,0x83); // SUB ESP,8
3814 emit_opcode(cbuf,0xEC);
3815 emit_d8(cbuf,0x08);
3816 // Encoding assumes a double has been pushed into FPR0.
3817 // Store down the double as a long, popping the FPU stack
3818 emit_opcode(cbuf,0xDF); // FISTP [ESP]
3819 emit_opcode(cbuf,0x3C);
3820 emit_d8(cbuf,0x24);
3821 // Restore the rounding mode; mask the exception
3822 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode
3823 emit_opcode(cbuf,0x2D);
3824 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
3825 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
3826 : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
3827
3828 // Load the converted int; adjust CPU stack
3829 emit_opcode(cbuf,0x58); // POP EAX
3830 emit_opcode(cbuf,0x5A); // POP EDX
3831 emit_opcode(cbuf,0x81); // CMP EDX,imm
3832 emit_d8 (cbuf,0xFA); // rdx
3833 emit_d32 (cbuf,0x80000000); // 0x80000000
3834 emit_opcode(cbuf,0x75); // JNE around_slow_call
3835 emit_d8 (cbuf,0x07+4); // Size of slow_call
3836 emit_opcode(cbuf,0x85); // TEST EAX,EAX
3837 emit_opcode(cbuf,0xC0); // 2/rax,/rax,
3838 emit_opcode(cbuf,0x75); // JNE around_slow_call
3839 emit_d8 (cbuf,0x07); // Size of slow_call
3840 // Push src onto stack slow-path
3841 emit_opcode(cbuf,0xD9 ); // FLD ST(i)
3842 emit_d8 (cbuf,0xC0-1+$src$$reg );
3843 // CALL directly to the runtime
3844 cbuf.set_inst_mark();
3845 emit_opcode(cbuf,0xE8); // Call into runtime
3846 emit_d32_reloc(cbuf, (StubRoutines::d2l_wrapper() - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
3847 // Carry on here...
3848 %}
3849
3850 enc_class X2L_encoding( regX src ) %{
3851 // Allocate a word
3852 emit_opcode(cbuf,0x83); // SUB ESP,8
3853 emit_opcode(cbuf,0xEC);
3854 emit_d8(cbuf,0x08);
3855
3856 emit_opcode (cbuf, 0xF3 ); // MOVSS [ESP], src
3857 emit_opcode (cbuf, 0x0F );
3858 emit_opcode (cbuf, 0x11 );
3859 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false);
3860
3861 emit_opcode(cbuf,0xD9 ); // FLD_S [ESP]
3862 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
3863
3864 emit_opcode(cbuf,0xD9); // FLDCW trunc
3865 emit_opcode(cbuf,0x2D);
3866 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
3867
3868 // Encoding assumes a double has been pushed into FPR0.
3869 // Store down the double as a long, popping the FPU stack
3870 emit_opcode(cbuf,0xDF); // FISTP [ESP]
3871 emit_opcode(cbuf,0x3C);
3872 emit_d8(cbuf,0x24);
3873
3874 // Restore the rounding mode; mask the exception
3875 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode
3876 emit_opcode(cbuf,0x2D);
3877 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
3878 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
3879 : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
3880
3881 // Load the converted int; adjust CPU stack
3882 emit_opcode(cbuf,0x58); // POP EAX
3883
3884 emit_opcode(cbuf,0x5A); // POP EDX
3885
3886 emit_opcode(cbuf,0x81); // CMP EDX,imm
3887 emit_d8 (cbuf,0xFA); // rdx
3888 emit_d32 (cbuf,0x80000000);// 0x80000000
3889
3890 emit_opcode(cbuf,0x75); // JNE around_slow_call
3891 emit_d8 (cbuf,0x13+4); // Size of slow_call
3892
3893 emit_opcode(cbuf,0x85); // TEST EAX,EAX
3894 emit_opcode(cbuf,0xC0); // 2/rax,/rax,
3895
3896 emit_opcode(cbuf,0x75); // JNE around_slow_call
3897 emit_d8 (cbuf,0x13); // Size of slow_call
3898
3899 // Allocate a word
3900 emit_opcode(cbuf,0x83); // SUB ESP,4
3901 emit_opcode(cbuf,0xEC);
3902 emit_d8(cbuf,0x04);
3903
3904 emit_opcode (cbuf, 0xF3 ); // MOVSS [ESP], src
3905 emit_opcode (cbuf, 0x0F );
3906 emit_opcode (cbuf, 0x11 );
3907 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false);
3908
3909 emit_opcode(cbuf,0xD9 ); // FLD_S [ESP]
3910 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
3911
3912 emit_opcode(cbuf,0x83); // ADD ESP,4
3913 emit_opcode(cbuf,0xC4);
3914 emit_d8(cbuf,0x04);
3915
3916 // CALL directly to the runtime
3917 cbuf.set_inst_mark();
3918 emit_opcode(cbuf,0xE8); // Call into runtime
3919 emit_d32_reloc(cbuf, (StubRoutines::d2l_wrapper() - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
3920 // Carry on here...
3921 %}
3922
3923 enc_class XD2L_encoding( regXD src ) %{
3924 // Allocate a word
3925 emit_opcode(cbuf,0x83); // SUB ESP,8
3926 emit_opcode(cbuf,0xEC);
3927 emit_d8(cbuf,0x08);
3928
3929 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], src
3930 emit_opcode (cbuf, 0x0F );
3931 emit_opcode (cbuf, 0x11 );
3932 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false);
3933
3934 emit_opcode(cbuf,0xDD ); // FLD_D [ESP]
3935 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
3936
3937 emit_opcode(cbuf,0xD9); // FLDCW trunc
3938 emit_opcode(cbuf,0x2D);
3939 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
3940
3941 // Encoding assumes a double has been pushed into FPR0.
3942 // Store down the double as a long, popping the FPU stack
3943 emit_opcode(cbuf,0xDF); // FISTP [ESP]
3944 emit_opcode(cbuf,0x3C);
3945 emit_d8(cbuf,0x24);
3946
3947 // Restore the rounding mode; mask the exception
3948 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode
3949 emit_opcode(cbuf,0x2D);
3950 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
3951 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
3952 : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
3953
3954 // Load the converted int; adjust CPU stack
3955 emit_opcode(cbuf,0x58); // POP EAX
3956
3957 emit_opcode(cbuf,0x5A); // POP EDX
3958
3959 emit_opcode(cbuf,0x81); // CMP EDX,imm
3960 emit_d8 (cbuf,0xFA); // rdx
3961 emit_d32 (cbuf,0x80000000); // 0x80000000
3962
3963 emit_opcode(cbuf,0x75); // JNE around_slow_call
3964 emit_d8 (cbuf,0x13+4); // Size of slow_call
3965
3966 emit_opcode(cbuf,0x85); // TEST EAX,EAX
3967 emit_opcode(cbuf,0xC0); // 2/rax,/rax,
3968
3969 emit_opcode(cbuf,0x75); // JNE around_slow_call
3970 emit_d8 (cbuf,0x13); // Size of slow_call
3971
3972 // Push src onto stack slow-path
3973 // Allocate a word
3974 emit_opcode(cbuf,0x83); // SUB ESP,8
3975 emit_opcode(cbuf,0xEC);
3976 emit_d8(cbuf,0x08);
3977
3978 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], src
3979 emit_opcode (cbuf, 0x0F );
3980 emit_opcode (cbuf, 0x11 );
3981 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false);
3982
3983 emit_opcode(cbuf,0xDD ); // FLD_D [ESP]
3984 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
3985
3986 emit_opcode(cbuf,0x83); // ADD ESP,8
3987 emit_opcode(cbuf,0xC4);
3988 emit_d8(cbuf,0x08);
3989
3990 // CALL directly to the runtime
3991 cbuf.set_inst_mark();
3992 emit_opcode(cbuf,0xE8); // Call into runtime
3993 emit_d32_reloc(cbuf, (StubRoutines::d2l_wrapper() - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
3994 // Carry on here...
3995 %}
3996
3997 enc_class D2X_encoding( regX dst, regD src ) %{
3998 // Allocate a word
3999 emit_opcode(cbuf,0x83); // SUB ESP,4
4000 emit_opcode(cbuf,0xEC);
4001 emit_d8(cbuf,0x04);
4002 int pop = 0x02;
4003 if ($src$$reg != FPR1L_enc) {
4004 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
4005 emit_d8( cbuf, 0xC0-1+$src$$reg );
4006 pop = 0x03;
4007 }
4008 store_to_stackslot( cbuf, 0xD9, pop, 0 ); // FST<P>_S [ESP]
4009
4010 emit_opcode (cbuf, 0xF3 ); // MOVSS dst(xmm), [ESP]
4011 emit_opcode (cbuf, 0x0F );
4012 emit_opcode (cbuf, 0x10 );
4013 encode_RegMem(cbuf, $dst$$reg, ESP_enc, 0x4, 0, 0, false);
4014
4015 emit_opcode(cbuf,0x83); // ADD ESP,4
4016 emit_opcode(cbuf,0xC4);
4017 emit_d8(cbuf,0x04);
4018 // Carry on here...
4019 %}
4020
4021 enc_class FX2I_encoding( regX src, eRegI dst ) %{
4022 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
4023
4024 // Compare the result to see if we need to go to the slow path
4025 emit_opcode(cbuf,0x81); // CMP dst,imm
4026 emit_rm (cbuf,0x3,0x7,$dst$$reg);
4027 emit_d32 (cbuf,0x80000000); // 0x80000000
4028
4029 emit_opcode(cbuf,0x75); // JNE around_slow_call
4030 emit_d8 (cbuf,0x13); // Size of slow_call
4031 // Store xmm to a temp memory
4032 // location and push it onto stack.
4033
4034 emit_opcode(cbuf,0x83); // SUB ESP,4
4035 emit_opcode(cbuf,0xEC);
4036 emit_d8(cbuf, $primary ? 0x8 : 0x4);
4037
4038 emit_opcode (cbuf, $primary ? 0xF2 : 0xF3 ); // MOVSS [ESP], xmm
4039 emit_opcode (cbuf, 0x0F );
4040 emit_opcode (cbuf, 0x11 );
4041 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false);
4042
4043 emit_opcode(cbuf, $primary ? 0xDD : 0xD9 ); // FLD [ESP]
4044 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
4045
4046 emit_opcode(cbuf,0x83); // ADD ESP,4
4047 emit_opcode(cbuf,0xC4);
4048 emit_d8(cbuf, $primary ? 0x8 : 0x4);
4049
4050 // CALL directly to the runtime
4051 cbuf.set_inst_mark();
4052 emit_opcode(cbuf,0xE8); // Call into runtime
4053 emit_d32_reloc(cbuf, (StubRoutines::d2i_wrapper() - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
4054
4055 // Carry on here...
4056 %}
4057
4058 enc_class X2D_encoding( regD dst, regX src ) %{
4059 // Allocate a word
4060 emit_opcode(cbuf,0x83); // SUB ESP,4
4061 emit_opcode(cbuf,0xEC);
4062 emit_d8(cbuf,0x04);
4063
4064 emit_opcode (cbuf, 0xF3 ); // MOVSS [ESP], xmm
4065 emit_opcode (cbuf, 0x0F );
4066 emit_opcode (cbuf, 0x11 );
4067 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false);
4068
4069 emit_opcode(cbuf,0xD9 ); // FLD_S [ESP]
4070 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
4071
4072 emit_opcode(cbuf,0x83); // ADD ESP,4
4073 emit_opcode(cbuf,0xC4);
4074 emit_d8(cbuf,0x04);
4075
4076 // Carry on here...
4077 %}
4078
4079 enc_class AbsXF_encoding(regX dst) %{
4080 address signmask_address=(address)float_signmask_pool;
4081 // andpd:\tANDPS $dst,[signconst]
4082 emit_opcode(cbuf, 0x0F);
4083 emit_opcode(cbuf, 0x54);
4084 emit_rm(cbuf, 0x0, $dst$$reg, 0x5);
4085 emit_d32(cbuf, (int)signmask_address);
4086 %}
4087
4088 enc_class AbsXD_encoding(regXD dst) %{
4089 address signmask_address=(address)double_signmask_pool;
4090 // andpd:\tANDPD $dst,[signconst]
4091 emit_opcode(cbuf, 0x66);
4092 emit_opcode(cbuf, 0x0F);
4093 emit_opcode(cbuf, 0x54);
4094 emit_rm(cbuf, 0x0, $dst$$reg, 0x5);
4095 emit_d32(cbuf, (int)signmask_address);
4096 %}
4097
4098 enc_class NegXF_encoding(regX dst) %{
4099 address signmask_address=(address)float_signflip_pool;
4100 // andpd:\tXORPS $dst,[signconst]
4101 emit_opcode(cbuf, 0x0F);
4102 emit_opcode(cbuf, 0x57);
4103 emit_rm(cbuf, 0x0, $dst$$reg, 0x5);
4104 emit_d32(cbuf, (int)signmask_address);
4105 %}
4106
4107 enc_class NegXD_encoding(regXD dst) %{
4108 address signmask_address=(address)double_signflip_pool;
4109 // andpd:\tXORPD $dst,[signconst]
4110 emit_opcode(cbuf, 0x66);
4111 emit_opcode(cbuf, 0x0F);
4112 emit_opcode(cbuf, 0x57);
4113 emit_rm(cbuf, 0x0, $dst$$reg, 0x5);
4114 emit_d32(cbuf, (int)signmask_address);
4115 %}
4116
4117 enc_class FMul_ST_reg( eRegF src1 ) %{
4118 // Operand was loaded from memory into fp ST (stack top)
4119 // FMUL ST,$src /* D8 C8+i */
4120 emit_opcode(cbuf, 0xD8);
4121 emit_opcode(cbuf, 0xC8 + $src1$$reg);
4122 %}
4123
4124 enc_class FAdd_ST_reg( eRegF src2 ) %{
4125 // FADDP ST,src2 /* D8 C0+i */
4126 emit_opcode(cbuf, 0xD8);
4127 emit_opcode(cbuf, 0xC0 + $src2$$reg);
4128 //could use FADDP src2,fpST /* DE C0+i */
4129 %}
4130
4131 enc_class FAddP_reg_ST( eRegF src2 ) %{
4132 // FADDP src2,ST /* DE C0+i */
4133 emit_opcode(cbuf, 0xDE);
4134 emit_opcode(cbuf, 0xC0 + $src2$$reg);
4135 %}
4136
4137 enc_class subF_divF_encode( eRegF src1, eRegF src2) %{
4138 // Operand has been loaded into fp ST (stack top)
4139 // FSUB ST,$src1
4140 emit_opcode(cbuf, 0xD8);
4141 emit_opcode(cbuf, 0xE0 + $src1$$reg);
4142
4143 // FDIV
4144 emit_opcode(cbuf, 0xD8);
4145 emit_opcode(cbuf, 0xF0 + $src2$$reg);
4146 %}
4147
4148 enc_class MulFAddF (eRegF src1, eRegF src2) %{
4149 // Operand was loaded from memory into fp ST (stack top)
4150 // FADD ST,$src /* D8 C0+i */
4151 emit_opcode(cbuf, 0xD8);
4152 emit_opcode(cbuf, 0xC0 + $src1$$reg);
4153
4154 // FMUL ST,src2 /* D8 C*+i */
4155 emit_opcode(cbuf, 0xD8);
4156 emit_opcode(cbuf, 0xC8 + $src2$$reg);
4157 %}
4158
4159
4160 enc_class MulFAddFreverse (eRegF src1, eRegF src2) %{
4161 // Operand was loaded from memory into fp ST (stack top)
4162 // FADD ST,$src /* D8 C0+i */
4163 emit_opcode(cbuf, 0xD8);
4164 emit_opcode(cbuf, 0xC0 + $src1$$reg);
4165
4166 // FMULP src2,ST /* DE C8+i */
4167 emit_opcode(cbuf, 0xDE);
4168 emit_opcode(cbuf, 0xC8 + $src2$$reg);
4169 %}
4170
4171 // Atomically load the volatile long
4172 enc_class enc_loadL_volatile( memory mem, stackSlotL dst ) %{
4173 emit_opcode(cbuf,0xDF);
4174 int rm_byte_opcode = 0x05;
4175 int base = $mem$$base;
4176 int index = $mem$$index;
4177 int scale = $mem$$scale;
4178 int displace = $mem$$disp;
4179 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
4180 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_is_oop);
4181 store_to_stackslot( cbuf, 0x0DF, 0x07, $dst$$disp );
4182 %}
4183
4184 enc_class enc_loadLX_volatile( memory mem, stackSlotL dst, regXD tmp ) %{
4185 { // Atomic long load
4186 // UseXmmLoadAndClearUpper ? movsd $tmp,$mem : movlpd $tmp,$mem
4187 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0xF2 : 0x66);
4188 emit_opcode(cbuf,0x0F);
4189 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0x10 : 0x12);
4190 int base = $mem$$base;
4191 int index = $mem$$index;
4192 int scale = $mem$$scale;
4193 int displace = $mem$$disp;
4194 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
4195 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop);
4196 }
4197 { // MOVSD $dst,$tmp ! atomic long store
4198 emit_opcode(cbuf,0xF2);
4199 emit_opcode(cbuf,0x0F);
4200 emit_opcode(cbuf,0x11);
4201 int base = $dst$$base;
4202 int index = $dst$$index;
4203 int scale = $dst$$scale;
4204 int displace = $dst$$disp;
4205 bool disp_is_oop = $dst->disp_is_oop(); // disp-as-oop when working with static globals
4206 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop);
4207 }
4208 %}
4209
4210 enc_class enc_loadLX_reg_volatile( memory mem, eRegL dst, regXD tmp ) %{
4211 { // Atomic long load
4212 // UseXmmLoadAndClearUpper ? movsd $tmp,$mem : movlpd $tmp,$mem
4213 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0xF2 : 0x66);
4214 emit_opcode(cbuf,0x0F);
4215 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0x10 : 0x12);
4216 int base = $mem$$base;
4217 int index = $mem$$index;
4218 int scale = $mem$$scale;
4219 int displace = $mem$$disp;
4220 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
4221 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop);
4222 }
4223 { // MOVD $dst.lo,$tmp
4224 emit_opcode(cbuf,0x66);
4225 emit_opcode(cbuf,0x0F);
4226 emit_opcode(cbuf,0x7E);
4227 emit_rm(cbuf, 0x3, $tmp$$reg, $dst$$reg);
4228 }
4229 { // PSRLQ $tmp,32
4230 emit_opcode(cbuf,0x66);
4231 emit_opcode(cbuf,0x0F);
4232 emit_opcode(cbuf,0x73);
4233 emit_rm(cbuf, 0x3, 0x02, $tmp$$reg);
4234 emit_d8(cbuf, 0x20);
4235 }
4236 { // MOVD $dst.hi,$tmp
4237 emit_opcode(cbuf,0x66);
4238 emit_opcode(cbuf,0x0F);
4239 emit_opcode(cbuf,0x7E);
4240 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg));
4241 }
4242 %}
4243
4244 // Volatile Store Long. Must be atomic, so move it into
4245 // the FP TOS and then do a 64-bit FIST. Has to probe the
4246 // target address before the store (for null-ptr checks)
4247 // so the memory operand is used twice in the encoding.
4248 enc_class enc_storeL_volatile( memory mem, stackSlotL src ) %{
4249 store_to_stackslot( cbuf, 0x0DF, 0x05, $src$$disp );
4250 cbuf.set_inst_mark(); // Mark start of FIST in case $mem has an oop
4251 emit_opcode(cbuf,0xDF);
4252 int rm_byte_opcode = 0x07;
4253 int base = $mem$$base;
4254 int index = $mem$$index;
4255 int scale = $mem$$scale;
4256 int displace = $mem$$disp;
4257 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
4258 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_is_oop);
4259 %}
4260
4261 enc_class enc_storeLX_volatile( memory mem, stackSlotL src, regXD tmp) %{
4262 { // Atomic long load
4263 // UseXmmLoadAndClearUpper ? movsd $tmp,[$src] : movlpd $tmp,[$src]
4264 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0xF2 : 0x66);
4265 emit_opcode(cbuf,0x0F);
4266 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0x10 : 0x12);
4267 int base = $src$$base;
4268 int index = $src$$index;
4269 int scale = $src$$scale;
4270 int displace = $src$$disp;
4271 bool disp_is_oop = $src->disp_is_oop(); // disp-as-oop when working with static globals
4272 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop);
4273 }
4274 cbuf.set_inst_mark(); // Mark start of MOVSD in case $mem has an oop
4275 { // MOVSD $mem,$tmp ! atomic long store
4276 emit_opcode(cbuf,0xF2);
4277 emit_opcode(cbuf,0x0F);
4278 emit_opcode(cbuf,0x11);
4279 int base = $mem$$base;
4280 int index = $mem$$index;
4281 int scale = $mem$$scale;
4282 int displace = $mem$$disp;
4283 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
4284 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop);
4285 }
4286 %}
4287
4288 enc_class enc_storeLX_reg_volatile( memory mem, eRegL src, regXD tmp, regXD tmp2) %{
4289 { // MOVD $tmp,$src.lo
4290 emit_opcode(cbuf,0x66);
4291 emit_opcode(cbuf,0x0F);
4292 emit_opcode(cbuf,0x6E);
4293 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg);
4294 }
4295 { // MOVD $tmp2,$src.hi
4296 emit_opcode(cbuf,0x66);
4297 emit_opcode(cbuf,0x0F);
4298 emit_opcode(cbuf,0x6E);
4299 emit_rm(cbuf, 0x3, $tmp2$$reg, HIGH_FROM_LOW($src$$reg));
4300 }
4301 { // PUNPCKLDQ $tmp,$tmp2
4302 emit_opcode(cbuf,0x66);
4303 emit_opcode(cbuf,0x0F);
4304 emit_opcode(cbuf,0x62);
4305 emit_rm(cbuf, 0x3, $tmp$$reg, $tmp2$$reg);
4306 }
4307 cbuf.set_inst_mark(); // Mark start of MOVSD in case $mem has an oop
4308 { // MOVSD $mem,$tmp ! atomic long store
4309 emit_opcode(cbuf,0xF2);
4310 emit_opcode(cbuf,0x0F);
4311 emit_opcode(cbuf,0x11);
4312 int base = $mem$$base;
4313 int index = $mem$$index;
4314 int scale = $mem$$scale;
4315 int displace = $mem$$disp;
4316 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
4317 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop);
4318 }
4319 %}
4320
4321 // Safepoint Poll. This polls the safepoint page, and causes an
4322 // exception if it is not readable. Unfortunately, it kills the condition code
4323 // in the process
4324 // We current use TESTL [spp],EDI
4325 // A better choice might be TESTB [spp + pagesize() - CacheLineSize()],0
4326
4327 enc_class Safepoint_Poll() %{
4328 cbuf.relocate(cbuf.inst_mark(), relocInfo::poll_type, 0);
4329 emit_opcode(cbuf,0x85);
4330 emit_rm (cbuf, 0x0, 0x7, 0x5);
4331 emit_d32(cbuf, (intptr_t)os::get_polling_page());
4332 %}
4333 %}
4334
4335
4336 //----------FRAME--------------------------------------------------------------
4337 // Definition of frame structure and management information.
4338 //
4339 // S T A C K L A Y O U T Allocators stack-slot number
4340 // | (to get allocators register number
4341 // G Owned by | | v add OptoReg::stack0())
4342 // r CALLER | |
4343 // o | +--------+ pad to even-align allocators stack-slot
4344 // w V | pad0 | numbers; owned by CALLER
4345 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
4346 // h ^ | in | 5
4347 // | | args | 4 Holes in incoming args owned by SELF
4348 // | | | | 3
4349 // | | +--------+
4350 // V | | old out| Empty on Intel, window on Sparc
4351 // | old |preserve| Must be even aligned.
4352 // | SP-+--------+----> Matcher::_old_SP, even aligned
4353 // | | in | 3 area for Intel ret address
4354 // Owned by |preserve| Empty on Sparc.
4355 // SELF +--------+
4356 // | | pad2 | 2 pad to align old SP
4357 // | +--------+ 1
4358 // | | locks | 0
4359 // | +--------+----> OptoReg::stack0(), even aligned
4360 // | | pad1 | 11 pad to align new SP
4361 // | +--------+
4362 // | | | 10
4363 // | | spills | 9 spills
4364 // V | | 8 (pad0 slot for callee)
4365 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
4366 // ^ | out | 7
4367 // | | args | 6 Holes in outgoing args owned by CALLEE
4368 // Owned by +--------+
4369 // CALLEE | new out| 6 Empty on Intel, window on Sparc
4370 // | new |preserve| Must be even-aligned.
4371 // | SP-+--------+----> Matcher::_new_SP, even aligned
4372 // | | |
4373 //
4374 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
4375 // known from SELF's arguments and the Java calling convention.
4376 // Region 6-7 is determined per call site.
4377 // Note 2: If the calling convention leaves holes in the incoming argument
4378 // area, those holes are owned by SELF. Holes in the outgoing area
4379 // are owned by the CALLEE. Holes should not be nessecary in the
4380 // incoming area, as the Java calling convention is completely under
4381 // the control of the AD file. Doubles can be sorted and packed to
4382 // avoid holes. Holes in the outgoing arguments may be nessecary for
4383 // varargs C calling conventions.
4384 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
4385 // even aligned with pad0 as needed.
4386 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
4387 // region 6-11 is even aligned; it may be padded out more so that
4388 // the region from SP to FP meets the minimum stack alignment.
4389
4390 frame %{
4391 // What direction does stack grow in (assumed to be same for C & Java)
4392 stack_direction(TOWARDS_LOW);
4393
4394 // These three registers define part of the calling convention
4395 // between compiled code and the interpreter.
4396 inline_cache_reg(EAX); // Inline Cache Register
4397 interpreter_method_oop_reg(EBX); // Method Oop Register when calling interpreter
4398
4399 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
4400 cisc_spilling_operand_name(indOffset32);
4401
4402 // Number of stack slots consumed by locking an object
4403 sync_stack_slots(1);
4404
4405 // Compiled code's Frame Pointer
4406 frame_pointer(ESP);
4407 // Interpreter stores its frame pointer in a register which is
4408 // stored to the stack by I2CAdaptors.
4409 // I2CAdaptors convert from interpreted java to compiled java.
4410 interpreter_frame_pointer(EBP);
4411
4412 // Stack alignment requirement
4413 // Alignment size in bytes (128-bit -> 16 bytes)
4414 stack_alignment(StackAlignmentInBytes);
4415
4416 // Number of stack slots between incoming argument block and the start of
4417 // a new frame. The PROLOG must add this many slots to the stack. The
4418 // EPILOG must remove this many slots. Intel needs one slot for
4419 // return address and one for rbp, (must save rbp)
4420 in_preserve_stack_slots(2+VerifyStackAtCalls);
4421
4422 // Number of outgoing stack slots killed above the out_preserve_stack_slots
4423 // for calls to C. Supports the var-args backing area for register parms.
4424 varargs_C_out_slots_killed(0);
4425
4426 // The after-PROLOG location of the return address. Location of
4427 // return address specifies a type (REG or STACK) and a number
4428 // representing the register number (i.e. - use a register name) or
4429 // stack slot.
4430 // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
4431 // Otherwise, it is above the locks and verification slot and alignment word
4432 return_addr(STACK - 1 +
4433 round_to(1+VerifyStackAtCalls+
4434 Compile::current()->fixed_slots(),
4435 (StackAlignmentInBytes/wordSize)));
4436
4437 // Body of function which returns an integer array locating
4438 // arguments either in registers or in stack slots. Passed an array
4439 // of ideal registers called "sig" and a "length" count. Stack-slot
4440 // offsets are based on outgoing arguments, i.e. a CALLER setting up
4441 // arguments for a CALLEE. Incoming stack arguments are
4442 // automatically biased by the preserve_stack_slots field above.
4443 calling_convention %{
4444 // No difference between ingoing/outgoing just pass false
4445 SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
4446 %}
4447
4448
4449 // Body of function which returns an integer array locating
4450 // arguments either in registers or in stack slots. Passed an array
4451 // of ideal registers called "sig" and a "length" count. Stack-slot
4452 // offsets are based on outgoing arguments, i.e. a CALLER setting up
4453 // arguments for a CALLEE. Incoming stack arguments are
4454 // automatically biased by the preserve_stack_slots field above.
4455 c_calling_convention %{
4456 // This is obviously always outgoing
4457 (void) SharedRuntime::c_calling_convention(sig_bt, regs, length);
4458 %}
4459
4460 // Location of C & interpreter return values
4461 c_return_value %{
4462 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
4463 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num };
4464 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num };
4465
4466 // in SSE2+ mode we want to keep the FPU stack clean so pretend
4467 // that C functions return float and double results in XMM0.
4468 if( ideal_reg == Op_RegD && UseSSE>=2 )
4469 return OptoRegPair(XMM0b_num,XMM0a_num);
4470 if( ideal_reg == Op_RegF && UseSSE>=2 )
4471 return OptoRegPair(OptoReg::Bad,XMM0a_num);
4472
4473 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]);
4474 %}
4475
4476 // Location of return values
4477 return_value %{
4478 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
4479 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num };
4480 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num };
4481 if( ideal_reg == Op_RegD && UseSSE>=2 )
4482 return OptoRegPair(XMM0b_num,XMM0a_num);
4483 if( ideal_reg == Op_RegF && UseSSE>=1 )
4484 return OptoRegPair(OptoReg::Bad,XMM0a_num);
4485 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]);
4486 %}
4487
4488 %}
4489
4490 //----------ATTRIBUTES---------------------------------------------------------
4491 //----------Operand Attributes-------------------------------------------------
4492 op_attrib op_cost(0); // Required cost attribute
4493
4494 //----------Instruction Attributes---------------------------------------------
4495 ins_attrib ins_cost(100); // Required cost attribute
4496 ins_attrib ins_size(8); // Required size attribute (in bits)
4497 ins_attrib ins_pc_relative(0); // Required PC Relative flag
4498 ins_attrib ins_short_branch(0); // Required flag: is this instruction a
4499 // non-matching short branch variant of some
4500 // long branch?
4501 ins_attrib ins_alignment(1); // Required alignment attribute (must be a power of 2)
4502 // specifies the alignment that some part of the instruction (not
4503 // necessarily the start) requires. If > 1, a compute_padding()
4504 // function must be provided for the instruction
4505
4506 //----------OPERANDS-----------------------------------------------------------
4507 // Operand definitions must precede instruction definitions for correct parsing
4508 // in the ADLC because operands constitute user defined types which are used in
4509 // instruction definitions.
4510
4511 //----------Simple Operands----------------------------------------------------
4512 // Immediate Operands
4513 // Integer Immediate
4514 operand immI() %{
4515 match(ConI);
4516
4517 op_cost(10);
4518 format %{ %}
4519 interface(CONST_INTER);
4520 %}
4521
4522 // Constant for test vs zero
4523 operand immI0() %{
4524 predicate(n->get_int() == 0);
4525 match(ConI);
4526
4527 op_cost(0);
4528 format %{ %}
4529 interface(CONST_INTER);
4530 %}
4531
4532 // Constant for increment
4533 operand immI1() %{
4534 predicate(n->get_int() == 1);
4535 match(ConI);
4536
4537 op_cost(0);
4538 format %{ %}
4539 interface(CONST_INTER);
4540 %}
4541
4542 // Constant for decrement
4543 operand immI_M1() %{
4544 predicate(n->get_int() == -1);
4545 match(ConI);
4546
4547 op_cost(0);
4548 format %{ %}
4549 interface(CONST_INTER);
4550 %}
4551
4552 // Valid scale values for addressing modes
4553 operand immI2() %{
4554 predicate(0 <= n->get_int() && (n->get_int() <= 3));
4555 match(ConI);
4556
4557 format %{ %}
4558 interface(CONST_INTER);
4559 %}
4560
4561 operand immI8() %{
4562 predicate((-128 <= n->get_int()) && (n->get_int() <= 127));
4563 match(ConI);
4564
4565 op_cost(5);
4566 format %{ %}
4567 interface(CONST_INTER);
4568 %}
4569
4570 operand immI16() %{
4571 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767));
4572 match(ConI);
4573
4574 op_cost(10);
4575 format %{ %}
4576 interface(CONST_INTER);
4577 %}
4578
4579 // Constant for long shifts
4580 operand immI_32() %{
4581 predicate( n->get_int() == 32 );
4582 match(ConI);
4583
4584 op_cost(0);
4585 format %{ %}
4586 interface(CONST_INTER);
4587 %}
4588
4589 operand immI_1_31() %{
4590 predicate( n->get_int() >= 1 && n->get_int() <= 31 );
4591 match(ConI);
4592
4593 op_cost(0);
4594 format %{ %}
4595 interface(CONST_INTER);
4596 %}
4597
4598 operand immI_32_63() %{
4599 predicate( n->get_int() >= 32 && n->get_int() <= 63 );
4600 match(ConI);
4601 op_cost(0);
4602
4603 format %{ %}
4604 interface(CONST_INTER);
4605 %}
4606
4607 operand immI_1() %{
4608 predicate( n->get_int() == 1 );
4609 match(ConI);
4610
4611 op_cost(0);
4612 format %{ %}
4613 interface(CONST_INTER);
4614 %}
4615
4616 operand immI_2() %{
4617 predicate( n->get_int() == 2 );
4618 match(ConI);
4619
4620 op_cost(0);
4621 format %{ %}
4622 interface(CONST_INTER);
4623 %}
4624
4625 operand immI_3() %{
4626 predicate( n->get_int() == 3 );
4627 match(ConI);
4628
4629 op_cost(0);
4630 format %{ %}
4631 interface(CONST_INTER);
4632 %}
4633
4634 // Pointer Immediate
4635 operand immP() %{
4636 match(ConP);
4637
4638 op_cost(10);
4639 format %{ %}
4640 interface(CONST_INTER);
4641 %}
4642
4643 // NULL Pointer Immediate
4644 operand immP0() %{
4645 predicate( n->get_ptr() == 0 );
4646 match(ConP);
4647 op_cost(0);
4648
4649 format %{ %}
4650 interface(CONST_INTER);
4651 %}
4652
4653 // Long Immediate
4654 operand immL() %{
4655 match(ConL);
4656
4657 op_cost(20);
4658 format %{ %}
4659 interface(CONST_INTER);
4660 %}
4661
4662 // Long Immediate zero
4663 operand immL0() %{
4664 predicate( n->get_long() == 0L );
4665 match(ConL);
4666 op_cost(0);
4667
4668 format %{ %}
4669 interface(CONST_INTER);
4670 %}
4671
4672 // Long Immediate zero
4673 operand immL_M1() %{
4674 predicate( n->get_long() == -1L );
4675 match(ConL);
4676 op_cost(0);
4677
4678 format %{ %}
4679 interface(CONST_INTER);
4680 %}
4681
4682 // Long immediate from 0 to 127.
4683 // Used for a shorter form of long mul by 10.
4684 operand immL_127() %{
4685 predicate((0 <= n->get_long()) && (n->get_long() <= 127));
4686 match(ConL);
4687 op_cost(0);
4688
4689 format %{ %}
4690 interface(CONST_INTER);
4691 %}
4692
4693 // Long Immediate: low 32-bit mask
4694 operand immL_32bits() %{
4695 predicate(n->get_long() == 0xFFFFFFFFL);
4696 match(ConL);
4697 op_cost(0);
4698
4699 format %{ %}
4700 interface(CONST_INTER);
4701 %}
4702
4703 // Long Immediate: low 32-bit mask
4704 operand immL32() %{
4705 predicate(n->get_long() == (int)(n->get_long()));
4706 match(ConL);
4707 op_cost(20);
4708
4709 format %{ %}
4710 interface(CONST_INTER);
4711 %}
4712
4713 //Double Immediate zero
4714 operand immD0() %{
4715 // Do additional (and counter-intuitive) test against NaN to work around VC++
4716 // bug that generates code such that NaNs compare equal to 0.0
4717 predicate( UseSSE<=1 && n->getd() == 0.0 && !g_isnan(n->getd()) );
4718 match(ConD);
4719
4720 op_cost(5);
4721 format %{ %}
4722 interface(CONST_INTER);
4723 %}
4724
4725 // Double Immediate
4726 operand immD1() %{
4727 predicate( UseSSE<=1 && n->getd() == 1.0 );
4728 match(ConD);
4729
4730 op_cost(5);
4731 format %{ %}
4732 interface(CONST_INTER);
4733 %}
4734
4735 // Double Immediate
4736 operand immD() %{
4737 predicate(UseSSE<=1);
4738 match(ConD);
4739
4740 op_cost(5);
4741 format %{ %}
4742 interface(CONST_INTER);
4743 %}
4744
4745 operand immXD() %{
4746 predicate(UseSSE>=2);
4747 match(ConD);
4748
4749 op_cost(5);
4750 format %{ %}
4751 interface(CONST_INTER);
4752 %}
4753
4754 // Double Immediate zero
4755 operand immXD0() %{
4756 // Do additional (and counter-intuitive) test against NaN to work around VC++
4757 // bug that generates code such that NaNs compare equal to 0.0 AND do not
4758 // compare equal to -0.0.
4759 predicate( UseSSE>=2 && jlong_cast(n->getd()) == 0 );
4760 match(ConD);
4761
4762 format %{ %}
4763 interface(CONST_INTER);
4764 %}
4765
4766 // Float Immediate zero
4767 operand immF0() %{
4768 predicate( UseSSE == 0 && n->getf() == 0.0 );
4769 match(ConF);
4770
4771 op_cost(5);
4772 format %{ %}
4773 interface(CONST_INTER);
4774 %}
4775
4776 // Float Immediate
4777 operand immF() %{
4778 predicate( UseSSE == 0 );
4779 match(ConF);
4780
4781 op_cost(5);
4782 format %{ %}
4783 interface(CONST_INTER);
4784 %}
4785
4786 // Float Immediate
4787 operand immXF() %{
4788 predicate(UseSSE >= 1);
4789 match(ConF);
4790
4791 op_cost(5);
4792 format %{ %}
4793 interface(CONST_INTER);
4794 %}
4795
4796 // Float Immediate zero. Zero and not -0.0
4797 operand immXF0() %{
4798 predicate( UseSSE >= 1 && jint_cast(n->getf()) == 0 );
4799 match(ConF);
4800
4801 op_cost(5);
4802 format %{ %}
4803 interface(CONST_INTER);
4804 %}
4805
4806 // Immediates for special shifts (sign extend)
4807
4808 // Constants for increment
4809 operand immI_16() %{
4810 predicate( n->get_int() == 16 );
4811 match(ConI);
4812
4813 format %{ %}
4814 interface(CONST_INTER);
4815 %}
4816
4817 operand immI_24() %{
4818 predicate( n->get_int() == 24 );
4819 match(ConI);
4820
4821 format %{ %}
4822 interface(CONST_INTER);
4823 %}
4824
4825 // Constant for byte-wide masking
4826 operand immI_255() %{
4827 predicate( n->get_int() == 255 );
4828 match(ConI);
4829
4830 format %{ %}
4831 interface(CONST_INTER);
4832 %}
4833
4834 // Constant for short-wide masking
4835 operand immI_65535() %{
4836 predicate(n->get_int() == 65535);
4837 match(ConI);
4838
4839 format %{ %}
4840 interface(CONST_INTER);
4841 %}
4842
4843 // Register Operands
4844 // Integer Register
4845 operand eRegI() %{
4846 constraint(ALLOC_IN_RC(e_reg));
4847 match(RegI);
4848 match(xRegI);
4849 match(eAXRegI);
4850 match(eBXRegI);
4851 match(eCXRegI);
4852 match(eDXRegI);
4853 match(eDIRegI);
4854 match(eSIRegI);
4855
4856 format %{ %}
4857 interface(REG_INTER);
4858 %}
4859
4860 // Subset of Integer Register
4861 operand xRegI(eRegI reg) %{
4862 constraint(ALLOC_IN_RC(x_reg));
4863 match(reg);
4864 match(eAXRegI);
4865 match(eBXRegI);
4866 match(eCXRegI);
4867 match(eDXRegI);
4868
4869 format %{ %}
4870 interface(REG_INTER);
4871 %}
4872
4873 // Special Registers
4874 operand eAXRegI(xRegI reg) %{
4875 constraint(ALLOC_IN_RC(eax_reg));
4876 match(reg);
4877 match(eRegI);
4878
4879 format %{ "EAX" %}
4880 interface(REG_INTER);
4881 %}
4882
4883 // Special Registers
4884 operand eBXRegI(xRegI reg) %{
4885 constraint(ALLOC_IN_RC(ebx_reg));
4886 match(reg);
4887 match(eRegI);
4888
4889 format %{ "EBX" %}
4890 interface(REG_INTER);
4891 %}
4892
4893 operand eCXRegI(xRegI reg) %{
4894 constraint(ALLOC_IN_RC(ecx_reg));
4895 match(reg);
4896 match(eRegI);
4897
4898 format %{ "ECX" %}
4899 interface(REG_INTER);
4900 %}
4901
4902 operand eDXRegI(xRegI reg) %{
4903 constraint(ALLOC_IN_RC(edx_reg));
4904 match(reg);
4905 match(eRegI);
4906
4907 format %{ "EDX" %}
4908 interface(REG_INTER);
4909 %}
4910
4911 operand eDIRegI(xRegI reg) %{
4912 constraint(ALLOC_IN_RC(edi_reg));
4913 match(reg);
4914 match(eRegI);
4915
4916 format %{ "EDI" %}
4917 interface(REG_INTER);
4918 %}
4919
4920 operand naxRegI() %{
4921 constraint(ALLOC_IN_RC(nax_reg));
4922 match(RegI);
4923 match(eCXRegI);
4924 match(eDXRegI);
4925 match(eSIRegI);
4926 match(eDIRegI);
4927
4928 format %{ %}
4929 interface(REG_INTER);
4930 %}
4931
4932 operand nadxRegI() %{
4933 constraint(ALLOC_IN_RC(nadx_reg));
4934 match(RegI);
4935 match(eBXRegI);
4936 match(eCXRegI);
4937 match(eSIRegI);
4938 match(eDIRegI);
4939
4940 format %{ %}
4941 interface(REG_INTER);
4942 %}
4943
4944 operand ncxRegI() %{
4945 constraint(ALLOC_IN_RC(ncx_reg));
4946 match(RegI);
4947 match(eAXRegI);
4948 match(eDXRegI);
4949 match(eSIRegI);
4950 match(eDIRegI);
4951
4952 format %{ %}
4953 interface(REG_INTER);
4954 %}
4955
4956 // // This operand was used by cmpFastUnlock, but conflicted with 'object' reg
4957 // //
4958 operand eSIRegI(xRegI reg) %{
4959 constraint(ALLOC_IN_RC(esi_reg));
4960 match(reg);
4961 match(eRegI);
4962
4963 format %{ "ESI" %}
4964 interface(REG_INTER);
4965 %}
4966
4967 // Pointer Register
4968 operand anyRegP() %{
4969 constraint(ALLOC_IN_RC(any_reg));
4970 match(RegP);
4971 match(eAXRegP);
4972 match(eBXRegP);
4973 match(eCXRegP);
4974 match(eDIRegP);
4975 match(eRegP);
4976
4977 format %{ %}
4978 interface(REG_INTER);
4979 %}
4980
4981 operand eRegP() %{
4982 constraint(ALLOC_IN_RC(e_reg));
4983 match(RegP);
4984 match(eAXRegP);
4985 match(eBXRegP);
4986 match(eCXRegP);
4987 match(eDIRegP);
4988
4989 format %{ %}
4990 interface(REG_INTER);
4991 %}
4992
4993 // On windows95, EBP is not safe to use for implicit null tests.
4994 operand eRegP_no_EBP() %{
4995 constraint(ALLOC_IN_RC(e_reg_no_rbp));
4996 match(RegP);
4997 match(eAXRegP);
4998 match(eBXRegP);
4999 match(eCXRegP);
5000 match(eDIRegP);
5001
5002 op_cost(100);
5003 format %{ %}
5004 interface(REG_INTER);
5005 %}
5006
5007 operand naxRegP() %{
5008 constraint(ALLOC_IN_RC(nax_reg));
5009 match(RegP);
5010 match(eBXRegP);
5011 match(eDXRegP);
5012 match(eCXRegP);
5013 match(eSIRegP);
5014 match(eDIRegP);
5015
5016 format %{ %}
5017 interface(REG_INTER);
5018 %}
5019
5020 operand nabxRegP() %{
5021 constraint(ALLOC_IN_RC(nabx_reg));
5022 match(RegP);
5023 match(eCXRegP);
5024 match(eDXRegP);
5025 match(eSIRegP);
5026 match(eDIRegP);
5027
5028 format %{ %}
5029 interface(REG_INTER);
5030 %}
5031
5032 operand pRegP() %{
5033 constraint(ALLOC_IN_RC(p_reg));
5034 match(RegP);
5035 match(eBXRegP);
5036 match(eDXRegP);
5037 match(eSIRegP);
5038 match(eDIRegP);
5039
5040 format %{ %}
5041 interface(REG_INTER);
5042 %}
5043
5044 // Special Registers
5045 // Return a pointer value
5046 operand eAXRegP(eRegP reg) %{
5047 constraint(ALLOC_IN_RC(eax_reg));
5048 match(reg);
5049 format %{ "EAX" %}
5050 interface(REG_INTER);
5051 %}
5052
5053 // Used in AtomicAdd
5054 operand eBXRegP(eRegP reg) %{
5055 constraint(ALLOC_IN_RC(ebx_reg));
5056 match(reg);
5057 format %{ "EBX" %}
5058 interface(REG_INTER);
5059 %}
5060
5061 // Tail-call (interprocedural jump) to interpreter
5062 operand eCXRegP(eRegP reg) %{
5063 constraint(ALLOC_IN_RC(ecx_reg));
5064 match(reg);
5065 format %{ "ECX" %}
5066 interface(REG_INTER);
5067 %}
5068
5069 operand eSIRegP(eRegP reg) %{
5070 constraint(ALLOC_IN_RC(esi_reg));
5071 match(reg);
5072 format %{ "ESI" %}
5073 interface(REG_INTER);
5074 %}
5075
5076 // Used in rep stosw
5077 operand eDIRegP(eRegP reg) %{
5078 constraint(ALLOC_IN_RC(edi_reg));
5079 match(reg);
5080 format %{ "EDI" %}
5081 interface(REG_INTER);
5082 %}
5083
5084 operand eBPRegP() %{
5085 constraint(ALLOC_IN_RC(ebp_reg));
5086 match(RegP);
5087 format %{ "EBP" %}
5088 interface(REG_INTER);
5089 %}
5090
5091 operand eRegL() %{
5092 constraint(ALLOC_IN_RC(long_reg));
5093 match(RegL);
5094 match(eADXRegL);
5095
5096 format %{ %}
5097 interface(REG_INTER);
5098 %}
5099
5100 operand eADXRegL( eRegL reg ) %{
5101 constraint(ALLOC_IN_RC(eadx_reg));
5102 match(reg);
5103
5104 format %{ "EDX:EAX" %}
5105 interface(REG_INTER);
5106 %}
5107
5108 operand eBCXRegL( eRegL reg ) %{
5109 constraint(ALLOC_IN_RC(ebcx_reg));
5110 match(reg);
5111
5112 format %{ "EBX:ECX" %}
5113 interface(REG_INTER);
5114 %}
5115
5116 // Special case for integer high multiply
5117 operand eADXRegL_low_only() %{
5118 constraint(ALLOC_IN_RC(eadx_reg));
5119 match(RegL);
5120
5121 format %{ "EAX" %}
5122 interface(REG_INTER);
5123 %}
5124
5125 // Flags register, used as output of compare instructions
5126 operand eFlagsReg() %{
5127 constraint(ALLOC_IN_RC(int_flags));
5128 match(RegFlags);
5129
5130 format %{ "EFLAGS" %}
5131 interface(REG_INTER);
5132 %}
5133
5134 // Flags register, used as output of FLOATING POINT compare instructions
5135 operand eFlagsRegU() %{
5136 constraint(ALLOC_IN_RC(int_flags));
5137 match(RegFlags);
5138
5139 format %{ "EFLAGS_U" %}
5140 interface(REG_INTER);
5141 %}
5142
5143 operand eFlagsRegUCF() %{
5144 constraint(ALLOC_IN_RC(int_flags));
5145 match(RegFlags);
5146 predicate(false);
5147
5148 format %{ "EFLAGS_U_CF" %}
5149 interface(REG_INTER);
5150 %}
5151
5152 // Condition Code Register used by long compare
5153 operand flagsReg_long_LTGE() %{
5154 constraint(ALLOC_IN_RC(int_flags));
5155 match(RegFlags);
5156 format %{ "FLAGS_LTGE" %}
5157 interface(REG_INTER);
5158 %}
5159 operand flagsReg_long_EQNE() %{
5160 constraint(ALLOC_IN_RC(int_flags));
5161 match(RegFlags);
5162 format %{ "FLAGS_EQNE" %}
5163 interface(REG_INTER);
5164 %}
5165 operand flagsReg_long_LEGT() %{
5166 constraint(ALLOC_IN_RC(int_flags));
5167 match(RegFlags);
5168 format %{ "FLAGS_LEGT" %}
5169 interface(REG_INTER);
5170 %}
5171
5172 // Float register operands
5173 operand regD() %{
5174 predicate( UseSSE < 2 );
5175 constraint(ALLOC_IN_RC(dbl_reg));
5176 match(RegD);
5177 match(regDPR1);
5178 match(regDPR2);
5179 format %{ %}
5180 interface(REG_INTER);
5181 %}
5182
5183 operand regDPR1(regD reg) %{
5184 predicate( UseSSE < 2 );
5185 constraint(ALLOC_IN_RC(dbl_reg0));
5186 match(reg);
5187 format %{ "FPR1" %}
5188 interface(REG_INTER);
5189 %}
5190
5191 operand regDPR2(regD reg) %{
5192 predicate( UseSSE < 2 );
5193 constraint(ALLOC_IN_RC(dbl_reg1));
5194 match(reg);
5195 format %{ "FPR2" %}
5196 interface(REG_INTER);
5197 %}
5198
5199 operand regnotDPR1(regD reg) %{
5200 predicate( UseSSE < 2 );
5201 constraint(ALLOC_IN_RC(dbl_notreg0));
5202 match(reg);
5203 format %{ %}
5204 interface(REG_INTER);
5205 %}
5206
5207 // XMM Double register operands
5208 operand regXD() %{
5209 predicate( UseSSE>=2 );
5210 constraint(ALLOC_IN_RC(xdb_reg));
5211 match(RegD);
5212 match(regXD6);
5213 match(regXD7);
5214 format %{ %}
5215 interface(REG_INTER);
5216 %}
5217
5218 // XMM6 double register operands
5219 operand regXD6(regXD reg) %{
5220 predicate( UseSSE>=2 );
5221 constraint(ALLOC_IN_RC(xdb_reg6));
5222 match(reg);
5223 format %{ "XMM6" %}
5224 interface(REG_INTER);
5225 %}
5226
5227 // XMM7 double register operands
5228 operand regXD7(regXD reg) %{
5229 predicate( UseSSE>=2 );
5230 constraint(ALLOC_IN_RC(xdb_reg7));
5231 match(reg);
5232 format %{ "XMM7" %}
5233 interface(REG_INTER);
5234 %}
5235
5236 // Float register operands
5237 operand regF() %{
5238 predicate( UseSSE < 2 );
5239 constraint(ALLOC_IN_RC(flt_reg));
5240 match(RegF);
5241 match(regFPR1);
5242 format %{ %}
5243 interface(REG_INTER);
5244 %}
5245
5246 // Float register operands
5247 operand regFPR1(regF reg) %{
5248 predicate( UseSSE < 2 );
5249 constraint(ALLOC_IN_RC(flt_reg0));
5250 match(reg);
5251 format %{ "FPR1" %}
5252 interface(REG_INTER);
5253 %}
5254
5255 // XMM register operands
5256 operand regX() %{
5257 predicate( UseSSE>=1 );
5258 constraint(ALLOC_IN_RC(xmm_reg));
5259 match(RegF);
5260 format %{ %}
5261 interface(REG_INTER);
5262 %}
5263
5264
5265 //----------Memory Operands----------------------------------------------------
5266 // Direct Memory Operand
5267 operand direct(immP addr) %{
5268 match(addr);
5269
5270 format %{ "[$addr]" %}
5271 interface(MEMORY_INTER) %{
5272 base(0xFFFFFFFF);
5273 index(0x4);
5274 scale(0x0);
5275 disp($addr);
5276 %}
5277 %}
5278
5279 // Indirect Memory Operand
5280 operand indirect(eRegP reg) %{
5281 constraint(ALLOC_IN_RC(e_reg));
5282 match(reg);
5283
5284 format %{ "[$reg]" %}
5285 interface(MEMORY_INTER) %{
5286 base($reg);
5287 index(0x4);
5288 scale(0x0);
5289 disp(0x0);
5290 %}
5291 %}
5292
5293 // Indirect Memory Plus Short Offset Operand
5294 operand indOffset8(eRegP reg, immI8 off) %{
5295 match(AddP reg off);
5296
5297 format %{ "[$reg + $off]" %}
5298 interface(MEMORY_INTER) %{
5299 base($reg);
5300 index(0x4);
5301 scale(0x0);
5302 disp($off);
5303 %}
5304 %}
5305
5306 // Indirect Memory Plus Long Offset Operand
5307 operand indOffset32(eRegP reg, immI off) %{
5308 match(AddP reg off);
5309
5310 format %{ "[$reg + $off]" %}
5311 interface(MEMORY_INTER) %{
5312 base($reg);
5313 index(0x4);
5314 scale(0x0);
5315 disp($off);
5316 %}
5317 %}
5318
5319 // Indirect Memory Plus Long Offset Operand
5320 operand indOffset32X(eRegI reg, immP off) %{
5321 match(AddP off reg);
5322
5323 format %{ "[$reg + $off]" %}
5324 interface(MEMORY_INTER) %{
5325 base($reg);
5326 index(0x4);
5327 scale(0x0);
5328 disp($off);
5329 %}
5330 %}
5331
5332 // Indirect Memory Plus Index Register Plus Offset Operand
5333 operand indIndexOffset(eRegP reg, eRegI ireg, immI off) %{
5334 match(AddP (AddP reg ireg) off);
5335
5336 op_cost(10);
5337 format %{"[$reg + $off + $ireg]" %}
5338 interface(MEMORY_INTER) %{
5339 base($reg);
5340 index($ireg);
5341 scale(0x0);
5342 disp($off);
5343 %}
5344 %}
5345
5346 // Indirect Memory Plus Index Register Plus Offset Operand
5347 operand indIndex(eRegP reg, eRegI ireg) %{
5348 match(AddP reg ireg);
5349
5350 op_cost(10);
5351 format %{"[$reg + $ireg]" %}
5352 interface(MEMORY_INTER) %{
5353 base($reg);
5354 index($ireg);
5355 scale(0x0);
5356 disp(0x0);
5357 %}
5358 %}
5359
5360 // // -------------------------------------------------------------------------
5361 // // 486 architecture doesn't support "scale * index + offset" with out a base
5362 // // -------------------------------------------------------------------------
5363 // // Scaled Memory Operands
5364 // // Indirect Memory Times Scale Plus Offset Operand
5365 // operand indScaleOffset(immP off, eRegI ireg, immI2 scale) %{
5366 // match(AddP off (LShiftI ireg scale));
5367 //
5368 // op_cost(10);
5369 // format %{"[$off + $ireg << $scale]" %}
5370 // interface(MEMORY_INTER) %{
5371 // base(0x4);
5372 // index($ireg);
5373 // scale($scale);
5374 // disp($off);
5375 // %}
5376 // %}
5377
5378 // Indirect Memory Times Scale Plus Index Register
5379 operand indIndexScale(eRegP reg, eRegI ireg, immI2 scale) %{
5380 match(AddP reg (LShiftI ireg scale));
5381
5382 op_cost(10);
5383 format %{"[$reg + $ireg << $scale]" %}
5384 interface(MEMORY_INTER) %{
5385 base($reg);
5386 index($ireg);
5387 scale($scale);
5388 disp(0x0);
5389 %}
5390 %}
5391
5392 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
5393 operand indIndexScaleOffset(eRegP reg, immI off, eRegI ireg, immI2 scale) %{
5394 match(AddP (AddP reg (LShiftI ireg scale)) off);
5395
5396 op_cost(10);
5397 format %{"[$reg + $off + $ireg << $scale]" %}
5398 interface(MEMORY_INTER) %{
5399 base($reg);
5400 index($ireg);
5401 scale($scale);
5402 disp($off);
5403 %}
5404 %}
5405
5406 //----------Load Long Memory Operands------------------------------------------
5407 // The load-long idiom will use it's address expression again after loading
5408 // the first word of the long. If the load-long destination overlaps with
5409 // registers used in the addressing expression, the 2nd half will be loaded
5410 // from a clobbered address. Fix this by requiring that load-long use
5411 // address registers that do not overlap with the load-long target.
5412
5413 // load-long support
5414 operand load_long_RegP() %{
5415 constraint(ALLOC_IN_RC(esi_reg));
5416 match(RegP);
5417 match(eSIRegP);
5418 op_cost(100);
5419 format %{ %}
5420 interface(REG_INTER);
5421 %}
5422
5423 // Indirect Memory Operand Long
5424 operand load_long_indirect(load_long_RegP reg) %{
5425 constraint(ALLOC_IN_RC(esi_reg));
5426 match(reg);
5427
5428 format %{ "[$reg]" %}
5429 interface(MEMORY_INTER) %{
5430 base($reg);
5431 index(0x4);
5432 scale(0x0);
5433 disp(0x0);
5434 %}
5435 %}
5436
5437 // Indirect Memory Plus Long Offset Operand
5438 operand load_long_indOffset32(load_long_RegP reg, immI off) %{
5439 match(AddP reg off);
5440
5441 format %{ "[$reg + $off]" %}
5442 interface(MEMORY_INTER) %{
5443 base($reg);
5444 index(0x4);
5445 scale(0x0);
5446 disp($off);
5447 %}
5448 %}
5449
5450 opclass load_long_memory(load_long_indirect, load_long_indOffset32);
5451
5452
5453 //----------Special Memory Operands--------------------------------------------
5454 // Stack Slot Operand - This operand is used for loading and storing temporary
5455 // values on the stack where a match requires a value to
5456 // flow through memory.
5457 operand stackSlotP(sRegP reg) %{
5458 constraint(ALLOC_IN_RC(stack_slots));
5459 // No match rule because this operand is only generated in matching
5460 format %{ "[$reg]" %}
5461 interface(MEMORY_INTER) %{
5462 base(0x4); // ESP
5463 index(0x4); // No Index
5464 scale(0x0); // No Scale
5465 disp($reg); // Stack Offset
5466 %}
5467 %}
5468
5469 operand stackSlotI(sRegI reg) %{
5470 constraint(ALLOC_IN_RC(stack_slots));
5471 // No match rule because this operand is only generated in matching
5472 format %{ "[$reg]" %}
5473 interface(MEMORY_INTER) %{
5474 base(0x4); // ESP
5475 index(0x4); // No Index
5476 scale(0x0); // No Scale
5477 disp($reg); // Stack Offset
5478 %}
5479 %}
5480
5481 operand stackSlotF(sRegF reg) %{
5482 constraint(ALLOC_IN_RC(stack_slots));
5483 // No match rule because this operand is only generated in matching
5484 format %{ "[$reg]" %}
5485 interface(MEMORY_INTER) %{
5486 base(0x4); // ESP
5487 index(0x4); // No Index
5488 scale(0x0); // No Scale
5489 disp($reg); // Stack Offset
5490 %}
5491 %}
5492
5493 operand stackSlotD(sRegD reg) %{
5494 constraint(ALLOC_IN_RC(stack_slots));
5495 // No match rule because this operand is only generated in matching
5496 format %{ "[$reg]" %}
5497 interface(MEMORY_INTER) %{
5498 base(0x4); // ESP
5499 index(0x4); // No Index
5500 scale(0x0); // No Scale
5501 disp($reg); // Stack Offset
5502 %}
5503 %}
5504
5505 operand stackSlotL(sRegL reg) %{
5506 constraint(ALLOC_IN_RC(stack_slots));
5507 // No match rule because this operand is only generated in matching
5508 format %{ "[$reg]" %}
5509 interface(MEMORY_INTER) %{
5510 base(0x4); // ESP
5511 index(0x4); // No Index
5512 scale(0x0); // No Scale
5513 disp($reg); // Stack Offset
5514 %}
5515 %}
5516
5517 //----------Memory Operands - Win95 Implicit Null Variants----------------
5518 // Indirect Memory Operand
5519 operand indirect_win95_safe(eRegP_no_EBP reg)
5520 %{
5521 constraint(ALLOC_IN_RC(e_reg));
5522 match(reg);
5523
5524 op_cost(100);
5525 format %{ "[$reg]" %}
5526 interface(MEMORY_INTER) %{
5527 base($reg);
5528 index(0x4);
5529 scale(0x0);
5530 disp(0x0);
5531 %}
5532 %}
5533
5534 // Indirect Memory Plus Short Offset Operand
5535 operand indOffset8_win95_safe(eRegP_no_EBP reg, immI8 off)
5536 %{
5537 match(AddP reg off);
5538
5539 op_cost(100);
5540 format %{ "[$reg + $off]" %}
5541 interface(MEMORY_INTER) %{
5542 base($reg);
5543 index(0x4);
5544 scale(0x0);
5545 disp($off);
5546 %}
5547 %}
5548
5549 // Indirect Memory Plus Long Offset Operand
5550 operand indOffset32_win95_safe(eRegP_no_EBP reg, immI off)
5551 %{
5552 match(AddP reg off);
5553
5554 op_cost(100);
5555 format %{ "[$reg + $off]" %}
5556 interface(MEMORY_INTER) %{
5557 base($reg);
5558 index(0x4);
5559 scale(0x0);
5560 disp($off);
5561 %}
5562 %}
5563
5564 // Indirect Memory Plus Index Register Plus Offset Operand
5565 operand indIndexOffset_win95_safe(eRegP_no_EBP reg, eRegI ireg, immI off)
5566 %{
5567 match(AddP (AddP reg ireg) off);
5568
5569 op_cost(100);
5570 format %{"[$reg + $off + $ireg]" %}
5571 interface(MEMORY_INTER) %{
5572 base($reg);
5573 index($ireg);
5574 scale(0x0);
5575 disp($off);
5576 %}
5577 %}
5578
5579 // Indirect Memory Times Scale Plus Index Register
5580 operand indIndexScale_win95_safe(eRegP_no_EBP reg, eRegI ireg, immI2 scale)
5581 %{
5582 match(AddP reg (LShiftI ireg scale));
5583
5584 op_cost(100);
5585 format %{"[$reg + $ireg << $scale]" %}
5586 interface(MEMORY_INTER) %{
5587 base($reg);
5588 index($ireg);
5589 scale($scale);
5590 disp(0x0);
5591 %}
5592 %}
5593
5594 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
5595 operand indIndexScaleOffset_win95_safe(eRegP_no_EBP reg, immI off, eRegI ireg, immI2 scale)
5596 %{
5597 match(AddP (AddP reg (LShiftI ireg scale)) off);
5598
5599 op_cost(100);
5600 format %{"[$reg + $off + $ireg << $scale]" %}
5601 interface(MEMORY_INTER) %{
5602 base($reg);
5603 index($ireg);
5604 scale($scale);
5605 disp($off);
5606 %}
5607 %}
5608
5609 //----------Conditional Branch Operands----------------------------------------
5610 // Comparison Op - This is the operation of the comparison, and is limited to
5611 // the following set of codes:
5612 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
5613 //
5614 // Other attributes of the comparison, such as unsignedness, are specified
5615 // by the comparison instruction that sets a condition code flags register.
5616 // That result is represented by a flags operand whose subtype is appropriate
5617 // to the unsignedness (etc.) of the comparison.
5618 //
5619 // Later, the instruction which matches both the Comparison Op (a Bool) and
5620 // the flags (produced by the Cmp) specifies the coding of the comparison op
5621 // by matching a specific subtype of Bool operand below, such as cmpOpU.
5622
5623 // Comparision Code
5624 operand cmpOp() %{
5625 match(Bool);
5626
5627 format %{ "" %}
5628 interface(COND_INTER) %{
5629 equal(0x4, "e");
5630 not_equal(0x5, "ne");
5631 less(0xC, "l");
5632 greater_equal(0xD, "ge");
5633 less_equal(0xE, "le");
5634 greater(0xF, "g");
5635 %}
5636 %}
5637
5638 // Comparison Code, unsigned compare. Used by FP also, with
5639 // C2 (unordered) turned into GT or LT already. The other bits
5640 // C0 and C3 are turned into Carry & Zero flags.
5641 operand cmpOpU() %{
5642 match(Bool);
5643
5644 format %{ "" %}
5645 interface(COND_INTER) %{
5646 equal(0x4, "e");
5647 not_equal(0x5, "ne");
5648 less(0x2, "b");
5649 greater_equal(0x3, "nb");
5650 less_equal(0x6, "be");
5651 greater(0x7, "nbe");
5652 %}
5653 %}
5654
5655 // Floating comparisons that don't require any fixup for the unordered case
5656 operand cmpOpUCF() %{
5657 match(Bool);
5658 predicate(n->as_Bool()->_test._test == BoolTest::lt ||
5659 n->as_Bool()->_test._test == BoolTest::ge ||
5660 n->as_Bool()->_test._test == BoolTest::le ||
5661 n->as_Bool()->_test._test == BoolTest::gt);
5662 format %{ "" %}
5663 interface(COND_INTER) %{
5664 equal(0x4, "e");
5665 not_equal(0x5, "ne");
5666 less(0x2, "b");
5667 greater_equal(0x3, "nb");
5668 less_equal(0x6, "be");
5669 greater(0x7, "nbe");
5670 %}
5671 %}
5672
5673
5674 // Floating comparisons that can be fixed up with extra conditional jumps
5675 operand cmpOpUCF2() %{
5676 match(Bool);
5677 predicate(n->as_Bool()->_test._test == BoolTest::ne ||
5678 n->as_Bool()->_test._test == BoolTest::eq);
5679 format %{ "" %}
5680 interface(COND_INTER) %{
5681 equal(0x4, "e");
5682 not_equal(0x5, "ne");
5683 less(0x2, "b");
5684 greater_equal(0x3, "nb");
5685 less_equal(0x6, "be");
5686 greater(0x7, "nbe");
5687 %}
5688 %}
5689
5690 // Comparison Code for FP conditional move
5691 operand cmpOp_fcmov() %{
5692 match(Bool);
5693
5694 format %{ "" %}
5695 interface(COND_INTER) %{
5696 equal (0x0C8);
5697 not_equal (0x1C8);
5698 less (0x0C0);
5699 greater_equal(0x1C0);
5700 less_equal (0x0D0);
5701 greater (0x1D0);
5702 %}
5703 %}
5704
5705 // Comparision Code used in long compares
5706 operand cmpOp_commute() %{
5707 match(Bool);
5708
5709 format %{ "" %}
5710 interface(COND_INTER) %{
5711 equal(0x4, "e");
5712 not_equal(0x5, "ne");
5713 less(0xF, "g");
5714 greater_equal(0xE, "le");
5715 less_equal(0xD, "ge");
5716 greater(0xC, "l");
5717 %}
5718 %}
5719
5720 //----------OPERAND CLASSES----------------------------------------------------
5721 // Operand Classes are groups of operands that are used as to simplify
5722 // instruction definitions by not requiring the AD writer to specify separate
5723 // instructions for every form of operand when the instruction accepts
5724 // multiple operand types with the same basic encoding and format. The classic
5725 // case of this is memory operands.
5726
5727 opclass memory(direct, indirect, indOffset8, indOffset32, indOffset32X, indIndexOffset,
5728 indIndex, indIndexScale, indIndexScaleOffset);
5729
5730 // Long memory operations are encoded in 2 instructions and a +4 offset.
5731 // This means some kind of offset is always required and you cannot use
5732 // an oop as the offset (done when working on static globals).
5733 opclass long_memory(direct, indirect, indOffset8, indOffset32, indIndexOffset,
5734 indIndex, indIndexScale, indIndexScaleOffset);
5735
5736
5737 //----------PIPELINE-----------------------------------------------------------
5738 // Rules which define the behavior of the target architectures pipeline.
5739 pipeline %{
5740
5741 //----------ATTRIBUTES---------------------------------------------------------
5742 attributes %{
5743 variable_size_instructions; // Fixed size instructions
5744 max_instructions_per_bundle = 3; // Up to 3 instructions per bundle
5745 instruction_unit_size = 1; // An instruction is 1 bytes long
5746 instruction_fetch_unit_size = 16; // The processor fetches one line
5747 instruction_fetch_units = 1; // of 16 bytes
5748
5749 // List of nop instructions
5750 nops( MachNop );
5751 %}
5752
5753 //----------RESOURCES----------------------------------------------------------
5754 // Resources are the functional units available to the machine
5755
5756 // Generic P2/P3 pipeline
5757 // 3 decoders, only D0 handles big operands; a "bundle" is the limit of
5758 // 3 instructions decoded per cycle.
5759 // 2 load/store ops per cycle, 1 branch, 1 FPU,
5760 // 2 ALU op, only ALU0 handles mul/div instructions.
5761 resources( D0, D1, D2, DECODE = D0 | D1 | D2,
5762 MS0, MS1, MEM = MS0 | MS1,
5763 BR, FPU,
5764 ALU0, ALU1, ALU = ALU0 | ALU1 );
5765
5766 //----------PIPELINE DESCRIPTION-----------------------------------------------
5767 // Pipeline Description specifies the stages in the machine's pipeline
5768
5769 // Generic P2/P3 pipeline
5770 pipe_desc(S0, S1, S2, S3, S4, S5);
5771
5772 //----------PIPELINE CLASSES---------------------------------------------------
5773 // Pipeline Classes describe the stages in which input and output are
5774 // referenced by the hardware pipeline.
5775
5776 // Naming convention: ialu or fpu
5777 // Then: _reg
5778 // Then: _reg if there is a 2nd register
5779 // Then: _long if it's a pair of instructions implementing a long
5780 // Then: _fat if it requires the big decoder
5781 // Or: _mem if it requires the big decoder and a memory unit.
5782
5783 // Integer ALU reg operation
5784 pipe_class ialu_reg(eRegI dst) %{
5785 single_instruction;
5786 dst : S4(write);
5787 dst : S3(read);
5788 DECODE : S0; // any decoder
5789 ALU : S3; // any alu
5790 %}
5791
5792 // Long ALU reg operation
5793 pipe_class ialu_reg_long(eRegL dst) %{
5794 instruction_count(2);
5795 dst : S4(write);
5796 dst : S3(read);
5797 DECODE : S0(2); // any 2 decoders
5798 ALU : S3(2); // both alus
5799 %}
5800
5801 // Integer ALU reg operation using big decoder
5802 pipe_class ialu_reg_fat(eRegI dst) %{
5803 single_instruction;
5804 dst : S4(write);
5805 dst : S3(read);
5806 D0 : S0; // big decoder only
5807 ALU : S3; // any alu
5808 %}
5809
5810 // Long ALU reg operation using big decoder
5811 pipe_class ialu_reg_long_fat(eRegL dst) %{
5812 instruction_count(2);
5813 dst : S4(write);
5814 dst : S3(read);
5815 D0 : S0(2); // big decoder only; twice
5816 ALU : S3(2); // any 2 alus
5817 %}
5818
5819 // Integer ALU reg-reg operation
5820 pipe_class ialu_reg_reg(eRegI dst, eRegI src) %{
5821 single_instruction;
5822 dst : S4(write);
5823 src : S3(read);
5824 DECODE : S0; // any decoder
5825 ALU : S3; // any alu
5826 %}
5827
5828 // Long ALU reg-reg operation
5829 pipe_class ialu_reg_reg_long(eRegL dst, eRegL src) %{
5830 instruction_count(2);
5831 dst : S4(write);
5832 src : S3(read);
5833 DECODE : S0(2); // any 2 decoders
5834 ALU : S3(2); // both alus
5835 %}
5836
5837 // Integer ALU reg-reg operation
5838 pipe_class ialu_reg_reg_fat(eRegI dst, memory src) %{
5839 single_instruction;
5840 dst : S4(write);
5841 src : S3(read);
5842 D0 : S0; // big decoder only
5843 ALU : S3; // any alu
5844 %}
5845
5846 // Long ALU reg-reg operation
5847 pipe_class ialu_reg_reg_long_fat(eRegL dst, eRegL src) %{
5848 instruction_count(2);
5849 dst : S4(write);
5850 src : S3(read);
5851 D0 : S0(2); // big decoder only; twice
5852 ALU : S3(2); // both alus
5853 %}
5854
5855 // Integer ALU reg-mem operation
5856 pipe_class ialu_reg_mem(eRegI dst, memory mem) %{
5857 single_instruction;
5858 dst : S5(write);
5859 mem : S3(read);
5860 D0 : S0; // big decoder only
5861 ALU : S4; // any alu
5862 MEM : S3; // any mem
5863 %}
5864
5865 // Long ALU reg-mem operation
5866 pipe_class ialu_reg_long_mem(eRegL dst, load_long_memory mem) %{
5867 instruction_count(2);
5868 dst : S5(write);
5869 mem : S3(read);
5870 D0 : S0(2); // big decoder only; twice
5871 ALU : S4(2); // any 2 alus
5872 MEM : S3(2); // both mems
5873 %}
5874
5875 // Integer mem operation (prefetch)
5876 pipe_class ialu_mem(memory mem)
5877 %{
5878 single_instruction;
5879 mem : S3(read);
5880 D0 : S0; // big decoder only
5881 MEM : S3; // any mem
5882 %}
5883
5884 // Integer Store to Memory
5885 pipe_class ialu_mem_reg(memory mem, eRegI src) %{
5886 single_instruction;
5887 mem : S3(read);
5888 src : S5(read);
5889 D0 : S0; // big decoder only
5890 ALU : S4; // any alu
5891 MEM : S3;
5892 %}
5893
5894 // Long Store to Memory
5895 pipe_class ialu_mem_long_reg(memory mem, eRegL src) %{
5896 instruction_count(2);
5897 mem : S3(read);
5898 src : S5(read);
5899 D0 : S0(2); // big decoder only; twice
5900 ALU : S4(2); // any 2 alus
5901 MEM : S3(2); // Both mems
5902 %}
5903
5904 // Integer Store to Memory
5905 pipe_class ialu_mem_imm(memory mem) %{
5906 single_instruction;
5907 mem : S3(read);
5908 D0 : S0; // big decoder only
5909 ALU : S4; // any alu
5910 MEM : S3;
5911 %}
5912
5913 // Integer ALU0 reg-reg operation
5914 pipe_class ialu_reg_reg_alu0(eRegI dst, eRegI src) %{
5915 single_instruction;
5916 dst : S4(write);
5917 src : S3(read);
5918 D0 : S0; // Big decoder only
5919 ALU0 : S3; // only alu0
5920 %}
5921
5922 // Integer ALU0 reg-mem operation
5923 pipe_class ialu_reg_mem_alu0(eRegI dst, memory mem) %{
5924 single_instruction;
5925 dst : S5(write);
5926 mem : S3(read);
5927 D0 : S0; // big decoder only
5928 ALU0 : S4; // ALU0 only
5929 MEM : S3; // any mem
5930 %}
5931
5932 // Integer ALU reg-reg operation
5933 pipe_class ialu_cr_reg_reg(eFlagsReg cr, eRegI src1, eRegI src2) %{
5934 single_instruction;
5935 cr : S4(write);
5936 src1 : S3(read);
5937 src2 : S3(read);
5938 DECODE : S0; // any decoder
5939 ALU : S3; // any alu
5940 %}
5941
5942 // Integer ALU reg-imm operation
5943 pipe_class ialu_cr_reg_imm(eFlagsReg cr, eRegI src1) %{
5944 single_instruction;
5945 cr : S4(write);
5946 src1 : S3(read);
5947 DECODE : S0; // any decoder
5948 ALU : S3; // any alu
5949 %}
5950
5951 // Integer ALU reg-mem operation
5952 pipe_class ialu_cr_reg_mem(eFlagsReg cr, eRegI src1, memory src2) %{
5953 single_instruction;
5954 cr : S4(write);
5955 src1 : S3(read);
5956 src2 : S3(read);
5957 D0 : S0; // big decoder only
5958 ALU : S4; // any alu
5959 MEM : S3;
5960 %}
5961
5962 // Conditional move reg-reg
5963 pipe_class pipe_cmplt( eRegI p, eRegI q, eRegI y ) %{
5964 instruction_count(4);
5965 y : S4(read);
5966 q : S3(read);
5967 p : S3(read);
5968 DECODE : S0(4); // any decoder
5969 %}
5970
5971 // Conditional move reg-reg
5972 pipe_class pipe_cmov_reg( eRegI dst, eRegI src, eFlagsReg cr ) %{
5973 single_instruction;
5974 dst : S4(write);
5975 src : S3(read);
5976 cr : S3(read);
5977 DECODE : S0; // any decoder
5978 %}
5979
5980 // Conditional move reg-mem
5981 pipe_class pipe_cmov_mem( eFlagsReg cr, eRegI dst, memory src) %{
5982 single_instruction;
5983 dst : S4(write);
5984 src : S3(read);
5985 cr : S3(read);
5986 DECODE : S0; // any decoder
5987 MEM : S3;
5988 %}
5989
5990 // Conditional move reg-reg long
5991 pipe_class pipe_cmov_reg_long( eFlagsReg cr, eRegL dst, eRegL src) %{
5992 single_instruction;
5993 dst : S4(write);
5994 src : S3(read);
5995 cr : S3(read);
5996 DECODE : S0(2); // any 2 decoders
5997 %}
5998
5999 // Conditional move double reg-reg
6000 pipe_class pipe_cmovD_reg( eFlagsReg cr, regDPR1 dst, regD src) %{
6001 single_instruction;
6002 dst : S4(write);
6003 src : S3(read);
6004 cr : S3(read);
6005 DECODE : S0; // any decoder
6006 %}
6007
6008 // Float reg-reg operation
6009 pipe_class fpu_reg(regD dst) %{
6010 instruction_count(2);
6011 dst : S3(read);
6012 DECODE : S0(2); // any 2 decoders
6013 FPU : S3;
6014 %}
6015
6016 // Float reg-reg operation
6017 pipe_class fpu_reg_reg(regD dst, regD src) %{
6018 instruction_count(2);
6019 dst : S4(write);
6020 src : S3(read);
6021 DECODE : S0(2); // any 2 decoders
6022 FPU : S3;
6023 %}
6024
6025 // Float reg-reg operation
6026 pipe_class fpu_reg_reg_reg(regD dst, regD src1, regD src2) %{
6027 instruction_count(3);
6028 dst : S4(write);
6029 src1 : S3(read);
6030 src2 : S3(read);
6031 DECODE : S0(3); // any 3 decoders
6032 FPU : S3(2);
6033 %}
6034
6035 // Float reg-reg operation
6036 pipe_class fpu_reg_reg_reg_reg(regD dst, regD src1, regD src2, regD src3) %{
6037 instruction_count(4);
6038 dst : S4(write);
6039 src1 : S3(read);
6040 src2 : S3(read);
6041 src3 : S3(read);
6042 DECODE : S0(4); // any 3 decoders
6043 FPU : S3(2);
6044 %}
6045
6046 // Float reg-reg operation
6047 pipe_class fpu_reg_mem_reg_reg(regD dst, memory src1, regD src2, regD src3) %{
6048 instruction_count(4);
6049 dst : S4(write);
6050 src1 : S3(read);
6051 src2 : S3(read);
6052 src3 : S3(read);
6053 DECODE : S1(3); // any 3 decoders
6054 D0 : S0; // Big decoder only
6055 FPU : S3(2);
6056 MEM : S3;
6057 %}
6058
6059 // Float reg-mem operation
6060 pipe_class fpu_reg_mem(regD dst, memory mem) %{
6061 instruction_count(2);
6062 dst : S5(write);
6063 mem : S3(read);
6064 D0 : S0; // big decoder only
6065 DECODE : S1; // any decoder for FPU POP
6066 FPU : S4;
6067 MEM : S3; // any mem
6068 %}
6069
6070 // Float reg-mem operation
6071 pipe_class fpu_reg_reg_mem(regD dst, regD src1, memory mem) %{
6072 instruction_count(3);
6073 dst : S5(write);
6074 src1 : S3(read);
6075 mem : S3(read);
6076 D0 : S0; // big decoder only
6077 DECODE : S1(2); // any decoder for FPU POP
6078 FPU : S4;
6079 MEM : S3; // any mem
6080 %}
6081
6082 // Float mem-reg operation
6083 pipe_class fpu_mem_reg(memory mem, regD src) %{
6084 instruction_count(2);
6085 src : S5(read);
6086 mem : S3(read);
6087 DECODE : S0; // any decoder for FPU PUSH
6088 D0 : S1; // big decoder only
6089 FPU : S4;
6090 MEM : S3; // any mem
6091 %}
6092
6093 pipe_class fpu_mem_reg_reg(memory mem, regD src1, regD src2) %{
6094 instruction_count(3);
6095 src1 : S3(read);
6096 src2 : S3(read);
6097 mem : S3(read);
6098 DECODE : S0(2); // any decoder for FPU PUSH
6099 D0 : S1; // big decoder only
6100 FPU : S4;
6101 MEM : S3; // any mem
6102 %}
6103
6104 pipe_class fpu_mem_reg_mem(memory mem, regD src1, memory src2) %{
6105 instruction_count(3);
6106 src1 : S3(read);
6107 src2 : S3(read);
6108 mem : S4(read);
6109 DECODE : S0; // any decoder for FPU PUSH
6110 D0 : S0(2); // big decoder only
6111 FPU : S4;
6112 MEM : S3(2); // any mem
6113 %}
6114
6115 pipe_class fpu_mem_mem(memory dst, memory src1) %{
6116 instruction_count(2);
6117 src1 : S3(read);
6118 dst : S4(read);
6119 D0 : S0(2); // big decoder only
6120 MEM : S3(2); // any mem
6121 %}
6122
6123 pipe_class fpu_mem_mem_mem(memory dst, memory src1, memory src2) %{
6124 instruction_count(3);
6125 src1 : S3(read);
6126 src2 : S3(read);
6127 dst : S4(read);
6128 D0 : S0(3); // big decoder only
6129 FPU : S4;
6130 MEM : S3(3); // any mem
6131 %}
6132
6133 pipe_class fpu_mem_reg_con(memory mem, regD src1) %{
6134 instruction_count(3);
6135 src1 : S4(read);
6136 mem : S4(read);
6137 DECODE : S0; // any decoder for FPU PUSH
6138 D0 : S0(2); // big decoder only
6139 FPU : S4;
6140 MEM : S3(2); // any mem
6141 %}
6142
6143 // Float load constant
6144 pipe_class fpu_reg_con(regD dst) %{
6145 instruction_count(2);
6146 dst : S5(write);
6147 D0 : S0; // big decoder only for the load
6148 DECODE : S1; // any decoder for FPU POP
6149 FPU : S4;
6150 MEM : S3; // any mem
6151 %}
6152
6153 // Float load constant
6154 pipe_class fpu_reg_reg_con(regD dst, regD src) %{
6155 instruction_count(3);
6156 dst : S5(write);
6157 src : S3(read);
6158 D0 : S0; // big decoder only for the load
6159 DECODE : S1(2); // any decoder for FPU POP
6160 FPU : S4;
6161 MEM : S3; // any mem
6162 %}
6163
6164 // UnConditional branch
6165 pipe_class pipe_jmp( label labl ) %{
6166 single_instruction;
6167 BR : S3;
6168 %}
6169
6170 // Conditional branch
6171 pipe_class pipe_jcc( cmpOp cmp, eFlagsReg cr, label labl ) %{
6172 single_instruction;
6173 cr : S1(read);
6174 BR : S3;
6175 %}
6176
6177 // Allocation idiom
6178 pipe_class pipe_cmpxchg( eRegP dst, eRegP heap_ptr ) %{
6179 instruction_count(1); force_serialization;
6180 fixed_latency(6);
6181 heap_ptr : S3(read);
6182 DECODE : S0(3);
6183 D0 : S2;
6184 MEM : S3;
6185 ALU : S3(2);
6186 dst : S5(write);
6187 BR : S5;
6188 %}
6189
6190 // Generic big/slow expanded idiom
6191 pipe_class pipe_slow( ) %{
6192 instruction_count(10); multiple_bundles; force_serialization;
6193 fixed_latency(100);
6194 D0 : S0(2);
6195 MEM : S3(2);
6196 %}
6197
6198 // The real do-nothing guy
6199 pipe_class empty( ) %{
6200 instruction_count(0);
6201 %}
6202
6203 // Define the class for the Nop node
6204 define %{
6205 MachNop = empty;
6206 %}
6207
6208 %}
6209
6210 //----------INSTRUCTIONS-------------------------------------------------------
6211 //
6212 // match -- States which machine-independent subtree may be replaced
6213 // by this instruction.
6214 // ins_cost -- The estimated cost of this instruction is used by instruction
6215 // selection to identify a minimum cost tree of machine
6216 // instructions that matches a tree of machine-independent
6217 // instructions.
6218 // format -- A string providing the disassembly for this instruction.
6219 // The value of an instruction's operand may be inserted
6220 // by referring to it with a '$' prefix.
6221 // opcode -- Three instruction opcodes may be provided. These are referred
6222 // to within an encode class as $primary, $secondary, and $tertiary
6223 // respectively. The primary opcode is commonly used to
6224 // indicate the type of machine instruction, while secondary
6225 // and tertiary are often used for prefix options or addressing
6226 // modes.
6227 // ins_encode -- A list of encode classes with parameters. The encode class
6228 // name must have been defined in an 'enc_class' specification
6229 // in the encode section of the architecture description.
6230
6231 //----------BSWAP-Instruction--------------------------------------------------
6232 instruct bytes_reverse_int(eRegI dst) %{
6233 match(Set dst (ReverseBytesI dst));
6234
6235 format %{ "BSWAP $dst" %}
6236 opcode(0x0F, 0xC8);
6237 ins_encode( OpcP, OpcSReg(dst) );
6238 ins_pipe( ialu_reg );
6239 %}
6240
6241 instruct bytes_reverse_long(eRegL dst) %{
6242 match(Set dst (ReverseBytesL dst));
6243
6244 format %{ "BSWAP $dst.lo\n\t"
6245 "BSWAP $dst.hi\n\t"
6246 "XCHG $dst.lo $dst.hi" %}
6247
6248 ins_cost(125);
6249 ins_encode( bswap_long_bytes(dst) );
6250 ins_pipe( ialu_reg_reg);
6251 %}
6252
6253
6254 //---------- Zeros Count Instructions ------------------------------------------
6255
6256 instruct countLeadingZerosI(eRegI dst, eRegI src, eFlagsReg cr) %{
6257 predicate(UseCountLeadingZerosInstruction);
6258 match(Set dst (CountLeadingZerosI src));
6259 effect(KILL cr);
6260
6261 format %{ "LZCNT $dst, $src\t# count leading zeros (int)" %}
6262 ins_encode %{
6263 __ lzcntl($dst$$Register, $src$$Register);
6264 %}
6265 ins_pipe(ialu_reg);
6266 %}
6267
6268 instruct countLeadingZerosI_bsr(eRegI dst, eRegI src, eFlagsReg cr) %{
6269 predicate(!UseCountLeadingZerosInstruction);
6270 match(Set dst (CountLeadingZerosI src));
6271 effect(KILL cr);
6272
6273 format %{ "BSR $dst, $src\t# count leading zeros (int)\n\t"
6274 "JNZ skip\n\t"
6275 "MOV $dst, -1\n"
6276 "skip:\n\t"
6277 "NEG $dst\n\t"
6278 "ADD $dst, 31" %}
6279 ins_encode %{
6280 Register Rdst = $dst$$Register;
6281 Register Rsrc = $src$$Register;
6282 Label skip;
6283 __ bsrl(Rdst, Rsrc);
6284 __ jccb(Assembler::notZero, skip);
6285 __ movl(Rdst, -1);
6286 __ bind(skip);
6287 __ negl(Rdst);
6288 __ addl(Rdst, BitsPerInt - 1);
6289 %}
6290 ins_pipe(ialu_reg);
6291 %}
6292
6293 instruct countLeadingZerosL(eRegI dst, eRegL src, eFlagsReg cr) %{
6294 predicate(UseCountLeadingZerosInstruction);
6295 match(Set dst (CountLeadingZerosL src));
6296 effect(TEMP dst, KILL cr);
6297
6298 format %{ "LZCNT $dst, $src.hi\t# count leading zeros (long)\n\t"
6299 "JNC done\n\t"
6300 "LZCNT $dst, $src.lo\n\t"
6301 "ADD $dst, 32\n"
6302 "done:" %}
6303 ins_encode %{
6304 Register Rdst = $dst$$Register;
6305 Register Rsrc = $src$$Register;
6306 Label done;
6307 __ lzcntl(Rdst, HIGH_FROM_LOW(Rsrc));
6308 __ jccb(Assembler::carryClear, done);
6309 __ lzcntl(Rdst, Rsrc);
6310 __ addl(Rdst, BitsPerInt);
6311 __ bind(done);
6312 %}
6313 ins_pipe(ialu_reg);
6314 %}
6315
6316 instruct countLeadingZerosL_bsr(eRegI dst, eRegL src, eFlagsReg cr) %{
6317 predicate(!UseCountLeadingZerosInstruction);
6318 match(Set dst (CountLeadingZerosL src));
6319 effect(TEMP dst, KILL cr);
6320
6321 format %{ "BSR $dst, $src.hi\t# count leading zeros (long)\n\t"
6322 "JZ msw_is_zero\n\t"
6323 "ADD $dst, 32\n\t"
6324 "JMP not_zero\n"
6325 "msw_is_zero:\n\t"
6326 "BSR $dst, $src.lo\n\t"
6327 "JNZ not_zero\n\t"
6328 "MOV $dst, -1\n"
6329 "not_zero:\n\t"
6330 "NEG $dst\n\t"
6331 "ADD $dst, 63\n" %}
6332 ins_encode %{
6333 Register Rdst = $dst$$Register;
6334 Register Rsrc = $src$$Register;
6335 Label msw_is_zero;
6336 Label not_zero;
6337 __ bsrl(Rdst, HIGH_FROM_LOW(Rsrc));
6338 __ jccb(Assembler::zero, msw_is_zero);
6339 __ addl(Rdst, BitsPerInt);
6340 __ jmpb(not_zero);
6341 __ bind(msw_is_zero);
6342 __ bsrl(Rdst, Rsrc);
6343 __ jccb(Assembler::notZero, not_zero);
6344 __ movl(Rdst, -1);
6345 __ bind(not_zero);
6346 __ negl(Rdst);
6347 __ addl(Rdst, BitsPerLong - 1);
6348 %}
6349 ins_pipe(ialu_reg);
6350 %}
6351
6352 instruct countTrailingZerosI(eRegI dst, eRegI src, eFlagsReg cr) %{
6353 match(Set dst (CountTrailingZerosI src));
6354 effect(KILL cr);
6355
6356 format %{ "BSF $dst, $src\t# count trailing zeros (int)\n\t"
6357 "JNZ done\n\t"
6358 "MOV $dst, 32\n"
6359 "done:" %}
6360 ins_encode %{
6361 Register Rdst = $dst$$Register;
6362 Label done;
6363 __ bsfl(Rdst, $src$$Register);
6364 __ jccb(Assembler::notZero, done);
6365 __ movl(Rdst, BitsPerInt);
6366 __ bind(done);
6367 %}
6368 ins_pipe(ialu_reg);
6369 %}
6370
6371 instruct countTrailingZerosL(eRegI dst, eRegL src, eFlagsReg cr) %{
6372 match(Set dst (CountTrailingZerosL src));
6373 effect(TEMP dst, KILL cr);
6374
6375 format %{ "BSF $dst, $src.lo\t# count trailing zeros (long)\n\t"
6376 "JNZ done\n\t"
6377 "BSF $dst, $src.hi\n\t"
6378 "JNZ msw_not_zero\n\t"
6379 "MOV $dst, 32\n"
6380 "msw_not_zero:\n\t"
6381 "ADD $dst, 32\n"
6382 "done:" %}
6383 ins_encode %{
6384 Register Rdst = $dst$$Register;
6385 Register Rsrc = $src$$Register;
6386 Label msw_not_zero;
6387 Label done;
6388 __ bsfl(Rdst, Rsrc);
6389 __ jccb(Assembler::notZero, done);
6390 __ bsfl(Rdst, HIGH_FROM_LOW(Rsrc));
6391 __ jccb(Assembler::notZero, msw_not_zero);
6392 __ movl(Rdst, BitsPerInt);
6393 __ bind(msw_not_zero);
6394 __ addl(Rdst, BitsPerInt);
6395 __ bind(done);
6396 %}
6397 ins_pipe(ialu_reg);
6398 %}
6399
6400
6401 //---------- Population Count Instructions -------------------------------------
6402
6403 instruct popCountI(eRegI dst, eRegI src) %{
6404 predicate(UsePopCountInstruction);
6405 match(Set dst (PopCountI src));
6406
6407 format %{ "POPCNT $dst, $src" %}
6408 ins_encode %{
6409 __ popcntl($dst$$Register, $src$$Register);
6410 %}
6411 ins_pipe(ialu_reg);
6412 %}
6413
6414 instruct popCountI_mem(eRegI dst, memory mem) %{
6415 predicate(UsePopCountInstruction);
6416 match(Set dst (PopCountI (LoadI mem)));
6417
6418 format %{ "POPCNT $dst, $mem" %}
6419 ins_encode %{
6420 __ popcntl($dst$$Register, $mem$$Address);
6421 %}
6422 ins_pipe(ialu_reg);
6423 %}
6424
6425 // Note: Long.bitCount(long) returns an int.
6426 instruct popCountL(eRegI dst, eRegL src, eRegI tmp, eFlagsReg cr) %{
6427 predicate(UsePopCountInstruction);
6428 match(Set dst (PopCountL src));
6429 effect(KILL cr, TEMP tmp, TEMP dst);
6430
6431 format %{ "POPCNT $dst, $src.lo\n\t"
6432 "POPCNT $tmp, $src.hi\n\t"
6433 "ADD $dst, $tmp" %}
6434 ins_encode %{
6435 __ popcntl($dst$$Register, $src$$Register);
6436 __ popcntl($tmp$$Register, HIGH_FROM_LOW($src$$Register));
6437 __ addl($dst$$Register, $tmp$$Register);
6438 %}
6439 ins_pipe(ialu_reg);
6440 %}
6441
6442 // Note: Long.bitCount(long) returns an int.
6443 instruct popCountL_mem(eRegI dst, memory mem, eRegI tmp, eFlagsReg cr) %{
6444 predicate(UsePopCountInstruction);
6445 match(Set dst (PopCountL (LoadL mem)));
6446 effect(KILL cr, TEMP tmp, TEMP dst);
6447
6448 format %{ "POPCNT $dst, $mem\n\t"
6449 "POPCNT $tmp, $mem+4\n\t"
6450 "ADD $dst, $tmp" %}
6451 ins_encode %{
6452 //__ popcntl($dst$$Register, $mem$$Address$$first);
6453 //__ popcntl($tmp$$Register, $mem$$Address$$second);
6454 __ popcntl($dst$$Register, Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp, false));
6455 __ popcntl($tmp$$Register, Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp + 4, false));
6456 __ addl($dst$$Register, $tmp$$Register);
6457 %}
6458 ins_pipe(ialu_reg);
6459 %}
6460
6461
6462 //----------Load/Store/Move Instructions---------------------------------------
6463 //----------Load Instructions--------------------------------------------------
6464 // Load Byte (8bit signed)
6465 instruct loadB(xRegI dst, memory mem) %{
6466 match(Set dst (LoadB mem));
6467
6468 ins_cost(125);
6469 format %{ "MOVSX8 $dst,$mem\t# byte" %}
6470
6471 ins_encode %{
6472 __ movsbl($dst$$Register, $mem$$Address);
6473 %}
6474
6475 ins_pipe(ialu_reg_mem);
6476 %}
6477
6478 // Load Byte (8bit signed) into Long Register
6479 instruct loadB2L(eRegL dst, memory mem, eFlagsReg cr) %{
6480 match(Set dst (ConvI2L (LoadB mem)));
6481 effect(KILL cr);
6482
6483 ins_cost(375);
6484 format %{ "MOVSX8 $dst.lo,$mem\t# byte -> long\n\t"
6485 "MOV $dst.hi,$dst.lo\n\t"
6486 "SAR $dst.hi,7" %}
6487
6488 ins_encode %{
6489 __ movsbl($dst$$Register, $mem$$Address);
6490 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
6491 __ sarl(HIGH_FROM_LOW($dst$$Register), 7); // 24+1 MSB are already signed extended.
6492 %}
6493
6494 ins_pipe(ialu_reg_mem);
6495 %}
6496
6497 // Load Unsigned Byte (8bit UNsigned)
6498 instruct loadUB(xRegI dst, memory mem) %{
6499 match(Set dst (LoadUB mem));
6500
6501 ins_cost(125);
6502 format %{ "MOVZX8 $dst,$mem\t# ubyte -> int" %}
6503
6504 ins_encode %{
6505 __ movzbl($dst$$Register, $mem$$Address);
6506 %}
6507
6508 ins_pipe(ialu_reg_mem);
6509 %}
6510
6511 // Load Unsigned Byte (8 bit UNsigned) into Long Register
6512 instruct loadUB2L(eRegL dst, memory mem, eFlagsReg cr) %{
6513 match(Set dst (ConvI2L (LoadUB mem)));
6514 effect(KILL cr);
6515
6516 ins_cost(250);
6517 format %{ "MOVZX8 $dst.lo,$mem\t# ubyte -> long\n\t"
6518 "XOR $dst.hi,$dst.hi" %}
6519
6520 ins_encode %{
6521 Register Rdst = $dst$$Register;
6522 __ movzbl(Rdst, $mem$$Address);
6523 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6524 %}
6525
6526 ins_pipe(ialu_reg_mem);
6527 %}
6528
6529 // Load Unsigned Byte (8 bit UNsigned) with mask into Long Register
6530 instruct loadUB2L_immI8(eRegL dst, memory mem, immI8 mask, eFlagsReg cr) %{
6531 match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
6532 effect(KILL cr);
6533
6534 format %{ "MOVZX8 $dst.lo,$mem\t# ubyte & 8-bit mask -> long\n\t"
6535 "XOR $dst.hi,$dst.hi\n\t"
6536 "AND $dst.lo,$mask" %}
6537 ins_encode %{
6538 Register Rdst = $dst$$Register;
6539 __ movzbl(Rdst, $mem$$Address);
6540 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6541 __ andl(Rdst, $mask$$constant);
6542 %}
6543 ins_pipe(ialu_reg_mem);
6544 %}
6545
6546 // Load Short (16bit signed)
6547 instruct loadS(eRegI dst, memory mem) %{
6548 match(Set dst (LoadS mem));
6549
6550 ins_cost(125);
6551 format %{ "MOVSX $dst,$mem\t# short" %}
6552
6553 ins_encode %{
6554 __ movswl($dst$$Register, $mem$$Address);
6555 %}
6556
6557 ins_pipe(ialu_reg_mem);
6558 %}
6559
6560 // Load Short (16 bit signed) to Byte (8 bit signed)
6561 instruct loadS2B(eRegI dst, memory mem, immI_24 twentyfour) %{
6562 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
6563
6564 ins_cost(125);
6565 format %{ "MOVSX $dst, $mem\t# short -> byte" %}
6566 ins_encode %{
6567 __ movsbl($dst$$Register, $mem$$Address);
6568 %}
6569 ins_pipe(ialu_reg_mem);
6570 %}
6571
6572 // Load Short (16bit signed) into Long Register
6573 instruct loadS2L(eRegL dst, memory mem, eFlagsReg cr) %{
6574 match(Set dst (ConvI2L (LoadS mem)));
6575 effect(KILL cr);
6576
6577 ins_cost(375);
6578 format %{ "MOVSX $dst.lo,$mem\t# short -> long\n\t"
6579 "MOV $dst.hi,$dst.lo\n\t"
6580 "SAR $dst.hi,15" %}
6581
6582 ins_encode %{
6583 __ movswl($dst$$Register, $mem$$Address);
6584 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
6585 __ sarl(HIGH_FROM_LOW($dst$$Register), 15); // 16+1 MSB are already signed extended.
6586 %}
6587
6588 ins_pipe(ialu_reg_mem);
6589 %}
6590
6591 // Load Unsigned Short/Char (16bit unsigned)
6592 instruct loadUS(eRegI dst, memory mem) %{
6593 match(Set dst (LoadUS mem));
6594
6595 ins_cost(125);
6596 format %{ "MOVZX $dst,$mem\t# ushort/char -> int" %}
6597
6598 ins_encode %{
6599 __ movzwl($dst$$Register, $mem$$Address);
6600 %}
6601
6602 ins_pipe(ialu_reg_mem);
6603 %}
6604
6605 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
6606 instruct loadUS2B(eRegI dst, memory mem, immI_24 twentyfour) %{
6607 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
6608
6609 ins_cost(125);
6610 format %{ "MOVSX $dst, $mem\t# ushort -> byte" %}
6611 ins_encode %{
6612 __ movsbl($dst$$Register, $mem$$Address);
6613 %}
6614 ins_pipe(ialu_reg_mem);
6615 %}
6616
6617 // Load Unsigned Short/Char (16 bit UNsigned) into Long Register
6618 instruct loadUS2L(eRegL dst, memory mem, eFlagsReg cr) %{
6619 match(Set dst (ConvI2L (LoadUS mem)));
6620 effect(KILL cr);
6621
6622 ins_cost(250);
6623 format %{ "MOVZX $dst.lo,$mem\t# ushort/char -> long\n\t"
6624 "XOR $dst.hi,$dst.hi" %}
6625
6626 ins_encode %{
6627 __ movzwl($dst$$Register, $mem$$Address);
6628 __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register));
6629 %}
6630
6631 ins_pipe(ialu_reg_mem);
6632 %}
6633
6634 // Load Unsigned Short/Char (16 bit UNsigned) with mask 0xFF into Long Register
6635 instruct loadUS2L_immI_255(eRegL dst, memory mem, immI_255 mask, eFlagsReg cr) %{
6636 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
6637 effect(KILL cr);
6638
6639 format %{ "MOVZX8 $dst.lo,$mem\t# ushort/char & 0xFF -> long\n\t"
6640 "XOR $dst.hi,$dst.hi" %}
6641 ins_encode %{
6642 Register Rdst = $dst$$Register;
6643 __ movzbl(Rdst, $mem$$Address);
6644 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6645 %}
6646 ins_pipe(ialu_reg_mem);
6647 %}
6648
6649 // Load Unsigned Short/Char (16 bit UNsigned) with a 16-bit mask into Long Register
6650 instruct loadUS2L_immI16(eRegL dst, memory mem, immI16 mask, eFlagsReg cr) %{
6651 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
6652 effect(KILL cr);
6653
6654 format %{ "MOVZX $dst.lo, $mem\t# ushort/char & 16-bit mask -> long\n\t"
6655 "XOR $dst.hi,$dst.hi\n\t"
6656 "AND $dst.lo,$mask" %}
6657 ins_encode %{
6658 Register Rdst = $dst$$Register;
6659 __ movzwl(Rdst, $mem$$Address);
6660 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6661 __ andl(Rdst, $mask$$constant);
6662 %}
6663 ins_pipe(ialu_reg_mem);
6664 %}
6665
6666 // Load Integer
6667 instruct loadI(eRegI dst, memory mem) %{
6668 match(Set dst (LoadI mem));
6669
6670 ins_cost(125);
6671 format %{ "MOV $dst,$mem\t# int" %}
6672
6673 ins_encode %{
6674 __ movl($dst$$Register, $mem$$Address);
6675 %}
6676
6677 ins_pipe(ialu_reg_mem);
6678 %}
6679
6680 // Load Integer (32 bit signed) to Byte (8 bit signed)
6681 instruct loadI2B(eRegI dst, memory mem, immI_24 twentyfour) %{
6682 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
6683
6684 ins_cost(125);
6685 format %{ "MOVSX $dst, $mem\t# int -> byte" %}
6686 ins_encode %{
6687 __ movsbl($dst$$Register, $mem$$Address);
6688 %}
6689 ins_pipe(ialu_reg_mem);
6690 %}
6691
6692 // Load Integer (32 bit signed) to Unsigned Byte (8 bit UNsigned)
6693 instruct loadI2UB(eRegI dst, memory mem, immI_255 mask) %{
6694 match(Set dst (AndI (LoadI mem) mask));
6695
6696 ins_cost(125);
6697 format %{ "MOVZX $dst, $mem\t# int -> ubyte" %}
6698 ins_encode %{
6699 __ movzbl($dst$$Register, $mem$$Address);
6700 %}
6701 ins_pipe(ialu_reg_mem);
6702 %}
6703
6704 // Load Integer (32 bit signed) to Short (16 bit signed)
6705 instruct loadI2S(eRegI dst, memory mem, immI_16 sixteen) %{
6706 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
6707
6708 ins_cost(125);
6709 format %{ "MOVSX $dst, $mem\t# int -> short" %}
6710 ins_encode %{
6711 __ movswl($dst$$Register, $mem$$Address);
6712 %}
6713 ins_pipe(ialu_reg_mem);
6714 %}
6715
6716 // Load Integer (32 bit signed) to Unsigned Short/Char (16 bit UNsigned)
6717 instruct loadI2US(eRegI dst, memory mem, immI_65535 mask) %{
6718 match(Set dst (AndI (LoadI mem) mask));
6719
6720 ins_cost(125);
6721 format %{ "MOVZX $dst, $mem\t# int -> ushort/char" %}
6722 ins_encode %{
6723 __ movzwl($dst$$Register, $mem$$Address);
6724 %}
6725 ins_pipe(ialu_reg_mem);
6726 %}
6727
6728 // Load Integer into Long Register
6729 instruct loadI2L(eRegL dst, memory mem, eFlagsReg cr) %{
6730 match(Set dst (ConvI2L (LoadI mem)));
6731 effect(KILL cr);
6732
6733 ins_cost(375);
6734 format %{ "MOV $dst.lo,$mem\t# int -> long\n\t"
6735 "MOV $dst.hi,$dst.lo\n\t"
6736 "SAR $dst.hi,31" %}
6737
6738 ins_encode %{
6739 __ movl($dst$$Register, $mem$$Address);
6740 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
6741 __ sarl(HIGH_FROM_LOW($dst$$Register), 31);
6742 %}
6743
6744 ins_pipe(ialu_reg_mem);
6745 %}
6746
6747 // Load Integer with mask 0xFF into Long Register
6748 instruct loadI2L_immI_255(eRegL dst, memory mem, immI_255 mask, eFlagsReg cr) %{
6749 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
6750 effect(KILL cr);
6751
6752 format %{ "MOVZX8 $dst.lo,$mem\t# int & 0xFF -> long\n\t"
6753 "XOR $dst.hi,$dst.hi" %}
6754 ins_encode %{
6755 Register Rdst = $dst$$Register;
6756 __ movzbl(Rdst, $mem$$Address);
6757 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6758 %}
6759 ins_pipe(ialu_reg_mem);
6760 %}
6761
6762 // Load Integer with mask 0xFFFF into Long Register
6763 instruct loadI2L_immI_65535(eRegL dst, memory mem, immI_65535 mask, eFlagsReg cr) %{
6764 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
6765 effect(KILL cr);
6766
6767 format %{ "MOVZX $dst.lo,$mem\t# int & 0xFFFF -> long\n\t"
6768 "XOR $dst.hi,$dst.hi" %}
6769 ins_encode %{
6770 Register Rdst = $dst$$Register;
6771 __ movzwl(Rdst, $mem$$Address);
6772 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6773 %}
6774 ins_pipe(ialu_reg_mem);
6775 %}
6776
6777 // Load Integer with 32-bit mask into Long Register
6778 instruct loadI2L_immI(eRegL dst, memory mem, immI mask, eFlagsReg cr) %{
6779 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
6780 effect(KILL cr);
6781
6782 format %{ "MOV $dst.lo,$mem\t# int & 32-bit mask -> long\n\t"
6783 "XOR $dst.hi,$dst.hi\n\t"
6784 "AND $dst.lo,$mask" %}
6785 ins_encode %{
6786 Register Rdst = $dst$$Register;
6787 __ movl(Rdst, $mem$$Address);
6788 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6789 __ andl(Rdst, $mask$$constant);
6790 %}
6791 ins_pipe(ialu_reg_mem);
6792 %}
6793
6794 // Load Unsigned Integer into Long Register
6795 instruct loadUI2L(eRegL dst, memory mem, eFlagsReg cr) %{
6796 match(Set dst (LoadUI2L mem));
6797 effect(KILL cr);
6798
6799 ins_cost(250);
6800 format %{ "MOV $dst.lo,$mem\t# uint -> long\n\t"
6801 "XOR $dst.hi,$dst.hi" %}
6802
6803 ins_encode %{
6804 __ movl($dst$$Register, $mem$$Address);
6805 __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register));
6806 %}
6807
6808 ins_pipe(ialu_reg_mem);
6809 %}
6810
6811 // Load Long. Cannot clobber address while loading, so restrict address
6812 // register to ESI
6813 instruct loadL(eRegL dst, load_long_memory mem) %{
6814 predicate(!((LoadLNode*)n)->require_atomic_access());
6815 match(Set dst (LoadL mem));
6816
6817 ins_cost(250);
6818 format %{ "MOV $dst.lo,$mem\t# long\n\t"
6819 "MOV $dst.hi,$mem+4" %}
6820
6821 ins_encode %{
6822 Address Amemlo = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp, false);
6823 Address Amemhi = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp + 4, false);
6824 __ movl($dst$$Register, Amemlo);
6825 __ movl(HIGH_FROM_LOW($dst$$Register), Amemhi);
6826 %}
6827
6828 ins_pipe(ialu_reg_long_mem);
6829 %}
6830
6831 // Volatile Load Long. Must be atomic, so do 64-bit FILD
6832 // then store it down to the stack and reload on the int
6833 // side.
6834 instruct loadL_volatile(stackSlotL dst, memory mem) %{
6835 predicate(UseSSE<=1 && ((LoadLNode*)n)->require_atomic_access());
6836 match(Set dst (LoadL mem));
6837
6838 ins_cost(200);
6839 format %{ "FILD $mem\t# Atomic volatile long load\n\t"
6840 "FISTp $dst" %}
6841 ins_encode(enc_loadL_volatile(mem,dst));
6842 ins_pipe( fpu_reg_mem );
6843 %}
6844
6845 instruct loadLX_volatile(stackSlotL dst, memory mem, regXD tmp) %{
6846 predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access());
6847 match(Set dst (LoadL mem));
6848 effect(TEMP tmp);
6849 ins_cost(180);
6850 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
6851 "MOVSD $dst,$tmp" %}
6852 ins_encode(enc_loadLX_volatile(mem, dst, tmp));
6853 ins_pipe( pipe_slow );
6854 %}
6855
6856 instruct loadLX_reg_volatile(eRegL dst, memory mem, regXD tmp) %{
6857 predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access());
6858 match(Set dst (LoadL mem));
6859 effect(TEMP tmp);
6860 ins_cost(160);
6861 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
6862 "MOVD $dst.lo,$tmp\n\t"
6863 "PSRLQ $tmp,32\n\t"
6864 "MOVD $dst.hi,$tmp" %}
6865 ins_encode(enc_loadLX_reg_volatile(mem, dst, tmp));
6866 ins_pipe( pipe_slow );
6867 %}
6868
6869 // Load Range
6870 instruct loadRange(eRegI dst, memory mem) %{
6871 match(Set dst (LoadRange mem));
6872
6873 ins_cost(125);
6874 format %{ "MOV $dst,$mem" %}
6875 opcode(0x8B);
6876 ins_encode( OpcP, RegMem(dst,mem));
6877 ins_pipe( ialu_reg_mem );
6878 %}
6879
6880
6881 // Load Pointer
6882 instruct loadP(eRegP dst, memory mem) %{
6883 match(Set dst (LoadP mem));
6884
6885 ins_cost(125);
6886 format %{ "MOV $dst,$mem" %}
6887 opcode(0x8B);
6888 ins_encode( OpcP, RegMem(dst,mem));
6889 ins_pipe( ialu_reg_mem );
6890 %}
6891
6892 // Load Klass Pointer
6893 instruct loadKlass(eRegP dst, memory mem) %{
6894 match(Set dst (LoadKlass mem));
6895
6896 ins_cost(125);
6897 format %{ "MOV $dst,$mem" %}
6898 opcode(0x8B);
6899 ins_encode( OpcP, RegMem(dst,mem));
6900 ins_pipe( ialu_reg_mem );
6901 %}
6902
6903 // Load Double
6904 instruct loadD(regD dst, memory mem) %{
6905 predicate(UseSSE<=1);
6906 match(Set dst (LoadD mem));
6907
6908 ins_cost(150);
6909 format %{ "FLD_D ST,$mem\n\t"
6910 "FSTP $dst" %}
6911 opcode(0xDD); /* DD /0 */
6912 ins_encode( OpcP, RMopc_Mem(0x00,mem),
6913 Pop_Reg_D(dst) );
6914 ins_pipe( fpu_reg_mem );
6915 %}
6916
6917 // Load Double to XMM
6918 instruct loadXD(regXD dst, memory mem) %{
6919 predicate(UseSSE>=2 && UseXmmLoadAndClearUpper);
6920 match(Set dst (LoadD mem));
6921 ins_cost(145);
6922 format %{ "MOVSD $dst,$mem" %}
6923 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x10), RegMem(dst,mem));
6924 ins_pipe( pipe_slow );
6925 %}
6926
6927 instruct loadXD_partial(regXD dst, memory mem) %{
6928 predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper);
6929 match(Set dst (LoadD mem));
6930 ins_cost(145);
6931 format %{ "MOVLPD $dst,$mem" %}
6932 ins_encode( Opcode(0x66), Opcode(0x0F), Opcode(0x12), RegMem(dst,mem));
6933 ins_pipe( pipe_slow );
6934 %}
6935
6936 // Load to XMM register (single-precision floating point)
6937 // MOVSS instruction
6938 instruct loadX(regX dst, memory mem) %{
6939 predicate(UseSSE>=1);
6940 match(Set dst (LoadF mem));
6941 ins_cost(145);
6942 format %{ "MOVSS $dst,$mem" %}
6943 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x10), RegMem(dst,mem));
6944 ins_pipe( pipe_slow );
6945 %}
6946
6947 // Load Float
6948 instruct loadF(regF dst, memory mem) %{
6949 predicate(UseSSE==0);
6950 match(Set dst (LoadF mem));
6951
6952 ins_cost(150);
6953 format %{ "FLD_S ST,$mem\n\t"
6954 "FSTP $dst" %}
6955 opcode(0xD9); /* D9 /0 */
6956 ins_encode( OpcP, RMopc_Mem(0x00,mem),
6957 Pop_Reg_F(dst) );
6958 ins_pipe( fpu_reg_mem );
6959 %}
6960
6961 // Load Aligned Packed Byte to XMM register
6962 instruct loadA8B(regXD dst, memory mem) %{
6963 predicate(UseSSE>=1);
6964 match(Set dst (Load8B mem));
6965 ins_cost(125);
6966 format %{ "MOVQ $dst,$mem\t! packed8B" %}
6967 ins_encode( movq_ld(dst, mem));
6968 ins_pipe( pipe_slow );
6969 %}
6970
6971 // Load Aligned Packed Short to XMM register
6972 instruct loadA4S(regXD dst, memory mem) %{
6973 predicate(UseSSE>=1);
6974 match(Set dst (Load4S mem));
6975 ins_cost(125);
6976 format %{ "MOVQ $dst,$mem\t! packed4S" %}
6977 ins_encode( movq_ld(dst, mem));
6978 ins_pipe( pipe_slow );
6979 %}
6980
6981 // Load Aligned Packed Char to XMM register
6982 instruct loadA4C(regXD dst, memory mem) %{
6983 predicate(UseSSE>=1);
6984 match(Set dst (Load4C mem));
6985 ins_cost(125);
6986 format %{ "MOVQ $dst,$mem\t! packed4C" %}
6987 ins_encode( movq_ld(dst, mem));
6988 ins_pipe( pipe_slow );
6989 %}
6990
6991 // Load Aligned Packed Integer to XMM register
6992 instruct load2IU(regXD dst, memory mem) %{
6993 predicate(UseSSE>=1);
6994 match(Set dst (Load2I mem));
6995 ins_cost(125);
6996 format %{ "MOVQ $dst,$mem\t! packed2I" %}
6997 ins_encode( movq_ld(dst, mem));
6998 ins_pipe( pipe_slow );
6999 %}
7000
7001 // Load Aligned Packed Single to XMM
7002 instruct loadA2F(regXD dst, memory mem) %{
7003 predicate(UseSSE>=1);
7004 match(Set dst (Load2F mem));
7005 ins_cost(145);
7006 format %{ "MOVQ $dst,$mem\t! packed2F" %}
7007 ins_encode( movq_ld(dst, mem));
7008 ins_pipe( pipe_slow );
7009 %}
7010
7011 // Load Effective Address
7012 instruct leaP8(eRegP dst, indOffset8 mem) %{
7013 match(Set dst mem);
7014
7015 ins_cost(110);
7016 format %{ "LEA $dst,$mem" %}
7017 opcode(0x8D);
7018 ins_encode( OpcP, RegMem(dst,mem));
7019 ins_pipe( ialu_reg_reg_fat );
7020 %}
7021
7022 instruct leaP32(eRegP dst, indOffset32 mem) %{
7023 match(Set dst mem);
7024
7025 ins_cost(110);
7026 format %{ "LEA $dst,$mem" %}
7027 opcode(0x8D);
7028 ins_encode( OpcP, RegMem(dst,mem));
7029 ins_pipe( ialu_reg_reg_fat );
7030 %}
7031
7032 instruct leaPIdxOff(eRegP dst, indIndexOffset mem) %{
7033 match(Set dst mem);
7034
7035 ins_cost(110);
7036 format %{ "LEA $dst,$mem" %}
7037 opcode(0x8D);
7038 ins_encode( OpcP, RegMem(dst,mem));
7039 ins_pipe( ialu_reg_reg_fat );
7040 %}
7041
7042 instruct leaPIdxScale(eRegP dst, indIndexScale mem) %{
7043 match(Set dst mem);
7044
7045 ins_cost(110);
7046 format %{ "LEA $dst,$mem" %}
7047 opcode(0x8D);
7048 ins_encode( OpcP, RegMem(dst,mem));
7049 ins_pipe( ialu_reg_reg_fat );
7050 %}
7051
7052 instruct leaPIdxScaleOff(eRegP dst, indIndexScaleOffset mem) %{
7053 match(Set dst mem);
7054
7055 ins_cost(110);
7056 format %{ "LEA $dst,$mem" %}
7057 opcode(0x8D);
7058 ins_encode( OpcP, RegMem(dst,mem));
7059 ins_pipe( ialu_reg_reg_fat );
7060 %}
7061
7062 // Load Constant
7063 instruct loadConI(eRegI dst, immI src) %{
7064 match(Set dst src);
7065
7066 format %{ "MOV $dst,$src" %}
7067 ins_encode( LdImmI(dst, src) );
7068 ins_pipe( ialu_reg_fat );
7069 %}
7070
7071 // Load Constant zero
7072 instruct loadConI0(eRegI dst, immI0 src, eFlagsReg cr) %{
7073 match(Set dst src);
7074 effect(KILL cr);
7075
7076 ins_cost(50);
7077 format %{ "XOR $dst,$dst" %}
7078 opcode(0x33); /* + rd */
7079 ins_encode( OpcP, RegReg( dst, dst ) );
7080 ins_pipe( ialu_reg );
7081 %}
7082
7083 instruct loadConP(eRegP dst, immP src) %{
7084 match(Set dst src);
7085
7086 format %{ "MOV $dst,$src" %}
7087 opcode(0xB8); /* + rd */
7088 ins_encode( LdImmP(dst, src) );
7089 ins_pipe( ialu_reg_fat );
7090 %}
7091
7092 instruct loadConL(eRegL dst, immL src, eFlagsReg cr) %{
7093 match(Set dst src);
7094 effect(KILL cr);
7095 ins_cost(200);
7096 format %{ "MOV $dst.lo,$src.lo\n\t"
7097 "MOV $dst.hi,$src.hi" %}
7098 opcode(0xB8);
7099 ins_encode( LdImmL_Lo(dst, src), LdImmL_Hi(dst, src) );
7100 ins_pipe( ialu_reg_long_fat );
7101 %}
7102
7103 instruct loadConL0(eRegL dst, immL0 src, eFlagsReg cr) %{
7104 match(Set dst src);
7105 effect(KILL cr);
7106 ins_cost(150);
7107 format %{ "XOR $dst.lo,$dst.lo\n\t"
7108 "XOR $dst.hi,$dst.hi" %}
7109 opcode(0x33,0x33);
7110 ins_encode( RegReg_Lo(dst,dst), RegReg_Hi(dst, dst) );
7111 ins_pipe( ialu_reg_long );
7112 %}
7113
7114 // The instruction usage is guarded by predicate in operand immF().
7115 instruct loadConF(regF dst, immF src) %{
7116 match(Set dst src);
7117 ins_cost(125);
7118
7119 format %{ "FLD_S ST,$src\n\t"
7120 "FSTP $dst" %}
7121 opcode(0xD9, 0x00); /* D9 /0 */
7122 ins_encode(LdImmF(src), Pop_Reg_F(dst) );
7123 ins_pipe( fpu_reg_con );
7124 %}
7125
7126 // The instruction usage is guarded by predicate in operand immXF().
7127 instruct loadConX(regX dst, immXF con) %{
7128 match(Set dst con);
7129 ins_cost(125);
7130 format %{ "MOVSS $dst,[$con]" %}
7131 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x10), LdImmX(dst, con));
7132 ins_pipe( pipe_slow );
7133 %}
7134
7135 // The instruction usage is guarded by predicate in operand immXF0().
7136 instruct loadConX0(regX dst, immXF0 src) %{
7137 match(Set dst src);
7138 ins_cost(100);
7139 format %{ "XORPS $dst,$dst\t# float 0.0" %}
7140 ins_encode( Opcode(0x0F), Opcode(0x57), RegReg(dst,dst));
7141 ins_pipe( pipe_slow );
7142 %}
7143
7144 // The instruction usage is guarded by predicate in operand immD().
7145 instruct loadConD(regD dst, immD src) %{
7146 match(Set dst src);
7147 ins_cost(125);
7148
7149 format %{ "FLD_D ST,$src\n\t"
7150 "FSTP $dst" %}
7151 ins_encode(LdImmD(src), Pop_Reg_D(dst) );
7152 ins_pipe( fpu_reg_con );
7153 %}
7154
7155 // The instruction usage is guarded by predicate in operand immXD().
7156 instruct loadConXD(regXD dst, immXD con) %{
7157 match(Set dst con);
7158 ins_cost(125);
7159 format %{ "MOVSD $dst,[$con]" %}
7160 ins_encode(load_conXD(dst, con));
7161 ins_pipe( pipe_slow );
7162 %}
7163
7164 // The instruction usage is guarded by predicate in operand immXD0().
7165 instruct loadConXD0(regXD dst, immXD0 src) %{
7166 match(Set dst src);
7167 ins_cost(100);
7168 format %{ "XORPD $dst,$dst\t# double 0.0" %}
7169 ins_encode( Opcode(0x66), Opcode(0x0F), Opcode(0x57), RegReg(dst,dst));
7170 ins_pipe( pipe_slow );
7171 %}
7172
7173 // Load Stack Slot
7174 instruct loadSSI(eRegI dst, stackSlotI src) %{
7175 match(Set dst src);
7176 ins_cost(125);
7177
7178 format %{ "MOV $dst,$src" %}
7179 opcode(0x8B);
7180 ins_encode( OpcP, RegMem(dst,src));
7181 ins_pipe( ialu_reg_mem );
7182 %}
7183
7184 instruct loadSSL(eRegL dst, stackSlotL src) %{
7185 match(Set dst src);
7186
7187 ins_cost(200);
7188 format %{ "MOV $dst,$src.lo\n\t"
7189 "MOV $dst+4,$src.hi" %}
7190 opcode(0x8B, 0x8B);
7191 ins_encode( OpcP, RegMem( dst, src ), OpcS, RegMem_Hi( dst, src ) );
7192 ins_pipe( ialu_mem_long_reg );
7193 %}
7194
7195 // Load Stack Slot
7196 instruct loadSSP(eRegP dst, stackSlotP src) %{
7197 match(Set dst src);
7198 ins_cost(125);
7199
7200 format %{ "MOV $dst,$src" %}
7201 opcode(0x8B);
7202 ins_encode( OpcP, RegMem(dst,src));
7203 ins_pipe( ialu_reg_mem );
7204 %}
7205
7206 // Load Stack Slot
7207 instruct loadSSF(regF dst, stackSlotF src) %{
7208 match(Set dst src);
7209 ins_cost(125);
7210
7211 format %{ "FLD_S $src\n\t"
7212 "FSTP $dst" %}
7213 opcode(0xD9); /* D9 /0, FLD m32real */
7214 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
7215 Pop_Reg_F(dst) );
7216 ins_pipe( fpu_reg_mem );
7217 %}
7218
7219 // Load Stack Slot
7220 instruct loadSSD(regD dst, stackSlotD src) %{
7221 match(Set dst src);
7222 ins_cost(125);
7223
7224 format %{ "FLD_D $src\n\t"
7225 "FSTP $dst" %}
7226 opcode(0xDD); /* DD /0, FLD m64real */
7227 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
7228 Pop_Reg_D(dst) );
7229 ins_pipe( fpu_reg_mem );
7230 %}
7231
7232 // Prefetch instructions.
7233 // Must be safe to execute with invalid address (cannot fault).
7234
7235 instruct prefetchr0( memory mem ) %{
7236 predicate(UseSSE==0 && !VM_Version::supports_3dnow());
7237 match(PrefetchRead mem);
7238 ins_cost(0);
7239 size(0);
7240 format %{ "PREFETCHR (non-SSE is empty encoding)" %}
7241 ins_encode();
7242 ins_pipe(empty);
7243 %}
7244
7245 instruct prefetchr( memory mem ) %{
7246 predicate(UseSSE==0 && VM_Version::supports_3dnow() || ReadPrefetchInstr==3);
7247 match(PrefetchRead mem);
7248 ins_cost(100);
7249
7250 format %{ "PREFETCHR $mem\t! Prefetch into level 1 cache for read" %}
7251 opcode(0x0F, 0x0d); /* Opcode 0F 0d /0 */
7252 ins_encode(OpcP, OpcS, RMopc_Mem(0x00,mem));
7253 ins_pipe(ialu_mem);
7254 %}
7255
7256 instruct prefetchrNTA( memory mem ) %{
7257 predicate(UseSSE>=1 && ReadPrefetchInstr==0);
7258 match(PrefetchRead mem);
7259 ins_cost(100);
7260
7261 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for read" %}
7262 opcode(0x0F, 0x18); /* Opcode 0F 18 /0 */
7263 ins_encode(OpcP, OpcS, RMopc_Mem(0x00,mem));
7264 ins_pipe(ialu_mem);
7265 %}
7266
7267 instruct prefetchrT0( memory mem ) %{
7268 predicate(UseSSE>=1 && ReadPrefetchInstr==1);
7269 match(PrefetchRead mem);
7270 ins_cost(100);
7271
7272 format %{ "PREFETCHT0 $mem\t! Prefetch into L1 and L2 caches for read" %}
7273 opcode(0x0F, 0x18); /* Opcode 0F 18 /1 */
7274 ins_encode(OpcP, OpcS, RMopc_Mem(0x01,mem));
7275 ins_pipe(ialu_mem);
7276 %}
7277
7278 instruct prefetchrT2( memory mem ) %{
7279 predicate(UseSSE>=1 && ReadPrefetchInstr==2);
7280 match(PrefetchRead mem);
7281 ins_cost(100);
7282
7283 format %{ "PREFETCHT2 $mem\t! Prefetch into L2 cache for read" %}
7284 opcode(0x0F, 0x18); /* Opcode 0F 18 /3 */
7285 ins_encode(OpcP, OpcS, RMopc_Mem(0x03,mem));
7286 ins_pipe(ialu_mem);
7287 %}
7288
7289 instruct prefetchw0( memory mem ) %{
7290 predicate(UseSSE==0 && !VM_Version::supports_3dnow());
7291 match(PrefetchWrite mem);
7292 ins_cost(0);
7293 size(0);
7294 format %{ "Prefetch (non-SSE is empty encoding)" %}
7295 ins_encode();
7296 ins_pipe(empty);
7297 %}
7298
7299 instruct prefetchw( memory mem ) %{
7300 predicate(UseSSE==0 && VM_Version::supports_3dnow() || AllocatePrefetchInstr==3);
7301 match( PrefetchWrite mem );
7302 ins_cost(100);
7303
7304 format %{ "PREFETCHW $mem\t! Prefetch into L1 cache and mark modified" %}
7305 opcode(0x0F, 0x0D); /* Opcode 0F 0D /1 */
7306 ins_encode(OpcP, OpcS, RMopc_Mem(0x01,mem));
7307 ins_pipe(ialu_mem);
7308 %}
7309
7310 instruct prefetchwNTA( memory mem ) %{
7311 predicate(UseSSE>=1 && AllocatePrefetchInstr==0);
7312 match(PrefetchWrite mem);
7313 ins_cost(100);
7314
7315 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for write" %}
7316 opcode(0x0F, 0x18); /* Opcode 0F 18 /0 */
7317 ins_encode(OpcP, OpcS, RMopc_Mem(0x00,mem));
7318 ins_pipe(ialu_mem);
7319 %}
7320
7321 instruct prefetchwT0( memory mem ) %{
7322 predicate(UseSSE>=1 && AllocatePrefetchInstr==1);
7323 match(PrefetchWrite mem);
7324 ins_cost(100);
7325
7326 format %{ "PREFETCHT0 $mem\t! Prefetch into L1 and L2 caches for write" %}
7327 opcode(0x0F, 0x18); /* Opcode 0F 18 /1 */
7328 ins_encode(OpcP, OpcS, RMopc_Mem(0x01,mem));
7329 ins_pipe(ialu_mem);
7330 %}
7331
7332 instruct prefetchwT2( memory mem ) %{
7333 predicate(UseSSE>=1 && AllocatePrefetchInstr==2);
7334 match(PrefetchWrite mem);
7335 ins_cost(100);
7336
7337 format %{ "PREFETCHT2 $mem\t! Prefetch into L2 cache for write" %}
7338 opcode(0x0F, 0x18); /* Opcode 0F 18 /3 */
7339 ins_encode(OpcP, OpcS, RMopc_Mem(0x03,mem));
7340 ins_pipe(ialu_mem);
7341 %}
7342
7343 //----------Store Instructions-------------------------------------------------
7344
7345 // Store Byte
7346 instruct storeB(memory mem, xRegI src) %{
7347 match(Set mem (StoreB mem src));
7348
7349 ins_cost(125);
7350 format %{ "MOV8 $mem,$src" %}
7351 opcode(0x88);
7352 ins_encode( OpcP, RegMem( src, mem ) );
7353 ins_pipe( ialu_mem_reg );
7354 %}
7355
7356 // Store Char/Short
7357 instruct storeC(memory mem, eRegI src) %{
7358 match(Set mem (StoreC mem src));
7359
7360 ins_cost(125);
7361 format %{ "MOV16 $mem,$src" %}
7362 opcode(0x89, 0x66);
7363 ins_encode( OpcS, OpcP, RegMem( src, mem ) );
7364 ins_pipe( ialu_mem_reg );
7365 %}
7366
7367 // Store Integer
7368 instruct storeI(memory mem, eRegI src) %{
7369 match(Set mem (StoreI mem src));
7370
7371 ins_cost(125);
7372 format %{ "MOV $mem,$src" %}
7373 opcode(0x89);
7374 ins_encode( OpcP, RegMem( src, mem ) );
7375 ins_pipe( ialu_mem_reg );
7376 %}
7377
7378 // Store Long
7379 instruct storeL(long_memory mem, eRegL src) %{
7380 predicate(!((StoreLNode*)n)->require_atomic_access());
7381 match(Set mem (StoreL mem src));
7382
7383 ins_cost(200);
7384 format %{ "MOV $mem,$src.lo\n\t"
7385 "MOV $mem+4,$src.hi" %}
7386 opcode(0x89, 0x89);
7387 ins_encode( OpcP, RegMem( src, mem ), OpcS, RegMem_Hi( src, mem ) );
7388 ins_pipe( ialu_mem_long_reg );
7389 %}
7390
7391 // Store Long to Integer
7392 instruct storeL2I(memory mem, eRegL src) %{
7393 match(Set mem (StoreI mem (ConvL2I src)));
7394
7395 format %{ "MOV $mem,$src.lo\t# long -> int" %}
7396 ins_encode %{
7397 __ movl($mem$$Address, $src$$Register);
7398 %}
7399 ins_pipe(ialu_mem_reg);
7400 %}
7401
7402 // Volatile Store Long. Must be atomic, so move it into
7403 // the FP TOS and then do a 64-bit FIST. Has to probe the
7404 // target address before the store (for null-ptr checks)
7405 // so the memory operand is used twice in the encoding.
7406 instruct storeL_volatile(memory mem, stackSlotL src, eFlagsReg cr ) %{
7407 predicate(UseSSE<=1 && ((StoreLNode*)n)->require_atomic_access());
7408 match(Set mem (StoreL mem src));
7409 effect( KILL cr );
7410 ins_cost(400);
7411 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
7412 "FILD $src\n\t"
7413 "FISTp $mem\t # 64-bit atomic volatile long store" %}
7414 opcode(0x3B);
7415 ins_encode( OpcP, RegMem( EAX, mem ), enc_storeL_volatile(mem,src));
7416 ins_pipe( fpu_reg_mem );
7417 %}
7418
7419 instruct storeLX_volatile(memory mem, stackSlotL src, regXD tmp, eFlagsReg cr) %{
7420 predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access());
7421 match(Set mem (StoreL mem src));
7422 effect( TEMP tmp, KILL cr );
7423 ins_cost(380);
7424 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
7425 "MOVSD $tmp,$src\n\t"
7426 "MOVSD $mem,$tmp\t # 64-bit atomic volatile long store" %}
7427 opcode(0x3B);
7428 ins_encode( OpcP, RegMem( EAX, mem ), enc_storeLX_volatile(mem, src, tmp));
7429 ins_pipe( pipe_slow );
7430 %}
7431
7432 instruct storeLX_reg_volatile(memory mem, eRegL src, regXD tmp2, regXD tmp, eFlagsReg cr) %{
7433 predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access());
7434 match(Set mem (StoreL mem src));
7435 effect( TEMP tmp2 , TEMP tmp, KILL cr );
7436 ins_cost(360);
7437 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
7438 "MOVD $tmp,$src.lo\n\t"
7439 "MOVD $tmp2,$src.hi\n\t"
7440 "PUNPCKLDQ $tmp,$tmp2\n\t"
7441 "MOVSD $mem,$tmp\t # 64-bit atomic volatile long store" %}
7442 opcode(0x3B);
7443 ins_encode( OpcP, RegMem( EAX, mem ), enc_storeLX_reg_volatile(mem, src, tmp, tmp2));
7444 ins_pipe( pipe_slow );
7445 %}
7446
7447 // Store Pointer; for storing unknown oops and raw pointers
7448 instruct storeP(memory mem, anyRegP src) %{
7449 match(Set mem (StoreP mem src));
7450
7451 ins_cost(125);
7452 format %{ "MOV $mem,$src" %}
7453 opcode(0x89);
7454 ins_encode( OpcP, RegMem( src, mem ) );
7455 ins_pipe( ialu_mem_reg );
7456 %}
7457
7458 // Store Integer Immediate
7459 instruct storeImmI(memory mem, immI src) %{
7460 match(Set mem (StoreI mem src));
7461
7462 ins_cost(150);
7463 format %{ "MOV $mem,$src" %}
7464 opcode(0xC7); /* C7 /0 */
7465 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32( src ));
7466 ins_pipe( ialu_mem_imm );
7467 %}
7468
7469 // Store Short/Char Immediate
7470 instruct storeImmI16(memory mem, immI16 src) %{
7471 predicate(UseStoreImmI16);
7472 match(Set mem (StoreC mem src));
7473
7474 ins_cost(150);
7475 format %{ "MOV16 $mem,$src" %}
7476 opcode(0xC7); /* C7 /0 Same as 32 store immediate with prefix */
7477 ins_encode( SizePrefix, OpcP, RMopc_Mem(0x00,mem), Con16( src ));
7478 ins_pipe( ialu_mem_imm );
7479 %}
7480
7481 // Store Pointer Immediate; null pointers or constant oops that do not
7482 // need card-mark barriers.
7483 instruct storeImmP(memory mem, immP src) %{
7484 match(Set mem (StoreP mem src));
7485
7486 ins_cost(150);
7487 format %{ "MOV $mem,$src" %}
7488 opcode(0xC7); /* C7 /0 */
7489 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32( src ));
7490 ins_pipe( ialu_mem_imm );
7491 %}
7492
7493 // Store Byte Immediate
7494 instruct storeImmB(memory mem, immI8 src) %{
7495 match(Set mem (StoreB mem src));
7496
7497 ins_cost(150);
7498 format %{ "MOV8 $mem,$src" %}
7499 opcode(0xC6); /* C6 /0 */
7500 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con8or32( src ));
7501 ins_pipe( ialu_mem_imm );
7502 %}
7503
7504 // Store Aligned Packed Byte XMM register to memory
7505 instruct storeA8B(memory mem, regXD src) %{
7506 predicate(UseSSE>=1);
7507 match(Set mem (Store8B mem src));
7508 ins_cost(145);
7509 format %{ "MOVQ $mem,$src\t! packed8B" %}
7510 ins_encode( movq_st(mem, src));
7511 ins_pipe( pipe_slow );
7512 %}
7513
7514 // Store Aligned Packed Char/Short XMM register to memory
7515 instruct storeA4C(memory mem, regXD src) %{
7516 predicate(UseSSE>=1);
7517 match(Set mem (Store4C mem src));
7518 ins_cost(145);
7519 format %{ "MOVQ $mem,$src\t! packed4C" %}
7520 ins_encode( movq_st(mem, src));
7521 ins_pipe( pipe_slow );
7522 %}
7523
7524 // Store Aligned Packed Integer XMM register to memory
7525 instruct storeA2I(memory mem, regXD src) %{
7526 predicate(UseSSE>=1);
7527 match(Set mem (Store2I mem src));
7528 ins_cost(145);
7529 format %{ "MOVQ $mem,$src\t! packed2I" %}
7530 ins_encode( movq_st(mem, src));
7531 ins_pipe( pipe_slow );
7532 %}
7533
7534 // Store CMS card-mark Immediate
7535 instruct storeImmCM(memory mem, immI8 src) %{
7536 match(Set mem (StoreCM mem src));
7537
7538 ins_cost(150);
7539 format %{ "MOV8 $mem,$src\t! CMS card-mark imm0" %}
7540 opcode(0xC6); /* C6 /0 */
7541 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con8or32( src ));
7542 ins_pipe( ialu_mem_imm );
7543 %}
7544
7545 // Store Double
7546 instruct storeD( memory mem, regDPR1 src) %{
7547 predicate(UseSSE<=1);
7548 match(Set mem (StoreD mem src));
7549
7550 ins_cost(100);
7551 format %{ "FST_D $mem,$src" %}
7552 opcode(0xDD); /* DD /2 */
7553 ins_encode( enc_FP_store(mem,src) );
7554 ins_pipe( fpu_mem_reg );
7555 %}
7556
7557 // Store double does rounding on x86
7558 instruct storeD_rounded( memory mem, regDPR1 src) %{
7559 predicate(UseSSE<=1);
7560 match(Set mem (StoreD mem (RoundDouble src)));
7561
7562 ins_cost(100);
7563 format %{ "FST_D $mem,$src\t# round" %}
7564 opcode(0xDD); /* DD /2 */
7565 ins_encode( enc_FP_store(mem,src) );
7566 ins_pipe( fpu_mem_reg );
7567 %}
7568
7569 // Store XMM register to memory (double-precision floating points)
7570 // MOVSD instruction
7571 instruct storeXD(memory mem, regXD src) %{
7572 predicate(UseSSE>=2);
7573 match(Set mem (StoreD mem src));
7574 ins_cost(95);
7575 format %{ "MOVSD $mem,$src" %}
7576 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x11), RegMem(src, mem));
7577 ins_pipe( pipe_slow );
7578 %}
7579
7580 // Store XMM register to memory (single-precision floating point)
7581 // MOVSS instruction
7582 instruct storeX(memory mem, regX src) %{
7583 predicate(UseSSE>=1);
7584 match(Set mem (StoreF mem src));
7585 ins_cost(95);
7586 format %{ "MOVSS $mem,$src" %}
7587 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x11), RegMem(src, mem));
7588 ins_pipe( pipe_slow );
7589 %}
7590
7591 // Store Aligned Packed Single Float XMM register to memory
7592 instruct storeA2F(memory mem, regXD src) %{
7593 predicate(UseSSE>=1);
7594 match(Set mem (Store2F mem src));
7595 ins_cost(145);
7596 format %{ "MOVQ $mem,$src\t! packed2F" %}
7597 ins_encode( movq_st(mem, src));
7598 ins_pipe( pipe_slow );
7599 %}
7600
7601 // Store Float
7602 instruct storeF( memory mem, regFPR1 src) %{
7603 predicate(UseSSE==0);
7604 match(Set mem (StoreF mem src));
7605
7606 ins_cost(100);
7607 format %{ "FST_S $mem,$src" %}
7608 opcode(0xD9); /* D9 /2 */
7609 ins_encode( enc_FP_store(mem,src) );
7610 ins_pipe( fpu_mem_reg );
7611 %}
7612
7613 // Store Float does rounding on x86
7614 instruct storeF_rounded( memory mem, regFPR1 src) %{
7615 predicate(UseSSE==0);
7616 match(Set mem (StoreF mem (RoundFloat src)));
7617
7618 ins_cost(100);
7619 format %{ "FST_S $mem,$src\t# round" %}
7620 opcode(0xD9); /* D9 /2 */
7621 ins_encode( enc_FP_store(mem,src) );
7622 ins_pipe( fpu_mem_reg );
7623 %}
7624
7625 // Store Float does rounding on x86
7626 instruct storeF_Drounded( memory mem, regDPR1 src) %{
7627 predicate(UseSSE<=1);
7628 match(Set mem (StoreF mem (ConvD2F src)));
7629
7630 ins_cost(100);
7631 format %{ "FST_S $mem,$src\t# D-round" %}
7632 opcode(0xD9); /* D9 /2 */
7633 ins_encode( enc_FP_store(mem,src) );
7634 ins_pipe( fpu_mem_reg );
7635 %}
7636
7637 // Store immediate Float value (it is faster than store from FPU register)
7638 // The instruction usage is guarded by predicate in operand immF().
7639 instruct storeF_imm( memory mem, immF src) %{
7640 match(Set mem (StoreF mem src));
7641
7642 ins_cost(50);
7643 format %{ "MOV $mem,$src\t# store float" %}
7644 opcode(0xC7); /* C7 /0 */
7645 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32F_as_bits( src ));
7646 ins_pipe( ialu_mem_imm );
7647 %}
7648
7649 // Store immediate Float value (it is faster than store from XMM register)
7650 // The instruction usage is guarded by predicate in operand immXF().
7651 instruct storeX_imm( memory mem, immXF src) %{
7652 match(Set mem (StoreF mem src));
7653
7654 ins_cost(50);
7655 format %{ "MOV $mem,$src\t# store float" %}
7656 opcode(0xC7); /* C7 /0 */
7657 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32XF_as_bits( src ));
7658 ins_pipe( ialu_mem_imm );
7659 %}
7660
7661 // Store Integer to stack slot
7662 instruct storeSSI(stackSlotI dst, eRegI src) %{
7663 match(Set dst src);
7664
7665 ins_cost(100);
7666 format %{ "MOV $dst,$src" %}
7667 opcode(0x89);
7668 ins_encode( OpcPRegSS( dst, src ) );
7669 ins_pipe( ialu_mem_reg );
7670 %}
7671
7672 // Store Integer to stack slot
7673 instruct storeSSP(stackSlotP dst, eRegP src) %{
7674 match(Set dst src);
7675
7676 ins_cost(100);
7677 format %{ "MOV $dst,$src" %}
7678 opcode(0x89);
7679 ins_encode( OpcPRegSS( dst, src ) );
7680 ins_pipe( ialu_mem_reg );
7681 %}
7682
7683 // Store Long to stack slot
7684 instruct storeSSL(stackSlotL dst, eRegL src) %{
7685 match(Set dst src);
7686
7687 ins_cost(200);
7688 format %{ "MOV $dst,$src.lo\n\t"
7689 "MOV $dst+4,$src.hi" %}
7690 opcode(0x89, 0x89);
7691 ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) );
7692 ins_pipe( ialu_mem_long_reg );
7693 %}
7694
7695 //----------MemBar Instructions-----------------------------------------------
7696 // Memory barrier flavors
7697
7698 instruct membar_acquire() %{
7699 match(MemBarAcquire);
7700 ins_cost(400);
7701
7702 size(0);
7703 format %{ "MEMBAR-acquire ! (empty encoding)" %}
7704 ins_encode();
7705 ins_pipe(empty);
7706 %}
7707
7708 instruct membar_acquire_lock() %{
7709 match(MemBarAcquire);
7710 predicate(Matcher::prior_fast_lock(n));
7711 ins_cost(0);
7712
7713 size(0);
7714 format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)" %}
7715 ins_encode( );
7716 ins_pipe(empty);
7717 %}
7718
7719 instruct membar_release() %{
7720 match(MemBarRelease);
7721 ins_cost(400);
7722
7723 size(0);
7724 format %{ "MEMBAR-release ! (empty encoding)" %}
7725 ins_encode( );
7726 ins_pipe(empty);
7727 %}
7728
7729 instruct membar_release_lock() %{
7730 match(MemBarRelease);
7731 predicate(Matcher::post_fast_unlock(n));
7732 ins_cost(0);
7733
7734 size(0);
7735 format %{ "MEMBAR-release (a FastUnlock follows so empty encoding)" %}
7736 ins_encode( );
7737 ins_pipe(empty);
7738 %}
7739
7740 instruct membar_volatile(eFlagsReg cr) %{
7741 match(MemBarVolatile);
7742 effect(KILL cr);
7743 ins_cost(400);
7744
7745 format %{
7746 $$template
7747 if (os::is_MP()) {
7748 $$emit$$"LOCK ADDL [ESP + #0], 0\t! membar_volatile"
7749 } else {
7750 $$emit$$"MEMBAR-volatile ! (empty encoding)"
7751 }
7752 %}
7753 ins_encode %{
7754 __ membar(Assembler::StoreLoad);
7755 %}
7756 ins_pipe(pipe_slow);
7757 %}
7758
7759 instruct unnecessary_membar_volatile() %{
7760 match(MemBarVolatile);
7761 predicate(Matcher::post_store_load_barrier(n));
7762 ins_cost(0);
7763
7764 size(0);
7765 format %{ "MEMBAR-volatile (unnecessary so empty encoding)" %}
7766 ins_encode( );
7767 ins_pipe(empty);
7768 %}
7769
7770 //----------Move Instructions--------------------------------------------------
7771 instruct castX2P(eAXRegP dst, eAXRegI src) %{
7772 match(Set dst (CastX2P src));
7773 format %{ "# X2P $dst, $src" %}
7774 ins_encode( /*empty encoding*/ );
7775 ins_cost(0);
7776 ins_pipe(empty);
7777 %}
7778
7779 instruct castP2X(eRegI dst, eRegP src ) %{
7780 match(Set dst (CastP2X src));
7781 ins_cost(50);
7782 format %{ "MOV $dst, $src\t# CastP2X" %}
7783 ins_encode( enc_Copy( dst, src) );
7784 ins_pipe( ialu_reg_reg );
7785 %}
7786
7787 //----------Conditional Move---------------------------------------------------
7788 // Conditional move
7789 instruct cmovI_reg(eRegI dst, eRegI src, eFlagsReg cr, cmpOp cop ) %{
7790 predicate(VM_Version::supports_cmov() );
7791 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7792 ins_cost(200);
7793 format %{ "CMOV$cop $dst,$src" %}
7794 opcode(0x0F,0x40);
7795 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7796 ins_pipe( pipe_cmov_reg );
7797 %}
7798
7799 instruct cmovI_regU( cmpOpU cop, eFlagsRegU cr, eRegI dst, eRegI src ) %{
7800 predicate(VM_Version::supports_cmov() );
7801 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7802 ins_cost(200);
7803 format %{ "CMOV$cop $dst,$src" %}
7804 opcode(0x0F,0x40);
7805 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7806 ins_pipe( pipe_cmov_reg );
7807 %}
7808
7809 instruct cmovI_regUCF( cmpOpUCF cop, eFlagsRegUCF cr, eRegI dst, eRegI src ) %{
7810 predicate(VM_Version::supports_cmov() );
7811 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7812 ins_cost(200);
7813 expand %{
7814 cmovI_regU(cop, cr, dst, src);
7815 %}
7816 %}
7817
7818 // Conditional move
7819 instruct cmovI_mem(cmpOp cop, eFlagsReg cr, eRegI dst, memory src) %{
7820 predicate(VM_Version::supports_cmov() );
7821 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7822 ins_cost(250);
7823 format %{ "CMOV$cop $dst,$src" %}
7824 opcode(0x0F,0x40);
7825 ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7826 ins_pipe( pipe_cmov_mem );
7827 %}
7828
7829 // Conditional move
7830 instruct cmovI_memU(cmpOpU cop, eFlagsRegU cr, eRegI dst, memory src) %{
7831 predicate(VM_Version::supports_cmov() );
7832 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7833 ins_cost(250);
7834 format %{ "CMOV$cop $dst,$src" %}
7835 opcode(0x0F,0x40);
7836 ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7837 ins_pipe( pipe_cmov_mem );
7838 %}
7839
7840 instruct cmovI_memUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegI dst, memory src) %{
7841 predicate(VM_Version::supports_cmov() );
7842 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7843 ins_cost(250);
7844 expand %{
7845 cmovI_memU(cop, cr, dst, src);
7846 %}
7847 %}
7848
7849 // Conditional move
7850 instruct cmovP_reg(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{
7851 predicate(VM_Version::supports_cmov() );
7852 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7853 ins_cost(200);
7854 format %{ "CMOV$cop $dst,$src\t# ptr" %}
7855 opcode(0x0F,0x40);
7856 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7857 ins_pipe( pipe_cmov_reg );
7858 %}
7859
7860 // Conditional move (non-P6 version)
7861 // Note: a CMoveP is generated for stubs and native wrappers
7862 // regardless of whether we are on a P6, so we
7863 // emulate a cmov here
7864 instruct cmovP_reg_nonP6(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{
7865 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7866 ins_cost(300);
7867 format %{ "Jn$cop skip\n\t"
7868 "MOV $dst,$src\t# pointer\n"
7869 "skip:" %}
7870 opcode(0x8b);
7871 ins_encode( enc_cmov_branch(cop, 0x2), OpcP, RegReg(dst, src));
7872 ins_pipe( pipe_cmov_reg );
7873 %}
7874
7875 // Conditional move
7876 instruct cmovP_regU(cmpOpU cop, eFlagsRegU cr, eRegP dst, eRegP src ) %{
7877 predicate(VM_Version::supports_cmov() );
7878 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7879 ins_cost(200);
7880 format %{ "CMOV$cop $dst,$src\t# ptr" %}
7881 opcode(0x0F,0x40);
7882 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7883 ins_pipe( pipe_cmov_reg );
7884 %}
7885
7886 instruct cmovP_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegP dst, eRegP src ) %{
7887 predicate(VM_Version::supports_cmov() );
7888 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7889 ins_cost(200);
7890 expand %{
7891 cmovP_regU(cop, cr, dst, src);
7892 %}
7893 %}
7894
7895 // DISABLED: Requires the ADLC to emit a bottom_type call that
7896 // correctly meets the two pointer arguments; one is an incoming
7897 // register but the other is a memory operand. ALSO appears to
7898 // be buggy with implicit null checks.
7899 //
7900 //// Conditional move
7901 //instruct cmovP_mem(cmpOp cop, eFlagsReg cr, eRegP dst, memory src) %{
7902 // predicate(VM_Version::supports_cmov() );
7903 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
7904 // ins_cost(250);
7905 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
7906 // opcode(0x0F,0x40);
7907 // ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7908 // ins_pipe( pipe_cmov_mem );
7909 //%}
7910 //
7911 //// Conditional move
7912 //instruct cmovP_memU(cmpOpU cop, eFlagsRegU cr, eRegP dst, memory src) %{
7913 // predicate(VM_Version::supports_cmov() );
7914 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
7915 // ins_cost(250);
7916 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
7917 // opcode(0x0F,0x40);
7918 // ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7919 // ins_pipe( pipe_cmov_mem );
7920 //%}
7921
7922 // Conditional move
7923 instruct fcmovD_regU(cmpOp_fcmov cop, eFlagsRegU cr, regDPR1 dst, regD src) %{
7924 predicate(UseSSE<=1);
7925 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7926 ins_cost(200);
7927 format %{ "FCMOV$cop $dst,$src\t# double" %}
7928 opcode(0xDA);
7929 ins_encode( enc_cmov_d(cop,src) );
7930 ins_pipe( pipe_cmovD_reg );
7931 %}
7932
7933 // Conditional move
7934 instruct fcmovF_regU(cmpOp_fcmov cop, eFlagsRegU cr, regFPR1 dst, regF src) %{
7935 predicate(UseSSE==0);
7936 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7937 ins_cost(200);
7938 format %{ "FCMOV$cop $dst,$src\t# float" %}
7939 opcode(0xDA);
7940 ins_encode( enc_cmov_d(cop,src) );
7941 ins_pipe( pipe_cmovD_reg );
7942 %}
7943
7944 // Float CMOV on Intel doesn't handle *signed* compares, only unsigned.
7945 instruct fcmovD_regS(cmpOp cop, eFlagsReg cr, regD dst, regD src) %{
7946 predicate(UseSSE<=1);
7947 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7948 ins_cost(200);
7949 format %{ "Jn$cop skip\n\t"
7950 "MOV $dst,$src\t# double\n"
7951 "skip:" %}
7952 opcode (0xdd, 0x3); /* DD D8+i or DD /3 */
7953 ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_D(src), OpcP, RegOpc(dst) );
7954 ins_pipe( pipe_cmovD_reg );
7955 %}
7956
7957 // Float CMOV on Intel doesn't handle *signed* compares, only unsigned.
7958 instruct fcmovF_regS(cmpOp cop, eFlagsReg cr, regF dst, regF src) %{
7959 predicate(UseSSE==0);
7960 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7961 ins_cost(200);
7962 format %{ "Jn$cop skip\n\t"
7963 "MOV $dst,$src\t# float\n"
7964 "skip:" %}
7965 opcode (0xdd, 0x3); /* DD D8+i or DD /3 */
7966 ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_F(src), OpcP, RegOpc(dst) );
7967 ins_pipe( pipe_cmovD_reg );
7968 %}
7969
7970 // No CMOVE with SSE/SSE2
7971 instruct fcmovX_regS(cmpOp cop, eFlagsReg cr, regX dst, regX src) %{
7972 predicate (UseSSE>=1);
7973 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7974 ins_cost(200);
7975 format %{ "Jn$cop skip\n\t"
7976 "MOVSS $dst,$src\t# float\n"
7977 "skip:" %}
7978 ins_encode %{
7979 Label skip;
7980 // Invert sense of branch from sense of CMOV
7981 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
7982 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
7983 __ bind(skip);
7984 %}
7985 ins_pipe( pipe_slow );
7986 %}
7987
7988 // No CMOVE with SSE/SSE2
7989 instruct fcmovXD_regS(cmpOp cop, eFlagsReg cr, regXD dst, regXD src) %{
7990 predicate (UseSSE>=2);
7991 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7992 ins_cost(200);
7993 format %{ "Jn$cop skip\n\t"
7994 "MOVSD $dst,$src\t# float\n"
7995 "skip:" %}
7996 ins_encode %{
7997 Label skip;
7998 // Invert sense of branch from sense of CMOV
7999 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
8000 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
8001 __ bind(skip);
8002 %}
8003 ins_pipe( pipe_slow );
8004 %}
8005
8006 // unsigned version
8007 instruct fcmovX_regU(cmpOpU cop, eFlagsRegU cr, regX dst, regX src) %{
8008 predicate (UseSSE>=1);
8009 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
8010 ins_cost(200);
8011 format %{ "Jn$cop skip\n\t"
8012 "MOVSS $dst,$src\t# float\n"
8013 "skip:" %}
8014 ins_encode %{
8015 Label skip;
8016 // Invert sense of branch from sense of CMOV
8017 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
8018 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
8019 __ bind(skip);
8020 %}
8021 ins_pipe( pipe_slow );
8022 %}
8023
8024 instruct fcmovX_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, regX dst, regX src) %{
8025 predicate (UseSSE>=1);
8026 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
8027 ins_cost(200);
8028 expand %{
8029 fcmovX_regU(cop, cr, dst, src);
8030 %}
8031 %}
8032
8033 // unsigned version
8034 instruct fcmovXD_regU(cmpOpU cop, eFlagsRegU cr, regXD dst, regXD src) %{
8035 predicate (UseSSE>=2);
8036 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
8037 ins_cost(200);
8038 format %{ "Jn$cop skip\n\t"
8039 "MOVSD $dst,$src\t# float\n"
8040 "skip:" %}
8041 ins_encode %{
8042 Label skip;
8043 // Invert sense of branch from sense of CMOV
8044 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
8045 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
8046 __ bind(skip);
8047 %}
8048 ins_pipe( pipe_slow );
8049 %}
8050
8051 instruct fcmovXD_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, regXD dst, regXD src) %{
8052 predicate (UseSSE>=2);
8053 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
8054 ins_cost(200);
8055 expand %{
8056 fcmovXD_regU(cop, cr, dst, src);
8057 %}
8058 %}
8059
8060 instruct cmovL_reg(cmpOp cop, eFlagsReg cr, eRegL dst, eRegL src) %{
8061 predicate(VM_Version::supports_cmov() );
8062 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
8063 ins_cost(200);
8064 format %{ "CMOV$cop $dst.lo,$src.lo\n\t"
8065 "CMOV$cop $dst.hi,$src.hi" %}
8066 opcode(0x0F,0x40);
8067 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) );
8068 ins_pipe( pipe_cmov_reg_long );
8069 %}
8070
8071 instruct cmovL_regU(cmpOpU cop, eFlagsRegU cr, eRegL dst, eRegL src) %{
8072 predicate(VM_Version::supports_cmov() );
8073 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
8074 ins_cost(200);
8075 format %{ "CMOV$cop $dst.lo,$src.lo\n\t"
8076 "CMOV$cop $dst.hi,$src.hi" %}
8077 opcode(0x0F,0x40);
8078 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) );
8079 ins_pipe( pipe_cmov_reg_long );
8080 %}
8081
8082 instruct cmovL_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegL dst, eRegL src) %{
8083 predicate(VM_Version::supports_cmov() );
8084 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
8085 ins_cost(200);
8086 expand %{
8087 cmovL_regU(cop, cr, dst, src);
8088 %}
8089 %}
8090
8091 //----------Arithmetic Instructions--------------------------------------------
8092 //----------Addition Instructions----------------------------------------------
8093 // Integer Addition Instructions
8094 instruct addI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
8095 match(Set dst (AddI dst src));
8096 effect(KILL cr);
8097
8098 size(2);
8099 format %{ "ADD $dst,$src" %}
8100 opcode(0x03);
8101 ins_encode( OpcP, RegReg( dst, src) );
8102 ins_pipe( ialu_reg_reg );
8103 %}
8104
8105 instruct addI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{
8106 match(Set dst (AddI dst src));
8107 effect(KILL cr);
8108
8109 format %{ "ADD $dst,$src" %}
8110 opcode(0x81, 0x00); /* /0 id */
8111 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8112 ins_pipe( ialu_reg );
8113 %}
8114
8115 instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
8116 predicate(UseIncDec);
8117 match(Set dst (AddI dst src));
8118 effect(KILL cr);
8119
8120 size(1);
8121 format %{ "INC $dst" %}
8122 opcode(0x40); /* */
8123 ins_encode( Opc_plus( primary, dst ) );
8124 ins_pipe( ialu_reg );
8125 %}
8126
8127 instruct leaI_eReg_immI(eRegI dst, eRegI src0, immI src1) %{
8128 match(Set dst (AddI src0 src1));
8129 ins_cost(110);
8130
8131 format %{ "LEA $dst,[$src0 + $src1]" %}
8132 opcode(0x8D); /* 0x8D /r */
8133 ins_encode( OpcP, RegLea( dst, src0, src1 ) );
8134 ins_pipe( ialu_reg_reg );
8135 %}
8136
8137 instruct leaP_eReg_immI(eRegP dst, eRegP src0, immI src1) %{
8138 match(Set dst (AddP src0 src1));
8139 ins_cost(110);
8140
8141 format %{ "LEA $dst,[$src0 + $src1]\t# ptr" %}
8142 opcode(0x8D); /* 0x8D /r */
8143 ins_encode( OpcP, RegLea( dst, src0, src1 ) );
8144 ins_pipe( ialu_reg_reg );
8145 %}
8146
8147 instruct decI_eReg(eRegI dst, immI_M1 src, eFlagsReg cr) %{
8148 predicate(UseIncDec);
8149 match(Set dst (AddI dst src));
8150 effect(KILL cr);
8151
8152 size(1);
8153 format %{ "DEC $dst" %}
8154 opcode(0x48); /* */
8155 ins_encode( Opc_plus( primary, dst ) );
8156 ins_pipe( ialu_reg );
8157 %}
8158
8159 instruct addP_eReg(eRegP dst, eRegI src, eFlagsReg cr) %{
8160 match(Set dst (AddP dst src));
8161 effect(KILL cr);
8162
8163 size(2);
8164 format %{ "ADD $dst,$src" %}
8165 opcode(0x03);
8166 ins_encode( OpcP, RegReg( dst, src) );
8167 ins_pipe( ialu_reg_reg );
8168 %}
8169
8170 instruct addP_eReg_imm(eRegP dst, immI src, eFlagsReg cr) %{
8171 match(Set dst (AddP dst src));
8172 effect(KILL cr);
8173
8174 format %{ "ADD $dst,$src" %}
8175 opcode(0x81,0x00); /* Opcode 81 /0 id */
8176 // ins_encode( RegImm( dst, src) );
8177 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8178 ins_pipe( ialu_reg );
8179 %}
8180
8181 instruct addI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{
8182 match(Set dst (AddI dst (LoadI src)));
8183 effect(KILL cr);
8184
8185 ins_cost(125);
8186 format %{ "ADD $dst,$src" %}
8187 opcode(0x03);
8188 ins_encode( OpcP, RegMem( dst, src) );
8189 ins_pipe( ialu_reg_mem );
8190 %}
8191
8192 instruct addI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{
8193 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
8194 effect(KILL cr);
8195
8196 ins_cost(150);
8197 format %{ "ADD $dst,$src" %}
8198 opcode(0x01); /* Opcode 01 /r */
8199 ins_encode( OpcP, RegMem( src, dst ) );
8200 ins_pipe( ialu_mem_reg );
8201 %}
8202
8203 // Add Memory with Immediate
8204 instruct addI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
8205 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
8206 effect(KILL cr);
8207
8208 ins_cost(125);
8209 format %{ "ADD $dst,$src" %}
8210 opcode(0x81); /* Opcode 81 /0 id */
8211 ins_encode( OpcSE( src ), RMopc_Mem(0x00,dst), Con8or32( src ) );
8212 ins_pipe( ialu_mem_imm );
8213 %}
8214
8215 instruct incI_mem(memory dst, immI1 src, eFlagsReg cr) %{
8216 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
8217 effect(KILL cr);
8218
8219 ins_cost(125);
8220 format %{ "INC $dst" %}
8221 opcode(0xFF); /* Opcode FF /0 */
8222 ins_encode( OpcP, RMopc_Mem(0x00,dst));
8223 ins_pipe( ialu_mem_imm );
8224 %}
8225
8226 instruct decI_mem(memory dst, immI_M1 src, eFlagsReg cr) %{
8227 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
8228 effect(KILL cr);
8229
8230 ins_cost(125);
8231 format %{ "DEC $dst" %}
8232 opcode(0xFF); /* Opcode FF /1 */
8233 ins_encode( OpcP, RMopc_Mem(0x01,dst));
8234 ins_pipe( ialu_mem_imm );
8235 %}
8236
8237
8238 instruct checkCastPP( eRegP dst ) %{
8239 match(Set dst (CheckCastPP dst));
8240
8241 size(0);
8242 format %{ "#checkcastPP of $dst" %}
8243 ins_encode( /*empty encoding*/ );
8244 ins_pipe( empty );
8245 %}
8246
8247 instruct castPP( eRegP dst ) %{
8248 match(Set dst (CastPP dst));
8249 format %{ "#castPP of $dst" %}
8250 ins_encode( /*empty encoding*/ );
8251 ins_pipe( empty );
8252 %}
8253
8254 instruct castII( eRegI dst ) %{
8255 match(Set dst (CastII dst));
8256 format %{ "#castII of $dst" %}
8257 ins_encode( /*empty encoding*/ );
8258 ins_cost(0);
8259 ins_pipe( empty );
8260 %}
8261
8262
8263 // Load-locked - same as a regular pointer load when used with compare-swap
8264 instruct loadPLocked(eRegP dst, memory mem) %{
8265 match(Set dst (LoadPLocked mem));
8266
8267 ins_cost(125);
8268 format %{ "MOV $dst,$mem\t# Load ptr. locked" %}
8269 opcode(0x8B);
8270 ins_encode( OpcP, RegMem(dst,mem));
8271 ins_pipe( ialu_reg_mem );
8272 %}
8273
8274 // LoadLong-locked - same as a volatile long load when used with compare-swap
8275 instruct loadLLocked(stackSlotL dst, load_long_memory mem) %{
8276 predicate(UseSSE<=1);
8277 match(Set dst (LoadLLocked mem));
8278
8279 ins_cost(200);
8280 format %{ "FILD $mem\t# Atomic volatile long load\n\t"
8281 "FISTp $dst" %}
8282 ins_encode(enc_loadL_volatile(mem,dst));
8283 ins_pipe( fpu_reg_mem );
8284 %}
8285
8286 instruct loadLX_Locked(stackSlotL dst, load_long_memory mem, regXD tmp) %{
8287 predicate(UseSSE>=2);
8288 match(Set dst (LoadLLocked mem));
8289 effect(TEMP tmp);
8290 ins_cost(180);
8291 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
8292 "MOVSD $dst,$tmp" %}
8293 ins_encode(enc_loadLX_volatile(mem, dst, tmp));
8294 ins_pipe( pipe_slow );
8295 %}
8296
8297 instruct loadLX_reg_Locked(eRegL dst, load_long_memory mem, regXD tmp) %{
8298 predicate(UseSSE>=2);
8299 match(Set dst (LoadLLocked mem));
8300 effect(TEMP tmp);
8301 ins_cost(160);
8302 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
8303 "MOVD $dst.lo,$tmp\n\t"
8304 "PSRLQ $tmp,32\n\t"
8305 "MOVD $dst.hi,$tmp" %}
8306 ins_encode(enc_loadLX_reg_volatile(mem, dst, tmp));
8307 ins_pipe( pipe_slow );
8308 %}
8309
8310 // Conditional-store of the updated heap-top.
8311 // Used during allocation of the shared heap.
8312 // Sets flags (EQ) on success. Implemented with a CMPXCHG on Intel.
8313 instruct storePConditional( memory heap_top_ptr, eAXRegP oldval, eRegP newval, eFlagsReg cr ) %{
8314 match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval)));
8315 // EAX is killed if there is contention, but then it's also unused.
8316 // In the common case of no contention, EAX holds the new oop address.
8317 format %{ "CMPXCHG $heap_top_ptr,$newval\t# If EAX==$heap_top_ptr Then store $newval into $heap_top_ptr" %}
8318 ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval,heap_top_ptr) );
8319 ins_pipe( pipe_cmpxchg );
8320 %}
8321
8322 // Conditional-store of an int value.
8323 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG on Intel.
8324 instruct storeIConditional( memory mem, eAXRegI oldval, eRegI newval, eFlagsReg cr ) %{
8325 match(Set cr (StoreIConditional mem (Binary oldval newval)));
8326 effect(KILL oldval);
8327 format %{ "CMPXCHG $mem,$newval\t# If EAX==$mem Then store $newval into $mem" %}
8328 ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval, mem) );
8329 ins_pipe( pipe_cmpxchg );
8330 %}
8331
8332 // Conditional-store of a long value.
8333 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG8 on Intel.
8334 instruct storeLConditional( memory mem, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{
8335 match(Set cr (StoreLConditional mem (Binary oldval newval)));
8336 effect(KILL oldval);
8337 format %{ "XCHG EBX,ECX\t# correct order for CMPXCHG8 instruction\n\t"
8338 "CMPXCHG8 $mem,ECX:EBX\t# If EDX:EAX==$mem Then store ECX:EBX into $mem\n\t"
8339 "XCHG EBX,ECX"
8340 %}
8341 ins_encode %{
8342 // Note: we need to swap rbx, and rcx before and after the
8343 // cmpxchg8 instruction because the instruction uses
8344 // rcx as the high order word of the new value to store but
8345 // our register encoding uses rbx.
8346 __ xchgl(as_Register(EBX_enc), as_Register(ECX_enc));
8347 if( os::is_MP() )
8348 __ lock();
8349 __ cmpxchg8($mem$$Address);
8350 __ xchgl(as_Register(EBX_enc), as_Register(ECX_enc));
8351 %}
8352 ins_pipe( pipe_cmpxchg );
8353 %}
8354
8355 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
8356
8357 instruct compareAndSwapL( eRegI res, eSIRegP mem_ptr, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{
8358 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
8359 effect(KILL cr, KILL oldval);
8360 format %{ "CMPXCHG8 [$mem_ptr],$newval\t# If EDX:EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
8361 "MOV $res,0\n\t"
8362 "JNE,s fail\n\t"
8363 "MOV $res,1\n"
8364 "fail:" %}
8365 ins_encode( enc_cmpxchg8(mem_ptr),
8366 enc_flags_ne_to_boolean(res) );
8367 ins_pipe( pipe_cmpxchg );
8368 %}
8369
8370 instruct compareAndSwapP( eRegI res, pRegP mem_ptr, eAXRegP oldval, eCXRegP newval, eFlagsReg cr) %{
8371 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
8372 effect(KILL cr, KILL oldval);
8373 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
8374 "MOV $res,0\n\t"
8375 "JNE,s fail\n\t"
8376 "MOV $res,1\n"
8377 "fail:" %}
8378 ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) );
8379 ins_pipe( pipe_cmpxchg );
8380 %}
8381
8382 instruct compareAndSwapI( eRegI res, pRegP mem_ptr, eAXRegI oldval, eCXRegI newval, eFlagsReg cr) %{
8383 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
8384 effect(KILL cr, KILL oldval);
8385 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
8386 "MOV $res,0\n\t"
8387 "JNE,s fail\n\t"
8388 "MOV $res,1\n"
8389 "fail:" %}
8390 ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) );
8391 ins_pipe( pipe_cmpxchg );
8392 %}
8393
8394 //----------Subtraction Instructions-------------------------------------------
8395 // Integer Subtraction Instructions
8396 instruct subI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
8397 match(Set dst (SubI dst src));
8398 effect(KILL cr);
8399
8400 size(2);
8401 format %{ "SUB $dst,$src" %}
8402 opcode(0x2B);
8403 ins_encode( OpcP, RegReg( dst, src) );
8404 ins_pipe( ialu_reg_reg );
8405 %}
8406
8407 instruct subI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{
8408 match(Set dst (SubI dst src));
8409 effect(KILL cr);
8410
8411 format %{ "SUB $dst,$src" %}
8412 opcode(0x81,0x05); /* Opcode 81 /5 */
8413 // ins_encode( RegImm( dst, src) );
8414 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8415 ins_pipe( ialu_reg );
8416 %}
8417
8418 instruct subI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{
8419 match(Set dst (SubI dst (LoadI src)));
8420 effect(KILL cr);
8421
8422 ins_cost(125);
8423 format %{ "SUB $dst,$src" %}
8424 opcode(0x2B);
8425 ins_encode( OpcP, RegMem( dst, src) );
8426 ins_pipe( ialu_reg_mem );
8427 %}
8428
8429 instruct subI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{
8430 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
8431 effect(KILL cr);
8432
8433 ins_cost(150);
8434 format %{ "SUB $dst,$src" %}
8435 opcode(0x29); /* Opcode 29 /r */
8436 ins_encode( OpcP, RegMem( src, dst ) );
8437 ins_pipe( ialu_mem_reg );
8438 %}
8439
8440 // Subtract from a pointer
8441 instruct subP_eReg(eRegP dst, eRegI src, immI0 zero, eFlagsReg cr) %{
8442 match(Set dst (AddP dst (SubI zero src)));
8443 effect(KILL cr);
8444
8445 size(2);
8446 format %{ "SUB $dst,$src" %}
8447 opcode(0x2B);
8448 ins_encode( OpcP, RegReg( dst, src) );
8449 ins_pipe( ialu_reg_reg );
8450 %}
8451
8452 instruct negI_eReg(eRegI dst, immI0 zero, eFlagsReg cr) %{
8453 match(Set dst (SubI zero dst));
8454 effect(KILL cr);
8455
8456 size(2);
8457 format %{ "NEG $dst" %}
8458 opcode(0xF7,0x03); // Opcode F7 /3
8459 ins_encode( OpcP, RegOpc( dst ) );
8460 ins_pipe( ialu_reg );
8461 %}
8462
8463
8464 //----------Multiplication/Division Instructions-------------------------------
8465 // Integer Multiplication Instructions
8466 // Multiply Register
8467 instruct mulI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
8468 match(Set dst (MulI dst src));
8469 effect(KILL cr);
8470
8471 size(3);
8472 ins_cost(300);
8473 format %{ "IMUL $dst,$src" %}
8474 opcode(0xAF, 0x0F);
8475 ins_encode( OpcS, OpcP, RegReg( dst, src) );
8476 ins_pipe( ialu_reg_reg_alu0 );
8477 %}
8478
8479 // Multiply 32-bit Immediate
8480 instruct mulI_eReg_imm(eRegI dst, eRegI src, immI imm, eFlagsReg cr) %{
8481 match(Set dst (MulI src imm));
8482 effect(KILL cr);
8483
8484 ins_cost(300);
8485 format %{ "IMUL $dst,$src,$imm" %}
8486 opcode(0x69); /* 69 /r id */
8487 ins_encode( OpcSE(imm), RegReg( dst, src ), Con8or32( imm ) );
8488 ins_pipe( ialu_reg_reg_alu0 );
8489 %}
8490
8491 instruct loadConL_low_only(eADXRegL_low_only dst, immL32 src, eFlagsReg cr) %{
8492 match(Set dst src);
8493 effect(KILL cr);
8494
8495 // Note that this is artificially increased to make it more expensive than loadConL
8496 ins_cost(250);
8497 format %{ "MOV EAX,$src\t// low word only" %}
8498 opcode(0xB8);
8499 ins_encode( LdImmL_Lo(dst, src) );
8500 ins_pipe( ialu_reg_fat );
8501 %}
8502
8503 // Multiply by 32-bit Immediate, taking the shifted high order results
8504 // (special case for shift by 32)
8505 instruct mulI_imm_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32 cnt, eFlagsReg cr) %{
8506 match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt)));
8507 predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL &&
8508 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint &&
8509 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint );
8510 effect(USE src1, KILL cr);
8511
8512 // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only
8513 ins_cost(0*100 + 1*400 - 150);
8514 format %{ "IMUL EDX:EAX,$src1" %}
8515 ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) );
8516 ins_pipe( pipe_slow );
8517 %}
8518
8519 // Multiply by 32-bit Immediate, taking the shifted high order results
8520 instruct mulI_imm_RShift_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr) %{
8521 match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt)));
8522 predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL &&
8523 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint &&
8524 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint );
8525 effect(USE src1, KILL cr);
8526
8527 // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only
8528 ins_cost(1*100 + 1*400 - 150);
8529 format %{ "IMUL EDX:EAX,$src1\n\t"
8530 "SAR EDX,$cnt-32" %}
8531 ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) );
8532 ins_pipe( pipe_slow );
8533 %}
8534
8535 // Multiply Memory 32-bit Immediate
8536 instruct mulI_mem_imm(eRegI dst, memory src, immI imm, eFlagsReg cr) %{
8537 match(Set dst (MulI (LoadI src) imm));
8538 effect(KILL cr);
8539
8540 ins_cost(300);
8541 format %{ "IMUL $dst,$src,$imm" %}
8542 opcode(0x69); /* 69 /r id */
8543 ins_encode( OpcSE(imm), RegMem( dst, src ), Con8or32( imm ) );
8544 ins_pipe( ialu_reg_mem_alu0 );
8545 %}
8546
8547 // Multiply Memory
8548 instruct mulI(eRegI dst, memory src, eFlagsReg cr) %{
8549 match(Set dst (MulI dst (LoadI src)));
8550 effect(KILL cr);
8551
8552 ins_cost(350);
8553 format %{ "IMUL $dst,$src" %}
8554 opcode(0xAF, 0x0F);
8555 ins_encode( OpcS, OpcP, RegMem( dst, src) );
8556 ins_pipe( ialu_reg_mem_alu0 );
8557 %}
8558
8559 // Multiply Register Int to Long
8560 instruct mulI2L(eADXRegL dst, eAXRegI src, nadxRegI src1, eFlagsReg flags) %{
8561 // Basic Idea: long = (long)int * (long)int
8562 match(Set dst (MulL (ConvI2L src) (ConvI2L src1)));
8563 effect(DEF dst, USE src, USE src1, KILL flags);
8564
8565 ins_cost(300);
8566 format %{ "IMUL $dst,$src1" %}
8567
8568 ins_encode( long_int_multiply( dst, src1 ) );
8569 ins_pipe( ialu_reg_reg_alu0 );
8570 %}
8571
8572 instruct mulIS_eReg(eADXRegL dst, immL_32bits mask, eFlagsReg flags, eAXRegI src, nadxRegI src1) %{
8573 // Basic Idea: long = (int & 0xffffffffL) * (int & 0xffffffffL)
8574 match(Set dst (MulL (AndL (ConvI2L src) mask) (AndL (ConvI2L src1) mask)));
8575 effect(KILL flags);
8576
8577 ins_cost(300);
8578 format %{ "MUL $dst,$src1" %}
8579
8580 ins_encode( long_uint_multiply(dst, src1) );
8581 ins_pipe( ialu_reg_reg_alu0 );
8582 %}
8583
8584 // Multiply Register Long
8585 instruct mulL_eReg(eADXRegL dst, eRegL src, eRegI tmp, eFlagsReg cr) %{
8586 match(Set dst (MulL dst src));
8587 effect(KILL cr, TEMP tmp);
8588 ins_cost(4*100+3*400);
8589 // Basic idea: lo(result) = lo(x_lo * y_lo)
8590 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
8591 format %{ "MOV $tmp,$src.lo\n\t"
8592 "IMUL $tmp,EDX\n\t"
8593 "MOV EDX,$src.hi\n\t"
8594 "IMUL EDX,EAX\n\t"
8595 "ADD $tmp,EDX\n\t"
8596 "MUL EDX:EAX,$src.lo\n\t"
8597 "ADD EDX,$tmp" %}
8598 ins_encode( long_multiply( dst, src, tmp ) );
8599 ins_pipe( pipe_slow );
8600 %}
8601
8602 // Multiply Register Long by small constant
8603 instruct mulL_eReg_con(eADXRegL dst, immL_127 src, eRegI tmp, eFlagsReg cr) %{
8604 match(Set dst (MulL dst src));
8605 effect(KILL cr, TEMP tmp);
8606 ins_cost(2*100+2*400);
8607 size(12);
8608 // Basic idea: lo(result) = lo(src * EAX)
8609 // hi(result) = hi(src * EAX) + lo(src * EDX)
8610 format %{ "IMUL $tmp,EDX,$src\n\t"
8611 "MOV EDX,$src\n\t"
8612 "MUL EDX\t# EDX*EAX -> EDX:EAX\n\t"
8613 "ADD EDX,$tmp" %}
8614 ins_encode( long_multiply_con( dst, src, tmp ) );
8615 ins_pipe( pipe_slow );
8616 %}
8617
8618 // Integer DIV with Register
8619 instruct divI_eReg(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{
8620 match(Set rax (DivI rax div));
8621 effect(KILL rdx, KILL cr);
8622 size(26);
8623 ins_cost(30*100+10*100);
8624 format %{ "CMP EAX,0x80000000\n\t"
8625 "JNE,s normal\n\t"
8626 "XOR EDX,EDX\n\t"
8627 "CMP ECX,-1\n\t"
8628 "JE,s done\n"
8629 "normal: CDQ\n\t"
8630 "IDIV $div\n\t"
8631 "done:" %}
8632 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8633 ins_encode( cdq_enc, OpcP, RegOpc(div) );
8634 ins_pipe( ialu_reg_reg_alu0 );
8635 %}
8636
8637 // Divide Register Long
8638 instruct divL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{
8639 match(Set dst (DivL src1 src2));
8640 effect( KILL cr, KILL cx, KILL bx );
8641 ins_cost(10000);
8642 format %{ "PUSH $src1.hi\n\t"
8643 "PUSH $src1.lo\n\t"
8644 "PUSH $src2.hi\n\t"
8645 "PUSH $src2.lo\n\t"
8646 "CALL SharedRuntime::ldiv\n\t"
8647 "ADD ESP,16" %}
8648 ins_encode( long_div(src1,src2) );
8649 ins_pipe( pipe_slow );
8650 %}
8651
8652 // Integer DIVMOD with Register, both quotient and mod results
8653 instruct divModI_eReg_divmod(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{
8654 match(DivModI rax div);
8655 effect(KILL cr);
8656 size(26);
8657 ins_cost(30*100+10*100);
8658 format %{ "CMP EAX,0x80000000\n\t"
8659 "JNE,s normal\n\t"
8660 "XOR EDX,EDX\n\t"
8661 "CMP ECX,-1\n\t"
8662 "JE,s done\n"
8663 "normal: CDQ\n\t"
8664 "IDIV $div\n\t"
8665 "done:" %}
8666 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8667 ins_encode( cdq_enc, OpcP, RegOpc(div) );
8668 ins_pipe( pipe_slow );
8669 %}
8670
8671 // Integer MOD with Register
8672 instruct modI_eReg(eDXRegI rdx, eAXRegI rax, eCXRegI div, eFlagsReg cr) %{
8673 match(Set rdx (ModI rax div));
8674 effect(KILL rax, KILL cr);
8675
8676 size(26);
8677 ins_cost(300);
8678 format %{ "CDQ\n\t"
8679 "IDIV $div" %}
8680 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8681 ins_encode( cdq_enc, OpcP, RegOpc(div) );
8682 ins_pipe( ialu_reg_reg_alu0 );
8683 %}
8684
8685 // Remainder Register Long
8686 instruct modL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{
8687 match(Set dst (ModL src1 src2));
8688 effect( KILL cr, KILL cx, KILL bx );
8689 ins_cost(10000);
8690 format %{ "PUSH $src1.hi\n\t"
8691 "PUSH $src1.lo\n\t"
8692 "PUSH $src2.hi\n\t"
8693 "PUSH $src2.lo\n\t"
8694 "CALL SharedRuntime::lrem\n\t"
8695 "ADD ESP,16" %}
8696 ins_encode( long_mod(src1,src2) );
8697 ins_pipe( pipe_slow );
8698 %}
8699
8700 // Integer Shift Instructions
8701 // Shift Left by one
8702 instruct shlI_eReg_1(eRegI dst, immI1 shift, eFlagsReg cr) %{
8703 match(Set dst (LShiftI dst shift));
8704 effect(KILL cr);
8705
8706 size(2);
8707 format %{ "SHL $dst,$shift" %}
8708 opcode(0xD1, 0x4); /* D1 /4 */
8709 ins_encode( OpcP, RegOpc( dst ) );
8710 ins_pipe( ialu_reg );
8711 %}
8712
8713 // Shift Left by 8-bit immediate
8714 instruct salI_eReg_imm(eRegI dst, immI8 shift, eFlagsReg cr) %{
8715 match(Set dst (LShiftI dst shift));
8716 effect(KILL cr);
8717
8718 size(3);
8719 format %{ "SHL $dst,$shift" %}
8720 opcode(0xC1, 0x4); /* C1 /4 ib */
8721 ins_encode( RegOpcImm( dst, shift) );
8722 ins_pipe( ialu_reg );
8723 %}
8724
8725 // Shift Left by variable
8726 instruct salI_eReg_CL(eRegI dst, eCXRegI shift, eFlagsReg cr) %{
8727 match(Set dst (LShiftI dst shift));
8728 effect(KILL cr);
8729
8730 size(2);
8731 format %{ "SHL $dst,$shift" %}
8732 opcode(0xD3, 0x4); /* D3 /4 */
8733 ins_encode( OpcP, RegOpc( dst ) );
8734 ins_pipe( ialu_reg_reg );
8735 %}
8736
8737 // Arithmetic shift right by one
8738 instruct sarI_eReg_1(eRegI dst, immI1 shift, eFlagsReg cr) %{
8739 match(Set dst (RShiftI dst shift));
8740 effect(KILL cr);
8741
8742 size(2);
8743 format %{ "SAR $dst,$shift" %}
8744 opcode(0xD1, 0x7); /* D1 /7 */
8745 ins_encode( OpcP, RegOpc( dst ) );
8746 ins_pipe( ialu_reg );
8747 %}
8748
8749 // Arithmetic shift right by one
8750 instruct sarI_mem_1(memory dst, immI1 shift, eFlagsReg cr) %{
8751 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8752 effect(KILL cr);
8753 format %{ "SAR $dst,$shift" %}
8754 opcode(0xD1, 0x7); /* D1 /7 */
8755 ins_encode( OpcP, RMopc_Mem(secondary,dst) );
8756 ins_pipe( ialu_mem_imm );
8757 %}
8758
8759 // Arithmetic Shift Right by 8-bit immediate
8760 instruct sarI_eReg_imm(eRegI dst, immI8 shift, eFlagsReg cr) %{
8761 match(Set dst (RShiftI dst shift));
8762 effect(KILL cr);
8763
8764 size(3);
8765 format %{ "SAR $dst,$shift" %}
8766 opcode(0xC1, 0x7); /* C1 /7 ib */
8767 ins_encode( RegOpcImm( dst, shift ) );
8768 ins_pipe( ialu_mem_imm );
8769 %}
8770
8771 // Arithmetic Shift Right by 8-bit immediate
8772 instruct sarI_mem_imm(memory dst, immI8 shift, eFlagsReg cr) %{
8773 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8774 effect(KILL cr);
8775
8776 format %{ "SAR $dst,$shift" %}
8777 opcode(0xC1, 0x7); /* C1 /7 ib */
8778 ins_encode( OpcP, RMopc_Mem(secondary, dst ), Con8or32( shift ) );
8779 ins_pipe( ialu_mem_imm );
8780 %}
8781
8782 // Arithmetic Shift Right by variable
8783 instruct sarI_eReg_CL(eRegI dst, eCXRegI shift, eFlagsReg cr) %{
8784 match(Set dst (RShiftI dst shift));
8785 effect(KILL cr);
8786
8787 size(2);
8788 format %{ "SAR $dst,$shift" %}
8789 opcode(0xD3, 0x7); /* D3 /7 */
8790 ins_encode( OpcP, RegOpc( dst ) );
8791 ins_pipe( ialu_reg_reg );
8792 %}
8793
8794 // Logical shift right by one
8795 instruct shrI_eReg_1(eRegI dst, immI1 shift, eFlagsReg cr) %{
8796 match(Set dst (URShiftI dst shift));
8797 effect(KILL cr);
8798
8799 size(2);
8800 format %{ "SHR $dst,$shift" %}
8801 opcode(0xD1, 0x5); /* D1 /5 */
8802 ins_encode( OpcP, RegOpc( dst ) );
8803 ins_pipe( ialu_reg );
8804 %}
8805
8806 // Logical Shift Right by 8-bit immediate
8807 instruct shrI_eReg_imm(eRegI dst, immI8 shift, eFlagsReg cr) %{
8808 match(Set dst (URShiftI dst shift));
8809 effect(KILL cr);
8810
8811 size(3);
8812 format %{ "SHR $dst,$shift" %}
8813 opcode(0xC1, 0x5); /* C1 /5 ib */
8814 ins_encode( RegOpcImm( dst, shift) );
8815 ins_pipe( ialu_reg );
8816 %}
8817
8818
8819 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24.
8820 // This idiom is used by the compiler for the i2b bytecode.
8821 instruct i2b(eRegI dst, xRegI src, immI_24 twentyfour) %{
8822 match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour));
8823
8824 size(3);
8825 format %{ "MOVSX $dst,$src :8" %}
8826 ins_encode %{
8827 __ movsbl($dst$$Register, $src$$Register);
8828 %}
8829 ins_pipe(ialu_reg_reg);
8830 %}
8831
8832 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16.
8833 // This idiom is used by the compiler the i2s bytecode.
8834 instruct i2s(eRegI dst, xRegI src, immI_16 sixteen) %{
8835 match(Set dst (RShiftI (LShiftI src sixteen) sixteen));
8836
8837 size(3);
8838 format %{ "MOVSX $dst,$src :16" %}
8839 ins_encode %{
8840 __ movswl($dst$$Register, $src$$Register);
8841 %}
8842 ins_pipe(ialu_reg_reg);
8843 %}
8844
8845
8846 // Logical Shift Right by variable
8847 instruct shrI_eReg_CL(eRegI dst, eCXRegI shift, eFlagsReg cr) %{
8848 match(Set dst (URShiftI dst shift));
8849 effect(KILL cr);
8850
8851 size(2);
8852 format %{ "SHR $dst,$shift" %}
8853 opcode(0xD3, 0x5); /* D3 /5 */
8854 ins_encode( OpcP, RegOpc( dst ) );
8855 ins_pipe( ialu_reg_reg );
8856 %}
8857
8858
8859 //----------Logical Instructions-----------------------------------------------
8860 //----------Integer Logical Instructions---------------------------------------
8861 // And Instructions
8862 // And Register with Register
8863 instruct andI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
8864 match(Set dst (AndI dst src));
8865 effect(KILL cr);
8866
8867 size(2);
8868 format %{ "AND $dst,$src" %}
8869 opcode(0x23);
8870 ins_encode( OpcP, RegReg( dst, src) );
8871 ins_pipe( ialu_reg_reg );
8872 %}
8873
8874 // And Register with Immediate
8875 instruct andI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{
8876 match(Set dst (AndI dst src));
8877 effect(KILL cr);
8878
8879 format %{ "AND $dst,$src" %}
8880 opcode(0x81,0x04); /* Opcode 81 /4 */
8881 // ins_encode( RegImm( dst, src) );
8882 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8883 ins_pipe( ialu_reg );
8884 %}
8885
8886 // And Register with Memory
8887 instruct andI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{
8888 match(Set dst (AndI dst (LoadI src)));
8889 effect(KILL cr);
8890
8891 ins_cost(125);
8892 format %{ "AND $dst,$src" %}
8893 opcode(0x23);
8894 ins_encode( OpcP, RegMem( dst, src) );
8895 ins_pipe( ialu_reg_mem );
8896 %}
8897
8898 // And Memory with Register
8899 instruct andI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{
8900 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
8901 effect(KILL cr);
8902
8903 ins_cost(150);
8904 format %{ "AND $dst,$src" %}
8905 opcode(0x21); /* Opcode 21 /r */
8906 ins_encode( OpcP, RegMem( src, dst ) );
8907 ins_pipe( ialu_mem_reg );
8908 %}
8909
8910 // And Memory with Immediate
8911 instruct andI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
8912 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
8913 effect(KILL cr);
8914
8915 ins_cost(125);
8916 format %{ "AND $dst,$src" %}
8917 opcode(0x81, 0x4); /* Opcode 81 /4 id */
8918 // ins_encode( MemImm( dst, src) );
8919 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
8920 ins_pipe( ialu_mem_imm );
8921 %}
8922
8923 // Or Instructions
8924 // Or Register with Register
8925 instruct orI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
8926 match(Set dst (OrI dst src));
8927 effect(KILL cr);
8928
8929 size(2);
8930 format %{ "OR $dst,$src" %}
8931 opcode(0x0B);
8932 ins_encode( OpcP, RegReg( dst, src) );
8933 ins_pipe( ialu_reg_reg );
8934 %}
8935
8936 instruct orI_eReg_castP2X(eRegI dst, eRegP src, eFlagsReg cr) %{
8937 match(Set dst (OrI dst (CastP2X src)));
8938 effect(KILL cr);
8939
8940 size(2);
8941 format %{ "OR $dst,$src" %}
8942 opcode(0x0B);
8943 ins_encode( OpcP, RegReg( dst, src) );
8944 ins_pipe( ialu_reg_reg );
8945 %}
8946
8947
8948 // Or Register with Immediate
8949 instruct orI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{
8950 match(Set dst (OrI dst src));
8951 effect(KILL cr);
8952
8953 format %{ "OR $dst,$src" %}
8954 opcode(0x81,0x01); /* Opcode 81 /1 id */
8955 // ins_encode( RegImm( dst, src) );
8956 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8957 ins_pipe( ialu_reg );
8958 %}
8959
8960 // Or Register with Memory
8961 instruct orI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{
8962 match(Set dst (OrI dst (LoadI src)));
8963 effect(KILL cr);
8964
8965 ins_cost(125);
8966 format %{ "OR $dst,$src" %}
8967 opcode(0x0B);
8968 ins_encode( OpcP, RegMem( dst, src) );
8969 ins_pipe( ialu_reg_mem );
8970 %}
8971
8972 // Or Memory with Register
8973 instruct orI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{
8974 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
8975 effect(KILL cr);
8976
8977 ins_cost(150);
8978 format %{ "OR $dst,$src" %}
8979 opcode(0x09); /* Opcode 09 /r */
8980 ins_encode( OpcP, RegMem( src, dst ) );
8981 ins_pipe( ialu_mem_reg );
8982 %}
8983
8984 // Or Memory with Immediate
8985 instruct orI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
8986 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
8987 effect(KILL cr);
8988
8989 ins_cost(125);
8990 format %{ "OR $dst,$src" %}
8991 opcode(0x81,0x1); /* Opcode 81 /1 id */
8992 // ins_encode( MemImm( dst, src) );
8993 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
8994 ins_pipe( ialu_mem_imm );
8995 %}
8996
8997 // ROL/ROR
8998 // ROL expand
8999 instruct rolI_eReg_imm1(eRegI dst, immI1 shift, eFlagsReg cr) %{
9000 effect(USE_DEF dst, USE shift, KILL cr);
9001
9002 format %{ "ROL $dst, $shift" %}
9003 opcode(0xD1, 0x0); /* Opcode D1 /0 */
9004 ins_encode( OpcP, RegOpc( dst ));
9005 ins_pipe( ialu_reg );
9006 %}
9007
9008 instruct rolI_eReg_imm8(eRegI dst, immI8 shift, eFlagsReg cr) %{
9009 effect(USE_DEF dst, USE shift, KILL cr);
9010
9011 format %{ "ROL $dst, $shift" %}
9012 opcode(0xC1, 0x0); /*Opcode /C1 /0 */
9013 ins_encode( RegOpcImm(dst, shift) );
9014 ins_pipe(ialu_reg);
9015 %}
9016
9017 instruct rolI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr) %{
9018 effect(USE_DEF dst, USE shift, KILL cr);
9019
9020 format %{ "ROL $dst, $shift" %}
9021 opcode(0xD3, 0x0); /* Opcode D3 /0 */
9022 ins_encode(OpcP, RegOpc(dst));
9023 ins_pipe( ialu_reg_reg );
9024 %}
9025 // end of ROL expand
9026
9027 // ROL 32bit by one once
9028 instruct rolI_eReg_i1(eRegI dst, immI1 lshift, immI_M1 rshift, eFlagsReg cr) %{
9029 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift)));
9030
9031 expand %{
9032 rolI_eReg_imm1(dst, lshift, cr);
9033 %}
9034 %}
9035
9036 // ROL 32bit var by imm8 once
9037 instruct rolI_eReg_i8(eRegI dst, immI8 lshift, immI8 rshift, eFlagsReg cr) %{
9038 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
9039 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift)));
9040
9041 expand %{
9042 rolI_eReg_imm8(dst, lshift, cr);
9043 %}
9044 %}
9045
9046 // ROL 32bit var by var once
9047 instruct rolI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{
9048 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI zero shift))));
9049
9050 expand %{
9051 rolI_eReg_CL(dst, shift, cr);
9052 %}
9053 %}
9054
9055 // ROL 32bit var by var once
9056 instruct rolI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{
9057 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI c32 shift))));
9058
9059 expand %{
9060 rolI_eReg_CL(dst, shift, cr);
9061 %}
9062 %}
9063
9064 // ROR expand
9065 instruct rorI_eReg_imm1(eRegI dst, immI1 shift, eFlagsReg cr) %{
9066 effect(USE_DEF dst, USE shift, KILL cr);
9067
9068 format %{ "ROR $dst, $shift" %}
9069 opcode(0xD1,0x1); /* Opcode D1 /1 */
9070 ins_encode( OpcP, RegOpc( dst ) );
9071 ins_pipe( ialu_reg );
9072 %}
9073
9074 instruct rorI_eReg_imm8(eRegI dst, immI8 shift, eFlagsReg cr) %{
9075 effect (USE_DEF dst, USE shift, KILL cr);
9076
9077 format %{ "ROR $dst, $shift" %}
9078 opcode(0xC1, 0x1); /* Opcode /C1 /1 ib */
9079 ins_encode( RegOpcImm(dst, shift) );
9080 ins_pipe( ialu_reg );
9081 %}
9082
9083 instruct rorI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr)%{
9084 effect(USE_DEF dst, USE shift, KILL cr);
9085
9086 format %{ "ROR $dst, $shift" %}
9087 opcode(0xD3, 0x1); /* Opcode D3 /1 */
9088 ins_encode(OpcP, RegOpc(dst));
9089 ins_pipe( ialu_reg_reg );
9090 %}
9091 // end of ROR expand
9092
9093 // ROR right once
9094 instruct rorI_eReg_i1(eRegI dst, immI1 rshift, immI_M1 lshift, eFlagsReg cr) %{
9095 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift)));
9096
9097 expand %{
9098 rorI_eReg_imm1(dst, rshift, cr);
9099 %}
9100 %}
9101
9102 // ROR 32bit by immI8 once
9103 instruct rorI_eReg_i8(eRegI dst, immI8 rshift, immI8 lshift, eFlagsReg cr) %{
9104 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
9105 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift)));
9106
9107 expand %{
9108 rorI_eReg_imm8(dst, rshift, cr);
9109 %}
9110 %}
9111
9112 // ROR 32bit var by var once
9113 instruct rorI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{
9114 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI zero shift))));
9115
9116 expand %{
9117 rorI_eReg_CL(dst, shift, cr);
9118 %}
9119 %}
9120
9121 // ROR 32bit var by var once
9122 instruct rorI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{
9123 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI c32 shift))));
9124
9125 expand %{
9126 rorI_eReg_CL(dst, shift, cr);
9127 %}
9128 %}
9129
9130 // Xor Instructions
9131 // Xor Register with Register
9132 instruct xorI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
9133 match(Set dst (XorI dst src));
9134 effect(KILL cr);
9135
9136 size(2);
9137 format %{ "XOR $dst,$src" %}
9138 opcode(0x33);
9139 ins_encode( OpcP, RegReg( dst, src) );
9140 ins_pipe( ialu_reg_reg );
9141 %}
9142
9143 // Xor Register with Immediate -1
9144 instruct xorI_eReg_im1(eRegI dst, immI_M1 imm) %{
9145 match(Set dst (XorI dst imm));
9146
9147 size(2);
9148 format %{ "NOT $dst" %}
9149 ins_encode %{
9150 __ notl($dst$$Register);
9151 %}
9152 ins_pipe( ialu_reg );
9153 %}
9154
9155 // Xor Register with Immediate
9156 instruct xorI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{
9157 match(Set dst (XorI dst src));
9158 effect(KILL cr);
9159
9160 format %{ "XOR $dst,$src" %}
9161 opcode(0x81,0x06); /* Opcode 81 /6 id */
9162 // ins_encode( RegImm( dst, src) );
9163 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
9164 ins_pipe( ialu_reg );
9165 %}
9166
9167 // Xor Register with Memory
9168 instruct xorI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{
9169 match(Set dst (XorI dst (LoadI src)));
9170 effect(KILL cr);
9171
9172 ins_cost(125);
9173 format %{ "XOR $dst,$src" %}
9174 opcode(0x33);
9175 ins_encode( OpcP, RegMem(dst, src) );
9176 ins_pipe( ialu_reg_mem );
9177 %}
9178
9179 // Xor Memory with Register
9180 instruct xorI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{
9181 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
9182 effect(KILL cr);
9183
9184 ins_cost(150);
9185 format %{ "XOR $dst,$src" %}
9186 opcode(0x31); /* Opcode 31 /r */
9187 ins_encode( OpcP, RegMem( src, dst ) );
9188 ins_pipe( ialu_mem_reg );
9189 %}
9190
9191 // Xor Memory with Immediate
9192 instruct xorI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
9193 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
9194 effect(KILL cr);
9195
9196 ins_cost(125);
9197 format %{ "XOR $dst,$src" %}
9198 opcode(0x81,0x6); /* Opcode 81 /6 id */
9199 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
9200 ins_pipe( ialu_mem_imm );
9201 %}
9202
9203 //----------Convert Int to Boolean---------------------------------------------
9204
9205 instruct movI_nocopy(eRegI dst, eRegI src) %{
9206 effect( DEF dst, USE src );
9207 format %{ "MOV $dst,$src" %}
9208 ins_encode( enc_Copy( dst, src) );
9209 ins_pipe( ialu_reg_reg );
9210 %}
9211
9212 instruct ci2b( eRegI dst, eRegI src, eFlagsReg cr ) %{
9213 effect( USE_DEF dst, USE src, KILL cr );
9214
9215 size(4);
9216 format %{ "NEG $dst\n\t"
9217 "ADC $dst,$src" %}
9218 ins_encode( neg_reg(dst),
9219 OpcRegReg(0x13,dst,src) );
9220 ins_pipe( ialu_reg_reg_long );
9221 %}
9222
9223 instruct convI2B( eRegI dst, eRegI src, eFlagsReg cr ) %{
9224 match(Set dst (Conv2B src));
9225
9226 expand %{
9227 movI_nocopy(dst,src);
9228 ci2b(dst,src,cr);
9229 %}
9230 %}
9231
9232 instruct movP_nocopy(eRegI dst, eRegP src) %{
9233 effect( DEF dst, USE src );
9234 format %{ "MOV $dst,$src" %}
9235 ins_encode( enc_Copy( dst, src) );
9236 ins_pipe( ialu_reg_reg );
9237 %}
9238
9239 instruct cp2b( eRegI dst, eRegP src, eFlagsReg cr ) %{
9240 effect( USE_DEF dst, USE src, KILL cr );
9241 format %{ "NEG $dst\n\t"
9242 "ADC $dst,$src" %}
9243 ins_encode( neg_reg(dst),
9244 OpcRegReg(0x13,dst,src) );
9245 ins_pipe( ialu_reg_reg_long );
9246 %}
9247
9248 instruct convP2B( eRegI dst, eRegP src, eFlagsReg cr ) %{
9249 match(Set dst (Conv2B src));
9250
9251 expand %{
9252 movP_nocopy(dst,src);
9253 cp2b(dst,src,cr);
9254 %}
9255 %}
9256
9257 instruct cmpLTMask( eCXRegI dst, ncxRegI p, ncxRegI q, eFlagsReg cr ) %{
9258 match(Set dst (CmpLTMask p q));
9259 effect( KILL cr );
9260 ins_cost(400);
9261
9262 // SETlt can only use low byte of EAX,EBX, ECX, or EDX as destination
9263 format %{ "XOR $dst,$dst\n\t"
9264 "CMP $p,$q\n\t"
9265 "SETlt $dst\n\t"
9266 "NEG $dst" %}
9267 ins_encode( OpcRegReg(0x33,dst,dst),
9268 OpcRegReg(0x3B,p,q),
9269 setLT_reg(dst), neg_reg(dst) );
9270 ins_pipe( pipe_slow );
9271 %}
9272
9273 instruct cmpLTMask0( eRegI dst, immI0 zero, eFlagsReg cr ) %{
9274 match(Set dst (CmpLTMask dst zero));
9275 effect( DEF dst, KILL cr );
9276 ins_cost(100);
9277
9278 format %{ "SAR $dst,31" %}
9279 opcode(0xC1, 0x7); /* C1 /7 ib */
9280 ins_encode( RegOpcImm( dst, 0x1F ) );
9281 ins_pipe( ialu_reg );
9282 %}
9283
9284
9285 instruct cadd_cmpLTMask( ncxRegI p, ncxRegI q, ncxRegI y, eCXRegI tmp, eFlagsReg cr ) %{
9286 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
9287 effect( KILL tmp, KILL cr );
9288 ins_cost(400);
9289 // annoyingly, $tmp has no edges so you cant ask for it in
9290 // any format or encoding
9291 format %{ "SUB $p,$q\n\t"
9292 "SBB ECX,ECX\n\t"
9293 "AND ECX,$y\n\t"
9294 "ADD $p,ECX" %}
9295 ins_encode( enc_cmpLTP(p,q,y,tmp) );
9296 ins_pipe( pipe_cmplt );
9297 %}
9298
9299 /* If I enable this, I encourage spilling in the inner loop of compress.
9300 instruct cadd_cmpLTMask_mem( ncxRegI p, ncxRegI q, memory y, eCXRegI tmp, eFlagsReg cr ) %{
9301 match(Set p (AddI (AndI (CmpLTMask p q) (LoadI y)) (SubI p q)));
9302 effect( USE_KILL tmp, KILL cr );
9303 ins_cost(400);
9304
9305 format %{ "SUB $p,$q\n\t"
9306 "SBB ECX,ECX\n\t"
9307 "AND ECX,$y\n\t"
9308 "ADD $p,ECX" %}
9309 ins_encode( enc_cmpLTP_mem(p,q,y,tmp) );
9310 %}
9311 */
9312
9313 //----------Long Instructions------------------------------------------------
9314 // Add Long Register with Register
9315 instruct addL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9316 match(Set dst (AddL dst src));
9317 effect(KILL cr);
9318 ins_cost(200);
9319 format %{ "ADD $dst.lo,$src.lo\n\t"
9320 "ADC $dst.hi,$src.hi" %}
9321 opcode(0x03, 0x13);
9322 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) );
9323 ins_pipe( ialu_reg_reg_long );
9324 %}
9325
9326 // Add Long Register with Immediate
9327 instruct addL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9328 match(Set dst (AddL dst src));
9329 effect(KILL cr);
9330 format %{ "ADD $dst.lo,$src.lo\n\t"
9331 "ADC $dst.hi,$src.hi" %}
9332 opcode(0x81,0x00,0x02); /* Opcode 81 /0, 81 /2 */
9333 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9334 ins_pipe( ialu_reg_long );
9335 %}
9336
9337 // Add Long Register with Memory
9338 instruct addL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9339 match(Set dst (AddL dst (LoadL mem)));
9340 effect(KILL cr);
9341 ins_cost(125);
9342 format %{ "ADD $dst.lo,$mem\n\t"
9343 "ADC $dst.hi,$mem+4" %}
9344 opcode(0x03, 0x13);
9345 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9346 ins_pipe( ialu_reg_long_mem );
9347 %}
9348
9349 // Subtract Long Register with Register.
9350 instruct subL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9351 match(Set dst (SubL dst src));
9352 effect(KILL cr);
9353 ins_cost(200);
9354 format %{ "SUB $dst.lo,$src.lo\n\t"
9355 "SBB $dst.hi,$src.hi" %}
9356 opcode(0x2B, 0x1B);
9357 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) );
9358 ins_pipe( ialu_reg_reg_long );
9359 %}
9360
9361 // Subtract Long Register with Immediate
9362 instruct subL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9363 match(Set dst (SubL dst src));
9364 effect(KILL cr);
9365 format %{ "SUB $dst.lo,$src.lo\n\t"
9366 "SBB $dst.hi,$src.hi" %}
9367 opcode(0x81,0x05,0x03); /* Opcode 81 /5, 81 /3 */
9368 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9369 ins_pipe( ialu_reg_long );
9370 %}
9371
9372 // Subtract Long Register with Memory
9373 instruct subL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9374 match(Set dst (SubL dst (LoadL mem)));
9375 effect(KILL cr);
9376 ins_cost(125);
9377 format %{ "SUB $dst.lo,$mem\n\t"
9378 "SBB $dst.hi,$mem+4" %}
9379 opcode(0x2B, 0x1B);
9380 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9381 ins_pipe( ialu_reg_long_mem );
9382 %}
9383
9384 instruct negL_eReg(eRegL dst, immL0 zero, eFlagsReg cr) %{
9385 match(Set dst (SubL zero dst));
9386 effect(KILL cr);
9387 ins_cost(300);
9388 format %{ "NEG $dst.hi\n\tNEG $dst.lo\n\tSBB $dst.hi,0" %}
9389 ins_encode( neg_long(dst) );
9390 ins_pipe( ialu_reg_reg_long );
9391 %}
9392
9393 // And Long Register with Register
9394 instruct andL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9395 match(Set dst (AndL dst src));
9396 effect(KILL cr);
9397 format %{ "AND $dst.lo,$src.lo\n\t"
9398 "AND $dst.hi,$src.hi" %}
9399 opcode(0x23,0x23);
9400 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
9401 ins_pipe( ialu_reg_reg_long );
9402 %}
9403
9404 // And Long Register with Immediate
9405 instruct andL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9406 match(Set dst (AndL dst src));
9407 effect(KILL cr);
9408 format %{ "AND $dst.lo,$src.lo\n\t"
9409 "AND $dst.hi,$src.hi" %}
9410 opcode(0x81,0x04,0x04); /* Opcode 81 /4, 81 /4 */
9411 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9412 ins_pipe( ialu_reg_long );
9413 %}
9414
9415 // And Long Register with Memory
9416 instruct andL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9417 match(Set dst (AndL dst (LoadL mem)));
9418 effect(KILL cr);
9419 ins_cost(125);
9420 format %{ "AND $dst.lo,$mem\n\t"
9421 "AND $dst.hi,$mem+4" %}
9422 opcode(0x23, 0x23);
9423 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9424 ins_pipe( ialu_reg_long_mem );
9425 %}
9426
9427 // Or Long Register with Register
9428 instruct orl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9429 match(Set dst (OrL dst src));
9430 effect(KILL cr);
9431 format %{ "OR $dst.lo,$src.lo\n\t"
9432 "OR $dst.hi,$src.hi" %}
9433 opcode(0x0B,0x0B);
9434 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
9435 ins_pipe( ialu_reg_reg_long );
9436 %}
9437
9438 // Or Long Register with Immediate
9439 instruct orl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9440 match(Set dst (OrL dst src));
9441 effect(KILL cr);
9442 format %{ "OR $dst.lo,$src.lo\n\t"
9443 "OR $dst.hi,$src.hi" %}
9444 opcode(0x81,0x01,0x01); /* Opcode 81 /1, 81 /1 */
9445 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9446 ins_pipe( ialu_reg_long );
9447 %}
9448
9449 // Or Long Register with Memory
9450 instruct orl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9451 match(Set dst (OrL dst (LoadL mem)));
9452 effect(KILL cr);
9453 ins_cost(125);
9454 format %{ "OR $dst.lo,$mem\n\t"
9455 "OR $dst.hi,$mem+4" %}
9456 opcode(0x0B,0x0B);
9457 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9458 ins_pipe( ialu_reg_long_mem );
9459 %}
9460
9461 // Xor Long Register with Register
9462 instruct xorl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9463 match(Set dst (XorL dst src));
9464 effect(KILL cr);
9465 format %{ "XOR $dst.lo,$src.lo\n\t"
9466 "XOR $dst.hi,$src.hi" %}
9467 opcode(0x33,0x33);
9468 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
9469 ins_pipe( ialu_reg_reg_long );
9470 %}
9471
9472 // Xor Long Register with Immediate -1
9473 instruct xorl_eReg_im1(eRegL dst, immL_M1 imm) %{
9474 match(Set dst (XorL dst imm));
9475 format %{ "NOT $dst.lo\n\t"
9476 "NOT $dst.hi" %}
9477 ins_encode %{
9478 __ notl($dst$$Register);
9479 __ notl(HIGH_FROM_LOW($dst$$Register));
9480 %}
9481 ins_pipe( ialu_reg_long );
9482 %}
9483
9484 // Xor Long Register with Immediate
9485 instruct xorl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9486 match(Set dst (XorL dst src));
9487 effect(KILL cr);
9488 format %{ "XOR $dst.lo,$src.lo\n\t"
9489 "XOR $dst.hi,$src.hi" %}
9490 opcode(0x81,0x06,0x06); /* Opcode 81 /6, 81 /6 */
9491 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9492 ins_pipe( ialu_reg_long );
9493 %}
9494
9495 // Xor Long Register with Memory
9496 instruct xorl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9497 match(Set dst (XorL dst (LoadL mem)));
9498 effect(KILL cr);
9499 ins_cost(125);
9500 format %{ "XOR $dst.lo,$mem\n\t"
9501 "XOR $dst.hi,$mem+4" %}
9502 opcode(0x33,0x33);
9503 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9504 ins_pipe( ialu_reg_long_mem );
9505 %}
9506
9507 // Shift Left Long by 1
9508 instruct shlL_eReg_1(eRegL dst, immI_1 cnt, eFlagsReg cr) %{
9509 predicate(UseNewLongLShift);
9510 match(Set dst (LShiftL dst cnt));
9511 effect(KILL cr);
9512 ins_cost(100);
9513 format %{ "ADD $dst.lo,$dst.lo\n\t"
9514 "ADC $dst.hi,$dst.hi" %}
9515 ins_encode %{
9516 __ addl($dst$$Register,$dst$$Register);
9517 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9518 %}
9519 ins_pipe( ialu_reg_long );
9520 %}
9521
9522 // Shift Left Long by 2
9523 instruct shlL_eReg_2(eRegL dst, immI_2 cnt, eFlagsReg cr) %{
9524 predicate(UseNewLongLShift);
9525 match(Set dst (LShiftL dst cnt));
9526 effect(KILL cr);
9527 ins_cost(100);
9528 format %{ "ADD $dst.lo,$dst.lo\n\t"
9529 "ADC $dst.hi,$dst.hi\n\t"
9530 "ADD $dst.lo,$dst.lo\n\t"
9531 "ADC $dst.hi,$dst.hi" %}
9532 ins_encode %{
9533 __ addl($dst$$Register,$dst$$Register);
9534 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9535 __ addl($dst$$Register,$dst$$Register);
9536 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9537 %}
9538 ins_pipe( ialu_reg_long );
9539 %}
9540
9541 // Shift Left Long by 3
9542 instruct shlL_eReg_3(eRegL dst, immI_3 cnt, eFlagsReg cr) %{
9543 predicate(UseNewLongLShift);
9544 match(Set dst (LShiftL dst cnt));
9545 effect(KILL cr);
9546 ins_cost(100);
9547 format %{ "ADD $dst.lo,$dst.lo\n\t"
9548 "ADC $dst.hi,$dst.hi\n\t"
9549 "ADD $dst.lo,$dst.lo\n\t"
9550 "ADC $dst.hi,$dst.hi\n\t"
9551 "ADD $dst.lo,$dst.lo\n\t"
9552 "ADC $dst.hi,$dst.hi" %}
9553 ins_encode %{
9554 __ addl($dst$$Register,$dst$$Register);
9555 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9556 __ addl($dst$$Register,$dst$$Register);
9557 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9558 __ addl($dst$$Register,$dst$$Register);
9559 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9560 %}
9561 ins_pipe( ialu_reg_long );
9562 %}
9563
9564 // Shift Left Long by 1-31
9565 instruct shlL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9566 match(Set dst (LShiftL dst cnt));
9567 effect(KILL cr);
9568 ins_cost(200);
9569 format %{ "SHLD $dst.hi,$dst.lo,$cnt\n\t"
9570 "SHL $dst.lo,$cnt" %}
9571 opcode(0xC1, 0x4, 0xA4); /* 0F/A4, then C1 /4 ib */
9572 ins_encode( move_long_small_shift(dst,cnt) );
9573 ins_pipe( ialu_reg_long );
9574 %}
9575
9576 // Shift Left Long by 32-63
9577 instruct shlL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9578 match(Set dst (LShiftL dst cnt));
9579 effect(KILL cr);
9580 ins_cost(300);
9581 format %{ "MOV $dst.hi,$dst.lo\n"
9582 "\tSHL $dst.hi,$cnt-32\n"
9583 "\tXOR $dst.lo,$dst.lo" %}
9584 opcode(0xC1, 0x4); /* C1 /4 ib */
9585 ins_encode( move_long_big_shift_clr(dst,cnt) );
9586 ins_pipe( ialu_reg_long );
9587 %}
9588
9589 // Shift Left Long by variable
9590 instruct salL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9591 match(Set dst (LShiftL dst shift));
9592 effect(KILL cr);
9593 ins_cost(500+200);
9594 size(17);
9595 format %{ "TEST $shift,32\n\t"
9596 "JEQ,s small\n\t"
9597 "MOV $dst.hi,$dst.lo\n\t"
9598 "XOR $dst.lo,$dst.lo\n"
9599 "small:\tSHLD $dst.hi,$dst.lo,$shift\n\t"
9600 "SHL $dst.lo,$shift" %}
9601 ins_encode( shift_left_long( dst, shift ) );
9602 ins_pipe( pipe_slow );
9603 %}
9604
9605 // Shift Right Long by 1-31
9606 instruct shrL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9607 match(Set dst (URShiftL dst cnt));
9608 effect(KILL cr);
9609 ins_cost(200);
9610 format %{ "SHRD $dst.lo,$dst.hi,$cnt\n\t"
9611 "SHR $dst.hi,$cnt" %}
9612 opcode(0xC1, 0x5, 0xAC); /* 0F/AC, then C1 /5 ib */
9613 ins_encode( move_long_small_shift(dst,cnt) );
9614 ins_pipe( ialu_reg_long );
9615 %}
9616
9617 // Shift Right Long by 32-63
9618 instruct shrL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9619 match(Set dst (URShiftL dst cnt));
9620 effect(KILL cr);
9621 ins_cost(300);
9622 format %{ "MOV $dst.lo,$dst.hi\n"
9623 "\tSHR $dst.lo,$cnt-32\n"
9624 "\tXOR $dst.hi,$dst.hi" %}
9625 opcode(0xC1, 0x5); /* C1 /5 ib */
9626 ins_encode( move_long_big_shift_clr(dst,cnt) );
9627 ins_pipe( ialu_reg_long );
9628 %}
9629
9630 // Shift Right Long by variable
9631 instruct shrL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9632 match(Set dst (URShiftL dst shift));
9633 effect(KILL cr);
9634 ins_cost(600);
9635 size(17);
9636 format %{ "TEST $shift,32\n\t"
9637 "JEQ,s small\n\t"
9638 "MOV $dst.lo,$dst.hi\n\t"
9639 "XOR $dst.hi,$dst.hi\n"
9640 "small:\tSHRD $dst.lo,$dst.hi,$shift\n\t"
9641 "SHR $dst.hi,$shift" %}
9642 ins_encode( shift_right_long( dst, shift ) );
9643 ins_pipe( pipe_slow );
9644 %}
9645
9646 // Shift Right Long by 1-31
9647 instruct sarL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9648 match(Set dst (RShiftL dst cnt));
9649 effect(KILL cr);
9650 ins_cost(200);
9651 format %{ "SHRD $dst.lo,$dst.hi,$cnt\n\t"
9652 "SAR $dst.hi,$cnt" %}
9653 opcode(0xC1, 0x7, 0xAC); /* 0F/AC, then C1 /7 ib */
9654 ins_encode( move_long_small_shift(dst,cnt) );
9655 ins_pipe( ialu_reg_long );
9656 %}
9657
9658 // Shift Right Long by 32-63
9659 instruct sarL_eReg_32_63( eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9660 match(Set dst (RShiftL dst cnt));
9661 effect(KILL cr);
9662 ins_cost(300);
9663 format %{ "MOV $dst.lo,$dst.hi\n"
9664 "\tSAR $dst.lo,$cnt-32\n"
9665 "\tSAR $dst.hi,31" %}
9666 opcode(0xC1, 0x7); /* C1 /7 ib */
9667 ins_encode( move_long_big_shift_sign(dst,cnt) );
9668 ins_pipe( ialu_reg_long );
9669 %}
9670
9671 // Shift Right arithmetic Long by variable
9672 instruct sarL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9673 match(Set dst (RShiftL dst shift));
9674 effect(KILL cr);
9675 ins_cost(600);
9676 size(18);
9677 format %{ "TEST $shift,32\n\t"
9678 "JEQ,s small\n\t"
9679 "MOV $dst.lo,$dst.hi\n\t"
9680 "SAR $dst.hi,31\n"
9681 "small:\tSHRD $dst.lo,$dst.hi,$shift\n\t"
9682 "SAR $dst.hi,$shift" %}
9683 ins_encode( shift_right_arith_long( dst, shift ) );
9684 ins_pipe( pipe_slow );
9685 %}
9686
9687
9688 //----------Double Instructions------------------------------------------------
9689 // Double Math
9690
9691 // Compare & branch
9692
9693 // P6 version of float compare, sets condition codes in EFLAGS
9694 instruct cmpD_cc_P6(eFlagsRegU cr, regD src1, regD src2, eAXRegI rax) %{
9695 predicate(VM_Version::supports_cmov() && UseSSE <=1);
9696 match(Set cr (CmpD src1 src2));
9697 effect(KILL rax);
9698 ins_cost(150);
9699 format %{ "FLD $src1\n\t"
9700 "FUCOMIP ST,$src2 // P6 instruction\n\t"
9701 "JNP exit\n\t"
9702 "MOV ah,1 // saw a NaN, set CF\n\t"
9703 "SAHF\n"
9704 "exit:\tNOP // avoid branch to branch" %}
9705 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
9706 ins_encode( Push_Reg_D(src1),
9707 OpcP, RegOpc(src2),
9708 cmpF_P6_fixup );
9709 ins_pipe( pipe_slow );
9710 %}
9711
9712 instruct cmpD_cc_P6CF(eFlagsRegUCF cr, regD src1, regD src2) %{
9713 predicate(VM_Version::supports_cmov() && UseSSE <=1);
9714 match(Set cr (CmpD src1 src2));
9715 ins_cost(150);
9716 format %{ "FLD $src1\n\t"
9717 "FUCOMIP ST,$src2 // P6 instruction" %}
9718 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
9719 ins_encode( Push_Reg_D(src1),
9720 OpcP, RegOpc(src2));
9721 ins_pipe( pipe_slow );
9722 %}
9723
9724 // Compare & branch
9725 instruct cmpD_cc(eFlagsRegU cr, regD src1, regD src2, eAXRegI rax) %{
9726 predicate(UseSSE<=1);
9727 match(Set cr (CmpD src1 src2));
9728 effect(KILL rax);
9729 ins_cost(200);
9730 format %{ "FLD $src1\n\t"
9731 "FCOMp $src2\n\t"
9732 "FNSTSW AX\n\t"
9733 "TEST AX,0x400\n\t"
9734 "JZ,s flags\n\t"
9735 "MOV AH,1\t# unordered treat as LT\n"
9736 "flags:\tSAHF" %}
9737 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
9738 ins_encode( Push_Reg_D(src1),
9739 OpcP, RegOpc(src2),
9740 fpu_flags);
9741 ins_pipe( pipe_slow );
9742 %}
9743
9744 // Compare vs zero into -1,0,1
9745 instruct cmpD_0(eRegI dst, regD src1, immD0 zero, eAXRegI rax, eFlagsReg cr) %{
9746 predicate(UseSSE<=1);
9747 match(Set dst (CmpD3 src1 zero));
9748 effect(KILL cr, KILL rax);
9749 ins_cost(280);
9750 format %{ "FTSTD $dst,$src1" %}
9751 opcode(0xE4, 0xD9);
9752 ins_encode( Push_Reg_D(src1),
9753 OpcS, OpcP, PopFPU,
9754 CmpF_Result(dst));
9755 ins_pipe( pipe_slow );
9756 %}
9757
9758 // Compare into -1,0,1
9759 instruct cmpD_reg(eRegI dst, regD src1, regD src2, eAXRegI rax, eFlagsReg cr) %{
9760 predicate(UseSSE<=1);
9761 match(Set dst (CmpD3 src1 src2));
9762 effect(KILL cr, KILL rax);
9763 ins_cost(300);
9764 format %{ "FCMPD $dst,$src1,$src2" %}
9765 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
9766 ins_encode( Push_Reg_D(src1),
9767 OpcP, RegOpc(src2),
9768 CmpF_Result(dst));
9769 ins_pipe( pipe_slow );
9770 %}
9771
9772 // float compare and set condition codes in EFLAGS by XMM regs
9773 instruct cmpXD_cc(eFlagsRegU cr, regXD dst, regXD src, eAXRegI rax) %{
9774 predicate(UseSSE>=2);
9775 match(Set cr (CmpD dst src));
9776 effect(KILL rax);
9777 ins_cost(125);
9778 format %{ "COMISD $dst,$src\n"
9779 "\tJNP exit\n"
9780 "\tMOV ah,1 // saw a NaN, set CF\n"
9781 "\tSAHF\n"
9782 "exit:\tNOP // avoid branch to branch" %}
9783 opcode(0x66, 0x0F, 0x2F);
9784 ins_encode(OpcP, OpcS, Opcode(tertiary), RegReg(dst, src), cmpF_P6_fixup);
9785 ins_pipe( pipe_slow );
9786 %}
9787
9788 instruct cmpXD_ccCF(eFlagsRegUCF cr, regXD dst, regXD src) %{
9789 predicate(UseSSE>=2);
9790 match(Set cr (CmpD dst src));
9791 ins_cost(100);
9792 format %{ "COMISD $dst,$src" %}
9793 opcode(0x66, 0x0F, 0x2F);
9794 ins_encode(OpcP, OpcS, Opcode(tertiary), RegReg(dst, src));
9795 ins_pipe( pipe_slow );
9796 %}
9797
9798 // float compare and set condition codes in EFLAGS by XMM regs
9799 instruct cmpXD_ccmem(eFlagsRegU cr, regXD dst, memory src, eAXRegI rax) %{
9800 predicate(UseSSE>=2);
9801 match(Set cr (CmpD dst (LoadD src)));
9802 effect(KILL rax);
9803 ins_cost(145);
9804 format %{ "COMISD $dst,$src\n"
9805 "\tJNP exit\n"
9806 "\tMOV ah,1 // saw a NaN, set CF\n"
9807 "\tSAHF\n"
9808 "exit:\tNOP // avoid branch to branch" %}
9809 opcode(0x66, 0x0F, 0x2F);
9810 ins_encode(OpcP, OpcS, Opcode(tertiary), RegMem(dst, src), cmpF_P6_fixup);
9811 ins_pipe( pipe_slow );
9812 %}
9813
9814 instruct cmpXD_ccmemCF(eFlagsRegUCF cr, regXD dst, memory src) %{
9815 predicate(UseSSE>=2);
9816 match(Set cr (CmpD dst (LoadD src)));
9817 ins_cost(100);
9818 format %{ "COMISD $dst,$src" %}
9819 opcode(0x66, 0x0F, 0x2F);
9820 ins_encode(OpcP, OpcS, Opcode(tertiary), RegMem(dst, src));
9821 ins_pipe( pipe_slow );
9822 %}
9823
9824 // Compare into -1,0,1 in XMM
9825 instruct cmpXD_reg(eRegI dst, regXD src1, regXD src2, eFlagsReg cr) %{
9826 predicate(UseSSE>=2);
9827 match(Set dst (CmpD3 src1 src2));
9828 effect(KILL cr);
9829 ins_cost(255);
9830 format %{ "XOR $dst,$dst\n"
9831 "\tCOMISD $src1,$src2\n"
9832 "\tJP,s nan\n"
9833 "\tJEQ,s exit\n"
9834 "\tJA,s inc\n"
9835 "nan:\tDEC $dst\n"
9836 "\tJMP,s exit\n"
9837 "inc:\tINC $dst\n"
9838 "exit:"
9839 %}
9840 opcode(0x66, 0x0F, 0x2F);
9841 ins_encode(Xor_Reg(dst), OpcP, OpcS, Opcode(tertiary), RegReg(src1, src2),
9842 CmpX_Result(dst));
9843 ins_pipe( pipe_slow );
9844 %}
9845
9846 // Compare into -1,0,1 in XMM and memory
9847 instruct cmpXD_regmem(eRegI dst, regXD src1, memory mem, eFlagsReg cr) %{
9848 predicate(UseSSE>=2);
9849 match(Set dst (CmpD3 src1 (LoadD mem)));
9850 effect(KILL cr);
9851 ins_cost(275);
9852 format %{ "COMISD $src1,$mem\n"
9853 "\tMOV $dst,0\t\t# do not blow flags\n"
9854 "\tJP,s nan\n"
9855 "\tJEQ,s exit\n"
9856 "\tJA,s inc\n"
9857 "nan:\tDEC $dst\n"
9858 "\tJMP,s exit\n"
9859 "inc:\tINC $dst\n"
9860 "exit:"
9861 %}
9862 opcode(0x66, 0x0F, 0x2F);
9863 ins_encode(OpcP, OpcS, Opcode(tertiary), RegMem(src1, mem),
9864 LdImmI(dst,0x0), CmpX_Result(dst));
9865 ins_pipe( pipe_slow );
9866 %}
9867
9868
9869 instruct subD_reg(regD dst, regD src) %{
9870 predicate (UseSSE <=1);
9871 match(Set dst (SubD dst src));
9872
9873 format %{ "FLD $src\n\t"
9874 "DSUBp $dst,ST" %}
9875 opcode(0xDE, 0x5); /* DE E8+i or DE /5 */
9876 ins_cost(150);
9877 ins_encode( Push_Reg_D(src),
9878 OpcP, RegOpc(dst) );
9879 ins_pipe( fpu_reg_reg );
9880 %}
9881
9882 instruct subD_reg_round(stackSlotD dst, regD src1, regD src2) %{
9883 predicate (UseSSE <=1);
9884 match(Set dst (RoundDouble (SubD src1 src2)));
9885 ins_cost(250);
9886
9887 format %{ "FLD $src2\n\t"
9888 "DSUB ST,$src1\n\t"
9889 "FSTP_D $dst\t# D-round" %}
9890 opcode(0xD8, 0x5);
9891 ins_encode( Push_Reg_D(src2),
9892 OpcP, RegOpc(src1), Pop_Mem_D(dst) );
9893 ins_pipe( fpu_mem_reg_reg );
9894 %}
9895
9896
9897 instruct subD_reg_mem(regD dst, memory src) %{
9898 predicate (UseSSE <=1);
9899 match(Set dst (SubD dst (LoadD src)));
9900 ins_cost(150);
9901
9902 format %{ "FLD $src\n\t"
9903 "DSUBp $dst,ST" %}
9904 opcode(0xDE, 0x5, 0xDD); /* DE C0+i */ /* LoadD DD /0 */
9905 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
9906 OpcP, RegOpc(dst) );
9907 ins_pipe( fpu_reg_mem );
9908 %}
9909
9910 instruct absD_reg(regDPR1 dst, regDPR1 src) %{
9911 predicate (UseSSE<=1);
9912 match(Set dst (AbsD src));
9913 ins_cost(100);
9914 format %{ "FABS" %}
9915 opcode(0xE1, 0xD9);
9916 ins_encode( OpcS, OpcP );
9917 ins_pipe( fpu_reg_reg );
9918 %}
9919
9920 instruct absXD_reg( regXD dst ) %{
9921 predicate(UseSSE>=2);
9922 match(Set dst (AbsD dst));
9923 format %{ "ANDPD $dst,[0x7FFFFFFFFFFFFFFF]\t# ABS D by sign masking" %}
9924 ins_encode( AbsXD_encoding(dst));
9925 ins_pipe( pipe_slow );
9926 %}
9927
9928 instruct negD_reg(regDPR1 dst, regDPR1 src) %{
9929 predicate(UseSSE<=1);
9930 match(Set dst (NegD src));
9931 ins_cost(100);
9932 format %{ "FCHS" %}
9933 opcode(0xE0, 0xD9);
9934 ins_encode( OpcS, OpcP );
9935 ins_pipe( fpu_reg_reg );
9936 %}
9937
9938 instruct negXD_reg( regXD dst ) %{
9939 predicate(UseSSE>=2);
9940 match(Set dst (NegD dst));
9941 format %{ "XORPD $dst,[0x8000000000000000]\t# CHS D by sign flipping" %}
9942 ins_encode %{
9943 __ xorpd($dst$$XMMRegister,
9944 ExternalAddress((address)double_signflip_pool));
9945 %}
9946 ins_pipe( pipe_slow );
9947 %}
9948
9949 instruct addD_reg(regD dst, regD src) %{
9950 predicate(UseSSE<=1);
9951 match(Set dst (AddD dst src));
9952 format %{ "FLD $src\n\t"
9953 "DADD $dst,ST" %}
9954 size(4);
9955 ins_cost(150);
9956 opcode(0xDE, 0x0); /* DE C0+i or DE /0*/
9957 ins_encode( Push_Reg_D(src),
9958 OpcP, RegOpc(dst) );
9959 ins_pipe( fpu_reg_reg );
9960 %}
9961
9962
9963 instruct addD_reg_round(stackSlotD dst, regD src1, regD src2) %{
9964 predicate(UseSSE<=1);
9965 match(Set dst (RoundDouble (AddD src1 src2)));
9966 ins_cost(250);
9967
9968 format %{ "FLD $src2\n\t"
9969 "DADD ST,$src1\n\t"
9970 "FSTP_D $dst\t# D-round" %}
9971 opcode(0xD8, 0x0); /* D8 C0+i or D8 /0*/
9972 ins_encode( Push_Reg_D(src2),
9973 OpcP, RegOpc(src1), Pop_Mem_D(dst) );
9974 ins_pipe( fpu_mem_reg_reg );
9975 %}
9976
9977
9978 instruct addD_reg_mem(regD dst, memory src) %{
9979 predicate(UseSSE<=1);
9980 match(Set dst (AddD dst (LoadD src)));
9981 ins_cost(150);
9982
9983 format %{ "FLD $src\n\t"
9984 "DADDp $dst,ST" %}
9985 opcode(0xDE, 0x0, 0xDD); /* DE C0+i */ /* LoadD DD /0 */
9986 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
9987 OpcP, RegOpc(dst) );
9988 ins_pipe( fpu_reg_mem );
9989 %}
9990
9991 // add-to-memory
9992 instruct addD_mem_reg(memory dst, regD src) %{
9993 predicate(UseSSE<=1);
9994 match(Set dst (StoreD dst (RoundDouble (AddD (LoadD dst) src))));
9995 ins_cost(150);
9996
9997 format %{ "FLD_D $dst\n\t"
9998 "DADD ST,$src\n\t"
9999 "FST_D $dst" %}
10000 opcode(0xDD, 0x0);
10001 ins_encode( Opcode(0xDD), RMopc_Mem(0x00,dst),
10002 Opcode(0xD8), RegOpc(src),
10003 set_instruction_start,
10004 Opcode(0xDD), RMopc_Mem(0x03,dst) );
10005 ins_pipe( fpu_reg_mem );
10006 %}
10007
10008 instruct addD_reg_imm1(regD dst, immD1 src) %{
10009 predicate(UseSSE<=1);
10010 match(Set dst (AddD dst src));
10011 ins_cost(125);
10012 format %{ "FLD1\n\t"
10013 "DADDp $dst,ST" %}
10014 opcode(0xDE, 0x00);
10015 ins_encode( LdImmD(src),
10016 OpcP, RegOpc(dst) );
10017 ins_pipe( fpu_reg );
10018 %}
10019
10020 instruct addD_reg_imm(regD dst, immD src) %{
10021 predicate(UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 );
10022 match(Set dst (AddD dst src));
10023 ins_cost(200);
10024 format %{ "FLD_D [$src]\n\t"
10025 "DADDp $dst,ST" %}
10026 opcode(0xDE, 0x00); /* DE /0 */
10027 ins_encode( LdImmD(src),
10028 OpcP, RegOpc(dst));
10029 ins_pipe( fpu_reg_mem );
10030 %}
10031
10032 instruct addD_reg_imm_round(stackSlotD dst, regD src, immD con) %{
10033 predicate(UseSSE<=1 && _kids[0]->_kids[1]->_leaf->getd() != 0.0 && _kids[0]->_kids[1]->_leaf->getd() != 1.0 );
10034 match(Set dst (RoundDouble (AddD src con)));
10035 ins_cost(200);
10036 format %{ "FLD_D [$con]\n\t"
10037 "DADD ST,$src\n\t"
10038 "FSTP_D $dst\t# D-round" %}
10039 opcode(0xD8, 0x00); /* D8 /0 */
10040 ins_encode( LdImmD(con),
10041 OpcP, RegOpc(src), Pop_Mem_D(dst));
10042 ins_pipe( fpu_mem_reg_con );
10043 %}
10044
10045 // Add two double precision floating point values in xmm
10046 instruct addXD_reg(regXD dst, regXD src) %{
10047 predicate(UseSSE>=2);
10048 match(Set dst (AddD dst src));
10049 format %{ "ADDSD $dst,$src" %}
10050 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x58), RegReg(dst, src));
10051 ins_pipe( pipe_slow );
10052 %}
10053
10054 instruct addXD_imm(regXD dst, immXD con) %{
10055 predicate(UseSSE>=2);
10056 match(Set dst (AddD dst con));
10057 format %{ "ADDSD $dst,[$con]" %}
10058 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x58), LdImmXD(dst, con) );
10059 ins_pipe( pipe_slow );
10060 %}
10061
10062 instruct addXD_mem(regXD dst, memory mem) %{
10063 predicate(UseSSE>=2);
10064 match(Set dst (AddD dst (LoadD mem)));
10065 format %{ "ADDSD $dst,$mem" %}
10066 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x58), RegMem(dst,mem));
10067 ins_pipe( pipe_slow );
10068 %}
10069
10070 // Sub two double precision floating point values in xmm
10071 instruct subXD_reg(regXD dst, regXD src) %{
10072 predicate(UseSSE>=2);
10073 match(Set dst (SubD dst src));
10074 format %{ "SUBSD $dst,$src" %}
10075 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5C), RegReg(dst, src));
10076 ins_pipe( pipe_slow );
10077 %}
10078
10079 instruct subXD_imm(regXD dst, immXD con) %{
10080 predicate(UseSSE>=2);
10081 match(Set dst (SubD dst con));
10082 format %{ "SUBSD $dst,[$con]" %}
10083 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5C), LdImmXD(dst, con) );
10084 ins_pipe( pipe_slow );
10085 %}
10086
10087 instruct subXD_mem(regXD dst, memory mem) %{
10088 predicate(UseSSE>=2);
10089 match(Set dst (SubD dst (LoadD mem)));
10090 format %{ "SUBSD $dst,$mem" %}
10091 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5C), RegMem(dst,mem));
10092 ins_pipe( pipe_slow );
10093 %}
10094
10095 // Mul two double precision floating point values in xmm
10096 instruct mulXD_reg(regXD dst, regXD src) %{
10097 predicate(UseSSE>=2);
10098 match(Set dst (MulD dst src));
10099 format %{ "MULSD $dst,$src" %}
10100 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x59), RegReg(dst, src));
10101 ins_pipe( pipe_slow );
10102 %}
10103
10104 instruct mulXD_imm(regXD dst, immXD con) %{
10105 predicate(UseSSE>=2);
10106 match(Set dst (MulD dst con));
10107 format %{ "MULSD $dst,[$con]" %}
10108 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x59), LdImmXD(dst, con) );
10109 ins_pipe( pipe_slow );
10110 %}
10111
10112 instruct mulXD_mem(regXD dst, memory mem) %{
10113 predicate(UseSSE>=2);
10114 match(Set dst (MulD dst (LoadD mem)));
10115 format %{ "MULSD $dst,$mem" %}
10116 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x59), RegMem(dst,mem));
10117 ins_pipe( pipe_slow );
10118 %}
10119
10120 // Div two double precision floating point values in xmm
10121 instruct divXD_reg(regXD dst, regXD src) %{
10122 predicate(UseSSE>=2);
10123 match(Set dst (DivD dst src));
10124 format %{ "DIVSD $dst,$src" %}
10125 opcode(0xF2, 0x0F, 0x5E);
10126 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5E), RegReg(dst, src));
10127 ins_pipe( pipe_slow );
10128 %}
10129
10130 instruct divXD_imm(regXD dst, immXD con) %{
10131 predicate(UseSSE>=2);
10132 match(Set dst (DivD dst con));
10133 format %{ "DIVSD $dst,[$con]" %}
10134 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5E), LdImmXD(dst, con));
10135 ins_pipe( pipe_slow );
10136 %}
10137
10138 instruct divXD_mem(regXD dst, memory mem) %{
10139 predicate(UseSSE>=2);
10140 match(Set dst (DivD dst (LoadD mem)));
10141 format %{ "DIVSD $dst,$mem" %}
10142 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5E), RegMem(dst,mem));
10143 ins_pipe( pipe_slow );
10144 %}
10145
10146
10147 instruct mulD_reg(regD dst, regD src) %{
10148 predicate(UseSSE<=1);
10149 match(Set dst (MulD dst src));
10150 format %{ "FLD $src\n\t"
10151 "DMULp $dst,ST" %}
10152 opcode(0xDE, 0x1); /* DE C8+i or DE /1*/
10153 ins_cost(150);
10154 ins_encode( Push_Reg_D(src),
10155 OpcP, RegOpc(dst) );
10156 ins_pipe( fpu_reg_reg );
10157 %}
10158
10159 // Strict FP instruction biases argument before multiply then
10160 // biases result to avoid double rounding of subnormals.
10161 //
10162 // scale arg1 by multiplying arg1 by 2^(-15360)
10163 // load arg2
10164 // multiply scaled arg1 by arg2
10165 // rescale product by 2^(15360)
10166 //
10167 instruct strictfp_mulD_reg(regDPR1 dst, regnotDPR1 src) %{
10168 predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() );
10169 match(Set dst (MulD dst src));
10170 ins_cost(1); // Select this instruction for all strict FP double multiplies
10171
10172 format %{ "FLD StubRoutines::_fpu_subnormal_bias1\n\t"
10173 "DMULp $dst,ST\n\t"
10174 "FLD $src\n\t"
10175 "DMULp $dst,ST\n\t"
10176 "FLD StubRoutines::_fpu_subnormal_bias2\n\t"
10177 "DMULp $dst,ST\n\t" %}
10178 opcode(0xDE, 0x1); /* DE C8+i or DE /1*/
10179 ins_encode( strictfp_bias1(dst),
10180 Push_Reg_D(src),
10181 OpcP, RegOpc(dst),
10182 strictfp_bias2(dst) );
10183 ins_pipe( fpu_reg_reg );
10184 %}
10185
10186 instruct mulD_reg_imm(regD dst, immD src) %{
10187 predicate( UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 );
10188 match(Set dst (MulD dst src));
10189 ins_cost(200);
10190 format %{ "FLD_D [$src]\n\t"
10191 "DMULp $dst,ST" %}
10192 opcode(0xDE, 0x1); /* DE /1 */
10193 ins_encode( LdImmD(src),
10194 OpcP, RegOpc(dst) );
10195 ins_pipe( fpu_reg_mem );
10196 %}
10197
10198
10199 instruct mulD_reg_mem(regD dst, memory src) %{
10200 predicate( UseSSE<=1 );
10201 match(Set dst (MulD dst (LoadD src)));
10202 ins_cost(200);
10203 format %{ "FLD_D $src\n\t"
10204 "DMULp $dst,ST" %}
10205 opcode(0xDE, 0x1, 0xDD); /* DE C8+i or DE /1*/ /* LoadD DD /0 */
10206 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
10207 OpcP, RegOpc(dst) );
10208 ins_pipe( fpu_reg_mem );
10209 %}
10210
10211 //
10212 // Cisc-alternate to reg-reg multiply
10213 instruct mulD_reg_mem_cisc(regD dst, regD src, memory mem) %{
10214 predicate( UseSSE<=1 );
10215 match(Set dst (MulD src (LoadD mem)));
10216 ins_cost(250);
10217 format %{ "FLD_D $mem\n\t"
10218 "DMUL ST,$src\n\t"
10219 "FSTP_D $dst" %}
10220 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */ /* LoadD D9 /0 */
10221 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem),
10222 OpcReg_F(src),
10223 Pop_Reg_D(dst) );
10224 ins_pipe( fpu_reg_reg_mem );
10225 %}
10226
10227
10228 // MACRO3 -- addD a mulD
10229 // This instruction is a '2-address' instruction in that the result goes
10230 // back to src2. This eliminates a move from the macro; possibly the
10231 // register allocator will have to add it back (and maybe not).
10232 instruct addD_mulD_reg(regD src2, regD src1, regD src0) %{
10233 predicate( UseSSE<=1 );
10234 match(Set src2 (AddD (MulD src0 src1) src2));
10235 format %{ "FLD $src0\t# ===MACRO3d===\n\t"
10236 "DMUL ST,$src1\n\t"
10237 "DADDp $src2,ST" %}
10238 ins_cost(250);
10239 opcode(0xDD); /* LoadD DD /0 */
10240 ins_encode( Push_Reg_F(src0),
10241 FMul_ST_reg(src1),
10242 FAddP_reg_ST(src2) );
10243 ins_pipe( fpu_reg_reg_reg );
10244 %}
10245
10246
10247 // MACRO3 -- subD a mulD
10248 instruct subD_mulD_reg(regD src2, regD src1, regD src0) %{
10249 predicate( UseSSE<=1 );
10250 match(Set src2 (SubD (MulD src0 src1) src2));
10251 format %{ "FLD $src0\t# ===MACRO3d===\n\t"
10252 "DMUL ST,$src1\n\t"
10253 "DSUBRp $src2,ST" %}
10254 ins_cost(250);
10255 ins_encode( Push_Reg_F(src0),
10256 FMul_ST_reg(src1),
10257 Opcode(0xDE), Opc_plus(0xE0,src2));
10258 ins_pipe( fpu_reg_reg_reg );
10259 %}
10260
10261
10262 instruct divD_reg(regD dst, regD src) %{
10263 predicate( UseSSE<=1 );
10264 match(Set dst (DivD dst src));
10265
10266 format %{ "FLD $src\n\t"
10267 "FDIVp $dst,ST" %}
10268 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
10269 ins_cost(150);
10270 ins_encode( Push_Reg_D(src),
10271 OpcP, RegOpc(dst) );
10272 ins_pipe( fpu_reg_reg );
10273 %}
10274
10275 // Strict FP instruction biases argument before division then
10276 // biases result, to avoid double rounding of subnormals.
10277 //
10278 // scale dividend by multiplying dividend by 2^(-15360)
10279 // load divisor
10280 // divide scaled dividend by divisor
10281 // rescale quotient by 2^(15360)
10282 //
10283 instruct strictfp_divD_reg(regDPR1 dst, regnotDPR1 src) %{
10284 predicate (UseSSE<=1);
10285 match(Set dst (DivD dst src));
10286 predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() );
10287 ins_cost(01);
10288
10289 format %{ "FLD StubRoutines::_fpu_subnormal_bias1\n\t"
10290 "DMULp $dst,ST\n\t"
10291 "FLD $src\n\t"
10292 "FDIVp $dst,ST\n\t"
10293 "FLD StubRoutines::_fpu_subnormal_bias2\n\t"
10294 "DMULp $dst,ST\n\t" %}
10295 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
10296 ins_encode( strictfp_bias1(dst),
10297 Push_Reg_D(src),
10298 OpcP, RegOpc(dst),
10299 strictfp_bias2(dst) );
10300 ins_pipe( fpu_reg_reg );
10301 %}
10302
10303 instruct divD_reg_round(stackSlotD dst, regD src1, regD src2) %{
10304 predicate( UseSSE<=1 && !(Compile::current()->has_method() && Compile::current()->method()->is_strict()) );
10305 match(Set dst (RoundDouble (DivD src1 src2)));
10306
10307 format %{ "FLD $src1\n\t"
10308 "FDIV ST,$src2\n\t"
10309 "FSTP_D $dst\t# D-round" %}
10310 opcode(0xD8, 0x6); /* D8 F0+i or D8 /6 */
10311 ins_encode( Push_Reg_D(src1),
10312 OpcP, RegOpc(src2), Pop_Mem_D(dst) );
10313 ins_pipe( fpu_mem_reg_reg );
10314 %}
10315
10316
10317 instruct modD_reg(regD dst, regD src, eAXRegI rax, eFlagsReg cr) %{
10318 predicate(UseSSE<=1);
10319 match(Set dst (ModD dst src));
10320 effect(KILL rax, KILL cr); // emitModD() uses EAX and EFLAGS
10321
10322 format %{ "DMOD $dst,$src" %}
10323 ins_cost(250);
10324 ins_encode(Push_Reg_Mod_D(dst, src),
10325 emitModD(),
10326 Push_Result_Mod_D(src),
10327 Pop_Reg_D(dst));
10328 ins_pipe( pipe_slow );
10329 %}
10330
10331 instruct modXD_reg(regXD dst, regXD src0, regXD src1, eAXRegI rax, eFlagsReg cr) %{
10332 predicate(UseSSE>=2);
10333 match(Set dst (ModD src0 src1));
10334 effect(KILL rax, KILL cr);
10335
10336 format %{ "SUB ESP,8\t # DMOD\n"
10337 "\tMOVSD [ESP+0],$src1\n"
10338 "\tFLD_D [ESP+0]\n"
10339 "\tMOVSD [ESP+0],$src0\n"
10340 "\tFLD_D [ESP+0]\n"
10341 "loop:\tFPREM\n"
10342 "\tFWAIT\n"
10343 "\tFNSTSW AX\n"
10344 "\tSAHF\n"
10345 "\tJP loop\n"
10346 "\tFSTP_D [ESP+0]\n"
10347 "\tMOVSD $dst,[ESP+0]\n"
10348 "\tADD ESP,8\n"
10349 "\tFSTP ST0\t # Restore FPU Stack"
10350 %}
10351 ins_cost(250);
10352 ins_encode( Push_ModD_encoding(src0, src1), emitModD(), Push_ResultXD(dst), PopFPU);
10353 ins_pipe( pipe_slow );
10354 %}
10355
10356 instruct sinD_reg(regDPR1 dst, regDPR1 src) %{
10357 predicate (UseSSE<=1);
10358 match(Set dst (SinD src));
10359 ins_cost(1800);
10360 format %{ "DSIN $dst" %}
10361 opcode(0xD9, 0xFE);
10362 ins_encode( OpcP, OpcS );
10363 ins_pipe( pipe_slow );
10364 %}
10365
10366 instruct sinXD_reg(regXD dst, eFlagsReg cr) %{
10367 predicate (UseSSE>=2);
10368 match(Set dst (SinD dst));
10369 effect(KILL cr); // Push_{Src|Result}XD() uses "{SUB|ADD} ESP,8"
10370 ins_cost(1800);
10371 format %{ "DSIN $dst" %}
10372 opcode(0xD9, 0xFE);
10373 ins_encode( Push_SrcXD(dst), OpcP, OpcS, Push_ResultXD(dst) );
10374 ins_pipe( pipe_slow );
10375 %}
10376
10377 instruct cosD_reg(regDPR1 dst, regDPR1 src) %{
10378 predicate (UseSSE<=1);
10379 match(Set dst (CosD src));
10380 ins_cost(1800);
10381 format %{ "DCOS $dst" %}
10382 opcode(0xD9, 0xFF);
10383 ins_encode( OpcP, OpcS );
10384 ins_pipe( pipe_slow );
10385 %}
10386
10387 instruct cosXD_reg(regXD dst, eFlagsReg cr) %{
10388 predicate (UseSSE>=2);
10389 match(Set dst (CosD dst));
10390 effect(KILL cr); // Push_{Src|Result}XD() uses "{SUB|ADD} ESP,8"
10391 ins_cost(1800);
10392 format %{ "DCOS $dst" %}
10393 opcode(0xD9, 0xFF);
10394 ins_encode( Push_SrcXD(dst), OpcP, OpcS, Push_ResultXD(dst) );
10395 ins_pipe( pipe_slow );
10396 %}
10397
10398 instruct tanD_reg(regDPR1 dst, regDPR1 src) %{
10399 predicate (UseSSE<=1);
10400 match(Set dst(TanD src));
10401 format %{ "DTAN $dst" %}
10402 ins_encode( Opcode(0xD9), Opcode(0xF2), // fptan
10403 Opcode(0xDD), Opcode(0xD8)); // fstp st
10404 ins_pipe( pipe_slow );
10405 %}
10406
10407 instruct tanXD_reg(regXD dst, eFlagsReg cr) %{
10408 predicate (UseSSE>=2);
10409 match(Set dst(TanD dst));
10410 effect(KILL cr); // Push_{Src|Result}XD() uses "{SUB|ADD} ESP,8"
10411 format %{ "DTAN $dst" %}
10412 ins_encode( Push_SrcXD(dst),
10413 Opcode(0xD9), Opcode(0xF2), // fptan
10414 Opcode(0xDD), Opcode(0xD8), // fstp st
10415 Push_ResultXD(dst) );
10416 ins_pipe( pipe_slow );
10417 %}
10418
10419 instruct atanD_reg(regD dst, regD src) %{
10420 predicate (UseSSE<=1);
10421 match(Set dst(AtanD dst src));
10422 format %{ "DATA $dst,$src" %}
10423 opcode(0xD9, 0xF3);
10424 ins_encode( Push_Reg_D(src),
10425 OpcP, OpcS, RegOpc(dst) );
10426 ins_pipe( pipe_slow );
10427 %}
10428
10429 instruct atanXD_reg(regXD dst, regXD src, eFlagsReg cr) %{
10430 predicate (UseSSE>=2);
10431 match(Set dst(AtanD dst src));
10432 effect(KILL cr); // Push_{Src|Result}XD() uses "{SUB|ADD} ESP,8"
10433 format %{ "DATA $dst,$src" %}
10434 opcode(0xD9, 0xF3);
10435 ins_encode( Push_SrcXD(src),
10436 OpcP, OpcS, Push_ResultXD(dst) );
10437 ins_pipe( pipe_slow );
10438 %}
10439
10440 instruct sqrtD_reg(regD dst, regD src) %{
10441 predicate (UseSSE<=1);
10442 match(Set dst (SqrtD src));
10443 format %{ "DSQRT $dst,$src" %}
10444 opcode(0xFA, 0xD9);
10445 ins_encode( Push_Reg_D(src),
10446 OpcS, OpcP, Pop_Reg_D(dst) );
10447 ins_pipe( pipe_slow );
10448 %}
10449
10450 instruct powD_reg(regD X, regDPR1 Y, eAXRegI rax, eBXRegI rbx, eCXRegI rcx) %{
10451 predicate (UseSSE<=1);
10452 match(Set Y (PowD X Y)); // Raise X to the Yth power
10453 effect(KILL rax, KILL rbx, KILL rcx);
10454 format %{ "SUB ESP,8\t\t# Fast-path POW encoding\n\t"
10455 "FLD_D $X\n\t"
10456 "FYL2X \t\t\t# Q=Y*ln2(X)\n\t"
10457
10458 "FDUP \t\t\t# Q Q\n\t"
10459 "FRNDINT\t\t\t# int(Q) Q\n\t"
10460 "FSUB ST(1),ST(0)\t# int(Q) frac(Q)\n\t"
10461 "FISTP dword [ESP]\n\t"
10462 "F2XM1 \t\t\t# 2^frac(Q)-1 int(Q)\n\t"
10463 "FLD1 \t\t\t# 1 2^frac(Q)-1 int(Q)\n\t"
10464 "FADDP \t\t\t# 2^frac(Q) int(Q)\n\t" // could use FADD [1.000] instead
10465 "MOV EAX,[ESP]\t# Pick up int(Q)\n\t"
10466 "MOV ECX,0xFFFFF800\t# Overflow mask\n\t"
10467 "ADD EAX,1023\t\t# Double exponent bias\n\t"
10468 "MOV EBX,EAX\t\t# Preshifted biased expo\n\t"
10469 "SHL EAX,20\t\t# Shift exponent into place\n\t"
10470 "TEST EBX,ECX\t\t# Check for overflow\n\t"
10471 "CMOVne EAX,ECX\t\t# If overflow, stuff NaN into EAX\n\t"
10472 "MOV [ESP+4],EAX\t# Marshal 64-bit scaling double\n\t"
10473 "MOV [ESP+0],0\n\t"
10474 "FMUL ST(0),[ESP+0]\t# Scale\n\t"
10475
10476 "ADD ESP,8"
10477 %}
10478 ins_encode( push_stack_temp_qword,
10479 Push_Reg_D(X),
10480 Opcode(0xD9), Opcode(0xF1), // fyl2x
10481 pow_exp_core_encoding,
10482 pop_stack_temp_qword);
10483 ins_pipe( pipe_slow );
10484 %}
10485
10486 instruct powXD_reg(regXD dst, regXD src0, regXD src1, regDPR1 tmp1, eAXRegI rax, eBXRegI rbx, eCXRegI rcx ) %{
10487 predicate (UseSSE>=2);
10488 match(Set dst (PowD src0 src1)); // Raise src0 to the src1'th power
10489 effect(KILL tmp1, KILL rax, KILL rbx, KILL rcx );
10490 format %{ "SUB ESP,8\t\t# Fast-path POW encoding\n\t"
10491 "MOVSD [ESP],$src1\n\t"
10492 "FLD FPR1,$src1\n\t"
10493 "MOVSD [ESP],$src0\n\t"
10494 "FLD FPR1,$src0\n\t"
10495 "FYL2X \t\t\t# Q=Y*ln2(X)\n\t"
10496
10497 "FDUP \t\t\t# Q Q\n\t"
10498 "FRNDINT\t\t\t# int(Q) Q\n\t"
10499 "FSUB ST(1),ST(0)\t# int(Q) frac(Q)\n\t"
10500 "FISTP dword [ESP]\n\t"
10501 "F2XM1 \t\t\t# 2^frac(Q)-1 int(Q)\n\t"
10502 "FLD1 \t\t\t# 1 2^frac(Q)-1 int(Q)\n\t"
10503 "FADDP \t\t\t# 2^frac(Q) int(Q)\n\t" // could use FADD [1.000] instead
10504 "MOV EAX,[ESP]\t# Pick up int(Q)\n\t"
10505 "MOV ECX,0xFFFFF800\t# Overflow mask\n\t"
10506 "ADD EAX,1023\t\t# Double exponent bias\n\t"
10507 "MOV EBX,EAX\t\t# Preshifted biased expo\n\t"
10508 "SHL EAX,20\t\t# Shift exponent into place\n\t"
10509 "TEST EBX,ECX\t\t# Check for overflow\n\t"
10510 "CMOVne EAX,ECX\t\t# If overflow, stuff NaN into EAX\n\t"
10511 "MOV [ESP+4],EAX\t# Marshal 64-bit scaling double\n\t"
10512 "MOV [ESP+0],0\n\t"
10513 "FMUL ST(0),[ESP+0]\t# Scale\n\t"
10514
10515 "FST_D [ESP]\n\t"
10516 "MOVSD $dst,[ESP]\n\t"
10517 "ADD ESP,8"
10518 %}
10519 ins_encode( push_stack_temp_qword,
10520 push_xmm_to_fpr1(src1),
10521 push_xmm_to_fpr1(src0),
10522 Opcode(0xD9), Opcode(0xF1), // fyl2x
10523 pow_exp_core_encoding,
10524 Push_ResultXD(dst) );
10525 ins_pipe( pipe_slow );
10526 %}
10527
10528
10529 instruct expD_reg(regDPR1 dpr1, eAXRegI rax, eBXRegI rbx, eCXRegI rcx) %{
10530 predicate (UseSSE<=1);
10531 match(Set dpr1 (ExpD dpr1));
10532 effect(KILL rax, KILL rbx, KILL rcx);
10533 format %{ "SUB ESP,8\t\t# Fast-path EXP encoding"
10534 "FLDL2E \t\t\t# Ld log2(e) X\n\t"
10535 "FMULP \t\t\t# Q=X*log2(e)\n\t"
10536
10537 "FDUP \t\t\t# Q Q\n\t"
10538 "FRNDINT\t\t\t# int(Q) Q\n\t"
10539 "FSUB ST(1),ST(0)\t# int(Q) frac(Q)\n\t"
10540 "FISTP dword [ESP]\n\t"
10541 "F2XM1 \t\t\t# 2^frac(Q)-1 int(Q)\n\t"
10542 "FLD1 \t\t\t# 1 2^frac(Q)-1 int(Q)\n\t"
10543 "FADDP \t\t\t# 2^frac(Q) int(Q)\n\t" // could use FADD [1.000] instead
10544 "MOV EAX,[ESP]\t# Pick up int(Q)\n\t"
10545 "MOV ECX,0xFFFFF800\t# Overflow mask\n\t"
10546 "ADD EAX,1023\t\t# Double exponent bias\n\t"
10547 "MOV EBX,EAX\t\t# Preshifted biased expo\n\t"
10548 "SHL EAX,20\t\t# Shift exponent into place\n\t"
10549 "TEST EBX,ECX\t\t# Check for overflow\n\t"
10550 "CMOVne EAX,ECX\t\t# If overflow, stuff NaN into EAX\n\t"
10551 "MOV [ESP+4],EAX\t# Marshal 64-bit scaling double\n\t"
10552 "MOV [ESP+0],0\n\t"
10553 "FMUL ST(0),[ESP+0]\t# Scale\n\t"
10554
10555 "ADD ESP,8"
10556 %}
10557 ins_encode( push_stack_temp_qword,
10558 Opcode(0xD9), Opcode(0xEA), // fldl2e
10559 Opcode(0xDE), Opcode(0xC9), // fmulp
10560 pow_exp_core_encoding,
10561 pop_stack_temp_qword);
10562 ins_pipe( pipe_slow );
10563 %}
10564
10565 instruct expXD_reg(regXD dst, regXD src, regDPR1 tmp1, eAXRegI rax, eBXRegI rbx, eCXRegI rcx) %{
10566 predicate (UseSSE>=2);
10567 match(Set dst (ExpD src));
10568 effect(KILL tmp1, KILL rax, KILL rbx, KILL rcx);
10569 format %{ "SUB ESP,8\t\t# Fast-path EXP encoding\n\t"
10570 "MOVSD [ESP],$src\n\t"
10571 "FLDL2E \t\t\t# Ld log2(e) X\n\t"
10572 "FMULP \t\t\t# Q=X*log2(e) X\n\t"
10573
10574 "FDUP \t\t\t# Q Q\n\t"
10575 "FRNDINT\t\t\t# int(Q) Q\n\t"
10576 "FSUB ST(1),ST(0)\t# int(Q) frac(Q)\n\t"
10577 "FISTP dword [ESP]\n\t"
10578 "F2XM1 \t\t\t# 2^frac(Q)-1 int(Q)\n\t"
10579 "FLD1 \t\t\t# 1 2^frac(Q)-1 int(Q)\n\t"
10580 "FADDP \t\t\t# 2^frac(Q) int(Q)\n\t" // could use FADD [1.000] instead
10581 "MOV EAX,[ESP]\t# Pick up int(Q)\n\t"
10582 "MOV ECX,0xFFFFF800\t# Overflow mask\n\t"
10583 "ADD EAX,1023\t\t# Double exponent bias\n\t"
10584 "MOV EBX,EAX\t\t# Preshifted biased expo\n\t"
10585 "SHL EAX,20\t\t# Shift exponent into place\n\t"
10586 "TEST EBX,ECX\t\t# Check for overflow\n\t"
10587 "CMOVne EAX,ECX\t\t# If overflow, stuff NaN into EAX\n\t"
10588 "MOV [ESP+4],EAX\t# Marshal 64-bit scaling double\n\t"
10589 "MOV [ESP+0],0\n\t"
10590 "FMUL ST(0),[ESP+0]\t# Scale\n\t"
10591
10592 "FST_D [ESP]\n\t"
10593 "MOVSD $dst,[ESP]\n\t"
10594 "ADD ESP,8"
10595 %}
10596 ins_encode( Push_SrcXD(src),
10597 Opcode(0xD9), Opcode(0xEA), // fldl2e
10598 Opcode(0xDE), Opcode(0xC9), // fmulp
10599 pow_exp_core_encoding,
10600 Push_ResultXD(dst) );
10601 ins_pipe( pipe_slow );
10602 %}
10603
10604
10605
10606 instruct log10D_reg(regDPR1 dst, regDPR1 src) %{
10607 predicate (UseSSE<=1);
10608 // The source Double operand on FPU stack
10609 match(Set dst (Log10D src));
10610 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number
10611 // fxch ; swap ST(0) with ST(1)
10612 // fyl2x ; compute log_10(2) * log_2(x)
10613 format %{ "FLDLG2 \t\t\t#Log10\n\t"
10614 "FXCH \n\t"
10615 "FYL2X \t\t\t# Q=Log10*Log_2(x)"
10616 %}
10617 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2
10618 Opcode(0xD9), Opcode(0xC9), // fxch
10619 Opcode(0xD9), Opcode(0xF1)); // fyl2x
10620
10621 ins_pipe( pipe_slow );
10622 %}
10623
10624 instruct log10XD_reg(regXD dst, regXD src, eFlagsReg cr) %{
10625 predicate (UseSSE>=2);
10626 effect(KILL cr);
10627 match(Set dst (Log10D src));
10628 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number
10629 // fyl2x ; compute log_10(2) * log_2(x)
10630 format %{ "FLDLG2 \t\t\t#Log10\n\t"
10631 "FYL2X \t\t\t# Q=Log10*Log_2(x)"
10632 %}
10633 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2
10634 Push_SrcXD(src),
10635 Opcode(0xD9), Opcode(0xF1), // fyl2x
10636 Push_ResultXD(dst));
10637
10638 ins_pipe( pipe_slow );
10639 %}
10640
10641 instruct logD_reg(regDPR1 dst, regDPR1 src) %{
10642 predicate (UseSSE<=1);
10643 // The source Double operand on FPU stack
10644 match(Set dst (LogD src));
10645 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number
10646 // fxch ; swap ST(0) with ST(1)
10647 // fyl2x ; compute log_e(2) * log_2(x)
10648 format %{ "FLDLN2 \t\t\t#Log_e\n\t"
10649 "FXCH \n\t"
10650 "FYL2X \t\t\t# Q=Log_e*Log_2(x)"
10651 %}
10652 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2
10653 Opcode(0xD9), Opcode(0xC9), // fxch
10654 Opcode(0xD9), Opcode(0xF1)); // fyl2x
10655
10656 ins_pipe( pipe_slow );
10657 %}
10658
10659 instruct logXD_reg(regXD dst, regXD src, eFlagsReg cr) %{
10660 predicate (UseSSE>=2);
10661 effect(KILL cr);
10662 // The source and result Double operands in XMM registers
10663 match(Set dst (LogD src));
10664 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number
10665 // fyl2x ; compute log_e(2) * log_2(x)
10666 format %{ "FLDLN2 \t\t\t#Log_e\n\t"
10667 "FYL2X \t\t\t# Q=Log_e*Log_2(x)"
10668 %}
10669 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2
10670 Push_SrcXD(src),
10671 Opcode(0xD9), Opcode(0xF1), // fyl2x
10672 Push_ResultXD(dst));
10673 ins_pipe( pipe_slow );
10674 %}
10675
10676 //-------------Float Instructions-------------------------------
10677 // Float Math
10678
10679 // Code for float compare:
10680 // fcompp();
10681 // fwait(); fnstsw_ax();
10682 // sahf();
10683 // movl(dst, unordered_result);
10684 // jcc(Assembler::parity, exit);
10685 // movl(dst, less_result);
10686 // jcc(Assembler::below, exit);
10687 // movl(dst, equal_result);
10688 // jcc(Assembler::equal, exit);
10689 // movl(dst, greater_result);
10690 // exit:
10691
10692 // P6 version of float compare, sets condition codes in EFLAGS
10693 instruct cmpF_cc_P6(eFlagsRegU cr, regF src1, regF src2, eAXRegI rax) %{
10694 predicate(VM_Version::supports_cmov() && UseSSE == 0);
10695 match(Set cr (CmpF src1 src2));
10696 effect(KILL rax);
10697 ins_cost(150);
10698 format %{ "FLD $src1\n\t"
10699 "FUCOMIP ST,$src2 // P6 instruction\n\t"
10700 "JNP exit\n\t"
10701 "MOV ah,1 // saw a NaN, set CF (treat as LT)\n\t"
10702 "SAHF\n"
10703 "exit:\tNOP // avoid branch to branch" %}
10704 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
10705 ins_encode( Push_Reg_D(src1),
10706 OpcP, RegOpc(src2),
10707 cmpF_P6_fixup );
10708 ins_pipe( pipe_slow );
10709 %}
10710
10711 instruct cmpF_cc_P6CF(eFlagsRegUCF cr, regF src1, regF src2) %{
10712 predicate(VM_Version::supports_cmov() && UseSSE == 0);
10713 match(Set cr (CmpF src1 src2));
10714 ins_cost(100);
10715 format %{ "FLD $src1\n\t"
10716 "FUCOMIP ST,$src2 // P6 instruction" %}
10717 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
10718 ins_encode( Push_Reg_D(src1),
10719 OpcP, RegOpc(src2));
10720 ins_pipe( pipe_slow );
10721 %}
10722
10723
10724 // Compare & branch
10725 instruct cmpF_cc(eFlagsRegU cr, regF src1, regF src2, eAXRegI rax) %{
10726 predicate(UseSSE == 0);
10727 match(Set cr (CmpF src1 src2));
10728 effect(KILL rax);
10729 ins_cost(200);
10730 format %{ "FLD $src1\n\t"
10731 "FCOMp $src2\n\t"
10732 "FNSTSW AX\n\t"
10733 "TEST AX,0x400\n\t"
10734 "JZ,s flags\n\t"
10735 "MOV AH,1\t# unordered treat as LT\n"
10736 "flags:\tSAHF" %}
10737 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
10738 ins_encode( Push_Reg_D(src1),
10739 OpcP, RegOpc(src2),
10740 fpu_flags);
10741 ins_pipe( pipe_slow );
10742 %}
10743
10744 // Compare vs zero into -1,0,1
10745 instruct cmpF_0(eRegI dst, regF src1, immF0 zero, eAXRegI rax, eFlagsReg cr) %{
10746 predicate(UseSSE == 0);
10747 match(Set dst (CmpF3 src1 zero));
10748 effect(KILL cr, KILL rax);
10749 ins_cost(280);
10750 format %{ "FTSTF $dst,$src1" %}
10751 opcode(0xE4, 0xD9);
10752 ins_encode( Push_Reg_D(src1),
10753 OpcS, OpcP, PopFPU,
10754 CmpF_Result(dst));
10755 ins_pipe( pipe_slow );
10756 %}
10757
10758 // Compare into -1,0,1
10759 instruct cmpF_reg(eRegI dst, regF src1, regF src2, eAXRegI rax, eFlagsReg cr) %{
10760 predicate(UseSSE == 0);
10761 match(Set dst (CmpF3 src1 src2));
10762 effect(KILL cr, KILL rax);
10763 ins_cost(300);
10764 format %{ "FCMPF $dst,$src1,$src2" %}
10765 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
10766 ins_encode( Push_Reg_D(src1),
10767 OpcP, RegOpc(src2),
10768 CmpF_Result(dst));
10769 ins_pipe( pipe_slow );
10770 %}
10771
10772 // float compare and set condition codes in EFLAGS by XMM regs
10773 instruct cmpX_cc(eFlagsRegU cr, regX dst, regX src, eAXRegI rax) %{
10774 predicate(UseSSE>=1);
10775 match(Set cr (CmpF dst src));
10776 effect(KILL rax);
10777 ins_cost(145);
10778 format %{ "COMISS $dst,$src\n"
10779 "\tJNP exit\n"
10780 "\tMOV ah,1 // saw a NaN, set CF\n"
10781 "\tSAHF\n"
10782 "exit:\tNOP // avoid branch to branch" %}
10783 opcode(0x0F, 0x2F);
10784 ins_encode(OpcP, OpcS, RegReg(dst, src), cmpF_P6_fixup);
10785 ins_pipe( pipe_slow );
10786 %}
10787
10788 instruct cmpX_ccCF(eFlagsRegUCF cr, regX dst, regX src) %{
10789 predicate(UseSSE>=1);
10790 match(Set cr (CmpF dst src));
10791 ins_cost(100);
10792 format %{ "COMISS $dst,$src" %}
10793 opcode(0x0F, 0x2F);
10794 ins_encode(OpcP, OpcS, RegReg(dst, src));
10795 ins_pipe( pipe_slow );
10796 %}
10797
10798 // float compare and set condition codes in EFLAGS by XMM regs
10799 instruct cmpX_ccmem(eFlagsRegU cr, regX dst, memory src, eAXRegI rax) %{
10800 predicate(UseSSE>=1);
10801 match(Set cr (CmpF dst (LoadF src)));
10802 effect(KILL rax);
10803 ins_cost(165);
10804 format %{ "COMISS $dst,$src\n"
10805 "\tJNP exit\n"
10806 "\tMOV ah,1 // saw a NaN, set CF\n"
10807 "\tSAHF\n"
10808 "exit:\tNOP // avoid branch to branch" %}
10809 opcode(0x0F, 0x2F);
10810 ins_encode(OpcP, OpcS, RegMem(dst, src), cmpF_P6_fixup);
10811 ins_pipe( pipe_slow );
10812 %}
10813
10814 instruct cmpX_ccmemCF(eFlagsRegUCF cr, regX dst, memory src) %{
10815 predicate(UseSSE>=1);
10816 match(Set cr (CmpF dst (LoadF src)));
10817 ins_cost(100);
10818 format %{ "COMISS $dst,$src" %}
10819 opcode(0x0F, 0x2F);
10820 ins_encode(OpcP, OpcS, RegMem(dst, src));
10821 ins_pipe( pipe_slow );
10822 %}
10823
10824 // Compare into -1,0,1 in XMM
10825 instruct cmpX_reg(eRegI dst, regX src1, regX src2, eFlagsReg cr) %{
10826 predicate(UseSSE>=1);
10827 match(Set dst (CmpF3 src1 src2));
10828 effect(KILL cr);
10829 ins_cost(255);
10830 format %{ "XOR $dst,$dst\n"
10831 "\tCOMISS $src1,$src2\n"
10832 "\tJP,s nan\n"
10833 "\tJEQ,s exit\n"
10834 "\tJA,s inc\n"
10835 "nan:\tDEC $dst\n"
10836 "\tJMP,s exit\n"
10837 "inc:\tINC $dst\n"
10838 "exit:"
10839 %}
10840 opcode(0x0F, 0x2F);
10841 ins_encode(Xor_Reg(dst), OpcP, OpcS, RegReg(src1, src2), CmpX_Result(dst));
10842 ins_pipe( pipe_slow );
10843 %}
10844
10845 // Compare into -1,0,1 in XMM and memory
10846 instruct cmpX_regmem(eRegI dst, regX src1, memory mem, eFlagsReg cr) %{
10847 predicate(UseSSE>=1);
10848 match(Set dst (CmpF3 src1 (LoadF mem)));
10849 effect(KILL cr);
10850 ins_cost(275);
10851 format %{ "COMISS $src1,$mem\n"
10852 "\tMOV $dst,0\t\t# do not blow flags\n"
10853 "\tJP,s nan\n"
10854 "\tJEQ,s exit\n"
10855 "\tJA,s inc\n"
10856 "nan:\tDEC $dst\n"
10857 "\tJMP,s exit\n"
10858 "inc:\tINC $dst\n"
10859 "exit:"
10860 %}
10861 opcode(0x0F, 0x2F);
10862 ins_encode(OpcP, OpcS, RegMem(src1, mem), LdImmI(dst,0x0), CmpX_Result(dst));
10863 ins_pipe( pipe_slow );
10864 %}
10865
10866 // Spill to obtain 24-bit precision
10867 instruct subF24_reg(stackSlotF dst, regF src1, regF src2) %{
10868 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10869 match(Set dst (SubF src1 src2));
10870
10871 format %{ "FSUB $dst,$src1 - $src2" %}
10872 opcode(0xD8, 0x4); /* D8 E0+i or D8 /4 mod==0x3 ;; result in TOS */
10873 ins_encode( Push_Reg_F(src1),
10874 OpcReg_F(src2),
10875 Pop_Mem_F(dst) );
10876 ins_pipe( fpu_mem_reg_reg );
10877 %}
10878 //
10879 // This instruction does not round to 24-bits
10880 instruct subF_reg(regF dst, regF src) %{
10881 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10882 match(Set dst (SubF dst src));
10883
10884 format %{ "FSUB $dst,$src" %}
10885 opcode(0xDE, 0x5); /* DE E8+i or DE /5 */
10886 ins_encode( Push_Reg_F(src),
10887 OpcP, RegOpc(dst) );
10888 ins_pipe( fpu_reg_reg );
10889 %}
10890
10891 // Spill to obtain 24-bit precision
10892 instruct addF24_reg(stackSlotF dst, regF src1, regF src2) %{
10893 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10894 match(Set dst (AddF src1 src2));
10895
10896 format %{ "FADD $dst,$src1,$src2" %}
10897 opcode(0xD8, 0x0); /* D8 C0+i */
10898 ins_encode( Push_Reg_F(src2),
10899 OpcReg_F(src1),
10900 Pop_Mem_F(dst) );
10901 ins_pipe( fpu_mem_reg_reg );
10902 %}
10903 //
10904 // This instruction does not round to 24-bits
10905 instruct addF_reg(regF dst, regF src) %{
10906 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10907 match(Set dst (AddF dst src));
10908
10909 format %{ "FLD $src\n\t"
10910 "FADDp $dst,ST" %}
10911 opcode(0xDE, 0x0); /* DE C0+i or DE /0*/
10912 ins_encode( Push_Reg_F(src),
10913 OpcP, RegOpc(dst) );
10914 ins_pipe( fpu_reg_reg );
10915 %}
10916
10917 // Add two single precision floating point values in xmm
10918 instruct addX_reg(regX dst, regX src) %{
10919 predicate(UseSSE>=1);
10920 match(Set dst (AddF dst src));
10921 format %{ "ADDSS $dst,$src" %}
10922 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x58), RegReg(dst, src));
10923 ins_pipe( pipe_slow );
10924 %}
10925
10926 instruct addX_imm(regX dst, immXF con) %{
10927 predicate(UseSSE>=1);
10928 match(Set dst (AddF dst con));
10929 format %{ "ADDSS $dst,[$con]" %}
10930 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x58), LdImmX(dst, con) );
10931 ins_pipe( pipe_slow );
10932 %}
10933
10934 instruct addX_mem(regX dst, memory mem) %{
10935 predicate(UseSSE>=1);
10936 match(Set dst (AddF dst (LoadF mem)));
10937 format %{ "ADDSS $dst,$mem" %}
10938 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x58), RegMem(dst, mem));
10939 ins_pipe( pipe_slow );
10940 %}
10941
10942 // Subtract two single precision floating point values in xmm
10943 instruct subX_reg(regX dst, regX src) %{
10944 predicate(UseSSE>=1);
10945 match(Set dst (SubF dst src));
10946 format %{ "SUBSS $dst,$src" %}
10947 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5C), RegReg(dst, src));
10948 ins_pipe( pipe_slow );
10949 %}
10950
10951 instruct subX_imm(regX dst, immXF con) %{
10952 predicate(UseSSE>=1);
10953 match(Set dst (SubF dst con));
10954 format %{ "SUBSS $dst,[$con]" %}
10955 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5C), LdImmX(dst, con) );
10956 ins_pipe( pipe_slow );
10957 %}
10958
10959 instruct subX_mem(regX dst, memory mem) %{
10960 predicate(UseSSE>=1);
10961 match(Set dst (SubF dst (LoadF mem)));
10962 format %{ "SUBSS $dst,$mem" %}
10963 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5C), RegMem(dst,mem));
10964 ins_pipe( pipe_slow );
10965 %}
10966
10967 // Multiply two single precision floating point values in xmm
10968 instruct mulX_reg(regX dst, regX src) %{
10969 predicate(UseSSE>=1);
10970 match(Set dst (MulF dst src));
10971 format %{ "MULSS $dst,$src" %}
10972 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x59), RegReg(dst, src));
10973 ins_pipe( pipe_slow );
10974 %}
10975
10976 instruct mulX_imm(regX dst, immXF con) %{
10977 predicate(UseSSE>=1);
10978 match(Set dst (MulF dst con));
10979 format %{ "MULSS $dst,[$con]" %}
10980 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x59), LdImmX(dst, con) );
10981 ins_pipe( pipe_slow );
10982 %}
10983
10984 instruct mulX_mem(regX dst, memory mem) %{
10985 predicate(UseSSE>=1);
10986 match(Set dst (MulF dst (LoadF mem)));
10987 format %{ "MULSS $dst,$mem" %}
10988 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x59), RegMem(dst,mem));
10989 ins_pipe( pipe_slow );
10990 %}
10991
10992 // Divide two single precision floating point values in xmm
10993 instruct divX_reg(regX dst, regX src) %{
10994 predicate(UseSSE>=1);
10995 match(Set dst (DivF dst src));
10996 format %{ "DIVSS $dst,$src" %}
10997 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5E), RegReg(dst, src));
10998 ins_pipe( pipe_slow );
10999 %}
11000
11001 instruct divX_imm(regX dst, immXF con) %{
11002 predicate(UseSSE>=1);
11003 match(Set dst (DivF dst con));
11004 format %{ "DIVSS $dst,[$con]" %}
11005 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5E), LdImmX(dst, con) );
11006 ins_pipe( pipe_slow );
11007 %}
11008
11009 instruct divX_mem(regX dst, memory mem) %{
11010 predicate(UseSSE>=1);
11011 match(Set dst (DivF dst (LoadF mem)));
11012 format %{ "DIVSS $dst,$mem" %}
11013 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5E), RegMem(dst,mem));
11014 ins_pipe( pipe_slow );
11015 %}
11016
11017 // Get the square root of a single precision floating point values in xmm
11018 instruct sqrtX_reg(regX dst, regX src) %{
11019 predicate(UseSSE>=1);
11020 match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
11021 format %{ "SQRTSS $dst,$src" %}
11022 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x51), RegReg(dst, src));
11023 ins_pipe( pipe_slow );
11024 %}
11025
11026 instruct sqrtX_mem(regX dst, memory mem) %{
11027 predicate(UseSSE>=1);
11028 match(Set dst (ConvD2F (SqrtD (ConvF2D (LoadF mem)))));
11029 format %{ "SQRTSS $dst,$mem" %}
11030 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x51), RegMem(dst, mem));
11031 ins_pipe( pipe_slow );
11032 %}
11033
11034 // Get the square root of a double precision floating point values in xmm
11035 instruct sqrtXD_reg(regXD dst, regXD src) %{
11036 predicate(UseSSE>=2);
11037 match(Set dst (SqrtD src));
11038 format %{ "SQRTSD $dst,$src" %}
11039 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x51), RegReg(dst, src));
11040 ins_pipe( pipe_slow );
11041 %}
11042
11043 instruct sqrtXD_mem(regXD dst, memory mem) %{
11044 predicate(UseSSE>=2);
11045 match(Set dst (SqrtD (LoadD mem)));
11046 format %{ "SQRTSD $dst,$mem" %}
11047 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x51), RegMem(dst, mem));
11048 ins_pipe( pipe_slow );
11049 %}
11050
11051 instruct absF_reg(regFPR1 dst, regFPR1 src) %{
11052 predicate(UseSSE==0);
11053 match(Set dst (AbsF src));
11054 ins_cost(100);
11055 format %{ "FABS" %}
11056 opcode(0xE1, 0xD9);
11057 ins_encode( OpcS, OpcP );
11058 ins_pipe( fpu_reg_reg );
11059 %}
11060
11061 instruct absX_reg(regX dst ) %{
11062 predicate(UseSSE>=1);
11063 match(Set dst (AbsF dst));
11064 format %{ "ANDPS $dst,[0x7FFFFFFF]\t# ABS F by sign masking" %}
11065 ins_encode( AbsXF_encoding(dst));
11066 ins_pipe( pipe_slow );
11067 %}
11068
11069 instruct negF_reg(regFPR1 dst, regFPR1 src) %{
11070 predicate(UseSSE==0);
11071 match(Set dst (NegF src));
11072 ins_cost(100);
11073 format %{ "FCHS" %}
11074 opcode(0xE0, 0xD9);
11075 ins_encode( OpcS, OpcP );
11076 ins_pipe( fpu_reg_reg );
11077 %}
11078
11079 instruct negX_reg( regX dst ) %{
11080 predicate(UseSSE>=1);
11081 match(Set dst (NegF dst));
11082 format %{ "XORPS $dst,[0x80000000]\t# CHS F by sign flipping" %}
11083 ins_encode( NegXF_encoding(dst));
11084 ins_pipe( pipe_slow );
11085 %}
11086
11087 // Cisc-alternate to addF_reg
11088 // Spill to obtain 24-bit precision
11089 instruct addF24_reg_mem(stackSlotF dst, regF src1, memory src2) %{
11090 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11091 match(Set dst (AddF src1 (LoadF src2)));
11092
11093 format %{ "FLD $src2\n\t"
11094 "FADD ST,$src1\n\t"
11095 "FSTP_S $dst" %}
11096 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
11097 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
11098 OpcReg_F(src1),
11099 Pop_Mem_F(dst) );
11100 ins_pipe( fpu_mem_reg_mem );
11101 %}
11102 //
11103 // Cisc-alternate to addF_reg
11104 // This instruction does not round to 24-bits
11105 instruct addF_reg_mem(regF dst, memory src) %{
11106 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11107 match(Set dst (AddF dst (LoadF src)));
11108
11109 format %{ "FADD $dst,$src" %}
11110 opcode(0xDE, 0x0, 0xD9); /* DE C0+i or DE /0*/ /* LoadF D9 /0 */
11111 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
11112 OpcP, RegOpc(dst) );
11113 ins_pipe( fpu_reg_mem );
11114 %}
11115
11116 // // Following two instructions for _222_mpegaudio
11117 // Spill to obtain 24-bit precision
11118 instruct addF24_mem_reg(stackSlotF dst, regF src2, memory src1 ) %{
11119 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11120 match(Set dst (AddF src1 src2));
11121
11122 format %{ "FADD $dst,$src1,$src2" %}
11123 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
11124 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src1),
11125 OpcReg_F(src2),
11126 Pop_Mem_F(dst) );
11127 ins_pipe( fpu_mem_reg_mem );
11128 %}
11129
11130 // Cisc-spill variant
11131 // Spill to obtain 24-bit precision
11132 instruct addF24_mem_cisc(stackSlotF dst, memory src1, memory src2) %{
11133 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11134 match(Set dst (AddF src1 (LoadF src2)));
11135
11136 format %{ "FADD $dst,$src1,$src2 cisc" %}
11137 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
11138 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
11139 set_instruction_start,
11140 OpcP, RMopc_Mem(secondary,src1),
11141 Pop_Mem_F(dst) );
11142 ins_pipe( fpu_mem_mem_mem );
11143 %}
11144
11145 // Spill to obtain 24-bit precision
11146 instruct addF24_mem_mem(stackSlotF dst, memory src1, memory src2) %{
11147 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11148 match(Set dst (AddF src1 src2));
11149
11150 format %{ "FADD $dst,$src1,$src2" %}
11151 opcode(0xD8, 0x0, 0xD9); /* D8 /0 */ /* LoadF D9 /0 */
11152 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
11153 set_instruction_start,
11154 OpcP, RMopc_Mem(secondary,src1),
11155 Pop_Mem_F(dst) );
11156 ins_pipe( fpu_mem_mem_mem );
11157 %}
11158
11159
11160 // Spill to obtain 24-bit precision
11161 instruct addF24_reg_imm(stackSlotF dst, regF src1, immF src2) %{
11162 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11163 match(Set dst (AddF src1 src2));
11164 format %{ "FLD $src1\n\t"
11165 "FADD $src2\n\t"
11166 "FSTP_S $dst" %}
11167 opcode(0xD8, 0x00); /* D8 /0 */
11168 ins_encode( Push_Reg_F(src1),
11169 Opc_MemImm_F(src2),
11170 Pop_Mem_F(dst));
11171 ins_pipe( fpu_mem_reg_con );
11172 %}
11173 //
11174 // This instruction does not round to 24-bits
11175 instruct addF_reg_imm(regF dst, regF src1, immF src2) %{
11176 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11177 match(Set dst (AddF src1 src2));
11178 format %{ "FLD $src1\n\t"
11179 "FADD $src2\n\t"
11180 "FSTP_S $dst" %}
11181 opcode(0xD8, 0x00); /* D8 /0 */
11182 ins_encode( Push_Reg_F(src1),
11183 Opc_MemImm_F(src2),
11184 Pop_Reg_F(dst));
11185 ins_pipe( fpu_reg_reg_con );
11186 %}
11187
11188 // Spill to obtain 24-bit precision
11189 instruct mulF24_reg(stackSlotF dst, regF src1, regF src2) %{
11190 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11191 match(Set dst (MulF src1 src2));
11192
11193 format %{ "FLD $src1\n\t"
11194 "FMUL $src2\n\t"
11195 "FSTP_S $dst" %}
11196 opcode(0xD8, 0x1); /* D8 C8+i or D8 /1 ;; result in TOS */
11197 ins_encode( Push_Reg_F(src1),
11198 OpcReg_F(src2),
11199 Pop_Mem_F(dst) );
11200 ins_pipe( fpu_mem_reg_reg );
11201 %}
11202 //
11203 // This instruction does not round to 24-bits
11204 instruct mulF_reg(regF dst, regF src1, regF src2) %{
11205 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11206 match(Set dst (MulF src1 src2));
11207
11208 format %{ "FLD $src1\n\t"
11209 "FMUL $src2\n\t"
11210 "FSTP_S $dst" %}
11211 opcode(0xD8, 0x1); /* D8 C8+i */
11212 ins_encode( Push_Reg_F(src2),
11213 OpcReg_F(src1),
11214 Pop_Reg_F(dst) );
11215 ins_pipe( fpu_reg_reg_reg );
11216 %}
11217
11218
11219 // Spill to obtain 24-bit precision
11220 // Cisc-alternate to reg-reg multiply
11221 instruct mulF24_reg_mem(stackSlotF dst, regF src1, memory src2) %{
11222 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11223 match(Set dst (MulF src1 (LoadF src2)));
11224
11225 format %{ "FLD_S $src2\n\t"
11226 "FMUL $src1\n\t"
11227 "FSTP_S $dst" %}
11228 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or DE /1*/ /* LoadF D9 /0 */
11229 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
11230 OpcReg_F(src1),
11231 Pop_Mem_F(dst) );
11232 ins_pipe( fpu_mem_reg_mem );
11233 %}
11234 //
11235 // This instruction does not round to 24-bits
11236 // Cisc-alternate to reg-reg multiply
11237 instruct mulF_reg_mem(regF dst, regF src1, memory src2) %{
11238 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11239 match(Set dst (MulF src1 (LoadF src2)));
11240
11241 format %{ "FMUL $dst,$src1,$src2" %}
11242 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */ /* LoadF D9 /0 */
11243 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
11244 OpcReg_F(src1),
11245 Pop_Reg_F(dst) );
11246 ins_pipe( fpu_reg_reg_mem );
11247 %}
11248
11249 // Spill to obtain 24-bit precision
11250 instruct mulF24_mem_mem(stackSlotF dst, memory src1, memory src2) %{
11251 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11252 match(Set dst (MulF src1 src2));
11253
11254 format %{ "FMUL $dst,$src1,$src2" %}
11255 opcode(0xD8, 0x1, 0xD9); /* D8 /1 */ /* LoadF D9 /0 */
11256 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
11257 set_instruction_start,
11258 OpcP, RMopc_Mem(secondary,src1),
11259 Pop_Mem_F(dst) );
11260 ins_pipe( fpu_mem_mem_mem );
11261 %}
11262
11263 // Spill to obtain 24-bit precision
11264 instruct mulF24_reg_imm(stackSlotF dst, regF src1, immF src2) %{
11265 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11266 match(Set dst (MulF src1 src2));
11267
11268 format %{ "FMULc $dst,$src1,$src2" %}
11269 opcode(0xD8, 0x1); /* D8 /1*/
11270 ins_encode( Push_Reg_F(src1),
11271 Opc_MemImm_F(src2),
11272 Pop_Mem_F(dst));
11273 ins_pipe( fpu_mem_reg_con );
11274 %}
11275 //
11276 // This instruction does not round to 24-bits
11277 instruct mulF_reg_imm(regF dst, regF src1, immF src2) %{
11278 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11279 match(Set dst (MulF src1 src2));
11280
11281 format %{ "FMULc $dst. $src1, $src2" %}
11282 opcode(0xD8, 0x1); /* D8 /1*/
11283 ins_encode( Push_Reg_F(src1),
11284 Opc_MemImm_F(src2),
11285 Pop_Reg_F(dst));
11286 ins_pipe( fpu_reg_reg_con );
11287 %}
11288
11289
11290 //
11291 // MACRO1 -- subsume unshared load into mulF
11292 // This instruction does not round to 24-bits
11293 instruct mulF_reg_load1(regF dst, regF src, memory mem1 ) %{
11294 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11295 match(Set dst (MulF (LoadF mem1) src));
11296
11297 format %{ "FLD $mem1 ===MACRO1===\n\t"
11298 "FMUL ST,$src\n\t"
11299 "FSTP $dst" %}
11300 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or D8 /1 */ /* LoadF D9 /0 */
11301 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem1),
11302 OpcReg_F(src),
11303 Pop_Reg_F(dst) );
11304 ins_pipe( fpu_reg_reg_mem );
11305 %}
11306 //
11307 // MACRO2 -- addF a mulF which subsumed an unshared load
11308 // This instruction does not round to 24-bits
11309 instruct addF_mulF_reg_load1(regF dst, memory mem1, regF src1, regF src2) %{
11310 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11311 match(Set dst (AddF (MulF (LoadF mem1) src1) src2));
11312 ins_cost(95);
11313
11314 format %{ "FLD $mem1 ===MACRO2===\n\t"
11315 "FMUL ST,$src1 subsume mulF left load\n\t"
11316 "FADD ST,$src2\n\t"
11317 "FSTP $dst" %}
11318 opcode(0xD9); /* LoadF D9 /0 */
11319 ins_encode( OpcP, RMopc_Mem(0x00,mem1),
11320 FMul_ST_reg(src1),
11321 FAdd_ST_reg(src2),
11322 Pop_Reg_F(dst) );
11323 ins_pipe( fpu_reg_mem_reg_reg );
11324 %}
11325
11326 // MACRO3 -- addF a mulF
11327 // This instruction does not round to 24-bits. It is a '2-address'
11328 // instruction in that the result goes back to src2. This eliminates
11329 // a move from the macro; possibly the register allocator will have
11330 // to add it back (and maybe not).
11331 instruct addF_mulF_reg(regF src2, regF src1, regF src0) %{
11332 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11333 match(Set src2 (AddF (MulF src0 src1) src2));
11334
11335 format %{ "FLD $src0 ===MACRO3===\n\t"
11336 "FMUL ST,$src1\n\t"
11337 "FADDP $src2,ST" %}
11338 opcode(0xD9); /* LoadF D9 /0 */
11339 ins_encode( Push_Reg_F(src0),
11340 FMul_ST_reg(src1),
11341 FAddP_reg_ST(src2) );
11342 ins_pipe( fpu_reg_reg_reg );
11343 %}
11344
11345 // MACRO4 -- divF subF
11346 // This instruction does not round to 24-bits
11347 instruct subF_divF_reg(regF dst, regF src1, regF src2, regF src3) %{
11348 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11349 match(Set dst (DivF (SubF src2 src1) src3));
11350
11351 format %{ "FLD $src2 ===MACRO4===\n\t"
11352 "FSUB ST,$src1\n\t"
11353 "FDIV ST,$src3\n\t"
11354 "FSTP $dst" %}
11355 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
11356 ins_encode( Push_Reg_F(src2),
11357 subF_divF_encode(src1,src3),
11358 Pop_Reg_F(dst) );
11359 ins_pipe( fpu_reg_reg_reg_reg );
11360 %}
11361
11362 // Spill to obtain 24-bit precision
11363 instruct divF24_reg(stackSlotF dst, regF src1, regF src2) %{
11364 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11365 match(Set dst (DivF src1 src2));
11366
11367 format %{ "FDIV $dst,$src1,$src2" %}
11368 opcode(0xD8, 0x6); /* D8 F0+i or DE /6*/
11369 ins_encode( Push_Reg_F(src1),
11370 OpcReg_F(src2),
11371 Pop_Mem_F(dst) );
11372 ins_pipe( fpu_mem_reg_reg );
11373 %}
11374 //
11375 // This instruction does not round to 24-bits
11376 instruct divF_reg(regF dst, regF src) %{
11377 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11378 match(Set dst (DivF dst src));
11379
11380 format %{ "FDIV $dst,$src" %}
11381 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
11382 ins_encode( Push_Reg_F(src),
11383 OpcP, RegOpc(dst) );
11384 ins_pipe( fpu_reg_reg );
11385 %}
11386
11387
11388 // Spill to obtain 24-bit precision
11389 instruct modF24_reg(stackSlotF dst, regF src1, regF src2, eAXRegI rax, eFlagsReg cr) %{
11390 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
11391 match(Set dst (ModF src1 src2));
11392 effect(KILL rax, KILL cr); // emitModD() uses EAX and EFLAGS
11393
11394 format %{ "FMOD $dst,$src1,$src2" %}
11395 ins_encode( Push_Reg_Mod_D(src1, src2),
11396 emitModD(),
11397 Push_Result_Mod_D(src2),
11398 Pop_Mem_F(dst));
11399 ins_pipe( pipe_slow );
11400 %}
11401 //
11402 // This instruction does not round to 24-bits
11403 instruct modF_reg(regF dst, regF src, eAXRegI rax, eFlagsReg cr) %{
11404 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
11405 match(Set dst (ModF dst src));
11406 effect(KILL rax, KILL cr); // emitModD() uses EAX and EFLAGS
11407
11408 format %{ "FMOD $dst,$src" %}
11409 ins_encode(Push_Reg_Mod_D(dst, src),
11410 emitModD(),
11411 Push_Result_Mod_D(src),
11412 Pop_Reg_F(dst));
11413 ins_pipe( pipe_slow );
11414 %}
11415
11416 instruct modX_reg(regX dst, regX src0, regX src1, eAXRegI rax, eFlagsReg cr) %{
11417 predicate(UseSSE>=1);
11418 match(Set dst (ModF src0 src1));
11419 effect(KILL rax, KILL cr);
11420 format %{ "SUB ESP,4\t # FMOD\n"
11421 "\tMOVSS [ESP+0],$src1\n"
11422 "\tFLD_S [ESP+0]\n"
11423 "\tMOVSS [ESP+0],$src0\n"
11424 "\tFLD_S [ESP+0]\n"
11425 "loop:\tFPREM\n"
11426 "\tFWAIT\n"
11427 "\tFNSTSW AX\n"
11428 "\tSAHF\n"
11429 "\tJP loop\n"
11430 "\tFSTP_S [ESP+0]\n"
11431 "\tMOVSS $dst,[ESP+0]\n"
11432 "\tADD ESP,4\n"
11433 "\tFSTP ST0\t # Restore FPU Stack"
11434 %}
11435 ins_cost(250);
11436 ins_encode( Push_ModX_encoding(src0, src1), emitModD(), Push_ResultX(dst,0x4), PopFPU);
11437 ins_pipe( pipe_slow );
11438 %}
11439
11440
11441 //----------Arithmetic Conversion Instructions---------------------------------
11442 // The conversions operations are all Alpha sorted. Please keep it that way!
11443
11444 instruct roundFloat_mem_reg(stackSlotF dst, regF src) %{
11445 predicate(UseSSE==0);
11446 match(Set dst (RoundFloat src));
11447 ins_cost(125);
11448 format %{ "FST_S $dst,$src\t# F-round" %}
11449 ins_encode( Pop_Mem_Reg_F(dst, src) );
11450 ins_pipe( fpu_mem_reg );
11451 %}
11452
11453 instruct roundDouble_mem_reg(stackSlotD dst, regD src) %{
11454 predicate(UseSSE<=1);
11455 match(Set dst (RoundDouble src));
11456 ins_cost(125);
11457 format %{ "FST_D $dst,$src\t# D-round" %}
11458 ins_encode( Pop_Mem_Reg_D(dst, src) );
11459 ins_pipe( fpu_mem_reg );
11460 %}
11461
11462 // Force rounding to 24-bit precision and 6-bit exponent
11463 instruct convD2F_reg(stackSlotF dst, regD src) %{
11464 predicate(UseSSE==0);
11465 match(Set dst (ConvD2F src));
11466 format %{ "FST_S $dst,$src\t# F-round" %}
11467 expand %{
11468 roundFloat_mem_reg(dst,src);
11469 %}
11470 %}
11471
11472 // Force rounding to 24-bit precision and 6-bit exponent
11473 instruct convD2X_reg(regX dst, regD src, eFlagsReg cr) %{
11474 predicate(UseSSE==1);
11475 match(Set dst (ConvD2F src));
11476 effect( KILL cr );
11477 format %{ "SUB ESP,4\n\t"
11478 "FST_S [ESP],$src\t# F-round\n\t"
11479 "MOVSS $dst,[ESP]\n\t"
11480 "ADD ESP,4" %}
11481 ins_encode( D2X_encoding(dst, src) );
11482 ins_pipe( pipe_slow );
11483 %}
11484
11485 // Force rounding double precision to single precision
11486 instruct convXD2X_reg(regX dst, regXD src) %{
11487 predicate(UseSSE>=2);
11488 match(Set dst (ConvD2F src));
11489 format %{ "CVTSD2SS $dst,$src\t# F-round" %}
11490 opcode(0xF2, 0x0F, 0x5A);
11491 ins_encode( OpcP, OpcS, Opcode(tertiary), RegReg(dst, src));
11492 ins_pipe( pipe_slow );
11493 %}
11494
11495 instruct convF2D_reg_reg(regD dst, regF src) %{
11496 predicate(UseSSE==0);
11497 match(Set dst (ConvF2D src));
11498 format %{ "FST_S $dst,$src\t# D-round" %}
11499 ins_encode( Pop_Reg_Reg_D(dst, src));
11500 ins_pipe( fpu_reg_reg );
11501 %}
11502
11503 instruct convF2D_reg(stackSlotD dst, regF src) %{
11504 predicate(UseSSE==1);
11505 match(Set dst (ConvF2D src));
11506 format %{ "FST_D $dst,$src\t# D-round" %}
11507 expand %{
11508 roundDouble_mem_reg(dst,src);
11509 %}
11510 %}
11511
11512 instruct convX2D_reg(regD dst, regX src, eFlagsReg cr) %{
11513 predicate(UseSSE==1);
11514 match(Set dst (ConvF2D src));
11515 effect( KILL cr );
11516 format %{ "SUB ESP,4\n\t"
11517 "MOVSS [ESP] $src\n\t"
11518 "FLD_S [ESP]\n\t"
11519 "ADD ESP,4\n\t"
11520 "FSTP $dst\t# D-round" %}
11521 ins_encode( X2D_encoding(dst, src), Pop_Reg_D(dst));
11522 ins_pipe( pipe_slow );
11523 %}
11524
11525 instruct convX2XD_reg(regXD dst, regX src) %{
11526 predicate(UseSSE>=2);
11527 match(Set dst (ConvF2D src));
11528 format %{ "CVTSS2SD $dst,$src\t# D-round" %}
11529 opcode(0xF3, 0x0F, 0x5A);
11530 ins_encode( OpcP, OpcS, Opcode(tertiary), RegReg(dst, src));
11531 ins_pipe( pipe_slow );
11532 %}
11533
11534 // Convert a double to an int. If the double is a NAN, stuff a zero in instead.
11535 instruct convD2I_reg_reg( eAXRegI dst, eDXRegI tmp, regD src, eFlagsReg cr ) %{
11536 predicate(UseSSE<=1);
11537 match(Set dst (ConvD2I src));
11538 effect( KILL tmp, KILL cr );
11539 format %{ "FLD $src\t# Convert double to int \n\t"
11540 "FLDCW trunc mode\n\t"
11541 "SUB ESP,4\n\t"
11542 "FISTp [ESP + #0]\n\t"
11543 "FLDCW std/24-bit mode\n\t"
11544 "POP EAX\n\t"
11545 "CMP EAX,0x80000000\n\t"
11546 "JNE,s fast\n\t"
11547 "FLD_D $src\n\t"
11548 "CALL d2i_wrapper\n"
11549 "fast:" %}
11550 ins_encode( Push_Reg_D(src), D2I_encoding(src) );
11551 ins_pipe( pipe_slow );
11552 %}
11553
11554 // Convert a double to an int. If the double is a NAN, stuff a zero in instead.
11555 instruct convXD2I_reg_reg( eAXRegI dst, eDXRegI tmp, regXD src, eFlagsReg cr ) %{
11556 predicate(UseSSE>=2);
11557 match(Set dst (ConvD2I src));
11558 effect( KILL tmp, KILL cr );
11559 format %{ "CVTTSD2SI $dst, $src\n\t"
11560 "CMP $dst,0x80000000\n\t"
11561 "JNE,s fast\n\t"
11562 "SUB ESP, 8\n\t"
11563 "MOVSD [ESP], $src\n\t"
11564 "FLD_D [ESP]\n\t"
11565 "ADD ESP, 8\n\t"
11566 "CALL d2i_wrapper\n"
11567 "fast:" %}
11568 opcode(0x1); // double-precision conversion
11569 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x2C), FX2I_encoding(src,dst));
11570 ins_pipe( pipe_slow );
11571 %}
11572
11573 instruct convD2L_reg_reg( eADXRegL dst, regD src, eFlagsReg cr ) %{
11574 predicate(UseSSE<=1);
11575 match(Set dst (ConvD2L src));
11576 effect( KILL cr );
11577 format %{ "FLD $src\t# Convert double to long\n\t"
11578 "FLDCW trunc mode\n\t"
11579 "SUB ESP,8\n\t"
11580 "FISTp [ESP + #0]\n\t"
11581 "FLDCW std/24-bit mode\n\t"
11582 "POP EAX\n\t"
11583 "POP EDX\n\t"
11584 "CMP EDX,0x80000000\n\t"
11585 "JNE,s fast\n\t"
11586 "TEST EAX,EAX\n\t"
11587 "JNE,s fast\n\t"
11588 "FLD $src\n\t"
11589 "CALL d2l_wrapper\n"
11590 "fast:" %}
11591 ins_encode( Push_Reg_D(src), D2L_encoding(src) );
11592 ins_pipe( pipe_slow );
11593 %}
11594
11595 // XMM lacks a float/double->long conversion, so use the old FPU stack.
11596 instruct convXD2L_reg_reg( eADXRegL dst, regXD src, eFlagsReg cr ) %{
11597 predicate (UseSSE>=2);
11598 match(Set dst (ConvD2L src));
11599 effect( KILL cr );
11600 format %{ "SUB ESP,8\t# Convert double to long\n\t"
11601 "MOVSD [ESP],$src\n\t"
11602 "FLD_D [ESP]\n\t"
11603 "FLDCW trunc mode\n\t"
11604 "FISTp [ESP + #0]\n\t"
11605 "FLDCW std/24-bit mode\n\t"
11606 "POP EAX\n\t"
11607 "POP EDX\n\t"
11608 "CMP EDX,0x80000000\n\t"
11609 "JNE,s fast\n\t"
11610 "TEST EAX,EAX\n\t"
11611 "JNE,s fast\n\t"
11612 "SUB ESP,8\n\t"
11613 "MOVSD [ESP],$src\n\t"
11614 "FLD_D [ESP]\n\t"
11615 "CALL d2l_wrapper\n"
11616 "fast:" %}
11617 ins_encode( XD2L_encoding(src) );
11618 ins_pipe( pipe_slow );
11619 %}
11620
11621 // Convert a double to an int. Java semantics require we do complex
11622 // manglations in the corner cases. So we set the rounding mode to
11623 // 'zero', store the darned double down as an int, and reset the
11624 // rounding mode to 'nearest'. The hardware stores a flag value down
11625 // if we would overflow or converted a NAN; we check for this and
11626 // and go the slow path if needed.
11627 instruct convF2I_reg_reg(eAXRegI dst, eDXRegI tmp, regF src, eFlagsReg cr ) %{
11628 predicate(UseSSE==0);
11629 match(Set dst (ConvF2I src));
11630 effect( KILL tmp, KILL cr );
11631 format %{ "FLD $src\t# Convert float to int \n\t"
11632 "FLDCW trunc mode\n\t"
11633 "SUB ESP,4\n\t"
11634 "FISTp [ESP + #0]\n\t"
11635 "FLDCW std/24-bit mode\n\t"
11636 "POP EAX\n\t"
11637 "CMP EAX,0x80000000\n\t"
11638 "JNE,s fast\n\t"
11639 "FLD $src\n\t"
11640 "CALL d2i_wrapper\n"
11641 "fast:" %}
11642 // D2I_encoding works for F2I
11643 ins_encode( Push_Reg_F(src), D2I_encoding(src) );
11644 ins_pipe( pipe_slow );
11645 %}
11646
11647 // Convert a float in xmm to an int reg.
11648 instruct convX2I_reg(eAXRegI dst, eDXRegI tmp, regX src, eFlagsReg cr ) %{
11649 predicate(UseSSE>=1);
11650 match(Set dst (ConvF2I src));
11651 effect( KILL tmp, KILL cr );
11652 format %{ "CVTTSS2SI $dst, $src\n\t"
11653 "CMP $dst,0x80000000\n\t"
11654 "JNE,s fast\n\t"
11655 "SUB ESP, 4\n\t"
11656 "MOVSS [ESP], $src\n\t"
11657 "FLD [ESP]\n\t"
11658 "ADD ESP, 4\n\t"
11659 "CALL d2i_wrapper\n"
11660 "fast:" %}
11661 opcode(0x0); // single-precision conversion
11662 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x2C), FX2I_encoding(src,dst));
11663 ins_pipe( pipe_slow );
11664 %}
11665
11666 instruct convF2L_reg_reg( eADXRegL dst, regF src, eFlagsReg cr ) %{
11667 predicate(UseSSE==0);
11668 match(Set dst (ConvF2L src));
11669 effect( KILL cr );
11670 format %{ "FLD $src\t# Convert float to long\n\t"
11671 "FLDCW trunc mode\n\t"
11672 "SUB ESP,8\n\t"
11673 "FISTp [ESP + #0]\n\t"
11674 "FLDCW std/24-bit mode\n\t"
11675 "POP EAX\n\t"
11676 "POP EDX\n\t"
11677 "CMP EDX,0x80000000\n\t"
11678 "JNE,s fast\n\t"
11679 "TEST EAX,EAX\n\t"
11680 "JNE,s fast\n\t"
11681 "FLD $src\n\t"
11682 "CALL d2l_wrapper\n"
11683 "fast:" %}
11684 // D2L_encoding works for F2L
11685 ins_encode( Push_Reg_F(src), D2L_encoding(src) );
11686 ins_pipe( pipe_slow );
11687 %}
11688
11689 // XMM lacks a float/double->long conversion, so use the old FPU stack.
11690 instruct convX2L_reg_reg( eADXRegL dst, regX src, eFlagsReg cr ) %{
11691 predicate (UseSSE>=1);
11692 match(Set dst (ConvF2L src));
11693 effect( KILL cr );
11694 format %{ "SUB ESP,8\t# Convert float to long\n\t"
11695 "MOVSS [ESP],$src\n\t"
11696 "FLD_S [ESP]\n\t"
11697 "FLDCW trunc mode\n\t"
11698 "FISTp [ESP + #0]\n\t"
11699 "FLDCW std/24-bit mode\n\t"
11700 "POP EAX\n\t"
11701 "POP EDX\n\t"
11702 "CMP EDX,0x80000000\n\t"
11703 "JNE,s fast\n\t"
11704 "TEST EAX,EAX\n\t"
11705 "JNE,s fast\n\t"
11706 "SUB ESP,4\t# Convert float to long\n\t"
11707 "MOVSS [ESP],$src\n\t"
11708 "FLD_S [ESP]\n\t"
11709 "ADD ESP,4\n\t"
11710 "CALL d2l_wrapper\n"
11711 "fast:" %}
11712 ins_encode( X2L_encoding(src) );
11713 ins_pipe( pipe_slow );
11714 %}
11715
11716 instruct convI2D_reg(regD dst, stackSlotI src) %{
11717 predicate( UseSSE<=1 );
11718 match(Set dst (ConvI2D src));
11719 format %{ "FILD $src\n\t"
11720 "FSTP $dst" %}
11721 opcode(0xDB, 0x0); /* DB /0 */
11722 ins_encode(Push_Mem_I(src), Pop_Reg_D(dst));
11723 ins_pipe( fpu_reg_mem );
11724 %}
11725
11726 instruct convI2XD_reg(regXD dst, eRegI src) %{
11727 predicate( UseSSE>=2 && !UseXmmI2D );
11728 match(Set dst (ConvI2D src));
11729 format %{ "CVTSI2SD $dst,$src" %}
11730 opcode(0xF2, 0x0F, 0x2A);
11731 ins_encode( OpcP, OpcS, Opcode(tertiary), RegReg(dst, src));
11732 ins_pipe( pipe_slow );
11733 %}
11734
11735 instruct convI2XD_mem(regXD dst, memory mem) %{
11736 predicate( UseSSE>=2 );
11737 match(Set dst (ConvI2D (LoadI mem)));
11738 format %{ "CVTSI2SD $dst,$mem" %}
11739 opcode(0xF2, 0x0F, 0x2A);
11740 ins_encode( OpcP, OpcS, Opcode(tertiary), RegMem(dst, mem));
11741 ins_pipe( pipe_slow );
11742 %}
11743
11744 instruct convXI2XD_reg(regXD dst, eRegI src)
11745 %{
11746 predicate( UseSSE>=2 && UseXmmI2D );
11747 match(Set dst (ConvI2D src));
11748
11749 format %{ "MOVD $dst,$src\n\t"
11750 "CVTDQ2PD $dst,$dst\t# i2d" %}
11751 ins_encode %{
11752 __ movdl($dst$$XMMRegister, $src$$Register);
11753 __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister);
11754 %}
11755 ins_pipe(pipe_slow); // XXX
11756 %}
11757
11758 instruct convI2D_mem(regD dst, memory mem) %{
11759 predicate( UseSSE<=1 && !Compile::current()->select_24_bit_instr());
11760 match(Set dst (ConvI2D (LoadI mem)));
11761 format %{ "FILD $mem\n\t"
11762 "FSTP $dst" %}
11763 opcode(0xDB); /* DB /0 */
11764 ins_encode( OpcP, RMopc_Mem(0x00,mem),
11765 Pop_Reg_D(dst));
11766 ins_pipe( fpu_reg_mem );
11767 %}
11768
11769 // Convert a byte to a float; no rounding step needed.
11770 instruct conv24I2F_reg(regF dst, stackSlotI src) %{
11771 predicate( UseSSE==0 && n->in(1)->Opcode() == Op_AndI && n->in(1)->in(2)->is_Con() && n->in(1)->in(2)->get_int() == 255 );
11772 match(Set dst (ConvI2F src));
11773 format %{ "FILD $src\n\t"
11774 "FSTP $dst" %}
11775
11776 opcode(0xDB, 0x0); /* DB /0 */
11777 ins_encode(Push_Mem_I(src), Pop_Reg_F(dst));
11778 ins_pipe( fpu_reg_mem );
11779 %}
11780
11781 // In 24-bit mode, force exponent rounding by storing back out
11782 instruct convI2F_SSF(stackSlotF dst, stackSlotI src) %{
11783 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
11784 match(Set dst (ConvI2F src));
11785 ins_cost(200);
11786 format %{ "FILD $src\n\t"
11787 "FSTP_S $dst" %}
11788 opcode(0xDB, 0x0); /* DB /0 */
11789 ins_encode( Push_Mem_I(src),
11790 Pop_Mem_F(dst));
11791 ins_pipe( fpu_mem_mem );
11792 %}
11793
11794 // In 24-bit mode, force exponent rounding by storing back out
11795 instruct convI2F_SSF_mem(stackSlotF dst, memory mem) %{
11796 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
11797 match(Set dst (ConvI2F (LoadI mem)));
11798 ins_cost(200);
11799 format %{ "FILD $mem\n\t"
11800 "FSTP_S $dst" %}
11801 opcode(0xDB); /* DB /0 */
11802 ins_encode( OpcP, RMopc_Mem(0x00,mem),
11803 Pop_Mem_F(dst));
11804 ins_pipe( fpu_mem_mem );
11805 %}
11806
11807 // This instruction does not round to 24-bits
11808 instruct convI2F_reg(regF dst, stackSlotI src) %{
11809 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
11810 match(Set dst (ConvI2F src));
11811 format %{ "FILD $src\n\t"
11812 "FSTP $dst" %}
11813 opcode(0xDB, 0x0); /* DB /0 */
11814 ins_encode( Push_Mem_I(src),
11815 Pop_Reg_F(dst));
11816 ins_pipe( fpu_reg_mem );
11817 %}
11818
11819 // This instruction does not round to 24-bits
11820 instruct convI2F_mem(regF dst, memory mem) %{
11821 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
11822 match(Set dst (ConvI2F (LoadI mem)));
11823 format %{ "FILD $mem\n\t"
11824 "FSTP $dst" %}
11825 opcode(0xDB); /* DB /0 */
11826 ins_encode( OpcP, RMopc_Mem(0x00,mem),
11827 Pop_Reg_F(dst));
11828 ins_pipe( fpu_reg_mem );
11829 %}
11830
11831 // Convert an int to a float in xmm; no rounding step needed.
11832 instruct convI2X_reg(regX dst, eRegI src) %{
11833 predicate( UseSSE==1 || UseSSE>=2 && !UseXmmI2F );
11834 match(Set dst (ConvI2F src));
11835 format %{ "CVTSI2SS $dst, $src" %}
11836
11837 opcode(0xF3, 0x0F, 0x2A); /* F3 0F 2A /r */
11838 ins_encode( OpcP, OpcS, Opcode(tertiary), RegReg(dst, src));
11839 ins_pipe( pipe_slow );
11840 %}
11841
11842 instruct convXI2X_reg(regX dst, eRegI src)
11843 %{
11844 predicate( UseSSE>=2 && UseXmmI2F );
11845 match(Set dst (ConvI2F src));
11846
11847 format %{ "MOVD $dst,$src\n\t"
11848 "CVTDQ2PS $dst,$dst\t# i2f" %}
11849 ins_encode %{
11850 __ movdl($dst$$XMMRegister, $src$$Register);
11851 __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister);
11852 %}
11853 ins_pipe(pipe_slow); // XXX
11854 %}
11855
11856 instruct convI2L_reg( eRegL dst, eRegI src, eFlagsReg cr) %{
11857 match(Set dst (ConvI2L src));
11858 effect(KILL cr);
11859 ins_cost(375);
11860 format %{ "MOV $dst.lo,$src\n\t"
11861 "MOV $dst.hi,$src\n\t"
11862 "SAR $dst.hi,31" %}
11863 ins_encode(convert_int_long(dst,src));
11864 ins_pipe( ialu_reg_reg_long );
11865 %}
11866
11867 // Zero-extend convert int to long
11868 instruct convI2L_reg_zex(eRegL dst, eRegI src, immL_32bits mask, eFlagsReg flags ) %{
11869 match(Set dst (AndL (ConvI2L src) mask) );
11870 effect( KILL flags );
11871 ins_cost(250);
11872 format %{ "MOV $dst.lo,$src\n\t"
11873 "XOR $dst.hi,$dst.hi" %}
11874 opcode(0x33); // XOR
11875 ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) );
11876 ins_pipe( ialu_reg_reg_long );
11877 %}
11878
11879 // Zero-extend long
11880 instruct zerox_long(eRegL dst, eRegL src, immL_32bits mask, eFlagsReg flags ) %{
11881 match(Set dst (AndL src mask) );
11882 effect( KILL flags );
11883 ins_cost(250);
11884 format %{ "MOV $dst.lo,$src.lo\n\t"
11885 "XOR $dst.hi,$dst.hi\n\t" %}
11886 opcode(0x33); // XOR
11887 ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) );
11888 ins_pipe( ialu_reg_reg_long );
11889 %}
11890
11891 instruct convL2D_reg( stackSlotD dst, eRegL src, eFlagsReg cr) %{
11892 predicate (UseSSE<=1);
11893 match(Set dst (ConvL2D src));
11894 effect( KILL cr );
11895 format %{ "PUSH $src.hi\t# Convert long to double\n\t"
11896 "PUSH $src.lo\n\t"
11897 "FILD ST,[ESP + #0]\n\t"
11898 "ADD ESP,8\n\t"
11899 "FSTP_D $dst\t# D-round" %}
11900 opcode(0xDF, 0x5); /* DF /5 */
11901 ins_encode(convert_long_double(src), Pop_Mem_D(dst));
11902 ins_pipe( pipe_slow );
11903 %}
11904
11905 instruct convL2XD_reg( regXD dst, eRegL src, eFlagsReg cr) %{
11906 predicate (UseSSE>=2);
11907 match(Set dst (ConvL2D src));
11908 effect( KILL cr );
11909 format %{ "PUSH $src.hi\t# Convert long to double\n\t"
11910 "PUSH $src.lo\n\t"
11911 "FILD_D [ESP]\n\t"
11912 "FSTP_D [ESP]\n\t"
11913 "MOVSD $dst,[ESP]\n\t"
11914 "ADD ESP,8" %}
11915 opcode(0xDF, 0x5); /* DF /5 */
11916 ins_encode(convert_long_double2(src), Push_ResultXD(dst));
11917 ins_pipe( pipe_slow );
11918 %}
11919
11920 instruct convL2X_reg( regX dst, eRegL src, eFlagsReg cr) %{
11921 predicate (UseSSE>=1);
11922 match(Set dst (ConvL2F src));
11923 effect( KILL cr );
11924 format %{ "PUSH $src.hi\t# Convert long to single float\n\t"
11925 "PUSH $src.lo\n\t"
11926 "FILD_D [ESP]\n\t"
11927 "FSTP_S [ESP]\n\t"
11928 "MOVSS $dst,[ESP]\n\t"
11929 "ADD ESP,8" %}
11930 opcode(0xDF, 0x5); /* DF /5 */
11931 ins_encode(convert_long_double2(src), Push_ResultX(dst,0x8));
11932 ins_pipe( pipe_slow );
11933 %}
11934
11935 instruct convL2F_reg( stackSlotF dst, eRegL src, eFlagsReg cr) %{
11936 match(Set dst (ConvL2F src));
11937 effect( KILL cr );
11938 format %{ "PUSH $src.hi\t# Convert long to single float\n\t"
11939 "PUSH $src.lo\n\t"
11940 "FILD ST,[ESP + #0]\n\t"
11941 "ADD ESP,8\n\t"
11942 "FSTP_S $dst\t# F-round" %}
11943 opcode(0xDF, 0x5); /* DF /5 */
11944 ins_encode(convert_long_double(src), Pop_Mem_F(dst));
11945 ins_pipe( pipe_slow );
11946 %}
11947
11948 instruct convL2I_reg( eRegI dst, eRegL src ) %{
11949 match(Set dst (ConvL2I src));
11950 effect( DEF dst, USE src );
11951 format %{ "MOV $dst,$src.lo" %}
11952 ins_encode(enc_CopyL_Lo(dst,src));
11953 ins_pipe( ialu_reg_reg );
11954 %}
11955
11956
11957 instruct MoveF2I_stack_reg(eRegI dst, stackSlotF src) %{
11958 match(Set dst (MoveF2I src));
11959 effect( DEF dst, USE src );
11960 ins_cost(100);
11961 format %{ "MOV $dst,$src\t# MoveF2I_stack_reg" %}
11962 opcode(0x8B);
11963 ins_encode( OpcP, RegMem(dst,src));
11964 ins_pipe( ialu_reg_mem );
11965 %}
11966
11967 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{
11968 predicate(UseSSE==0);
11969 match(Set dst (MoveF2I src));
11970 effect( DEF dst, USE src );
11971
11972 ins_cost(125);
11973 format %{ "FST_S $dst,$src\t# MoveF2I_reg_stack" %}
11974 ins_encode( Pop_Mem_Reg_F(dst, src) );
11975 ins_pipe( fpu_mem_reg );
11976 %}
11977
11978 instruct MoveF2I_reg_stack_sse(stackSlotI dst, regX src) %{
11979 predicate(UseSSE>=1);
11980 match(Set dst (MoveF2I src));
11981 effect( DEF dst, USE src );
11982
11983 ins_cost(95);
11984 format %{ "MOVSS $dst,$src\t# MoveF2I_reg_stack_sse" %}
11985 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x11), RegMem(src, dst));
11986 ins_pipe( pipe_slow );
11987 %}
11988
11989 instruct MoveF2I_reg_reg_sse(eRegI dst, regX src) %{
11990 predicate(UseSSE>=2);
11991 match(Set dst (MoveF2I src));
11992 effect( DEF dst, USE src );
11993 ins_cost(85);
11994 format %{ "MOVD $dst,$src\t# MoveF2I_reg_reg_sse" %}
11995 ins_encode( MovX2I_reg(dst, src));
11996 ins_pipe( pipe_slow );
11997 %}
11998
11999 instruct MoveI2F_reg_stack(stackSlotF dst, eRegI src) %{
12000 match(Set dst (MoveI2F src));
12001 effect( DEF dst, USE src );
12002
12003 ins_cost(100);
12004 format %{ "MOV $dst,$src\t# MoveI2F_reg_stack" %}
12005 opcode(0x89);
12006 ins_encode( OpcPRegSS( dst, src ) );
12007 ins_pipe( ialu_mem_reg );
12008 %}
12009
12010
12011 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
12012 predicate(UseSSE==0);
12013 match(Set dst (MoveI2F src));
12014 effect(DEF dst, USE src);
12015
12016 ins_cost(125);
12017 format %{ "FLD_S $src\n\t"
12018 "FSTP $dst\t# MoveI2F_stack_reg" %}
12019 opcode(0xD9); /* D9 /0, FLD m32real */
12020 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
12021 Pop_Reg_F(dst) );
12022 ins_pipe( fpu_reg_mem );
12023 %}
12024
12025 instruct MoveI2F_stack_reg_sse(regX dst, stackSlotI src) %{
12026 predicate(UseSSE>=1);
12027 match(Set dst (MoveI2F src));
12028 effect( DEF dst, USE src );
12029
12030 ins_cost(95);
12031 format %{ "MOVSS $dst,$src\t# MoveI2F_stack_reg_sse" %}
12032 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x10), RegMem(dst,src));
12033 ins_pipe( pipe_slow );
12034 %}
12035
12036 instruct MoveI2F_reg_reg_sse(regX dst, eRegI src) %{
12037 predicate(UseSSE>=2);
12038 match(Set dst (MoveI2F src));
12039 effect( DEF dst, USE src );
12040
12041 ins_cost(85);
12042 format %{ "MOVD $dst,$src\t# MoveI2F_reg_reg_sse" %}
12043 ins_encode( MovI2X_reg(dst, src) );
12044 ins_pipe( pipe_slow );
12045 %}
12046
12047 instruct MoveD2L_stack_reg(eRegL dst, stackSlotD src) %{
12048 match(Set dst (MoveD2L src));
12049 effect(DEF dst, USE src);
12050
12051 ins_cost(250);
12052 format %{ "MOV $dst.lo,$src\n\t"
12053 "MOV $dst.hi,$src+4\t# MoveD2L_stack_reg" %}
12054 opcode(0x8B, 0x8B);
12055 ins_encode( OpcP, RegMem(dst,src), OpcS, RegMem_Hi(dst,src));
12056 ins_pipe( ialu_mem_long_reg );
12057 %}
12058
12059 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
12060 predicate(UseSSE<=1);
12061 match(Set dst (MoveD2L src));
12062 effect(DEF dst, USE src);
12063
12064 ins_cost(125);
12065 format %{ "FST_D $dst,$src\t# MoveD2L_reg_stack" %}
12066 ins_encode( Pop_Mem_Reg_D(dst, src) );
12067 ins_pipe( fpu_mem_reg );
12068 %}
12069
12070 instruct MoveD2L_reg_stack_sse(stackSlotL dst, regXD src) %{
12071 predicate(UseSSE>=2);
12072 match(Set dst (MoveD2L src));
12073 effect(DEF dst, USE src);
12074 ins_cost(95);
12075
12076 format %{ "MOVSD $dst,$src\t# MoveD2L_reg_stack_sse" %}
12077 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x11), RegMem(src,dst));
12078 ins_pipe( pipe_slow );
12079 %}
12080
12081 instruct MoveD2L_reg_reg_sse(eRegL dst, regXD src, regXD tmp) %{
12082 predicate(UseSSE>=2);
12083 match(Set dst (MoveD2L src));
12084 effect(DEF dst, USE src, TEMP tmp);
12085 ins_cost(85);
12086 format %{ "MOVD $dst.lo,$src\n\t"
12087 "PSHUFLW $tmp,$src,0x4E\n\t"
12088 "MOVD $dst.hi,$tmp\t# MoveD2L_reg_reg_sse" %}
12089 ins_encode( MovXD2L_reg(dst, src, tmp) );
12090 ins_pipe( pipe_slow );
12091 %}
12092
12093 instruct MoveL2D_reg_stack(stackSlotD dst, eRegL src) %{
12094 match(Set dst (MoveL2D src));
12095 effect(DEF dst, USE src);
12096
12097 ins_cost(200);
12098 format %{ "MOV $dst,$src.lo\n\t"
12099 "MOV $dst+4,$src.hi\t# MoveL2D_reg_stack" %}
12100 opcode(0x89, 0x89);
12101 ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) );
12102 ins_pipe( ialu_mem_long_reg );
12103 %}
12104
12105
12106 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
12107 predicate(UseSSE<=1);
12108 match(Set dst (MoveL2D src));
12109 effect(DEF dst, USE src);
12110 ins_cost(125);
12111
12112 format %{ "FLD_D $src\n\t"
12113 "FSTP $dst\t# MoveL2D_stack_reg" %}
12114 opcode(0xDD); /* DD /0, FLD m64real */
12115 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
12116 Pop_Reg_D(dst) );
12117 ins_pipe( fpu_reg_mem );
12118 %}
12119
12120
12121 instruct MoveL2D_stack_reg_sse(regXD dst, stackSlotL src) %{
12122 predicate(UseSSE>=2 && UseXmmLoadAndClearUpper);
12123 match(Set dst (MoveL2D src));
12124 effect(DEF dst, USE src);
12125
12126 ins_cost(95);
12127 format %{ "MOVSD $dst,$src\t# MoveL2D_stack_reg_sse" %}
12128 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x10), RegMem(dst,src));
12129 ins_pipe( pipe_slow );
12130 %}
12131
12132 instruct MoveL2D_stack_reg_sse_partial(regXD dst, stackSlotL src) %{
12133 predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper);
12134 match(Set dst (MoveL2D src));
12135 effect(DEF dst, USE src);
12136
12137 ins_cost(95);
12138 format %{ "MOVLPD $dst,$src\t# MoveL2D_stack_reg_sse" %}
12139 ins_encode( Opcode(0x66), Opcode(0x0F), Opcode(0x12), RegMem(dst,src));
12140 ins_pipe( pipe_slow );
12141 %}
12142
12143 instruct MoveL2D_reg_reg_sse(regXD dst, eRegL src, regXD tmp) %{
12144 predicate(UseSSE>=2);
12145 match(Set dst (MoveL2D src));
12146 effect(TEMP dst, USE src, TEMP tmp);
12147 ins_cost(85);
12148 format %{ "MOVD $dst,$src.lo\n\t"
12149 "MOVD $tmp,$src.hi\n\t"
12150 "PUNPCKLDQ $dst,$tmp\t# MoveL2D_reg_reg_sse" %}
12151 ins_encode( MovL2XD_reg(dst, src, tmp) );
12152 ins_pipe( pipe_slow );
12153 %}
12154
12155 // Replicate scalar to packed byte (1 byte) values in xmm
12156 instruct Repl8B_reg(regXD dst, regXD src) %{
12157 predicate(UseSSE>=2);
12158 match(Set dst (Replicate8B src));
12159 format %{ "MOVDQA $dst,$src\n\t"
12160 "PUNPCKLBW $dst,$dst\n\t"
12161 "PSHUFLW $dst,$dst,0x00\t! replicate8B" %}
12162 ins_encode( pshufd_8x8(dst, src));
12163 ins_pipe( pipe_slow );
12164 %}
12165
12166 // Replicate scalar to packed byte (1 byte) values in xmm
12167 instruct Repl8B_eRegI(regXD dst, eRegI src) %{
12168 predicate(UseSSE>=2);
12169 match(Set dst (Replicate8B src));
12170 format %{ "MOVD $dst,$src\n\t"
12171 "PUNPCKLBW $dst,$dst\n\t"
12172 "PSHUFLW $dst,$dst,0x00\t! replicate8B" %}
12173 ins_encode( mov_i2x(dst, src), pshufd_8x8(dst, dst));
12174 ins_pipe( pipe_slow );
12175 %}
12176
12177 // Replicate scalar zero to packed byte (1 byte) values in xmm
12178 instruct Repl8B_immI0(regXD dst, immI0 zero) %{
12179 predicate(UseSSE>=2);
12180 match(Set dst (Replicate8B zero));
12181 format %{ "PXOR $dst,$dst\t! replicate8B" %}
12182 ins_encode( pxor(dst, dst));
12183 ins_pipe( fpu_reg_reg );
12184 %}
12185
12186 // Replicate scalar to packed shore (2 byte) values in xmm
12187 instruct Repl4S_reg(regXD dst, regXD src) %{
12188 predicate(UseSSE>=2);
12189 match(Set dst (Replicate4S src));
12190 format %{ "PSHUFLW $dst,$src,0x00\t! replicate4S" %}
12191 ins_encode( pshufd_4x16(dst, src));
12192 ins_pipe( fpu_reg_reg );
12193 %}
12194
12195 // Replicate scalar to packed shore (2 byte) values in xmm
12196 instruct Repl4S_eRegI(regXD dst, eRegI src) %{
12197 predicate(UseSSE>=2);
12198 match(Set dst (Replicate4S src));
12199 format %{ "MOVD $dst,$src\n\t"
12200 "PSHUFLW $dst,$dst,0x00\t! replicate4S" %}
12201 ins_encode( mov_i2x(dst, src), pshufd_4x16(dst, dst));
12202 ins_pipe( fpu_reg_reg );
12203 %}
12204
12205 // Replicate scalar zero to packed short (2 byte) values in xmm
12206 instruct Repl4S_immI0(regXD dst, immI0 zero) %{
12207 predicate(UseSSE>=2);
12208 match(Set dst (Replicate4S zero));
12209 format %{ "PXOR $dst,$dst\t! replicate4S" %}
12210 ins_encode( pxor(dst, dst));
12211 ins_pipe( fpu_reg_reg );
12212 %}
12213
12214 // Replicate scalar to packed char (2 byte) values in xmm
12215 instruct Repl4C_reg(regXD dst, regXD src) %{
12216 predicate(UseSSE>=2);
12217 match(Set dst (Replicate4C src));
12218 format %{ "PSHUFLW $dst,$src,0x00\t! replicate4C" %}
12219 ins_encode( pshufd_4x16(dst, src));
12220 ins_pipe( fpu_reg_reg );
12221 %}
12222
12223 // Replicate scalar to packed char (2 byte) values in xmm
12224 instruct Repl4C_eRegI(regXD dst, eRegI src) %{
12225 predicate(UseSSE>=2);
12226 match(Set dst (Replicate4C src));
12227 format %{ "MOVD $dst,$src\n\t"
12228 "PSHUFLW $dst,$dst,0x00\t! replicate4C" %}
12229 ins_encode( mov_i2x(dst, src), pshufd_4x16(dst, dst));
12230 ins_pipe( fpu_reg_reg );
12231 %}
12232
12233 // Replicate scalar zero to packed char (2 byte) values in xmm
12234 instruct Repl4C_immI0(regXD dst, immI0 zero) %{
12235 predicate(UseSSE>=2);
12236 match(Set dst (Replicate4C zero));
12237 format %{ "PXOR $dst,$dst\t! replicate4C" %}
12238 ins_encode( pxor(dst, dst));
12239 ins_pipe( fpu_reg_reg );
12240 %}
12241
12242 // Replicate scalar to packed integer (4 byte) values in xmm
12243 instruct Repl2I_reg(regXD dst, regXD src) %{
12244 predicate(UseSSE>=2);
12245 match(Set dst (Replicate2I src));
12246 format %{ "PSHUFD $dst,$src,0x00\t! replicate2I" %}
12247 ins_encode( pshufd(dst, src, 0x00));
12248 ins_pipe( fpu_reg_reg );
12249 %}
12250
12251 // Replicate scalar to packed integer (4 byte) values in xmm
12252 instruct Repl2I_eRegI(regXD dst, eRegI src) %{
12253 predicate(UseSSE>=2);
12254 match(Set dst (Replicate2I src));
12255 format %{ "MOVD $dst,$src\n\t"
12256 "PSHUFD $dst,$dst,0x00\t! replicate2I" %}
12257 ins_encode( mov_i2x(dst, src), pshufd(dst, dst, 0x00));
12258 ins_pipe( fpu_reg_reg );
12259 %}
12260
12261 // Replicate scalar zero to packed integer (2 byte) values in xmm
12262 instruct Repl2I_immI0(regXD dst, immI0 zero) %{
12263 predicate(UseSSE>=2);
12264 match(Set dst (Replicate2I zero));
12265 format %{ "PXOR $dst,$dst\t! replicate2I" %}
12266 ins_encode( pxor(dst, dst));
12267 ins_pipe( fpu_reg_reg );
12268 %}
12269
12270 // Replicate scalar to packed single precision floating point values in xmm
12271 instruct Repl2F_reg(regXD dst, regXD src) %{
12272 predicate(UseSSE>=2);
12273 match(Set dst (Replicate2F src));
12274 format %{ "PSHUFD $dst,$src,0xe0\t! replicate2F" %}
12275 ins_encode( pshufd(dst, src, 0xe0));
12276 ins_pipe( fpu_reg_reg );
12277 %}
12278
12279 // Replicate scalar to packed single precision floating point values in xmm
12280 instruct Repl2F_regX(regXD dst, regX src) %{
12281 predicate(UseSSE>=2);
12282 match(Set dst (Replicate2F src));
12283 format %{ "PSHUFD $dst,$src,0xe0\t! replicate2F" %}
12284 ins_encode( pshufd(dst, src, 0xe0));
12285 ins_pipe( fpu_reg_reg );
12286 %}
12287
12288 // Replicate scalar to packed single precision floating point values in xmm
12289 instruct Repl2F_immXF0(regXD dst, immXF0 zero) %{
12290 predicate(UseSSE>=2);
12291 match(Set dst (Replicate2F zero));
12292 format %{ "PXOR $dst,$dst\t! replicate2F" %}
12293 ins_encode( pxor(dst, dst));
12294 ins_pipe( fpu_reg_reg );
12295 %}
12296
12297 // =======================================================================
12298 // fast clearing of an array
12299 instruct rep_stos(eCXRegI cnt, eDIRegP base, eAXRegI zero, Universe dummy, eFlagsReg cr) %{
12300 match(Set dummy (ClearArray cnt base));
12301 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr);
12302 format %{ "SHL ECX,1\t# Convert doublewords to words\n\t"
12303 "XOR EAX,EAX\n\t"
12304 "REP STOS\t# store EAX into [EDI++] while ECX--" %}
12305 opcode(0,0x4);
12306 ins_encode( Opcode(0xD1), RegOpc(ECX),
12307 OpcRegReg(0x33,EAX,EAX),
12308 Opcode(0xF3), Opcode(0xAB) );
12309 ins_pipe( pipe_slow );
12310 %}
12311
12312 instruct string_compare(eDIRegP str1, eCXRegI cnt1, eSIRegP str2, eBXRegI cnt2,
12313 eAXRegI result, regXD tmp1, regXD tmp2, eFlagsReg cr) %{
12314 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
12315 effect(TEMP tmp1, TEMP tmp2, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
12316
12317 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1, $tmp2" %}
12318 ins_encode %{
12319 __ string_compare($str1$$Register, $str2$$Register,
12320 $cnt1$$Register, $cnt2$$Register, $result$$Register,
12321 $tmp1$$XMMRegister, $tmp2$$XMMRegister);
12322 %}
12323 ins_pipe( pipe_slow );
12324 %}
12325
12326 // fast string equals
12327 instruct string_equals(eDIRegP str1, eSIRegP str2, eCXRegI cnt, eAXRegI result,
12328 regXD tmp1, regXD tmp2, eBXRegI tmp3, eFlagsReg cr) %{
12329 match(Set result (StrEquals (Binary str1 str2) cnt));
12330 effect(TEMP tmp1, TEMP tmp2, USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp3, KILL cr);
12331
12332 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp1, $tmp2, $tmp3" %}
12333 ins_encode %{
12334 __ char_arrays_equals(false, $str1$$Register, $str2$$Register,
12335 $cnt$$Register, $result$$Register, $tmp3$$Register,
12336 $tmp1$$XMMRegister, $tmp2$$XMMRegister);
12337 %}
12338 ins_pipe( pipe_slow );
12339 %}
12340
12341 instruct string_indexof(eDIRegP str1, eDXRegI cnt1, eSIRegP str2, eAXRegI cnt2,
12342 eBXRegI result, regXD tmp1, eCXRegI tmp2, eFlagsReg cr) %{
12343 predicate(UseSSE42Intrinsics);
12344 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
12345 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp2, KILL cr);
12346
12347 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp2, $tmp1" %}
12348 ins_encode %{
12349 __ string_indexof($str1$$Register, $str2$$Register,
12350 $cnt1$$Register, $cnt2$$Register, $result$$Register,
12351 $tmp1$$XMMRegister, $tmp2$$Register);
12352 %}
12353 ins_pipe( pipe_slow );
12354 %}
12355
12356 // fast array equals
12357 instruct array_equals(eDIRegP ary1, eSIRegP ary2, eAXRegI result,
12358 regXD tmp1, regXD tmp2, eCXRegI tmp3, eBXRegI tmp4, eFlagsReg cr)
12359 %{
12360 match(Set result (AryEq ary1 ary2));
12361 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
12362 //ins_cost(300);
12363
12364 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
12365 ins_encode %{
12366 __ char_arrays_equals(true, $ary1$$Register, $ary2$$Register,
12367 $tmp3$$Register, $result$$Register, $tmp4$$Register,
12368 $tmp1$$XMMRegister, $tmp2$$XMMRegister);
12369 %}
12370 ins_pipe( pipe_slow );
12371 %}
12372
12373 //----------Control Flow Instructions------------------------------------------
12374 // Signed compare Instructions
12375 instruct compI_eReg(eFlagsReg cr, eRegI op1, eRegI op2) %{
12376 match(Set cr (CmpI op1 op2));
12377 effect( DEF cr, USE op1, USE op2 );
12378 format %{ "CMP $op1,$op2" %}
12379 opcode(0x3B); /* Opcode 3B /r */
12380 ins_encode( OpcP, RegReg( op1, op2) );
12381 ins_pipe( ialu_cr_reg_reg );
12382 %}
12383
12384 instruct compI_eReg_imm(eFlagsReg cr, eRegI op1, immI op2) %{
12385 match(Set cr (CmpI op1 op2));
12386 effect( DEF cr, USE op1 );
12387 format %{ "CMP $op1,$op2" %}
12388 opcode(0x81,0x07); /* Opcode 81 /7 */
12389 // ins_encode( RegImm( op1, op2) ); /* Was CmpImm */
12390 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
12391 ins_pipe( ialu_cr_reg_imm );
12392 %}
12393
12394 // Cisc-spilled version of cmpI_eReg
12395 instruct compI_eReg_mem(eFlagsReg cr, eRegI op1, memory op2) %{
12396 match(Set cr (CmpI op1 (LoadI op2)));
12397
12398 format %{ "CMP $op1,$op2" %}
12399 ins_cost(500);
12400 opcode(0x3B); /* Opcode 3B /r */
12401 ins_encode( OpcP, RegMem( op1, op2) );
12402 ins_pipe( ialu_cr_reg_mem );
12403 %}
12404
12405 instruct testI_reg( eFlagsReg cr, eRegI src, immI0 zero ) %{
12406 match(Set cr (CmpI src zero));
12407 effect( DEF cr, USE src );
12408
12409 format %{ "TEST $src,$src" %}
12410 opcode(0x85);
12411 ins_encode( OpcP, RegReg( src, src ) );
12412 ins_pipe( ialu_cr_reg_imm );
12413 %}
12414
12415 instruct testI_reg_imm( eFlagsReg cr, eRegI src, immI con, immI0 zero ) %{
12416 match(Set cr (CmpI (AndI src con) zero));
12417
12418 format %{ "TEST $src,$con" %}
12419 opcode(0xF7,0x00);
12420 ins_encode( OpcP, RegOpc(src), Con32(con) );
12421 ins_pipe( ialu_cr_reg_imm );
12422 %}
12423
12424 instruct testI_reg_mem( eFlagsReg cr, eRegI src, memory mem, immI0 zero ) %{
12425 match(Set cr (CmpI (AndI src mem) zero));
12426
12427 format %{ "TEST $src,$mem" %}
12428 opcode(0x85);
12429 ins_encode( OpcP, RegMem( src, mem ) );
12430 ins_pipe( ialu_cr_reg_mem );
12431 %}
12432
12433 // Unsigned compare Instructions; really, same as signed except they
12434 // produce an eFlagsRegU instead of eFlagsReg.
12435 instruct compU_eReg(eFlagsRegU cr, eRegI op1, eRegI op2) %{
12436 match(Set cr (CmpU op1 op2));
12437
12438 format %{ "CMPu $op1,$op2" %}
12439 opcode(0x3B); /* Opcode 3B /r */
12440 ins_encode( OpcP, RegReg( op1, op2) );
12441 ins_pipe( ialu_cr_reg_reg );
12442 %}
12443
12444 instruct compU_eReg_imm(eFlagsRegU cr, eRegI op1, immI op2) %{
12445 match(Set cr (CmpU op1 op2));
12446
12447 format %{ "CMPu $op1,$op2" %}
12448 opcode(0x81,0x07); /* Opcode 81 /7 */
12449 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
12450 ins_pipe( ialu_cr_reg_imm );
12451 %}
12452
12453 // // Cisc-spilled version of cmpU_eReg
12454 instruct compU_eReg_mem(eFlagsRegU cr, eRegI op1, memory op2) %{
12455 match(Set cr (CmpU op1 (LoadI op2)));
12456
12457 format %{ "CMPu $op1,$op2" %}
12458 ins_cost(500);
12459 opcode(0x3B); /* Opcode 3B /r */
12460 ins_encode( OpcP, RegMem( op1, op2) );
12461 ins_pipe( ialu_cr_reg_mem );
12462 %}
12463
12464 // // Cisc-spilled version of cmpU_eReg
12465 //instruct compU_mem_eReg(eFlagsRegU cr, memory op1, eRegI op2) %{
12466 // match(Set cr (CmpU (LoadI op1) op2));
12467 //
12468 // format %{ "CMPu $op1,$op2" %}
12469 // ins_cost(500);
12470 // opcode(0x39); /* Opcode 39 /r */
12471 // ins_encode( OpcP, RegMem( op1, op2) );
12472 //%}
12473
12474 instruct testU_reg( eFlagsRegU cr, eRegI src, immI0 zero ) %{
12475 match(Set cr (CmpU src zero));
12476
12477 format %{ "TESTu $src,$src" %}
12478 opcode(0x85);
12479 ins_encode( OpcP, RegReg( src, src ) );
12480 ins_pipe( ialu_cr_reg_imm );
12481 %}
12482
12483 // Unsigned pointer compare Instructions
12484 instruct compP_eReg(eFlagsRegU cr, eRegP op1, eRegP op2) %{
12485 match(Set cr (CmpP op1 op2));
12486
12487 format %{ "CMPu $op1,$op2" %}
12488 opcode(0x3B); /* Opcode 3B /r */
12489 ins_encode( OpcP, RegReg( op1, op2) );
12490 ins_pipe( ialu_cr_reg_reg );
12491 %}
12492
12493 instruct compP_eReg_imm(eFlagsRegU cr, eRegP op1, immP op2) %{
12494 match(Set cr (CmpP op1 op2));
12495
12496 format %{ "CMPu $op1,$op2" %}
12497 opcode(0x81,0x07); /* Opcode 81 /7 */
12498 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
12499 ins_pipe( ialu_cr_reg_imm );
12500 %}
12501
12502 // // Cisc-spilled version of cmpP_eReg
12503 instruct compP_eReg_mem(eFlagsRegU cr, eRegP op1, memory op2) %{
12504 match(Set cr (CmpP op1 (LoadP op2)));
12505
12506 format %{ "CMPu $op1,$op2" %}
12507 ins_cost(500);
12508 opcode(0x3B); /* Opcode 3B /r */
12509 ins_encode( OpcP, RegMem( op1, op2) );
12510 ins_pipe( ialu_cr_reg_mem );
12511 %}
12512
12513 // // Cisc-spilled version of cmpP_eReg
12514 //instruct compP_mem_eReg(eFlagsRegU cr, memory op1, eRegP op2) %{
12515 // match(Set cr (CmpP (LoadP op1) op2));
12516 //
12517 // format %{ "CMPu $op1,$op2" %}
12518 // ins_cost(500);
12519 // opcode(0x39); /* Opcode 39 /r */
12520 // ins_encode( OpcP, RegMem( op1, op2) );
12521 //%}
12522
12523 // Compare raw pointer (used in out-of-heap check).
12524 // Only works because non-oop pointers must be raw pointers
12525 // and raw pointers have no anti-dependencies.
12526 instruct compP_mem_eReg( eFlagsRegU cr, eRegP op1, memory op2 ) %{
12527 predicate( !n->in(2)->in(2)->bottom_type()->isa_oop_ptr() );
12528 match(Set cr (CmpP op1 (LoadP op2)));
12529
12530 format %{ "CMPu $op1,$op2" %}
12531 opcode(0x3B); /* Opcode 3B /r */
12532 ins_encode( OpcP, RegMem( op1, op2) );
12533 ins_pipe( ialu_cr_reg_mem );
12534 %}
12535
12536 //
12537 // This will generate a signed flags result. This should be ok
12538 // since any compare to a zero should be eq/neq.
12539 instruct testP_reg( eFlagsReg cr, eRegP src, immP0 zero ) %{
12540 match(Set cr (CmpP src zero));
12541
12542 format %{ "TEST $src,$src" %}
12543 opcode(0x85);
12544 ins_encode( OpcP, RegReg( src, src ) );
12545 ins_pipe( ialu_cr_reg_imm );
12546 %}
12547
12548 // Cisc-spilled version of testP_reg
12549 // This will generate a signed flags result. This should be ok
12550 // since any compare to a zero should be eq/neq.
12551 instruct testP_Reg_mem( eFlagsReg cr, memory op, immI0 zero ) %{
12552 match(Set cr (CmpP (LoadP op) zero));
12553
12554 format %{ "TEST $op,0xFFFFFFFF" %}
12555 ins_cost(500);
12556 opcode(0xF7); /* Opcode F7 /0 */
12557 ins_encode( OpcP, RMopc_Mem(0x00,op), Con_d32(0xFFFFFFFF) );
12558 ins_pipe( ialu_cr_reg_imm );
12559 %}
12560
12561 // Yanked all unsigned pointer compare operations.
12562 // Pointer compares are done with CmpP which is already unsigned.
12563
12564 //----------Max and Min--------------------------------------------------------
12565 // Min Instructions
12566 ////
12567 // *** Min and Max using the conditional move are slower than the
12568 // *** branch version on a Pentium III.
12569 // // Conditional move for min
12570 //instruct cmovI_reg_lt( eRegI op2, eRegI op1, eFlagsReg cr ) %{
12571 // effect( USE_DEF op2, USE op1, USE cr );
12572 // format %{ "CMOVlt $op2,$op1\t! min" %}
12573 // opcode(0x4C,0x0F);
12574 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) );
12575 // ins_pipe( pipe_cmov_reg );
12576 //%}
12577 //
12578 //// Min Register with Register (P6 version)
12579 //instruct minI_eReg_p6( eRegI op1, eRegI op2 ) %{
12580 // predicate(VM_Version::supports_cmov() );
12581 // match(Set op2 (MinI op1 op2));
12582 // ins_cost(200);
12583 // expand %{
12584 // eFlagsReg cr;
12585 // compI_eReg(cr,op1,op2);
12586 // cmovI_reg_lt(op2,op1,cr);
12587 // %}
12588 //%}
12589
12590 // Min Register with Register (generic version)
12591 instruct minI_eReg(eRegI dst, eRegI src, eFlagsReg flags) %{
12592 match(Set dst (MinI dst src));
12593 effect(KILL flags);
12594 ins_cost(300);
12595
12596 format %{ "MIN $dst,$src" %}
12597 opcode(0xCC);
12598 ins_encode( min_enc(dst,src) );
12599 ins_pipe( pipe_slow );
12600 %}
12601
12602 // Max Register with Register
12603 // *** Min and Max using the conditional move are slower than the
12604 // *** branch version on a Pentium III.
12605 // // Conditional move for max
12606 //instruct cmovI_reg_gt( eRegI op2, eRegI op1, eFlagsReg cr ) %{
12607 // effect( USE_DEF op2, USE op1, USE cr );
12608 // format %{ "CMOVgt $op2,$op1\t! max" %}
12609 // opcode(0x4F,0x0F);
12610 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) );
12611 // ins_pipe( pipe_cmov_reg );
12612 //%}
12613 //
12614 // // Max Register with Register (P6 version)
12615 //instruct maxI_eReg_p6( eRegI op1, eRegI op2 ) %{
12616 // predicate(VM_Version::supports_cmov() );
12617 // match(Set op2 (MaxI op1 op2));
12618 // ins_cost(200);
12619 // expand %{
12620 // eFlagsReg cr;
12621 // compI_eReg(cr,op1,op2);
12622 // cmovI_reg_gt(op2,op1,cr);
12623 // %}
12624 //%}
12625
12626 // Max Register with Register (generic version)
12627 instruct maxI_eReg(eRegI dst, eRegI src, eFlagsReg flags) %{
12628 match(Set dst (MaxI dst src));
12629 effect(KILL flags);
12630 ins_cost(300);
12631
12632 format %{ "MAX $dst,$src" %}
12633 opcode(0xCC);
12634 ins_encode( max_enc(dst,src) );
12635 ins_pipe( pipe_slow );
12636 %}
12637
12638 // ============================================================================
12639 // Branch Instructions
12640 // Jump Table
12641 instruct jumpXtnd(eRegI switch_val) %{
12642 match(Jump switch_val);
12643 ins_cost(350);
12644
12645 format %{ "JMP [table_base](,$switch_val,1)\n\t" %}
12646
12647 ins_encode %{
12648 address table_base = __ address_table_constant(_index2label);
12649
12650 // Jump to Address(table_base + switch_reg)
12651 InternalAddress table(table_base);
12652 Address index(noreg, $switch_val$$Register, Address::times_1);
12653 __ jump(ArrayAddress(table, index));
12654 %}
12655 ins_pc_relative(1);
12656 ins_pipe(pipe_jmp);
12657 %}
12658
12659 // Jump Direct - Label defines a relative address from JMP+1
12660 instruct jmpDir(label labl) %{
12661 match(Goto);
12662 effect(USE labl);
12663
12664 ins_cost(300);
12665 format %{ "JMP $labl" %}
12666 size(5);
12667 opcode(0xE9);
12668 ins_encode( OpcP, Lbl( labl ) );
12669 ins_pipe( pipe_jmp );
12670 ins_pc_relative(1);
12671 %}
12672
12673 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12674 instruct jmpCon(cmpOp cop, eFlagsReg cr, label labl) %{
12675 match(If cop cr);
12676 effect(USE labl);
12677
12678 ins_cost(300);
12679 format %{ "J$cop $labl" %}
12680 size(6);
12681 opcode(0x0F, 0x80);
12682 ins_encode( Jcc( cop, labl) );
12683 ins_pipe( pipe_jcc );
12684 ins_pc_relative(1);
12685 %}
12686
12687 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12688 instruct jmpLoopEnd(cmpOp cop, eFlagsReg cr, label labl) %{
12689 match(CountedLoopEnd cop cr);
12690 effect(USE labl);
12691
12692 ins_cost(300);
12693 format %{ "J$cop $labl\t# Loop end" %}
12694 size(6);
12695 opcode(0x0F, 0x80);
12696 ins_encode( Jcc( cop, labl) );
12697 ins_pipe( pipe_jcc );
12698 ins_pc_relative(1);
12699 %}
12700
12701 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12702 instruct jmpLoopEndU(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12703 match(CountedLoopEnd cop cmp);
12704 effect(USE labl);
12705
12706 ins_cost(300);
12707 format %{ "J$cop,u $labl\t# Loop end" %}
12708 size(6);
12709 opcode(0x0F, 0x80);
12710 ins_encode( Jcc( cop, labl) );
12711 ins_pipe( pipe_jcc );
12712 ins_pc_relative(1);
12713 %}
12714
12715 instruct jmpLoopEndUCF(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12716 match(CountedLoopEnd cop cmp);
12717 effect(USE labl);
12718
12719 ins_cost(200);
12720 format %{ "J$cop,u $labl\t# Loop end" %}
12721 size(6);
12722 opcode(0x0F, 0x80);
12723 ins_encode( Jcc( cop, labl) );
12724 ins_pipe( pipe_jcc );
12725 ins_pc_relative(1);
12726 %}
12727
12728 // Jump Direct Conditional - using unsigned comparison
12729 instruct jmpConU(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12730 match(If cop cmp);
12731 effect(USE labl);
12732
12733 ins_cost(300);
12734 format %{ "J$cop,u $labl" %}
12735 size(6);
12736 opcode(0x0F, 0x80);
12737 ins_encode(Jcc(cop, labl));
12738 ins_pipe(pipe_jcc);
12739 ins_pc_relative(1);
12740 %}
12741
12742 instruct jmpConUCF(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12743 match(If cop cmp);
12744 effect(USE labl);
12745
12746 ins_cost(200);
12747 format %{ "J$cop,u $labl" %}
12748 size(6);
12749 opcode(0x0F, 0x80);
12750 ins_encode(Jcc(cop, labl));
12751 ins_pipe(pipe_jcc);
12752 ins_pc_relative(1);
12753 %}
12754
12755 instruct jmpConUCF2(cmpOpUCF2 cop, eFlagsRegUCF cmp, label labl) %{
12756 match(If cop cmp);
12757 effect(USE labl);
12758
12759 ins_cost(200);
12760 format %{ $$template
12761 if ($cop$$cmpcode == Assembler::notEqual) {
12762 $$emit$$"JP,u $labl\n\t"
12763 $$emit$$"J$cop,u $labl"
12764 } else {
12765 $$emit$$"JP,u done\n\t"
12766 $$emit$$"J$cop,u $labl\n\t"
12767 $$emit$$"done:"
12768 }
12769 %}
12770 size(12);
12771 opcode(0x0F, 0x80);
12772 ins_encode %{
12773 Label* l = $labl$$label;
12774 $$$emit8$primary;
12775 emit_cc(cbuf, $secondary, Assembler::parity);
12776 int parity_disp = -1;
12777 bool ok = false;
12778 if ($cop$$cmpcode == Assembler::notEqual) {
12779 // the two jumps 6 bytes apart so the jump distances are too
12780 parity_disp = l ? (l->loc_pos() - (cbuf.code_size() + 4)) : 0;
12781 } else if ($cop$$cmpcode == Assembler::equal) {
12782 parity_disp = 6;
12783 ok = true;
12784 } else {
12785 ShouldNotReachHere();
12786 }
12787 emit_d32(cbuf, parity_disp);
12788 $$$emit8$primary;
12789 emit_cc(cbuf, $secondary, $cop$$cmpcode);
12790 int disp = l ? (l->loc_pos() - (cbuf.code_size() + 4)) : 0;
12791 emit_d32(cbuf, disp);
12792 %}
12793 ins_pipe(pipe_jcc);
12794 ins_pc_relative(1);
12795 %}
12796
12797 // ============================================================================
12798 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
12799 // array for an instance of the superklass. Set a hidden internal cache on a
12800 // hit (cache is checked with exposed code in gen_subtype_check()). Return
12801 // NZ for a miss or zero for a hit. The encoding ALSO sets flags.
12802 instruct partialSubtypeCheck( eDIRegP result, eSIRegP sub, eAXRegP super, eCXRegI rcx, eFlagsReg cr ) %{
12803 match(Set result (PartialSubtypeCheck sub super));
12804 effect( KILL rcx, KILL cr );
12805
12806 ins_cost(1100); // slightly larger than the next version
12807 format %{ "MOV EDI,[$sub+Klass::secondary_supers]\n\t"
12808 "MOV ECX,[EDI+arrayKlass::length]\t# length to scan\n\t"
12809 "ADD EDI,arrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t"
12810 "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t"
12811 "JNE,s miss\t\t# Missed: EDI not-zero\n\t"
12812 "MOV [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache\n\t"
12813 "XOR $result,$result\t\t Hit: EDI zero\n\t"
12814 "miss:\t" %}
12815
12816 opcode(0x1); // Force a XOR of EDI
12817 ins_encode( enc_PartialSubtypeCheck() );
12818 ins_pipe( pipe_slow );
12819 %}
12820
12821 instruct partialSubtypeCheck_vs_Zero( eFlagsReg cr, eSIRegP sub, eAXRegP super, eCXRegI rcx, eDIRegP result, immP0 zero ) %{
12822 match(Set cr (CmpP (PartialSubtypeCheck sub super) zero));
12823 effect( KILL rcx, KILL result );
12824
12825 ins_cost(1000);
12826 format %{ "MOV EDI,[$sub+Klass::secondary_supers]\n\t"
12827 "MOV ECX,[EDI+arrayKlass::length]\t# length to scan\n\t"
12828 "ADD EDI,arrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t"
12829 "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t"
12830 "JNE,s miss\t\t# Missed: flags NZ\n\t"
12831 "MOV [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache, flags Z\n\t"
12832 "miss:\t" %}
12833
12834 opcode(0x0); // No need to XOR EDI
12835 ins_encode( enc_PartialSubtypeCheck() );
12836 ins_pipe( pipe_slow );
12837 %}
12838
12839 // ============================================================================
12840 // Branch Instructions -- short offset versions
12841 //
12842 // These instructions are used to replace jumps of a long offset (the default
12843 // match) with jumps of a shorter offset. These instructions are all tagged
12844 // with the ins_short_branch attribute, which causes the ADLC to suppress the
12845 // match rules in general matching. Instead, the ADLC generates a conversion
12846 // method in the MachNode which can be used to do in-place replacement of the
12847 // long variant with the shorter variant. The compiler will determine if a
12848 // branch can be taken by the is_short_branch_offset() predicate in the machine
12849 // specific code section of the file.
12850
12851 // Jump Direct - Label defines a relative address from JMP+1
12852 instruct jmpDir_short(label labl) %{
12853 match(Goto);
12854 effect(USE labl);
12855
12856 ins_cost(300);
12857 format %{ "JMP,s $labl" %}
12858 size(2);
12859 opcode(0xEB);
12860 ins_encode( OpcP, LblShort( labl ) );
12861 ins_pipe( pipe_jmp );
12862 ins_pc_relative(1);
12863 ins_short_branch(1);
12864 %}
12865
12866 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12867 instruct jmpCon_short(cmpOp cop, eFlagsReg cr, label labl) %{
12868 match(If cop cr);
12869 effect(USE labl);
12870
12871 ins_cost(300);
12872 format %{ "J$cop,s $labl" %}
12873 size(2);
12874 opcode(0x70);
12875 ins_encode( JccShort( cop, labl) );
12876 ins_pipe( pipe_jcc );
12877 ins_pc_relative(1);
12878 ins_short_branch(1);
12879 %}
12880
12881 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12882 instruct jmpLoopEnd_short(cmpOp cop, eFlagsReg cr, label labl) %{
12883 match(CountedLoopEnd cop cr);
12884 effect(USE labl);
12885
12886 ins_cost(300);
12887 format %{ "J$cop,s $labl\t# Loop end" %}
12888 size(2);
12889 opcode(0x70);
12890 ins_encode( JccShort( cop, labl) );
12891 ins_pipe( pipe_jcc );
12892 ins_pc_relative(1);
12893 ins_short_branch(1);
12894 %}
12895
12896 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12897 instruct jmpLoopEndU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12898 match(CountedLoopEnd cop cmp);
12899 effect(USE labl);
12900
12901 ins_cost(300);
12902 format %{ "J$cop,us $labl\t# Loop end" %}
12903 size(2);
12904 opcode(0x70);
12905 ins_encode( JccShort( cop, labl) );
12906 ins_pipe( pipe_jcc );
12907 ins_pc_relative(1);
12908 ins_short_branch(1);
12909 %}
12910
12911 instruct jmpLoopEndUCF_short(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12912 match(CountedLoopEnd cop cmp);
12913 effect(USE labl);
12914
12915 ins_cost(300);
12916 format %{ "J$cop,us $labl\t# Loop end" %}
12917 size(2);
12918 opcode(0x70);
12919 ins_encode( JccShort( cop, labl) );
12920 ins_pipe( pipe_jcc );
12921 ins_pc_relative(1);
12922 ins_short_branch(1);
12923 %}
12924
12925 // Jump Direct Conditional - using unsigned comparison
12926 instruct jmpConU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12927 match(If cop cmp);
12928 effect(USE labl);
12929
12930 ins_cost(300);
12931 format %{ "J$cop,us $labl" %}
12932 size(2);
12933 opcode(0x70);
12934 ins_encode( JccShort( cop, labl) );
12935 ins_pipe( pipe_jcc );
12936 ins_pc_relative(1);
12937 ins_short_branch(1);
12938 %}
12939
12940 instruct jmpConUCF_short(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12941 match(If cop cmp);
12942 effect(USE labl);
12943
12944 ins_cost(300);
12945 format %{ "J$cop,us $labl" %}
12946 size(2);
12947 opcode(0x70);
12948 ins_encode( JccShort( cop, labl) );
12949 ins_pipe( pipe_jcc );
12950 ins_pc_relative(1);
12951 ins_short_branch(1);
12952 %}
12953
12954 instruct jmpConUCF2_short(cmpOpUCF2 cop, eFlagsRegUCF cmp, label labl) %{
12955 match(If cop cmp);
12956 effect(USE labl);
12957
12958 ins_cost(300);
12959 format %{ $$template
12960 if ($cop$$cmpcode == Assembler::notEqual) {
12961 $$emit$$"JP,u,s $labl\n\t"
12962 $$emit$$"J$cop,u,s $labl"
12963 } else {
12964 $$emit$$"JP,u,s done\n\t"
12965 $$emit$$"J$cop,u,s $labl\n\t"
12966 $$emit$$"done:"
12967 }
12968 %}
12969 size(4);
12970 opcode(0x70);
12971 ins_encode %{
12972 Label* l = $labl$$label;
12973 emit_cc(cbuf, $primary, Assembler::parity);
12974 int parity_disp = -1;
12975 if ($cop$$cmpcode == Assembler::notEqual) {
12976 parity_disp = l ? (l->loc_pos() - (cbuf.code_size() + 1)) : 0;
12977 } else if ($cop$$cmpcode == Assembler::equal) {
12978 parity_disp = 2;
12979 } else {
12980 ShouldNotReachHere();
12981 }
12982 emit_d8(cbuf, parity_disp);
12983 emit_cc(cbuf, $primary, $cop$$cmpcode);
12984 int disp = l ? (l->loc_pos() - (cbuf.code_size() + 1)) : 0;
12985 emit_d8(cbuf, disp);
12986 assert(-128 <= disp && disp <= 127, "Displacement too large for short jmp");
12987 assert(-128 <= parity_disp && parity_disp <= 127, "Displacement too large for short jmp");
12988 %}
12989 ins_pipe(pipe_jcc);
12990 ins_pc_relative(1);
12991 ins_short_branch(1);
12992 %}
12993
12994 // ============================================================================
12995 // Long Compare
12996 //
12997 // Currently we hold longs in 2 registers. Comparing such values efficiently
12998 // is tricky. The flavor of compare used depends on whether we are testing
12999 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit.
13000 // The GE test is the negated LT test. The LE test can be had by commuting
13001 // the operands (yielding a GE test) and then negating; negate again for the
13002 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the
13003 // NE test is negated from that.
13004
13005 // Due to a shortcoming in the ADLC, it mixes up expressions like:
13006 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the
13007 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections
13008 // are collapsed internally in the ADLC's dfa-gen code. The match for
13009 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the
13010 // foo match ends up with the wrong leaf. One fix is to not match both
13011 // reg-reg and reg-zero forms of long-compare. This is unfortunate because
13012 // both forms beat the trinary form of long-compare and both are very useful
13013 // on Intel which has so few registers.
13014
13015 // Manifest a CmpL result in an integer register. Very painful.
13016 // This is the test to avoid.
13017 instruct cmpL3_reg_reg(eSIRegI dst, eRegL src1, eRegL src2, eFlagsReg flags ) %{
13018 match(Set dst (CmpL3 src1 src2));
13019 effect( KILL flags );
13020 ins_cost(1000);
13021 format %{ "XOR $dst,$dst\n\t"
13022 "CMP $src1.hi,$src2.hi\n\t"
13023 "JLT,s m_one\n\t"
13024 "JGT,s p_one\n\t"
13025 "CMP $src1.lo,$src2.lo\n\t"
13026 "JB,s m_one\n\t"
13027 "JEQ,s done\n"
13028 "p_one:\tINC $dst\n\t"
13029 "JMP,s done\n"
13030 "m_one:\tDEC $dst\n"
13031 "done:" %}
13032 ins_encode %{
13033 Label p_one, m_one, done;
13034 __ xorptr($dst$$Register, $dst$$Register);
13035 __ cmpl(HIGH_FROM_LOW($src1$$Register), HIGH_FROM_LOW($src2$$Register));
13036 __ jccb(Assembler::less, m_one);
13037 __ jccb(Assembler::greater, p_one);
13038 __ cmpl($src1$$Register, $src2$$Register);
13039 __ jccb(Assembler::below, m_one);
13040 __ jccb(Assembler::equal, done);
13041 __ bind(p_one);
13042 __ incrementl($dst$$Register);
13043 __ jmpb(done);
13044 __ bind(m_one);
13045 __ decrementl($dst$$Register);
13046 __ bind(done);
13047 %}
13048 ins_pipe( pipe_slow );
13049 %}
13050
13051 //======
13052 // Manifest a CmpL result in the normal flags. Only good for LT or GE
13053 // compares. Can be used for LE or GT compares by reversing arguments.
13054 // NOT GOOD FOR EQ/NE tests.
13055 instruct cmpL_zero_flags_LTGE( flagsReg_long_LTGE flags, eRegL src, immL0 zero ) %{
13056 match( Set flags (CmpL src zero ));
13057 ins_cost(100);
13058 format %{ "TEST $src.hi,$src.hi" %}
13059 opcode(0x85);
13060 ins_encode( OpcP, RegReg_Hi2( src, src ) );
13061 ins_pipe( ialu_cr_reg_reg );
13062 %}
13063
13064 // Manifest a CmpL result in the normal flags. Only good for LT or GE
13065 // compares. Can be used for LE or GT compares by reversing arguments.
13066 // NOT GOOD FOR EQ/NE tests.
13067 instruct cmpL_reg_flags_LTGE( flagsReg_long_LTGE flags, eRegL src1, eRegL src2, eRegI tmp ) %{
13068 match( Set flags (CmpL src1 src2 ));
13069 effect( TEMP tmp );
13070 ins_cost(300);
13071 format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t"
13072 "MOV $tmp,$src1.hi\n\t"
13073 "SBB $tmp,$src2.hi\t! Compute flags for long compare" %}
13074 ins_encode( long_cmp_flags2( src1, src2, tmp ) );
13075 ins_pipe( ialu_cr_reg_reg );
13076 %}
13077
13078 // Long compares reg < zero/req OR reg >= zero/req.
13079 // Just a wrapper for a normal branch, plus the predicate test.
13080 instruct cmpL_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, label labl) %{
13081 match(If cmp flags);
13082 effect(USE labl);
13083 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
13084 expand %{
13085 jmpCon(cmp,flags,labl); // JLT or JGE...
13086 %}
13087 %}
13088
13089 // Compare 2 longs and CMOVE longs.
13090 instruct cmovLL_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, eRegL src) %{
13091 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
13092 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
13093 ins_cost(400);
13094 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
13095 "CMOV$cmp $dst.hi,$src.hi" %}
13096 opcode(0x0F,0x40);
13097 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
13098 ins_pipe( pipe_cmov_reg_long );
13099 %}
13100
13101 instruct cmovLL_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, load_long_memory src) %{
13102 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
13103 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
13104 ins_cost(500);
13105 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
13106 "CMOV$cmp $dst.hi,$src.hi" %}
13107 opcode(0x0F,0x40);
13108 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
13109 ins_pipe( pipe_cmov_reg_long );
13110 %}
13111
13112 // Compare 2 longs and CMOVE ints.
13113 instruct cmovII_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegI dst, eRegI src) %{
13114 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
13115 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
13116 ins_cost(200);
13117 format %{ "CMOV$cmp $dst,$src" %}
13118 opcode(0x0F,0x40);
13119 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
13120 ins_pipe( pipe_cmov_reg );
13121 %}
13122
13123 instruct cmovII_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegI dst, memory src) %{
13124 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
13125 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
13126 ins_cost(250);
13127 format %{ "CMOV$cmp $dst,$src" %}
13128 opcode(0x0F,0x40);
13129 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
13130 ins_pipe( pipe_cmov_mem );
13131 %}
13132
13133 // Compare 2 longs and CMOVE ints.
13134 instruct cmovPP_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegP dst, eRegP src) %{
13135 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
13136 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
13137 ins_cost(200);
13138 format %{ "CMOV$cmp $dst,$src" %}
13139 opcode(0x0F,0x40);
13140 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
13141 ins_pipe( pipe_cmov_reg );
13142 %}
13143
13144 // Compare 2 longs and CMOVE doubles
13145 instruct cmovDD_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regD dst, regD src) %{
13146 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
13147 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
13148 ins_cost(200);
13149 expand %{
13150 fcmovD_regS(cmp,flags,dst,src);
13151 %}
13152 %}
13153
13154 // Compare 2 longs and CMOVE doubles
13155 instruct cmovXDD_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regXD dst, regXD src) %{
13156 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
13157 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
13158 ins_cost(200);
13159 expand %{
13160 fcmovXD_regS(cmp,flags,dst,src);
13161 %}
13162 %}
13163
13164 instruct cmovFF_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regF dst, regF src) %{
13165 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
13166 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
13167 ins_cost(200);
13168 expand %{
13169 fcmovF_regS(cmp,flags,dst,src);
13170 %}
13171 %}
13172
13173 instruct cmovXX_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regX dst, regX src) %{
13174 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
13175 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
13176 ins_cost(200);
13177 expand %{
13178 fcmovX_regS(cmp,flags,dst,src);
13179 %}
13180 %}
13181
13182 //======
13183 // Manifest a CmpL result in the normal flags. Only good for EQ/NE compares.
13184 instruct cmpL_zero_flags_EQNE( flagsReg_long_EQNE flags, eRegL src, immL0 zero, eRegI tmp ) %{
13185 match( Set flags (CmpL src zero ));
13186 effect(TEMP tmp);
13187 ins_cost(200);
13188 format %{ "MOV $tmp,$src.lo\n\t"
13189 "OR $tmp,$src.hi\t! Long is EQ/NE 0?" %}
13190 ins_encode( long_cmp_flags0( src, tmp ) );
13191 ins_pipe( ialu_reg_reg_long );
13192 %}
13193
13194 // Manifest a CmpL result in the normal flags. Only good for EQ/NE compares.
13195 instruct cmpL_reg_flags_EQNE( flagsReg_long_EQNE flags, eRegL src1, eRegL src2 ) %{
13196 match( Set flags (CmpL src1 src2 ));
13197 ins_cost(200+300);
13198 format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t"
13199 "JNE,s skip\n\t"
13200 "CMP $src1.hi,$src2.hi\n\t"
13201 "skip:\t" %}
13202 ins_encode( long_cmp_flags1( src1, src2 ) );
13203 ins_pipe( ialu_cr_reg_reg );
13204 %}
13205
13206 // Long compare reg == zero/reg OR reg != zero/reg
13207 // Just a wrapper for a normal branch, plus the predicate test.
13208 instruct cmpL_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, label labl) %{
13209 match(If cmp flags);
13210 effect(USE labl);
13211 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
13212 expand %{
13213 jmpCon(cmp,flags,labl); // JEQ or JNE...
13214 %}
13215 %}
13216
13217 // Compare 2 longs and CMOVE longs.
13218 instruct cmovLL_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, eRegL src) %{
13219 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
13220 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
13221 ins_cost(400);
13222 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
13223 "CMOV$cmp $dst.hi,$src.hi" %}
13224 opcode(0x0F,0x40);
13225 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
13226 ins_pipe( pipe_cmov_reg_long );
13227 %}
13228
13229 instruct cmovLL_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, load_long_memory src) %{
13230 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
13231 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
13232 ins_cost(500);
13233 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
13234 "CMOV$cmp $dst.hi,$src.hi" %}
13235 opcode(0x0F,0x40);
13236 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
13237 ins_pipe( pipe_cmov_reg_long );
13238 %}
13239
13240 // Compare 2 longs and CMOVE ints.
13241 instruct cmovII_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegI dst, eRegI src) %{
13242 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
13243 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
13244 ins_cost(200);
13245 format %{ "CMOV$cmp $dst,$src" %}
13246 opcode(0x0F,0x40);
13247 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
13248 ins_pipe( pipe_cmov_reg );
13249 %}
13250
13251 instruct cmovII_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegI dst, memory src) %{
13252 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
13253 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
13254 ins_cost(250);
13255 format %{ "CMOV$cmp $dst,$src" %}
13256 opcode(0x0F,0x40);
13257 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
13258 ins_pipe( pipe_cmov_mem );
13259 %}
13260
13261 // Compare 2 longs and CMOVE ints.
13262 instruct cmovPP_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegP dst, eRegP src) %{
13263 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
13264 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
13265 ins_cost(200);
13266 format %{ "CMOV$cmp $dst,$src" %}
13267 opcode(0x0F,0x40);
13268 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
13269 ins_pipe( pipe_cmov_reg );
13270 %}
13271
13272 // Compare 2 longs and CMOVE doubles
13273 instruct cmovDD_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regD dst, regD src) %{
13274 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
13275 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
13276 ins_cost(200);
13277 expand %{
13278 fcmovD_regS(cmp,flags,dst,src);
13279 %}
13280 %}
13281
13282 // Compare 2 longs and CMOVE doubles
13283 instruct cmovXDD_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regXD dst, regXD src) %{
13284 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
13285 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
13286 ins_cost(200);
13287 expand %{
13288 fcmovXD_regS(cmp,flags,dst,src);
13289 %}
13290 %}
13291
13292 instruct cmovFF_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regF dst, regF src) %{
13293 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
13294 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
13295 ins_cost(200);
13296 expand %{
13297 fcmovF_regS(cmp,flags,dst,src);
13298 %}
13299 %}
13300
13301 instruct cmovXX_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regX dst, regX src) %{
13302 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
13303 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
13304 ins_cost(200);
13305 expand %{
13306 fcmovX_regS(cmp,flags,dst,src);
13307 %}
13308 %}
13309
13310 //======
13311 // Manifest a CmpL result in the normal flags. Only good for LE or GT compares.
13312 // Same as cmpL_reg_flags_LEGT except must negate src
13313 instruct cmpL_zero_flags_LEGT( flagsReg_long_LEGT flags, eRegL src, immL0 zero, eRegI tmp ) %{
13314 match( Set flags (CmpL src zero ));
13315 effect( TEMP tmp );
13316 ins_cost(300);
13317 format %{ "XOR $tmp,$tmp\t# Long compare for -$src < 0, use commuted test\n\t"
13318 "CMP $tmp,$src.lo\n\t"
13319 "SBB $tmp,$src.hi\n\t" %}
13320 ins_encode( long_cmp_flags3(src, tmp) );
13321 ins_pipe( ialu_reg_reg_long );
13322 %}
13323
13324 // Manifest a CmpL result in the normal flags. Only good for LE or GT compares.
13325 // Same as cmpL_reg_flags_LTGE except operands swapped. Swapping operands
13326 // requires a commuted test to get the same result.
13327 instruct cmpL_reg_flags_LEGT( flagsReg_long_LEGT flags, eRegL src1, eRegL src2, eRegI tmp ) %{
13328 match( Set flags (CmpL src1 src2 ));
13329 effect( TEMP tmp );
13330 ins_cost(300);
13331 format %{ "CMP $src2.lo,$src1.lo\t! Long compare, swapped operands, use with commuted test\n\t"
13332 "MOV $tmp,$src2.hi\n\t"
13333 "SBB $tmp,$src1.hi\t! Compute flags for long compare" %}
13334 ins_encode( long_cmp_flags2( src2, src1, tmp ) );
13335 ins_pipe( ialu_cr_reg_reg );
13336 %}
13337
13338 // Long compares reg < zero/req OR reg >= zero/req.
13339 // Just a wrapper for a normal branch, plus the predicate test
13340 instruct cmpL_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, label labl) %{
13341 match(If cmp flags);
13342 effect(USE labl);
13343 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le );
13344 ins_cost(300);
13345 expand %{
13346 jmpCon(cmp,flags,labl); // JGT or JLE...
13347 %}
13348 %}
13349
13350 // Compare 2 longs and CMOVE longs.
13351 instruct cmovLL_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, eRegL src) %{
13352 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
13353 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
13354 ins_cost(400);
13355 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
13356 "CMOV$cmp $dst.hi,$src.hi" %}
13357 opcode(0x0F,0x40);
13358 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
13359 ins_pipe( pipe_cmov_reg_long );
13360 %}
13361
13362 instruct cmovLL_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, load_long_memory src) %{
13363 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
13364 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
13365 ins_cost(500);
13366 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
13367 "CMOV$cmp $dst.hi,$src.hi+4" %}
13368 opcode(0x0F,0x40);
13369 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
13370 ins_pipe( pipe_cmov_reg_long );
13371 %}
13372
13373 // Compare 2 longs and CMOVE ints.
13374 instruct cmovII_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegI dst, eRegI src) %{
13375 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
13376 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
13377 ins_cost(200);
13378 format %{ "CMOV$cmp $dst,$src" %}
13379 opcode(0x0F,0x40);
13380 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
13381 ins_pipe( pipe_cmov_reg );
13382 %}
13383
13384 instruct cmovII_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegI dst, memory src) %{
13385 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
13386 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
13387 ins_cost(250);
13388 format %{ "CMOV$cmp $dst,$src" %}
13389 opcode(0x0F,0x40);
13390 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
13391 ins_pipe( pipe_cmov_mem );
13392 %}
13393
13394 // Compare 2 longs and CMOVE ptrs.
13395 instruct cmovPP_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegP dst, eRegP src) %{
13396 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
13397 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
13398 ins_cost(200);
13399 format %{ "CMOV$cmp $dst,$src" %}
13400 opcode(0x0F,0x40);
13401 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
13402 ins_pipe( pipe_cmov_reg );
13403 %}
13404
13405 // Compare 2 longs and CMOVE doubles
13406 instruct cmovDD_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regD dst, regD src) %{
13407 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
13408 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
13409 ins_cost(200);
13410 expand %{
13411 fcmovD_regS(cmp,flags,dst,src);
13412 %}
13413 %}
13414
13415 // Compare 2 longs and CMOVE doubles
13416 instruct cmovXDD_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regXD dst, regXD src) %{
13417 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
13418 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
13419 ins_cost(200);
13420 expand %{
13421 fcmovXD_regS(cmp,flags,dst,src);
13422 %}
13423 %}
13424
13425 instruct cmovFF_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regF dst, regF src) %{
13426 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
13427 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
13428 ins_cost(200);
13429 expand %{
13430 fcmovF_regS(cmp,flags,dst,src);
13431 %}
13432 %}
13433
13434
13435 instruct cmovXX_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regX dst, regX src) %{
13436 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
13437 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
13438 ins_cost(200);
13439 expand %{
13440 fcmovX_regS(cmp,flags,dst,src);
13441 %}
13442 %}
13443
13444
13445 // ============================================================================
13446 // Procedure Call/Return Instructions
13447 // Call Java Static Instruction
13448 // Note: If this code changes, the corresponding ret_addr_offset() and
13449 // compute_padding() functions will have to be adjusted.
13450 instruct CallStaticJavaDirect(method meth) %{
13451 match(CallStaticJava);
13452 predicate(! ((CallStaticJavaNode*)n)->is_method_handle_invoke());
13453 effect(USE meth);
13454
13455 ins_cost(300);
13456 format %{ "CALL,static " %}
13457 opcode(0xE8); /* E8 cd */
13458 ins_encode( pre_call_FPU,
13459 Java_Static_Call( meth ),
13460 call_epilog,
13461 post_call_FPU );
13462 ins_pipe( pipe_slow );
13463 ins_pc_relative(1);
13464 ins_alignment(4);
13465 %}
13466
13467 // Call Java Static Instruction (method handle version)
13468 // Note: If this code changes, the corresponding ret_addr_offset() and
13469 // compute_padding() functions will have to be adjusted.
13470 instruct CallStaticJavaHandle(method meth, eBPRegP ebp) %{
13471 match(CallStaticJava);
13472 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke());
13473 effect(USE meth);
13474 // EBP is saved by all callees (for interpreter stack correction).
13475 // We use it here for a similar purpose, in {preserve,restore}_SP.
13476
13477 ins_cost(300);
13478 format %{ "CALL,static MethodHandle " %}
13479 opcode(0xE8); /* E8 cd */
13480 ins_encode( pre_call_FPU,
13481 preserve_SP,
13482 Java_Static_Call( meth ),
13483 restore_SP,
13484 call_epilog,
13485 post_call_FPU );
13486 ins_pipe( pipe_slow );
13487 ins_pc_relative(1);
13488 ins_alignment(4);
13489 %}
13490
13491 // Call Java Dynamic Instruction
13492 // Note: If this code changes, the corresponding ret_addr_offset() and
13493 // compute_padding() functions will have to be adjusted.
13494 instruct CallDynamicJavaDirect(method meth) %{
13495 match(CallDynamicJava);
13496 effect(USE meth);
13497
13498 ins_cost(300);
13499 format %{ "MOV EAX,(oop)-1\n\t"
13500 "CALL,dynamic" %}
13501 opcode(0xE8); /* E8 cd */
13502 ins_encode( pre_call_FPU,
13503 Java_Dynamic_Call( meth ),
13504 call_epilog,
13505 post_call_FPU );
13506 ins_pipe( pipe_slow );
13507 ins_pc_relative(1);
13508 ins_alignment(4);
13509 %}
13510
13511 // Call Runtime Instruction
13512 instruct CallRuntimeDirect(method meth) %{
13513 match(CallRuntime );
13514 effect(USE meth);
13515
13516 ins_cost(300);
13517 format %{ "CALL,runtime " %}
13518 opcode(0xE8); /* E8 cd */
13519 // Use FFREEs to clear entries in float stack
13520 ins_encode( pre_call_FPU,
13521 FFree_Float_Stack_All,
13522 Java_To_Runtime( meth ),
13523 post_call_FPU );
13524 ins_pipe( pipe_slow );
13525 ins_pc_relative(1);
13526 %}
13527
13528 // Call runtime without safepoint
13529 instruct CallLeafDirect(method meth) %{
13530 match(CallLeaf);
13531 effect(USE meth);
13532
13533 ins_cost(300);
13534 format %{ "CALL_LEAF,runtime " %}
13535 opcode(0xE8); /* E8 cd */
13536 ins_encode( pre_call_FPU,
13537 FFree_Float_Stack_All,
13538 Java_To_Runtime( meth ),
13539 Verify_FPU_For_Leaf, post_call_FPU );
13540 ins_pipe( pipe_slow );
13541 ins_pc_relative(1);
13542 %}
13543
13544 instruct CallLeafNoFPDirect(method meth) %{
13545 match(CallLeafNoFP);
13546 effect(USE meth);
13547
13548 ins_cost(300);
13549 format %{ "CALL_LEAF_NOFP,runtime " %}
13550 opcode(0xE8); /* E8 cd */
13551 ins_encode(Java_To_Runtime(meth));
13552 ins_pipe( pipe_slow );
13553 ins_pc_relative(1);
13554 %}
13555
13556
13557 // Return Instruction
13558 // Remove the return address & jump to it.
13559 instruct Ret() %{
13560 match(Return);
13561 format %{ "RET" %}
13562 opcode(0xC3);
13563 ins_encode(OpcP);
13564 ins_pipe( pipe_jmp );
13565 %}
13566
13567 // Tail Call; Jump from runtime stub to Java code.
13568 // Also known as an 'interprocedural jump'.
13569 // Target of jump will eventually return to caller.
13570 // TailJump below removes the return address.
13571 instruct TailCalljmpInd(eRegP_no_EBP jump_target, eBXRegP method_oop) %{
13572 match(TailCall jump_target method_oop );
13573 ins_cost(300);
13574 format %{ "JMP $jump_target \t# EBX holds method oop" %}
13575 opcode(0xFF, 0x4); /* Opcode FF /4 */
13576 ins_encode( OpcP, RegOpc(jump_target) );
13577 ins_pipe( pipe_jmp );
13578 %}
13579
13580
13581 // Tail Jump; remove the return address; jump to target.
13582 // TailCall above leaves the return address around.
13583 instruct tailjmpInd(eRegP_no_EBP jump_target, eAXRegP ex_oop) %{
13584 match( TailJump jump_target ex_oop );
13585 ins_cost(300);
13586 format %{ "POP EDX\t# pop return address into dummy\n\t"
13587 "JMP $jump_target " %}
13588 opcode(0xFF, 0x4); /* Opcode FF /4 */
13589 ins_encode( enc_pop_rdx,
13590 OpcP, RegOpc(jump_target) );
13591 ins_pipe( pipe_jmp );
13592 %}
13593
13594 // Create exception oop: created by stack-crawling runtime code.
13595 // Created exception is now available to this handler, and is setup
13596 // just prior to jumping to this handler. No code emitted.
13597 instruct CreateException( eAXRegP ex_oop )
13598 %{
13599 match(Set ex_oop (CreateEx));
13600
13601 size(0);
13602 // use the following format syntax
13603 format %{ "# exception oop is in EAX; no code emitted" %}
13604 ins_encode();
13605 ins_pipe( empty );
13606 %}
13607
13608
13609 // Rethrow exception:
13610 // The exception oop will come in the first argument position.
13611 // Then JUMP (not call) to the rethrow stub code.
13612 instruct RethrowException()
13613 %{
13614 match(Rethrow);
13615
13616 // use the following format syntax
13617 format %{ "JMP rethrow_stub" %}
13618 ins_encode(enc_rethrow);
13619 ins_pipe( pipe_jmp );
13620 %}
13621
13622 // inlined locking and unlocking
13623
13624
13625 instruct cmpFastLock( eFlagsReg cr, eRegP object, eRegP box, eAXRegI tmp, eRegP scr) %{
13626 match( Set cr (FastLock object box) );
13627 effect( TEMP tmp, TEMP scr );
13628 ins_cost(300);
13629 format %{ "FASTLOCK $object, $box KILLS $tmp,$scr" %}
13630 ins_encode( Fast_Lock(object,box,tmp,scr) );
13631 ins_pipe( pipe_slow );
13632 ins_pc_relative(1);
13633 %}
13634
13635 instruct cmpFastUnlock( eFlagsReg cr, eRegP object, eAXRegP box, eRegP tmp ) %{
13636 match( Set cr (FastUnlock object box) );
13637 effect( TEMP tmp );
13638 ins_cost(300);
13639 format %{ "FASTUNLOCK $object, $box, $tmp" %}
13640 ins_encode( Fast_Unlock(object,box,tmp) );
13641 ins_pipe( pipe_slow );
13642 ins_pc_relative(1);
13643 %}
13644
13645
13646
13647 // ============================================================================
13648 // Safepoint Instruction
13649 instruct safePoint_poll(eFlagsReg cr) %{
13650 match(SafePoint);
13651 effect(KILL cr);
13652
13653 // TODO-FIXME: we currently poll at offset 0 of the safepoint polling page.
13654 // On SPARC that might be acceptable as we can generate the address with
13655 // just a sethi, saving an or. By polling at offset 0 we can end up
13656 // putting additional pressure on the index-0 in the D$. Because of
13657 // alignment (just like the situation at hand) the lower indices tend
13658 // to see more traffic. It'd be better to change the polling address
13659 // to offset 0 of the last $line in the polling page.
13660
13661 format %{ "TSTL #polladdr,EAX\t! Safepoint: poll for GC" %}
13662 ins_cost(125);
13663 size(6) ;
13664 ins_encode( Safepoint_Poll() );
13665 ins_pipe( ialu_reg_mem );
13666 %}
13667
13668 //----------PEEPHOLE RULES-----------------------------------------------------
13669 // These must follow all instruction definitions as they use the names
13670 // defined in the instructions definitions.
13671 //
13672 // peepmatch ( root_instr_name [preceding_instruction]* );
13673 //
13674 // peepconstraint %{
13675 // (instruction_number.operand_name relational_op instruction_number.operand_name
13676 // [, ...] );
13677 // // instruction numbers are zero-based using left to right order in peepmatch
13678 //
13679 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
13680 // // provide an instruction_number.operand_name for each operand that appears
13681 // // in the replacement instruction's match rule
13682 //
13683 // ---------VM FLAGS---------------------------------------------------------
13684 //
13685 // All peephole optimizations can be turned off using -XX:-OptoPeephole
13686 //
13687 // Each peephole rule is given an identifying number starting with zero and
13688 // increasing by one in the order seen by the parser. An individual peephole
13689 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
13690 // on the command-line.
13691 //
13692 // ---------CURRENT LIMITATIONS----------------------------------------------
13693 //
13694 // Only match adjacent instructions in same basic block
13695 // Only equality constraints
13696 // Only constraints between operands, not (0.dest_reg == EAX_enc)
13697 // Only one replacement instruction
13698 //
13699 // ---------EXAMPLE----------------------------------------------------------
13700 //
13701 // // pertinent parts of existing instructions in architecture description
13702 // instruct movI(eRegI dst, eRegI src) %{
13703 // match(Set dst (CopyI src));
13704 // %}
13705 //
13706 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
13707 // match(Set dst (AddI dst src));
13708 // effect(KILL cr);
13709 // %}
13710 //
13711 // // Change (inc mov) to lea
13712 // peephole %{
13713 // // increment preceeded by register-register move
13714 // peepmatch ( incI_eReg movI );
13715 // // require that the destination register of the increment
13716 // // match the destination register of the move
13717 // peepconstraint ( 0.dst == 1.dst );
13718 // // construct a replacement instruction that sets
13719 // // the destination to ( move's source register + one )
13720 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13721 // %}
13722 //
13723 // Implementation no longer uses movX instructions since
13724 // machine-independent system no longer uses CopyX nodes.
13725 //
13726 // peephole %{
13727 // peepmatch ( incI_eReg movI );
13728 // peepconstraint ( 0.dst == 1.dst );
13729 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13730 // %}
13731 //
13732 // peephole %{
13733 // peepmatch ( decI_eReg movI );
13734 // peepconstraint ( 0.dst == 1.dst );
13735 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13736 // %}
13737 //
13738 // peephole %{
13739 // peepmatch ( addI_eReg_imm movI );
13740 // peepconstraint ( 0.dst == 1.dst );
13741 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13742 // %}
13743 //
13744 // peephole %{
13745 // peepmatch ( addP_eReg_imm movP );
13746 // peepconstraint ( 0.dst == 1.dst );
13747 // peepreplace ( leaP_eReg_immI( 0.dst 1.src 0.src ) );
13748 // %}
13749
13750 // // Change load of spilled value to only a spill
13751 // instruct storeI(memory mem, eRegI src) %{
13752 // match(Set mem (StoreI mem src));
13753 // %}
13754 //
13755 // instruct loadI(eRegI dst, memory mem) %{
13756 // match(Set dst (LoadI mem));
13757 // %}
13758 //
13759 peephole %{
13760 peepmatch ( loadI storeI );
13761 peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
13762 peepreplace ( storeI( 1.mem 1.mem 1.src ) );
13763 %}
13764
13765 //----------SMARTSPILL RULES---------------------------------------------------
13766 // These must follow all instruction definitions as they use the names
13767 // defined in the instructions definitions.