src/cpu/x86/vm/x86_32.ad
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src/cpu/x86/vm/x86_32.ad

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rev 1082 : [mq]: indy.compiler.patch


 251 // Note: 'double' and 'long long' have 32-bits alignment on x86.
 252 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) {
 253   // Use the expression (adr)&(~0xF) to provide 128-bits aligned address
 254   // of 128-bits operands for SSE instructions.
 255   jlong *operand = (jlong*)(((uintptr_t)adr)&((uintptr_t)(~0xF)));
 256   // Store the value to a 128-bits operand.
 257   operand[0] = lo;
 258   operand[1] = hi;
 259   return operand;
 260 }
 261 
 262 // Buffer for 128-bits masks used by SSE instructions.
 263 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment)
 264 
 265 // Static initialization during VM startup.
 266 static jlong *float_signmask_pool  = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF));
 267 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF));
 268 static jlong *float_signflip_pool  = double_quadword(&fp_signmask_pool[3*2], CONST64(0x8000000080000000), CONST64(0x8000000080000000));
 269 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], CONST64(0x8000000000000000), CONST64(0x8000000000000000));
 270 











 271 // !!!!! Special hack to get all type of calls to specify the byte offset
 272 //       from the start of the call to the point where the return address
 273 //       will point.
 274 int MachCallStaticJavaNode::ret_addr_offset() {
 275   return 5 + (Compile::current()->in_24_bit_fp_mode() ? 6 : 0);  // 5 bytes from start of call to where return address points



 276 }
 277 
 278 int MachCallDynamicJavaNode::ret_addr_offset() {
 279   return 10 + (Compile::current()->in_24_bit_fp_mode() ? 6 : 0);  // 10 bytes from start of call to where return address points
 280 }
 281 
 282 static int sizeof_FFree_Float_Stack_All = -1;
 283 
 284 int MachCallRuntimeNode::ret_addr_offset() {
 285   assert(sizeof_FFree_Float_Stack_All != -1, "must have been emitted already");
 286   return sizeof_FFree_Float_Stack_All + 5 + (Compile::current()->in_24_bit_fp_mode() ? 6 : 0);
 287 }
 288 
 289 // Indicate if the safepoint node needs the polling page as an input.
 290 // Since x86 does have absolute addressing, it doesn't.
 291 bool SafePointNode::needs_polling_address_input() {
 292   return false;
 293 }
 294 
 295 //
 296 // Compute padding required for nodes which need alignment
 297 //
 298 
 299 // The address of the call instruction needs to be 4-byte aligned to
 300 // ensure that it does not span a cache line so that it can be patched.
 301 int CallStaticJavaDirectNode::compute_padding(int current_offset) const {
 302   if (Compile::current()->in_24_bit_fp_mode())
 303     current_offset += 6;    // skip fldcw in pre_call_FPU, if any








 304   current_offset += 1;      // skip call opcode byte
 305   return round_to(current_offset, alignment_required()) - current_offset;
 306 }
 307 
 308 // The address of the call instruction needs to be 4-byte aligned to
 309 // ensure that it does not span a cache line so that it can be patched.
 310 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const {
 311   if (Compile::current()->in_24_bit_fp_mode())
 312     current_offset += 6;    // skip fldcw in pre_call_FPU, if any
 313   current_offset += 5;      // skip MOV instruction
 314   current_offset += 1;      // skip call opcode byte
 315   return round_to(current_offset, alignment_required()) - current_offset;
 316 }
 317 
 318 #ifndef PRODUCT
 319 void MachBreakpointNode::format( PhaseRegAlloc *, outputStream* st ) const {
 320   st->print("INT3");
 321 }
 322 #endif
 323 
 324 // EMIT_RM()
 325 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) {
 326   unsigned char c = (unsigned char)((f1 << 6) | (f2 << 3) | f3);
 327   *(cbuf.code_end()) = c;
 328   cbuf.set_code_end(cbuf.code_end() + 1);
 329 }
 330 
 331 // EMIT_CC()
 332 void emit_cc(CodeBuffer &cbuf, int f1, int f2) {


1443   return EAX_REG_mask;
1444 }
1445 
1446 // Register for MODI projection of divmodI
1447 RegMask Matcher::modI_proj_mask() {
1448   return EDX_REG_mask;
1449 }
1450 
1451 // Register for DIVL projection of divmodL
1452 RegMask Matcher::divL_proj_mask() {
1453   ShouldNotReachHere();
1454   return RegMask();
1455 }
1456 
1457 // Register for MODL projection of divmodL
1458 RegMask Matcher::modL_proj_mask() {
1459   ShouldNotReachHere();
1460   return RegMask();
1461 }
1462 




1463 %}
1464 
1465 //----------ENCODING BLOCK-----------------------------------------------------
1466 // This block specifies the encoding classes used by the compiler to output
1467 // byte streams.  Encoding classes generate functions which are called by
1468 // Machine Instruction Nodes in order to generate the bit encoding of the
1469 // instruction.  Operands specify their base encoding interface with the
1470 // interface keyword.  There are currently supported four interfaces,
1471 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER.  REG_INTER causes an
1472 // operand to generate a function which returns its register number when
1473 // queried.   CONST_INTER causes an operand to generate a function which
1474 // returns the value of the constant when queried.  MEMORY_INTER causes an
1475 // operand to generate four functions which return the Base Register, the
1476 // Index Register, the Scale Value, and the Offset Value of the operand when
1477 // queried.  COND_INTER causes an operand to generate six functions which
1478 // return the encoding code (ie - encoding bits for the instruction)
1479 // associated with each basic boolean condition for a conditional instruction.
1480 // Instructions specify two basic values for encoding.  They use the
1481 // ins_encode keyword to specify their encoding class (which must be one of
1482 // the class names specified in the encoding block), and they use the


1755         // likely that this function call could be removed by the
1756         // optimizer if the C function is a pure function.
1757         __ ffree(0);
1758       } else if (rt == T_FLOAT) {
1759         __ lea(rsp, Address(rsp, -4));
1760         __ fstp_s(Address(rsp, 0));
1761         __ movflt(xmm0, Address(rsp, 0));
1762         __ lea(rsp, Address(rsp,  4));
1763       } else if (rt == T_DOUBLE) {
1764         __ lea(rsp, Address(rsp, -8));
1765         __ fstp_d(Address(rsp, 0));
1766         __ movdbl(xmm0, Address(rsp, 0));
1767         __ lea(rsp, Address(rsp,  8));
1768       }
1769     }
1770   %}
1771 
1772 
1773   enc_class pre_call_FPU %{
1774     // If method sets FPU control word restore it here

1775     if( Compile::current()->in_24_bit_fp_mode() ) {
1776       MacroAssembler masm(&cbuf);
1777       masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
1778     }


1779   %}
1780 
1781   enc_class post_call_FPU %{
1782     // If method sets FPU control word do it here also
1783     if( Compile::current()->in_24_bit_fp_mode() ) {
1784       MacroAssembler masm(&cbuf);
1785       masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
1786     }
1787   %}
1788 















1789   enc_class Java_Static_Call (method meth) %{    // JAVA STATIC CALL
1790     // CALL to fixup routine.  Fixup routine uses ScopeDesc info to determine
1791     // who we intended to call.
1792     cbuf.set_inst_mark();
1793     $$$emit8$primary;
1794     if ( !_method ) {
1795       emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.code_end()) - 4),
1796                      runtime_call_Relocation::spec(), RELOC_IMM32 );
1797     } else if(_optimized_virtual) {
1798       emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.code_end()) - 4),
1799                      opt_virtual_call_Relocation::spec(), RELOC_IMM32 );
1800     } else {
1801       emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.code_end()) - 4),
1802                      static_call_Relocation::spec(), RELOC_IMM32 );
1803     }
1804     if( _method ) {  // Emit stub for static call
1805       emit_java_to_interp(cbuf);
1806     }
1807   %}
1808 


13389 %}
13390 
13391 
13392 instruct cmovXX_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regX dst, regX src) %{
13393   predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
13394   match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
13395   ins_cost(200);
13396   expand %{
13397     fcmovX_regS(cmp,flags,dst,src);
13398   %}
13399 %}
13400 
13401 
13402 // ============================================================================
13403 // Procedure Call/Return Instructions
13404 // Call Java Static Instruction
13405 // Note: If this code changes, the corresponding ret_addr_offset() and
13406 //       compute_padding() functions will have to be adjusted.
13407 instruct CallStaticJavaDirect(method meth) %{
13408   match(CallStaticJava);

13409   effect(USE meth);
13410 
13411   ins_cost(300);
13412   format %{ "CALL,static " %}
13413   opcode(0xE8); /* E8 cd */
13414   ins_encode( pre_call_FPU,
13415               Java_Static_Call( meth ),
13416               call_epilog,
13417               post_call_FPU );
13418   ins_pipe( pipe_slow );
13419   ins_pc_relative(1);
13420   ins_alignment(4);
13421 %}
13422 
























13423 // Call Java Dynamic Instruction
13424 // Note: If this code changes, the corresponding ret_addr_offset() and
13425 //       compute_padding() functions will have to be adjusted.
13426 instruct CallDynamicJavaDirect(method meth) %{
13427   match(CallDynamicJava);
13428   effect(USE meth);
13429 
13430   ins_cost(300);
13431   format %{ "MOV    EAX,(oop)-1\n\t"
13432             "CALL,dynamic" %}
13433   opcode(0xE8); /* E8 cd */
13434   ins_encode( pre_call_FPU,
13435               Java_Dynamic_Call( meth ),
13436               call_epilog,
13437               post_call_FPU );
13438   ins_pipe( pipe_slow );
13439   ins_pc_relative(1);
13440   ins_alignment(4);
13441 %}
13442 




 251 // Note: 'double' and 'long long' have 32-bits alignment on x86.
 252 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) {
 253   // Use the expression (adr)&(~0xF) to provide 128-bits aligned address
 254   // of 128-bits operands for SSE instructions.
 255   jlong *operand = (jlong*)(((uintptr_t)adr)&((uintptr_t)(~0xF)));
 256   // Store the value to a 128-bits operand.
 257   operand[0] = lo;
 258   operand[1] = hi;
 259   return operand;
 260 }
 261 
 262 // Buffer for 128-bits masks used by SSE instructions.
 263 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment)
 264 
 265 // Static initialization during VM startup.
 266 static jlong *float_signmask_pool  = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF));
 267 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF));
 268 static jlong *float_signflip_pool  = double_quadword(&fp_signmask_pool[3*2], CONST64(0x8000000080000000), CONST64(0x8000000080000000));
 269 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], CONST64(0x8000000000000000), CONST64(0x8000000000000000));
 270 
 271 // Offset hacking within calls.
 272 static int pre_call_FPU_size() {
 273   if (Compile::current()->in_24_bit_fp_mode())
 274     return 6; // fldcw
 275   return 0;
 276 }
 277 
 278 static int preserve_SP_size() {
 279   return LP64_ONLY(1 +) 2;  // [rex,] op, rm(reg/reg)
 280 }
 281 
 282 // !!!!! Special hack to get all type of calls to specify the byte offset
 283 //       from the start of the call to the point where the return address
 284 //       will point.
 285 int MachCallStaticJavaNode::ret_addr_offset() {
 286   int offset = 5 + pre_call_FPU_size();  // 5 bytes from start of call to where return address points
 287   if (_method_handle_invoke)
 288     offset += preserve_SP_size();
 289   return offset;
 290 }
 291 
 292 int MachCallDynamicJavaNode::ret_addr_offset() {
 293   return 10 + pre_call_FPU_size();  // 10 bytes from start of call to where return address points
 294 }
 295 
 296 static int sizeof_FFree_Float_Stack_All = -1;
 297 
 298 int MachCallRuntimeNode::ret_addr_offset() {
 299   assert(sizeof_FFree_Float_Stack_All != -1, "must have been emitted already");
 300   return sizeof_FFree_Float_Stack_All + 5 + pre_call_FPU_size();
 301 }
 302 
 303 // Indicate if the safepoint node needs the polling page as an input.
 304 // Since x86 does have absolute addressing, it doesn't.
 305 bool SafePointNode::needs_polling_address_input() {
 306   return false;
 307 }
 308 
 309 //
 310 // Compute padding required for nodes which need alignment
 311 //
 312 
 313 // The address of the call instruction needs to be 4-byte aligned to
 314 // ensure that it does not span a cache line so that it can be patched.
 315 int CallStaticJavaDirectNode::compute_padding(int current_offset) const {
 316   current_offset += pre_call_FPU_size();  // skip fldcw, if any
 317   current_offset += 1;      // skip call opcode byte
 318   return round_to(current_offset, alignment_required()) - current_offset;
 319 }
 320 
 321 // The address of the call instruction needs to be 4-byte aligned to
 322 // ensure that it does not span a cache line so that it can be patched.
 323 int CallStaticJavaHandleNode::compute_padding(int current_offset) const {
 324   current_offset += pre_call_FPU_size();  // skip fldcw, if any
 325   current_offset += preserve_SP_size();   // skip mov rbp, rsp
 326   current_offset += 1;      // skip call opcode byte
 327   return round_to(current_offset, alignment_required()) - current_offset;
 328 }
 329 
 330 // The address of the call instruction needs to be 4-byte aligned to
 331 // ensure that it does not span a cache line so that it can be patched.
 332 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const {
 333   current_offset += pre_call_FPU_size();  // skip fldcw, if any

 334   current_offset += 5;      // skip MOV instruction
 335   current_offset += 1;      // skip call opcode byte
 336   return round_to(current_offset, alignment_required()) - current_offset;
 337 }
 338 
 339 #ifndef PRODUCT
 340 void MachBreakpointNode::format( PhaseRegAlloc *, outputStream* st ) const {
 341   st->print("INT3");
 342 }
 343 #endif
 344 
 345 // EMIT_RM()
 346 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) {
 347   unsigned char c = (unsigned char)((f1 << 6) | (f2 << 3) | f3);
 348   *(cbuf.code_end()) = c;
 349   cbuf.set_code_end(cbuf.code_end() + 1);
 350 }
 351 
 352 // EMIT_CC()
 353 void emit_cc(CodeBuffer &cbuf, int f1, int f2) {


1464   return EAX_REG_mask;
1465 }
1466 
1467 // Register for MODI projection of divmodI
1468 RegMask Matcher::modI_proj_mask() {
1469   return EDX_REG_mask;
1470 }
1471 
1472 // Register for DIVL projection of divmodL
1473 RegMask Matcher::divL_proj_mask() {
1474   ShouldNotReachHere();
1475   return RegMask();
1476 }
1477 
1478 // Register for MODL projection of divmodL
1479 RegMask Matcher::modL_proj_mask() {
1480   ShouldNotReachHere();
1481   return RegMask();
1482 }
1483 
1484 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
1485   return EBP_REG_mask;
1486 }
1487 
1488 %}
1489 
1490 //----------ENCODING BLOCK-----------------------------------------------------
1491 // This block specifies the encoding classes used by the compiler to output
1492 // byte streams.  Encoding classes generate functions which are called by
1493 // Machine Instruction Nodes in order to generate the bit encoding of the
1494 // instruction.  Operands specify their base encoding interface with the
1495 // interface keyword.  There are currently supported four interfaces,
1496 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER.  REG_INTER causes an
1497 // operand to generate a function which returns its register number when
1498 // queried.   CONST_INTER causes an operand to generate a function which
1499 // returns the value of the constant when queried.  MEMORY_INTER causes an
1500 // operand to generate four functions which return the Base Register, the
1501 // Index Register, the Scale Value, and the Offset Value of the operand when
1502 // queried.  COND_INTER causes an operand to generate six functions which
1503 // return the encoding code (ie - encoding bits for the instruction)
1504 // associated with each basic boolean condition for a conditional instruction.
1505 // Instructions specify two basic values for encoding.  They use the
1506 // ins_encode keyword to specify their encoding class (which must be one of
1507 // the class names specified in the encoding block), and they use the


1780         // likely that this function call could be removed by the
1781         // optimizer if the C function is a pure function.
1782         __ ffree(0);
1783       } else if (rt == T_FLOAT) {
1784         __ lea(rsp, Address(rsp, -4));
1785         __ fstp_s(Address(rsp, 0));
1786         __ movflt(xmm0, Address(rsp, 0));
1787         __ lea(rsp, Address(rsp,  4));
1788       } else if (rt == T_DOUBLE) {
1789         __ lea(rsp, Address(rsp, -8));
1790         __ fstp_d(Address(rsp, 0));
1791         __ movdbl(xmm0, Address(rsp, 0));
1792         __ lea(rsp, Address(rsp,  8));
1793       }
1794     }
1795   %}
1796 
1797 
1798   enc_class pre_call_FPU %{
1799     // If method sets FPU control word restore it here
1800     debug_only(int off0 = cbuf.code_size());
1801     if( Compile::current()->in_24_bit_fp_mode() ) {
1802       MacroAssembler masm(&cbuf);
1803       masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
1804     }
1805     debug_only(int off1 = cbuf.code_size());
1806     assert(off1 - off0 == pre_call_FPU_size(), "correct size prediction");
1807   %}
1808 
1809   enc_class post_call_FPU %{
1810     // If method sets FPU control word do it here also
1811     if( Compile::current()->in_24_bit_fp_mode() ) {
1812       MacroAssembler masm(&cbuf);
1813       masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
1814     }
1815   %}
1816 
1817   enc_class preserve_SP %{
1818     debug_only(int off0 = cbuf.code_size());
1819     MacroAssembler _masm(&cbuf);
1820     // RBP is preserved across all calls, even compiled calls.
1821     // Use it to preserve RSP in places where the callee might change the SP.
1822     __ movptr(rbp, rsp);
1823     debug_only(int off1 = cbuf.code_size());
1824     assert(off1 - off0 == preserve_SP_size(), "correct size prediction");
1825   %}
1826 
1827   enc_class restore_SP %{
1828     MacroAssembler _masm(&cbuf);
1829     __ movptr(rsp, rbp);
1830   %}
1831 
1832   enc_class Java_Static_Call (method meth) %{    // JAVA STATIC CALL
1833     // CALL to fixup routine.  Fixup routine uses ScopeDesc info to determine
1834     // who we intended to call.
1835     cbuf.set_inst_mark();
1836     $$$emit8$primary;
1837     if ( !_method ) {
1838       emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.code_end()) - 4),
1839                      runtime_call_Relocation::spec(), RELOC_IMM32 );
1840     } else if(_optimized_virtual) {
1841       emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.code_end()) - 4),
1842                      opt_virtual_call_Relocation::spec(), RELOC_IMM32 );
1843     } else {
1844       emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.code_end()) - 4),
1845                      static_call_Relocation::spec(), RELOC_IMM32 );
1846     }
1847     if( _method ) {  // Emit stub for static call
1848       emit_java_to_interp(cbuf);
1849     }
1850   %}
1851 


13432 %}
13433 
13434 
13435 instruct cmovXX_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regX dst, regX src) %{
13436   predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
13437   match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
13438   ins_cost(200);
13439   expand %{
13440     fcmovX_regS(cmp,flags,dst,src);
13441   %}
13442 %}
13443 
13444 
13445 // ============================================================================
13446 // Procedure Call/Return Instructions
13447 // Call Java Static Instruction
13448 // Note: If this code changes, the corresponding ret_addr_offset() and
13449 //       compute_padding() functions will have to be adjusted.
13450 instruct CallStaticJavaDirect(method meth) %{
13451   match(CallStaticJava);
13452   predicate(! ((CallStaticJavaNode*)n)->is_method_handle_invoke());
13453   effect(USE meth);
13454 
13455   ins_cost(300);
13456   format %{ "CALL,static " %}
13457   opcode(0xE8); /* E8 cd */
13458   ins_encode( pre_call_FPU,
13459               Java_Static_Call( meth ),
13460               call_epilog,
13461               post_call_FPU );
13462   ins_pipe( pipe_slow );
13463   ins_pc_relative(1);
13464   ins_alignment(4);
13465 %}
13466 
13467 // Call Java Static Instruction (method handle version)
13468 // Note: If this code changes, the corresponding ret_addr_offset() and
13469 //       compute_padding() functions will have to be adjusted.
13470 instruct CallStaticJavaHandle(method meth, eBPRegP ebp) %{
13471   match(CallStaticJava);
13472   predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke());
13473   effect(USE meth);
13474   // EBP is saved by all callees (for interpreter stack correction).
13475   // We use it here for a similar purpose, in {preserve,restore}_SP.
13476 
13477   ins_cost(300);
13478   format %{ "CALL,static MethodHandle " %}
13479   opcode(0xE8); /* E8 cd */
13480   ins_encode( pre_call_FPU,
13481               preserve_SP,
13482               Java_Static_Call( meth ),
13483               restore_SP,
13484               call_epilog,
13485               post_call_FPU );
13486   ins_pipe( pipe_slow );
13487   ins_pc_relative(1);
13488   ins_alignment(4);
13489 %}
13490 
13491 // Call Java Dynamic Instruction
13492 // Note: If this code changes, the corresponding ret_addr_offset() and
13493 //       compute_padding() functions will have to be adjusted.
13494 instruct CallDynamicJavaDirect(method meth) %{
13495   match(CallDynamicJava);
13496   effect(USE meth);
13497 
13498   ins_cost(300);
13499   format %{ "MOV    EAX,(oop)-1\n\t"
13500             "CALL,dynamic" %}
13501   opcode(0xE8); /* E8 cd */
13502   ins_encode( pre_call_FPU,
13503               Java_Dynamic_Call( meth ),
13504               call_epilog,
13505               post_call_FPU );
13506   ins_pipe( pipe_slow );
13507   ins_pc_relative(1);
13508   ins_alignment(4);
13509 %}
13510 


src/cpu/x86/vm/x86_32.ad
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