src/cpu/sparc/vm/assembler_sparc.hpp
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6829193 Cdiff src/cpu/sparc/vm/assembler_sparc.hpp
src/cpu/sparc/vm/assembler_sparc.hpp
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*** 1,7 ****
/*
! * Copyright 1997-2009 Sun Microsystems, Inc. All Rights Reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 only, as
* published by the Free Software Foundation.
--- 1,7 ----
/*
! * Copyright 1997-2010 Sun Microsystems, Inc. All Rights Reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 only, as
* published by the Free Software Foundation.
*** 1387,1396 ****
--- 1387,1397 ----
void and3( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(and_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
void andcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(and_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
void andcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(and_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
void andn( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(andn_op3 ) | rs1(s1) | rs2(s2) ); }
void andn( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(andn_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
+ void andn( Register s1, RegisterOrConstant s2, Register d, int offset = 0);
void andncc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(andn_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
void andncc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(andn_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
void or3( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(or_op3 ) | rs1(s1) | rs2(s2) ); }
void or3( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(or_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
void orcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(or_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
*** 2027,2065 ****
// ByteSize is only a class when ASSERT is defined, otherwise it's an int.
inline void ld_ptr(Register s1, ByteSize simm13a, Register d);
inline void st_ptr(Register d, Register s1, ByteSize simm13a);
#endif
! // ld_long will perform ld for 32 bit VM's and ldx for 64 bit VM's
! // st_long will perform st for 32 bit VM's and stx for 64 bit VM's
inline void ld_long(Register s1, Register s2, Register d);
inline void ld_long(Register s1, int simm13a, Register d);
inline void ld_long(Register s1, RegisterOrConstant s2, Register d);
inline void ld_long(const Address& a, Register d, int offset = 0);
inline void st_long(Register d, Register s1, Register s2);
inline void st_long(Register d, Register s1, int simm13a);
inline void st_long(Register d, Register s1, RegisterOrConstant s2);
inline void st_long(Register d, const Address& a, int offset = 0);
// Helpers for address formation.
! // They update the dest in place, whether it is a register or constant.
! // They emit no code at all if src is a constant zero.
! // If dest is a constant and src is a register, the temp argument
! // is required, and becomes the result.
! // If dest is a register and src is a non-simm13 constant,
! // the temp argument is required, and is used to materialize the constant.
! void regcon_inc_ptr( RegisterOrConstant& dest, RegisterOrConstant src,
! Register temp = noreg );
! void regcon_sll_ptr( RegisterOrConstant& dest, RegisterOrConstant src,
! Register temp = noreg );
!
! RegisterOrConstant ensure_simm13_or_reg(RegisterOrConstant roc, Register Rtemp) {
! guarantee(Rtemp != noreg, "constant offset overflow");
! if (is_simm13(roc.constant_or_zero()))
! return roc; // register or short constant
! set(roc.as_constant(), Rtemp);
! return RegisterOrConstant(Rtemp);
}
// --------------------------------------------------
public:
--- 2028,2062 ----
// ByteSize is only a class when ASSERT is defined, otherwise it's an int.
inline void ld_ptr(Register s1, ByteSize simm13a, Register d);
inline void st_ptr(Register d, Register s1, ByteSize simm13a);
#endif
! // ld_long will perform ldd for 32 bit VM's and ldx for 64 bit VM's
! // st_long will perform std for 32 bit VM's and stx for 64 bit VM's
inline void ld_long(Register s1, Register s2, Register d);
inline void ld_long(Register s1, int simm13a, Register d);
inline void ld_long(Register s1, RegisterOrConstant s2, Register d);
inline void ld_long(const Address& a, Register d, int offset = 0);
inline void st_long(Register d, Register s1, Register s2);
inline void st_long(Register d, Register s1, int simm13a);
inline void st_long(Register d, Register s1, RegisterOrConstant s2);
inline void st_long(Register d, const Address& a, int offset = 0);
// Helpers for address formation.
! // - They emit only a move if s2 is a constant zero.
! // - If dest is a constant the temp argument is required and becomes the result.
! // - If dest is a register and s2 is a non-simm13 constant, the temp argument is required and is used to materialize the constant.
! void regcon_andn_ptr(RegisterOrConstant s1, RegisterOrConstant s2, RegisterOrConstant& d, Register temp = noreg);
! void regcon_inc_ptr( RegisterOrConstant s1, RegisterOrConstant s2, RegisterOrConstant& d, Register temp = noreg);
! void regcon_sll_ptr( RegisterOrConstant s1, RegisterOrConstant s2, RegisterOrConstant& d, Register temp = noreg);
!
! RegisterOrConstant ensure_simm13_or_reg(RegisterOrConstant src, Register temp) {
! if (is_simm13(src.constant_or_zero()))
! return src; // register or short constant
! guarantee(temp != noreg, "constant offset overflow");
! set(src.as_constant(), temp);
! return temp;
}
// --------------------------------------------------
public:
*** 2304,2313 ****
--- 2301,2313 ----
#ifdef _LP64
void lcmp( Register Ra, Register Rb, Register Rresult);
#endif
+ // Loading values by size and signed-ness
+ void load_sized_value(Address src, Register dst, int size_in_bytes, bool is_signed);
+
void float_cmp( bool is_float, int unordered_result,
FloatRegister Fa, FloatRegister Fb,
Register Rresult);
void fneg( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d);
*** 2422,2437 ****
// method handles (JSR 292)
void check_method_handle_type(Register mtype_reg, Register mh_reg,
Register temp_reg,
Label& wrong_method_type);
! void jump_to_method_handle_entry(Register mh_reg, Register temp_reg);
// offset relative to Gargs of argument at tos[arg_slot].
// (arg_slot == 0 means the last argument, not the first).
RegisterOrConstant argument_offset(RegisterOrConstant arg_slot,
int extra_slot_offset = 0);
!
// Stack overflow checking
// Note: this clobbers G3_scratch
void bang_stack_with_offset(int offset) {
--- 2422,2441 ----
// method handles (JSR 292)
void check_method_handle_type(Register mtype_reg, Register mh_reg,
Register temp_reg,
Label& wrong_method_type);
! void load_method_handle_vmslots(Register vmslots_reg, Register mh_reg,
! Register temp_reg);
! void jump_to_method_handle_entry(Register mh_reg, Register temp_reg, bool emit_delayed_nop = true);
// offset relative to Gargs of argument at tos[arg_slot].
// (arg_slot == 0 means the last argument, not the first).
RegisterOrConstant argument_offset(RegisterOrConstant arg_slot,
int extra_slot_offset = 0);
! // Address of Gargs and argument_offset.
! Address argument_address(RegisterOrConstant arg_slot,
! int extra_slot_offset = 0);
// Stack overflow checking
// Note: this clobbers G3_scratch
void bang_stack_with_offset(int offset) {
src/cpu/sparc/vm/assembler_sparc.hpp
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