1 /*
2 * Copyright 1997-2009 Sun Microsystems, Inc. All Rights Reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
20 * CA 95054 USA or visit www.sun.com if you need additional information or
21 * have any questions.
22 *
1372 void ldda( Register s1, int simm13a, Register d ) { v9_dep(); emit_long( op(ldst_op) | rd(d) | op3(ldd_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1373
1374 // pp 179
1375
1376 inline void ldstub( Register s1, Register s2, Register d );
1377 inline void ldstub( Register s1, int simm13a, Register d);
1378
1379 // pp 180
1380
1381 void ldstuba( Register s1, Register s2, int ia, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(ldstub_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1382 void ldstuba( Register s1, int simm13a, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(ldstub_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1383
1384 // pp 181
1385
1386 void and3( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(and_op3 ) | rs1(s1) | rs2(s2) ); }
1387 void and3( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(and_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1388 void andcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(and_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
1389 void andcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(and_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1390 void andn( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(andn_op3 ) | rs1(s1) | rs2(s2) ); }
1391 void andn( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(andn_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1392 void andncc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(andn_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
1393 void andncc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(andn_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1394 void or3( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(or_op3 ) | rs1(s1) | rs2(s2) ); }
1395 void or3( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(or_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1396 void orcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(or_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
1397 void orcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(or_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1398 void orn( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(orn_op3) | rs1(s1) | rs2(s2) ); }
1399 void orn( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(orn_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1400 void orncc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(orn_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
1401 void orncc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(orn_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1402 void xor3( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xor_op3 ) | rs1(s1) | rs2(s2) ); }
1403 void xor3( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xor_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1404 void xorcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xor_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
1405 void xorcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xor_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1406 void xnor( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xnor_op3 ) | rs1(s1) | rs2(s2) ); }
1407 void xnor( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xnor_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1408 void xnorcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xnor_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
1409 void xnorcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xnor_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1410
1411 // pp 183
2012 // --------------------------------------------------
2013
2014 // Functions for isolating 64 bit loads for LP64
2015 // ld_ptr will perform ld for 32 bit VM's and ldx for 64 bit VM's
2016 // st_ptr will perform st for 32 bit VM's and stx for 64 bit VM's
2017 inline void ld_ptr(Register s1, Register s2, Register d);
2018 inline void ld_ptr(Register s1, int simm13a, Register d);
2019 inline void ld_ptr(Register s1, RegisterOrConstant s2, Register d);
2020 inline void ld_ptr(const Address& a, Register d, int offset = 0);
2021 inline void st_ptr(Register d, Register s1, Register s2);
2022 inline void st_ptr(Register d, Register s1, int simm13a);
2023 inline void st_ptr(Register d, Register s1, RegisterOrConstant s2);
2024 inline void st_ptr(Register d, const Address& a, int offset = 0);
2025
2026 #ifdef ASSERT
2027 // ByteSize is only a class when ASSERT is defined, otherwise it's an int.
2028 inline void ld_ptr(Register s1, ByteSize simm13a, Register d);
2029 inline void st_ptr(Register d, Register s1, ByteSize simm13a);
2030 #endif
2031
2032 // ld_long will perform ld for 32 bit VM's and ldx for 64 bit VM's
2033 // st_long will perform st for 32 bit VM's and stx for 64 bit VM's
2034 inline void ld_long(Register s1, Register s2, Register d);
2035 inline void ld_long(Register s1, int simm13a, Register d);
2036 inline void ld_long(Register s1, RegisterOrConstant s2, Register d);
2037 inline void ld_long(const Address& a, Register d, int offset = 0);
2038 inline void st_long(Register d, Register s1, Register s2);
2039 inline void st_long(Register d, Register s1, int simm13a);
2040 inline void st_long(Register d, Register s1, RegisterOrConstant s2);
2041 inline void st_long(Register d, const Address& a, int offset = 0);
2042
2043 // Helpers for address formation.
2044 // They update the dest in place, whether it is a register or constant.
2045 // They emit no code at all if src is a constant zero.
2046 // If dest is a constant and src is a register, the temp argument
2047 // is required, and becomes the result.
2048 // If dest is a register and src is a non-simm13 constant,
2049 // the temp argument is required, and is used to materialize the constant.
2050 void regcon_inc_ptr( RegisterOrConstant& dest, RegisterOrConstant src,
2051 Register temp = noreg );
2052 void regcon_sll_ptr( RegisterOrConstant& dest, RegisterOrConstant src,
2053 Register temp = noreg );
2054
2055 RegisterOrConstant ensure_simm13_or_reg(RegisterOrConstant roc, Register Rtemp) {
2056 guarantee(Rtemp != noreg, "constant offset overflow");
2057 if (is_simm13(roc.constant_or_zero()))
2058 return roc; // register or short constant
2059 set(roc.as_constant(), Rtemp);
2060 return RegisterOrConstant(Rtemp);
2061 }
2062
2063 // --------------------------------------------------
2064
2065 public:
2066 // traps as per trap.h (SPARC ABI?)
2067
2068 void breakpoint_trap();
2069 void breakpoint_trap(Condition c, CC cc = icc);
2070 void flush_windows_trap();
2071 void clean_windows_trap();
2072 void get_psr_trap();
2073 void set_psr_trap();
2074
2075 // V8/V9 flush_windows
2076 void flush_windows();
2077
2078 // Support for serializing memory accesses between threads
2079 void serialize_memory(Register thread, Register tmp1, Register tmp2);
2080
2289
2290 void lcmp( Register Ra_hi, Register Ra_low,
2291 Register Rb_hi, Register Rb_low,
2292 Register Rresult);
2293
2294 void lneg( Register Rhi, Register Rlow );
2295
2296 void lshl( Register Rin_high, Register Rin_low, Register Rcount,
2297 Register Rout_high, Register Rout_low, Register Rtemp );
2298
2299 void lshr( Register Rin_high, Register Rin_low, Register Rcount,
2300 Register Rout_high, Register Rout_low, Register Rtemp );
2301
2302 void lushr( Register Rin_high, Register Rin_low, Register Rcount,
2303 Register Rout_high, Register Rout_low, Register Rtemp );
2304
2305 #ifdef _LP64
2306 void lcmp( Register Ra, Register Rb, Register Rresult);
2307 #endif
2308
2309 void float_cmp( bool is_float, int unordered_result,
2310 FloatRegister Fa, FloatRegister Fb,
2311 Register Rresult);
2312
2313 void fneg( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d);
2314 void fneg( FloatRegisterImpl::Width w, FloatRegister sd ) { Assembler::fneg(w, sd); }
2315 void fmov( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d);
2316 void fabs( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d);
2317
2318 void save_all_globals_into_locals();
2319 void restore_globals_from_locals();
2320
2321 void casx_under_lock(Register top_ptr_reg, Register top_reg, Register ptr_reg,
2322 address lock_addr=0, bool use_call_vm=false);
2323 void cas_under_lock(Register top_ptr_reg, Register top_reg, Register ptr_reg,
2324 address lock_addr=0, bool use_call_vm=false);
2325 void casn (Register addr_reg, Register cmp_reg, Register set_reg) ;
2326
2327 // These set the icc condition code to equal if the lock succeeded
2328 // and notEqual if it failed and requires a slow case
2407 Register super_klass,
2408 Register temp_reg,
2409 Register temp2_reg,
2410 Register temp3_reg,
2411 Register temp4_reg,
2412 Label* L_success,
2413 Label* L_failure);
2414
2415 // Simplified, combined version, good for typical uses.
2416 // Falls through on failure.
2417 void check_klass_subtype(Register sub_klass,
2418 Register super_klass,
2419 Register temp_reg,
2420 Register temp2_reg,
2421 Label& L_success);
2422
2423 // method handles (JSR 292)
2424 void check_method_handle_type(Register mtype_reg, Register mh_reg,
2425 Register temp_reg,
2426 Label& wrong_method_type);
2427 void jump_to_method_handle_entry(Register mh_reg, Register temp_reg);
2428 // offset relative to Gargs of argument at tos[arg_slot].
2429 // (arg_slot == 0 means the last argument, not the first).
2430 RegisterOrConstant argument_offset(RegisterOrConstant arg_slot,
2431 int extra_slot_offset = 0);
2432
2433
2434 // Stack overflow checking
2435
2436 // Note: this clobbers G3_scratch
2437 void bang_stack_with_offset(int offset) {
2438 // stack grows down, caller passes positive offset
2439 assert(offset > 0, "must bang with negative offset");
2440 set((-offset)+STACK_BIAS, G3_scratch);
2441 st(G0, SP, G3_scratch);
2442 }
2443
2444 // Writes to stack successive pages until offset reached to check for
2445 // stack overflow + shadow pages. Clobbers tsp and scratch registers.
2446 void bang_stack_size(Register Rsize, Register Rtsp, Register Rscratch);
2447
2448 virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr, Register tmp, int offset);
2449
2450 void verify_tlab();
2451
2452 Condition negate_condition(Condition cond);
|
1 /*
2 * Copyright 1997-2010 Sun Microsystems, Inc. All Rights Reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
20 * CA 95054 USA or visit www.sun.com if you need additional information or
21 * have any questions.
22 *
1372 void ldda( Register s1, int simm13a, Register d ) { v9_dep(); emit_long( op(ldst_op) | rd(d) | op3(ldd_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1373
1374 // pp 179
1375
1376 inline void ldstub( Register s1, Register s2, Register d );
1377 inline void ldstub( Register s1, int simm13a, Register d);
1378
1379 // pp 180
1380
1381 void ldstuba( Register s1, Register s2, int ia, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(ldstub_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1382 void ldstuba( Register s1, int simm13a, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(ldstub_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1383
1384 // pp 181
1385
1386 void and3( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(and_op3 ) | rs1(s1) | rs2(s2) ); }
1387 void and3( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(and_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1388 void andcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(and_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
1389 void andcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(and_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1390 void andn( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(andn_op3 ) | rs1(s1) | rs2(s2) ); }
1391 void andn( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(andn_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1392 void andn( Register s1, RegisterOrConstant s2, Register d, int offset = 0);
1393 void andncc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(andn_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
1394 void andncc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(andn_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1395 void or3( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(or_op3 ) | rs1(s1) | rs2(s2) ); }
1396 void or3( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(or_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1397 void orcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(or_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
1398 void orcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(or_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1399 void orn( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(orn_op3) | rs1(s1) | rs2(s2) ); }
1400 void orn( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(orn_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1401 void orncc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(orn_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
1402 void orncc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(orn_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1403 void xor3( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xor_op3 ) | rs1(s1) | rs2(s2) ); }
1404 void xor3( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xor_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1405 void xorcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xor_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
1406 void xorcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xor_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1407 void xnor( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xnor_op3 ) | rs1(s1) | rs2(s2) ); }
1408 void xnor( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xnor_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1409 void xnorcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xnor_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
1410 void xnorcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xnor_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1411
1412 // pp 183
2013 // --------------------------------------------------
2014
2015 // Functions for isolating 64 bit loads for LP64
2016 // ld_ptr will perform ld for 32 bit VM's and ldx for 64 bit VM's
2017 // st_ptr will perform st for 32 bit VM's and stx for 64 bit VM's
2018 inline void ld_ptr(Register s1, Register s2, Register d);
2019 inline void ld_ptr(Register s1, int simm13a, Register d);
2020 inline void ld_ptr(Register s1, RegisterOrConstant s2, Register d);
2021 inline void ld_ptr(const Address& a, Register d, int offset = 0);
2022 inline void st_ptr(Register d, Register s1, Register s2);
2023 inline void st_ptr(Register d, Register s1, int simm13a);
2024 inline void st_ptr(Register d, Register s1, RegisterOrConstant s2);
2025 inline void st_ptr(Register d, const Address& a, int offset = 0);
2026
2027 #ifdef ASSERT
2028 // ByteSize is only a class when ASSERT is defined, otherwise it's an int.
2029 inline void ld_ptr(Register s1, ByteSize simm13a, Register d);
2030 inline void st_ptr(Register d, Register s1, ByteSize simm13a);
2031 #endif
2032
2033 // ld_long will perform ldd for 32 bit VM's and ldx for 64 bit VM's
2034 // st_long will perform std for 32 bit VM's and stx for 64 bit VM's
2035 inline void ld_long(Register s1, Register s2, Register d);
2036 inline void ld_long(Register s1, int simm13a, Register d);
2037 inline void ld_long(Register s1, RegisterOrConstant s2, Register d);
2038 inline void ld_long(const Address& a, Register d, int offset = 0);
2039 inline void st_long(Register d, Register s1, Register s2);
2040 inline void st_long(Register d, Register s1, int simm13a);
2041 inline void st_long(Register d, Register s1, RegisterOrConstant s2);
2042 inline void st_long(Register d, const Address& a, int offset = 0);
2043
2044 // Helpers for address formation.
2045 // - They emit only a move if s2 is a constant zero.
2046 // - If dest is a constant and either s1 or s2 is a register, the temp argument is required and becomes the result.
2047 // - If dest is a register and either s1 or s2 is a non-simm13 constant, the temp argument is required and used to materialize the constant.
2048 RegisterOrConstant regcon_andn_ptr(RegisterOrConstant s1, RegisterOrConstant s2, RegisterOrConstant d, Register temp = noreg);
2049 RegisterOrConstant regcon_inc_ptr( RegisterOrConstant s1, RegisterOrConstant s2, RegisterOrConstant d, Register temp = noreg);
2050 RegisterOrConstant regcon_sll_ptr( RegisterOrConstant s1, RegisterOrConstant s2, RegisterOrConstant d, Register temp = noreg);
2051
2052 RegisterOrConstant ensure_simm13_or_reg(RegisterOrConstant src, Register temp) {
2053 if (is_simm13(src.constant_or_zero()))
2054 return src; // register or short constant
2055 guarantee(temp != noreg, "constant offset overflow");
2056 set(src.as_constant(), temp);
2057 return temp;
2058 }
2059
2060 // --------------------------------------------------
2061
2062 public:
2063 // traps as per trap.h (SPARC ABI?)
2064
2065 void breakpoint_trap();
2066 void breakpoint_trap(Condition c, CC cc = icc);
2067 void flush_windows_trap();
2068 void clean_windows_trap();
2069 void get_psr_trap();
2070 void set_psr_trap();
2071
2072 // V8/V9 flush_windows
2073 void flush_windows();
2074
2075 // Support for serializing memory accesses between threads
2076 void serialize_memory(Register thread, Register tmp1, Register tmp2);
2077
2286
2287 void lcmp( Register Ra_hi, Register Ra_low,
2288 Register Rb_hi, Register Rb_low,
2289 Register Rresult);
2290
2291 void lneg( Register Rhi, Register Rlow );
2292
2293 void lshl( Register Rin_high, Register Rin_low, Register Rcount,
2294 Register Rout_high, Register Rout_low, Register Rtemp );
2295
2296 void lshr( Register Rin_high, Register Rin_low, Register Rcount,
2297 Register Rout_high, Register Rout_low, Register Rtemp );
2298
2299 void lushr( Register Rin_high, Register Rin_low, Register Rcount,
2300 Register Rout_high, Register Rout_low, Register Rtemp );
2301
2302 #ifdef _LP64
2303 void lcmp( Register Ra, Register Rb, Register Rresult);
2304 #endif
2305
2306 // Loading values by size and signed-ness
2307 void load_sized_value(Address src, Register dst, int size_in_bytes, bool is_signed);
2308
2309 void float_cmp( bool is_float, int unordered_result,
2310 FloatRegister Fa, FloatRegister Fb,
2311 Register Rresult);
2312
2313 void fneg( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d);
2314 void fneg( FloatRegisterImpl::Width w, FloatRegister sd ) { Assembler::fneg(w, sd); }
2315 void fmov( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d);
2316 void fabs( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d);
2317
2318 void save_all_globals_into_locals();
2319 void restore_globals_from_locals();
2320
2321 void casx_under_lock(Register top_ptr_reg, Register top_reg, Register ptr_reg,
2322 address lock_addr=0, bool use_call_vm=false);
2323 void cas_under_lock(Register top_ptr_reg, Register top_reg, Register ptr_reg,
2324 address lock_addr=0, bool use_call_vm=false);
2325 void casn (Register addr_reg, Register cmp_reg, Register set_reg) ;
2326
2327 // These set the icc condition code to equal if the lock succeeded
2328 // and notEqual if it failed and requires a slow case
2407 Register super_klass,
2408 Register temp_reg,
2409 Register temp2_reg,
2410 Register temp3_reg,
2411 Register temp4_reg,
2412 Label* L_success,
2413 Label* L_failure);
2414
2415 // Simplified, combined version, good for typical uses.
2416 // Falls through on failure.
2417 void check_klass_subtype(Register sub_klass,
2418 Register super_klass,
2419 Register temp_reg,
2420 Register temp2_reg,
2421 Label& L_success);
2422
2423 // method handles (JSR 292)
2424 void check_method_handle_type(Register mtype_reg, Register mh_reg,
2425 Register temp_reg,
2426 Label& wrong_method_type);
2427 void load_method_handle_vmslots(Register vmslots_reg, Register mh_reg,
2428 Register temp_reg);
2429 void jump_to_method_handle_entry(Register mh_reg, Register temp_reg, bool emit_delayed_nop = true);
2430 // offset relative to Gargs of argument at tos[arg_slot].
2431 // (arg_slot == 0 means the last argument, not the first).
2432 RegisterOrConstant argument_offset(RegisterOrConstant arg_slot,
2433 int extra_slot_offset = 0);
2434 // Address of Gargs and argument_offset.
2435 Address argument_address(RegisterOrConstant arg_slot,
2436 int extra_slot_offset = 0);
2437
2438 // Stack overflow checking
2439
2440 // Note: this clobbers G3_scratch
2441 void bang_stack_with_offset(int offset) {
2442 // stack grows down, caller passes positive offset
2443 assert(offset > 0, "must bang with negative offset");
2444 set((-offset)+STACK_BIAS, G3_scratch);
2445 st(G0, SP, G3_scratch);
2446 }
2447
2448 // Writes to stack successive pages until offset reached to check for
2449 // stack overflow + shadow pages. Clobbers tsp and scratch registers.
2450 void bang_stack_size(Register Rsize, Register Rtsp, Register Rscratch);
2451
2452 virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr, Register tmp, int offset);
2453
2454 void verify_tlab();
2455
2456 Condition negate_condition(Condition cond);
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