--- old/src/cpu/sparc/vm/assembler_sparc.hpp
          +++ new/src/cpu/sparc/vm/assembler_sparc.hpp
   1    1  /*
   2      - * Copyright 1997-2009 Sun Microsystems, Inc.  All Rights Reserved.
        2 + * Copyright 1997-2010 Sun Microsystems, Inc.  All Rights Reserved.
   3    3   * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4    4   *
   5    5   * This code is free software; you can redistribute it and/or modify it
   6    6   * under the terms of the GNU General Public License version 2 only, as
   7    7   * published by the Free Software Foundation.
   8    8   *
   9    9   * This code is distributed in the hope that it will be useful, but WITHOUT
  10   10   * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11   11   * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12   12   * version 2 for more details (a copy is included in the LICENSE file that

  13   13   * accompanied this code).
  14   14   *
  15   15   * You should have received a copy of the GNU General Public License version
  16   16   * 2 along with this work; if not, write to the Free Software Foundation,
  17   17   * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18   18   *
  19   19   * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
  20   20   * CA 95054 USA or visit www.sun.com if you need additional information or
  21   21   * have any questions.
  22   22   *
  23   23   */
  24   24  
  25   25  class BiasedLockingCounters;
  26   26  
  27   27  // <sys/trap.h> promises that the system will not use traps 16-31
  28   28  #define ST_RESERVED_FOR_USER_0 0x10
  29   29  
  30   30  /* Written: David Ungar 4/19/97 */
  31   31  
  32   32  // Contains all the definitions needed for sparc assembly code generation.
  33   33  
  34   34  // Register aliases for parts of the system:
  35   35  
  36   36  // 64 bit values can be kept in g1-g5, o1-o5 and o7 and all 64 bits are safe
  37   37  // across context switches in V8+ ABI.  Of course, there are no 64 bit regs
  38   38  // in V8 ABI. All 64 bits are preserved in V9 ABI for all registers.
  39   39  
  40   40  // g2-g4 are scratch registers called "application globals".  Their
  41   41  // meaning is reserved to the "compilation system"--which means us!
  42   42  // They are are not supposed to be touched by ordinary C code, although
  43   43  // highly-optimized C code might steal them for temps.  They are safe
  44   44  // across thread switches, and the ABI requires that they be safe
  45   45  // across function calls.
  46   46  //
  47   47  // g1 and g3 are touched by more modules.  V8 allows g1 to be clobbered
  48   48  // across func calls, and V8+ also allows g5 to be clobbered across
  49   49  // func calls.  Also, g1 and g5 can get touched while doing shared
  50   50  // library loading.
  51   51  //
  52   52  // We must not touch g7 (it is the thread-self register) and g6 is
  53   53  // reserved for certain tools.  g0, of course, is always zero.
  54   54  //
  55   55  // (Sources:  SunSoft Compilers Group, thread library engineers.)
  56   56  
  57   57  // %%%% The interpreter should be revisited to reduce global scratch regs.
  58   58  
  59   59  // This global always holds the current JavaThread pointer:
  60   60  
  61   61  REGISTER_DECLARATION(Register, G2_thread , G2);
  62   62  REGISTER_DECLARATION(Register, G6_heapbase , G6);
  63   63  
  64   64  // The following globals are part of the Java calling convention:
  65   65  
  66   66  REGISTER_DECLARATION(Register, G5_method             , G5);
  67   67  REGISTER_DECLARATION(Register, G5_megamorphic_method , G5_method);
  68   68  REGISTER_DECLARATION(Register, G5_inline_cache_reg   , G5_method);
  69   69  
  70   70  // The following globals are used for the new C1 & interpreter calling convention:
  71   71  REGISTER_DECLARATION(Register, Gargs        , G4); // pointing to the last argument
  72   72  
  73   73  // This local is used to preserve G2_thread in the interpreter and in stubs:
  74   74  REGISTER_DECLARATION(Register, L7_thread_cache , L7);
  75   75  
  76   76  // These globals are used as scratch registers in the interpreter:
  77   77  
  78   78  REGISTER_DECLARATION(Register, Gframe_size   , G1); // SAME REG as G1_scratch
  79   79  REGISTER_DECLARATION(Register, G1_scratch    , G1); // also SAME
  80   80  REGISTER_DECLARATION(Register, G3_scratch    , G3);
  81   81  REGISTER_DECLARATION(Register, G4_scratch    , G4);
  82   82  
  83   83  // These globals are used as short-lived scratch registers in the compiler:
  84   84  
  85   85  REGISTER_DECLARATION(Register, Gtemp  , G5);
  86   86  
  87   87  // JSR 292 fixed register usages:
  88   88  REGISTER_DECLARATION(Register, G5_method_type        , G5);
  89   89  REGISTER_DECLARATION(Register, G3_method_handle      , G3);
  90   90  
  91   91  // The compiler requires that G5_megamorphic_method is G5_inline_cache_klass,
  92   92  // because a single patchable "set" instruction (NativeMovConstReg,
  93   93  // or NativeMovConstPatching for compiler1) instruction
  94   94  // serves to set up either quantity, depending on whether the compiled
  95   95  // call site is an inline cache or is megamorphic.  See the function
  96   96  // CompiledIC::set_to_megamorphic.
  97   97  //
  98   98  // If a inline cache targets an interpreted method, then the
  99   99  // G5 register will be used twice during the call.  First,
 100  100  // the call site will be patched to load a compiledICHolder
 101  101  // into G5. (This is an ordered pair of ic_klass, method.)
 102  102  // The c2i adapter will first check the ic_klass, then load
 103  103  // G5_method with the method part of the pair just before
 104  104  // jumping into the interpreter.
 105  105  //
 106  106  // Note that G5_method is only the method-self for the interpreter,
 107  107  // and is logically unrelated to G5_megamorphic_method.
 108  108  //
 109  109  // Invariants on G2_thread (the JavaThread pointer):
 110  110  //  - it should not be used for any other purpose anywhere
 111  111  //  - it must be re-initialized by StubRoutines::call_stub()
 112  112  //  - it must be preserved around every use of call_VM
 113  113  
 114  114  // We can consider using g2/g3/g4 to cache more values than the
 115  115  // JavaThread, such as the card-marking base or perhaps pointers into
 116  116  // Eden.  It's something of a waste to use them as scratch temporaries,
 117  117  // since they are not supposed to be volatile.  (Of course, if we find
 118  118  // that Java doesn't benefit from application globals, then we can just
 119  119  // use them as ordinary temporaries.)
 120  120  //
 121  121  // Since g1 and g5 (and/or g6) are the volatile (caller-save) registers,
 122  122  // it makes sense to use them routinely for procedure linkage,
 123  123  // whenever the On registers are not applicable.  Examples:  G5_method,
 124  124  // G5_inline_cache_klass, and a double handful of miscellaneous compiler
 125  125  // stubs.  This means that compiler stubs, etc., should be kept to a
 126  126  // maximum of two or three G-register arguments.
 127  127  
 128  128  
 129  129  // stub frames
 130  130  
 131  131  REGISTER_DECLARATION(Register, Lentry_args      , L0); // pointer to args passed to callee (interpreter) not stub itself
 132  132  
 133  133  // Interpreter frames
 134  134  
 135  135  #ifdef CC_INTERP
 136  136  REGISTER_DECLARATION(Register, Lstate           , L0); // interpreter state object pointer
 137  137  REGISTER_DECLARATION(Register, L1_scratch       , L1); // scratch
 138  138  REGISTER_DECLARATION(Register, Lmirror          , L1); // mirror (for native methods only)
 139  139  REGISTER_DECLARATION(Register, L2_scratch       , L2);
 140  140  REGISTER_DECLARATION(Register, L3_scratch       , L3);
 141  141  REGISTER_DECLARATION(Register, L4_scratch       , L4);
 142  142  REGISTER_DECLARATION(Register, Lscratch         , L5); // C1 uses
 143  143  REGISTER_DECLARATION(Register, Lscratch2        , L6); // C1 uses
 144  144  REGISTER_DECLARATION(Register, L7_scratch       , L7); // constant pool cache
 145  145  REGISTER_DECLARATION(Register, O5_savedSP       , O5);
 146  146  REGISTER_DECLARATION(Register, I5_savedSP       , I5); // Saved SP before bumping for locals.  This is simply
 147  147                                                         // a copy SP, so in 64-bit it's a biased value.  The bias
 148  148                                                         // is added and removed as needed in the frame code.
 149  149  // Interface to signature handler
 150  150  REGISTER_DECLARATION(Register, Llocals          , L7); // pointer to locals for signature handler
 151  151  REGISTER_DECLARATION(Register, Lmethod          , L6); // methodOop when calling signature handler
 152  152  
 153  153  #else
 154  154  REGISTER_DECLARATION(Register, Lesp             , L0); // expression stack pointer
 155  155  REGISTER_DECLARATION(Register, Lbcp             , L1); // pointer to next bytecode
 156  156  REGISTER_DECLARATION(Register, Lmethod          , L2);
 157  157  REGISTER_DECLARATION(Register, Llocals          , L3);
 158  158  REGISTER_DECLARATION(Register, Largs            , L3); // pointer to locals for signature handler
 159  159                                                         // must match Llocals in asm interpreter
 160  160  REGISTER_DECLARATION(Register, Lmonitors        , L4);
 161  161  REGISTER_DECLARATION(Register, Lbyte_code       , L5);
 162  162  // When calling out from the interpreter we record SP so that we can remove any extra stack
 163  163  // space allocated during adapter transitions. This register is only live from the point
 164  164  // of the call until we return.
 165  165  REGISTER_DECLARATION(Register, Llast_SP         , L5);
 166  166  REGISTER_DECLARATION(Register, Lscratch         , L5);
 167  167  REGISTER_DECLARATION(Register, Lscratch2        , L6);
 168  168  REGISTER_DECLARATION(Register, LcpoolCache      , L6); // constant pool cache
 169  169  
 170  170  REGISTER_DECLARATION(Register, O5_savedSP       , O5);
 171  171  REGISTER_DECLARATION(Register, I5_savedSP       , I5); // Saved SP before bumping for locals.  This is simply
 172  172                                                         // a copy SP, so in 64-bit it's a biased value.  The bias
 173  173                                                         // is added and removed as needed in the frame code.
 174  174  REGISTER_DECLARATION(Register, IdispatchTables  , I4); // Base address of the bytecode dispatch tables
 175  175  REGISTER_DECLARATION(Register, IdispatchAddress , I3); // Register which saves the dispatch address for each bytecode
 176  176  REGISTER_DECLARATION(Register, ImethodDataPtr   , I2); // Pointer to the current method data
 177  177  #endif /* CC_INTERP */
 178  178  
 179  179  // NOTE: Lscratch2 and LcpoolCache point to the same registers in
 180  180  //       the interpreter code. If Lscratch2 needs to be used for some
 181  181  //       purpose than LcpoolCache should be restore after that for
 182  182  //       the interpreter to work right
 183  183  // (These assignments must be compatible with L7_thread_cache; see above.)
 184  184  
 185  185  // Since Lbcp points into the middle of the method object,
 186  186  // it is temporarily converted into a "bcx" during GC.
 187  187  
 188  188  // Exception processing
 189  189  // These registers are passed into exception handlers.
 190  190  // All exception handlers require the exception object being thrown.
 191  191  // In addition, an nmethod's exception handler must be passed
 192  192  // the address of the call site within the nmethod, to allow
 193  193  // proper selection of the applicable catch block.
 194  194  // (Interpreter frames use their own bcp() for this purpose.)
 195  195  //
 196  196  // The Oissuing_pc value is not always needed.  When jumping to a
 197  197  // handler that is known to be interpreted, the Oissuing_pc value can be
 198  198  // omitted.  An actual catch block in compiled code receives (from its
 199  199  // nmethod's exception handler) the thrown exception in the Oexception,
 200  200  // but it doesn't need the Oissuing_pc.
 201  201  //
 202  202  // If an exception handler (either interpreted or compiled)
 203  203  // discovers there is no applicable catch block, it updates
 204  204  // the Oissuing_pc to the continuation PC of its own caller,
 205  205  // pops back to that caller's stack frame, and executes that
 206  206  // caller's exception handler.  Obviously, this process will
 207  207  // iterate until the control stack is popped back to a method
 208  208  // containing an applicable catch block.  A key invariant is
 209  209  // that the Oissuing_pc value is always a value local to
 210  210  // the method whose exception handler is currently executing.
 211  211  //
 212  212  // Note:  The issuing PC value is __not__ a raw return address (I7 value).
 213  213  // It is a "return pc", the address __following__ the call.
 214  214  // Raw return addresses are converted to issuing PCs by frame::pc(),
 215  215  // or by stubs.  Issuing PCs can be used directly with PC range tables.
 216  216  //
 217  217  REGISTER_DECLARATION(Register, Oexception  , O0); // exception being thrown
 218  218  REGISTER_DECLARATION(Register, Oissuing_pc , O1); // where the exception is coming from
 219  219  
 220  220  
 221  221  // These must occur after the declarations above
 222  222  #ifndef DONT_USE_REGISTER_DEFINES
 223  223  
 224  224  #define Gthread             AS_REGISTER(Register, Gthread)
 225  225  #define Gmethod             AS_REGISTER(Register, Gmethod)
 226  226  #define Gmegamorphic_method AS_REGISTER(Register, Gmegamorphic_method)
 227  227  #define Ginline_cache_reg   AS_REGISTER(Register, Ginline_cache_reg)
 228  228  #define Gargs               AS_REGISTER(Register, Gargs)
 229  229  #define Lthread_cache       AS_REGISTER(Register, Lthread_cache)
 230  230  #define Gframe_size         AS_REGISTER(Register, Gframe_size)
 231  231  #define Gtemp               AS_REGISTER(Register, Gtemp)
 232  232  
 233  233  #ifdef CC_INTERP
 234  234  #define Lstate              AS_REGISTER(Register, Lstate)
 235  235  #define Lesp                AS_REGISTER(Register, Lesp)
 236  236  #define L1_scratch          AS_REGISTER(Register, L1_scratch)
 237  237  #define Lmirror             AS_REGISTER(Register, Lmirror)
 238  238  #define L2_scratch          AS_REGISTER(Register, L2_scratch)
 239  239  #define L3_scratch          AS_REGISTER(Register, L3_scratch)
 240  240  #define L4_scratch          AS_REGISTER(Register, L4_scratch)
 241  241  #define Lscratch            AS_REGISTER(Register, Lscratch)
 242  242  #define Lscratch2           AS_REGISTER(Register, Lscratch2)
 243  243  #define L7_scratch          AS_REGISTER(Register, L7_scratch)
 244  244  #define Ostate              AS_REGISTER(Register, Ostate)
 245  245  #else
 246  246  #define Lesp                AS_REGISTER(Register, Lesp)
 247  247  #define Lbcp                AS_REGISTER(Register, Lbcp)
 248  248  #define Lmethod             AS_REGISTER(Register, Lmethod)
 249  249  #define Llocals             AS_REGISTER(Register, Llocals)
 250  250  #define Lmonitors           AS_REGISTER(Register, Lmonitors)
 251  251  #define Lbyte_code          AS_REGISTER(Register, Lbyte_code)
 252  252  #define Lscratch            AS_REGISTER(Register, Lscratch)
 253  253  #define Lscratch2           AS_REGISTER(Register, Lscratch2)
 254  254  #define LcpoolCache         AS_REGISTER(Register, LcpoolCache)
 255  255  #endif /* ! CC_INTERP */
 256  256  
 257  257  #define Lentry_args         AS_REGISTER(Register, Lentry_args)
 258  258  #define I5_savedSP          AS_REGISTER(Register, I5_savedSP)
 259  259  #define O5_savedSP          AS_REGISTER(Register, O5_savedSP)
 260  260  #define IdispatchAddress    AS_REGISTER(Register, IdispatchAddress)
 261  261  #define ImethodDataPtr      AS_REGISTER(Register, ImethodDataPtr)
 262  262  #define IdispatchTables     AS_REGISTER(Register, IdispatchTables)
 263  263  
 264  264  #define Oexception          AS_REGISTER(Register, Oexception)
 265  265  #define Oissuing_pc         AS_REGISTER(Register, Oissuing_pc)
 266  266  
 267  267  
 268  268  #endif
 269  269  
 270  270  // Address is an abstraction used to represent a memory location.
 271  271  //
 272  272  // Note: A register location is represented via a Register, not
 273  273  //       via an address for efficiency & simplicity reasons.
 274  274  
 275  275  class Address VALUE_OBJ_CLASS_SPEC {
 276  276   private:
 277  277    Register           _base;           // Base register.
 278  278    RegisterOrConstant _index_or_disp;  // Index register or constant displacement.
 279  279    RelocationHolder   _rspec;
 280  280  
 281  281   public:
 282  282    Address() : _base(noreg), _index_or_disp(noreg) {}
 283  283  
 284  284    Address(Register base, RegisterOrConstant index_or_disp)
 285  285      : _base(base),
 286  286        _index_or_disp(index_or_disp) {
 287  287    }
 288  288  
 289  289    Address(Register base, Register index)
 290  290      : _base(base),
 291  291        _index_or_disp(index) {
 292  292    }
 293  293  
 294  294    Address(Register base, int disp)
 295  295      : _base(base),
 296  296        _index_or_disp(disp) {
 297  297    }
 298  298  
 299  299  #ifdef ASSERT
 300  300    // ByteSize is only a class when ASSERT is defined, otherwise it's an int.
 301  301    Address(Register base, ByteSize disp)
 302  302      : _base(base),
 303  303        _index_or_disp(in_bytes(disp)) {
 304  304    }
 305  305  #endif
 306  306  
 307  307    // accessors
 308  308    Register base()      const { return _base; }
 309  309    Register index()     const { return _index_or_disp.as_register(); }
 310  310    int      disp()      const { return _index_or_disp.as_constant(); }
 311  311  
 312  312    bool     has_index() const { return _index_or_disp.is_register(); }
 313  313    bool     has_disp()  const { return _index_or_disp.is_constant(); }
 314  314  
 315  315    const relocInfo::relocType rtype() { return _rspec.type(); }
 316  316    const RelocationHolder&    rspec() { return _rspec; }
 317  317  
 318  318    RelocationHolder rspec(int offset) const {
 319  319      return offset == 0 ? _rspec : _rspec.plus(offset);
 320  320    }
 321  321  
 322  322    inline bool is_simm13(int offset = 0);  // check disp+offset for overflow
 323  323  
 324  324    Address plus_disp(int plusdisp) const {     // bump disp by a small amount
 325  325      assert(_index_or_disp.is_constant(), "must have a displacement");
 326  326      Address a(base(), disp() + plusdisp);
 327  327      return a;
 328  328    }
 329  329  
 330  330    Address after_save() const {
 331  331      Address a = (*this);
 332  332      a._base = a._base->after_save();
 333  333      return a;
 334  334    }
 335  335  
 336  336    Address after_restore() const {
 337  337      Address a = (*this);
 338  338      a._base = a._base->after_restore();
 339  339      return a;
 340  340    }
 341  341  
 342  342    // Convert the raw encoding form into the form expected by the
 343  343    // constructor for Address.
 344  344    static Address make_raw(int base, int index, int scale, int disp, bool disp_is_oop);
 345  345  
 346  346    friend class Assembler;
 347  347  };
 348  348  
 349  349  
 350  350  class AddressLiteral VALUE_OBJ_CLASS_SPEC {
 351  351   private:
 352  352    address          _address;
 353  353    RelocationHolder _rspec;
 354  354  
 355  355    RelocationHolder rspec_from_rtype(relocInfo::relocType rtype, address addr) {
 356  356      switch (rtype) {
 357  357      case relocInfo::external_word_type:
 358  358        return external_word_Relocation::spec(addr);
 359  359      case relocInfo::internal_word_type:
 360  360        return internal_word_Relocation::spec(addr);
 361  361  #ifdef _LP64
 362  362      case relocInfo::opt_virtual_call_type:
 363  363        return opt_virtual_call_Relocation::spec();
 364  364      case relocInfo::static_call_type:
 365  365        return static_call_Relocation::spec();
 366  366      case relocInfo::runtime_call_type:
 367  367        return runtime_call_Relocation::spec();
 368  368  #endif
 369  369      case relocInfo::none:
 370  370        return RelocationHolder();
 371  371      default:
 372  372        ShouldNotReachHere();
 373  373        return RelocationHolder();
 374  374      }
 375  375    }
 376  376  
 377  377   protected:
 378  378    // creation
 379  379    AddressLiteral() : _address(NULL), _rspec(NULL) {}
 380  380  
 381  381   public:
 382  382    AddressLiteral(address addr, RelocationHolder const& rspec)
 383  383      : _address(addr),
 384  384        _rspec(rspec) {}
 385  385  
 386  386    // Some constructors to avoid casting at the call site.
 387  387    AddressLiteral(jobject obj, RelocationHolder const& rspec)
 388  388      : _address((address) obj),
 389  389        _rspec(rspec) {}
 390  390  
 391  391    AddressLiteral(intptr_t value, RelocationHolder const& rspec)
 392  392      : _address((address) value),
 393  393        _rspec(rspec) {}
 394  394  
 395  395    AddressLiteral(address addr, relocInfo::relocType rtype = relocInfo::none)
 396  396      : _address((address) addr),
 397  397      _rspec(rspec_from_rtype(rtype, (address) addr)) {}
 398  398  
 399  399    // Some constructors to avoid casting at the call site.
 400  400    AddressLiteral(address* addr, relocInfo::relocType rtype = relocInfo::none)
 401  401      : _address((address) addr),
 402  402      _rspec(rspec_from_rtype(rtype, (address) addr)) {}
 403  403  
 404  404    AddressLiteral(bool* addr, relocInfo::relocType rtype = relocInfo::none)
 405  405      : _address((address) addr),
 406  406        _rspec(rspec_from_rtype(rtype, (address) addr)) {}
 407  407  
 408  408    AddressLiteral(const bool* addr, relocInfo::relocType rtype = relocInfo::none)
 409  409      : _address((address) addr),
 410  410        _rspec(rspec_from_rtype(rtype, (address) addr)) {}
 411  411  
 412  412    AddressLiteral(signed char* addr, relocInfo::relocType rtype = relocInfo::none)
 413  413      : _address((address) addr),
 414  414        _rspec(rspec_from_rtype(rtype, (address) addr)) {}
 415  415  
 416  416    AddressLiteral(int* addr, relocInfo::relocType rtype = relocInfo::none)
 417  417      : _address((address) addr),
 418  418        _rspec(rspec_from_rtype(rtype, (address) addr)) {}
 419  419  
 420  420    AddressLiteral(intptr_t addr, relocInfo::relocType rtype = relocInfo::none)
 421  421      : _address((address) addr),
 422  422        _rspec(rspec_from_rtype(rtype, (address) addr)) {}
 423  423  
 424  424  #ifdef _LP64
 425  425    // 32-bit complains about a multiple declaration for int*.
 426  426    AddressLiteral(intptr_t* addr, relocInfo::relocType rtype = relocInfo::none)
 427  427      : _address((address) addr),
 428  428        _rspec(rspec_from_rtype(rtype, (address) addr)) {}
 429  429  #endif
 430  430  
 431  431    AddressLiteral(oop addr, relocInfo::relocType rtype = relocInfo::none)
 432  432      : _address((address) addr),
 433  433        _rspec(rspec_from_rtype(rtype, (address) addr)) {}
 434  434  
 435  435    AddressLiteral(float* addr, relocInfo::relocType rtype = relocInfo::none)
 436  436      : _address((address) addr),
 437  437        _rspec(rspec_from_rtype(rtype, (address) addr)) {}
 438  438  
 439  439    AddressLiteral(double* addr, relocInfo::relocType rtype = relocInfo::none)
 440  440      : _address((address) addr),
 441  441        _rspec(rspec_from_rtype(rtype, (address) addr)) {}
 442  442  
 443  443    intptr_t value() const { return (intptr_t) _address; }
 444  444    int      low10() const;
 445  445  
 446  446    const relocInfo::relocType rtype() const { return _rspec.type(); }
 447  447    const RelocationHolder&    rspec() const { return _rspec; }
 448  448  
 449  449    RelocationHolder rspec(int offset) const {
 450  450      return offset == 0 ? _rspec : _rspec.plus(offset);
 451  451    }
 452  452  };
 453  453  
 454  454  
 455  455  inline Address RegisterImpl::address_in_saved_window() const {
 456  456     return (Address(SP, (sp_offset_in_saved_window() * wordSize) + STACK_BIAS));
 457  457  }
 458  458  
 459  459  
 460  460  
 461  461  // Argument is an abstraction used to represent an outgoing
 462  462  // actual argument or an incoming formal parameter, whether
 463  463  // it resides in memory or in a register, in a manner consistent
 464  464  // with the SPARC Application Binary Interface, or ABI.  This is
 465  465  // often referred to as the native or C calling convention.
 466  466  
 467  467  class Argument VALUE_OBJ_CLASS_SPEC {
 468  468   private:
 469  469    int _number;
 470  470    bool _is_in;
 471  471  
 472  472   public:
 473  473  #ifdef _LP64
 474  474    enum {
 475  475      n_register_parameters = 6,          // only 6 registers may contain integer parameters
 476  476      n_float_register_parameters = 16    // Can have up to 16 floating registers
 477  477    };
 478  478  #else
 479  479    enum {
 480  480      n_register_parameters = 6           // only 6 registers may contain integer parameters
 481  481    };
 482  482  #endif
 483  483  
 484  484    // creation
 485  485    Argument(int number, bool is_in) : _number(number), _is_in(is_in) {}
 486  486  
 487  487    int  number() const  { return _number;  }
 488  488    bool is_in()  const  { return _is_in;   }
 489  489    bool is_out() const  { return !is_in(); }
 490  490  
 491  491    Argument successor() const  { return Argument(number() + 1, is_in()); }
 492  492    Argument as_in()     const  { return Argument(number(), true ); }
 493  493    Argument as_out()    const  { return Argument(number(), false); }
 494  494  
 495  495    // locating register-based arguments:
 496  496    bool is_register() const { return _number < n_register_parameters; }
 497  497  
 498  498  #ifdef _LP64
 499  499    // locating Floating Point register-based arguments:
 500  500    bool is_float_register() const { return _number < n_float_register_parameters; }
 501  501  
 502  502    FloatRegister as_float_register() const {
 503  503      assert(is_float_register(), "must be a register argument");
 504  504      return as_FloatRegister(( number() *2 ) + 1);
 505  505    }
 506  506    FloatRegister as_double_register() const {
 507  507      assert(is_float_register(), "must be a register argument");
 508  508      return as_FloatRegister(( number() *2 ));
 509  509    }
 510  510  #endif
 511  511  
 512  512    Register as_register() const {
 513  513      assert(is_register(), "must be a register argument");
 514  514      return is_in() ? as_iRegister(number()) : as_oRegister(number());
 515  515    }
 516  516  
 517  517    // locating memory-based arguments
 518  518    Address as_address() const {
 519  519      assert(!is_register(), "must be a memory argument");
 520  520      return address_in_frame();
 521  521    }
 522  522  
 523  523    // When applied to a register-based argument, give the corresponding address
 524  524    // into the 6-word area "into which callee may store register arguments"
 525  525    // (This is a different place than the corresponding register-save area location.)
 526  526    Address address_in_frame() const;
 527  527  
 528  528    // debugging
 529  529    const char* name() const;
 530  530  
 531  531    friend class Assembler;
 532  532  };
 533  533  
 534  534  
 535  535  // The SPARC Assembler: Pure assembler doing NO optimizations on the instruction
 536  536  // level; i.e., what you write
 537  537  // is what you get. The Assembler is generating code into a CodeBuffer.
 538  538  
 539  539  class Assembler : public AbstractAssembler  {
 540  540   protected:
 541  541  
 542  542    static void print_instruction(int inst);
 543  543    static int  patched_branch(int dest_pos, int inst, int inst_pos);
 544  544    static int  branch_destination(int inst, int pos);
 545  545  
 546  546  
 547  547    friend class AbstractAssembler;
 548  548    friend class AddressLiteral;
 549  549  
 550  550    // code patchers need various routines like inv_wdisp()
 551  551    friend class NativeInstruction;
 552  552    friend class NativeGeneralJump;
 553  553    friend class Relocation;
 554  554    friend class Label;
 555  555  
 556  556   public:
 557  557    // op carries format info; see page 62 & 267
 558  558  
 559  559    enum ops {
 560  560      call_op   = 1, // fmt 1
 561  561      branch_op = 0, // also sethi (fmt2)
 562  562      arith_op  = 2, // fmt 3, arith & misc
 563  563      ldst_op   = 3  // fmt 3, load/store
 564  564    };
 565  565  
 566  566    enum op2s {
 567  567      bpr_op2   = 3,
 568  568      fb_op2    = 6,
 569  569      fbp_op2   = 5,
 570  570      br_op2    = 2,
 571  571      bp_op2    = 1,
 572  572      cb_op2    = 7, // V8
 573  573      sethi_op2 = 4
 574  574    };
 575  575  
 576  576    enum op3s {
 577  577      // selected op3s
 578  578      add_op3      = 0x00,
 579  579      and_op3      = 0x01,
 580  580      or_op3       = 0x02,
 581  581      xor_op3      = 0x03,
 582  582      sub_op3      = 0x04,
 583  583      andn_op3     = 0x05,
 584  584      orn_op3      = 0x06,
 585  585      xnor_op3     = 0x07,
 586  586      addc_op3     = 0x08,
 587  587      mulx_op3     = 0x09,
 588  588      umul_op3     = 0x0a,
 589  589      smul_op3     = 0x0b,
 590  590      subc_op3     = 0x0c,
 591  591      udivx_op3    = 0x0d,
 592  592      udiv_op3     = 0x0e,
 593  593      sdiv_op3     = 0x0f,
 594  594  
 595  595      addcc_op3    = 0x10,
 596  596      andcc_op3    = 0x11,
 597  597      orcc_op3     = 0x12,
 598  598      xorcc_op3    = 0x13,
 599  599      subcc_op3    = 0x14,
 600  600      andncc_op3   = 0x15,
 601  601      orncc_op3    = 0x16,
 602  602      xnorcc_op3   = 0x17,
 603  603      addccc_op3   = 0x18,
 604  604      umulcc_op3   = 0x1a,
 605  605      smulcc_op3   = 0x1b,
 606  606      subccc_op3   = 0x1c,
 607  607      udivcc_op3   = 0x1e,
 608  608      sdivcc_op3   = 0x1f,
 609  609  
 610  610      taddcc_op3   = 0x20,
 611  611      tsubcc_op3   = 0x21,
 612  612      taddcctv_op3 = 0x22,
 613  613      tsubcctv_op3 = 0x23,
 614  614      mulscc_op3   = 0x24,
 615  615      sll_op3      = 0x25,
 616  616      sllx_op3     = 0x25,
 617  617      srl_op3      = 0x26,
 618  618      srlx_op3     = 0x26,
 619  619      sra_op3      = 0x27,
 620  620      srax_op3     = 0x27,
 621  621      rdreg_op3    = 0x28,
 622  622      membar_op3   = 0x28,
 623  623  
 624  624      flushw_op3   = 0x2b,
 625  625      movcc_op3    = 0x2c,
 626  626      sdivx_op3    = 0x2d,
 627  627      popc_op3     = 0x2e,
 628  628      movr_op3     = 0x2f,
 629  629  
 630  630      sir_op3      = 0x30,
 631  631      wrreg_op3    = 0x30,
 632  632      saved_op3    = 0x31,
 633  633  
 634  634      fpop1_op3    = 0x34,
 635  635      fpop2_op3    = 0x35,
 636  636      impdep1_op3  = 0x36,
 637  637      impdep2_op3  = 0x37,
 638  638      jmpl_op3     = 0x38,
 639  639      rett_op3     = 0x39,
 640  640      trap_op3     = 0x3a,
 641  641      flush_op3    = 0x3b,
 642  642      save_op3     = 0x3c,
 643  643      restore_op3  = 0x3d,
 644  644      done_op3     = 0x3e,
 645  645      retry_op3    = 0x3e,
 646  646  
 647  647      lduw_op3     = 0x00,
 648  648      ldub_op3     = 0x01,
 649  649      lduh_op3     = 0x02,
 650  650      ldd_op3      = 0x03,
 651  651      stw_op3      = 0x04,
 652  652      stb_op3      = 0x05,
 653  653      sth_op3      = 0x06,
 654  654      std_op3      = 0x07,
 655  655      ldsw_op3     = 0x08,
 656  656      ldsb_op3     = 0x09,
 657  657      ldsh_op3     = 0x0a,
 658  658      ldx_op3      = 0x0b,
 659  659  
 660  660      ldstub_op3   = 0x0d,
 661  661      stx_op3      = 0x0e,
 662  662      swap_op3     = 0x0f,
 663  663  
 664  664      lduwa_op3    = 0x10,
 665  665      ldxa_op3     = 0x1b,
 666  666  
 667  667      stwa_op3     = 0x14,
 668  668      stxa_op3     = 0x1e,
 669  669  
 670  670      ldf_op3      = 0x20,
 671  671      ldfsr_op3    = 0x21,
 672  672      ldqf_op3     = 0x22,
 673  673      lddf_op3     = 0x23,
 674  674      stf_op3      = 0x24,
 675  675      stfsr_op3    = 0x25,
 676  676      stqf_op3     = 0x26,
 677  677      stdf_op3     = 0x27,
 678  678  
 679  679      prefetch_op3 = 0x2d,
 680  680  
 681  681  
 682  682      ldc_op3      = 0x30,
 683  683      ldcsr_op3    = 0x31,
 684  684      lddc_op3     = 0x33,
 685  685      stc_op3      = 0x34,
 686  686      stcsr_op3    = 0x35,
 687  687      stdcq_op3    = 0x36,
 688  688      stdc_op3     = 0x37,
 689  689  
 690  690      casa_op3     = 0x3c,
 691  691      casxa_op3    = 0x3e,
 692  692  
 693  693      alt_bit_op3  = 0x10,
 694  694       cc_bit_op3  = 0x10
 695  695    };
 696  696  
 697  697    enum opfs {
 698  698      // selected opfs
 699  699      fmovs_opf   = 0x01,
 700  700      fmovd_opf   = 0x02,
 701  701  
 702  702      fnegs_opf   = 0x05,
 703  703      fnegd_opf   = 0x06,
 704  704  
 705  705      fadds_opf   = 0x41,
 706  706      faddd_opf   = 0x42,
 707  707      fsubs_opf   = 0x45,
 708  708      fsubd_opf   = 0x46,
 709  709  
 710  710      fmuls_opf   = 0x49,
 711  711      fmuld_opf   = 0x4a,
 712  712      fdivs_opf   = 0x4d,
 713  713      fdivd_opf   = 0x4e,
 714  714  
 715  715      fcmps_opf   = 0x51,
 716  716      fcmpd_opf   = 0x52,
 717  717  
 718  718      fstox_opf   = 0x81,
 719  719      fdtox_opf   = 0x82,
 720  720      fxtos_opf   = 0x84,
 721  721      fxtod_opf   = 0x88,
 722  722      fitos_opf   = 0xc4,
 723  723      fdtos_opf   = 0xc6,
 724  724      fitod_opf   = 0xc8,
 725  725      fstod_opf   = 0xc9,
 726  726      fstoi_opf   = 0xd1,
 727  727      fdtoi_opf   = 0xd2
 728  728    };
 729  729  
 730  730    enum RCondition {  rc_z = 1,  rc_lez = 2,  rc_lz = 3, rc_nz = 5, rc_gz = 6, rc_gez = 7  };
 731  731  
 732  732    enum Condition {
 733  733       // for FBfcc & FBPfcc instruction
 734  734      f_never                     = 0,
 735  735      f_notEqual                  = 1,
 736  736      f_notZero                   = 1,
 737  737      f_lessOrGreater             = 2,
 738  738      f_unorderedOrLess           = 3,
 739  739      f_less                      = 4,
 740  740      f_unorderedOrGreater        = 5,
 741  741      f_greater                   = 6,
 742  742      f_unordered                 = 7,
 743  743      f_always                    = 8,
 744  744      f_equal                     = 9,
 745  745      f_zero                      = 9,
 746  746      f_unorderedOrEqual          = 10,
 747  747      f_greaterOrEqual            = 11,
 748  748      f_unorderedOrGreaterOrEqual = 12,
 749  749      f_lessOrEqual               = 13,
 750  750      f_unorderedOrLessOrEqual    = 14,
 751  751      f_ordered                   = 15,
 752  752  
 753  753      // V8 coproc, pp 123 v8 manual
 754  754  
 755  755      cp_always  = 8,
 756  756      cp_never   = 0,
 757  757      cp_3       = 7,
 758  758      cp_2       = 6,
 759  759      cp_2or3    = 5,
 760  760      cp_1       = 4,
 761  761      cp_1or3    = 3,
 762  762      cp_1or2    = 2,
 763  763      cp_1or2or3 = 1,
 764  764      cp_0       = 9,
 765  765      cp_0or3    = 10,
 766  766      cp_0or2    = 11,
 767  767      cp_0or2or3 = 12,
 768  768      cp_0or1    = 13,
 769  769      cp_0or1or3 = 14,
 770  770      cp_0or1or2 = 15,
 771  771  
 772  772  
 773  773      // for integers
 774  774  
 775  775      never                 =  0,
 776  776      equal                 =  1,
 777  777      zero                  =  1,
 778  778      lessEqual             =  2,
 779  779      less                  =  3,
 780  780      lessEqualUnsigned     =  4,
 781  781      lessUnsigned          =  5,
 782  782      carrySet              =  5,
 783  783      negative              =  6,
 784  784      overflowSet           =  7,
 785  785      always                =  8,
 786  786      notEqual              =  9,
 787  787      notZero               =  9,
 788  788      greater               =  10,
 789  789      greaterEqual          =  11,
 790  790      greaterUnsigned       =  12,
 791  791      greaterEqualUnsigned  =  13,
 792  792      carryClear            =  13,
 793  793      positive              =  14,
 794  794      overflowClear         =  15
 795  795    };
 796  796  
 797  797    enum CC {
 798  798      icc  = 0,  xcc  = 2,
 799  799      // ptr_cc is the correct condition code for a pointer or intptr_t:
 800  800      ptr_cc = NOT_LP64(icc) LP64_ONLY(xcc),
 801  801      fcc0 = 0,  fcc1 = 1, fcc2 = 2, fcc3 = 3
 802  802    };
 803  803  
 804  804    enum PrefetchFcn {
 805  805      severalReads = 0,  oneRead = 1,  severalWritesAndPossiblyReads = 2, oneWrite = 3, page = 4
 806  806    };
 807  807  
 808  808   public:
 809  809    // Helper functions for groups of instructions
 810  810  
 811  811    enum Predict { pt = 1, pn = 0 }; // pt = predict taken
 812  812  
 813  813    enum Membar_mask_bits { // page 184, v9
 814  814      StoreStore = 1 << 3,
 815  815      LoadStore  = 1 << 2,
 816  816      StoreLoad  = 1 << 1,
 817  817      LoadLoad   = 1 << 0,
 818  818  
 819  819      Sync       = 1 << 6,
 820  820      MemIssue   = 1 << 5,
 821  821      Lookaside  = 1 << 4
 822  822    };
 823  823  
 824  824    // test if x is within signed immediate range for nbits
 825  825    static bool is_simm(int x, int nbits) { return -( 1 << nbits-1 )  <= x   &&   x  <  ( 1 << nbits-1 ); }
 826  826  
 827  827    // test if -4096 <= x <= 4095
 828  828    static bool is_simm13(int x) { return is_simm(x, 13); }
 829  829  
 830  830    enum ASIs { // page 72, v9
 831  831      ASI_PRIMARY        = 0x80,
 832  832      ASI_PRIMARY_LITTLE = 0x88
 833  833      // add more from book as needed
 834  834    };
 835  835  
 836  836   protected:
 837  837    // helpers
 838  838  
 839  839    // x is supposed to fit in a field "nbits" wide
 840  840    // and be sign-extended. Check the range.
 841  841  
 842  842    static void assert_signed_range(intptr_t x, int nbits) {
 843  843      assert( nbits == 32
 844  844          ||  -(1 << nbits-1) <= x  &&  x < ( 1 << nbits-1),
 845  845        "value out of range");
 846  846    }
 847  847  
 848  848    static void assert_signed_word_disp_range(intptr_t x, int nbits) {
 849  849      assert( (x & 3) == 0, "not word aligned");
 850  850      assert_signed_range(x, nbits + 2);
 851  851    }
 852  852  
 853  853    static void assert_unsigned_const(int x, int nbits) {
 854  854      assert( juint(x)  <  juint(1 << nbits), "unsigned constant out of range");
 855  855    }
 856  856  
 857  857    // fields: note bits numbered from LSB = 0,
 858  858    //  fields known by inclusive bit range
 859  859  
 860  860    static int fmask(juint hi_bit, juint lo_bit) {
 861  861      assert( hi_bit >= lo_bit  &&  0 <= lo_bit  &&  hi_bit < 32, "bad bits");
 862  862      return (1 << ( hi_bit-lo_bit + 1 )) - 1;
 863  863    }
 864  864  
 865  865    // inverse of u_field
 866  866  
 867  867    static int inv_u_field(int x, int hi_bit, int lo_bit) {
 868  868      juint r = juint(x) >> lo_bit;
 869  869      r &= fmask( hi_bit, lo_bit);
 870  870      return int(r);
 871  871    }
 872  872  
 873  873  
 874  874    // signed version: extract from field and sign-extend
 875  875  
 876  876    static int inv_s_field(int x, int hi_bit, int lo_bit) {
 877  877      int sign_shift = 31 - hi_bit;
 878  878      return inv_u_field( ((x << sign_shift) >> sign_shift), hi_bit, lo_bit);
 879  879    }
 880  880  
 881  881    // given a field that ranges from hi_bit to lo_bit (inclusive,
 882  882    // LSB = 0), and an unsigned value for the field,
 883  883    // shift it into the field
 884  884  
 885  885  #ifdef ASSERT
 886  886    static int u_field(int x, int hi_bit, int lo_bit) {
 887  887      assert( ( x & ~fmask(hi_bit, lo_bit))  == 0,
 888  888              "value out of range");
 889  889      int r = x << lo_bit;
 890  890      assert( inv_u_field(r, hi_bit, lo_bit) == x, "just checking");
 891  891      return r;
 892  892    }
 893  893  #else
 894  894    // make sure this is inlined as it will reduce code size significantly
 895  895    #define u_field(x, hi_bit, lo_bit)   ((x) << (lo_bit))
 896  896  #endif
 897  897  
 898  898    static int inv_op(  int x ) { return inv_u_field(x, 31, 30); }
 899  899    static int inv_op2( int x ) { return inv_u_field(x, 24, 22); }
 900  900    static int inv_op3( int x ) { return inv_u_field(x, 24, 19); }
 901  901    static int inv_cond( int x ){ return inv_u_field(x, 28, 25); }
 902  902  
 903  903    static bool inv_immed( int x ) { return (x & Assembler::immed(true)) != 0; }
 904  904  
 905  905    static Register inv_rd(  int x ) { return as_Register(inv_u_field(x, 29, 25)); }
 906  906    static Register inv_rs1( int x ) { return as_Register(inv_u_field(x, 18, 14)); }
 907  907    static Register inv_rs2( int x ) { return as_Register(inv_u_field(x,  4,  0)); }
 908  908  
 909  909    static int op(       int         x)  { return  u_field(x,             31, 30); }
 910  910    static int rd(       Register    r)  { return  u_field(r->encoding(), 29, 25); }
 911  911    static int fcn(      int         x)  { return  u_field(x,             29, 25); }
 912  912    static int op3(      int         x)  { return  u_field(x,             24, 19); }
 913  913    static int rs1(      Register    r)  { return  u_field(r->encoding(), 18, 14); }
 914  914    static int rs2(      Register    r)  { return  u_field(r->encoding(),  4,  0); }
 915  915    static int annul(    bool        a)  { return  u_field(a ? 1 : 0,     29, 29); }
 916  916    static int cond(     int         x)  { return  u_field(x,             28, 25); }
 917  917    static int cond_mov( int         x)  { return  u_field(x,             17, 14); }
 918  918    static int rcond(    RCondition  x)  { return  u_field(x,             12, 10); }
 919  919    static int op2(      int         x)  { return  u_field(x,             24, 22); }
 920  920    static int predict(  bool        p)  { return  u_field(p ? 1 : 0,     19, 19); }
 921  921    static int branchcc( CC       fcca)  { return  u_field(fcca,          21, 20); }
 922  922    static int cmpcc(    CC       fcca)  { return  u_field(fcca,          26, 25); }
 923  923    static int imm_asi(  int         x)  { return  u_field(x,             12,  5); }
 924  924    static int immed(    bool        i)  { return  u_field(i ? 1 : 0,     13, 13); }
 925  925    static int opf_low6( int         w)  { return  u_field(w,             10,  5); }
 926  926    static int opf_low5( int         w)  { return  u_field(w,              9,  5); }
 927  927    static int trapcc(   CC         cc)  { return  u_field(cc,            12, 11); }
 928  928    static int sx(       int         i)  { return  u_field(i,             12, 12); } // shift x=1 means 64-bit
 929  929    static int opf(      int         x)  { return  u_field(x,             13,  5); }
 930  930  
 931  931    static int opf_cc(   CC          c, bool useFloat ) { return u_field((useFloat ? 0 : 4) + c, 13, 11); }
 932  932    static int mov_cc(   CC          c, bool useFloat ) { return u_field(useFloat ? 0 : 1,  18, 18) | u_field(c, 12, 11); }
 933  933  
 934  934    static int fd( FloatRegister r,  FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 29, 25); };
 935  935    static int fs1(FloatRegister r,  FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 18, 14); };
 936  936    static int fs2(FloatRegister r,  FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa),  4,  0); };
 937  937  
 938  938    // some float instructions use this encoding on the op3 field
 939  939    static int alt_op3(int op, FloatRegisterImpl::Width w) {
 940  940      int r;
 941  941      switch(w) {
 942  942       case FloatRegisterImpl::S: r = op + 0;  break;
 943  943       case FloatRegisterImpl::D: r = op + 3;  break;
 944  944       case FloatRegisterImpl::Q: r = op + 2;  break;
 945  945       default: ShouldNotReachHere(); break;
 946  946      }
 947  947      return op3(r);
 948  948    }
 949  949  
 950  950  
 951  951    // compute inverse of simm
 952  952    static int inv_simm(int x, int nbits) {
 953  953      return (int)(x << (32 - nbits)) >> (32 - nbits);
 954  954    }
 955  955  
 956  956    static int inv_simm13( int x ) { return inv_simm(x, 13); }
 957  957  
 958  958    // signed immediate, in low bits, nbits long
 959  959    static int simm(int x, int nbits) {
 960  960      assert_signed_range(x, nbits);
 961  961      return x  &  (( 1 << nbits ) - 1);
 962  962    }
 963  963  
 964  964    // compute inverse of wdisp16
 965  965    static intptr_t inv_wdisp16(int x, intptr_t pos) {
 966  966      int lo = x & (( 1 << 14 ) - 1);
 967  967      int hi = (x >> 20) & 3;
 968  968      if (hi >= 2) hi |= ~1;
 969  969      return (((hi << 14) | lo) << 2) + pos;
 970  970    }
 971  971  
 972  972    // word offset, 14 bits at LSend, 2 bits at B21, B20
 973  973    static int wdisp16(intptr_t x, intptr_t off) {
 974  974      intptr_t xx = x - off;
 975  975      assert_signed_word_disp_range(xx, 16);
 976  976      int r =  (xx >> 2) & ((1 << 14) - 1)
 977  977             |  (  ( (xx>>(2+14)) & 3 )  <<  20 );
 978  978      assert( inv_wdisp16(r, off) == x,  "inverse is not inverse");
 979  979      return r;
 980  980    }
 981  981  
 982  982  
 983  983    // word displacement in low-order nbits bits
 984  984  
 985  985    static intptr_t inv_wdisp( int x, intptr_t pos, int nbits ) {
 986  986      int pre_sign_extend = x & (( 1 << nbits ) - 1);
 987  987      int r =  pre_sign_extend >= ( 1 << (nbits-1) )
 988  988         ?   pre_sign_extend | ~(( 1 << nbits ) - 1)
 989  989         :   pre_sign_extend;
 990  990      return (r << 2) + pos;
 991  991    }
 992  992  
 993  993    static int wdisp( intptr_t x, intptr_t off, int nbits ) {
 994  994      intptr_t xx = x - off;
 995  995      assert_signed_word_disp_range(xx, nbits);
 996  996      int r =  (xx >> 2) & (( 1 << nbits ) - 1);
 997  997      assert( inv_wdisp( r, off, nbits )  ==  x, "inverse not inverse");
 998  998      return r;
 999  999    }
1000 1000  
1001 1001  
1002 1002    // Extract the top 32 bits in a 64 bit word
1003 1003    static int32_t hi32( int64_t x ) {
1004 1004      int32_t r = int32_t( (uint64_t)x >> 32 );
1005 1005      return r;
1006 1006    }
1007 1007  
1008 1008    // given a sethi instruction, extract the constant, left-justified
1009 1009    static int inv_hi22( int x ) {
1010 1010      return x << 10;
1011 1011    }
1012 1012  
1013 1013    // create an imm22 field, given a 32-bit left-justified constant
1014 1014    static int hi22( int x ) {
1015 1015      int r = int( juint(x) >> 10 );
1016 1016      assert( (r & ~((1 << 22) - 1))  ==  0, "just checkin'");
1017 1017      return r;
1018 1018    }
1019 1019  
1020 1020    // create a low10 __value__ (not a field) for a given a 32-bit constant
1021 1021    static int low10( int x ) {
1022 1022      return x & ((1 << 10) - 1);
1023 1023    }
1024 1024  
1025 1025    // instruction only in v9
1026 1026    static void v9_only() { assert( VM_Version::v9_instructions_work(), "This instruction only works on SPARC V9"); }
1027 1027  
1028 1028    // instruction only in v8
1029 1029    static void v8_only() { assert( VM_Version::v8_instructions_work(), "This instruction only works on SPARC V8"); }
1030 1030  
1031 1031    // instruction deprecated in v9
1032 1032    static void v9_dep()  { } // do nothing for now
1033 1033  
1034 1034    // some float instructions only exist for single prec. on v8
1035 1035    static void v8_s_only(FloatRegisterImpl::Width w)  { if (w != FloatRegisterImpl::S)  v9_only(); }
1036 1036  
1037 1037    // v8 has no CC field
1038 1038    static void v8_no_cc(CC cc)  { if (cc)  v9_only(); }
1039 1039  
1040 1040   protected:
1041 1041    // Simple delay-slot scheme:
1042 1042    // In order to check the programmer, the assembler keeps track of deley slots.
1043 1043    // It forbids CTIs in delay slots (conservative, but should be OK).
1044 1044    // Also, when putting an instruction into a delay slot, you must say
1045 1045    // asm->delayed()->add(...), in order to check that you don't omit
1046 1046    // delay-slot instructions.
1047 1047    // To implement this, we use a simple FSA
1048 1048  
1049 1049  #ifdef ASSERT
1050 1050    #define CHECK_DELAY
1051 1051  #endif
1052 1052  #ifdef CHECK_DELAY
1053 1053    enum Delay_state { no_delay, at_delay_slot, filling_delay_slot } delay_state;
1054 1054  #endif
1055 1055  
1056 1056   public:
1057 1057    // Tells assembler next instruction must NOT be in delay slot.
1058 1058    // Use at start of multinstruction macros.
1059 1059    void assert_not_delayed() {
1060 1060      // This is a separate overloading to avoid creation of string constants
1061 1061      // in non-asserted code--with some compilers this pollutes the object code.
1062 1062  #ifdef CHECK_DELAY
1063 1063      assert_not_delayed("next instruction should not be a delay slot");
1064 1064  #endif
1065 1065    }
1066 1066    void assert_not_delayed(const char* msg) {
1067 1067  #ifdef CHECK_DELAY
1068 1068      assert_msg ( delay_state == no_delay, msg);
1069 1069  #endif
1070 1070    }
1071 1071  
1072 1072   protected:
1073 1073    // Delay slot helpers
1074 1074    // cti is called when emitting control-transfer instruction,
1075 1075    // BEFORE doing the emitting.
1076 1076    // Only effective when assertion-checking is enabled.
1077 1077    void cti() {
1078 1078  #ifdef CHECK_DELAY
1079 1079      assert_not_delayed("cti should not be in delay slot");
1080 1080  #endif
1081 1081    }
1082 1082  
1083 1083    // called when emitting cti with a delay slot, AFTER emitting
1084 1084    void has_delay_slot() {
1085 1085  #ifdef CHECK_DELAY
1086 1086      assert_not_delayed("just checking");
1087 1087      delay_state = at_delay_slot;
1088 1088  #endif
1089 1089    }
1090 1090  
1091 1091  public:
1092 1092    // Tells assembler you know that next instruction is delayed
1093 1093    Assembler* delayed() {
1094 1094  #ifdef CHECK_DELAY
1095 1095      assert ( delay_state == at_delay_slot, "delayed instruction is not in delay slot");
1096 1096      delay_state = filling_delay_slot;
1097 1097  #endif
1098 1098      return this;
1099 1099    }
1100 1100  
1101 1101    void flush() {
1102 1102  #ifdef CHECK_DELAY
1103 1103      assert ( delay_state == no_delay, "ending code with a delay slot");
1104 1104  #endif
1105 1105      AbstractAssembler::flush();
1106 1106    }
1107 1107  
1108 1108    inline void emit_long(int);  // shadows AbstractAssembler::emit_long
1109 1109    inline void emit_data(int x) { emit_long(x); }
1110 1110    inline void emit_data(int, RelocationHolder const&);
1111 1111    inline void emit_data(int, relocInfo::relocType rtype);
1112 1112    // helper for above fcns
1113 1113    inline void check_delay();
1114 1114  
1115 1115  
1116 1116   public:
1117 1117    // instructions, refer to page numbers in the SPARC Architecture Manual, V9
1118 1118  
1119 1119    // pp 135 (addc was addx in v8)
1120 1120  
1121 1121    inline void add(Register s1, Register s2, Register d );
1122 1122    inline void add(Register s1, int simm13a, Register d, relocInfo::relocType rtype = relocInfo::none);
1123 1123    inline void add(Register s1, int simm13a, Register d, RelocationHolder const& rspec);
1124 1124    inline void add(Register s1, RegisterOrConstant s2, Register d, int offset = 0);
1125 1125    inline void add(const Address& a, Register d, int offset = 0) { add( a.base(), a.disp() + offset, d, a.rspec(offset)); }
1126 1126  
1127 1127    void addcc(  Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(add_op3  | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
1128 1128    void addcc(  Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(add_op3  | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1129 1129    void addc(   Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(addc_op3             ) | rs1(s1) | rs2(s2) ); }
1130 1130    void addc(   Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(addc_op3             ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1131 1131    void addccc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(addc_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
1132 1132    void addccc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(addc_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1133 1133  
1134 1134    // pp 136
1135 1135  
1136 1136    inline void bpr( RCondition c, bool a, Predict p, Register s1, address d, relocInfo::relocType rt = relocInfo::none );
1137 1137    inline void bpr( RCondition c, bool a, Predict p, Register s1, Label& L);
1138 1138  
1139 1139   protected: // use MacroAssembler::br instead
1140 1140  
1141 1141    // pp 138
1142 1142  
1143 1143    inline void fb( Condition c, bool a, address d, relocInfo::relocType rt = relocInfo::none );
1144 1144    inline void fb( Condition c, bool a, Label& L );
1145 1145  
1146 1146    // pp 141
1147 1147  
1148 1148    inline void fbp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
1149 1149    inline void fbp( Condition c, bool a, CC cc, Predict p, Label& L );
1150 1150  
1151 1151   public:
1152 1152  
1153 1153    // pp 144
1154 1154  
1155 1155    inline void br( Condition c, bool a, address d, relocInfo::relocType rt = relocInfo::none );
1156 1156    inline void br( Condition c, bool a, Label& L );
1157 1157  
1158 1158    // pp 146
1159 1159  
1160 1160    inline void bp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
1161 1161    inline void bp( Condition c, bool a, CC cc, Predict p, Label& L );
1162 1162  
1163 1163    // pp 121 (V8)
1164 1164  
1165 1165    inline void cb( Condition c, bool a, address d, relocInfo::relocType rt = relocInfo::none );
1166 1166    inline void cb( Condition c, bool a, Label& L );
1167 1167  
1168 1168    // pp 149
1169 1169  
1170 1170    inline void call( address d,  relocInfo::relocType rt = relocInfo::runtime_call_type );
1171 1171    inline void call( Label& L,   relocInfo::relocType rt = relocInfo::runtime_call_type );
1172 1172  
1173 1173    // pp 150
1174 1174  
1175 1175    // These instructions compare the contents of s2 with the contents of
1176 1176    // memory at address in s1. If the values are equal, the contents of memory
1177 1177    // at address s1 is swapped with the data in d. If the values are not equal,
1178 1178    // the the contents of memory at s1 is loaded into d, without the swap.
1179 1179  
1180 1180    void casa(  Register s1, Register s2, Register d, int ia = -1 ) { v9_only();  emit_long( op(ldst_op) | rd(d) | op3(casa_op3 ) | rs1(s1) | (ia == -1  ? immed(true) : imm_asi(ia)) | rs2(s2)); }
1181 1181    void casxa( Register s1, Register s2, Register d, int ia = -1 ) { v9_only();  emit_long( op(ldst_op) | rd(d) | op3(casxa_op3) | rs1(s1) | (ia == -1  ? immed(true) : imm_asi(ia)) | rs2(s2)); }
1182 1182  
1183 1183    // pp 152
1184 1184  
1185 1185    void udiv(   Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(udiv_op3             ) | rs1(s1) | rs2(s2)); }
1186 1186    void udiv(   Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(udiv_op3             ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1187 1187    void sdiv(   Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sdiv_op3             ) | rs1(s1) | rs2(s2)); }
1188 1188    void sdiv(   Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sdiv_op3             ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1189 1189    void udivcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(udiv_op3 | cc_bit_op3) | rs1(s1) | rs2(s2)); }
1190 1190    void udivcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(udiv_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1191 1191    void sdivcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sdiv_op3 | cc_bit_op3) | rs1(s1) | rs2(s2)); }
1192 1192    void sdivcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sdiv_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1193 1193  
1194 1194    // pp 155
1195 1195  
1196 1196    void done()  { v9_only();  cti();  emit_long( op(arith_op) | fcn(0) | op3(done_op3) ); }
1197 1197    void retry() { v9_only();  cti();  emit_long( op(arith_op) | fcn(1) | op3(retry_op3) ); }
1198 1198  
1199 1199    // pp 156
1200 1200  
1201 1201    void fadd( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x40 + w) | fs2(s2, w)); }
1202 1202    void fsub( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x44 + w) | fs2(s2, w)); }
1203 1203  
1204 1204    // pp 157
1205 1205  
1206 1206    void fcmp(  FloatRegisterImpl::Width w, CC cc, FloatRegister s1, FloatRegister s2) { v8_no_cc(cc);  emit_long( op(arith_op) | cmpcc(cc) | op3(fpop2_op3) | fs1(s1, w) | opf(0x50 + w) | fs2(s2, w)); }
1207 1207    void fcmpe( FloatRegisterImpl::Width w, CC cc, FloatRegister s1, FloatRegister s2) { v8_no_cc(cc);  emit_long( op(arith_op) | cmpcc(cc) | op3(fpop2_op3) | fs1(s1, w) | opf(0x54 + w) | fs2(s2, w)); }
1208 1208  
1209 1209    // pp 159
1210 1210  
1211 1211    void ftox( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { v9_only();  emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x80 + w) | fs2(s, w)); }
1212 1212    void ftoi( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) {             emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0xd0 + w) | fs2(s, w)); }
1213 1213  
1214 1214    // pp 160
1215 1215  
1216 1216    void ftof( FloatRegisterImpl::Width sw, FloatRegisterImpl::Width dw, FloatRegister s, FloatRegister d ) { emit_long( op(arith_op) | fd(d, dw) | op3(fpop1_op3) | opf(0xc0 + sw + dw*4) | fs2(s, sw)); }
1217 1217  
1218 1218    // pp 161
1219 1219  
1220 1220    void fxtof( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { v9_only();  emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x80 + w*4) | fs2(s, w)); }
1221 1221    void fitof( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) {             emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0xc0 + w*4) | fs2(s, w)); }
1222 1222  
1223 1223    // pp 162
1224 1224  
1225 1225    void fmov( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { v8_s_only(w);  emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x00 + w) | fs2(s, w)); }
1226 1226  
1227 1227    void fneg( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { v8_s_only(w);  emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x04 + w) | fs2(s, w)); }
1228 1228  
1229 1229    // page 144 sparc v8 architecture (double prec works on v8 if the source and destination registers are the same). fnegs is the only instruction available
1230 1230    // on v8 to do negation of single, double and quad precision floats.
1231 1231  
1232 1232    void fneg( FloatRegisterImpl::Width w, FloatRegister sd ) { if (VM_Version::v9_instructions_work()) emit_long( op(arith_op) | fd(sd, w) | op3(fpop1_op3) | opf(0x04 + w) | fs2(sd, w)); else emit_long( op(arith_op) | fd(sd, w) | op3(fpop1_op3) |  opf(0x05) | fs2(sd, w)); }
1233 1233  
1234 1234    void fabs( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { v8_s_only(w);  emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x08 + w) | fs2(s, w)); }
1235 1235  
1236 1236    // page 144 sparc v8 architecture (double prec works on v8 if the source and destination registers are the same). fabss is the only instruction available
1237 1237    // on v8 to do abs operation on single/double/quad precision floats.
1238 1238  
1239 1239    void fabs( FloatRegisterImpl::Width w, FloatRegister sd ) { if (VM_Version::v9_instructions_work()) emit_long( op(arith_op) | fd(sd, w) | op3(fpop1_op3) | opf(0x08 + w) | fs2(sd, w)); else emit_long( op(arith_op) | fd(sd, w) | op3(fpop1_op3) | opf(0x09) | fs2(sd, w)); }
1240 1240  
1241 1241    // pp 163
1242 1242  
1243 1243    void fmul( FloatRegisterImpl::Width w,                            FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_long( op(arith_op) | fd(d, w)  | op3(fpop1_op3) | fs1(s1, w)  | opf(0x48 + w)         | fs2(s2, w)); }
1244 1244    void fmul( FloatRegisterImpl::Width sw, FloatRegisterImpl::Width dw,  FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_long( op(arith_op) | fd(d, dw) | op3(fpop1_op3) | fs1(s1, sw) | opf(0x60 + sw + dw*4) | fs2(s2, sw)); }
1245 1245    void fdiv( FloatRegisterImpl::Width w,                            FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_long( op(arith_op) | fd(d, w)  | op3(fpop1_op3) | fs1(s1, w)  | opf(0x4c + w)         | fs2(s2, w)); }
1246 1246  
1247 1247    // pp 164
1248 1248  
1249 1249    void fsqrt( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x28 + w) | fs2(s, w)); }
1250 1250  
1251 1251    // pp 165
1252 1252  
1253 1253    inline void flush( Register s1, Register s2 );
1254 1254    inline void flush( Register s1, int simm13a);
1255 1255  
1256 1256    // pp 167
1257 1257  
1258 1258    void flushw() { v9_only();  emit_long( op(arith_op) | op3(flushw_op3) ); }
1259 1259  
1260 1260    // pp 168
1261 1261  
1262 1262    void illtrap( int const22a) { if (const22a != 0) v9_only();  emit_long( op(branch_op) | u_field(const22a, 21, 0) ); }
1263 1263    // v8 unimp == illtrap(0)
1264 1264  
1265 1265    // pp 169
1266 1266  
1267 1267    void impdep1( int id1, int const19a ) { v9_only();  emit_long( op(arith_op) | fcn(id1) | op3(impdep1_op3) | u_field(const19a, 18, 0)); }
1268 1268    void impdep2( int id1, int const19a ) { v9_only();  emit_long( op(arith_op) | fcn(id1) | op3(impdep2_op3) | u_field(const19a, 18, 0)); }
1269 1269  
1270 1270    // pp 149 (v8)
1271 1271  
1272 1272    void cpop1( int opc, int cr1, int cr2, int crd ) { v8_only();  emit_long( op(arith_op) | fcn(crd) | op3(impdep1_op3) | u_field(cr1, 18, 14) | opf(opc) | u_field(cr2, 4, 0)); }
1273 1273    void cpop2( int opc, int cr1, int cr2, int crd ) { v8_only();  emit_long( op(arith_op) | fcn(crd) | op3(impdep2_op3) | u_field(cr1, 18, 14) | opf(opc) | u_field(cr2, 4, 0)); }
1274 1274  
1275 1275    // pp 170
1276 1276  
1277 1277    void jmpl( Register s1, Register s2, Register d );
1278 1278    void jmpl( Register s1, int simm13a, Register d, RelocationHolder const& rspec = RelocationHolder() );
1279 1279  
1280 1280    // 171
1281 1281  
1282 1282    inline void ldf(FloatRegisterImpl::Width w, Register s1, RegisterOrConstant s2, FloatRegister d);
1283 1283    inline void ldf(FloatRegisterImpl::Width w, Register s1, Register s2, FloatRegister d);
1284 1284    inline void ldf(FloatRegisterImpl::Width w, Register s1, int simm13a, FloatRegister d, RelocationHolder const& rspec = RelocationHolder());
1285 1285  
1286 1286    inline void ldf(FloatRegisterImpl::Width w, const Address& a, FloatRegister d, int offset = 0);
1287 1287  
1288 1288  
1289 1289    inline void ldfsr(  Register s1, Register s2 );
1290 1290    inline void ldfsr(  Register s1, int simm13a);
1291 1291    inline void ldxfsr( Register s1, Register s2 );
1292 1292    inline void ldxfsr( Register s1, int simm13a);
1293 1293  
1294 1294    // pp 94 (v8)
1295 1295  
1296 1296    inline void ldc(   Register s1, Register s2, int crd );
1297 1297    inline void ldc(   Register s1, int simm13a, int crd);
1298 1298    inline void lddc(  Register s1, Register s2, int crd );
1299 1299    inline void lddc(  Register s1, int simm13a, int crd);
1300 1300    inline void ldcsr( Register s1, Register s2, int crd );
1301 1301    inline void ldcsr( Register s1, int simm13a, int crd);
1302 1302  
1303 1303  
1304 1304    // 173
1305 1305  
1306 1306    void ldfa(  FloatRegisterImpl::Width w, Register s1, Register s2, int ia, FloatRegister d ) { v9_only();  emit_long( op(ldst_op) | fd(d, w) | alt_op3(ldf_op3 | alt_bit_op3, w) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1307 1307    void ldfa(  FloatRegisterImpl::Width w, Register s1, int simm13a,         FloatRegister d ) { v9_only();  emit_long( op(ldst_op) | fd(d, w) | alt_op3(ldf_op3 | alt_bit_op3, w) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1308 1308  
1309 1309    // pp 175, lduw is ld on v8
1310 1310  
1311 1311    inline void ldsb(  Register s1, Register s2, Register d );
1312 1312    inline void ldsb(  Register s1, int simm13a, Register d);
1313 1313    inline void ldsh(  Register s1, Register s2, Register d );
1314 1314    inline void ldsh(  Register s1, int simm13a, Register d);
1315 1315    inline void ldsw(  Register s1, Register s2, Register d );
1316 1316    inline void ldsw(  Register s1, int simm13a, Register d);
1317 1317    inline void ldub(  Register s1, Register s2, Register d );
1318 1318    inline void ldub(  Register s1, int simm13a, Register d);
1319 1319    inline void lduh(  Register s1, Register s2, Register d );
1320 1320    inline void lduh(  Register s1, int simm13a, Register d);
1321 1321    inline void lduw(  Register s1, Register s2, Register d );
1322 1322    inline void lduw(  Register s1, int simm13a, Register d);
1323 1323    inline void ldx(   Register s1, Register s2, Register d );
1324 1324    inline void ldx(   Register s1, int simm13a, Register d);
1325 1325    inline void ld(    Register s1, Register s2, Register d );
1326 1326    inline void ld(    Register s1, int simm13a, Register d);
1327 1327    inline void ldd(   Register s1, Register s2, Register d );
1328 1328    inline void ldd(   Register s1, int simm13a, Register d);
1329 1329  
1330 1330  #ifdef ASSERT
1331 1331    // ByteSize is only a class when ASSERT is defined, otherwise it's an int.
1332 1332    inline void ld(    Register s1, ByteSize simm13a, Register d);
1333 1333  #endif
1334 1334  
1335 1335    inline void ldsb(const Address& a, Register d, int offset = 0);
1336 1336    inline void ldsh(const Address& a, Register d, int offset = 0);
1337 1337    inline void ldsw(const Address& a, Register d, int offset = 0);
1338 1338    inline void ldub(const Address& a, Register d, int offset = 0);
1339 1339    inline void lduh(const Address& a, Register d, int offset = 0);
1340 1340    inline void lduw(const Address& a, Register d, int offset = 0);
1341 1341    inline void ldx( const Address& a, Register d, int offset = 0);
1342 1342    inline void ld(  const Address& a, Register d, int offset = 0);
1343 1343    inline void ldd( const Address& a, Register d, int offset = 0);
1344 1344  
1345 1345    inline void ldub(  Register s1, RegisterOrConstant s2, Register d );
1346 1346    inline void ldsb(  Register s1, RegisterOrConstant s2, Register d );
1347 1347    inline void lduh(  Register s1, RegisterOrConstant s2, Register d );
1348 1348    inline void ldsh(  Register s1, RegisterOrConstant s2, Register d );
1349 1349    inline void lduw(  Register s1, RegisterOrConstant s2, Register d );
1350 1350    inline void ldsw(  Register s1, RegisterOrConstant s2, Register d );
1351 1351    inline void ldx(   Register s1, RegisterOrConstant s2, Register d );
1352 1352    inline void ld(    Register s1, RegisterOrConstant s2, Register d );
1353 1353    inline void ldd(   Register s1, RegisterOrConstant s2, Register d );
1354 1354  
1355 1355    // pp 177
1356 1356  
1357 1357    void ldsba(  Register s1, Register s2, int ia, Register d ) {             emit_long( op(ldst_op) | rd(d) | op3(ldsb_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1358 1358    void ldsba(  Register s1, int simm13a,         Register d ) {             emit_long( op(ldst_op) | rd(d) | op3(ldsb_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1359 1359    void ldsha(  Register s1, Register s2, int ia, Register d ) {             emit_long( op(ldst_op) | rd(d) | op3(ldsh_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1360 1360    void ldsha(  Register s1, int simm13a,         Register d ) {             emit_long( op(ldst_op) | rd(d) | op3(ldsh_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1361 1361    void ldswa(  Register s1, Register s2, int ia, Register d ) { v9_only();  emit_long( op(ldst_op) | rd(d) | op3(ldsw_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1362 1362    void ldswa(  Register s1, int simm13a,         Register d ) { v9_only();  emit_long( op(ldst_op) | rd(d) | op3(ldsw_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1363 1363    void lduba(  Register s1, Register s2, int ia, Register d ) {             emit_long( op(ldst_op) | rd(d) | op3(ldub_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1364 1364    void lduba(  Register s1, int simm13a,         Register d ) {             emit_long( op(ldst_op) | rd(d) | op3(ldub_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1365 1365    void lduha(  Register s1, Register s2, int ia, Register d ) {             emit_long( op(ldst_op) | rd(d) | op3(lduh_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1366 1366    void lduha(  Register s1, int simm13a,         Register d ) {             emit_long( op(ldst_op) | rd(d) | op3(lduh_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1367 1367    void lduwa(  Register s1, Register s2, int ia, Register d ) {             emit_long( op(ldst_op) | rd(d) | op3(lduw_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1368 1368    void lduwa(  Register s1, int simm13a,         Register d ) {             emit_long( op(ldst_op) | rd(d) | op3(lduw_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1369 1369    void ldxa(   Register s1, Register s2, int ia, Register d ) { v9_only();  emit_long( op(ldst_op) | rd(d) | op3(ldx_op3  | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1370 1370    void ldxa(   Register s1, int simm13a,         Register d ) { v9_only();  emit_long( op(ldst_op) | rd(d) | op3(ldx_op3  | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1371 1371    void ldda(   Register s1, Register s2, int ia, Register d ) { v9_dep();   emit_long( op(ldst_op) | rd(d) | op3(ldd_op3  | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1372 1372    void ldda(   Register s1, int simm13a,         Register d ) { v9_dep();   emit_long( op(ldst_op) | rd(d) | op3(ldd_op3  | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1373 1373  
1374 1374    // pp 179
1375 1375  

1376 1376    inline void ldstub(  Register s1, Register s2, Register d );
1377 1377    inline void ldstub(  Register s1, int simm13a, Register d);
1378 1378  
1379 1379    // pp 180
1380 1380  
1381 1381    void ldstuba( Register s1, Register s2, int ia, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(ldstub_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1382 1382    void ldstuba( Register s1, int simm13a,         Register d ) { emit_long( op(ldst_op) | rd(d) | op3(ldstub_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1383 1383  
1384 1384    // pp 181
1385 1385  
1386      -  void and3(     Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(and_op3               ) | rs1(s1) | rs2(s2) ); }
1387      -  void and3(     Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(and_op3               ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
     1386 +  void and3(    Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(and_op3              ) | rs1(s1) | rs2(s2) ); }
     1387 +  void and3(    Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(and_op3              ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1388 1388    void andcc(   Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(and_op3  | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
1389 1389    void andcc(   Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(and_op3  | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1390 1390    void andn(    Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(andn_op3             ) | rs1(s1) | rs2(s2) ); }
1391 1391    void andn(    Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(andn_op3             ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
     1392 +  void andn(    Register s1, RegisterOrConstant s2, Register d, int offset = 0);
1392 1393    void andncc(  Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(andn_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
1393 1394    void andncc(  Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(andn_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1394      -  void or3(      Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(or_op3               ) | rs1(s1) | rs2(s2) ); }
1395      -  void or3(      Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(or_op3               ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
     1395 +  void or3(     Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(or_op3               ) | rs1(s1) | rs2(s2) ); }
     1396 +  void or3(     Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(or_op3               ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1396 1397    void orcc(    Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(or_op3   | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
1397 1398    void orcc(    Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(or_op3   | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1398 1399    void orn(     Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(orn_op3) | rs1(s1) | rs2(s2) ); }
1399 1400    void orn(     Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(orn_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1400 1401    void orncc(   Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(orn_op3  | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
1401 1402    void orncc(   Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(orn_op3  | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1402      -  void xor3(     Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xor_op3              ) | rs1(s1) | rs2(s2) ); }
1403      -  void xor3(     Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xor_op3              ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
     1403 +  void xor3(    Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xor_op3              ) | rs1(s1) | rs2(s2) ); }
     1404 +  void xor3(    Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xor_op3              ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1404 1405    void xorcc(   Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xor_op3  | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
1405 1406    void xorcc(   Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xor_op3  | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1406 1407    void xnor(    Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xnor_op3             ) | rs1(s1) | rs2(s2) ); }
1407 1408    void xnor(    Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xnor_op3             ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1408 1409    void xnorcc(  Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xnor_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
1409 1410    void xnorcc(  Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xnor_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1410 1411  
1411 1412    // pp 183
1412 1413  
1413 1414    void membar( Membar_mask_bits const7a ) { v9_only(); emit_long( op(arith_op) | op3(membar_op3) | rs1(O7) | immed(true) | u_field( int(const7a), 6, 0)); }

1414 1415  
1415 1416    // pp 185
1416 1417  
1417 1418    void fmov( FloatRegisterImpl::Width w, Condition c,  bool floatCC, CC cca, FloatRegister s2, FloatRegister d ) { v9_only();  emit_long( op(arith_op) | fd(d, w) | op3(fpop2_op3) | cond_mov(c) | opf_cc(cca, floatCC) | opf_low6(w) | fs2(s2, w)); }
1418 1419  
1419 1420    // pp 189
1420 1421  
1421 1422    void fmov( FloatRegisterImpl::Width w, RCondition c, Register s1,  FloatRegister s2, FloatRegister d ) { v9_only();  emit_long( op(arith_op) | fd(d, w) | op3(fpop2_op3) | rs1(s1) | rcond(c) | opf_low5(4 + w) | fs2(s2, w)); }
1422 1423  
1423 1424    // pp 191
1424 1425  
1425 1426    void movcc( Condition c, bool floatCC, CC cca, Register s2, Register d ) { v9_only();  emit_long( op(arith_op) | rd(d) | op3(movcc_op3) | mov_cc(cca, floatCC) | cond_mov(c) | rs2(s2) ); }
1426 1427    void movcc( Condition c, bool floatCC, CC cca, int simm11a, Register d ) { v9_only();  emit_long( op(arith_op) | rd(d) | op3(movcc_op3) | mov_cc(cca, floatCC) | cond_mov(c) | immed(true) | simm(simm11a, 11) ); }
1427 1428  
1428 1429    // pp 195
1429 1430  
1430 1431    void movr( RCondition c, Register s1, Register s2,  Register d ) { v9_only();  emit_long( op(arith_op) | rd(d) | op3(movr_op3) | rs1(s1) | rcond(c) | rs2(s2) ); }
1431 1432    void movr( RCondition c, Register s1, int simm10a,  Register d ) { v9_only();  emit_long( op(arith_op) | rd(d) | op3(movr_op3) | rs1(s1) | rcond(c) | immed(true) | simm(simm10a, 10) ); }
1432 1433  
1433 1434    // pp 196
1434 1435  
1435 1436    void mulx(  Register s1, Register s2, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(mulx_op3 ) | rs1(s1) | rs2(s2) ); }
1436 1437    void mulx(  Register s1, int simm13a, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(mulx_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1437 1438    void sdivx( Register s1, Register s2, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(sdivx_op3) | rs1(s1) | rs2(s2) ); }
1438 1439    void sdivx( Register s1, int simm13a, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(sdivx_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1439 1440    void udivx( Register s1, Register s2, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(udivx_op3) | rs1(s1) | rs2(s2) ); }
1440 1441    void udivx( Register s1, int simm13a, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(udivx_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1441 1442  
1442 1443    // pp 197
1443 1444  
1444 1445    void umul(   Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(umul_op3             ) | rs1(s1) | rs2(s2) ); }
1445 1446    void umul(   Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(umul_op3             ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1446 1447    void smul(   Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(smul_op3             ) | rs1(s1) | rs2(s2) ); }
1447 1448    void smul(   Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(smul_op3             ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1448 1449    void umulcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(umul_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
1449 1450    void umulcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(umul_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1450 1451    void smulcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(smul_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
1451 1452    void smulcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(smul_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1452 1453  
1453 1454    // pp 199
1454 1455  
1455 1456    void mulscc(   Register s1, Register s2, Register d ) { v9_dep();  emit_long( op(arith_op) | rd(d) | op3(mulscc_op3) | rs1(s1) | rs2(s2) ); }
1456 1457    void mulscc(   Register s1, int simm13a, Register d ) { v9_dep();  emit_long( op(arith_op) | rd(d) | op3(mulscc_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1457 1458  
1458 1459    // pp 201
1459 1460  
1460 1461    void nop() { emit_long( op(branch_op) | op2(sethi_op2) ); }
1461 1462  
1462 1463  
1463 1464    // pp 202
1464 1465  
1465 1466    void popc( Register s,  Register d) { v9_only();  emit_long( op(arith_op) | rd(d) | op3(popc_op3) | rs2(s)); }
1466 1467    void popc( int simm13a, Register d) { v9_only();  emit_long( op(arith_op) | rd(d) | op3(popc_op3) | immed(true) | simm(simm13a, 13)); }
1467 1468  
1468 1469    // pp 203
1469 1470  
1470 1471    void prefetch(   Register s1, Register s2,         PrefetchFcn f);
1471 1472    void prefetch(   Register s1, int simm13a,         PrefetchFcn f);
1472 1473    void prefetcha(  Register s1, Register s2, int ia, PrefetchFcn f ) { v9_only();  emit_long( op(ldst_op) | fcn(f) | op3(prefetch_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1473 1474    void prefetcha(  Register s1, int simm13a,         PrefetchFcn f ) { v9_only();  emit_long( op(ldst_op) | fcn(f) | op3(prefetch_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1474 1475  
1475 1476    inline void prefetch(const Address& a, PrefetchFcn F, int offset = 0);
1476 1477  
1477 1478    // pp 208
1478 1479  
1479 1480    // not implementing read privileged register
1480 1481  
1481 1482    inline void rdy(    Register d) { v9_dep();  emit_long( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(0, 18, 14)); }
1482 1483    inline void rdccr(  Register d) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(2, 18, 14)); }
1483 1484    inline void rdasi(  Register d) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(3, 18, 14)); }
1484 1485    inline void rdtick( Register d) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(4, 18, 14)); } // Spoon!
1485 1486    inline void rdpc(   Register d) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(5, 18, 14)); }
1486 1487    inline void rdfprs( Register d) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(6, 18, 14)); }
1487 1488  
1488 1489    // pp 213
1489 1490  
1490 1491    inline void rett( Register s1, Register s2);
1491 1492    inline void rett( Register s1, int simm13a, relocInfo::relocType rt = relocInfo::none);
1492 1493  
1493 1494    // pp 214
1494 1495  
1495 1496    void save(    Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(save_op3) | rs1(s1) | rs2(s2) ); }
1496 1497    void save(    Register s1, int simm13a, Register d ) {
1497 1498      // make sure frame is at least large enough for the register save area
1498 1499      assert(-simm13a >= 16 * wordSize, "frame too small");
1499 1500      emit_long( op(arith_op) | rd(d) | op3(save_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) );
1500 1501    }
1501 1502  
1502 1503    void restore( Register s1 = G0,  Register s2 = G0, Register d = G0 ) { emit_long( op(arith_op) | rd(d) | op3(restore_op3) | rs1(s1) | rs2(s2) ); }
1503 1504    void restore( Register s1,       int simm13a,      Register d      ) { emit_long( op(arith_op) | rd(d) | op3(restore_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1504 1505  
1505 1506    // pp 216
1506 1507  
1507 1508    void saved()    { v9_only();  emit_long( op(arith_op) | fcn(0) | op3(saved_op3)); }
1508 1509    void restored() { v9_only();  emit_long( op(arith_op) | fcn(1) | op3(saved_op3)); }
1509 1510  
1510 1511    // pp 217
1511 1512  
1512 1513    inline void sethi( int imm22a, Register d, RelocationHolder const& rspec = RelocationHolder() );
1513 1514    // pp 218
1514 1515  
1515 1516    void sll(  Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sll_op3) | rs1(s1) | sx(0) | rs2(s2) ); }
1516 1517    void sll(  Register s1, int imm5a,   Register d ) { emit_long( op(arith_op) | rd(d) | op3(sll_op3) | rs1(s1) | sx(0) | immed(true) | u_field(imm5a, 4, 0) ); }
1517 1518    void srl(  Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(srl_op3) | rs1(s1) | sx(0) | rs2(s2) ); }
1518 1519    void srl(  Register s1, int imm5a,   Register d ) { emit_long( op(arith_op) | rd(d) | op3(srl_op3) | rs1(s1) | sx(0) | immed(true) | u_field(imm5a, 4, 0) ); }
1519 1520    void sra(  Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sra_op3) | rs1(s1) | sx(0) | rs2(s2) ); }
1520 1521    void sra(  Register s1, int imm5a,   Register d ) { emit_long( op(arith_op) | rd(d) | op3(sra_op3) | rs1(s1) | sx(0) | immed(true) | u_field(imm5a, 4, 0) ); }
1521 1522  
1522 1523    void sllx( Register s1, Register s2, Register d ) { v9_only();  emit_long( op(arith_op) | rd(d) | op3(sll_op3) | rs1(s1) | sx(1) | rs2(s2) ); }
1523 1524    void sllx( Register s1, int imm6a,   Register d ) { v9_only();  emit_long( op(arith_op) | rd(d) | op3(sll_op3) | rs1(s1) | sx(1) | immed(true) | u_field(imm6a, 5, 0) ); }
1524 1525    void srlx( Register s1, Register s2, Register d ) { v9_only();  emit_long( op(arith_op) | rd(d) | op3(srl_op3) | rs1(s1) | sx(1) | rs2(s2) ); }
1525 1526    void srlx( Register s1, int imm6a,   Register d ) { v9_only();  emit_long( op(arith_op) | rd(d) | op3(srl_op3) | rs1(s1) | sx(1) | immed(true) | u_field(imm6a, 5, 0) ); }
1526 1527    void srax( Register s1, Register s2, Register d ) { v9_only();  emit_long( op(arith_op) | rd(d) | op3(sra_op3) | rs1(s1) | sx(1) | rs2(s2) ); }
1527 1528    void srax( Register s1, int imm6a,   Register d ) { v9_only();  emit_long( op(arith_op) | rd(d) | op3(sra_op3) | rs1(s1) | sx(1) | immed(true) | u_field(imm6a, 5, 0) ); }
1528 1529  
1529 1530    // pp 220
1530 1531  
1531 1532    void sir( int simm13a ) { emit_long( op(arith_op) | fcn(15) | op3(sir_op3) | immed(true) | simm(simm13a, 13)); }
1532 1533  
1533 1534    // pp 221
1534 1535  
1535 1536    void stbar() { emit_long( op(arith_op) | op3(membar_op3) | u_field(15, 18, 14)); }
1536 1537  
1537 1538    // pp 222
1538 1539  
1539 1540    inline void stf(    FloatRegisterImpl::Width w, FloatRegister d, Register s1, RegisterOrConstant s2);
1540 1541    inline void stf(    FloatRegisterImpl::Width w, FloatRegister d, Register s1, Register s2);
1541 1542    inline void stf(    FloatRegisterImpl::Width w, FloatRegister d, Register s1, int simm13a);
1542 1543    inline void stf(    FloatRegisterImpl::Width w, FloatRegister d, const Address& a, int offset = 0);
1543 1544  
1544 1545    inline void stfsr(  Register s1, Register s2 );
1545 1546    inline void stfsr(  Register s1, int simm13a);
1546 1547    inline void stxfsr( Register s1, Register s2 );
1547 1548    inline void stxfsr( Register s1, int simm13a);
1548 1549  
1549 1550    //  pp 224
1550 1551  
1551 1552    void stfa(  FloatRegisterImpl::Width w, FloatRegister d, Register s1, Register s2, int ia ) { v9_only();  emit_long( op(ldst_op) | fd(d, w) | alt_op3(stf_op3 | alt_bit_op3, w) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1552 1553    void stfa(  FloatRegisterImpl::Width w, FloatRegister d, Register s1, int simm13a         ) { v9_only();  emit_long( op(ldst_op) | fd(d, w) | alt_op3(stf_op3 | alt_bit_op3, w) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1553 1554  
1554 1555    // p 226
1555 1556  
1556 1557    inline void stb(  Register d, Register s1, Register s2 );
1557 1558    inline void stb(  Register d, Register s1, int simm13a);
1558 1559    inline void sth(  Register d, Register s1, Register s2 );
1559 1560    inline void sth(  Register d, Register s1, int simm13a);
1560 1561    inline void stw(  Register d, Register s1, Register s2 );
1561 1562    inline void stw(  Register d, Register s1, int simm13a);
1562 1563    inline void st(   Register d, Register s1, Register s2 );
1563 1564    inline void st(   Register d, Register s1, int simm13a);
1564 1565    inline void stx(  Register d, Register s1, Register s2 );
1565 1566    inline void stx(  Register d, Register s1, int simm13a);
1566 1567    inline void std(  Register d, Register s1, Register s2 );
1567 1568    inline void std(  Register d, Register s1, int simm13a);
1568 1569  
1569 1570  #ifdef ASSERT
1570 1571    // ByteSize is only a class when ASSERT is defined, otherwise it's an int.
1571 1572    inline void st(   Register d, Register s1, ByteSize simm13a);
1572 1573  #endif
1573 1574  
1574 1575    inline void stb(  Register d, const Address& a, int offset = 0 );
1575 1576    inline void sth(  Register d, const Address& a, int offset = 0 );
1576 1577    inline void stw(  Register d, const Address& a, int offset = 0 );
1577 1578    inline void stx(  Register d, const Address& a, int offset = 0 );
1578 1579    inline void st(   Register d, const Address& a, int offset = 0 );
1579 1580    inline void std(  Register d, const Address& a, int offset = 0 );
1580 1581  
1581 1582    inline void stb(  Register d, Register s1, RegisterOrConstant s2 );
1582 1583    inline void sth(  Register d, Register s1, RegisterOrConstant s2 );
1583 1584    inline void stw(  Register d, Register s1, RegisterOrConstant s2 );
1584 1585    inline void stx(  Register d, Register s1, RegisterOrConstant s2 );
1585 1586    inline void std(  Register d, Register s1, RegisterOrConstant s2 );
1586 1587    inline void st(   Register d, Register s1, RegisterOrConstant s2 );
1587 1588  
1588 1589    // pp 177
1589 1590  
1590 1591    void stba(  Register d, Register s1, Register s2, int ia ) {             emit_long( op(ldst_op) | rd(d) | op3(stb_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1591 1592    void stba(  Register d, Register s1, int simm13a         ) {             emit_long( op(ldst_op) | rd(d) | op3(stb_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1592 1593    void stha(  Register d, Register s1, Register s2, int ia ) {             emit_long( op(ldst_op) | rd(d) | op3(sth_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1593 1594    void stha(  Register d, Register s1, int simm13a         ) {             emit_long( op(ldst_op) | rd(d) | op3(sth_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1594 1595    void stwa(  Register d, Register s1, Register s2, int ia ) {             emit_long( op(ldst_op) | rd(d) | op3(stw_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1595 1596    void stwa(  Register d, Register s1, int simm13a         ) {             emit_long( op(ldst_op) | rd(d) | op3(stw_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1596 1597    void stxa(  Register d, Register s1, Register s2, int ia ) { v9_only();  emit_long( op(ldst_op) | rd(d) | op3(stx_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1597 1598    void stxa(  Register d, Register s1, int simm13a         ) { v9_only();  emit_long( op(ldst_op) | rd(d) | op3(stx_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1598 1599    void stda(  Register d, Register s1, Register s2, int ia ) {             emit_long( op(ldst_op) | rd(d) | op3(std_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1599 1600    void stda(  Register d, Register s1, int simm13a         ) {             emit_long( op(ldst_op) | rd(d) | op3(std_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1600 1601  
1601 1602    // pp 97 (v8)
1602 1603  
1603 1604    inline void stc(   int crd, Register s1, Register s2 );
1604 1605    inline void stc(   int crd, Register s1, int simm13a);
1605 1606    inline void stdc(  int crd, Register s1, Register s2 );
1606 1607    inline void stdc(  int crd, Register s1, int simm13a);
1607 1608    inline void stcsr( int crd, Register s1, Register s2 );
1608 1609    inline void stcsr( int crd, Register s1, int simm13a);
1609 1610    inline void stdcq( int crd, Register s1, Register s2 );
1610 1611    inline void stdcq( int crd, Register s1, int simm13a);
1611 1612  
1612 1613    // pp 230
1613 1614  
1614 1615    void sub(    Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sub_op3              ) | rs1(s1) | rs2(s2) ); }
1615 1616    void sub(    Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sub_op3              ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1616 1617    void subcc(  Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sub_op3 | cc_bit_op3 ) | rs1(s1) | rs2(s2) ); }
1617 1618    void subcc(  Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sub_op3 | cc_bit_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1618 1619    void subc(   Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(subc_op3             ) | rs1(s1) | rs2(s2) ); }
1619 1620    void subc(   Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(subc_op3             ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1620 1621    void subccc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(subc_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
1621 1622    void subccc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(subc_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1622 1623  
1623 1624    // pp 231
1624 1625  
1625 1626    inline void swap( Register s1, Register s2, Register d );
1626 1627    inline void swap( Register s1, int simm13a, Register d);
1627 1628    inline void swap( Address& a,               Register d, int offset = 0 );
1628 1629  
1629 1630    // pp 232
1630 1631  
1631 1632    void swapa(   Register s1, Register s2, int ia, Register d ) { v9_dep();  emit_long( op(ldst_op) | rd(d) | op3(swap_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1632 1633    void swapa(   Register s1, int simm13a,         Register d ) { v9_dep();  emit_long( op(ldst_op) | rd(d) | op3(swap_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1633 1634  
1634 1635    // pp 234, note op in book is wrong, see pp 268
1635 1636  
1636 1637    void taddcc(    Register s1, Register s2, Register d ) {            emit_long( op(arith_op) | rd(d) | op3(taddcc_op3  ) | rs1(s1) | rs2(s2) ); }
1637 1638    void taddcc(    Register s1, int simm13a, Register d ) {            emit_long( op(arith_op) | rd(d) | op3(taddcc_op3  ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1638 1639    void taddcctv(  Register s1, Register s2, Register d ) { v9_dep();  emit_long( op(arith_op) | rd(d) | op3(taddcctv_op3) | rs1(s1) | rs2(s2) ); }
1639 1640    void taddcctv(  Register s1, int simm13a, Register d ) { v9_dep();  emit_long( op(arith_op) | rd(d) | op3(taddcctv_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1640 1641  
1641 1642    // pp 235
1642 1643  
1643 1644    void tsubcc(    Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(tsubcc_op3  ) | rs1(s1) | rs2(s2) ); }
1644 1645    void tsubcc(    Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(tsubcc_op3  ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1645 1646    void tsubcctv(  Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(tsubcctv_op3) | rs1(s1) | rs2(s2) ); }
1646 1647    void tsubcctv(  Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(tsubcctv_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1647 1648  
1648 1649    // pp 237
1649 1650  
1650 1651    void trap( Condition c, CC cc, Register s1, Register s2 ) { v8_no_cc(cc);  emit_long( op(arith_op) | cond(c) | op3(trap_op3) | rs1(s1) | trapcc(cc) | rs2(s2)); }
1651 1652    void trap( Condition c, CC cc, Register s1, int trapa   ) { v8_no_cc(cc);  emit_long( op(arith_op) | cond(c) | op3(trap_op3) | rs1(s1) | trapcc(cc) | immed(true) | u_field(trapa, 6, 0)); }
1652 1653    // simple uncond. trap
1653 1654    void trap( int trapa ) { trap( always, icc, G0, trapa ); }
1654 1655  
1655 1656    // pp 239 omit write priv register for now
1656 1657  
1657 1658    inline void wry(    Register d) { v9_dep();  emit_long( op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(0, 29, 25)); }
1658 1659    inline void wrccr(Register s) { v9_only(); emit_long( op(arith_op) | rs1(s) | op3(wrreg_op3) | u_field(2, 29, 25)); }
1659 1660    inline void wrccr(Register s, int simm13a) { v9_only(); emit_long( op(arith_op) |
1660 1661                                                                             rs1(s) |
1661 1662                                                                             op3(wrreg_op3) |
1662 1663                                                                             u_field(2, 29, 25) |
1663 1664                                                                             u_field(1, 13, 13) |
1664 1665                                                                             simm(simm13a, 13)); }
1665 1666    inline void wrasi(  Register d) { v9_only(); emit_long( op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(3, 29, 25)); }
1666 1667    inline void wrfprs( Register d) { v9_only(); emit_long( op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(6, 29, 25)); }
1667 1668  
1668 1669    // For a given register condition, return the appropriate condition code
1669 1670    // Condition (the one you would use to get the same effect after "tst" on
1670 1671    // the target register.)
1671 1672    Assembler::Condition reg_cond_to_cc_cond(RCondition in);
1672 1673  
1673 1674  
1674 1675    // Creation
1675 1676    Assembler(CodeBuffer* code) : AbstractAssembler(code) {
1676 1677  #ifdef CHECK_DELAY
1677 1678      delay_state = no_delay;
1678 1679  #endif
1679 1680    }
1680 1681  
1681 1682    // Testing
1682 1683  #ifndef PRODUCT
1683 1684    void test_v9();
1684 1685    void test_v8_onlys();
1685 1686  #endif
1686 1687  };
1687 1688  
1688 1689  
1689 1690  class RegistersForDebugging : public StackObj {
1690 1691   public:
1691 1692    intptr_t i[8], l[8], o[8], g[8];
1692 1693    float    f[32];
1693 1694    double   d[32];
1694 1695  
1695 1696    void print(outputStream* s);
1696 1697  
1697 1698    static int i_offset(int j) { return offset_of(RegistersForDebugging, i[j]); }
1698 1699    static int l_offset(int j) { return offset_of(RegistersForDebugging, l[j]); }
1699 1700    static int o_offset(int j) { return offset_of(RegistersForDebugging, o[j]); }
1700 1701    static int g_offset(int j) { return offset_of(RegistersForDebugging, g[j]); }
1701 1702    static int f_offset(int j) { return offset_of(RegistersForDebugging, f[j]); }
1702 1703    static int d_offset(int j) { return offset_of(RegistersForDebugging, d[j / 2]); }
1703 1704  
1704 1705    // gen asm code to save regs
1705 1706    static void save_registers(MacroAssembler* a);
1706 1707  
1707 1708    // restore global registers in case C code disturbed them
1708 1709    static void restore_registers(MacroAssembler* a, Register r);
1709 1710  
1710 1711  
1711 1712  };
1712 1713  
1713 1714  
1714 1715  // MacroAssembler extends Assembler by a few frequently used macros.
1715 1716  //
1716 1717  // Most of the standard SPARC synthetic ops are defined here.
1717 1718  // Instructions for which a 'better' code sequence exists depending
1718 1719  // on arguments should also go in here.
1719 1720  
1720 1721  #define JMP2(r1, r2) jmp(r1, r2, __FILE__, __LINE__)
1721 1722  #define JMP(r1, off) jmp(r1, off, __FILE__, __LINE__)
1722 1723  #define JUMP(a, temp, off)     jump(a, temp, off, __FILE__, __LINE__)
1723 1724  #define JUMPL(a, temp, d, off) jumpl(a, temp, d, off, __FILE__, __LINE__)
1724 1725  
1725 1726  
1726 1727  class MacroAssembler: public Assembler {
1727 1728   protected:
1728 1729    // Support for VM calls
1729 1730    // This is the base routine called by the different versions of call_VM_leaf. The interpreter
1730 1731    // may customize this version by overriding it for its purposes (e.g., to save/restore
1731 1732    // additional registers when doing a VM call).
1732 1733  #ifdef CC_INTERP
1733 1734    #define VIRTUAL
1734 1735  #else
1735 1736    #define VIRTUAL virtual
1736 1737  #endif
1737 1738  
1738 1739    VIRTUAL void call_VM_leaf_base(Register thread_cache, address entry_point, int number_of_arguments);
1739 1740  
1740 1741    //
1741 1742    // It is imperative that all calls into the VM are handled via the call_VM macros.
1742 1743    // They make sure that the stack linkage is setup correctly. call_VM's correspond
1743 1744    // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
1744 1745    //
1745 1746    // This is the base routine called by the different versions of call_VM. The interpreter
1746 1747    // may customize this version by overriding it for its purposes (e.g., to save/restore
1747 1748    // additional registers when doing a VM call).
1748 1749    //
1749 1750    // A non-volatile java_thread_cache register should be specified so
1750 1751    // that the G2_thread value can be preserved across the call.
1751 1752    // (If java_thread_cache is noreg, then a slow get_thread call
1752 1753    // will re-initialize the G2_thread.) call_VM_base returns the register that contains the
1753 1754    // thread.
1754 1755    //
1755 1756    // If no last_java_sp is specified (noreg) than SP will be used instead.
1756 1757  
1757 1758    virtual void call_VM_base(
1758 1759      Register        oop_result,             // where an oop-result ends up if any; use noreg otherwise
1759 1760      Register        java_thread_cache,      // the thread if computed before     ; use noreg otherwise
1760 1761      Register        last_java_sp,           // to set up last_Java_frame in stubs; use noreg otherwise
1761 1762      address         entry_point,            // the entry point
1762 1763      int             number_of_arguments,    // the number of arguments (w/o thread) to pop after call
1763 1764      bool            check_exception=true    // flag which indicates if exception should be checked
1764 1765    );
1765 1766  
1766 1767    // This routine should emit JVMTI PopFrame and ForceEarlyReturn handling code.
1767 1768    // The implementation is only non-empty for the InterpreterMacroAssembler,
1768 1769    // as only the interpreter handles and ForceEarlyReturn PopFrame requests.
1769 1770    virtual void check_and_handle_popframe(Register scratch_reg);
1770 1771    virtual void check_and_handle_earlyret(Register scratch_reg);
1771 1772  
1772 1773   public:
1773 1774    MacroAssembler(CodeBuffer* code) : Assembler(code) {}
1774 1775  
1775 1776    // Support for NULL-checks
1776 1777    //
1777 1778    // Generates code that causes a NULL OS exception if the content of reg is NULL.
1778 1779    // If the accessed location is M[reg + offset] and the offset is known, provide the
1779 1780    // offset.  No explicit code generation is needed if the offset is within a certain
1780 1781    // range (0 <= offset <= page_size).
1781 1782    //
1782 1783    // %%%%%% Currently not done for SPARC
1783 1784  
1784 1785    void null_check(Register reg, int offset = -1);
1785 1786    static bool needs_explicit_null_check(intptr_t offset);
1786 1787  
1787 1788    // support for delayed instructions
1788 1789    MacroAssembler* delayed() { Assembler::delayed();  return this; }
1789 1790  
1790 1791    // branches that use right instruction for v8 vs. v9
1791 1792    inline void br( Condition c, bool a, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
1792 1793    inline void br( Condition c, bool a, Predict p, Label& L );
1793 1794    inline void fb( Condition c, bool a, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
1794 1795    inline void fb( Condition c, bool a, Predict p, Label& L );
1795 1796  
1796 1797    // compares register with zero and branches (V9 and V8 instructions)
1797 1798    void br_zero( Condition c, bool a, Predict p, Register s1, Label& L);
1798 1799    // Compares a pointer register with zero and branches on (not)null.
1799 1800    // Does a test & branch on 32-bit systems and a register-branch on 64-bit.
1800 1801    void br_null   ( Register s1, bool a, Predict p, Label& L );
1801 1802    void br_notnull( Register s1, bool a, Predict p, Label& L );
1802 1803  
1803 1804    // These versions will do the most efficient thing on v8 and v9.  Perhaps
1804 1805    // this is what the routine above was meant to do, but it didn't (and
1805 1806    // didn't cover both target address kinds.)
1806 1807    void br_on_reg_cond( RCondition c, bool a, Predict p, Register s1, address d, relocInfo::relocType rt = relocInfo::none );
1807 1808    void br_on_reg_cond( RCondition c, bool a, Predict p, Register s1, Label& L);
1808 1809  
1809 1810    inline void bp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
1810 1811    inline void bp( Condition c, bool a, CC cc, Predict p, Label& L );
1811 1812  
1812 1813    // Branch that tests xcc in LP64 and icc in !LP64
1813 1814    inline void brx( Condition c, bool a, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
1814 1815    inline void brx( Condition c, bool a, Predict p, Label& L );
1815 1816  
1816 1817    // unconditional short branch
1817 1818    inline void ba( bool a, Label& L );
1818 1819  
1819 1820    // Branch that tests fp condition codes
1820 1821    inline void fbp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
1821 1822    inline void fbp( Condition c, bool a, CC cc, Predict p, Label& L );
1822 1823  
1823 1824    // get PC the best way
1824 1825    inline int get_pc( Register d );
1825 1826  
1826 1827    // Sparc shorthands(pp 85, V8 manual, pp 289 V9 manual)
1827 1828    inline void cmp(  Register s1, Register s2 ) { subcc( s1, s2, G0 ); }
1828 1829    inline void cmp(  Register s1, int simm13a ) { subcc( s1, simm13a, G0 ); }
1829 1830  
1830 1831    inline void jmp( Register s1, Register s2 );
1831 1832    inline void jmp( Register s1, int simm13a, RelocationHolder const& rspec = RelocationHolder() );
1832 1833  
1833 1834    inline void call( address d,  relocInfo::relocType rt = relocInfo::runtime_call_type );
1834 1835    inline void call( Label& L,   relocInfo::relocType rt = relocInfo::runtime_call_type );
1835 1836    inline void callr( Register s1, Register s2 );
1836 1837    inline void callr( Register s1, int simm13a, RelocationHolder const& rspec = RelocationHolder() );
1837 1838  
1838 1839    // Emits nothing on V8
1839 1840    inline void iprefetch( address d, relocInfo::relocType rt = relocInfo::none );
1840 1841    inline void iprefetch( Label& L);
1841 1842  
1842 1843    inline void tst( Register s ) { orcc( G0, s, G0 ); }
1843 1844  
1844 1845  #ifdef PRODUCT
1845 1846    inline void ret(  bool trace = TraceJumps )   { if (trace) {
1846 1847                                                      mov(I7, O7); // traceable register
1847 1848                                                      JMP(O7, 2 * BytesPerInstWord);
1848 1849                                                    } else {
1849 1850                                                      jmpl( I7, 2 * BytesPerInstWord, G0 );
1850 1851                                                    }
1851 1852                                                  }
1852 1853  
1853 1854    inline void retl( bool trace = TraceJumps )  { if (trace) JMP(O7, 2 * BytesPerInstWord);
1854 1855                                                   else jmpl( O7, 2 * BytesPerInstWord, G0 ); }
1855 1856  #else
1856 1857    void ret(  bool trace = TraceJumps );
1857 1858    void retl( bool trace = TraceJumps );
1858 1859  #endif /* PRODUCT */
1859 1860  
1860 1861    // Required platform-specific helpers for Label::patch_instructions.
1861 1862    // They _shadow_ the declarations in AbstractAssembler, which are undefined.
1862 1863    void pd_patch_instruction(address branch, address target);
1863 1864  #ifndef PRODUCT
1864 1865    static void pd_print_patched_instruction(address branch);
1865 1866  #endif
1866 1867  
1867 1868    // sethi Macro handles optimizations and relocations
1868 1869  private:
1869 1870    void internal_sethi(const AddressLiteral& addrlit, Register d, bool ForceRelocatable);
1870 1871  public:
1871 1872    void sethi(const AddressLiteral& addrlit, Register d);
1872 1873    void patchable_sethi(const AddressLiteral& addrlit, Register d);
1873 1874  
1874 1875    // compute the size of a sethi/set
1875 1876    static int  size_of_sethi( address a, bool worst_case = false );
1876 1877    static int  worst_case_size_of_set();
1877 1878  
1878 1879    // set may be either setsw or setuw (high 32 bits may be zero or sign)
1879 1880  private:
1880 1881    void internal_set(const AddressLiteral& al, Register d, bool ForceRelocatable);
1881 1882  public:
1882 1883    void set(const AddressLiteral& addrlit, Register d);
1883 1884    void set(intptr_t value, Register d);
1884 1885    void set(address addr, Register d, RelocationHolder const& rspec);
1885 1886    void patchable_set(const AddressLiteral& addrlit, Register d);
1886 1887    void patchable_set(intptr_t value, Register d);
1887 1888    void set64(jlong value, Register d, Register tmp);
1888 1889  
1889 1890    // sign-extend 32 to 64
1890 1891    inline void signx( Register s, Register d ) { sra( s, G0, d); }
1891 1892    inline void signx( Register d )             { sra( d, G0, d); }
1892 1893  
1893 1894    inline void not1( Register s, Register d ) { xnor( s, G0, d ); }
1894 1895    inline void not1( Register d )             { xnor( d, G0, d ); }
1895 1896  
1896 1897    inline void neg( Register s, Register d ) { sub( G0, s, d ); }
1897 1898    inline void neg( Register d )             { sub( G0, d, d ); }
1898 1899  
1899 1900    inline void cas(  Register s1, Register s2, Register d) { casa( s1, s2, d, ASI_PRIMARY); }
1900 1901    inline void casx( Register s1, Register s2, Register d) { casxa(s1, s2, d, ASI_PRIMARY); }
1901 1902    // Functions for isolating 64 bit atomic swaps for LP64
1902 1903    // cas_ptr will perform cas for 32 bit VM's and casx for 64 bit VM's
1903 1904    inline void cas_ptr(  Register s1, Register s2, Register d) {
1904 1905  #ifdef _LP64
1905 1906      casx( s1, s2, d );
1906 1907  #else
1907 1908      cas( s1, s2, d );
1908 1909  #endif
1909 1910    }
1910 1911  
1911 1912    // Functions for isolating 64 bit shifts for LP64
1912 1913    inline void sll_ptr( Register s1, Register s2, Register d );
1913 1914    inline void sll_ptr( Register s1, int imm6a,   Register d );
1914 1915    inline void sll_ptr( Register s1, RegisterOrConstant s2, Register d );
1915 1916    inline void srl_ptr( Register s1, Register s2, Register d );
1916 1917    inline void srl_ptr( Register s1, int imm6a,   Register d );
1917 1918  
1918 1919    // little-endian
1919 1920    inline void casl(  Register s1, Register s2, Register d) { casa( s1, s2, d, ASI_PRIMARY_LITTLE); }
1920 1921    inline void casxl( Register s1, Register s2, Register d) { casxa(s1, s2, d, ASI_PRIMARY_LITTLE); }
1921 1922  
1922 1923    inline void inc(   Register d,  int const13 = 1 ) { add(   d, const13, d); }
1923 1924    inline void inccc( Register d,  int const13 = 1 ) { addcc( d, const13, d); }
1924 1925  
1925 1926    inline void dec(   Register d,  int const13 = 1 ) { sub(   d, const13, d); }
1926 1927    inline void deccc( Register d,  int const13 = 1 ) { subcc( d, const13, d); }
1927 1928  
1928 1929    inline void btst( Register s1,  Register s2 ) { andcc( s1, s2, G0 ); }
1929 1930    inline void btst( int simm13a,  Register s )  { andcc( s,  simm13a, G0 ); }
1930 1931  
1931 1932    inline void bset( Register s1,  Register s2 ) { or3( s1, s2, s2 ); }
1932 1933    inline void bset( int simm13a,  Register s )  { or3( s,  simm13a, s ); }
1933 1934  
1934 1935    inline void bclr( Register s1,  Register s2 ) { andn( s1, s2, s2 ); }
1935 1936    inline void bclr( int simm13a,  Register s )  { andn( s,  simm13a, s ); }
1936 1937  
1937 1938    inline void btog( Register s1,  Register s2 ) { xor3( s1, s2, s2 ); }
1938 1939    inline void btog( int simm13a,  Register s )  { xor3( s,  simm13a, s ); }
1939 1940  
1940 1941    inline void clr( Register d ) { or3( G0, G0, d ); }
1941 1942  
1942 1943    inline void clrb( Register s1, Register s2);
1943 1944    inline void clrh( Register s1, Register s2);
1944 1945    inline void clr(  Register s1, Register s2);
1945 1946    inline void clrx( Register s1, Register s2);
1946 1947  
1947 1948    inline void clrb( Register s1, int simm13a);
1948 1949    inline void clrh( Register s1, int simm13a);
1949 1950    inline void clr(  Register s1, int simm13a);
1950 1951    inline void clrx( Register s1, int simm13a);
1951 1952  
1952 1953    // copy & clear upper word
1953 1954    inline void clruw( Register s, Register d ) { srl( s, G0, d); }
1954 1955    // clear upper word
1955 1956    inline void clruwu( Register d ) { srl( d, G0, d); }
1956 1957  
1957 1958    // membar psuedo instruction.  takes into account target memory model.
1958 1959    inline void membar( Assembler::Membar_mask_bits const7a );
1959 1960  
1960 1961    // returns if membar generates anything.
1961 1962    inline bool membar_has_effect( Assembler::Membar_mask_bits const7a );
1962 1963  
1963 1964    // mov pseudo instructions
1964 1965    inline void mov( Register s,  Register d) {
1965 1966      if ( s != d )    or3( G0, s, d);
1966 1967      else             assert_not_delayed();  // Put something useful in the delay slot!
1967 1968    }
1968 1969  
1969 1970    inline void mov_or_nop( Register s,  Register d) {
1970 1971      if ( s != d )    or3( G0, s, d);
1971 1972      else             nop();
1972 1973    }
1973 1974  
1974 1975    inline void mov( int simm13a, Register d) { or3( G0, simm13a, d); }
1975 1976  
1976 1977    // address pseudos: make these names unlike instruction names to avoid confusion
1977 1978    inline intptr_t load_pc_address( Register reg, int bytes_to_skip );
1978 1979    inline void load_contents(AddressLiteral& addrlit, Register d, int offset = 0);
1979 1980    inline void load_ptr_contents(AddressLiteral& addrlit, Register d, int offset = 0);
1980 1981    inline void store_contents(Register s, AddressLiteral& addrlit, Register temp, int offset = 0);
1981 1982    inline void store_ptr_contents(Register s, AddressLiteral& addrlit, Register temp, int offset = 0);
1982 1983    inline void jumpl_to(AddressLiteral& addrlit, Register temp, Register d, int offset = 0);
1983 1984    inline void jump_to(AddressLiteral& addrlit, Register temp, int offset = 0);
1984 1985    inline void jump_indirect_to(Address& a, Register temp, int ld_offset = 0, int jmp_offset = 0);
1985 1986  
1986 1987    // ring buffer traceable jumps
1987 1988  
1988 1989    void jmp2( Register r1, Register r2, const char* file, int line );
1989 1990    void jmp ( Register r1, int offset,  const char* file, int line );
1990 1991  
1991 1992    void jumpl(AddressLiteral& addrlit, Register temp, Register d, int offset, const char* file, int line);
1992 1993    void jump (AddressLiteral& addrlit, Register temp,             int offset, const char* file, int line);
1993 1994  
1994 1995  
1995 1996    // argument pseudos:
1996 1997  
1997 1998    inline void load_argument( Argument& a, Register  d );
1998 1999    inline void store_argument( Register s, Argument& a );
1999 2000    inline void store_ptr_argument( Register s, Argument& a );
2000 2001    inline void store_float_argument( FloatRegister s, Argument& a );
2001 2002    inline void store_double_argument( FloatRegister s, Argument& a );
2002 2003    inline void store_long_argument( Register s, Argument& a );
2003 2004  
2004 2005    // handy macros:
2005 2006  
2006 2007    inline void round_to( Register r, int modulus ) {
2007 2008      assert_not_delayed();
2008 2009      inc( r, modulus - 1 );
2009 2010      and3( r, -modulus, r );
2010 2011    }
2011 2012  
2012 2013    // --------------------------------------------------
2013 2014  
2014 2015    // Functions for isolating 64 bit loads for LP64
2015 2016    // ld_ptr will perform ld for 32 bit VM's and ldx for 64 bit VM's
2016 2017    // st_ptr will perform st for 32 bit VM's and stx for 64 bit VM's
2017 2018    inline void ld_ptr(Register s1, Register s2, Register d);
2018 2019    inline void ld_ptr(Register s1, int simm13a, Register d);
2019 2020    inline void ld_ptr(Register s1, RegisterOrConstant s2, Register d);
2020 2021    inline void ld_ptr(const Address& a, Register d, int offset = 0);
2021 2022    inline void st_ptr(Register d, Register s1, Register s2);

2022 2023    inline void st_ptr(Register d, Register s1, int simm13a);
2023 2024    inline void st_ptr(Register d, Register s1, RegisterOrConstant s2);
2024 2025    inline void st_ptr(Register d, const Address& a, int offset = 0);
2025 2026  
2026 2027  #ifdef ASSERT
2027 2028    // ByteSize is only a class when ASSERT is defined, otherwise it's an int.
2028 2029    inline void ld_ptr(Register s1, ByteSize simm13a, Register d);
2029 2030    inline void st_ptr(Register d, Register s1, ByteSize simm13a);
2030 2031  #endif
2031 2032  
2032      -  // ld_long will perform ld for 32 bit VM's and ldx for 64 bit VM's
2033      -  // st_long will perform st for 32 bit VM's and stx for 64 bit VM's
     2033 +  // ld_long will perform ldd for 32 bit VM's and ldx for 64 bit VM's
     2034 +  // st_long will perform std for 32 bit VM's and stx for 64 bit VM's
2034 2035    inline void ld_long(Register s1, Register s2, Register d);
2035 2036    inline void ld_long(Register s1, int simm13a, Register d);
2036 2037    inline void ld_long(Register s1, RegisterOrConstant s2, Register d);
2037 2038    inline void ld_long(const Address& a, Register d, int offset = 0);
2038 2039    inline void st_long(Register d, Register s1, Register s2);
2039 2040    inline void st_long(Register d, Register s1, int simm13a);
2040 2041    inline void st_long(Register d, Register s1, RegisterOrConstant s2);
2041 2042    inline void st_long(Register d, const Address& a, int offset = 0);
2042 2043  
2043 2044    // Helpers for address formation.
2044      -  // They update the dest in place, whether it is a register or constant.
2045      -  // They emit no code at all if src is a constant zero.
2046      -  // If dest is a constant and src is a register, the temp argument
2047      -  // is required, and becomes the result.
2048      -  // If dest is a register and src is a non-simm13 constant,
2049      -  // the temp argument is required, and is used to materialize the constant.
2050      -  void regcon_inc_ptr( RegisterOrConstant& dest, RegisterOrConstant src,
2051      -                       Register temp = noreg );
2052      -  void regcon_sll_ptr( RegisterOrConstant& dest, RegisterOrConstant src,
2053      -                       Register temp = noreg );
2054      -
2055      -  RegisterOrConstant ensure_simm13_or_reg(RegisterOrConstant roc, Register Rtemp) {
2056      -    guarantee(Rtemp != noreg, "constant offset overflow");
2057      -    if (is_simm13(roc.constant_or_zero()))
2058      -      return roc;               // register or short constant
2059      -    set(roc.as_constant(), Rtemp);
2060      -    return RegisterOrConstant(Rtemp);
     2045 +  // - They emit only a move if s2 is a constant zero.
     2046 +  // - If dest is a constant and either s1 or s2 is a register, the temp argument is required and becomes the result.
     2047 +  // - If dest is a register and either s1 or s2 is a non-simm13 constant, the temp argument is required and used to materialize the constant.
     2048 +  RegisterOrConstant regcon_andn_ptr(RegisterOrConstant s1, RegisterOrConstant s2, RegisterOrConstant d, Register temp = noreg);
     2049 +  RegisterOrConstant regcon_inc_ptr( RegisterOrConstant s1, RegisterOrConstant s2, RegisterOrConstant d, Register temp = noreg);
     2050 +  RegisterOrConstant regcon_sll_ptr( RegisterOrConstant s1, RegisterOrConstant s2, RegisterOrConstant d, Register temp = noreg);
     2051 +
     2052 +  RegisterOrConstant ensure_simm13_or_reg(RegisterOrConstant src, Register temp) {
     2053 +    if (is_simm13(src.constant_or_zero()))
     2054 +      return src;               // register or short constant
     2055 +    guarantee(temp != noreg, "constant offset overflow");
     2056 +    set(src.as_constant(), temp);
     2057 +    return temp;
2061 2058    }
2062 2059  
2063 2060    // --------------------------------------------------
2064 2061  
2065 2062   public:
2066 2063    // traps as per trap.h (SPARC ABI?)
2067 2064  
2068 2065    void breakpoint_trap();
2069 2066    void breakpoint_trap(Condition c, CC cc = icc);
2070 2067    void flush_windows_trap();

2071 2068    void clean_windows_trap();
2072 2069    void get_psr_trap();
2073 2070    void set_psr_trap();
2074 2071  
2075 2072    // V8/V9 flush_windows
2076 2073    void flush_windows();
2077 2074  
2078 2075    // Support for serializing memory accesses between threads
2079 2076    void serialize_memory(Register thread, Register tmp1, Register tmp2);
2080 2077  
2081 2078    // Stack frame creation/removal
2082 2079    void enter();
2083 2080    void leave();
2084 2081  
2085 2082    // V8/V9 integer multiply
2086 2083    void mult(Register s1, Register s2, Register d);
2087 2084    void mult(Register s1, int simm13a, Register d);
2088 2085  
2089 2086    // V8/V9 read and write of condition codes.
2090 2087    void read_ccr(Register d);
2091 2088    void write_ccr(Register s);
2092 2089  
2093 2090    // Manipulation of C++ bools
2094 2091    // These are idioms to flag the need for care with accessing bools but on
2095 2092    // this platform we assume byte size
2096 2093  
2097 2094    inline void stbool(Register d, const Address& a) { stb(d, a); }
2098 2095    inline void ldbool(const Address& a, Register d) { ldsb(a, d); }
2099 2096    inline void tstbool( Register s ) { tst(s); }
2100 2097    inline void movbool( bool boolconst, Register d) { mov( (int) boolconst, d); }
2101 2098  
2102 2099    // klass oop manipulations if compressed
2103 2100    void load_klass(Register src_oop, Register klass);
2104 2101    void store_klass(Register klass, Register dst_oop);
2105 2102    void store_klass_gap(Register s, Register dst_oop);
2106 2103  
2107 2104     // oop manipulations
2108 2105    void load_heap_oop(const Address& s, Register d);
2109 2106    void load_heap_oop(Register s1, Register s2, Register d);
2110 2107    void load_heap_oop(Register s1, int simm13a, Register d);
2111 2108    void store_heap_oop(Register d, Register s1, Register s2);
2112 2109    void store_heap_oop(Register d, Register s1, int simm13a);
2113 2110    void store_heap_oop(Register d, const Address& a, int offset = 0);
2114 2111  
2115 2112    void encode_heap_oop(Register src, Register dst);
2116 2113    void encode_heap_oop(Register r) {
2117 2114      encode_heap_oop(r, r);
2118 2115    }
2119 2116    void decode_heap_oop(Register src, Register dst);
2120 2117    void decode_heap_oop(Register r) {
2121 2118      decode_heap_oop(r, r);
2122 2119    }
2123 2120    void encode_heap_oop_not_null(Register r);
2124 2121    void decode_heap_oop_not_null(Register r);
2125 2122    void encode_heap_oop_not_null(Register src, Register dst);
2126 2123    void decode_heap_oop_not_null(Register src, Register dst);
2127 2124  
2128 2125    // Support for managing the JavaThread pointer (i.e.; the reference to
2129 2126    // thread-local information).
2130 2127    void get_thread();                                // load G2_thread
2131 2128    void verify_thread();                             // verify G2_thread contents
2132 2129    void save_thread   (const Register threache); // save to cache
2133 2130    void restore_thread(const Register thread_cache); // restore from cache
2134 2131  
2135 2132    // Support for last Java frame (but use call_VM instead where possible)
2136 2133    void set_last_Java_frame(Register last_java_sp, Register last_Java_pc);
2137 2134    void reset_last_Java_frame(void);
2138 2135  
2139 2136    // Call into the VM.
2140 2137    // Passes the thread pointer (in O0) as a prepended argument.
2141 2138    // Makes sure oop return values are visible to the GC.
2142 2139    void call_VM(Register oop_result, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
2143 2140    void call_VM(Register oop_result, address entry_point, Register arg_1, bool check_exceptions = true);
2144 2141    void call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
2145 2142    void call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
2146 2143  
2147 2144    // these overloadings are not presently used on SPARC:
2148 2145    void call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
2149 2146    void call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
2150 2147    void call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
2151 2148    void call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
2152 2149  
2153 2150    void call_VM_leaf(Register thread_cache, address entry_point, int number_of_arguments = 0);
2154 2151    void call_VM_leaf(Register thread_cache, address entry_point, Register arg_1);
2155 2152    void call_VM_leaf(Register thread_cache, address entry_point, Register arg_1, Register arg_2);
2156 2153    void call_VM_leaf(Register thread_cache, address entry_point, Register arg_1, Register arg_2, Register arg_3);
2157 2154  
2158 2155    void get_vm_result  (Register oop_result);
2159 2156    void get_vm_result_2(Register oop_result);
2160 2157  
2161 2158    // vm result is currently getting hijacked to for oop preservation
2162 2159    void set_vm_result(Register oop_result);
2163 2160  
2164 2161    // if call_VM_base was called with check_exceptions=false, then call
2165 2162    // check_and_forward_exception to handle exceptions when it is safe
2166 2163    void check_and_forward_exception(Register scratch_reg);
2167 2164  
2168 2165   private:
2169 2166    // For V8
2170 2167    void read_ccr_trap(Register ccr_save);
2171 2168    void write_ccr_trap(Register ccr_save1, Register scratch1, Register scratch2);
2172 2169  
2173 2170  #ifdef ASSERT
2174 2171    // For V8 debugging.  Uses V8 instruction sequence and checks
2175 2172    // result with V9 insturctions rdccr and wrccr.
2176 2173    // Uses Gscatch and Gscatch2
2177 2174    void read_ccr_v8_assert(Register ccr_save);
2178 2175    void write_ccr_v8_assert(Register ccr_save);
2179 2176  #endif // ASSERT
2180 2177  
2181 2178   public:
2182 2179  
2183 2180    // Write to card table for - register is destroyed afterwards.
2184 2181    void card_table_write(jbyte* byte_map_base, Register tmp, Register obj);
2185 2182  
2186 2183    void card_write_barrier_post(Register store_addr, Register new_val, Register tmp);
2187 2184  
2188 2185  #ifndef SERIALGC
2189 2186    // Array store and offset
2190 2187    void g1_write_barrier_pre(Register obj, Register index, int offset, Register tmp, bool preserve_o_regs);
2191 2188  
2192 2189    void g1_write_barrier_post(Register store_addr, Register new_val, Register tmp);
2193 2190  
2194 2191    // May do filtering, depending on the boolean arguments.
2195 2192    void g1_card_table_write(jbyte* byte_map_base,
2196 2193                             Register tmp, Register obj, Register new_val,
2197 2194                             bool region_filter, bool null_filter);
2198 2195  #endif // SERIALGC
2199 2196  
2200 2197    // pushes double TOS element of FPU stack on CPU stack; pops from FPU stack
2201 2198    void push_fTOS();
2202 2199  
2203 2200    // pops double TOS element from CPU stack and pushes on FPU stack
2204 2201    void pop_fTOS();
2205 2202  
2206 2203    void empty_FPU_stack();
2207 2204  
2208 2205    void push_IU_state();
2209 2206    void pop_IU_state();
2210 2207  
2211 2208    void push_FPU_state();
2212 2209    void pop_FPU_state();
2213 2210  
2214 2211    void push_CPU_state();
2215 2212    void pop_CPU_state();
2216 2213  
2217 2214    // if heap base register is used - reinit it with the correct value
2218 2215    void reinit_heapbase();
2219 2216  
2220 2217    // Debugging
2221 2218    void _verify_oop(Register reg, const char * msg, const char * file, int line);
2222 2219    void _verify_oop_addr(Address addr, const char * msg, const char * file, int line);
2223 2220  
2224 2221  #define verify_oop(reg) _verify_oop(reg, "broken oop " #reg, __FILE__, __LINE__)
2225 2222  #define verify_oop_addr(addr) _verify_oop_addr(addr, "broken oop addr ", __FILE__, __LINE__)
2226 2223  
2227 2224          // only if +VerifyOops
2228 2225    void verify_FPU(int stack_depth, const char* s = "illegal FPU state");
2229 2226          // only if +VerifyFPU
2230 2227    void stop(const char* msg);                          // prints msg, dumps registers and stops execution
2231 2228    void warn(const char* msg);                          // prints msg, but don't stop
2232 2229    void untested(const char* what = "");
2233 2230    void unimplemented(const char* what = "")              { char* b = new char[1024];  sprintf(b, "unimplemented: %s", what);  stop(b); }
2234 2231    void should_not_reach_here()                   { stop("should not reach here"); }
2235 2232    void print_CPU_state();
2236 2233  
2237 2234    // oops in code
2238 2235    AddressLiteral allocate_oop_address(jobject obj);                          // allocate_index
2239 2236    AddressLiteral constant_oop_address(jobject obj);                          // find_index
2240 2237    inline void    set_oop             (jobject obj, Register d);              // uses allocate_oop_address
2241 2238    inline void    set_oop_constant    (jobject obj, Register d);              // uses constant_oop_address
2242 2239    inline void    set_oop             (AddressLiteral& obj_addr, Register d); // same as load_address
2243 2240  
2244 2241    void set_narrow_oop( jobject obj, Register d );
2245 2242  
2246 2243    // nop padding
2247 2244    void align(int modulus);
2248 2245  
2249 2246    // declare a safepoint
2250 2247    void safepoint();
2251 2248  
2252 2249    // factor out part of stop into subroutine to save space
2253 2250    void stop_subroutine();
2254 2251    // factor out part of verify_oop into subroutine to save space
2255 2252    void verify_oop_subroutine();
2256 2253  
2257 2254    // side-door communication with signalHandler in os_solaris.cpp
2258 2255    static address _verify_oop_implicit_branch[3];
2259 2256  
2260 2257  #ifndef PRODUCT
2261 2258    static void test();
2262 2259  #endif
2263 2260  
2264 2261    // convert an incoming arglist to varargs format; put the pointer in d
2265 2262    void set_varargs( Argument a, Register d );
2266 2263  
2267 2264    int total_frame_size_in_bytes(int extraWords);
2268 2265  
2269 2266    // used when extraWords known statically
2270 2267    void save_frame(int extraWords);
2271 2268    void save_frame_c1(int size_in_bytes);
2272 2269    // make a frame, and simultaneously pass up one or two register value
2273 2270    // into the new register window
2274 2271    void save_frame_and_mov(int extraWords, Register s1, Register d1, Register s2 = Register(), Register d2 = Register());
2275 2272  
2276 2273    // give no. (outgoing) params, calc # of words will need on frame
2277 2274    void calc_mem_param_words(Register Rparam_words, Register Rresult);
2278 2275  
2279 2276    // used to calculate frame size dynamically
2280 2277    // result is in bytes and must be negated for save inst
2281 2278    void calc_frame_size(Register extraWords, Register resultReg);
2282 2279  
2283 2280    // calc and also save
2284 2281    void calc_frame_size_and_save(Register extraWords, Register resultReg);
2285 2282  
2286 2283    static void debug(char* msg, RegistersForDebugging* outWindow);
2287 2284  
2288 2285    // implementations of bytecodes used by both interpreter and compiler
2289 2286  
2290 2287    void lcmp( Register Ra_hi, Register Ra_low,
2291 2288               Register Rb_hi, Register Rb_low,
2292 2289               Register Rresult);
2293 2290  
2294 2291    void lneg( Register Rhi, Register Rlow );
2295 2292  
2296 2293    void lshl(  Register Rin_high,  Register Rin_low,  Register Rcount,
2297 2294                Register Rout_high, Register Rout_low, Register Rtemp );
2298 2295  

2299 2296    void lshr(  Register Rin_high,  Register Rin_low,  Register Rcount,
2300 2297                Register Rout_high, Register Rout_low, Register Rtemp );
2301 2298  
2302 2299    void lushr( Register Rin_high,  Register Rin_low,  Register Rcount,
2303 2300                Register Rout_high, Register Rout_low, Register Rtemp );
2304 2301  
2305 2302  #ifdef _LP64
2306 2303    void lcmp( Register Ra, Register Rb, Register Rresult);
2307 2304  #endif
2308 2305  
     2306 +  // Loading values by size and signed-ness
     2307 +  void load_sized_value(Address src, Register dst, int size_in_bytes, bool is_signed);
     2308 +
2309 2309    void float_cmp( bool is_float, int unordered_result,
2310 2310                    FloatRegister Fa, FloatRegister Fb,
2311 2311                    Register Rresult);
2312 2312  
2313 2313    void fneg( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d);
2314 2314    void fneg( FloatRegisterImpl::Width w, FloatRegister sd ) { Assembler::fneg(w, sd); }
2315 2315    void fmov( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d);
2316 2316    void fabs( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d);
2317 2317  
2318 2318    void save_all_globals_into_locals();

2319 2319    void restore_globals_from_locals();
2320 2320  
2321 2321    void casx_under_lock(Register top_ptr_reg, Register top_reg, Register ptr_reg,
2322 2322      address lock_addr=0, bool use_call_vm=false);
2323 2323    void cas_under_lock(Register top_ptr_reg, Register top_reg, Register ptr_reg,
2324 2324      address lock_addr=0, bool use_call_vm=false);
2325 2325    void casn (Register addr_reg, Register cmp_reg, Register set_reg) ;
2326 2326  
2327 2327    // These set the icc condition code to equal if the lock succeeded
2328 2328    // and notEqual if it failed and requires a slow case
2329 2329    void compiler_lock_object(Register Roop, Register Rmark, Register Rbox,
2330 2330                              Register Rscratch,
2331 2331                              BiasedLockingCounters* counters = NULL,
2332 2332                              bool try_bias = UseBiasedLocking);
2333 2333    void compiler_unlock_object(Register Roop, Register Rmark, Register Rbox,
2334 2334                                Register Rscratch,
2335 2335                                bool try_bias = UseBiasedLocking);
2336 2336  
2337 2337    // Biased locking support
2338 2338    // Upon entry, lock_reg must point to the lock record on the stack,
2339 2339    // obj_reg must contain the target object, and mark_reg must contain
2340 2340    // the target object's header.
2341 2341    // Destroys mark_reg if an attempt is made to bias an anonymously
2342 2342    // biased lock. In this case a failure will go either to the slow
2343 2343    // case or fall through with the notEqual condition code set with
2344 2344    // the expectation that the slow case in the runtime will be called.
2345 2345    // In the fall-through case where the CAS-based lock is done,
2346 2346    // mark_reg is not destroyed.
2347 2347    void biased_locking_enter(Register obj_reg, Register mark_reg, Register temp_reg,
2348 2348                              Label& done, Label* slow_case = NULL,
2349 2349                              BiasedLockingCounters* counters = NULL);
2350 2350    // Upon entry, the base register of mark_addr must contain the oop.
2351 2351    // Destroys temp_reg.
2352 2352  
2353 2353    // If allow_delay_slot_filling is set to true, the next instruction
2354 2354    // emitted after this one will go in an annulled delay slot if the
2355 2355    // biased locking exit case failed.
2356 2356    void biased_locking_exit(Address mark_addr, Register temp_reg, Label& done, bool allow_delay_slot_filling = false);
2357 2357  
2358 2358    // allocation
2359 2359    void eden_allocate(
2360 2360      Register obj,                      // result: pointer to object after successful allocation
2361 2361      Register var_size_in_bytes,        // object size in bytes if unknown at compile time; invalid otherwise
2362 2362      int      con_size_in_bytes,        // object size in bytes if   known at compile time
2363 2363      Register t1,                       // temp register
2364 2364      Register t2,                       // temp register
2365 2365      Label&   slow_case                 // continuation point if fast allocation fails
2366 2366    );
2367 2367    void tlab_allocate(
2368 2368      Register obj,                      // result: pointer to object after successful allocation
2369 2369      Register var_size_in_bytes,        // object size in bytes if unknown at compile time; invalid otherwise
2370 2370      int      con_size_in_bytes,        // object size in bytes if   known at compile time
2371 2371      Register t1,                       // temp register
2372 2372      Label&   slow_case                 // continuation point if fast allocation fails
2373 2373    );
2374 2374    void tlab_refill(Label& retry_tlab, Label& try_eden, Label& slow_case);
2375 2375  
2376 2376    // interface method calling
2377 2377    void lookup_interface_method(Register recv_klass,
2378 2378                                 Register intf_klass,
2379 2379                                 RegisterOrConstant itable_index,
2380 2380                                 Register method_result,
2381 2381                                 Register temp_reg, Register temp2_reg,
2382 2382                                 Label& no_such_interface);
2383 2383  
2384 2384    // Test sub_klass against super_klass, with fast and slow paths.
2385 2385  
2386 2386    // The fast path produces a tri-state answer: yes / no / maybe-slow.
2387 2387    // One of the three labels can be NULL, meaning take the fall-through.
2388 2388    // If super_check_offset is -1, the value is loaded up from super_klass.
2389 2389    // No registers are killed, except temp_reg and temp2_reg.
2390 2390    // If super_check_offset is not -1, temp2_reg is not used and can be noreg.
2391 2391    void check_klass_subtype_fast_path(Register sub_klass,
2392 2392                                       Register super_klass,
2393 2393                                       Register temp_reg,
2394 2394                                       Register temp2_reg,
2395 2395                                       Label* L_success,
2396 2396                                       Label* L_failure,
2397 2397                                       Label* L_slow_path,
2398 2398                  RegisterOrConstant super_check_offset = RegisterOrConstant(-1),
2399 2399                  Register instanceof_hack = noreg);
2400 2400  
2401 2401    // The rest of the type check; must be wired to a corresponding fast path.
2402 2402    // It does not repeat the fast path logic, so don't use it standalone.
2403 2403    // The temp_reg can be noreg, if no temps are available.
2404 2404    // It can also be sub_klass or super_klass, meaning it's OK to kill that one.
2405 2405    // Updates the sub's secondary super cache as necessary.
2406 2406    void check_klass_subtype_slow_path(Register sub_klass,
2407 2407                                       Register super_klass,
2408 2408                                       Register temp_reg,
2409 2409                                       Register temp2_reg,
2410 2410                                       Register temp3_reg,
2411 2411                                       Register temp4_reg,
2412 2412                                       Label* L_success,
2413 2413                                       Label* L_failure);
2414 2414  
2415 2415    // Simplified, combined version, good for typical uses.
2416 2416    // Falls through on failure.

2417 2417    void check_klass_subtype(Register sub_klass,
2418 2418                             Register super_klass,
2419 2419                             Register temp_reg,
2420 2420                             Register temp2_reg,
2421 2421                             Label& L_success);
2422 2422  
2423 2423    // method handles (JSR 292)
2424 2424    void check_method_handle_type(Register mtype_reg, Register mh_reg,
2425 2425                                  Register temp_reg,
2426 2426                                  Label& wrong_method_type);
2427      -  void jump_to_method_handle_entry(Register mh_reg, Register temp_reg);
     2427 +  void load_method_handle_vmslots(Register vmslots_reg, Register mh_reg,
     2428 +                                  Register temp_reg);
     2429 +  void jump_to_method_handle_entry(Register mh_reg, Register temp_reg, bool emit_delayed_nop = true);
2428 2430    // offset relative to Gargs of argument at tos[arg_slot].
2429 2431    // (arg_slot == 0 means the last argument, not the first).
2430 2432    RegisterOrConstant argument_offset(RegisterOrConstant arg_slot,
2431 2433                                       int extra_slot_offset = 0);
2432      -
     2434 +  // Address of Gargs and argument_offset.
     2435 +  Address            argument_address(RegisterOrConstant arg_slot,
     2436 +                                      int extra_slot_offset = 0);
2433 2437  
2434 2438    // Stack overflow checking
2435 2439  
2436 2440    // Note: this clobbers G3_scratch
2437 2441    void bang_stack_with_offset(int offset) {
2438 2442      // stack grows down, caller passes positive offset
2439 2443      assert(offset > 0, "must bang with negative offset");
2440 2444      set((-offset)+STACK_BIAS, G3_scratch);
2441 2445      st(G0, SP, G3_scratch);
2442 2446    }

2443 2447  
2444 2448    // Writes to stack successive pages until offset reached to check for
2445 2449    // stack overflow + shadow pages.  Clobbers tsp and scratch registers.
2446 2450    void bang_stack_size(Register Rsize, Register Rtsp, Register Rscratch);
2447 2451  
2448 2452    virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr, Register tmp, int offset);
2449 2453  
2450 2454    void verify_tlab();
2451 2455  
2452 2456    Condition negate_condition(Condition cond);
2453 2457  
2454 2458    // Helper functions for statistics gathering.
2455 2459    // Conditionally (non-atomically) increments passed counter address, preserving condition codes.
2456 2460    void cond_inc(Condition cond, address counter_addr, Register Rtemp1, Register Rtemp2);
2457 2461    // Unconditional increment.
2458 2462    void inc_counter(address counter_addr, Register Rtmp1, Register Rtmp2);
2459 2463    void inc_counter(int*    counter_addr, Register Rtmp1, Register Rtmp2);
2460 2464  
2461 2465    // Compare char[] arrays aligned to 4 bytes.
2462 2466    void char_arrays_equals(Register ary1, Register ary2,
2463 2467                            Register limit, Register result,
2464 2468                            Register chr1, Register chr2, Label& Ldone);
2465 2469  
2466 2470  #undef VIRTUAL
2467 2471  
2468 2472  };
2469 2473  
2470 2474  /**
2471 2475   * class SkipIfEqual:
2472 2476   *
2473 2477   * Instantiating this class will result in assembly code being output that will
2474 2478   * jump around any code emitted between the creation of the instance and it's
2475 2479   * automatic destruction at the end of a scope block, depending on the value of
2476 2480   * the flag passed to the constructor, which will be checked at run-time.
2477 2481   */
2478 2482  class SkipIfEqual : public StackObj {
2479 2483   private:
2480 2484    MacroAssembler* _masm;
2481 2485    Label _label;
2482 2486  
2483 2487   public:
2484 2488     // 'temp' is a temp register that this object can use (and trash)
2485 2489     SkipIfEqual(MacroAssembler*, Register temp,
2486 2490                 const bool* flag_addr, Assembler::Condition condition);
2487 2491     ~SkipIfEqual();
2488 2492  };
2489 2493  
2490 2494  #ifdef ASSERT
2491 2495  // On RISC, there's no benefit to verifying instruction boundaries.
2492 2496  inline bool AbstractAssembler::pd_check_instruction_mark() { return false; }
2493 2497  #endif

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