5690 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5691 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5692
5693 size(2*4);
5694 format %{ "LDUH $mem,$dst\t! ushort/char & 13-bit mask -> long\n\t"
5695 "AND $dst,$mask,$dst" %}
5696 ins_encode %{
5697 Register Rdst = $dst$$Register;
5698 __ lduh($mem$$Address, Rdst);
5699 __ and3(Rdst, $mask$$constant, Rdst);
5700 %}
5701 ins_pipe(iload_mem);
5702 %}
5703
5704 // Load Unsigned Short/Char (16bit UNsigned) with a 16-bit mask into a Long Register
5705 instruct loadUS2L_immI16(iRegL dst, memory mem, immI16 mask, iRegL tmp) %{
5706 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5707 effect(TEMP dst, TEMP tmp);
5708 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST);
5709
5710 size(3*4);
5711 format %{ "LDUH $mem,$dst\t! ushort/char & 16-bit mask -> long\n\t"
5712 "SET $mask,$tmp\n\t"
5713 "AND $dst,$tmp,$dst" %}
5714 ins_encode %{
5715 Register Rdst = $dst$$Register;
5716 Register Rtmp = $tmp$$Register;
5717 __ lduh($mem$$Address, Rdst);
5718 __ set($mask$$constant, Rtmp);
5719 __ and3(Rdst, Rtmp, Rdst);
5720 %}
5721 ins_pipe(iload_mem);
5722 %}
5723
5724 // Load Integer
5725 instruct loadI(iRegI dst, memory mem) %{
5726 match(Set dst (LoadI mem));
5727 ins_cost(MEMORY_REF_COST);
5728
5729 size(4);
5730 format %{ "LDUW $mem,$dst\t! int" %}
5834 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5835 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5836
5837 size(2*4);
5838 format %{ "LDUW $mem,$dst\t! int & 13-bit mask -> long\n\t"
5839 "AND $dst,$mask,$dst" %}
5840 ins_encode %{
5841 Register Rdst = $dst$$Register;
5842 __ lduw($mem$$Address, Rdst);
5843 __ and3(Rdst, $mask$$constant, Rdst);
5844 %}
5845 ins_pipe(iload_mem);
5846 %}
5847
5848 // Load Integer with a 32-bit mask into a Long Register
5849 instruct loadI2L_immI(iRegL dst, memory mem, immI mask, iRegL tmp) %{
5850 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5851 effect(TEMP dst, TEMP tmp);
5852 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST);
5853
5854 size(3*4);
5855 format %{ "LDUW $mem,$dst\t! int & 32-bit mask -> long\n\t"
5856 "SET $mask,$tmp\n\t"
5857 "AND $dst,$tmp,$dst" %}
5858 ins_encode %{
5859 Register Rdst = $dst$$Register;
5860 Register Rtmp = $tmp$$Register;
5861 __ lduw($mem$$Address, Rdst);
5862 __ set($mask$$constant, Rtmp);
5863 __ and3(Rdst, Rtmp, Rdst);
5864 %}
5865 ins_pipe(iload_mem);
5866 %}
5867
5868 // Load Unsigned Integer into a Long Register
5869 instruct loadUI2L(iRegL dst, memory mem) %{
5870 match(Set dst (LoadUI2L mem));
5871 ins_cost(MEMORY_REF_COST);
5872
5873 size(4);
5874 format %{ "LDUW $mem,$dst\t! uint -> long" %}
|
5690 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5691 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5692
5693 size(2*4);
5694 format %{ "LDUH $mem,$dst\t! ushort/char & 13-bit mask -> long\n\t"
5695 "AND $dst,$mask,$dst" %}
5696 ins_encode %{
5697 Register Rdst = $dst$$Register;
5698 __ lduh($mem$$Address, Rdst);
5699 __ and3(Rdst, $mask$$constant, Rdst);
5700 %}
5701 ins_pipe(iload_mem);
5702 %}
5703
5704 // Load Unsigned Short/Char (16bit UNsigned) with a 16-bit mask into a Long Register
5705 instruct loadUS2L_immI16(iRegL dst, memory mem, immI16 mask, iRegL tmp) %{
5706 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5707 effect(TEMP dst, TEMP tmp);
5708 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST);
5709
5710 size((3+1)*4); // set may use two instructions.
5711 format %{ "LDUH $mem,$dst\t! ushort/char & 16-bit mask -> long\n\t"
5712 "SET $mask,$tmp\n\t"
5713 "AND $dst,$tmp,$dst" %}
5714 ins_encode %{
5715 Register Rdst = $dst$$Register;
5716 Register Rtmp = $tmp$$Register;
5717 __ lduh($mem$$Address, Rdst);
5718 __ set($mask$$constant, Rtmp);
5719 __ and3(Rdst, Rtmp, Rdst);
5720 %}
5721 ins_pipe(iload_mem);
5722 %}
5723
5724 // Load Integer
5725 instruct loadI(iRegI dst, memory mem) %{
5726 match(Set dst (LoadI mem));
5727 ins_cost(MEMORY_REF_COST);
5728
5729 size(4);
5730 format %{ "LDUW $mem,$dst\t! int" %}
5834 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5835 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5836
5837 size(2*4);
5838 format %{ "LDUW $mem,$dst\t! int & 13-bit mask -> long\n\t"
5839 "AND $dst,$mask,$dst" %}
5840 ins_encode %{
5841 Register Rdst = $dst$$Register;
5842 __ lduw($mem$$Address, Rdst);
5843 __ and3(Rdst, $mask$$constant, Rdst);
5844 %}
5845 ins_pipe(iload_mem);
5846 %}
5847
5848 // Load Integer with a 32-bit mask into a Long Register
5849 instruct loadI2L_immI(iRegL dst, memory mem, immI mask, iRegL tmp) %{
5850 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5851 effect(TEMP dst, TEMP tmp);
5852 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST);
5853
5854 size((3+1)*4); // set may use two instructions.
5855 format %{ "LDUW $mem,$dst\t! int & 32-bit mask -> long\n\t"
5856 "SET $mask,$tmp\n\t"
5857 "AND $dst,$tmp,$dst" %}
5858 ins_encode %{
5859 Register Rdst = $dst$$Register;
5860 Register Rtmp = $tmp$$Register;
5861 __ lduw($mem$$Address, Rdst);
5862 __ set($mask$$constant, Rtmp);
5863 __ and3(Rdst, Rtmp, Rdst);
5864 %}
5865 ins_pipe(iload_mem);
5866 %}
5867
5868 // Load Unsigned Integer into a Long Register
5869 instruct loadUI2L(iRegL dst, memory mem) %{
5870 match(Set dst (LoadUI2L mem));
5871 ins_cost(MEMORY_REF_COST);
5872
5873 size(4);
5874 format %{ "LDUW $mem,$dst\t! uint -> long" %}
|