1 /*
2 * Copyright 2003-2009 Sun Microsystems, Inc. All Rights Reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
20 * CA 95054 USA or visit www.sun.com if you need additional information or
21 * have any questions.
22 *
23 */
24
25 #include "incls/_precompiled.incl"
26 #include "incls/_sharedRuntime_sparc.cpp.incl"
27
28 #define __ masm->
29
30 #ifdef COMPILER2
31 UncommonTrapBlob* SharedRuntime::_uncommon_trap_blob;
32 #endif // COMPILER2
33
34 DeoptimizationBlob* SharedRuntime::_deopt_blob;
35 SafepointBlob* SharedRuntime::_polling_page_safepoint_handler_blob;
36 SafepointBlob* SharedRuntime::_polling_page_return_handler_blob;
37 RuntimeStub* SharedRuntime::_wrong_method_blob;
38 RuntimeStub* SharedRuntime::_ic_miss_blob;
39 RuntimeStub* SharedRuntime::_resolve_opt_virtual_call_blob;
40 RuntimeStub* SharedRuntime::_resolve_virtual_call_blob;
41 RuntimeStub* SharedRuntime::_resolve_static_call_blob;
42
43 class RegisterSaver {
44
45 // Used for saving volatile registers. This is Gregs, Fregs, I/L/O.
46 // The Oregs are problematic. In the 32bit build the compiler can
47 // have O registers live with 64 bit quantities. A window save will
48 // cut the heads off of the registers. We have to do a very extensive
49 // stack dance to save and restore these properly.
50
51 // Note that the Oregs problem only exists if we block at either a polling
52 // page exception a compiled code safepoint that was not originally a call
53 // or deoptimize following one of these kinds of safepoints.
54
55 // Lots of registers to save. For all builds, a window save will preserve
56 // the %i and %l registers. For the 32-bit longs-in-two entries and 64-bit
57 // builds a window-save will preserve the %o registers. In the LION build
58 // we need to save the 64-bit %o registers which requires we save them
59 // before the window-save (as then they become %i registers and get their
60 // heads chopped off on interrupt). We have to save some %g registers here
61 // as well.
62 enum {
63 // This frame's save area. Includes extra space for the native call:
64 // vararg's layout space and the like. Briefly holds the caller's
65 // register save area.
66 call_args_area = frame::register_save_words_sp_offset +
67 frame::memory_parameter_word_sp_offset*wordSize,
68 // Make sure save locations are always 8 byte aligned.
69 // can't use round_to because it doesn't produce compile time constant
70 start_of_extra_save_area = ((call_args_area + 7) & ~7),
71 g1_offset = start_of_extra_save_area, // g-regs needing saving
72 g3_offset = g1_offset+8,
73 g4_offset = g3_offset+8,
74 g5_offset = g4_offset+8,
75 o0_offset = g5_offset+8,
76 o1_offset = o0_offset+8,
77 o2_offset = o1_offset+8,
78 o3_offset = o2_offset+8,
79 o4_offset = o3_offset+8,
80 o5_offset = o4_offset+8,
81 start_of_flags_save_area = o5_offset+8,
82 ccr_offset = start_of_flags_save_area,
83 fsr_offset = ccr_offset + 8,
84 d00_offset = fsr_offset+8, // Start of float save area
85 register_save_size = d00_offset+8*32
86 };
87
88
89 public:
90
91 static int Oexception_offset() { return o0_offset; };
92 static int G3_offset() { return g3_offset; };
93 static int G5_offset() { return g5_offset; };
94 static OopMap* save_live_registers(MacroAssembler* masm, int additional_frame_words, int* total_frame_words);
95 static void restore_live_registers(MacroAssembler* masm);
96
97 // During deoptimization only the result register need to be restored
98 // all the other values have already been extracted.
99
100 static void restore_result_registers(MacroAssembler* masm);
101 };
102
103 OopMap* RegisterSaver::save_live_registers(MacroAssembler* masm, int additional_frame_words, int* total_frame_words) {
104 // Record volatile registers as callee-save values in an OopMap so their save locations will be
105 // propagated to the caller frame's RegisterMap during StackFrameStream construction (needed for
106 // deoptimization; see compiledVFrame::create_stack_value). The caller's I, L and O registers
107 // are saved in register windows - I's and L's in the caller's frame and O's in the stub frame
108 // (as the stub's I's) when the runtime routine called by the stub creates its frame.
109 int i;
110 // Always make the frame size 16 bytr aligned.
111 int frame_size = round_to(additional_frame_words + register_save_size, 16);
112 // OopMap frame size is in c2 stack slots (sizeof(jint)) not bytes or words
113 int frame_size_in_slots = frame_size / sizeof(jint);
114 // CodeBlob frame size is in words.
115 *total_frame_words = frame_size / wordSize;
116 // OopMap* map = new OopMap(*total_frame_words, 0);
117 OopMap* map = new OopMap(frame_size_in_slots, 0);
118
119 #if !defined(_LP64)
120
121 // Save 64-bit O registers; they will get their heads chopped off on a 'save'.
122 __ stx(O0, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+0*8);
123 __ stx(O1, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+1*8);
124 __ stx(O2, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+2*8);
125 __ stx(O3, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+3*8);
126 __ stx(O4, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+4*8);
127 __ stx(O5, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+5*8);
128 #endif /* _LP64 */
129
130 __ save(SP, -frame_size, SP);
131
132 #ifndef _LP64
133 // Reload the 64 bit Oregs. Although they are now Iregs we load them
134 // to Oregs here to avoid interrupts cutting off their heads
135
136 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+0*8, O0);
137 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+1*8, O1);
138 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+2*8, O2);
139 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+3*8, O3);
140 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+4*8, O4);
141 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+5*8, O5);
142
143 __ stx(O0, SP, o0_offset+STACK_BIAS);
144 map->set_callee_saved(VMRegImpl::stack2reg((o0_offset + 4)>>2), O0->as_VMReg());
145
146 __ stx(O1, SP, o1_offset+STACK_BIAS);
147
148 map->set_callee_saved(VMRegImpl::stack2reg((o1_offset + 4)>>2), O1->as_VMReg());
149
150 __ stx(O2, SP, o2_offset+STACK_BIAS);
151 map->set_callee_saved(VMRegImpl::stack2reg((o2_offset + 4)>>2), O2->as_VMReg());
152
153 __ stx(O3, SP, o3_offset+STACK_BIAS);
154 map->set_callee_saved(VMRegImpl::stack2reg((o3_offset + 4)>>2), O3->as_VMReg());
155
156 __ stx(O4, SP, o4_offset+STACK_BIAS);
157 map->set_callee_saved(VMRegImpl::stack2reg((o4_offset + 4)>>2), O4->as_VMReg());
158
159 __ stx(O5, SP, o5_offset+STACK_BIAS);
160 map->set_callee_saved(VMRegImpl::stack2reg((o5_offset + 4)>>2), O5->as_VMReg());
161 #endif /* _LP64 */
162
163
164 #ifdef _LP64
165 int debug_offset = 0;
166 #else
167 int debug_offset = 4;
168 #endif
169 // Save the G's
170 __ stx(G1, SP, g1_offset+STACK_BIAS);
171 map->set_callee_saved(VMRegImpl::stack2reg((g1_offset + debug_offset)>>2), G1->as_VMReg());
172
173 __ stx(G3, SP, g3_offset+STACK_BIAS);
174 map->set_callee_saved(VMRegImpl::stack2reg((g3_offset + debug_offset)>>2), G3->as_VMReg());
175
176 __ stx(G4, SP, g4_offset+STACK_BIAS);
177 map->set_callee_saved(VMRegImpl::stack2reg((g4_offset + debug_offset)>>2), G4->as_VMReg());
178
179 __ stx(G5, SP, g5_offset+STACK_BIAS);
180 map->set_callee_saved(VMRegImpl::stack2reg((g5_offset + debug_offset)>>2), G5->as_VMReg());
181
182 // This is really a waste but we'll keep things as they were for now
183 if (true) {
184 #ifndef _LP64
185 map->set_callee_saved(VMRegImpl::stack2reg((o0_offset)>>2), O0->as_VMReg()->next());
186 map->set_callee_saved(VMRegImpl::stack2reg((o1_offset)>>2), O1->as_VMReg()->next());
187 map->set_callee_saved(VMRegImpl::stack2reg((o2_offset)>>2), O2->as_VMReg()->next());
188 map->set_callee_saved(VMRegImpl::stack2reg((o3_offset)>>2), O3->as_VMReg()->next());
189 map->set_callee_saved(VMRegImpl::stack2reg((o4_offset)>>2), O4->as_VMReg()->next());
190 map->set_callee_saved(VMRegImpl::stack2reg((o5_offset)>>2), O5->as_VMReg()->next());
191 map->set_callee_saved(VMRegImpl::stack2reg((g1_offset)>>2), G1->as_VMReg()->next());
192 map->set_callee_saved(VMRegImpl::stack2reg((g3_offset)>>2), G3->as_VMReg()->next());
193 map->set_callee_saved(VMRegImpl::stack2reg((g4_offset)>>2), G4->as_VMReg()->next());
194 map->set_callee_saved(VMRegImpl::stack2reg((g5_offset)>>2), G5->as_VMReg()->next());
195 #endif /* _LP64 */
196 }
197
198
199 // Save the flags
200 __ rdccr( G5 );
201 __ stx(G5, SP, ccr_offset+STACK_BIAS);
202 __ stxfsr(SP, fsr_offset+STACK_BIAS);
203
204 // Save all the FP registers
205 int offset = d00_offset;
206 for( int i=0; i<64; i+=2 ) {
207 FloatRegister f = as_FloatRegister(i);
208 __ stf(FloatRegisterImpl::D, f, SP, offset+STACK_BIAS);
209 map->set_callee_saved(VMRegImpl::stack2reg(offset>>2), f->as_VMReg());
210 if (true) {
211 map->set_callee_saved(VMRegImpl::stack2reg((offset + sizeof(float))>>2), f->as_VMReg()->next());
212 }
213 offset += sizeof(double);
214 }
215
216 // And we're done.
217
218 return map;
219 }
220
221
222 // Pop the current frame and restore all the registers that we
223 // saved.
224 void RegisterSaver::restore_live_registers(MacroAssembler* masm) {
225
226 // Restore all the FP registers
227 for( int i=0; i<64; i+=2 ) {
228 __ ldf(FloatRegisterImpl::D, SP, d00_offset+i*sizeof(float)+STACK_BIAS, as_FloatRegister(i));
229 }
230
231 __ ldx(SP, ccr_offset+STACK_BIAS, G1);
232 __ wrccr (G1) ;
233
234 // Restore the G's
235 // Note that G2 (AKA GThread) must be saved and restored separately.
236 // TODO-FIXME: save and restore some of the other ASRs, viz., %asi and %gsr.
237
238 __ ldx(SP, g1_offset+STACK_BIAS, G1);
239 __ ldx(SP, g3_offset+STACK_BIAS, G3);
240 __ ldx(SP, g4_offset+STACK_BIAS, G4);
241 __ ldx(SP, g5_offset+STACK_BIAS, G5);
242
243
244 #if !defined(_LP64)
245 // Restore the 64-bit O's.
246 __ ldx(SP, o0_offset+STACK_BIAS, O0);
247 __ ldx(SP, o1_offset+STACK_BIAS, O1);
248 __ ldx(SP, o2_offset+STACK_BIAS, O2);
249 __ ldx(SP, o3_offset+STACK_BIAS, O3);
250 __ ldx(SP, o4_offset+STACK_BIAS, O4);
251 __ ldx(SP, o5_offset+STACK_BIAS, O5);
252
253 // And temporarily place them in TLS
254
255 __ stx(O0, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+0*8);
256 __ stx(O1, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+1*8);
257 __ stx(O2, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+2*8);
258 __ stx(O3, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+3*8);
259 __ stx(O4, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+4*8);
260 __ stx(O5, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+5*8);
261 #endif /* _LP64 */
262
263 // Restore flags
264
265 __ ldxfsr(SP, fsr_offset+STACK_BIAS);
266
267 __ restore();
268
269 #if !defined(_LP64)
270 // Now reload the 64bit Oregs after we've restore the window.
271 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+0*8, O0);
272 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+1*8, O1);
273 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+2*8, O2);
274 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+3*8, O3);
275 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+4*8, O4);
276 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+5*8, O5);
277 #endif /* _LP64 */
278
279 }
280
281 // Pop the current frame and restore the registers that might be holding
282 // a result.
283 void RegisterSaver::restore_result_registers(MacroAssembler* masm) {
284
285 #if !defined(_LP64)
286 // 32bit build returns longs in G1
287 __ ldx(SP, g1_offset+STACK_BIAS, G1);
288
289 // Retrieve the 64-bit O's.
290 __ ldx(SP, o0_offset+STACK_BIAS, O0);
291 __ ldx(SP, o1_offset+STACK_BIAS, O1);
292 // and save to TLS
293 __ stx(O0, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+0*8);
294 __ stx(O1, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+1*8);
295 #endif /* _LP64 */
296
297 __ ldf(FloatRegisterImpl::D, SP, d00_offset+STACK_BIAS, as_FloatRegister(0));
298
299 __ restore();
300
301 #if !defined(_LP64)
302 // Now reload the 64bit Oregs after we've restore the window.
303 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+0*8, O0);
304 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+1*8, O1);
305 #endif /* _LP64 */
306
307 }
308
309 // The java_calling_convention describes stack locations as ideal slots on
310 // a frame with no abi restrictions. Since we must observe abi restrictions
311 // (like the placement of the register window) the slots must be biased by
312 // the following value.
313 static int reg2offset(VMReg r) {
314 return (r->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size;
315 }
316
317 // ---------------------------------------------------------------------------
318 // Read the array of BasicTypes from a signature, and compute where the
319 // arguments should go. Values in the VMRegPair regs array refer to 4-byte (VMRegImpl::stack_slot_size)
320 // quantities. Values less than VMRegImpl::stack0 are registers, those above
321 // refer to 4-byte stack slots. All stack slots are based off of the window
322 // top. VMRegImpl::stack0 refers to the first slot past the 16-word window,
323 // and VMRegImpl::stack0+1 refers to the memory word 4-byes higher. Register
324 // values 0-63 (up to RegisterImpl::number_of_registers) are the 64-bit
325 // integer registers. Values 64-95 are the (32-bit only) float registers.
326 // Each 32-bit quantity is given its own number, so the integer registers
327 // (in either 32- or 64-bit builds) use 2 numbers. For example, there is
328 // an O0-low and an O0-high. Essentially, all int register numbers are doubled.
329
330 // Register results are passed in O0-O5, for outgoing call arguments. To
331 // convert to incoming arguments, convert all O's to I's. The regs array
332 // refer to the low and hi 32-bit words of 64-bit registers or stack slots.
333 // If the regs[].second() field is set to VMRegImpl::Bad(), it means it's unused (a
334 // 32-bit value was passed). If both are VMRegImpl::Bad(), it means no value was
335 // passed (used as a placeholder for the other half of longs and doubles in
336 // the 64-bit build). regs[].second() is either VMRegImpl::Bad() or regs[].second() is
337 // regs[].first()+1 (regs[].first() may be misaligned in the C calling convention).
338 // Sparc never passes a value in regs[].second() but not regs[].first() (regs[].first()
339 // == VMRegImpl::Bad() && regs[].second() != VMRegImpl::Bad()) nor unrelated values in the
340 // same VMRegPair.
341
342 // Note: the INPUTS in sig_bt are in units of Java argument words, which are
343 // either 32-bit or 64-bit depending on the build. The OUTPUTS are in 32-bit
344 // units regardless of build.
345
346
347 // ---------------------------------------------------------------------------
348 // The compiled Java calling convention. The Java convention always passes
349 // 64-bit values in adjacent aligned locations (either registers or stack),
350 // floats in float registers and doubles in aligned float pairs. Values are
351 // packed in the registers. There is no backing varargs store for values in
352 // registers. In the 32-bit build, longs are passed in G1 and G4 (cannot be
353 // passed in I's, because longs in I's get their heads chopped off at
354 // interrupt).
355 int SharedRuntime::java_calling_convention(const BasicType *sig_bt,
356 VMRegPair *regs,
357 int total_args_passed,
358 int is_outgoing) {
359 assert(F31->as_VMReg()->is_reg(), "overlapping stack/register numbers");
360
361 // Convention is to pack the first 6 int/oop args into the first 6 registers
362 // (I0-I5), extras spill to the stack. Then pack the first 8 float args
363 // into F0-F7, extras spill to the stack. Then pad all register sets to
364 // align. Then put longs and doubles into the same registers as they fit,
365 // else spill to the stack.
366 const int int_reg_max = SPARC_ARGS_IN_REGS_NUM;
367 const int flt_reg_max = 8;
368 //
369 // Where 32-bit 1-reg longs start being passed
370 // In tiered we must pass on stack because c1 can't use a "pair" in a single reg.
371 // So make it look like we've filled all the G regs that c2 wants to use.
372 Register g_reg = TieredCompilation ? noreg : G1;
373
374 // Count int/oop and float args. See how many stack slots we'll need and
375 // where the longs & doubles will go.
376 int int_reg_cnt = 0;
377 int flt_reg_cnt = 0;
378 // int stk_reg_pairs = frame::register_save_words*(wordSize>>2);
379 // int stk_reg_pairs = SharedRuntime::out_preserve_stack_slots();
380 int stk_reg_pairs = 0;
381 for (int i = 0; i < total_args_passed; i++) {
382 switch (sig_bt[i]) {
383 case T_LONG: // LP64, longs compete with int args
384 assert(sig_bt[i+1] == T_VOID, "");
385 #ifdef _LP64
386 if (int_reg_cnt < int_reg_max) int_reg_cnt++;
387 #endif
388 break;
389 case T_OBJECT:
390 case T_ARRAY:
391 case T_ADDRESS: // Used, e.g., in slow-path locking for the lock's stack address
392 if (int_reg_cnt < int_reg_max) int_reg_cnt++;
393 #ifndef _LP64
394 else stk_reg_pairs++;
395 #endif
396 break;
397 case T_INT:
398 case T_SHORT:
399 case T_CHAR:
400 case T_BYTE:
401 case T_BOOLEAN:
402 if (int_reg_cnt < int_reg_max) int_reg_cnt++;
403 else stk_reg_pairs++;
404 break;
405 case T_FLOAT:
406 if (flt_reg_cnt < flt_reg_max) flt_reg_cnt++;
407 else stk_reg_pairs++;
408 break;
409 case T_DOUBLE:
410 assert(sig_bt[i+1] == T_VOID, "");
411 break;
412 case T_VOID:
413 break;
414 default:
415 ShouldNotReachHere();
416 }
417 }
418
419 // This is where the longs/doubles start on the stack.
420 stk_reg_pairs = (stk_reg_pairs+1) & ~1; // Round
421
422 int int_reg_pairs = (int_reg_cnt+1) & ~1; // 32-bit 2-reg longs only
423 int flt_reg_pairs = (flt_reg_cnt+1) & ~1;
424
425 // int stk_reg = frame::register_save_words*(wordSize>>2);
426 // int stk_reg = SharedRuntime::out_preserve_stack_slots();
427 int stk_reg = 0;
428 int int_reg = 0;
429 int flt_reg = 0;
430
431 // Now do the signature layout
432 for (int i = 0; i < total_args_passed; i++) {
433 switch (sig_bt[i]) {
434 case T_INT:
435 case T_SHORT:
436 case T_CHAR:
437 case T_BYTE:
438 case T_BOOLEAN:
439 #ifndef _LP64
440 case T_OBJECT:
441 case T_ARRAY:
442 case T_ADDRESS: // Used, e.g., in slow-path locking for the lock's stack address
443 #endif // _LP64
444 if (int_reg < int_reg_max) {
445 Register r = is_outgoing ? as_oRegister(int_reg++) : as_iRegister(int_reg++);
446 regs[i].set1(r->as_VMReg());
447 } else {
448 regs[i].set1(VMRegImpl::stack2reg(stk_reg++));
449 }
450 break;
451
452 #ifdef _LP64
453 case T_OBJECT:
454 case T_ARRAY:
455 case T_ADDRESS: // Used, e.g., in slow-path locking for the lock's stack address
456 if (int_reg < int_reg_max) {
457 Register r = is_outgoing ? as_oRegister(int_reg++) : as_iRegister(int_reg++);
458 regs[i].set2(r->as_VMReg());
459 } else {
460 regs[i].set2(VMRegImpl::stack2reg(stk_reg_pairs));
461 stk_reg_pairs += 2;
462 }
463 break;
464 #endif // _LP64
465
466 case T_LONG:
467 assert(sig_bt[i+1] == T_VOID, "expecting VOID in other half");
468 #ifdef _LP64
469 if (int_reg < int_reg_max) {
470 Register r = is_outgoing ? as_oRegister(int_reg++) : as_iRegister(int_reg++);
471 regs[i].set2(r->as_VMReg());
472 } else {
473 regs[i].set2(VMRegImpl::stack2reg(stk_reg_pairs));
474 stk_reg_pairs += 2;
475 }
476 #else
477 #ifdef COMPILER2
478 // For 32-bit build, can't pass longs in O-regs because they become
479 // I-regs and get trashed. Use G-regs instead. G1 and G4 are almost
480 // spare and available. This convention isn't used by the Sparc ABI or
481 // anywhere else. If we're tiered then we don't use G-regs because c1
482 // can't deal with them as a "pair". (Tiered makes this code think g's are filled)
483 // G0: zero
484 // G1: 1st Long arg
485 // G2: global allocated to TLS
486 // G3: used in inline cache check
487 // G4: 2nd Long arg
488 // G5: used in inline cache check
489 // G6: used by OS
490 // G7: used by OS
491
492 if (g_reg == G1) {
493 regs[i].set2(G1->as_VMReg()); // This long arg in G1
494 g_reg = G4; // Where the next arg goes
495 } else if (g_reg == G4) {
496 regs[i].set2(G4->as_VMReg()); // The 2nd long arg in G4
497 g_reg = noreg; // No more longs in registers
498 } else {
499 regs[i].set2(VMRegImpl::stack2reg(stk_reg_pairs));
500 stk_reg_pairs += 2;
501 }
502 #else // COMPILER2
503 if (int_reg_pairs + 1 < int_reg_max) {
504 if (is_outgoing) {
505 regs[i].set_pair(as_oRegister(int_reg_pairs + 1)->as_VMReg(), as_oRegister(int_reg_pairs)->as_VMReg());
506 } else {
507 regs[i].set_pair(as_iRegister(int_reg_pairs + 1)->as_VMReg(), as_iRegister(int_reg_pairs)->as_VMReg());
508 }
509 int_reg_pairs += 2;
510 } else {
511 regs[i].set2(VMRegImpl::stack2reg(stk_reg_pairs));
512 stk_reg_pairs += 2;
513 }
514 #endif // COMPILER2
515 #endif // _LP64
516 break;
517
518 case T_FLOAT:
519 if (flt_reg < flt_reg_max) regs[i].set1(as_FloatRegister(flt_reg++)->as_VMReg());
520 else regs[i].set1( VMRegImpl::stack2reg(stk_reg++));
521 break;
522 case T_DOUBLE:
523 assert(sig_bt[i+1] == T_VOID, "expecting half");
524 if (flt_reg_pairs + 1 < flt_reg_max) {
525 regs[i].set2(as_FloatRegister(flt_reg_pairs)->as_VMReg());
526 flt_reg_pairs += 2;
527 } else {
528 regs[i].set2(VMRegImpl::stack2reg(stk_reg_pairs));
529 stk_reg_pairs += 2;
530 }
531 break;
532 case T_VOID: regs[i].set_bad(); break; // Halves of longs & doubles
533 default:
534 ShouldNotReachHere();
535 }
536 }
537
538 // retun the amount of stack space these arguments will need.
539 return stk_reg_pairs;
540
541 }
542
543 // Helper class mostly to avoid passing masm everywhere, and handle store
544 // displacement overflow logic for LP64
545 class AdapterGenerator {
546 MacroAssembler *masm;
547 #ifdef _LP64
548 Register Rdisp;
549 void set_Rdisp(Register r) { Rdisp = r; }
550 #endif // _LP64
551
552 void patch_callers_callsite();
553 void tag_c2i_arg(frame::Tag t, Register base, int st_off, Register scratch);
554
555 // base+st_off points to top of argument
556 int arg_offset(const int st_off) { return st_off + Interpreter::value_offset_in_bytes(); }
557 int next_arg_offset(const int st_off) {
558 return st_off - Interpreter::stackElementSize() + Interpreter::value_offset_in_bytes();
559 }
560
561 #ifdef _LP64
562 // On _LP64 argument slot values are loaded first into a register
563 // because they might not fit into displacement.
564 Register arg_slot(const int st_off);
565 Register next_arg_slot(const int st_off);
566 #else
567 int arg_slot(const int st_off) { return arg_offset(st_off); }
568 int next_arg_slot(const int st_off) { return next_arg_offset(st_off); }
569 #endif // _LP64
570
571 // Stores long into offset pointed to by base
572 void store_c2i_long(Register r, Register base,
573 const int st_off, bool is_stack);
574 void store_c2i_object(Register r, Register base,
575 const int st_off);
576 void store_c2i_int(Register r, Register base,
577 const int st_off);
578 void store_c2i_double(VMReg r_2,
579 VMReg r_1, Register base, const int st_off);
580 void store_c2i_float(FloatRegister f, Register base,
581 const int st_off);
582
583 public:
584 void gen_c2i_adapter(int total_args_passed,
585 // VMReg max_arg,
586 int comp_args_on_stack, // VMRegStackSlots
587 const BasicType *sig_bt,
588 const VMRegPair *regs,
589 Label& skip_fixup);
590 void gen_i2c_adapter(int total_args_passed,
591 // VMReg max_arg,
592 int comp_args_on_stack, // VMRegStackSlots
593 const BasicType *sig_bt,
594 const VMRegPair *regs);
595
596 AdapterGenerator(MacroAssembler *_masm) : masm(_masm) {}
597 };
598
599
600 // Patch the callers callsite with entry to compiled code if it exists.
601 void AdapterGenerator::patch_callers_callsite() {
602 Label L;
603 __ ld_ptr(G5_method, in_bytes(methodOopDesc::code_offset()), G3_scratch);
604 __ br_null(G3_scratch, false, __ pt, L);
605 // Schedule the branch target address early.
606 __ delayed()->ld_ptr(G5_method, in_bytes(methodOopDesc::interpreter_entry_offset()), G3_scratch);
607 // Call into the VM to patch the caller, then jump to compiled callee
608 __ save_frame(4); // Args in compiled layout; do not blow them
609
610 // Must save all the live Gregs the list is:
611 // G1: 1st Long arg (32bit build)
612 // G2: global allocated to TLS
613 // G3: used in inline cache check (scratch)
614 // G4: 2nd Long arg (32bit build);
615 // G5: used in inline cache check (methodOop)
616
617 // The longs must go to the stack by hand since in the 32 bit build they can be trashed by window ops.
618
619 #ifdef _LP64
620 // mov(s,d)
621 __ mov(G1, L1);
622 __ mov(G4, L4);
623 __ mov(G5_method, L5);
624 __ mov(G5_method, O0); // VM needs target method
625 __ mov(I7, O1); // VM needs caller's callsite
626 // Must be a leaf call...
627 // can be very far once the blob has been relocated
628 AddressLiteral dest(CAST_FROM_FN_PTR(address, SharedRuntime::fixup_callers_callsite));
629 __ relocate(relocInfo::runtime_call_type);
630 __ jumpl_to(dest, O7, O7);
631 __ delayed()->mov(G2_thread, L7_thread_cache);
632 __ mov(L7_thread_cache, G2_thread);
633 __ mov(L1, G1);
634 __ mov(L4, G4);
635 __ mov(L5, G5_method);
636 #else
637 __ stx(G1, FP, -8 + STACK_BIAS);
638 __ stx(G4, FP, -16 + STACK_BIAS);
639 __ mov(G5_method, L5);
640 __ mov(G5_method, O0); // VM needs target method
641 __ mov(I7, O1); // VM needs caller's callsite
642 // Must be a leaf call...
643 __ call(CAST_FROM_FN_PTR(address, SharedRuntime::fixup_callers_callsite), relocInfo::runtime_call_type);
644 __ delayed()->mov(G2_thread, L7_thread_cache);
645 __ mov(L7_thread_cache, G2_thread);
646 __ ldx(FP, -8 + STACK_BIAS, G1);
647 __ ldx(FP, -16 + STACK_BIAS, G4);
648 __ mov(L5, G5_method);
649 __ ld_ptr(G5_method, in_bytes(methodOopDesc::interpreter_entry_offset()), G3_scratch);
650 #endif /* _LP64 */
651
652 __ restore(); // Restore args
653 __ bind(L);
654 }
655
656 void AdapterGenerator::tag_c2i_arg(frame::Tag t, Register base, int st_off,
657 Register scratch) {
658 if (TaggedStackInterpreter) {
659 int tag_off = st_off + Interpreter::tag_offset_in_bytes();
660 #ifdef _LP64
661 Register tag_slot = Rdisp;
662 __ set(tag_off, tag_slot);
663 #else
664 int tag_slot = tag_off;
665 #endif // _LP64
666 // have to store zero because local slots can be reused (rats!)
667 if (t == frame::TagValue) {
668 __ st_ptr(G0, base, tag_slot);
669 } else if (t == frame::TagCategory2) {
670 __ st_ptr(G0, base, tag_slot);
671 int next_tag_off = st_off - Interpreter::stackElementSize() +
672 Interpreter::tag_offset_in_bytes();
673 #ifdef _LP64
674 __ set(next_tag_off, tag_slot);
675 #else
676 tag_slot = next_tag_off;
677 #endif // _LP64
678 __ st_ptr(G0, base, tag_slot);
679 } else {
680 __ mov(t, scratch);
681 __ st_ptr(scratch, base, tag_slot);
682 }
683 }
684 }
685
686 #ifdef _LP64
687 Register AdapterGenerator::arg_slot(const int st_off) {
688 __ set( arg_offset(st_off), Rdisp);
689 return Rdisp;
690 }
691
692 Register AdapterGenerator::next_arg_slot(const int st_off){
693 __ set( next_arg_offset(st_off), Rdisp);
694 return Rdisp;
695 }
696 #endif // _LP64
697
698 // Stores long into offset pointed to by base
699 void AdapterGenerator::store_c2i_long(Register r, Register base,
700 const int st_off, bool is_stack) {
701 #ifdef _LP64
702 // In V9, longs are given 2 64-bit slots in the interpreter, but the
703 // data is passed in only 1 slot.
704 __ stx(r, base, next_arg_slot(st_off));
705 #else
706 #ifdef COMPILER2
707 // Misaligned store of 64-bit data
708 __ stw(r, base, arg_slot(st_off)); // lo bits
709 __ srlx(r, 32, r);
710 __ stw(r, base, next_arg_slot(st_off)); // hi bits
711 #else
712 if (is_stack) {
713 // Misaligned store of 64-bit data
714 __ stw(r, base, arg_slot(st_off)); // lo bits
715 __ srlx(r, 32, r);
716 __ stw(r, base, next_arg_slot(st_off)); // hi bits
717 } else {
718 __ stw(r->successor(), base, arg_slot(st_off) ); // lo bits
719 __ stw(r , base, next_arg_slot(st_off)); // hi bits
720 }
721 #endif // COMPILER2
722 #endif // _LP64
723 tag_c2i_arg(frame::TagCategory2, base, st_off, r);
724 }
725
726 void AdapterGenerator::store_c2i_object(Register r, Register base,
727 const int st_off) {
728 __ st_ptr (r, base, arg_slot(st_off));
729 tag_c2i_arg(frame::TagReference, base, st_off, r);
730 }
731
732 void AdapterGenerator::store_c2i_int(Register r, Register base,
733 const int st_off) {
734 __ st (r, base, arg_slot(st_off));
735 tag_c2i_arg(frame::TagValue, base, st_off, r);
736 }
737
738 // Stores into offset pointed to by base
739 void AdapterGenerator::store_c2i_double(VMReg r_2,
740 VMReg r_1, Register base, const int st_off) {
741 #ifdef _LP64
742 // In V9, doubles are given 2 64-bit slots in the interpreter, but the
743 // data is passed in only 1 slot.
744 __ stf(FloatRegisterImpl::D, r_1->as_FloatRegister(), base, next_arg_slot(st_off));
745 #else
746 // Need to marshal 64-bit value from misaligned Lesp loads
747 __ stf(FloatRegisterImpl::S, r_1->as_FloatRegister(), base, next_arg_slot(st_off));
748 __ stf(FloatRegisterImpl::S, r_2->as_FloatRegister(), base, arg_slot(st_off) );
749 #endif
750 tag_c2i_arg(frame::TagCategory2, base, st_off, G1_scratch);
751 }
752
753 void AdapterGenerator::store_c2i_float(FloatRegister f, Register base,
754 const int st_off) {
755 __ stf(FloatRegisterImpl::S, f, base, arg_slot(st_off));
756 tag_c2i_arg(frame::TagValue, base, st_off, G1_scratch);
757 }
758
759 void AdapterGenerator::gen_c2i_adapter(
760 int total_args_passed,
761 // VMReg max_arg,
762 int comp_args_on_stack, // VMRegStackSlots
763 const BasicType *sig_bt,
764 const VMRegPair *regs,
765 Label& skip_fixup) {
766
767 // Before we get into the guts of the C2I adapter, see if we should be here
768 // at all. We've come from compiled code and are attempting to jump to the
769 // interpreter, which means the caller made a static call to get here
770 // (vcalls always get a compiled target if there is one). Check for a
771 // compiled target. If there is one, we need to patch the caller's call.
772 // However we will run interpreted if we come thru here. The next pass
773 // thru the call site will run compiled. If we ran compiled here then
774 // we can (theorectically) do endless i2c->c2i->i2c transitions during
775 // deopt/uncommon trap cycles. If we always go interpreted here then
776 // we can have at most one and don't need to play any tricks to keep
777 // from endlessly growing the stack.
778 //
779 // Actually if we detected that we had an i2c->c2i transition here we
780 // ought to be able to reset the world back to the state of the interpreted
781 // call and not bother building another interpreter arg area. We don't
782 // do that at this point.
783
784 patch_callers_callsite();
785
786 __ bind(skip_fixup);
787
788 // Since all args are passed on the stack, total_args_passed*wordSize is the
789 // space we need. Add in varargs area needed by the interpreter. Round up
790 // to stack alignment.
791 const int arg_size = total_args_passed * Interpreter::stackElementSize();
792 const int varargs_area =
793 (frame::varargs_offset - frame::register_save_words)*wordSize;
794 const int extraspace = round_to(arg_size + varargs_area, 2*wordSize);
795
796 int bias = STACK_BIAS;
797 const int interp_arg_offset = frame::varargs_offset*wordSize +
798 (total_args_passed-1)*Interpreter::stackElementSize();
799
800 Register base = SP;
801
802 #ifdef _LP64
803 // In the 64bit build because of wider slots and STACKBIAS we can run
804 // out of bits in the displacement to do loads and stores. Use g3 as
805 // temporary displacement.
806 if (! __ is_simm13(extraspace)) {
807 __ set(extraspace, G3_scratch);
808 __ sub(SP, G3_scratch, SP);
809 } else {
810 __ sub(SP, extraspace, SP);
811 }
812 set_Rdisp(G3_scratch);
813 #else
814 __ sub(SP, extraspace, SP);
815 #endif // _LP64
816
817 // First write G1 (if used) to where ever it must go
818 for (int i=0; i<total_args_passed; i++) {
819 const int st_off = interp_arg_offset - (i*Interpreter::stackElementSize()) + bias;
820 VMReg r_1 = regs[i].first();
821 VMReg r_2 = regs[i].second();
822 if (r_1 == G1_scratch->as_VMReg()) {
823 if (sig_bt[i] == T_OBJECT || sig_bt[i] == T_ARRAY) {
824 store_c2i_object(G1_scratch, base, st_off);
825 } else if (sig_bt[i] == T_LONG) {
826 assert(!TieredCompilation, "should not use register args for longs");
827 store_c2i_long(G1_scratch, base, st_off, false);
828 } else {
829 store_c2i_int(G1_scratch, base, st_off);
830 }
831 }
832 }
833
834 // Now write the args into the outgoing interpreter space
835 for (int i=0; i<total_args_passed; i++) {
836 const int st_off = interp_arg_offset - (i*Interpreter::stackElementSize()) + bias;
837 VMReg r_1 = regs[i].first();
838 VMReg r_2 = regs[i].second();
839 if (!r_1->is_valid()) {
840 assert(!r_2->is_valid(), "");
841 continue;
842 }
843 // Skip G1 if found as we did it first in order to free it up
844 if (r_1 == G1_scratch->as_VMReg()) {
845 continue;
846 }
847 #ifdef ASSERT
848 bool G1_forced = false;
849 #endif // ASSERT
850 if (r_1->is_stack()) { // Pretend stack targets are loaded into G1
851 #ifdef _LP64
852 Register ld_off = Rdisp;
853 __ set(reg2offset(r_1) + extraspace + bias, ld_off);
854 #else
855 int ld_off = reg2offset(r_1) + extraspace + bias;
856 #ifdef ASSERT
857 G1_forced = true;
858 #endif // ASSERT
859 #endif // _LP64
860 r_1 = G1_scratch->as_VMReg();// as part of the load/store shuffle
861 if (!r_2->is_valid()) __ ld (base, ld_off, G1_scratch);
862 else __ ldx(base, ld_off, G1_scratch);
863 }
864
865 if (r_1->is_Register()) {
866 Register r = r_1->as_Register()->after_restore();
867 if (sig_bt[i] == T_OBJECT || sig_bt[i] == T_ARRAY) {
868 store_c2i_object(r, base, st_off);
869 } else if (sig_bt[i] == T_LONG || sig_bt[i] == T_DOUBLE) {
870 if (TieredCompilation) {
871 assert(G1_forced || sig_bt[i] != T_LONG, "should not use register args for longs");
872 }
873 store_c2i_long(r, base, st_off, r_2->is_stack());
874 } else {
875 store_c2i_int(r, base, st_off);
876 }
877 } else {
878 assert(r_1->is_FloatRegister(), "");
879 if (sig_bt[i] == T_FLOAT) {
880 store_c2i_float(r_1->as_FloatRegister(), base, st_off);
881 } else {
882 assert(sig_bt[i] == T_DOUBLE, "wrong type");
883 store_c2i_double(r_2, r_1, base, st_off);
884 }
885 }
886 }
887
888 #ifdef _LP64
889 // Need to reload G3_scratch, used for temporary displacements.
890 __ ld_ptr(G5_method, in_bytes(methodOopDesc::interpreter_entry_offset()), G3_scratch);
891
892 // Pass O5_savedSP as an argument to the interpreter.
893 // The interpreter will restore SP to this value before returning.
894 __ set(extraspace, G1);
895 __ add(SP, G1, O5_savedSP);
896 #else
897 // Pass O5_savedSP as an argument to the interpreter.
898 // The interpreter will restore SP to this value before returning.
899 __ add(SP, extraspace, O5_savedSP);
900 #endif // _LP64
901
902 __ mov((frame::varargs_offset)*wordSize -
903 1*Interpreter::stackElementSize()+bias+BytesPerWord, G1);
904 // Jump to the interpreter just as if interpreter was doing it.
905 __ jmpl(G3_scratch, 0, G0);
906 // Setup Lesp for the call. Cannot actually set Lesp as the current Lesp
907 // (really L0) is in use by the compiled frame as a generic temp. However,
908 // the interpreter does not know where its args are without some kind of
909 // arg pointer being passed in. Pass it in Gargs.
910 __ delayed()->add(SP, G1, Gargs);
911 }
912
913 void AdapterGenerator::gen_i2c_adapter(
914 int total_args_passed,
915 // VMReg max_arg,
916 int comp_args_on_stack, // VMRegStackSlots
917 const BasicType *sig_bt,
918 const VMRegPair *regs) {
919
920 // Generate an I2C adapter: adjust the I-frame to make space for the C-frame
921 // layout. Lesp was saved by the calling I-frame and will be restored on
922 // return. Meanwhile, outgoing arg space is all owned by the callee
923 // C-frame, so we can mangle it at will. After adjusting the frame size,
924 // hoist register arguments and repack other args according to the compiled
925 // code convention. Finally, end in a jump to the compiled code. The entry
926 // point address is the start of the buffer.
927
928 // We will only enter here from an interpreted frame and never from after
929 // passing thru a c2i. Azul allowed this but we do not. If we lose the
930 // race and use a c2i we will remain interpreted for the race loser(s).
931 // This removes all sorts of headaches on the x86 side and also eliminates
932 // the possibility of having c2i -> i2c -> c2i -> ... endless transitions.
933
934 // As you can see from the list of inputs & outputs there are not a lot
935 // of temp registers to work with: mostly G1, G3 & G4.
936
937 // Inputs:
938 // G2_thread - TLS
939 // G5_method - Method oop
940 // G4 (Gargs) - Pointer to interpreter's args
941 // O0..O4 - free for scratch
942 // O5_savedSP - Caller's saved SP, to be restored if needed
943 // O6 - Current SP!
944 // O7 - Valid return address
945 // L0-L7, I0-I7 - Caller's temps (no frame pushed yet)
946
947 // Outputs:
948 // G2_thread - TLS
949 // G1, G4 - Outgoing long args in 32-bit build
950 // O0-O5 - Outgoing args in compiled layout
951 // O6 - Adjusted or restored SP
952 // O7 - Valid return address
953 // L0-L7, I0-I7 - Caller's temps (no frame pushed yet)
954 // F0-F7 - more outgoing args
955
956
957 // Gargs is the incoming argument base, and also an outgoing argument.
958 __ sub(Gargs, BytesPerWord, Gargs);
959
960 #ifdef ASSERT
961 {
962 // on entry OsavedSP and SP should be equal
963 Label ok;
964 __ cmp(O5_savedSP, SP);
965 __ br(Assembler::equal, false, Assembler::pt, ok);
966 __ delayed()->nop();
967 __ stop("I5_savedSP not set");
968 __ should_not_reach_here();
969 __ bind(ok);
970 }
971 #endif
972
973 // ON ENTRY TO THE CODE WE ARE MAKING, WE HAVE AN INTERPRETED FRAME
974 // WITH O7 HOLDING A VALID RETURN PC
975 //
976 // | |
977 // : java stack :
978 // | |
979 // +--------------+ <--- start of outgoing args
980 // | receiver | |
981 // : rest of args : |---size is java-arg-words
982 // | | |
983 // +--------------+ <--- O4_args (misaligned) and Lesp if prior is not C2I
984 // | | |
985 // : unused : |---Space for max Java stack, plus stack alignment
986 // | | |
987 // +--------------+ <--- SP + 16*wordsize
988 // | |
989 // : window :
990 // | |
991 // +--------------+ <--- SP
992
993 // WE REPACK THE STACK. We use the common calling convention layout as
994 // discovered by calling SharedRuntime::calling_convention. We assume it
995 // causes an arbitrary shuffle of memory, which may require some register
996 // temps to do the shuffle. We hope for (and optimize for) the case where
997 // temps are not needed. We may have to resize the stack slightly, in case
998 // we need alignment padding (32-bit interpreter can pass longs & doubles
999 // misaligned, but the compilers expect them aligned).
1000 //
1001 // | |
1002 // : java stack :
1003 // | |
1004 // +--------------+ <--- start of outgoing args
1005 // | pad, align | |
1006 // +--------------+ |
1007 // | ints, floats | |---Outgoing stack args, packed low.
1008 // +--------------+ | First few args in registers.
1009 // : doubles : |
1010 // | longs | |
1011 // +--------------+ <--- SP' + 16*wordsize
1012 // | |
1013 // : window :
1014 // | |
1015 // +--------------+ <--- SP'
1016
1017 // ON EXIT FROM THE CODE WE ARE MAKING, WE STILL HAVE AN INTERPRETED FRAME
1018 // WITH O7 HOLDING A VALID RETURN PC - ITS JUST THAT THE ARGS ARE NOW SETUP
1019 // FOR COMPILED CODE AND THE FRAME SLIGHTLY GROWN.
1020
1021 // Cut-out for having no stack args. Since up to 6 args are passed
1022 // in registers, we will commonly have no stack args.
1023 if (comp_args_on_stack > 0) {
1024
1025 // Convert VMReg stack slots to words.
1026 int comp_words_on_stack = round_to(comp_args_on_stack*VMRegImpl::stack_slot_size, wordSize)>>LogBytesPerWord;
1027 // Round up to miminum stack alignment, in wordSize
1028 comp_words_on_stack = round_to(comp_words_on_stack, 2);
1029 // Now compute the distance from Lesp to SP. This calculation does not
1030 // include the space for total_args_passed because Lesp has not yet popped
1031 // the arguments.
1032 __ sub(SP, (comp_words_on_stack)*wordSize, SP);
1033 }
1034
1035 // Will jump to the compiled code just as if compiled code was doing it.
1036 // Pre-load the register-jump target early, to schedule it better.
1037 __ ld_ptr(G5_method, in_bytes(methodOopDesc::from_compiled_offset()), G3);
1038
1039 // Now generate the shuffle code. Pick up all register args and move the
1040 // rest through G1_scratch.
1041 for (int i=0; i<total_args_passed; i++) {
1042 if (sig_bt[i] == T_VOID) {
1043 // Longs and doubles are passed in native word order, but misaligned
1044 // in the 32-bit build.
1045 assert(i > 0 && (sig_bt[i-1] == T_LONG || sig_bt[i-1] == T_DOUBLE), "missing half");
1046 continue;
1047 }
1048
1049 // Pick up 0, 1 or 2 words from Lesp+offset. Assume mis-aligned in the
1050 // 32-bit build and aligned in the 64-bit build. Look for the obvious
1051 // ldx/lddf optimizations.
1052
1053 // Load in argument order going down.
1054 const int ld_off = (total_args_passed-i)*Interpreter::stackElementSize();
1055 #ifdef _LP64
1056 set_Rdisp(G1_scratch);
1057 #endif // _LP64
1058
1059 VMReg r_1 = regs[i].first();
1060 VMReg r_2 = regs[i].second();
1061 if (!r_1->is_valid()) {
1062 assert(!r_2->is_valid(), "");
1063 continue;
1064 }
1065 if (r_1->is_stack()) { // Pretend stack targets are loaded into F8/F9
1066 r_1 = F8->as_VMReg(); // as part of the load/store shuffle
1067 if (r_2->is_valid()) r_2 = r_1->next();
1068 }
1069 if (r_1->is_Register()) { // Register argument
1070 Register r = r_1->as_Register()->after_restore();
1071 if (!r_2->is_valid()) {
1072 __ ld(Gargs, arg_slot(ld_off), r);
1073 } else {
1074 #ifdef _LP64
1075 // In V9, longs are given 2 64-bit slots in the interpreter, but the
1076 // data is passed in only 1 slot.
1077 Register slot = (sig_bt[i]==T_LONG) ?
1078 next_arg_slot(ld_off) : arg_slot(ld_off);
1079 __ ldx(Gargs, slot, r);
1080 #else
1081 // Need to load a 64-bit value into G1/G4, but G1/G4 is being used in the
1082 // stack shuffle. Load the first 2 longs into G1/G4 later.
1083 #endif
1084 }
1085 } else {
1086 assert(r_1->is_FloatRegister(), "");
1087 if (!r_2->is_valid()) {
1088 __ ldf(FloatRegisterImpl::S, Gargs, arg_slot(ld_off), r_1->as_FloatRegister());
1089 } else {
1090 #ifdef _LP64
1091 // In V9, doubles are given 2 64-bit slots in the interpreter, but the
1092 // data is passed in only 1 slot. This code also handles longs that
1093 // are passed on the stack, but need a stack-to-stack move through a
1094 // spare float register.
1095 Register slot = (sig_bt[i]==T_LONG || sig_bt[i] == T_DOUBLE) ?
1096 next_arg_slot(ld_off) : arg_slot(ld_off);
1097 __ ldf(FloatRegisterImpl::D, Gargs, slot, r_1->as_FloatRegister());
1098 #else
1099 // Need to marshal 64-bit value from misaligned Lesp loads
1100 __ ldf(FloatRegisterImpl::S, Gargs, next_arg_slot(ld_off), r_1->as_FloatRegister());
1101 __ ldf(FloatRegisterImpl::S, Gargs, arg_slot(ld_off), r_2->as_FloatRegister());
1102 #endif
1103 }
1104 }
1105 // Was the argument really intended to be on the stack, but was loaded
1106 // into F8/F9?
1107 if (regs[i].first()->is_stack()) {
1108 assert(r_1->as_FloatRegister() == F8, "fix this code");
1109 // Convert stack slot to an SP offset
1110 int st_off = reg2offset(regs[i].first()) + STACK_BIAS;
1111 // Store down the shuffled stack word. Target address _is_ aligned.
1112 if (Assembler::is_simm13(st_off)) {
1113 if (!r_2->is_valid()) __ stf(FloatRegisterImpl::S, r_1->as_FloatRegister(), SP, st_off);
1114 else __ stf(FloatRegisterImpl::D, r_1->as_FloatRegister(), SP, st_off);
1115 } else {
1116 __ set(st_off, Rdisp);
1117 if (!r_2->is_valid()) __ stf(FloatRegisterImpl::S, r_1->as_FloatRegister(), SP, Rdisp);
1118 else __ stf(FloatRegisterImpl::D, r_1->as_FloatRegister(), SP, Rdisp);
1119 }
1120 }
1121 }
1122 bool made_space = false;
1123 #ifndef _LP64
1124 // May need to pick up a few long args in G1/G4
1125 bool g4_crushed = false;
1126 bool g3_crushed = false;
1127 for (int i=0; i<total_args_passed; i++) {
1128 if (regs[i].first()->is_Register() && regs[i].second()->is_valid()) {
1129 // Load in argument order going down
1130 int ld_off = (total_args_passed-i)*Interpreter::stackElementSize();
1131 // Need to marshal 64-bit value from misaligned Lesp loads
1132 Register r = regs[i].first()->as_Register()->after_restore();
1133 if (r == G1 || r == G4) {
1134 assert(!g4_crushed, "ordering problem");
1135 if (r == G4){
1136 g4_crushed = true;
1137 __ lduw(Gargs, arg_slot(ld_off) , G3_scratch); // Load lo bits
1138 __ ld (Gargs, next_arg_slot(ld_off), r); // Load hi bits
1139 } else {
1140 // better schedule this way
1141 __ ld (Gargs, next_arg_slot(ld_off), r); // Load hi bits
1142 __ lduw(Gargs, arg_slot(ld_off) , G3_scratch); // Load lo bits
1143 }
1144 g3_crushed = true;
1145 __ sllx(r, 32, r);
1146 __ or3(G3_scratch, r, r);
1147 } else {
1148 assert(r->is_out(), "longs passed in two O registers");
1149 __ ld (Gargs, arg_slot(ld_off) , r->successor()); // Load lo bits
1150 __ ld (Gargs, next_arg_slot(ld_off), r); // Load hi bits
1151 }
1152 }
1153 }
1154 #endif
1155
1156 // Jump to the compiled code just as if compiled code was doing it.
1157 //
1158 #ifndef _LP64
1159 if (g3_crushed) {
1160 // Rats load was wasted, at least it is in cache...
1161 __ ld_ptr(G5_method, methodOopDesc::from_compiled_offset(), G3);
1162 }
1163 #endif /* _LP64 */
1164
1165 // 6243940 We might end up in handle_wrong_method if
1166 // the callee is deoptimized as we race thru here. If that
1167 // happens we don't want to take a safepoint because the
1168 // caller frame will look interpreted and arguments are now
1169 // "compiled" so it is much better to make this transition
1170 // invisible to the stack walking code. Unfortunately if
1171 // we try and find the callee by normal means a safepoint
1172 // is possible. So we stash the desired callee in the thread
1173 // and the vm will find there should this case occur.
1174 Address callee_target_addr(G2_thread, JavaThread::callee_target_offset());
1175 __ st_ptr(G5_method, callee_target_addr);
1176
1177 if (StressNonEntrant) {
1178 // Open a big window for deopt failure
1179 __ save_frame(0);
1180 __ mov(G0, L0);
1181 Label loop;
1182 __ bind(loop);
1183 __ sub(L0, 1, L0);
1184 __ br_null(L0, false, Assembler::pt, loop);
1185 __ delayed()->nop();
1186
1187 __ restore();
1188 }
1189
1190
1191 __ jmpl(G3, 0, G0);
1192 __ delayed()->nop();
1193 }
1194
1195 // ---------------------------------------------------------------
1196 AdapterHandlerEntry* SharedRuntime::generate_i2c2i_adapters(MacroAssembler *masm,
1197 int total_args_passed,
1198 // VMReg max_arg,
1199 int comp_args_on_stack, // VMRegStackSlots
1200 const BasicType *sig_bt,
1201 const VMRegPair *regs) {
1202 address i2c_entry = __ pc();
1203
1204 AdapterGenerator agen(masm);
1205
1206 agen.gen_i2c_adapter(total_args_passed, comp_args_on_stack, sig_bt, regs);
1207
1208
1209 // -------------------------------------------------------------------------
1210 // Generate a C2I adapter. On entry we know G5 holds the methodOop. The
1211 // args start out packed in the compiled layout. They need to be unpacked
1212 // into the interpreter layout. This will almost always require some stack
1213 // space. We grow the current (compiled) stack, then repack the args. We
1214 // finally end in a jump to the generic interpreter entry point. On exit
1215 // from the interpreter, the interpreter will restore our SP (lest the
1216 // compiled code, which relys solely on SP and not FP, get sick).
1217
1218 address c2i_unverified_entry = __ pc();
1219 Label skip_fixup;
1220 {
1221 #if !defined(_LP64) && defined(COMPILER2)
1222 Register R_temp = L0; // another scratch register
1223 #else
1224 Register R_temp = G1; // another scratch register
1225 #endif
1226
1227 AddressLiteral ic_miss(SharedRuntime::get_ic_miss_stub());
1228
1229 __ verify_oop(O0);
1230 __ verify_oop(G5_method);
1231 __ load_klass(O0, G3_scratch);
1232 __ verify_oop(G3_scratch);
1233
1234 #if !defined(_LP64) && defined(COMPILER2)
1235 __ save(SP, -frame::register_save_words*wordSize, SP);
1236 __ ld_ptr(G5_method, compiledICHolderOopDesc::holder_klass_offset(), R_temp);
1237 __ verify_oop(R_temp);
1238 __ cmp(G3_scratch, R_temp);
1239 __ restore();
1240 #else
1241 __ ld_ptr(G5_method, compiledICHolderOopDesc::holder_klass_offset(), R_temp);
1242 __ verify_oop(R_temp);
1243 __ cmp(G3_scratch, R_temp);
1244 #endif
1245
1246 Label ok, ok2;
1247 __ brx(Assembler::equal, false, Assembler::pt, ok);
1248 __ delayed()->ld_ptr(G5_method, compiledICHolderOopDesc::holder_method_offset(), G5_method);
1249 __ jump_to(ic_miss, G3_scratch);
1250 __ delayed()->nop();
1251
1252 __ bind(ok);
1253 // Method might have been compiled since the call site was patched to
1254 // interpreted if that is the case treat it as a miss so we can get
1255 // the call site corrected.
1256 __ ld_ptr(G5_method, in_bytes(methodOopDesc::code_offset()), G3_scratch);
1257 __ bind(ok2);
1258 __ br_null(G3_scratch, false, __ pt, skip_fixup);
1259 __ delayed()->ld_ptr(G5_method, in_bytes(methodOopDesc::interpreter_entry_offset()), G3_scratch);
1260 __ jump_to(ic_miss, G3_scratch);
1261 __ delayed()->nop();
1262
1263 }
1264
1265 address c2i_entry = __ pc();
1266
1267 agen.gen_c2i_adapter(total_args_passed, comp_args_on_stack, sig_bt, regs, skip_fixup);
1268
1269 __ flush();
1270 return new AdapterHandlerEntry(i2c_entry, c2i_entry, c2i_unverified_entry);
1271
1272 }
1273
1274 // Helper function for native calling conventions
1275 static VMReg int_stk_helper( int i ) {
1276 // Bias any stack based VMReg we get by ignoring the window area
1277 // but not the register parameter save area.
1278 //
1279 // This is strange for the following reasons. We'd normally expect
1280 // the calling convention to return an VMReg for a stack slot
1281 // completely ignoring any abi reserved area. C2 thinks of that
1282 // abi area as only out_preserve_stack_slots. This does not include
1283 // the area allocated by the C abi to store down integer arguments
1284 // because the java calling convention does not use it. So
1285 // since c2 assumes that there are only out_preserve_stack_slots
1286 // to bias the optoregs (which impacts VMRegs) when actually referencing any actual stack
1287 // location the c calling convention must add in this bias amount
1288 // to make up for the fact that the out_preserve_stack_slots is
1289 // insufficient for C calls. What a mess. I sure hope those 6
1290 // stack words were worth it on every java call!
1291
1292 // Another way of cleaning this up would be for out_preserve_stack_slots
1293 // to take a parameter to say whether it was C or java calling conventions.
1294 // Then things might look a little better (but not much).
1295
1296 int mem_parm_offset = i - SPARC_ARGS_IN_REGS_NUM;
1297 if( mem_parm_offset < 0 ) {
1298 return as_oRegister(i)->as_VMReg();
1299 } else {
1300 int actual_offset = (mem_parm_offset + frame::memory_parameter_word_sp_offset) * VMRegImpl::slots_per_word;
1301 // Now return a biased offset that will be correct when out_preserve_slots is added back in
1302 return VMRegImpl::stack2reg(actual_offset - SharedRuntime::out_preserve_stack_slots());
1303 }
1304 }
1305
1306
1307 int SharedRuntime::c_calling_convention(const BasicType *sig_bt,
1308 VMRegPair *regs,
1309 int total_args_passed) {
1310
1311 // Return the number of VMReg stack_slots needed for the args.
1312 // This value does not include an abi space (like register window
1313 // save area).
1314
1315 // The native convention is V8 if !LP64
1316 // The LP64 convention is the V9 convention which is slightly more sane.
1317
1318 // We return the amount of VMReg stack slots we need to reserve for all
1319 // the arguments NOT counting out_preserve_stack_slots. Since we always
1320 // have space for storing at least 6 registers to memory we start with that.
1321 // See int_stk_helper for a further discussion.
1322 int max_stack_slots = (frame::varargs_offset * VMRegImpl::slots_per_word) - SharedRuntime::out_preserve_stack_slots();
1323
1324 #ifdef _LP64
1325 // V9 convention: All things "as-if" on double-wide stack slots.
1326 // Hoist any int/ptr/long's in the first 6 to int regs.
1327 // Hoist any flt/dbl's in the first 16 dbl regs.
1328 int j = 0; // Count of actual args, not HALVES
1329 for( int i=0; i<total_args_passed; i++, j++ ) {
1330 switch( sig_bt[i] ) {
1331 case T_BOOLEAN:
1332 case T_BYTE:
1333 case T_CHAR:
1334 case T_INT:
1335 case T_SHORT:
1336 regs[i].set1( int_stk_helper( j ) ); break;
1337 case T_LONG:
1338 assert( sig_bt[i+1] == T_VOID, "expecting half" );
1339 case T_ADDRESS: // raw pointers, like current thread, for VM calls
1340 case T_ARRAY:
1341 case T_OBJECT:
1342 regs[i].set2( int_stk_helper( j ) );
1343 break;
1344 case T_FLOAT:
1345 if ( j < 16 ) {
1346 // V9ism: floats go in ODD registers
1347 regs[i].set1(as_FloatRegister(1 + (j<<1))->as_VMReg());
1348 } else {
1349 // V9ism: floats go in ODD stack slot
1350 regs[i].set1(VMRegImpl::stack2reg(1 + (j<<1)));
1351 }
1352 break;
1353 case T_DOUBLE:
1354 assert( sig_bt[i+1] == T_VOID, "expecting half" );
1355 if ( j < 16 ) {
1356 // V9ism: doubles go in EVEN/ODD regs
1357 regs[i].set2(as_FloatRegister(j<<1)->as_VMReg());
1358 } else {
1359 // V9ism: doubles go in EVEN/ODD stack slots
1360 regs[i].set2(VMRegImpl::stack2reg(j<<1));
1361 }
1362 break;
1363 case T_VOID: regs[i].set_bad(); j--; break; // Do not count HALVES
1364 default:
1365 ShouldNotReachHere();
1366 }
1367 if (regs[i].first()->is_stack()) {
1368 int off = regs[i].first()->reg2stack();
1369 if (off > max_stack_slots) max_stack_slots = off;
1370 }
1371 if (regs[i].second()->is_stack()) {
1372 int off = regs[i].second()->reg2stack();
1373 if (off > max_stack_slots) max_stack_slots = off;
1374 }
1375 }
1376
1377 #else // _LP64
1378 // V8 convention: first 6 things in O-regs, rest on stack.
1379 // Alignment is willy-nilly.
1380 for( int i=0; i<total_args_passed; i++ ) {
1381 switch( sig_bt[i] ) {
1382 case T_ADDRESS: // raw pointers, like current thread, for VM calls
1383 case T_ARRAY:
1384 case T_BOOLEAN:
1385 case T_BYTE:
1386 case T_CHAR:
1387 case T_FLOAT:
1388 case T_INT:
1389 case T_OBJECT:
1390 case T_SHORT:
1391 regs[i].set1( int_stk_helper( i ) );
1392 break;
1393 case T_DOUBLE:
1394 case T_LONG:
1395 assert( sig_bt[i+1] == T_VOID, "expecting half" );
1396 regs[i].set_pair( int_stk_helper( i+1 ), int_stk_helper( i ) );
1397 break;
1398 case T_VOID: regs[i].set_bad(); break;
1399 default:
1400 ShouldNotReachHere();
1401 }
1402 if (regs[i].first()->is_stack()) {
1403 int off = regs[i].first()->reg2stack();
1404 if (off > max_stack_slots) max_stack_slots = off;
1405 }
1406 if (regs[i].second()->is_stack()) {
1407 int off = regs[i].second()->reg2stack();
1408 if (off > max_stack_slots) max_stack_slots = off;
1409 }
1410 }
1411 #endif // _LP64
1412
1413 return round_to(max_stack_slots + 1, 2);
1414
1415 }
1416
1417
1418 // ---------------------------------------------------------------------------
1419 void SharedRuntime::save_native_result(MacroAssembler *masm, BasicType ret_type, int frame_slots) {
1420 switch (ret_type) {
1421 case T_FLOAT:
1422 __ stf(FloatRegisterImpl::S, F0, SP, frame_slots*VMRegImpl::stack_slot_size - 4+STACK_BIAS);
1423 break;
1424 case T_DOUBLE:
1425 __ stf(FloatRegisterImpl::D, F0, SP, frame_slots*VMRegImpl::stack_slot_size - 8+STACK_BIAS);
1426 break;
1427 }
1428 }
1429
1430 void SharedRuntime::restore_native_result(MacroAssembler *masm, BasicType ret_type, int frame_slots) {
1431 switch (ret_type) {
1432 case T_FLOAT:
1433 __ ldf(FloatRegisterImpl::S, SP, frame_slots*VMRegImpl::stack_slot_size - 4+STACK_BIAS, F0);
1434 break;
1435 case T_DOUBLE:
1436 __ ldf(FloatRegisterImpl::D, SP, frame_slots*VMRegImpl::stack_slot_size - 8+STACK_BIAS, F0);
1437 break;
1438 }
1439 }
1440
1441 // Check and forward and pending exception. Thread is stored in
1442 // L7_thread_cache and possibly NOT in G2_thread. Since this is a native call, there
1443 // is no exception handler. We merely pop this frame off and throw the
1444 // exception in the caller's frame.
1445 static void check_forward_pending_exception(MacroAssembler *masm, Register Rex_oop) {
1446 Label L;
1447 __ br_null(Rex_oop, false, Assembler::pt, L);
1448 __ delayed()->mov(L7_thread_cache, G2_thread); // restore in case we have exception
1449 // Since this is a native call, we *know* the proper exception handler
1450 // without calling into the VM: it's the empty function. Just pop this
1451 // frame and then jump to forward_exception_entry; O7 will contain the
1452 // native caller's return PC.
1453 AddressLiteral exception_entry(StubRoutines::forward_exception_entry());
1454 __ jump_to(exception_entry, G3_scratch);
1455 __ delayed()->restore(); // Pop this frame off.
1456 __ bind(L);
1457 }
1458
1459 // A simple move of integer like type
1460 static void simple_move32(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
1461 if (src.first()->is_stack()) {
1462 if (dst.first()->is_stack()) {
1463 // stack to stack
1464 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, L5);
1465 __ st(L5, SP, reg2offset(dst.first()) + STACK_BIAS);
1466 } else {
1467 // stack to reg
1468 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_Register());
1469 }
1470 } else if (dst.first()->is_stack()) {
1471 // reg to stack
1472 __ st(src.first()->as_Register(), SP, reg2offset(dst.first()) + STACK_BIAS);
1473 } else {
1474 __ mov(src.first()->as_Register(), dst.first()->as_Register());
1475 }
1476 }
1477
1478 // On 64 bit we will store integer like items to the stack as
1479 // 64 bits items (sparc abi) even though java would only store
1480 // 32bits for a parameter. On 32bit it will simply be 32 bits
1481 // So this routine will do 32->32 on 32bit and 32->64 on 64bit
1482 static void move32_64(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
1483 if (src.first()->is_stack()) {
1484 if (dst.first()->is_stack()) {
1485 // stack to stack
1486 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, L5);
1487 __ st_ptr(L5, SP, reg2offset(dst.first()) + STACK_BIAS);
1488 } else {
1489 // stack to reg
1490 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_Register());
1491 }
1492 } else if (dst.first()->is_stack()) {
1493 // reg to stack
1494 __ st_ptr(src.first()->as_Register(), SP, reg2offset(dst.first()) + STACK_BIAS);
1495 } else {
1496 __ mov(src.first()->as_Register(), dst.first()->as_Register());
1497 }
1498 }
1499
1500
1501 // An oop arg. Must pass a handle not the oop itself
1502 static void object_move(MacroAssembler* masm,
1503 OopMap* map,
1504 int oop_handle_offset,
1505 int framesize_in_slots,
1506 VMRegPair src,
1507 VMRegPair dst,
1508 bool is_receiver,
1509 int* receiver_offset) {
1510
1511 // must pass a handle. First figure out the location we use as a handle
1512
1513 if (src.first()->is_stack()) {
1514 // Oop is already on the stack
1515 Register rHandle = dst.first()->is_stack() ? L5 : dst.first()->as_Register();
1516 __ add(FP, reg2offset(src.first()) + STACK_BIAS, rHandle);
1517 __ ld_ptr(rHandle, 0, L4);
1518 #ifdef _LP64
1519 __ movr( Assembler::rc_z, L4, G0, rHandle );
1520 #else
1521 __ tst( L4 );
1522 __ movcc( Assembler::zero, false, Assembler::icc, G0, rHandle );
1523 #endif
1524 if (dst.first()->is_stack()) {
1525 __ st_ptr(rHandle, SP, reg2offset(dst.first()) + STACK_BIAS);
1526 }
1527 int offset_in_older_frame = src.first()->reg2stack() + SharedRuntime::out_preserve_stack_slots();
1528 if (is_receiver) {
1529 *receiver_offset = (offset_in_older_frame + framesize_in_slots) * VMRegImpl::stack_slot_size;
1530 }
1531 map->set_oop(VMRegImpl::stack2reg(offset_in_older_frame + framesize_in_slots));
1532 } else {
1533 // Oop is in an input register pass we must flush it to the stack
1534 const Register rOop = src.first()->as_Register();
1535 const Register rHandle = L5;
1536 int oop_slot = rOop->input_number() * VMRegImpl::slots_per_word + oop_handle_offset;
1537 int offset = oop_slot*VMRegImpl::stack_slot_size;
1538 Label skip;
1539 __ st_ptr(rOop, SP, offset + STACK_BIAS);
1540 if (is_receiver) {
1541 *receiver_offset = oop_slot * VMRegImpl::stack_slot_size;
1542 }
1543 map->set_oop(VMRegImpl::stack2reg(oop_slot));
1544 __ add(SP, offset + STACK_BIAS, rHandle);
1545 #ifdef _LP64
1546 __ movr( Assembler::rc_z, rOop, G0, rHandle );
1547 #else
1548 __ tst( rOop );
1549 __ movcc( Assembler::zero, false, Assembler::icc, G0, rHandle );
1550 #endif
1551
1552 if (dst.first()->is_stack()) {
1553 __ st_ptr(rHandle, SP, reg2offset(dst.first()) + STACK_BIAS);
1554 } else {
1555 __ mov(rHandle, dst.first()->as_Register());
1556 }
1557 }
1558 }
1559
1560 // A float arg may have to do float reg int reg conversion
1561 static void float_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
1562 assert(!src.second()->is_valid() && !dst.second()->is_valid(), "bad float_move");
1563
1564 if (src.first()->is_stack()) {
1565 if (dst.first()->is_stack()) {
1566 // stack to stack the easiest of the bunch
1567 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, L5);
1568 __ st(L5, SP, reg2offset(dst.first()) + STACK_BIAS);
1569 } else {
1570 // stack to reg
1571 if (dst.first()->is_Register()) {
1572 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_Register());
1573 } else {
1574 __ ldf(FloatRegisterImpl::S, FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_FloatRegister());
1575 }
1576 }
1577 } else if (dst.first()->is_stack()) {
1578 // reg to stack
1579 if (src.first()->is_Register()) {
1580 __ st(src.first()->as_Register(), SP, reg2offset(dst.first()) + STACK_BIAS);
1581 } else {
1582 __ stf(FloatRegisterImpl::S, src.first()->as_FloatRegister(), SP, reg2offset(dst.first()) + STACK_BIAS);
1583 }
1584 } else {
1585 // reg to reg
1586 if (src.first()->is_Register()) {
1587 if (dst.first()->is_Register()) {
1588 // gpr -> gpr
1589 __ mov(src.first()->as_Register(), dst.first()->as_Register());
1590 } else {
1591 // gpr -> fpr
1592 __ st(src.first()->as_Register(), FP, -4 + STACK_BIAS);
1593 __ ldf(FloatRegisterImpl::S, FP, -4 + STACK_BIAS, dst.first()->as_FloatRegister());
1594 }
1595 } else if (dst.first()->is_Register()) {
1596 // fpr -> gpr
1597 __ stf(FloatRegisterImpl::S, src.first()->as_FloatRegister(), FP, -4 + STACK_BIAS);
1598 __ ld(FP, -4 + STACK_BIAS, dst.first()->as_Register());
1599 } else {
1600 // fpr -> fpr
1601 // In theory these overlap but the ordering is such that this is likely a nop
1602 if ( src.first() != dst.first()) {
1603 __ fmov(FloatRegisterImpl::S, src.first()->as_FloatRegister(), dst.first()->as_FloatRegister());
1604 }
1605 }
1606 }
1607 }
1608
1609 static void split_long_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
1610 VMRegPair src_lo(src.first());
1611 VMRegPair src_hi(src.second());
1612 VMRegPair dst_lo(dst.first());
1613 VMRegPair dst_hi(dst.second());
1614 simple_move32(masm, src_lo, dst_lo);
1615 simple_move32(masm, src_hi, dst_hi);
1616 }
1617
1618 // A long move
1619 static void long_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
1620
1621 // Do the simple ones here else do two int moves
1622 if (src.is_single_phys_reg() ) {
1623 if (dst.is_single_phys_reg()) {
1624 __ mov(src.first()->as_Register(), dst.first()->as_Register());
1625 } else {
1626 // split src into two separate registers
1627 // Remember hi means hi address or lsw on sparc
1628 // Move msw to lsw
1629 if (dst.second()->is_reg()) {
1630 // MSW -> MSW
1631 __ srax(src.first()->as_Register(), 32, dst.first()->as_Register());
1632 // Now LSW -> LSW
1633 // this will only move lo -> lo and ignore hi
1634 VMRegPair split(dst.second());
1635 simple_move32(masm, src, split);
1636 } else {
1637 VMRegPair split(src.first(), L4->as_VMReg());
1638 // MSW -> MSW (lo ie. first word)
1639 __ srax(src.first()->as_Register(), 32, L4);
1640 split_long_move(masm, split, dst);
1641 }
1642 }
1643 } else if (dst.is_single_phys_reg()) {
1644 if (src.is_adjacent_aligned_on_stack(2)) {
1645 __ ldx(FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_Register());
1646 } else {
1647 // dst is a single reg.
1648 // Remember lo is low address not msb for stack slots
1649 // and lo is the "real" register for registers
1650 // src is
1651
1652 VMRegPair split;
1653
1654 if (src.first()->is_reg()) {
1655 // src.lo (msw) is a reg, src.hi is stk/reg
1656 // we will move: src.hi (LSW) -> dst.lo, src.lo (MSW) -> src.lo [the MSW is in the LSW of the reg]
1657 split.set_pair(dst.first(), src.first());
1658 } else {
1659 // msw is stack move to L5
1660 // lsw is stack move to dst.lo (real reg)
1661 // we will move: src.hi (LSW) -> dst.lo, src.lo (MSW) -> L5
1662 split.set_pair(dst.first(), L5->as_VMReg());
1663 }
1664
1665 // src.lo -> src.lo/L5, src.hi -> dst.lo (the real reg)
1666 // msw -> src.lo/L5, lsw -> dst.lo
1667 split_long_move(masm, src, split);
1668
1669 // So dst now has the low order correct position the
1670 // msw half
1671 __ sllx(split.first()->as_Register(), 32, L5);
1672
1673 const Register d = dst.first()->as_Register();
1674 __ or3(L5, d, d);
1675 }
1676 } else {
1677 // For LP64 we can probably do better.
1678 split_long_move(masm, src, dst);
1679 }
1680 }
1681
1682 // A double move
1683 static void double_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
1684
1685 // The painful thing here is that like long_move a VMRegPair might be
1686 // 1: a single physical register
1687 // 2: two physical registers (v8)
1688 // 3: a physical reg [lo] and a stack slot [hi] (v8)
1689 // 4: two stack slots
1690
1691 // Since src is always a java calling convention we know that the src pair
1692 // is always either all registers or all stack (and aligned?)
1693
1694 // in a register [lo] and a stack slot [hi]
1695 if (src.first()->is_stack()) {
1696 if (dst.first()->is_stack()) {
1697 // stack to stack the easiest of the bunch
1698 // ought to be a way to do this where if alignment is ok we use ldd/std when possible
1699 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, L5);
1700 __ ld(FP, reg2offset(src.second()) + STACK_BIAS, L4);
1701 __ st(L5, SP, reg2offset(dst.first()) + STACK_BIAS);
1702 __ st(L4, SP, reg2offset(dst.second()) + STACK_BIAS);
1703 } else {
1704 // stack to reg
1705 if (dst.second()->is_stack()) {
1706 // stack -> reg, stack -> stack
1707 __ ld(FP, reg2offset(src.second()) + STACK_BIAS, L4);
1708 if (dst.first()->is_Register()) {
1709 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_Register());
1710 } else {
1711 __ ldf(FloatRegisterImpl::S, FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_FloatRegister());
1712 }
1713 // This was missing. (very rare case)
1714 __ st(L4, SP, reg2offset(dst.second()) + STACK_BIAS);
1715 } else {
1716 // stack -> reg
1717 // Eventually optimize for alignment QQQ
1718 if (dst.first()->is_Register()) {
1719 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_Register());
1720 __ ld(FP, reg2offset(src.second()) + STACK_BIAS, dst.second()->as_Register());
1721 } else {
1722 __ ldf(FloatRegisterImpl::S, FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_FloatRegister());
1723 __ ldf(FloatRegisterImpl::S, FP, reg2offset(src.second()) + STACK_BIAS, dst.second()->as_FloatRegister());
1724 }
1725 }
1726 }
1727 } else if (dst.first()->is_stack()) {
1728 // reg to stack
1729 if (src.first()->is_Register()) {
1730 // Eventually optimize for alignment QQQ
1731 __ st(src.first()->as_Register(), SP, reg2offset(dst.first()) + STACK_BIAS);
1732 if (src.second()->is_stack()) {
1733 __ ld(FP, reg2offset(src.second()) + STACK_BIAS, L4);
1734 __ st(L4, SP, reg2offset(dst.second()) + STACK_BIAS);
1735 } else {
1736 __ st(src.second()->as_Register(), SP, reg2offset(dst.second()) + STACK_BIAS);
1737 }
1738 } else {
1739 // fpr to stack
1740 if (src.second()->is_stack()) {
1741 ShouldNotReachHere();
1742 } else {
1743 // Is the stack aligned?
1744 if (reg2offset(dst.first()) & 0x7) {
1745 // No do as pairs
1746 __ stf(FloatRegisterImpl::S, src.first()->as_FloatRegister(), SP, reg2offset(dst.first()) + STACK_BIAS);
1747 __ stf(FloatRegisterImpl::S, src.second()->as_FloatRegister(), SP, reg2offset(dst.second()) + STACK_BIAS);
1748 } else {
1749 __ stf(FloatRegisterImpl::D, src.first()->as_FloatRegister(), SP, reg2offset(dst.first()) + STACK_BIAS);
1750 }
1751 }
1752 }
1753 } else {
1754 // reg to reg
1755 if (src.first()->is_Register()) {
1756 if (dst.first()->is_Register()) {
1757 // gpr -> gpr
1758 __ mov(src.first()->as_Register(), dst.first()->as_Register());
1759 __ mov(src.second()->as_Register(), dst.second()->as_Register());
1760 } else {
1761 // gpr -> fpr
1762 // ought to be able to do a single store
1763 __ stx(src.first()->as_Register(), FP, -8 + STACK_BIAS);
1764 __ stx(src.second()->as_Register(), FP, -4 + STACK_BIAS);
1765 // ought to be able to do a single load
1766 __ ldf(FloatRegisterImpl::S, FP, -8 + STACK_BIAS, dst.first()->as_FloatRegister());
1767 __ ldf(FloatRegisterImpl::S, FP, -4 + STACK_BIAS, dst.second()->as_FloatRegister());
1768 }
1769 } else if (dst.first()->is_Register()) {
1770 // fpr -> gpr
1771 // ought to be able to do a single store
1772 __ stf(FloatRegisterImpl::D, src.first()->as_FloatRegister(), FP, -8 + STACK_BIAS);
1773 // ought to be able to do a single load
1774 // REMEMBER first() is low address not LSB
1775 __ ld(FP, -8 + STACK_BIAS, dst.first()->as_Register());
1776 if (dst.second()->is_Register()) {
1777 __ ld(FP, -4 + STACK_BIAS, dst.second()->as_Register());
1778 } else {
1779 __ ld(FP, -4 + STACK_BIAS, L4);
1780 __ st(L4, SP, reg2offset(dst.second()) + STACK_BIAS);
1781 }
1782 } else {
1783 // fpr -> fpr
1784 // In theory these overlap but the ordering is such that this is likely a nop
1785 if ( src.first() != dst.first()) {
1786 __ fmov(FloatRegisterImpl::D, src.first()->as_FloatRegister(), dst.first()->as_FloatRegister());
1787 }
1788 }
1789 }
1790 }
1791
1792 // Creates an inner frame if one hasn't already been created, and
1793 // saves a copy of the thread in L7_thread_cache
1794 static void create_inner_frame(MacroAssembler* masm, bool* already_created) {
1795 if (!*already_created) {
1796 __ save_frame(0);
1797 // Save thread in L7 (INNER FRAME); it crosses a bunch of VM calls below
1798 // Don't use save_thread because it smashes G2 and we merely want to save a
1799 // copy
1800 __ mov(G2_thread, L7_thread_cache);
1801 *already_created = true;
1802 }
1803 }
1804
1805 // ---------------------------------------------------------------------------
1806 // Generate a native wrapper for a given method. The method takes arguments
1807 // in the Java compiled code convention, marshals them to the native
1808 // convention (handlizes oops, etc), transitions to native, makes the call,
1809 // returns to java state (possibly blocking), unhandlizes any result and
1810 // returns.
1811 nmethod *SharedRuntime::generate_native_wrapper(MacroAssembler* masm,
1812 methodHandle method,
1813 int total_in_args,
1814 int comp_args_on_stack, // in VMRegStackSlots
1815 BasicType *in_sig_bt,
1816 VMRegPair *in_regs,
1817 BasicType ret_type) {
1818
1819 // Native nmethod wrappers never take possesion of the oop arguments.
1820 // So the caller will gc the arguments. The only thing we need an
1821 // oopMap for is if the call is static
1822 //
1823 // An OopMap for lock (and class if static), and one for the VM call itself
1824 OopMapSet *oop_maps = new OopMapSet();
1825 intptr_t start = (intptr_t)__ pc();
1826
1827 // First thing make an ic check to see if we should even be here
1828 {
1829 Label L;
1830 const Register temp_reg = G3_scratch;
1831 AddressLiteral ic_miss(SharedRuntime::get_ic_miss_stub());
1832 __ verify_oop(O0);
1833 __ load_klass(O0, temp_reg);
1834 __ cmp(temp_reg, G5_inline_cache_reg);
1835 __ brx(Assembler::equal, true, Assembler::pt, L);
1836 __ delayed()->nop();
1837
1838 __ jump_to(ic_miss, temp_reg);
1839 __ delayed()->nop();
1840 __ align(CodeEntryAlignment);
1841 __ bind(L);
1842 }
1843
1844 int vep_offset = ((intptr_t)__ pc()) - start;
1845
1846 #ifdef COMPILER1
1847 if (InlineObjectHash && method->intrinsic_id() == vmIntrinsics::_hashCode) {
1848 // Object.hashCode can pull the hashCode from the header word
1849 // instead of doing a full VM transition once it's been computed.
1850 // Since hashCode is usually polymorphic at call sites we can't do
1851 // this optimization at the call site without a lot of work.
1852 Label slowCase;
1853 Register receiver = O0;
1854 Register result = O0;
1855 Register header = G3_scratch;
1856 Register hash = G3_scratch; // overwrite header value with hash value
1857 Register mask = G1; // to get hash field from header
1858
1859 // Read the header and build a mask to get its hash field. Give up if the object is not unlocked.
1860 // We depend on hash_mask being at most 32 bits and avoid the use of
1861 // hash_mask_in_place because it could be larger than 32 bits in a 64-bit
1862 // vm: see markOop.hpp.
1863 __ ld_ptr(receiver, oopDesc::mark_offset_in_bytes(), header);
1864 __ sethi(markOopDesc::hash_mask, mask);
1865 __ btst(markOopDesc::unlocked_value, header);
1866 __ br(Assembler::zero, false, Assembler::pn, slowCase);
1867 if (UseBiasedLocking) {
1868 // Check if biased and fall through to runtime if so
1869 __ delayed()->nop();
1870 __ btst(markOopDesc::biased_lock_bit_in_place, header);
1871 __ br(Assembler::notZero, false, Assembler::pn, slowCase);
1872 }
1873 __ delayed()->or3(mask, markOopDesc::hash_mask & 0x3ff, mask);
1874
1875 // Check for a valid (non-zero) hash code and get its value.
1876 #ifdef _LP64
1877 __ srlx(header, markOopDesc::hash_shift, hash);
1878 #else
1879 __ srl(header, markOopDesc::hash_shift, hash);
1880 #endif
1881 __ andcc(hash, mask, hash);
1882 __ br(Assembler::equal, false, Assembler::pn, slowCase);
1883 __ delayed()->nop();
1884
1885 // leaf return.
1886 __ retl();
1887 __ delayed()->mov(hash, result);
1888 __ bind(slowCase);
1889 }
1890 #endif // COMPILER1
1891
1892
1893 // We have received a description of where all the java arg are located
1894 // on entry to the wrapper. We need to convert these args to where
1895 // the jni function will expect them. To figure out where they go
1896 // we convert the java signature to a C signature by inserting
1897 // the hidden arguments as arg[0] and possibly arg[1] (static method)
1898
1899 int total_c_args = total_in_args + 1;
1900 if (method->is_static()) {
1901 total_c_args++;
1902 }
1903
1904 BasicType* out_sig_bt = NEW_RESOURCE_ARRAY(BasicType, total_c_args);
1905 VMRegPair * out_regs = NEW_RESOURCE_ARRAY(VMRegPair, total_c_args);
1906
1907 int argc = 0;
1908 out_sig_bt[argc++] = T_ADDRESS;
1909 if (method->is_static()) {
1910 out_sig_bt[argc++] = T_OBJECT;
1911 }
1912
1913 for (int i = 0; i < total_in_args ; i++ ) {
1914 out_sig_bt[argc++] = in_sig_bt[i];
1915 }
1916
1917 // Now figure out where the args must be stored and how much stack space
1918 // they require (neglecting out_preserve_stack_slots but space for storing
1919 // the 1st six register arguments). It's weird see int_stk_helper.
1920 //
1921 int out_arg_slots;
1922 out_arg_slots = c_calling_convention(out_sig_bt, out_regs, total_c_args);
1923
1924 // Compute framesize for the wrapper. We need to handlize all oops in
1925 // registers. We must create space for them here that is disjoint from
1926 // the windowed save area because we have no control over when we might
1927 // flush the window again and overwrite values that gc has since modified.
1928 // (The live window race)
1929 //
1930 // We always just allocate 6 word for storing down these object. This allow
1931 // us to simply record the base and use the Ireg number to decide which
1932 // slot to use. (Note that the reg number is the inbound number not the
1933 // outbound number).
1934 // We must shuffle args to match the native convention, and include var-args space.
1935
1936 // Calculate the total number of stack slots we will need.
1937
1938 // First count the abi requirement plus all of the outgoing args
1939 int stack_slots = SharedRuntime::out_preserve_stack_slots() + out_arg_slots;
1940
1941 // Now the space for the inbound oop handle area
1942
1943 int oop_handle_offset = stack_slots;
1944 stack_slots += 6*VMRegImpl::slots_per_word;
1945
1946 // Now any space we need for handlizing a klass if static method
1947
1948 int oop_temp_slot_offset = 0;
1949 int klass_slot_offset = 0;
1950 int klass_offset = -1;
1951 int lock_slot_offset = 0;
1952 bool is_static = false;
1953
1954 if (method->is_static()) {
1955 klass_slot_offset = stack_slots;
1956 stack_slots += VMRegImpl::slots_per_word;
1957 klass_offset = klass_slot_offset * VMRegImpl::stack_slot_size;
1958 is_static = true;
1959 }
1960
1961 // Plus a lock if needed
1962
1963 if (method->is_synchronized()) {
1964 lock_slot_offset = stack_slots;
1965 stack_slots += VMRegImpl::slots_per_word;
1966 }
1967
1968 // Now a place to save return value or as a temporary for any gpr -> fpr moves
1969 stack_slots += 2;
1970
1971 // Ok The space we have allocated will look like:
1972 //
1973 //
1974 // FP-> | |
1975 // |---------------------|
1976 // | 2 slots for moves |
1977 // |---------------------|
1978 // | lock box (if sync) |
1979 // |---------------------| <- lock_slot_offset
1980 // | klass (if static) |
1981 // |---------------------| <- klass_slot_offset
1982 // | oopHandle area |
1983 // |---------------------| <- oop_handle_offset
1984 // | outbound memory |
1985 // | based arguments |
1986 // | |
1987 // |---------------------|
1988 // | vararg area |
1989 // |---------------------|
1990 // | |
1991 // SP-> | out_preserved_slots |
1992 //
1993 //
1994
1995
1996 // Now compute actual number of stack words we need rounding to make
1997 // stack properly aligned.
1998 stack_slots = round_to(stack_slots, 2 * VMRegImpl::slots_per_word);
1999
2000 int stack_size = stack_slots * VMRegImpl::stack_slot_size;
2001
2002 // Generate stack overflow check before creating frame
2003 __ generate_stack_overflow_check(stack_size);
2004
2005 // Generate a new frame for the wrapper.
2006 __ save(SP, -stack_size, SP);
2007
2008 int frame_complete = ((intptr_t)__ pc()) - start;
2009
2010 __ verify_thread();
2011
2012
2013 //
2014 // We immediately shuffle the arguments so that any vm call we have to
2015 // make from here on out (sync slow path, jvmti, etc.) we will have
2016 // captured the oops from our caller and have a valid oopMap for
2017 // them.
2018
2019 // -----------------
2020 // The Grand Shuffle
2021 //
2022 // Natives require 1 or 2 extra arguments over the normal ones: the JNIEnv*
2023 // (derived from JavaThread* which is in L7_thread_cache) and, if static,
2024 // the class mirror instead of a receiver. This pretty much guarantees that
2025 // register layout will not match. We ignore these extra arguments during
2026 // the shuffle. The shuffle is described by the two calling convention
2027 // vectors we have in our possession. We simply walk the java vector to
2028 // get the source locations and the c vector to get the destinations.
2029 // Because we have a new window and the argument registers are completely
2030 // disjoint ( I0 -> O1, I1 -> O2, ...) we have nothing to worry about
2031 // here.
2032
2033 // This is a trick. We double the stack slots so we can claim
2034 // the oops in the caller's frame. Since we are sure to have
2035 // more args than the caller doubling is enough to make
2036 // sure we can capture all the incoming oop args from the
2037 // caller.
2038 //
2039 OopMap* map = new OopMap(stack_slots * 2, 0 /* arg_slots*/);
2040 int c_arg = total_c_args - 1;
2041 // Record sp-based slot for receiver on stack for non-static methods
2042 int receiver_offset = -1;
2043
2044 // We move the arguments backward because the floating point registers
2045 // destination will always be to a register with a greater or equal register
2046 // number or the stack.
2047
2048 #ifdef ASSERT
2049 bool reg_destroyed[RegisterImpl::number_of_registers];
2050 bool freg_destroyed[FloatRegisterImpl::number_of_registers];
2051 for ( int r = 0 ; r < RegisterImpl::number_of_registers ; r++ ) {
2052 reg_destroyed[r] = false;
2053 }
2054 for ( int f = 0 ; f < FloatRegisterImpl::number_of_registers ; f++ ) {
2055 freg_destroyed[f] = false;
2056 }
2057
2058 #endif /* ASSERT */
2059
2060 for ( int i = total_in_args - 1; i >= 0 ; i--, c_arg-- ) {
2061
2062 #ifdef ASSERT
2063 if (in_regs[i].first()->is_Register()) {
2064 assert(!reg_destroyed[in_regs[i].first()->as_Register()->encoding()], "ack!");
2065 } else if (in_regs[i].first()->is_FloatRegister()) {
2066 assert(!freg_destroyed[in_regs[i].first()->as_FloatRegister()->encoding(FloatRegisterImpl::S)], "ack!");
2067 }
2068 if (out_regs[c_arg].first()->is_Register()) {
2069 reg_destroyed[out_regs[c_arg].first()->as_Register()->encoding()] = true;
2070 } else if (out_regs[c_arg].first()->is_FloatRegister()) {
2071 freg_destroyed[out_regs[c_arg].first()->as_FloatRegister()->encoding(FloatRegisterImpl::S)] = true;
2072 }
2073 #endif /* ASSERT */
2074
2075 switch (in_sig_bt[i]) {
2076 case T_ARRAY:
2077 case T_OBJECT:
2078 object_move(masm, map, oop_handle_offset, stack_slots, in_regs[i], out_regs[c_arg],
2079 ((i == 0) && (!is_static)),
2080 &receiver_offset);
2081 break;
2082 case T_VOID:
2083 break;
2084
2085 case T_FLOAT:
2086 float_move(masm, in_regs[i], out_regs[c_arg]);
2087 break;
2088
2089 case T_DOUBLE:
2090 assert( i + 1 < total_in_args &&
2091 in_sig_bt[i + 1] == T_VOID &&
2092 out_sig_bt[c_arg+1] == T_VOID, "bad arg list");
2093 double_move(masm, in_regs[i], out_regs[c_arg]);
2094 break;
2095
2096 case T_LONG :
2097 long_move(masm, in_regs[i], out_regs[c_arg]);
2098 break;
2099
2100 case T_ADDRESS: assert(false, "found T_ADDRESS in java args");
2101
2102 default:
2103 move32_64(masm, in_regs[i], out_regs[c_arg]);
2104 }
2105 }
2106
2107 // Pre-load a static method's oop into O1. Used both by locking code and
2108 // the normal JNI call code.
2109 if (method->is_static()) {
2110 __ set_oop_constant(JNIHandles::make_local(Klass::cast(method->method_holder())->java_mirror()), O1);
2111
2112 // Now handlize the static class mirror in O1. It's known not-null.
2113 __ st_ptr(O1, SP, klass_offset + STACK_BIAS);
2114 map->set_oop(VMRegImpl::stack2reg(klass_slot_offset));
2115 __ add(SP, klass_offset + STACK_BIAS, O1);
2116 }
2117
2118
2119 const Register L6_handle = L6;
2120
2121 if (method->is_synchronized()) {
2122 __ mov(O1, L6_handle);
2123 }
2124
2125 // We have all of the arguments setup at this point. We MUST NOT touch any Oregs
2126 // except O6/O7. So if we must call out we must push a new frame. We immediately
2127 // push a new frame and flush the windows.
2128
2129 #ifdef _LP64
2130 intptr_t thepc = (intptr_t) __ pc();
2131 {
2132 address here = __ pc();
2133 // Call the next instruction
2134 __ call(here + 8, relocInfo::none);
2135 __ delayed()->nop();
2136 }
2137 #else
2138 intptr_t thepc = __ load_pc_address(O7, 0);
2139 #endif /* _LP64 */
2140
2141 // We use the same pc/oopMap repeatedly when we call out
2142 oop_maps->add_gc_map(thepc - start, map);
2143
2144 // O7 now has the pc loaded that we will use when we finally call to native.
2145
2146 // Save thread in L7; it crosses a bunch of VM calls below
2147 // Don't use save_thread because it smashes G2 and we merely
2148 // want to save a copy
2149 __ mov(G2_thread, L7_thread_cache);
2150
2151
2152 // If we create an inner frame once is plenty
2153 // when we create it we must also save G2_thread
2154 bool inner_frame_created = false;
2155
2156 // dtrace method entry support
2157 {
2158 SkipIfEqual skip_if(
2159 masm, G3_scratch, &DTraceMethodProbes, Assembler::zero);
2160 // create inner frame
2161 __ save_frame(0);
2162 __ mov(G2_thread, L7_thread_cache);
2163 __ set_oop_constant(JNIHandles::make_local(method()), O1);
2164 __ call_VM_leaf(L7_thread_cache,
2165 CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_entry),
2166 G2_thread, O1);
2167 __ restore();
2168 }
2169
2170 // RedefineClasses() tracing support for obsolete method entry
2171 if (RC_TRACE_IN_RANGE(0x00001000, 0x00002000)) {
2172 // create inner frame
2173 __ save_frame(0);
2174 __ mov(G2_thread, L7_thread_cache);
2175 __ set_oop_constant(JNIHandles::make_local(method()), O1);
2176 __ call_VM_leaf(L7_thread_cache,
2177 CAST_FROM_FN_PTR(address, SharedRuntime::rc_trace_method_entry),
2178 G2_thread, O1);
2179 __ restore();
2180 }
2181
2182 // We are in the jni frame unless saved_frame is true in which case
2183 // we are in one frame deeper (the "inner" frame). If we are in the
2184 // "inner" frames the args are in the Iregs and if the jni frame then
2185 // they are in the Oregs.
2186 // If we ever need to go to the VM (for locking, jvmti) then
2187 // we will always be in the "inner" frame.
2188
2189 // Lock a synchronized method
2190 int lock_offset = -1; // Set if locked
2191 if (method->is_synchronized()) {
2192 Register Roop = O1;
2193 const Register L3_box = L3;
2194
2195 create_inner_frame(masm, &inner_frame_created);
2196
2197 __ ld_ptr(I1, 0, O1);
2198 Label done;
2199
2200 lock_offset = (lock_slot_offset * VMRegImpl::stack_slot_size);
2201 __ add(FP, lock_offset+STACK_BIAS, L3_box);
2202 #ifdef ASSERT
2203 if (UseBiasedLocking) {
2204 // making the box point to itself will make it clear it went unused
2205 // but also be obviously invalid
2206 __ st_ptr(L3_box, L3_box, 0);
2207 }
2208 #endif // ASSERT
2209 //
2210 // Compiler_lock_object (Roop, Rmark, Rbox, Rscratch) -- kills Rmark, Rbox, Rscratch
2211 //
2212 __ compiler_lock_object(Roop, L1, L3_box, L2);
2213 __ br(Assembler::equal, false, Assembler::pt, done);
2214 __ delayed() -> add(FP, lock_offset+STACK_BIAS, L3_box);
2215
2216
2217 // None of the above fast optimizations worked so we have to get into the
2218 // slow case of monitor enter. Inline a special case of call_VM that
2219 // disallows any pending_exception.
2220 __ mov(Roop, O0); // Need oop in O0
2221 __ mov(L3_box, O1);
2222
2223 // Record last_Java_sp, in case the VM code releases the JVM lock.
2224
2225 __ set_last_Java_frame(FP, I7);
2226
2227 // do the call
2228 __ call(CAST_FROM_FN_PTR(address, SharedRuntime::complete_monitor_locking_C), relocInfo::runtime_call_type);
2229 __ delayed()->mov(L7_thread_cache, O2);
2230
2231 __ restore_thread(L7_thread_cache); // restore G2_thread
2232 __ reset_last_Java_frame();
2233
2234 #ifdef ASSERT
2235 { Label L;
2236 __ ld_ptr(G2_thread, in_bytes(Thread::pending_exception_offset()), O0);
2237 __ br_null(O0, false, Assembler::pt, L);
2238 __ delayed()->nop();
2239 __ stop("no pending exception allowed on exit from IR::monitorenter");
2240 __ bind(L);
2241 }
2242 #endif
2243 __ bind(done);
2244 }
2245
2246
2247 // Finally just about ready to make the JNI call
2248
2249 __ flush_windows();
2250 if (inner_frame_created) {
2251 __ restore();
2252 } else {
2253 // Store only what we need from this frame
2254 // QQQ I think that non-v9 (like we care) we don't need these saves
2255 // either as the flush traps and the current window goes too.
2256 __ st_ptr(FP, SP, FP->sp_offset_in_saved_window()*wordSize + STACK_BIAS);
2257 __ st_ptr(I7, SP, I7->sp_offset_in_saved_window()*wordSize + STACK_BIAS);
2258 }
2259
2260 // get JNIEnv* which is first argument to native
2261
2262 __ add(G2_thread, in_bytes(JavaThread::jni_environment_offset()), O0);
2263
2264 // Use that pc we placed in O7 a while back as the current frame anchor
2265
2266 __ set_last_Java_frame(SP, O7);
2267
2268 // Transition from _thread_in_Java to _thread_in_native.
2269 __ set(_thread_in_native, G3_scratch);
2270 __ st(G3_scratch, G2_thread, JavaThread::thread_state_offset());
2271
2272 // We flushed the windows ages ago now mark them as flushed
2273
2274 // mark windows as flushed
2275 __ set(JavaFrameAnchor::flushed, G3_scratch);
2276
2277 Address flags(G2_thread, JavaThread::frame_anchor_offset() + JavaFrameAnchor::flags_offset());
2278
2279 #ifdef _LP64
2280 AddressLiteral dest(method->native_function());
2281 __ relocate(relocInfo::runtime_call_type);
2282 __ jumpl_to(dest, O7, O7);
2283 #else
2284 __ call(method->native_function(), relocInfo::runtime_call_type);
2285 #endif
2286 __ delayed()->st(G3_scratch, flags);
2287
2288 __ restore_thread(L7_thread_cache); // restore G2_thread
2289
2290 // Unpack native results. For int-types, we do any needed sign-extension
2291 // and move things into I0. The return value there will survive any VM
2292 // calls for blocking or unlocking. An FP or OOP result (handle) is done
2293 // specially in the slow-path code.
2294 switch (ret_type) {
2295 case T_VOID: break; // Nothing to do!
2296 case T_FLOAT: break; // Got it where we want it (unless slow-path)
2297 case T_DOUBLE: break; // Got it where we want it (unless slow-path)
2298 // In 64 bits build result is in O0, in O0, O1 in 32bit build
2299 case T_LONG:
2300 #ifndef _LP64
2301 __ mov(O1, I1);
2302 #endif
2303 // Fall thru
2304 case T_OBJECT: // Really a handle
2305 case T_ARRAY:
2306 case T_INT:
2307 __ mov(O0, I0);
2308 break;
2309 case T_BOOLEAN: __ subcc(G0, O0, G0); __ addc(G0, 0, I0); break; // !0 => true; 0 => false
2310 case T_BYTE : __ sll(O0, 24, O0); __ sra(O0, 24, I0); break;
2311 case T_CHAR : __ sll(O0, 16, O0); __ srl(O0, 16, I0); break; // cannot use and3, 0xFFFF too big as immediate value!
2312 case T_SHORT : __ sll(O0, 16, O0); __ sra(O0, 16, I0); break;
2313 break; // Cannot de-handlize until after reclaiming jvm_lock
2314 default:
2315 ShouldNotReachHere();
2316 }
2317
2318 // must we block?
2319
2320 // Block, if necessary, before resuming in _thread_in_Java state.
2321 // In order for GC to work, don't clear the last_Java_sp until after blocking.
2322 { Label no_block;
2323 AddressLiteral sync_state(SafepointSynchronize::address_of_state());
2324
2325 // Switch thread to "native transition" state before reading the synchronization state.
2326 // This additional state is necessary because reading and testing the synchronization
2327 // state is not atomic w.r.t. GC, as this scenario demonstrates:
2328 // Java thread A, in _thread_in_native state, loads _not_synchronized and is preempted.
2329 // VM thread changes sync state to synchronizing and suspends threads for GC.
2330 // Thread A is resumed to finish this native method, but doesn't block here since it
2331 // didn't see any synchronization is progress, and escapes.
2332 __ set(_thread_in_native_trans, G3_scratch);
2333 __ st(G3_scratch, G2_thread, JavaThread::thread_state_offset());
2334 if(os::is_MP()) {
2335 if (UseMembar) {
2336 // Force this write out before the read below
2337 __ membar(Assembler::StoreLoad);
2338 } else {
2339 // Write serialization page so VM thread can do a pseudo remote membar.
2340 // We use the current thread pointer to calculate a thread specific
2341 // offset to write to within the page. This minimizes bus traffic
2342 // due to cache line collision.
2343 __ serialize_memory(G2_thread, G1_scratch, G3_scratch);
2344 }
2345 }
2346 __ load_contents(sync_state, G3_scratch);
2347 __ cmp(G3_scratch, SafepointSynchronize::_not_synchronized);
2348
2349 Label L;
2350 Address suspend_state(G2_thread, JavaThread::suspend_flags_offset());
2351 __ br(Assembler::notEqual, false, Assembler::pn, L);
2352 __ delayed()->ld(suspend_state, G3_scratch);
2353 __ cmp(G3_scratch, 0);
2354 __ br(Assembler::equal, false, Assembler::pt, no_block);
2355 __ delayed()->nop();
2356 __ bind(L);
2357
2358 // Block. Save any potential method result value before the operation and
2359 // use a leaf call to leave the last_Java_frame setup undisturbed. Doing this
2360 // lets us share the oopMap we used when we went native rather the create
2361 // a distinct one for this pc
2362 //
2363 save_native_result(masm, ret_type, stack_slots);
2364 __ call_VM_leaf(L7_thread_cache,
2365 CAST_FROM_FN_PTR(address, JavaThread::check_special_condition_for_native_trans),
2366 G2_thread);
2367
2368 // Restore any method result value
2369 restore_native_result(masm, ret_type, stack_slots);
2370 __ bind(no_block);
2371 }
2372
2373 // thread state is thread_in_native_trans. Any safepoint blocking has already
2374 // happened so we can now change state to _thread_in_Java.
2375
2376
2377 __ set(_thread_in_Java, G3_scratch);
2378 __ st(G3_scratch, G2_thread, JavaThread::thread_state_offset());
2379
2380
2381 Label no_reguard;
2382 __ ld(G2_thread, JavaThread::stack_guard_state_offset(), G3_scratch);
2383 __ cmp(G3_scratch, JavaThread::stack_guard_yellow_disabled);
2384 __ br(Assembler::notEqual, false, Assembler::pt, no_reguard);
2385 __ delayed()->nop();
2386
2387 save_native_result(masm, ret_type, stack_slots);
2388 __ call(CAST_FROM_FN_PTR(address, SharedRuntime::reguard_yellow_pages));
2389 __ delayed()->nop();
2390
2391 __ restore_thread(L7_thread_cache); // restore G2_thread
2392 restore_native_result(masm, ret_type, stack_slots);
2393
2394 __ bind(no_reguard);
2395
2396 // Handle possible exception (will unlock if necessary)
2397
2398 // native result if any is live in freg or I0 (and I1 if long and 32bit vm)
2399
2400 // Unlock
2401 if (method->is_synchronized()) {
2402 Label done;
2403 Register I2_ex_oop = I2;
2404 const Register L3_box = L3;
2405 // Get locked oop from the handle we passed to jni
2406 __ ld_ptr(L6_handle, 0, L4);
2407 __ add(SP, lock_offset+STACK_BIAS, L3_box);
2408 // Must save pending exception around the slow-path VM call. Since it's a
2409 // leaf call, the pending exception (if any) can be kept in a register.
2410 __ ld_ptr(G2_thread, in_bytes(Thread::pending_exception_offset()), I2_ex_oop);
2411 // Now unlock
2412 // (Roop, Rmark, Rbox, Rscratch)
2413 __ compiler_unlock_object(L4, L1, L3_box, L2);
2414 __ br(Assembler::equal, false, Assembler::pt, done);
2415 __ delayed()-> add(SP, lock_offset+STACK_BIAS, L3_box);
2416
2417 // save and restore any potential method result value around the unlocking
2418 // operation. Will save in I0 (or stack for FP returns).
2419 save_native_result(masm, ret_type, stack_slots);
2420
2421 // Must clear pending-exception before re-entering the VM. Since this is
2422 // a leaf call, pending-exception-oop can be safely kept in a register.
2423 __ st_ptr(G0, G2_thread, in_bytes(Thread::pending_exception_offset()));
2424
2425 // slow case of monitor enter. Inline a special case of call_VM that
2426 // disallows any pending_exception.
2427 __ mov(L3_box, O1);
2428
2429 __ call(CAST_FROM_FN_PTR(address, SharedRuntime::complete_monitor_unlocking_C), relocInfo::runtime_call_type);
2430 __ delayed()->mov(L4, O0); // Need oop in O0
2431
2432 __ restore_thread(L7_thread_cache); // restore G2_thread
2433
2434 #ifdef ASSERT
2435 { Label L;
2436 __ ld_ptr(G2_thread, in_bytes(Thread::pending_exception_offset()), O0);
2437 __ br_null(O0, false, Assembler::pt, L);
2438 __ delayed()->nop();
2439 __ stop("no pending exception allowed on exit from IR::monitorexit");
2440 __ bind(L);
2441 }
2442 #endif
2443 restore_native_result(masm, ret_type, stack_slots);
2444 // check_forward_pending_exception jump to forward_exception if any pending
2445 // exception is set. The forward_exception routine expects to see the
2446 // exception in pending_exception and not in a register. Kind of clumsy,
2447 // since all folks who branch to forward_exception must have tested
2448 // pending_exception first and hence have it in a register already.
2449 __ st_ptr(I2_ex_oop, G2_thread, in_bytes(Thread::pending_exception_offset()));
2450 __ bind(done);
2451 }
2452
2453 // Tell dtrace about this method exit
2454 {
2455 SkipIfEqual skip_if(
2456 masm, G3_scratch, &DTraceMethodProbes, Assembler::zero);
2457 save_native_result(masm, ret_type, stack_slots);
2458 __ set_oop_constant(JNIHandles::make_local(method()), O1);
2459 __ call_VM_leaf(L7_thread_cache,
2460 CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit),
2461 G2_thread, O1);
2462 restore_native_result(masm, ret_type, stack_slots);
2463 }
2464
2465 // Clear "last Java frame" SP and PC.
2466 __ verify_thread(); // G2_thread must be correct
2467 __ reset_last_Java_frame();
2468
2469 // Unpack oop result
2470 if (ret_type == T_OBJECT || ret_type == T_ARRAY) {
2471 Label L;
2472 __ addcc(G0, I0, G0);
2473 __ brx(Assembler::notZero, true, Assembler::pt, L);
2474 __ delayed()->ld_ptr(I0, 0, I0);
2475 __ mov(G0, I0);
2476 __ bind(L);
2477 __ verify_oop(I0);
2478 }
2479
2480 // reset handle block
2481 __ ld_ptr(G2_thread, in_bytes(JavaThread::active_handles_offset()), L5);
2482 __ st_ptr(G0, L5, JNIHandleBlock::top_offset_in_bytes());
2483
2484 __ ld_ptr(G2_thread, in_bytes(Thread::pending_exception_offset()), G3_scratch);
2485 check_forward_pending_exception(masm, G3_scratch);
2486
2487
2488 // Return
2489
2490 #ifndef _LP64
2491 if (ret_type == T_LONG) {
2492
2493 // Must leave proper result in O0,O1 and G1 (c2/tiered only)
2494 __ sllx(I0, 32, G1); // Shift bits into high G1
2495 __ srl (I1, 0, I1); // Zero extend O1 (harmless?)
2496 __ or3 (I1, G1, G1); // OR 64 bits into G1
2497 }
2498 #endif
2499
2500 __ ret();
2501 __ delayed()->restore();
2502
2503 __ flush();
2504
2505 nmethod *nm = nmethod::new_native_nmethod(method,
2506 masm->code(),
2507 vep_offset,
2508 frame_complete,
2509 stack_slots / VMRegImpl::slots_per_word,
2510 (is_static ? in_ByteSize(klass_offset) : in_ByteSize(receiver_offset)),
2511 in_ByteSize(lock_offset),
2512 oop_maps);
2513 return nm;
2514
2515 }
2516
2517 #ifdef HAVE_DTRACE_H
2518 // ---------------------------------------------------------------------------
2519 // Generate a dtrace nmethod for a given signature. The method takes arguments
2520 // in the Java compiled code convention, marshals them to the native
2521 // abi and then leaves nops at the position you would expect to call a native
2522 // function. When the probe is enabled the nops are replaced with a trap
2523 // instruction that dtrace inserts and the trace will cause a notification
2524 // to dtrace.
2525 //
2526 // The probes are only able to take primitive types and java/lang/String as
2527 // arguments. No other java types are allowed. Strings are converted to utf8
2528 // strings so that from dtrace point of view java strings are converted to C
2529 // strings. There is an arbitrary fixed limit on the total space that a method
2530 // can use for converting the strings. (256 chars per string in the signature).
2531 // So any java string larger then this is truncated.
2532
2533 static int fp_offset[ConcreteRegisterImpl::number_of_registers] = { 0 };
2534 static bool offsets_initialized = false;
2535
2536 static VMRegPair reg64_to_VMRegPair(Register r) {
2537 VMRegPair ret;
2538 if (wordSize == 8) {
2539 ret.set2(r->as_VMReg());
2540 } else {
2541 ret.set_pair(r->successor()->as_VMReg(), r->as_VMReg());
2542 }
2543 return ret;
2544 }
2545
2546
2547 nmethod *SharedRuntime::generate_dtrace_nmethod(
2548 MacroAssembler *masm, methodHandle method) {
2549
2550
2551 // generate_dtrace_nmethod is guarded by a mutex so we are sure to
2552 // be single threaded in this method.
2553 assert(AdapterHandlerLibrary_lock->owned_by_self(), "must be");
2554
2555 // Fill in the signature array, for the calling-convention call.
2556 int total_args_passed = method->size_of_parameters();
2557
2558 BasicType* in_sig_bt = NEW_RESOURCE_ARRAY(BasicType, total_args_passed);
2559 VMRegPair *in_regs = NEW_RESOURCE_ARRAY(VMRegPair, total_args_passed);
2560
2561 // The signature we are going to use for the trap that dtrace will see
2562 // java/lang/String is converted. We drop "this" and any other object
2563 // is converted to NULL. (A one-slot java/lang/Long object reference
2564 // is converted to a two-slot long, which is why we double the allocation).
2565 BasicType* out_sig_bt = NEW_RESOURCE_ARRAY(BasicType, total_args_passed * 2);
2566 VMRegPair* out_regs = NEW_RESOURCE_ARRAY(VMRegPair, total_args_passed * 2);
2567
2568 int i=0;
2569 int total_strings = 0;
2570 int first_arg_to_pass = 0;
2571 int total_c_args = 0;
2572
2573 // Skip the receiver as dtrace doesn't want to see it
2574 if( !method->is_static() ) {
2575 in_sig_bt[i++] = T_OBJECT;
2576 first_arg_to_pass = 1;
2577 }
2578
2579 SignatureStream ss(method->signature());
2580 for ( ; !ss.at_return_type(); ss.next()) {
2581 BasicType bt = ss.type();
2582 in_sig_bt[i++] = bt; // Collect remaining bits of signature
2583 out_sig_bt[total_c_args++] = bt;
2584 if( bt == T_OBJECT) {
2585 symbolOop s = ss.as_symbol_or_null();
2586 if (s == vmSymbols::java_lang_String()) {
2587 total_strings++;
2588 out_sig_bt[total_c_args-1] = T_ADDRESS;
2589 } else if (s == vmSymbols::java_lang_Boolean() ||
2590 s == vmSymbols::java_lang_Byte()) {
2591 out_sig_bt[total_c_args-1] = T_BYTE;
2592 } else if (s == vmSymbols::java_lang_Character() ||
2593 s == vmSymbols::java_lang_Short()) {
2594 out_sig_bt[total_c_args-1] = T_SHORT;
2595 } else if (s == vmSymbols::java_lang_Integer() ||
2596 s == vmSymbols::java_lang_Float()) {
2597 out_sig_bt[total_c_args-1] = T_INT;
2598 } else if (s == vmSymbols::java_lang_Long() ||
2599 s == vmSymbols::java_lang_Double()) {
2600 out_sig_bt[total_c_args-1] = T_LONG;
2601 out_sig_bt[total_c_args++] = T_VOID;
2602 }
2603 } else if ( bt == T_LONG || bt == T_DOUBLE ) {
2604 in_sig_bt[i++] = T_VOID; // Longs & doubles take 2 Java slots
2605 // We convert double to long
2606 out_sig_bt[total_c_args-1] = T_LONG;
2607 out_sig_bt[total_c_args++] = T_VOID;
2608 } else if ( bt == T_FLOAT) {
2609 // We convert float to int
2610 out_sig_bt[total_c_args-1] = T_INT;
2611 }
2612 }
2613
2614 assert(i==total_args_passed, "validly parsed signature");
2615
2616 // Now get the compiled-Java layout as input arguments
2617 int comp_args_on_stack;
2618 comp_args_on_stack = SharedRuntime::java_calling_convention(
2619 in_sig_bt, in_regs, total_args_passed, false);
2620
2621 // We have received a description of where all the java arg are located
2622 // on entry to the wrapper. We need to convert these args to where
2623 // the a native (non-jni) function would expect them. To figure out
2624 // where they go we convert the java signature to a C signature and remove
2625 // T_VOID for any long/double we might have received.
2626
2627
2628 // Now figure out where the args must be stored and how much stack space
2629 // they require (neglecting out_preserve_stack_slots but space for storing
2630 // the 1st six register arguments). It's weird see int_stk_helper.
2631 //
2632 int out_arg_slots;
2633 out_arg_slots = c_calling_convention(out_sig_bt, out_regs, total_c_args);
2634
2635 // Calculate the total number of stack slots we will need.
2636
2637 // First count the abi requirement plus all of the outgoing args
2638 int stack_slots = SharedRuntime::out_preserve_stack_slots() + out_arg_slots;
2639
2640 // Plus a temp for possible converion of float/double/long register args
2641
2642 int conversion_temp = stack_slots;
2643 stack_slots += 2;
2644
2645
2646 // Now space for the string(s) we must convert
2647
2648 int string_locs = stack_slots;
2649 stack_slots += total_strings *
2650 (max_dtrace_string_size / VMRegImpl::stack_slot_size);
2651
2652 // Ok The space we have allocated will look like:
2653 //
2654 //
2655 // FP-> | |
2656 // |---------------------|
2657 // | string[n] |
2658 // |---------------------| <- string_locs[n]
2659 // | string[n-1] |
2660 // |---------------------| <- string_locs[n-1]
2661 // | ... |
2662 // | ... |
2663 // |---------------------| <- string_locs[1]
2664 // | string[0] |
2665 // |---------------------| <- string_locs[0]
2666 // | temp |
2667 // |---------------------| <- conversion_temp
2668 // | outbound memory |
2669 // | based arguments |
2670 // | |
2671 // |---------------------|
2672 // | |
2673 // SP-> | out_preserved_slots |
2674 //
2675 //
2676
2677 // Now compute actual number of stack words we need rounding to make
2678 // stack properly aligned.
2679 stack_slots = round_to(stack_slots, 4 * VMRegImpl::slots_per_word);
2680
2681 int stack_size = stack_slots * VMRegImpl::stack_slot_size;
2682
2683 intptr_t start = (intptr_t)__ pc();
2684
2685 // First thing make an ic check to see if we should even be here
2686
2687 {
2688 Label L;
2689 const Register temp_reg = G3_scratch;
2690 AddressLiteral ic_miss(SharedRuntime::get_ic_miss_stub());
2691 __ verify_oop(O0);
2692 __ ld_ptr(O0, oopDesc::klass_offset_in_bytes(), temp_reg);
2693 __ cmp(temp_reg, G5_inline_cache_reg);
2694 __ brx(Assembler::equal, true, Assembler::pt, L);
2695 __ delayed()->nop();
2696
2697 __ jump_to(ic_miss, temp_reg);
2698 __ delayed()->nop();
2699 __ align(CodeEntryAlignment);
2700 __ bind(L);
2701 }
2702
2703 int vep_offset = ((intptr_t)__ pc()) - start;
2704
2705
2706 // The instruction at the verified entry point must be 5 bytes or longer
2707 // because it can be patched on the fly by make_non_entrant. The stack bang
2708 // instruction fits that requirement.
2709
2710 // Generate stack overflow check before creating frame
2711 __ generate_stack_overflow_check(stack_size);
2712
2713 assert(((intptr_t)__ pc() - start - vep_offset) >= 5,
2714 "valid size for make_non_entrant");
2715
2716 // Generate a new frame for the wrapper.
2717 __ save(SP, -stack_size, SP);
2718
2719 // Frame is now completed as far a size and linkage.
2720
2721 int frame_complete = ((intptr_t)__ pc()) - start;
2722
2723 #ifdef ASSERT
2724 bool reg_destroyed[RegisterImpl::number_of_registers];
2725 bool freg_destroyed[FloatRegisterImpl::number_of_registers];
2726 for ( int r = 0 ; r < RegisterImpl::number_of_registers ; r++ ) {
2727 reg_destroyed[r] = false;
2728 }
2729 for ( int f = 0 ; f < FloatRegisterImpl::number_of_registers ; f++ ) {
2730 freg_destroyed[f] = false;
2731 }
2732
2733 #endif /* ASSERT */
2734
2735 VMRegPair zero;
2736 const Register g0 = G0; // without this we get a compiler warning (why??)
2737 zero.set2(g0->as_VMReg());
2738
2739 int c_arg, j_arg;
2740
2741 Register conversion_off = noreg;
2742
2743 for (j_arg = first_arg_to_pass, c_arg = 0 ;
2744 j_arg < total_args_passed ; j_arg++, c_arg++ ) {
2745
2746 VMRegPair src = in_regs[j_arg];
2747 VMRegPair dst = out_regs[c_arg];
2748
2749 #ifdef ASSERT
2750 if (src.first()->is_Register()) {
2751 assert(!reg_destroyed[src.first()->as_Register()->encoding()], "ack!");
2752 } else if (src.first()->is_FloatRegister()) {
2753 assert(!freg_destroyed[src.first()->as_FloatRegister()->encoding(
2754 FloatRegisterImpl::S)], "ack!");
2755 }
2756 if (dst.first()->is_Register()) {
2757 reg_destroyed[dst.first()->as_Register()->encoding()] = true;
2758 } else if (dst.first()->is_FloatRegister()) {
2759 freg_destroyed[dst.first()->as_FloatRegister()->encoding(
2760 FloatRegisterImpl::S)] = true;
2761 }
2762 #endif /* ASSERT */
2763
2764 switch (in_sig_bt[j_arg]) {
2765 case T_ARRAY:
2766 case T_OBJECT:
2767 {
2768 if (out_sig_bt[c_arg] == T_BYTE || out_sig_bt[c_arg] == T_SHORT ||
2769 out_sig_bt[c_arg] == T_INT || out_sig_bt[c_arg] == T_LONG) {
2770 // need to unbox a one-slot value
2771 Register in_reg = L0;
2772 Register tmp = L2;
2773 if ( src.first()->is_reg() ) {
2774 in_reg = src.first()->as_Register();
2775 } else {
2776 assert(Assembler::is_simm13(reg2offset(src.first()) + STACK_BIAS),
2777 "must be");
2778 __ ld_ptr(FP, reg2offset(src.first()) + STACK_BIAS, in_reg);
2779 }
2780 // If the final destination is an acceptable register
2781 if ( dst.first()->is_reg() ) {
2782 if ( dst.is_single_phys_reg() || out_sig_bt[c_arg] != T_LONG ) {
2783 tmp = dst.first()->as_Register();
2784 }
2785 }
2786
2787 Label skipUnbox;
2788 if ( wordSize == 4 && out_sig_bt[c_arg] == T_LONG ) {
2789 __ mov(G0, tmp->successor());
2790 }
2791 __ br_null(in_reg, true, Assembler::pn, skipUnbox);
2792 __ delayed()->mov(G0, tmp);
2793
2794 BasicType bt = out_sig_bt[c_arg];
2795 int box_offset = java_lang_boxing_object::value_offset_in_bytes(bt);
2796 switch (bt) {
2797 case T_BYTE:
2798 __ ldub(in_reg, box_offset, tmp); break;
2799 case T_SHORT:
2800 __ lduh(in_reg, box_offset, tmp); break;
2801 case T_INT:
2802 __ ld(in_reg, box_offset, tmp); break;
2803 case T_LONG:
2804 __ ld_long(in_reg, box_offset, tmp); break;
2805 default: ShouldNotReachHere();
2806 }
2807
2808 __ bind(skipUnbox);
2809 // If tmp wasn't final destination copy to final destination
2810 if (tmp == L2) {
2811 VMRegPair tmp_as_VM = reg64_to_VMRegPair(L2);
2812 if (out_sig_bt[c_arg] == T_LONG) {
2813 long_move(masm, tmp_as_VM, dst);
2814 } else {
2815 move32_64(masm, tmp_as_VM, out_regs[c_arg]);
2816 }
2817 }
2818 if (out_sig_bt[c_arg] == T_LONG) {
2819 assert(out_sig_bt[c_arg+1] == T_VOID, "must be");
2820 ++c_arg; // move over the T_VOID to keep the loop indices in sync
2821 }
2822 } else if (out_sig_bt[c_arg] == T_ADDRESS) {
2823 Register s =
2824 src.first()->is_reg() ? src.first()->as_Register() : L2;
2825 Register d =
2826 dst.first()->is_reg() ? dst.first()->as_Register() : L2;
2827
2828 // We store the oop now so that the conversion pass can reach
2829 // while in the inner frame. This will be the only store if
2830 // the oop is NULL.
2831 if (s != L2) {
2832 // src is register
2833 if (d != L2) {
2834 // dst is register
2835 __ mov(s, d);
2836 } else {
2837 assert(Assembler::is_simm13(reg2offset(dst.first()) +
2838 STACK_BIAS), "must be");
2839 __ st_ptr(s, SP, reg2offset(dst.first()) + STACK_BIAS);
2840 }
2841 } else {
2842 // src not a register
2843 assert(Assembler::is_simm13(reg2offset(src.first()) +
2844 STACK_BIAS), "must be");
2845 __ ld_ptr(FP, reg2offset(src.first()) + STACK_BIAS, d);
2846 if (d == L2) {
2847 assert(Assembler::is_simm13(reg2offset(dst.first()) +
2848 STACK_BIAS), "must be");
2849 __ st_ptr(d, SP, reg2offset(dst.first()) + STACK_BIAS);
2850 }
2851 }
2852 } else if (out_sig_bt[c_arg] != T_VOID) {
2853 // Convert the arg to NULL
2854 if (dst.first()->is_reg()) {
2855 __ mov(G0, dst.first()->as_Register());
2856 } else {
2857 assert(Assembler::is_simm13(reg2offset(dst.first()) +
2858 STACK_BIAS), "must be");
2859 __ st_ptr(G0, SP, reg2offset(dst.first()) + STACK_BIAS);
2860 }
2861 }
2862 }
2863 break;
2864 case T_VOID:
2865 break;
2866
2867 case T_FLOAT:
2868 if (src.first()->is_stack()) {
2869 // Stack to stack/reg is simple
2870 move32_64(masm, src, dst);
2871 } else {
2872 if (dst.first()->is_reg()) {
2873 // freg -> reg
2874 int off =
2875 STACK_BIAS + conversion_temp * VMRegImpl::stack_slot_size;
2876 Register d = dst.first()->as_Register();
2877 if (Assembler::is_simm13(off)) {
2878 __ stf(FloatRegisterImpl::S, src.first()->as_FloatRegister(),
2879 SP, off);
2880 __ ld(SP, off, d);
2881 } else {
2882 if (conversion_off == noreg) {
2883 __ set(off, L6);
2884 conversion_off = L6;
2885 }
2886 __ stf(FloatRegisterImpl::S, src.first()->as_FloatRegister(),
2887 SP, conversion_off);
2888 __ ld(SP, conversion_off , d);
2889 }
2890 } else {
2891 // freg -> mem
2892 int off = STACK_BIAS + reg2offset(dst.first());
2893 if (Assembler::is_simm13(off)) {
2894 __ stf(FloatRegisterImpl::S, src.first()->as_FloatRegister(),
2895 SP, off);
2896 } else {
2897 if (conversion_off == noreg) {
2898 __ set(off, L6);
2899 conversion_off = L6;
2900 }
2901 __ stf(FloatRegisterImpl::S, src.first()->as_FloatRegister(),
2902 SP, conversion_off);
2903 }
2904 }
2905 }
2906 break;
2907
2908 case T_DOUBLE:
2909 assert( j_arg + 1 < total_args_passed &&
2910 in_sig_bt[j_arg + 1] == T_VOID &&
2911 out_sig_bt[c_arg+1] == T_VOID, "bad arg list");
2912 if (src.first()->is_stack()) {
2913 // Stack to stack/reg is simple
2914 long_move(masm, src, dst);
2915 } else {
2916 Register d = dst.first()->is_reg() ? dst.first()->as_Register() : L2;
2917
2918 // Destination could be an odd reg on 32bit in which case
2919 // we can't load direct to the destination.
2920
2921 if (!d->is_even() && wordSize == 4) {
2922 d = L2;
2923 }
2924 int off = STACK_BIAS + conversion_temp * VMRegImpl::stack_slot_size;
2925 if (Assembler::is_simm13(off)) {
2926 __ stf(FloatRegisterImpl::D, src.first()->as_FloatRegister(),
2927 SP, off);
2928 __ ld_long(SP, off, d);
2929 } else {
2930 if (conversion_off == noreg) {
2931 __ set(off, L6);
2932 conversion_off = L6;
2933 }
2934 __ stf(FloatRegisterImpl::D, src.first()->as_FloatRegister(),
2935 SP, conversion_off);
2936 __ ld_long(SP, conversion_off, d);
2937 }
2938 if (d == L2) {
2939 long_move(masm, reg64_to_VMRegPair(L2), dst);
2940 }
2941 }
2942 break;
2943
2944 case T_LONG :
2945 // 32bit can't do a split move of something like g1 -> O0, O1
2946 // so use a memory temp
2947 if (src.is_single_phys_reg() && wordSize == 4) {
2948 Register tmp = L2;
2949 if (dst.first()->is_reg() &&
2950 (wordSize == 8 || dst.first()->as_Register()->is_even())) {
2951 tmp = dst.first()->as_Register();
2952 }
2953
2954 int off = STACK_BIAS + conversion_temp * VMRegImpl::stack_slot_size;
2955 if (Assembler::is_simm13(off)) {
2956 __ stx(src.first()->as_Register(), SP, off);
2957 __ ld_long(SP, off, tmp);
2958 } else {
2959 if (conversion_off == noreg) {
2960 __ set(off, L6);
2961 conversion_off = L6;
2962 }
2963 __ stx(src.first()->as_Register(), SP, conversion_off);
2964 __ ld_long(SP, conversion_off, tmp);
2965 }
2966
2967 if (tmp == L2) {
2968 long_move(masm, reg64_to_VMRegPair(L2), dst);
2969 }
2970 } else {
2971 long_move(masm, src, dst);
2972 }
2973 break;
2974
2975 case T_ADDRESS: assert(false, "found T_ADDRESS in java args");
2976
2977 default:
2978 move32_64(masm, src, dst);
2979 }
2980 }
2981
2982
2983 // If we have any strings we must store any register based arg to the stack
2984 // This includes any still live xmm registers too.
2985
2986 if (total_strings > 0 ) {
2987
2988 // protect all the arg registers
2989 __ save_frame(0);
2990 __ mov(G2_thread, L7_thread_cache);
2991 const Register L2_string_off = L2;
2992
2993 // Get first string offset
2994 __ set(string_locs * VMRegImpl::stack_slot_size, L2_string_off);
2995
2996 for (c_arg = 0 ; c_arg < total_c_args ; c_arg++ ) {
2997 if (out_sig_bt[c_arg] == T_ADDRESS) {
2998
2999 VMRegPair dst = out_regs[c_arg];
3000 const Register d = dst.first()->is_reg() ?
3001 dst.first()->as_Register()->after_save() : noreg;
3002
3003 // It's a string the oop and it was already copied to the out arg
3004 // position
3005 if (d != noreg) {
3006 __ mov(d, O0);
3007 } else {
3008 assert(Assembler::is_simm13(reg2offset(dst.first()) + STACK_BIAS),
3009 "must be");
3010 __ ld_ptr(FP, reg2offset(dst.first()) + STACK_BIAS, O0);
3011 }
3012 Label skip;
3013
3014 __ br_null(O0, false, Assembler::pn, skip);
3015 __ delayed()->add(FP, L2_string_off, O1);
3016
3017 if (d != noreg) {
3018 __ mov(O1, d);
3019 } else {
3020 assert(Assembler::is_simm13(reg2offset(dst.first()) + STACK_BIAS),
3021 "must be");
3022 __ st_ptr(O1, FP, reg2offset(dst.first()) + STACK_BIAS);
3023 }
3024
3025 __ call(CAST_FROM_FN_PTR(address, SharedRuntime::get_utf),
3026 relocInfo::runtime_call_type);
3027 __ delayed()->add(L2_string_off, max_dtrace_string_size, L2_string_off);
3028
3029 __ bind(skip);
3030
3031 }
3032
3033 }
3034 __ mov(L7_thread_cache, G2_thread);
3035 __ restore();
3036
3037 }
3038
3039
3040 // Ok now we are done. Need to place the nop that dtrace wants in order to
3041 // patch in the trap
3042
3043 int patch_offset = ((intptr_t)__ pc()) - start;
3044
3045 __ nop();
3046
3047
3048 // Return
3049
3050 __ ret();
3051 __ delayed()->restore();
3052
3053 __ flush();
3054
3055 nmethod *nm = nmethod::new_dtrace_nmethod(
3056 method, masm->code(), vep_offset, patch_offset, frame_complete,
3057 stack_slots / VMRegImpl::slots_per_word);
3058 return nm;
3059
3060 }
3061
3062 #endif // HAVE_DTRACE_H
3063
3064 // this function returns the adjust size (in number of words) to a c2i adapter
3065 // activation for use during deoptimization
3066 int Deoptimization::last_frame_adjust(int callee_parameters, int callee_locals) {
3067 assert(callee_locals >= callee_parameters,
3068 "test and remove; got more parms than locals");
3069 if (callee_locals < callee_parameters)
3070 return 0; // No adjustment for negative locals
3071 int diff = (callee_locals - callee_parameters) * Interpreter::stackElementWords();
3072 return round_to(diff, WordsPerLong);
3073 }
3074
3075 // "Top of Stack" slots that may be unused by the calling convention but must
3076 // otherwise be preserved.
3077 // On Intel these are not necessary and the value can be zero.
3078 // On Sparc this describes the words reserved for storing a register window
3079 // when an interrupt occurs.
3080 uint SharedRuntime::out_preserve_stack_slots() {
3081 return frame::register_save_words * VMRegImpl::slots_per_word;
3082 }
3083
3084 static void gen_new_frame(MacroAssembler* masm, bool deopt) {
3085 //
3086 // Common out the new frame generation for deopt and uncommon trap
3087 //
3088 Register G3pcs = G3_scratch; // Array of new pcs (input)
3089 Register Oreturn0 = O0;
3090 Register Oreturn1 = O1;
3091 Register O2UnrollBlock = O2;
3092 Register O3array = O3; // Array of frame sizes (input)
3093 Register O4array_size = O4; // number of frames (input)
3094 Register O7frame_size = O7; // number of frames (input)
3095
3096 __ ld_ptr(O3array, 0, O7frame_size);
3097 __ sub(G0, O7frame_size, O7frame_size);
3098 __ save(SP, O7frame_size, SP);
3099 __ ld_ptr(G3pcs, 0, I7); // load frame's new pc
3100
3101 #ifdef ASSERT
3102 // make sure that the frames are aligned properly
3103 #ifndef _LP64
3104 __ btst(wordSize*2-1, SP);
3105 __ breakpoint_trap(Assembler::notZero);
3106 #endif
3107 #endif
3108
3109 // Deopt needs to pass some extra live values from frame to frame
3110
3111 if (deopt) {
3112 __ mov(Oreturn0->after_save(), Oreturn0);
3113 __ mov(Oreturn1->after_save(), Oreturn1);
3114 }
3115
3116 __ mov(O4array_size->after_save(), O4array_size);
3117 __ sub(O4array_size, 1, O4array_size);
3118 __ mov(O3array->after_save(), O3array);
3119 __ mov(O2UnrollBlock->after_save(), O2UnrollBlock);
3120 __ add(G3pcs, wordSize, G3pcs); // point to next pc value
3121
3122 #ifdef ASSERT
3123 // trash registers to show a clear pattern in backtraces
3124 __ set(0xDEAD0000, I0);
3125 __ add(I0, 2, I1);
3126 __ add(I0, 4, I2);
3127 __ add(I0, 6, I3);
3128 __ add(I0, 8, I4);
3129 // Don't touch I5 could have valuable savedSP
3130 __ set(0xDEADBEEF, L0);
3131 __ mov(L0, L1);
3132 __ mov(L0, L2);
3133 __ mov(L0, L3);
3134 __ mov(L0, L4);
3135 __ mov(L0, L5);
3136
3137 // trash the return value as there is nothing to return yet
3138 __ set(0xDEAD0001, O7);
3139 #endif
3140
3141 __ mov(SP, O5_savedSP);
3142 }
3143
3144
3145 static void make_new_frames(MacroAssembler* masm, bool deopt) {
3146 //
3147 // loop through the UnrollBlock info and create new frames
3148 //
3149 Register G3pcs = G3_scratch;
3150 Register Oreturn0 = O0;
3151 Register Oreturn1 = O1;
3152 Register O2UnrollBlock = O2;
3153 Register O3array = O3;
3154 Register O4array_size = O4;
3155 Label loop;
3156
3157 // Before we make new frames, check to see if stack is available.
3158 // Do this after the caller's return address is on top of stack
3159 if (UseStackBanging) {
3160 // Get total frame size for interpreted frames
3161 __ ld(O2UnrollBlock, Deoptimization::UnrollBlock::total_frame_sizes_offset_in_bytes(), O4);
3162 __ bang_stack_size(O4, O3, G3_scratch);
3163 }
3164
3165 __ ld(O2UnrollBlock, Deoptimization::UnrollBlock::number_of_frames_offset_in_bytes(), O4array_size);
3166 __ ld_ptr(O2UnrollBlock, Deoptimization::UnrollBlock::frame_pcs_offset_in_bytes(), G3pcs);
3167 __ ld_ptr(O2UnrollBlock, Deoptimization::UnrollBlock::frame_sizes_offset_in_bytes(), O3array);
3168
3169 // Adjust old interpreter frame to make space for new frame's extra java locals
3170 //
3171 // We capture the original sp for the transition frame only because it is needed in
3172 // order to properly calculate interpreter_sp_adjustment. Even though in real life
3173 // every interpreter frame captures a savedSP it is only needed at the transition
3174 // (fortunately). If we had to have it correct everywhere then we would need to
3175 // be told the sp_adjustment for each frame we create. If the frame size array
3176 // were to have twice the frame count entries then we could have pairs [sp_adjustment, frame_size]
3177 // for each frame we create and keep up the illusion every where.
3178 //
3179
3180 __ ld(O2UnrollBlock, Deoptimization::UnrollBlock::caller_adjustment_offset_in_bytes(), O7);
3181 __ mov(SP, O5_savedSP); // remember initial sender's original sp before adjustment
3182 __ sub(SP, O7, SP);
3183
3184 #ifdef ASSERT
3185 // make sure that there is at least one entry in the array
3186 __ tst(O4array_size);
3187 __ breakpoint_trap(Assembler::zero);
3188 #endif
3189
3190 // Now push the new interpreter frames
3191 __ bind(loop);
3192
3193 // allocate a new frame, filling the registers
3194
3195 gen_new_frame(masm, deopt); // allocate an interpreter frame
3196
3197 __ tst(O4array_size);
3198 __ br(Assembler::notZero, false, Assembler::pn, loop);
3199 __ delayed()->add(O3array, wordSize, O3array);
3200 __ ld_ptr(G3pcs, 0, O7); // load final frame new pc
3201
3202 }
3203
3204 //------------------------------generate_deopt_blob----------------------------
3205 // Ought to generate an ideal graph & compile, but here's some SPARC ASM
3206 // instead.
3207 void SharedRuntime::generate_deopt_blob() {
3208 // allocate space for the code
3209 ResourceMark rm;
3210 // setup code generation tools
3211 int pad = VerifyThread ? 512 : 0;// Extra slop space for more verify code
3212 #ifdef _LP64
3213 CodeBuffer buffer("deopt_blob", 2100+pad, 512);
3214 #else
3215 // Measured 8/7/03 at 1212 in 32bit debug build (no VerifyThread)
3216 // Measured 8/7/03 at 1396 in 32bit debug build (VerifyThread)
3217 CodeBuffer buffer("deopt_blob", 1600+pad, 512);
3218 #endif /* _LP64 */
3219 MacroAssembler* masm = new MacroAssembler(&buffer);
3220 FloatRegister Freturn0 = F0;
3221 Register Greturn1 = G1;
3222 Register Oreturn0 = O0;
3223 Register Oreturn1 = O1;
3224 Register O2UnrollBlock = O2;
3225 Register O3tmp = O3;
3226 Register I5exception_tmp = I5;
3227 Register G4exception_tmp = G4_scratch;
3228 int frame_size_words;
3229 Address saved_Freturn0_addr(FP, -sizeof(double) + STACK_BIAS);
3230 #if !defined(_LP64) && defined(COMPILER2)
3231 Address saved_Greturn1_addr(FP, -sizeof(double) -sizeof(jlong) + STACK_BIAS);
3232 #endif
3233 Label cont;
3234
3235 OopMapSet *oop_maps = new OopMapSet();
3236
3237 //
3238 // This is the entry point for code which is returning to a de-optimized
3239 // frame.
3240 // The steps taken by this frame are as follows:
3241 // - push a dummy "register_save" and save the return values (O0, O1, F0/F1, G1)
3242 // and all potentially live registers (at a pollpoint many registers can be live).
3243 //
3244 // - call the C routine: Deoptimization::fetch_unroll_info (this function
3245 // returns information about the number and size of interpreter frames
3246 // which are equivalent to the frame which is being deoptimized)
3247 // - deallocate the unpack frame, restoring only results values. Other
3248 // volatile registers will now be captured in the vframeArray as needed.
3249 // - deallocate the deoptimization frame
3250 // - in a loop using the information returned in the previous step
3251 // push new interpreter frames (take care to propagate the return
3252 // values through each new frame pushed)
3253 // - create a dummy "unpack_frame" and save the return values (O0, O1, F0)
3254 // - call the C routine: Deoptimization::unpack_frames (this function
3255 // lays out values on the interpreter frame which was just created)
3256 // - deallocate the dummy unpack_frame
3257 // - ensure that all the return values are correctly set and then do
3258 // a return to the interpreter entry point
3259 //
3260 // Refer to the following methods for more information:
3261 // - Deoptimization::fetch_unroll_info
3262 // - Deoptimization::unpack_frames
3263
3264 OopMap* map = NULL;
3265
3266 int start = __ offset();
3267
3268 // restore G2, the trampoline destroyed it
3269 __ get_thread();
3270
3271 // On entry we have been called by the deoptimized nmethod with a call that
3272 // replaced the original call (or safepoint polling location) so the deoptimizing
3273 // pc is now in O7. Return values are still in the expected places
3274
3275 map = RegisterSaver::save_live_registers(masm, 0, &frame_size_words);
3276 __ ba(false, cont);
3277 __ delayed()->mov(Deoptimization::Unpack_deopt, I5exception_tmp);
3278
3279 int exception_offset = __ offset() - start;
3280
3281 // restore G2, the trampoline destroyed it
3282 __ get_thread();
3283
3284 // On entry we have been jumped to by the exception handler (or exception_blob
3285 // for server). O0 contains the exception oop and O7 contains the original
3286 // exception pc. So if we push a frame here it will look to the
3287 // stack walking code (fetch_unroll_info) just like a normal call so
3288 // state will be extracted normally.
3289
3290 // save exception oop in JavaThread and fall through into the
3291 // exception_in_tls case since they are handled in same way except
3292 // for where the pending exception is kept.
3293 __ st_ptr(Oexception, G2_thread, JavaThread::exception_oop_offset());
3294
3295 //
3296 // Vanilla deoptimization with an exception pending in exception_oop
3297 //
3298 int exception_in_tls_offset = __ offset() - start;
3299
3300 // No need to update oop_map as each call to save_live_registers will produce identical oopmap
3301 (void) RegisterSaver::save_live_registers(masm, 0, &frame_size_words);
3302
3303 // Restore G2_thread
3304 __ get_thread();
3305
3306 #ifdef ASSERT
3307 {
3308 // verify that there is really an exception oop in exception_oop
3309 Label has_exception;
3310 __ ld_ptr(G2_thread, JavaThread::exception_oop_offset(), Oexception);
3311 __ br_notnull(Oexception, false, Assembler::pt, has_exception);
3312 __ delayed()-> nop();
3313 __ stop("no exception in thread");
3314 __ bind(has_exception);
3315
3316 // verify that there is no pending exception
3317 Label no_pending_exception;
3318 Address exception_addr(G2_thread, Thread::pending_exception_offset());
3319 __ ld_ptr(exception_addr, Oexception);
3320 __ br_null(Oexception, false, Assembler::pt, no_pending_exception);
3321 __ delayed()->nop();
3322 __ stop("must not have pending exception here");
3323 __ bind(no_pending_exception);
3324 }
3325 #endif
3326
3327 __ ba(false, cont);
3328 __ delayed()->mov(Deoptimization::Unpack_exception, I5exception_tmp);;
3329
3330 //
3331 // Reexecute entry, similar to c2 uncommon trap
3332 //
3333 int reexecute_offset = __ offset() - start;
3334
3335 // No need to update oop_map as each call to save_live_registers will produce identical oopmap
3336 (void) RegisterSaver::save_live_registers(masm, 0, &frame_size_words);
3337
3338 __ mov(Deoptimization::Unpack_reexecute, I5exception_tmp);
3339
3340 __ bind(cont);
3341
3342 __ set_last_Java_frame(SP, noreg);
3343
3344 // do the call by hand so we can get the oopmap
3345
3346 __ mov(G2_thread, L7_thread_cache);
3347 __ call(CAST_FROM_FN_PTR(address, Deoptimization::fetch_unroll_info), relocInfo::runtime_call_type);
3348 __ delayed()->mov(G2_thread, O0);
3349
3350 // Set an oopmap for the call site this describes all our saved volatile registers
3351
3352 oop_maps->add_gc_map( __ offset()-start, map);
3353
3354 __ mov(L7_thread_cache, G2_thread);
3355
3356 __ reset_last_Java_frame();
3357
3358 // NOTE: we know that only O0/O1 will be reloaded by restore_result_registers
3359 // so this move will survive
3360
3361 __ mov(I5exception_tmp, G4exception_tmp);
3362
3363 __ mov(O0, O2UnrollBlock->after_save());
3364
3365 RegisterSaver::restore_result_registers(masm);
3366
3367 Label noException;
3368 __ cmp(G4exception_tmp, Deoptimization::Unpack_exception); // Was exception pending?
3369 __ br(Assembler::notEqual, false, Assembler::pt, noException);
3370 __ delayed()->nop();
3371
3372 // Move the pending exception from exception_oop to Oexception so
3373 // the pending exception will be picked up the interpreter.
3374 __ ld_ptr(G2_thread, in_bytes(JavaThread::exception_oop_offset()), Oexception);
3375 __ st_ptr(G0, G2_thread, in_bytes(JavaThread::exception_oop_offset()));
3376 __ bind(noException);
3377
3378 // deallocate the deoptimization frame taking care to preserve the return values
3379 __ mov(Oreturn0, Oreturn0->after_save());
3380 __ mov(Oreturn1, Oreturn1->after_save());
3381 __ mov(O2UnrollBlock, O2UnrollBlock->after_save());
3382 __ restore();
3383
3384 // Allocate new interpreter frame(s) and possible c2i adapter frame
3385
3386 make_new_frames(masm, true);
3387
3388 // push a dummy "unpack_frame" taking care of float return values and
3389 // call Deoptimization::unpack_frames to have the unpacker layout
3390 // information in the interpreter frames just created and then return
3391 // to the interpreter entry point
3392 __ save(SP, -frame_size_words*wordSize, SP);
3393 __ stf(FloatRegisterImpl::D, Freturn0, saved_Freturn0_addr);
3394 #if !defined(_LP64)
3395 #if defined(COMPILER2)
3396 if (!TieredCompilation) {
3397 // 32-bit 1-register longs return longs in G1
3398 __ stx(Greturn1, saved_Greturn1_addr);
3399 }
3400 #endif
3401 __ set_last_Java_frame(SP, noreg);
3402 __ call_VM_leaf(L7_thread_cache, CAST_FROM_FN_PTR(address, Deoptimization::unpack_frames), G2_thread, G4exception_tmp);
3403 #else
3404 // LP64 uses g4 in set_last_Java_frame
3405 __ mov(G4exception_tmp, O1);
3406 __ set_last_Java_frame(SP, G0);
3407 __ call_VM_leaf(L7_thread_cache, CAST_FROM_FN_PTR(address, Deoptimization::unpack_frames), G2_thread, O1);
3408 #endif
3409 __ reset_last_Java_frame();
3410 __ ldf(FloatRegisterImpl::D, saved_Freturn0_addr, Freturn0);
3411
3412 // In tiered we never use C2 to compile methods returning longs so
3413 // the result is where we expect it already.
3414
3415 #if !defined(_LP64) && defined(COMPILER2)
3416 // In 32 bit, C2 returns longs in G1 so restore the saved G1 into
3417 // I0/I1 if the return value is long. In the tiered world there is
3418 // a mismatch between how C1 and C2 return longs compiles and so
3419 // currently compilation of methods which return longs is disabled
3420 // for C2 and so is this code. Eventually C1 and C2 will do the
3421 // same thing for longs in the tiered world.
3422 if (!TieredCompilation) {
3423 Label not_long;
3424 __ cmp(O0,T_LONG);
3425 __ br(Assembler::notEqual, false, Assembler::pt, not_long);
3426 __ delayed()->nop();
3427 __ ldd(saved_Greturn1_addr,I0);
3428 __ bind(not_long);
3429 }
3430 #endif
3431 __ ret();
3432 __ delayed()->restore();
3433
3434 masm->flush();
3435 _deopt_blob = DeoptimizationBlob::create(&buffer, oop_maps, 0, exception_offset, reexecute_offset, frame_size_words);
3436 _deopt_blob->set_unpack_with_exception_in_tls_offset(exception_in_tls_offset);
3437 }
3438
3439 #ifdef COMPILER2
3440
3441 //------------------------------generate_uncommon_trap_blob--------------------
3442 // Ought to generate an ideal graph & compile, but here's some SPARC ASM
3443 // instead.
3444 void SharedRuntime::generate_uncommon_trap_blob() {
3445 // allocate space for the code
3446 ResourceMark rm;
3447 // setup code generation tools
3448 int pad = VerifyThread ? 512 : 0;
3449 #ifdef _LP64
3450 CodeBuffer buffer("uncommon_trap_blob", 2700+pad, 512);
3451 #else
3452 // Measured 8/7/03 at 660 in 32bit debug build (no VerifyThread)
3453 // Measured 8/7/03 at 1028 in 32bit debug build (VerifyThread)
3454 CodeBuffer buffer("uncommon_trap_blob", 2000+pad, 512);
3455 #endif
3456 MacroAssembler* masm = new MacroAssembler(&buffer);
3457 Register O2UnrollBlock = O2;
3458 Register O3tmp = O3;
3459 Register O2klass_index = O2;
3460
3461 //
3462 // This is the entry point for all traps the compiler takes when it thinks
3463 // it cannot handle further execution of compilation code. The frame is
3464 // deoptimized in these cases and converted into interpreter frames for
3465 // execution
3466 // The steps taken by this frame are as follows:
3467 // - push a fake "unpack_frame"
3468 // - call the C routine Deoptimization::uncommon_trap (this function
3469 // packs the current compiled frame into vframe arrays and returns
3470 // information about the number and size of interpreter frames which
3471 // are equivalent to the frame which is being deoptimized)
3472 // - deallocate the "unpack_frame"
3473 // - deallocate the deoptimization frame
3474 // - in a loop using the information returned in the previous step
3475 // push interpreter frames;
3476 // - create a dummy "unpack_frame"
3477 // - call the C routine: Deoptimization::unpack_frames (this function
3478 // lays out values on the interpreter frame which was just created)
3479 // - deallocate the dummy unpack_frame
3480 // - return to the interpreter entry point
3481 //
3482 // Refer to the following methods for more information:
3483 // - Deoptimization::uncommon_trap
3484 // - Deoptimization::unpack_frame
3485
3486 // the unloaded class index is in O0 (first parameter to this blob)
3487
3488 // push a dummy "unpack_frame"
3489 // and call Deoptimization::uncommon_trap to pack the compiled frame into
3490 // vframe array and return the UnrollBlock information
3491 __ save_frame(0);
3492 __ set_last_Java_frame(SP, noreg);
3493 __ mov(I0, O2klass_index);
3494 __ call_VM_leaf(L7_thread_cache, CAST_FROM_FN_PTR(address, Deoptimization::uncommon_trap), G2_thread, O2klass_index);
3495 __ reset_last_Java_frame();
3496 __ mov(O0, O2UnrollBlock->after_save());
3497 __ restore();
3498
3499 // deallocate the deoptimized frame taking care to preserve the return values
3500 __ mov(O2UnrollBlock, O2UnrollBlock->after_save());
3501 __ restore();
3502
3503 // Allocate new interpreter frame(s) and possible c2i adapter frame
3504
3505 make_new_frames(masm, false);
3506
3507 // push a dummy "unpack_frame" taking care of float return values and
3508 // call Deoptimization::unpack_frames to have the unpacker layout
3509 // information in the interpreter frames just created and then return
3510 // to the interpreter entry point
3511 __ save_frame(0);
3512 __ set_last_Java_frame(SP, noreg);
3513 __ mov(Deoptimization::Unpack_uncommon_trap, O3); // indicate it is the uncommon trap case
3514 __ call_VM_leaf(L7_thread_cache, CAST_FROM_FN_PTR(address, Deoptimization::unpack_frames), G2_thread, O3);
3515 __ reset_last_Java_frame();
3516 __ ret();
3517 __ delayed()->restore();
3518
3519 masm->flush();
3520 _uncommon_trap_blob = UncommonTrapBlob::create(&buffer, NULL, __ total_frame_size_in_bytes(0)/wordSize);
3521 }
3522
3523 #endif // COMPILER2
3524
3525 //------------------------------generate_handler_blob-------------------
3526 //
3527 // Generate a special Compile2Runtime blob that saves all registers, and sets
3528 // up an OopMap.
3529 //
3530 // This blob is jumped to (via a breakpoint and the signal handler) from a
3531 // safepoint in compiled code. On entry to this blob, O7 contains the
3532 // address in the original nmethod at which we should resume normal execution.
3533 // Thus, this blob looks like a subroutine which must preserve lots of
3534 // registers and return normally. Note that O7 is never register-allocated,
3535 // so it is guaranteed to be free here.
3536 //
3537
3538 // The hardest part of what this blob must do is to save the 64-bit %o
3539 // registers in the 32-bit build. A simple 'save' turn the %o's to %i's and
3540 // an interrupt will chop off their heads. Making space in the caller's frame
3541 // first will let us save the 64-bit %o's before save'ing, but we cannot hand
3542 // the adjusted FP off to the GC stack-crawler: this will modify the caller's
3543 // SP and mess up HIS OopMaps. So we first adjust the caller's SP, then save
3544 // the 64-bit %o's, then do a save, then fixup the caller's SP (our FP).
3545 // Tricky, tricky, tricky...
3546
3547 static SafepointBlob* generate_handler_blob(address call_ptr, bool cause_return) {
3548 assert (StubRoutines::forward_exception_entry() != NULL, "must be generated before");
3549
3550 // allocate space for the code
3551 ResourceMark rm;
3552 // setup code generation tools
3553 // Measured 8/7/03 at 896 in 32bit debug build (no VerifyThread)
3554 // Measured 8/7/03 at 1080 in 32bit debug build (VerifyThread)
3555 // even larger with TraceJumps
3556 int pad = TraceJumps ? 512 : 0;
3557 CodeBuffer buffer("handler_blob", 1600 + pad, 512);
3558 MacroAssembler* masm = new MacroAssembler(&buffer);
3559 int frame_size_words;
3560 OopMapSet *oop_maps = new OopMapSet();
3561 OopMap* map = NULL;
3562
3563 int start = __ offset();
3564
3565 // If this causes a return before the processing, then do a "restore"
3566 if (cause_return) {
3567 __ restore();
3568 } else {
3569 // Make it look like we were called via the poll
3570 // so that frame constructor always sees a valid return address
3571 __ ld_ptr(G2_thread, in_bytes(JavaThread::saved_exception_pc_offset()), O7);
3572 __ sub(O7, frame::pc_return_offset, O7);
3573 }
3574
3575 map = RegisterSaver::save_live_registers(masm, 0, &frame_size_words);
3576
3577 // setup last_Java_sp (blows G4)
3578 __ set_last_Java_frame(SP, noreg);
3579
3580 // call into the runtime to handle illegal instructions exception
3581 // Do not use call_VM_leaf, because we need to make a GC map at this call site.
3582 __ mov(G2_thread, O0);
3583 __ save_thread(L7_thread_cache);
3584 __ call(call_ptr);
3585 __ delayed()->nop();
3586
3587 // Set an oopmap for the call site.
3588 // We need this not only for callee-saved registers, but also for volatile
3589 // registers that the compiler might be keeping live across a safepoint.
3590
3591 oop_maps->add_gc_map( __ offset() - start, map);
3592
3593 __ restore_thread(L7_thread_cache);
3594 // clear last_Java_sp
3595 __ reset_last_Java_frame();
3596
3597 // Check for exceptions
3598 Label pending;
3599
3600 __ ld_ptr(G2_thread, in_bytes(Thread::pending_exception_offset()), O1);
3601 __ tst(O1);
3602 __ brx(Assembler::notEqual, true, Assembler::pn, pending);
3603 __ delayed()->nop();
3604
3605 RegisterSaver::restore_live_registers(masm);
3606
3607 // We are back the the original state on entry and ready to go.
3608
3609 __ retl();
3610 __ delayed()->nop();
3611
3612 // Pending exception after the safepoint
3613
3614 __ bind(pending);
3615
3616 RegisterSaver::restore_live_registers(masm);
3617
3618 // We are back the the original state on entry.
3619
3620 // Tail-call forward_exception_entry, with the issuing PC in O7,
3621 // so it looks like the original nmethod called forward_exception_entry.
3622 __ set((intptr_t)StubRoutines::forward_exception_entry(), O0);
3623 __ JMP(O0, 0);
3624 __ delayed()->nop();
3625
3626 // -------------
3627 // make sure all code is generated
3628 masm->flush();
3629
3630 // return exception blob
3631 return SafepointBlob::create(&buffer, oop_maps, frame_size_words);
3632 }
3633
3634 //
3635 // generate_resolve_blob - call resolution (static/virtual/opt-virtual/ic-miss
3636 //
3637 // Generate a stub that calls into vm to find out the proper destination
3638 // of a java call. All the argument registers are live at this point
3639 // but since this is generic code we don't know what they are and the caller
3640 // must do any gc of the args.
3641 //
3642 static RuntimeStub* generate_resolve_blob(address destination, const char* name) {
3643 assert (StubRoutines::forward_exception_entry() != NULL, "must be generated before");
3644
3645 // allocate space for the code
3646 ResourceMark rm;
3647 // setup code generation tools
3648 // Measured 8/7/03 at 896 in 32bit debug build (no VerifyThread)
3649 // Measured 8/7/03 at 1080 in 32bit debug build (VerifyThread)
3650 // even larger with TraceJumps
3651 int pad = TraceJumps ? 512 : 0;
3652 CodeBuffer buffer(name, 1600 + pad, 512);
3653 MacroAssembler* masm = new MacroAssembler(&buffer);
3654 int frame_size_words;
3655 OopMapSet *oop_maps = new OopMapSet();
3656 OopMap* map = NULL;
3657
3658 int start = __ offset();
3659
3660 map = RegisterSaver::save_live_registers(masm, 0, &frame_size_words);
3661
3662 int frame_complete = __ offset();
3663
3664 // setup last_Java_sp (blows G4)
3665 __ set_last_Java_frame(SP, noreg);
3666
3667 // call into the runtime to handle illegal instructions exception
3668 // Do not use call_VM_leaf, because we need to make a GC map at this call site.
3669 __ mov(G2_thread, O0);
3670 __ save_thread(L7_thread_cache);
3671 __ call(destination, relocInfo::runtime_call_type);
3672 __ delayed()->nop();
3673
3674 // O0 contains the address we are going to jump to assuming no exception got installed
3675
3676 // Set an oopmap for the call site.
3677 // We need this not only for callee-saved registers, but also for volatile
3678 // registers that the compiler might be keeping live across a safepoint.
3679
3680 oop_maps->add_gc_map( __ offset() - start, map);
3681
3682 __ restore_thread(L7_thread_cache);
3683 // clear last_Java_sp
3684 __ reset_last_Java_frame();
3685
3686 // Check for exceptions
3687 Label pending;
3688
3689 __ ld_ptr(G2_thread, in_bytes(Thread::pending_exception_offset()), O1);
3690 __ tst(O1);
3691 __ brx(Assembler::notEqual, true, Assembler::pn, pending);
3692 __ delayed()->nop();
3693
3694 // get the returned methodOop
3695
3696 __ get_vm_result(G5_method);
3697 __ stx(G5_method, SP, RegisterSaver::G5_offset()+STACK_BIAS);
3698
3699 // O0 is where we want to jump, overwrite G3 which is saved and scratch
3700
3701 __ stx(O0, SP, RegisterSaver::G3_offset()+STACK_BIAS);
3702
3703 RegisterSaver::restore_live_registers(masm);
3704
3705 // We are back the the original state on entry and ready to go.
3706
3707 __ JMP(G3, 0);
3708 __ delayed()->nop();
3709
3710 // Pending exception after the safepoint
3711
3712 __ bind(pending);
3713
3714 RegisterSaver::restore_live_registers(masm);
3715
3716 // We are back the the original state on entry.
3717
3718 // Tail-call forward_exception_entry, with the issuing PC in O7,
3719 // so it looks like the original nmethod called forward_exception_entry.
3720 __ set((intptr_t)StubRoutines::forward_exception_entry(), O0);
3721 __ JMP(O0, 0);
3722 __ delayed()->nop();
3723
3724 // -------------
3725 // make sure all code is generated
3726 masm->flush();
3727
3728 // return the blob
3729 // frame_size_words or bytes??
3730 return RuntimeStub::new_runtime_stub(name, &buffer, frame_complete, frame_size_words, oop_maps, true);
3731 }
3732
3733 void SharedRuntime::generate_stubs() {
3734
3735 _wrong_method_blob = generate_resolve_blob(CAST_FROM_FN_PTR(address, SharedRuntime::handle_wrong_method),
3736 "wrong_method_stub");
3737
3738 _ic_miss_blob = generate_resolve_blob(CAST_FROM_FN_PTR(address, SharedRuntime::handle_wrong_method_ic_miss),
3739 "ic_miss_stub");
3740
3741 _resolve_opt_virtual_call_blob = generate_resolve_blob(CAST_FROM_FN_PTR(address, SharedRuntime::resolve_opt_virtual_call_C),
3742 "resolve_opt_virtual_call");
3743
3744 _resolve_virtual_call_blob = generate_resolve_blob(CAST_FROM_FN_PTR(address, SharedRuntime::resolve_virtual_call_C),
3745 "resolve_virtual_call");
3746
3747 _resolve_static_call_blob = generate_resolve_blob(CAST_FROM_FN_PTR(address, SharedRuntime::resolve_static_call_C),
3748 "resolve_static_call");
3749
3750 _polling_page_safepoint_handler_blob =
3751 generate_handler_blob(CAST_FROM_FN_PTR(address,
3752 SafepointSynchronize::handle_polling_page_exception), false);
3753
3754 _polling_page_return_handler_blob =
3755 generate_handler_blob(CAST_FROM_FN_PTR(address,
3756 SafepointSynchronize::handle_polling_page_exception), true);
3757
3758 generate_deopt_blob();
3759
3760 #ifdef COMPILER2
3761 generate_uncommon_trap_blob();
3762 #endif // COMPILER2
3763 }