1092 // data is passed in only 1 slot. This code also handles longs that
1093 // are passed on the stack, but need a stack-to-stack move through a
1094 // spare float register.
1095 Register slot = (sig_bt[i]==T_LONG || sig_bt[i] == T_DOUBLE) ?
1096 next_arg_slot(ld_off) : arg_slot(ld_off);
1097 __ ldf(FloatRegisterImpl::D, Gargs, slot, r_1->as_FloatRegister());
1098 #else
1099 // Need to marshal 64-bit value from misaligned Lesp loads
1100 __ ldf(FloatRegisterImpl::S, Gargs, next_arg_slot(ld_off), r_1->as_FloatRegister());
1101 __ ldf(FloatRegisterImpl::S, Gargs, arg_slot(ld_off), r_2->as_FloatRegister());
1102 #endif
1103 }
1104 }
1105 // Was the argument really intended to be on the stack, but was loaded
1106 // into F8/F9?
1107 if (regs[i].first()->is_stack()) {
1108 assert(r_1->as_FloatRegister() == F8, "fix this code");
1109 // Convert stack slot to an SP offset
1110 int st_off = reg2offset(regs[i].first()) + STACK_BIAS;
1111 // Store down the shuffled stack word. Target address _is_ aligned.
1112 if (!r_2->is_valid()) __ stf(FloatRegisterImpl::S, r_1->as_FloatRegister(), SP, st_off);
1113 else __ stf(FloatRegisterImpl::D, r_1->as_FloatRegister(), SP, st_off);
1114 }
1115 }
1116 bool made_space = false;
1117 #ifndef _LP64
1118 // May need to pick up a few long args in G1/G4
1119 bool g4_crushed = false;
1120 bool g3_crushed = false;
1121 for (int i=0; i<total_args_passed; i++) {
1122 if (regs[i].first()->is_Register() && regs[i].second()->is_valid()) {
1123 // Load in argument order going down
1124 int ld_off = (total_args_passed-i)*Interpreter::stackElementSize();
1125 // Need to marshal 64-bit value from misaligned Lesp loads
1126 Register r = regs[i].first()->as_Register()->after_restore();
1127 if (r == G1 || r == G4) {
1128 assert(!g4_crushed, "ordering problem");
1129 if (r == G4){
1130 g4_crushed = true;
1131 __ lduw(Gargs, arg_slot(ld_off) , G3_scratch); // Load lo bits
1132 __ ld (Gargs, next_arg_slot(ld_off), r); // Load hi bits
1133 } else {
|
1092 // data is passed in only 1 slot. This code also handles longs that
1093 // are passed on the stack, but need a stack-to-stack move through a
1094 // spare float register.
1095 Register slot = (sig_bt[i]==T_LONG || sig_bt[i] == T_DOUBLE) ?
1096 next_arg_slot(ld_off) : arg_slot(ld_off);
1097 __ ldf(FloatRegisterImpl::D, Gargs, slot, r_1->as_FloatRegister());
1098 #else
1099 // Need to marshal 64-bit value from misaligned Lesp loads
1100 __ ldf(FloatRegisterImpl::S, Gargs, next_arg_slot(ld_off), r_1->as_FloatRegister());
1101 __ ldf(FloatRegisterImpl::S, Gargs, arg_slot(ld_off), r_2->as_FloatRegister());
1102 #endif
1103 }
1104 }
1105 // Was the argument really intended to be on the stack, but was loaded
1106 // into F8/F9?
1107 if (regs[i].first()->is_stack()) {
1108 assert(r_1->as_FloatRegister() == F8, "fix this code");
1109 // Convert stack slot to an SP offset
1110 int st_off = reg2offset(regs[i].first()) + STACK_BIAS;
1111 // Store down the shuffled stack word. Target address _is_ aligned.
1112 if (Assembler::is_simm13(st_off)) {
1113 if (!r_2->is_valid()) __ stf(FloatRegisterImpl::S, r_1->as_FloatRegister(), SP, st_off);
1114 else __ stf(FloatRegisterImpl::D, r_1->as_FloatRegister(), SP, st_off);
1115 } else {
1116 __ set(st_off, Rdisp);
1117 if (!r_2->is_valid()) __ stf(FloatRegisterImpl::S, r_1->as_FloatRegister(), SP, Rdisp);
1118 else __ stf(FloatRegisterImpl::D, r_1->as_FloatRegister(), SP, Rdisp);
1119 }
1120 }
1121 }
1122 bool made_space = false;
1123 #ifndef _LP64
1124 // May need to pick up a few long args in G1/G4
1125 bool g4_crushed = false;
1126 bool g3_crushed = false;
1127 for (int i=0; i<total_args_passed; i++) {
1128 if (regs[i].first()->is_Register() && regs[i].second()->is_valid()) {
1129 // Load in argument order going down
1130 int ld_off = (total_args_passed-i)*Interpreter::stackElementSize();
1131 // Need to marshal 64-bit value from misaligned Lesp loads
1132 Register r = regs[i].first()->as_Register()->after_restore();
1133 if (r == G1 || r == G4) {
1134 assert(!g4_crushed, "ordering problem");
1135 if (r == G4){
1136 g4_crushed = true;
1137 __ lduw(Gargs, arg_slot(ld_off) , G3_scratch); // Load lo bits
1138 __ ld (Gargs, next_arg_slot(ld_off), r); // Load hi bits
1139 } else {
|