src/cpu/sparc/vm/sparc.ad
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src/cpu/sparc/vm/sparc.ad

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*** 9417,9428 **** // x |= (x >> 2); // x |= (x >> 4); // x |= (x >> 8); // x |= (x >> 16); // return (WORDBITS - popc(x)); ! format %{ "SRL $src,1,$dst\t! count leading zeros (int)\n\t" "OR $src,$tmp,$dst\n\t" "SRL $dst,2,$tmp\n\t" "OR $dst,$tmp,$dst\n\t" "SRL $dst,4,$tmp\n\t" "OR $dst,$tmp,$dst\n\t" "SRL $dst,8,$tmp\n\t" --- 9417,9433 ---- // x |= (x >> 2); // x |= (x >> 4); // x |= (x >> 8); // x |= (x >> 16); // return (WORDBITS - popc(x)); ! format %{ "SRL $src,1,$tmp\t! count leading zeros (int)\n\t" ! #ifdef _LP64 ! "SRL $src,0,$dst\t! 32-bit zero extend\n\t" ! "OR $dst,$tmp,$dst\n\t" ! #else "OR $src,$tmp,$dst\n\t" + #endif "SRL $dst,2,$tmp\n\t" "OR $dst,$tmp,$dst\n\t" "SRL $dst,4,$tmp\n\t" "OR $dst,$tmp,$dst\n\t" "SRL $dst,8,$tmp\n\t"
*** 9435,9445 **** --- 9440,9455 ---- ins_encode %{ Register Rdst = $dst$$Register; Register Rsrc = $src$$Register; Register Rtmp = $tmp$$Register; __ srl(Rsrc, 1, Rtmp); + #ifdef _LP64 + __ srl(Rsrc, 0, Rdst); + __ or3(Rdst, Rtmp, Rdst); + #else __ or3(Rsrc, Rtmp, Rdst); + #endif __ srl(Rdst, 2, Rtmp); __ or3(Rdst, Rtmp, Rdst); __ srl(Rdst, 4, Rtmp); __ or3(Rdst, Rtmp, Rdst); __ srl(Rdst, 8, Rtmp);
*** 9463,9473 **** // x |= (x >> 4); // x |= (x >> 8); // x |= (x >> 16); // x |= (x >> 32); // return (WORDBITS - popc(x)); ! format %{ "SRLX $src,1,$dst\t! count leading zeros (long)\n\t" "OR $src,$tmp,$dst\n\t" "SRLX $dst,2,$tmp\n\t" "OR $dst,$tmp,$dst\n\t" "SRLX $dst,4,$tmp\n\t" "OR $dst,$tmp,$dst\n\t" --- 9473,9483 ---- // x |= (x >> 4); // x |= (x >> 8); // x |= (x >> 16); // x |= (x >> 32); // return (WORDBITS - popc(x)); ! format %{ "SRLX $src,1,$tmp\t! count leading zeros (long)\n\t" "OR $src,$tmp,$dst\n\t" "SRLX $dst,2,$tmp\n\t" "OR $dst,$tmp,$dst\n\t" "SRLX $dst,4,$tmp\n\t" "OR $dst,$tmp,$dst\n\t"
src/cpu/sparc/vm/sparc.ad
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