src/cpu/sparc/vm/sparc.ad
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src/cpu/sparc/vm/sparc.ad

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9402   ins_cost(300);
9403   format %{ "Array Equals $ary1,$ary2 -> $result   // KILL $tmp1,$tmp2" %}
9404   ins_encode( enc_Array_Equals(ary1, ary2, tmp1, result));
9405   ins_pipe(long_memory_op);
9406 %}
9407 
9408 
9409 //---------- Zeros Count Instructions ------------------------------------------
9410 
9411 instruct countLeadingZerosI(iRegI dst, iRegI src, iRegI tmp, flagsReg cr) %{
9412   predicate(UsePopCountInstruction);  // See Matcher::match_rule_supported
9413   match(Set dst (CountLeadingZerosI src));
9414   effect(TEMP dst, TEMP tmp, KILL cr);
9415 
9416   // x |= (x >> 1);
9417   // x |= (x >> 2);
9418   // x |= (x >> 4);
9419   // x |= (x >> 8);
9420   // x |= (x >> 16);
9421   // return (WORDBITS - popc(x));
9422   format %{ "SRL     $src,1,$dst\t! count leading zeros (int)\n\t"
9423             "OR      $src,$tmp,$dst\n\t"

9424             "SRL     $dst,2,$tmp\n\t"
9425             "OR      $dst,$tmp,$dst\n\t"
9426             "SRL     $dst,4,$tmp\n\t"
9427             "OR      $dst,$tmp,$dst\n\t"
9428             "SRL     $dst,8,$tmp\n\t"
9429             "OR      $dst,$tmp,$dst\n\t"
9430             "SRL     $dst,16,$tmp\n\t"
9431             "OR      $dst,$tmp,$dst\n\t"
9432             "POPC    $dst,$dst\n\t"
9433             "MOV     32,$tmp\n\t"
9434             "SUB     $tmp,$dst,$dst" %}
9435   ins_encode %{
9436     Register Rdst = $dst$$Register;
9437     Register Rsrc = $src$$Register;
9438     Register Rtmp = $tmp$$Register;
9439     __ srl(Rsrc, 1, Rtmp);
9440     __ or3(Rsrc, Rtmp, Rdst);

9441     __ srl(Rdst, 2, Rtmp);
9442     __ or3(Rdst, Rtmp, Rdst);
9443     __ srl(Rdst, 4, Rtmp);
9444     __ or3(Rdst, Rtmp, Rdst);
9445     __ srl(Rdst, 8, Rtmp);
9446     __ or3(Rdst, Rtmp, Rdst);
9447     __ srl(Rdst, 16, Rtmp);
9448     __ or3(Rdst, Rtmp, Rdst);
9449     __ popc(Rdst, Rdst);
9450     __ mov(BitsPerInt, Rtmp);
9451     __ sub(Rtmp, Rdst, Rdst);
9452   %}
9453   ins_pipe(ialu_reg);
9454 %}
9455 
9456 instruct countLeadingZerosL(iRegI dst, iRegL src, iRegL tmp, flagsReg cr) %{
9457   predicate(UsePopCountInstruction);  // See Matcher::match_rule_supported
9458   match(Set dst (CountLeadingZerosL src));
9459   effect(TEMP dst, TEMP tmp, KILL cr);
9460 
9461   // x |= (x >> 1);
9462   // x |= (x >> 2);
9463   // x |= (x >> 4);
9464   // x |= (x >> 8);
9465   // x |= (x >> 16);
9466   // x |= (x >> 32);
9467   // return (WORDBITS - popc(x));
9468   format %{ "SRLX    $src,1,$dst\t! count leading zeros (long)\n\t"
9469             "OR      $src,$tmp,$dst\n\t"
9470             "SRLX    $dst,2,$tmp\n\t"
9471             "OR      $dst,$tmp,$dst\n\t"
9472             "SRLX    $dst,4,$tmp\n\t"
9473             "OR      $dst,$tmp,$dst\n\t"
9474             "SRLX    $dst,8,$tmp\n\t"
9475             "OR      $dst,$tmp,$dst\n\t"
9476             "SRLX    $dst,16,$tmp\n\t"
9477             "OR      $dst,$tmp,$dst\n\t"
9478             "SRLX    $dst,32,$tmp\n\t"
9479             "OR      $dst,$tmp,$dst\n\t"
9480             "POPC    $dst,$dst\n\t"
9481             "MOV     64,$tmp\n\t"
9482             "SUB     $tmp,$dst,$dst" %}
9483   ins_encode %{
9484     Register Rdst = $dst$$Register;
9485     Register Rsrc = $src$$Register;
9486     Register Rtmp = $tmp$$Register;
9487     __ srlx(Rsrc, 1, Rtmp);
9488     __ or3(Rsrc, Rtmp, Rdst);




9402   ins_cost(300);
9403   format %{ "Array Equals $ary1,$ary2 -> $result   // KILL $tmp1,$tmp2" %}
9404   ins_encode( enc_Array_Equals(ary1, ary2, tmp1, result));
9405   ins_pipe(long_memory_op);
9406 %}
9407 
9408 
9409 //---------- Zeros Count Instructions ------------------------------------------
9410 
9411 instruct countLeadingZerosI(iRegI dst, iRegI src, iRegI tmp, flagsReg cr) %{
9412   predicate(UsePopCountInstruction);  // See Matcher::match_rule_supported
9413   match(Set dst (CountLeadingZerosI src));
9414   effect(TEMP dst, TEMP tmp, KILL cr);
9415 
9416   // x |= (x >> 1);
9417   // x |= (x >> 2);
9418   // x |= (x >> 4);
9419   // x |= (x >> 8);
9420   // x |= (x >> 16);
9421   // return (WORDBITS - popc(x));
9422   format %{ "SRL     $src,1,$tmp\t! count leading zeros (int)\n\t"
9423             "SRL     $src,0,$dst\t! 32-bit zero extend\n\t"
9424             "OR      $dst,$tmp,$dst\n\t"
9425             "SRL     $dst,2,$tmp\n\t"
9426             "OR      $dst,$tmp,$dst\n\t"
9427             "SRL     $dst,4,$tmp\n\t"
9428             "OR      $dst,$tmp,$dst\n\t"
9429             "SRL     $dst,8,$tmp\n\t"
9430             "OR      $dst,$tmp,$dst\n\t"
9431             "SRL     $dst,16,$tmp\n\t"
9432             "OR      $dst,$tmp,$dst\n\t"
9433             "POPC    $dst,$dst\n\t"
9434             "MOV     32,$tmp\n\t"
9435             "SUB     $tmp,$dst,$dst" %}
9436   ins_encode %{
9437     Register Rdst = $dst$$Register;
9438     Register Rsrc = $src$$Register;
9439     Register Rtmp = $tmp$$Register;
9440     __ srl(Rsrc, 1, Rtmp);
9441     __ srl(Rsrc, 0, Rdst);
9442     __ or3(Rdst, Rtmp, Rdst);
9443     __ srl(Rdst, 2, Rtmp);
9444     __ or3(Rdst, Rtmp, Rdst);
9445     __ srl(Rdst, 4, Rtmp);
9446     __ or3(Rdst, Rtmp, Rdst);
9447     __ srl(Rdst, 8, Rtmp);
9448     __ or3(Rdst, Rtmp, Rdst);
9449     __ srl(Rdst, 16, Rtmp);
9450     __ or3(Rdst, Rtmp, Rdst);
9451     __ popc(Rdst, Rdst);
9452     __ mov(BitsPerInt, Rtmp);
9453     __ sub(Rtmp, Rdst, Rdst);
9454   %}
9455   ins_pipe(ialu_reg);
9456 %}
9457 
9458 instruct countLeadingZerosL(iRegI dst, iRegL src, iRegL tmp, flagsReg cr) %{
9459   predicate(UsePopCountInstruction);  // See Matcher::match_rule_supported
9460   match(Set dst (CountLeadingZerosL src));
9461   effect(TEMP dst, TEMP tmp, KILL cr);
9462 
9463   // x |= (x >> 1);
9464   // x |= (x >> 2);
9465   // x |= (x >> 4);
9466   // x |= (x >> 8);
9467   // x |= (x >> 16);
9468   // x |= (x >> 32);
9469   // return (WORDBITS - popc(x));
9470   format %{ "SRLX    $src,1,$tmp\t! count leading zeros (long)\n\t"
9471             "OR      $src,$tmp,$dst\n\t"
9472             "SRLX    $dst,2,$tmp\n\t"
9473             "OR      $dst,$tmp,$dst\n\t"
9474             "SRLX    $dst,4,$tmp\n\t"
9475             "OR      $dst,$tmp,$dst\n\t"
9476             "SRLX    $dst,8,$tmp\n\t"
9477             "OR      $dst,$tmp,$dst\n\t"
9478             "SRLX    $dst,16,$tmp\n\t"
9479             "OR      $dst,$tmp,$dst\n\t"
9480             "SRLX    $dst,32,$tmp\n\t"
9481             "OR      $dst,$tmp,$dst\n\t"
9482             "POPC    $dst,$dst\n\t"
9483             "MOV     64,$tmp\n\t"
9484             "SUB     $tmp,$dst,$dst" %}
9485   ins_encode %{
9486     Register Rdst = $dst$$Register;
9487     Register Rsrc = $src$$Register;
9488     Register Rtmp = $tmp$$Register;
9489     __ srlx(Rsrc, 1, Rtmp);
9490     __ or3(Rsrc, Rtmp, Rdst);


src/cpu/sparc/vm/sparc.ad
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