1 /*
2 * Copyright 2000-2010 Sun Microsystems, Inc. All Rights Reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
20 * CA 95054 USA or visit www.sun.com if you need additional information or
21 * have any questions.
22 *
23 */
24
25 # include "incls/_precompiled.incl"
26 # include "incls/_c1_LIRAssembler_sparc.cpp.incl"
27
28 #define __ _masm->
29
30
31 //------------------------------------------------------------
32
33
34 bool LIR_Assembler::is_small_constant(LIR_Opr opr) {
35 if (opr->is_constant()) {
36 LIR_Const* constant = opr->as_constant_ptr();
37 switch (constant->type()) {
38 case T_INT: {
39 jint value = constant->as_jint();
40 return Assembler::is_simm13(value);
41 }
42
43 default:
44 return false;
45 }
46 }
47 return false;
48 }
49
50
51 bool LIR_Assembler::is_single_instruction(LIR_Op* op) {
52 switch (op->code()) {
53 case lir_null_check:
54 return true;
55
56
57 case lir_add:
58 case lir_ushr:
59 case lir_shr:
60 case lir_shl:
61 // integer shifts and adds are always one instruction
62 return op->result_opr()->is_single_cpu();
63
64
65 case lir_move: {
66 LIR_Op1* op1 = op->as_Op1();
67 LIR_Opr src = op1->in_opr();
68 LIR_Opr dst = op1->result_opr();
69
70 if (src == dst) {
71 NEEDS_CLEANUP;
72 // this works around a problem where moves with the same src and dst
73 // end up in the delay slot and then the assembler swallows the mov
74 // since it has no effect and then it complains because the delay slot
75 // is empty. returning false stops the optimizer from putting this in
76 // the delay slot
77 return false;
78 }
79
80 // don't put moves involving oops into the delay slot since the VerifyOops code
81 // will make it much larger than a single instruction.
82 if (VerifyOops) {
83 return false;
84 }
85
86 if (src->is_double_cpu() || dst->is_double_cpu() || op1->patch_code() != lir_patch_none ||
87 ((src->is_double_fpu() || dst->is_double_fpu()) && op1->move_kind() != lir_move_normal)) {
88 return false;
89 }
90
91 if (dst->is_register()) {
92 if (src->is_address() && Assembler::is_simm13(src->as_address_ptr()->disp())) {
93 return !PatchALot;
94 } else if (src->is_single_stack()) {
95 return true;
96 }
97 }
98
99 if (src->is_register()) {
100 if (dst->is_address() && Assembler::is_simm13(dst->as_address_ptr()->disp())) {
101 return !PatchALot;
102 } else if (dst->is_single_stack()) {
103 return true;
104 }
105 }
106
107 if (dst->is_register() &&
108 ((src->is_register() && src->is_single_word() && src->is_same_type(dst)) ||
109 (src->is_constant() && LIR_Assembler::is_small_constant(op->as_Op1()->in_opr())))) {
110 return true;
111 }
112
113 return false;
114 }
115
116 default:
117 return false;
118 }
119 ShouldNotReachHere();
120 }
121
122
123 LIR_Opr LIR_Assembler::receiverOpr() {
124 return FrameMap::O0_oop_opr;
125 }
126
127
128 LIR_Opr LIR_Assembler::incomingReceiverOpr() {
129 return FrameMap::I0_oop_opr;
130 }
131
132
133 LIR_Opr LIR_Assembler::osrBufferPointer() {
134 return FrameMap::I0_opr;
135 }
136
137
138 int LIR_Assembler::initial_frame_size_in_bytes() {
139 return in_bytes(frame_map()->framesize_in_bytes());
140 }
141
142
143 // inline cache check: the inline cached class is in G5_inline_cache_reg(G5);
144 // we fetch the class of the receiver (O0) and compare it with the cached class.
145 // If they do not match we jump to slow case.
146 int LIR_Assembler::check_icache() {
147 int offset = __ offset();
148 __ inline_cache_check(O0, G5_inline_cache_reg);
149 return offset;
150 }
151
152
153 void LIR_Assembler::osr_entry() {
154 // On-stack-replacement entry sequence (interpreter frame layout described in interpreter_sparc.cpp):
155 //
156 // 1. Create a new compiled activation.
157 // 2. Initialize local variables in the compiled activation. The expression stack must be empty
158 // at the osr_bci; it is not initialized.
159 // 3. Jump to the continuation address in compiled code to resume execution.
160
161 // OSR entry point
162 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
163 BlockBegin* osr_entry = compilation()->hir()->osr_entry();
164 ValueStack* entry_state = osr_entry->end()->state();
165 int number_of_locks = entry_state->locks_size();
166
167 // Create a frame for the compiled activation.
168 __ build_frame(initial_frame_size_in_bytes());
169
170 // OSR buffer is
171 //
172 // locals[nlocals-1..0]
173 // monitors[number_of_locks-1..0]
174 //
175 // locals is a direct copy of the interpreter frame so in the osr buffer
176 // so first slot in the local array is the last local from the interpreter
177 // and last slot is local[0] (receiver) from the interpreter
178 //
179 // Similarly with locks. The first lock slot in the osr buffer is the nth lock
180 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
181 // in the interpreter frame (the method lock if a sync method)
182
183 // Initialize monitors in the compiled activation.
184 // I0: pointer to osr buffer
185 //
186 // All other registers are dead at this point and the locals will be
187 // copied into place by code emitted in the IR.
188
189 Register OSR_buf = osrBufferPointer()->as_register();
190 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
191 int monitor_offset = BytesPerWord * method()->max_locals() +
192 (2 * BytesPerWord) * (number_of_locks - 1);
193 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
194 // the OSR buffer using 2 word entries: first the lock and then
195 // the oop.
196 for (int i = 0; i < number_of_locks; i++) {
197 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
198 #ifdef ASSERT
199 // verify the interpreter's monitor has a non-null object
200 {
201 Label L;
202 __ ld_ptr(OSR_buf, slot_offset + 1*BytesPerWord, O7);
203 __ cmp(G0, O7);
204 __ br(Assembler::notEqual, false, Assembler::pt, L);
205 __ delayed()->nop();
206 __ stop("locked object is NULL");
207 __ bind(L);
208 }
209 #endif // ASSERT
210 // Copy the lock field into the compiled activation.
211 __ ld_ptr(OSR_buf, slot_offset + 0, O7);
212 __ st_ptr(O7, frame_map()->address_for_monitor_lock(i));
213 __ ld_ptr(OSR_buf, slot_offset + 1*BytesPerWord, O7);
214 __ st_ptr(O7, frame_map()->address_for_monitor_object(i));
215 }
216 }
217 }
218
219
220 // Optimized Library calls
221 // This is the fast version of java.lang.String.compare; it has not
222 // OSR-entry and therefore, we generate a slow version for OSR's
223 void LIR_Assembler::emit_string_compare(LIR_Opr left, LIR_Opr right, LIR_Opr dst, CodeEmitInfo* info) {
224 Register str0 = left->as_register();
225 Register str1 = right->as_register();
226
227 Label Ldone;
228
229 Register result = dst->as_register();
230 {
231 // Get a pointer to the first character of string0 in tmp0 and get string0.count in str0
232 // Get a pointer to the first character of string1 in tmp1 and get string1.count in str1
233 // Also, get string0.count-string1.count in o7 and get the condition code set
234 // Note: some instructions have been hoisted for better instruction scheduling
235
236 Register tmp0 = L0;
237 Register tmp1 = L1;
238 Register tmp2 = L2;
239
240 int value_offset = java_lang_String:: value_offset_in_bytes(); // char array
241 int offset_offset = java_lang_String::offset_offset_in_bytes(); // first character position
242 int count_offset = java_lang_String:: count_offset_in_bytes();
243
244 __ ld_ptr(str0, value_offset, tmp0);
245 __ ld(str0, offset_offset, tmp2);
246 __ add(tmp0, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp0);
247 __ ld(str0, count_offset, str0);
248 __ sll(tmp2, exact_log2(sizeof(jchar)), tmp2);
249
250 // str1 may be null
251 add_debug_info_for_null_check_here(info);
252
253 __ ld_ptr(str1, value_offset, tmp1);
254 __ add(tmp0, tmp2, tmp0);
255
256 __ ld(str1, offset_offset, tmp2);
257 __ add(tmp1, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp1);
258 __ ld(str1, count_offset, str1);
259 __ sll(tmp2, exact_log2(sizeof(jchar)), tmp2);
260 __ subcc(str0, str1, O7);
261 __ add(tmp1, tmp2, tmp1);
262 }
263
264 {
265 // Compute the minimum of the string lengths, scale it and store it in limit
266 Register count0 = I0;
267 Register count1 = I1;
268 Register limit = L3;
269
270 Label Lskip;
271 __ sll(count0, exact_log2(sizeof(jchar)), limit); // string0 is shorter
272 __ br(Assembler::greater, true, Assembler::pt, Lskip);
273 __ delayed()->sll(count1, exact_log2(sizeof(jchar)), limit); // string1 is shorter
274 __ bind(Lskip);
275
276 // If either string is empty (or both of them) the result is the difference in lengths
277 __ cmp(limit, 0);
278 __ br(Assembler::equal, true, Assembler::pn, Ldone);
279 __ delayed()->mov(O7, result); // result is difference in lengths
280 }
281
282 {
283 // Neither string is empty
284 Label Lloop;
285
286 Register base0 = L0;
287 Register base1 = L1;
288 Register chr0 = I0;
289 Register chr1 = I1;
290 Register limit = L3;
291
292 // Shift base0 and base1 to the end of the arrays, negate limit
293 __ add(base0, limit, base0);
294 __ add(base1, limit, base1);
295 __ neg(limit); // limit = -min{string0.count, strin1.count}
296
297 __ lduh(base0, limit, chr0);
298 __ bind(Lloop);
299 __ lduh(base1, limit, chr1);
300 __ subcc(chr0, chr1, chr0);
301 __ br(Assembler::notZero, false, Assembler::pn, Ldone);
302 assert(chr0 == result, "result must be pre-placed");
303 __ delayed()->inccc(limit, sizeof(jchar));
304 __ br(Assembler::notZero, true, Assembler::pt, Lloop);
305 __ delayed()->lduh(base0, limit, chr0);
306 }
307
308 // If strings are equal up to min length, return the length difference.
309 __ mov(O7, result);
310
311 // Otherwise, return the difference between the first mismatched chars.
312 __ bind(Ldone);
313 }
314
315
316 // --------------------------------------------------------------------------------------------
317
318 void LIR_Assembler::monitorexit(LIR_Opr obj_opr, LIR_Opr lock_opr, Register hdr, int monitor_no) {
319 if (!GenerateSynchronizationCode) return;
320
321 Register obj_reg = obj_opr->as_register();
322 Register lock_reg = lock_opr->as_register();
323
324 Address mon_addr = frame_map()->address_for_monitor_lock(monitor_no);
325 Register reg = mon_addr.base();
326 int offset = mon_addr.disp();
327 // compute pointer to BasicLock
328 if (mon_addr.is_simm13()) {
329 __ add(reg, offset, lock_reg);
330 }
331 else {
332 __ set(offset, lock_reg);
333 __ add(reg, lock_reg, lock_reg);
334 }
335 // unlock object
336 MonitorAccessStub* slow_case = new MonitorExitStub(lock_opr, UseFastLocking, monitor_no);
337 // _slow_case_stubs->append(slow_case);
338 // temporary fix: must be created after exceptionhandler, therefore as call stub
339 _slow_case_stubs->append(slow_case);
340 if (UseFastLocking) {
341 // try inlined fast unlocking first, revert to slow locking if it fails
342 // note: lock_reg points to the displaced header since the displaced header offset is 0!
343 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
344 __ unlock_object(hdr, obj_reg, lock_reg, *slow_case->entry());
345 } else {
346 // always do slow unlocking
347 // note: the slow unlocking code could be inlined here, however if we use
348 // slow unlocking, speed doesn't matter anyway and this solution is
349 // simpler and requires less duplicated code - additionally, the
350 // slow unlocking code is the same in either case which simplifies
351 // debugging
352 __ br(Assembler::always, false, Assembler::pt, *slow_case->entry());
353 __ delayed()->nop();
354 }
355 // done
356 __ bind(*slow_case->continuation());
357 }
358
359
360 int LIR_Assembler::emit_exception_handler() {
361 // if the last instruction is a call (typically to do a throw which
362 // is coming at the end after block reordering) the return address
363 // must still point into the code area in order to avoid assertion
364 // failures when searching for the corresponding bci => add a nop
365 // (was bug 5/14/1999 - gri)
366 __ nop();
367
368 // generate code for exception handler
369 ciMethod* method = compilation()->method();
370
371 address handler_base = __ start_a_stub(exception_handler_size);
372
373 if (handler_base == NULL) {
374 // not enough space left for the handler
375 bailout("exception handler overflow");
376 return -1;
377 }
378
379 int offset = code_offset();
380
381 __ call(Runtime1::entry_for(Runtime1::handle_exception_id), relocInfo::runtime_call_type);
382 __ delayed()->nop();
383 debug_only(__ stop("should have gone to the caller");)
384 assert(code_offset() - offset <= exception_handler_size, "overflow");
385 __ end_a_stub();
386
387 return offset;
388 }
389
390
391 int LIR_Assembler::emit_deopt_handler() {
392 // if the last instruction is a call (typically to do a throw which
393 // is coming at the end after block reordering) the return address
394 // must still point into the code area in order to avoid assertion
395 // failures when searching for the corresponding bci => add a nop
396 // (was bug 5/14/1999 - gri)
397 __ nop();
398
399 // generate code for deopt handler
400 ciMethod* method = compilation()->method();
401 address handler_base = __ start_a_stub(deopt_handler_size);
402 if (handler_base == NULL) {
403 // not enough space left for the handler
404 bailout("deopt handler overflow");
405 return -1;
406 }
407
408 int offset = code_offset();
409 AddressLiteral deopt_blob(SharedRuntime::deopt_blob()->unpack());
410 __ JUMP(deopt_blob, G3_scratch, 0); // sethi;jmp
411 __ delayed()->nop();
412 assert(code_offset() - offset <= deopt_handler_size, "overflow");
413 debug_only(__ stop("should have gone to the caller");)
414 __ end_a_stub();
415
416 return offset;
417 }
418
419
420 void LIR_Assembler::jobject2reg(jobject o, Register reg) {
421 if (o == NULL) {
422 __ set(NULL_WORD, reg);
423 } else {
424 int oop_index = __ oop_recorder()->find_index(o);
425 RelocationHolder rspec = oop_Relocation::spec(oop_index);
426 __ set(NULL_WORD, reg, rspec); // Will be set when the nmethod is created
427 }
428 }
429
430
431 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo *info) {
432 // Allocate a new index in oop table to hold the oop once it's been patched
433 int oop_index = __ oop_recorder()->allocate_index((jobject)NULL);
434 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id, oop_index);
435
436 AddressLiteral addrlit(NULL, oop_Relocation::spec(oop_index));
437 assert(addrlit.rspec().type() == relocInfo::oop_type, "must be an oop reloc");
438 // It may not seem necessary to use a sethi/add pair to load a NULL into dest, but the
439 // NULL will be dynamically patched later and the patched value may be large. We must
440 // therefore generate the sethi/add as a placeholders
441 __ patchable_set(addrlit, reg);
442
443 patching_epilog(patch, lir_patch_normal, reg, info);
444 }
445
446
447 void LIR_Assembler::emit_op3(LIR_Op3* op) {
448 Register Rdividend = op->in_opr1()->as_register();
449 Register Rdivisor = noreg;
450 Register Rscratch = op->in_opr3()->as_register();
451 Register Rresult = op->result_opr()->as_register();
452 int divisor = -1;
453
454 if (op->in_opr2()->is_register()) {
455 Rdivisor = op->in_opr2()->as_register();
456 } else {
457 divisor = op->in_opr2()->as_constant_ptr()->as_jint();
458 assert(Assembler::is_simm13(divisor), "can only handle simm13");
459 }
460
461 assert(Rdividend != Rscratch, "");
462 assert(Rdivisor != Rscratch, "");
463 assert(op->code() == lir_idiv || op->code() == lir_irem, "Must be irem or idiv");
464
465 if (Rdivisor == noreg && is_power_of_2(divisor)) {
466 // convert division by a power of two into some shifts and logical operations
467 if (op->code() == lir_idiv) {
468 if (divisor == 2) {
469 __ srl(Rdividend, 31, Rscratch);
470 } else {
471 __ sra(Rdividend, 31, Rscratch);
472 __ and3(Rscratch, divisor - 1, Rscratch);
473 }
474 __ add(Rdividend, Rscratch, Rscratch);
475 __ sra(Rscratch, log2_intptr(divisor), Rresult);
476 return;
477 } else {
478 if (divisor == 2) {
479 __ srl(Rdividend, 31, Rscratch);
480 } else {
481 __ sra(Rdividend, 31, Rscratch);
482 __ and3(Rscratch, divisor - 1,Rscratch);
483 }
484 __ add(Rdividend, Rscratch, Rscratch);
485 __ andn(Rscratch, divisor - 1,Rscratch);
486 __ sub(Rdividend, Rscratch, Rresult);
487 return;
488 }
489 }
490
491 __ sra(Rdividend, 31, Rscratch);
492 __ wry(Rscratch);
493 if (!VM_Version::v9_instructions_work()) {
494 // v9 doesn't require these nops
495 __ nop();
496 __ nop();
497 __ nop();
498 __ nop();
499 }
500
501 add_debug_info_for_div0_here(op->info());
502
503 if (Rdivisor != noreg) {
504 __ sdivcc(Rdividend, Rdivisor, (op->code() == lir_idiv ? Rresult : Rscratch));
505 } else {
506 assert(Assembler::is_simm13(divisor), "can only handle simm13");
507 __ sdivcc(Rdividend, divisor, (op->code() == lir_idiv ? Rresult : Rscratch));
508 }
509
510 Label skip;
511 __ br(Assembler::overflowSet, true, Assembler::pn, skip);
512 __ delayed()->Assembler::sethi(0x80000000, (op->code() == lir_idiv ? Rresult : Rscratch));
513 __ bind(skip);
514
515 if (op->code() == lir_irem) {
516 if (Rdivisor != noreg) {
517 __ smul(Rscratch, Rdivisor, Rscratch);
518 } else {
519 __ smul(Rscratch, divisor, Rscratch);
520 }
521 __ sub(Rdividend, Rscratch, Rresult);
522 }
523 }
524
525
526 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
527 #ifdef ASSERT
528 assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label");
529 if (op->block() != NULL) _branch_target_blocks.append(op->block());
530 if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock());
531 #endif
532 assert(op->info() == NULL, "shouldn't have CodeEmitInfo");
533
534 if (op->cond() == lir_cond_always) {
535 __ br(Assembler::always, false, Assembler::pt, *(op->label()));
536 } else if (op->code() == lir_cond_float_branch) {
537 assert(op->ublock() != NULL, "must have unordered successor");
538 bool is_unordered = (op->ublock() == op->block());
539 Assembler::Condition acond;
540 switch (op->cond()) {
541 case lir_cond_equal: acond = Assembler::f_equal; break;
542 case lir_cond_notEqual: acond = Assembler::f_notEqual; break;
543 case lir_cond_less: acond = (is_unordered ? Assembler::f_unorderedOrLess : Assembler::f_less); break;
544 case lir_cond_greater: acond = (is_unordered ? Assembler::f_unorderedOrGreater : Assembler::f_greater); break;
545 case lir_cond_lessEqual: acond = (is_unordered ? Assembler::f_unorderedOrLessOrEqual : Assembler::f_lessOrEqual); break;
546 case lir_cond_greaterEqual: acond = (is_unordered ? Assembler::f_unorderedOrGreaterOrEqual: Assembler::f_greaterOrEqual); break;
547 default : ShouldNotReachHere();
548 };
549
550 if (!VM_Version::v9_instructions_work()) {
551 __ nop();
552 }
553 __ fb( acond, false, Assembler::pn, *(op->label()));
554 } else {
555 assert (op->code() == lir_branch, "just checking");
556
557 Assembler::Condition acond;
558 switch (op->cond()) {
559 case lir_cond_equal: acond = Assembler::equal; break;
560 case lir_cond_notEqual: acond = Assembler::notEqual; break;
561 case lir_cond_less: acond = Assembler::less; break;
562 case lir_cond_lessEqual: acond = Assembler::lessEqual; break;
563 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; break;
564 case lir_cond_greater: acond = Assembler::greater; break;
565 case lir_cond_aboveEqual: acond = Assembler::greaterEqualUnsigned; break;
566 case lir_cond_belowEqual: acond = Assembler::lessEqualUnsigned; break;
567 default: ShouldNotReachHere();
568 };
569
570 // sparc has different condition codes for testing 32-bit
571 // vs. 64-bit values. We could always test xcc is we could
572 // guarantee that 32-bit loads always sign extended but that isn't
573 // true and since sign extension isn't free, it would impose a
574 // slight cost.
575 #ifdef _LP64
576 if (op->type() == T_INT) {
577 __ br(acond, false, Assembler::pn, *(op->label()));
578 } else
579 #endif
580 __ brx(acond, false, Assembler::pn, *(op->label()));
581 }
582 // The peephole pass fills the delay slot
583 }
584
585
586 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
587 Bytecodes::Code code = op->bytecode();
588 LIR_Opr dst = op->result_opr();
589
590 switch(code) {
591 case Bytecodes::_i2l: {
592 Register rlo = dst->as_register_lo();
593 Register rhi = dst->as_register_hi();
594 Register rval = op->in_opr()->as_register();
595 #ifdef _LP64
596 __ sra(rval, 0, rlo);
597 #else
598 __ mov(rval, rlo);
599 __ sra(rval, BitsPerInt-1, rhi);
600 #endif
601 break;
602 }
603 case Bytecodes::_i2d:
604 case Bytecodes::_i2f: {
605 bool is_double = (code == Bytecodes::_i2d);
606 FloatRegister rdst = is_double ? dst->as_double_reg() : dst->as_float_reg();
607 FloatRegisterImpl::Width w = is_double ? FloatRegisterImpl::D : FloatRegisterImpl::S;
608 FloatRegister rsrc = op->in_opr()->as_float_reg();
609 if (rsrc != rdst) {
610 __ fmov(FloatRegisterImpl::S, rsrc, rdst);
611 }
612 __ fitof(w, rdst, rdst);
613 break;
614 }
615 case Bytecodes::_f2i:{
616 FloatRegister rsrc = op->in_opr()->as_float_reg();
617 Address addr = frame_map()->address_for_slot(dst->single_stack_ix());
618 Label L;
619 // result must be 0 if value is NaN; test by comparing value to itself
620 __ fcmp(FloatRegisterImpl::S, Assembler::fcc0, rsrc, rsrc);
621 if (!VM_Version::v9_instructions_work()) {
622 __ nop();
623 }
624 __ fb(Assembler::f_unordered, true, Assembler::pn, L);
625 __ delayed()->st(G0, addr); // annuled if contents of rsrc is not NaN
626 __ ftoi(FloatRegisterImpl::S, rsrc, rsrc);
627 // move integer result from float register to int register
628 __ stf(FloatRegisterImpl::S, rsrc, addr.base(), addr.disp());
629 __ bind (L);
630 break;
631 }
632 case Bytecodes::_l2i: {
633 Register rlo = op->in_opr()->as_register_lo();
634 Register rhi = op->in_opr()->as_register_hi();
635 Register rdst = dst->as_register();
636 #ifdef _LP64
637 __ sra(rlo, 0, rdst);
638 #else
639 __ mov(rlo, rdst);
640 #endif
641 break;
642 }
643 case Bytecodes::_d2f:
644 case Bytecodes::_f2d: {
645 bool is_double = (code == Bytecodes::_f2d);
646 assert((!is_double && dst->is_single_fpu()) || (is_double && dst->is_double_fpu()), "check");
647 LIR_Opr val = op->in_opr();
648 FloatRegister rval = (code == Bytecodes::_d2f) ? val->as_double_reg() : val->as_float_reg();
649 FloatRegister rdst = is_double ? dst->as_double_reg() : dst->as_float_reg();
650 FloatRegisterImpl::Width vw = is_double ? FloatRegisterImpl::S : FloatRegisterImpl::D;
651 FloatRegisterImpl::Width dw = is_double ? FloatRegisterImpl::D : FloatRegisterImpl::S;
652 __ ftof(vw, dw, rval, rdst);
653 break;
654 }
655 case Bytecodes::_i2s:
656 case Bytecodes::_i2b: {
657 Register rval = op->in_opr()->as_register();
658 Register rdst = dst->as_register();
659 int shift = (code == Bytecodes::_i2b) ? (BitsPerInt - T_BYTE_aelem_bytes * BitsPerByte) : (BitsPerInt - BitsPerShort);
660 __ sll (rval, shift, rdst);
661 __ sra (rdst, shift, rdst);
662 break;
663 }
664 case Bytecodes::_i2c: {
665 Register rval = op->in_opr()->as_register();
666 Register rdst = dst->as_register();
667 int shift = BitsPerInt - T_CHAR_aelem_bytes * BitsPerByte;
668 __ sll (rval, shift, rdst);
669 __ srl (rdst, shift, rdst);
670 break;
671 }
672
673 default: ShouldNotReachHere();
674 }
675 }
676
677
678 void LIR_Assembler::align_call(LIR_Code) {
679 // do nothing since all instructions are word aligned on sparc
680 }
681
682
683 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
684 __ call(op->addr(), rtype);
685 // the peephole pass fills the delay slot
686 }
687
688
689 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
690 RelocationHolder rspec = virtual_call_Relocation::spec(pc());
691 __ set_oop((jobject)Universe::non_oop_word(), G5_inline_cache_reg);
692 __ relocate(rspec);
693 __ call(op->addr(), relocInfo::none);
694 // the peephole pass fills the delay slot
695 }
696
697
698 void LIR_Assembler::vtable_call(LIR_OpJavaCall* op) {
699 add_debug_info_for_null_check_here(op->info());
700 __ ld_ptr(O0, oopDesc::klass_offset_in_bytes(), G3_scratch);
701 if (__ is_simm13(op->vtable_offset())) {
702 __ ld_ptr(G3_scratch, op->vtable_offset(), G5_method);
703 } else {
704 // This will generate 2 instructions
705 __ set(op->vtable_offset(), G5_method);
706 // ld_ptr, set_hi, set
707 __ ld_ptr(G3_scratch, G5_method, G5_method);
708 }
709 __ ld_ptr(G5_method, methodOopDesc::from_compiled_offset(), G3_scratch);
710 __ callr(G3_scratch, G0);
711 // the peephole pass fills the delay slot
712 }
713
714
715 void LIR_Assembler::preserve_SP() {
716 // XXX I'm not sure yet if these are required on SPARC.
717 }
718
719
720 void LIR_Assembler::restore_SP() {
721 // XXX I'm not sure yet if these are required on SPARC.
722 }
723
724
725 // load with 32-bit displacement
726 int LIR_Assembler::load(Register s, int disp, Register d, BasicType ld_type, CodeEmitInfo *info) {
727 int load_offset = code_offset();
728 if (Assembler::is_simm13(disp)) {
729 if (info != NULL) add_debug_info_for_null_check_here(info);
730 switch(ld_type) {
731 case T_BOOLEAN: // fall through
732 case T_BYTE : __ ldsb(s, disp, d); break;
733 case T_CHAR : __ lduh(s, disp, d); break;
734 case T_SHORT : __ ldsh(s, disp, d); break;
735 case T_INT : __ ld(s, disp, d); break;
736 case T_ADDRESS:// fall through
737 case T_ARRAY : // fall through
738 case T_OBJECT: __ ld_ptr(s, disp, d); break;
739 default : ShouldNotReachHere();
740 }
741 } else {
742 __ set(disp, O7);
743 if (info != NULL) add_debug_info_for_null_check_here(info);
744 load_offset = code_offset();
745 switch(ld_type) {
746 case T_BOOLEAN: // fall through
747 case T_BYTE : __ ldsb(s, O7, d); break;
748 case T_CHAR : __ lduh(s, O7, d); break;
749 case T_SHORT : __ ldsh(s, O7, d); break;
750 case T_INT : __ ld(s, O7, d); break;
751 case T_ADDRESS:// fall through
752 case T_ARRAY : // fall through
753 case T_OBJECT: __ ld_ptr(s, O7, d); break;
754 default : ShouldNotReachHere();
755 }
756 }
757 if (ld_type == T_ARRAY || ld_type == T_OBJECT) __ verify_oop(d);
758 return load_offset;
759 }
760
761
762 // store with 32-bit displacement
763 void LIR_Assembler::store(Register value, Register base, int offset, BasicType type, CodeEmitInfo *info) {
764 if (Assembler::is_simm13(offset)) {
765 if (info != NULL) add_debug_info_for_null_check_here(info);
766 switch (type) {
767 case T_BOOLEAN: // fall through
768 case T_BYTE : __ stb(value, base, offset); break;
769 case T_CHAR : __ sth(value, base, offset); break;
770 case T_SHORT : __ sth(value, base, offset); break;
771 case T_INT : __ stw(value, base, offset); break;
772 case T_ADDRESS:// fall through
773 case T_ARRAY : // fall through
774 case T_OBJECT: __ st_ptr(value, base, offset); break;
775 default : ShouldNotReachHere();
776 }
777 } else {
778 __ set(offset, O7);
779 if (info != NULL) add_debug_info_for_null_check_here(info);
780 switch (type) {
781 case T_BOOLEAN: // fall through
782 case T_BYTE : __ stb(value, base, O7); break;
783 case T_CHAR : __ sth(value, base, O7); break;
784 case T_SHORT : __ sth(value, base, O7); break;
785 case T_INT : __ stw(value, base, O7); break;
786 case T_ADDRESS:// fall through
787 case T_ARRAY : //fall through
788 case T_OBJECT: __ st_ptr(value, base, O7); break;
789 default : ShouldNotReachHere();
790 }
791 }
792 // Note: Do the store before verification as the code might be patched!
793 if (type == T_ARRAY || type == T_OBJECT) __ verify_oop(value);
794 }
795
796
797 // load float with 32-bit displacement
798 void LIR_Assembler::load(Register s, int disp, FloatRegister d, BasicType ld_type, CodeEmitInfo *info) {
799 FloatRegisterImpl::Width w;
800 switch(ld_type) {
801 case T_FLOAT : w = FloatRegisterImpl::S; break;
802 case T_DOUBLE: w = FloatRegisterImpl::D; break;
803 default : ShouldNotReachHere();
804 }
805
806 if (Assembler::is_simm13(disp)) {
807 if (info != NULL) add_debug_info_for_null_check_here(info);
808 if (disp % BytesPerLong != 0 && w == FloatRegisterImpl::D) {
809 __ ldf(FloatRegisterImpl::S, s, disp + BytesPerWord, d->successor());
810 __ ldf(FloatRegisterImpl::S, s, disp , d);
811 } else {
812 __ ldf(w, s, disp, d);
813 }
814 } else {
815 __ set(disp, O7);
816 if (info != NULL) add_debug_info_for_null_check_here(info);
817 __ ldf(w, s, O7, d);
818 }
819 }
820
821
822 // store float with 32-bit displacement
823 void LIR_Assembler::store(FloatRegister value, Register base, int offset, BasicType type, CodeEmitInfo *info) {
824 FloatRegisterImpl::Width w;
825 switch(type) {
826 case T_FLOAT : w = FloatRegisterImpl::S; break;
827 case T_DOUBLE: w = FloatRegisterImpl::D; break;
828 default : ShouldNotReachHere();
829 }
830
831 if (Assembler::is_simm13(offset)) {
832 if (info != NULL) add_debug_info_for_null_check_here(info);
833 if (w == FloatRegisterImpl::D && offset % BytesPerLong != 0) {
834 __ stf(FloatRegisterImpl::S, value->successor(), base, offset + BytesPerWord);
835 __ stf(FloatRegisterImpl::S, value , base, offset);
836 } else {
837 __ stf(w, value, base, offset);
838 }
839 } else {
840 __ set(offset, O7);
841 if (info != NULL) add_debug_info_for_null_check_here(info);
842 __ stf(w, value, O7, base);
843 }
844 }
845
846
847 int LIR_Assembler::store(LIR_Opr from_reg, Register base, int offset, BasicType type, bool unaligned) {
848 int store_offset;
849 if (!Assembler::is_simm13(offset + (type == T_LONG) ? wordSize : 0)) {
850 assert(!unaligned, "can't handle this");
851 // for offsets larger than a simm13 we setup the offset in O7
852 __ set(offset, O7);
853 store_offset = store(from_reg, base, O7, type);
854 } else {
855 if (type == T_ARRAY || type == T_OBJECT) __ verify_oop(from_reg->as_register());
856 store_offset = code_offset();
857 switch (type) {
858 case T_BOOLEAN: // fall through
859 case T_BYTE : __ stb(from_reg->as_register(), base, offset); break;
860 case T_CHAR : __ sth(from_reg->as_register(), base, offset); break;
861 case T_SHORT : __ sth(from_reg->as_register(), base, offset); break;
862 case T_INT : __ stw(from_reg->as_register(), base, offset); break;
863 case T_LONG :
864 #ifdef _LP64
865 if (unaligned || PatchALot) {
866 __ srax(from_reg->as_register_lo(), 32, O7);
867 __ stw(from_reg->as_register_lo(), base, offset + lo_word_offset_in_bytes);
868 __ stw(O7, base, offset + hi_word_offset_in_bytes);
869 } else {
870 __ stx(from_reg->as_register_lo(), base, offset);
871 }
872 #else
873 assert(Assembler::is_simm13(offset + 4), "must be");
874 __ stw(from_reg->as_register_lo(), base, offset + lo_word_offset_in_bytes);
875 __ stw(from_reg->as_register_hi(), base, offset + hi_word_offset_in_bytes);
876 #endif
877 break;
878 case T_ADDRESS:// fall through
879 case T_ARRAY : // fall through
880 case T_OBJECT: __ st_ptr(from_reg->as_register(), base, offset); break;
881 case T_FLOAT : __ stf(FloatRegisterImpl::S, from_reg->as_float_reg(), base, offset); break;
882 case T_DOUBLE:
883 {
884 FloatRegister reg = from_reg->as_double_reg();
885 // split unaligned stores
886 if (unaligned || PatchALot) {
887 assert(Assembler::is_simm13(offset + 4), "must be");
888 __ stf(FloatRegisterImpl::S, reg->successor(), base, offset + 4);
889 __ stf(FloatRegisterImpl::S, reg, base, offset);
890 } else {
891 __ stf(FloatRegisterImpl::D, reg, base, offset);
892 }
893 break;
894 }
895 default : ShouldNotReachHere();
896 }
897 }
898 return store_offset;
899 }
900
901
902 int LIR_Assembler::store(LIR_Opr from_reg, Register base, Register disp, BasicType type) {
903 if (type == T_ARRAY || type == T_OBJECT) __ verify_oop(from_reg->as_register());
904 int store_offset = code_offset();
905 switch (type) {
906 case T_BOOLEAN: // fall through
907 case T_BYTE : __ stb(from_reg->as_register(), base, disp); break;
908 case T_CHAR : __ sth(from_reg->as_register(), base, disp); break;
909 case T_SHORT : __ sth(from_reg->as_register(), base, disp); break;
910 case T_INT : __ stw(from_reg->as_register(), base, disp); break;
911 case T_LONG :
912 #ifdef _LP64
913 __ stx(from_reg->as_register_lo(), base, disp);
914 #else
915 assert(from_reg->as_register_hi()->successor() == from_reg->as_register_lo(), "must match");
916 __ std(from_reg->as_register_hi(), base, disp);
917 #endif
918 break;
919 case T_ADDRESS:// fall through
920 case T_ARRAY : // fall through
921 case T_OBJECT: __ st_ptr(from_reg->as_register(), base, disp); break;
922 case T_FLOAT : __ stf(FloatRegisterImpl::S, from_reg->as_float_reg(), base, disp); break;
923 case T_DOUBLE: __ stf(FloatRegisterImpl::D, from_reg->as_double_reg(), base, disp); break;
924 default : ShouldNotReachHere();
925 }
926 return store_offset;
927 }
928
929
930 int LIR_Assembler::load(Register base, int offset, LIR_Opr to_reg, BasicType type, bool unaligned) {
931 int load_offset;
932 if (!Assembler::is_simm13(offset + (type == T_LONG) ? wordSize : 0)) {
933 assert(base != O7, "destroying register");
934 assert(!unaligned, "can't handle this");
935 // for offsets larger than a simm13 we setup the offset in O7
936 __ set(offset, O7);
937 load_offset = load(base, O7, to_reg, type);
938 } else {
939 load_offset = code_offset();
940 switch(type) {
941 case T_BOOLEAN: // fall through
942 case T_BYTE : __ ldsb(base, offset, to_reg->as_register()); break;
943 case T_CHAR : __ lduh(base, offset, to_reg->as_register()); break;
944 case T_SHORT : __ ldsh(base, offset, to_reg->as_register()); break;
945 case T_INT : __ ld(base, offset, to_reg->as_register()); break;
946 case T_LONG :
947 if (!unaligned) {
948 #ifdef _LP64
949 __ ldx(base, offset, to_reg->as_register_lo());
950 #else
951 assert(to_reg->as_register_hi()->successor() == to_reg->as_register_lo(),
952 "must be sequential");
953 __ ldd(base, offset, to_reg->as_register_hi());
954 #endif
955 } else {
956 #ifdef _LP64
957 assert(base != to_reg->as_register_lo(), "can't handle this");
958 assert(O7 != to_reg->as_register_lo(), "can't handle this");
959 __ ld(base, offset + hi_word_offset_in_bytes, to_reg->as_register_lo());
960 __ lduw(base, offset + lo_word_offset_in_bytes, O7); // in case O7 is base or offset, use it last
961 __ sllx(to_reg->as_register_lo(), 32, to_reg->as_register_lo());
962 __ or3(to_reg->as_register_lo(), O7, to_reg->as_register_lo());
963 #else
964 if (base == to_reg->as_register_lo()) {
965 __ ld(base, offset + hi_word_offset_in_bytes, to_reg->as_register_hi());
966 __ ld(base, offset + lo_word_offset_in_bytes, to_reg->as_register_lo());
967 } else {
968 __ ld(base, offset + lo_word_offset_in_bytes, to_reg->as_register_lo());
969 __ ld(base, offset + hi_word_offset_in_bytes, to_reg->as_register_hi());
970 }
971 #endif
972 }
973 break;
974 case T_ADDRESS:// fall through
975 case T_ARRAY : // fall through
976 case T_OBJECT: __ ld_ptr(base, offset, to_reg->as_register()); break;
977 case T_FLOAT: __ ldf(FloatRegisterImpl::S, base, offset, to_reg->as_float_reg()); break;
978 case T_DOUBLE:
979 {
980 FloatRegister reg = to_reg->as_double_reg();
981 // split unaligned loads
982 if (unaligned || PatchALot) {
983 __ ldf(FloatRegisterImpl::S, base, offset + 4, reg->successor());
984 __ ldf(FloatRegisterImpl::S, base, offset, reg);
985 } else {
986 __ ldf(FloatRegisterImpl::D, base, offset, to_reg->as_double_reg());
987 }
988 break;
989 }
990 default : ShouldNotReachHere();
991 }
992 if (type == T_ARRAY || type == T_OBJECT) __ verify_oop(to_reg->as_register());
993 }
994 return load_offset;
995 }
996
997
998 int LIR_Assembler::load(Register base, Register disp, LIR_Opr to_reg, BasicType type) {
999 int load_offset = code_offset();
1000 switch(type) {
1001 case T_BOOLEAN: // fall through
1002 case T_BYTE : __ ldsb(base, disp, to_reg->as_register()); break;
1003 case T_CHAR : __ lduh(base, disp, to_reg->as_register()); break;
1004 case T_SHORT : __ ldsh(base, disp, to_reg->as_register()); break;
1005 case T_INT : __ ld(base, disp, to_reg->as_register()); break;
1006 case T_ADDRESS:// fall through
1007 case T_ARRAY : // fall through
1008 case T_OBJECT: __ ld_ptr(base, disp, to_reg->as_register()); break;
1009 case T_FLOAT: __ ldf(FloatRegisterImpl::S, base, disp, to_reg->as_float_reg()); break;
1010 case T_DOUBLE: __ ldf(FloatRegisterImpl::D, base, disp, to_reg->as_double_reg()); break;
1011 case T_LONG :
1012 #ifdef _LP64
1013 __ ldx(base, disp, to_reg->as_register_lo());
1014 #else
1015 assert(to_reg->as_register_hi()->successor() == to_reg->as_register_lo(),
1016 "must be sequential");
1017 __ ldd(base, disp, to_reg->as_register_hi());
1018 #endif
1019 break;
1020 default : ShouldNotReachHere();
1021 }
1022 if (type == T_ARRAY || type == T_OBJECT) __ verify_oop(to_reg->as_register());
1023 return load_offset;
1024 }
1025
1026
1027 // load/store with an Address
1028 void LIR_Assembler::load(const Address& a, Register d, BasicType ld_type, CodeEmitInfo *info, int offset) {
1029 load(a.base(), a.disp() + offset, d, ld_type, info);
1030 }
1031
1032
1033 void LIR_Assembler::store(Register value, const Address& dest, BasicType type, CodeEmitInfo *info, int offset) {
1034 store(value, dest.base(), dest.disp() + offset, type, info);
1035 }
1036
1037
1038 // loadf/storef with an Address
1039 void LIR_Assembler::load(const Address& a, FloatRegister d, BasicType ld_type, CodeEmitInfo *info, int offset) {
1040 load(a.base(), a.disp() + offset, d, ld_type, info);
1041 }
1042
1043
1044 void LIR_Assembler::store(FloatRegister value, const Address& dest, BasicType type, CodeEmitInfo *info, int offset) {
1045 store(value, dest.base(), dest.disp() + offset, type, info);
1046 }
1047
1048
1049 // load/store with an Address
1050 void LIR_Assembler::load(LIR_Address* a, Register d, BasicType ld_type, CodeEmitInfo *info) {
1051 load(as_Address(a), d, ld_type, info);
1052 }
1053
1054
1055 void LIR_Assembler::store(Register value, LIR_Address* dest, BasicType type, CodeEmitInfo *info) {
1056 store(value, as_Address(dest), type, info);
1057 }
1058
1059
1060 // loadf/storef with an Address
1061 void LIR_Assembler::load(LIR_Address* a, FloatRegister d, BasicType ld_type, CodeEmitInfo *info) {
1062 load(as_Address(a), d, ld_type, info);
1063 }
1064
1065
1066 void LIR_Assembler::store(FloatRegister value, LIR_Address* dest, BasicType type, CodeEmitInfo *info) {
1067 store(value, as_Address(dest), type, info);
1068 }
1069
1070
1071 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
1072 LIR_Const* c = src->as_constant_ptr();
1073 switch (c->type()) {
1074 case T_INT:
1075 case T_FLOAT: {
1076 Register src_reg = O7;
1077 int value = c->as_jint_bits();
1078 if (value == 0) {
1079 src_reg = G0;
1080 } else {
1081 __ set(value, O7);
1082 }
1083 Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
1084 __ stw(src_reg, addr.base(), addr.disp());
1085 break;
1086 }
1087 case T_OBJECT: {
1088 Register src_reg = O7;
1089 jobject2reg(c->as_jobject(), src_reg);
1090 Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
1091 __ st_ptr(src_reg, addr.base(), addr.disp());
1092 break;
1093 }
1094 case T_LONG:
1095 case T_DOUBLE: {
1096 Address addr = frame_map()->address_for_double_slot(dest->double_stack_ix());
1097
1098 Register tmp = O7;
1099 int value_lo = c->as_jint_lo_bits();
1100 if (value_lo == 0) {
1101 tmp = G0;
1102 } else {
1103 __ set(value_lo, O7);
1104 }
1105 __ stw(tmp, addr.base(), addr.disp() + lo_word_offset_in_bytes);
1106 int value_hi = c->as_jint_hi_bits();
1107 if (value_hi == 0) {
1108 tmp = G0;
1109 } else {
1110 __ set(value_hi, O7);
1111 }
1112 __ stw(tmp, addr.base(), addr.disp() + hi_word_offset_in_bytes);
1113 break;
1114 }
1115 default:
1116 Unimplemented();
1117 }
1118 }
1119
1120
1121 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info ) {
1122 LIR_Const* c = src->as_constant_ptr();
1123 LIR_Address* addr = dest->as_address_ptr();
1124 Register base = addr->base()->as_pointer_register();
1125
1126 if (info != NULL) {
1127 add_debug_info_for_null_check_here(info);
1128 }
1129 switch (c->type()) {
1130 case T_INT:
1131 case T_FLOAT: {
1132 LIR_Opr tmp = FrameMap::O7_opr;
1133 int value = c->as_jint_bits();
1134 if (value == 0) {
1135 tmp = FrameMap::G0_opr;
1136 } else if (Assembler::is_simm13(value)) {
1137 __ set(value, O7);
1138 }
1139 if (addr->index()->is_valid()) {
1140 assert(addr->disp() == 0, "must be zero");
1141 store(tmp, base, addr->index()->as_pointer_register(), type);
1142 } else {
1143 assert(Assembler::is_simm13(addr->disp()), "can't handle larger addresses");
1144 store(tmp, base, addr->disp(), type);
1145 }
1146 break;
1147 }
1148 case T_LONG:
1149 case T_DOUBLE: {
1150 assert(!addr->index()->is_valid(), "can't handle reg reg address here");
1151 assert(Assembler::is_simm13(addr->disp()) &&
1152 Assembler::is_simm13(addr->disp() + 4), "can't handle larger addresses");
1153
1154 Register tmp = O7;
1155 int value_lo = c->as_jint_lo_bits();
1156 if (value_lo == 0) {
1157 tmp = G0;
1158 } else {
1159 __ set(value_lo, O7);
1160 }
1161 store(tmp, base, addr->disp() + lo_word_offset_in_bytes, T_INT);
1162 int value_hi = c->as_jint_hi_bits();
1163 if (value_hi == 0) {
1164 tmp = G0;
1165 } else {
1166 __ set(value_hi, O7);
1167 }
1168 store(tmp, base, addr->disp() + hi_word_offset_in_bytes, T_INT);
1169 break;
1170 }
1171 case T_OBJECT: {
1172 jobject obj = c->as_jobject();
1173 LIR_Opr tmp;
1174 if (obj == NULL) {
1175 tmp = FrameMap::G0_opr;
1176 } else {
1177 tmp = FrameMap::O7_opr;
1178 jobject2reg(c->as_jobject(), O7);
1179 }
1180 // handle either reg+reg or reg+disp address
1181 if (addr->index()->is_valid()) {
1182 assert(addr->disp() == 0, "must be zero");
1183 store(tmp, base, addr->index()->as_pointer_register(), type);
1184 } else {
1185 assert(Assembler::is_simm13(addr->disp()), "can't handle larger addresses");
1186 store(tmp, base, addr->disp(), type);
1187 }
1188
1189 break;
1190 }
1191 default:
1192 Unimplemented();
1193 }
1194 }
1195
1196
1197 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
1198 LIR_Const* c = src->as_constant_ptr();
1199 LIR_Opr to_reg = dest;
1200
1201 switch (c->type()) {
1202 case T_INT:
1203 {
1204 jint con = c->as_jint();
1205 if (to_reg->is_single_cpu()) {
1206 assert(patch_code == lir_patch_none, "no patching handled here");
1207 __ set(con, to_reg->as_register());
1208 } else {
1209 ShouldNotReachHere();
1210 assert(to_reg->is_single_fpu(), "wrong register kind");
1211
1212 __ set(con, O7);
1213 Address temp_slot(SP, (frame::register_save_words * wordSize) + STACK_BIAS);
1214 __ st(O7, temp_slot);
1215 __ ldf(FloatRegisterImpl::S, temp_slot, to_reg->as_float_reg());
1216 }
1217 }
1218 break;
1219
1220 case T_LONG:
1221 {
1222 jlong con = c->as_jlong();
1223
1224 if (to_reg->is_double_cpu()) {
1225 #ifdef _LP64
1226 __ set(con, to_reg->as_register_lo());
1227 #else
1228 __ set(low(con), to_reg->as_register_lo());
1229 __ set(high(con), to_reg->as_register_hi());
1230 #endif
1231 #ifdef _LP64
1232 } else if (to_reg->is_single_cpu()) {
1233 __ set(con, to_reg->as_register());
1234 #endif
1235 } else {
1236 ShouldNotReachHere();
1237 assert(to_reg->is_double_fpu(), "wrong register kind");
1238 Address temp_slot_lo(SP, ((frame::register_save_words ) * wordSize) + STACK_BIAS);
1239 Address temp_slot_hi(SP, ((frame::register_save_words) * wordSize) + (longSize/2) + STACK_BIAS);
1240 __ set(low(con), O7);
1241 __ st(O7, temp_slot_lo);
1242 __ set(high(con), O7);
1243 __ st(O7, temp_slot_hi);
1244 __ ldf(FloatRegisterImpl::D, temp_slot_lo, to_reg->as_double_reg());
1245 }
1246 }
1247 break;
1248
1249 case T_OBJECT:
1250 {
1251 if (patch_code == lir_patch_none) {
1252 jobject2reg(c->as_jobject(), to_reg->as_register());
1253 } else {
1254 jobject2reg_with_patching(to_reg->as_register(), info);
1255 }
1256 }
1257 break;
1258
1259 case T_FLOAT:
1260 {
1261 address const_addr = __ float_constant(c->as_jfloat());
1262 if (const_addr == NULL) {
1263 bailout("const section overflow");
1264 break;
1265 }
1266 RelocationHolder rspec = internal_word_Relocation::spec(const_addr);
1267 AddressLiteral const_addrlit(const_addr, rspec);
1268 if (to_reg->is_single_fpu()) {
1269 __ patchable_sethi(const_addrlit, O7);
1270 __ relocate(rspec);
1271 __ ldf(FloatRegisterImpl::S, O7, const_addrlit.low10(), to_reg->as_float_reg());
1272
1273 } else {
1274 assert(to_reg->is_single_cpu(), "Must be a cpu register.");
1275
1276 __ set(const_addrlit, O7);
1277 load(O7, 0, to_reg->as_register(), T_INT);
1278 }
1279 }
1280 break;
1281
1282 case T_DOUBLE:
1283 {
1284 address const_addr = __ double_constant(c->as_jdouble());
1285 if (const_addr == NULL) {
1286 bailout("const section overflow");
1287 break;
1288 }
1289 RelocationHolder rspec = internal_word_Relocation::spec(const_addr);
1290
1291 if (to_reg->is_double_fpu()) {
1292 AddressLiteral const_addrlit(const_addr, rspec);
1293 __ patchable_sethi(const_addrlit, O7);
1294 __ relocate(rspec);
1295 __ ldf (FloatRegisterImpl::D, O7, const_addrlit.low10(), to_reg->as_double_reg());
1296 } else {
1297 assert(to_reg->is_double_cpu(), "Must be a long register.");
1298 #ifdef _LP64
1299 __ set(jlong_cast(c->as_jdouble()), to_reg->as_register_lo());
1300 #else
1301 __ set(low(jlong_cast(c->as_jdouble())), to_reg->as_register_lo());
1302 __ set(high(jlong_cast(c->as_jdouble())), to_reg->as_register_hi());
1303 #endif
1304 }
1305
1306 }
1307 break;
1308
1309 default:
1310 ShouldNotReachHere();
1311 }
1312 }
1313
1314 Address LIR_Assembler::as_Address(LIR_Address* addr) {
1315 Register reg = addr->base()->as_register();
1316 return Address(reg, addr->disp());
1317 }
1318
1319
1320 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
1321 switch (type) {
1322 case T_INT:
1323 case T_FLOAT: {
1324 Register tmp = O7;
1325 Address from = frame_map()->address_for_slot(src->single_stack_ix());
1326 Address to = frame_map()->address_for_slot(dest->single_stack_ix());
1327 __ lduw(from.base(), from.disp(), tmp);
1328 __ stw(tmp, to.base(), to.disp());
1329 break;
1330 }
1331 case T_OBJECT: {
1332 Register tmp = O7;
1333 Address from = frame_map()->address_for_slot(src->single_stack_ix());
1334 Address to = frame_map()->address_for_slot(dest->single_stack_ix());
1335 __ ld_ptr(from.base(), from.disp(), tmp);
1336 __ st_ptr(tmp, to.base(), to.disp());
1337 break;
1338 }
1339 case T_LONG:
1340 case T_DOUBLE: {
1341 Register tmp = O7;
1342 Address from = frame_map()->address_for_double_slot(src->double_stack_ix());
1343 Address to = frame_map()->address_for_double_slot(dest->double_stack_ix());
1344 __ lduw(from.base(), from.disp(), tmp);
1345 __ stw(tmp, to.base(), to.disp());
1346 __ lduw(from.base(), from.disp() + 4, tmp);
1347 __ stw(tmp, to.base(), to.disp() + 4);
1348 break;
1349 }
1350
1351 default:
1352 ShouldNotReachHere();
1353 }
1354 }
1355
1356
1357 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
1358 Address base = as_Address(addr);
1359 return Address(base.base(), base.disp() + hi_word_offset_in_bytes);
1360 }
1361
1362
1363 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
1364 Address base = as_Address(addr);
1365 return Address(base.base(), base.disp() + lo_word_offset_in_bytes);
1366 }
1367
1368
1369 void LIR_Assembler::mem2reg(LIR_Opr src_opr, LIR_Opr dest, BasicType type,
1370 LIR_PatchCode patch_code, CodeEmitInfo* info, bool unaligned) {
1371
1372 LIR_Address* addr = src_opr->as_address_ptr();
1373 LIR_Opr to_reg = dest;
1374
1375 Register src = addr->base()->as_pointer_register();
1376 Register disp_reg = noreg;
1377 int disp_value = addr->disp();
1378 bool needs_patching = (patch_code != lir_patch_none);
1379
1380 if (addr->base()->type() == T_OBJECT) {
1381 __ verify_oop(src);
1382 }
1383
1384 PatchingStub* patch = NULL;
1385 if (needs_patching) {
1386 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1387 assert(!to_reg->is_double_cpu() ||
1388 patch_code == lir_patch_none ||
1389 patch_code == lir_patch_normal, "patching doesn't match register");
1390 }
1391
1392 if (addr->index()->is_illegal()) {
1393 if (!Assembler::is_simm13(disp_value) && (!unaligned || Assembler::is_simm13(disp_value + 4))) {
1394 if (needs_patching) {
1395 __ patchable_set(0, O7);
1396 } else {
1397 __ set(disp_value, O7);
1398 }
1399 disp_reg = O7;
1400 }
1401 } else if (unaligned || PatchALot) {
1402 __ add(src, addr->index()->as_register(), O7);
1403 src = O7;
1404 } else {
1405 disp_reg = addr->index()->as_pointer_register();
1406 assert(disp_value == 0, "can't handle 3 operand addresses");
1407 }
1408
1409 // remember the offset of the load. The patching_epilog must be done
1410 // before the call to add_debug_info, otherwise the PcDescs don't get
1411 // entered in increasing order.
1412 int offset = code_offset();
1413
1414 assert(disp_reg != noreg || Assembler::is_simm13(disp_value), "should have set this up");
1415 if (disp_reg == noreg) {
1416 offset = load(src, disp_value, to_reg, type, unaligned);
1417 } else {
1418 assert(!unaligned, "can't handle this");
1419 offset = load(src, disp_reg, to_reg, type);
1420 }
1421
1422 if (patch != NULL) {
1423 patching_epilog(patch, patch_code, src, info);
1424 }
1425
1426 if (info != NULL) add_debug_info_for_null_check(offset, info);
1427 }
1428
1429
1430 void LIR_Assembler::prefetchr(LIR_Opr src) {
1431 LIR_Address* addr = src->as_address_ptr();
1432 Address from_addr = as_Address(addr);
1433
1434 if (VM_Version::has_v9()) {
1435 __ prefetch(from_addr, Assembler::severalReads);
1436 }
1437 }
1438
1439
1440 void LIR_Assembler::prefetchw(LIR_Opr src) {
1441 LIR_Address* addr = src->as_address_ptr();
1442 Address from_addr = as_Address(addr);
1443
1444 if (VM_Version::has_v9()) {
1445 __ prefetch(from_addr, Assembler::severalWritesAndPossiblyReads);
1446 }
1447 }
1448
1449
1450 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
1451 Address addr;
1452 if (src->is_single_word()) {
1453 addr = frame_map()->address_for_slot(src->single_stack_ix());
1454 } else if (src->is_double_word()) {
1455 addr = frame_map()->address_for_double_slot(src->double_stack_ix());
1456 }
1457
1458 bool unaligned = (addr.disp() - STACK_BIAS) % 8 != 0;
1459 load(addr.base(), addr.disp(), dest, dest->type(), unaligned);
1460 }
1461
1462
1463 void LIR_Assembler::reg2stack(LIR_Opr from_reg, LIR_Opr dest, BasicType type, bool pop_fpu_stack) {
1464 Address addr;
1465 if (dest->is_single_word()) {
1466 addr = frame_map()->address_for_slot(dest->single_stack_ix());
1467 } else if (dest->is_double_word()) {
1468 addr = frame_map()->address_for_slot(dest->double_stack_ix());
1469 }
1470 bool unaligned = (addr.disp() - STACK_BIAS) % 8 != 0;
1471 store(from_reg, addr.base(), addr.disp(), from_reg->type(), unaligned);
1472 }
1473
1474
1475 void LIR_Assembler::reg2reg(LIR_Opr from_reg, LIR_Opr to_reg) {
1476 if (from_reg->is_float_kind() && to_reg->is_float_kind()) {
1477 if (from_reg->is_double_fpu()) {
1478 // double to double moves
1479 assert(to_reg->is_double_fpu(), "should match");
1480 __ fmov(FloatRegisterImpl::D, from_reg->as_double_reg(), to_reg->as_double_reg());
1481 } else {
1482 // float to float moves
1483 assert(to_reg->is_single_fpu(), "should match");
1484 __ fmov(FloatRegisterImpl::S, from_reg->as_float_reg(), to_reg->as_float_reg());
1485 }
1486 } else if (!from_reg->is_float_kind() && !to_reg->is_float_kind()) {
1487 if (from_reg->is_double_cpu()) {
1488 #ifdef _LP64
1489 __ mov(from_reg->as_pointer_register(), to_reg->as_pointer_register());
1490 #else
1491 assert(to_reg->is_double_cpu() &&
1492 from_reg->as_register_hi() != to_reg->as_register_lo() &&
1493 from_reg->as_register_lo() != to_reg->as_register_hi(),
1494 "should both be long and not overlap");
1495 // long to long moves
1496 __ mov(from_reg->as_register_hi(), to_reg->as_register_hi());
1497 __ mov(from_reg->as_register_lo(), to_reg->as_register_lo());
1498 #endif
1499 #ifdef _LP64
1500 } else if (to_reg->is_double_cpu()) {
1501 // int to int moves
1502 __ mov(from_reg->as_register(), to_reg->as_register_lo());
1503 #endif
1504 } else {
1505 // int to int moves
1506 __ mov(from_reg->as_register(), to_reg->as_register());
1507 }
1508 } else {
1509 ShouldNotReachHere();
1510 }
1511 if (to_reg->type() == T_OBJECT || to_reg->type() == T_ARRAY) {
1512 __ verify_oop(to_reg->as_register());
1513 }
1514 }
1515
1516
1517 void LIR_Assembler::reg2mem(LIR_Opr from_reg, LIR_Opr dest, BasicType type,
1518 LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack,
1519 bool unaligned) {
1520 LIR_Address* addr = dest->as_address_ptr();
1521
1522 Register src = addr->base()->as_pointer_register();
1523 Register disp_reg = noreg;
1524 int disp_value = addr->disp();
1525 bool needs_patching = (patch_code != lir_patch_none);
1526
1527 if (addr->base()->is_oop_register()) {
1528 __ verify_oop(src);
1529 }
1530
1531 PatchingStub* patch = NULL;
1532 if (needs_patching) {
1533 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1534 assert(!from_reg->is_double_cpu() ||
1535 patch_code == lir_patch_none ||
1536 patch_code == lir_patch_normal, "patching doesn't match register");
1537 }
1538
1539 if (addr->index()->is_illegal()) {
1540 if (!Assembler::is_simm13(disp_value) && (!unaligned || Assembler::is_simm13(disp_value + 4))) {
1541 if (needs_patching) {
1542 __ patchable_set(0, O7);
1543 } else {
1544 __ set(disp_value, O7);
1545 }
1546 disp_reg = O7;
1547 }
1548 } else if (unaligned || PatchALot) {
1549 __ add(src, addr->index()->as_register(), O7);
1550 src = O7;
1551 } else {
1552 disp_reg = addr->index()->as_pointer_register();
1553 assert(disp_value == 0, "can't handle 3 operand addresses");
1554 }
1555
1556 // remember the offset of the store. The patching_epilog must be done
1557 // before the call to add_debug_info_for_null_check, otherwise the PcDescs don't get
1558 // entered in increasing order.
1559 int offset;
1560
1561 assert(disp_reg != noreg || Assembler::is_simm13(disp_value), "should have set this up");
1562 if (disp_reg == noreg) {
1563 offset = store(from_reg, src, disp_value, type, unaligned);
1564 } else {
1565 assert(!unaligned, "can't handle this");
1566 offset = store(from_reg, src, disp_reg, type);
1567 }
1568
1569 if (patch != NULL) {
1570 patching_epilog(patch, patch_code, src, info);
1571 }
1572
1573 if (info != NULL) add_debug_info_for_null_check(offset, info);
1574 }
1575
1576
1577 void LIR_Assembler::return_op(LIR_Opr result) {
1578 // the poll may need a register so just pick one that isn't the return register
1579 #ifdef TIERED
1580 if (result->type_field() == LIR_OprDesc::long_type) {
1581 // Must move the result to G1
1582 // Must leave proper result in O0,O1 and G1 (TIERED only)
1583 __ sllx(I0, 32, G1); // Shift bits into high G1
1584 __ srl (I1, 0, I1); // Zero extend O1 (harmless?)
1585 __ or3 (I1, G1, G1); // OR 64 bits into G1
1586 }
1587 #endif // TIERED
1588 __ set((intptr_t)os::get_polling_page(), L0);
1589 __ relocate(relocInfo::poll_return_type);
1590 __ ld_ptr(L0, 0, G0);
1591 __ ret();
1592 __ delayed()->restore();
1593 }
1594
1595
1596 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
1597 __ set((intptr_t)os::get_polling_page(), tmp->as_register());
1598 if (info != NULL) {
1599 add_debug_info_for_branch(info);
1600 } else {
1601 __ relocate(relocInfo::poll_type);
1602 }
1603
1604 int offset = __ offset();
1605 __ ld_ptr(tmp->as_register(), 0, G0);
1606
1607 return offset;
1608 }
1609
1610
1611 void LIR_Assembler::emit_static_call_stub() {
1612 address call_pc = __ pc();
1613 address stub = __ start_a_stub(call_stub_size);
1614 if (stub == NULL) {
1615 bailout("static call stub overflow");
1616 return;
1617 }
1618
1619 int start = __ offset();
1620 __ relocate(static_stub_Relocation::spec(call_pc));
1621
1622 __ set_oop(NULL, G5);
1623 // must be set to -1 at code generation time
1624 AddressLiteral addrlit(-1);
1625 __ jump_to(addrlit, G3);
1626 __ delayed()->nop();
1627
1628 assert(__ offset() - start <= call_stub_size, "stub too big");
1629 __ end_a_stub();
1630 }
1631
1632
1633 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
1634 if (opr1->is_single_fpu()) {
1635 __ fcmp(FloatRegisterImpl::S, Assembler::fcc0, opr1->as_float_reg(), opr2->as_float_reg());
1636 } else if (opr1->is_double_fpu()) {
1637 __ fcmp(FloatRegisterImpl::D, Assembler::fcc0, opr1->as_double_reg(), opr2->as_double_reg());
1638 } else if (opr1->is_single_cpu()) {
1639 if (opr2->is_constant()) {
1640 switch (opr2->as_constant_ptr()->type()) {
1641 case T_INT:
1642 { jint con = opr2->as_constant_ptr()->as_jint();
1643 if (Assembler::is_simm13(con)) {
1644 __ cmp(opr1->as_register(), con);
1645 } else {
1646 __ set(con, O7);
1647 __ cmp(opr1->as_register(), O7);
1648 }
1649 }
1650 break;
1651
1652 case T_OBJECT:
1653 // there are only equal/notequal comparisions on objects
1654 { jobject con = opr2->as_constant_ptr()->as_jobject();
1655 if (con == NULL) {
1656 __ cmp(opr1->as_register(), 0);
1657 } else {
1658 jobject2reg(con, O7);
1659 __ cmp(opr1->as_register(), O7);
1660 }
1661 }
1662 break;
1663
1664 default:
1665 ShouldNotReachHere();
1666 break;
1667 }
1668 } else {
1669 if (opr2->is_address()) {
1670 LIR_Address * addr = opr2->as_address_ptr();
1671 BasicType type = addr->type();
1672 if ( type == T_OBJECT ) __ ld_ptr(as_Address(addr), O7);
1673 else __ ld(as_Address(addr), O7);
1674 __ cmp(opr1->as_register(), O7);
1675 } else {
1676 __ cmp(opr1->as_register(), opr2->as_register());
1677 }
1678 }
1679 } else if (opr1->is_double_cpu()) {
1680 Register xlo = opr1->as_register_lo();
1681 Register xhi = opr1->as_register_hi();
1682 if (opr2->is_constant() && opr2->as_jlong() == 0) {
1683 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "only handles these cases");
1684 #ifdef _LP64
1685 __ orcc(xhi, G0, G0);
1686 #else
1687 __ orcc(xhi, xlo, G0);
1688 #endif
1689 } else if (opr2->is_register()) {
1690 Register ylo = opr2->as_register_lo();
1691 Register yhi = opr2->as_register_hi();
1692 #ifdef _LP64
1693 __ cmp(xlo, ylo);
1694 #else
1695 __ subcc(xlo, ylo, xlo);
1696 __ subccc(xhi, yhi, xhi);
1697 if (condition == lir_cond_equal || condition == lir_cond_notEqual) {
1698 __ orcc(xhi, xlo, G0);
1699 }
1700 #endif
1701 } else {
1702 ShouldNotReachHere();
1703 }
1704 } else if (opr1->is_address()) {
1705 LIR_Address * addr = opr1->as_address_ptr();
1706 BasicType type = addr->type();
1707 assert (opr2->is_constant(), "Checking");
1708 if ( type == T_OBJECT ) __ ld_ptr(as_Address(addr), O7);
1709 else __ ld(as_Address(addr), O7);
1710 __ cmp(O7, opr2->as_constant_ptr()->as_jint());
1711 } else {
1712 ShouldNotReachHere();
1713 }
1714 }
1715
1716
1717 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op){
1718 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
1719 bool is_unordered_less = (code == lir_ucmp_fd2i);
1720 if (left->is_single_fpu()) {
1721 __ float_cmp(true, is_unordered_less ? -1 : 1, left->as_float_reg(), right->as_float_reg(), dst->as_register());
1722 } else if (left->is_double_fpu()) {
1723 __ float_cmp(false, is_unordered_less ? -1 : 1, left->as_double_reg(), right->as_double_reg(), dst->as_register());
1724 } else {
1725 ShouldNotReachHere();
1726 }
1727 } else if (code == lir_cmp_l2i) {
1728 __ lcmp(left->as_register_hi(), left->as_register_lo(),
1729 right->as_register_hi(), right->as_register_lo(),
1730 dst->as_register());
1731 } else {
1732 ShouldNotReachHere();
1733 }
1734 }
1735
1736
1737 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result) {
1738
1739 Assembler::Condition acond;
1740 switch (condition) {
1741 case lir_cond_equal: acond = Assembler::equal; break;
1742 case lir_cond_notEqual: acond = Assembler::notEqual; break;
1743 case lir_cond_less: acond = Assembler::less; break;
1744 case lir_cond_lessEqual: acond = Assembler::lessEqual; break;
1745 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; break;
1746 case lir_cond_greater: acond = Assembler::greater; break;
1747 case lir_cond_aboveEqual: acond = Assembler::greaterEqualUnsigned; break;
1748 case lir_cond_belowEqual: acond = Assembler::lessEqualUnsigned; break;
1749 default: ShouldNotReachHere();
1750 };
1751
1752 if (opr1->is_constant() && opr1->type() == T_INT) {
1753 Register dest = result->as_register();
1754 // load up first part of constant before branch
1755 // and do the rest in the delay slot.
1756 if (!Assembler::is_simm13(opr1->as_jint())) {
1757 __ sethi(opr1->as_jint(), dest);
1758 }
1759 } else if (opr1->is_constant()) {
1760 const2reg(opr1, result, lir_patch_none, NULL);
1761 } else if (opr1->is_register()) {
1762 reg2reg(opr1, result);
1763 } else if (opr1->is_stack()) {
1764 stack2reg(opr1, result, result->type());
1765 } else {
1766 ShouldNotReachHere();
1767 }
1768 Label skip;
1769 __ br(acond, false, Assembler::pt, skip);
1770 if (opr1->is_constant() && opr1->type() == T_INT) {
1771 Register dest = result->as_register();
1772 if (Assembler::is_simm13(opr1->as_jint())) {
1773 __ delayed()->or3(G0, opr1->as_jint(), dest);
1774 } else {
1775 // the sethi has been done above, so just put in the low 10 bits
1776 __ delayed()->or3(dest, opr1->as_jint() & 0x3ff, dest);
1777 }
1778 } else {
1779 // can't do anything useful in the delay slot
1780 __ delayed()->nop();
1781 }
1782 if (opr2->is_constant()) {
1783 const2reg(opr2, result, lir_patch_none, NULL);
1784 } else if (opr2->is_register()) {
1785 reg2reg(opr2, result);
1786 } else if (opr2->is_stack()) {
1787 stack2reg(opr2, result, result->type());
1788 } else {
1789 ShouldNotReachHere();
1790 }
1791 __ bind(skip);
1792 }
1793
1794
1795 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) {
1796 assert(info == NULL, "unused on this code path");
1797 assert(left->is_register(), "wrong items state");
1798 assert(dest->is_register(), "wrong items state");
1799
1800 if (right->is_register()) {
1801 if (dest->is_float_kind()) {
1802
1803 FloatRegister lreg, rreg, res;
1804 FloatRegisterImpl::Width w;
1805 if (right->is_single_fpu()) {
1806 w = FloatRegisterImpl::S;
1807 lreg = left->as_float_reg();
1808 rreg = right->as_float_reg();
1809 res = dest->as_float_reg();
1810 } else {
1811 w = FloatRegisterImpl::D;
1812 lreg = left->as_double_reg();
1813 rreg = right->as_double_reg();
1814 res = dest->as_double_reg();
1815 }
1816
1817 switch (code) {
1818 case lir_add: __ fadd(w, lreg, rreg, res); break;
1819 case lir_sub: __ fsub(w, lreg, rreg, res); break;
1820 case lir_mul: // fall through
1821 case lir_mul_strictfp: __ fmul(w, lreg, rreg, res); break;
1822 case lir_div: // fall through
1823 case lir_div_strictfp: __ fdiv(w, lreg, rreg, res); break;
1824 default: ShouldNotReachHere();
1825 }
1826
1827 } else if (dest->is_double_cpu()) {
1828 #ifdef _LP64
1829 Register dst_lo = dest->as_register_lo();
1830 Register op1_lo = left->as_pointer_register();
1831 Register op2_lo = right->as_pointer_register();
1832
1833 switch (code) {
1834 case lir_add:
1835 __ add(op1_lo, op2_lo, dst_lo);
1836 break;
1837
1838 case lir_sub:
1839 __ sub(op1_lo, op2_lo, dst_lo);
1840 break;
1841
1842 default: ShouldNotReachHere();
1843 }
1844 #else
1845 Register op1_lo = left->as_register_lo();
1846 Register op1_hi = left->as_register_hi();
1847 Register op2_lo = right->as_register_lo();
1848 Register op2_hi = right->as_register_hi();
1849 Register dst_lo = dest->as_register_lo();
1850 Register dst_hi = dest->as_register_hi();
1851
1852 switch (code) {
1853 case lir_add:
1854 __ addcc(op1_lo, op2_lo, dst_lo);
1855 __ addc (op1_hi, op2_hi, dst_hi);
1856 break;
1857
1858 case lir_sub:
1859 __ subcc(op1_lo, op2_lo, dst_lo);
1860 __ subc (op1_hi, op2_hi, dst_hi);
1861 break;
1862
1863 default: ShouldNotReachHere();
1864 }
1865 #endif
1866 } else {
1867 assert (right->is_single_cpu(), "Just Checking");
1868
1869 Register lreg = left->as_register();
1870 Register res = dest->as_register();
1871 Register rreg = right->as_register();
1872 switch (code) {
1873 case lir_add: __ add (lreg, rreg, res); break;
1874 case lir_sub: __ sub (lreg, rreg, res); break;
1875 case lir_mul: __ mult (lreg, rreg, res); break;
1876 default: ShouldNotReachHere();
1877 }
1878 }
1879 } else {
1880 assert (right->is_constant(), "must be constant");
1881
1882 if (dest->is_single_cpu()) {
1883 Register lreg = left->as_register();
1884 Register res = dest->as_register();
1885 int simm13 = right->as_constant_ptr()->as_jint();
1886
1887 switch (code) {
1888 case lir_add: __ add (lreg, simm13, res); break;
1889 case lir_sub: __ sub (lreg, simm13, res); break;
1890 case lir_mul: __ mult (lreg, simm13, res); break;
1891 default: ShouldNotReachHere();
1892 }
1893 } else {
1894 Register lreg = left->as_pointer_register();
1895 Register res = dest->as_register_lo();
1896 long con = right->as_constant_ptr()->as_jlong();
1897 assert(Assembler::is_simm13(con), "must be simm13");
1898
1899 switch (code) {
1900 case lir_add: __ add (lreg, (int)con, res); break;
1901 case lir_sub: __ sub (lreg, (int)con, res); break;
1902 case lir_mul: __ mult (lreg, (int)con, res); break;
1903 default: ShouldNotReachHere();
1904 }
1905 }
1906 }
1907 }
1908
1909
1910 void LIR_Assembler::fpop() {
1911 // do nothing
1912 }
1913
1914
1915 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr thread, LIR_Opr dest, LIR_Op* op) {
1916 switch (code) {
1917 case lir_sin:
1918 case lir_tan:
1919 case lir_cos: {
1920 assert(thread->is_valid(), "preserve the thread object for performance reasons");
1921 assert(dest->as_double_reg() == F0, "the result will be in f0/f1");
1922 break;
1923 }
1924 case lir_sqrt: {
1925 assert(!thread->is_valid(), "there is no need for a thread_reg for dsqrt");
1926 FloatRegister src_reg = value->as_double_reg();
1927 FloatRegister dst_reg = dest->as_double_reg();
1928 __ fsqrt(FloatRegisterImpl::D, src_reg, dst_reg);
1929 break;
1930 }
1931 case lir_abs: {
1932 assert(!thread->is_valid(), "there is no need for a thread_reg for fabs");
1933 FloatRegister src_reg = value->as_double_reg();
1934 FloatRegister dst_reg = dest->as_double_reg();
1935 __ fabs(FloatRegisterImpl::D, src_reg, dst_reg);
1936 break;
1937 }
1938 default: {
1939 ShouldNotReachHere();
1940 break;
1941 }
1942 }
1943 }
1944
1945
1946 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest) {
1947 if (right->is_constant()) {
1948 if (dest->is_single_cpu()) {
1949 int simm13 = right->as_constant_ptr()->as_jint();
1950 switch (code) {
1951 case lir_logic_and: __ and3 (left->as_register(), simm13, dest->as_register()); break;
1952 case lir_logic_or: __ or3 (left->as_register(), simm13, dest->as_register()); break;
1953 case lir_logic_xor: __ xor3 (left->as_register(), simm13, dest->as_register()); break;
1954 default: ShouldNotReachHere();
1955 }
1956 } else {
1957 long c = right->as_constant_ptr()->as_jlong();
1958 assert(c == (int)c && Assembler::is_simm13(c), "out of range");
1959 int simm13 = (int)c;
1960 switch (code) {
1961 case lir_logic_and:
1962 #ifndef _LP64
1963 __ and3 (left->as_register_hi(), 0, dest->as_register_hi());
1964 #endif
1965 __ and3 (left->as_register_lo(), simm13, dest->as_register_lo());
1966 break;
1967
1968 case lir_logic_or:
1969 #ifndef _LP64
1970 __ or3 (left->as_register_hi(), 0, dest->as_register_hi());
1971 #endif
1972 __ or3 (left->as_register_lo(), simm13, dest->as_register_lo());
1973 break;
1974
1975 case lir_logic_xor:
1976 #ifndef _LP64
1977 __ xor3 (left->as_register_hi(), 0, dest->as_register_hi());
1978 #endif
1979 __ xor3 (left->as_register_lo(), simm13, dest->as_register_lo());
1980 break;
1981
1982 default: ShouldNotReachHere();
1983 }
1984 }
1985 } else {
1986 assert(right->is_register(), "right should be in register");
1987
1988 if (dest->is_single_cpu()) {
1989 switch (code) {
1990 case lir_logic_and: __ and3 (left->as_register(), right->as_register(), dest->as_register()); break;
1991 case lir_logic_or: __ or3 (left->as_register(), right->as_register(), dest->as_register()); break;
1992 case lir_logic_xor: __ xor3 (left->as_register(), right->as_register(), dest->as_register()); break;
1993 default: ShouldNotReachHere();
1994 }
1995 } else {
1996 #ifdef _LP64
1997 Register l = (left->is_single_cpu() && left->is_oop_register()) ? left->as_register() :
1998 left->as_register_lo();
1999 Register r = (right->is_single_cpu() && right->is_oop_register()) ? right->as_register() :
2000 right->as_register_lo();
2001
2002 switch (code) {
2003 case lir_logic_and: __ and3 (l, r, dest->as_register_lo()); break;
2004 case lir_logic_or: __ or3 (l, r, dest->as_register_lo()); break;
2005 case lir_logic_xor: __ xor3 (l, r, dest->as_register_lo()); break;
2006 default: ShouldNotReachHere();
2007 }
2008 #else
2009 switch (code) {
2010 case lir_logic_and:
2011 __ and3 (left->as_register_hi(), right->as_register_hi(), dest->as_register_hi());
2012 __ and3 (left->as_register_lo(), right->as_register_lo(), dest->as_register_lo());
2013 break;
2014
2015 case lir_logic_or:
2016 __ or3 (left->as_register_hi(), right->as_register_hi(), dest->as_register_hi());
2017 __ or3 (left->as_register_lo(), right->as_register_lo(), dest->as_register_lo());
2018 break;
2019
2020 case lir_logic_xor:
2021 __ xor3 (left->as_register_hi(), right->as_register_hi(), dest->as_register_hi());
2022 __ xor3 (left->as_register_lo(), right->as_register_lo(), dest->as_register_lo());
2023 break;
2024
2025 default: ShouldNotReachHere();
2026 }
2027 #endif
2028 }
2029 }
2030 }
2031
2032
2033 int LIR_Assembler::shift_amount(BasicType t) {
2034 int elem_size = type2aelembytes(t);
2035 switch (elem_size) {
2036 case 1 : return 0;
2037 case 2 : return 1;
2038 case 4 : return 2;
2039 case 8 : return 3;
2040 }
2041 ShouldNotReachHere();
2042 return -1;
2043 }
2044
2045
2046 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info, bool unwind) {
2047 assert(exceptionOop->as_register() == Oexception, "should match");
2048 assert(unwind || exceptionPC->as_register() == Oissuing_pc, "should match");
2049
2050 info->add_register_oop(exceptionOop);
2051
2052 if (unwind) {
2053 __ call(Runtime1::entry_for(Runtime1::unwind_exception_id), relocInfo::runtime_call_type);
2054 __ delayed()->nop();
2055 } else {
2056 // reuse the debug info from the safepoint poll for the throw op itself
2057 address pc_for_athrow = __ pc();
2058 int pc_for_athrow_offset = __ offset();
2059 RelocationHolder rspec = internal_word_Relocation::spec(pc_for_athrow);
2060 __ set(pc_for_athrow, Oissuing_pc, rspec);
2061 add_call_info(pc_for_athrow_offset, info); // for exception handler
2062
2063 __ call(Runtime1::entry_for(Runtime1::handle_exception_id), relocInfo::runtime_call_type);
2064 __ delayed()->nop();
2065 }
2066 }
2067
2068
2069 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
2070 Register src = op->src()->as_register();
2071 Register dst = op->dst()->as_register();
2072 Register src_pos = op->src_pos()->as_register();
2073 Register dst_pos = op->dst_pos()->as_register();
2074 Register length = op->length()->as_register();
2075 Register tmp = op->tmp()->as_register();
2076 Register tmp2 = O7;
2077
2078 int flags = op->flags();
2079 ciArrayKlass* default_type = op->expected_type();
2080 BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL;
2081 if (basic_type == T_ARRAY) basic_type = T_OBJECT;
2082
2083 // set up the arraycopy stub information
2084 ArrayCopyStub* stub = op->stub();
2085
2086 // always do stub if no type information is available. it's ok if
2087 // the known type isn't loaded since the code sanity checks
2088 // in debug mode and the type isn't required when we know the exact type
2089 // also check that the type is an array type.
2090 // We also, for now, always call the stub if the barrier set requires a
2091 // write_ref_pre barrier (which the stub does, but none of the optimized
2092 // cases currently does).
2093 if (op->expected_type() == NULL ||
2094 Universe::heap()->barrier_set()->has_write_ref_pre_barrier()) {
2095 __ mov(src, O0);
2096 __ mov(src_pos, O1);
2097 __ mov(dst, O2);
2098 __ mov(dst_pos, O3);
2099 __ mov(length, O4);
2100 __ call_VM_leaf(tmp, CAST_FROM_FN_PTR(address, Runtime1::arraycopy));
2101
2102 __ br_zero(Assembler::less, false, Assembler::pn, O0, *stub->entry());
2103 __ delayed()->nop();
2104 __ bind(*stub->continuation());
2105 return;
2106 }
2107
2108 assert(default_type != NULL && default_type->is_array_klass(), "must be true at this point");
2109
2110 // make sure src and dst are non-null and load array length
2111 if (flags & LIR_OpArrayCopy::src_null_check) {
2112 __ tst(src);
2113 __ br(Assembler::equal, false, Assembler::pn, *stub->entry());
2114 __ delayed()->nop();
2115 }
2116
2117 if (flags & LIR_OpArrayCopy::dst_null_check) {
2118 __ tst(dst);
2119 __ br(Assembler::equal, false, Assembler::pn, *stub->entry());
2120 __ delayed()->nop();
2121 }
2122
2123 if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
2124 // test src_pos register
2125 __ tst(src_pos);
2126 __ br(Assembler::less, false, Assembler::pn, *stub->entry());
2127 __ delayed()->nop();
2128 }
2129
2130 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
2131 // test dst_pos register
2132 __ tst(dst_pos);
2133 __ br(Assembler::less, false, Assembler::pn, *stub->entry());
2134 __ delayed()->nop();
2135 }
2136
2137 if (flags & LIR_OpArrayCopy::length_positive_check) {
2138 // make sure length isn't negative
2139 __ tst(length);
2140 __ br(Assembler::less, false, Assembler::pn, *stub->entry());
2141 __ delayed()->nop();
2142 }
2143
2144 if (flags & LIR_OpArrayCopy::src_range_check) {
2145 __ ld(src, arrayOopDesc::length_offset_in_bytes(), tmp2);
2146 __ add(length, src_pos, tmp);
2147 __ cmp(tmp2, tmp);
2148 __ br(Assembler::carrySet, false, Assembler::pn, *stub->entry());
2149 __ delayed()->nop();
2150 }
2151
2152 if (flags & LIR_OpArrayCopy::dst_range_check) {
2153 __ ld(dst, arrayOopDesc::length_offset_in_bytes(), tmp2);
2154 __ add(length, dst_pos, tmp);
2155 __ cmp(tmp2, tmp);
2156 __ br(Assembler::carrySet, false, Assembler::pn, *stub->entry());
2157 __ delayed()->nop();
2158 }
2159
2160 if (flags & LIR_OpArrayCopy::type_check) {
2161 __ ld_ptr(src, oopDesc::klass_offset_in_bytes(), tmp);
2162 __ ld_ptr(dst, oopDesc::klass_offset_in_bytes(), tmp2);
2163 __ cmp(tmp, tmp2);
2164 __ br(Assembler::notEqual, false, Assembler::pt, *stub->entry());
2165 __ delayed()->nop();
2166 }
2167
2168 #ifdef ASSERT
2169 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
2170 // Sanity check the known type with the incoming class. For the
2171 // primitive case the types must match exactly with src.klass and
2172 // dst.klass each exactly matching the default type. For the
2173 // object array case, if no type check is needed then either the
2174 // dst type is exactly the expected type and the src type is a
2175 // subtype which we can't check or src is the same array as dst
2176 // but not necessarily exactly of type default_type.
2177 Label known_ok, halt;
2178 jobject2reg(op->expected_type()->constant_encoding(), tmp);
2179 __ ld_ptr(dst, oopDesc::klass_offset_in_bytes(), tmp2);
2180 if (basic_type != T_OBJECT) {
2181 __ cmp(tmp, tmp2);
2182 __ br(Assembler::notEqual, false, Assembler::pn, halt);
2183 __ delayed()->ld_ptr(src, oopDesc::klass_offset_in_bytes(), tmp2);
2184 __ cmp(tmp, tmp2);
2185 __ br(Assembler::equal, false, Assembler::pn, known_ok);
2186 __ delayed()->nop();
2187 } else {
2188 __ cmp(tmp, tmp2);
2189 __ br(Assembler::equal, false, Assembler::pn, known_ok);
2190 __ delayed()->cmp(src, dst);
2191 __ br(Assembler::equal, false, Assembler::pn, known_ok);
2192 __ delayed()->nop();
2193 }
2194 __ bind(halt);
2195 __ stop("incorrect type information in arraycopy");
2196 __ bind(known_ok);
2197 }
2198 #endif
2199
2200 int shift = shift_amount(basic_type);
2201
2202 Register src_ptr = O0;
2203 Register dst_ptr = O1;
2204 Register len = O2;
2205
2206 __ add(src, arrayOopDesc::base_offset_in_bytes(basic_type), src_ptr);
2207 LP64_ONLY(__ sra(src_pos, 0, src_pos);) //higher 32bits must be null
2208 if (shift == 0) {
2209 __ add(src_ptr, src_pos, src_ptr);
2210 } else {
2211 __ sll(src_pos, shift, tmp);
2212 __ add(src_ptr, tmp, src_ptr);
2213 }
2214
2215 __ add(dst, arrayOopDesc::base_offset_in_bytes(basic_type), dst_ptr);
2216 LP64_ONLY(__ sra(dst_pos, 0, dst_pos);) //higher 32bits must be null
2217 if (shift == 0) {
2218 __ add(dst_ptr, dst_pos, dst_ptr);
2219 } else {
2220 __ sll(dst_pos, shift, tmp);
2221 __ add(dst_ptr, tmp, dst_ptr);
2222 }
2223
2224 if (basic_type != T_OBJECT) {
2225 if (shift == 0) {
2226 __ mov(length, len);
2227 } else {
2228 __ sll(length, shift, len);
2229 }
2230 __ call_VM_leaf(tmp, CAST_FROM_FN_PTR(address, Runtime1::primitive_arraycopy));
2231 } else {
2232 // oop_arraycopy takes a length in number of elements, so don't scale it.
2233 __ mov(length, len);
2234 __ call_VM_leaf(tmp, CAST_FROM_FN_PTR(address, Runtime1::oop_arraycopy));
2235 }
2236
2237 __ bind(*stub->continuation());
2238 }
2239
2240
2241 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2242 if (dest->is_single_cpu()) {
2243 #ifdef _LP64
2244 if (left->type() == T_OBJECT) {
2245 switch (code) {
2246 case lir_shl: __ sllx (left->as_register(), count->as_register(), dest->as_register()); break;
2247 case lir_shr: __ srax (left->as_register(), count->as_register(), dest->as_register()); break;
2248 case lir_ushr: __ srl (left->as_register(), count->as_register(), dest->as_register()); break;
2249 default: ShouldNotReachHere();
2250 }
2251 } else
2252 #endif
2253 switch (code) {
2254 case lir_shl: __ sll (left->as_register(), count->as_register(), dest->as_register()); break;
2255 case lir_shr: __ sra (left->as_register(), count->as_register(), dest->as_register()); break;
2256 case lir_ushr: __ srl (left->as_register(), count->as_register(), dest->as_register()); break;
2257 default: ShouldNotReachHere();
2258 }
2259 } else {
2260 #ifdef _LP64
2261 switch (code) {
2262 case lir_shl: __ sllx (left->as_register_lo(), count->as_register(), dest->as_register_lo()); break;
2263 case lir_shr: __ srax (left->as_register_lo(), count->as_register(), dest->as_register_lo()); break;
2264 case lir_ushr: __ srlx (left->as_register_lo(), count->as_register(), dest->as_register_lo()); break;
2265 default: ShouldNotReachHere();
2266 }
2267 #else
2268 switch (code) {
2269 case lir_shl: __ lshl (left->as_register_hi(), left->as_register_lo(), count->as_register(), dest->as_register_hi(), dest->as_register_lo(), G3_scratch); break;
2270 case lir_shr: __ lshr (left->as_register_hi(), left->as_register_lo(), count->as_register(), dest->as_register_hi(), dest->as_register_lo(), G3_scratch); break;
2271 case lir_ushr: __ lushr (left->as_register_hi(), left->as_register_lo(), count->as_register(), dest->as_register_hi(), dest->as_register_lo(), G3_scratch); break;
2272 default: ShouldNotReachHere();
2273 }
2274 #endif
2275 }
2276 }
2277
2278
2279 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2280 #ifdef _LP64
2281 if (left->type() == T_OBJECT) {
2282 count = count & 63; // shouldn't shift by more than sizeof(intptr_t)
2283 Register l = left->as_register();
2284 Register d = dest->as_register_lo();
2285 switch (code) {
2286 case lir_shl: __ sllx (l, count, d); break;
2287 case lir_shr: __ srax (l, count, d); break;
2288 case lir_ushr: __ srlx (l, count, d); break;
2289 default: ShouldNotReachHere();
2290 }
2291 return;
2292 }
2293 #endif
2294
2295 if (dest->is_single_cpu()) {
2296 count = count & 0x1F; // Java spec
2297 switch (code) {
2298 case lir_shl: __ sll (left->as_register(), count, dest->as_register()); break;
2299 case lir_shr: __ sra (left->as_register(), count, dest->as_register()); break;
2300 case lir_ushr: __ srl (left->as_register(), count, dest->as_register()); break;
2301 default: ShouldNotReachHere();
2302 }
2303 } else if (dest->is_double_cpu()) {
2304 count = count & 63; // Java spec
2305 switch (code) {
2306 case lir_shl: __ sllx (left->as_pointer_register(), count, dest->as_pointer_register()); break;
2307 case lir_shr: __ srax (left->as_pointer_register(), count, dest->as_pointer_register()); break;
2308 case lir_ushr: __ srlx (left->as_pointer_register(), count, dest->as_pointer_register()); break;
2309 default: ShouldNotReachHere();
2310 }
2311 } else {
2312 ShouldNotReachHere();
2313 }
2314 }
2315
2316
2317 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
2318 assert(op->tmp1()->as_register() == G1 &&
2319 op->tmp2()->as_register() == G3 &&
2320 op->tmp3()->as_register() == G4 &&
2321 op->obj()->as_register() == O0 &&
2322 op->klass()->as_register() == G5, "must be");
2323 if (op->init_check()) {
2324 __ ld(op->klass()->as_register(),
2325 instanceKlass::init_state_offset_in_bytes() + sizeof(oopDesc),
2326 op->tmp1()->as_register());
2327 add_debug_info_for_null_check_here(op->stub()->info());
2328 __ cmp(op->tmp1()->as_register(), instanceKlass::fully_initialized);
2329 __ br(Assembler::notEqual, false, Assembler::pn, *op->stub()->entry());
2330 __ delayed()->nop();
2331 }
2332 __ allocate_object(op->obj()->as_register(),
2333 op->tmp1()->as_register(),
2334 op->tmp2()->as_register(),
2335 op->tmp3()->as_register(),
2336 op->header_size(),
2337 op->object_size(),
2338 op->klass()->as_register(),
2339 *op->stub()->entry());
2340 __ bind(*op->stub()->continuation());
2341 __ verify_oop(op->obj()->as_register());
2342 }
2343
2344
2345 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
2346 assert(op->tmp1()->as_register() == G1 &&
2347 op->tmp2()->as_register() == G3 &&
2348 op->tmp3()->as_register() == G4 &&
2349 op->tmp4()->as_register() == O1 &&
2350 op->klass()->as_register() == G5, "must be");
2351 if (UseSlowPath ||
2352 (!UseFastNewObjectArray && (op->type() == T_OBJECT || op->type() == T_ARRAY)) ||
2353 (!UseFastNewTypeArray && (op->type() != T_OBJECT && op->type() != T_ARRAY))) {
2354 __ br(Assembler::always, false, Assembler::pn, *op->stub()->entry());
2355 __ delayed()->nop();
2356 } else {
2357 __ allocate_array(op->obj()->as_register(),
2358 op->len()->as_register(),
2359 op->tmp1()->as_register(),
2360 op->tmp2()->as_register(),
2361 op->tmp3()->as_register(),
2362 arrayOopDesc::header_size(op->type()),
2363 type2aelembytes(op->type()),
2364 op->klass()->as_register(),
2365 *op->stub()->entry());
2366 }
2367 __ bind(*op->stub()->continuation());
2368 }
2369
2370
2371 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
2372 LIR_Code code = op->code();
2373 if (code == lir_store_check) {
2374 Register value = op->object()->as_register();
2375 Register array = op->array()->as_register();
2376 Register k_RInfo = op->tmp1()->as_register();
2377 Register klass_RInfo = op->tmp2()->as_register();
2378 Register Rtmp1 = op->tmp3()->as_register();
2379
2380 __ verify_oop(value);
2381
2382 CodeStub* stub = op->stub();
2383 Label done;
2384 __ cmp(value, 0);
2385 __ br(Assembler::equal, false, Assembler::pn, done);
2386 __ delayed()->nop();
2387 load(array, oopDesc::klass_offset_in_bytes(), k_RInfo, T_OBJECT, op->info_for_exception());
2388 load(value, oopDesc::klass_offset_in_bytes(), klass_RInfo, T_OBJECT, NULL);
2389
2390 // get instance klass
2391 load(k_RInfo, objArrayKlass::element_klass_offset_in_bytes() + sizeof(oopDesc), k_RInfo, T_OBJECT, NULL);
2392 // perform the fast part of the checking logic
2393 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, O7, &done, stub->entry(), NULL);
2394
2395 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
2396 assert(klass_RInfo == G3 && k_RInfo == G1, "incorrect call setup");
2397 __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type);
2398 __ delayed()->nop();
2399 __ cmp(G3, 0);
2400 __ br(Assembler::equal, false, Assembler::pn, *stub->entry());
2401 __ delayed()->nop();
2402 __ bind(done);
2403 } else if (op->code() == lir_checkcast) {
2404 // we always need a stub for the failure case.
2405 CodeStub* stub = op->stub();
2406 Register obj = op->object()->as_register();
2407 Register k_RInfo = op->tmp1()->as_register();
2408 Register klass_RInfo = op->tmp2()->as_register();
2409 Register dst = op->result_opr()->as_register();
2410 Register Rtmp1 = op->tmp3()->as_register();
2411 ciKlass* k = op->klass();
2412
2413 if (obj == k_RInfo) {
2414 k_RInfo = klass_RInfo;
2415 klass_RInfo = obj;
2416 }
2417 if (op->profiled_method() != NULL) {
2418 ciMethod* method = op->profiled_method();
2419 int bci = op->profiled_bci();
2420
2421 // We need two temporaries to perform this operation on SPARC,
2422 // so to keep things simple we perform a redundant test here
2423 Label profile_done;
2424 __ cmp(obj, 0);
2425 __ br(Assembler::notEqual, false, Assembler::pn, profile_done);
2426 __ delayed()->nop();
2427 // Object is null; update methodDataOop
2428 ciMethodData* md = method->method_data();
2429 if (md == NULL) {
2430 bailout("out of memory building methodDataOop");
2431 return;
2432 }
2433 ciProfileData* data = md->bci_to_data(bci);
2434 assert(data != NULL, "need data for checkcast");
2435 assert(data->is_BitData(), "need BitData for checkcast");
2436 Register mdo = k_RInfo;
2437 Register data_val = Rtmp1;
2438 jobject2reg(md->constant_encoding(), mdo);
2439
2440 int mdo_offset_bias = 0;
2441 if (!Assembler::is_simm13(md->byte_offset_of_slot(data, DataLayout::header_offset()) + data->size_in_bytes())) {
2442 // The offset is large so bias the mdo by the base of the slot so
2443 // that the ld can use simm13s to reference the slots of the data
2444 mdo_offset_bias = md->byte_offset_of_slot(data, DataLayout::header_offset());
2445 __ set(mdo_offset_bias, data_val);
2446 __ add(mdo, data_val, mdo);
2447 }
2448
2449
2450 Address flags_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias);
2451 __ ldub(flags_addr, data_val);
2452 __ or3(data_val, BitData::null_seen_byte_constant(), data_val);
2453 __ stb(data_val, flags_addr);
2454 __ bind(profile_done);
2455 }
2456
2457 Label done;
2458 // patching may screw with our temporaries on sparc,
2459 // so let's do it before loading the class
2460 if (k->is_loaded()) {
2461 jobject2reg(k->constant_encoding(), k_RInfo);
2462 } else {
2463 jobject2reg_with_patching(k_RInfo, op->info_for_patch());
2464 }
2465 assert(obj != k_RInfo, "must be different");
2466 __ cmp(obj, 0);
2467 __ br(Assembler::equal, false, Assembler::pn, done);
2468 __ delayed()->nop();
2469
2470 // get object class
2471 // not a safepoint as obj null check happens earlier
2472 load(obj, oopDesc::klass_offset_in_bytes(), klass_RInfo, T_OBJECT, NULL);
2473 if (op->fast_check()) {
2474 assert_different_registers(klass_RInfo, k_RInfo);
2475 __ cmp(k_RInfo, klass_RInfo);
2476 __ br(Assembler::notEqual, false, Assembler::pt, *stub->entry());
2477 __ delayed()->nop();
2478 __ bind(done);
2479 } else {
2480 bool need_slow_path = true;
2481 if (k->is_loaded()) {
2482 if (k->super_check_offset() != sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes())
2483 need_slow_path = false;
2484 // perform the fast part of the checking logic
2485 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, noreg,
2486 (need_slow_path ? &done : NULL),
2487 stub->entry(), NULL,
2488 RegisterOrConstant(k->super_check_offset()));
2489 } else {
2490 // perform the fast part of the checking logic
2491 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, O7,
2492 &done, stub->entry(), NULL);
2493 }
2494 if (need_slow_path) {
2495 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
2496 assert(klass_RInfo == G3 && k_RInfo == G1, "incorrect call setup");
2497 __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type);
2498 __ delayed()->nop();
2499 __ cmp(G3, 0);
2500 __ br(Assembler::equal, false, Assembler::pn, *stub->entry());
2501 __ delayed()->nop();
2502 }
2503 __ bind(done);
2504 }
2505 __ mov(obj, dst);
2506 } else if (code == lir_instanceof) {
2507 Register obj = op->object()->as_register();
2508 Register k_RInfo = op->tmp1()->as_register();
2509 Register klass_RInfo = op->tmp2()->as_register();
2510 Register dst = op->result_opr()->as_register();
2511 Register Rtmp1 = op->tmp3()->as_register();
2512 ciKlass* k = op->klass();
2513
2514 Label done;
2515 if (obj == k_RInfo) {
2516 k_RInfo = klass_RInfo;
2517 klass_RInfo = obj;
2518 }
2519 // patching may screw with our temporaries on sparc,
2520 // so let's do it before loading the class
2521 if (k->is_loaded()) {
2522 jobject2reg(k->constant_encoding(), k_RInfo);
2523 } else {
2524 jobject2reg_with_patching(k_RInfo, op->info_for_patch());
2525 }
2526 assert(obj != k_RInfo, "must be different");
2527 __ cmp(obj, 0);
2528 __ br(Assembler::equal, true, Assembler::pn, done);
2529 __ delayed()->set(0, dst);
2530
2531 // get object class
2532 // not a safepoint as obj null check happens earlier
2533 load(obj, oopDesc::klass_offset_in_bytes(), klass_RInfo, T_OBJECT, NULL);
2534 if (op->fast_check()) {
2535 __ cmp(k_RInfo, klass_RInfo);
2536 __ br(Assembler::equal, true, Assembler::pt, done);
2537 __ delayed()->set(1, dst);
2538 __ set(0, dst);
2539 __ bind(done);
2540 } else {
2541 bool need_slow_path = true;
2542 if (k->is_loaded()) {
2543 if (k->super_check_offset() != sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes())
2544 need_slow_path = false;
2545 // perform the fast part of the checking logic
2546 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, O7, noreg,
2547 (need_slow_path ? &done : NULL),
2548 (need_slow_path ? &done : NULL), NULL,
2549 RegisterOrConstant(k->super_check_offset()),
2550 dst);
2551 } else {
2552 assert(dst != klass_RInfo && dst != k_RInfo, "need 3 registers");
2553 // perform the fast part of the checking logic
2554 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, O7, dst,
2555 &done, &done, NULL,
2556 RegisterOrConstant(-1),
2557 dst);
2558 }
2559 if (need_slow_path) {
2560 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
2561 assert(klass_RInfo == G3 && k_RInfo == G1, "incorrect call setup");
2562 __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type);
2563 __ delayed()->nop();
2564 __ mov(G3, dst);
2565 }
2566 __ bind(done);
2567 }
2568 } else {
2569 ShouldNotReachHere();
2570 }
2571
2572 }
2573
2574
2575 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
2576 if (op->code() == lir_cas_long) {
2577 assert(VM_Version::supports_cx8(), "wrong machine");
2578 Register addr = op->addr()->as_pointer_register();
2579 Register cmp_value_lo = op->cmp_value()->as_register_lo();
2580 Register cmp_value_hi = op->cmp_value()->as_register_hi();
2581 Register new_value_lo = op->new_value()->as_register_lo();
2582 Register new_value_hi = op->new_value()->as_register_hi();
2583 Register t1 = op->tmp1()->as_register();
2584 Register t2 = op->tmp2()->as_register();
2585 #ifdef _LP64
2586 __ mov(cmp_value_lo, t1);
2587 __ mov(new_value_lo, t2);
2588 #else
2589 // move high and low halves of long values into single registers
2590 __ sllx(cmp_value_hi, 32, t1); // shift high half into temp reg
2591 __ srl(cmp_value_lo, 0, cmp_value_lo); // clear upper 32 bits of low half
2592 __ or3(t1, cmp_value_lo, t1); // t1 holds 64-bit compare value
2593 __ sllx(new_value_hi, 32, t2);
2594 __ srl(new_value_lo, 0, new_value_lo);
2595 __ or3(t2, new_value_lo, t2); // t2 holds 64-bit value to swap
2596 #endif
2597 // perform the compare and swap operation
2598 __ casx(addr, t1, t2);
2599 // generate condition code - if the swap succeeded, t2 ("new value" reg) was
2600 // overwritten with the original value in "addr" and will be equal to t1.
2601 __ cmp(t1, t2);
2602
2603 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj) {
2604 Register addr = op->addr()->as_pointer_register();
2605 Register cmp_value = op->cmp_value()->as_register();
2606 Register new_value = op->new_value()->as_register();
2607 Register t1 = op->tmp1()->as_register();
2608 Register t2 = op->tmp2()->as_register();
2609 __ mov(cmp_value, t1);
2610 __ mov(new_value, t2);
2611 #ifdef _LP64
2612 if (op->code() == lir_cas_obj) {
2613 __ casx(addr, t1, t2);
2614 } else
2615 #endif
2616 {
2617 __ cas(addr, t1, t2);
2618 }
2619 __ cmp(t1, t2);
2620 } else {
2621 Unimplemented();
2622 }
2623 }
2624
2625 void LIR_Assembler::set_24bit_FPU() {
2626 Unimplemented();
2627 }
2628
2629
2630 void LIR_Assembler::reset_FPU() {
2631 Unimplemented();
2632 }
2633
2634
2635 void LIR_Assembler::breakpoint() {
2636 __ breakpoint_trap();
2637 }
2638
2639
2640 void LIR_Assembler::push(LIR_Opr opr) {
2641 Unimplemented();
2642 }
2643
2644
2645 void LIR_Assembler::pop(LIR_Opr opr) {
2646 Unimplemented();
2647 }
2648
2649
2650 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst_opr) {
2651 Address mon_addr = frame_map()->address_for_monitor_lock(monitor_no);
2652 Register dst = dst_opr->as_register();
2653 Register reg = mon_addr.base();
2654 int offset = mon_addr.disp();
2655 // compute pointer to BasicLock
2656 if (mon_addr.is_simm13()) {
2657 __ add(reg, offset, dst);
2658 } else {
2659 __ set(offset, dst);
2660 __ add(dst, reg, dst);
2661 }
2662 }
2663
2664
2665 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
2666 Register obj = op->obj_opr()->as_register();
2667 Register hdr = op->hdr_opr()->as_register();
2668 Register lock = op->lock_opr()->as_register();
2669
2670 // obj may not be an oop
2671 if (op->code() == lir_lock) {
2672 MonitorEnterStub* stub = (MonitorEnterStub*)op->stub();
2673 if (UseFastLocking) {
2674 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2675 // add debug info for NullPointerException only if one is possible
2676 if (op->info() != NULL) {
2677 add_debug_info_for_null_check_here(op->info());
2678 }
2679 __ lock_object(hdr, obj, lock, op->scratch_opr()->as_register(), *op->stub()->entry());
2680 } else {
2681 // always do slow locking
2682 // note: the slow locking code could be inlined here, however if we use
2683 // slow locking, speed doesn't matter anyway and this solution is
2684 // simpler and requires less duplicated code - additionally, the
2685 // slow locking code is the same in either case which simplifies
2686 // debugging
2687 __ br(Assembler::always, false, Assembler::pt, *op->stub()->entry());
2688 __ delayed()->nop();
2689 }
2690 } else {
2691 assert (op->code() == lir_unlock, "Invalid code, expected lir_unlock");
2692 if (UseFastLocking) {
2693 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2694 __ unlock_object(hdr, obj, lock, *op->stub()->entry());
2695 } else {
2696 // always do slow unlocking
2697 // note: the slow unlocking code could be inlined here, however if we use
2698 // slow unlocking, speed doesn't matter anyway and this solution is
2699 // simpler and requires less duplicated code - additionally, the
2700 // slow unlocking code is the same in either case which simplifies
2701 // debugging
2702 __ br(Assembler::always, false, Assembler::pt, *op->stub()->entry());
2703 __ delayed()->nop();
2704 }
2705 }
2706 __ bind(*op->stub()->continuation());
2707 }
2708
2709
2710 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
2711 ciMethod* method = op->profiled_method();
2712 int bci = op->profiled_bci();
2713
2714 // Update counter for all call types
2715 ciMethodData* md = method->method_data();
2716 if (md == NULL) {
2717 bailout("out of memory building methodDataOop");
2718 return;
2719 }
2720 ciProfileData* data = md->bci_to_data(bci);
2721 assert(data->is_CounterData(), "need CounterData for calls");
2722 assert(op->mdo()->is_single_cpu(), "mdo must be allocated");
2723 assert(op->tmp1()->is_single_cpu(), "tmp1 must be allocated");
2724 Register mdo = op->mdo()->as_register();
2725 Register tmp1 = op->tmp1()->as_register();
2726 jobject2reg(md->constant_encoding(), mdo);
2727 int mdo_offset_bias = 0;
2728 if (!Assembler::is_simm13(md->byte_offset_of_slot(data, CounterData::count_offset()) +
2729 data->size_in_bytes())) {
2730 // The offset is large so bias the mdo by the base of the slot so
2731 // that the ld can use simm13s to reference the slots of the data
2732 mdo_offset_bias = md->byte_offset_of_slot(data, CounterData::count_offset());
2733 __ set(mdo_offset_bias, O7);
2734 __ add(mdo, O7, mdo);
2735 }
2736
2737 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias);
2738 Bytecodes::Code bc = method->java_code_at_bci(bci);
2739 // Perform additional virtual call profiling for invokevirtual and
2740 // invokeinterface bytecodes
2741 if ((bc == Bytecodes::_invokevirtual || bc == Bytecodes::_invokeinterface) &&
2742 Tier1ProfileVirtualCalls) {
2743 assert(op->recv()->is_single_cpu(), "recv must be allocated");
2744 Register recv = op->recv()->as_register();
2745 assert_different_registers(mdo, tmp1, recv);
2746 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
2747 ciKlass* known_klass = op->known_holder();
2748 if (Tier1OptimizeVirtualCallProfiling && known_klass != NULL) {
2749 // We know the type that will be seen at this call site; we can
2750 // statically update the methodDataOop rather than needing to do
2751 // dynamic tests on the receiver type
2752
2753 // NOTE: we should probably put a lock around this search to
2754 // avoid collisions by concurrent compilations
2755 ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
2756 uint i;
2757 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2758 ciKlass* receiver = vc_data->receiver(i);
2759 if (known_klass->equals(receiver)) {
2760 Address data_addr(mdo, md->byte_offset_of_slot(data,
2761 VirtualCallData::receiver_count_offset(i)) -
2762 mdo_offset_bias);
2763 __ lduw(data_addr, tmp1);
2764 __ add(tmp1, DataLayout::counter_increment, tmp1);
2765 __ stw(tmp1, data_addr);
2766 return;
2767 }
2768 }
2769
2770 // Receiver type not found in profile data; select an empty slot
2771
2772 // Note that this is less efficient than it should be because it
2773 // always does a write to the receiver part of the
2774 // VirtualCallData rather than just the first time
2775 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2776 ciKlass* receiver = vc_data->receiver(i);
2777 if (receiver == NULL) {
2778 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)) -
2779 mdo_offset_bias);
2780 jobject2reg(known_klass->constant_encoding(), tmp1);
2781 __ st_ptr(tmp1, recv_addr);
2782 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) -
2783 mdo_offset_bias);
2784 __ lduw(data_addr, tmp1);
2785 __ add(tmp1, DataLayout::counter_increment, tmp1);
2786 __ stw(tmp1, data_addr);
2787 return;
2788 }
2789 }
2790 } else {
2791 load(Address(recv, oopDesc::klass_offset_in_bytes()), recv, T_OBJECT);
2792 Label update_done;
2793 uint i;
2794 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2795 Label next_test;
2796 // See if the receiver is receiver[n].
2797 Address receiver_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)) -
2798 mdo_offset_bias);
2799 __ ld_ptr(receiver_addr, tmp1);
2800 __ verify_oop(tmp1);
2801 __ cmp(recv, tmp1);
2802 __ brx(Assembler::notEqual, false, Assembler::pt, next_test);
2803 __ delayed()->nop();
2804 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) -
2805 mdo_offset_bias);
2806 __ lduw(data_addr, tmp1);
2807 __ add(tmp1, DataLayout::counter_increment, tmp1);
2808 __ stw(tmp1, data_addr);
2809 __ br(Assembler::always, false, Assembler::pt, update_done);
2810 __ delayed()->nop();
2811 __ bind(next_test);
2812 }
2813
2814 // Didn't find receiver; find next empty slot and fill it in
2815 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2816 Label next_test;
2817 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)) -
2818 mdo_offset_bias);
2819 load(recv_addr, tmp1, T_OBJECT);
2820 __ tst(tmp1);
2821 __ brx(Assembler::notEqual, false, Assembler::pt, next_test);
2822 __ delayed()->nop();
2823 __ st_ptr(recv, recv_addr);
2824 __ set(DataLayout::counter_increment, tmp1);
2825 __ st_ptr(tmp1, mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) -
2826 mdo_offset_bias);
2827 __ br(Assembler::always, false, Assembler::pt, update_done);
2828 __ delayed()->nop();
2829 __ bind(next_test);
2830 }
2831 // Receiver did not match any saved receiver and there is no empty row for it.
2832 // Increment total counter to indicate polymorphic case.
2833 __ lduw(counter_addr, tmp1);
2834 __ add(tmp1, DataLayout::counter_increment, tmp1);
2835 __ stw(tmp1, counter_addr);
2836
2837 __ bind(update_done);
2838 }
2839 } else {
2840 // Static call
2841 __ lduw(counter_addr, tmp1);
2842 __ add(tmp1, DataLayout::counter_increment, tmp1);
2843 __ stw(tmp1, counter_addr);
2844 }
2845 }
2846
2847
2848 void LIR_Assembler::align_backward_branch_target() {
2849 __ align(16);
2850 }
2851
2852
2853 void LIR_Assembler::emit_delay(LIR_OpDelay* op) {
2854 // make sure we are expecting a delay
2855 // this has the side effect of clearing the delay state
2856 // so we can use _masm instead of _masm->delayed() to do the
2857 // code generation.
2858 __ delayed();
2859
2860 // make sure we only emit one instruction
2861 int offset = code_offset();
2862 op->delay_op()->emit_code(this);
2863 #ifdef ASSERT
2864 if (code_offset() - offset != NativeInstruction::nop_instruction_size) {
2865 op->delay_op()->print();
2866 }
2867 assert(code_offset() - offset == NativeInstruction::nop_instruction_size,
2868 "only one instruction can go in a delay slot");
2869 #endif
2870
2871 // we may also be emitting the call info for the instruction
2872 // which we are the delay slot of.
2873 CodeEmitInfo * call_info = op->call_info();
2874 if (call_info) {
2875 add_call_info(code_offset(), call_info);
2876 }
2877
2878 if (VerifyStackAtCalls) {
2879 _masm->sub(FP, SP, O7);
2880 _masm->cmp(O7, initial_frame_size_in_bytes());
2881 _masm->trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2 );
2882 }
2883 }
2884
2885
2886 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest) {
2887 assert(left->is_register(), "can only handle registers");
2888
2889 if (left->is_single_cpu()) {
2890 __ neg(left->as_register(), dest->as_register());
2891 } else if (left->is_single_fpu()) {
2892 __ fneg(FloatRegisterImpl::S, left->as_float_reg(), dest->as_float_reg());
2893 } else if (left->is_double_fpu()) {
2894 __ fneg(FloatRegisterImpl::D, left->as_double_reg(), dest->as_double_reg());
2895 } else {
2896 assert (left->is_double_cpu(), "Must be a long");
2897 Register Rlow = left->as_register_lo();
2898 Register Rhi = left->as_register_hi();
2899 #ifdef _LP64
2900 __ sub(G0, Rlow, dest->as_register_lo());
2901 #else
2902 __ subcc(G0, Rlow, dest->as_register_lo());
2903 __ subc (G0, Rhi, dest->as_register_hi());
2904 #endif
2905 }
2906 }
2907
2908
2909 void LIR_Assembler::fxch(int i) {
2910 Unimplemented();
2911 }
2912
2913 void LIR_Assembler::fld(int i) {
2914 Unimplemented();
2915 }
2916
2917 void LIR_Assembler::ffree(int i) {
2918 Unimplemented();
2919 }
2920
2921 void LIR_Assembler::rt_call(LIR_Opr result, address dest,
2922 const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
2923
2924 // if tmp is invalid, then the function being called doesn't destroy the thread
2925 if (tmp->is_valid()) {
2926 __ save_thread(tmp->as_register());
2927 }
2928 __ call(dest, relocInfo::runtime_call_type);
2929 __ delayed()->nop();
2930 if (info != NULL) {
2931 add_call_info_here(info);
2932 }
2933 if (tmp->is_valid()) {
2934 __ restore_thread(tmp->as_register());
2935 }
2936
2937 #ifdef ASSERT
2938 __ verify_thread();
2939 #endif // ASSERT
2940 }
2941
2942
2943 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
2944 #ifdef _LP64
2945 ShouldNotReachHere();
2946 #endif
2947
2948 NEEDS_CLEANUP;
2949 if (type == T_LONG) {
2950 LIR_Address* mem_addr = dest->is_address() ? dest->as_address_ptr() : src->as_address_ptr();
2951
2952 // (extended to allow indexed as well as constant displaced for JSR-166)
2953 Register idx = noreg; // contains either constant offset or index
2954
2955 int disp = mem_addr->disp();
2956 if (mem_addr->index() == LIR_OprFact::illegalOpr) {
2957 if (!Assembler::is_simm13(disp)) {
2958 idx = O7;
2959 __ set(disp, idx);
2960 }
2961 } else {
2962 assert(disp == 0, "not both indexed and disp");
2963 idx = mem_addr->index()->as_register();
2964 }
2965
2966 int null_check_offset = -1;
2967
2968 Register base = mem_addr->base()->as_register();
2969 if (src->is_register() && dest->is_address()) {
2970 // G4 is high half, G5 is low half
2971 if (VM_Version::v9_instructions_work()) {
2972 // clear the top bits of G5, and scale up G4
2973 __ srl (src->as_register_lo(), 0, G5);
2974 __ sllx(src->as_register_hi(), 32, G4);
2975 // combine the two halves into the 64 bits of G4
2976 __ or3(G4, G5, G4);
2977 null_check_offset = __ offset();
2978 if (idx == noreg) {
2979 __ stx(G4, base, disp);
2980 } else {
2981 __ stx(G4, base, idx);
2982 }
2983 } else {
2984 __ mov (src->as_register_hi(), G4);
2985 __ mov (src->as_register_lo(), G5);
2986 null_check_offset = __ offset();
2987 if (idx == noreg) {
2988 __ std(G4, base, disp);
2989 } else {
2990 __ std(G4, base, idx);
2991 }
2992 }
2993 } else if (src->is_address() && dest->is_register()) {
2994 null_check_offset = __ offset();
2995 if (VM_Version::v9_instructions_work()) {
2996 if (idx == noreg) {
2997 __ ldx(base, disp, G5);
2998 } else {
2999 __ ldx(base, idx, G5);
3000 }
3001 __ srax(G5, 32, dest->as_register_hi()); // fetch the high half into hi
3002 __ mov (G5, dest->as_register_lo()); // copy low half into lo
3003 } else {
3004 if (idx == noreg) {
3005 __ ldd(base, disp, G4);
3006 } else {
3007 __ ldd(base, idx, G4);
3008 }
3009 // G4 is high half, G5 is low half
3010 __ mov (G4, dest->as_register_hi());
3011 __ mov (G5, dest->as_register_lo());
3012 }
3013 } else {
3014 Unimplemented();
3015 }
3016 if (info != NULL) {
3017 add_debug_info_for_null_check(null_check_offset, info);
3018 }
3019
3020 } else {
3021 // use normal move for all other volatiles since they don't need
3022 // special handling to remain atomic.
3023 move_op(src, dest, type, lir_patch_none, info, false, false);
3024 }
3025 }
3026
3027 void LIR_Assembler::membar() {
3028 // only StoreLoad membars are ever explicitly needed on sparcs in TSO mode
3029 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad) );
3030 }
3031
3032 void LIR_Assembler::membar_acquire() {
3033 // no-op on TSO
3034 }
3035
3036 void LIR_Assembler::membar_release() {
3037 // no-op on TSO
3038 }
3039
3040 // Macro to Pack two sequential registers containing 32 bit values
3041 // into a single 64 bit register.
3042 // rs and rs->successor() are packed into rd
3043 // rd and rs may be the same register.
3044 // Note: rs and rs->successor() are destroyed.
3045 void LIR_Assembler::pack64( Register rs, Register rd ) {
3046 __ sllx(rs, 32, rs);
3047 __ srl(rs->successor(), 0, rs->successor());
3048 __ or3(rs, rs->successor(), rd);
3049 }
3050
3051 // Macro to unpack a 64 bit value in a register into
3052 // two sequential registers.
3053 // rd is unpacked into rd and rd->successor()
3054 void LIR_Assembler::unpack64( Register rd ) {
3055 __ mov(rd, rd->successor());
3056 __ srax(rd, 32, rd);
3057 __ sra(rd->successor(), 0, rd->successor());
3058 }
3059
3060
3061 void LIR_Assembler::leal(LIR_Opr addr_opr, LIR_Opr dest) {
3062 LIR_Address* addr = addr_opr->as_address_ptr();
3063 assert(addr->index()->is_illegal() && addr->scale() == LIR_Address::times_1 && Assembler::is_simm13(addr->disp()), "can't handle complex addresses yet");
3064 __ add(addr->base()->as_register(), addr->disp(), dest->as_register());
3065 }
3066
3067
3068 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
3069 assert(result_reg->is_register(), "check");
3070 __ mov(G2_thread, result_reg->as_register());
3071 }
3072
3073
3074 void LIR_Assembler::peephole(LIR_List* lir) {
3075 LIR_OpList* inst = lir->instructions_list();
3076 for (int i = 0; i < inst->length(); i++) {
3077 LIR_Op* op = inst->at(i);
3078 switch (op->code()) {
3079 case lir_cond_float_branch:
3080 case lir_branch: {
3081 LIR_OpBranch* branch = op->as_OpBranch();
3082 assert(branch->info() == NULL, "shouldn't be state on branches anymore");
3083 LIR_Op* delay_op = NULL;
3084 // we'd like to be able to pull following instructions into
3085 // this slot but we don't know enough to do it safely yet so
3086 // only optimize block to block control flow.
3087 if (LIRFillDelaySlots && branch->block()) {
3088 LIR_Op* prev = inst->at(i - 1);
3089 if (prev && LIR_Assembler::is_single_instruction(prev) && prev->info() == NULL) {
3090 // swap previous instruction into delay slot
3091 inst->at_put(i - 1, op);
3092 inst->at_put(i, new LIR_OpDelay(prev, op->info()));
3093 #ifndef PRODUCT
3094 if (LIRTracePeephole) {
3095 tty->print_cr("delayed");
3096 inst->at(i - 1)->print();
3097 inst->at(i)->print();
3098 }
3099 #endif
3100 continue;
3101 }
3102 }
3103
3104 if (!delay_op) {
3105 delay_op = new LIR_OpDelay(new LIR_Op0(lir_nop), NULL);
3106 }
3107 inst->insert_before(i + 1, delay_op);
3108 break;
3109 }
3110 case lir_static_call:
3111 case lir_virtual_call:
3112 case lir_icvirtual_call:
3113 case lir_optvirtual_call: {
3114 LIR_Op* delay_op = NULL;
3115 LIR_Op* prev = inst->at(i - 1);
3116 if (LIRFillDelaySlots && prev && prev->code() == lir_move && prev->info() == NULL &&
3117 (op->code() != lir_virtual_call ||
3118 !prev->result_opr()->is_single_cpu() ||
3119 prev->result_opr()->as_register() != O0) &&
3120 LIR_Assembler::is_single_instruction(prev)) {
3121 // Only moves without info can be put into the delay slot.
3122 // Also don't allow the setup of the receiver in the delay
3123 // slot for vtable calls.
3124 inst->at_put(i - 1, op);
3125 inst->at_put(i, new LIR_OpDelay(prev, op->info()));
3126 #ifndef PRODUCT
3127 if (LIRTracePeephole) {
3128 tty->print_cr("delayed");
3129 inst->at(i - 1)->print();
3130 inst->at(i)->print();
3131 }
3132 #endif
3133 continue;
3134 }
3135
3136 if (!delay_op) {
3137 delay_op = new LIR_OpDelay(new LIR_Op0(lir_nop), op->as_OpJavaCall()->info());
3138 inst->insert_before(i + 1, delay_op);
3139 }
3140 break;
3141 }
3142 }
3143 }
3144 }
3145
3146
3147
3148
3149 #undef __