1 /* 2 * Copyright 2000-2010 Sun Microsystems, Inc. All Rights Reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 20 * CA 95054 USA or visit www.sun.com if you need additional information or 21 * have any questions. 22 * 23 */ 24 25 # include "incls/_precompiled.incl" 26 # include "incls/_c1_LIRAssembler_x86.cpp.incl" 27 28 29 // These masks are used to provide 128-bit aligned bitmasks to the XMM 30 // instructions, to allow sign-masking or sign-bit flipping. They allow 31 // fast versions of NegF/NegD and AbsF/AbsD. 32 33 // Note: 'double' and 'long long' have 32-bits alignment on x86. 34 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) { 35 // Use the expression (adr)&(~0xF) to provide 128-bits aligned address 36 // of 128-bits operands for SSE instructions. 37 jlong *operand = (jlong*)(((long)adr)&((long)(~0xF))); 38 // Store the value to a 128-bits operand. 39 operand[0] = lo; 40 operand[1] = hi; 41 return operand; 42 } 43 44 // Buffer for 128-bits masks used by SSE instructions. 45 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment) 46 47 // Static initialization during VM startup. 48 static jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF)); 49 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF)); 50 static jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], CONST64(0x8000000080000000), CONST64(0x8000000080000000)); 51 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], CONST64(0x8000000000000000), CONST64(0x8000000000000000)); 52 53 54 55 NEEDS_CLEANUP // remove this definitions ? 56 const Register IC_Klass = rax; // where the IC klass is cached 57 const Register SYNC_header = rax; // synchronization header 58 const Register SHIFT_count = rcx; // where count for shift operations must be 59 60 #define __ _masm-> 61 62 63 static void select_different_registers(Register preserve, 64 Register extra, 65 Register &tmp1, 66 Register &tmp2) { 67 if (tmp1 == preserve) { 68 assert_different_registers(tmp1, tmp2, extra); 69 tmp1 = extra; 70 } else if (tmp2 == preserve) { 71 assert_different_registers(tmp1, tmp2, extra); 72 tmp2 = extra; 73 } 74 assert_different_registers(preserve, tmp1, tmp2); 75 } 76 77 78 79 static void select_different_registers(Register preserve, 80 Register extra, 81 Register &tmp1, 82 Register &tmp2, 83 Register &tmp3) { 84 if (tmp1 == preserve) { 85 assert_different_registers(tmp1, tmp2, tmp3, extra); 86 tmp1 = extra; 87 } else if (tmp2 == preserve) { 88 assert_different_registers(tmp1, tmp2, tmp3, extra); 89 tmp2 = extra; 90 } else if (tmp3 == preserve) { 91 assert_different_registers(tmp1, tmp2, tmp3, extra); 92 tmp3 = extra; 93 } 94 assert_different_registers(preserve, tmp1, tmp2, tmp3); 95 } 96 97 98 99 bool LIR_Assembler::is_small_constant(LIR_Opr opr) { 100 if (opr->is_constant()) { 101 LIR_Const* constant = opr->as_constant_ptr(); 102 switch (constant->type()) { 103 case T_INT: { 104 return true; 105 } 106 107 default: 108 return false; 109 } 110 } 111 return false; 112 } 113 114 115 LIR_Opr LIR_Assembler::receiverOpr() { 116 return FrameMap::receiver_opr; 117 } 118 119 LIR_Opr LIR_Assembler::incomingReceiverOpr() { 120 return receiverOpr(); 121 } 122 123 LIR_Opr LIR_Assembler::osrBufferPointer() { 124 return FrameMap::as_pointer_opr(receiverOpr()->as_register()); 125 } 126 127 //--------------fpu register translations----------------------- 128 129 130 address LIR_Assembler::float_constant(float f) { 131 address const_addr = __ float_constant(f); 132 if (const_addr == NULL) { 133 bailout("const section overflow"); 134 return __ code()->consts()->start(); 135 } else { 136 return const_addr; 137 } 138 } 139 140 141 address LIR_Assembler::double_constant(double d) { 142 address const_addr = __ double_constant(d); 143 if (const_addr == NULL) { 144 bailout("const section overflow"); 145 return __ code()->consts()->start(); 146 } else { 147 return const_addr; 148 } 149 } 150 151 152 void LIR_Assembler::set_24bit_FPU() { 153 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24())); 154 } 155 156 void LIR_Assembler::reset_FPU() { 157 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std())); 158 } 159 160 void LIR_Assembler::fpop() { 161 __ fpop(); 162 } 163 164 void LIR_Assembler::fxch(int i) { 165 __ fxch(i); 166 } 167 168 void LIR_Assembler::fld(int i) { 169 __ fld_s(i); 170 } 171 172 void LIR_Assembler::ffree(int i) { 173 __ ffree(i); 174 } 175 176 void LIR_Assembler::breakpoint() { 177 __ int3(); 178 } 179 180 void LIR_Assembler::push(LIR_Opr opr) { 181 if (opr->is_single_cpu()) { 182 __ push_reg(opr->as_register()); 183 } else if (opr->is_double_cpu()) { 184 NOT_LP64(__ push_reg(opr->as_register_hi())); 185 __ push_reg(opr->as_register_lo()); 186 } else if (opr->is_stack()) { 187 __ push_addr(frame_map()->address_for_slot(opr->single_stack_ix())); 188 } else if (opr->is_constant()) { 189 LIR_Const* const_opr = opr->as_constant_ptr(); 190 if (const_opr->type() == T_OBJECT) { 191 __ push_oop(const_opr->as_jobject()); 192 } else if (const_opr->type() == T_INT) { 193 __ push_jint(const_opr->as_jint()); 194 } else { 195 ShouldNotReachHere(); 196 } 197 198 } else { 199 ShouldNotReachHere(); 200 } 201 } 202 203 void LIR_Assembler::pop(LIR_Opr opr) { 204 if (opr->is_single_cpu()) { 205 __ pop_reg(opr->as_register()); 206 } else { 207 ShouldNotReachHere(); 208 } 209 } 210 211 bool LIR_Assembler::is_literal_address(LIR_Address* addr) { 212 return addr->base()->is_illegal() && addr->index()->is_illegal(); 213 } 214 215 //------------------------------------------- 216 217 Address LIR_Assembler::as_Address(LIR_Address* addr) { 218 return as_Address(addr, rscratch1); 219 } 220 221 Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) { 222 if (addr->base()->is_illegal()) { 223 assert(addr->index()->is_illegal(), "must be illegal too"); 224 AddressLiteral laddr((address)addr->disp(), relocInfo::none); 225 if (! __ reachable(laddr)) { 226 __ movptr(tmp, laddr.addr()); 227 Address res(tmp, 0); 228 return res; 229 } else { 230 return __ as_Address(laddr); 231 } 232 } 233 234 Register base = addr->base()->as_pointer_register(); 235 236 if (addr->index()->is_illegal()) { 237 return Address( base, addr->disp()); 238 } else if (addr->index()->is_cpu_register()) { 239 Register index = addr->index()->as_pointer_register(); 240 return Address(base, index, (Address::ScaleFactor) addr->scale(), addr->disp()); 241 } else if (addr->index()->is_constant()) { 242 intptr_t addr_offset = (addr->index()->as_constant_ptr()->as_jint() << addr->scale()) + addr->disp(); 243 assert(Assembler::is_simm32(addr_offset), "must be"); 244 245 return Address(base, addr_offset); 246 } else { 247 Unimplemented(); 248 return Address(); 249 } 250 } 251 252 253 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) { 254 Address base = as_Address(addr); 255 return Address(base._base, base._index, base._scale, base._disp + BytesPerWord); 256 } 257 258 259 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) { 260 return as_Address(addr); 261 } 262 263 264 void LIR_Assembler::osr_entry() { 265 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset()); 266 BlockBegin* osr_entry = compilation()->hir()->osr_entry(); 267 ValueStack* entry_state = osr_entry->state(); 268 int number_of_locks = entry_state->locks_size(); 269 270 // we jump here if osr happens with the interpreter 271 // state set up to continue at the beginning of the 272 // loop that triggered osr - in particular, we have 273 // the following registers setup: 274 // 275 // rcx: osr buffer 276 // 277 278 // build frame 279 ciMethod* m = compilation()->method(); 280 __ build_frame(initial_frame_size_in_bytes()); 281 282 // OSR buffer is 283 // 284 // locals[nlocals-1..0] 285 // monitors[0..number_of_locks] 286 // 287 // locals is a direct copy of the interpreter frame so in the osr buffer 288 // so first slot in the local array is the last local from the interpreter 289 // and last slot is local[0] (receiver) from the interpreter 290 // 291 // Similarly with locks. The first lock slot in the osr buffer is the nth lock 292 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock 293 // in the interpreter frame (the method lock if a sync method) 294 295 // Initialize monitors in the compiled activation. 296 // rcx: pointer to osr buffer 297 // 298 // All other registers are dead at this point and the locals will be 299 // copied into place by code emitted in the IR. 300 301 Register OSR_buf = osrBufferPointer()->as_pointer_register(); 302 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below"); 303 int monitor_offset = BytesPerWord * method()->max_locals() + 304 (2 * BytesPerWord) * (number_of_locks - 1); 305 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in 306 // the OSR buffer using 2 word entries: first the lock and then 307 // the oop. 308 for (int i = 0; i < number_of_locks; i++) { 309 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord); 310 #ifdef ASSERT 311 // verify the interpreter's monitor has a non-null object 312 { 313 Label L; 314 __ cmpptr(Address(OSR_buf, slot_offset + 1*BytesPerWord), (int32_t)NULL_WORD); 315 __ jcc(Assembler::notZero, L); 316 __ stop("locked object is NULL"); 317 __ bind(L); 318 } 319 #endif 320 __ movptr(rbx, Address(OSR_buf, slot_offset + 0)); 321 __ movptr(frame_map()->address_for_monitor_lock(i), rbx); 322 __ movptr(rbx, Address(OSR_buf, slot_offset + 1*BytesPerWord)); 323 __ movptr(frame_map()->address_for_monitor_object(i), rbx); 324 } 325 } 326 } 327 328 329 // inline cache check; done before the frame is built. 330 int LIR_Assembler::check_icache() { 331 Register receiver = FrameMap::receiver_opr->as_register(); 332 Register ic_klass = IC_Klass; 333 const int ic_cmp_size = LP64_ONLY(10) NOT_LP64(9); 334 335 if (!VerifyOops) { 336 // insert some nops so that the verified entry point is aligned on CodeEntryAlignment 337 while ((__ offset() + ic_cmp_size) % CodeEntryAlignment != 0) { 338 __ nop(); 339 } 340 } 341 int offset = __ offset(); 342 __ inline_cache_check(receiver, IC_Klass); 343 assert(__ offset() % CodeEntryAlignment == 0 || VerifyOops, "alignment must be correct"); 344 if (VerifyOops) { 345 // force alignment after the cache check. 346 // It's been verified to be aligned if !VerifyOops 347 __ align(CodeEntryAlignment); 348 } 349 return offset; 350 } 351 352 353 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo* info) { 354 jobject o = NULL; 355 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id); 356 __ movoop(reg, o); 357 patching_epilog(patch, lir_patch_normal, reg, info); 358 } 359 360 361 void LIR_Assembler::monitorexit(LIR_Opr obj_opr, LIR_Opr lock_opr, Register new_hdr, int monitor_no, Register exception) { 362 if (exception->is_valid()) { 363 // preserve exception 364 // note: the monitor_exit runtime call is a leaf routine 365 // and cannot block => no GC can happen 366 // The slow case (MonitorAccessStub) uses the first two stack slots 367 // ([esp+0] and [esp+4]), therefore we store the exception at [esp+8] 368 __ movptr (Address(rsp, 2*wordSize), exception); 369 } 370 371 Register obj_reg = obj_opr->as_register(); 372 Register lock_reg = lock_opr->as_register(); 373 374 // setup registers (lock_reg must be rax, for lock_object) 375 assert(obj_reg != SYNC_header && lock_reg != SYNC_header, "rax, must be available here"); 376 Register hdr = lock_reg; 377 assert(new_hdr == SYNC_header, "wrong register"); 378 lock_reg = new_hdr; 379 // compute pointer to BasicLock 380 Address lock_addr = frame_map()->address_for_monitor_lock(monitor_no); 381 __ lea(lock_reg, lock_addr); 382 // unlock object 383 MonitorAccessStub* slow_case = new MonitorExitStub(lock_opr, true, monitor_no); 384 // _slow_case_stubs->append(slow_case); 385 // temporary fix: must be created after exceptionhandler, therefore as call stub 386 _slow_case_stubs->append(slow_case); 387 if (UseFastLocking) { 388 // try inlined fast unlocking first, revert to slow locking if it fails 389 // note: lock_reg points to the displaced header since the displaced header offset is 0! 390 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header"); 391 __ unlock_object(hdr, obj_reg, lock_reg, *slow_case->entry()); 392 } else { 393 // always do slow unlocking 394 // note: the slow unlocking code could be inlined here, however if we use 395 // slow unlocking, speed doesn't matter anyway and this solution is 396 // simpler and requires less duplicated code - additionally, the 397 // slow unlocking code is the same in either case which simplifies 398 // debugging 399 __ jmp(*slow_case->entry()); 400 } 401 // done 402 __ bind(*slow_case->continuation()); 403 404 if (exception->is_valid()) { 405 // restore exception 406 __ movptr (exception, Address(rsp, 2 * wordSize)); 407 } 408 } 409 410 // This specifies the rsp decrement needed to build the frame 411 int LIR_Assembler::initial_frame_size_in_bytes() { 412 // if rounding, must let FrameMap know! 413 414 // The frame_map records size in slots (32bit word) 415 416 // subtract two words to account for return address and link 417 return (frame_map()->framesize() - (2*VMRegImpl::slots_per_word)) * VMRegImpl::stack_slot_size; 418 } 419 420 421 int LIR_Assembler::emit_exception_handler() { 422 // if the last instruction is a call (typically to do a throw which 423 // is coming at the end after block reordering) the return address 424 // must still point into the code area in order to avoid assertion 425 // failures when searching for the corresponding bci => add a nop 426 // (was bug 5/14/1999 - gri) 427 __ nop(); 428 429 // generate code for exception handler 430 address handler_base = __ start_a_stub(exception_handler_size); 431 if (handler_base == NULL) { 432 // not enough space left for the handler 433 bailout("exception handler overflow"); 434 return -1; 435 } 436 437 int offset = code_offset(); 438 439 // the exception oop and pc are in rax, and rdx 440 // no other registers need to be preserved, so invalidate them 441 __ invalidate_registers(false, true, true, false, true, true); 442 443 // check that there is really an exception 444 __ verify_not_null_oop(rax); 445 446 // search an exception handler (rax: exception oop, rdx: throwing pc) 447 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::handle_exception_nofpu_id))); 448 449 __ stop("should not reach here"); 450 451 assert(code_offset() - offset <= exception_handler_size, "overflow"); 452 __ end_a_stub(); 453 454 return offset; 455 } 456 457 458 int LIR_Assembler::emit_deopt_handler() { 459 // if the last instruction is a call (typically to do a throw which 460 // is coming at the end after block reordering) the return address 461 // must still point into the code area in order to avoid assertion 462 // failures when searching for the corresponding bci => add a nop 463 // (was bug 5/14/1999 - gri) 464 __ nop(); 465 466 // generate code for exception handler 467 address handler_base = __ start_a_stub(deopt_handler_size); 468 if (handler_base == NULL) { 469 // not enough space left for the handler 470 bailout("deopt handler overflow"); 471 return -1; 472 } 473 474 int offset = code_offset(); 475 InternalAddress here(__ pc()); 476 477 __ pushptr(here.addr()); 478 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack())); 479 480 assert(code_offset() - offset <= deopt_handler_size, "overflow"); 481 __ end_a_stub(); 482 483 return offset; 484 } 485 486 487 // This is the fast version of java.lang.String.compare; it has not 488 // OSR-entry and therefore, we generate a slow version for OSR's 489 void LIR_Assembler::emit_string_compare(LIR_Opr arg0, LIR_Opr arg1, LIR_Opr dst, CodeEmitInfo* info) { 490 __ movptr (rbx, rcx); // receiver is in rcx 491 __ movptr (rax, arg1->as_register()); 492 493 // Get addresses of first characters from both Strings 494 __ movptr (rsi, Address(rax, java_lang_String::value_offset_in_bytes())); 495 __ movptr (rcx, Address(rax, java_lang_String::offset_offset_in_bytes())); 496 __ lea (rsi, Address(rsi, rcx, Address::times_2, arrayOopDesc::base_offset_in_bytes(T_CHAR))); 497 498 499 // rbx, may be NULL 500 add_debug_info_for_null_check_here(info); 501 __ movptr (rdi, Address(rbx, java_lang_String::value_offset_in_bytes())); 502 __ movptr (rcx, Address(rbx, java_lang_String::offset_offset_in_bytes())); 503 __ lea (rdi, Address(rdi, rcx, Address::times_2, arrayOopDesc::base_offset_in_bytes(T_CHAR))); 504 505 // compute minimum length (in rax) and difference of lengths (on top of stack) 506 if (VM_Version::supports_cmov()) { 507 __ movl (rbx, Address(rbx, java_lang_String::count_offset_in_bytes())); 508 __ movl (rax, Address(rax, java_lang_String::count_offset_in_bytes())); 509 __ mov (rcx, rbx); 510 __ subptr (rbx, rax); // subtract lengths 511 __ push (rbx); // result 512 __ cmov (Assembler::lessEqual, rax, rcx); 513 } else { 514 Label L; 515 __ movl (rbx, Address(rbx, java_lang_String::count_offset_in_bytes())); 516 __ movl (rcx, Address(rax, java_lang_String::count_offset_in_bytes())); 517 __ mov (rax, rbx); 518 __ subptr (rbx, rcx); 519 __ push (rbx); 520 __ jcc (Assembler::lessEqual, L); 521 __ mov (rax, rcx); 522 __ bind (L); 523 } 524 // is minimum length 0? 525 Label noLoop, haveResult; 526 __ testptr (rax, rax); 527 __ jcc (Assembler::zero, noLoop); 528 529 // compare first characters 530 __ load_unsigned_short(rcx, Address(rdi, 0)); 531 __ load_unsigned_short(rbx, Address(rsi, 0)); 532 __ subl(rcx, rbx); 533 __ jcc(Assembler::notZero, haveResult); 534 // starting loop 535 __ decrement(rax); // we already tested index: skip one 536 __ jcc(Assembler::zero, noLoop); 537 538 // set rsi.edi to the end of the arrays (arrays have same length) 539 // negate the index 540 541 __ lea(rsi, Address(rsi, rax, Address::times_2, type2aelembytes(T_CHAR))); 542 __ lea(rdi, Address(rdi, rax, Address::times_2, type2aelembytes(T_CHAR))); 543 __ negptr(rax); 544 545 // compare the strings in a loop 546 547 Label loop; 548 __ align(wordSize); 549 __ bind(loop); 550 __ load_unsigned_short(rcx, Address(rdi, rax, Address::times_2, 0)); 551 __ load_unsigned_short(rbx, Address(rsi, rax, Address::times_2, 0)); 552 __ subl(rcx, rbx); 553 __ jcc(Assembler::notZero, haveResult); 554 __ increment(rax); 555 __ jcc(Assembler::notZero, loop); 556 557 // strings are equal up to min length 558 559 __ bind(noLoop); 560 __ pop(rax); 561 return_op(LIR_OprFact::illegalOpr); 562 563 __ bind(haveResult); 564 // leave instruction is going to discard the TOS value 565 __ mov (rax, rcx); // result of call is in rax, 566 } 567 568 569 void LIR_Assembler::return_op(LIR_Opr result) { 570 assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == rax, "word returns are in rax,"); 571 if (!result->is_illegal() && result->is_float_kind() && !result->is_xmm_register()) { 572 assert(result->fpu() == 0, "result must already be on TOS"); 573 } 574 575 // Pop the stack before the safepoint code 576 __ remove_frame(initial_frame_size_in_bytes()); 577 578 bool result_is_oop = result->is_valid() ? result->is_oop() : false; 579 580 // Note: we do not need to round double result; float result has the right precision 581 // the poll sets the condition code, but no data registers 582 AddressLiteral polling_page(os::get_polling_page() + (SafepointPollOffset % os::vm_page_size()), 583 relocInfo::poll_return_type); 584 585 // NOTE: the requires that the polling page be reachable else the reloc 586 // goes to the movq that loads the address and not the faulting instruction 587 // which breaks the signal handler code 588 589 __ test32(rax, polling_page); 590 591 __ ret(0); 592 } 593 594 595 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) { 596 AddressLiteral polling_page(os::get_polling_page() + (SafepointPollOffset % os::vm_page_size()), 597 relocInfo::poll_type); 598 599 if (info != NULL) { 600 add_debug_info_for_branch(info); 601 } else { 602 ShouldNotReachHere(); 603 } 604 605 int offset = __ offset(); 606 607 // NOTE: the requires that the polling page be reachable else the reloc 608 // goes to the movq that loads the address and not the faulting instruction 609 // which breaks the signal handler code 610 611 __ test32(rax, polling_page); 612 return offset; 613 } 614 615 616 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) { 617 if (from_reg != to_reg) __ mov(to_reg, from_reg); 618 } 619 620 void LIR_Assembler::swap_reg(Register a, Register b) { 621 __ xchgptr(a, b); 622 } 623 624 625 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) { 626 assert(src->is_constant(), "should not call otherwise"); 627 assert(dest->is_register(), "should not call otherwise"); 628 LIR_Const* c = src->as_constant_ptr(); 629 630 switch (c->type()) { 631 case T_INT: { 632 assert(patch_code == lir_patch_none, "no patching handled here"); 633 __ movl(dest->as_register(), c->as_jint()); 634 break; 635 } 636 637 case T_LONG: { 638 assert(patch_code == lir_patch_none, "no patching handled here"); 639 #ifdef _LP64 640 __ movptr(dest->as_register_lo(), (intptr_t)c->as_jlong()); 641 #else 642 __ movptr(dest->as_register_lo(), c->as_jint_lo()); 643 __ movptr(dest->as_register_hi(), c->as_jint_hi()); 644 #endif // _LP64 645 break; 646 } 647 648 case T_OBJECT: { 649 if (patch_code != lir_patch_none) { 650 jobject2reg_with_patching(dest->as_register(), info); 651 } else { 652 __ movoop(dest->as_register(), c->as_jobject()); 653 } 654 break; 655 } 656 657 case T_FLOAT: { 658 if (dest->is_single_xmm()) { 659 if (c->is_zero_float()) { 660 __ xorps(dest->as_xmm_float_reg(), dest->as_xmm_float_reg()); 661 } else { 662 __ movflt(dest->as_xmm_float_reg(), 663 InternalAddress(float_constant(c->as_jfloat()))); 664 } 665 } else { 666 assert(dest->is_single_fpu(), "must be"); 667 assert(dest->fpu_regnr() == 0, "dest must be TOS"); 668 if (c->is_zero_float()) { 669 __ fldz(); 670 } else if (c->is_one_float()) { 671 __ fld1(); 672 } else { 673 __ fld_s (InternalAddress(float_constant(c->as_jfloat()))); 674 } 675 } 676 break; 677 } 678 679 case T_DOUBLE: { 680 if (dest->is_double_xmm()) { 681 if (c->is_zero_double()) { 682 __ xorpd(dest->as_xmm_double_reg(), dest->as_xmm_double_reg()); 683 } else { 684 __ movdbl(dest->as_xmm_double_reg(), 685 InternalAddress(double_constant(c->as_jdouble()))); 686 } 687 } else { 688 assert(dest->is_double_fpu(), "must be"); 689 assert(dest->fpu_regnrLo() == 0, "dest must be TOS"); 690 if (c->is_zero_double()) { 691 __ fldz(); 692 } else if (c->is_one_double()) { 693 __ fld1(); 694 } else { 695 __ fld_d (InternalAddress(double_constant(c->as_jdouble()))); 696 } 697 } 698 break; 699 } 700 701 default: 702 ShouldNotReachHere(); 703 } 704 } 705 706 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) { 707 assert(src->is_constant(), "should not call otherwise"); 708 assert(dest->is_stack(), "should not call otherwise"); 709 LIR_Const* c = src->as_constant_ptr(); 710 711 switch (c->type()) { 712 case T_INT: // fall through 713 case T_FLOAT: 714 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits()); 715 break; 716 717 case T_OBJECT: 718 __ movoop(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jobject()); 719 break; 720 721 case T_LONG: // fall through 722 case T_DOUBLE: 723 #ifdef _LP64 724 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(), 725 lo_word_offset_in_bytes), (intptr_t)c->as_jlong_bits()); 726 #else 727 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(), 728 lo_word_offset_in_bytes), c->as_jint_lo_bits()); 729 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(), 730 hi_word_offset_in_bytes), c->as_jint_hi_bits()); 731 #endif // _LP64 732 break; 733 734 default: 735 ShouldNotReachHere(); 736 } 737 } 738 739 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info ) { 740 assert(src->is_constant(), "should not call otherwise"); 741 assert(dest->is_address(), "should not call otherwise"); 742 LIR_Const* c = src->as_constant_ptr(); 743 LIR_Address* addr = dest->as_address_ptr(); 744 745 int null_check_here = code_offset(); 746 switch (type) { 747 case T_INT: // fall through 748 case T_FLOAT: 749 __ movl(as_Address(addr), c->as_jint_bits()); 750 break; 751 752 case T_OBJECT: // fall through 753 case T_ARRAY: 754 if (c->as_jobject() == NULL) { 755 __ movptr(as_Address(addr), NULL_WORD); 756 } else { 757 if (is_literal_address(addr)) { 758 ShouldNotReachHere(); 759 __ movoop(as_Address(addr, noreg), c->as_jobject()); 760 } else { 761 #ifdef _LP64 762 __ movoop(rscratch1, c->as_jobject()); 763 null_check_here = code_offset(); 764 __ movptr(as_Address_lo(addr), rscratch1); 765 #else 766 __ movoop(as_Address(addr), c->as_jobject()); 767 #endif 768 } 769 } 770 break; 771 772 case T_LONG: // fall through 773 case T_DOUBLE: 774 #ifdef _LP64 775 if (is_literal_address(addr)) { 776 ShouldNotReachHere(); 777 __ movptr(as_Address(addr, r15_thread), (intptr_t)c->as_jlong_bits()); 778 } else { 779 __ movptr(r10, (intptr_t)c->as_jlong_bits()); 780 null_check_here = code_offset(); 781 __ movptr(as_Address_lo(addr), r10); 782 } 783 #else 784 // Always reachable in 32bit so this doesn't produce useless move literal 785 __ movptr(as_Address_hi(addr), c->as_jint_hi_bits()); 786 __ movptr(as_Address_lo(addr), c->as_jint_lo_bits()); 787 #endif // _LP64 788 break; 789 790 case T_BOOLEAN: // fall through 791 case T_BYTE: 792 __ movb(as_Address(addr), c->as_jint() & 0xFF); 793 break; 794 795 case T_CHAR: // fall through 796 case T_SHORT: 797 __ movw(as_Address(addr), c->as_jint() & 0xFFFF); 798 break; 799 800 default: 801 ShouldNotReachHere(); 802 }; 803 804 if (info != NULL) { 805 add_debug_info_for_null_check(null_check_here, info); 806 } 807 } 808 809 810 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) { 811 assert(src->is_register(), "should not call otherwise"); 812 assert(dest->is_register(), "should not call otherwise"); 813 814 // move between cpu-registers 815 if (dest->is_single_cpu()) { 816 #ifdef _LP64 817 if (src->type() == T_LONG) { 818 // Can do LONG -> OBJECT 819 move_regs(src->as_register_lo(), dest->as_register()); 820 return; 821 } 822 #endif 823 assert(src->is_single_cpu(), "must match"); 824 if (src->type() == T_OBJECT) { 825 __ verify_oop(src->as_register()); 826 } 827 move_regs(src->as_register(), dest->as_register()); 828 829 } else if (dest->is_double_cpu()) { 830 #ifdef _LP64 831 if (src->type() == T_OBJECT || src->type() == T_ARRAY) { 832 // Surprising to me but we can see move of a long to t_object 833 __ verify_oop(src->as_register()); 834 move_regs(src->as_register(), dest->as_register_lo()); 835 return; 836 } 837 #endif 838 assert(src->is_double_cpu(), "must match"); 839 Register f_lo = src->as_register_lo(); 840 Register f_hi = src->as_register_hi(); 841 Register t_lo = dest->as_register_lo(); 842 Register t_hi = dest->as_register_hi(); 843 #ifdef _LP64 844 assert(f_hi == f_lo, "must be same"); 845 assert(t_hi == t_lo, "must be same"); 846 move_regs(f_lo, t_lo); 847 #else 848 assert(f_lo != f_hi && t_lo != t_hi, "invalid register allocation"); 849 850 851 if (f_lo == t_hi && f_hi == t_lo) { 852 swap_reg(f_lo, f_hi); 853 } else if (f_hi == t_lo) { 854 assert(f_lo != t_hi, "overwriting register"); 855 move_regs(f_hi, t_hi); 856 move_regs(f_lo, t_lo); 857 } else { 858 assert(f_hi != t_lo, "overwriting register"); 859 move_regs(f_lo, t_lo); 860 move_regs(f_hi, t_hi); 861 } 862 #endif // LP64 863 864 // special moves from fpu-register to xmm-register 865 // necessary for method results 866 } else if (src->is_single_xmm() && !dest->is_single_xmm()) { 867 __ movflt(Address(rsp, 0), src->as_xmm_float_reg()); 868 __ fld_s(Address(rsp, 0)); 869 } else if (src->is_double_xmm() && !dest->is_double_xmm()) { 870 __ movdbl(Address(rsp, 0), src->as_xmm_double_reg()); 871 __ fld_d(Address(rsp, 0)); 872 } else if (dest->is_single_xmm() && !src->is_single_xmm()) { 873 __ fstp_s(Address(rsp, 0)); 874 __ movflt(dest->as_xmm_float_reg(), Address(rsp, 0)); 875 } else if (dest->is_double_xmm() && !src->is_double_xmm()) { 876 __ fstp_d(Address(rsp, 0)); 877 __ movdbl(dest->as_xmm_double_reg(), Address(rsp, 0)); 878 879 // move between xmm-registers 880 } else if (dest->is_single_xmm()) { 881 assert(src->is_single_xmm(), "must match"); 882 __ movflt(dest->as_xmm_float_reg(), src->as_xmm_float_reg()); 883 } else if (dest->is_double_xmm()) { 884 assert(src->is_double_xmm(), "must match"); 885 __ movdbl(dest->as_xmm_double_reg(), src->as_xmm_double_reg()); 886 887 // move between fpu-registers (no instruction necessary because of fpu-stack) 888 } else if (dest->is_single_fpu() || dest->is_double_fpu()) { 889 assert(src->is_single_fpu() || src->is_double_fpu(), "must match"); 890 assert(src->fpu() == dest->fpu(), "currently should be nothing to do"); 891 } else { 892 ShouldNotReachHere(); 893 } 894 } 895 896 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) { 897 assert(src->is_register(), "should not call otherwise"); 898 assert(dest->is_stack(), "should not call otherwise"); 899 900 if (src->is_single_cpu()) { 901 Address dst = frame_map()->address_for_slot(dest->single_stack_ix()); 902 if (type == T_OBJECT || type == T_ARRAY) { 903 __ verify_oop(src->as_register()); 904 __ movptr (dst, src->as_register()); 905 } else { 906 __ movl (dst, src->as_register()); 907 } 908 909 } else if (src->is_double_cpu()) { 910 Address dstLO = frame_map()->address_for_slot(dest->double_stack_ix(), lo_word_offset_in_bytes); 911 Address dstHI = frame_map()->address_for_slot(dest->double_stack_ix(), hi_word_offset_in_bytes); 912 __ movptr (dstLO, src->as_register_lo()); 913 NOT_LP64(__ movptr (dstHI, src->as_register_hi())); 914 915 } else if (src->is_single_xmm()) { 916 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix()); 917 __ movflt(dst_addr, src->as_xmm_float_reg()); 918 919 } else if (src->is_double_xmm()) { 920 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix()); 921 __ movdbl(dst_addr, src->as_xmm_double_reg()); 922 923 } else if (src->is_single_fpu()) { 924 assert(src->fpu_regnr() == 0, "argument must be on TOS"); 925 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix()); 926 if (pop_fpu_stack) __ fstp_s (dst_addr); 927 else __ fst_s (dst_addr); 928 929 } else if (src->is_double_fpu()) { 930 assert(src->fpu_regnrLo() == 0, "argument must be on TOS"); 931 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix()); 932 if (pop_fpu_stack) __ fstp_d (dst_addr); 933 else __ fst_d (dst_addr); 934 935 } else { 936 ShouldNotReachHere(); 937 } 938 } 939 940 941 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool /* unaligned */) { 942 LIR_Address* to_addr = dest->as_address_ptr(); 943 PatchingStub* patch = NULL; 944 945 if (type == T_ARRAY || type == T_OBJECT) { 946 __ verify_oop(src->as_register()); 947 } 948 if (patch_code != lir_patch_none) { 949 patch = new PatchingStub(_masm, PatchingStub::access_field_id); 950 Address toa = as_Address(to_addr); 951 assert(toa.disp() != 0, "must have"); 952 } 953 if (info != NULL) { 954 add_debug_info_for_null_check_here(info); 955 } 956 957 switch (type) { 958 case T_FLOAT: { 959 if (src->is_single_xmm()) { 960 __ movflt(as_Address(to_addr), src->as_xmm_float_reg()); 961 } else { 962 assert(src->is_single_fpu(), "must be"); 963 assert(src->fpu_regnr() == 0, "argument must be on TOS"); 964 if (pop_fpu_stack) __ fstp_s(as_Address(to_addr)); 965 else __ fst_s (as_Address(to_addr)); 966 } 967 break; 968 } 969 970 case T_DOUBLE: { 971 if (src->is_double_xmm()) { 972 __ movdbl(as_Address(to_addr), src->as_xmm_double_reg()); 973 } else { 974 assert(src->is_double_fpu(), "must be"); 975 assert(src->fpu_regnrLo() == 0, "argument must be on TOS"); 976 if (pop_fpu_stack) __ fstp_d(as_Address(to_addr)); 977 else __ fst_d (as_Address(to_addr)); 978 } 979 break; 980 } 981 982 case T_ADDRESS: // fall through 983 case T_ARRAY: // fall through 984 case T_OBJECT: // fall through 985 #ifdef _LP64 986 __ movptr(as_Address(to_addr), src->as_register()); 987 break; 988 #endif // _LP64 989 case T_INT: 990 __ movl(as_Address(to_addr), src->as_register()); 991 break; 992 993 case T_LONG: { 994 Register from_lo = src->as_register_lo(); 995 Register from_hi = src->as_register_hi(); 996 #ifdef _LP64 997 __ movptr(as_Address_lo(to_addr), from_lo); 998 #else 999 Register base = to_addr->base()->as_register(); 1000 Register index = noreg; 1001 if (to_addr->index()->is_register()) { 1002 index = to_addr->index()->as_register(); 1003 } 1004 if (base == from_lo || index == from_lo) { 1005 assert(base != from_hi, "can't be"); 1006 assert(index == noreg || (index != base && index != from_hi), "can't handle this"); 1007 __ movl(as_Address_hi(to_addr), from_hi); 1008 if (patch != NULL) { 1009 patching_epilog(patch, lir_patch_high, base, info); 1010 patch = new PatchingStub(_masm, PatchingStub::access_field_id); 1011 patch_code = lir_patch_low; 1012 } 1013 __ movl(as_Address_lo(to_addr), from_lo); 1014 } else { 1015 assert(index == noreg || (index != base && index != from_lo), "can't handle this"); 1016 __ movl(as_Address_lo(to_addr), from_lo); 1017 if (patch != NULL) { 1018 patching_epilog(patch, lir_patch_low, base, info); 1019 patch = new PatchingStub(_masm, PatchingStub::access_field_id); 1020 patch_code = lir_patch_high; 1021 } 1022 __ movl(as_Address_hi(to_addr), from_hi); 1023 } 1024 #endif // _LP64 1025 break; 1026 } 1027 1028 case T_BYTE: // fall through 1029 case T_BOOLEAN: { 1030 Register src_reg = src->as_register(); 1031 Address dst_addr = as_Address(to_addr); 1032 assert(VM_Version::is_P6() || src_reg->has_byte_register(), "must use byte registers if not P6"); 1033 __ movb(dst_addr, src_reg); 1034 break; 1035 } 1036 1037 case T_CHAR: // fall through 1038 case T_SHORT: 1039 __ movw(as_Address(to_addr), src->as_register()); 1040 break; 1041 1042 default: 1043 ShouldNotReachHere(); 1044 } 1045 1046 if (patch_code != lir_patch_none) { 1047 patching_epilog(patch, patch_code, to_addr->base()->as_register(), info); 1048 } 1049 } 1050 1051 1052 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) { 1053 assert(src->is_stack(), "should not call otherwise"); 1054 assert(dest->is_register(), "should not call otherwise"); 1055 1056 if (dest->is_single_cpu()) { 1057 if (type == T_ARRAY || type == T_OBJECT) { 1058 __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix())); 1059 __ verify_oop(dest->as_register()); 1060 } else { 1061 __ movl(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix())); 1062 } 1063 1064 } else if (dest->is_double_cpu()) { 1065 Address src_addr_LO = frame_map()->address_for_slot(src->double_stack_ix(), lo_word_offset_in_bytes); 1066 Address src_addr_HI = frame_map()->address_for_slot(src->double_stack_ix(), hi_word_offset_in_bytes); 1067 __ movptr(dest->as_register_lo(), src_addr_LO); 1068 NOT_LP64(__ movptr(dest->as_register_hi(), src_addr_HI)); 1069 1070 } else if (dest->is_single_xmm()) { 1071 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix()); 1072 __ movflt(dest->as_xmm_float_reg(), src_addr); 1073 1074 } else if (dest->is_double_xmm()) { 1075 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix()); 1076 __ movdbl(dest->as_xmm_double_reg(), src_addr); 1077 1078 } else if (dest->is_single_fpu()) { 1079 assert(dest->fpu_regnr() == 0, "dest must be TOS"); 1080 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix()); 1081 __ fld_s(src_addr); 1082 1083 } else if (dest->is_double_fpu()) { 1084 assert(dest->fpu_regnrLo() == 0, "dest must be TOS"); 1085 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix()); 1086 __ fld_d(src_addr); 1087 1088 } else { 1089 ShouldNotReachHere(); 1090 } 1091 } 1092 1093 1094 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) { 1095 if (src->is_single_stack()) { 1096 if (type == T_OBJECT || type == T_ARRAY) { 1097 __ pushptr(frame_map()->address_for_slot(src ->single_stack_ix())); 1098 __ popptr (frame_map()->address_for_slot(dest->single_stack_ix())); 1099 } else { 1100 #ifndef _LP64 1101 __ pushl(frame_map()->address_for_slot(src ->single_stack_ix())); 1102 __ popl (frame_map()->address_for_slot(dest->single_stack_ix())); 1103 #else 1104 //no pushl on 64bits 1105 __ movl(rscratch1, frame_map()->address_for_slot(src ->single_stack_ix())); 1106 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), rscratch1); 1107 #endif 1108 } 1109 1110 } else if (src->is_double_stack()) { 1111 #ifdef _LP64 1112 __ pushptr(frame_map()->address_for_slot(src ->double_stack_ix())); 1113 __ popptr (frame_map()->address_for_slot(dest->double_stack_ix())); 1114 #else 1115 __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 0)); 1116 // push and pop the part at src + wordSize, adding wordSize for the previous push 1117 __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 2 * wordSize)); 1118 __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 2 * wordSize)); 1119 __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 0)); 1120 #endif // _LP64 1121 1122 } else { 1123 ShouldNotReachHere(); 1124 } 1125 } 1126 1127 1128 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool /* unaligned */) { 1129 assert(src->is_address(), "should not call otherwise"); 1130 assert(dest->is_register(), "should not call otherwise"); 1131 1132 LIR_Address* addr = src->as_address_ptr(); 1133 Address from_addr = as_Address(addr); 1134 1135 switch (type) { 1136 case T_BOOLEAN: // fall through 1137 case T_BYTE: // fall through 1138 case T_CHAR: // fall through 1139 case T_SHORT: 1140 if (!VM_Version::is_P6() && !from_addr.uses(dest->as_register())) { 1141 // on pre P6 processors we may get partial register stalls 1142 // so blow away the value of to_rinfo before loading a 1143 // partial word into it. Do it here so that it precedes 1144 // the potential patch point below. 1145 __ xorptr(dest->as_register(), dest->as_register()); 1146 } 1147 break; 1148 } 1149 1150 PatchingStub* patch = NULL; 1151 if (patch_code != lir_patch_none) { 1152 patch = new PatchingStub(_masm, PatchingStub::access_field_id); 1153 assert(from_addr.disp() != 0, "must have"); 1154 } 1155 if (info != NULL) { 1156 add_debug_info_for_null_check_here(info); 1157 } 1158 1159 switch (type) { 1160 case T_FLOAT: { 1161 if (dest->is_single_xmm()) { 1162 __ movflt(dest->as_xmm_float_reg(), from_addr); 1163 } else { 1164 assert(dest->is_single_fpu(), "must be"); 1165 assert(dest->fpu_regnr() == 0, "dest must be TOS"); 1166 __ fld_s(from_addr); 1167 } 1168 break; 1169 } 1170 1171 case T_DOUBLE: { 1172 if (dest->is_double_xmm()) { 1173 __ movdbl(dest->as_xmm_double_reg(), from_addr); 1174 } else { 1175 assert(dest->is_double_fpu(), "must be"); 1176 assert(dest->fpu_regnrLo() == 0, "dest must be TOS"); 1177 __ fld_d(from_addr); 1178 } 1179 break; 1180 } 1181 1182 case T_ADDRESS: // fall through 1183 case T_OBJECT: // fall through 1184 case T_ARRAY: // fall through 1185 #ifdef _LP64 1186 __ movptr(dest->as_register(), from_addr); 1187 break; 1188 #endif // _L64 1189 case T_INT: 1190 // %%% could this be a movl? this is safer but longer instruction 1191 __ movl2ptr(dest->as_register(), from_addr); 1192 break; 1193 1194 case T_LONG: { 1195 Register to_lo = dest->as_register_lo(); 1196 Register to_hi = dest->as_register_hi(); 1197 #ifdef _LP64 1198 __ movptr(to_lo, as_Address_lo(addr)); 1199 #else 1200 Register base = addr->base()->as_register(); 1201 Register index = noreg; 1202 if (addr->index()->is_register()) { 1203 index = addr->index()->as_register(); 1204 } 1205 if ((base == to_lo && index == to_hi) || 1206 (base == to_hi && index == to_lo)) { 1207 // addresses with 2 registers are only formed as a result of 1208 // array access so this code will never have to deal with 1209 // patches or null checks. 1210 assert(info == NULL && patch == NULL, "must be"); 1211 __ lea(to_hi, as_Address(addr)); 1212 __ movl(to_lo, Address(to_hi, 0)); 1213 __ movl(to_hi, Address(to_hi, BytesPerWord)); 1214 } else if (base == to_lo || index == to_lo) { 1215 assert(base != to_hi, "can't be"); 1216 assert(index == noreg || (index != base && index != to_hi), "can't handle this"); 1217 __ movl(to_hi, as_Address_hi(addr)); 1218 if (patch != NULL) { 1219 patching_epilog(patch, lir_patch_high, base, info); 1220 patch = new PatchingStub(_masm, PatchingStub::access_field_id); 1221 patch_code = lir_patch_low; 1222 } 1223 __ movl(to_lo, as_Address_lo(addr)); 1224 } else { 1225 assert(index == noreg || (index != base && index != to_lo), "can't handle this"); 1226 __ movl(to_lo, as_Address_lo(addr)); 1227 if (patch != NULL) { 1228 patching_epilog(patch, lir_patch_low, base, info); 1229 patch = new PatchingStub(_masm, PatchingStub::access_field_id); 1230 patch_code = lir_patch_high; 1231 } 1232 __ movl(to_hi, as_Address_hi(addr)); 1233 } 1234 #endif // _LP64 1235 break; 1236 } 1237 1238 case T_BOOLEAN: // fall through 1239 case T_BYTE: { 1240 Register dest_reg = dest->as_register(); 1241 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6"); 1242 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) { 1243 __ movsbl(dest_reg, from_addr); 1244 } else { 1245 __ movb(dest_reg, from_addr); 1246 __ shll(dest_reg, 24); 1247 __ sarl(dest_reg, 24); 1248 } 1249 // These are unsigned so the zero extension on 64bit is just what we need 1250 break; 1251 } 1252 1253 case T_CHAR: { 1254 Register dest_reg = dest->as_register(); 1255 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6"); 1256 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) { 1257 __ movzwl(dest_reg, from_addr); 1258 } else { 1259 __ movw(dest_reg, from_addr); 1260 } 1261 // This is unsigned so the zero extension on 64bit is just what we need 1262 // __ movl2ptr(dest_reg, dest_reg); 1263 break; 1264 } 1265 1266 case T_SHORT: { 1267 Register dest_reg = dest->as_register(); 1268 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) { 1269 __ movswl(dest_reg, from_addr); 1270 } else { 1271 __ movw(dest_reg, from_addr); 1272 __ shll(dest_reg, 16); 1273 __ sarl(dest_reg, 16); 1274 } 1275 // Might not be needed in 64bit but certainly doesn't hurt (except for code size) 1276 __ movl2ptr(dest_reg, dest_reg); 1277 break; 1278 } 1279 1280 default: 1281 ShouldNotReachHere(); 1282 } 1283 1284 if (patch != NULL) { 1285 patching_epilog(patch, patch_code, addr->base()->as_register(), info); 1286 } 1287 1288 if (type == T_ARRAY || type == T_OBJECT) { 1289 __ verify_oop(dest->as_register()); 1290 } 1291 } 1292 1293 1294 void LIR_Assembler::prefetchr(LIR_Opr src) { 1295 LIR_Address* addr = src->as_address_ptr(); 1296 Address from_addr = as_Address(addr); 1297 1298 if (VM_Version::supports_sse()) { 1299 switch (ReadPrefetchInstr) { 1300 case 0: 1301 __ prefetchnta(from_addr); break; 1302 case 1: 1303 __ prefetcht0(from_addr); break; 1304 case 2: 1305 __ prefetcht2(from_addr); break; 1306 default: 1307 ShouldNotReachHere(); break; 1308 } 1309 } else if (VM_Version::supports_3dnow()) { 1310 __ prefetchr(from_addr); 1311 } 1312 } 1313 1314 1315 void LIR_Assembler::prefetchw(LIR_Opr src) { 1316 LIR_Address* addr = src->as_address_ptr(); 1317 Address from_addr = as_Address(addr); 1318 1319 if (VM_Version::supports_sse()) { 1320 switch (AllocatePrefetchInstr) { 1321 case 0: 1322 __ prefetchnta(from_addr); break; 1323 case 1: 1324 __ prefetcht0(from_addr); break; 1325 case 2: 1326 __ prefetcht2(from_addr); break; 1327 case 3: 1328 __ prefetchw(from_addr); break; 1329 default: 1330 ShouldNotReachHere(); break; 1331 } 1332 } else if (VM_Version::supports_3dnow()) { 1333 __ prefetchw(from_addr); 1334 } 1335 } 1336 1337 1338 NEEDS_CLEANUP; // This could be static? 1339 Address::ScaleFactor LIR_Assembler::array_element_size(BasicType type) const { 1340 int elem_size = type2aelembytes(type); 1341 switch (elem_size) { 1342 case 1: return Address::times_1; 1343 case 2: return Address::times_2; 1344 case 4: return Address::times_4; 1345 case 8: return Address::times_8; 1346 } 1347 ShouldNotReachHere(); 1348 return Address::no_scale; 1349 } 1350 1351 1352 void LIR_Assembler::emit_op3(LIR_Op3* op) { 1353 switch (op->code()) { 1354 case lir_idiv: 1355 case lir_irem: 1356 arithmetic_idiv(op->code(), 1357 op->in_opr1(), 1358 op->in_opr2(), 1359 op->in_opr3(), 1360 op->result_opr(), 1361 op->info()); 1362 break; 1363 default: ShouldNotReachHere(); break; 1364 } 1365 } 1366 1367 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) { 1368 #ifdef ASSERT 1369 assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label"); 1370 if (op->block() != NULL) _branch_target_blocks.append(op->block()); 1371 if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock()); 1372 #endif 1373 1374 if (op->cond() == lir_cond_always) { 1375 if (op->info() != NULL) add_debug_info_for_branch(op->info()); 1376 __ jmp (*(op->label())); 1377 } else { 1378 Assembler::Condition acond = Assembler::zero; 1379 if (op->code() == lir_cond_float_branch) { 1380 assert(op->ublock() != NULL, "must have unordered successor"); 1381 __ jcc(Assembler::parity, *(op->ublock()->label())); 1382 switch(op->cond()) { 1383 case lir_cond_equal: acond = Assembler::equal; break; 1384 case lir_cond_notEqual: acond = Assembler::notEqual; break; 1385 case lir_cond_less: acond = Assembler::below; break; 1386 case lir_cond_lessEqual: acond = Assembler::belowEqual; break; 1387 case lir_cond_greaterEqual: acond = Assembler::aboveEqual; break; 1388 case lir_cond_greater: acond = Assembler::above; break; 1389 default: ShouldNotReachHere(); 1390 } 1391 } else { 1392 switch (op->cond()) { 1393 case lir_cond_equal: acond = Assembler::equal; break; 1394 case lir_cond_notEqual: acond = Assembler::notEqual; break; 1395 case lir_cond_less: acond = Assembler::less; break; 1396 case lir_cond_lessEqual: acond = Assembler::lessEqual; break; 1397 case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break; 1398 case lir_cond_greater: acond = Assembler::greater; break; 1399 case lir_cond_belowEqual: acond = Assembler::belowEqual; break; 1400 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; break; 1401 default: ShouldNotReachHere(); 1402 } 1403 } 1404 __ jcc(acond,*(op->label())); 1405 } 1406 } 1407 1408 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) { 1409 LIR_Opr src = op->in_opr(); 1410 LIR_Opr dest = op->result_opr(); 1411 1412 switch (op->bytecode()) { 1413 case Bytecodes::_i2l: 1414 #ifdef _LP64 1415 __ movl2ptr(dest->as_register_lo(), src->as_register()); 1416 #else 1417 move_regs(src->as_register(), dest->as_register_lo()); 1418 move_regs(src->as_register(), dest->as_register_hi()); 1419 __ sarl(dest->as_register_hi(), 31); 1420 #endif // LP64 1421 break; 1422 1423 case Bytecodes::_l2i: 1424 move_regs(src->as_register_lo(), dest->as_register()); 1425 break; 1426 1427 case Bytecodes::_i2b: 1428 move_regs(src->as_register(), dest->as_register()); 1429 __ sign_extend_byte(dest->as_register()); 1430 break; 1431 1432 case Bytecodes::_i2c: 1433 move_regs(src->as_register(), dest->as_register()); 1434 __ andl(dest->as_register(), 0xFFFF); 1435 break; 1436 1437 case Bytecodes::_i2s: 1438 move_regs(src->as_register(), dest->as_register()); 1439 __ sign_extend_short(dest->as_register()); 1440 break; 1441 1442 1443 case Bytecodes::_f2d: 1444 case Bytecodes::_d2f: 1445 if (dest->is_single_xmm()) { 1446 __ cvtsd2ss(dest->as_xmm_float_reg(), src->as_xmm_double_reg()); 1447 } else if (dest->is_double_xmm()) { 1448 __ cvtss2sd(dest->as_xmm_double_reg(), src->as_xmm_float_reg()); 1449 } else { 1450 assert(src->fpu() == dest->fpu(), "register must be equal"); 1451 // do nothing (float result is rounded later through spilling) 1452 } 1453 break; 1454 1455 case Bytecodes::_i2f: 1456 case Bytecodes::_i2d: 1457 if (dest->is_single_xmm()) { 1458 __ cvtsi2ssl(dest->as_xmm_float_reg(), src->as_register()); 1459 } else if (dest->is_double_xmm()) { 1460 __ cvtsi2sdl(dest->as_xmm_double_reg(), src->as_register()); 1461 } else { 1462 assert(dest->fpu() == 0, "result must be on TOS"); 1463 __ movl(Address(rsp, 0), src->as_register()); 1464 __ fild_s(Address(rsp, 0)); 1465 } 1466 break; 1467 1468 case Bytecodes::_f2i: 1469 case Bytecodes::_d2i: 1470 if (src->is_single_xmm()) { 1471 __ cvttss2sil(dest->as_register(), src->as_xmm_float_reg()); 1472 } else if (src->is_double_xmm()) { 1473 __ cvttsd2sil(dest->as_register(), src->as_xmm_double_reg()); 1474 } else { 1475 assert(src->fpu() == 0, "input must be on TOS"); 1476 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc())); 1477 __ fist_s(Address(rsp, 0)); 1478 __ movl(dest->as_register(), Address(rsp, 0)); 1479 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std())); 1480 } 1481 1482 // IA32 conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub 1483 assert(op->stub() != NULL, "stub required"); 1484 __ cmpl(dest->as_register(), 0x80000000); 1485 __ jcc(Assembler::equal, *op->stub()->entry()); 1486 __ bind(*op->stub()->continuation()); 1487 break; 1488 1489 case Bytecodes::_l2f: 1490 case Bytecodes::_l2d: 1491 assert(!dest->is_xmm_register(), "result in xmm register not supported (no SSE instruction present)"); 1492 assert(dest->fpu() == 0, "result must be on TOS"); 1493 1494 __ movptr(Address(rsp, 0), src->as_register_lo()); 1495 NOT_LP64(__ movl(Address(rsp, BytesPerWord), src->as_register_hi())); 1496 __ fild_d(Address(rsp, 0)); 1497 // float result is rounded later through spilling 1498 break; 1499 1500 case Bytecodes::_f2l: 1501 case Bytecodes::_d2l: 1502 assert(!src->is_xmm_register(), "input in xmm register not supported (no SSE instruction present)"); 1503 assert(src->fpu() == 0, "input must be on TOS"); 1504 assert(dest == FrameMap::long0_opr, "runtime stub places result in these registers"); 1505 1506 // instruction sequence too long to inline it here 1507 { 1508 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::fpu2long_stub_id))); 1509 } 1510 break; 1511 1512 default: ShouldNotReachHere(); 1513 } 1514 } 1515 1516 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) { 1517 if (op->init_check()) { 1518 __ cmpl(Address(op->klass()->as_register(), 1519 instanceKlass::init_state_offset_in_bytes() + sizeof(oopDesc)), 1520 instanceKlass::fully_initialized); 1521 add_debug_info_for_null_check_here(op->stub()->info()); 1522 __ jcc(Assembler::notEqual, *op->stub()->entry()); 1523 } 1524 __ allocate_object(op->obj()->as_register(), 1525 op->tmp1()->as_register(), 1526 op->tmp2()->as_register(), 1527 op->header_size(), 1528 op->object_size(), 1529 op->klass()->as_register(), 1530 *op->stub()->entry()); 1531 __ bind(*op->stub()->continuation()); 1532 } 1533 1534 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) { 1535 if (UseSlowPath || 1536 (!UseFastNewObjectArray && (op->type() == T_OBJECT || op->type() == T_ARRAY)) || 1537 (!UseFastNewTypeArray && (op->type() != T_OBJECT && op->type() != T_ARRAY))) { 1538 __ jmp(*op->stub()->entry()); 1539 } else { 1540 Register len = op->len()->as_register(); 1541 Register tmp1 = op->tmp1()->as_register(); 1542 Register tmp2 = op->tmp2()->as_register(); 1543 Register tmp3 = op->tmp3()->as_register(); 1544 if (len == tmp1) { 1545 tmp1 = tmp3; 1546 } else if (len == tmp2) { 1547 tmp2 = tmp3; 1548 } else if (len == tmp3) { 1549 // everything is ok 1550 } else { 1551 __ mov(tmp3, len); 1552 } 1553 __ allocate_array(op->obj()->as_register(), 1554 len, 1555 tmp1, 1556 tmp2, 1557 arrayOopDesc::header_size(op->type()), 1558 array_element_size(op->type()), 1559 op->klass()->as_register(), 1560 *op->stub()->entry()); 1561 } 1562 __ bind(*op->stub()->continuation()); 1563 } 1564 1565 1566 1567 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) { 1568 LIR_Code code = op->code(); 1569 if (code == lir_store_check) { 1570 Register value = op->object()->as_register(); 1571 Register array = op->array()->as_register(); 1572 Register k_RInfo = op->tmp1()->as_register(); 1573 Register klass_RInfo = op->tmp2()->as_register(); 1574 Register Rtmp1 = op->tmp3()->as_register(); 1575 1576 CodeStub* stub = op->stub(); 1577 Label done; 1578 __ cmpptr(value, (int32_t)NULL_WORD); 1579 __ jcc(Assembler::equal, done); 1580 add_debug_info_for_null_check_here(op->info_for_exception()); 1581 __ movptr(k_RInfo, Address(array, oopDesc::klass_offset_in_bytes())); 1582 __ movptr(klass_RInfo, Address(value, oopDesc::klass_offset_in_bytes())); 1583 1584 // get instance klass 1585 __ movptr(k_RInfo, Address(k_RInfo, objArrayKlass::element_klass_offset_in_bytes() + sizeof(oopDesc))); 1586 // perform the fast part of the checking logic 1587 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, &done, stub->entry(), NULL); 1588 // call out-of-line instance of __ check_klass_subtype_slow_path(...): 1589 __ push(klass_RInfo); 1590 __ push(k_RInfo); 1591 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); 1592 __ pop(klass_RInfo); 1593 __ pop(k_RInfo); 1594 // result is a boolean 1595 __ cmpl(k_RInfo, 0); 1596 __ jcc(Assembler::equal, *stub->entry()); 1597 __ bind(done); 1598 } else if (op->code() == lir_checkcast) { 1599 // we always need a stub for the failure case. 1600 CodeStub* stub = op->stub(); 1601 Register obj = op->object()->as_register(); 1602 Register k_RInfo = op->tmp1()->as_register(); 1603 Register klass_RInfo = op->tmp2()->as_register(); 1604 Register dst = op->result_opr()->as_register(); 1605 ciKlass* k = op->klass(); 1606 Register Rtmp1 = noreg; 1607 1608 Label done; 1609 if (obj == k_RInfo) { 1610 k_RInfo = dst; 1611 } else if (obj == klass_RInfo) { 1612 klass_RInfo = dst; 1613 } 1614 if (k->is_loaded()) { 1615 select_different_registers(obj, dst, k_RInfo, klass_RInfo); 1616 } else { 1617 Rtmp1 = op->tmp3()->as_register(); 1618 select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1); 1619 } 1620 1621 assert_different_registers(obj, k_RInfo, klass_RInfo); 1622 if (!k->is_loaded()) { 1623 jobject2reg_with_patching(k_RInfo, op->info_for_patch()); 1624 } else { 1625 #ifdef _LP64 1626 __ movoop(k_RInfo, k->constant_encoding()); 1627 #else 1628 k_RInfo = noreg; 1629 #endif // _LP64 1630 } 1631 assert(obj != k_RInfo, "must be different"); 1632 __ cmpptr(obj, (int32_t)NULL_WORD); 1633 if (op->profiled_method() != NULL) { 1634 ciMethod* method = op->profiled_method(); 1635 int bci = op->profiled_bci(); 1636 1637 Label profile_done; 1638 __ jcc(Assembler::notEqual, profile_done); 1639 // Object is null; update methodDataOop 1640 ciMethodData* md = method->method_data(); 1641 if (md == NULL) { 1642 bailout("out of memory building methodDataOop"); 1643 return; 1644 } 1645 ciProfileData* data = md->bci_to_data(bci); 1646 assert(data != NULL, "need data for checkcast"); 1647 assert(data->is_BitData(), "need BitData for checkcast"); 1648 Register mdo = klass_RInfo; 1649 __ movoop(mdo, md->constant_encoding()); 1650 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::header_offset())); 1651 int header_bits = DataLayout::flag_mask_to_header_mask(BitData::null_seen_byte_constant()); 1652 __ orl(data_addr, header_bits); 1653 __ jmp(done); 1654 __ bind(profile_done); 1655 } else { 1656 __ jcc(Assembler::equal, done); 1657 } 1658 __ verify_oop(obj); 1659 1660 if (op->fast_check()) { 1661 // get object classo 1662 // not a safepoint as obj null check happens earlier 1663 if (k->is_loaded()) { 1664 #ifdef _LP64 1665 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes())); 1666 #else 1667 __ cmpoop(Address(obj, oopDesc::klass_offset_in_bytes()), k->constant_encoding()); 1668 #endif // _LP64 1669 } else { 1670 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes())); 1671 1672 } 1673 __ jcc(Assembler::notEqual, *stub->entry()); 1674 __ bind(done); 1675 } else { 1676 // get object class 1677 // not a safepoint as obj null check happens earlier 1678 __ movptr(klass_RInfo, Address(obj, oopDesc::klass_offset_in_bytes())); 1679 if (k->is_loaded()) { 1680 // See if we get an immediate positive hit 1681 #ifdef _LP64 1682 __ cmpptr(k_RInfo, Address(klass_RInfo, k->super_check_offset())); 1683 #else 1684 __ cmpoop(Address(klass_RInfo, k->super_check_offset()), k->constant_encoding()); 1685 #endif // _LP64 1686 if (sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes() != k->super_check_offset()) { 1687 __ jcc(Assembler::notEqual, *stub->entry()); 1688 } else { 1689 // See if we get an immediate positive hit 1690 __ jcc(Assembler::equal, done); 1691 // check for self 1692 #ifdef _LP64 1693 __ cmpptr(klass_RInfo, k_RInfo); 1694 #else 1695 __ cmpoop(klass_RInfo, k->constant_encoding()); 1696 #endif // _LP64 1697 __ jcc(Assembler::equal, done); 1698 1699 __ push(klass_RInfo); 1700 #ifdef _LP64 1701 __ push(k_RInfo); 1702 #else 1703 __ pushoop(k->constant_encoding()); 1704 #endif // _LP64 1705 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); 1706 __ pop(klass_RInfo); 1707 __ pop(klass_RInfo); 1708 // result is a boolean 1709 __ cmpl(klass_RInfo, 0); 1710 __ jcc(Assembler::equal, *stub->entry()); 1711 } 1712 __ bind(done); 1713 } else { 1714 // perform the fast part of the checking logic 1715 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, &done, stub->entry(), NULL); 1716 // call out-of-line instance of __ check_klass_subtype_slow_path(...): 1717 __ push(klass_RInfo); 1718 __ push(k_RInfo); 1719 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); 1720 __ pop(klass_RInfo); 1721 __ pop(k_RInfo); 1722 // result is a boolean 1723 __ cmpl(k_RInfo, 0); 1724 __ jcc(Assembler::equal, *stub->entry()); 1725 __ bind(done); 1726 } 1727 1728 } 1729 if (dst != obj) { 1730 __ mov(dst, obj); 1731 } 1732 } else if (code == lir_instanceof) { 1733 Register obj = op->object()->as_register(); 1734 Register k_RInfo = op->tmp1()->as_register(); 1735 Register klass_RInfo = op->tmp2()->as_register(); 1736 Register dst = op->result_opr()->as_register(); 1737 ciKlass* k = op->klass(); 1738 1739 Label done; 1740 Label zero; 1741 Label one; 1742 if (obj == k_RInfo) { 1743 k_RInfo = klass_RInfo; 1744 klass_RInfo = obj; 1745 } 1746 // patching may screw with our temporaries on sparc, 1747 // so let's do it before loading the class 1748 if (!k->is_loaded()) { 1749 jobject2reg_with_patching(k_RInfo, op->info_for_patch()); 1750 } else { 1751 LP64_ONLY(__ movoop(k_RInfo, k->constant_encoding())); 1752 } 1753 assert(obj != k_RInfo, "must be different"); 1754 1755 __ verify_oop(obj); 1756 if (op->fast_check()) { 1757 __ cmpptr(obj, (int32_t)NULL_WORD); 1758 __ jcc(Assembler::equal, zero); 1759 // get object class 1760 // not a safepoint as obj null check happens earlier 1761 if (LP64_ONLY(false &&) k->is_loaded()) { 1762 NOT_LP64(__ cmpoop(Address(obj, oopDesc::klass_offset_in_bytes()), k->constant_encoding())); 1763 k_RInfo = noreg; 1764 } else { 1765 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes())); 1766 1767 } 1768 __ jcc(Assembler::equal, one); 1769 } else { 1770 // get object class 1771 // not a safepoint as obj null check happens earlier 1772 __ cmpptr(obj, (int32_t)NULL_WORD); 1773 __ jcc(Assembler::equal, zero); 1774 __ movptr(klass_RInfo, Address(obj, oopDesc::klass_offset_in_bytes())); 1775 1776 #ifndef _LP64 1777 if (k->is_loaded()) { 1778 // See if we get an immediate positive hit 1779 __ cmpoop(Address(klass_RInfo, k->super_check_offset()), k->constant_encoding()); 1780 __ jcc(Assembler::equal, one); 1781 if (sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes() == k->super_check_offset()) { 1782 // check for self 1783 __ cmpoop(klass_RInfo, k->constant_encoding()); 1784 __ jcc(Assembler::equal, one); 1785 __ push(klass_RInfo); 1786 __ pushoop(k->constant_encoding()); 1787 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); 1788 __ pop(klass_RInfo); 1789 __ pop(dst); 1790 __ jmp(done); 1791 } 1792 } 1793 else // next block is unconditional if LP64: 1794 #endif // LP64 1795 { 1796 assert(dst != klass_RInfo && dst != k_RInfo, "need 3 registers"); 1797 1798 // perform the fast part of the checking logic 1799 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, dst, &one, &zero, NULL); 1800 // call out-of-line instance of __ check_klass_subtype_slow_path(...): 1801 __ push(klass_RInfo); 1802 __ push(k_RInfo); 1803 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); 1804 __ pop(klass_RInfo); 1805 __ pop(dst); 1806 __ jmp(done); 1807 } 1808 } 1809 __ bind(zero); 1810 __ xorptr(dst, dst); 1811 __ jmp(done); 1812 __ bind(one); 1813 __ movptr(dst, 1); 1814 __ bind(done); 1815 } else { 1816 ShouldNotReachHere(); 1817 } 1818 1819 } 1820 1821 1822 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) { 1823 if (LP64_ONLY(false &&) op->code() == lir_cas_long && VM_Version::supports_cx8()) { 1824 assert(op->cmp_value()->as_register_lo() == rax, "wrong register"); 1825 assert(op->cmp_value()->as_register_hi() == rdx, "wrong register"); 1826 assert(op->new_value()->as_register_lo() == rbx, "wrong register"); 1827 assert(op->new_value()->as_register_hi() == rcx, "wrong register"); 1828 Register addr = op->addr()->as_register(); 1829 if (os::is_MP()) { 1830 __ lock(); 1831 } 1832 NOT_LP64(__ cmpxchg8(Address(addr, 0))); 1833 1834 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj ) { 1835 NOT_LP64(assert(op->addr()->is_single_cpu(), "must be single");) 1836 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo()); 1837 Register newval = op->new_value()->as_register(); 1838 Register cmpval = op->cmp_value()->as_register(); 1839 assert(cmpval == rax, "wrong register"); 1840 assert(newval != NULL, "new val must be register"); 1841 assert(cmpval != newval, "cmp and new values must be in different registers"); 1842 assert(cmpval != addr, "cmp and addr must be in different registers"); 1843 assert(newval != addr, "new value and addr must be in different registers"); 1844 if (os::is_MP()) { 1845 __ lock(); 1846 } 1847 if ( op->code() == lir_cas_obj) { 1848 __ cmpxchgptr(newval, Address(addr, 0)); 1849 } else if (op->code() == lir_cas_int) { 1850 __ cmpxchgl(newval, Address(addr, 0)); 1851 } else { 1852 LP64_ONLY(__ cmpxchgq(newval, Address(addr, 0))); 1853 } 1854 #ifdef _LP64 1855 } else if (op->code() == lir_cas_long) { 1856 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo()); 1857 Register newval = op->new_value()->as_register_lo(); 1858 Register cmpval = op->cmp_value()->as_register_lo(); 1859 assert(cmpval == rax, "wrong register"); 1860 assert(newval != NULL, "new val must be register"); 1861 assert(cmpval != newval, "cmp and new values must be in different registers"); 1862 assert(cmpval != addr, "cmp and addr must be in different registers"); 1863 assert(newval != addr, "new value and addr must be in different registers"); 1864 if (os::is_MP()) { 1865 __ lock(); 1866 } 1867 __ cmpxchgq(newval, Address(addr, 0)); 1868 #endif // _LP64 1869 } else { 1870 Unimplemented(); 1871 } 1872 } 1873 1874 1875 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result) { 1876 Assembler::Condition acond, ncond; 1877 switch (condition) { 1878 case lir_cond_equal: acond = Assembler::equal; ncond = Assembler::notEqual; break; 1879 case lir_cond_notEqual: acond = Assembler::notEqual; ncond = Assembler::equal; break; 1880 case lir_cond_less: acond = Assembler::less; ncond = Assembler::greaterEqual; break; 1881 case lir_cond_lessEqual: acond = Assembler::lessEqual; ncond = Assembler::greater; break; 1882 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; ncond = Assembler::less; break; 1883 case lir_cond_greater: acond = Assembler::greater; ncond = Assembler::lessEqual; break; 1884 case lir_cond_belowEqual: acond = Assembler::belowEqual; ncond = Assembler::above; break; 1885 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; ncond = Assembler::below; break; 1886 default: ShouldNotReachHere(); 1887 } 1888 1889 if (opr1->is_cpu_register()) { 1890 reg2reg(opr1, result); 1891 } else if (opr1->is_stack()) { 1892 stack2reg(opr1, result, result->type()); 1893 } else if (opr1->is_constant()) { 1894 const2reg(opr1, result, lir_patch_none, NULL); 1895 } else { 1896 ShouldNotReachHere(); 1897 } 1898 1899 if (VM_Version::supports_cmov() && !opr2->is_constant()) { 1900 // optimized version that does not require a branch 1901 if (opr2->is_single_cpu()) { 1902 assert(opr2->cpu_regnr() != result->cpu_regnr(), "opr2 already overwritten by previous move"); 1903 __ cmov(ncond, result->as_register(), opr2->as_register()); 1904 } else if (opr2->is_double_cpu()) { 1905 assert(opr2->cpu_regnrLo() != result->cpu_regnrLo() && opr2->cpu_regnrLo() != result->cpu_regnrHi(), "opr2 already overwritten by previous move"); 1906 assert(opr2->cpu_regnrHi() != result->cpu_regnrLo() && opr2->cpu_regnrHi() != result->cpu_regnrHi(), "opr2 already overwritten by previous move"); 1907 __ cmovptr(ncond, result->as_register_lo(), opr2->as_register_lo()); 1908 NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), opr2->as_register_hi());) 1909 } else if (opr2->is_single_stack()) { 1910 __ cmovl(ncond, result->as_register(), frame_map()->address_for_slot(opr2->single_stack_ix())); 1911 } else if (opr2->is_double_stack()) { 1912 __ cmovptr(ncond, result->as_register_lo(), frame_map()->address_for_slot(opr2->double_stack_ix(), lo_word_offset_in_bytes)); 1913 NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), frame_map()->address_for_slot(opr2->double_stack_ix(), hi_word_offset_in_bytes));) 1914 } else { 1915 ShouldNotReachHere(); 1916 } 1917 1918 } else { 1919 Label skip; 1920 __ jcc (acond, skip); 1921 if (opr2->is_cpu_register()) { 1922 reg2reg(opr2, result); 1923 } else if (opr2->is_stack()) { 1924 stack2reg(opr2, result, result->type()); 1925 } else if (opr2->is_constant()) { 1926 const2reg(opr2, result, lir_patch_none, NULL); 1927 } else { 1928 ShouldNotReachHere(); 1929 } 1930 __ bind(skip); 1931 } 1932 } 1933 1934 1935 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) { 1936 assert(info == NULL, "should never be used, idiv/irem and ldiv/lrem not handled by this method"); 1937 1938 if (left->is_single_cpu()) { 1939 assert(left == dest, "left and dest must be equal"); 1940 Register lreg = left->as_register(); 1941 1942 if (right->is_single_cpu()) { 1943 // cpu register - cpu register 1944 Register rreg = right->as_register(); 1945 switch (code) { 1946 case lir_add: __ addl (lreg, rreg); break; 1947 case lir_sub: __ subl (lreg, rreg); break; 1948 case lir_mul: __ imull(lreg, rreg); break; 1949 default: ShouldNotReachHere(); 1950 } 1951 1952 } else if (right->is_stack()) { 1953 // cpu register - stack 1954 Address raddr = frame_map()->address_for_slot(right->single_stack_ix()); 1955 switch (code) { 1956 case lir_add: __ addl(lreg, raddr); break; 1957 case lir_sub: __ subl(lreg, raddr); break; 1958 default: ShouldNotReachHere(); 1959 } 1960 1961 } else if (right->is_constant()) { 1962 // cpu register - constant 1963 jint c = right->as_constant_ptr()->as_jint(); 1964 switch (code) { 1965 case lir_add: { 1966 __ increment(lreg, c); 1967 break; 1968 } 1969 case lir_sub: { 1970 __ decrement(lreg, c); 1971 break; 1972 } 1973 default: ShouldNotReachHere(); 1974 } 1975 1976 } else { 1977 ShouldNotReachHere(); 1978 } 1979 1980 } else if (left->is_double_cpu()) { 1981 assert(left == dest, "left and dest must be equal"); 1982 Register lreg_lo = left->as_register_lo(); 1983 Register lreg_hi = left->as_register_hi(); 1984 1985 if (right->is_double_cpu()) { 1986 // cpu register - cpu register 1987 Register rreg_lo = right->as_register_lo(); 1988 Register rreg_hi = right->as_register_hi(); 1989 NOT_LP64(assert_different_registers(lreg_lo, lreg_hi, rreg_lo, rreg_hi)); 1990 LP64_ONLY(assert_different_registers(lreg_lo, rreg_lo)); 1991 switch (code) { 1992 case lir_add: 1993 __ addptr(lreg_lo, rreg_lo); 1994 NOT_LP64(__ adcl(lreg_hi, rreg_hi)); 1995 break; 1996 case lir_sub: 1997 __ subptr(lreg_lo, rreg_lo); 1998 NOT_LP64(__ sbbl(lreg_hi, rreg_hi)); 1999 break; 2000 case lir_mul: 2001 #ifdef _LP64 2002 __ imulq(lreg_lo, rreg_lo); 2003 #else 2004 assert(lreg_lo == rax && lreg_hi == rdx, "must be"); 2005 __ imull(lreg_hi, rreg_lo); 2006 __ imull(rreg_hi, lreg_lo); 2007 __ addl (rreg_hi, lreg_hi); 2008 __ mull (rreg_lo); 2009 __ addl (lreg_hi, rreg_hi); 2010 #endif // _LP64 2011 break; 2012 default: 2013 ShouldNotReachHere(); 2014 } 2015 2016 } else if (right->is_constant()) { 2017 // cpu register - constant 2018 #ifdef _LP64 2019 jlong c = right->as_constant_ptr()->as_jlong_bits(); 2020 __ movptr(r10, (intptr_t) c); 2021 switch (code) { 2022 case lir_add: 2023 __ addptr(lreg_lo, r10); 2024 break; 2025 case lir_sub: 2026 __ subptr(lreg_lo, r10); 2027 break; 2028 default: 2029 ShouldNotReachHere(); 2030 } 2031 #else 2032 jint c_lo = right->as_constant_ptr()->as_jint_lo(); 2033 jint c_hi = right->as_constant_ptr()->as_jint_hi(); 2034 switch (code) { 2035 case lir_add: 2036 __ addptr(lreg_lo, c_lo); 2037 __ adcl(lreg_hi, c_hi); 2038 break; 2039 case lir_sub: 2040 __ subptr(lreg_lo, c_lo); 2041 __ sbbl(lreg_hi, c_hi); 2042 break; 2043 default: 2044 ShouldNotReachHere(); 2045 } 2046 #endif // _LP64 2047 2048 } else { 2049 ShouldNotReachHere(); 2050 } 2051 2052 } else if (left->is_single_xmm()) { 2053 assert(left == dest, "left and dest must be equal"); 2054 XMMRegister lreg = left->as_xmm_float_reg(); 2055 2056 if (right->is_single_xmm()) { 2057 XMMRegister rreg = right->as_xmm_float_reg(); 2058 switch (code) { 2059 case lir_add: __ addss(lreg, rreg); break; 2060 case lir_sub: __ subss(lreg, rreg); break; 2061 case lir_mul_strictfp: // fall through 2062 case lir_mul: __ mulss(lreg, rreg); break; 2063 case lir_div_strictfp: // fall through 2064 case lir_div: __ divss(lreg, rreg); break; 2065 default: ShouldNotReachHere(); 2066 } 2067 } else { 2068 Address raddr; 2069 if (right->is_single_stack()) { 2070 raddr = frame_map()->address_for_slot(right->single_stack_ix()); 2071 } else if (right->is_constant()) { 2072 // hack for now 2073 raddr = __ as_Address(InternalAddress(float_constant(right->as_jfloat()))); 2074 } else { 2075 ShouldNotReachHere(); 2076 } 2077 switch (code) { 2078 case lir_add: __ addss(lreg, raddr); break; 2079 case lir_sub: __ subss(lreg, raddr); break; 2080 case lir_mul_strictfp: // fall through 2081 case lir_mul: __ mulss(lreg, raddr); break; 2082 case lir_div_strictfp: // fall through 2083 case lir_div: __ divss(lreg, raddr); break; 2084 default: ShouldNotReachHere(); 2085 } 2086 } 2087 2088 } else if (left->is_double_xmm()) { 2089 assert(left == dest, "left and dest must be equal"); 2090 2091 XMMRegister lreg = left->as_xmm_double_reg(); 2092 if (right->is_double_xmm()) { 2093 XMMRegister rreg = right->as_xmm_double_reg(); 2094 switch (code) { 2095 case lir_add: __ addsd(lreg, rreg); break; 2096 case lir_sub: __ subsd(lreg, rreg); break; 2097 case lir_mul_strictfp: // fall through 2098 case lir_mul: __ mulsd(lreg, rreg); break; 2099 case lir_div_strictfp: // fall through 2100 case lir_div: __ divsd(lreg, rreg); break; 2101 default: ShouldNotReachHere(); 2102 } 2103 } else { 2104 Address raddr; 2105 if (right->is_double_stack()) { 2106 raddr = frame_map()->address_for_slot(right->double_stack_ix()); 2107 } else if (right->is_constant()) { 2108 // hack for now 2109 raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble()))); 2110 } else { 2111 ShouldNotReachHere(); 2112 } 2113 switch (code) { 2114 case lir_add: __ addsd(lreg, raddr); break; 2115 case lir_sub: __ subsd(lreg, raddr); break; 2116 case lir_mul_strictfp: // fall through 2117 case lir_mul: __ mulsd(lreg, raddr); break; 2118 case lir_div_strictfp: // fall through 2119 case lir_div: __ divsd(lreg, raddr); break; 2120 default: ShouldNotReachHere(); 2121 } 2122 } 2123 2124 } else if (left->is_single_fpu()) { 2125 assert(dest->is_single_fpu(), "fpu stack allocation required"); 2126 2127 if (right->is_single_fpu()) { 2128 arith_fpu_implementation(code, left->fpu_regnr(), right->fpu_regnr(), dest->fpu_regnr(), pop_fpu_stack); 2129 2130 } else { 2131 assert(left->fpu_regnr() == 0, "left must be on TOS"); 2132 assert(dest->fpu_regnr() == 0, "dest must be on TOS"); 2133 2134 Address raddr; 2135 if (right->is_single_stack()) { 2136 raddr = frame_map()->address_for_slot(right->single_stack_ix()); 2137 } else if (right->is_constant()) { 2138 address const_addr = float_constant(right->as_jfloat()); 2139 assert(const_addr != NULL, "incorrect float/double constant maintainance"); 2140 // hack for now 2141 raddr = __ as_Address(InternalAddress(const_addr)); 2142 } else { 2143 ShouldNotReachHere(); 2144 } 2145 2146 switch (code) { 2147 case lir_add: __ fadd_s(raddr); break; 2148 case lir_sub: __ fsub_s(raddr); break; 2149 case lir_mul_strictfp: // fall through 2150 case lir_mul: __ fmul_s(raddr); break; 2151 case lir_div_strictfp: // fall through 2152 case lir_div: __ fdiv_s(raddr); break; 2153 default: ShouldNotReachHere(); 2154 } 2155 } 2156 2157 } else if (left->is_double_fpu()) { 2158 assert(dest->is_double_fpu(), "fpu stack allocation required"); 2159 2160 if (code == lir_mul_strictfp || code == lir_div_strictfp) { 2161 // Double values require special handling for strictfp mul/div on x86 2162 __ fld_x(ExternalAddress(StubRoutines::addr_fpu_subnormal_bias1())); 2163 __ fmulp(left->fpu_regnrLo() + 1); 2164 } 2165 2166 if (right->is_double_fpu()) { 2167 arith_fpu_implementation(code, left->fpu_regnrLo(), right->fpu_regnrLo(), dest->fpu_regnrLo(), pop_fpu_stack); 2168 2169 } else { 2170 assert(left->fpu_regnrLo() == 0, "left must be on TOS"); 2171 assert(dest->fpu_regnrLo() == 0, "dest must be on TOS"); 2172 2173 Address raddr; 2174 if (right->is_double_stack()) { 2175 raddr = frame_map()->address_for_slot(right->double_stack_ix()); 2176 } else if (right->is_constant()) { 2177 // hack for now 2178 raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble()))); 2179 } else { 2180 ShouldNotReachHere(); 2181 } 2182 2183 switch (code) { 2184 case lir_add: __ fadd_d(raddr); break; 2185 case lir_sub: __ fsub_d(raddr); break; 2186 case lir_mul_strictfp: // fall through 2187 case lir_mul: __ fmul_d(raddr); break; 2188 case lir_div_strictfp: // fall through 2189 case lir_div: __ fdiv_d(raddr); break; 2190 default: ShouldNotReachHere(); 2191 } 2192 } 2193 2194 if (code == lir_mul_strictfp || code == lir_div_strictfp) { 2195 // Double values require special handling for strictfp mul/div on x86 2196 __ fld_x(ExternalAddress(StubRoutines::addr_fpu_subnormal_bias2())); 2197 __ fmulp(dest->fpu_regnrLo() + 1); 2198 } 2199 2200 } else if (left->is_single_stack() || left->is_address()) { 2201 assert(left == dest, "left and dest must be equal"); 2202 2203 Address laddr; 2204 if (left->is_single_stack()) { 2205 laddr = frame_map()->address_for_slot(left->single_stack_ix()); 2206 } else if (left->is_address()) { 2207 laddr = as_Address(left->as_address_ptr()); 2208 } else { 2209 ShouldNotReachHere(); 2210 } 2211 2212 if (right->is_single_cpu()) { 2213 Register rreg = right->as_register(); 2214 switch (code) { 2215 case lir_add: __ addl(laddr, rreg); break; 2216 case lir_sub: __ subl(laddr, rreg); break; 2217 default: ShouldNotReachHere(); 2218 } 2219 } else if (right->is_constant()) { 2220 jint c = right->as_constant_ptr()->as_jint(); 2221 switch (code) { 2222 case lir_add: { 2223 __ incrementl(laddr, c); 2224 break; 2225 } 2226 case lir_sub: { 2227 __ decrementl(laddr, c); 2228 break; 2229 } 2230 default: ShouldNotReachHere(); 2231 } 2232 } else { 2233 ShouldNotReachHere(); 2234 } 2235 2236 } else { 2237 ShouldNotReachHere(); 2238 } 2239 } 2240 2241 void LIR_Assembler::arith_fpu_implementation(LIR_Code code, int left_index, int right_index, int dest_index, bool pop_fpu_stack) { 2242 assert(pop_fpu_stack || (left_index == dest_index || right_index == dest_index), "invalid LIR"); 2243 assert(!pop_fpu_stack || (left_index - 1 == dest_index || right_index - 1 == dest_index), "invalid LIR"); 2244 assert(left_index == 0 || right_index == 0, "either must be on top of stack"); 2245 2246 bool left_is_tos = (left_index == 0); 2247 bool dest_is_tos = (dest_index == 0); 2248 int non_tos_index = (left_is_tos ? right_index : left_index); 2249 2250 switch (code) { 2251 case lir_add: 2252 if (pop_fpu_stack) __ faddp(non_tos_index); 2253 else if (dest_is_tos) __ fadd (non_tos_index); 2254 else __ fadda(non_tos_index); 2255 break; 2256 2257 case lir_sub: 2258 if (left_is_tos) { 2259 if (pop_fpu_stack) __ fsubrp(non_tos_index); 2260 else if (dest_is_tos) __ fsub (non_tos_index); 2261 else __ fsubra(non_tos_index); 2262 } else { 2263 if (pop_fpu_stack) __ fsubp (non_tos_index); 2264 else if (dest_is_tos) __ fsubr (non_tos_index); 2265 else __ fsuba (non_tos_index); 2266 } 2267 break; 2268 2269 case lir_mul_strictfp: // fall through 2270 case lir_mul: 2271 if (pop_fpu_stack) __ fmulp(non_tos_index); 2272 else if (dest_is_tos) __ fmul (non_tos_index); 2273 else __ fmula(non_tos_index); 2274 break; 2275 2276 case lir_div_strictfp: // fall through 2277 case lir_div: 2278 if (left_is_tos) { 2279 if (pop_fpu_stack) __ fdivrp(non_tos_index); 2280 else if (dest_is_tos) __ fdiv (non_tos_index); 2281 else __ fdivra(non_tos_index); 2282 } else { 2283 if (pop_fpu_stack) __ fdivp (non_tos_index); 2284 else if (dest_is_tos) __ fdivr (non_tos_index); 2285 else __ fdiva (non_tos_index); 2286 } 2287 break; 2288 2289 case lir_rem: 2290 assert(left_is_tos && dest_is_tos && right_index == 1, "must be guaranteed by FPU stack allocation"); 2291 __ fremr(noreg); 2292 break; 2293 2294 default: 2295 ShouldNotReachHere(); 2296 } 2297 } 2298 2299 2300 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr unused, LIR_Opr dest, LIR_Op* op) { 2301 if (value->is_double_xmm()) { 2302 switch(code) { 2303 case lir_abs : 2304 { 2305 if (dest->as_xmm_double_reg() != value->as_xmm_double_reg()) { 2306 __ movdbl(dest->as_xmm_double_reg(), value->as_xmm_double_reg()); 2307 } 2308 __ andpd(dest->as_xmm_double_reg(), 2309 ExternalAddress((address)double_signmask_pool)); 2310 } 2311 break; 2312 2313 case lir_sqrt: __ sqrtsd(dest->as_xmm_double_reg(), value->as_xmm_double_reg()); break; 2314 // all other intrinsics are not available in the SSE instruction set, so FPU is used 2315 default : ShouldNotReachHere(); 2316 } 2317 2318 } else if (value->is_double_fpu()) { 2319 assert(value->fpu_regnrLo() == 0 && dest->fpu_regnrLo() == 0, "both must be on TOS"); 2320 switch(code) { 2321 case lir_log : __ flog() ; break; 2322 case lir_log10 : __ flog10() ; break; 2323 case lir_abs : __ fabs() ; break; 2324 case lir_sqrt : __ fsqrt(); break; 2325 case lir_sin : 2326 // Should consider not saving rbx, if not necessary 2327 __ trigfunc('s', op->as_Op2()->fpu_stack_size()); 2328 break; 2329 case lir_cos : 2330 // Should consider not saving rbx, if not necessary 2331 assert(op->as_Op2()->fpu_stack_size() <= 6, "sin and cos need two free stack slots"); 2332 __ trigfunc('c', op->as_Op2()->fpu_stack_size()); 2333 break; 2334 case lir_tan : 2335 // Should consider not saving rbx, if not necessary 2336 __ trigfunc('t', op->as_Op2()->fpu_stack_size()); 2337 break; 2338 default : ShouldNotReachHere(); 2339 } 2340 } else { 2341 Unimplemented(); 2342 } 2343 } 2344 2345 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) { 2346 // assert(left->destroys_register(), "check"); 2347 if (left->is_single_cpu()) { 2348 Register reg = left->as_register(); 2349 if (right->is_constant()) { 2350 int val = right->as_constant_ptr()->as_jint(); 2351 switch (code) { 2352 case lir_logic_and: __ andl (reg, val); break; 2353 case lir_logic_or: __ orl (reg, val); break; 2354 case lir_logic_xor: __ xorl (reg, val); break; 2355 default: ShouldNotReachHere(); 2356 } 2357 } else if (right->is_stack()) { 2358 // added support for stack operands 2359 Address raddr = frame_map()->address_for_slot(right->single_stack_ix()); 2360 switch (code) { 2361 case lir_logic_and: __ andl (reg, raddr); break; 2362 case lir_logic_or: __ orl (reg, raddr); break; 2363 case lir_logic_xor: __ xorl (reg, raddr); break; 2364 default: ShouldNotReachHere(); 2365 } 2366 } else { 2367 Register rright = right->as_register(); 2368 switch (code) { 2369 case lir_logic_and: __ andptr (reg, rright); break; 2370 case lir_logic_or : __ orptr (reg, rright); break; 2371 case lir_logic_xor: __ xorptr (reg, rright); break; 2372 default: ShouldNotReachHere(); 2373 } 2374 } 2375 move_regs(reg, dst->as_register()); 2376 } else { 2377 Register l_lo = left->as_register_lo(); 2378 Register l_hi = left->as_register_hi(); 2379 if (right->is_constant()) { 2380 #ifdef _LP64 2381 __ mov64(rscratch1, right->as_constant_ptr()->as_jlong()); 2382 switch (code) { 2383 case lir_logic_and: 2384 __ andq(l_lo, rscratch1); 2385 break; 2386 case lir_logic_or: 2387 __ orq(l_lo, rscratch1); 2388 break; 2389 case lir_logic_xor: 2390 __ xorq(l_lo, rscratch1); 2391 break; 2392 default: ShouldNotReachHere(); 2393 } 2394 #else 2395 int r_lo = right->as_constant_ptr()->as_jint_lo(); 2396 int r_hi = right->as_constant_ptr()->as_jint_hi(); 2397 switch (code) { 2398 case lir_logic_and: 2399 __ andl(l_lo, r_lo); 2400 __ andl(l_hi, r_hi); 2401 break; 2402 case lir_logic_or: 2403 __ orl(l_lo, r_lo); 2404 __ orl(l_hi, r_hi); 2405 break; 2406 case lir_logic_xor: 2407 __ xorl(l_lo, r_lo); 2408 __ xorl(l_hi, r_hi); 2409 break; 2410 default: ShouldNotReachHere(); 2411 } 2412 #endif // _LP64 2413 } else { 2414 Register r_lo = right->as_register_lo(); 2415 Register r_hi = right->as_register_hi(); 2416 assert(l_lo != r_hi, "overwriting registers"); 2417 switch (code) { 2418 case lir_logic_and: 2419 __ andptr(l_lo, r_lo); 2420 NOT_LP64(__ andptr(l_hi, r_hi);) 2421 break; 2422 case lir_logic_or: 2423 __ orptr(l_lo, r_lo); 2424 NOT_LP64(__ orptr(l_hi, r_hi);) 2425 break; 2426 case lir_logic_xor: 2427 __ xorptr(l_lo, r_lo); 2428 NOT_LP64(__ xorptr(l_hi, r_hi);) 2429 break; 2430 default: ShouldNotReachHere(); 2431 } 2432 } 2433 2434 Register dst_lo = dst->as_register_lo(); 2435 Register dst_hi = dst->as_register_hi(); 2436 2437 #ifdef _LP64 2438 move_regs(l_lo, dst_lo); 2439 #else 2440 if (dst_lo == l_hi) { 2441 assert(dst_hi != l_lo, "overwriting registers"); 2442 move_regs(l_hi, dst_hi); 2443 move_regs(l_lo, dst_lo); 2444 } else { 2445 assert(dst_lo != l_hi, "overwriting registers"); 2446 move_regs(l_lo, dst_lo); 2447 move_regs(l_hi, dst_hi); 2448 } 2449 #endif // _LP64 2450 } 2451 } 2452 2453 2454 // we assume that rax, and rdx can be overwritten 2455 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info) { 2456 2457 assert(left->is_single_cpu(), "left must be register"); 2458 assert(right->is_single_cpu() || right->is_constant(), "right must be register or constant"); 2459 assert(result->is_single_cpu(), "result must be register"); 2460 2461 // assert(left->destroys_register(), "check"); 2462 // assert(right->destroys_register(), "check"); 2463 2464 Register lreg = left->as_register(); 2465 Register dreg = result->as_register(); 2466 2467 if (right->is_constant()) { 2468 int divisor = right->as_constant_ptr()->as_jint(); 2469 assert(divisor > 0 && is_power_of_2(divisor), "must be"); 2470 if (code == lir_idiv) { 2471 assert(lreg == rax, "must be rax,"); 2472 assert(temp->as_register() == rdx, "tmp register must be rdx"); 2473 __ cdql(); // sign extend into rdx:rax 2474 if (divisor == 2) { 2475 __ subl(lreg, rdx); 2476 } else { 2477 __ andl(rdx, divisor - 1); 2478 __ addl(lreg, rdx); 2479 } 2480 __ sarl(lreg, log2_intptr(divisor)); 2481 move_regs(lreg, dreg); 2482 } else if (code == lir_irem) { 2483 Label done; 2484 __ mov(dreg, lreg); 2485 __ andl(dreg, 0x80000000 | (divisor - 1)); 2486 __ jcc(Assembler::positive, done); 2487 __ decrement(dreg); 2488 __ orl(dreg, ~(divisor - 1)); 2489 __ increment(dreg); 2490 __ bind(done); 2491 } else { 2492 ShouldNotReachHere(); 2493 } 2494 } else { 2495 Register rreg = right->as_register(); 2496 assert(lreg == rax, "left register must be rax,"); 2497 assert(rreg != rdx, "right register must not be rdx"); 2498 assert(temp->as_register() == rdx, "tmp register must be rdx"); 2499 2500 move_regs(lreg, rax); 2501 2502 int idivl_offset = __ corrected_idivl(rreg); 2503 add_debug_info_for_div0(idivl_offset, info); 2504 if (code == lir_irem) { 2505 move_regs(rdx, dreg); // result is in rdx 2506 } else { 2507 move_regs(rax, dreg); 2508 } 2509 } 2510 } 2511 2512 2513 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) { 2514 if (opr1->is_single_cpu()) { 2515 Register reg1 = opr1->as_register(); 2516 if (opr2->is_single_cpu()) { 2517 // cpu register - cpu register 2518 if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) { 2519 __ cmpptr(reg1, opr2->as_register()); 2520 } else { 2521 assert(opr2->type() != T_OBJECT && opr2->type() != T_ARRAY, "cmp int, oop?"); 2522 __ cmpl(reg1, opr2->as_register()); 2523 } 2524 } else if (opr2->is_stack()) { 2525 // cpu register - stack 2526 if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) { 2527 __ cmpptr(reg1, frame_map()->address_for_slot(opr2->single_stack_ix())); 2528 } else { 2529 __ cmpl(reg1, frame_map()->address_for_slot(opr2->single_stack_ix())); 2530 } 2531 } else if (opr2->is_constant()) { 2532 // cpu register - constant 2533 LIR_Const* c = opr2->as_constant_ptr(); 2534 if (c->type() == T_INT) { 2535 __ cmpl(reg1, c->as_jint()); 2536 } else if (c->type() == T_OBJECT || c->type() == T_ARRAY) { 2537 // In 64bit oops are single register 2538 jobject o = c->as_jobject(); 2539 if (o == NULL) { 2540 __ cmpptr(reg1, (int32_t)NULL_WORD); 2541 } else { 2542 #ifdef _LP64 2543 __ movoop(rscratch1, o); 2544 __ cmpptr(reg1, rscratch1); 2545 #else 2546 __ cmpoop(reg1, c->as_jobject()); 2547 #endif // _LP64 2548 } 2549 } else { 2550 ShouldNotReachHere(); 2551 } 2552 // cpu register - address 2553 } else if (opr2->is_address()) { 2554 if (op->info() != NULL) { 2555 add_debug_info_for_null_check_here(op->info()); 2556 } 2557 __ cmpl(reg1, as_Address(opr2->as_address_ptr())); 2558 } else { 2559 ShouldNotReachHere(); 2560 } 2561 2562 } else if(opr1->is_double_cpu()) { 2563 Register xlo = opr1->as_register_lo(); 2564 Register xhi = opr1->as_register_hi(); 2565 if (opr2->is_double_cpu()) { 2566 #ifdef _LP64 2567 __ cmpptr(xlo, opr2->as_register_lo()); 2568 #else 2569 // cpu register - cpu register 2570 Register ylo = opr2->as_register_lo(); 2571 Register yhi = opr2->as_register_hi(); 2572 __ subl(xlo, ylo); 2573 __ sbbl(xhi, yhi); 2574 if (condition == lir_cond_equal || condition == lir_cond_notEqual) { 2575 __ orl(xhi, xlo); 2576 } 2577 #endif // _LP64 2578 } else if (opr2->is_constant()) { 2579 // cpu register - constant 0 2580 assert(opr2->as_jlong() == (jlong)0, "only handles zero"); 2581 #ifdef _LP64 2582 __ cmpptr(xlo, (int32_t)opr2->as_jlong()); 2583 #else 2584 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "only handles equals case"); 2585 __ orl(xhi, xlo); 2586 #endif // _LP64 2587 } else { 2588 ShouldNotReachHere(); 2589 } 2590 2591 } else if (opr1->is_single_xmm()) { 2592 XMMRegister reg1 = opr1->as_xmm_float_reg(); 2593 if (opr2->is_single_xmm()) { 2594 // xmm register - xmm register 2595 __ ucomiss(reg1, opr2->as_xmm_float_reg()); 2596 } else if (opr2->is_stack()) { 2597 // xmm register - stack 2598 __ ucomiss(reg1, frame_map()->address_for_slot(opr2->single_stack_ix())); 2599 } else if (opr2->is_constant()) { 2600 // xmm register - constant 2601 __ ucomiss(reg1, InternalAddress(float_constant(opr2->as_jfloat()))); 2602 } else if (opr2->is_address()) { 2603 // xmm register - address 2604 if (op->info() != NULL) { 2605 add_debug_info_for_null_check_here(op->info()); 2606 } 2607 __ ucomiss(reg1, as_Address(opr2->as_address_ptr())); 2608 } else { 2609 ShouldNotReachHere(); 2610 } 2611 2612 } else if (opr1->is_double_xmm()) { 2613 XMMRegister reg1 = opr1->as_xmm_double_reg(); 2614 if (opr2->is_double_xmm()) { 2615 // xmm register - xmm register 2616 __ ucomisd(reg1, opr2->as_xmm_double_reg()); 2617 } else if (opr2->is_stack()) { 2618 // xmm register - stack 2619 __ ucomisd(reg1, frame_map()->address_for_slot(opr2->double_stack_ix())); 2620 } else if (opr2->is_constant()) { 2621 // xmm register - constant 2622 __ ucomisd(reg1, InternalAddress(double_constant(opr2->as_jdouble()))); 2623 } else if (opr2->is_address()) { 2624 // xmm register - address 2625 if (op->info() != NULL) { 2626 add_debug_info_for_null_check_here(op->info()); 2627 } 2628 __ ucomisd(reg1, as_Address(opr2->pointer()->as_address())); 2629 } else { 2630 ShouldNotReachHere(); 2631 } 2632 2633 } else if(opr1->is_single_fpu() || opr1->is_double_fpu()) { 2634 assert(opr1->is_fpu_register() && opr1->fpu() == 0, "currently left-hand side must be on TOS (relax this restriction)"); 2635 assert(opr2->is_fpu_register(), "both must be registers"); 2636 __ fcmp(noreg, opr2->fpu(), op->fpu_pop_count() > 0, op->fpu_pop_count() > 1); 2637 2638 } else if (opr1->is_address() && opr2->is_constant()) { 2639 LIR_Const* c = opr2->as_constant_ptr(); 2640 #ifdef _LP64 2641 if (c->type() == T_OBJECT || c->type() == T_ARRAY) { 2642 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "need to reverse"); 2643 __ movoop(rscratch1, c->as_jobject()); 2644 } 2645 #endif // LP64 2646 if (op->info() != NULL) { 2647 add_debug_info_for_null_check_here(op->info()); 2648 } 2649 // special case: address - constant 2650 LIR_Address* addr = opr1->as_address_ptr(); 2651 if (c->type() == T_INT) { 2652 __ cmpl(as_Address(addr), c->as_jint()); 2653 } else if (c->type() == T_OBJECT || c->type() == T_ARRAY) { 2654 #ifdef _LP64 2655 // %%% Make this explode if addr isn't reachable until we figure out a 2656 // better strategy by giving noreg as the temp for as_Address 2657 __ cmpptr(rscratch1, as_Address(addr, noreg)); 2658 #else 2659 __ cmpoop(as_Address(addr), c->as_jobject()); 2660 #endif // _LP64 2661 } else { 2662 ShouldNotReachHere(); 2663 } 2664 2665 } else { 2666 ShouldNotReachHere(); 2667 } 2668 } 2669 2670 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op) { 2671 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) { 2672 if (left->is_single_xmm()) { 2673 assert(right->is_single_xmm(), "must match"); 2674 __ cmpss2int(left->as_xmm_float_reg(), right->as_xmm_float_reg(), dst->as_register(), code == lir_ucmp_fd2i); 2675 } else if (left->is_double_xmm()) { 2676 assert(right->is_double_xmm(), "must match"); 2677 __ cmpsd2int(left->as_xmm_double_reg(), right->as_xmm_double_reg(), dst->as_register(), code == lir_ucmp_fd2i); 2678 2679 } else { 2680 assert(left->is_single_fpu() || left->is_double_fpu(), "must be"); 2681 assert(right->is_single_fpu() || right->is_double_fpu(), "must match"); 2682 2683 assert(left->fpu() == 0, "left must be on TOS"); 2684 __ fcmp2int(dst->as_register(), code == lir_ucmp_fd2i, right->fpu(), 2685 op->fpu_pop_count() > 0, op->fpu_pop_count() > 1); 2686 } 2687 } else { 2688 assert(code == lir_cmp_l2i, "check"); 2689 #ifdef _LP64 2690 Register dest = dst->as_register(); 2691 __ xorptr(dest, dest); 2692 Label high, done; 2693 __ cmpptr(left->as_register_lo(), right->as_register_lo()); 2694 __ jcc(Assembler::equal, done); 2695 __ jcc(Assembler::greater, high); 2696 __ decrement(dest); 2697 __ jmp(done); 2698 __ bind(high); 2699 __ increment(dest); 2700 2701 __ bind(done); 2702 2703 #else 2704 __ lcmp2int(left->as_register_hi(), 2705 left->as_register_lo(), 2706 right->as_register_hi(), 2707 right->as_register_lo()); 2708 move_regs(left->as_register_hi(), dst->as_register()); 2709 #endif // _LP64 2710 } 2711 } 2712 2713 2714 void LIR_Assembler::align_call(LIR_Code code) { 2715 if (os::is_MP()) { 2716 // make sure that the displacement word of the call ends up word aligned 2717 int offset = __ offset(); 2718 switch (code) { 2719 case lir_static_call: 2720 case lir_optvirtual_call: 2721 case lir_dynamic_call: 2722 offset += NativeCall::displacement_offset; 2723 break; 2724 case lir_icvirtual_call: 2725 offset += NativeCall::displacement_offset + NativeMovConstReg::instruction_size; 2726 break; 2727 case lir_virtual_call: // currently, sparc-specific for niagara 2728 default: ShouldNotReachHere(); 2729 } 2730 while (offset++ % BytesPerWord != 0) { 2731 __ nop(); 2732 } 2733 } 2734 } 2735 2736 2737 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) { 2738 assert(!os::is_MP() || (__ offset() + NativeCall::displacement_offset) % BytesPerWord == 0, 2739 "must be aligned"); 2740 __ call(AddressLiteral(op->addr(), rtype)); 2741 add_call_info(code_offset(), op->info(), op->is_method_handle_invoke()); 2742 } 2743 2744 2745 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) { 2746 RelocationHolder rh = virtual_call_Relocation::spec(pc()); 2747 __ movoop(IC_Klass, (jobject)Universe::non_oop_word()); 2748 assert(!os::is_MP() || 2749 (__ offset() + NativeCall::displacement_offset) % BytesPerWord == 0, 2750 "must be aligned"); 2751 __ call(AddressLiteral(op->addr(), rh)); 2752 add_call_info(code_offset(), op->info(), op->is_method_handle_invoke()); 2753 } 2754 2755 2756 /* Currently, vtable-dispatch is only enabled for sparc platforms */ 2757 void LIR_Assembler::vtable_call(LIR_OpJavaCall* op) { 2758 ShouldNotReachHere(); 2759 } 2760 2761 2762 void LIR_Assembler::preserve_SP() { 2763 __ movptr(rbp, rsp); 2764 } 2765 2766 2767 void LIR_Assembler::restore_SP() { 2768 __ movptr(rsp, rbp); 2769 } 2770 2771 2772 void LIR_Assembler::emit_static_call_stub() { 2773 address call_pc = __ pc(); 2774 address stub = __ start_a_stub(call_stub_size); 2775 if (stub == NULL) { 2776 bailout("static call stub overflow"); 2777 return; 2778 } 2779 2780 int start = __ offset(); 2781 if (os::is_MP()) { 2782 // make sure that the displacement word of the call ends up word aligned 2783 int offset = __ offset() + NativeMovConstReg::instruction_size + NativeCall::displacement_offset; 2784 while (offset++ % BytesPerWord != 0) { 2785 __ nop(); 2786 } 2787 } 2788 __ relocate(static_stub_Relocation::spec(call_pc)); 2789 __ movoop(rbx, (jobject)NULL); 2790 // must be set to -1 at code generation time 2791 assert(!os::is_MP() || ((__ offset() + 1) % BytesPerWord) == 0, "must be aligned on MP"); 2792 // On 64bit this will die since it will take a movq & jmp, must be only a jmp 2793 __ jump(RuntimeAddress(__ pc())); 2794 2795 assert(__ offset() - start <= call_stub_size, "stub too big") 2796 __ end_a_stub(); 2797 } 2798 2799 2800 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info, bool unwind) { 2801 assert(exceptionOop->as_register() == rax, "must match"); 2802 assert(unwind || exceptionPC->as_register() == rdx, "must match"); 2803 2804 // exception object is not added to oop map by LinearScan 2805 // (LinearScan assumes that no oops are in fixed registers) 2806 info->add_register_oop(exceptionOop); 2807 Runtime1::StubID unwind_id; 2808 2809 if (!unwind) { 2810 // get current pc information 2811 // pc is only needed if the method has an exception handler, the unwind code does not need it. 2812 int pc_for_athrow_offset = __ offset(); 2813 InternalAddress pc_for_athrow(__ pc()); 2814 __ lea(exceptionPC->as_register(), pc_for_athrow); 2815 add_call_info(pc_for_athrow_offset, info); // for exception handler 2816 2817 __ verify_not_null_oop(rax); 2818 // search an exception handler (rax: exception oop, rdx: throwing pc) 2819 if (compilation()->has_fpu_code()) { 2820 unwind_id = Runtime1::handle_exception_id; 2821 } else { 2822 unwind_id = Runtime1::handle_exception_nofpu_id; 2823 } 2824 __ call(RuntimeAddress(Runtime1::entry_for(unwind_id))); 2825 } else { 2826 // remove the activation 2827 __ remove_frame(initial_frame_size_in_bytes()); 2828 __ jump(RuntimeAddress(Runtime1::entry_for(Runtime1::unwind_exception_id))); 2829 } 2830 2831 // enough room for two byte trap 2832 __ nop(); 2833 } 2834 2835 2836 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) { 2837 2838 // optimized version for linear scan: 2839 // * count must be already in ECX (guaranteed by LinearScan) 2840 // * left and dest must be equal 2841 // * tmp must be unused 2842 assert(count->as_register() == SHIFT_count, "count must be in ECX"); 2843 assert(left == dest, "left and dest must be equal"); 2844 assert(tmp->is_illegal(), "wasting a register if tmp is allocated"); 2845 2846 if (left->is_single_cpu()) { 2847 Register value = left->as_register(); 2848 assert(value != SHIFT_count, "left cannot be ECX"); 2849 2850 switch (code) { 2851 case lir_shl: __ shll(value); break; 2852 case lir_shr: __ sarl(value); break; 2853 case lir_ushr: __ shrl(value); break; 2854 default: ShouldNotReachHere(); 2855 } 2856 } else if (left->is_double_cpu()) { 2857 Register lo = left->as_register_lo(); 2858 Register hi = left->as_register_hi(); 2859 assert(lo != SHIFT_count && hi != SHIFT_count, "left cannot be ECX"); 2860 #ifdef _LP64 2861 switch (code) { 2862 case lir_shl: __ shlptr(lo); break; 2863 case lir_shr: __ sarptr(lo); break; 2864 case lir_ushr: __ shrptr(lo); break; 2865 default: ShouldNotReachHere(); 2866 } 2867 #else 2868 2869 switch (code) { 2870 case lir_shl: __ lshl(hi, lo); break; 2871 case lir_shr: __ lshr(hi, lo, true); break; 2872 case lir_ushr: __ lshr(hi, lo, false); break; 2873 default: ShouldNotReachHere(); 2874 } 2875 #endif // LP64 2876 } else { 2877 ShouldNotReachHere(); 2878 } 2879 } 2880 2881 2882 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) { 2883 if (dest->is_single_cpu()) { 2884 // first move left into dest so that left is not destroyed by the shift 2885 Register value = dest->as_register(); 2886 count = count & 0x1F; // Java spec 2887 2888 move_regs(left->as_register(), value); 2889 switch (code) { 2890 case lir_shl: __ shll(value, count); break; 2891 case lir_shr: __ sarl(value, count); break; 2892 case lir_ushr: __ shrl(value, count); break; 2893 default: ShouldNotReachHere(); 2894 } 2895 } else if (dest->is_double_cpu()) { 2896 #ifndef _LP64 2897 Unimplemented(); 2898 #else 2899 // first move left into dest so that left is not destroyed by the shift 2900 Register value = dest->as_register_lo(); 2901 count = count & 0x1F; // Java spec 2902 2903 move_regs(left->as_register_lo(), value); 2904 switch (code) { 2905 case lir_shl: __ shlptr(value, count); break; 2906 case lir_shr: __ sarptr(value, count); break; 2907 case lir_ushr: __ shrptr(value, count); break; 2908 default: ShouldNotReachHere(); 2909 } 2910 #endif // _LP64 2911 } else { 2912 ShouldNotReachHere(); 2913 } 2914 } 2915 2916 2917 void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) { 2918 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp"); 2919 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord; 2920 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset"); 2921 __ movptr (Address(rsp, offset_from_rsp_in_bytes), r); 2922 } 2923 2924 2925 void LIR_Assembler::store_parameter(jint c, int offset_from_rsp_in_words) { 2926 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp"); 2927 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord; 2928 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset"); 2929 __ movptr (Address(rsp, offset_from_rsp_in_bytes), c); 2930 } 2931 2932 2933 void LIR_Assembler::store_parameter(jobject o, int offset_from_rsp_in_words) { 2934 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp"); 2935 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord; 2936 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset"); 2937 __ movoop (Address(rsp, offset_from_rsp_in_bytes), o); 2938 } 2939 2940 2941 // This code replaces a call to arraycopy; no exception may 2942 // be thrown in this code, they must be thrown in the System.arraycopy 2943 // activation frame; we could save some checks if this would not be the case 2944 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) { 2945 ciArrayKlass* default_type = op->expected_type(); 2946 Register src = op->src()->as_register(); 2947 Register dst = op->dst()->as_register(); 2948 Register src_pos = op->src_pos()->as_register(); 2949 Register dst_pos = op->dst_pos()->as_register(); 2950 Register length = op->length()->as_register(); 2951 Register tmp = op->tmp()->as_register(); 2952 2953 CodeStub* stub = op->stub(); 2954 int flags = op->flags(); 2955 BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL; 2956 if (basic_type == T_ARRAY) basic_type = T_OBJECT; 2957 2958 // if we don't know anything or it's an object array, just go through the generic arraycopy 2959 if (default_type == NULL) { 2960 Label done; 2961 // save outgoing arguments on stack in case call to System.arraycopy is needed 2962 // HACK ALERT. This code used to push the parameters in a hardwired fashion 2963 // for interpreter calling conventions. Now we have to do it in new style conventions. 2964 // For the moment until C1 gets the new register allocator I just force all the 2965 // args to the right place (except the register args) and then on the back side 2966 // reload the register args properly if we go slow path. Yuck 2967 2968 // These are proper for the calling convention 2969 2970 store_parameter(length, 2); 2971 store_parameter(dst_pos, 1); 2972 store_parameter(dst, 0); 2973 2974 // these are just temporary placements until we need to reload 2975 store_parameter(src_pos, 3); 2976 store_parameter(src, 4); 2977 NOT_LP64(assert(src == rcx && src_pos == rdx, "mismatch in calling convention");) 2978 2979 address entry = CAST_FROM_FN_PTR(address, Runtime1::arraycopy); 2980 2981 // pass arguments: may push as this is not a safepoint; SP must be fix at each safepoint 2982 #ifdef _LP64 2983 // The arguments are in java calling convention so we can trivially shift them to C 2984 // convention 2985 assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4); 2986 __ mov(c_rarg0, j_rarg0); 2987 assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4); 2988 __ mov(c_rarg1, j_rarg1); 2989 assert_different_registers(c_rarg2, j_rarg3, j_rarg4); 2990 __ mov(c_rarg2, j_rarg2); 2991 assert_different_registers(c_rarg3, j_rarg4); 2992 __ mov(c_rarg3, j_rarg3); 2993 #ifdef _WIN64 2994 // Allocate abi space for args but be sure to keep stack aligned 2995 __ subptr(rsp, 6*wordSize); 2996 store_parameter(j_rarg4, 4); 2997 __ call(RuntimeAddress(entry)); 2998 __ addptr(rsp, 6*wordSize); 2999 #else 3000 __ mov(c_rarg4, j_rarg4); 3001 __ call(RuntimeAddress(entry)); 3002 #endif // _WIN64 3003 #else 3004 __ push(length); 3005 __ push(dst_pos); 3006 __ push(dst); 3007 __ push(src_pos); 3008 __ push(src); 3009 __ call_VM_leaf(entry, 5); // removes pushed parameter from the stack 3010 3011 #endif // _LP64 3012 3013 __ cmpl(rax, 0); 3014 __ jcc(Assembler::equal, *stub->continuation()); 3015 3016 // Reload values from the stack so they are where the stub 3017 // expects them. 3018 __ movptr (dst, Address(rsp, 0*BytesPerWord)); 3019 __ movptr (dst_pos, Address(rsp, 1*BytesPerWord)); 3020 __ movptr (length, Address(rsp, 2*BytesPerWord)); 3021 __ movptr (src_pos, Address(rsp, 3*BytesPerWord)); 3022 __ movptr (src, Address(rsp, 4*BytesPerWord)); 3023 __ jmp(*stub->entry()); 3024 3025 __ bind(*stub->continuation()); 3026 return; 3027 } 3028 3029 assert(default_type != NULL && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point"); 3030 3031 int elem_size = type2aelembytes(basic_type); 3032 int shift_amount; 3033 Address::ScaleFactor scale; 3034 3035 switch (elem_size) { 3036 case 1 : 3037 shift_amount = 0; 3038 scale = Address::times_1; 3039 break; 3040 case 2 : 3041 shift_amount = 1; 3042 scale = Address::times_2; 3043 break; 3044 case 4 : 3045 shift_amount = 2; 3046 scale = Address::times_4; 3047 break; 3048 case 8 : 3049 shift_amount = 3; 3050 scale = Address::times_8; 3051 break; 3052 default: 3053 ShouldNotReachHere(); 3054 } 3055 3056 Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes()); 3057 Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes()); 3058 Address src_klass_addr = Address(src, oopDesc::klass_offset_in_bytes()); 3059 Address dst_klass_addr = Address(dst, oopDesc::klass_offset_in_bytes()); 3060 3061 // length and pos's are all sign extended at this point on 64bit 3062 3063 // test for NULL 3064 if (flags & LIR_OpArrayCopy::src_null_check) { 3065 __ testptr(src, src); 3066 __ jcc(Assembler::zero, *stub->entry()); 3067 } 3068 if (flags & LIR_OpArrayCopy::dst_null_check) { 3069 __ testptr(dst, dst); 3070 __ jcc(Assembler::zero, *stub->entry()); 3071 } 3072 3073 // check if negative 3074 if (flags & LIR_OpArrayCopy::src_pos_positive_check) { 3075 __ testl(src_pos, src_pos); 3076 __ jcc(Assembler::less, *stub->entry()); 3077 } 3078 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) { 3079 __ testl(dst_pos, dst_pos); 3080 __ jcc(Assembler::less, *stub->entry()); 3081 } 3082 if (flags & LIR_OpArrayCopy::length_positive_check) { 3083 __ testl(length, length); 3084 __ jcc(Assembler::less, *stub->entry()); 3085 } 3086 3087 if (flags & LIR_OpArrayCopy::src_range_check) { 3088 __ lea(tmp, Address(src_pos, length, Address::times_1, 0)); 3089 __ cmpl(tmp, src_length_addr); 3090 __ jcc(Assembler::above, *stub->entry()); 3091 } 3092 if (flags & LIR_OpArrayCopy::dst_range_check) { 3093 __ lea(tmp, Address(dst_pos, length, Address::times_1, 0)); 3094 __ cmpl(tmp, dst_length_addr); 3095 __ jcc(Assembler::above, *stub->entry()); 3096 } 3097 3098 if (flags & LIR_OpArrayCopy::type_check) { 3099 __ movptr(tmp, src_klass_addr); 3100 __ cmpptr(tmp, dst_klass_addr); 3101 __ jcc(Assembler::notEqual, *stub->entry()); 3102 } 3103 3104 #ifdef ASSERT 3105 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) { 3106 // Sanity check the known type with the incoming class. For the 3107 // primitive case the types must match exactly with src.klass and 3108 // dst.klass each exactly matching the default type. For the 3109 // object array case, if no type check is needed then either the 3110 // dst type is exactly the expected type and the src type is a 3111 // subtype which we can't check or src is the same array as dst 3112 // but not necessarily exactly of type default_type. 3113 Label known_ok, halt; 3114 __ movoop(tmp, default_type->constant_encoding()); 3115 if (basic_type != T_OBJECT) { 3116 __ cmpptr(tmp, dst_klass_addr); 3117 __ jcc(Assembler::notEqual, halt); 3118 __ cmpptr(tmp, src_klass_addr); 3119 __ jcc(Assembler::equal, known_ok); 3120 } else { 3121 __ cmpptr(tmp, dst_klass_addr); 3122 __ jcc(Assembler::equal, known_ok); 3123 __ cmpptr(src, dst); 3124 __ jcc(Assembler::equal, known_ok); 3125 } 3126 __ bind(halt); 3127 __ stop("incorrect type information in arraycopy"); 3128 __ bind(known_ok); 3129 } 3130 #endif 3131 3132 if (shift_amount > 0 && basic_type != T_OBJECT) { 3133 __ shlptr(length, shift_amount); 3134 } 3135 3136 #ifdef _LP64 3137 assert_different_registers(c_rarg0, dst, dst_pos, length); 3138 __ movl2ptr(src_pos, src_pos); //higher 32bits must be null 3139 __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); 3140 assert_different_registers(c_rarg1, length); 3141 __ movl2ptr(dst_pos, dst_pos); //higher 32bits must be null 3142 __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); 3143 __ mov(c_rarg2, length); 3144 3145 #else 3146 __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); 3147 store_parameter(tmp, 0); 3148 __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); 3149 store_parameter(tmp, 1); 3150 store_parameter(length, 2); 3151 #endif // _LP64 3152 if (basic_type == T_OBJECT) { 3153 __ call_VM_leaf(CAST_FROM_FN_PTR(address, Runtime1::oop_arraycopy), 0); 3154 } else { 3155 __ call_VM_leaf(CAST_FROM_FN_PTR(address, Runtime1::primitive_arraycopy), 0); 3156 } 3157 3158 __ bind(*stub->continuation()); 3159 } 3160 3161 3162 void LIR_Assembler::emit_lock(LIR_OpLock* op) { 3163 Register obj = op->obj_opr()->as_register(); // may not be an oop 3164 Register hdr = op->hdr_opr()->as_register(); 3165 Register lock = op->lock_opr()->as_register(); 3166 if (!UseFastLocking) { 3167 __ jmp(*op->stub()->entry()); 3168 } else if (op->code() == lir_lock) { 3169 Register scratch = noreg; 3170 if (UseBiasedLocking) { 3171 scratch = op->scratch_opr()->as_register(); 3172 } 3173 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header"); 3174 // add debug info for NullPointerException only if one is possible 3175 int null_check_offset = __ lock_object(hdr, obj, lock, scratch, *op->stub()->entry()); 3176 if (op->info() != NULL) { 3177 add_debug_info_for_null_check(null_check_offset, op->info()); 3178 } 3179 // done 3180 } else if (op->code() == lir_unlock) { 3181 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header"); 3182 __ unlock_object(hdr, obj, lock, *op->stub()->entry()); 3183 } else { 3184 Unimplemented(); 3185 } 3186 __ bind(*op->stub()->continuation()); 3187 } 3188 3189 3190 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) { 3191 ciMethod* method = op->profiled_method(); 3192 int bci = op->profiled_bci(); 3193 3194 // Update counter for all call types 3195 ciMethodData* md = method->method_data(); 3196 if (md == NULL) { 3197 bailout("out of memory building methodDataOop"); 3198 return; 3199 } 3200 ciProfileData* data = md->bci_to_data(bci); 3201 assert(data->is_CounterData(), "need CounterData for calls"); 3202 assert(op->mdo()->is_single_cpu(), "mdo must be allocated"); 3203 Register mdo = op->mdo()->as_register(); 3204 __ movoop(mdo, md->constant_encoding()); 3205 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset())); 3206 Bytecodes::Code bc = method->java_code_at_bci(bci); 3207 // Perform additional virtual call profiling for invokevirtual and 3208 // invokeinterface bytecodes 3209 if ((bc == Bytecodes::_invokevirtual || bc == Bytecodes::_invokeinterface) && 3210 Tier1ProfileVirtualCalls) { 3211 assert(op->recv()->is_single_cpu(), "recv must be allocated"); 3212 Register recv = op->recv()->as_register(); 3213 assert_different_registers(mdo, recv); 3214 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls"); 3215 ciKlass* known_klass = op->known_holder(); 3216 if (Tier1OptimizeVirtualCallProfiling && known_klass != NULL) { 3217 // We know the type that will be seen at this call site; we can 3218 // statically update the methodDataOop rather than needing to do 3219 // dynamic tests on the receiver type 3220 3221 // NOTE: we should probably put a lock around this search to 3222 // avoid collisions by concurrent compilations 3223 ciVirtualCallData* vc_data = (ciVirtualCallData*) data; 3224 uint i; 3225 for (i = 0; i < VirtualCallData::row_limit(); i++) { 3226 ciKlass* receiver = vc_data->receiver(i); 3227 if (known_klass->equals(receiver)) { 3228 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i))); 3229 __ addl(data_addr, DataLayout::counter_increment); 3230 return; 3231 } 3232 } 3233 3234 // Receiver type not found in profile data; select an empty slot 3235 3236 // Note that this is less efficient than it should be because it 3237 // always does a write to the receiver part of the 3238 // VirtualCallData rather than just the first time 3239 for (i = 0; i < VirtualCallData::row_limit(); i++) { 3240 ciKlass* receiver = vc_data->receiver(i); 3241 if (receiver == NULL) { 3242 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i))); 3243 __ movoop(recv_addr, known_klass->constant_encoding()); 3244 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i))); 3245 __ addl(data_addr, DataLayout::counter_increment); 3246 return; 3247 } 3248 } 3249 } else { 3250 __ movptr(recv, Address(recv, oopDesc::klass_offset_in_bytes())); 3251 Label update_done; 3252 uint i; 3253 for (i = 0; i < VirtualCallData::row_limit(); i++) { 3254 Label next_test; 3255 // See if the receiver is receiver[n]. 3256 __ cmpptr(recv, Address(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)))); 3257 __ jcc(Assembler::notEqual, next_test); 3258 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i))); 3259 __ addl(data_addr, DataLayout::counter_increment); 3260 __ jmp(update_done); 3261 __ bind(next_test); 3262 } 3263 3264 // Didn't find receiver; find next empty slot and fill it in 3265 for (i = 0; i < VirtualCallData::row_limit(); i++) { 3266 Label next_test; 3267 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i))); 3268 __ cmpptr(recv_addr, (int32_t)NULL_WORD); 3269 __ jcc(Assembler::notEqual, next_test); 3270 __ movptr(recv_addr, recv); 3271 __ movl(Address(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i))), DataLayout::counter_increment); 3272 __ jmp(update_done); 3273 __ bind(next_test); 3274 } 3275 // Receiver did not match any saved receiver and there is no empty row for it. 3276 // Increment total counter to indicate polymorphic case. 3277 __ addl(counter_addr, DataLayout::counter_increment); 3278 3279 __ bind(update_done); 3280 } 3281 } else { 3282 // Static call 3283 __ addl(counter_addr, DataLayout::counter_increment); 3284 } 3285 } 3286 3287 3288 void LIR_Assembler::emit_delay(LIR_OpDelay*) { 3289 Unimplemented(); 3290 } 3291 3292 3293 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) { 3294 __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no)); 3295 } 3296 3297 3298 void LIR_Assembler::align_backward_branch_target() { 3299 __ align(BytesPerWord); 3300 } 3301 3302 3303 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest) { 3304 if (left->is_single_cpu()) { 3305 __ negl(left->as_register()); 3306 move_regs(left->as_register(), dest->as_register()); 3307 3308 } else if (left->is_double_cpu()) { 3309 Register lo = left->as_register_lo(); 3310 #ifdef _LP64 3311 Register dst = dest->as_register_lo(); 3312 __ movptr(dst, lo); 3313 __ negptr(dst); 3314 #else 3315 Register hi = left->as_register_hi(); 3316 __ lneg(hi, lo); 3317 if (dest->as_register_lo() == hi) { 3318 assert(dest->as_register_hi() != lo, "destroying register"); 3319 move_regs(hi, dest->as_register_hi()); 3320 move_regs(lo, dest->as_register_lo()); 3321 } else { 3322 move_regs(lo, dest->as_register_lo()); 3323 move_regs(hi, dest->as_register_hi()); 3324 } 3325 #endif // _LP64 3326 3327 } else if (dest->is_single_xmm()) { 3328 if (left->as_xmm_float_reg() != dest->as_xmm_float_reg()) { 3329 __ movflt(dest->as_xmm_float_reg(), left->as_xmm_float_reg()); 3330 } 3331 __ xorps(dest->as_xmm_float_reg(), 3332 ExternalAddress((address)float_signflip_pool)); 3333 3334 } else if (dest->is_double_xmm()) { 3335 if (left->as_xmm_double_reg() != dest->as_xmm_double_reg()) { 3336 __ movdbl(dest->as_xmm_double_reg(), left->as_xmm_double_reg()); 3337 } 3338 __ xorpd(dest->as_xmm_double_reg(), 3339 ExternalAddress((address)double_signflip_pool)); 3340 3341 } else if (left->is_single_fpu() || left->is_double_fpu()) { 3342 assert(left->fpu() == 0, "arg must be on TOS"); 3343 assert(dest->fpu() == 0, "dest must be TOS"); 3344 __ fchs(); 3345 3346 } else { 3347 ShouldNotReachHere(); 3348 } 3349 } 3350 3351 3352 void LIR_Assembler::leal(LIR_Opr addr, LIR_Opr dest) { 3353 assert(addr->is_address() && dest->is_register(), "check"); 3354 Register reg; 3355 reg = dest->as_pointer_register(); 3356 __ lea(reg, as_Address(addr->as_address_ptr())); 3357 } 3358 3359 3360 3361 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) { 3362 assert(!tmp->is_valid(), "don't need temporary"); 3363 __ call(RuntimeAddress(dest)); 3364 if (info != NULL) { 3365 add_call_info_here(info); 3366 } 3367 } 3368 3369 3370 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) { 3371 assert(type == T_LONG, "only for volatile long fields"); 3372 3373 if (info != NULL) { 3374 add_debug_info_for_null_check_here(info); 3375 } 3376 3377 if (src->is_double_xmm()) { 3378 if (dest->is_double_cpu()) { 3379 #ifdef _LP64 3380 __ movdq(dest->as_register_lo(), src->as_xmm_double_reg()); 3381 #else 3382 __ movdl(dest->as_register_lo(), src->as_xmm_double_reg()); 3383 __ psrlq(src->as_xmm_double_reg(), 32); 3384 __ movdl(dest->as_register_hi(), src->as_xmm_double_reg()); 3385 #endif // _LP64 3386 } else if (dest->is_double_stack()) { 3387 __ movdbl(frame_map()->address_for_slot(dest->double_stack_ix()), src->as_xmm_double_reg()); 3388 } else if (dest->is_address()) { 3389 __ movdbl(as_Address(dest->as_address_ptr()), src->as_xmm_double_reg()); 3390 } else { 3391 ShouldNotReachHere(); 3392 } 3393 3394 } else if (dest->is_double_xmm()) { 3395 if (src->is_double_stack()) { 3396 __ movdbl(dest->as_xmm_double_reg(), frame_map()->address_for_slot(src->double_stack_ix())); 3397 } else if (src->is_address()) { 3398 __ movdbl(dest->as_xmm_double_reg(), as_Address(src->as_address_ptr())); 3399 } else { 3400 ShouldNotReachHere(); 3401 } 3402 3403 } else if (src->is_double_fpu()) { 3404 assert(src->fpu_regnrLo() == 0, "must be TOS"); 3405 if (dest->is_double_stack()) { 3406 __ fistp_d(frame_map()->address_for_slot(dest->double_stack_ix())); 3407 } else if (dest->is_address()) { 3408 __ fistp_d(as_Address(dest->as_address_ptr())); 3409 } else { 3410 ShouldNotReachHere(); 3411 } 3412 3413 } else if (dest->is_double_fpu()) { 3414 assert(dest->fpu_regnrLo() == 0, "must be TOS"); 3415 if (src->is_double_stack()) { 3416 __ fild_d(frame_map()->address_for_slot(src->double_stack_ix())); 3417 } else if (src->is_address()) { 3418 __ fild_d(as_Address(src->as_address_ptr())); 3419 } else { 3420 ShouldNotReachHere(); 3421 } 3422 } else { 3423 ShouldNotReachHere(); 3424 } 3425 } 3426 3427 3428 void LIR_Assembler::membar() { 3429 // QQQ sparc TSO uses this, 3430 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad)); 3431 } 3432 3433 void LIR_Assembler::membar_acquire() { 3434 // No x86 machines currently require load fences 3435 // __ load_fence(); 3436 } 3437 3438 void LIR_Assembler::membar_release() { 3439 // No x86 machines currently require store fences 3440 // __ store_fence(); 3441 } 3442 3443 void LIR_Assembler::get_thread(LIR_Opr result_reg) { 3444 assert(result_reg->is_register(), "check"); 3445 #ifdef _LP64 3446 // __ get_thread(result_reg->as_register_lo()); 3447 __ mov(result_reg->as_register(), r15_thread); 3448 #else 3449 __ get_thread(result_reg->as_register()); 3450 #endif // _LP64 3451 } 3452 3453 3454 void LIR_Assembler::peephole(LIR_List*) { 3455 // do nothing for now 3456 } 3457 3458 3459 #undef __