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--- old/src/cpu/x86/vm/c1_LIRAssembler_x86.cpp
+++ new/src/cpu/x86/vm/c1_LIRAssembler_x86.cpp
1 1 /*
2 2 * Copyright 2000-2010 Sun Microsystems, Inc. All Rights Reserved.
3 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 4 *
5 5 * This code is free software; you can redistribute it and/or modify it
6 6 * under the terms of the GNU General Public License version 2 only, as
7 7 * published by the Free Software Foundation.
8 8 *
9 9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 12 * version 2 for more details (a copy is included in the LICENSE file that
13 13 * accompanied this code).
14 14 *
15 15 * You should have received a copy of the GNU General Public License version
16 16 * 2 along with this work; if not, write to the Free Software Foundation,
17 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 18 *
19 19 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
20 20 * CA 95054 USA or visit www.sun.com if you need additional information or
21 21 * have any questions.
22 22 *
23 23 */
24 24
25 25 # include "incls/_precompiled.incl"
26 26 # include "incls/_c1_LIRAssembler_x86.cpp.incl"
27 27
28 28
29 29 // These masks are used to provide 128-bit aligned bitmasks to the XMM
30 30 // instructions, to allow sign-masking or sign-bit flipping. They allow
31 31 // fast versions of NegF/NegD and AbsF/AbsD.
32 32
33 33 // Note: 'double' and 'long long' have 32-bits alignment on x86.
34 34 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) {
35 35 // Use the expression (adr)&(~0xF) to provide 128-bits aligned address
36 36 // of 128-bits operands for SSE instructions.
37 37 jlong *operand = (jlong*)(((long)adr)&((long)(~0xF)));
38 38 // Store the value to a 128-bits operand.
39 39 operand[0] = lo;
40 40 operand[1] = hi;
41 41 return operand;
42 42 }
43 43
44 44 // Buffer for 128-bits masks used by SSE instructions.
45 45 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment)
46 46
47 47 // Static initialization during VM startup.
48 48 static jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF));
49 49 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF));
50 50 static jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], CONST64(0x8000000080000000), CONST64(0x8000000080000000));
51 51 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], CONST64(0x8000000000000000), CONST64(0x8000000000000000));
52 52
53 53
54 54
55 55 NEEDS_CLEANUP // remove this definitions ?
56 56 const Register IC_Klass = rax; // where the IC klass is cached
57 57 const Register SYNC_header = rax; // synchronization header
58 58 const Register SHIFT_count = rcx; // where count for shift operations must be
59 59
60 60 #define __ _masm->
61 61
62 62
63 63 static void select_different_registers(Register preserve,
64 64 Register extra,
65 65 Register &tmp1,
66 66 Register &tmp2) {
67 67 if (tmp1 == preserve) {
68 68 assert_different_registers(tmp1, tmp2, extra);
69 69 tmp1 = extra;
70 70 } else if (tmp2 == preserve) {
71 71 assert_different_registers(tmp1, tmp2, extra);
72 72 tmp2 = extra;
73 73 }
74 74 assert_different_registers(preserve, tmp1, tmp2);
75 75 }
76 76
77 77
78 78
79 79 static void select_different_registers(Register preserve,
80 80 Register extra,
81 81 Register &tmp1,
82 82 Register &tmp2,
83 83 Register &tmp3) {
84 84 if (tmp1 == preserve) {
85 85 assert_different_registers(tmp1, tmp2, tmp3, extra);
86 86 tmp1 = extra;
87 87 } else if (tmp2 == preserve) {
88 88 assert_different_registers(tmp1, tmp2, tmp3, extra);
89 89 tmp2 = extra;
90 90 } else if (tmp3 == preserve) {
91 91 assert_different_registers(tmp1, tmp2, tmp3, extra);
92 92 tmp3 = extra;
93 93 }
94 94 assert_different_registers(preserve, tmp1, tmp2, tmp3);
95 95 }
96 96
97 97
98 98
99 99 bool LIR_Assembler::is_small_constant(LIR_Opr opr) {
100 100 if (opr->is_constant()) {
101 101 LIR_Const* constant = opr->as_constant_ptr();
102 102 switch (constant->type()) {
103 103 case T_INT: {
104 104 return true;
105 105 }
106 106
107 107 default:
108 108 return false;
109 109 }
110 110 }
111 111 return false;
112 112 }
113 113
114 114
115 115 LIR_Opr LIR_Assembler::receiverOpr() {
116 116 return FrameMap::receiver_opr;
117 117 }
118 118
119 119 LIR_Opr LIR_Assembler::incomingReceiverOpr() {
120 120 return receiverOpr();
121 121 }
122 122
123 123 LIR_Opr LIR_Assembler::osrBufferPointer() {
124 124 return FrameMap::as_pointer_opr(receiverOpr()->as_register());
125 125 }
126 126
127 127 //--------------fpu register translations-----------------------
128 128
129 129
130 130 address LIR_Assembler::float_constant(float f) {
131 131 address const_addr = __ float_constant(f);
132 132 if (const_addr == NULL) {
133 133 bailout("const section overflow");
134 134 return __ code()->consts()->start();
135 135 } else {
136 136 return const_addr;
137 137 }
138 138 }
139 139
140 140
141 141 address LIR_Assembler::double_constant(double d) {
142 142 address const_addr = __ double_constant(d);
143 143 if (const_addr == NULL) {
144 144 bailout("const section overflow");
145 145 return __ code()->consts()->start();
146 146 } else {
147 147 return const_addr;
148 148 }
149 149 }
150 150
151 151
152 152 void LIR_Assembler::set_24bit_FPU() {
153 153 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
154 154 }
155 155
156 156 void LIR_Assembler::reset_FPU() {
157 157 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
158 158 }
159 159
160 160 void LIR_Assembler::fpop() {
161 161 __ fpop();
162 162 }
163 163
164 164 void LIR_Assembler::fxch(int i) {
165 165 __ fxch(i);
166 166 }
167 167
168 168 void LIR_Assembler::fld(int i) {
169 169 __ fld_s(i);
170 170 }
171 171
172 172 void LIR_Assembler::ffree(int i) {
173 173 __ ffree(i);
174 174 }
175 175
176 176 void LIR_Assembler::breakpoint() {
177 177 __ int3();
178 178 }
179 179
180 180 void LIR_Assembler::push(LIR_Opr opr) {
181 181 if (opr->is_single_cpu()) {
182 182 __ push_reg(opr->as_register());
183 183 } else if (opr->is_double_cpu()) {
184 184 NOT_LP64(__ push_reg(opr->as_register_hi()));
185 185 __ push_reg(opr->as_register_lo());
186 186 } else if (opr->is_stack()) {
187 187 __ push_addr(frame_map()->address_for_slot(opr->single_stack_ix()));
188 188 } else if (opr->is_constant()) {
189 189 LIR_Const* const_opr = opr->as_constant_ptr();
190 190 if (const_opr->type() == T_OBJECT) {
191 191 __ push_oop(const_opr->as_jobject());
192 192 } else if (const_opr->type() == T_INT) {
193 193 __ push_jint(const_opr->as_jint());
194 194 } else {
195 195 ShouldNotReachHere();
196 196 }
197 197
198 198 } else {
199 199 ShouldNotReachHere();
200 200 }
201 201 }
202 202
203 203 void LIR_Assembler::pop(LIR_Opr opr) {
204 204 if (opr->is_single_cpu()) {
205 205 __ pop_reg(opr->as_register());
206 206 } else {
207 207 ShouldNotReachHere();
208 208 }
209 209 }
210 210
211 211 bool LIR_Assembler::is_literal_address(LIR_Address* addr) {
212 212 return addr->base()->is_illegal() && addr->index()->is_illegal();
213 213 }
214 214
215 215 //-------------------------------------------
216 216
217 217 Address LIR_Assembler::as_Address(LIR_Address* addr) {
218 218 return as_Address(addr, rscratch1);
219 219 }
220 220
221 221 Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) {
222 222 if (addr->base()->is_illegal()) {
223 223 assert(addr->index()->is_illegal(), "must be illegal too");
224 224 AddressLiteral laddr((address)addr->disp(), relocInfo::none);
225 225 if (! __ reachable(laddr)) {
226 226 __ movptr(tmp, laddr.addr());
227 227 Address res(tmp, 0);
228 228 return res;
229 229 } else {
230 230 return __ as_Address(laddr);
231 231 }
232 232 }
233 233
234 234 Register base = addr->base()->as_pointer_register();
235 235
236 236 if (addr->index()->is_illegal()) {
237 237 return Address( base, addr->disp());
238 238 } else if (addr->index()->is_cpu_register()) {
239 239 Register index = addr->index()->as_pointer_register();
240 240 return Address(base, index, (Address::ScaleFactor) addr->scale(), addr->disp());
241 241 } else if (addr->index()->is_constant()) {
242 242 intptr_t addr_offset = (addr->index()->as_constant_ptr()->as_jint() << addr->scale()) + addr->disp();
243 243 assert(Assembler::is_simm32(addr_offset), "must be");
244 244
245 245 return Address(base, addr_offset);
246 246 } else {
247 247 Unimplemented();
248 248 return Address();
249 249 }
250 250 }
251 251
252 252
253 253 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
254 254 Address base = as_Address(addr);
255 255 return Address(base._base, base._index, base._scale, base._disp + BytesPerWord);
256 256 }
257 257
258 258
259 259 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
260 260 return as_Address(addr);
261 261 }
262 262
263 263
264 264 void LIR_Assembler::osr_entry() {
265 265 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
266 266 BlockBegin* osr_entry = compilation()->hir()->osr_entry();
267 267 ValueStack* entry_state = osr_entry->state();
268 268 int number_of_locks = entry_state->locks_size();
269 269
270 270 // we jump here if osr happens with the interpreter
271 271 // state set up to continue at the beginning of the
272 272 // loop that triggered osr - in particular, we have
273 273 // the following registers setup:
274 274 //
275 275 // rcx: osr buffer
276 276 //
277 277
278 278 // build frame
279 279 ciMethod* m = compilation()->method();
280 280 __ build_frame(initial_frame_size_in_bytes());
281 281
282 282 // OSR buffer is
283 283 //
284 284 // locals[nlocals-1..0]
285 285 // monitors[0..number_of_locks]
286 286 //
287 287 // locals is a direct copy of the interpreter frame so in the osr buffer
288 288 // so first slot in the local array is the last local from the interpreter
289 289 // and last slot is local[0] (receiver) from the interpreter
290 290 //
291 291 // Similarly with locks. The first lock slot in the osr buffer is the nth lock
292 292 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
293 293 // in the interpreter frame (the method lock if a sync method)
294 294
295 295 // Initialize monitors in the compiled activation.
296 296 // rcx: pointer to osr buffer
297 297 //
298 298 // All other registers are dead at this point and the locals will be
299 299 // copied into place by code emitted in the IR.
300 300
301 301 Register OSR_buf = osrBufferPointer()->as_pointer_register();
302 302 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
303 303 int monitor_offset = BytesPerWord * method()->max_locals() +
304 304 (2 * BytesPerWord) * (number_of_locks - 1);
305 305 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
306 306 // the OSR buffer using 2 word entries: first the lock and then
307 307 // the oop.
308 308 for (int i = 0; i < number_of_locks; i++) {
309 309 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
310 310 #ifdef ASSERT
311 311 // verify the interpreter's monitor has a non-null object
312 312 {
313 313 Label L;
314 314 __ cmpptr(Address(OSR_buf, slot_offset + 1*BytesPerWord), (int32_t)NULL_WORD);
315 315 __ jcc(Assembler::notZero, L);
316 316 __ stop("locked object is NULL");
317 317 __ bind(L);
318 318 }
319 319 #endif
320 320 __ movptr(rbx, Address(OSR_buf, slot_offset + 0));
321 321 __ movptr(frame_map()->address_for_monitor_lock(i), rbx);
322 322 __ movptr(rbx, Address(OSR_buf, slot_offset + 1*BytesPerWord));
323 323 __ movptr(frame_map()->address_for_monitor_object(i), rbx);
324 324 }
325 325 }
326 326 }
327 327
328 328
329 329 // inline cache check; done before the frame is built.
330 330 int LIR_Assembler::check_icache() {
331 331 Register receiver = FrameMap::receiver_opr->as_register();
332 332 Register ic_klass = IC_Klass;
333 333 const int ic_cmp_size = LP64_ONLY(10) NOT_LP64(9);
334 334
335 335 if (!VerifyOops) {
336 336 // insert some nops so that the verified entry point is aligned on CodeEntryAlignment
337 337 while ((__ offset() + ic_cmp_size) % CodeEntryAlignment != 0) {
338 338 __ nop();
339 339 }
340 340 }
341 341 int offset = __ offset();
342 342 __ inline_cache_check(receiver, IC_Klass);
343 343 assert(__ offset() % CodeEntryAlignment == 0 || VerifyOops, "alignment must be correct");
344 344 if (VerifyOops) {
345 345 // force alignment after the cache check.
346 346 // It's been verified to be aligned if !VerifyOops
347 347 __ align(CodeEntryAlignment);
348 348 }
349 349 return offset;
350 350 }
351 351
352 352
353 353 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo* info) {
354 354 jobject o = NULL;
355 355 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id);
356 356 __ movoop(reg, o);
357 357 patching_epilog(patch, lir_patch_normal, reg, info);
358 358 }
359 359
360 360
361 361 void LIR_Assembler::monitorexit(LIR_Opr obj_opr, LIR_Opr lock_opr, Register new_hdr, int monitor_no, Register exception) {
362 362 if (exception->is_valid()) {
363 363 // preserve exception
364 364 // note: the monitor_exit runtime call is a leaf routine
365 365 // and cannot block => no GC can happen
366 366 // The slow case (MonitorAccessStub) uses the first two stack slots
367 367 // ([esp+0] and [esp+4]), therefore we store the exception at [esp+8]
368 368 __ movptr (Address(rsp, 2*wordSize), exception);
369 369 }
370 370
371 371 Register obj_reg = obj_opr->as_register();
372 372 Register lock_reg = lock_opr->as_register();
373 373
374 374 // setup registers (lock_reg must be rax, for lock_object)
375 375 assert(obj_reg != SYNC_header && lock_reg != SYNC_header, "rax, must be available here");
376 376 Register hdr = lock_reg;
377 377 assert(new_hdr == SYNC_header, "wrong register");
378 378 lock_reg = new_hdr;
379 379 // compute pointer to BasicLock
380 380 Address lock_addr = frame_map()->address_for_monitor_lock(monitor_no);
381 381 __ lea(lock_reg, lock_addr);
382 382 // unlock object
383 383 MonitorAccessStub* slow_case = new MonitorExitStub(lock_opr, true, monitor_no);
384 384 // _slow_case_stubs->append(slow_case);
385 385 // temporary fix: must be created after exceptionhandler, therefore as call stub
386 386 _slow_case_stubs->append(slow_case);
387 387 if (UseFastLocking) {
388 388 // try inlined fast unlocking first, revert to slow locking if it fails
389 389 // note: lock_reg points to the displaced header since the displaced header offset is 0!
390 390 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
391 391 __ unlock_object(hdr, obj_reg, lock_reg, *slow_case->entry());
392 392 } else {
393 393 // always do slow unlocking
394 394 // note: the slow unlocking code could be inlined here, however if we use
395 395 // slow unlocking, speed doesn't matter anyway and this solution is
396 396 // simpler and requires less duplicated code - additionally, the
397 397 // slow unlocking code is the same in either case which simplifies
398 398 // debugging
399 399 __ jmp(*slow_case->entry());
400 400 }
401 401 // done
402 402 __ bind(*slow_case->continuation());
403 403
404 404 if (exception->is_valid()) {
405 405 // restore exception
406 406 __ movptr (exception, Address(rsp, 2 * wordSize));
407 407 }
408 408 }
409 409
410 410 // This specifies the rsp decrement needed to build the frame
411 411 int LIR_Assembler::initial_frame_size_in_bytes() {
412 412 // if rounding, must let FrameMap know!
413 413
414 414 // The frame_map records size in slots (32bit word)
415 415
416 416 // subtract two words to account for return address and link
417 417 return (frame_map()->framesize() - (2*VMRegImpl::slots_per_word)) * VMRegImpl::stack_slot_size;
418 418 }
419 419
420 420
421 421 int LIR_Assembler::emit_exception_handler() {
422 422 // if the last instruction is a call (typically to do a throw which
423 423 // is coming at the end after block reordering) the return address
424 424 // must still point into the code area in order to avoid assertion
425 425 // failures when searching for the corresponding bci => add a nop
426 426 // (was bug 5/14/1999 - gri)
427 427 __ nop();
428 428
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429 429 // generate code for exception handler
430 430 address handler_base = __ start_a_stub(exception_handler_size);
431 431 if (handler_base == NULL) {
432 432 // not enough space left for the handler
433 433 bailout("exception handler overflow");
434 434 return -1;
435 435 }
436 436
437 437 int offset = code_offset();
438 438
439 - // if the method does not have an exception handler, then there is
440 - // no reason to search for one
441 - if (compilation()->has_exception_handlers() || compilation()->env()->jvmti_can_post_on_exceptions()) {
442 - // the exception oop and pc are in rax, and rdx
443 - // no other registers need to be preserved, so invalidate them
444 - __ invalidate_registers(false, true, true, false, true, true);
445 -
446 - // check that there is really an exception
447 - __ verify_not_null_oop(rax);
448 -
449 - // search an exception handler (rax: exception oop, rdx: throwing pc)
450 - __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::handle_exception_nofpu_id)));
451 -
452 - // if the call returns here, then the exception handler for particular
453 - // exception doesn't exist -> unwind activation and forward exception to caller
454 - }
455 -
456 - // the exception oop is in rax,
439 + // the exception oop and pc are in rax, and rdx
457 440 // no other registers need to be preserved, so invalidate them
458 - __ invalidate_registers(false, true, true, true, true, true);
441 + __ invalidate_registers(false, true, true, false, true, true);
459 442
460 443 // check that there is really an exception
461 444 __ verify_not_null_oop(rax);
462 445
463 - // unlock the receiver/klass if necessary
464 - // rax,: exception
465 - ciMethod* method = compilation()->method();
466 - if (method->is_synchronized() && GenerateSynchronizationCode) {
467 - monitorexit(FrameMap::rbx_oop_opr, FrameMap::rcx_opr, SYNC_header, 0, rax);
468 - }
446 + // search an exception handler (rax: exception oop, rdx: throwing pc)
447 + __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::handle_exception_nofpu_id)));
448 +
449 + __ stop("should not reach here");
469 450
470 - // unwind activation and forward exception to caller
471 - // rax,: exception
472 - __ jump(RuntimeAddress(Runtime1::entry_for(Runtime1::unwind_exception_id)));
473 451 assert(code_offset() - offset <= exception_handler_size, "overflow");
474 452 __ end_a_stub();
475 453
476 454 return offset;
477 455 }
478 456
479 457
480 458 int LIR_Assembler::emit_deopt_handler() {
481 459 // if the last instruction is a call (typically to do a throw which
482 460 // is coming at the end after block reordering) the return address
483 461 // must still point into the code area in order to avoid assertion
484 462 // failures when searching for the corresponding bci => add a nop
485 463 // (was bug 5/14/1999 - gri)
486 464 __ nop();
487 465
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488 466 // generate code for exception handler
489 467 address handler_base = __ start_a_stub(deopt_handler_size);
490 468 if (handler_base == NULL) {
491 469 // not enough space left for the handler
492 470 bailout("deopt handler overflow");
493 471 return -1;
494 472 }
495 473
496 474 int offset = code_offset();
497 475 InternalAddress here(__ pc());
476 +
498 477 __ pushptr(here.addr());
499 478 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
479 +
500 480 assert(code_offset() - offset <= deopt_handler_size, "overflow");
501 481 __ end_a_stub();
502 482
503 483 return offset;
504 484 }
505 485
506 486
507 487 // This is the fast version of java.lang.String.compare; it has not
508 488 // OSR-entry and therefore, we generate a slow version for OSR's
509 489 void LIR_Assembler::emit_string_compare(LIR_Opr arg0, LIR_Opr arg1, LIR_Opr dst, CodeEmitInfo* info) {
510 490 __ movptr (rbx, rcx); // receiver is in rcx
511 491 __ movptr (rax, arg1->as_register());
512 492
513 493 // Get addresses of first characters from both Strings
514 494 __ movptr (rsi, Address(rax, java_lang_String::value_offset_in_bytes()));
515 495 __ movptr (rcx, Address(rax, java_lang_String::offset_offset_in_bytes()));
516 496 __ lea (rsi, Address(rsi, rcx, Address::times_2, arrayOopDesc::base_offset_in_bytes(T_CHAR)));
517 497
518 498
519 499 // rbx, may be NULL
520 500 add_debug_info_for_null_check_here(info);
521 501 __ movptr (rdi, Address(rbx, java_lang_String::value_offset_in_bytes()));
522 502 __ movptr (rcx, Address(rbx, java_lang_String::offset_offset_in_bytes()));
523 503 __ lea (rdi, Address(rdi, rcx, Address::times_2, arrayOopDesc::base_offset_in_bytes(T_CHAR)));
524 504
525 505 // compute minimum length (in rax) and difference of lengths (on top of stack)
526 506 if (VM_Version::supports_cmov()) {
527 507 __ movl (rbx, Address(rbx, java_lang_String::count_offset_in_bytes()));
528 508 __ movl (rax, Address(rax, java_lang_String::count_offset_in_bytes()));
529 509 __ mov (rcx, rbx);
530 510 __ subptr (rbx, rax); // subtract lengths
531 511 __ push (rbx); // result
532 512 __ cmov (Assembler::lessEqual, rax, rcx);
533 513 } else {
534 514 Label L;
535 515 __ movl (rbx, Address(rbx, java_lang_String::count_offset_in_bytes()));
536 516 __ movl (rcx, Address(rax, java_lang_String::count_offset_in_bytes()));
537 517 __ mov (rax, rbx);
538 518 __ subptr (rbx, rcx);
539 519 __ push (rbx);
540 520 __ jcc (Assembler::lessEqual, L);
541 521 __ mov (rax, rcx);
542 522 __ bind (L);
543 523 }
544 524 // is minimum length 0?
545 525 Label noLoop, haveResult;
546 526 __ testptr (rax, rax);
547 527 __ jcc (Assembler::zero, noLoop);
548 528
549 529 // compare first characters
550 530 __ load_unsigned_short(rcx, Address(rdi, 0));
551 531 __ load_unsigned_short(rbx, Address(rsi, 0));
552 532 __ subl(rcx, rbx);
553 533 __ jcc(Assembler::notZero, haveResult);
554 534 // starting loop
555 535 __ decrement(rax); // we already tested index: skip one
556 536 __ jcc(Assembler::zero, noLoop);
557 537
558 538 // set rsi.edi to the end of the arrays (arrays have same length)
559 539 // negate the index
560 540
561 541 __ lea(rsi, Address(rsi, rax, Address::times_2, type2aelembytes(T_CHAR)));
562 542 __ lea(rdi, Address(rdi, rax, Address::times_2, type2aelembytes(T_CHAR)));
563 543 __ negptr(rax);
564 544
565 545 // compare the strings in a loop
566 546
567 547 Label loop;
568 548 __ align(wordSize);
569 549 __ bind(loop);
570 550 __ load_unsigned_short(rcx, Address(rdi, rax, Address::times_2, 0));
571 551 __ load_unsigned_short(rbx, Address(rsi, rax, Address::times_2, 0));
572 552 __ subl(rcx, rbx);
573 553 __ jcc(Assembler::notZero, haveResult);
574 554 __ increment(rax);
575 555 __ jcc(Assembler::notZero, loop);
576 556
577 557 // strings are equal up to min length
578 558
579 559 __ bind(noLoop);
580 560 __ pop(rax);
581 561 return_op(LIR_OprFact::illegalOpr);
582 562
583 563 __ bind(haveResult);
584 564 // leave instruction is going to discard the TOS value
585 565 __ mov (rax, rcx); // result of call is in rax,
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586 566 }
587 567
588 568
589 569 void LIR_Assembler::return_op(LIR_Opr result) {
590 570 assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == rax, "word returns are in rax,");
591 571 if (!result->is_illegal() && result->is_float_kind() && !result->is_xmm_register()) {
592 572 assert(result->fpu() == 0, "result must already be on TOS");
593 573 }
594 574
595 575 // Pop the stack before the safepoint code
596 - __ leave();
576 + __ remove_frame(initial_frame_size_in_bytes());
597 577
598 578 bool result_is_oop = result->is_valid() ? result->is_oop() : false;
599 579
600 580 // Note: we do not need to round double result; float result has the right precision
601 581 // the poll sets the condition code, but no data registers
602 582 AddressLiteral polling_page(os::get_polling_page() + (SafepointPollOffset % os::vm_page_size()),
603 583 relocInfo::poll_return_type);
604 584
605 585 // NOTE: the requires that the polling page be reachable else the reloc
606 586 // goes to the movq that loads the address and not the faulting instruction
607 587 // which breaks the signal handler code
608 588
609 589 __ test32(rax, polling_page);
610 590
611 591 __ ret(0);
612 592 }
613 593
614 594
615 595 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
616 596 AddressLiteral polling_page(os::get_polling_page() + (SafepointPollOffset % os::vm_page_size()),
617 597 relocInfo::poll_type);
618 598
619 599 if (info != NULL) {
620 600 add_debug_info_for_branch(info);
621 601 } else {
622 602 ShouldNotReachHere();
623 603 }
624 604
625 605 int offset = __ offset();
626 606
627 607 // NOTE: the requires that the polling page be reachable else the reloc
628 608 // goes to the movq that loads the address and not the faulting instruction
629 609 // which breaks the signal handler code
630 610
631 611 __ test32(rax, polling_page);
632 612 return offset;
633 613 }
634 614
635 615
636 616 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) {
637 617 if (from_reg != to_reg) __ mov(to_reg, from_reg);
638 618 }
639 619
640 620 void LIR_Assembler::swap_reg(Register a, Register b) {
641 621 __ xchgptr(a, b);
642 622 }
643 623
644 624
645 625 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
646 626 assert(src->is_constant(), "should not call otherwise");
647 627 assert(dest->is_register(), "should not call otherwise");
648 628 LIR_Const* c = src->as_constant_ptr();
649 629
650 630 switch (c->type()) {
651 631 case T_INT: {
652 632 assert(patch_code == lir_patch_none, "no patching handled here");
653 633 __ movl(dest->as_register(), c->as_jint());
654 634 break;
655 635 }
656 636
657 637 case T_LONG: {
658 638 assert(patch_code == lir_patch_none, "no patching handled here");
659 639 #ifdef _LP64
660 640 __ movptr(dest->as_register_lo(), (intptr_t)c->as_jlong());
661 641 #else
662 642 __ movptr(dest->as_register_lo(), c->as_jint_lo());
663 643 __ movptr(dest->as_register_hi(), c->as_jint_hi());
664 644 #endif // _LP64
665 645 break;
666 646 }
667 647
668 648 case T_OBJECT: {
669 649 if (patch_code != lir_patch_none) {
670 650 jobject2reg_with_patching(dest->as_register(), info);
671 651 } else {
672 652 __ movoop(dest->as_register(), c->as_jobject());
673 653 }
674 654 break;
675 655 }
676 656
677 657 case T_FLOAT: {
678 658 if (dest->is_single_xmm()) {
679 659 if (c->is_zero_float()) {
680 660 __ xorps(dest->as_xmm_float_reg(), dest->as_xmm_float_reg());
681 661 } else {
682 662 __ movflt(dest->as_xmm_float_reg(),
683 663 InternalAddress(float_constant(c->as_jfloat())));
684 664 }
685 665 } else {
686 666 assert(dest->is_single_fpu(), "must be");
687 667 assert(dest->fpu_regnr() == 0, "dest must be TOS");
688 668 if (c->is_zero_float()) {
689 669 __ fldz();
690 670 } else if (c->is_one_float()) {
691 671 __ fld1();
692 672 } else {
693 673 __ fld_s (InternalAddress(float_constant(c->as_jfloat())));
694 674 }
695 675 }
696 676 break;
697 677 }
698 678
699 679 case T_DOUBLE: {
700 680 if (dest->is_double_xmm()) {
701 681 if (c->is_zero_double()) {
702 682 __ xorpd(dest->as_xmm_double_reg(), dest->as_xmm_double_reg());
703 683 } else {
704 684 __ movdbl(dest->as_xmm_double_reg(),
705 685 InternalAddress(double_constant(c->as_jdouble())));
706 686 }
707 687 } else {
708 688 assert(dest->is_double_fpu(), "must be");
709 689 assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
710 690 if (c->is_zero_double()) {
711 691 __ fldz();
712 692 } else if (c->is_one_double()) {
713 693 __ fld1();
714 694 } else {
715 695 __ fld_d (InternalAddress(double_constant(c->as_jdouble())));
716 696 }
717 697 }
718 698 break;
719 699 }
720 700
721 701 default:
722 702 ShouldNotReachHere();
723 703 }
724 704 }
725 705
726 706 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
727 707 assert(src->is_constant(), "should not call otherwise");
728 708 assert(dest->is_stack(), "should not call otherwise");
729 709 LIR_Const* c = src->as_constant_ptr();
730 710
731 711 switch (c->type()) {
732 712 case T_INT: // fall through
733 713 case T_FLOAT:
734 714 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits());
735 715 break;
736 716
737 717 case T_OBJECT:
738 718 __ movoop(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jobject());
739 719 break;
740 720
741 721 case T_LONG: // fall through
742 722 case T_DOUBLE:
743 723 #ifdef _LP64
744 724 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
745 725 lo_word_offset_in_bytes), (intptr_t)c->as_jlong_bits());
746 726 #else
747 727 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
748 728 lo_word_offset_in_bytes), c->as_jint_lo_bits());
749 729 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
750 730 hi_word_offset_in_bytes), c->as_jint_hi_bits());
751 731 #endif // _LP64
752 732 break;
753 733
754 734 default:
755 735 ShouldNotReachHere();
756 736 }
757 737 }
758 738
759 739 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info ) {
760 740 assert(src->is_constant(), "should not call otherwise");
761 741 assert(dest->is_address(), "should not call otherwise");
762 742 LIR_Const* c = src->as_constant_ptr();
763 743 LIR_Address* addr = dest->as_address_ptr();
764 744
765 745 int null_check_here = code_offset();
766 746 switch (type) {
767 747 case T_INT: // fall through
768 748 case T_FLOAT:
769 749 __ movl(as_Address(addr), c->as_jint_bits());
770 750 break;
771 751
772 752 case T_OBJECT: // fall through
773 753 case T_ARRAY:
774 754 if (c->as_jobject() == NULL) {
775 755 __ movptr(as_Address(addr), NULL_WORD);
776 756 } else {
777 757 if (is_literal_address(addr)) {
778 758 ShouldNotReachHere();
779 759 __ movoop(as_Address(addr, noreg), c->as_jobject());
780 760 } else {
781 761 #ifdef _LP64
782 762 __ movoop(rscratch1, c->as_jobject());
783 763 null_check_here = code_offset();
784 764 __ movptr(as_Address_lo(addr), rscratch1);
785 765 #else
786 766 __ movoop(as_Address(addr), c->as_jobject());
787 767 #endif
788 768 }
789 769 }
790 770 break;
791 771
792 772 case T_LONG: // fall through
793 773 case T_DOUBLE:
794 774 #ifdef _LP64
795 775 if (is_literal_address(addr)) {
796 776 ShouldNotReachHere();
797 777 __ movptr(as_Address(addr, r15_thread), (intptr_t)c->as_jlong_bits());
798 778 } else {
799 779 __ movptr(r10, (intptr_t)c->as_jlong_bits());
800 780 null_check_here = code_offset();
801 781 __ movptr(as_Address_lo(addr), r10);
802 782 }
803 783 #else
804 784 // Always reachable in 32bit so this doesn't produce useless move literal
805 785 __ movptr(as_Address_hi(addr), c->as_jint_hi_bits());
806 786 __ movptr(as_Address_lo(addr), c->as_jint_lo_bits());
807 787 #endif // _LP64
808 788 break;
809 789
810 790 case T_BOOLEAN: // fall through
811 791 case T_BYTE:
812 792 __ movb(as_Address(addr), c->as_jint() & 0xFF);
813 793 break;
814 794
815 795 case T_CHAR: // fall through
816 796 case T_SHORT:
817 797 __ movw(as_Address(addr), c->as_jint() & 0xFFFF);
818 798 break;
819 799
820 800 default:
821 801 ShouldNotReachHere();
822 802 };
823 803
824 804 if (info != NULL) {
825 805 add_debug_info_for_null_check(null_check_here, info);
826 806 }
827 807 }
828 808
829 809
830 810 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) {
831 811 assert(src->is_register(), "should not call otherwise");
832 812 assert(dest->is_register(), "should not call otherwise");
833 813
834 814 // move between cpu-registers
835 815 if (dest->is_single_cpu()) {
836 816 #ifdef _LP64
837 817 if (src->type() == T_LONG) {
838 818 // Can do LONG -> OBJECT
839 819 move_regs(src->as_register_lo(), dest->as_register());
840 820 return;
841 821 }
842 822 #endif
843 823 assert(src->is_single_cpu(), "must match");
844 824 if (src->type() == T_OBJECT) {
845 825 __ verify_oop(src->as_register());
846 826 }
847 827 move_regs(src->as_register(), dest->as_register());
848 828
849 829 } else if (dest->is_double_cpu()) {
850 830 #ifdef _LP64
851 831 if (src->type() == T_OBJECT || src->type() == T_ARRAY) {
852 832 // Surprising to me but we can see move of a long to t_object
853 833 __ verify_oop(src->as_register());
854 834 move_regs(src->as_register(), dest->as_register_lo());
855 835 return;
856 836 }
857 837 #endif
858 838 assert(src->is_double_cpu(), "must match");
859 839 Register f_lo = src->as_register_lo();
860 840 Register f_hi = src->as_register_hi();
861 841 Register t_lo = dest->as_register_lo();
862 842 Register t_hi = dest->as_register_hi();
863 843 #ifdef _LP64
864 844 assert(f_hi == f_lo, "must be same");
865 845 assert(t_hi == t_lo, "must be same");
866 846 move_regs(f_lo, t_lo);
867 847 #else
868 848 assert(f_lo != f_hi && t_lo != t_hi, "invalid register allocation");
869 849
870 850
871 851 if (f_lo == t_hi && f_hi == t_lo) {
872 852 swap_reg(f_lo, f_hi);
873 853 } else if (f_hi == t_lo) {
874 854 assert(f_lo != t_hi, "overwriting register");
875 855 move_regs(f_hi, t_hi);
876 856 move_regs(f_lo, t_lo);
877 857 } else {
878 858 assert(f_hi != t_lo, "overwriting register");
879 859 move_regs(f_lo, t_lo);
880 860 move_regs(f_hi, t_hi);
881 861 }
882 862 #endif // LP64
883 863
884 864 // special moves from fpu-register to xmm-register
885 865 // necessary for method results
886 866 } else if (src->is_single_xmm() && !dest->is_single_xmm()) {
887 867 __ movflt(Address(rsp, 0), src->as_xmm_float_reg());
888 868 __ fld_s(Address(rsp, 0));
889 869 } else if (src->is_double_xmm() && !dest->is_double_xmm()) {
890 870 __ movdbl(Address(rsp, 0), src->as_xmm_double_reg());
891 871 __ fld_d(Address(rsp, 0));
892 872 } else if (dest->is_single_xmm() && !src->is_single_xmm()) {
893 873 __ fstp_s(Address(rsp, 0));
894 874 __ movflt(dest->as_xmm_float_reg(), Address(rsp, 0));
895 875 } else if (dest->is_double_xmm() && !src->is_double_xmm()) {
896 876 __ fstp_d(Address(rsp, 0));
897 877 __ movdbl(dest->as_xmm_double_reg(), Address(rsp, 0));
898 878
899 879 // move between xmm-registers
900 880 } else if (dest->is_single_xmm()) {
901 881 assert(src->is_single_xmm(), "must match");
902 882 __ movflt(dest->as_xmm_float_reg(), src->as_xmm_float_reg());
903 883 } else if (dest->is_double_xmm()) {
904 884 assert(src->is_double_xmm(), "must match");
905 885 __ movdbl(dest->as_xmm_double_reg(), src->as_xmm_double_reg());
906 886
907 887 // move between fpu-registers (no instruction necessary because of fpu-stack)
908 888 } else if (dest->is_single_fpu() || dest->is_double_fpu()) {
909 889 assert(src->is_single_fpu() || src->is_double_fpu(), "must match");
910 890 assert(src->fpu() == dest->fpu(), "currently should be nothing to do");
911 891 } else {
912 892 ShouldNotReachHere();
913 893 }
914 894 }
915 895
916 896 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) {
917 897 assert(src->is_register(), "should not call otherwise");
918 898 assert(dest->is_stack(), "should not call otherwise");
919 899
920 900 if (src->is_single_cpu()) {
921 901 Address dst = frame_map()->address_for_slot(dest->single_stack_ix());
922 902 if (type == T_OBJECT || type == T_ARRAY) {
923 903 __ verify_oop(src->as_register());
924 904 __ movptr (dst, src->as_register());
925 905 } else {
926 906 __ movl (dst, src->as_register());
927 907 }
928 908
929 909 } else if (src->is_double_cpu()) {
930 910 Address dstLO = frame_map()->address_for_slot(dest->double_stack_ix(), lo_word_offset_in_bytes);
931 911 Address dstHI = frame_map()->address_for_slot(dest->double_stack_ix(), hi_word_offset_in_bytes);
932 912 __ movptr (dstLO, src->as_register_lo());
933 913 NOT_LP64(__ movptr (dstHI, src->as_register_hi()));
934 914
935 915 } else if (src->is_single_xmm()) {
936 916 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix());
937 917 __ movflt(dst_addr, src->as_xmm_float_reg());
938 918
939 919 } else if (src->is_double_xmm()) {
940 920 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix());
941 921 __ movdbl(dst_addr, src->as_xmm_double_reg());
942 922
943 923 } else if (src->is_single_fpu()) {
944 924 assert(src->fpu_regnr() == 0, "argument must be on TOS");
945 925 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix());
946 926 if (pop_fpu_stack) __ fstp_s (dst_addr);
947 927 else __ fst_s (dst_addr);
948 928
949 929 } else if (src->is_double_fpu()) {
950 930 assert(src->fpu_regnrLo() == 0, "argument must be on TOS");
951 931 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix());
952 932 if (pop_fpu_stack) __ fstp_d (dst_addr);
953 933 else __ fst_d (dst_addr);
954 934
955 935 } else {
956 936 ShouldNotReachHere();
957 937 }
958 938 }
959 939
960 940
961 941 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool /* unaligned */) {
962 942 LIR_Address* to_addr = dest->as_address_ptr();
963 943 PatchingStub* patch = NULL;
964 944
965 945 if (type == T_ARRAY || type == T_OBJECT) {
966 946 __ verify_oop(src->as_register());
967 947 }
968 948 if (patch_code != lir_patch_none) {
969 949 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
970 950 Address toa = as_Address(to_addr);
971 951 assert(toa.disp() != 0, "must have");
972 952 }
973 953 if (info != NULL) {
974 954 add_debug_info_for_null_check_here(info);
975 955 }
976 956
977 957 switch (type) {
978 958 case T_FLOAT: {
979 959 if (src->is_single_xmm()) {
980 960 __ movflt(as_Address(to_addr), src->as_xmm_float_reg());
981 961 } else {
982 962 assert(src->is_single_fpu(), "must be");
983 963 assert(src->fpu_regnr() == 0, "argument must be on TOS");
984 964 if (pop_fpu_stack) __ fstp_s(as_Address(to_addr));
985 965 else __ fst_s (as_Address(to_addr));
986 966 }
987 967 break;
988 968 }
989 969
990 970 case T_DOUBLE: {
991 971 if (src->is_double_xmm()) {
992 972 __ movdbl(as_Address(to_addr), src->as_xmm_double_reg());
993 973 } else {
994 974 assert(src->is_double_fpu(), "must be");
995 975 assert(src->fpu_regnrLo() == 0, "argument must be on TOS");
996 976 if (pop_fpu_stack) __ fstp_d(as_Address(to_addr));
997 977 else __ fst_d (as_Address(to_addr));
998 978 }
999 979 break;
1000 980 }
1001 981
1002 982 case T_ADDRESS: // fall through
1003 983 case T_ARRAY: // fall through
1004 984 case T_OBJECT: // fall through
1005 985 #ifdef _LP64
1006 986 __ movptr(as_Address(to_addr), src->as_register());
1007 987 break;
1008 988 #endif // _LP64
1009 989 case T_INT:
1010 990 __ movl(as_Address(to_addr), src->as_register());
1011 991 break;
1012 992
1013 993 case T_LONG: {
1014 994 Register from_lo = src->as_register_lo();
1015 995 Register from_hi = src->as_register_hi();
1016 996 #ifdef _LP64
1017 997 __ movptr(as_Address_lo(to_addr), from_lo);
1018 998 #else
1019 999 Register base = to_addr->base()->as_register();
1020 1000 Register index = noreg;
1021 1001 if (to_addr->index()->is_register()) {
1022 1002 index = to_addr->index()->as_register();
1023 1003 }
1024 1004 if (base == from_lo || index == from_lo) {
1025 1005 assert(base != from_hi, "can't be");
1026 1006 assert(index == noreg || (index != base && index != from_hi), "can't handle this");
1027 1007 __ movl(as_Address_hi(to_addr), from_hi);
1028 1008 if (patch != NULL) {
1029 1009 patching_epilog(patch, lir_patch_high, base, info);
1030 1010 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1031 1011 patch_code = lir_patch_low;
1032 1012 }
1033 1013 __ movl(as_Address_lo(to_addr), from_lo);
1034 1014 } else {
1035 1015 assert(index == noreg || (index != base && index != from_lo), "can't handle this");
1036 1016 __ movl(as_Address_lo(to_addr), from_lo);
1037 1017 if (patch != NULL) {
1038 1018 patching_epilog(patch, lir_patch_low, base, info);
1039 1019 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1040 1020 patch_code = lir_patch_high;
1041 1021 }
1042 1022 __ movl(as_Address_hi(to_addr), from_hi);
1043 1023 }
1044 1024 #endif // _LP64
1045 1025 break;
1046 1026 }
1047 1027
1048 1028 case T_BYTE: // fall through
1049 1029 case T_BOOLEAN: {
1050 1030 Register src_reg = src->as_register();
1051 1031 Address dst_addr = as_Address(to_addr);
1052 1032 assert(VM_Version::is_P6() || src_reg->has_byte_register(), "must use byte registers if not P6");
1053 1033 __ movb(dst_addr, src_reg);
1054 1034 break;
1055 1035 }
1056 1036
1057 1037 case T_CHAR: // fall through
1058 1038 case T_SHORT:
1059 1039 __ movw(as_Address(to_addr), src->as_register());
1060 1040 break;
1061 1041
1062 1042 default:
1063 1043 ShouldNotReachHere();
1064 1044 }
1065 1045
1066 1046 if (patch_code != lir_patch_none) {
1067 1047 patching_epilog(patch, patch_code, to_addr->base()->as_register(), info);
1068 1048 }
1069 1049 }
1070 1050
1071 1051
1072 1052 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
1073 1053 assert(src->is_stack(), "should not call otherwise");
1074 1054 assert(dest->is_register(), "should not call otherwise");
1075 1055
1076 1056 if (dest->is_single_cpu()) {
1077 1057 if (type == T_ARRAY || type == T_OBJECT) {
1078 1058 __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1079 1059 __ verify_oop(dest->as_register());
1080 1060 } else {
1081 1061 __ movl(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1082 1062 }
1083 1063
1084 1064 } else if (dest->is_double_cpu()) {
1085 1065 Address src_addr_LO = frame_map()->address_for_slot(src->double_stack_ix(), lo_word_offset_in_bytes);
1086 1066 Address src_addr_HI = frame_map()->address_for_slot(src->double_stack_ix(), hi_word_offset_in_bytes);
1087 1067 __ movptr(dest->as_register_lo(), src_addr_LO);
1088 1068 NOT_LP64(__ movptr(dest->as_register_hi(), src_addr_HI));
1089 1069
1090 1070 } else if (dest->is_single_xmm()) {
1091 1071 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix());
1092 1072 __ movflt(dest->as_xmm_float_reg(), src_addr);
1093 1073
1094 1074 } else if (dest->is_double_xmm()) {
1095 1075 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix());
1096 1076 __ movdbl(dest->as_xmm_double_reg(), src_addr);
1097 1077
1098 1078 } else if (dest->is_single_fpu()) {
1099 1079 assert(dest->fpu_regnr() == 0, "dest must be TOS");
1100 1080 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix());
1101 1081 __ fld_s(src_addr);
1102 1082
1103 1083 } else if (dest->is_double_fpu()) {
1104 1084 assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
1105 1085 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix());
1106 1086 __ fld_d(src_addr);
1107 1087
1108 1088 } else {
1109 1089 ShouldNotReachHere();
1110 1090 }
1111 1091 }
1112 1092
1113 1093
1114 1094 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
1115 1095 if (src->is_single_stack()) {
1116 1096 if (type == T_OBJECT || type == T_ARRAY) {
1117 1097 __ pushptr(frame_map()->address_for_slot(src ->single_stack_ix()));
1118 1098 __ popptr (frame_map()->address_for_slot(dest->single_stack_ix()));
1119 1099 } else {
1120 1100 #ifndef _LP64
1121 1101 __ pushl(frame_map()->address_for_slot(src ->single_stack_ix()));
1122 1102 __ popl (frame_map()->address_for_slot(dest->single_stack_ix()));
1123 1103 #else
1124 1104 //no pushl on 64bits
1125 1105 __ movl(rscratch1, frame_map()->address_for_slot(src ->single_stack_ix()));
1126 1106 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), rscratch1);
1127 1107 #endif
1128 1108 }
1129 1109
1130 1110 } else if (src->is_double_stack()) {
1131 1111 #ifdef _LP64
1132 1112 __ pushptr(frame_map()->address_for_slot(src ->double_stack_ix()));
1133 1113 __ popptr (frame_map()->address_for_slot(dest->double_stack_ix()));
1134 1114 #else
1135 1115 __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 0));
1136 1116 // push and pop the part at src + wordSize, adding wordSize for the previous push
1137 1117 __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 2 * wordSize));
1138 1118 __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 2 * wordSize));
1139 1119 __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 0));
1140 1120 #endif // _LP64
1141 1121
1142 1122 } else {
1143 1123 ShouldNotReachHere();
1144 1124 }
1145 1125 }
1146 1126
1147 1127
1148 1128 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool /* unaligned */) {
1149 1129 assert(src->is_address(), "should not call otherwise");
1150 1130 assert(dest->is_register(), "should not call otherwise");
1151 1131
1152 1132 LIR_Address* addr = src->as_address_ptr();
1153 1133 Address from_addr = as_Address(addr);
1154 1134
1155 1135 switch (type) {
1156 1136 case T_BOOLEAN: // fall through
1157 1137 case T_BYTE: // fall through
1158 1138 case T_CHAR: // fall through
1159 1139 case T_SHORT:
1160 1140 if (!VM_Version::is_P6() && !from_addr.uses(dest->as_register())) {
1161 1141 // on pre P6 processors we may get partial register stalls
1162 1142 // so blow away the value of to_rinfo before loading a
1163 1143 // partial word into it. Do it here so that it precedes
1164 1144 // the potential patch point below.
1165 1145 __ xorptr(dest->as_register(), dest->as_register());
1166 1146 }
1167 1147 break;
1168 1148 }
1169 1149
1170 1150 PatchingStub* patch = NULL;
1171 1151 if (patch_code != lir_patch_none) {
1172 1152 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1173 1153 assert(from_addr.disp() != 0, "must have");
1174 1154 }
1175 1155 if (info != NULL) {
1176 1156 add_debug_info_for_null_check_here(info);
1177 1157 }
1178 1158
1179 1159 switch (type) {
1180 1160 case T_FLOAT: {
1181 1161 if (dest->is_single_xmm()) {
1182 1162 __ movflt(dest->as_xmm_float_reg(), from_addr);
1183 1163 } else {
1184 1164 assert(dest->is_single_fpu(), "must be");
1185 1165 assert(dest->fpu_regnr() == 0, "dest must be TOS");
1186 1166 __ fld_s(from_addr);
1187 1167 }
1188 1168 break;
1189 1169 }
1190 1170
1191 1171 case T_DOUBLE: {
1192 1172 if (dest->is_double_xmm()) {
1193 1173 __ movdbl(dest->as_xmm_double_reg(), from_addr);
1194 1174 } else {
1195 1175 assert(dest->is_double_fpu(), "must be");
1196 1176 assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
1197 1177 __ fld_d(from_addr);
1198 1178 }
1199 1179 break;
1200 1180 }
1201 1181
1202 1182 case T_ADDRESS: // fall through
1203 1183 case T_OBJECT: // fall through
1204 1184 case T_ARRAY: // fall through
1205 1185 #ifdef _LP64
1206 1186 __ movptr(dest->as_register(), from_addr);
1207 1187 break;
1208 1188 #endif // _L64
1209 1189 case T_INT:
1210 1190 // %%% could this be a movl? this is safer but longer instruction
1211 1191 __ movl2ptr(dest->as_register(), from_addr);
1212 1192 break;
1213 1193
1214 1194 case T_LONG: {
1215 1195 Register to_lo = dest->as_register_lo();
1216 1196 Register to_hi = dest->as_register_hi();
1217 1197 #ifdef _LP64
1218 1198 __ movptr(to_lo, as_Address_lo(addr));
1219 1199 #else
1220 1200 Register base = addr->base()->as_register();
1221 1201 Register index = noreg;
1222 1202 if (addr->index()->is_register()) {
1223 1203 index = addr->index()->as_register();
1224 1204 }
1225 1205 if ((base == to_lo && index == to_hi) ||
1226 1206 (base == to_hi && index == to_lo)) {
1227 1207 // addresses with 2 registers are only formed as a result of
1228 1208 // array access so this code will never have to deal with
1229 1209 // patches or null checks.
1230 1210 assert(info == NULL && patch == NULL, "must be");
1231 1211 __ lea(to_hi, as_Address(addr));
1232 1212 __ movl(to_lo, Address(to_hi, 0));
1233 1213 __ movl(to_hi, Address(to_hi, BytesPerWord));
1234 1214 } else if (base == to_lo || index == to_lo) {
1235 1215 assert(base != to_hi, "can't be");
1236 1216 assert(index == noreg || (index != base && index != to_hi), "can't handle this");
1237 1217 __ movl(to_hi, as_Address_hi(addr));
1238 1218 if (patch != NULL) {
1239 1219 patching_epilog(patch, lir_patch_high, base, info);
1240 1220 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1241 1221 patch_code = lir_patch_low;
1242 1222 }
1243 1223 __ movl(to_lo, as_Address_lo(addr));
1244 1224 } else {
1245 1225 assert(index == noreg || (index != base && index != to_lo), "can't handle this");
1246 1226 __ movl(to_lo, as_Address_lo(addr));
1247 1227 if (patch != NULL) {
1248 1228 patching_epilog(patch, lir_patch_low, base, info);
1249 1229 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1250 1230 patch_code = lir_patch_high;
1251 1231 }
1252 1232 __ movl(to_hi, as_Address_hi(addr));
1253 1233 }
1254 1234 #endif // _LP64
1255 1235 break;
1256 1236 }
1257 1237
1258 1238 case T_BOOLEAN: // fall through
1259 1239 case T_BYTE: {
1260 1240 Register dest_reg = dest->as_register();
1261 1241 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6");
1262 1242 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1263 1243 __ movsbl(dest_reg, from_addr);
1264 1244 } else {
1265 1245 __ movb(dest_reg, from_addr);
1266 1246 __ shll(dest_reg, 24);
1267 1247 __ sarl(dest_reg, 24);
1268 1248 }
1269 1249 // These are unsigned so the zero extension on 64bit is just what we need
1270 1250 break;
1271 1251 }
1272 1252
1273 1253 case T_CHAR: {
1274 1254 Register dest_reg = dest->as_register();
1275 1255 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6");
1276 1256 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1277 1257 __ movzwl(dest_reg, from_addr);
1278 1258 } else {
1279 1259 __ movw(dest_reg, from_addr);
1280 1260 }
1281 1261 // This is unsigned so the zero extension on 64bit is just what we need
1282 1262 // __ movl2ptr(dest_reg, dest_reg);
1283 1263 break;
1284 1264 }
1285 1265
1286 1266 case T_SHORT: {
1287 1267 Register dest_reg = dest->as_register();
1288 1268 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1289 1269 __ movswl(dest_reg, from_addr);
1290 1270 } else {
1291 1271 __ movw(dest_reg, from_addr);
1292 1272 __ shll(dest_reg, 16);
1293 1273 __ sarl(dest_reg, 16);
1294 1274 }
1295 1275 // Might not be needed in 64bit but certainly doesn't hurt (except for code size)
1296 1276 __ movl2ptr(dest_reg, dest_reg);
1297 1277 break;
1298 1278 }
1299 1279
1300 1280 default:
1301 1281 ShouldNotReachHere();
1302 1282 }
1303 1283
1304 1284 if (patch != NULL) {
1305 1285 patching_epilog(patch, patch_code, addr->base()->as_register(), info);
1306 1286 }
1307 1287
1308 1288 if (type == T_ARRAY || type == T_OBJECT) {
1309 1289 __ verify_oop(dest->as_register());
1310 1290 }
1311 1291 }
1312 1292
1313 1293
1314 1294 void LIR_Assembler::prefetchr(LIR_Opr src) {
1315 1295 LIR_Address* addr = src->as_address_ptr();
1316 1296 Address from_addr = as_Address(addr);
1317 1297
1318 1298 if (VM_Version::supports_sse()) {
1319 1299 switch (ReadPrefetchInstr) {
1320 1300 case 0:
1321 1301 __ prefetchnta(from_addr); break;
1322 1302 case 1:
1323 1303 __ prefetcht0(from_addr); break;
1324 1304 case 2:
1325 1305 __ prefetcht2(from_addr); break;
1326 1306 default:
1327 1307 ShouldNotReachHere(); break;
1328 1308 }
1329 1309 } else if (VM_Version::supports_3dnow()) {
1330 1310 __ prefetchr(from_addr);
1331 1311 }
1332 1312 }
1333 1313
1334 1314
1335 1315 void LIR_Assembler::prefetchw(LIR_Opr src) {
1336 1316 LIR_Address* addr = src->as_address_ptr();
1337 1317 Address from_addr = as_Address(addr);
1338 1318
1339 1319 if (VM_Version::supports_sse()) {
1340 1320 switch (AllocatePrefetchInstr) {
1341 1321 case 0:
1342 1322 __ prefetchnta(from_addr); break;
1343 1323 case 1:
1344 1324 __ prefetcht0(from_addr); break;
1345 1325 case 2:
1346 1326 __ prefetcht2(from_addr); break;
1347 1327 case 3:
1348 1328 __ prefetchw(from_addr); break;
1349 1329 default:
1350 1330 ShouldNotReachHere(); break;
1351 1331 }
1352 1332 } else if (VM_Version::supports_3dnow()) {
1353 1333 __ prefetchw(from_addr);
1354 1334 }
1355 1335 }
1356 1336
1357 1337
1358 1338 NEEDS_CLEANUP; // This could be static?
1359 1339 Address::ScaleFactor LIR_Assembler::array_element_size(BasicType type) const {
1360 1340 int elem_size = type2aelembytes(type);
1361 1341 switch (elem_size) {
1362 1342 case 1: return Address::times_1;
1363 1343 case 2: return Address::times_2;
1364 1344 case 4: return Address::times_4;
1365 1345 case 8: return Address::times_8;
1366 1346 }
1367 1347 ShouldNotReachHere();
1368 1348 return Address::no_scale;
1369 1349 }
1370 1350
1371 1351
1372 1352 void LIR_Assembler::emit_op3(LIR_Op3* op) {
1373 1353 switch (op->code()) {
1374 1354 case lir_idiv:
1375 1355 case lir_irem:
1376 1356 arithmetic_idiv(op->code(),
1377 1357 op->in_opr1(),
1378 1358 op->in_opr2(),
1379 1359 op->in_opr3(),
1380 1360 op->result_opr(),
1381 1361 op->info());
1382 1362 break;
1383 1363 default: ShouldNotReachHere(); break;
1384 1364 }
1385 1365 }
1386 1366
1387 1367 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
1388 1368 #ifdef ASSERT
1389 1369 assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label");
1390 1370 if (op->block() != NULL) _branch_target_blocks.append(op->block());
1391 1371 if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock());
1392 1372 #endif
1393 1373
1394 1374 if (op->cond() == lir_cond_always) {
1395 1375 if (op->info() != NULL) add_debug_info_for_branch(op->info());
1396 1376 __ jmp (*(op->label()));
1397 1377 } else {
1398 1378 Assembler::Condition acond = Assembler::zero;
1399 1379 if (op->code() == lir_cond_float_branch) {
1400 1380 assert(op->ublock() != NULL, "must have unordered successor");
1401 1381 __ jcc(Assembler::parity, *(op->ublock()->label()));
1402 1382 switch(op->cond()) {
1403 1383 case lir_cond_equal: acond = Assembler::equal; break;
1404 1384 case lir_cond_notEqual: acond = Assembler::notEqual; break;
1405 1385 case lir_cond_less: acond = Assembler::below; break;
1406 1386 case lir_cond_lessEqual: acond = Assembler::belowEqual; break;
1407 1387 case lir_cond_greaterEqual: acond = Assembler::aboveEqual; break;
1408 1388 case lir_cond_greater: acond = Assembler::above; break;
1409 1389 default: ShouldNotReachHere();
1410 1390 }
1411 1391 } else {
1412 1392 switch (op->cond()) {
1413 1393 case lir_cond_equal: acond = Assembler::equal; break;
1414 1394 case lir_cond_notEqual: acond = Assembler::notEqual; break;
1415 1395 case lir_cond_less: acond = Assembler::less; break;
1416 1396 case lir_cond_lessEqual: acond = Assembler::lessEqual; break;
1417 1397 case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break;
1418 1398 case lir_cond_greater: acond = Assembler::greater; break;
1419 1399 case lir_cond_belowEqual: acond = Assembler::belowEqual; break;
1420 1400 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; break;
1421 1401 default: ShouldNotReachHere();
1422 1402 }
1423 1403 }
1424 1404 __ jcc(acond,*(op->label()));
1425 1405 }
1426 1406 }
1427 1407
1428 1408 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
1429 1409 LIR_Opr src = op->in_opr();
1430 1410 LIR_Opr dest = op->result_opr();
1431 1411
1432 1412 switch (op->bytecode()) {
1433 1413 case Bytecodes::_i2l:
1434 1414 #ifdef _LP64
1435 1415 __ movl2ptr(dest->as_register_lo(), src->as_register());
1436 1416 #else
1437 1417 move_regs(src->as_register(), dest->as_register_lo());
1438 1418 move_regs(src->as_register(), dest->as_register_hi());
1439 1419 __ sarl(dest->as_register_hi(), 31);
1440 1420 #endif // LP64
1441 1421 break;
1442 1422
1443 1423 case Bytecodes::_l2i:
1444 1424 move_regs(src->as_register_lo(), dest->as_register());
1445 1425 break;
1446 1426
1447 1427 case Bytecodes::_i2b:
1448 1428 move_regs(src->as_register(), dest->as_register());
1449 1429 __ sign_extend_byte(dest->as_register());
1450 1430 break;
1451 1431
1452 1432 case Bytecodes::_i2c:
1453 1433 move_regs(src->as_register(), dest->as_register());
1454 1434 __ andl(dest->as_register(), 0xFFFF);
1455 1435 break;
1456 1436
1457 1437 case Bytecodes::_i2s:
1458 1438 move_regs(src->as_register(), dest->as_register());
1459 1439 __ sign_extend_short(dest->as_register());
1460 1440 break;
1461 1441
1462 1442
1463 1443 case Bytecodes::_f2d:
1464 1444 case Bytecodes::_d2f:
1465 1445 if (dest->is_single_xmm()) {
1466 1446 __ cvtsd2ss(dest->as_xmm_float_reg(), src->as_xmm_double_reg());
1467 1447 } else if (dest->is_double_xmm()) {
1468 1448 __ cvtss2sd(dest->as_xmm_double_reg(), src->as_xmm_float_reg());
1469 1449 } else {
1470 1450 assert(src->fpu() == dest->fpu(), "register must be equal");
1471 1451 // do nothing (float result is rounded later through spilling)
1472 1452 }
1473 1453 break;
1474 1454
1475 1455 case Bytecodes::_i2f:
1476 1456 case Bytecodes::_i2d:
1477 1457 if (dest->is_single_xmm()) {
1478 1458 __ cvtsi2ssl(dest->as_xmm_float_reg(), src->as_register());
1479 1459 } else if (dest->is_double_xmm()) {
1480 1460 __ cvtsi2sdl(dest->as_xmm_double_reg(), src->as_register());
1481 1461 } else {
1482 1462 assert(dest->fpu() == 0, "result must be on TOS");
1483 1463 __ movl(Address(rsp, 0), src->as_register());
1484 1464 __ fild_s(Address(rsp, 0));
1485 1465 }
1486 1466 break;
1487 1467
1488 1468 case Bytecodes::_f2i:
1489 1469 case Bytecodes::_d2i:
1490 1470 if (src->is_single_xmm()) {
1491 1471 __ cvttss2sil(dest->as_register(), src->as_xmm_float_reg());
1492 1472 } else if (src->is_double_xmm()) {
1493 1473 __ cvttsd2sil(dest->as_register(), src->as_xmm_double_reg());
1494 1474 } else {
1495 1475 assert(src->fpu() == 0, "input must be on TOS");
1496 1476 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc()));
1497 1477 __ fist_s(Address(rsp, 0));
1498 1478 __ movl(dest->as_register(), Address(rsp, 0));
1499 1479 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
1500 1480 }
1501 1481
1502 1482 // IA32 conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub
1503 1483 assert(op->stub() != NULL, "stub required");
1504 1484 __ cmpl(dest->as_register(), 0x80000000);
1505 1485 __ jcc(Assembler::equal, *op->stub()->entry());
1506 1486 __ bind(*op->stub()->continuation());
1507 1487 break;
1508 1488
1509 1489 case Bytecodes::_l2f:
1510 1490 case Bytecodes::_l2d:
1511 1491 assert(!dest->is_xmm_register(), "result in xmm register not supported (no SSE instruction present)");
1512 1492 assert(dest->fpu() == 0, "result must be on TOS");
1513 1493
1514 1494 __ movptr(Address(rsp, 0), src->as_register_lo());
1515 1495 NOT_LP64(__ movl(Address(rsp, BytesPerWord), src->as_register_hi()));
1516 1496 __ fild_d(Address(rsp, 0));
1517 1497 // float result is rounded later through spilling
1518 1498 break;
1519 1499
1520 1500 case Bytecodes::_f2l:
1521 1501 case Bytecodes::_d2l:
1522 1502 assert(!src->is_xmm_register(), "input in xmm register not supported (no SSE instruction present)");
1523 1503 assert(src->fpu() == 0, "input must be on TOS");
1524 1504 assert(dest == FrameMap::long0_opr, "runtime stub places result in these registers");
1525 1505
1526 1506 // instruction sequence too long to inline it here
1527 1507 {
1528 1508 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::fpu2long_stub_id)));
1529 1509 }
1530 1510 break;
1531 1511
1532 1512 default: ShouldNotReachHere();
1533 1513 }
1534 1514 }
1535 1515
1536 1516 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
1537 1517 if (op->init_check()) {
1538 1518 __ cmpl(Address(op->klass()->as_register(),
1539 1519 instanceKlass::init_state_offset_in_bytes() + sizeof(oopDesc)),
1540 1520 instanceKlass::fully_initialized);
1541 1521 add_debug_info_for_null_check_here(op->stub()->info());
1542 1522 __ jcc(Assembler::notEqual, *op->stub()->entry());
1543 1523 }
1544 1524 __ allocate_object(op->obj()->as_register(),
1545 1525 op->tmp1()->as_register(),
1546 1526 op->tmp2()->as_register(),
1547 1527 op->header_size(),
1548 1528 op->object_size(),
1549 1529 op->klass()->as_register(),
1550 1530 *op->stub()->entry());
1551 1531 __ bind(*op->stub()->continuation());
1552 1532 }
1553 1533
1554 1534 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
1555 1535 if (UseSlowPath ||
1556 1536 (!UseFastNewObjectArray && (op->type() == T_OBJECT || op->type() == T_ARRAY)) ||
1557 1537 (!UseFastNewTypeArray && (op->type() != T_OBJECT && op->type() != T_ARRAY))) {
1558 1538 __ jmp(*op->stub()->entry());
1559 1539 } else {
1560 1540 Register len = op->len()->as_register();
1561 1541 Register tmp1 = op->tmp1()->as_register();
1562 1542 Register tmp2 = op->tmp2()->as_register();
1563 1543 Register tmp3 = op->tmp3()->as_register();
1564 1544 if (len == tmp1) {
1565 1545 tmp1 = tmp3;
1566 1546 } else if (len == tmp2) {
1567 1547 tmp2 = tmp3;
1568 1548 } else if (len == tmp3) {
1569 1549 // everything is ok
1570 1550 } else {
1571 1551 __ mov(tmp3, len);
1572 1552 }
1573 1553 __ allocate_array(op->obj()->as_register(),
1574 1554 len,
1575 1555 tmp1,
1576 1556 tmp2,
1577 1557 arrayOopDesc::header_size(op->type()),
1578 1558 array_element_size(op->type()),
1579 1559 op->klass()->as_register(),
1580 1560 *op->stub()->entry());
1581 1561 }
1582 1562 __ bind(*op->stub()->continuation());
1583 1563 }
1584 1564
1585 1565
1586 1566
1587 1567 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
1588 1568 LIR_Code code = op->code();
1589 1569 if (code == lir_store_check) {
1590 1570 Register value = op->object()->as_register();
1591 1571 Register array = op->array()->as_register();
1592 1572 Register k_RInfo = op->tmp1()->as_register();
1593 1573 Register klass_RInfo = op->tmp2()->as_register();
1594 1574 Register Rtmp1 = op->tmp3()->as_register();
1595 1575
1596 1576 CodeStub* stub = op->stub();
1597 1577 Label done;
1598 1578 __ cmpptr(value, (int32_t)NULL_WORD);
1599 1579 __ jcc(Assembler::equal, done);
1600 1580 add_debug_info_for_null_check_here(op->info_for_exception());
1601 1581 __ movptr(k_RInfo, Address(array, oopDesc::klass_offset_in_bytes()));
1602 1582 __ movptr(klass_RInfo, Address(value, oopDesc::klass_offset_in_bytes()));
1603 1583
1604 1584 // get instance klass
1605 1585 __ movptr(k_RInfo, Address(k_RInfo, objArrayKlass::element_klass_offset_in_bytes() + sizeof(oopDesc)));
1606 1586 // perform the fast part of the checking logic
1607 1587 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, &done, stub->entry(), NULL);
1608 1588 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1609 1589 __ push(klass_RInfo);
1610 1590 __ push(k_RInfo);
1611 1591 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1612 1592 __ pop(klass_RInfo);
1613 1593 __ pop(k_RInfo);
1614 1594 // result is a boolean
1615 1595 __ cmpl(k_RInfo, 0);
1616 1596 __ jcc(Assembler::equal, *stub->entry());
1617 1597 __ bind(done);
1618 1598 } else if (op->code() == lir_checkcast) {
1619 1599 // we always need a stub for the failure case.
1620 1600 CodeStub* stub = op->stub();
1621 1601 Register obj = op->object()->as_register();
1622 1602 Register k_RInfo = op->tmp1()->as_register();
1623 1603 Register klass_RInfo = op->tmp2()->as_register();
1624 1604 Register dst = op->result_opr()->as_register();
1625 1605 ciKlass* k = op->klass();
1626 1606 Register Rtmp1 = noreg;
1627 1607
1628 1608 Label done;
1629 1609 if (obj == k_RInfo) {
1630 1610 k_RInfo = dst;
1631 1611 } else if (obj == klass_RInfo) {
1632 1612 klass_RInfo = dst;
1633 1613 }
1634 1614 if (k->is_loaded()) {
1635 1615 select_different_registers(obj, dst, k_RInfo, klass_RInfo);
1636 1616 } else {
1637 1617 Rtmp1 = op->tmp3()->as_register();
1638 1618 select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1);
1639 1619 }
1640 1620
1641 1621 assert_different_registers(obj, k_RInfo, klass_RInfo);
1642 1622 if (!k->is_loaded()) {
1643 1623 jobject2reg_with_patching(k_RInfo, op->info_for_patch());
1644 1624 } else {
1645 1625 #ifdef _LP64
1646 1626 __ movoop(k_RInfo, k->constant_encoding());
1647 1627 #else
1648 1628 k_RInfo = noreg;
1649 1629 #endif // _LP64
1650 1630 }
1651 1631 assert(obj != k_RInfo, "must be different");
1652 1632 __ cmpptr(obj, (int32_t)NULL_WORD);
1653 1633 if (op->profiled_method() != NULL) {
1654 1634 ciMethod* method = op->profiled_method();
1655 1635 int bci = op->profiled_bci();
1656 1636
1657 1637 Label profile_done;
1658 1638 __ jcc(Assembler::notEqual, profile_done);
1659 1639 // Object is null; update methodDataOop
1660 1640 ciMethodData* md = method->method_data();
1661 1641 if (md == NULL) {
1662 1642 bailout("out of memory building methodDataOop");
1663 1643 return;
1664 1644 }
1665 1645 ciProfileData* data = md->bci_to_data(bci);
1666 1646 assert(data != NULL, "need data for checkcast");
1667 1647 assert(data->is_BitData(), "need BitData for checkcast");
1668 1648 Register mdo = klass_RInfo;
1669 1649 __ movoop(mdo, md->constant_encoding());
1670 1650 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::header_offset()));
1671 1651 int header_bits = DataLayout::flag_mask_to_header_mask(BitData::null_seen_byte_constant());
1672 1652 __ orl(data_addr, header_bits);
1673 1653 __ jmp(done);
1674 1654 __ bind(profile_done);
1675 1655 } else {
1676 1656 __ jcc(Assembler::equal, done);
1677 1657 }
1678 1658 __ verify_oop(obj);
1679 1659
1680 1660 if (op->fast_check()) {
1681 1661 // get object classo
1682 1662 // not a safepoint as obj null check happens earlier
1683 1663 if (k->is_loaded()) {
1684 1664 #ifdef _LP64
1685 1665 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
1686 1666 #else
1687 1667 __ cmpoop(Address(obj, oopDesc::klass_offset_in_bytes()), k->constant_encoding());
1688 1668 #endif // _LP64
1689 1669 } else {
1690 1670 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
1691 1671
1692 1672 }
1693 1673 __ jcc(Assembler::notEqual, *stub->entry());
1694 1674 __ bind(done);
1695 1675 } else {
1696 1676 // get object class
1697 1677 // not a safepoint as obj null check happens earlier
1698 1678 __ movptr(klass_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
1699 1679 if (k->is_loaded()) {
1700 1680 // See if we get an immediate positive hit
1701 1681 #ifdef _LP64
1702 1682 __ cmpptr(k_RInfo, Address(klass_RInfo, k->super_check_offset()));
1703 1683 #else
1704 1684 __ cmpoop(Address(klass_RInfo, k->super_check_offset()), k->constant_encoding());
1705 1685 #endif // _LP64
1706 1686 if (sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes() != k->super_check_offset()) {
1707 1687 __ jcc(Assembler::notEqual, *stub->entry());
1708 1688 } else {
1709 1689 // See if we get an immediate positive hit
1710 1690 __ jcc(Assembler::equal, done);
1711 1691 // check for self
1712 1692 #ifdef _LP64
1713 1693 __ cmpptr(klass_RInfo, k_RInfo);
1714 1694 #else
1715 1695 __ cmpoop(klass_RInfo, k->constant_encoding());
1716 1696 #endif // _LP64
1717 1697 __ jcc(Assembler::equal, done);
1718 1698
1719 1699 __ push(klass_RInfo);
1720 1700 #ifdef _LP64
1721 1701 __ push(k_RInfo);
1722 1702 #else
1723 1703 __ pushoop(k->constant_encoding());
1724 1704 #endif // _LP64
1725 1705 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1726 1706 __ pop(klass_RInfo);
1727 1707 __ pop(klass_RInfo);
1728 1708 // result is a boolean
1729 1709 __ cmpl(klass_RInfo, 0);
1730 1710 __ jcc(Assembler::equal, *stub->entry());
1731 1711 }
1732 1712 __ bind(done);
1733 1713 } else {
1734 1714 // perform the fast part of the checking logic
1735 1715 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, &done, stub->entry(), NULL);
1736 1716 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1737 1717 __ push(klass_RInfo);
1738 1718 __ push(k_RInfo);
1739 1719 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1740 1720 __ pop(klass_RInfo);
1741 1721 __ pop(k_RInfo);
1742 1722 // result is a boolean
1743 1723 __ cmpl(k_RInfo, 0);
1744 1724 __ jcc(Assembler::equal, *stub->entry());
1745 1725 __ bind(done);
1746 1726 }
1747 1727
1748 1728 }
1749 1729 if (dst != obj) {
1750 1730 __ mov(dst, obj);
1751 1731 }
1752 1732 } else if (code == lir_instanceof) {
1753 1733 Register obj = op->object()->as_register();
1754 1734 Register k_RInfo = op->tmp1()->as_register();
1755 1735 Register klass_RInfo = op->tmp2()->as_register();
1756 1736 Register dst = op->result_opr()->as_register();
1757 1737 ciKlass* k = op->klass();
1758 1738
1759 1739 Label done;
1760 1740 Label zero;
1761 1741 Label one;
1762 1742 if (obj == k_RInfo) {
1763 1743 k_RInfo = klass_RInfo;
1764 1744 klass_RInfo = obj;
1765 1745 }
1766 1746 // patching may screw with our temporaries on sparc,
1767 1747 // so let's do it before loading the class
1768 1748 if (!k->is_loaded()) {
1769 1749 jobject2reg_with_patching(k_RInfo, op->info_for_patch());
1770 1750 } else {
1771 1751 LP64_ONLY(__ movoop(k_RInfo, k->constant_encoding()));
1772 1752 }
1773 1753 assert(obj != k_RInfo, "must be different");
1774 1754
1775 1755 __ verify_oop(obj);
1776 1756 if (op->fast_check()) {
1777 1757 __ cmpptr(obj, (int32_t)NULL_WORD);
1778 1758 __ jcc(Assembler::equal, zero);
1779 1759 // get object class
1780 1760 // not a safepoint as obj null check happens earlier
1781 1761 if (LP64_ONLY(false &&) k->is_loaded()) {
1782 1762 NOT_LP64(__ cmpoop(Address(obj, oopDesc::klass_offset_in_bytes()), k->constant_encoding()));
1783 1763 k_RInfo = noreg;
1784 1764 } else {
1785 1765 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
1786 1766
1787 1767 }
1788 1768 __ jcc(Assembler::equal, one);
1789 1769 } else {
1790 1770 // get object class
1791 1771 // not a safepoint as obj null check happens earlier
1792 1772 __ cmpptr(obj, (int32_t)NULL_WORD);
1793 1773 __ jcc(Assembler::equal, zero);
1794 1774 __ movptr(klass_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
1795 1775
1796 1776 #ifndef _LP64
1797 1777 if (k->is_loaded()) {
1798 1778 // See if we get an immediate positive hit
1799 1779 __ cmpoop(Address(klass_RInfo, k->super_check_offset()), k->constant_encoding());
1800 1780 __ jcc(Assembler::equal, one);
1801 1781 if (sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes() == k->super_check_offset()) {
1802 1782 // check for self
1803 1783 __ cmpoop(klass_RInfo, k->constant_encoding());
1804 1784 __ jcc(Assembler::equal, one);
1805 1785 __ push(klass_RInfo);
1806 1786 __ pushoop(k->constant_encoding());
1807 1787 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1808 1788 __ pop(klass_RInfo);
1809 1789 __ pop(dst);
1810 1790 __ jmp(done);
1811 1791 }
1812 1792 }
1813 1793 else // next block is unconditional if LP64:
1814 1794 #endif // LP64
1815 1795 {
1816 1796 assert(dst != klass_RInfo && dst != k_RInfo, "need 3 registers");
1817 1797
1818 1798 // perform the fast part of the checking logic
1819 1799 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, dst, &one, &zero, NULL);
1820 1800 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1821 1801 __ push(klass_RInfo);
1822 1802 __ push(k_RInfo);
1823 1803 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1824 1804 __ pop(klass_RInfo);
1825 1805 __ pop(dst);
1826 1806 __ jmp(done);
1827 1807 }
1828 1808 }
1829 1809 __ bind(zero);
1830 1810 __ xorptr(dst, dst);
1831 1811 __ jmp(done);
1832 1812 __ bind(one);
1833 1813 __ movptr(dst, 1);
1834 1814 __ bind(done);
1835 1815 } else {
1836 1816 ShouldNotReachHere();
1837 1817 }
1838 1818
1839 1819 }
1840 1820
1841 1821
1842 1822 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
1843 1823 if (LP64_ONLY(false &&) op->code() == lir_cas_long && VM_Version::supports_cx8()) {
1844 1824 assert(op->cmp_value()->as_register_lo() == rax, "wrong register");
1845 1825 assert(op->cmp_value()->as_register_hi() == rdx, "wrong register");
1846 1826 assert(op->new_value()->as_register_lo() == rbx, "wrong register");
1847 1827 assert(op->new_value()->as_register_hi() == rcx, "wrong register");
1848 1828 Register addr = op->addr()->as_register();
1849 1829 if (os::is_MP()) {
1850 1830 __ lock();
1851 1831 }
1852 1832 NOT_LP64(__ cmpxchg8(Address(addr, 0)));
1853 1833
1854 1834 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj ) {
1855 1835 NOT_LP64(assert(op->addr()->is_single_cpu(), "must be single");)
1856 1836 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo());
1857 1837 Register newval = op->new_value()->as_register();
1858 1838 Register cmpval = op->cmp_value()->as_register();
1859 1839 assert(cmpval == rax, "wrong register");
1860 1840 assert(newval != NULL, "new val must be register");
1861 1841 assert(cmpval != newval, "cmp and new values must be in different registers");
1862 1842 assert(cmpval != addr, "cmp and addr must be in different registers");
1863 1843 assert(newval != addr, "new value and addr must be in different registers");
1864 1844 if (os::is_MP()) {
1865 1845 __ lock();
1866 1846 }
1867 1847 if ( op->code() == lir_cas_obj) {
1868 1848 __ cmpxchgptr(newval, Address(addr, 0));
1869 1849 } else if (op->code() == lir_cas_int) {
1870 1850 __ cmpxchgl(newval, Address(addr, 0));
1871 1851 } else {
1872 1852 LP64_ONLY(__ cmpxchgq(newval, Address(addr, 0)));
1873 1853 }
1874 1854 #ifdef _LP64
1875 1855 } else if (op->code() == lir_cas_long) {
1876 1856 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo());
1877 1857 Register newval = op->new_value()->as_register_lo();
1878 1858 Register cmpval = op->cmp_value()->as_register_lo();
1879 1859 assert(cmpval == rax, "wrong register");
1880 1860 assert(newval != NULL, "new val must be register");
1881 1861 assert(cmpval != newval, "cmp and new values must be in different registers");
1882 1862 assert(cmpval != addr, "cmp and addr must be in different registers");
1883 1863 assert(newval != addr, "new value and addr must be in different registers");
1884 1864 if (os::is_MP()) {
1885 1865 __ lock();
1886 1866 }
1887 1867 __ cmpxchgq(newval, Address(addr, 0));
1888 1868 #endif // _LP64
1889 1869 } else {
1890 1870 Unimplemented();
1891 1871 }
1892 1872 }
1893 1873
1894 1874
1895 1875 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result) {
1896 1876 Assembler::Condition acond, ncond;
1897 1877 switch (condition) {
1898 1878 case lir_cond_equal: acond = Assembler::equal; ncond = Assembler::notEqual; break;
1899 1879 case lir_cond_notEqual: acond = Assembler::notEqual; ncond = Assembler::equal; break;
1900 1880 case lir_cond_less: acond = Assembler::less; ncond = Assembler::greaterEqual; break;
1901 1881 case lir_cond_lessEqual: acond = Assembler::lessEqual; ncond = Assembler::greater; break;
1902 1882 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; ncond = Assembler::less; break;
1903 1883 case lir_cond_greater: acond = Assembler::greater; ncond = Assembler::lessEqual; break;
1904 1884 case lir_cond_belowEqual: acond = Assembler::belowEqual; ncond = Assembler::above; break;
1905 1885 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; ncond = Assembler::below; break;
1906 1886 default: ShouldNotReachHere();
1907 1887 }
1908 1888
1909 1889 if (opr1->is_cpu_register()) {
1910 1890 reg2reg(opr1, result);
1911 1891 } else if (opr1->is_stack()) {
1912 1892 stack2reg(opr1, result, result->type());
1913 1893 } else if (opr1->is_constant()) {
1914 1894 const2reg(opr1, result, lir_patch_none, NULL);
1915 1895 } else {
1916 1896 ShouldNotReachHere();
1917 1897 }
1918 1898
1919 1899 if (VM_Version::supports_cmov() && !opr2->is_constant()) {
1920 1900 // optimized version that does not require a branch
1921 1901 if (opr2->is_single_cpu()) {
1922 1902 assert(opr2->cpu_regnr() != result->cpu_regnr(), "opr2 already overwritten by previous move");
1923 1903 __ cmov(ncond, result->as_register(), opr2->as_register());
1924 1904 } else if (opr2->is_double_cpu()) {
1925 1905 assert(opr2->cpu_regnrLo() != result->cpu_regnrLo() && opr2->cpu_regnrLo() != result->cpu_regnrHi(), "opr2 already overwritten by previous move");
1926 1906 assert(opr2->cpu_regnrHi() != result->cpu_regnrLo() && opr2->cpu_regnrHi() != result->cpu_regnrHi(), "opr2 already overwritten by previous move");
1927 1907 __ cmovptr(ncond, result->as_register_lo(), opr2->as_register_lo());
1928 1908 NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), opr2->as_register_hi());)
1929 1909 } else if (opr2->is_single_stack()) {
1930 1910 __ cmovl(ncond, result->as_register(), frame_map()->address_for_slot(opr2->single_stack_ix()));
1931 1911 } else if (opr2->is_double_stack()) {
1932 1912 __ cmovptr(ncond, result->as_register_lo(), frame_map()->address_for_slot(opr2->double_stack_ix(), lo_word_offset_in_bytes));
1933 1913 NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), frame_map()->address_for_slot(opr2->double_stack_ix(), hi_word_offset_in_bytes));)
1934 1914 } else {
1935 1915 ShouldNotReachHere();
1936 1916 }
1937 1917
1938 1918 } else {
1939 1919 Label skip;
1940 1920 __ jcc (acond, skip);
1941 1921 if (opr2->is_cpu_register()) {
1942 1922 reg2reg(opr2, result);
1943 1923 } else if (opr2->is_stack()) {
1944 1924 stack2reg(opr2, result, result->type());
1945 1925 } else if (opr2->is_constant()) {
1946 1926 const2reg(opr2, result, lir_patch_none, NULL);
1947 1927 } else {
1948 1928 ShouldNotReachHere();
1949 1929 }
1950 1930 __ bind(skip);
1951 1931 }
1952 1932 }
1953 1933
1954 1934
1955 1935 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) {
1956 1936 assert(info == NULL, "should never be used, idiv/irem and ldiv/lrem not handled by this method");
1957 1937
1958 1938 if (left->is_single_cpu()) {
1959 1939 assert(left == dest, "left and dest must be equal");
1960 1940 Register lreg = left->as_register();
1961 1941
1962 1942 if (right->is_single_cpu()) {
1963 1943 // cpu register - cpu register
1964 1944 Register rreg = right->as_register();
1965 1945 switch (code) {
1966 1946 case lir_add: __ addl (lreg, rreg); break;
1967 1947 case lir_sub: __ subl (lreg, rreg); break;
1968 1948 case lir_mul: __ imull(lreg, rreg); break;
1969 1949 default: ShouldNotReachHere();
1970 1950 }
1971 1951
1972 1952 } else if (right->is_stack()) {
1973 1953 // cpu register - stack
1974 1954 Address raddr = frame_map()->address_for_slot(right->single_stack_ix());
1975 1955 switch (code) {
1976 1956 case lir_add: __ addl(lreg, raddr); break;
1977 1957 case lir_sub: __ subl(lreg, raddr); break;
1978 1958 default: ShouldNotReachHere();
1979 1959 }
1980 1960
1981 1961 } else if (right->is_constant()) {
1982 1962 // cpu register - constant
1983 1963 jint c = right->as_constant_ptr()->as_jint();
1984 1964 switch (code) {
1985 1965 case lir_add: {
1986 1966 __ increment(lreg, c);
1987 1967 break;
1988 1968 }
1989 1969 case lir_sub: {
1990 1970 __ decrement(lreg, c);
1991 1971 break;
1992 1972 }
1993 1973 default: ShouldNotReachHere();
1994 1974 }
1995 1975
1996 1976 } else {
1997 1977 ShouldNotReachHere();
1998 1978 }
1999 1979
2000 1980 } else if (left->is_double_cpu()) {
2001 1981 assert(left == dest, "left and dest must be equal");
2002 1982 Register lreg_lo = left->as_register_lo();
2003 1983 Register lreg_hi = left->as_register_hi();
2004 1984
2005 1985 if (right->is_double_cpu()) {
2006 1986 // cpu register - cpu register
2007 1987 Register rreg_lo = right->as_register_lo();
2008 1988 Register rreg_hi = right->as_register_hi();
2009 1989 NOT_LP64(assert_different_registers(lreg_lo, lreg_hi, rreg_lo, rreg_hi));
2010 1990 LP64_ONLY(assert_different_registers(lreg_lo, rreg_lo));
2011 1991 switch (code) {
2012 1992 case lir_add:
2013 1993 __ addptr(lreg_lo, rreg_lo);
2014 1994 NOT_LP64(__ adcl(lreg_hi, rreg_hi));
2015 1995 break;
2016 1996 case lir_sub:
2017 1997 __ subptr(lreg_lo, rreg_lo);
2018 1998 NOT_LP64(__ sbbl(lreg_hi, rreg_hi));
2019 1999 break;
2020 2000 case lir_mul:
2021 2001 #ifdef _LP64
2022 2002 __ imulq(lreg_lo, rreg_lo);
2023 2003 #else
2024 2004 assert(lreg_lo == rax && lreg_hi == rdx, "must be");
2025 2005 __ imull(lreg_hi, rreg_lo);
2026 2006 __ imull(rreg_hi, lreg_lo);
2027 2007 __ addl (rreg_hi, lreg_hi);
2028 2008 __ mull (rreg_lo);
2029 2009 __ addl (lreg_hi, rreg_hi);
2030 2010 #endif // _LP64
2031 2011 break;
2032 2012 default:
2033 2013 ShouldNotReachHere();
2034 2014 }
2035 2015
2036 2016 } else if (right->is_constant()) {
2037 2017 // cpu register - constant
2038 2018 #ifdef _LP64
2039 2019 jlong c = right->as_constant_ptr()->as_jlong_bits();
2040 2020 __ movptr(r10, (intptr_t) c);
2041 2021 switch (code) {
2042 2022 case lir_add:
2043 2023 __ addptr(lreg_lo, r10);
2044 2024 break;
2045 2025 case lir_sub:
2046 2026 __ subptr(lreg_lo, r10);
2047 2027 break;
2048 2028 default:
2049 2029 ShouldNotReachHere();
2050 2030 }
2051 2031 #else
2052 2032 jint c_lo = right->as_constant_ptr()->as_jint_lo();
2053 2033 jint c_hi = right->as_constant_ptr()->as_jint_hi();
2054 2034 switch (code) {
2055 2035 case lir_add:
2056 2036 __ addptr(lreg_lo, c_lo);
2057 2037 __ adcl(lreg_hi, c_hi);
2058 2038 break;
2059 2039 case lir_sub:
2060 2040 __ subptr(lreg_lo, c_lo);
2061 2041 __ sbbl(lreg_hi, c_hi);
2062 2042 break;
2063 2043 default:
2064 2044 ShouldNotReachHere();
2065 2045 }
2066 2046 #endif // _LP64
2067 2047
2068 2048 } else {
2069 2049 ShouldNotReachHere();
2070 2050 }
2071 2051
2072 2052 } else if (left->is_single_xmm()) {
2073 2053 assert(left == dest, "left and dest must be equal");
2074 2054 XMMRegister lreg = left->as_xmm_float_reg();
2075 2055
2076 2056 if (right->is_single_xmm()) {
2077 2057 XMMRegister rreg = right->as_xmm_float_reg();
2078 2058 switch (code) {
2079 2059 case lir_add: __ addss(lreg, rreg); break;
2080 2060 case lir_sub: __ subss(lreg, rreg); break;
2081 2061 case lir_mul_strictfp: // fall through
2082 2062 case lir_mul: __ mulss(lreg, rreg); break;
2083 2063 case lir_div_strictfp: // fall through
2084 2064 case lir_div: __ divss(lreg, rreg); break;
2085 2065 default: ShouldNotReachHere();
2086 2066 }
2087 2067 } else {
2088 2068 Address raddr;
2089 2069 if (right->is_single_stack()) {
2090 2070 raddr = frame_map()->address_for_slot(right->single_stack_ix());
2091 2071 } else if (right->is_constant()) {
2092 2072 // hack for now
2093 2073 raddr = __ as_Address(InternalAddress(float_constant(right->as_jfloat())));
2094 2074 } else {
2095 2075 ShouldNotReachHere();
2096 2076 }
2097 2077 switch (code) {
2098 2078 case lir_add: __ addss(lreg, raddr); break;
2099 2079 case lir_sub: __ subss(lreg, raddr); break;
2100 2080 case lir_mul_strictfp: // fall through
2101 2081 case lir_mul: __ mulss(lreg, raddr); break;
2102 2082 case lir_div_strictfp: // fall through
2103 2083 case lir_div: __ divss(lreg, raddr); break;
2104 2084 default: ShouldNotReachHere();
2105 2085 }
2106 2086 }
2107 2087
2108 2088 } else if (left->is_double_xmm()) {
2109 2089 assert(left == dest, "left and dest must be equal");
2110 2090
2111 2091 XMMRegister lreg = left->as_xmm_double_reg();
2112 2092 if (right->is_double_xmm()) {
2113 2093 XMMRegister rreg = right->as_xmm_double_reg();
2114 2094 switch (code) {
2115 2095 case lir_add: __ addsd(lreg, rreg); break;
2116 2096 case lir_sub: __ subsd(lreg, rreg); break;
2117 2097 case lir_mul_strictfp: // fall through
2118 2098 case lir_mul: __ mulsd(lreg, rreg); break;
2119 2099 case lir_div_strictfp: // fall through
2120 2100 case lir_div: __ divsd(lreg, rreg); break;
2121 2101 default: ShouldNotReachHere();
2122 2102 }
2123 2103 } else {
2124 2104 Address raddr;
2125 2105 if (right->is_double_stack()) {
2126 2106 raddr = frame_map()->address_for_slot(right->double_stack_ix());
2127 2107 } else if (right->is_constant()) {
2128 2108 // hack for now
2129 2109 raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble())));
2130 2110 } else {
2131 2111 ShouldNotReachHere();
2132 2112 }
2133 2113 switch (code) {
2134 2114 case lir_add: __ addsd(lreg, raddr); break;
2135 2115 case lir_sub: __ subsd(lreg, raddr); break;
2136 2116 case lir_mul_strictfp: // fall through
2137 2117 case lir_mul: __ mulsd(lreg, raddr); break;
2138 2118 case lir_div_strictfp: // fall through
2139 2119 case lir_div: __ divsd(lreg, raddr); break;
2140 2120 default: ShouldNotReachHere();
2141 2121 }
2142 2122 }
2143 2123
2144 2124 } else if (left->is_single_fpu()) {
2145 2125 assert(dest->is_single_fpu(), "fpu stack allocation required");
2146 2126
2147 2127 if (right->is_single_fpu()) {
2148 2128 arith_fpu_implementation(code, left->fpu_regnr(), right->fpu_regnr(), dest->fpu_regnr(), pop_fpu_stack);
2149 2129
2150 2130 } else {
2151 2131 assert(left->fpu_regnr() == 0, "left must be on TOS");
2152 2132 assert(dest->fpu_regnr() == 0, "dest must be on TOS");
2153 2133
2154 2134 Address raddr;
2155 2135 if (right->is_single_stack()) {
2156 2136 raddr = frame_map()->address_for_slot(right->single_stack_ix());
2157 2137 } else if (right->is_constant()) {
2158 2138 address const_addr = float_constant(right->as_jfloat());
2159 2139 assert(const_addr != NULL, "incorrect float/double constant maintainance");
2160 2140 // hack for now
2161 2141 raddr = __ as_Address(InternalAddress(const_addr));
2162 2142 } else {
2163 2143 ShouldNotReachHere();
2164 2144 }
2165 2145
2166 2146 switch (code) {
2167 2147 case lir_add: __ fadd_s(raddr); break;
2168 2148 case lir_sub: __ fsub_s(raddr); break;
2169 2149 case lir_mul_strictfp: // fall through
2170 2150 case lir_mul: __ fmul_s(raddr); break;
2171 2151 case lir_div_strictfp: // fall through
2172 2152 case lir_div: __ fdiv_s(raddr); break;
2173 2153 default: ShouldNotReachHere();
2174 2154 }
2175 2155 }
2176 2156
2177 2157 } else if (left->is_double_fpu()) {
2178 2158 assert(dest->is_double_fpu(), "fpu stack allocation required");
2179 2159
2180 2160 if (code == lir_mul_strictfp || code == lir_div_strictfp) {
2181 2161 // Double values require special handling for strictfp mul/div on x86
2182 2162 __ fld_x(ExternalAddress(StubRoutines::addr_fpu_subnormal_bias1()));
2183 2163 __ fmulp(left->fpu_regnrLo() + 1);
2184 2164 }
2185 2165
2186 2166 if (right->is_double_fpu()) {
2187 2167 arith_fpu_implementation(code, left->fpu_regnrLo(), right->fpu_regnrLo(), dest->fpu_regnrLo(), pop_fpu_stack);
2188 2168
2189 2169 } else {
2190 2170 assert(left->fpu_regnrLo() == 0, "left must be on TOS");
2191 2171 assert(dest->fpu_regnrLo() == 0, "dest must be on TOS");
2192 2172
2193 2173 Address raddr;
2194 2174 if (right->is_double_stack()) {
2195 2175 raddr = frame_map()->address_for_slot(right->double_stack_ix());
2196 2176 } else if (right->is_constant()) {
2197 2177 // hack for now
2198 2178 raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble())));
2199 2179 } else {
2200 2180 ShouldNotReachHere();
2201 2181 }
2202 2182
2203 2183 switch (code) {
2204 2184 case lir_add: __ fadd_d(raddr); break;
2205 2185 case lir_sub: __ fsub_d(raddr); break;
2206 2186 case lir_mul_strictfp: // fall through
2207 2187 case lir_mul: __ fmul_d(raddr); break;
2208 2188 case lir_div_strictfp: // fall through
2209 2189 case lir_div: __ fdiv_d(raddr); break;
2210 2190 default: ShouldNotReachHere();
2211 2191 }
2212 2192 }
2213 2193
2214 2194 if (code == lir_mul_strictfp || code == lir_div_strictfp) {
2215 2195 // Double values require special handling for strictfp mul/div on x86
2216 2196 __ fld_x(ExternalAddress(StubRoutines::addr_fpu_subnormal_bias2()));
2217 2197 __ fmulp(dest->fpu_regnrLo() + 1);
2218 2198 }
2219 2199
2220 2200 } else if (left->is_single_stack() || left->is_address()) {
2221 2201 assert(left == dest, "left and dest must be equal");
2222 2202
2223 2203 Address laddr;
2224 2204 if (left->is_single_stack()) {
2225 2205 laddr = frame_map()->address_for_slot(left->single_stack_ix());
2226 2206 } else if (left->is_address()) {
2227 2207 laddr = as_Address(left->as_address_ptr());
2228 2208 } else {
2229 2209 ShouldNotReachHere();
2230 2210 }
2231 2211
2232 2212 if (right->is_single_cpu()) {
2233 2213 Register rreg = right->as_register();
2234 2214 switch (code) {
2235 2215 case lir_add: __ addl(laddr, rreg); break;
2236 2216 case lir_sub: __ subl(laddr, rreg); break;
2237 2217 default: ShouldNotReachHere();
2238 2218 }
2239 2219 } else if (right->is_constant()) {
2240 2220 jint c = right->as_constant_ptr()->as_jint();
2241 2221 switch (code) {
2242 2222 case lir_add: {
2243 2223 __ incrementl(laddr, c);
2244 2224 break;
2245 2225 }
2246 2226 case lir_sub: {
2247 2227 __ decrementl(laddr, c);
2248 2228 break;
2249 2229 }
2250 2230 default: ShouldNotReachHere();
2251 2231 }
2252 2232 } else {
2253 2233 ShouldNotReachHere();
2254 2234 }
2255 2235
2256 2236 } else {
2257 2237 ShouldNotReachHere();
2258 2238 }
2259 2239 }
2260 2240
2261 2241 void LIR_Assembler::arith_fpu_implementation(LIR_Code code, int left_index, int right_index, int dest_index, bool pop_fpu_stack) {
2262 2242 assert(pop_fpu_stack || (left_index == dest_index || right_index == dest_index), "invalid LIR");
2263 2243 assert(!pop_fpu_stack || (left_index - 1 == dest_index || right_index - 1 == dest_index), "invalid LIR");
2264 2244 assert(left_index == 0 || right_index == 0, "either must be on top of stack");
2265 2245
2266 2246 bool left_is_tos = (left_index == 0);
2267 2247 bool dest_is_tos = (dest_index == 0);
2268 2248 int non_tos_index = (left_is_tos ? right_index : left_index);
2269 2249
2270 2250 switch (code) {
2271 2251 case lir_add:
2272 2252 if (pop_fpu_stack) __ faddp(non_tos_index);
2273 2253 else if (dest_is_tos) __ fadd (non_tos_index);
2274 2254 else __ fadda(non_tos_index);
2275 2255 break;
2276 2256
2277 2257 case lir_sub:
2278 2258 if (left_is_tos) {
2279 2259 if (pop_fpu_stack) __ fsubrp(non_tos_index);
2280 2260 else if (dest_is_tos) __ fsub (non_tos_index);
2281 2261 else __ fsubra(non_tos_index);
2282 2262 } else {
2283 2263 if (pop_fpu_stack) __ fsubp (non_tos_index);
2284 2264 else if (dest_is_tos) __ fsubr (non_tos_index);
2285 2265 else __ fsuba (non_tos_index);
2286 2266 }
2287 2267 break;
2288 2268
2289 2269 case lir_mul_strictfp: // fall through
2290 2270 case lir_mul:
2291 2271 if (pop_fpu_stack) __ fmulp(non_tos_index);
2292 2272 else if (dest_is_tos) __ fmul (non_tos_index);
2293 2273 else __ fmula(non_tos_index);
2294 2274 break;
2295 2275
2296 2276 case lir_div_strictfp: // fall through
2297 2277 case lir_div:
2298 2278 if (left_is_tos) {
2299 2279 if (pop_fpu_stack) __ fdivrp(non_tos_index);
2300 2280 else if (dest_is_tos) __ fdiv (non_tos_index);
2301 2281 else __ fdivra(non_tos_index);
2302 2282 } else {
2303 2283 if (pop_fpu_stack) __ fdivp (non_tos_index);
2304 2284 else if (dest_is_tos) __ fdivr (non_tos_index);
2305 2285 else __ fdiva (non_tos_index);
2306 2286 }
2307 2287 break;
2308 2288
2309 2289 case lir_rem:
2310 2290 assert(left_is_tos && dest_is_tos && right_index == 1, "must be guaranteed by FPU stack allocation");
2311 2291 __ fremr(noreg);
2312 2292 break;
2313 2293
2314 2294 default:
2315 2295 ShouldNotReachHere();
2316 2296 }
2317 2297 }
2318 2298
2319 2299
2320 2300 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr unused, LIR_Opr dest, LIR_Op* op) {
2321 2301 if (value->is_double_xmm()) {
2322 2302 switch(code) {
2323 2303 case lir_abs :
2324 2304 {
2325 2305 if (dest->as_xmm_double_reg() != value->as_xmm_double_reg()) {
2326 2306 __ movdbl(dest->as_xmm_double_reg(), value->as_xmm_double_reg());
2327 2307 }
2328 2308 __ andpd(dest->as_xmm_double_reg(),
2329 2309 ExternalAddress((address)double_signmask_pool));
2330 2310 }
2331 2311 break;
2332 2312
2333 2313 case lir_sqrt: __ sqrtsd(dest->as_xmm_double_reg(), value->as_xmm_double_reg()); break;
2334 2314 // all other intrinsics are not available in the SSE instruction set, so FPU is used
2335 2315 default : ShouldNotReachHere();
2336 2316 }
2337 2317
2338 2318 } else if (value->is_double_fpu()) {
2339 2319 assert(value->fpu_regnrLo() == 0 && dest->fpu_regnrLo() == 0, "both must be on TOS");
2340 2320 switch(code) {
2341 2321 case lir_log : __ flog() ; break;
2342 2322 case lir_log10 : __ flog10() ; break;
2343 2323 case lir_abs : __ fabs() ; break;
2344 2324 case lir_sqrt : __ fsqrt(); break;
2345 2325 case lir_sin :
2346 2326 // Should consider not saving rbx, if not necessary
2347 2327 __ trigfunc('s', op->as_Op2()->fpu_stack_size());
2348 2328 break;
2349 2329 case lir_cos :
2350 2330 // Should consider not saving rbx, if not necessary
2351 2331 assert(op->as_Op2()->fpu_stack_size() <= 6, "sin and cos need two free stack slots");
2352 2332 __ trigfunc('c', op->as_Op2()->fpu_stack_size());
2353 2333 break;
2354 2334 case lir_tan :
2355 2335 // Should consider not saving rbx, if not necessary
2356 2336 __ trigfunc('t', op->as_Op2()->fpu_stack_size());
2357 2337 break;
2358 2338 default : ShouldNotReachHere();
2359 2339 }
2360 2340 } else {
2361 2341 Unimplemented();
2362 2342 }
2363 2343 }
2364 2344
2365 2345 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) {
2366 2346 // assert(left->destroys_register(), "check");
2367 2347 if (left->is_single_cpu()) {
2368 2348 Register reg = left->as_register();
2369 2349 if (right->is_constant()) {
2370 2350 int val = right->as_constant_ptr()->as_jint();
2371 2351 switch (code) {
2372 2352 case lir_logic_and: __ andl (reg, val); break;
2373 2353 case lir_logic_or: __ orl (reg, val); break;
2374 2354 case lir_logic_xor: __ xorl (reg, val); break;
2375 2355 default: ShouldNotReachHere();
2376 2356 }
2377 2357 } else if (right->is_stack()) {
2378 2358 // added support for stack operands
2379 2359 Address raddr = frame_map()->address_for_slot(right->single_stack_ix());
2380 2360 switch (code) {
2381 2361 case lir_logic_and: __ andl (reg, raddr); break;
2382 2362 case lir_logic_or: __ orl (reg, raddr); break;
2383 2363 case lir_logic_xor: __ xorl (reg, raddr); break;
2384 2364 default: ShouldNotReachHere();
2385 2365 }
2386 2366 } else {
2387 2367 Register rright = right->as_register();
2388 2368 switch (code) {
2389 2369 case lir_logic_and: __ andptr (reg, rright); break;
2390 2370 case lir_logic_or : __ orptr (reg, rright); break;
2391 2371 case lir_logic_xor: __ xorptr (reg, rright); break;
2392 2372 default: ShouldNotReachHere();
2393 2373 }
2394 2374 }
2395 2375 move_regs(reg, dst->as_register());
2396 2376 } else {
2397 2377 Register l_lo = left->as_register_lo();
2398 2378 Register l_hi = left->as_register_hi();
2399 2379 if (right->is_constant()) {
2400 2380 #ifdef _LP64
2401 2381 __ mov64(rscratch1, right->as_constant_ptr()->as_jlong());
2402 2382 switch (code) {
2403 2383 case lir_logic_and:
2404 2384 __ andq(l_lo, rscratch1);
2405 2385 break;
2406 2386 case lir_logic_or:
2407 2387 __ orq(l_lo, rscratch1);
2408 2388 break;
2409 2389 case lir_logic_xor:
2410 2390 __ xorq(l_lo, rscratch1);
2411 2391 break;
2412 2392 default: ShouldNotReachHere();
2413 2393 }
2414 2394 #else
2415 2395 int r_lo = right->as_constant_ptr()->as_jint_lo();
2416 2396 int r_hi = right->as_constant_ptr()->as_jint_hi();
2417 2397 switch (code) {
2418 2398 case lir_logic_and:
2419 2399 __ andl(l_lo, r_lo);
2420 2400 __ andl(l_hi, r_hi);
2421 2401 break;
2422 2402 case lir_logic_or:
2423 2403 __ orl(l_lo, r_lo);
2424 2404 __ orl(l_hi, r_hi);
2425 2405 break;
2426 2406 case lir_logic_xor:
2427 2407 __ xorl(l_lo, r_lo);
2428 2408 __ xorl(l_hi, r_hi);
2429 2409 break;
2430 2410 default: ShouldNotReachHere();
2431 2411 }
2432 2412 #endif // _LP64
2433 2413 } else {
2434 2414 Register r_lo = right->as_register_lo();
2435 2415 Register r_hi = right->as_register_hi();
2436 2416 assert(l_lo != r_hi, "overwriting registers");
2437 2417 switch (code) {
2438 2418 case lir_logic_and:
2439 2419 __ andptr(l_lo, r_lo);
2440 2420 NOT_LP64(__ andptr(l_hi, r_hi);)
2441 2421 break;
2442 2422 case lir_logic_or:
2443 2423 __ orptr(l_lo, r_lo);
2444 2424 NOT_LP64(__ orptr(l_hi, r_hi);)
2445 2425 break;
2446 2426 case lir_logic_xor:
2447 2427 __ xorptr(l_lo, r_lo);
2448 2428 NOT_LP64(__ xorptr(l_hi, r_hi);)
2449 2429 break;
2450 2430 default: ShouldNotReachHere();
2451 2431 }
2452 2432 }
2453 2433
2454 2434 Register dst_lo = dst->as_register_lo();
2455 2435 Register dst_hi = dst->as_register_hi();
2456 2436
2457 2437 #ifdef _LP64
2458 2438 move_regs(l_lo, dst_lo);
2459 2439 #else
2460 2440 if (dst_lo == l_hi) {
2461 2441 assert(dst_hi != l_lo, "overwriting registers");
2462 2442 move_regs(l_hi, dst_hi);
2463 2443 move_regs(l_lo, dst_lo);
2464 2444 } else {
2465 2445 assert(dst_lo != l_hi, "overwriting registers");
2466 2446 move_regs(l_lo, dst_lo);
2467 2447 move_regs(l_hi, dst_hi);
2468 2448 }
2469 2449 #endif // _LP64
2470 2450 }
2471 2451 }
2472 2452
2473 2453
2474 2454 // we assume that rax, and rdx can be overwritten
2475 2455 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info) {
2476 2456
2477 2457 assert(left->is_single_cpu(), "left must be register");
2478 2458 assert(right->is_single_cpu() || right->is_constant(), "right must be register or constant");
2479 2459 assert(result->is_single_cpu(), "result must be register");
2480 2460
2481 2461 // assert(left->destroys_register(), "check");
2482 2462 // assert(right->destroys_register(), "check");
2483 2463
2484 2464 Register lreg = left->as_register();
2485 2465 Register dreg = result->as_register();
2486 2466
2487 2467 if (right->is_constant()) {
2488 2468 int divisor = right->as_constant_ptr()->as_jint();
2489 2469 assert(divisor > 0 && is_power_of_2(divisor), "must be");
2490 2470 if (code == lir_idiv) {
2491 2471 assert(lreg == rax, "must be rax,");
2492 2472 assert(temp->as_register() == rdx, "tmp register must be rdx");
2493 2473 __ cdql(); // sign extend into rdx:rax
2494 2474 if (divisor == 2) {
2495 2475 __ subl(lreg, rdx);
2496 2476 } else {
2497 2477 __ andl(rdx, divisor - 1);
2498 2478 __ addl(lreg, rdx);
2499 2479 }
2500 2480 __ sarl(lreg, log2_intptr(divisor));
2501 2481 move_regs(lreg, dreg);
2502 2482 } else if (code == lir_irem) {
2503 2483 Label done;
2504 2484 __ mov(dreg, lreg);
2505 2485 __ andl(dreg, 0x80000000 | (divisor - 1));
2506 2486 __ jcc(Assembler::positive, done);
2507 2487 __ decrement(dreg);
2508 2488 __ orl(dreg, ~(divisor - 1));
2509 2489 __ increment(dreg);
2510 2490 __ bind(done);
2511 2491 } else {
2512 2492 ShouldNotReachHere();
2513 2493 }
2514 2494 } else {
2515 2495 Register rreg = right->as_register();
2516 2496 assert(lreg == rax, "left register must be rax,");
2517 2497 assert(rreg != rdx, "right register must not be rdx");
2518 2498 assert(temp->as_register() == rdx, "tmp register must be rdx");
2519 2499
2520 2500 move_regs(lreg, rax);
2521 2501
2522 2502 int idivl_offset = __ corrected_idivl(rreg);
2523 2503 add_debug_info_for_div0(idivl_offset, info);
2524 2504 if (code == lir_irem) {
2525 2505 move_regs(rdx, dreg); // result is in rdx
2526 2506 } else {
2527 2507 move_regs(rax, dreg);
2528 2508 }
2529 2509 }
2530 2510 }
2531 2511
2532 2512
2533 2513 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
2534 2514 if (opr1->is_single_cpu()) {
2535 2515 Register reg1 = opr1->as_register();
2536 2516 if (opr2->is_single_cpu()) {
2537 2517 // cpu register - cpu register
2538 2518 if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) {
2539 2519 __ cmpptr(reg1, opr2->as_register());
2540 2520 } else {
2541 2521 assert(opr2->type() != T_OBJECT && opr2->type() != T_ARRAY, "cmp int, oop?");
2542 2522 __ cmpl(reg1, opr2->as_register());
2543 2523 }
2544 2524 } else if (opr2->is_stack()) {
2545 2525 // cpu register - stack
2546 2526 if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) {
2547 2527 __ cmpptr(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2548 2528 } else {
2549 2529 __ cmpl(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2550 2530 }
2551 2531 } else if (opr2->is_constant()) {
2552 2532 // cpu register - constant
2553 2533 LIR_Const* c = opr2->as_constant_ptr();
2554 2534 if (c->type() == T_INT) {
2555 2535 __ cmpl(reg1, c->as_jint());
2556 2536 } else if (c->type() == T_OBJECT || c->type() == T_ARRAY) {
2557 2537 // In 64bit oops are single register
2558 2538 jobject o = c->as_jobject();
2559 2539 if (o == NULL) {
2560 2540 __ cmpptr(reg1, (int32_t)NULL_WORD);
2561 2541 } else {
2562 2542 #ifdef _LP64
2563 2543 __ movoop(rscratch1, o);
2564 2544 __ cmpptr(reg1, rscratch1);
2565 2545 #else
2566 2546 __ cmpoop(reg1, c->as_jobject());
2567 2547 #endif // _LP64
2568 2548 }
2569 2549 } else {
2570 2550 ShouldNotReachHere();
2571 2551 }
2572 2552 // cpu register - address
2573 2553 } else if (opr2->is_address()) {
2574 2554 if (op->info() != NULL) {
2575 2555 add_debug_info_for_null_check_here(op->info());
2576 2556 }
2577 2557 __ cmpl(reg1, as_Address(opr2->as_address_ptr()));
2578 2558 } else {
2579 2559 ShouldNotReachHere();
2580 2560 }
2581 2561
2582 2562 } else if(opr1->is_double_cpu()) {
2583 2563 Register xlo = opr1->as_register_lo();
2584 2564 Register xhi = opr1->as_register_hi();
2585 2565 if (opr2->is_double_cpu()) {
2586 2566 #ifdef _LP64
2587 2567 __ cmpptr(xlo, opr2->as_register_lo());
2588 2568 #else
2589 2569 // cpu register - cpu register
2590 2570 Register ylo = opr2->as_register_lo();
2591 2571 Register yhi = opr2->as_register_hi();
2592 2572 __ subl(xlo, ylo);
2593 2573 __ sbbl(xhi, yhi);
2594 2574 if (condition == lir_cond_equal || condition == lir_cond_notEqual) {
2595 2575 __ orl(xhi, xlo);
2596 2576 }
2597 2577 #endif // _LP64
2598 2578 } else if (opr2->is_constant()) {
2599 2579 // cpu register - constant 0
2600 2580 assert(opr2->as_jlong() == (jlong)0, "only handles zero");
2601 2581 #ifdef _LP64
2602 2582 __ cmpptr(xlo, (int32_t)opr2->as_jlong());
2603 2583 #else
2604 2584 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "only handles equals case");
2605 2585 __ orl(xhi, xlo);
2606 2586 #endif // _LP64
2607 2587 } else {
2608 2588 ShouldNotReachHere();
2609 2589 }
2610 2590
2611 2591 } else if (opr1->is_single_xmm()) {
2612 2592 XMMRegister reg1 = opr1->as_xmm_float_reg();
2613 2593 if (opr2->is_single_xmm()) {
2614 2594 // xmm register - xmm register
2615 2595 __ ucomiss(reg1, opr2->as_xmm_float_reg());
2616 2596 } else if (opr2->is_stack()) {
2617 2597 // xmm register - stack
2618 2598 __ ucomiss(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2619 2599 } else if (opr2->is_constant()) {
2620 2600 // xmm register - constant
2621 2601 __ ucomiss(reg1, InternalAddress(float_constant(opr2->as_jfloat())));
2622 2602 } else if (opr2->is_address()) {
2623 2603 // xmm register - address
2624 2604 if (op->info() != NULL) {
2625 2605 add_debug_info_for_null_check_here(op->info());
2626 2606 }
2627 2607 __ ucomiss(reg1, as_Address(opr2->as_address_ptr()));
2628 2608 } else {
2629 2609 ShouldNotReachHere();
2630 2610 }
2631 2611
2632 2612 } else if (opr1->is_double_xmm()) {
2633 2613 XMMRegister reg1 = opr1->as_xmm_double_reg();
2634 2614 if (opr2->is_double_xmm()) {
2635 2615 // xmm register - xmm register
2636 2616 __ ucomisd(reg1, opr2->as_xmm_double_reg());
2637 2617 } else if (opr2->is_stack()) {
2638 2618 // xmm register - stack
2639 2619 __ ucomisd(reg1, frame_map()->address_for_slot(opr2->double_stack_ix()));
2640 2620 } else if (opr2->is_constant()) {
2641 2621 // xmm register - constant
2642 2622 __ ucomisd(reg1, InternalAddress(double_constant(opr2->as_jdouble())));
2643 2623 } else if (opr2->is_address()) {
2644 2624 // xmm register - address
2645 2625 if (op->info() != NULL) {
2646 2626 add_debug_info_for_null_check_here(op->info());
2647 2627 }
2648 2628 __ ucomisd(reg1, as_Address(opr2->pointer()->as_address()));
2649 2629 } else {
2650 2630 ShouldNotReachHere();
2651 2631 }
2652 2632
2653 2633 } else if(opr1->is_single_fpu() || opr1->is_double_fpu()) {
2654 2634 assert(opr1->is_fpu_register() && opr1->fpu() == 0, "currently left-hand side must be on TOS (relax this restriction)");
2655 2635 assert(opr2->is_fpu_register(), "both must be registers");
2656 2636 __ fcmp(noreg, opr2->fpu(), op->fpu_pop_count() > 0, op->fpu_pop_count() > 1);
2657 2637
2658 2638 } else if (opr1->is_address() && opr2->is_constant()) {
2659 2639 LIR_Const* c = opr2->as_constant_ptr();
2660 2640 #ifdef _LP64
2661 2641 if (c->type() == T_OBJECT || c->type() == T_ARRAY) {
2662 2642 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "need to reverse");
2663 2643 __ movoop(rscratch1, c->as_jobject());
2664 2644 }
2665 2645 #endif // LP64
2666 2646 if (op->info() != NULL) {
2667 2647 add_debug_info_for_null_check_here(op->info());
2668 2648 }
2669 2649 // special case: address - constant
2670 2650 LIR_Address* addr = opr1->as_address_ptr();
2671 2651 if (c->type() == T_INT) {
2672 2652 __ cmpl(as_Address(addr), c->as_jint());
2673 2653 } else if (c->type() == T_OBJECT || c->type() == T_ARRAY) {
2674 2654 #ifdef _LP64
2675 2655 // %%% Make this explode if addr isn't reachable until we figure out a
2676 2656 // better strategy by giving noreg as the temp for as_Address
2677 2657 __ cmpptr(rscratch1, as_Address(addr, noreg));
2678 2658 #else
2679 2659 __ cmpoop(as_Address(addr), c->as_jobject());
2680 2660 #endif // _LP64
2681 2661 } else {
2682 2662 ShouldNotReachHere();
2683 2663 }
2684 2664
2685 2665 } else {
2686 2666 ShouldNotReachHere();
2687 2667 }
2688 2668 }
2689 2669
2690 2670 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op) {
2691 2671 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
2692 2672 if (left->is_single_xmm()) {
2693 2673 assert(right->is_single_xmm(), "must match");
2694 2674 __ cmpss2int(left->as_xmm_float_reg(), right->as_xmm_float_reg(), dst->as_register(), code == lir_ucmp_fd2i);
2695 2675 } else if (left->is_double_xmm()) {
2696 2676 assert(right->is_double_xmm(), "must match");
2697 2677 __ cmpsd2int(left->as_xmm_double_reg(), right->as_xmm_double_reg(), dst->as_register(), code == lir_ucmp_fd2i);
2698 2678
2699 2679 } else {
2700 2680 assert(left->is_single_fpu() || left->is_double_fpu(), "must be");
2701 2681 assert(right->is_single_fpu() || right->is_double_fpu(), "must match");
2702 2682
2703 2683 assert(left->fpu() == 0, "left must be on TOS");
2704 2684 __ fcmp2int(dst->as_register(), code == lir_ucmp_fd2i, right->fpu(),
2705 2685 op->fpu_pop_count() > 0, op->fpu_pop_count() > 1);
2706 2686 }
2707 2687 } else {
2708 2688 assert(code == lir_cmp_l2i, "check");
2709 2689 #ifdef _LP64
2710 2690 Register dest = dst->as_register();
2711 2691 __ xorptr(dest, dest);
2712 2692 Label high, done;
2713 2693 __ cmpptr(left->as_register_lo(), right->as_register_lo());
2714 2694 __ jcc(Assembler::equal, done);
2715 2695 __ jcc(Assembler::greater, high);
2716 2696 __ decrement(dest);
2717 2697 __ jmp(done);
2718 2698 __ bind(high);
2719 2699 __ increment(dest);
2720 2700
2721 2701 __ bind(done);
2722 2702
2723 2703 #else
2724 2704 __ lcmp2int(left->as_register_hi(),
2725 2705 left->as_register_lo(),
2726 2706 right->as_register_hi(),
2727 2707 right->as_register_lo());
2728 2708 move_regs(left->as_register_hi(), dst->as_register());
2729 2709 #endif // _LP64
2730 2710 }
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2731 2711 }
2732 2712
2733 2713
2734 2714 void LIR_Assembler::align_call(LIR_Code code) {
2735 2715 if (os::is_MP()) {
2736 2716 // make sure that the displacement word of the call ends up word aligned
2737 2717 int offset = __ offset();
2738 2718 switch (code) {
2739 2719 case lir_static_call:
2740 2720 case lir_optvirtual_call:
2721 + case lir_dynamic_call:
2741 2722 offset += NativeCall::displacement_offset;
2742 2723 break;
2743 2724 case lir_icvirtual_call:
2744 2725 offset += NativeCall::displacement_offset + NativeMovConstReg::instruction_size;
2745 2726 break;
2746 2727 case lir_virtual_call: // currently, sparc-specific for niagara
2747 2728 default: ShouldNotReachHere();
2748 2729 }
2749 2730 while (offset++ % BytesPerWord != 0) {
2750 2731 __ nop();
2751 2732 }
2752 2733 }
2753 2734 }
2754 2735
2755 2736
2756 -void LIR_Assembler::call(address entry, relocInfo::relocType rtype, CodeEmitInfo* info) {
2737 +void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
2757 2738 assert(!os::is_MP() || (__ offset() + NativeCall::displacement_offset) % BytesPerWord == 0,
2758 2739 "must be aligned");
2759 - __ call(AddressLiteral(entry, rtype));
2760 - add_call_info(code_offset(), info);
2740 + __ call(AddressLiteral(op->addr(), rtype));
2741 + add_call_info(code_offset(), op->info(), op->is_method_handle_invoke());
2761 2742 }
2762 2743
2763 2744
2764 -void LIR_Assembler::ic_call(address entry, CodeEmitInfo* info) {
2745 +void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
2765 2746 RelocationHolder rh = virtual_call_Relocation::spec(pc());
2766 2747 __ movoop(IC_Klass, (jobject)Universe::non_oop_word());
2767 2748 assert(!os::is_MP() ||
2768 2749 (__ offset() + NativeCall::displacement_offset) % BytesPerWord == 0,
2769 2750 "must be aligned");
2770 - __ call(AddressLiteral(entry, rh));
2771 - add_call_info(code_offset(), info);
2751 + __ call(AddressLiteral(op->addr(), rh));
2752 + add_call_info(code_offset(), op->info(), op->is_method_handle_invoke());
2772 2753 }
2773 2754
2774 2755
2775 2756 /* Currently, vtable-dispatch is only enabled for sparc platforms */
2776 -void LIR_Assembler::vtable_call(int vtable_offset, CodeEmitInfo* info) {
2757 +void LIR_Assembler::vtable_call(LIR_OpJavaCall* op) {
2777 2758 ShouldNotReachHere();
2778 2759 }
2779 2760
2761 +
2762 +void LIR_Assembler::preserve_SP() {
2763 + __ movptr(rbp, rsp);
2764 +}
2765 +
2766 +
2767 +void LIR_Assembler::restore_SP() {
2768 + __ movptr(rsp, rbp);
2769 +}
2770 +
2771 +
2780 2772 void LIR_Assembler::emit_static_call_stub() {
2781 2773 address call_pc = __ pc();
2782 2774 address stub = __ start_a_stub(call_stub_size);
2783 2775 if (stub == NULL) {
2784 2776 bailout("static call stub overflow");
2785 2777 return;
2786 2778 }
2787 2779
2788 2780 int start = __ offset();
2789 2781 if (os::is_MP()) {
2790 2782 // make sure that the displacement word of the call ends up word aligned
2791 2783 int offset = __ offset() + NativeMovConstReg::instruction_size + NativeCall::displacement_offset;
2792 2784 while (offset++ % BytesPerWord != 0) {
2793 2785 __ nop();
2794 2786 }
2795 2787 }
2796 2788 __ relocate(static_stub_Relocation::spec(call_pc));
2797 2789 __ movoop(rbx, (jobject)NULL);
2798 2790 // must be set to -1 at code generation time
2799 2791 assert(!os::is_MP() || ((__ offset() + 1) % BytesPerWord) == 0, "must be aligned on MP");
2800 2792 // On 64bit this will die since it will take a movq & jmp, must be only a jmp
2801 2793 __ jump(RuntimeAddress(__ pc()));
2802 2794
2803 2795 assert(__ offset() - start <= call_stub_size, "stub too big")
2804 2796 __ end_a_stub();
2805 2797 }
2806 2798
2807 2799
2808 2800 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info, bool unwind) {
2809 2801 assert(exceptionOop->as_register() == rax, "must match");
2810 2802 assert(unwind || exceptionPC->as_register() == rdx, "must match");
2811 2803
2812 2804 // exception object is not added to oop map by LinearScan
2813 2805 // (LinearScan assumes that no oops are in fixed registers)
2814 2806 info->add_register_oop(exceptionOop);
2815 2807 Runtime1::StubID unwind_id;
2816 2808
2817 2809 if (!unwind) {
2818 2810 // get current pc information
2819 2811 // pc is only needed if the method has an exception handler, the unwind code does not need it.
2820 2812 int pc_for_athrow_offset = __ offset();
2821 2813 InternalAddress pc_for_athrow(__ pc());
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2822 2814 __ lea(exceptionPC->as_register(), pc_for_athrow);
2823 2815 add_call_info(pc_for_athrow_offset, info); // for exception handler
2824 2816
2825 2817 __ verify_not_null_oop(rax);
2826 2818 // search an exception handler (rax: exception oop, rdx: throwing pc)
2827 2819 if (compilation()->has_fpu_code()) {
2828 2820 unwind_id = Runtime1::handle_exception_id;
2829 2821 } else {
2830 2822 unwind_id = Runtime1::handle_exception_nofpu_id;
2831 2823 }
2824 + __ call(RuntimeAddress(Runtime1::entry_for(unwind_id)));
2832 2825 } else {
2833 - unwind_id = Runtime1::unwind_exception_id;
2826 + // remove the activation
2827 + __ remove_frame(initial_frame_size_in_bytes());
2828 + __ jump(RuntimeAddress(Runtime1::entry_for(Runtime1::unwind_exception_id)));
2834 2829 }
2835 - __ call(RuntimeAddress(Runtime1::entry_for(unwind_id)));
2836 2830
2837 2831 // enough room for two byte trap
2838 2832 __ nop();
2839 2833 }
2840 2834
2841 2835
2842 2836 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2843 2837
2844 2838 // optimized version for linear scan:
2845 2839 // * count must be already in ECX (guaranteed by LinearScan)
2846 2840 // * left and dest must be equal
2847 2841 // * tmp must be unused
2848 2842 assert(count->as_register() == SHIFT_count, "count must be in ECX");
2849 2843 assert(left == dest, "left and dest must be equal");
2850 2844 assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
2851 2845
2852 2846 if (left->is_single_cpu()) {
2853 2847 Register value = left->as_register();
2854 2848 assert(value != SHIFT_count, "left cannot be ECX");
2855 2849
2856 2850 switch (code) {
2857 2851 case lir_shl: __ shll(value); break;
2858 2852 case lir_shr: __ sarl(value); break;
2859 2853 case lir_ushr: __ shrl(value); break;
2860 2854 default: ShouldNotReachHere();
2861 2855 }
2862 2856 } else if (left->is_double_cpu()) {
2863 2857 Register lo = left->as_register_lo();
2864 2858 Register hi = left->as_register_hi();
2865 2859 assert(lo != SHIFT_count && hi != SHIFT_count, "left cannot be ECX");
2866 2860 #ifdef _LP64
2867 2861 switch (code) {
2868 2862 case lir_shl: __ shlptr(lo); break;
2869 2863 case lir_shr: __ sarptr(lo); break;
2870 2864 case lir_ushr: __ shrptr(lo); break;
2871 2865 default: ShouldNotReachHere();
2872 2866 }
2873 2867 #else
2874 2868
2875 2869 switch (code) {
2876 2870 case lir_shl: __ lshl(hi, lo); break;
2877 2871 case lir_shr: __ lshr(hi, lo, true); break;
2878 2872 case lir_ushr: __ lshr(hi, lo, false); break;
2879 2873 default: ShouldNotReachHere();
2880 2874 }
2881 2875 #endif // LP64
2882 2876 } else {
2883 2877 ShouldNotReachHere();
2884 2878 }
2885 2879 }
2886 2880
2887 2881
2888 2882 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2889 2883 if (dest->is_single_cpu()) {
2890 2884 // first move left into dest so that left is not destroyed by the shift
2891 2885 Register value = dest->as_register();
2892 2886 count = count & 0x1F; // Java spec
2893 2887
2894 2888 move_regs(left->as_register(), value);
2895 2889 switch (code) {
2896 2890 case lir_shl: __ shll(value, count); break;
2897 2891 case lir_shr: __ sarl(value, count); break;
2898 2892 case lir_ushr: __ shrl(value, count); break;
2899 2893 default: ShouldNotReachHere();
2900 2894 }
2901 2895 } else if (dest->is_double_cpu()) {
2902 2896 #ifndef _LP64
2903 2897 Unimplemented();
2904 2898 #else
2905 2899 // first move left into dest so that left is not destroyed by the shift
2906 2900 Register value = dest->as_register_lo();
2907 2901 count = count & 0x1F; // Java spec
2908 2902
2909 2903 move_regs(left->as_register_lo(), value);
2910 2904 switch (code) {
2911 2905 case lir_shl: __ shlptr(value, count); break;
2912 2906 case lir_shr: __ sarptr(value, count); break;
2913 2907 case lir_ushr: __ shrptr(value, count); break;
2914 2908 default: ShouldNotReachHere();
2915 2909 }
2916 2910 #endif // _LP64
2917 2911 } else {
2918 2912 ShouldNotReachHere();
2919 2913 }
2920 2914 }
2921 2915
2922 2916
2923 2917 void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) {
2924 2918 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2925 2919 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2926 2920 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2927 2921 __ movptr (Address(rsp, offset_from_rsp_in_bytes), r);
2928 2922 }
2929 2923
2930 2924
2931 2925 void LIR_Assembler::store_parameter(jint c, int offset_from_rsp_in_words) {
2932 2926 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2933 2927 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2934 2928 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2935 2929 __ movptr (Address(rsp, offset_from_rsp_in_bytes), c);
2936 2930 }
2937 2931
2938 2932
2939 2933 void LIR_Assembler::store_parameter(jobject o, int offset_from_rsp_in_words) {
2940 2934 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2941 2935 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2942 2936 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2943 2937 __ movoop (Address(rsp, offset_from_rsp_in_bytes), o);
2944 2938 }
2945 2939
2946 2940
2947 2941 // This code replaces a call to arraycopy; no exception may
2948 2942 // be thrown in this code, they must be thrown in the System.arraycopy
2949 2943 // activation frame; we could save some checks if this would not be the case
2950 2944 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
2951 2945 ciArrayKlass* default_type = op->expected_type();
2952 2946 Register src = op->src()->as_register();
2953 2947 Register dst = op->dst()->as_register();
2954 2948 Register src_pos = op->src_pos()->as_register();
2955 2949 Register dst_pos = op->dst_pos()->as_register();
2956 2950 Register length = op->length()->as_register();
2957 2951 Register tmp = op->tmp()->as_register();
2958 2952
2959 2953 CodeStub* stub = op->stub();
2960 2954 int flags = op->flags();
2961 2955 BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL;
2962 2956 if (basic_type == T_ARRAY) basic_type = T_OBJECT;
2963 2957
2964 2958 // if we don't know anything or it's an object array, just go through the generic arraycopy
2965 2959 if (default_type == NULL) {
2966 2960 Label done;
2967 2961 // save outgoing arguments on stack in case call to System.arraycopy is needed
2968 2962 // HACK ALERT. This code used to push the parameters in a hardwired fashion
2969 2963 // for interpreter calling conventions. Now we have to do it in new style conventions.
2970 2964 // For the moment until C1 gets the new register allocator I just force all the
2971 2965 // args to the right place (except the register args) and then on the back side
2972 2966 // reload the register args properly if we go slow path. Yuck
2973 2967
2974 2968 // These are proper for the calling convention
2975 2969
2976 2970 store_parameter(length, 2);
2977 2971 store_parameter(dst_pos, 1);
2978 2972 store_parameter(dst, 0);
2979 2973
2980 2974 // these are just temporary placements until we need to reload
2981 2975 store_parameter(src_pos, 3);
2982 2976 store_parameter(src, 4);
2983 2977 NOT_LP64(assert(src == rcx && src_pos == rdx, "mismatch in calling convention");)
2984 2978
2985 2979 address entry = CAST_FROM_FN_PTR(address, Runtime1::arraycopy);
2986 2980
2987 2981 // pass arguments: may push as this is not a safepoint; SP must be fix at each safepoint
2988 2982 #ifdef _LP64
2989 2983 // The arguments are in java calling convention so we can trivially shift them to C
2990 2984 // convention
2991 2985 assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4);
2992 2986 __ mov(c_rarg0, j_rarg0);
2993 2987 assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4);
2994 2988 __ mov(c_rarg1, j_rarg1);
2995 2989 assert_different_registers(c_rarg2, j_rarg3, j_rarg4);
2996 2990 __ mov(c_rarg2, j_rarg2);
2997 2991 assert_different_registers(c_rarg3, j_rarg4);
2998 2992 __ mov(c_rarg3, j_rarg3);
2999 2993 #ifdef _WIN64
3000 2994 // Allocate abi space for args but be sure to keep stack aligned
3001 2995 __ subptr(rsp, 6*wordSize);
3002 2996 store_parameter(j_rarg4, 4);
3003 2997 __ call(RuntimeAddress(entry));
3004 2998 __ addptr(rsp, 6*wordSize);
3005 2999 #else
3006 3000 __ mov(c_rarg4, j_rarg4);
3007 3001 __ call(RuntimeAddress(entry));
3008 3002 #endif // _WIN64
3009 3003 #else
3010 3004 __ push(length);
3011 3005 __ push(dst_pos);
3012 3006 __ push(dst);
3013 3007 __ push(src_pos);
3014 3008 __ push(src);
3015 3009 __ call_VM_leaf(entry, 5); // removes pushed parameter from the stack
3016 3010
3017 3011 #endif // _LP64
3018 3012
3019 3013 __ cmpl(rax, 0);
3020 3014 __ jcc(Assembler::equal, *stub->continuation());
3021 3015
3022 3016 // Reload values from the stack so they are where the stub
3023 3017 // expects them.
3024 3018 __ movptr (dst, Address(rsp, 0*BytesPerWord));
3025 3019 __ movptr (dst_pos, Address(rsp, 1*BytesPerWord));
3026 3020 __ movptr (length, Address(rsp, 2*BytesPerWord));
3027 3021 __ movptr (src_pos, Address(rsp, 3*BytesPerWord));
3028 3022 __ movptr (src, Address(rsp, 4*BytesPerWord));
3029 3023 __ jmp(*stub->entry());
3030 3024
3031 3025 __ bind(*stub->continuation());
3032 3026 return;
3033 3027 }
3034 3028
3035 3029 assert(default_type != NULL && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point");
3036 3030
3037 3031 int elem_size = type2aelembytes(basic_type);
3038 3032 int shift_amount;
3039 3033 Address::ScaleFactor scale;
3040 3034
3041 3035 switch (elem_size) {
3042 3036 case 1 :
3043 3037 shift_amount = 0;
3044 3038 scale = Address::times_1;
3045 3039 break;
3046 3040 case 2 :
3047 3041 shift_amount = 1;
3048 3042 scale = Address::times_2;
3049 3043 break;
3050 3044 case 4 :
3051 3045 shift_amount = 2;
3052 3046 scale = Address::times_4;
3053 3047 break;
3054 3048 case 8 :
3055 3049 shift_amount = 3;
3056 3050 scale = Address::times_8;
3057 3051 break;
3058 3052 default:
3059 3053 ShouldNotReachHere();
3060 3054 }
3061 3055
3062 3056 Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes());
3063 3057 Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes());
3064 3058 Address src_klass_addr = Address(src, oopDesc::klass_offset_in_bytes());
3065 3059 Address dst_klass_addr = Address(dst, oopDesc::klass_offset_in_bytes());
3066 3060
3067 3061 // length and pos's are all sign extended at this point on 64bit
3068 3062
3069 3063 // test for NULL
3070 3064 if (flags & LIR_OpArrayCopy::src_null_check) {
3071 3065 __ testptr(src, src);
3072 3066 __ jcc(Assembler::zero, *stub->entry());
3073 3067 }
3074 3068 if (flags & LIR_OpArrayCopy::dst_null_check) {
3075 3069 __ testptr(dst, dst);
3076 3070 __ jcc(Assembler::zero, *stub->entry());
3077 3071 }
3078 3072
3079 3073 // check if negative
3080 3074 if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
3081 3075 __ testl(src_pos, src_pos);
3082 3076 __ jcc(Assembler::less, *stub->entry());
3083 3077 }
3084 3078 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
3085 3079 __ testl(dst_pos, dst_pos);
3086 3080 __ jcc(Assembler::less, *stub->entry());
3087 3081 }
3088 3082 if (flags & LIR_OpArrayCopy::length_positive_check) {
3089 3083 __ testl(length, length);
3090 3084 __ jcc(Assembler::less, *stub->entry());
3091 3085 }
3092 3086
3093 3087 if (flags & LIR_OpArrayCopy::src_range_check) {
3094 3088 __ lea(tmp, Address(src_pos, length, Address::times_1, 0));
3095 3089 __ cmpl(tmp, src_length_addr);
3096 3090 __ jcc(Assembler::above, *stub->entry());
3097 3091 }
3098 3092 if (flags & LIR_OpArrayCopy::dst_range_check) {
3099 3093 __ lea(tmp, Address(dst_pos, length, Address::times_1, 0));
3100 3094 __ cmpl(tmp, dst_length_addr);
3101 3095 __ jcc(Assembler::above, *stub->entry());
3102 3096 }
3103 3097
3104 3098 if (flags & LIR_OpArrayCopy::type_check) {
3105 3099 __ movptr(tmp, src_klass_addr);
3106 3100 __ cmpptr(tmp, dst_klass_addr);
3107 3101 __ jcc(Assembler::notEqual, *stub->entry());
3108 3102 }
3109 3103
3110 3104 #ifdef ASSERT
3111 3105 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
3112 3106 // Sanity check the known type with the incoming class. For the
3113 3107 // primitive case the types must match exactly with src.klass and
3114 3108 // dst.klass each exactly matching the default type. For the
3115 3109 // object array case, if no type check is needed then either the
3116 3110 // dst type is exactly the expected type and the src type is a
3117 3111 // subtype which we can't check or src is the same array as dst
3118 3112 // but not necessarily exactly of type default_type.
3119 3113 Label known_ok, halt;
3120 3114 __ movoop(tmp, default_type->constant_encoding());
3121 3115 if (basic_type != T_OBJECT) {
3122 3116 __ cmpptr(tmp, dst_klass_addr);
3123 3117 __ jcc(Assembler::notEqual, halt);
3124 3118 __ cmpptr(tmp, src_klass_addr);
3125 3119 __ jcc(Assembler::equal, known_ok);
3126 3120 } else {
3127 3121 __ cmpptr(tmp, dst_klass_addr);
3128 3122 __ jcc(Assembler::equal, known_ok);
3129 3123 __ cmpptr(src, dst);
3130 3124 __ jcc(Assembler::equal, known_ok);
3131 3125 }
3132 3126 __ bind(halt);
3133 3127 __ stop("incorrect type information in arraycopy");
3134 3128 __ bind(known_ok);
3135 3129 }
3136 3130 #endif
3137 3131
3138 3132 if (shift_amount > 0 && basic_type != T_OBJECT) {
3139 3133 __ shlptr(length, shift_amount);
3140 3134 }
3141 3135
3142 3136 #ifdef _LP64
3143 3137 assert_different_registers(c_rarg0, dst, dst_pos, length);
3144 3138 __ movl2ptr(src_pos, src_pos); //higher 32bits must be null
3145 3139 __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3146 3140 assert_different_registers(c_rarg1, length);
3147 3141 __ movl2ptr(dst_pos, dst_pos); //higher 32bits must be null
3148 3142 __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3149 3143 __ mov(c_rarg2, length);
3150 3144
3151 3145 #else
3152 3146 __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3153 3147 store_parameter(tmp, 0);
3154 3148 __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3155 3149 store_parameter(tmp, 1);
3156 3150 store_parameter(length, 2);
3157 3151 #endif // _LP64
3158 3152 if (basic_type == T_OBJECT) {
3159 3153 __ call_VM_leaf(CAST_FROM_FN_PTR(address, Runtime1::oop_arraycopy), 0);
3160 3154 } else {
3161 3155 __ call_VM_leaf(CAST_FROM_FN_PTR(address, Runtime1::primitive_arraycopy), 0);
3162 3156 }
3163 3157
3164 3158 __ bind(*stub->continuation());
3165 3159 }
3166 3160
3167 3161
3168 3162 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
3169 3163 Register obj = op->obj_opr()->as_register(); // may not be an oop
3170 3164 Register hdr = op->hdr_opr()->as_register();
3171 3165 Register lock = op->lock_opr()->as_register();
3172 3166 if (!UseFastLocking) {
3173 3167 __ jmp(*op->stub()->entry());
3174 3168 } else if (op->code() == lir_lock) {
3175 3169 Register scratch = noreg;
3176 3170 if (UseBiasedLocking) {
3177 3171 scratch = op->scratch_opr()->as_register();
3178 3172 }
3179 3173 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
3180 3174 // add debug info for NullPointerException only if one is possible
3181 3175 int null_check_offset = __ lock_object(hdr, obj, lock, scratch, *op->stub()->entry());
3182 3176 if (op->info() != NULL) {
3183 3177 add_debug_info_for_null_check(null_check_offset, op->info());
3184 3178 }
3185 3179 // done
3186 3180 } else if (op->code() == lir_unlock) {
3187 3181 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
3188 3182 __ unlock_object(hdr, obj, lock, *op->stub()->entry());
3189 3183 } else {
3190 3184 Unimplemented();
3191 3185 }
3192 3186 __ bind(*op->stub()->continuation());
3193 3187 }
3194 3188
3195 3189
3196 3190 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
3197 3191 ciMethod* method = op->profiled_method();
3198 3192 int bci = op->profiled_bci();
3199 3193
3200 3194 // Update counter for all call types
3201 3195 ciMethodData* md = method->method_data();
3202 3196 if (md == NULL) {
3203 3197 bailout("out of memory building methodDataOop");
3204 3198 return;
3205 3199 }
3206 3200 ciProfileData* data = md->bci_to_data(bci);
3207 3201 assert(data->is_CounterData(), "need CounterData for calls");
3208 3202 assert(op->mdo()->is_single_cpu(), "mdo must be allocated");
3209 3203 Register mdo = op->mdo()->as_register();
3210 3204 __ movoop(mdo, md->constant_encoding());
3211 3205 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
3212 3206 Bytecodes::Code bc = method->java_code_at_bci(bci);
3213 3207 // Perform additional virtual call profiling for invokevirtual and
3214 3208 // invokeinterface bytecodes
3215 3209 if ((bc == Bytecodes::_invokevirtual || bc == Bytecodes::_invokeinterface) &&
3216 3210 Tier1ProfileVirtualCalls) {
3217 3211 assert(op->recv()->is_single_cpu(), "recv must be allocated");
3218 3212 Register recv = op->recv()->as_register();
3219 3213 assert_different_registers(mdo, recv);
3220 3214 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
3221 3215 ciKlass* known_klass = op->known_holder();
3222 3216 if (Tier1OptimizeVirtualCallProfiling && known_klass != NULL) {
3223 3217 // We know the type that will be seen at this call site; we can
3224 3218 // statically update the methodDataOop rather than needing to do
3225 3219 // dynamic tests on the receiver type
3226 3220
3227 3221 // NOTE: we should probably put a lock around this search to
3228 3222 // avoid collisions by concurrent compilations
3229 3223 ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
3230 3224 uint i;
3231 3225 for (i = 0; i < VirtualCallData::row_limit(); i++) {
3232 3226 ciKlass* receiver = vc_data->receiver(i);
3233 3227 if (known_klass->equals(receiver)) {
3234 3228 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
3235 3229 __ addl(data_addr, DataLayout::counter_increment);
3236 3230 return;
3237 3231 }
3238 3232 }
3239 3233
3240 3234 // Receiver type not found in profile data; select an empty slot
3241 3235
3242 3236 // Note that this is less efficient than it should be because it
3243 3237 // always does a write to the receiver part of the
3244 3238 // VirtualCallData rather than just the first time
3245 3239 for (i = 0; i < VirtualCallData::row_limit(); i++) {
3246 3240 ciKlass* receiver = vc_data->receiver(i);
3247 3241 if (receiver == NULL) {
3248 3242 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)));
3249 3243 __ movoop(recv_addr, known_klass->constant_encoding());
3250 3244 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
3251 3245 __ addl(data_addr, DataLayout::counter_increment);
3252 3246 return;
3253 3247 }
3254 3248 }
3255 3249 } else {
3256 3250 __ movptr(recv, Address(recv, oopDesc::klass_offset_in_bytes()));
3257 3251 Label update_done;
3258 3252 uint i;
3259 3253 for (i = 0; i < VirtualCallData::row_limit(); i++) {
3260 3254 Label next_test;
3261 3255 // See if the receiver is receiver[n].
3262 3256 __ cmpptr(recv, Address(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i))));
3263 3257 __ jcc(Assembler::notEqual, next_test);
3264 3258 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
3265 3259 __ addl(data_addr, DataLayout::counter_increment);
3266 3260 __ jmp(update_done);
3267 3261 __ bind(next_test);
3268 3262 }
3269 3263
3270 3264 // Didn't find receiver; find next empty slot and fill it in
3271 3265 for (i = 0; i < VirtualCallData::row_limit(); i++) {
3272 3266 Label next_test;
3273 3267 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)));
3274 3268 __ cmpptr(recv_addr, (int32_t)NULL_WORD);
3275 3269 __ jcc(Assembler::notEqual, next_test);
3276 3270 __ movptr(recv_addr, recv);
3277 3271 __ movl(Address(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i))), DataLayout::counter_increment);
3278 3272 __ jmp(update_done);
3279 3273 __ bind(next_test);
3280 3274 }
3281 3275 // Receiver did not match any saved receiver and there is no empty row for it.
3282 3276 // Increment total counter to indicate polymorphic case.
3283 3277 __ addl(counter_addr, DataLayout::counter_increment);
3284 3278
3285 3279 __ bind(update_done);
3286 3280 }
3287 3281 } else {
3288 3282 // Static call
3289 3283 __ addl(counter_addr, DataLayout::counter_increment);
3290 3284 }
3291 3285 }
3292 3286
3293 3287
3294 3288 void LIR_Assembler::emit_delay(LIR_OpDelay*) {
3295 3289 Unimplemented();
3296 3290 }
3297 3291
3298 3292
3299 3293 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) {
3300 3294 __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no));
3301 3295 }
3302 3296
3303 3297
3304 3298 void LIR_Assembler::align_backward_branch_target() {
3305 3299 __ align(BytesPerWord);
3306 3300 }
3307 3301
3308 3302
3309 3303 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest) {
3310 3304 if (left->is_single_cpu()) {
3311 3305 __ negl(left->as_register());
3312 3306 move_regs(left->as_register(), dest->as_register());
3313 3307
3314 3308 } else if (left->is_double_cpu()) {
3315 3309 Register lo = left->as_register_lo();
3316 3310 #ifdef _LP64
3317 3311 Register dst = dest->as_register_lo();
3318 3312 __ movptr(dst, lo);
3319 3313 __ negptr(dst);
3320 3314 #else
3321 3315 Register hi = left->as_register_hi();
3322 3316 __ lneg(hi, lo);
3323 3317 if (dest->as_register_lo() == hi) {
3324 3318 assert(dest->as_register_hi() != lo, "destroying register");
3325 3319 move_regs(hi, dest->as_register_hi());
3326 3320 move_regs(lo, dest->as_register_lo());
3327 3321 } else {
3328 3322 move_regs(lo, dest->as_register_lo());
3329 3323 move_regs(hi, dest->as_register_hi());
3330 3324 }
3331 3325 #endif // _LP64
3332 3326
3333 3327 } else if (dest->is_single_xmm()) {
3334 3328 if (left->as_xmm_float_reg() != dest->as_xmm_float_reg()) {
3335 3329 __ movflt(dest->as_xmm_float_reg(), left->as_xmm_float_reg());
3336 3330 }
3337 3331 __ xorps(dest->as_xmm_float_reg(),
3338 3332 ExternalAddress((address)float_signflip_pool));
3339 3333
3340 3334 } else if (dest->is_double_xmm()) {
3341 3335 if (left->as_xmm_double_reg() != dest->as_xmm_double_reg()) {
3342 3336 __ movdbl(dest->as_xmm_double_reg(), left->as_xmm_double_reg());
3343 3337 }
3344 3338 __ xorpd(dest->as_xmm_double_reg(),
3345 3339 ExternalAddress((address)double_signflip_pool));
3346 3340
3347 3341 } else if (left->is_single_fpu() || left->is_double_fpu()) {
3348 3342 assert(left->fpu() == 0, "arg must be on TOS");
3349 3343 assert(dest->fpu() == 0, "dest must be TOS");
3350 3344 __ fchs();
3351 3345
3352 3346 } else {
3353 3347 ShouldNotReachHere();
3354 3348 }
3355 3349 }
3356 3350
3357 3351
3358 3352 void LIR_Assembler::leal(LIR_Opr addr, LIR_Opr dest) {
3359 3353 assert(addr->is_address() && dest->is_register(), "check");
3360 3354 Register reg;
3361 3355 reg = dest->as_pointer_register();
3362 3356 __ lea(reg, as_Address(addr->as_address_ptr()));
3363 3357 }
3364 3358
3365 3359
3366 3360
3367 3361 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
3368 3362 assert(!tmp->is_valid(), "don't need temporary");
3369 3363 __ call(RuntimeAddress(dest));
3370 3364 if (info != NULL) {
3371 3365 add_call_info_here(info);
3372 3366 }
3373 3367 }
3374 3368
3375 3369
3376 3370 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
3377 3371 assert(type == T_LONG, "only for volatile long fields");
3378 3372
3379 3373 if (info != NULL) {
3380 3374 add_debug_info_for_null_check_here(info);
3381 3375 }
3382 3376
3383 3377 if (src->is_double_xmm()) {
3384 3378 if (dest->is_double_cpu()) {
3385 3379 #ifdef _LP64
3386 3380 __ movdq(dest->as_register_lo(), src->as_xmm_double_reg());
3387 3381 #else
3388 3382 __ movdl(dest->as_register_lo(), src->as_xmm_double_reg());
3389 3383 __ psrlq(src->as_xmm_double_reg(), 32);
3390 3384 __ movdl(dest->as_register_hi(), src->as_xmm_double_reg());
3391 3385 #endif // _LP64
3392 3386 } else if (dest->is_double_stack()) {
3393 3387 __ movdbl(frame_map()->address_for_slot(dest->double_stack_ix()), src->as_xmm_double_reg());
3394 3388 } else if (dest->is_address()) {
3395 3389 __ movdbl(as_Address(dest->as_address_ptr()), src->as_xmm_double_reg());
3396 3390 } else {
3397 3391 ShouldNotReachHere();
3398 3392 }
3399 3393
3400 3394 } else if (dest->is_double_xmm()) {
3401 3395 if (src->is_double_stack()) {
3402 3396 __ movdbl(dest->as_xmm_double_reg(), frame_map()->address_for_slot(src->double_stack_ix()));
3403 3397 } else if (src->is_address()) {
3404 3398 __ movdbl(dest->as_xmm_double_reg(), as_Address(src->as_address_ptr()));
3405 3399 } else {
3406 3400 ShouldNotReachHere();
3407 3401 }
3408 3402
3409 3403 } else if (src->is_double_fpu()) {
3410 3404 assert(src->fpu_regnrLo() == 0, "must be TOS");
3411 3405 if (dest->is_double_stack()) {
3412 3406 __ fistp_d(frame_map()->address_for_slot(dest->double_stack_ix()));
3413 3407 } else if (dest->is_address()) {
3414 3408 __ fistp_d(as_Address(dest->as_address_ptr()));
3415 3409 } else {
3416 3410 ShouldNotReachHere();
3417 3411 }
3418 3412
3419 3413 } else if (dest->is_double_fpu()) {
3420 3414 assert(dest->fpu_regnrLo() == 0, "must be TOS");
3421 3415 if (src->is_double_stack()) {
3422 3416 __ fild_d(frame_map()->address_for_slot(src->double_stack_ix()));
3423 3417 } else if (src->is_address()) {
3424 3418 __ fild_d(as_Address(src->as_address_ptr()));
3425 3419 } else {
3426 3420 ShouldNotReachHere();
3427 3421 }
3428 3422 } else {
3429 3423 ShouldNotReachHere();
3430 3424 }
3431 3425 }
3432 3426
3433 3427
3434 3428 void LIR_Assembler::membar() {
3435 3429 // QQQ sparc TSO uses this,
3436 3430 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad));
3437 3431 }
3438 3432
3439 3433 void LIR_Assembler::membar_acquire() {
3440 3434 // No x86 machines currently require load fences
3441 3435 // __ load_fence();
3442 3436 }
3443 3437
3444 3438 void LIR_Assembler::membar_release() {
3445 3439 // No x86 machines currently require store fences
3446 3440 // __ store_fence();
3447 3441 }
3448 3442
3449 3443 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
3450 3444 assert(result_reg->is_register(), "check");
3451 3445 #ifdef _LP64
3452 3446 // __ get_thread(result_reg->as_register_lo());
3453 3447 __ mov(result_reg->as_register(), r15_thread);
3454 3448 #else
3455 3449 __ get_thread(result_reg->as_register());
3456 3450 #endif // _LP64
3457 3451 }
3458 3452
3459 3453
3460 3454 void LIR_Assembler::peephole(LIR_List*) {
3461 3455 // do nothing for now
3462 3456 }
3463 3457
3464 3458
3465 3459 #undef __
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