src/cpu/sparc/vm/c1_LIRAssembler_sparc.cpp
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src/cpu/sparc/vm/c1_LIRAssembler_sparc.cpp

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*** 680,699 **** } void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) { __ call(op->addr(), rtype); ! // the peephole pass fills the delay slot } void LIR_Assembler::ic_call(LIR_OpJavaCall* op) { RelocationHolder rspec = virtual_call_Relocation::spec(pc()); __ set_oop((jobject)Universe::non_oop_word(), G5_inline_cache_reg); __ relocate(rspec); __ call(op->addr(), relocInfo::none); ! // the peephole pass fills the delay slot } void LIR_Assembler::vtable_call(LIR_OpJavaCall* op) { add_debug_info_for_null_check_here(op->info()); --- 680,701 ---- } void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) { __ call(op->addr(), rtype); ! // The peephole pass fills the delay slot, add_call_info is done in ! // LIR_Assembler::emit_delay. } void LIR_Assembler::ic_call(LIR_OpJavaCall* op) { RelocationHolder rspec = virtual_call_Relocation::spec(pc()); __ set_oop((jobject)Universe::non_oop_word(), G5_inline_cache_reg); __ relocate(rspec); __ call(op->addr(), relocInfo::none); ! // The peephole pass fills the delay slot, add_call_info is done in ! // LIR_Assembler::emit_delay. } void LIR_Assembler::vtable_call(LIR_OpJavaCall* op) { add_debug_info_for_null_check_here(op->info());
*** 710,729 **** __ callr(G3_scratch, G0); // the peephole pass fills the delay slot } - void LIR_Assembler::preserve_SP(LIR_OpJavaCall* op) { - Unimplemented(); - } - - - void LIR_Assembler::restore_SP(LIR_OpJavaCall* op) { - Unimplemented(); - } - - // load with 32-bit displacement int LIR_Assembler::load(Register s, int disp, Register d, BasicType ld_type, CodeEmitInfo *info) { int load_offset = code_offset(); if (Assembler::is_simm13(disp)) { if (info != NULL) add_debug_info_for_null_check_here(info); --- 712,721 ----
*** 2875,2885 **** "only one instruction can go in a delay slot"); #endif // we may also be emitting the call info for the instruction // which we are the delay slot of. ! CodeEmitInfo * call_info = op->call_info(); if (call_info) { add_call_info(code_offset(), call_info); } if (VerifyStackAtCalls) { --- 2867,2877 ---- "only one instruction can go in a delay slot"); #endif // we may also be emitting the call info for the instruction // which we are the delay slot of. ! CodeEmitInfo* call_info = op->call_info(); if (call_info) { add_call_info(code_offset(), call_info); } if (VerifyStackAtCalls) {
*** 3100,3109 **** --- 3092,3102 ---- #ifndef PRODUCT if (LIRTracePeephole) { tty->print_cr("delayed"); inst->at(i - 1)->print(); inst->at(i)->print(); + tty->cr(); } #endif continue; } }
*** 3115,3126 **** break; } case lir_static_call: case lir_virtual_call: case lir_icvirtual_call: ! case lir_optvirtual_call: { ! LIR_Op* delay_op = NULL; LIR_Op* prev = inst->at(i - 1); if (LIRFillDelaySlots && prev && prev->code() == lir_move && prev->info() == NULL && (op->code() != lir_virtual_call || !prev->result_opr()->is_single_cpu() || prev->result_opr()->as_register() != O0) && --- 3108,3119 ---- break; } case lir_static_call: case lir_virtual_call: case lir_icvirtual_call: ! case lir_optvirtual_call: ! case lir_dynamic_call: { LIR_Op* prev = inst->at(i - 1); if (LIRFillDelaySlots && prev && prev->code() == lir_move && prev->info() == NULL && (op->code() != lir_virtual_call || !prev->result_opr()->is_single_cpu() || prev->result_opr()->as_register() != O0) &&
*** 3133,3151 **** #ifndef PRODUCT if (LIRTracePeephole) { tty->print_cr("delayed"); inst->at(i - 1)->print(); inst->at(i)->print(); } #endif continue; } ! if (!delay_op) { ! delay_op = new LIR_OpDelay(new LIR_Op0(lir_nop), op->as_OpJavaCall()->info()); inst->insert_before(i + 1, delay_op); - } break; } } } } --- 3126,3143 ---- #ifndef PRODUCT if (LIRTracePeephole) { tty->print_cr("delayed"); inst->at(i - 1)->print(); inst->at(i)->print(); + tty->cr(); } #endif continue; } ! LIR_Op* delay_op = new LIR_OpDelay(new LIR_Op0(lir_nop), op->as_OpJavaCall()->info()); inst->insert_before(i + 1, delay_op); break; } } } }
src/cpu/sparc/vm/c1_LIRAssembler_sparc.cpp
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