1 /*
2 * Copyright 2000-2010 Sun Microsystems, Inc. All Rights Reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
20 * CA 95054 USA or visit www.sun.com if you need additional information or
21 * have any questions.
22 *
23 */
24
25 # include "incls/_precompiled.incl"
26 # include "incls/_c1_LIRAssembler_sparc.cpp.incl"
27
28 #define __ _masm->
29
30
31 //------------------------------------------------------------
32
33
34 bool LIR_Assembler::is_small_constant(LIR_Opr opr) {
35 if (opr->is_constant()) {
36 LIR_Const* constant = opr->as_constant_ptr();
37 switch (constant->type()) {
38 case T_INT: {
39 jint value = constant->as_jint();
40 return Assembler::is_simm13(value);
41 }
42
43 default:
44 return false;
45 }
46 }
47 return false;
48 }
49
50
51 bool LIR_Assembler::is_single_instruction(LIR_Op* op) {
52 switch (op->code()) {
53 case lir_null_check:
54 return true;
55
56
57 case lir_add:
58 case lir_ushr:
59 case lir_shr:
60 case lir_shl:
61 // integer shifts and adds are always one instruction
62 return op->result_opr()->is_single_cpu();
63
64
65 case lir_move: {
66 LIR_Op1* op1 = op->as_Op1();
67 LIR_Opr src = op1->in_opr();
68 LIR_Opr dst = op1->result_opr();
69
70 if (src == dst) {
71 NEEDS_CLEANUP;
72 // this works around a problem where moves with the same src and dst
73 // end up in the delay slot and then the assembler swallows the mov
74 // since it has no effect and then it complains because the delay slot
75 // is empty. returning false stops the optimizer from putting this in
76 // the delay slot
77 return false;
78 }
79
80 // don't put moves involving oops into the delay slot since the VerifyOops code
81 // will make it much larger than a single instruction.
82 if (VerifyOops) {
83 return false;
84 }
85
86 if (src->is_double_cpu() || dst->is_double_cpu() || op1->patch_code() != lir_patch_none ||
87 ((src->is_double_fpu() || dst->is_double_fpu()) && op1->move_kind() != lir_move_normal)) {
88 return false;
89 }
90
91 if (dst->is_register()) {
92 if (src->is_address() && Assembler::is_simm13(src->as_address_ptr()->disp())) {
93 return !PatchALot;
94 } else if (src->is_single_stack()) {
95 return true;
96 }
97 }
98
99 if (src->is_register()) {
100 if (dst->is_address() && Assembler::is_simm13(dst->as_address_ptr()->disp())) {
101 return !PatchALot;
102 } else if (dst->is_single_stack()) {
103 return true;
104 }
105 }
106
107 if (dst->is_register() &&
108 ((src->is_register() && src->is_single_word() && src->is_same_type(dst)) ||
109 (src->is_constant() && LIR_Assembler::is_small_constant(op->as_Op1()->in_opr())))) {
110 return true;
111 }
112
113 return false;
114 }
115
116 default:
117 return false;
118 }
119 ShouldNotReachHere();
120 }
121
122
123 LIR_Opr LIR_Assembler::receiverOpr() {
124 return FrameMap::O0_oop_opr;
125 }
126
127
128 LIR_Opr LIR_Assembler::incomingReceiverOpr() {
129 return FrameMap::I0_oop_opr;
130 }
131
132
133 LIR_Opr LIR_Assembler::osrBufferPointer() {
134 return FrameMap::I0_opr;
135 }
136
137
138 int LIR_Assembler::initial_frame_size_in_bytes() {
139 return in_bytes(frame_map()->framesize_in_bytes());
140 }
141
142
143 // inline cache check: the inline cached class is in G5_inline_cache_reg(G5);
144 // we fetch the class of the receiver (O0) and compare it with the cached class.
145 // If they do not match we jump to slow case.
146 int LIR_Assembler::check_icache() {
147 int offset = __ offset();
148 __ inline_cache_check(O0, G5_inline_cache_reg);
149 return offset;
150 }
151
152
153 void LIR_Assembler::osr_entry() {
154 // On-stack-replacement entry sequence (interpreter frame layout described in interpreter_sparc.cpp):
155 //
156 // 1. Create a new compiled activation.
157 // 2. Initialize local variables in the compiled activation. The expression stack must be empty
158 // at the osr_bci; it is not initialized.
159 // 3. Jump to the continuation address in compiled code to resume execution.
160
161 // OSR entry point
162 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
163 BlockBegin* osr_entry = compilation()->hir()->osr_entry();
164 ValueStack* entry_state = osr_entry->end()->state();
165 int number_of_locks = entry_state->locks_size();
166
167 // Create a frame for the compiled activation.
168 __ build_frame(initial_frame_size_in_bytes());
169
170 // OSR buffer is
171 //
172 // locals[nlocals-1..0]
173 // monitors[number_of_locks-1..0]
174 //
175 // locals is a direct copy of the interpreter frame so in the osr buffer
176 // so first slot in the local array is the last local from the interpreter
177 // and last slot is local[0] (receiver) from the interpreter
178 //
179 // Similarly with locks. The first lock slot in the osr buffer is the nth lock
180 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
181 // in the interpreter frame (the method lock if a sync method)
182
183 // Initialize monitors in the compiled activation.
184 // I0: pointer to osr buffer
185 //
186 // All other registers are dead at this point and the locals will be
187 // copied into place by code emitted in the IR.
188
189 Register OSR_buf = osrBufferPointer()->as_register();
190 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
191 int monitor_offset = BytesPerWord * method()->max_locals() +
192 (2 * BytesPerWord) * (number_of_locks - 1);
193 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
194 // the OSR buffer using 2 word entries: first the lock and then
195 // the oop.
196 for (int i = 0; i < number_of_locks; i++) {
197 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
198 #ifdef ASSERT
199 // verify the interpreter's monitor has a non-null object
200 {
201 Label L;
202 __ ld_ptr(OSR_buf, slot_offset + 1*BytesPerWord, O7);
203 __ cmp(G0, O7);
204 __ br(Assembler::notEqual, false, Assembler::pt, L);
205 __ delayed()->nop();
206 __ stop("locked object is NULL");
207 __ bind(L);
208 }
209 #endif // ASSERT
210 // Copy the lock field into the compiled activation.
211 __ ld_ptr(OSR_buf, slot_offset + 0, O7);
212 __ st_ptr(O7, frame_map()->address_for_monitor_lock(i));
213 __ ld_ptr(OSR_buf, slot_offset + 1*BytesPerWord, O7);
214 __ st_ptr(O7, frame_map()->address_for_monitor_object(i));
215 }
216 }
217 }
218
219
220 // Optimized Library calls
221 // This is the fast version of java.lang.String.compare; it has not
222 // OSR-entry and therefore, we generate a slow version for OSR's
223 void LIR_Assembler::emit_string_compare(LIR_Opr left, LIR_Opr right, LIR_Opr dst, CodeEmitInfo* info) {
224 Register str0 = left->as_register();
225 Register str1 = right->as_register();
226
227 Label Ldone;
228
229 Register result = dst->as_register();
230 {
231 // Get a pointer to the first character of string0 in tmp0 and get string0.count in str0
232 // Get a pointer to the first character of string1 in tmp1 and get string1.count in str1
233 // Also, get string0.count-string1.count in o7 and get the condition code set
234 // Note: some instructions have been hoisted for better instruction scheduling
235
236 Register tmp0 = L0;
237 Register tmp1 = L1;
238 Register tmp2 = L2;
239
240 int value_offset = java_lang_String:: value_offset_in_bytes(); // char array
241 int offset_offset = java_lang_String::offset_offset_in_bytes(); // first character position
242 int count_offset = java_lang_String:: count_offset_in_bytes();
243
244 __ ld_ptr(str0, value_offset, tmp0);
245 __ ld(str0, offset_offset, tmp2);
246 __ add(tmp0, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp0);
247 __ ld(str0, count_offset, str0);
248 __ sll(tmp2, exact_log2(sizeof(jchar)), tmp2);
249
250 // str1 may be null
251 add_debug_info_for_null_check_here(info);
252
253 __ ld_ptr(str1, value_offset, tmp1);
254 __ add(tmp0, tmp2, tmp0);
255
256 __ ld(str1, offset_offset, tmp2);
257 __ add(tmp1, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp1);
258 __ ld(str1, count_offset, str1);
259 __ sll(tmp2, exact_log2(sizeof(jchar)), tmp2);
260 __ subcc(str0, str1, O7);
261 __ add(tmp1, tmp2, tmp1);
262 }
263
264 {
265 // Compute the minimum of the string lengths, scale it and store it in limit
266 Register count0 = I0;
267 Register count1 = I1;
268 Register limit = L3;
269
270 Label Lskip;
271 __ sll(count0, exact_log2(sizeof(jchar)), limit); // string0 is shorter
272 __ br(Assembler::greater, true, Assembler::pt, Lskip);
273 __ delayed()->sll(count1, exact_log2(sizeof(jchar)), limit); // string1 is shorter
274 __ bind(Lskip);
275
276 // If either string is empty (or both of them) the result is the difference in lengths
277 __ cmp(limit, 0);
278 __ br(Assembler::equal, true, Assembler::pn, Ldone);
279 __ delayed()->mov(O7, result); // result is difference in lengths
280 }
281
282 {
283 // Neither string is empty
284 Label Lloop;
285
286 Register base0 = L0;
287 Register base1 = L1;
288 Register chr0 = I0;
289 Register chr1 = I1;
290 Register limit = L3;
291
292 // Shift base0 and base1 to the end of the arrays, negate limit
293 __ add(base0, limit, base0);
294 __ add(base1, limit, base1);
295 __ neg(limit); // limit = -min{string0.count, strin1.count}
296
297 __ lduh(base0, limit, chr0);
298 __ bind(Lloop);
299 __ lduh(base1, limit, chr1);
300 __ subcc(chr0, chr1, chr0);
301 __ br(Assembler::notZero, false, Assembler::pn, Ldone);
302 assert(chr0 == result, "result must be pre-placed");
303 __ delayed()->inccc(limit, sizeof(jchar));
304 __ br(Assembler::notZero, true, Assembler::pt, Lloop);
305 __ delayed()->lduh(base0, limit, chr0);
306 }
307
308 // If strings are equal up to min length, return the length difference.
309 __ mov(O7, result);
310
311 // Otherwise, return the difference between the first mismatched chars.
312 __ bind(Ldone);
313 }
314
315
316 // --------------------------------------------------------------------------------------------
317
318 void LIR_Assembler::monitorexit(LIR_Opr obj_opr, LIR_Opr lock_opr, Register hdr, int monitor_no) {
319 if (!GenerateSynchronizationCode) return;
320
321 Register obj_reg = obj_opr->as_register();
322 Register lock_reg = lock_opr->as_register();
323
324 Address mon_addr = frame_map()->address_for_monitor_lock(monitor_no);
325 Register reg = mon_addr.base();
326 int offset = mon_addr.disp();
327 // compute pointer to BasicLock
328 if (mon_addr.is_simm13()) {
329 __ add(reg, offset, lock_reg);
330 }
331 else {
332 __ set(offset, lock_reg);
333 __ add(reg, lock_reg, lock_reg);
334 }
335 // unlock object
336 MonitorAccessStub* slow_case = new MonitorExitStub(lock_opr, UseFastLocking, monitor_no);
337 // _slow_case_stubs->append(slow_case);
338 // temporary fix: must be created after exceptionhandler, therefore as call stub
339 _slow_case_stubs->append(slow_case);
340 if (UseFastLocking) {
341 // try inlined fast unlocking first, revert to slow locking if it fails
342 // note: lock_reg points to the displaced header since the displaced header offset is 0!
343 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
344 __ unlock_object(hdr, obj_reg, lock_reg, *slow_case->entry());
345 } else {
346 // always do slow unlocking
347 // note: the slow unlocking code could be inlined here, however if we use
348 // slow unlocking, speed doesn't matter anyway and this solution is
349 // simpler and requires less duplicated code - additionally, the
350 // slow unlocking code is the same in either case which simplifies
351 // debugging
352 __ br(Assembler::always, false, Assembler::pt, *slow_case->entry());
353 __ delayed()->nop();
354 }
355 // done
356 __ bind(*slow_case->continuation());
357 }
358
359
360 int LIR_Assembler::emit_exception_handler() {
361 // if the last instruction is a call (typically to do a throw which
362 // is coming at the end after block reordering) the return address
363 // must still point into the code area in order to avoid assertion
364 // failures when searching for the corresponding bci => add a nop
365 // (was bug 5/14/1999 - gri)
366 __ nop();
367
368 // generate code for exception handler
369 ciMethod* method = compilation()->method();
370
371 address handler_base = __ start_a_stub(exception_handler_size);
372
373 if (handler_base == NULL) {
374 // not enough space left for the handler
375 bailout("exception handler overflow");
376 return -1;
377 }
378
379 int offset = code_offset();
380
381 __ call(Runtime1::entry_for(Runtime1::handle_exception_id), relocInfo::runtime_call_type);
382 __ delayed()->nop();
383 debug_only(__ stop("should have gone to the caller");)
384 assert(code_offset() - offset <= exception_handler_size, "overflow");
385 __ end_a_stub();
386
387 return offset;
388 }
389
390
391 int LIR_Assembler::emit_deopt_handler() {
392 // if the last instruction is a call (typically to do a throw which
393 // is coming at the end after block reordering) the return address
394 // must still point into the code area in order to avoid assertion
395 // failures when searching for the corresponding bci => add a nop
396 // (was bug 5/14/1999 - gri)
397 __ nop();
398
399 // generate code for deopt handler
400 ciMethod* method = compilation()->method();
401 address handler_base = __ start_a_stub(deopt_handler_size);
402 if (handler_base == NULL) {
403 // not enough space left for the handler
404 bailout("deopt handler overflow");
405 return -1;
406 }
407
408 int offset = code_offset();
409 AddressLiteral deopt_blob(SharedRuntime::deopt_blob()->unpack());
410 __ JUMP(deopt_blob, G3_scratch, 0); // sethi;jmp
411 __ delayed()->nop();
412 assert(code_offset() - offset <= deopt_handler_size, "overflow");
413 debug_only(__ stop("should have gone to the caller");)
414 __ end_a_stub();
415
416 return offset;
417 }
418
419
420 void LIR_Assembler::jobject2reg(jobject o, Register reg) {
421 if (o == NULL) {
422 __ set(NULL_WORD, reg);
423 } else {
424 int oop_index = __ oop_recorder()->find_index(o);
425 RelocationHolder rspec = oop_Relocation::spec(oop_index);
426 __ set(NULL_WORD, reg, rspec); // Will be set when the nmethod is created
427 }
428 }
429
430
431 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo *info) {
432 // Allocate a new index in oop table to hold the oop once it's been patched
433 int oop_index = __ oop_recorder()->allocate_index((jobject)NULL);
434 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id, oop_index);
435
436 AddressLiteral addrlit(NULL, oop_Relocation::spec(oop_index));
437 assert(addrlit.rspec().type() == relocInfo::oop_type, "must be an oop reloc");
438 // It may not seem necessary to use a sethi/add pair to load a NULL into dest, but the
439 // NULL will be dynamically patched later and the patched value may be large. We must
440 // therefore generate the sethi/add as a placeholders
441 __ patchable_set(addrlit, reg);
442
443 patching_epilog(patch, lir_patch_normal, reg, info);
444 }
445
446
447 void LIR_Assembler::emit_op3(LIR_Op3* op) {
448 Register Rdividend = op->in_opr1()->as_register();
449 Register Rdivisor = noreg;
450 Register Rscratch = op->in_opr3()->as_register();
451 Register Rresult = op->result_opr()->as_register();
452 int divisor = -1;
453
454 if (op->in_opr2()->is_register()) {
455 Rdivisor = op->in_opr2()->as_register();
456 } else {
457 divisor = op->in_opr2()->as_constant_ptr()->as_jint();
458 assert(Assembler::is_simm13(divisor), "can only handle simm13");
459 }
460
461 assert(Rdividend != Rscratch, "");
462 assert(Rdivisor != Rscratch, "");
463 assert(op->code() == lir_idiv || op->code() == lir_irem, "Must be irem or idiv");
464
465 if (Rdivisor == noreg && is_power_of_2(divisor)) {
466 // convert division by a power of two into some shifts and logical operations
467 if (op->code() == lir_idiv) {
468 if (divisor == 2) {
469 __ srl(Rdividend, 31, Rscratch);
470 } else {
471 __ sra(Rdividend, 31, Rscratch);
472 __ and3(Rscratch, divisor - 1, Rscratch);
473 }
474 __ add(Rdividend, Rscratch, Rscratch);
475 __ sra(Rscratch, log2_intptr(divisor), Rresult);
476 return;
477 } else {
478 if (divisor == 2) {
479 __ srl(Rdividend, 31, Rscratch);
480 } else {
481 __ sra(Rdividend, 31, Rscratch);
482 __ and3(Rscratch, divisor - 1,Rscratch);
483 }
484 __ add(Rdividend, Rscratch, Rscratch);
485 __ andn(Rscratch, divisor - 1,Rscratch);
486 __ sub(Rdividend, Rscratch, Rresult);
487 return;
488 }
489 }
490
491 __ sra(Rdividend, 31, Rscratch);
492 __ wry(Rscratch);
493 if (!VM_Version::v9_instructions_work()) {
494 // v9 doesn't require these nops
495 __ nop();
496 __ nop();
497 __ nop();
498 __ nop();
499 }
500
501 add_debug_info_for_div0_here(op->info());
502
503 if (Rdivisor != noreg) {
504 __ sdivcc(Rdividend, Rdivisor, (op->code() == lir_idiv ? Rresult : Rscratch));
505 } else {
506 assert(Assembler::is_simm13(divisor), "can only handle simm13");
507 __ sdivcc(Rdividend, divisor, (op->code() == lir_idiv ? Rresult : Rscratch));
508 }
509
510 Label skip;
511 __ br(Assembler::overflowSet, true, Assembler::pn, skip);
512 __ delayed()->Assembler::sethi(0x80000000, (op->code() == lir_idiv ? Rresult : Rscratch));
513 __ bind(skip);
514
515 if (op->code() == lir_irem) {
516 if (Rdivisor != noreg) {
517 __ smul(Rscratch, Rdivisor, Rscratch);
518 } else {
519 __ smul(Rscratch, divisor, Rscratch);
520 }
521 __ sub(Rdividend, Rscratch, Rresult);
522 }
523 }
524
525
526 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
527 #ifdef ASSERT
528 assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label");
529 if (op->block() != NULL) _branch_target_blocks.append(op->block());
530 if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock());
531 #endif
532 assert(op->info() == NULL, "shouldn't have CodeEmitInfo");
533
534 if (op->cond() == lir_cond_always) {
535 __ br(Assembler::always, false, Assembler::pt, *(op->label()));
536 } else if (op->code() == lir_cond_float_branch) {
537 assert(op->ublock() != NULL, "must have unordered successor");
538 bool is_unordered = (op->ublock() == op->block());
539 Assembler::Condition acond;
540 switch (op->cond()) {
541 case lir_cond_equal: acond = Assembler::f_equal; break;
542 case lir_cond_notEqual: acond = Assembler::f_notEqual; break;
543 case lir_cond_less: acond = (is_unordered ? Assembler::f_unorderedOrLess : Assembler::f_less); break;
544 case lir_cond_greater: acond = (is_unordered ? Assembler::f_unorderedOrGreater : Assembler::f_greater); break;
545 case lir_cond_lessEqual: acond = (is_unordered ? Assembler::f_unorderedOrLessOrEqual : Assembler::f_lessOrEqual); break;
546 case lir_cond_greaterEqual: acond = (is_unordered ? Assembler::f_unorderedOrGreaterOrEqual: Assembler::f_greaterOrEqual); break;
547 default : ShouldNotReachHere();
548 };
549
550 if (!VM_Version::v9_instructions_work()) {
551 __ nop();
552 }
553 __ fb( acond, false, Assembler::pn, *(op->label()));
554 } else {
555 assert (op->code() == lir_branch, "just checking");
556
557 Assembler::Condition acond;
558 switch (op->cond()) {
559 case lir_cond_equal: acond = Assembler::equal; break;
560 case lir_cond_notEqual: acond = Assembler::notEqual; break;
561 case lir_cond_less: acond = Assembler::less; break;
562 case lir_cond_lessEqual: acond = Assembler::lessEqual; break;
563 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; break;
564 case lir_cond_greater: acond = Assembler::greater; break;
565 case lir_cond_aboveEqual: acond = Assembler::greaterEqualUnsigned; break;
566 case lir_cond_belowEqual: acond = Assembler::lessEqualUnsigned; break;
567 default: ShouldNotReachHere();
568 };
569
570 // sparc has different condition codes for testing 32-bit
571 // vs. 64-bit values. We could always test xcc is we could
572 // guarantee that 32-bit loads always sign extended but that isn't
573 // true and since sign extension isn't free, it would impose a
574 // slight cost.
575 #ifdef _LP64
576 if (op->type() == T_INT) {
577 __ br(acond, false, Assembler::pn, *(op->label()));
578 } else
579 #endif
580 __ brx(acond, false, Assembler::pn, *(op->label()));
581 }
582 // The peephole pass fills the delay slot
583 }
584
585
586 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
587 Bytecodes::Code code = op->bytecode();
588 LIR_Opr dst = op->result_opr();
589
590 switch(code) {
591 case Bytecodes::_i2l: {
592 Register rlo = dst->as_register_lo();
593 Register rhi = dst->as_register_hi();
594 Register rval = op->in_opr()->as_register();
595 #ifdef _LP64
596 __ sra(rval, 0, rlo);
597 #else
598 __ mov(rval, rlo);
599 __ sra(rval, BitsPerInt-1, rhi);
600 #endif
601 break;
602 }
603 case Bytecodes::_i2d:
604 case Bytecodes::_i2f: {
605 bool is_double = (code == Bytecodes::_i2d);
606 FloatRegister rdst = is_double ? dst->as_double_reg() : dst->as_float_reg();
607 FloatRegisterImpl::Width w = is_double ? FloatRegisterImpl::D : FloatRegisterImpl::S;
608 FloatRegister rsrc = op->in_opr()->as_float_reg();
609 if (rsrc != rdst) {
610 __ fmov(FloatRegisterImpl::S, rsrc, rdst);
611 }
612 __ fitof(w, rdst, rdst);
613 break;
614 }
615 case Bytecodes::_f2i:{
616 FloatRegister rsrc = op->in_opr()->as_float_reg();
617 Address addr = frame_map()->address_for_slot(dst->single_stack_ix());
618 Label L;
619 // result must be 0 if value is NaN; test by comparing value to itself
620 __ fcmp(FloatRegisterImpl::S, Assembler::fcc0, rsrc, rsrc);
621 if (!VM_Version::v9_instructions_work()) {
622 __ nop();
623 }
624 __ fb(Assembler::f_unordered, true, Assembler::pn, L);
625 __ delayed()->st(G0, addr); // annuled if contents of rsrc is not NaN
626 __ ftoi(FloatRegisterImpl::S, rsrc, rsrc);
627 // move integer result from float register to int register
628 __ stf(FloatRegisterImpl::S, rsrc, addr.base(), addr.disp());
629 __ bind (L);
630 break;
631 }
632 case Bytecodes::_l2i: {
633 Register rlo = op->in_opr()->as_register_lo();
634 Register rhi = op->in_opr()->as_register_hi();
635 Register rdst = dst->as_register();
636 #ifdef _LP64
637 __ sra(rlo, 0, rdst);
638 #else
639 __ mov(rlo, rdst);
640 #endif
641 break;
642 }
643 case Bytecodes::_d2f:
644 case Bytecodes::_f2d: {
645 bool is_double = (code == Bytecodes::_f2d);
646 assert((!is_double && dst->is_single_fpu()) || (is_double && dst->is_double_fpu()), "check");
647 LIR_Opr val = op->in_opr();
648 FloatRegister rval = (code == Bytecodes::_d2f) ? val->as_double_reg() : val->as_float_reg();
649 FloatRegister rdst = is_double ? dst->as_double_reg() : dst->as_float_reg();
650 FloatRegisterImpl::Width vw = is_double ? FloatRegisterImpl::S : FloatRegisterImpl::D;
651 FloatRegisterImpl::Width dw = is_double ? FloatRegisterImpl::D : FloatRegisterImpl::S;
652 __ ftof(vw, dw, rval, rdst);
653 break;
654 }
655 case Bytecodes::_i2s:
656 case Bytecodes::_i2b: {
657 Register rval = op->in_opr()->as_register();
658 Register rdst = dst->as_register();
659 int shift = (code == Bytecodes::_i2b) ? (BitsPerInt - T_BYTE_aelem_bytes * BitsPerByte) : (BitsPerInt - BitsPerShort);
660 __ sll (rval, shift, rdst);
661 __ sra (rdst, shift, rdst);
662 break;
663 }
664 case Bytecodes::_i2c: {
665 Register rval = op->in_opr()->as_register();
666 Register rdst = dst->as_register();
667 int shift = BitsPerInt - T_CHAR_aelem_bytes * BitsPerByte;
668 __ sll (rval, shift, rdst);
669 __ srl (rdst, shift, rdst);
670 break;
671 }
672
673 default: ShouldNotReachHere();
674 }
675 }
676
677
678 void LIR_Assembler::align_call(LIR_Code) {
679 // do nothing since all instructions are word aligned on sparc
680 }
681
682
683 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
684 __ call(op->addr(), rtype);
685 // The peephole pass fills the delay slot, add_call_info is done in
686 // LIR_Assembler::emit_delay.
687 }
688
689
690 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
691 RelocationHolder rspec = virtual_call_Relocation::spec(pc());
692 __ set_oop((jobject)Universe::non_oop_word(), G5_inline_cache_reg);
693 __ relocate(rspec);
694 __ call(op->addr(), relocInfo::none);
695 // The peephole pass fills the delay slot, add_call_info is done in
696 // LIR_Assembler::emit_delay.
697 }
698
699
700 void LIR_Assembler::vtable_call(LIR_OpJavaCall* op) {
701 add_debug_info_for_null_check_here(op->info());
702 __ ld_ptr(O0, oopDesc::klass_offset_in_bytes(), G3_scratch);
703 if (__ is_simm13(op->vtable_offset())) {
704 __ ld_ptr(G3_scratch, op->vtable_offset(), G5_method);
705 } else {
706 // This will generate 2 instructions
707 __ set(op->vtable_offset(), G5_method);
708 // ld_ptr, set_hi, set
709 __ ld_ptr(G3_scratch, G5_method, G5_method);
710 }
711 __ ld_ptr(G5_method, methodOopDesc::from_compiled_offset(), G3_scratch);
712 __ callr(G3_scratch, G0);
713 // the peephole pass fills the delay slot
714 }
715
716
717 // load with 32-bit displacement
718 int LIR_Assembler::load(Register s, int disp, Register d, BasicType ld_type, CodeEmitInfo *info) {
719 int load_offset = code_offset();
720 if (Assembler::is_simm13(disp)) {
721 if (info != NULL) add_debug_info_for_null_check_here(info);
722 switch(ld_type) {
723 case T_BOOLEAN: // fall through
724 case T_BYTE : __ ldsb(s, disp, d); break;
725 case T_CHAR : __ lduh(s, disp, d); break;
726 case T_SHORT : __ ldsh(s, disp, d); break;
727 case T_INT : __ ld(s, disp, d); break;
728 case T_ADDRESS:// fall through
729 case T_ARRAY : // fall through
730 case T_OBJECT: __ ld_ptr(s, disp, d); break;
731 default : ShouldNotReachHere();
732 }
733 } else {
734 __ set(disp, O7);
735 if (info != NULL) add_debug_info_for_null_check_here(info);
736 load_offset = code_offset();
737 switch(ld_type) {
738 case T_BOOLEAN: // fall through
739 case T_BYTE : __ ldsb(s, O7, d); break;
740 case T_CHAR : __ lduh(s, O7, d); break;
741 case T_SHORT : __ ldsh(s, O7, d); break;
742 case T_INT : __ ld(s, O7, d); break;
743 case T_ADDRESS:// fall through
744 case T_ARRAY : // fall through
745 case T_OBJECT: __ ld_ptr(s, O7, d); break;
746 default : ShouldNotReachHere();
747 }
748 }
749 if (ld_type == T_ARRAY || ld_type == T_OBJECT) __ verify_oop(d);
750 return load_offset;
751 }
752
753
754 // store with 32-bit displacement
755 void LIR_Assembler::store(Register value, Register base, int offset, BasicType type, CodeEmitInfo *info) {
756 if (Assembler::is_simm13(offset)) {
757 if (info != NULL) add_debug_info_for_null_check_here(info);
758 switch (type) {
759 case T_BOOLEAN: // fall through
760 case T_BYTE : __ stb(value, base, offset); break;
761 case T_CHAR : __ sth(value, base, offset); break;
762 case T_SHORT : __ sth(value, base, offset); break;
763 case T_INT : __ stw(value, base, offset); break;
764 case T_ADDRESS:// fall through
765 case T_ARRAY : // fall through
766 case T_OBJECT: __ st_ptr(value, base, offset); break;
767 default : ShouldNotReachHere();
768 }
769 } else {
770 __ set(offset, O7);
771 if (info != NULL) add_debug_info_for_null_check_here(info);
772 switch (type) {
773 case T_BOOLEAN: // fall through
774 case T_BYTE : __ stb(value, base, O7); break;
775 case T_CHAR : __ sth(value, base, O7); break;
776 case T_SHORT : __ sth(value, base, O7); break;
777 case T_INT : __ stw(value, base, O7); break;
778 case T_ADDRESS:// fall through
779 case T_ARRAY : //fall through
780 case T_OBJECT: __ st_ptr(value, base, O7); break;
781 default : ShouldNotReachHere();
782 }
783 }
784 // Note: Do the store before verification as the code might be patched!
785 if (type == T_ARRAY || type == T_OBJECT) __ verify_oop(value);
786 }
787
788
789 // load float with 32-bit displacement
790 void LIR_Assembler::load(Register s, int disp, FloatRegister d, BasicType ld_type, CodeEmitInfo *info) {
791 FloatRegisterImpl::Width w;
792 switch(ld_type) {
793 case T_FLOAT : w = FloatRegisterImpl::S; break;
794 case T_DOUBLE: w = FloatRegisterImpl::D; break;
795 default : ShouldNotReachHere();
796 }
797
798 if (Assembler::is_simm13(disp)) {
799 if (info != NULL) add_debug_info_for_null_check_here(info);
800 if (disp % BytesPerLong != 0 && w == FloatRegisterImpl::D) {
801 __ ldf(FloatRegisterImpl::S, s, disp + BytesPerWord, d->successor());
802 __ ldf(FloatRegisterImpl::S, s, disp , d);
803 } else {
804 __ ldf(w, s, disp, d);
805 }
806 } else {
807 __ set(disp, O7);
808 if (info != NULL) add_debug_info_for_null_check_here(info);
809 __ ldf(w, s, O7, d);
810 }
811 }
812
813
814 // store float with 32-bit displacement
815 void LIR_Assembler::store(FloatRegister value, Register base, int offset, BasicType type, CodeEmitInfo *info) {
816 FloatRegisterImpl::Width w;
817 switch(type) {
818 case T_FLOAT : w = FloatRegisterImpl::S; break;
819 case T_DOUBLE: w = FloatRegisterImpl::D; break;
820 default : ShouldNotReachHere();
821 }
822
823 if (Assembler::is_simm13(offset)) {
824 if (info != NULL) add_debug_info_for_null_check_here(info);
825 if (w == FloatRegisterImpl::D && offset % BytesPerLong != 0) {
826 __ stf(FloatRegisterImpl::S, value->successor(), base, offset + BytesPerWord);
827 __ stf(FloatRegisterImpl::S, value , base, offset);
828 } else {
829 __ stf(w, value, base, offset);
830 }
831 } else {
832 __ set(offset, O7);
833 if (info != NULL) add_debug_info_for_null_check_here(info);
834 __ stf(w, value, O7, base);
835 }
836 }
837
838
839 int LIR_Assembler::store(LIR_Opr from_reg, Register base, int offset, BasicType type, bool unaligned) {
840 int store_offset;
841 if (!Assembler::is_simm13(offset + (type == T_LONG) ? wordSize : 0)) {
842 assert(!unaligned, "can't handle this");
843 // for offsets larger than a simm13 we setup the offset in O7
844 __ set(offset, O7);
845 store_offset = store(from_reg, base, O7, type);
846 } else {
847 if (type == T_ARRAY || type == T_OBJECT) __ verify_oop(from_reg->as_register());
848 store_offset = code_offset();
849 switch (type) {
850 case T_BOOLEAN: // fall through
851 case T_BYTE : __ stb(from_reg->as_register(), base, offset); break;
852 case T_CHAR : __ sth(from_reg->as_register(), base, offset); break;
853 case T_SHORT : __ sth(from_reg->as_register(), base, offset); break;
854 case T_INT : __ stw(from_reg->as_register(), base, offset); break;
855 case T_LONG :
856 #ifdef _LP64
857 if (unaligned || PatchALot) {
858 __ srax(from_reg->as_register_lo(), 32, O7);
859 __ stw(from_reg->as_register_lo(), base, offset + lo_word_offset_in_bytes);
860 __ stw(O7, base, offset + hi_word_offset_in_bytes);
861 } else {
862 __ stx(from_reg->as_register_lo(), base, offset);
863 }
864 #else
865 assert(Assembler::is_simm13(offset + 4), "must be");
866 __ stw(from_reg->as_register_lo(), base, offset + lo_word_offset_in_bytes);
867 __ stw(from_reg->as_register_hi(), base, offset + hi_word_offset_in_bytes);
868 #endif
869 break;
870 case T_ADDRESS:// fall through
871 case T_ARRAY : // fall through
872 case T_OBJECT: __ st_ptr(from_reg->as_register(), base, offset); break;
873 case T_FLOAT : __ stf(FloatRegisterImpl::S, from_reg->as_float_reg(), base, offset); break;
874 case T_DOUBLE:
875 {
876 FloatRegister reg = from_reg->as_double_reg();
877 // split unaligned stores
878 if (unaligned || PatchALot) {
879 assert(Assembler::is_simm13(offset + 4), "must be");
880 __ stf(FloatRegisterImpl::S, reg->successor(), base, offset + 4);
881 __ stf(FloatRegisterImpl::S, reg, base, offset);
882 } else {
883 __ stf(FloatRegisterImpl::D, reg, base, offset);
884 }
885 break;
886 }
887 default : ShouldNotReachHere();
888 }
889 }
890 return store_offset;
891 }
892
893
894 int LIR_Assembler::store(LIR_Opr from_reg, Register base, Register disp, BasicType type) {
895 if (type == T_ARRAY || type == T_OBJECT) __ verify_oop(from_reg->as_register());
896 int store_offset = code_offset();
897 switch (type) {
898 case T_BOOLEAN: // fall through
899 case T_BYTE : __ stb(from_reg->as_register(), base, disp); break;
900 case T_CHAR : __ sth(from_reg->as_register(), base, disp); break;
901 case T_SHORT : __ sth(from_reg->as_register(), base, disp); break;
902 case T_INT : __ stw(from_reg->as_register(), base, disp); break;
903 case T_LONG :
904 #ifdef _LP64
905 __ stx(from_reg->as_register_lo(), base, disp);
906 #else
907 assert(from_reg->as_register_hi()->successor() == from_reg->as_register_lo(), "must match");
908 __ std(from_reg->as_register_hi(), base, disp);
909 #endif
910 break;
911 case T_ADDRESS:// fall through
912 case T_ARRAY : // fall through
913 case T_OBJECT: __ st_ptr(from_reg->as_register(), base, disp); break;
914 case T_FLOAT : __ stf(FloatRegisterImpl::S, from_reg->as_float_reg(), base, disp); break;
915 case T_DOUBLE: __ stf(FloatRegisterImpl::D, from_reg->as_double_reg(), base, disp); break;
916 default : ShouldNotReachHere();
917 }
918 return store_offset;
919 }
920
921
922 int LIR_Assembler::load(Register base, int offset, LIR_Opr to_reg, BasicType type, bool unaligned) {
923 int load_offset;
924 if (!Assembler::is_simm13(offset + (type == T_LONG) ? wordSize : 0)) {
925 assert(base != O7, "destroying register");
926 assert(!unaligned, "can't handle this");
927 // for offsets larger than a simm13 we setup the offset in O7
928 __ set(offset, O7);
929 load_offset = load(base, O7, to_reg, type);
930 } else {
931 load_offset = code_offset();
932 switch(type) {
933 case T_BOOLEAN: // fall through
934 case T_BYTE : __ ldsb(base, offset, to_reg->as_register()); break;
935 case T_CHAR : __ lduh(base, offset, to_reg->as_register()); break;
936 case T_SHORT : __ ldsh(base, offset, to_reg->as_register()); break;
937 case T_INT : __ ld(base, offset, to_reg->as_register()); break;
938 case T_LONG :
939 if (!unaligned) {
940 #ifdef _LP64
941 __ ldx(base, offset, to_reg->as_register_lo());
942 #else
943 assert(to_reg->as_register_hi()->successor() == to_reg->as_register_lo(),
944 "must be sequential");
945 __ ldd(base, offset, to_reg->as_register_hi());
946 #endif
947 } else {
948 #ifdef _LP64
949 assert(base != to_reg->as_register_lo(), "can't handle this");
950 assert(O7 != to_reg->as_register_lo(), "can't handle this");
951 __ ld(base, offset + hi_word_offset_in_bytes, to_reg->as_register_lo());
952 __ lduw(base, offset + lo_word_offset_in_bytes, O7); // in case O7 is base or offset, use it last
953 __ sllx(to_reg->as_register_lo(), 32, to_reg->as_register_lo());
954 __ or3(to_reg->as_register_lo(), O7, to_reg->as_register_lo());
955 #else
956 if (base == to_reg->as_register_lo()) {
957 __ ld(base, offset + hi_word_offset_in_bytes, to_reg->as_register_hi());
958 __ ld(base, offset + lo_word_offset_in_bytes, to_reg->as_register_lo());
959 } else {
960 __ ld(base, offset + lo_word_offset_in_bytes, to_reg->as_register_lo());
961 __ ld(base, offset + hi_word_offset_in_bytes, to_reg->as_register_hi());
962 }
963 #endif
964 }
965 break;
966 case T_ADDRESS:// fall through
967 case T_ARRAY : // fall through
968 case T_OBJECT: __ ld_ptr(base, offset, to_reg->as_register()); break;
969 case T_FLOAT: __ ldf(FloatRegisterImpl::S, base, offset, to_reg->as_float_reg()); break;
970 case T_DOUBLE:
971 {
972 FloatRegister reg = to_reg->as_double_reg();
973 // split unaligned loads
974 if (unaligned || PatchALot) {
975 __ ldf(FloatRegisterImpl::S, base, offset + 4, reg->successor());
976 __ ldf(FloatRegisterImpl::S, base, offset, reg);
977 } else {
978 __ ldf(FloatRegisterImpl::D, base, offset, to_reg->as_double_reg());
979 }
980 break;
981 }
982 default : ShouldNotReachHere();
983 }
984 if (type == T_ARRAY || type == T_OBJECT) __ verify_oop(to_reg->as_register());
985 }
986 return load_offset;
987 }
988
989
990 int LIR_Assembler::load(Register base, Register disp, LIR_Opr to_reg, BasicType type) {
991 int load_offset = code_offset();
992 switch(type) {
993 case T_BOOLEAN: // fall through
994 case T_BYTE : __ ldsb(base, disp, to_reg->as_register()); break;
995 case T_CHAR : __ lduh(base, disp, to_reg->as_register()); break;
996 case T_SHORT : __ ldsh(base, disp, to_reg->as_register()); break;
997 case T_INT : __ ld(base, disp, to_reg->as_register()); break;
998 case T_ADDRESS:// fall through
999 case T_ARRAY : // fall through
1000 case T_OBJECT: __ ld_ptr(base, disp, to_reg->as_register()); break;
1001 case T_FLOAT: __ ldf(FloatRegisterImpl::S, base, disp, to_reg->as_float_reg()); break;
1002 case T_DOUBLE: __ ldf(FloatRegisterImpl::D, base, disp, to_reg->as_double_reg()); break;
1003 case T_LONG :
1004 #ifdef _LP64
1005 __ ldx(base, disp, to_reg->as_register_lo());
1006 #else
1007 assert(to_reg->as_register_hi()->successor() == to_reg->as_register_lo(),
1008 "must be sequential");
1009 __ ldd(base, disp, to_reg->as_register_hi());
1010 #endif
1011 break;
1012 default : ShouldNotReachHere();
1013 }
1014 if (type == T_ARRAY || type == T_OBJECT) __ verify_oop(to_reg->as_register());
1015 return load_offset;
1016 }
1017
1018
1019 // load/store with an Address
1020 void LIR_Assembler::load(const Address& a, Register d, BasicType ld_type, CodeEmitInfo *info, int offset) {
1021 load(a.base(), a.disp() + offset, d, ld_type, info);
1022 }
1023
1024
1025 void LIR_Assembler::store(Register value, const Address& dest, BasicType type, CodeEmitInfo *info, int offset) {
1026 store(value, dest.base(), dest.disp() + offset, type, info);
1027 }
1028
1029
1030 // loadf/storef with an Address
1031 void LIR_Assembler::load(const Address& a, FloatRegister d, BasicType ld_type, CodeEmitInfo *info, int offset) {
1032 load(a.base(), a.disp() + offset, d, ld_type, info);
1033 }
1034
1035
1036 void LIR_Assembler::store(FloatRegister value, const Address& dest, BasicType type, CodeEmitInfo *info, int offset) {
1037 store(value, dest.base(), dest.disp() + offset, type, info);
1038 }
1039
1040
1041 // load/store with an Address
1042 void LIR_Assembler::load(LIR_Address* a, Register d, BasicType ld_type, CodeEmitInfo *info) {
1043 load(as_Address(a), d, ld_type, info);
1044 }
1045
1046
1047 void LIR_Assembler::store(Register value, LIR_Address* dest, BasicType type, CodeEmitInfo *info) {
1048 store(value, as_Address(dest), type, info);
1049 }
1050
1051
1052 // loadf/storef with an Address
1053 void LIR_Assembler::load(LIR_Address* a, FloatRegister d, BasicType ld_type, CodeEmitInfo *info) {
1054 load(as_Address(a), d, ld_type, info);
1055 }
1056
1057
1058 void LIR_Assembler::store(FloatRegister value, LIR_Address* dest, BasicType type, CodeEmitInfo *info) {
1059 store(value, as_Address(dest), type, info);
1060 }
1061
1062
1063 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
1064 LIR_Const* c = src->as_constant_ptr();
1065 switch (c->type()) {
1066 case T_INT:
1067 case T_FLOAT:
1068 case T_ADDRESS: {
1069 Register src_reg = O7;
1070 int value = c->as_jint_bits();
1071 if (value == 0) {
1072 src_reg = G0;
1073 } else {
1074 __ set(value, O7);
1075 }
1076 Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
1077 __ stw(src_reg, addr.base(), addr.disp());
1078 break;
1079 }
1080 case T_OBJECT: {
1081 Register src_reg = O7;
1082 jobject2reg(c->as_jobject(), src_reg);
1083 Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
1084 __ st_ptr(src_reg, addr.base(), addr.disp());
1085 break;
1086 }
1087 case T_LONG:
1088 case T_DOUBLE: {
1089 Address addr = frame_map()->address_for_double_slot(dest->double_stack_ix());
1090
1091 Register tmp = O7;
1092 int value_lo = c->as_jint_lo_bits();
1093 if (value_lo == 0) {
1094 tmp = G0;
1095 } else {
1096 __ set(value_lo, O7);
1097 }
1098 __ stw(tmp, addr.base(), addr.disp() + lo_word_offset_in_bytes);
1099 int value_hi = c->as_jint_hi_bits();
1100 if (value_hi == 0) {
1101 tmp = G0;
1102 } else {
1103 __ set(value_hi, O7);
1104 }
1105 __ stw(tmp, addr.base(), addr.disp() + hi_word_offset_in_bytes);
1106 break;
1107 }
1108 default:
1109 Unimplemented();
1110 }
1111 }
1112
1113
1114 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info ) {
1115 LIR_Const* c = src->as_constant_ptr();
1116 LIR_Address* addr = dest->as_address_ptr();
1117 Register base = addr->base()->as_pointer_register();
1118
1119 if (info != NULL) {
1120 add_debug_info_for_null_check_here(info);
1121 }
1122 switch (c->type()) {
1123 case T_INT:
1124 case T_FLOAT:
1125 case T_ADDRESS: {
1126 LIR_Opr tmp = FrameMap::O7_opr;
1127 int value = c->as_jint_bits();
1128 if (value == 0) {
1129 tmp = FrameMap::G0_opr;
1130 } else if (Assembler::is_simm13(value)) {
1131 __ set(value, O7);
1132 }
1133 if (addr->index()->is_valid()) {
1134 assert(addr->disp() == 0, "must be zero");
1135 store(tmp, base, addr->index()->as_pointer_register(), type);
1136 } else {
1137 assert(Assembler::is_simm13(addr->disp()), "can't handle larger addresses");
1138 store(tmp, base, addr->disp(), type);
1139 }
1140 break;
1141 }
1142 case T_LONG:
1143 case T_DOUBLE: {
1144 assert(!addr->index()->is_valid(), "can't handle reg reg address here");
1145 assert(Assembler::is_simm13(addr->disp()) &&
1146 Assembler::is_simm13(addr->disp() + 4), "can't handle larger addresses");
1147
1148 Register tmp = O7;
1149 int value_lo = c->as_jint_lo_bits();
1150 if (value_lo == 0) {
1151 tmp = G0;
1152 } else {
1153 __ set(value_lo, O7);
1154 }
1155 store(tmp, base, addr->disp() + lo_word_offset_in_bytes, T_INT);
1156 int value_hi = c->as_jint_hi_bits();
1157 if (value_hi == 0) {
1158 tmp = G0;
1159 } else {
1160 __ set(value_hi, O7);
1161 }
1162 store(tmp, base, addr->disp() + hi_word_offset_in_bytes, T_INT);
1163 break;
1164 }
1165 case T_OBJECT: {
1166 jobject obj = c->as_jobject();
1167 LIR_Opr tmp;
1168 if (obj == NULL) {
1169 tmp = FrameMap::G0_opr;
1170 } else {
1171 tmp = FrameMap::O7_opr;
1172 jobject2reg(c->as_jobject(), O7);
1173 }
1174 // handle either reg+reg or reg+disp address
1175 if (addr->index()->is_valid()) {
1176 assert(addr->disp() == 0, "must be zero");
1177 store(tmp, base, addr->index()->as_pointer_register(), type);
1178 } else {
1179 assert(Assembler::is_simm13(addr->disp()), "can't handle larger addresses");
1180 store(tmp, base, addr->disp(), type);
1181 }
1182
1183 break;
1184 }
1185 default:
1186 Unimplemented();
1187 }
1188 }
1189
1190
1191 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
1192 LIR_Const* c = src->as_constant_ptr();
1193 LIR_Opr to_reg = dest;
1194
1195 switch (c->type()) {
1196 case T_INT:
1197 case T_ADDRESS:
1198 {
1199 jint con = c->as_jint();
1200 if (to_reg->is_single_cpu()) {
1201 assert(patch_code == lir_patch_none, "no patching handled here");
1202 __ set(con, to_reg->as_register());
1203 } else {
1204 ShouldNotReachHere();
1205 assert(to_reg->is_single_fpu(), "wrong register kind");
1206
1207 __ set(con, O7);
1208 Address temp_slot(SP, (frame::register_save_words * wordSize) + STACK_BIAS);
1209 __ st(O7, temp_slot);
1210 __ ldf(FloatRegisterImpl::S, temp_slot, to_reg->as_float_reg());
1211 }
1212 }
1213 break;
1214
1215 case T_LONG:
1216 {
1217 jlong con = c->as_jlong();
1218
1219 if (to_reg->is_double_cpu()) {
1220 #ifdef _LP64
1221 __ set(con, to_reg->as_register_lo());
1222 #else
1223 __ set(low(con), to_reg->as_register_lo());
1224 __ set(high(con), to_reg->as_register_hi());
1225 #endif
1226 #ifdef _LP64
1227 } else if (to_reg->is_single_cpu()) {
1228 __ set(con, to_reg->as_register());
1229 #endif
1230 } else {
1231 ShouldNotReachHere();
1232 assert(to_reg->is_double_fpu(), "wrong register kind");
1233 Address temp_slot_lo(SP, ((frame::register_save_words ) * wordSize) + STACK_BIAS);
1234 Address temp_slot_hi(SP, ((frame::register_save_words) * wordSize) + (longSize/2) + STACK_BIAS);
1235 __ set(low(con), O7);
1236 __ st(O7, temp_slot_lo);
1237 __ set(high(con), O7);
1238 __ st(O7, temp_slot_hi);
1239 __ ldf(FloatRegisterImpl::D, temp_slot_lo, to_reg->as_double_reg());
1240 }
1241 }
1242 break;
1243
1244 case T_OBJECT:
1245 {
1246 if (patch_code == lir_patch_none) {
1247 jobject2reg(c->as_jobject(), to_reg->as_register());
1248 } else {
1249 jobject2reg_with_patching(to_reg->as_register(), info);
1250 }
1251 }
1252 break;
1253
1254 case T_FLOAT:
1255 {
1256 address const_addr = __ float_constant(c->as_jfloat());
1257 if (const_addr == NULL) {
1258 bailout("const section overflow");
1259 break;
1260 }
1261 RelocationHolder rspec = internal_word_Relocation::spec(const_addr);
1262 AddressLiteral const_addrlit(const_addr, rspec);
1263 if (to_reg->is_single_fpu()) {
1264 __ patchable_sethi(const_addrlit, O7);
1265 __ relocate(rspec);
1266 __ ldf(FloatRegisterImpl::S, O7, const_addrlit.low10(), to_reg->as_float_reg());
1267
1268 } else {
1269 assert(to_reg->is_single_cpu(), "Must be a cpu register.");
1270
1271 __ set(const_addrlit, O7);
1272 load(O7, 0, to_reg->as_register(), T_INT);
1273 }
1274 }
1275 break;
1276
1277 case T_DOUBLE:
1278 {
1279 address const_addr = __ double_constant(c->as_jdouble());
1280 if (const_addr == NULL) {
1281 bailout("const section overflow");
1282 break;
1283 }
1284 RelocationHolder rspec = internal_word_Relocation::spec(const_addr);
1285
1286 if (to_reg->is_double_fpu()) {
1287 AddressLiteral const_addrlit(const_addr, rspec);
1288 __ patchable_sethi(const_addrlit, O7);
1289 __ relocate(rspec);
1290 __ ldf (FloatRegisterImpl::D, O7, const_addrlit.low10(), to_reg->as_double_reg());
1291 } else {
1292 assert(to_reg->is_double_cpu(), "Must be a long register.");
1293 #ifdef _LP64
1294 __ set(jlong_cast(c->as_jdouble()), to_reg->as_register_lo());
1295 #else
1296 __ set(low(jlong_cast(c->as_jdouble())), to_reg->as_register_lo());
1297 __ set(high(jlong_cast(c->as_jdouble())), to_reg->as_register_hi());
1298 #endif
1299 }
1300
1301 }
1302 break;
1303
1304 default:
1305 ShouldNotReachHere();
1306 }
1307 }
1308
1309 Address LIR_Assembler::as_Address(LIR_Address* addr) {
1310 Register reg = addr->base()->as_register();
1311 return Address(reg, addr->disp());
1312 }
1313
1314
1315 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
1316 switch (type) {
1317 case T_INT:
1318 case T_FLOAT: {
1319 Register tmp = O7;
1320 Address from = frame_map()->address_for_slot(src->single_stack_ix());
1321 Address to = frame_map()->address_for_slot(dest->single_stack_ix());
1322 __ lduw(from.base(), from.disp(), tmp);
1323 __ stw(tmp, to.base(), to.disp());
1324 break;
1325 }
1326 case T_OBJECT: {
1327 Register tmp = O7;
1328 Address from = frame_map()->address_for_slot(src->single_stack_ix());
1329 Address to = frame_map()->address_for_slot(dest->single_stack_ix());
1330 __ ld_ptr(from.base(), from.disp(), tmp);
1331 __ st_ptr(tmp, to.base(), to.disp());
1332 break;
1333 }
1334 case T_LONG:
1335 case T_DOUBLE: {
1336 Register tmp = O7;
1337 Address from = frame_map()->address_for_double_slot(src->double_stack_ix());
1338 Address to = frame_map()->address_for_double_slot(dest->double_stack_ix());
1339 __ lduw(from.base(), from.disp(), tmp);
1340 __ stw(tmp, to.base(), to.disp());
1341 __ lduw(from.base(), from.disp() + 4, tmp);
1342 __ stw(tmp, to.base(), to.disp() + 4);
1343 break;
1344 }
1345
1346 default:
1347 ShouldNotReachHere();
1348 }
1349 }
1350
1351
1352 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
1353 Address base = as_Address(addr);
1354 return Address(base.base(), base.disp() + hi_word_offset_in_bytes);
1355 }
1356
1357
1358 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
1359 Address base = as_Address(addr);
1360 return Address(base.base(), base.disp() + lo_word_offset_in_bytes);
1361 }
1362
1363
1364 void LIR_Assembler::mem2reg(LIR_Opr src_opr, LIR_Opr dest, BasicType type,
1365 LIR_PatchCode patch_code, CodeEmitInfo* info, bool unaligned) {
1366
1367 LIR_Address* addr = src_opr->as_address_ptr();
1368 LIR_Opr to_reg = dest;
1369
1370 Register src = addr->base()->as_pointer_register();
1371 Register disp_reg = noreg;
1372 int disp_value = addr->disp();
1373 bool needs_patching = (patch_code != lir_patch_none);
1374
1375 if (addr->base()->type() == T_OBJECT) {
1376 __ verify_oop(src);
1377 }
1378
1379 PatchingStub* patch = NULL;
1380 if (needs_patching) {
1381 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1382 assert(!to_reg->is_double_cpu() ||
1383 patch_code == lir_patch_none ||
1384 patch_code == lir_patch_normal, "patching doesn't match register");
1385 }
1386
1387 if (addr->index()->is_illegal()) {
1388 if (!Assembler::is_simm13(disp_value) && (!unaligned || Assembler::is_simm13(disp_value + 4))) {
1389 if (needs_patching) {
1390 __ patchable_set(0, O7);
1391 } else {
1392 __ set(disp_value, O7);
1393 }
1394 disp_reg = O7;
1395 }
1396 } else if (unaligned || PatchALot) {
1397 __ add(src, addr->index()->as_register(), O7);
1398 src = O7;
1399 } else {
1400 disp_reg = addr->index()->as_pointer_register();
1401 assert(disp_value == 0, "can't handle 3 operand addresses");
1402 }
1403
1404 // remember the offset of the load. The patching_epilog must be done
1405 // before the call to add_debug_info, otherwise the PcDescs don't get
1406 // entered in increasing order.
1407 int offset = code_offset();
1408
1409 assert(disp_reg != noreg || Assembler::is_simm13(disp_value), "should have set this up");
1410 if (disp_reg == noreg) {
1411 offset = load(src, disp_value, to_reg, type, unaligned);
1412 } else {
1413 assert(!unaligned, "can't handle this");
1414 offset = load(src, disp_reg, to_reg, type);
1415 }
1416
1417 if (patch != NULL) {
1418 patching_epilog(patch, patch_code, src, info);
1419 }
1420
1421 if (info != NULL) add_debug_info_for_null_check(offset, info);
1422 }
1423
1424
1425 void LIR_Assembler::prefetchr(LIR_Opr src) {
1426 LIR_Address* addr = src->as_address_ptr();
1427 Address from_addr = as_Address(addr);
1428
1429 if (VM_Version::has_v9()) {
1430 __ prefetch(from_addr, Assembler::severalReads);
1431 }
1432 }
1433
1434
1435 void LIR_Assembler::prefetchw(LIR_Opr src) {
1436 LIR_Address* addr = src->as_address_ptr();
1437 Address from_addr = as_Address(addr);
1438
1439 if (VM_Version::has_v9()) {
1440 __ prefetch(from_addr, Assembler::severalWritesAndPossiblyReads);
1441 }
1442 }
1443
1444
1445 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
1446 Address addr;
1447 if (src->is_single_word()) {
1448 addr = frame_map()->address_for_slot(src->single_stack_ix());
1449 } else if (src->is_double_word()) {
1450 addr = frame_map()->address_for_double_slot(src->double_stack_ix());
1451 }
1452
1453 bool unaligned = (addr.disp() - STACK_BIAS) % 8 != 0;
1454 load(addr.base(), addr.disp(), dest, dest->type(), unaligned);
1455 }
1456
1457
1458 void LIR_Assembler::reg2stack(LIR_Opr from_reg, LIR_Opr dest, BasicType type, bool pop_fpu_stack) {
1459 Address addr;
1460 if (dest->is_single_word()) {
1461 addr = frame_map()->address_for_slot(dest->single_stack_ix());
1462 } else if (dest->is_double_word()) {
1463 addr = frame_map()->address_for_slot(dest->double_stack_ix());
1464 }
1465 bool unaligned = (addr.disp() - STACK_BIAS) % 8 != 0;
1466 store(from_reg, addr.base(), addr.disp(), from_reg->type(), unaligned);
1467 }
1468
1469
1470 void LIR_Assembler::reg2reg(LIR_Opr from_reg, LIR_Opr to_reg) {
1471 if (from_reg->is_float_kind() && to_reg->is_float_kind()) {
1472 if (from_reg->is_double_fpu()) {
1473 // double to double moves
1474 assert(to_reg->is_double_fpu(), "should match");
1475 __ fmov(FloatRegisterImpl::D, from_reg->as_double_reg(), to_reg->as_double_reg());
1476 } else {
1477 // float to float moves
1478 assert(to_reg->is_single_fpu(), "should match");
1479 __ fmov(FloatRegisterImpl::S, from_reg->as_float_reg(), to_reg->as_float_reg());
1480 }
1481 } else if (!from_reg->is_float_kind() && !to_reg->is_float_kind()) {
1482 if (from_reg->is_double_cpu()) {
1483 #ifdef _LP64
1484 __ mov(from_reg->as_pointer_register(), to_reg->as_pointer_register());
1485 #else
1486 assert(to_reg->is_double_cpu() &&
1487 from_reg->as_register_hi() != to_reg->as_register_lo() &&
1488 from_reg->as_register_lo() != to_reg->as_register_hi(),
1489 "should both be long and not overlap");
1490 // long to long moves
1491 __ mov(from_reg->as_register_hi(), to_reg->as_register_hi());
1492 __ mov(from_reg->as_register_lo(), to_reg->as_register_lo());
1493 #endif
1494 #ifdef _LP64
1495 } else if (to_reg->is_double_cpu()) {
1496 // int to int moves
1497 __ mov(from_reg->as_register(), to_reg->as_register_lo());
1498 #endif
1499 } else {
1500 // int to int moves
1501 __ mov(from_reg->as_register(), to_reg->as_register());
1502 }
1503 } else {
1504 ShouldNotReachHere();
1505 }
1506 if (to_reg->type() == T_OBJECT || to_reg->type() == T_ARRAY) {
1507 __ verify_oop(to_reg->as_register());
1508 }
1509 }
1510
1511
1512 void LIR_Assembler::reg2mem(LIR_Opr from_reg, LIR_Opr dest, BasicType type,
1513 LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack,
1514 bool unaligned) {
1515 LIR_Address* addr = dest->as_address_ptr();
1516
1517 Register src = addr->base()->as_pointer_register();
1518 Register disp_reg = noreg;
1519 int disp_value = addr->disp();
1520 bool needs_patching = (patch_code != lir_patch_none);
1521
1522 if (addr->base()->is_oop_register()) {
1523 __ verify_oop(src);
1524 }
1525
1526 PatchingStub* patch = NULL;
1527 if (needs_patching) {
1528 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1529 assert(!from_reg->is_double_cpu() ||
1530 patch_code == lir_patch_none ||
1531 patch_code == lir_patch_normal, "patching doesn't match register");
1532 }
1533
1534 if (addr->index()->is_illegal()) {
1535 if (!Assembler::is_simm13(disp_value) && (!unaligned || Assembler::is_simm13(disp_value + 4))) {
1536 if (needs_patching) {
1537 __ patchable_set(0, O7);
1538 } else {
1539 __ set(disp_value, O7);
1540 }
1541 disp_reg = O7;
1542 }
1543 } else if (unaligned || PatchALot) {
1544 __ add(src, addr->index()->as_register(), O7);
1545 src = O7;
1546 } else {
1547 disp_reg = addr->index()->as_pointer_register();
1548 assert(disp_value == 0, "can't handle 3 operand addresses");
1549 }
1550
1551 // remember the offset of the store. The patching_epilog must be done
1552 // before the call to add_debug_info_for_null_check, otherwise the PcDescs don't get
1553 // entered in increasing order.
1554 int offset;
1555
1556 assert(disp_reg != noreg || Assembler::is_simm13(disp_value), "should have set this up");
1557 if (disp_reg == noreg) {
1558 offset = store(from_reg, src, disp_value, type, unaligned);
1559 } else {
1560 assert(!unaligned, "can't handle this");
1561 offset = store(from_reg, src, disp_reg, type);
1562 }
1563
1564 if (patch != NULL) {
1565 patching_epilog(patch, patch_code, src, info);
1566 }
1567
1568 if (info != NULL) add_debug_info_for_null_check(offset, info);
1569 }
1570
1571
1572 void LIR_Assembler::return_op(LIR_Opr result) {
1573 // the poll may need a register so just pick one that isn't the return register
1574 #ifdef TIERED
1575 if (result->type_field() == LIR_OprDesc::long_type) {
1576 // Must move the result to G1
1577 // Must leave proper result in O0,O1 and G1 (TIERED only)
1578 __ sllx(I0, 32, G1); // Shift bits into high G1
1579 __ srl (I1, 0, I1); // Zero extend O1 (harmless?)
1580 __ or3 (I1, G1, G1); // OR 64 bits into G1
1581 }
1582 #endif // TIERED
1583 __ set((intptr_t)os::get_polling_page(), L0);
1584 __ relocate(relocInfo::poll_return_type);
1585 __ ld_ptr(L0, 0, G0);
1586 __ ret();
1587 __ delayed()->restore();
1588 }
1589
1590
1591 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
1592 __ set((intptr_t)os::get_polling_page(), tmp->as_register());
1593 if (info != NULL) {
1594 add_debug_info_for_branch(info);
1595 } else {
1596 __ relocate(relocInfo::poll_type);
1597 }
1598
1599 int offset = __ offset();
1600 __ ld_ptr(tmp->as_register(), 0, G0);
1601
1602 return offset;
1603 }
1604
1605
1606 void LIR_Assembler::emit_static_call_stub() {
1607 address call_pc = __ pc();
1608 address stub = __ start_a_stub(call_stub_size);
1609 if (stub == NULL) {
1610 bailout("static call stub overflow");
1611 return;
1612 }
1613
1614 int start = __ offset();
1615 __ relocate(static_stub_Relocation::spec(call_pc));
1616
1617 __ set_oop(NULL, G5);
1618 // must be set to -1 at code generation time
1619 AddressLiteral addrlit(-1);
1620 __ jump_to(addrlit, G3);
1621 __ delayed()->nop();
1622
1623 assert(__ offset() - start <= call_stub_size, "stub too big");
1624 __ end_a_stub();
1625 }
1626
1627
1628 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
1629 if (opr1->is_single_fpu()) {
1630 __ fcmp(FloatRegisterImpl::S, Assembler::fcc0, opr1->as_float_reg(), opr2->as_float_reg());
1631 } else if (opr1->is_double_fpu()) {
1632 __ fcmp(FloatRegisterImpl::D, Assembler::fcc0, opr1->as_double_reg(), opr2->as_double_reg());
1633 } else if (opr1->is_single_cpu()) {
1634 if (opr2->is_constant()) {
1635 switch (opr2->as_constant_ptr()->type()) {
1636 case T_INT:
1637 { jint con = opr2->as_constant_ptr()->as_jint();
1638 if (Assembler::is_simm13(con)) {
1639 __ cmp(opr1->as_register(), con);
1640 } else {
1641 __ set(con, O7);
1642 __ cmp(opr1->as_register(), O7);
1643 }
1644 }
1645 break;
1646
1647 case T_OBJECT:
1648 // there are only equal/notequal comparisions on objects
1649 { jobject con = opr2->as_constant_ptr()->as_jobject();
1650 if (con == NULL) {
1651 __ cmp(opr1->as_register(), 0);
1652 } else {
1653 jobject2reg(con, O7);
1654 __ cmp(opr1->as_register(), O7);
1655 }
1656 }
1657 break;
1658
1659 default:
1660 ShouldNotReachHere();
1661 break;
1662 }
1663 } else {
1664 if (opr2->is_address()) {
1665 LIR_Address * addr = opr2->as_address_ptr();
1666 BasicType type = addr->type();
1667 if ( type == T_OBJECT ) __ ld_ptr(as_Address(addr), O7);
1668 else __ ld(as_Address(addr), O7);
1669 __ cmp(opr1->as_register(), O7);
1670 } else {
1671 __ cmp(opr1->as_register(), opr2->as_register());
1672 }
1673 }
1674 } else if (opr1->is_double_cpu()) {
1675 Register xlo = opr1->as_register_lo();
1676 Register xhi = opr1->as_register_hi();
1677 if (opr2->is_constant() && opr2->as_jlong() == 0) {
1678 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "only handles these cases");
1679 #ifdef _LP64
1680 __ orcc(xhi, G0, G0);
1681 #else
1682 __ orcc(xhi, xlo, G0);
1683 #endif
1684 } else if (opr2->is_register()) {
1685 Register ylo = opr2->as_register_lo();
1686 Register yhi = opr2->as_register_hi();
1687 #ifdef _LP64
1688 __ cmp(xlo, ylo);
1689 #else
1690 __ subcc(xlo, ylo, xlo);
1691 __ subccc(xhi, yhi, xhi);
1692 if (condition == lir_cond_equal || condition == lir_cond_notEqual) {
1693 __ orcc(xhi, xlo, G0);
1694 }
1695 #endif
1696 } else {
1697 ShouldNotReachHere();
1698 }
1699 } else if (opr1->is_address()) {
1700 LIR_Address * addr = opr1->as_address_ptr();
1701 BasicType type = addr->type();
1702 assert (opr2->is_constant(), "Checking");
1703 if ( type == T_OBJECT ) __ ld_ptr(as_Address(addr), O7);
1704 else __ ld(as_Address(addr), O7);
1705 __ cmp(O7, opr2->as_constant_ptr()->as_jint());
1706 } else {
1707 ShouldNotReachHere();
1708 }
1709 }
1710
1711
1712 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op){
1713 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
1714 bool is_unordered_less = (code == lir_ucmp_fd2i);
1715 if (left->is_single_fpu()) {
1716 __ float_cmp(true, is_unordered_less ? -1 : 1, left->as_float_reg(), right->as_float_reg(), dst->as_register());
1717 } else if (left->is_double_fpu()) {
1718 __ float_cmp(false, is_unordered_less ? -1 : 1, left->as_double_reg(), right->as_double_reg(), dst->as_register());
1719 } else {
1720 ShouldNotReachHere();
1721 }
1722 } else if (code == lir_cmp_l2i) {
1723 #ifdef _LP64
1724 __ lcmp(left->as_register_lo(), right->as_register_lo(), dst->as_register());
1725 #else
1726 __ lcmp(left->as_register_hi(), left->as_register_lo(),
1727 right->as_register_hi(), right->as_register_lo(),
1728 dst->as_register());
1729 #endif
1730 } else {
1731 ShouldNotReachHere();
1732 }
1733 }
1734
1735
1736 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result) {
1737
1738 Assembler::Condition acond;
1739 switch (condition) {
1740 case lir_cond_equal: acond = Assembler::equal; break;
1741 case lir_cond_notEqual: acond = Assembler::notEqual; break;
1742 case lir_cond_less: acond = Assembler::less; break;
1743 case lir_cond_lessEqual: acond = Assembler::lessEqual; break;
1744 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; break;
1745 case lir_cond_greater: acond = Assembler::greater; break;
1746 case lir_cond_aboveEqual: acond = Assembler::greaterEqualUnsigned; break;
1747 case lir_cond_belowEqual: acond = Assembler::lessEqualUnsigned; break;
1748 default: ShouldNotReachHere();
1749 };
1750
1751 if (opr1->is_constant() && opr1->type() == T_INT) {
1752 Register dest = result->as_register();
1753 // load up first part of constant before branch
1754 // and do the rest in the delay slot.
1755 if (!Assembler::is_simm13(opr1->as_jint())) {
1756 __ sethi(opr1->as_jint(), dest);
1757 }
1758 } else if (opr1->is_constant()) {
1759 const2reg(opr1, result, lir_patch_none, NULL);
1760 } else if (opr1->is_register()) {
1761 reg2reg(opr1, result);
1762 } else if (opr1->is_stack()) {
1763 stack2reg(opr1, result, result->type());
1764 } else {
1765 ShouldNotReachHere();
1766 }
1767 Label skip;
1768 __ br(acond, false, Assembler::pt, skip);
1769 if (opr1->is_constant() && opr1->type() == T_INT) {
1770 Register dest = result->as_register();
1771 if (Assembler::is_simm13(opr1->as_jint())) {
1772 __ delayed()->or3(G0, opr1->as_jint(), dest);
1773 } else {
1774 // the sethi has been done above, so just put in the low 10 bits
1775 __ delayed()->or3(dest, opr1->as_jint() & 0x3ff, dest);
1776 }
1777 } else {
1778 // can't do anything useful in the delay slot
1779 __ delayed()->nop();
1780 }
1781 if (opr2->is_constant()) {
1782 const2reg(opr2, result, lir_patch_none, NULL);
1783 } else if (opr2->is_register()) {
1784 reg2reg(opr2, result);
1785 } else if (opr2->is_stack()) {
1786 stack2reg(opr2, result, result->type());
1787 } else {
1788 ShouldNotReachHere();
1789 }
1790 __ bind(skip);
1791 }
1792
1793
1794 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) {
1795 assert(info == NULL, "unused on this code path");
1796 assert(left->is_register(), "wrong items state");
1797 assert(dest->is_register(), "wrong items state");
1798
1799 if (right->is_register()) {
1800 if (dest->is_float_kind()) {
1801
1802 FloatRegister lreg, rreg, res;
1803 FloatRegisterImpl::Width w;
1804 if (right->is_single_fpu()) {
1805 w = FloatRegisterImpl::S;
1806 lreg = left->as_float_reg();
1807 rreg = right->as_float_reg();
1808 res = dest->as_float_reg();
1809 } else {
1810 w = FloatRegisterImpl::D;
1811 lreg = left->as_double_reg();
1812 rreg = right->as_double_reg();
1813 res = dest->as_double_reg();
1814 }
1815
1816 switch (code) {
1817 case lir_add: __ fadd(w, lreg, rreg, res); break;
1818 case lir_sub: __ fsub(w, lreg, rreg, res); break;
1819 case lir_mul: // fall through
1820 case lir_mul_strictfp: __ fmul(w, lreg, rreg, res); break;
1821 case lir_div: // fall through
1822 case lir_div_strictfp: __ fdiv(w, lreg, rreg, res); break;
1823 default: ShouldNotReachHere();
1824 }
1825
1826 } else if (dest->is_double_cpu()) {
1827 #ifdef _LP64
1828 Register dst_lo = dest->as_register_lo();
1829 Register op1_lo = left->as_pointer_register();
1830 Register op2_lo = right->as_pointer_register();
1831
1832 switch (code) {
1833 case lir_add:
1834 __ add(op1_lo, op2_lo, dst_lo);
1835 break;
1836
1837 case lir_sub:
1838 __ sub(op1_lo, op2_lo, dst_lo);
1839 break;
1840
1841 default: ShouldNotReachHere();
1842 }
1843 #else
1844 Register op1_lo = left->as_register_lo();
1845 Register op1_hi = left->as_register_hi();
1846 Register op2_lo = right->as_register_lo();
1847 Register op2_hi = right->as_register_hi();
1848 Register dst_lo = dest->as_register_lo();
1849 Register dst_hi = dest->as_register_hi();
1850
1851 switch (code) {
1852 case lir_add:
1853 __ addcc(op1_lo, op2_lo, dst_lo);
1854 __ addc (op1_hi, op2_hi, dst_hi);
1855 break;
1856
1857 case lir_sub:
1858 __ subcc(op1_lo, op2_lo, dst_lo);
1859 __ subc (op1_hi, op2_hi, dst_hi);
1860 break;
1861
1862 default: ShouldNotReachHere();
1863 }
1864 #endif
1865 } else {
1866 assert (right->is_single_cpu(), "Just Checking");
1867
1868 Register lreg = left->as_register();
1869 Register res = dest->as_register();
1870 Register rreg = right->as_register();
1871 switch (code) {
1872 case lir_add: __ add (lreg, rreg, res); break;
1873 case lir_sub: __ sub (lreg, rreg, res); break;
1874 case lir_mul: __ mult (lreg, rreg, res); break;
1875 default: ShouldNotReachHere();
1876 }
1877 }
1878 } else {
1879 assert (right->is_constant(), "must be constant");
1880
1881 if (dest->is_single_cpu()) {
1882 Register lreg = left->as_register();
1883 Register res = dest->as_register();
1884 int simm13 = right->as_constant_ptr()->as_jint();
1885
1886 switch (code) {
1887 case lir_add: __ add (lreg, simm13, res); break;
1888 case lir_sub: __ sub (lreg, simm13, res); break;
1889 case lir_mul: __ mult (lreg, simm13, res); break;
1890 default: ShouldNotReachHere();
1891 }
1892 } else {
1893 Register lreg = left->as_pointer_register();
1894 Register res = dest->as_register_lo();
1895 long con = right->as_constant_ptr()->as_jlong();
1896 assert(Assembler::is_simm13(con), "must be simm13");
1897
1898 switch (code) {
1899 case lir_add: __ add (lreg, (int)con, res); break;
1900 case lir_sub: __ sub (lreg, (int)con, res); break;
1901 case lir_mul: __ mult (lreg, (int)con, res); break;
1902 default: ShouldNotReachHere();
1903 }
1904 }
1905 }
1906 }
1907
1908
1909 void LIR_Assembler::fpop() {
1910 // do nothing
1911 }
1912
1913
1914 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr thread, LIR_Opr dest, LIR_Op* op) {
1915 switch (code) {
1916 case lir_sin:
1917 case lir_tan:
1918 case lir_cos: {
1919 assert(thread->is_valid(), "preserve the thread object for performance reasons");
1920 assert(dest->as_double_reg() == F0, "the result will be in f0/f1");
1921 break;
1922 }
1923 case lir_sqrt: {
1924 assert(!thread->is_valid(), "there is no need for a thread_reg for dsqrt");
1925 FloatRegister src_reg = value->as_double_reg();
1926 FloatRegister dst_reg = dest->as_double_reg();
1927 __ fsqrt(FloatRegisterImpl::D, src_reg, dst_reg);
1928 break;
1929 }
1930 case lir_abs: {
1931 assert(!thread->is_valid(), "there is no need for a thread_reg for fabs");
1932 FloatRegister src_reg = value->as_double_reg();
1933 FloatRegister dst_reg = dest->as_double_reg();
1934 __ fabs(FloatRegisterImpl::D, src_reg, dst_reg);
1935 break;
1936 }
1937 default: {
1938 ShouldNotReachHere();
1939 break;
1940 }
1941 }
1942 }
1943
1944
1945 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest) {
1946 if (right->is_constant()) {
1947 if (dest->is_single_cpu()) {
1948 int simm13 = right->as_constant_ptr()->as_jint();
1949 switch (code) {
1950 case lir_logic_and: __ and3 (left->as_register(), simm13, dest->as_register()); break;
1951 case lir_logic_or: __ or3 (left->as_register(), simm13, dest->as_register()); break;
1952 case lir_logic_xor: __ xor3 (left->as_register(), simm13, dest->as_register()); break;
1953 default: ShouldNotReachHere();
1954 }
1955 } else {
1956 long c = right->as_constant_ptr()->as_jlong();
1957 assert(c == (int)c && Assembler::is_simm13(c), "out of range");
1958 int simm13 = (int)c;
1959 switch (code) {
1960 case lir_logic_and:
1961 #ifndef _LP64
1962 __ and3 (left->as_register_hi(), 0, dest->as_register_hi());
1963 #endif
1964 __ and3 (left->as_register_lo(), simm13, dest->as_register_lo());
1965 break;
1966
1967 case lir_logic_or:
1968 #ifndef _LP64
1969 __ or3 (left->as_register_hi(), 0, dest->as_register_hi());
1970 #endif
1971 __ or3 (left->as_register_lo(), simm13, dest->as_register_lo());
1972 break;
1973
1974 case lir_logic_xor:
1975 #ifndef _LP64
1976 __ xor3 (left->as_register_hi(), 0, dest->as_register_hi());
1977 #endif
1978 __ xor3 (left->as_register_lo(), simm13, dest->as_register_lo());
1979 break;
1980
1981 default: ShouldNotReachHere();
1982 }
1983 }
1984 } else {
1985 assert(right->is_register(), "right should be in register");
1986
1987 if (dest->is_single_cpu()) {
1988 switch (code) {
1989 case lir_logic_and: __ and3 (left->as_register(), right->as_register(), dest->as_register()); break;
1990 case lir_logic_or: __ or3 (left->as_register(), right->as_register(), dest->as_register()); break;
1991 case lir_logic_xor: __ xor3 (left->as_register(), right->as_register(), dest->as_register()); break;
1992 default: ShouldNotReachHere();
1993 }
1994 } else {
1995 #ifdef _LP64
1996 Register l = (left->is_single_cpu() && left->is_oop_register()) ? left->as_register() :
1997 left->as_register_lo();
1998 Register r = (right->is_single_cpu() && right->is_oop_register()) ? right->as_register() :
1999 right->as_register_lo();
2000
2001 switch (code) {
2002 case lir_logic_and: __ and3 (l, r, dest->as_register_lo()); break;
2003 case lir_logic_or: __ or3 (l, r, dest->as_register_lo()); break;
2004 case lir_logic_xor: __ xor3 (l, r, dest->as_register_lo()); break;
2005 default: ShouldNotReachHere();
2006 }
2007 #else
2008 switch (code) {
2009 case lir_logic_and:
2010 __ and3 (left->as_register_hi(), right->as_register_hi(), dest->as_register_hi());
2011 __ and3 (left->as_register_lo(), right->as_register_lo(), dest->as_register_lo());
2012 break;
2013
2014 case lir_logic_or:
2015 __ or3 (left->as_register_hi(), right->as_register_hi(), dest->as_register_hi());
2016 __ or3 (left->as_register_lo(), right->as_register_lo(), dest->as_register_lo());
2017 break;
2018
2019 case lir_logic_xor:
2020 __ xor3 (left->as_register_hi(), right->as_register_hi(), dest->as_register_hi());
2021 __ xor3 (left->as_register_lo(), right->as_register_lo(), dest->as_register_lo());
2022 break;
2023
2024 default: ShouldNotReachHere();
2025 }
2026 #endif
2027 }
2028 }
2029 }
2030
2031
2032 int LIR_Assembler::shift_amount(BasicType t) {
2033 int elem_size = type2aelembytes(t);
2034 switch (elem_size) {
2035 case 1 : return 0;
2036 case 2 : return 1;
2037 case 4 : return 2;
2038 case 8 : return 3;
2039 }
2040 ShouldNotReachHere();
2041 return -1;
2042 }
2043
2044
2045 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info, bool unwind) {
2046 assert(exceptionOop->as_register() == Oexception, "should match");
2047 assert(unwind || exceptionPC->as_register() == Oissuing_pc, "should match");
2048
2049 info->add_register_oop(exceptionOop);
2050
2051 if (unwind) {
2052 __ call(Runtime1::entry_for(Runtime1::unwind_exception_id), relocInfo::runtime_call_type);
2053 __ delayed()->nop();
2054 } else {
2055 // reuse the debug info from the safepoint poll for the throw op itself
2056 address pc_for_athrow = __ pc();
2057 int pc_for_athrow_offset = __ offset();
2058 RelocationHolder rspec = internal_word_Relocation::spec(pc_for_athrow);
2059 __ set(pc_for_athrow, Oissuing_pc, rspec);
2060 add_call_info(pc_for_athrow_offset, info); // for exception handler
2061
2062 __ call(Runtime1::entry_for(Runtime1::handle_exception_id), relocInfo::runtime_call_type);
2063 __ delayed()->nop();
2064 }
2065 }
2066
2067
2068 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
2069 Register src = op->src()->as_register();
2070 Register dst = op->dst()->as_register();
2071 Register src_pos = op->src_pos()->as_register();
2072 Register dst_pos = op->dst_pos()->as_register();
2073 Register length = op->length()->as_register();
2074 Register tmp = op->tmp()->as_register();
2075 Register tmp2 = O7;
2076
2077 int flags = op->flags();
2078 ciArrayKlass* default_type = op->expected_type();
2079 BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL;
2080 if (basic_type == T_ARRAY) basic_type = T_OBJECT;
2081
2082 // set up the arraycopy stub information
2083 ArrayCopyStub* stub = op->stub();
2084
2085 // always do stub if no type information is available. it's ok if
2086 // the known type isn't loaded since the code sanity checks
2087 // in debug mode and the type isn't required when we know the exact type
2088 // also check that the type is an array type.
2089 // We also, for now, always call the stub if the barrier set requires a
2090 // write_ref_pre barrier (which the stub does, but none of the optimized
2091 // cases currently does).
2092 if (op->expected_type() == NULL ||
2093 Universe::heap()->barrier_set()->has_write_ref_pre_barrier()) {
2094 __ mov(src, O0);
2095 __ mov(src_pos, O1);
2096 __ mov(dst, O2);
2097 __ mov(dst_pos, O3);
2098 __ mov(length, O4);
2099 __ call_VM_leaf(tmp, CAST_FROM_FN_PTR(address, Runtime1::arraycopy));
2100
2101 __ br_zero(Assembler::less, false, Assembler::pn, O0, *stub->entry());
2102 __ delayed()->nop();
2103 __ bind(*stub->continuation());
2104 return;
2105 }
2106
2107 assert(default_type != NULL && default_type->is_array_klass(), "must be true at this point");
2108
2109 // make sure src and dst are non-null and load array length
2110 if (flags & LIR_OpArrayCopy::src_null_check) {
2111 __ tst(src);
2112 __ br(Assembler::equal, false, Assembler::pn, *stub->entry());
2113 __ delayed()->nop();
2114 }
2115
2116 if (flags & LIR_OpArrayCopy::dst_null_check) {
2117 __ tst(dst);
2118 __ br(Assembler::equal, false, Assembler::pn, *stub->entry());
2119 __ delayed()->nop();
2120 }
2121
2122 if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
2123 // test src_pos register
2124 __ tst(src_pos);
2125 __ br(Assembler::less, false, Assembler::pn, *stub->entry());
2126 __ delayed()->nop();
2127 }
2128
2129 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
2130 // test dst_pos register
2131 __ tst(dst_pos);
2132 __ br(Assembler::less, false, Assembler::pn, *stub->entry());
2133 __ delayed()->nop();
2134 }
2135
2136 if (flags & LIR_OpArrayCopy::length_positive_check) {
2137 // make sure length isn't negative
2138 __ tst(length);
2139 __ br(Assembler::less, false, Assembler::pn, *stub->entry());
2140 __ delayed()->nop();
2141 }
2142
2143 if (flags & LIR_OpArrayCopy::src_range_check) {
2144 __ ld(src, arrayOopDesc::length_offset_in_bytes(), tmp2);
2145 __ add(length, src_pos, tmp);
2146 __ cmp(tmp2, tmp);
2147 __ br(Assembler::carrySet, false, Assembler::pn, *stub->entry());
2148 __ delayed()->nop();
2149 }
2150
2151 if (flags & LIR_OpArrayCopy::dst_range_check) {
2152 __ ld(dst, arrayOopDesc::length_offset_in_bytes(), tmp2);
2153 __ add(length, dst_pos, tmp);
2154 __ cmp(tmp2, tmp);
2155 __ br(Assembler::carrySet, false, Assembler::pn, *stub->entry());
2156 __ delayed()->nop();
2157 }
2158
2159 if (flags & LIR_OpArrayCopy::type_check) {
2160 __ ld_ptr(src, oopDesc::klass_offset_in_bytes(), tmp);
2161 __ ld_ptr(dst, oopDesc::klass_offset_in_bytes(), tmp2);
2162 __ cmp(tmp, tmp2);
2163 __ br(Assembler::notEqual, false, Assembler::pt, *stub->entry());
2164 __ delayed()->nop();
2165 }
2166
2167 #ifdef ASSERT
2168 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
2169 // Sanity check the known type with the incoming class. For the
2170 // primitive case the types must match exactly with src.klass and
2171 // dst.klass each exactly matching the default type. For the
2172 // object array case, if no type check is needed then either the
2173 // dst type is exactly the expected type and the src type is a
2174 // subtype which we can't check or src is the same array as dst
2175 // but not necessarily exactly of type default_type.
2176 Label known_ok, halt;
2177 jobject2reg(op->expected_type()->constant_encoding(), tmp);
2178 __ ld_ptr(dst, oopDesc::klass_offset_in_bytes(), tmp2);
2179 if (basic_type != T_OBJECT) {
2180 __ cmp(tmp, tmp2);
2181 __ br(Assembler::notEqual, false, Assembler::pn, halt);
2182 __ delayed()->ld_ptr(src, oopDesc::klass_offset_in_bytes(), tmp2);
2183 __ cmp(tmp, tmp2);
2184 __ br(Assembler::equal, false, Assembler::pn, known_ok);
2185 __ delayed()->nop();
2186 } else {
2187 __ cmp(tmp, tmp2);
2188 __ br(Assembler::equal, false, Assembler::pn, known_ok);
2189 __ delayed()->cmp(src, dst);
2190 __ br(Assembler::equal, false, Assembler::pn, known_ok);
2191 __ delayed()->nop();
2192 }
2193 __ bind(halt);
2194 __ stop("incorrect type information in arraycopy");
2195 __ bind(known_ok);
2196 }
2197 #endif
2198
2199 int shift = shift_amount(basic_type);
2200
2201 Register src_ptr = O0;
2202 Register dst_ptr = O1;
2203 Register len = O2;
2204
2205 __ add(src, arrayOopDesc::base_offset_in_bytes(basic_type), src_ptr);
2206 LP64_ONLY(__ sra(src_pos, 0, src_pos);) //higher 32bits must be null
2207 if (shift == 0) {
2208 __ add(src_ptr, src_pos, src_ptr);
2209 } else {
2210 __ sll(src_pos, shift, tmp);
2211 __ add(src_ptr, tmp, src_ptr);
2212 }
2213
2214 __ add(dst, arrayOopDesc::base_offset_in_bytes(basic_type), dst_ptr);
2215 LP64_ONLY(__ sra(dst_pos, 0, dst_pos);) //higher 32bits must be null
2216 if (shift == 0) {
2217 __ add(dst_ptr, dst_pos, dst_ptr);
2218 } else {
2219 __ sll(dst_pos, shift, tmp);
2220 __ add(dst_ptr, tmp, dst_ptr);
2221 }
2222
2223 if (basic_type != T_OBJECT) {
2224 if (shift == 0) {
2225 __ mov(length, len);
2226 } else {
2227 __ sll(length, shift, len);
2228 }
2229 __ call_VM_leaf(tmp, CAST_FROM_FN_PTR(address, Runtime1::primitive_arraycopy));
2230 } else {
2231 // oop_arraycopy takes a length in number of elements, so don't scale it.
2232 __ mov(length, len);
2233 __ call_VM_leaf(tmp, CAST_FROM_FN_PTR(address, Runtime1::oop_arraycopy));
2234 }
2235
2236 __ bind(*stub->continuation());
2237 }
2238
2239
2240 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2241 if (dest->is_single_cpu()) {
2242 #ifdef _LP64
2243 if (left->type() == T_OBJECT) {
2244 switch (code) {
2245 case lir_shl: __ sllx (left->as_register(), count->as_register(), dest->as_register()); break;
2246 case lir_shr: __ srax (left->as_register(), count->as_register(), dest->as_register()); break;
2247 case lir_ushr: __ srl (left->as_register(), count->as_register(), dest->as_register()); break;
2248 default: ShouldNotReachHere();
2249 }
2250 } else
2251 #endif
2252 switch (code) {
2253 case lir_shl: __ sll (left->as_register(), count->as_register(), dest->as_register()); break;
2254 case lir_shr: __ sra (left->as_register(), count->as_register(), dest->as_register()); break;
2255 case lir_ushr: __ srl (left->as_register(), count->as_register(), dest->as_register()); break;
2256 default: ShouldNotReachHere();
2257 }
2258 } else {
2259 #ifdef _LP64
2260 switch (code) {
2261 case lir_shl: __ sllx (left->as_register_lo(), count->as_register(), dest->as_register_lo()); break;
2262 case lir_shr: __ srax (left->as_register_lo(), count->as_register(), dest->as_register_lo()); break;
2263 case lir_ushr: __ srlx (left->as_register_lo(), count->as_register(), dest->as_register_lo()); break;
2264 default: ShouldNotReachHere();
2265 }
2266 #else
2267 switch (code) {
2268 case lir_shl: __ lshl (left->as_register_hi(), left->as_register_lo(), count->as_register(), dest->as_register_hi(), dest->as_register_lo(), G3_scratch); break;
2269 case lir_shr: __ lshr (left->as_register_hi(), left->as_register_lo(), count->as_register(), dest->as_register_hi(), dest->as_register_lo(), G3_scratch); break;
2270 case lir_ushr: __ lushr (left->as_register_hi(), left->as_register_lo(), count->as_register(), dest->as_register_hi(), dest->as_register_lo(), G3_scratch); break;
2271 default: ShouldNotReachHere();
2272 }
2273 #endif
2274 }
2275 }
2276
2277
2278 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2279 #ifdef _LP64
2280 if (left->type() == T_OBJECT) {
2281 count = count & 63; // shouldn't shift by more than sizeof(intptr_t)
2282 Register l = left->as_register();
2283 Register d = dest->as_register_lo();
2284 switch (code) {
2285 case lir_shl: __ sllx (l, count, d); break;
2286 case lir_shr: __ srax (l, count, d); break;
2287 case lir_ushr: __ srlx (l, count, d); break;
2288 default: ShouldNotReachHere();
2289 }
2290 return;
2291 }
2292 #endif
2293
2294 if (dest->is_single_cpu()) {
2295 count = count & 0x1F; // Java spec
2296 switch (code) {
2297 case lir_shl: __ sll (left->as_register(), count, dest->as_register()); break;
2298 case lir_shr: __ sra (left->as_register(), count, dest->as_register()); break;
2299 case lir_ushr: __ srl (left->as_register(), count, dest->as_register()); break;
2300 default: ShouldNotReachHere();
2301 }
2302 } else if (dest->is_double_cpu()) {
2303 count = count & 63; // Java spec
2304 switch (code) {
2305 case lir_shl: __ sllx (left->as_pointer_register(), count, dest->as_pointer_register()); break;
2306 case lir_shr: __ srax (left->as_pointer_register(), count, dest->as_pointer_register()); break;
2307 case lir_ushr: __ srlx (left->as_pointer_register(), count, dest->as_pointer_register()); break;
2308 default: ShouldNotReachHere();
2309 }
2310 } else {
2311 ShouldNotReachHere();
2312 }
2313 }
2314
2315
2316 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
2317 assert(op->tmp1()->as_register() == G1 &&
2318 op->tmp2()->as_register() == G3 &&
2319 op->tmp3()->as_register() == G4 &&
2320 op->obj()->as_register() == O0 &&
2321 op->klass()->as_register() == G5, "must be");
2322 if (op->init_check()) {
2323 __ ld(op->klass()->as_register(),
2324 instanceKlass::init_state_offset_in_bytes() + sizeof(oopDesc),
2325 op->tmp1()->as_register());
2326 add_debug_info_for_null_check_here(op->stub()->info());
2327 __ cmp(op->tmp1()->as_register(), instanceKlass::fully_initialized);
2328 __ br(Assembler::notEqual, false, Assembler::pn, *op->stub()->entry());
2329 __ delayed()->nop();
2330 }
2331 __ allocate_object(op->obj()->as_register(),
2332 op->tmp1()->as_register(),
2333 op->tmp2()->as_register(),
2334 op->tmp3()->as_register(),
2335 op->header_size(),
2336 op->object_size(),
2337 op->klass()->as_register(),
2338 *op->stub()->entry());
2339 __ bind(*op->stub()->continuation());
2340 __ verify_oop(op->obj()->as_register());
2341 }
2342
2343
2344 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
2345 assert(op->tmp1()->as_register() == G1 &&
2346 op->tmp2()->as_register() == G3 &&
2347 op->tmp3()->as_register() == G4 &&
2348 op->tmp4()->as_register() == O1 &&
2349 op->klass()->as_register() == G5, "must be");
2350 if (UseSlowPath ||
2351 (!UseFastNewObjectArray && (op->type() == T_OBJECT || op->type() == T_ARRAY)) ||
2352 (!UseFastNewTypeArray && (op->type() != T_OBJECT && op->type() != T_ARRAY))) {
2353 __ br(Assembler::always, false, Assembler::pn, *op->stub()->entry());
2354 __ delayed()->nop();
2355 } else {
2356 __ allocate_array(op->obj()->as_register(),
2357 op->len()->as_register(),
2358 op->tmp1()->as_register(),
2359 op->tmp2()->as_register(),
2360 op->tmp3()->as_register(),
2361 arrayOopDesc::header_size(op->type()),
2362 type2aelembytes(op->type()),
2363 op->klass()->as_register(),
2364 *op->stub()->entry());
2365 }
2366 __ bind(*op->stub()->continuation());
2367 }
2368
2369
2370 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
2371 LIR_Code code = op->code();
2372 if (code == lir_store_check) {
2373 Register value = op->object()->as_register();
2374 Register array = op->array()->as_register();
2375 Register k_RInfo = op->tmp1()->as_register();
2376 Register klass_RInfo = op->tmp2()->as_register();
2377 Register Rtmp1 = op->tmp3()->as_register();
2378
2379 __ verify_oop(value);
2380
2381 CodeStub* stub = op->stub();
2382 Label done;
2383 __ cmp(value, 0);
2384 __ br(Assembler::equal, false, Assembler::pn, done);
2385 __ delayed()->nop();
2386 load(array, oopDesc::klass_offset_in_bytes(), k_RInfo, T_OBJECT, op->info_for_exception());
2387 load(value, oopDesc::klass_offset_in_bytes(), klass_RInfo, T_OBJECT, NULL);
2388
2389 // get instance klass
2390 load(k_RInfo, objArrayKlass::element_klass_offset_in_bytes() + sizeof(oopDesc), k_RInfo, T_OBJECT, NULL);
2391 // perform the fast part of the checking logic
2392 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, O7, &done, stub->entry(), NULL);
2393
2394 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
2395 assert(klass_RInfo == G3 && k_RInfo == G1, "incorrect call setup");
2396 __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type);
2397 __ delayed()->nop();
2398 __ cmp(G3, 0);
2399 __ br(Assembler::equal, false, Assembler::pn, *stub->entry());
2400 __ delayed()->nop();
2401 __ bind(done);
2402 } else if (op->code() == lir_checkcast) {
2403 // we always need a stub for the failure case.
2404 CodeStub* stub = op->stub();
2405 Register obj = op->object()->as_register();
2406 Register k_RInfo = op->tmp1()->as_register();
2407 Register klass_RInfo = op->tmp2()->as_register();
2408 Register dst = op->result_opr()->as_register();
2409 Register Rtmp1 = op->tmp3()->as_register();
2410 ciKlass* k = op->klass();
2411
2412 if (obj == k_RInfo) {
2413 k_RInfo = klass_RInfo;
2414 klass_RInfo = obj;
2415 }
2416 if (op->profiled_method() != NULL) {
2417 ciMethod* method = op->profiled_method();
2418 int bci = op->profiled_bci();
2419
2420 // We need two temporaries to perform this operation on SPARC,
2421 // so to keep things simple we perform a redundant test here
2422 Label profile_done;
2423 __ cmp(obj, 0);
2424 __ br(Assembler::notEqual, false, Assembler::pn, profile_done);
2425 __ delayed()->nop();
2426 // Object is null; update methodDataOop
2427 ciMethodData* md = method->method_data();
2428 if (md == NULL) {
2429 bailout("out of memory building methodDataOop");
2430 return;
2431 }
2432 ciProfileData* data = md->bci_to_data(bci);
2433 assert(data != NULL, "need data for checkcast");
2434 assert(data->is_BitData(), "need BitData for checkcast");
2435 Register mdo = k_RInfo;
2436 Register data_val = Rtmp1;
2437 jobject2reg(md->constant_encoding(), mdo);
2438
2439 int mdo_offset_bias = 0;
2440 if (!Assembler::is_simm13(md->byte_offset_of_slot(data, DataLayout::header_offset()) + data->size_in_bytes())) {
2441 // The offset is large so bias the mdo by the base of the slot so
2442 // that the ld can use simm13s to reference the slots of the data
2443 mdo_offset_bias = md->byte_offset_of_slot(data, DataLayout::header_offset());
2444 __ set(mdo_offset_bias, data_val);
2445 __ add(mdo, data_val, mdo);
2446 }
2447
2448
2449 Address flags_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias);
2450 __ ldub(flags_addr, data_val);
2451 __ or3(data_val, BitData::null_seen_byte_constant(), data_val);
2452 __ stb(data_val, flags_addr);
2453 __ bind(profile_done);
2454 }
2455
2456 Label done;
2457 // patching may screw with our temporaries on sparc,
2458 // so let's do it before loading the class
2459 if (k->is_loaded()) {
2460 jobject2reg(k->constant_encoding(), k_RInfo);
2461 } else {
2462 jobject2reg_with_patching(k_RInfo, op->info_for_patch());
2463 }
2464 assert(obj != k_RInfo, "must be different");
2465 __ cmp(obj, 0);
2466 __ br(Assembler::equal, false, Assembler::pn, done);
2467 __ delayed()->nop();
2468
2469 // get object class
2470 // not a safepoint as obj null check happens earlier
2471 load(obj, oopDesc::klass_offset_in_bytes(), klass_RInfo, T_OBJECT, NULL);
2472 if (op->fast_check()) {
2473 assert_different_registers(klass_RInfo, k_RInfo);
2474 __ cmp(k_RInfo, klass_RInfo);
2475 __ br(Assembler::notEqual, false, Assembler::pt, *stub->entry());
2476 __ delayed()->nop();
2477 __ bind(done);
2478 } else {
2479 bool need_slow_path = true;
2480 if (k->is_loaded()) {
2481 if (k->super_check_offset() != sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes())
2482 need_slow_path = false;
2483 // perform the fast part of the checking logic
2484 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, noreg,
2485 (need_slow_path ? &done : NULL),
2486 stub->entry(), NULL,
2487 RegisterOrConstant(k->super_check_offset()));
2488 } else {
2489 // perform the fast part of the checking logic
2490 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, O7,
2491 &done, stub->entry(), NULL);
2492 }
2493 if (need_slow_path) {
2494 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
2495 assert(klass_RInfo == G3 && k_RInfo == G1, "incorrect call setup");
2496 __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type);
2497 __ delayed()->nop();
2498 __ cmp(G3, 0);
2499 __ br(Assembler::equal, false, Assembler::pn, *stub->entry());
2500 __ delayed()->nop();
2501 }
2502 __ bind(done);
2503 }
2504 __ mov(obj, dst);
2505 } else if (code == lir_instanceof) {
2506 Register obj = op->object()->as_register();
2507 Register k_RInfo = op->tmp1()->as_register();
2508 Register klass_RInfo = op->tmp2()->as_register();
2509 Register dst = op->result_opr()->as_register();
2510 Register Rtmp1 = op->tmp3()->as_register();
2511 ciKlass* k = op->klass();
2512
2513 Label done;
2514 if (obj == k_RInfo) {
2515 k_RInfo = klass_RInfo;
2516 klass_RInfo = obj;
2517 }
2518 // patching may screw with our temporaries on sparc,
2519 // so let's do it before loading the class
2520 if (k->is_loaded()) {
2521 jobject2reg(k->constant_encoding(), k_RInfo);
2522 } else {
2523 jobject2reg_with_patching(k_RInfo, op->info_for_patch());
2524 }
2525 assert(obj != k_RInfo, "must be different");
2526 __ cmp(obj, 0);
2527 __ br(Assembler::equal, true, Assembler::pn, done);
2528 __ delayed()->set(0, dst);
2529
2530 // get object class
2531 // not a safepoint as obj null check happens earlier
2532 load(obj, oopDesc::klass_offset_in_bytes(), klass_RInfo, T_OBJECT, NULL);
2533 if (op->fast_check()) {
2534 __ cmp(k_RInfo, klass_RInfo);
2535 __ br(Assembler::equal, true, Assembler::pt, done);
2536 __ delayed()->set(1, dst);
2537 __ set(0, dst);
2538 __ bind(done);
2539 } else {
2540 bool need_slow_path = true;
2541 if (k->is_loaded()) {
2542 if (k->super_check_offset() != sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes())
2543 need_slow_path = false;
2544 // perform the fast part of the checking logic
2545 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, O7, noreg,
2546 (need_slow_path ? &done : NULL),
2547 (need_slow_path ? &done : NULL), NULL,
2548 RegisterOrConstant(k->super_check_offset()),
2549 dst);
2550 } else {
2551 assert(dst != klass_RInfo && dst != k_RInfo, "need 3 registers");
2552 // perform the fast part of the checking logic
2553 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, O7, dst,
2554 &done, &done, NULL,
2555 RegisterOrConstant(-1),
2556 dst);
2557 }
2558 if (need_slow_path) {
2559 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
2560 assert(klass_RInfo == G3 && k_RInfo == G1, "incorrect call setup");
2561 __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type);
2562 __ delayed()->nop();
2563 __ mov(G3, dst);
2564 }
2565 __ bind(done);
2566 }
2567 } else {
2568 ShouldNotReachHere();
2569 }
2570
2571 }
2572
2573
2574 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
2575 if (op->code() == lir_cas_long) {
2576 assert(VM_Version::supports_cx8(), "wrong machine");
2577 Register addr = op->addr()->as_pointer_register();
2578 Register cmp_value_lo = op->cmp_value()->as_register_lo();
2579 Register cmp_value_hi = op->cmp_value()->as_register_hi();
2580 Register new_value_lo = op->new_value()->as_register_lo();
2581 Register new_value_hi = op->new_value()->as_register_hi();
2582 Register t1 = op->tmp1()->as_register();
2583 Register t2 = op->tmp2()->as_register();
2584 #ifdef _LP64
2585 __ mov(cmp_value_lo, t1);
2586 __ mov(new_value_lo, t2);
2587 #else
2588 // move high and low halves of long values into single registers
2589 __ sllx(cmp_value_hi, 32, t1); // shift high half into temp reg
2590 __ srl(cmp_value_lo, 0, cmp_value_lo); // clear upper 32 bits of low half
2591 __ or3(t1, cmp_value_lo, t1); // t1 holds 64-bit compare value
2592 __ sllx(new_value_hi, 32, t2);
2593 __ srl(new_value_lo, 0, new_value_lo);
2594 __ or3(t2, new_value_lo, t2); // t2 holds 64-bit value to swap
2595 #endif
2596 // perform the compare and swap operation
2597 __ casx(addr, t1, t2);
2598 // generate condition code - if the swap succeeded, t2 ("new value" reg) was
2599 // overwritten with the original value in "addr" and will be equal to t1.
2600 __ cmp(t1, t2);
2601
2602 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj) {
2603 Register addr = op->addr()->as_pointer_register();
2604 Register cmp_value = op->cmp_value()->as_register();
2605 Register new_value = op->new_value()->as_register();
2606 Register t1 = op->tmp1()->as_register();
2607 Register t2 = op->tmp2()->as_register();
2608 __ mov(cmp_value, t1);
2609 __ mov(new_value, t2);
2610 #ifdef _LP64
2611 if (op->code() == lir_cas_obj) {
2612 __ casx(addr, t1, t2);
2613 } else
2614 #endif
2615 {
2616 __ cas(addr, t1, t2);
2617 }
2618 __ cmp(t1, t2);
2619 } else {
2620 Unimplemented();
2621 }
2622 }
2623
2624 void LIR_Assembler::set_24bit_FPU() {
2625 Unimplemented();
2626 }
2627
2628
2629 void LIR_Assembler::reset_FPU() {
2630 Unimplemented();
2631 }
2632
2633
2634 void LIR_Assembler::breakpoint() {
2635 __ breakpoint_trap();
2636 }
2637
2638
2639 void LIR_Assembler::push(LIR_Opr opr) {
2640 Unimplemented();
2641 }
2642
2643
2644 void LIR_Assembler::pop(LIR_Opr opr) {
2645 Unimplemented();
2646 }
2647
2648
2649 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst_opr) {
2650 Address mon_addr = frame_map()->address_for_monitor_lock(monitor_no);
2651 Register dst = dst_opr->as_register();
2652 Register reg = mon_addr.base();
2653 int offset = mon_addr.disp();
2654 // compute pointer to BasicLock
2655 if (mon_addr.is_simm13()) {
2656 __ add(reg, offset, dst);
2657 } else {
2658 __ set(offset, dst);
2659 __ add(dst, reg, dst);
2660 }
2661 }
2662
2663
2664 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
2665 Register obj = op->obj_opr()->as_register();
2666 Register hdr = op->hdr_opr()->as_register();
2667 Register lock = op->lock_opr()->as_register();
2668
2669 // obj may not be an oop
2670 if (op->code() == lir_lock) {
2671 MonitorEnterStub* stub = (MonitorEnterStub*)op->stub();
2672 if (UseFastLocking) {
2673 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2674 // add debug info for NullPointerException only if one is possible
2675 if (op->info() != NULL) {
2676 add_debug_info_for_null_check_here(op->info());
2677 }
2678 __ lock_object(hdr, obj, lock, op->scratch_opr()->as_register(), *op->stub()->entry());
2679 } else {
2680 // always do slow locking
2681 // note: the slow locking code could be inlined here, however if we use
2682 // slow locking, speed doesn't matter anyway and this solution is
2683 // simpler and requires less duplicated code - additionally, the
2684 // slow locking code is the same in either case which simplifies
2685 // debugging
2686 __ br(Assembler::always, false, Assembler::pt, *op->stub()->entry());
2687 __ delayed()->nop();
2688 }
2689 } else {
2690 assert (op->code() == lir_unlock, "Invalid code, expected lir_unlock");
2691 if (UseFastLocking) {
2692 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2693 __ unlock_object(hdr, obj, lock, *op->stub()->entry());
2694 } else {
2695 // always do slow unlocking
2696 // note: the slow unlocking code could be inlined here, however if we use
2697 // slow unlocking, speed doesn't matter anyway and this solution is
2698 // simpler and requires less duplicated code - additionally, the
2699 // slow unlocking code is the same in either case which simplifies
2700 // debugging
2701 __ br(Assembler::always, false, Assembler::pt, *op->stub()->entry());
2702 __ delayed()->nop();
2703 }
2704 }
2705 __ bind(*op->stub()->continuation());
2706 }
2707
2708
2709 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
2710 ciMethod* method = op->profiled_method();
2711 int bci = op->profiled_bci();
2712
2713 // Update counter for all call types
2714 ciMethodData* md = method->method_data();
2715 if (md == NULL) {
2716 bailout("out of memory building methodDataOop");
2717 return;
2718 }
2719 ciProfileData* data = md->bci_to_data(bci);
2720 assert(data->is_CounterData(), "need CounterData for calls");
2721 assert(op->mdo()->is_single_cpu(), "mdo must be allocated");
2722 assert(op->tmp1()->is_single_cpu(), "tmp1 must be allocated");
2723 Register mdo = op->mdo()->as_register();
2724 Register tmp1 = op->tmp1()->as_register();
2725 jobject2reg(md->constant_encoding(), mdo);
2726 int mdo_offset_bias = 0;
2727 if (!Assembler::is_simm13(md->byte_offset_of_slot(data, CounterData::count_offset()) +
2728 data->size_in_bytes())) {
2729 // The offset is large so bias the mdo by the base of the slot so
2730 // that the ld can use simm13s to reference the slots of the data
2731 mdo_offset_bias = md->byte_offset_of_slot(data, CounterData::count_offset());
2732 __ set(mdo_offset_bias, O7);
2733 __ add(mdo, O7, mdo);
2734 }
2735
2736 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias);
2737 Bytecodes::Code bc = method->java_code_at_bci(bci);
2738 // Perform additional virtual call profiling for invokevirtual and
2739 // invokeinterface bytecodes
2740 if ((bc == Bytecodes::_invokevirtual || bc == Bytecodes::_invokeinterface) &&
2741 Tier1ProfileVirtualCalls) {
2742 assert(op->recv()->is_single_cpu(), "recv must be allocated");
2743 Register recv = op->recv()->as_register();
2744 assert_different_registers(mdo, tmp1, recv);
2745 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
2746 ciKlass* known_klass = op->known_holder();
2747 if (Tier1OptimizeVirtualCallProfiling && known_klass != NULL) {
2748 // We know the type that will be seen at this call site; we can
2749 // statically update the methodDataOop rather than needing to do
2750 // dynamic tests on the receiver type
2751
2752 // NOTE: we should probably put a lock around this search to
2753 // avoid collisions by concurrent compilations
2754 ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
2755 uint i;
2756 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2757 ciKlass* receiver = vc_data->receiver(i);
2758 if (known_klass->equals(receiver)) {
2759 Address data_addr(mdo, md->byte_offset_of_slot(data,
2760 VirtualCallData::receiver_count_offset(i)) -
2761 mdo_offset_bias);
2762 __ lduw(data_addr, tmp1);
2763 __ add(tmp1, DataLayout::counter_increment, tmp1);
2764 __ stw(tmp1, data_addr);
2765 return;
2766 }
2767 }
2768
2769 // Receiver type not found in profile data; select an empty slot
2770
2771 // Note that this is less efficient than it should be because it
2772 // always does a write to the receiver part of the
2773 // VirtualCallData rather than just the first time
2774 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2775 ciKlass* receiver = vc_data->receiver(i);
2776 if (receiver == NULL) {
2777 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)) -
2778 mdo_offset_bias);
2779 jobject2reg(known_klass->constant_encoding(), tmp1);
2780 __ st_ptr(tmp1, recv_addr);
2781 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) -
2782 mdo_offset_bias);
2783 __ lduw(data_addr, tmp1);
2784 __ add(tmp1, DataLayout::counter_increment, tmp1);
2785 __ stw(tmp1, data_addr);
2786 return;
2787 }
2788 }
2789 } else {
2790 load(Address(recv, oopDesc::klass_offset_in_bytes()), recv, T_OBJECT);
2791 Label update_done;
2792 uint i;
2793 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2794 Label next_test;
2795 // See if the receiver is receiver[n].
2796 Address receiver_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)) -
2797 mdo_offset_bias);
2798 __ ld_ptr(receiver_addr, tmp1);
2799 __ verify_oop(tmp1);
2800 __ cmp(recv, tmp1);
2801 __ brx(Assembler::notEqual, false, Assembler::pt, next_test);
2802 __ delayed()->nop();
2803 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) -
2804 mdo_offset_bias);
2805 __ lduw(data_addr, tmp1);
2806 __ add(tmp1, DataLayout::counter_increment, tmp1);
2807 __ stw(tmp1, data_addr);
2808 __ br(Assembler::always, false, Assembler::pt, update_done);
2809 __ delayed()->nop();
2810 __ bind(next_test);
2811 }
2812
2813 // Didn't find receiver; find next empty slot and fill it in
2814 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2815 Label next_test;
2816 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)) -
2817 mdo_offset_bias);
2818 load(recv_addr, tmp1, T_OBJECT);
2819 __ tst(tmp1);
2820 __ brx(Assembler::notEqual, false, Assembler::pt, next_test);
2821 __ delayed()->nop();
2822 __ st_ptr(recv, recv_addr);
2823 __ set(DataLayout::counter_increment, tmp1);
2824 __ st_ptr(tmp1, mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) -
2825 mdo_offset_bias);
2826 __ br(Assembler::always, false, Assembler::pt, update_done);
2827 __ delayed()->nop();
2828 __ bind(next_test);
2829 }
2830 // Receiver did not match any saved receiver and there is no empty row for it.
2831 // Increment total counter to indicate polymorphic case.
2832 __ lduw(counter_addr, tmp1);
2833 __ add(tmp1, DataLayout::counter_increment, tmp1);
2834 __ stw(tmp1, counter_addr);
2835
2836 __ bind(update_done);
2837 }
2838 } else {
2839 // Static call
2840 __ lduw(counter_addr, tmp1);
2841 __ add(tmp1, DataLayout::counter_increment, tmp1);
2842 __ stw(tmp1, counter_addr);
2843 }
2844 }
2845
2846
2847 void LIR_Assembler::align_backward_branch_target() {
2848 __ align(OptoLoopAlignment);
2849 }
2850
2851
2852 void LIR_Assembler::emit_delay(LIR_OpDelay* op) {
2853 // make sure we are expecting a delay
2854 // this has the side effect of clearing the delay state
2855 // so we can use _masm instead of _masm->delayed() to do the
2856 // code generation.
2857 __ delayed();
2858
2859 // make sure we only emit one instruction
2860 int offset = code_offset();
2861 op->delay_op()->emit_code(this);
2862 #ifdef ASSERT
2863 if (code_offset() - offset != NativeInstruction::nop_instruction_size) {
2864 op->delay_op()->print();
2865 }
2866 assert(code_offset() - offset == NativeInstruction::nop_instruction_size,
2867 "only one instruction can go in a delay slot");
2868 #endif
2869
2870 // we may also be emitting the call info for the instruction
2871 // which we are the delay slot of.
2872 CodeEmitInfo* call_info = op->call_info();
2873 if (call_info) {
2874 add_call_info(code_offset(), call_info);
2875 }
2876
2877 if (VerifyStackAtCalls) {
2878 _masm->sub(FP, SP, O7);
2879 _masm->cmp(O7, initial_frame_size_in_bytes());
2880 _masm->trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2 );
2881 }
2882 }
2883
2884
2885 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest) {
2886 assert(left->is_register(), "can only handle registers");
2887
2888 if (left->is_single_cpu()) {
2889 __ neg(left->as_register(), dest->as_register());
2890 } else if (left->is_single_fpu()) {
2891 __ fneg(FloatRegisterImpl::S, left->as_float_reg(), dest->as_float_reg());
2892 } else if (left->is_double_fpu()) {
2893 __ fneg(FloatRegisterImpl::D, left->as_double_reg(), dest->as_double_reg());
2894 } else {
2895 assert (left->is_double_cpu(), "Must be a long");
2896 Register Rlow = left->as_register_lo();
2897 Register Rhi = left->as_register_hi();
2898 #ifdef _LP64
2899 __ sub(G0, Rlow, dest->as_register_lo());
2900 #else
2901 __ subcc(G0, Rlow, dest->as_register_lo());
2902 __ subc (G0, Rhi, dest->as_register_hi());
2903 #endif
2904 }
2905 }
2906
2907
2908 void LIR_Assembler::fxch(int i) {
2909 Unimplemented();
2910 }
2911
2912 void LIR_Assembler::fld(int i) {
2913 Unimplemented();
2914 }
2915
2916 void LIR_Assembler::ffree(int i) {
2917 Unimplemented();
2918 }
2919
2920 void LIR_Assembler::rt_call(LIR_Opr result, address dest,
2921 const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
2922
2923 // if tmp is invalid, then the function being called doesn't destroy the thread
2924 if (tmp->is_valid()) {
2925 __ save_thread(tmp->as_register());
2926 }
2927 __ call(dest, relocInfo::runtime_call_type);
2928 __ delayed()->nop();
2929 if (info != NULL) {
2930 add_call_info_here(info);
2931 }
2932 if (tmp->is_valid()) {
2933 __ restore_thread(tmp->as_register());
2934 }
2935
2936 #ifdef ASSERT
2937 __ verify_thread();
2938 #endif // ASSERT
2939 }
2940
2941
2942 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
2943 #ifdef _LP64
2944 ShouldNotReachHere();
2945 #endif
2946
2947 NEEDS_CLEANUP;
2948 if (type == T_LONG) {
2949 LIR_Address* mem_addr = dest->is_address() ? dest->as_address_ptr() : src->as_address_ptr();
2950
2951 // (extended to allow indexed as well as constant displaced for JSR-166)
2952 Register idx = noreg; // contains either constant offset or index
2953
2954 int disp = mem_addr->disp();
2955 if (mem_addr->index() == LIR_OprFact::illegalOpr) {
2956 if (!Assembler::is_simm13(disp)) {
2957 idx = O7;
2958 __ set(disp, idx);
2959 }
2960 } else {
2961 assert(disp == 0, "not both indexed and disp");
2962 idx = mem_addr->index()->as_register();
2963 }
2964
2965 int null_check_offset = -1;
2966
2967 Register base = mem_addr->base()->as_register();
2968 if (src->is_register() && dest->is_address()) {
2969 // G4 is high half, G5 is low half
2970 if (VM_Version::v9_instructions_work()) {
2971 // clear the top bits of G5, and scale up G4
2972 __ srl (src->as_register_lo(), 0, G5);
2973 __ sllx(src->as_register_hi(), 32, G4);
2974 // combine the two halves into the 64 bits of G4
2975 __ or3(G4, G5, G4);
2976 null_check_offset = __ offset();
2977 if (idx == noreg) {
2978 __ stx(G4, base, disp);
2979 } else {
2980 __ stx(G4, base, idx);
2981 }
2982 } else {
2983 __ mov (src->as_register_hi(), G4);
2984 __ mov (src->as_register_lo(), G5);
2985 null_check_offset = __ offset();
2986 if (idx == noreg) {
2987 __ std(G4, base, disp);
2988 } else {
2989 __ std(G4, base, idx);
2990 }
2991 }
2992 } else if (src->is_address() && dest->is_register()) {
2993 null_check_offset = __ offset();
2994 if (VM_Version::v9_instructions_work()) {
2995 if (idx == noreg) {
2996 __ ldx(base, disp, G5);
2997 } else {
2998 __ ldx(base, idx, G5);
2999 }
3000 __ srax(G5, 32, dest->as_register_hi()); // fetch the high half into hi
3001 __ mov (G5, dest->as_register_lo()); // copy low half into lo
3002 } else {
3003 if (idx == noreg) {
3004 __ ldd(base, disp, G4);
3005 } else {
3006 __ ldd(base, idx, G4);
3007 }
3008 // G4 is high half, G5 is low half
3009 __ mov (G4, dest->as_register_hi());
3010 __ mov (G5, dest->as_register_lo());
3011 }
3012 } else {
3013 Unimplemented();
3014 }
3015 if (info != NULL) {
3016 add_debug_info_for_null_check(null_check_offset, info);
3017 }
3018
3019 } else {
3020 // use normal move for all other volatiles since they don't need
3021 // special handling to remain atomic.
3022 move_op(src, dest, type, lir_patch_none, info, false, false);
3023 }
3024 }
3025
3026 void LIR_Assembler::membar() {
3027 // only StoreLoad membars are ever explicitly needed on sparcs in TSO mode
3028 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad) );
3029 }
3030
3031 void LIR_Assembler::membar_acquire() {
3032 // no-op on TSO
3033 }
3034
3035 void LIR_Assembler::membar_release() {
3036 // no-op on TSO
3037 }
3038
3039 // Macro to Pack two sequential registers containing 32 bit values
3040 // into a single 64 bit register.
3041 // rs and rs->successor() are packed into rd
3042 // rd and rs may be the same register.
3043 // Note: rs and rs->successor() are destroyed.
3044 void LIR_Assembler::pack64( Register rs, Register rd ) {
3045 __ sllx(rs, 32, rs);
3046 __ srl(rs->successor(), 0, rs->successor());
3047 __ or3(rs, rs->successor(), rd);
3048 }
3049
3050 // Macro to unpack a 64 bit value in a register into
3051 // two sequential registers.
3052 // rd is unpacked into rd and rd->successor()
3053 void LIR_Assembler::unpack64( Register rd ) {
3054 __ mov(rd, rd->successor());
3055 __ srax(rd, 32, rd);
3056 __ sra(rd->successor(), 0, rd->successor());
3057 }
3058
3059
3060 void LIR_Assembler::leal(LIR_Opr addr_opr, LIR_Opr dest) {
3061 LIR_Address* addr = addr_opr->as_address_ptr();
3062 assert(addr->index()->is_illegal() && addr->scale() == LIR_Address::times_1 && Assembler::is_simm13(addr->disp()), "can't handle complex addresses yet");
3063 __ add(addr->base()->as_register(), addr->disp(), dest->as_register());
3064 }
3065
3066
3067 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
3068 assert(result_reg->is_register(), "check");
3069 __ mov(G2_thread, result_reg->as_register());
3070 }
3071
3072
3073 void LIR_Assembler::peephole(LIR_List* lir) {
3074 LIR_OpList* inst = lir->instructions_list();
3075 for (int i = 0; i < inst->length(); i++) {
3076 LIR_Op* op = inst->at(i);
3077 switch (op->code()) {
3078 case lir_cond_float_branch:
3079 case lir_branch: {
3080 LIR_OpBranch* branch = op->as_OpBranch();
3081 assert(branch->info() == NULL, "shouldn't be state on branches anymore");
3082 LIR_Op* delay_op = NULL;
3083 // we'd like to be able to pull following instructions into
3084 // this slot but we don't know enough to do it safely yet so
3085 // only optimize block to block control flow.
3086 if (LIRFillDelaySlots && branch->block()) {
3087 LIR_Op* prev = inst->at(i - 1);
3088 if (prev && LIR_Assembler::is_single_instruction(prev) && prev->info() == NULL) {
3089 // swap previous instruction into delay slot
3090 inst->at_put(i - 1, op);
3091 inst->at_put(i, new LIR_OpDelay(prev, op->info()));
3092 #ifndef PRODUCT
3093 if (LIRTracePeephole) {
3094 tty->print_cr("delayed");
3095 inst->at(i - 1)->print();
3096 inst->at(i)->print();
3097 tty->cr();
3098 }
3099 #endif
3100 continue;
3101 }
3102 }
3103
3104 if (!delay_op) {
3105 delay_op = new LIR_OpDelay(new LIR_Op0(lir_nop), NULL);
3106 }
3107 inst->insert_before(i + 1, delay_op);
3108 break;
3109 }
3110 case lir_static_call:
3111 case lir_virtual_call:
3112 case lir_icvirtual_call:
3113 case lir_optvirtual_call:
3114 case lir_dynamic_call: {
3115 LIR_Op* prev = inst->at(i - 1);
3116 if (LIRFillDelaySlots && prev && prev->code() == lir_move && prev->info() == NULL &&
3117 (op->code() != lir_virtual_call ||
3118 !prev->result_opr()->is_single_cpu() ||
3119 prev->result_opr()->as_register() != O0) &&
3120 LIR_Assembler::is_single_instruction(prev)) {
3121 // Only moves without info can be put into the delay slot.
3122 // Also don't allow the setup of the receiver in the delay
3123 // slot for vtable calls.
3124 inst->at_put(i - 1, op);
3125 inst->at_put(i, new LIR_OpDelay(prev, op->info()));
3126 #ifndef PRODUCT
3127 if (LIRTracePeephole) {
3128 tty->print_cr("delayed");
3129 inst->at(i - 1)->print();
3130 inst->at(i)->print();
3131 tty->cr();
3132 }
3133 #endif
3134 continue;
3135 }
3136
3137 LIR_Op* delay_op = new LIR_OpDelay(new LIR_Op0(lir_nop), op->as_OpJavaCall()->info());
3138 inst->insert_before(i + 1, delay_op);
3139 break;
3140 }
3141 }
3142 }
3143 }
3144
3145
3146
3147
3148 #undef __