665 Register rval = op->in_opr()->as_register();
666 Register rdst = dst->as_register();
667 int shift = BitsPerInt - T_CHAR_aelem_bytes * BitsPerByte;
668 __ sll (rval, shift, rdst);
669 __ srl (rdst, shift, rdst);
670 break;
671 }
672
673 default: ShouldNotReachHere();
674 }
675 }
676
677
678 void LIR_Assembler::align_call(LIR_Code) {
679 // do nothing since all instructions are word aligned on sparc
680 }
681
682
683 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
684 __ call(op->addr(), rtype);
685 // the peephole pass fills the delay slot
686 }
687
688
689 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
690 RelocationHolder rspec = virtual_call_Relocation::spec(pc());
691 __ set_oop((jobject)Universe::non_oop_word(), G5_inline_cache_reg);
692 __ relocate(rspec);
693 __ call(op->addr(), relocInfo::none);
694 // the peephole pass fills the delay slot
695 }
696
697
698 void LIR_Assembler::vtable_call(LIR_OpJavaCall* op) {
699 add_debug_info_for_null_check_here(op->info());
700 __ ld_ptr(O0, oopDesc::klass_offset_in_bytes(), G3_scratch);
701 if (__ is_simm13(op->vtable_offset())) {
702 __ ld_ptr(G3_scratch, op->vtable_offset(), G5_method);
703 } else {
704 // This will generate 2 instructions
705 __ set(op->vtable_offset(), G5_method);
706 // ld_ptr, set_hi, set
707 __ ld_ptr(G3_scratch, G5_method, G5_method);
708 }
709 __ ld_ptr(G5_method, methodOopDesc::from_compiled_offset(), G3_scratch);
710 __ callr(G3_scratch, G0);
711 // the peephole pass fills the delay slot
712 }
713
714
715 void LIR_Assembler::preserve_SP(LIR_OpJavaCall* op) {
716 Unimplemented();
717 }
718
719
720 void LIR_Assembler::restore_SP(LIR_OpJavaCall* op) {
721 Unimplemented();
722 }
723
724
725 // load with 32-bit displacement
726 int LIR_Assembler::load(Register s, int disp, Register d, BasicType ld_type, CodeEmitInfo *info) {
727 int load_offset = code_offset();
728 if (Assembler::is_simm13(disp)) {
729 if (info != NULL) add_debug_info_for_null_check_here(info);
730 switch(ld_type) {
731 case T_BOOLEAN: // fall through
732 case T_BYTE : __ ldsb(s, disp, d); break;
733 case T_CHAR : __ lduh(s, disp, d); break;
734 case T_SHORT : __ ldsh(s, disp, d); break;
735 case T_INT : __ ld(s, disp, d); break;
736 case T_ADDRESS:// fall through
737 case T_ARRAY : // fall through
738 case T_OBJECT: __ ld_ptr(s, disp, d); break;
739 default : ShouldNotReachHere();
740 }
741 } else {
742 __ set(disp, O7);
743 if (info != NULL) add_debug_info_for_null_check_here(info);
744 load_offset = code_offset();
2860 void LIR_Assembler::emit_delay(LIR_OpDelay* op) {
2861 // make sure we are expecting a delay
2862 // this has the side effect of clearing the delay state
2863 // so we can use _masm instead of _masm->delayed() to do the
2864 // code generation.
2865 __ delayed();
2866
2867 // make sure we only emit one instruction
2868 int offset = code_offset();
2869 op->delay_op()->emit_code(this);
2870 #ifdef ASSERT
2871 if (code_offset() - offset != NativeInstruction::nop_instruction_size) {
2872 op->delay_op()->print();
2873 }
2874 assert(code_offset() - offset == NativeInstruction::nop_instruction_size,
2875 "only one instruction can go in a delay slot");
2876 #endif
2877
2878 // we may also be emitting the call info for the instruction
2879 // which we are the delay slot of.
2880 CodeEmitInfo * call_info = op->call_info();
2881 if (call_info) {
2882 add_call_info(code_offset(), call_info);
2883 }
2884
2885 if (VerifyStackAtCalls) {
2886 _masm->sub(FP, SP, O7);
2887 _masm->cmp(O7, initial_frame_size_in_bytes());
2888 _masm->trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2 );
2889 }
2890 }
2891
2892
2893 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest) {
2894 assert(left->is_register(), "can only handle registers");
2895
2896 if (left->is_single_cpu()) {
2897 __ neg(left->as_register(), dest->as_register());
2898 } else if (left->is_single_fpu()) {
2899 __ fneg(FloatRegisterImpl::S, left->as_float_reg(), dest->as_float_reg());
2900 } else if (left->is_double_fpu()) {
3085 switch (op->code()) {
3086 case lir_cond_float_branch:
3087 case lir_branch: {
3088 LIR_OpBranch* branch = op->as_OpBranch();
3089 assert(branch->info() == NULL, "shouldn't be state on branches anymore");
3090 LIR_Op* delay_op = NULL;
3091 // we'd like to be able to pull following instructions into
3092 // this slot but we don't know enough to do it safely yet so
3093 // only optimize block to block control flow.
3094 if (LIRFillDelaySlots && branch->block()) {
3095 LIR_Op* prev = inst->at(i - 1);
3096 if (prev && LIR_Assembler::is_single_instruction(prev) && prev->info() == NULL) {
3097 // swap previous instruction into delay slot
3098 inst->at_put(i - 1, op);
3099 inst->at_put(i, new LIR_OpDelay(prev, op->info()));
3100 #ifndef PRODUCT
3101 if (LIRTracePeephole) {
3102 tty->print_cr("delayed");
3103 inst->at(i - 1)->print();
3104 inst->at(i)->print();
3105 }
3106 #endif
3107 continue;
3108 }
3109 }
3110
3111 if (!delay_op) {
3112 delay_op = new LIR_OpDelay(new LIR_Op0(lir_nop), NULL);
3113 }
3114 inst->insert_before(i + 1, delay_op);
3115 break;
3116 }
3117 case lir_static_call:
3118 case lir_virtual_call:
3119 case lir_icvirtual_call:
3120 case lir_optvirtual_call: {
3121 LIR_Op* delay_op = NULL;
3122 LIR_Op* prev = inst->at(i - 1);
3123 if (LIRFillDelaySlots && prev && prev->code() == lir_move && prev->info() == NULL &&
3124 (op->code() != lir_virtual_call ||
3125 !prev->result_opr()->is_single_cpu() ||
3126 prev->result_opr()->as_register() != O0) &&
3127 LIR_Assembler::is_single_instruction(prev)) {
3128 // Only moves without info can be put into the delay slot.
3129 // Also don't allow the setup of the receiver in the delay
3130 // slot for vtable calls.
3131 inst->at_put(i - 1, op);
3132 inst->at_put(i, new LIR_OpDelay(prev, op->info()));
3133 #ifndef PRODUCT
3134 if (LIRTracePeephole) {
3135 tty->print_cr("delayed");
3136 inst->at(i - 1)->print();
3137 inst->at(i)->print();
3138 }
3139 #endif
3140 continue;
3141 }
3142
3143 if (!delay_op) {
3144 delay_op = new LIR_OpDelay(new LIR_Op0(lir_nop), op->as_OpJavaCall()->info());
3145 inst->insert_before(i + 1, delay_op);
3146 }
3147 break;
3148 }
3149 }
3150 }
3151 }
3152
3153
3154
3155
3156 #undef __
|
665 Register rval = op->in_opr()->as_register();
666 Register rdst = dst->as_register();
667 int shift = BitsPerInt - T_CHAR_aelem_bytes * BitsPerByte;
668 __ sll (rval, shift, rdst);
669 __ srl (rdst, shift, rdst);
670 break;
671 }
672
673 default: ShouldNotReachHere();
674 }
675 }
676
677
678 void LIR_Assembler::align_call(LIR_Code) {
679 // do nothing since all instructions are word aligned on sparc
680 }
681
682
683 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
684 __ call(op->addr(), rtype);
685 // The peephole pass fills the delay slot, add_call_info is done in
686 // LIR_Assembler::emit_delay.
687 }
688
689
690 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
691 RelocationHolder rspec = virtual_call_Relocation::spec(pc());
692 __ set_oop((jobject)Universe::non_oop_word(), G5_inline_cache_reg);
693 __ relocate(rspec);
694 __ call(op->addr(), relocInfo::none);
695 // The peephole pass fills the delay slot, add_call_info is done in
696 // LIR_Assembler::emit_delay.
697 }
698
699
700 void LIR_Assembler::vtable_call(LIR_OpJavaCall* op) {
701 add_debug_info_for_null_check_here(op->info());
702 __ ld_ptr(O0, oopDesc::klass_offset_in_bytes(), G3_scratch);
703 if (__ is_simm13(op->vtable_offset())) {
704 __ ld_ptr(G3_scratch, op->vtable_offset(), G5_method);
705 } else {
706 // This will generate 2 instructions
707 __ set(op->vtable_offset(), G5_method);
708 // ld_ptr, set_hi, set
709 __ ld_ptr(G3_scratch, G5_method, G5_method);
710 }
711 __ ld_ptr(G5_method, methodOopDesc::from_compiled_offset(), G3_scratch);
712 __ callr(G3_scratch, G0);
713 // the peephole pass fills the delay slot
714 }
715
716
717 // load with 32-bit displacement
718 int LIR_Assembler::load(Register s, int disp, Register d, BasicType ld_type, CodeEmitInfo *info) {
719 int load_offset = code_offset();
720 if (Assembler::is_simm13(disp)) {
721 if (info != NULL) add_debug_info_for_null_check_here(info);
722 switch(ld_type) {
723 case T_BOOLEAN: // fall through
724 case T_BYTE : __ ldsb(s, disp, d); break;
725 case T_CHAR : __ lduh(s, disp, d); break;
726 case T_SHORT : __ ldsh(s, disp, d); break;
727 case T_INT : __ ld(s, disp, d); break;
728 case T_ADDRESS:// fall through
729 case T_ARRAY : // fall through
730 case T_OBJECT: __ ld_ptr(s, disp, d); break;
731 default : ShouldNotReachHere();
732 }
733 } else {
734 __ set(disp, O7);
735 if (info != NULL) add_debug_info_for_null_check_here(info);
736 load_offset = code_offset();
2852 void LIR_Assembler::emit_delay(LIR_OpDelay* op) {
2853 // make sure we are expecting a delay
2854 // this has the side effect of clearing the delay state
2855 // so we can use _masm instead of _masm->delayed() to do the
2856 // code generation.
2857 __ delayed();
2858
2859 // make sure we only emit one instruction
2860 int offset = code_offset();
2861 op->delay_op()->emit_code(this);
2862 #ifdef ASSERT
2863 if (code_offset() - offset != NativeInstruction::nop_instruction_size) {
2864 op->delay_op()->print();
2865 }
2866 assert(code_offset() - offset == NativeInstruction::nop_instruction_size,
2867 "only one instruction can go in a delay slot");
2868 #endif
2869
2870 // we may also be emitting the call info for the instruction
2871 // which we are the delay slot of.
2872 CodeEmitInfo* call_info = op->call_info();
2873 if (call_info) {
2874 add_call_info(code_offset(), call_info);
2875 }
2876
2877 if (VerifyStackAtCalls) {
2878 _masm->sub(FP, SP, O7);
2879 _masm->cmp(O7, initial_frame_size_in_bytes());
2880 _masm->trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2 );
2881 }
2882 }
2883
2884
2885 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest) {
2886 assert(left->is_register(), "can only handle registers");
2887
2888 if (left->is_single_cpu()) {
2889 __ neg(left->as_register(), dest->as_register());
2890 } else if (left->is_single_fpu()) {
2891 __ fneg(FloatRegisterImpl::S, left->as_float_reg(), dest->as_float_reg());
2892 } else if (left->is_double_fpu()) {
3077 switch (op->code()) {
3078 case lir_cond_float_branch:
3079 case lir_branch: {
3080 LIR_OpBranch* branch = op->as_OpBranch();
3081 assert(branch->info() == NULL, "shouldn't be state on branches anymore");
3082 LIR_Op* delay_op = NULL;
3083 // we'd like to be able to pull following instructions into
3084 // this slot but we don't know enough to do it safely yet so
3085 // only optimize block to block control flow.
3086 if (LIRFillDelaySlots && branch->block()) {
3087 LIR_Op* prev = inst->at(i - 1);
3088 if (prev && LIR_Assembler::is_single_instruction(prev) && prev->info() == NULL) {
3089 // swap previous instruction into delay slot
3090 inst->at_put(i - 1, op);
3091 inst->at_put(i, new LIR_OpDelay(prev, op->info()));
3092 #ifndef PRODUCT
3093 if (LIRTracePeephole) {
3094 tty->print_cr("delayed");
3095 inst->at(i - 1)->print();
3096 inst->at(i)->print();
3097 tty->cr();
3098 }
3099 #endif
3100 continue;
3101 }
3102 }
3103
3104 if (!delay_op) {
3105 delay_op = new LIR_OpDelay(new LIR_Op0(lir_nop), NULL);
3106 }
3107 inst->insert_before(i + 1, delay_op);
3108 break;
3109 }
3110 case lir_static_call:
3111 case lir_virtual_call:
3112 case lir_icvirtual_call:
3113 case lir_optvirtual_call:
3114 case lir_dynamic_call: {
3115 LIR_Op* prev = inst->at(i - 1);
3116 if (LIRFillDelaySlots && prev && prev->code() == lir_move && prev->info() == NULL &&
3117 (op->code() != lir_virtual_call ||
3118 !prev->result_opr()->is_single_cpu() ||
3119 prev->result_opr()->as_register() != O0) &&
3120 LIR_Assembler::is_single_instruction(prev)) {
3121 // Only moves without info can be put into the delay slot.
3122 // Also don't allow the setup of the receiver in the delay
3123 // slot for vtable calls.
3124 inst->at_put(i - 1, op);
3125 inst->at_put(i, new LIR_OpDelay(prev, op->info()));
3126 #ifndef PRODUCT
3127 if (LIRTracePeephole) {
3128 tty->print_cr("delayed");
3129 inst->at(i - 1)->print();
3130 inst->at(i)->print();
3131 tty->cr();
3132 }
3133 #endif
3134 continue;
3135 }
3136
3137 LIR_Op* delay_op = new LIR_OpDelay(new LIR_Op0(lir_nop), op->as_OpJavaCall()->info());
3138 inst->insert_before(i + 1, delay_op);
3139 break;
3140 }
3141 }
3142 }
3143 }
3144
3145
3146
3147
3148 #undef __
|