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          --- old/src/cpu/sparc/vm/c1_LIRAssembler_sparc.cpp
          +++ new/src/cpu/sparc/vm/c1_LIRAssembler_sparc.cpp
↓ open down ↓ 674 lines elided ↑ open up ↑
 675  675  }
 676  676  
 677  677  
 678  678  void LIR_Assembler::align_call(LIR_Code) {
 679  679    // do nothing since all instructions are word aligned on sparc
 680  680  }
 681  681  
 682  682  
 683  683  void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
 684  684    __ call(op->addr(), rtype);
 685      -  // the peephole pass fills the delay slot
      685 +  // The peephole pass fills the delay slot, add_call_info is done in
      686 +  // LIR_Assembler::emit_delay.
 686  687  }
 687  688  
 688  689  
 689  690  void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
 690  691    RelocationHolder rspec = virtual_call_Relocation::spec(pc());
 691  692    __ set_oop((jobject)Universe::non_oop_word(), G5_inline_cache_reg);
 692  693    __ relocate(rspec);
 693  694    __ call(op->addr(), relocInfo::none);
 694      -  // the peephole pass fills the delay slot
      695 +  // The peephole pass fills the delay slot, add_call_info is done in
      696 +  // LIR_Assembler::emit_delay.
 695  697  }
 696  698  
 697  699  
 698  700  void LIR_Assembler::vtable_call(LIR_OpJavaCall* op) {
 699  701    add_debug_info_for_null_check_here(op->info());
 700  702    __ ld_ptr(O0, oopDesc::klass_offset_in_bytes(), G3_scratch);
 701  703    if (__ is_simm13(op->vtable_offset())) {
 702  704      __ ld_ptr(G3_scratch, op->vtable_offset(), G5_method);
 703  705    } else {
 704  706      // This will generate 2 instructions
 705  707      __ set(op->vtable_offset(), G5_method);
 706  708      // ld_ptr, set_hi, set
 707  709      __ ld_ptr(G3_scratch, G5_method, G5_method);
 708  710    }
 709  711    __ ld_ptr(G5_method, methodOopDesc::from_compiled_offset(), G3_scratch);
 710  712    __ callr(G3_scratch, G0);
 711  713    // the peephole pass fills the delay slot
 712  714  }
 713  715  
 714  716  
 715      -void LIR_Assembler::preserve_SP(LIR_OpJavaCall* op) {
 716      -  Unimplemented();
 717      -}
 718      -
 719      -
 720      -void LIR_Assembler::restore_SP(LIR_OpJavaCall* op) {
 721      -  Unimplemented();
 722      -}
 723      -
 724      -
 725  717  // load with 32-bit displacement
 726  718  int LIR_Assembler::load(Register s, int disp, Register d, BasicType ld_type, CodeEmitInfo *info) {
 727  719    int load_offset = code_offset();
 728  720    if (Assembler::is_simm13(disp)) {
 729  721      if (info != NULL) add_debug_info_for_null_check_here(info);
 730  722      switch(ld_type) {
 731  723        case T_BOOLEAN: // fall through
 732  724        case T_BYTE  : __ ldsb(s, disp, d); break;
 733  725        case T_CHAR  : __ lduh(s, disp, d); break;
 734  726        case T_SHORT : __ ldsh(s, disp, d); break;
↓ open down ↓ 2135 lines elided ↑ open up ↑
2870 2862  #ifdef ASSERT
2871 2863    if (code_offset() - offset != NativeInstruction::nop_instruction_size) {
2872 2864      op->delay_op()->print();
2873 2865    }
2874 2866    assert(code_offset() - offset == NativeInstruction::nop_instruction_size,
2875 2867           "only one instruction can go in a delay slot");
2876 2868  #endif
2877 2869  
2878 2870    // we may also be emitting the call info for the instruction
2879 2871    // which we are the delay slot of.
2880      -  CodeEmitInfo * call_info = op->call_info();
     2872 +  CodeEmitInfo* call_info = op->call_info();
2881 2873    if (call_info) {
2882 2874      add_call_info(code_offset(), call_info);
2883 2875    }
2884 2876  
2885 2877    if (VerifyStackAtCalls) {
2886 2878      _masm->sub(FP, SP, O7);
2887 2879      _masm->cmp(O7, initial_frame_size_in_bytes());
2888 2880      _masm->trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2 );
2889 2881    }
2890 2882  }
↓ open down ↓ 204 lines elided ↑ open up ↑
3095 3087            LIR_Op* prev = inst->at(i - 1);
3096 3088            if (prev && LIR_Assembler::is_single_instruction(prev) && prev->info() == NULL) {
3097 3089              // swap previous instruction into delay slot
3098 3090              inst->at_put(i - 1, op);
3099 3091              inst->at_put(i, new LIR_OpDelay(prev, op->info()));
3100 3092  #ifndef PRODUCT
3101 3093              if (LIRTracePeephole) {
3102 3094                tty->print_cr("delayed");
3103 3095                inst->at(i - 1)->print();
3104 3096                inst->at(i)->print();
     3097 +              tty->cr();
3105 3098              }
3106 3099  #endif
3107 3100              continue;
3108 3101            }
3109 3102          }
3110 3103  
3111 3104          if (!delay_op) {
3112 3105            delay_op = new LIR_OpDelay(new LIR_Op0(lir_nop), NULL);
3113 3106          }
3114 3107          inst->insert_before(i + 1, delay_op);
3115 3108          break;
3116 3109        }
3117 3110        case lir_static_call:
3118 3111        case lir_virtual_call:
3119 3112        case lir_icvirtual_call:
3120      -      case lir_optvirtual_call: {
3121      -        LIR_Op* delay_op = NULL;
     3113 +      case lir_optvirtual_call:
     3114 +      case lir_dynamic_call: {
3122 3115          LIR_Op* prev = inst->at(i - 1);
3123 3116          if (LIRFillDelaySlots && prev && prev->code() == lir_move && prev->info() == NULL &&
3124 3117              (op->code() != lir_virtual_call ||
3125 3118               !prev->result_opr()->is_single_cpu() ||
3126 3119               prev->result_opr()->as_register() != O0) &&
3127 3120              LIR_Assembler::is_single_instruction(prev)) {
3128 3121            // Only moves without info can be put into the delay slot.
3129 3122            // Also don't allow the setup of the receiver in the delay
3130 3123            // slot for vtable calls.
3131 3124            inst->at_put(i - 1, op);
3132 3125            inst->at_put(i, new LIR_OpDelay(prev, op->info()));
3133 3126  #ifndef PRODUCT
3134 3127            if (LIRTracePeephole) {
3135 3128              tty->print_cr("delayed");
3136 3129              inst->at(i - 1)->print();
3137 3130              inst->at(i)->print();
     3131 +            tty->cr();
3138 3132            }
3139 3133  #endif
3140 3134            continue;
3141 3135          }
3142 3136  
3143      -        if (!delay_op) {
3144      -          delay_op = new LIR_OpDelay(new LIR_Op0(lir_nop), op->as_OpJavaCall()->info());
3145      -          inst->insert_before(i + 1, delay_op);
3146      -        }
     3137 +        LIR_Op* delay_op = new LIR_OpDelay(new LIR_Op0(lir_nop), op->as_OpJavaCall()->info());
     3138 +        inst->insert_before(i + 1, delay_op);
3147 3139          break;
3148 3140        }
3149 3141      }
3150 3142    }
3151 3143  }
3152 3144  
3153 3145  
3154 3146  
3155 3147  
3156 3148  #undef __
    
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