1 /*
   2  * Copyright 2003-2010 Sun Microsystems, Inc.  All Rights Reserved.
   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
  20  * CA 95054 USA or visit www.sun.com if you need additional information or
  21  * have any questions.
  22  *
  23  */
  24 
  25 #include "incls/_precompiled.incl"
  26 #include "incls/_sharedRuntime_sparc.cpp.incl"
  27 
  28 #define __ masm->
  29 
  30 #ifdef COMPILER2
  31 UncommonTrapBlob*   SharedRuntime::_uncommon_trap_blob;
  32 #endif // COMPILER2
  33 
  34 DeoptimizationBlob* SharedRuntime::_deopt_blob;
  35 SafepointBlob*      SharedRuntime::_polling_page_safepoint_handler_blob;
  36 SafepointBlob*      SharedRuntime::_polling_page_return_handler_blob;
  37 RuntimeStub*        SharedRuntime::_wrong_method_blob;
  38 RuntimeStub*        SharedRuntime::_ic_miss_blob;
  39 RuntimeStub*        SharedRuntime::_resolve_opt_virtual_call_blob;
  40 RuntimeStub*        SharedRuntime::_resolve_virtual_call_blob;
  41 RuntimeStub*        SharedRuntime::_resolve_static_call_blob;
  42 
  43 class RegisterSaver {
  44 
  45   // Used for saving volatile registers. This is Gregs, Fregs, I/L/O.
  46   // The Oregs are problematic. In the 32bit build the compiler can
  47   // have O registers live with 64 bit quantities. A window save will
  48   // cut the heads off of the registers. We have to do a very extensive
  49   // stack dance to save and restore these properly.
  50 
  51   // Note that the Oregs problem only exists if we block at either a polling
  52   // page exception a compiled code safepoint that was not originally a call
  53   // or deoptimize following one of these kinds of safepoints.
  54 
  55   // Lots of registers to save.  For all builds, a window save will preserve
  56   // the %i and %l registers.  For the 32-bit longs-in-two entries and 64-bit
  57   // builds a window-save will preserve the %o registers.  In the LION build
  58   // we need to save the 64-bit %o registers which requires we save them
  59   // before the window-save (as then they become %i registers and get their
  60   // heads chopped off on interrupt).  We have to save some %g registers here
  61   // as well.
  62   enum {
  63     // This frame's save area.  Includes extra space for the native call:
  64     // vararg's layout space and the like.  Briefly holds the caller's
  65     // register save area.
  66     call_args_area = frame::register_save_words_sp_offset +
  67                      frame::memory_parameter_word_sp_offset*wordSize,
  68     // Make sure save locations are always 8 byte aligned.
  69     // can't use round_to because it doesn't produce compile time constant
  70     start_of_extra_save_area = ((call_args_area + 7) & ~7),
  71     g1_offset = start_of_extra_save_area, // g-regs needing saving
  72     g3_offset = g1_offset+8,
  73     g4_offset = g3_offset+8,
  74     g5_offset = g4_offset+8,
  75     o0_offset = g5_offset+8,
  76     o1_offset = o0_offset+8,
  77     o2_offset = o1_offset+8,
  78     o3_offset = o2_offset+8,
  79     o4_offset = o3_offset+8,
  80     o5_offset = o4_offset+8,
  81     start_of_flags_save_area = o5_offset+8,
  82     ccr_offset = start_of_flags_save_area,
  83     fsr_offset = ccr_offset + 8,
  84     d00_offset = fsr_offset+8,  // Start of float save area
  85     register_save_size = d00_offset+8*32
  86   };
  87 
  88 
  89   public:
  90 
  91   static int Oexception_offset() { return o0_offset; };
  92   static int G3_offset() { return g3_offset; };
  93   static int G5_offset() { return g5_offset; };
  94   static OopMap* save_live_registers(MacroAssembler* masm, int additional_frame_words, int* total_frame_words);
  95   static void restore_live_registers(MacroAssembler* masm);
  96 
  97   // During deoptimization only the result register need to be restored
  98   // all the other values have already been extracted.
  99 
 100   static void restore_result_registers(MacroAssembler* masm);
 101 };
 102 
 103 OopMap* RegisterSaver::save_live_registers(MacroAssembler* masm, int additional_frame_words, int* total_frame_words) {
 104   // Record volatile registers as callee-save values in an OopMap so their save locations will be
 105   // propagated to the caller frame's RegisterMap during StackFrameStream construction (needed for
 106   // deoptimization; see compiledVFrame::create_stack_value).  The caller's I, L and O registers
 107   // are saved in register windows - I's and L's in the caller's frame and O's in the stub frame
 108   // (as the stub's I's) when the runtime routine called by the stub creates its frame.
 109   int i;
 110   // Always make the frame size 16 byte aligned.
 111   int frame_size = round_to(additional_frame_words + register_save_size, 16);
 112   // OopMap frame size is in c2 stack slots (sizeof(jint)) not bytes or words
 113   int frame_size_in_slots = frame_size / sizeof(jint);
 114   // CodeBlob frame size is in words.
 115   *total_frame_words = frame_size / wordSize;
 116   // OopMap* map = new OopMap(*total_frame_words, 0);
 117   OopMap* map = new OopMap(frame_size_in_slots, 0);
 118 
 119 #if !defined(_LP64)
 120 
 121   // Save 64-bit O registers; they will get their heads chopped off on a 'save'.
 122   __ stx(O0, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+0*8);
 123   __ stx(O1, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+1*8);
 124   __ stx(O2, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+2*8);
 125   __ stx(O3, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+3*8);
 126   __ stx(O4, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+4*8);
 127   __ stx(O5, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+5*8);
 128 #endif /* _LP64 */
 129 
 130   __ save(SP, -frame_size, SP);
 131 
 132 #ifndef _LP64
 133   // Reload the 64 bit Oregs. Although they are now Iregs we load them
 134   // to Oregs here to avoid interrupts cutting off their heads
 135 
 136   __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+0*8, O0);
 137   __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+1*8, O1);
 138   __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+2*8, O2);
 139   __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+3*8, O3);
 140   __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+4*8, O4);
 141   __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+5*8, O5);
 142 
 143   __ stx(O0, SP, o0_offset+STACK_BIAS);
 144   map->set_callee_saved(VMRegImpl::stack2reg((o0_offset + 4)>>2), O0->as_VMReg());
 145 
 146   __ stx(O1, SP, o1_offset+STACK_BIAS);
 147 
 148   map->set_callee_saved(VMRegImpl::stack2reg((o1_offset + 4)>>2), O1->as_VMReg());
 149 
 150   __ stx(O2, SP, o2_offset+STACK_BIAS);
 151   map->set_callee_saved(VMRegImpl::stack2reg((o2_offset + 4)>>2), O2->as_VMReg());
 152 
 153   __ stx(O3, SP, o3_offset+STACK_BIAS);
 154   map->set_callee_saved(VMRegImpl::stack2reg((o3_offset + 4)>>2), O3->as_VMReg());
 155 
 156   __ stx(O4, SP, o4_offset+STACK_BIAS);
 157   map->set_callee_saved(VMRegImpl::stack2reg((o4_offset + 4)>>2), O4->as_VMReg());
 158 
 159   __ stx(O5, SP, o5_offset+STACK_BIAS);
 160   map->set_callee_saved(VMRegImpl::stack2reg((o5_offset + 4)>>2), O5->as_VMReg());
 161 #endif /* _LP64 */
 162 
 163 
 164 #ifdef _LP64
 165   int debug_offset = 0;
 166 #else
 167   int debug_offset = 4;
 168 #endif
 169   // Save the G's
 170   __ stx(G1, SP, g1_offset+STACK_BIAS);
 171   map->set_callee_saved(VMRegImpl::stack2reg((g1_offset + debug_offset)>>2), G1->as_VMReg());
 172 
 173   __ stx(G3, SP, g3_offset+STACK_BIAS);
 174   map->set_callee_saved(VMRegImpl::stack2reg((g3_offset + debug_offset)>>2), G3->as_VMReg());
 175 
 176   __ stx(G4, SP, g4_offset+STACK_BIAS);
 177   map->set_callee_saved(VMRegImpl::stack2reg((g4_offset + debug_offset)>>2), G4->as_VMReg());
 178 
 179   __ stx(G5, SP, g5_offset+STACK_BIAS);
 180   map->set_callee_saved(VMRegImpl::stack2reg((g5_offset + debug_offset)>>2), G5->as_VMReg());
 181 
 182   // This is really a waste but we'll keep things as they were for now
 183   if (true) {
 184 #ifndef _LP64
 185     map->set_callee_saved(VMRegImpl::stack2reg((o0_offset)>>2), O0->as_VMReg()->next());
 186     map->set_callee_saved(VMRegImpl::stack2reg((o1_offset)>>2), O1->as_VMReg()->next());
 187     map->set_callee_saved(VMRegImpl::stack2reg((o2_offset)>>2), O2->as_VMReg()->next());
 188     map->set_callee_saved(VMRegImpl::stack2reg((o3_offset)>>2), O3->as_VMReg()->next());
 189     map->set_callee_saved(VMRegImpl::stack2reg((o4_offset)>>2), O4->as_VMReg()->next());
 190     map->set_callee_saved(VMRegImpl::stack2reg((o5_offset)>>2), O5->as_VMReg()->next());
 191     map->set_callee_saved(VMRegImpl::stack2reg((g1_offset)>>2), G1->as_VMReg()->next());
 192     map->set_callee_saved(VMRegImpl::stack2reg((g3_offset)>>2), G3->as_VMReg()->next());
 193     map->set_callee_saved(VMRegImpl::stack2reg((g4_offset)>>2), G4->as_VMReg()->next());
 194     map->set_callee_saved(VMRegImpl::stack2reg((g5_offset)>>2), G5->as_VMReg()->next());
 195 #endif /* _LP64 */
 196   }
 197 
 198 
 199   // Save the flags
 200   __ rdccr( G5 );
 201   __ stx(G5, SP, ccr_offset+STACK_BIAS);
 202   __ stxfsr(SP, fsr_offset+STACK_BIAS);
 203 
 204   // Save all the FP registers: 32 doubles (32 floats correspond to the 2 halves of the first 16 doubles)
 205   int offset = d00_offset;
 206   for( int i=0; i<FloatRegisterImpl::number_of_registers; i+=2 ) {
 207     FloatRegister f = as_FloatRegister(i);
 208     __ stf(FloatRegisterImpl::D,  f, SP, offset+STACK_BIAS);
 209     // Record as callee saved both halves of double registers (2 float registers).
 210     map->set_callee_saved(VMRegImpl::stack2reg(offset>>2), f->as_VMReg());
 211     map->set_callee_saved(VMRegImpl::stack2reg((offset + sizeof(float))>>2), f->as_VMReg()->next());
 212     offset += sizeof(double);
 213   }
 214 
 215   // And we're done.
 216 
 217   return map;
 218 }
 219 
 220 
 221 // Pop the current frame and restore all the registers that we
 222 // saved.
 223 void RegisterSaver::restore_live_registers(MacroAssembler* masm) {
 224 
 225   // Restore all the FP registers
 226   for( int i=0; i<FloatRegisterImpl::number_of_registers; i+=2 ) {
 227     __ ldf(FloatRegisterImpl::D, SP, d00_offset+i*sizeof(float)+STACK_BIAS, as_FloatRegister(i));
 228   }
 229 
 230   __ ldx(SP, ccr_offset+STACK_BIAS, G1);
 231   __ wrccr (G1) ;
 232 
 233   // Restore the G's
 234   // Note that G2 (AKA GThread) must be saved and restored separately.
 235   // TODO-FIXME: save and restore some of the other ASRs, viz., %asi and %gsr.
 236 
 237   __ ldx(SP, g1_offset+STACK_BIAS, G1);
 238   __ ldx(SP, g3_offset+STACK_BIAS, G3);
 239   __ ldx(SP, g4_offset+STACK_BIAS, G4);
 240   __ ldx(SP, g5_offset+STACK_BIAS, G5);
 241 
 242 
 243 #if !defined(_LP64)
 244   // Restore the 64-bit O's.
 245   __ ldx(SP, o0_offset+STACK_BIAS, O0);
 246   __ ldx(SP, o1_offset+STACK_BIAS, O1);
 247   __ ldx(SP, o2_offset+STACK_BIAS, O2);
 248   __ ldx(SP, o3_offset+STACK_BIAS, O3);
 249   __ ldx(SP, o4_offset+STACK_BIAS, O4);
 250   __ ldx(SP, o5_offset+STACK_BIAS, O5);
 251 
 252   // And temporarily place them in TLS
 253 
 254   __ stx(O0, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+0*8);
 255   __ stx(O1, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+1*8);
 256   __ stx(O2, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+2*8);
 257   __ stx(O3, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+3*8);
 258   __ stx(O4, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+4*8);
 259   __ stx(O5, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+5*8);
 260 #endif /* _LP64 */
 261 
 262   // Restore flags
 263 
 264   __ ldxfsr(SP, fsr_offset+STACK_BIAS);
 265 
 266   __ restore();
 267 
 268 #if !defined(_LP64)
 269   // Now reload the 64bit Oregs after we've restore the window.
 270   __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+0*8, O0);
 271   __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+1*8, O1);
 272   __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+2*8, O2);
 273   __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+3*8, O3);
 274   __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+4*8, O4);
 275   __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+5*8, O5);
 276 #endif /* _LP64 */
 277 
 278 }
 279 
 280 // Pop the current frame and restore the registers that might be holding
 281 // a result.
 282 void RegisterSaver::restore_result_registers(MacroAssembler* masm) {
 283 
 284 #if !defined(_LP64)
 285   // 32bit build returns longs in G1
 286   __ ldx(SP, g1_offset+STACK_BIAS, G1);
 287 
 288   // Retrieve the 64-bit O's.
 289   __ ldx(SP, o0_offset+STACK_BIAS, O0);
 290   __ ldx(SP, o1_offset+STACK_BIAS, O1);
 291   // and save to TLS
 292   __ stx(O0, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+0*8);
 293   __ stx(O1, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+1*8);
 294 #endif /* _LP64 */
 295 
 296   __ ldf(FloatRegisterImpl::D, SP, d00_offset+STACK_BIAS, as_FloatRegister(0));
 297 
 298   __ restore();
 299 
 300 #if !defined(_LP64)
 301   // Now reload the 64bit Oregs after we've restore the window.
 302   __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+0*8, O0);
 303   __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+1*8, O1);
 304 #endif /* _LP64 */
 305 
 306 }
 307 
 308 // The java_calling_convention describes stack locations as ideal slots on
 309 // a frame with no abi restrictions. Since we must observe abi restrictions
 310 // (like the placement of the register window) the slots must be biased by
 311 // the following value.
 312 static int reg2offset(VMReg r) {
 313   return (r->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size;
 314 }
 315 
 316 // ---------------------------------------------------------------------------
 317 // Read the array of BasicTypes from a signature, and compute where the
 318 // arguments should go.  Values in the VMRegPair regs array refer to 4-byte (VMRegImpl::stack_slot_size)
 319 // quantities.  Values less than VMRegImpl::stack0 are registers, those above
 320 // refer to 4-byte stack slots.  All stack slots are based off of the window
 321 // top.  VMRegImpl::stack0 refers to the first slot past the 16-word window,
 322 // and VMRegImpl::stack0+1 refers to the memory word 4-byes higher.  Register
 323 // values 0-63 (up to RegisterImpl::number_of_registers) are the 64-bit
 324 // integer registers.  Values 64-95 are the (32-bit only) float registers.
 325 // Each 32-bit quantity is given its own number, so the integer registers
 326 // (in either 32- or 64-bit builds) use 2 numbers.  For example, there is
 327 // an O0-low and an O0-high.  Essentially, all int register numbers are doubled.
 328 
 329 // Register results are passed in O0-O5, for outgoing call arguments.  To
 330 // convert to incoming arguments, convert all O's to I's.  The regs array
 331 // refer to the low and hi 32-bit words of 64-bit registers or stack slots.
 332 // If the regs[].second() field is set to VMRegImpl::Bad(), it means it's unused (a
 333 // 32-bit value was passed).  If both are VMRegImpl::Bad(), it means no value was
 334 // passed (used as a placeholder for the other half of longs and doubles in
 335 // the 64-bit build).  regs[].second() is either VMRegImpl::Bad() or regs[].second() is
 336 // regs[].first()+1 (regs[].first() may be misaligned in the C calling convention).
 337 // Sparc never passes a value in regs[].second() but not regs[].first() (regs[].first()
 338 // == VMRegImpl::Bad() && regs[].second() != VMRegImpl::Bad()) nor unrelated values in the
 339 // same VMRegPair.
 340 
 341 // Note: the INPUTS in sig_bt are in units of Java argument words, which are
 342 // either 32-bit or 64-bit depending on the build.  The OUTPUTS are in 32-bit
 343 // units regardless of build.
 344 
 345 
 346 // ---------------------------------------------------------------------------
 347 // The compiled Java calling convention.  The Java convention always passes
 348 // 64-bit values in adjacent aligned locations (either registers or stack),
 349 // floats in float registers and doubles in aligned float pairs.  Values are
 350 // packed in the registers.  There is no backing varargs store for values in
 351 // registers.  In the 32-bit build, longs are passed in G1 and G4 (cannot be
 352 // passed in I's, because longs in I's get their heads chopped off at
 353 // interrupt).
 354 int SharedRuntime::java_calling_convention(const BasicType *sig_bt,
 355                                            VMRegPair *regs,
 356                                            int total_args_passed,
 357                                            int is_outgoing) {
 358   assert(F31->as_VMReg()->is_reg(), "overlapping stack/register numbers");
 359 
 360   // Convention is to pack the first 6 int/oop args into the first 6 registers
 361   // (I0-I5), extras spill to the stack.  Then pack the first 8 float args
 362   // into F0-F7, extras spill to the stack.  Then pad all register sets to
 363   // align.  Then put longs and doubles into the same registers as they fit,
 364   // else spill to the stack.
 365   const int int_reg_max = SPARC_ARGS_IN_REGS_NUM;
 366   const int flt_reg_max = 8;
 367   //
 368   // Where 32-bit 1-reg longs start being passed
 369   // In tiered we must pass on stack because c1 can't use a "pair" in a single reg.
 370   // So make it look like we've filled all the G regs that c2 wants to use.
 371   Register g_reg = TieredCompilation ? noreg : G1;
 372 
 373   // Count int/oop and float args.  See how many stack slots we'll need and
 374   // where the longs & doubles will go.
 375   int int_reg_cnt   = 0;
 376   int flt_reg_cnt   = 0;
 377   // int stk_reg_pairs = frame::register_save_words*(wordSize>>2);
 378   // int stk_reg_pairs = SharedRuntime::out_preserve_stack_slots();
 379   int stk_reg_pairs = 0;
 380   for (int i = 0; i < total_args_passed; i++) {
 381     switch (sig_bt[i]) {
 382     case T_LONG:                // LP64, longs compete with int args
 383       assert(sig_bt[i+1] == T_VOID, "");
 384 #ifdef _LP64
 385       if (int_reg_cnt < int_reg_max) int_reg_cnt++;
 386 #endif
 387       break;
 388     case T_OBJECT:
 389     case T_ARRAY:
 390     case T_ADDRESS: // Used, e.g., in slow-path locking for the lock's stack address
 391       if (int_reg_cnt < int_reg_max) int_reg_cnt++;
 392 #ifndef _LP64
 393       else                            stk_reg_pairs++;
 394 #endif
 395       break;
 396     case T_INT:
 397     case T_SHORT:
 398     case T_CHAR:
 399     case T_BYTE:
 400     case T_BOOLEAN:
 401       if (int_reg_cnt < int_reg_max) int_reg_cnt++;
 402       else                            stk_reg_pairs++;
 403       break;
 404     case T_FLOAT:
 405       if (flt_reg_cnt < flt_reg_max) flt_reg_cnt++;
 406       else                            stk_reg_pairs++;
 407       break;
 408     case T_DOUBLE:
 409       assert(sig_bt[i+1] == T_VOID, "");
 410       break;
 411     case T_VOID:
 412       break;
 413     default:
 414       ShouldNotReachHere();
 415     }
 416   }
 417 
 418   // This is where the longs/doubles start on the stack.
 419   stk_reg_pairs = (stk_reg_pairs+1) & ~1; // Round
 420 
 421   int int_reg_pairs = (int_reg_cnt+1) & ~1; // 32-bit 2-reg longs only
 422   int flt_reg_pairs = (flt_reg_cnt+1) & ~1;
 423 
 424   // int stk_reg = frame::register_save_words*(wordSize>>2);
 425   // int stk_reg = SharedRuntime::out_preserve_stack_slots();
 426   int stk_reg = 0;
 427   int int_reg = 0;
 428   int flt_reg = 0;
 429 
 430   // Now do the signature layout
 431   for (int i = 0; i < total_args_passed; i++) {
 432     switch (sig_bt[i]) {
 433     case T_INT:
 434     case T_SHORT:
 435     case T_CHAR:
 436     case T_BYTE:
 437     case T_BOOLEAN:
 438 #ifndef _LP64
 439     case T_OBJECT:
 440     case T_ARRAY:
 441     case T_ADDRESS: // Used, e.g., in slow-path locking for the lock's stack address
 442 #endif // _LP64
 443       if (int_reg < int_reg_max) {
 444         Register r = is_outgoing ? as_oRegister(int_reg++) : as_iRegister(int_reg++);
 445         regs[i].set1(r->as_VMReg());
 446       } else {
 447         regs[i].set1(VMRegImpl::stack2reg(stk_reg++));
 448       }
 449       break;
 450 
 451 #ifdef _LP64
 452     case T_OBJECT:
 453     case T_ARRAY:
 454     case T_ADDRESS: // Used, e.g., in slow-path locking for the lock's stack address
 455       if (int_reg < int_reg_max) {
 456         Register r = is_outgoing ? as_oRegister(int_reg++) : as_iRegister(int_reg++);
 457         regs[i].set2(r->as_VMReg());
 458       } else {
 459         regs[i].set2(VMRegImpl::stack2reg(stk_reg_pairs));
 460         stk_reg_pairs += 2;
 461       }
 462       break;
 463 #endif // _LP64
 464 
 465     case T_LONG:
 466       assert(sig_bt[i+1] == T_VOID, "expecting VOID in other half");
 467 #ifdef _LP64
 468         if (int_reg < int_reg_max) {
 469           Register r = is_outgoing ? as_oRegister(int_reg++) : as_iRegister(int_reg++);
 470           regs[i].set2(r->as_VMReg());
 471         } else {
 472           regs[i].set2(VMRegImpl::stack2reg(stk_reg_pairs));
 473           stk_reg_pairs += 2;
 474         }
 475 #else
 476 #ifdef COMPILER2
 477         // For 32-bit build, can't pass longs in O-regs because they become
 478         // I-regs and get trashed.  Use G-regs instead.  G1 and G4 are almost
 479         // spare and available.  This convention isn't used by the Sparc ABI or
 480         // anywhere else. If we're tiered then we don't use G-regs because c1
 481         // can't deal with them as a "pair". (Tiered makes this code think g's are filled)
 482         // G0: zero
 483         // G1: 1st Long arg
 484         // G2: global allocated to TLS
 485         // G3: used in inline cache check
 486         // G4: 2nd Long arg
 487         // G5: used in inline cache check
 488         // G6: used by OS
 489         // G7: used by OS
 490 
 491         if (g_reg == G1) {
 492           regs[i].set2(G1->as_VMReg()); // This long arg in G1
 493           g_reg = G4;                  // Where the next arg goes
 494         } else if (g_reg == G4) {
 495           regs[i].set2(G4->as_VMReg()); // The 2nd long arg in G4
 496           g_reg = noreg;               // No more longs in registers
 497         } else {
 498           regs[i].set2(VMRegImpl::stack2reg(stk_reg_pairs));
 499           stk_reg_pairs += 2;
 500         }
 501 #else // COMPILER2
 502         if (int_reg_pairs + 1 < int_reg_max) {
 503           if (is_outgoing) {
 504             regs[i].set_pair(as_oRegister(int_reg_pairs + 1)->as_VMReg(), as_oRegister(int_reg_pairs)->as_VMReg());
 505           } else {
 506             regs[i].set_pair(as_iRegister(int_reg_pairs + 1)->as_VMReg(), as_iRegister(int_reg_pairs)->as_VMReg());
 507           }
 508           int_reg_pairs += 2;
 509         } else {
 510           regs[i].set2(VMRegImpl::stack2reg(stk_reg_pairs));
 511           stk_reg_pairs += 2;
 512         }
 513 #endif // COMPILER2
 514 #endif // _LP64
 515       break;
 516 
 517     case T_FLOAT:
 518       if (flt_reg < flt_reg_max) regs[i].set1(as_FloatRegister(flt_reg++)->as_VMReg());
 519       else                       regs[i].set1(    VMRegImpl::stack2reg(stk_reg++));
 520       break;
 521     case T_DOUBLE:
 522       assert(sig_bt[i+1] == T_VOID, "expecting half");
 523       if (flt_reg_pairs + 1 < flt_reg_max) {
 524         regs[i].set2(as_FloatRegister(flt_reg_pairs)->as_VMReg());
 525         flt_reg_pairs += 2;
 526       } else {
 527         regs[i].set2(VMRegImpl::stack2reg(stk_reg_pairs));
 528         stk_reg_pairs += 2;
 529       }
 530       break;
 531     case T_VOID: regs[i].set_bad();  break; // Halves of longs & doubles
 532     default:
 533       ShouldNotReachHere();
 534     }
 535   }
 536 
 537   // retun the amount of stack space these arguments will need.
 538   return stk_reg_pairs;
 539 
 540 }
 541 
 542 // Helper class mostly to avoid passing masm everywhere, and handle
 543 // store displacement overflow logic.
 544 class AdapterGenerator {
 545   MacroAssembler *masm;
 546   Register Rdisp;
 547   void set_Rdisp(Register r)  { Rdisp = r; }
 548 
 549   void patch_callers_callsite();
 550   void tag_c2i_arg(frame::Tag t, Register base, int st_off, Register scratch);
 551 
 552   // base+st_off points to top of argument
 553   int arg_offset(const int st_off) { return st_off + Interpreter::value_offset_in_bytes(); }
 554   int next_arg_offset(const int st_off) {
 555     return st_off - Interpreter::stackElementSize() + Interpreter::value_offset_in_bytes();
 556   }
 557 
 558   int tag_offset(const int st_off) { return st_off + Interpreter::tag_offset_in_bytes(); }
 559   int next_tag_offset(const int st_off) {
 560     return st_off - Interpreter::stackElementSize() + Interpreter::tag_offset_in_bytes();
 561   }
 562 
 563   // Argument slot values may be loaded first into a register because
 564   // they might not fit into displacement.
 565   RegisterOrConstant arg_slot(const int st_off);
 566   RegisterOrConstant next_arg_slot(const int st_off);
 567 
 568   RegisterOrConstant tag_slot(const int st_off);
 569   RegisterOrConstant next_tag_slot(const int st_off);
 570 
 571   // Stores long into offset pointed to by base
 572   void store_c2i_long(Register r, Register base,
 573                       const int st_off, bool is_stack);
 574   void store_c2i_object(Register r, Register base,
 575                         const int st_off);
 576   void store_c2i_int(Register r, Register base,
 577                      const int st_off);
 578   void store_c2i_double(VMReg r_2,
 579                         VMReg r_1, Register base, const int st_off);
 580   void store_c2i_float(FloatRegister f, Register base,
 581                        const int st_off);
 582 
 583  public:
 584   void gen_c2i_adapter(int total_args_passed,
 585                               // VMReg max_arg,
 586                               int comp_args_on_stack, // VMRegStackSlots
 587                               const BasicType *sig_bt,
 588                               const VMRegPair *regs,
 589                               Label& skip_fixup);
 590   void gen_i2c_adapter(int total_args_passed,
 591                               // VMReg max_arg,
 592                               int comp_args_on_stack, // VMRegStackSlots
 593                               const BasicType *sig_bt,
 594                               const VMRegPair *regs);
 595 
 596   AdapterGenerator(MacroAssembler *_masm) : masm(_masm) {}
 597 };
 598 
 599 
 600 // Patch the callers callsite with entry to compiled code if it exists.
 601 void AdapterGenerator::patch_callers_callsite() {
 602   Label L;
 603   __ ld_ptr(G5_method, in_bytes(methodOopDesc::code_offset()), G3_scratch);
 604   __ br_null(G3_scratch, false, __ pt, L);
 605   // Schedule the branch target address early.
 606   __ delayed()->ld_ptr(G5_method, in_bytes(methodOopDesc::interpreter_entry_offset()), G3_scratch);
 607   // Call into the VM to patch the caller, then jump to compiled callee
 608   __ save_frame(4);     // Args in compiled layout; do not blow them
 609 
 610   // Must save all the live Gregs the list is:
 611   // G1: 1st Long arg (32bit build)
 612   // G2: global allocated to TLS
 613   // G3: used in inline cache check (scratch)
 614   // G4: 2nd Long arg (32bit build);
 615   // G5: used in inline cache check (methodOop)
 616 
 617   // The longs must go to the stack by hand since in the 32 bit build they can be trashed by window ops.
 618 
 619 #ifdef _LP64
 620   // mov(s,d)
 621   __ mov(G1, L1);
 622   __ mov(G4, L4);
 623   __ mov(G5_method, L5);
 624   __ mov(G5_method, O0);         // VM needs target method
 625   __ mov(I7, O1);                // VM needs caller's callsite
 626   // Must be a leaf call...
 627   // can be very far once the blob has been relocated
 628   AddressLiteral dest(CAST_FROM_FN_PTR(address, SharedRuntime::fixup_callers_callsite));
 629   __ relocate(relocInfo::runtime_call_type);
 630   __ jumpl_to(dest, O7, O7);
 631   __ delayed()->mov(G2_thread, L7_thread_cache);
 632   __ mov(L7_thread_cache, G2_thread);
 633   __ mov(L1, G1);
 634   __ mov(L4, G4);
 635   __ mov(L5, G5_method);
 636 #else
 637   __ stx(G1, FP, -8 + STACK_BIAS);
 638   __ stx(G4, FP, -16 + STACK_BIAS);
 639   __ mov(G5_method, L5);
 640   __ mov(G5_method, O0);         // VM needs target method
 641   __ mov(I7, O1);                // VM needs caller's callsite
 642   // Must be a leaf call...
 643   __ call(CAST_FROM_FN_PTR(address, SharedRuntime::fixup_callers_callsite), relocInfo::runtime_call_type);
 644   __ delayed()->mov(G2_thread, L7_thread_cache);
 645   __ mov(L7_thread_cache, G2_thread);
 646   __ ldx(FP, -8 + STACK_BIAS, G1);
 647   __ ldx(FP, -16 + STACK_BIAS, G4);
 648   __ mov(L5, G5_method);
 649   __ ld_ptr(G5_method, in_bytes(methodOopDesc::interpreter_entry_offset()), G3_scratch);
 650 #endif /* _LP64 */
 651 
 652   __ restore();      // Restore args
 653   __ bind(L);
 654 }
 655 
 656 void AdapterGenerator::tag_c2i_arg(frame::Tag t, Register base, int st_off,
 657                  Register scratch) {
 658   if (TaggedStackInterpreter) {
 659     RegisterOrConstant slot = tag_slot(st_off);
 660     // have to store zero because local slots can be reused (rats!)
 661     if (t == frame::TagValue) {
 662       __ st_ptr(G0, base, slot);
 663     } else if (t == frame::TagCategory2) {
 664       __ st_ptr(G0, base, slot);
 665       __ st_ptr(G0, base, next_tag_slot(st_off));
 666     } else {
 667       __ mov(t, scratch);
 668       __ st_ptr(scratch, base, slot);
 669     }
 670   }
 671 }
 672 
 673 
 674 RegisterOrConstant AdapterGenerator::arg_slot(const int st_off) {
 675   RegisterOrConstant roc(arg_offset(st_off));
 676   return __ ensure_simm13_or_reg(roc, Rdisp);
 677 }
 678 
 679 RegisterOrConstant AdapterGenerator::next_arg_slot(const int st_off) {
 680   RegisterOrConstant roc(next_arg_offset(st_off));
 681   return __ ensure_simm13_or_reg(roc, Rdisp);
 682 }
 683 
 684 
 685 RegisterOrConstant AdapterGenerator::tag_slot(const int st_off) {
 686   RegisterOrConstant roc(tag_offset(st_off));
 687   return __ ensure_simm13_or_reg(roc, Rdisp);
 688 }
 689 
 690 RegisterOrConstant AdapterGenerator::next_tag_slot(const int st_off) {
 691   RegisterOrConstant roc(next_tag_offset(st_off));
 692   return __ ensure_simm13_or_reg(roc, Rdisp);
 693 }
 694 
 695 
 696 // Stores long into offset pointed to by base
 697 void AdapterGenerator::store_c2i_long(Register r, Register base,
 698                                       const int st_off, bool is_stack) {
 699 #ifdef _LP64
 700   // In V9, longs are given 2 64-bit slots in the interpreter, but the
 701   // data is passed in only 1 slot.
 702   __ stx(r, base, next_arg_slot(st_off));
 703 #else
 704 #ifdef COMPILER2
 705   // Misaligned store of 64-bit data
 706   __ stw(r, base, arg_slot(st_off));    // lo bits
 707   __ srlx(r, 32, r);
 708   __ stw(r, base, next_arg_slot(st_off));  // hi bits
 709 #else
 710   if (is_stack) {
 711     // Misaligned store of 64-bit data
 712     __ stw(r, base, arg_slot(st_off));    // lo bits
 713     __ srlx(r, 32, r);
 714     __ stw(r, base, next_arg_slot(st_off));  // hi bits
 715   } else {
 716     __ stw(r->successor(), base, arg_slot(st_off)     ); // lo bits
 717     __ stw(r             , base, next_arg_slot(st_off)); // hi bits
 718   }
 719 #endif // COMPILER2
 720 #endif // _LP64
 721   tag_c2i_arg(frame::TagCategory2, base, st_off, r);
 722 }
 723 
 724 void AdapterGenerator::store_c2i_object(Register r, Register base,
 725                       const int st_off) {
 726   __ st_ptr (r, base, arg_slot(st_off));
 727   tag_c2i_arg(frame::TagReference, base, st_off, r);
 728 }
 729 
 730 void AdapterGenerator::store_c2i_int(Register r, Register base,
 731                    const int st_off) {
 732   __ st (r, base, arg_slot(st_off));
 733   tag_c2i_arg(frame::TagValue, base, st_off, r);
 734 }
 735 
 736 // Stores into offset pointed to by base
 737 void AdapterGenerator::store_c2i_double(VMReg r_2,
 738                       VMReg r_1, Register base, const int st_off) {
 739 #ifdef _LP64
 740   // In V9, doubles are given 2 64-bit slots in the interpreter, but the
 741   // data is passed in only 1 slot.
 742   __ stf(FloatRegisterImpl::D, r_1->as_FloatRegister(), base, next_arg_slot(st_off));
 743 #else
 744   // Need to marshal 64-bit value from misaligned Lesp loads
 745   __ stf(FloatRegisterImpl::S, r_1->as_FloatRegister(), base, next_arg_slot(st_off));
 746   __ stf(FloatRegisterImpl::S, r_2->as_FloatRegister(), base, arg_slot(st_off) );
 747 #endif
 748   tag_c2i_arg(frame::TagCategory2, base, st_off, G1_scratch);
 749 }
 750 
 751 void AdapterGenerator::store_c2i_float(FloatRegister f, Register base,
 752                                        const int st_off) {
 753   __ stf(FloatRegisterImpl::S, f, base, arg_slot(st_off));
 754   tag_c2i_arg(frame::TagValue, base, st_off, G1_scratch);
 755 }
 756 
 757 void AdapterGenerator::gen_c2i_adapter(
 758                             int total_args_passed,
 759                             // VMReg max_arg,
 760                             int comp_args_on_stack, // VMRegStackSlots
 761                             const BasicType *sig_bt,
 762                             const VMRegPair *regs,
 763                             Label& skip_fixup) {
 764 
 765   // Before we get into the guts of the C2I adapter, see if we should be here
 766   // at all.  We've come from compiled code and are attempting to jump to the
 767   // interpreter, which means the caller made a static call to get here
 768   // (vcalls always get a compiled target if there is one).  Check for a
 769   // compiled target.  If there is one, we need to patch the caller's call.
 770   // However we will run interpreted if we come thru here. The next pass
 771   // thru the call site will run compiled. If we ran compiled here then
 772   // we can (theorectically) do endless i2c->c2i->i2c transitions during
 773   // deopt/uncommon trap cycles. If we always go interpreted here then
 774   // we can have at most one and don't need to play any tricks to keep
 775   // from endlessly growing the stack.
 776   //
 777   // Actually if we detected that we had an i2c->c2i transition here we
 778   // ought to be able to reset the world back to the state of the interpreted
 779   // call and not bother building another interpreter arg area. We don't
 780   // do that at this point.
 781 
 782   patch_callers_callsite();
 783 
 784   __ bind(skip_fixup);
 785 
 786   // Since all args are passed on the stack, total_args_passed*wordSize is the
 787   // space we need.  Add in varargs area needed by the interpreter. Round up
 788   // to stack alignment.
 789   const int arg_size = total_args_passed * Interpreter::stackElementSize();
 790   const int varargs_area =
 791                  (frame::varargs_offset - frame::register_save_words)*wordSize;
 792   const int extraspace = round_to(arg_size + varargs_area, 2*wordSize);
 793 
 794   int bias = STACK_BIAS;
 795   const int interp_arg_offset = frame::varargs_offset*wordSize +
 796                         (total_args_passed-1)*Interpreter::stackElementSize();
 797 
 798   Register base = SP;
 799 
 800 #ifdef _LP64
 801   // In the 64bit build because of wider slots and STACKBIAS we can run
 802   // out of bits in the displacement to do loads and stores.  Use g3 as
 803   // temporary displacement.
 804   if (! __ is_simm13(extraspace)) {
 805     __ set(extraspace, G3_scratch);
 806     __ sub(SP, G3_scratch, SP);
 807   } else {
 808     __ sub(SP, extraspace, SP);
 809   }
 810   set_Rdisp(G3_scratch);
 811 #else
 812   __ sub(SP, extraspace, SP);
 813 #endif // _LP64
 814 
 815   // First write G1 (if used) to where ever it must go
 816   for (int i=0; i<total_args_passed; i++) {
 817     const int st_off = interp_arg_offset - (i*Interpreter::stackElementSize()) + bias;
 818     VMReg r_1 = regs[i].first();
 819     VMReg r_2 = regs[i].second();
 820     if (r_1 == G1_scratch->as_VMReg()) {
 821       if (sig_bt[i] == T_OBJECT || sig_bt[i] == T_ARRAY) {
 822         store_c2i_object(G1_scratch, base, st_off);
 823       } else if (sig_bt[i] == T_LONG) {
 824         assert(!TieredCompilation, "should not use register args for longs");
 825         store_c2i_long(G1_scratch, base, st_off, false);
 826       } else {
 827         store_c2i_int(G1_scratch, base, st_off);
 828       }
 829     }
 830   }
 831 
 832   // Now write the args into the outgoing interpreter space
 833   for (int i=0; i<total_args_passed; i++) {
 834     const int st_off = interp_arg_offset - (i*Interpreter::stackElementSize()) + bias;
 835     VMReg r_1 = regs[i].first();
 836     VMReg r_2 = regs[i].second();
 837     if (!r_1->is_valid()) {
 838       assert(!r_2->is_valid(), "");
 839       continue;
 840     }
 841     // Skip G1 if found as we did it first in order to free it up
 842     if (r_1 == G1_scratch->as_VMReg()) {
 843       continue;
 844     }
 845 #ifdef ASSERT
 846     bool G1_forced = false;
 847 #endif // ASSERT
 848     if (r_1->is_stack()) {        // Pretend stack targets are loaded into G1
 849 #ifdef _LP64
 850       Register ld_off = Rdisp;
 851       __ set(reg2offset(r_1) + extraspace + bias, ld_off);
 852 #else
 853       int ld_off = reg2offset(r_1) + extraspace + bias;
 854 #endif // _LP64
 855 #ifdef ASSERT
 856       G1_forced = true;
 857 #endif // ASSERT
 858       r_1 = G1_scratch->as_VMReg();// as part of the load/store shuffle
 859       if (!r_2->is_valid()) __ ld (base, ld_off, G1_scratch);
 860       else                  __ ldx(base, ld_off, G1_scratch);
 861     }
 862 
 863     if (r_1->is_Register()) {
 864       Register r = r_1->as_Register()->after_restore();
 865       if (sig_bt[i] == T_OBJECT || sig_bt[i] == T_ARRAY) {
 866         store_c2i_object(r, base, st_off);
 867       } else if (sig_bt[i] == T_LONG || sig_bt[i] == T_DOUBLE) {
 868 #ifndef _LP64
 869         if (TieredCompilation) {
 870           assert(G1_forced || sig_bt[i] != T_LONG, "should not use register args for longs");
 871         }
 872 #endif // _LP64
 873         store_c2i_long(r, base, st_off, r_2->is_stack());
 874       } else {
 875         store_c2i_int(r, base, st_off);
 876       }
 877     } else {
 878       assert(r_1->is_FloatRegister(), "");
 879       if (sig_bt[i] == T_FLOAT) {
 880         store_c2i_float(r_1->as_FloatRegister(), base, st_off);
 881       } else {
 882         assert(sig_bt[i] == T_DOUBLE, "wrong type");
 883         store_c2i_double(r_2, r_1, base, st_off);
 884       }
 885     }
 886   }
 887 
 888 #ifdef _LP64
 889   // Need to reload G3_scratch, used for temporary displacements.
 890   __ ld_ptr(G5_method, in_bytes(methodOopDesc::interpreter_entry_offset()), G3_scratch);
 891 
 892   // Pass O5_savedSP as an argument to the interpreter.
 893   // The interpreter will restore SP to this value before returning.
 894   __ set(extraspace, G1);
 895   __ add(SP, G1, O5_savedSP);
 896 #else
 897   // Pass O5_savedSP as an argument to the interpreter.
 898   // The interpreter will restore SP to this value before returning.
 899   __ add(SP, extraspace, O5_savedSP);
 900 #endif // _LP64
 901 
 902   __ mov((frame::varargs_offset)*wordSize -
 903          1*Interpreter::stackElementSize()+bias+BytesPerWord, G1);
 904   // Jump to the interpreter just as if interpreter was doing it.
 905   __ jmpl(G3_scratch, 0, G0);
 906   // Setup Lesp for the call.  Cannot actually set Lesp as the current Lesp
 907   // (really L0) is in use by the compiled frame as a generic temp.  However,
 908   // the interpreter does not know where its args are without some kind of
 909   // arg pointer being passed in.  Pass it in Gargs.
 910   __ delayed()->add(SP, G1, Gargs);
 911 }
 912 
 913 void AdapterGenerator::gen_i2c_adapter(
 914                             int total_args_passed,
 915                             // VMReg max_arg,
 916                             int comp_args_on_stack, // VMRegStackSlots
 917                             const BasicType *sig_bt,
 918                             const VMRegPair *regs) {
 919 
 920   // Generate an I2C adapter: adjust the I-frame to make space for the C-frame
 921   // layout.  Lesp was saved by the calling I-frame and will be restored on
 922   // return.  Meanwhile, outgoing arg space is all owned by the callee
 923   // C-frame, so we can mangle it at will.  After adjusting the frame size,
 924   // hoist register arguments and repack other args according to the compiled
 925   // code convention.  Finally, end in a jump to the compiled code.  The entry
 926   // point address is the start of the buffer.
 927 
 928   // We will only enter here from an interpreted frame and never from after
 929   // passing thru a c2i. Azul allowed this but we do not. If we lose the
 930   // race and use a c2i we will remain interpreted for the race loser(s).
 931   // This removes all sorts of headaches on the x86 side and also eliminates
 932   // the possibility of having c2i -> i2c -> c2i -> ... endless transitions.
 933 
 934   // As you can see from the list of inputs & outputs there are not a lot
 935   // of temp registers to work with: mostly G1, G3 & G4.
 936 
 937   // Inputs:
 938   // G2_thread      - TLS
 939   // G5_method      - Method oop
 940   // G4 (Gargs)     - Pointer to interpreter's args
 941   // O0..O4         - free for scratch
 942   // O5_savedSP     - Caller's saved SP, to be restored if needed
 943   // O6             - Current SP!
 944   // O7             - Valid return address
 945   // L0-L7, I0-I7   - Caller's temps (no frame pushed yet)
 946 
 947   // Outputs:
 948   // G2_thread      - TLS
 949   // G1, G4         - Outgoing long args in 32-bit build
 950   // O0-O5          - Outgoing args in compiled layout
 951   // O6             - Adjusted or restored SP
 952   // O7             - Valid return address
 953   // L0-L7, I0-I7    - Caller's temps (no frame pushed yet)
 954   // F0-F7          - more outgoing args
 955 
 956 
 957   // Gargs is the incoming argument base, and also an outgoing argument.
 958   __ sub(Gargs, BytesPerWord, Gargs);
 959 
 960 #ifdef ASSERT
 961   {
 962     // on entry OsavedSP and SP should be equal
 963     Label ok;
 964     __ cmp(O5_savedSP, SP);
 965     __ br(Assembler::equal, false, Assembler::pt, ok);
 966     __ delayed()->nop();
 967     __ stop("I5_savedSP not set");
 968     __ should_not_reach_here();
 969     __ bind(ok);
 970   }
 971 #endif
 972 
 973   // ON ENTRY TO THE CODE WE ARE MAKING, WE HAVE AN INTERPRETED FRAME
 974   // WITH O7 HOLDING A VALID RETURN PC
 975   //
 976   // |              |
 977   // :  java stack  :
 978   // |              |
 979   // +--------------+ <--- start of outgoing args
 980   // |   receiver   |   |
 981   // : rest of args :   |---size is java-arg-words
 982   // |              |   |
 983   // +--------------+ <--- O4_args (misaligned) and Lesp if prior is not C2I
 984   // |              |   |
 985   // :    unused    :   |---Space for max Java stack, plus stack alignment
 986   // |              |   |
 987   // +--------------+ <--- SP + 16*wordsize
 988   // |              |
 989   // :    window    :
 990   // |              |
 991   // +--------------+ <--- SP
 992 
 993   // WE REPACK THE STACK.  We use the common calling convention layout as
 994   // discovered by calling SharedRuntime::calling_convention.  We assume it
 995   // causes an arbitrary shuffle of memory, which may require some register
 996   // temps to do the shuffle.  We hope for (and optimize for) the case where
 997   // temps are not needed.  We may have to resize the stack slightly, in case
 998   // we need alignment padding (32-bit interpreter can pass longs & doubles
 999   // misaligned, but the compilers expect them aligned).
1000   //
1001   // |              |
1002   // :  java stack  :
1003   // |              |
1004   // +--------------+ <--- start of outgoing args
1005   // |  pad, align  |   |
1006   // +--------------+   |
1007   // | ints, floats |   |---Outgoing stack args, packed low.
1008   // +--------------+   |   First few args in registers.
1009   // :   doubles    :   |
1010   // |   longs      |   |
1011   // +--------------+ <--- SP' + 16*wordsize
1012   // |              |
1013   // :    window    :
1014   // |              |
1015   // +--------------+ <--- SP'
1016 
1017   // ON EXIT FROM THE CODE WE ARE MAKING, WE STILL HAVE AN INTERPRETED FRAME
1018   // WITH O7 HOLDING A VALID RETURN PC - ITS JUST THAT THE ARGS ARE NOW SETUP
1019   // FOR COMPILED CODE AND THE FRAME SLIGHTLY GROWN.
1020 
1021   // Cut-out for having no stack args.  Since up to 6 args are passed
1022   // in registers, we will commonly have no stack args.
1023   if (comp_args_on_stack > 0) {
1024 
1025     // Convert VMReg stack slots to words.
1026     int comp_words_on_stack = round_to(comp_args_on_stack*VMRegImpl::stack_slot_size, wordSize)>>LogBytesPerWord;
1027     // Round up to miminum stack alignment, in wordSize
1028     comp_words_on_stack = round_to(comp_words_on_stack, 2);
1029     // Now compute the distance from Lesp to SP.  This calculation does not
1030     // include the space for total_args_passed because Lesp has not yet popped
1031     // the arguments.
1032     __ sub(SP, (comp_words_on_stack)*wordSize, SP);
1033   }
1034 
1035   // Will jump to the compiled code just as if compiled code was doing it.
1036   // Pre-load the register-jump target early, to schedule it better.
1037   __ ld_ptr(G5_method, in_bytes(methodOopDesc::from_compiled_offset()), G3);
1038 
1039   // Now generate the shuffle code.  Pick up all register args and move the
1040   // rest through G1_scratch.
1041   for (int i=0; i<total_args_passed; i++) {
1042     if (sig_bt[i] == T_VOID) {
1043       // Longs and doubles are passed in native word order, but misaligned
1044       // in the 32-bit build.
1045       assert(i > 0 && (sig_bt[i-1] == T_LONG || sig_bt[i-1] == T_DOUBLE), "missing half");
1046       continue;
1047     }
1048 
1049     // Pick up 0, 1 or 2 words from Lesp+offset.  Assume mis-aligned in the
1050     // 32-bit build and aligned in the 64-bit build.  Look for the obvious
1051     // ldx/lddf optimizations.
1052 
1053     // Load in argument order going down.
1054     const int ld_off = (total_args_passed-i)*Interpreter::stackElementSize();
1055     set_Rdisp(G1_scratch);
1056 
1057     VMReg r_1 = regs[i].first();
1058     VMReg r_2 = regs[i].second();
1059     if (!r_1->is_valid()) {
1060       assert(!r_2->is_valid(), "");
1061       continue;
1062     }
1063     if (r_1->is_stack()) {        // Pretend stack targets are loaded into F8/F9
1064       r_1 = F8->as_VMReg();        // as part of the load/store shuffle
1065       if (r_2->is_valid()) r_2 = r_1->next();
1066     }
1067     if (r_1->is_Register()) {  // Register argument
1068       Register r = r_1->as_Register()->after_restore();
1069       if (!r_2->is_valid()) {
1070         __ ld(Gargs, arg_slot(ld_off), r);
1071       } else {
1072 #ifdef _LP64
1073         // In V9, longs are given 2 64-bit slots in the interpreter, but the
1074         // data is passed in only 1 slot.
1075         RegisterOrConstant slot = (sig_bt[i] == T_LONG) ?
1076               next_arg_slot(ld_off) : arg_slot(ld_off);
1077         __ ldx(Gargs, slot, r);
1078 #else
1079         // Need to load a 64-bit value into G1/G4, but G1/G4 is being used in the
1080         // stack shuffle.  Load the first 2 longs into G1/G4 later.
1081 #endif
1082       }
1083     } else {
1084       assert(r_1->is_FloatRegister(), "");
1085       if (!r_2->is_valid()) {
1086         __ ldf(FloatRegisterImpl::S, Gargs, arg_slot(ld_off), r_1->as_FloatRegister());
1087       } else {
1088 #ifdef _LP64
1089         // In V9, doubles are given 2 64-bit slots in the interpreter, but the
1090         // data is passed in only 1 slot.  This code also handles longs that
1091         // are passed on the stack, but need a stack-to-stack move through a
1092         // spare float register.
1093         RegisterOrConstant slot = (sig_bt[i] == T_LONG || sig_bt[i] == T_DOUBLE) ?
1094               next_arg_slot(ld_off) : arg_slot(ld_off);
1095         __ ldf(FloatRegisterImpl::D, Gargs, slot, r_1->as_FloatRegister());
1096 #else
1097         // Need to marshal 64-bit value from misaligned Lesp loads
1098         __ ldf(FloatRegisterImpl::S, Gargs, next_arg_slot(ld_off), r_1->as_FloatRegister());
1099         __ ldf(FloatRegisterImpl::S, Gargs, arg_slot(ld_off), r_2->as_FloatRegister());
1100 #endif
1101       }
1102     }
1103     // Was the argument really intended to be on the stack, but was loaded
1104     // into F8/F9?
1105     if (regs[i].first()->is_stack()) {
1106       assert(r_1->as_FloatRegister() == F8, "fix this code");
1107       // Convert stack slot to an SP offset
1108       int st_off = reg2offset(regs[i].first()) + STACK_BIAS;
1109       // Store down the shuffled stack word.  Target address _is_ aligned.
1110       RegisterOrConstant slot = __ ensure_simm13_or_reg(st_off, Rdisp);
1111       if (!r_2->is_valid()) __ stf(FloatRegisterImpl::S, r_1->as_FloatRegister(), SP, slot);
1112       else                  __ stf(FloatRegisterImpl::D, r_1->as_FloatRegister(), SP, slot);
1113     }
1114   }
1115   bool made_space = false;
1116 #ifndef _LP64
1117   // May need to pick up a few long args in G1/G4
1118   bool g4_crushed = false;
1119   bool g3_crushed = false;
1120   for (int i=0; i<total_args_passed; i++) {
1121     if (regs[i].first()->is_Register() && regs[i].second()->is_valid()) {
1122       // Load in argument order going down
1123       int ld_off = (total_args_passed-i)*Interpreter::stackElementSize();
1124       // Need to marshal 64-bit value from misaligned Lesp loads
1125       Register r = regs[i].first()->as_Register()->after_restore();
1126       if (r == G1 || r == G4) {
1127         assert(!g4_crushed, "ordering problem");
1128         if (r == G4){
1129           g4_crushed = true;
1130           __ lduw(Gargs, arg_slot(ld_off)     , G3_scratch); // Load lo bits
1131           __ ld  (Gargs, next_arg_slot(ld_off), r);          // Load hi bits
1132         } else {
1133           // better schedule this way
1134           __ ld  (Gargs, next_arg_slot(ld_off), r);          // Load hi bits
1135           __ lduw(Gargs, arg_slot(ld_off)     , G3_scratch); // Load lo bits
1136         }
1137         g3_crushed = true;
1138         __ sllx(r, 32, r);
1139         __ or3(G3_scratch, r, r);
1140       } else {
1141         assert(r->is_out(), "longs passed in two O registers");
1142         __ ld  (Gargs, arg_slot(ld_off)     , r->successor()); // Load lo bits
1143         __ ld  (Gargs, next_arg_slot(ld_off), r);              // Load hi bits
1144       }
1145     }
1146   }
1147 #endif
1148 
1149   // Jump to the compiled code just as if compiled code was doing it.
1150   //
1151 #ifndef _LP64
1152     if (g3_crushed) {
1153       // Rats load was wasted, at least it is in cache...
1154       __ ld_ptr(G5_method, methodOopDesc::from_compiled_offset(), G3);
1155     }
1156 #endif /* _LP64 */
1157 
1158     // 6243940 We might end up in handle_wrong_method if
1159     // the callee is deoptimized as we race thru here. If that
1160     // happens we don't want to take a safepoint because the
1161     // caller frame will look interpreted and arguments are now
1162     // "compiled" so it is much better to make this transition
1163     // invisible to the stack walking code. Unfortunately if
1164     // we try and find the callee by normal means a safepoint
1165     // is possible. So we stash the desired callee in the thread
1166     // and the vm will find there should this case occur.
1167     Address callee_target_addr(G2_thread, JavaThread::callee_target_offset());
1168     __ st_ptr(G5_method, callee_target_addr);
1169 
1170     if (StressNonEntrant) {
1171       // Open a big window for deopt failure
1172       __ save_frame(0);
1173       __ mov(G0, L0);
1174       Label loop;
1175       __ bind(loop);
1176       __ sub(L0, 1, L0);
1177       __ br_null(L0, false, Assembler::pt, loop);
1178       __ delayed()->nop();
1179 
1180       __ restore();
1181     }
1182 
1183 
1184     __ jmpl(G3, 0, G0);
1185     __ delayed()->nop();
1186 }
1187 
1188 // ---------------------------------------------------------------
1189 AdapterHandlerEntry* SharedRuntime::generate_i2c2i_adapters(MacroAssembler *masm,
1190                                                             int total_args_passed,
1191                                                             // VMReg max_arg,
1192                                                             int comp_args_on_stack, // VMRegStackSlots
1193                                                             const BasicType *sig_bt,
1194                                                             const VMRegPair *regs,
1195                                                             AdapterFingerPrint* fingerprint) {
1196   address i2c_entry = __ pc();
1197 
1198   AdapterGenerator agen(masm);
1199 
1200   agen.gen_i2c_adapter(total_args_passed, comp_args_on_stack, sig_bt, regs);
1201 
1202 
1203   // -------------------------------------------------------------------------
1204   // Generate a C2I adapter.  On entry we know G5 holds the methodOop.  The
1205   // args start out packed in the compiled layout.  They need to be unpacked
1206   // into the interpreter layout.  This will almost always require some stack
1207   // space.  We grow the current (compiled) stack, then repack the args.  We
1208   // finally end in a jump to the generic interpreter entry point.  On exit
1209   // from the interpreter, the interpreter will restore our SP (lest the
1210   // compiled code, which relys solely on SP and not FP, get sick).
1211 
1212   address c2i_unverified_entry = __ pc();
1213   Label skip_fixup;
1214   {
1215 #if !defined(_LP64) && defined(COMPILER2)
1216     Register R_temp   = L0;   // another scratch register
1217 #else
1218     Register R_temp   = G1;   // another scratch register
1219 #endif
1220 
1221     AddressLiteral ic_miss(SharedRuntime::get_ic_miss_stub());
1222 
1223     __ verify_oop(O0);
1224     __ verify_oop(G5_method);
1225     __ load_klass(O0, G3_scratch);
1226     __ verify_oop(G3_scratch);
1227 
1228 #if !defined(_LP64) && defined(COMPILER2)
1229     __ save(SP, -frame::register_save_words*wordSize, SP);
1230     __ ld_ptr(G5_method, compiledICHolderOopDesc::holder_klass_offset(), R_temp);
1231     __ verify_oop(R_temp);
1232     __ cmp(G3_scratch, R_temp);
1233     __ restore();
1234 #else
1235     __ ld_ptr(G5_method, compiledICHolderOopDesc::holder_klass_offset(), R_temp);
1236     __ verify_oop(R_temp);
1237     __ cmp(G3_scratch, R_temp);
1238 #endif
1239 
1240     Label ok, ok2;
1241     __ brx(Assembler::equal, false, Assembler::pt, ok);
1242     __ delayed()->ld_ptr(G5_method, compiledICHolderOopDesc::holder_method_offset(), G5_method);
1243     __ jump_to(ic_miss, G3_scratch);
1244     __ delayed()->nop();
1245 
1246     __ bind(ok);
1247     // Method might have been compiled since the call site was patched to
1248     // interpreted if that is the case treat it as a miss so we can get
1249     // the call site corrected.
1250     __ ld_ptr(G5_method, in_bytes(methodOopDesc::code_offset()), G3_scratch);
1251     __ bind(ok2);
1252     __ br_null(G3_scratch, false, __ pt, skip_fixup);
1253     __ delayed()->ld_ptr(G5_method, in_bytes(methodOopDesc::interpreter_entry_offset()), G3_scratch);
1254     __ jump_to(ic_miss, G3_scratch);
1255     __ delayed()->nop();
1256 
1257   }
1258 
1259   address c2i_entry = __ pc();
1260 
1261   agen.gen_c2i_adapter(total_args_passed, comp_args_on_stack, sig_bt, regs, skip_fixup);
1262 
1263   __ flush();
1264   return AdapterHandlerLibrary::new_entry(fingerprint, i2c_entry, c2i_entry, c2i_unverified_entry);
1265 
1266 }
1267 
1268 // Helper function for native calling conventions
1269 static VMReg int_stk_helper( int i ) {
1270   // Bias any stack based VMReg we get by ignoring the window area
1271   // but not the register parameter save area.
1272   //
1273   // This is strange for the following reasons. We'd normally expect
1274   // the calling convention to return an VMReg for a stack slot
1275   // completely ignoring any abi reserved area. C2 thinks of that
1276   // abi area as only out_preserve_stack_slots. This does not include
1277   // the area allocated by the C abi to store down integer arguments
1278   // because the java calling convention does not use it. So
1279   // since c2 assumes that there are only out_preserve_stack_slots
1280   // to bias the optoregs (which impacts VMRegs) when actually referencing any actual stack
1281   // location the c calling convention must add in this bias amount
1282   // to make up for the fact that the out_preserve_stack_slots is
1283   // insufficient for C calls. What a mess. I sure hope those 6
1284   // stack words were worth it on every java call!
1285 
1286   // Another way of cleaning this up would be for out_preserve_stack_slots
1287   // to take a parameter to say whether it was C or java calling conventions.
1288   // Then things might look a little better (but not much).
1289 
1290   int mem_parm_offset = i - SPARC_ARGS_IN_REGS_NUM;
1291   if( mem_parm_offset < 0 ) {
1292     return as_oRegister(i)->as_VMReg();
1293   } else {
1294     int actual_offset = (mem_parm_offset + frame::memory_parameter_word_sp_offset) * VMRegImpl::slots_per_word;
1295     // Now return a biased offset that will be correct when out_preserve_slots is added back in
1296     return VMRegImpl::stack2reg(actual_offset - SharedRuntime::out_preserve_stack_slots());
1297   }
1298 }
1299 
1300 
1301 int SharedRuntime::c_calling_convention(const BasicType *sig_bt,
1302                                          VMRegPair *regs,
1303                                          int total_args_passed) {
1304 
1305     // Return the number of VMReg stack_slots needed for the args.
1306     // This value does not include an abi space (like register window
1307     // save area).
1308 
1309     // The native convention is V8 if !LP64
1310     // The LP64 convention is the V9 convention which is slightly more sane.
1311 
1312     // We return the amount of VMReg stack slots we need to reserve for all
1313     // the arguments NOT counting out_preserve_stack_slots. Since we always
1314     // have space for storing at least 6 registers to memory we start with that.
1315     // See int_stk_helper for a further discussion.
1316     int max_stack_slots = (frame::varargs_offset * VMRegImpl::slots_per_word) - SharedRuntime::out_preserve_stack_slots();
1317 
1318 #ifdef _LP64
1319     // V9 convention: All things "as-if" on double-wide stack slots.
1320     // Hoist any int/ptr/long's in the first 6 to int regs.
1321     // Hoist any flt/dbl's in the first 16 dbl regs.
1322     int j = 0;                  // Count of actual args, not HALVES
1323     for( int i=0; i<total_args_passed; i++, j++ ) {
1324       switch( sig_bt[i] ) {
1325       case T_BOOLEAN:
1326       case T_BYTE:
1327       case T_CHAR:
1328       case T_INT:
1329       case T_SHORT:
1330         regs[i].set1( int_stk_helper( j ) ); break;
1331       case T_LONG:
1332         assert( sig_bt[i+1] == T_VOID, "expecting half" );
1333       case T_ADDRESS: // raw pointers, like current thread, for VM calls
1334       case T_ARRAY:
1335       case T_OBJECT:
1336         regs[i].set2( int_stk_helper( j ) );
1337         break;
1338       case T_FLOAT:
1339         if ( j < 16 ) {
1340           // V9ism: floats go in ODD registers
1341           regs[i].set1(as_FloatRegister(1 + (j<<1))->as_VMReg());
1342         } else {
1343           // V9ism: floats go in ODD stack slot
1344           regs[i].set1(VMRegImpl::stack2reg(1 + (j<<1)));
1345         }
1346         break;
1347       case T_DOUBLE:
1348         assert( sig_bt[i+1] == T_VOID, "expecting half" );
1349         if ( j < 16 ) {
1350           // V9ism: doubles go in EVEN/ODD regs
1351           regs[i].set2(as_FloatRegister(j<<1)->as_VMReg());
1352         } else {
1353           // V9ism: doubles go in EVEN/ODD stack slots
1354           regs[i].set2(VMRegImpl::stack2reg(j<<1));
1355         }
1356         break;
1357       case T_VOID:  regs[i].set_bad(); j--; break; // Do not count HALVES
1358       default:
1359         ShouldNotReachHere();
1360       }
1361       if (regs[i].first()->is_stack()) {
1362         int off =  regs[i].first()->reg2stack();
1363         if (off > max_stack_slots) max_stack_slots = off;
1364       }
1365       if (regs[i].second()->is_stack()) {
1366         int off =  regs[i].second()->reg2stack();
1367         if (off > max_stack_slots) max_stack_slots = off;
1368       }
1369     }
1370 
1371 #else // _LP64
1372     // V8 convention: first 6 things in O-regs, rest on stack.
1373     // Alignment is willy-nilly.
1374     for( int i=0; i<total_args_passed; i++ ) {
1375       switch( sig_bt[i] ) {
1376       case T_ADDRESS: // raw pointers, like current thread, for VM calls
1377       case T_ARRAY:
1378       case T_BOOLEAN:
1379       case T_BYTE:
1380       case T_CHAR:
1381       case T_FLOAT:
1382       case T_INT:
1383       case T_OBJECT:
1384       case T_SHORT:
1385         regs[i].set1( int_stk_helper( i ) );
1386         break;
1387       case T_DOUBLE:
1388       case T_LONG:
1389         assert( sig_bt[i+1] == T_VOID, "expecting half" );
1390         regs[i].set_pair( int_stk_helper( i+1 ), int_stk_helper( i ) );
1391         break;
1392       case T_VOID: regs[i].set_bad(); break;
1393       default:
1394         ShouldNotReachHere();
1395       }
1396       if (regs[i].first()->is_stack()) {
1397         int off =  regs[i].first()->reg2stack();
1398         if (off > max_stack_slots) max_stack_slots = off;
1399       }
1400       if (regs[i].second()->is_stack()) {
1401         int off =  regs[i].second()->reg2stack();
1402         if (off > max_stack_slots) max_stack_slots = off;
1403       }
1404     }
1405 #endif // _LP64
1406 
1407   return round_to(max_stack_slots + 1, 2);
1408 
1409 }
1410 
1411 
1412 // ---------------------------------------------------------------------------
1413 void SharedRuntime::save_native_result(MacroAssembler *masm, BasicType ret_type, int frame_slots) {
1414   switch (ret_type) {
1415   case T_FLOAT:
1416     __ stf(FloatRegisterImpl::S, F0, SP, frame_slots*VMRegImpl::stack_slot_size - 4+STACK_BIAS);
1417     break;
1418   case T_DOUBLE:
1419     __ stf(FloatRegisterImpl::D, F0, SP, frame_slots*VMRegImpl::stack_slot_size - 8+STACK_BIAS);
1420     break;
1421   }
1422 }
1423 
1424 void SharedRuntime::restore_native_result(MacroAssembler *masm, BasicType ret_type, int frame_slots) {
1425   switch (ret_type) {
1426   case T_FLOAT:
1427     __ ldf(FloatRegisterImpl::S, SP, frame_slots*VMRegImpl::stack_slot_size - 4+STACK_BIAS, F0);
1428     break;
1429   case T_DOUBLE:
1430     __ ldf(FloatRegisterImpl::D, SP, frame_slots*VMRegImpl::stack_slot_size - 8+STACK_BIAS, F0);
1431     break;
1432   }
1433 }
1434 
1435 // Check and forward and pending exception.  Thread is stored in
1436 // L7_thread_cache and possibly NOT in G2_thread.  Since this is a native call, there
1437 // is no exception handler.  We merely pop this frame off and throw the
1438 // exception in the caller's frame.
1439 static void check_forward_pending_exception(MacroAssembler *masm, Register Rex_oop) {
1440   Label L;
1441   __ br_null(Rex_oop, false, Assembler::pt, L);
1442   __ delayed()->mov(L7_thread_cache, G2_thread); // restore in case we have exception
1443   // Since this is a native call, we *know* the proper exception handler
1444   // without calling into the VM: it's the empty function.  Just pop this
1445   // frame and then jump to forward_exception_entry; O7 will contain the
1446   // native caller's return PC.
1447  AddressLiteral exception_entry(StubRoutines::forward_exception_entry());
1448   __ jump_to(exception_entry, G3_scratch);
1449   __ delayed()->restore();      // Pop this frame off.
1450   __ bind(L);
1451 }
1452 
1453 // A simple move of integer like type
1454 static void simple_move32(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
1455   if (src.first()->is_stack()) {
1456     if (dst.first()->is_stack()) {
1457       // stack to stack
1458       __ ld(FP, reg2offset(src.first()) + STACK_BIAS, L5);
1459       __ st(L5, SP, reg2offset(dst.first()) + STACK_BIAS);
1460     } else {
1461       // stack to reg
1462       __ ld(FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_Register());
1463     }
1464   } else if (dst.first()->is_stack()) {
1465     // reg to stack
1466     __ st(src.first()->as_Register(), SP, reg2offset(dst.first()) + STACK_BIAS);
1467   } else {
1468     __ mov(src.first()->as_Register(), dst.first()->as_Register());
1469   }
1470 }
1471 
1472 // On 64 bit we will store integer like items to the stack as
1473 // 64 bits items (sparc abi) even though java would only store
1474 // 32bits for a parameter. On 32bit it will simply be 32 bits
1475 // So this routine will do 32->32 on 32bit and 32->64 on 64bit
1476 static void move32_64(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
1477   if (src.first()->is_stack()) {
1478     if (dst.first()->is_stack()) {
1479       // stack to stack
1480       __ ld(FP, reg2offset(src.first()) + STACK_BIAS, L5);
1481       __ st_ptr(L5, SP, reg2offset(dst.first()) + STACK_BIAS);
1482     } else {
1483       // stack to reg
1484       __ ld(FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_Register());
1485     }
1486   } else if (dst.first()->is_stack()) {
1487     // reg to stack
1488     __ st_ptr(src.first()->as_Register(), SP, reg2offset(dst.first()) + STACK_BIAS);
1489   } else {
1490     __ mov(src.first()->as_Register(), dst.first()->as_Register());
1491   }
1492 }
1493 
1494 
1495 // An oop arg. Must pass a handle not the oop itself
1496 static void object_move(MacroAssembler* masm,
1497                         OopMap* map,
1498                         int oop_handle_offset,
1499                         int framesize_in_slots,
1500                         VMRegPair src,
1501                         VMRegPair dst,
1502                         bool is_receiver,
1503                         int* receiver_offset) {
1504 
1505   // must pass a handle. First figure out the location we use as a handle
1506 
1507   if (src.first()->is_stack()) {
1508     // Oop is already on the stack
1509     Register rHandle = dst.first()->is_stack() ? L5 : dst.first()->as_Register();
1510     __ add(FP, reg2offset(src.first()) + STACK_BIAS, rHandle);
1511     __ ld_ptr(rHandle, 0, L4);
1512 #ifdef _LP64
1513     __ movr( Assembler::rc_z, L4, G0, rHandle );
1514 #else
1515     __ tst( L4 );
1516     __ movcc( Assembler::zero, false, Assembler::icc, G0, rHandle );
1517 #endif
1518     if (dst.first()->is_stack()) {
1519       __ st_ptr(rHandle, SP, reg2offset(dst.first()) + STACK_BIAS);
1520     }
1521     int offset_in_older_frame = src.first()->reg2stack() + SharedRuntime::out_preserve_stack_slots();
1522     if (is_receiver) {
1523       *receiver_offset = (offset_in_older_frame + framesize_in_slots) * VMRegImpl::stack_slot_size;
1524     }
1525     map->set_oop(VMRegImpl::stack2reg(offset_in_older_frame + framesize_in_slots));
1526   } else {
1527     // Oop is in an input register pass we must flush it to the stack
1528     const Register rOop = src.first()->as_Register();
1529     const Register rHandle = L5;
1530     int oop_slot = rOop->input_number() * VMRegImpl::slots_per_word + oop_handle_offset;
1531     int offset = oop_slot*VMRegImpl::stack_slot_size;
1532     Label skip;
1533     __ st_ptr(rOop, SP, offset + STACK_BIAS);
1534     if (is_receiver) {
1535       *receiver_offset = oop_slot * VMRegImpl::stack_slot_size;
1536     }
1537     map->set_oop(VMRegImpl::stack2reg(oop_slot));
1538     __ add(SP, offset + STACK_BIAS, rHandle);
1539 #ifdef _LP64
1540     __ movr( Assembler::rc_z, rOop, G0, rHandle );
1541 #else
1542     __ tst( rOop );
1543     __ movcc( Assembler::zero, false, Assembler::icc, G0, rHandle );
1544 #endif
1545 
1546     if (dst.first()->is_stack()) {
1547       __ st_ptr(rHandle, SP, reg2offset(dst.first()) + STACK_BIAS);
1548     } else {
1549       __ mov(rHandle, dst.first()->as_Register());
1550     }
1551   }
1552 }
1553 
1554 // A float arg may have to do float reg int reg conversion
1555 static void float_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
1556   assert(!src.second()->is_valid() && !dst.second()->is_valid(), "bad float_move");
1557 
1558   if (src.first()->is_stack()) {
1559     if (dst.first()->is_stack()) {
1560       // stack to stack the easiest of the bunch
1561       __ ld(FP, reg2offset(src.first()) + STACK_BIAS, L5);
1562       __ st(L5, SP, reg2offset(dst.first()) + STACK_BIAS);
1563     } else {
1564       // stack to reg
1565       if (dst.first()->is_Register()) {
1566         __ ld(FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_Register());
1567       } else {
1568         __ ldf(FloatRegisterImpl::S, FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_FloatRegister());
1569       }
1570     }
1571   } else if (dst.first()->is_stack()) {
1572     // reg to stack
1573     if (src.first()->is_Register()) {
1574       __ st(src.first()->as_Register(), SP, reg2offset(dst.first()) + STACK_BIAS);
1575     } else {
1576       __ stf(FloatRegisterImpl::S, src.first()->as_FloatRegister(), SP, reg2offset(dst.first()) + STACK_BIAS);
1577     }
1578   } else {
1579     // reg to reg
1580     if (src.first()->is_Register()) {
1581       if (dst.first()->is_Register()) {
1582         // gpr -> gpr
1583         __ mov(src.first()->as_Register(), dst.first()->as_Register());
1584       } else {
1585         // gpr -> fpr
1586         __ st(src.first()->as_Register(), FP, -4 + STACK_BIAS);
1587         __ ldf(FloatRegisterImpl::S, FP, -4 + STACK_BIAS, dst.first()->as_FloatRegister());
1588       }
1589     } else if (dst.first()->is_Register()) {
1590       // fpr -> gpr
1591       __ stf(FloatRegisterImpl::S, src.first()->as_FloatRegister(), FP, -4 + STACK_BIAS);
1592       __ ld(FP, -4 + STACK_BIAS, dst.first()->as_Register());
1593     } else {
1594       // fpr -> fpr
1595       // In theory these overlap but the ordering is such that this is likely a nop
1596       if ( src.first() != dst.first()) {
1597         __ fmov(FloatRegisterImpl::S, src.first()->as_FloatRegister(), dst.first()->as_FloatRegister());
1598       }
1599     }
1600   }
1601 }
1602 
1603 static void split_long_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
1604   VMRegPair src_lo(src.first());
1605   VMRegPair src_hi(src.second());
1606   VMRegPair dst_lo(dst.first());
1607   VMRegPair dst_hi(dst.second());
1608   simple_move32(masm, src_lo, dst_lo);
1609   simple_move32(masm, src_hi, dst_hi);
1610 }
1611 
1612 // A long move
1613 static void long_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
1614 
1615   // Do the simple ones here else do two int moves
1616   if (src.is_single_phys_reg() ) {
1617     if (dst.is_single_phys_reg()) {
1618       __ mov(src.first()->as_Register(), dst.first()->as_Register());
1619     } else {
1620       // split src into two separate registers
1621       // Remember hi means hi address or lsw on sparc
1622       // Move msw to lsw
1623       if (dst.second()->is_reg()) {
1624         // MSW -> MSW
1625         __ srax(src.first()->as_Register(), 32, dst.first()->as_Register());
1626         // Now LSW -> LSW
1627         // this will only move lo -> lo and ignore hi
1628         VMRegPair split(dst.second());
1629         simple_move32(masm, src, split);
1630       } else {
1631         VMRegPair split(src.first(), L4->as_VMReg());
1632         // MSW -> MSW (lo ie. first word)
1633         __ srax(src.first()->as_Register(), 32, L4);
1634         split_long_move(masm, split, dst);
1635       }
1636     }
1637   } else if (dst.is_single_phys_reg()) {
1638     if (src.is_adjacent_aligned_on_stack(2)) {
1639       __ ldx(FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_Register());
1640     } else {
1641       // dst is a single reg.
1642       // Remember lo is low address not msb for stack slots
1643       // and lo is the "real" register for registers
1644       // src is
1645 
1646       VMRegPair split;
1647 
1648       if (src.first()->is_reg()) {
1649         // src.lo (msw) is a reg, src.hi is stk/reg
1650         // we will move: src.hi (LSW) -> dst.lo, src.lo (MSW) -> src.lo [the MSW is in the LSW of the reg]
1651         split.set_pair(dst.first(), src.first());
1652       } else {
1653         // msw is stack move to L5
1654         // lsw is stack move to dst.lo (real reg)
1655         // we will move: src.hi (LSW) -> dst.lo, src.lo (MSW) -> L5
1656         split.set_pair(dst.first(), L5->as_VMReg());
1657       }
1658 
1659       // src.lo -> src.lo/L5, src.hi -> dst.lo (the real reg)
1660       // msw   -> src.lo/L5,  lsw -> dst.lo
1661       split_long_move(masm, src, split);
1662 
1663       // So dst now has the low order correct position the
1664       // msw half
1665       __ sllx(split.first()->as_Register(), 32, L5);
1666 
1667       const Register d = dst.first()->as_Register();
1668       __ or3(L5, d, d);
1669     }
1670   } else {
1671     // For LP64 we can probably do better.
1672     split_long_move(masm, src, dst);
1673   }
1674 }
1675 
1676 // A double move
1677 static void double_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
1678 
1679   // The painful thing here is that like long_move a VMRegPair might be
1680   // 1: a single physical register
1681   // 2: two physical registers (v8)
1682   // 3: a physical reg [lo] and a stack slot [hi] (v8)
1683   // 4: two stack slots
1684 
1685   // Since src is always a java calling convention we know that the src pair
1686   // is always either all registers or all stack (and aligned?)
1687 
1688   // in a register [lo] and a stack slot [hi]
1689   if (src.first()->is_stack()) {
1690     if (dst.first()->is_stack()) {
1691       // stack to stack the easiest of the bunch
1692       // ought to be a way to do this where if alignment is ok we use ldd/std when possible
1693       __ ld(FP, reg2offset(src.first()) + STACK_BIAS, L5);
1694       __ ld(FP, reg2offset(src.second()) + STACK_BIAS, L4);
1695       __ st(L5, SP, reg2offset(dst.first()) + STACK_BIAS);
1696       __ st(L4, SP, reg2offset(dst.second()) + STACK_BIAS);
1697     } else {
1698       // stack to reg
1699       if (dst.second()->is_stack()) {
1700         // stack -> reg, stack -> stack
1701         __ ld(FP, reg2offset(src.second()) + STACK_BIAS, L4);
1702         if (dst.first()->is_Register()) {
1703           __ ld(FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_Register());
1704         } else {
1705           __ ldf(FloatRegisterImpl::S, FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_FloatRegister());
1706         }
1707         // This was missing. (very rare case)
1708         __ st(L4, SP, reg2offset(dst.second()) + STACK_BIAS);
1709       } else {
1710         // stack -> reg
1711         // Eventually optimize for alignment QQQ
1712         if (dst.first()->is_Register()) {
1713           __ ld(FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_Register());
1714           __ ld(FP, reg2offset(src.second()) + STACK_BIAS, dst.second()->as_Register());
1715         } else {
1716           __ ldf(FloatRegisterImpl::S, FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_FloatRegister());
1717           __ ldf(FloatRegisterImpl::S, FP, reg2offset(src.second()) + STACK_BIAS, dst.second()->as_FloatRegister());
1718         }
1719       }
1720     }
1721   } else if (dst.first()->is_stack()) {
1722     // reg to stack
1723     if (src.first()->is_Register()) {
1724       // Eventually optimize for alignment QQQ
1725       __ st(src.first()->as_Register(), SP, reg2offset(dst.first()) + STACK_BIAS);
1726       if (src.second()->is_stack()) {
1727         __ ld(FP, reg2offset(src.second()) + STACK_BIAS, L4);
1728         __ st(L4, SP, reg2offset(dst.second()) + STACK_BIAS);
1729       } else {
1730         __ st(src.second()->as_Register(), SP, reg2offset(dst.second()) + STACK_BIAS);
1731       }
1732     } else {
1733       // fpr to stack
1734       if (src.second()->is_stack()) {
1735         ShouldNotReachHere();
1736       } else {
1737         // Is the stack aligned?
1738         if (reg2offset(dst.first()) & 0x7) {
1739           // No do as pairs
1740           __ stf(FloatRegisterImpl::S, src.first()->as_FloatRegister(), SP, reg2offset(dst.first()) + STACK_BIAS);
1741           __ stf(FloatRegisterImpl::S, src.second()->as_FloatRegister(), SP, reg2offset(dst.second()) + STACK_BIAS);
1742         } else {
1743           __ stf(FloatRegisterImpl::D, src.first()->as_FloatRegister(), SP, reg2offset(dst.first()) + STACK_BIAS);
1744         }
1745       }
1746     }
1747   } else {
1748     // reg to reg
1749     if (src.first()->is_Register()) {
1750       if (dst.first()->is_Register()) {
1751         // gpr -> gpr
1752         __ mov(src.first()->as_Register(), dst.first()->as_Register());
1753         __ mov(src.second()->as_Register(), dst.second()->as_Register());
1754       } else {
1755         // gpr -> fpr
1756         // ought to be able to do a single store
1757         __ stx(src.first()->as_Register(), FP, -8 + STACK_BIAS);
1758         __ stx(src.second()->as_Register(), FP, -4 + STACK_BIAS);
1759         // ought to be able to do a single load
1760         __ ldf(FloatRegisterImpl::S, FP, -8 + STACK_BIAS, dst.first()->as_FloatRegister());
1761         __ ldf(FloatRegisterImpl::S, FP, -4 + STACK_BIAS, dst.second()->as_FloatRegister());
1762       }
1763     } else if (dst.first()->is_Register()) {
1764       // fpr -> gpr
1765       // ought to be able to do a single store
1766       __ stf(FloatRegisterImpl::D, src.first()->as_FloatRegister(), FP, -8 + STACK_BIAS);
1767       // ought to be able to do a single load
1768       // REMEMBER first() is low address not LSB
1769       __ ld(FP, -8 + STACK_BIAS, dst.first()->as_Register());
1770       if (dst.second()->is_Register()) {
1771         __ ld(FP, -4 + STACK_BIAS, dst.second()->as_Register());
1772       } else {
1773         __ ld(FP, -4 + STACK_BIAS, L4);
1774         __ st(L4, SP, reg2offset(dst.second()) + STACK_BIAS);
1775       }
1776     } else {
1777       // fpr -> fpr
1778       // In theory these overlap but the ordering is such that this is likely a nop
1779       if ( src.first() != dst.first()) {
1780         __ fmov(FloatRegisterImpl::D, src.first()->as_FloatRegister(), dst.first()->as_FloatRegister());
1781       }
1782     }
1783   }
1784 }
1785 
1786 // Creates an inner frame if one hasn't already been created, and
1787 // saves a copy of the thread in L7_thread_cache
1788 static void create_inner_frame(MacroAssembler* masm, bool* already_created) {
1789   if (!*already_created) {
1790     __ save_frame(0);
1791     // Save thread in L7 (INNER FRAME); it crosses a bunch of VM calls below
1792     // Don't use save_thread because it smashes G2 and we merely want to save a
1793     // copy
1794     __ mov(G2_thread, L7_thread_cache);
1795     *already_created = true;
1796   }
1797 }
1798 
1799 // ---------------------------------------------------------------------------
1800 // Generate a native wrapper for a given method.  The method takes arguments
1801 // in the Java compiled code convention, marshals them to the native
1802 // convention (handlizes oops, etc), transitions to native, makes the call,
1803 // returns to java state (possibly blocking), unhandlizes any result and
1804 // returns.
1805 nmethod *SharedRuntime::generate_native_wrapper(MacroAssembler* masm,
1806                                                 methodHandle method,
1807                                                 int total_in_args,
1808                                                 int comp_args_on_stack, // in VMRegStackSlots
1809                                                 BasicType *in_sig_bt,
1810                                                 VMRegPair *in_regs,
1811                                                 BasicType ret_type) {
1812 
1813   // Native nmethod wrappers never take possesion of the oop arguments.
1814   // So the caller will gc the arguments. The only thing we need an
1815   // oopMap for is if the call is static
1816   //
1817   // An OopMap for lock (and class if static), and one for the VM call itself
1818   OopMapSet *oop_maps = new OopMapSet();
1819   intptr_t start = (intptr_t)__ pc();
1820 
1821   // First thing make an ic check to see if we should even be here
1822   {
1823     Label L;
1824     const Register temp_reg = G3_scratch;
1825     AddressLiteral ic_miss(SharedRuntime::get_ic_miss_stub());
1826     __ verify_oop(O0);
1827     __ load_klass(O0, temp_reg);
1828     __ cmp(temp_reg, G5_inline_cache_reg);
1829     __ brx(Assembler::equal, true, Assembler::pt, L);
1830     __ delayed()->nop();
1831 
1832     __ jump_to(ic_miss, temp_reg);
1833     __ delayed()->nop();
1834     __ align(CodeEntryAlignment);
1835     __ bind(L);
1836   }
1837 
1838   int vep_offset = ((intptr_t)__ pc()) - start;
1839 
1840 #ifdef COMPILER1
1841   if (InlineObjectHash && method->intrinsic_id() == vmIntrinsics::_hashCode) {
1842     // Object.hashCode can pull the hashCode from the header word
1843     // instead of doing a full VM transition once it's been computed.
1844     // Since hashCode is usually polymorphic at call sites we can't do
1845     // this optimization at the call site without a lot of work.
1846     Label slowCase;
1847     Register receiver             = O0;
1848     Register result               = O0;
1849     Register header               = G3_scratch;
1850     Register hash                 = G3_scratch; // overwrite header value with hash value
1851     Register mask                 = G1;         // to get hash field from header
1852 
1853     // Read the header and build a mask to get its hash field.  Give up if the object is not unlocked.
1854     // We depend on hash_mask being at most 32 bits and avoid the use of
1855     // hash_mask_in_place because it could be larger than 32 bits in a 64-bit
1856     // vm: see markOop.hpp.
1857     __ ld_ptr(receiver, oopDesc::mark_offset_in_bytes(), header);
1858     __ sethi(markOopDesc::hash_mask, mask);
1859     __ btst(markOopDesc::unlocked_value, header);
1860     __ br(Assembler::zero, false, Assembler::pn, slowCase);
1861     if (UseBiasedLocking) {
1862       // Check if biased and fall through to runtime if so
1863       __ delayed()->nop();
1864       __ btst(markOopDesc::biased_lock_bit_in_place, header);
1865       __ br(Assembler::notZero, false, Assembler::pn, slowCase);
1866     }
1867     __ delayed()->or3(mask, markOopDesc::hash_mask & 0x3ff, mask);
1868 
1869     // Check for a valid (non-zero) hash code and get its value.
1870 #ifdef _LP64
1871     __ srlx(header, markOopDesc::hash_shift, hash);
1872 #else
1873     __ srl(header, markOopDesc::hash_shift, hash);
1874 #endif
1875     __ andcc(hash, mask, hash);
1876     __ br(Assembler::equal, false, Assembler::pn, slowCase);
1877     __ delayed()->nop();
1878 
1879     // leaf return.
1880     __ retl();
1881     __ delayed()->mov(hash, result);
1882     __ bind(slowCase);
1883   }
1884 #endif // COMPILER1
1885 
1886 
1887   // We have received a description of where all the java arg are located
1888   // on entry to the wrapper. We need to convert these args to where
1889   // the jni function will expect them. To figure out where they go
1890   // we convert the java signature to a C signature by inserting
1891   // the hidden arguments as arg[0] and possibly arg[1] (static method)
1892 
1893   int total_c_args = total_in_args + 1;
1894   if (method->is_static()) {
1895     total_c_args++;
1896   }
1897 
1898   BasicType* out_sig_bt = NEW_RESOURCE_ARRAY(BasicType, total_c_args);
1899   VMRegPair  * out_regs   = NEW_RESOURCE_ARRAY(VMRegPair,   total_c_args);
1900 
1901   int argc = 0;
1902   out_sig_bt[argc++] = T_ADDRESS;
1903   if (method->is_static()) {
1904     out_sig_bt[argc++] = T_OBJECT;
1905   }
1906 
1907   for (int i = 0; i < total_in_args ; i++ ) {
1908     out_sig_bt[argc++] = in_sig_bt[i];
1909   }
1910 
1911   // Now figure out where the args must be stored and how much stack space
1912   // they require (neglecting out_preserve_stack_slots but space for storing
1913   // the 1st six register arguments). It's weird see int_stk_helper.
1914   //
1915   int out_arg_slots;
1916   out_arg_slots = c_calling_convention(out_sig_bt, out_regs, total_c_args);
1917 
1918   // Compute framesize for the wrapper.  We need to handlize all oops in
1919   // registers. We must create space for them here that is disjoint from
1920   // the windowed save area because we have no control over when we might
1921   // flush the window again and overwrite values that gc has since modified.
1922   // (The live window race)
1923   //
1924   // We always just allocate 6 word for storing down these object. This allow
1925   // us to simply record the base and use the Ireg number to decide which
1926   // slot to use. (Note that the reg number is the inbound number not the
1927   // outbound number).
1928   // We must shuffle args to match the native convention, and include var-args space.
1929 
1930   // Calculate the total number of stack slots we will need.
1931 
1932   // First count the abi requirement plus all of the outgoing args
1933   int stack_slots = SharedRuntime::out_preserve_stack_slots() + out_arg_slots;
1934 
1935   // Now the space for the inbound oop handle area
1936 
1937   int oop_handle_offset = stack_slots;
1938   stack_slots += 6*VMRegImpl::slots_per_word;
1939 
1940   // Now any space we need for handlizing a klass if static method
1941 
1942   int oop_temp_slot_offset = 0;
1943   int klass_slot_offset = 0;
1944   int klass_offset = -1;
1945   int lock_slot_offset = 0;
1946   bool is_static = false;
1947 
1948   if (method->is_static()) {
1949     klass_slot_offset = stack_slots;
1950     stack_slots += VMRegImpl::slots_per_word;
1951     klass_offset = klass_slot_offset * VMRegImpl::stack_slot_size;
1952     is_static = true;
1953   }
1954 
1955   // Plus a lock if needed
1956 
1957   if (method->is_synchronized()) {
1958     lock_slot_offset = stack_slots;
1959     stack_slots += VMRegImpl::slots_per_word;
1960   }
1961 
1962   // Now a place to save return value or as a temporary for any gpr -> fpr moves
1963   stack_slots += 2;
1964 
1965   // Ok The space we have allocated will look like:
1966   //
1967   //
1968   // FP-> |                     |
1969   //      |---------------------|
1970   //      | 2 slots for moves   |
1971   //      |---------------------|
1972   //      | lock box (if sync)  |
1973   //      |---------------------| <- lock_slot_offset
1974   //      | klass (if static)   |
1975   //      |---------------------| <- klass_slot_offset
1976   //      | oopHandle area      |
1977   //      |---------------------| <- oop_handle_offset
1978   //      | outbound memory     |
1979   //      | based arguments     |
1980   //      |                     |
1981   //      |---------------------|
1982   //      | vararg area         |
1983   //      |---------------------|
1984   //      |                     |
1985   // SP-> | out_preserved_slots |
1986   //
1987   //
1988 
1989 
1990   // Now compute actual number of stack words we need rounding to make
1991   // stack properly aligned.
1992   stack_slots = round_to(stack_slots, 2 * VMRegImpl::slots_per_word);
1993 
1994   int stack_size = stack_slots * VMRegImpl::stack_slot_size;
1995 
1996   // Generate stack overflow check before creating frame
1997   __ generate_stack_overflow_check(stack_size);
1998 
1999   // Generate a new frame for the wrapper.
2000   __ save(SP, -stack_size, SP);
2001 
2002   int frame_complete = ((intptr_t)__ pc()) - start;
2003 
2004   __ verify_thread();
2005 
2006 
2007   //
2008   // We immediately shuffle the arguments so that any vm call we have to
2009   // make from here on out (sync slow path, jvmti, etc.) we will have
2010   // captured the oops from our caller and have a valid oopMap for
2011   // them.
2012 
2013   // -----------------
2014   // The Grand Shuffle
2015   //
2016   // Natives require 1 or 2 extra arguments over the normal ones: the JNIEnv*
2017   // (derived from JavaThread* which is in L7_thread_cache) and, if static,
2018   // the class mirror instead of a receiver.  This pretty much guarantees that
2019   // register layout will not match.  We ignore these extra arguments during
2020   // the shuffle. The shuffle is described by the two calling convention
2021   // vectors we have in our possession. We simply walk the java vector to
2022   // get the source locations and the c vector to get the destinations.
2023   // Because we have a new window and the argument registers are completely
2024   // disjoint ( I0 -> O1, I1 -> O2, ...) we have nothing to worry about
2025   // here.
2026 
2027   // This is a trick. We double the stack slots so we can claim
2028   // the oops in the caller's frame. Since we are sure to have
2029   // more args than the caller doubling is enough to make
2030   // sure we can capture all the incoming oop args from the
2031   // caller.
2032   //
2033   OopMap* map = new OopMap(stack_slots * 2, 0 /* arg_slots*/);
2034   int c_arg = total_c_args - 1;
2035   // Record sp-based slot for receiver on stack for non-static methods
2036   int receiver_offset = -1;
2037 
2038   // We move the arguments backward because the floating point registers
2039   // destination will always be to a register with a greater or equal register
2040   // number or the stack.
2041 
2042 #ifdef ASSERT
2043   bool reg_destroyed[RegisterImpl::number_of_registers];
2044   bool freg_destroyed[FloatRegisterImpl::number_of_registers];
2045   for ( int r = 0 ; r < RegisterImpl::number_of_registers ; r++ ) {
2046     reg_destroyed[r] = false;
2047   }
2048   for ( int f = 0 ; f < FloatRegisterImpl::number_of_registers ; f++ ) {
2049     freg_destroyed[f] = false;
2050   }
2051 
2052 #endif /* ASSERT */
2053 
2054   for ( int i = total_in_args - 1; i >= 0 ; i--, c_arg-- ) {
2055 
2056 #ifdef ASSERT
2057     if (in_regs[i].first()->is_Register()) {
2058       assert(!reg_destroyed[in_regs[i].first()->as_Register()->encoding()], "ack!");
2059     } else if (in_regs[i].first()->is_FloatRegister()) {
2060       assert(!freg_destroyed[in_regs[i].first()->as_FloatRegister()->encoding(FloatRegisterImpl::S)], "ack!");
2061     }
2062     if (out_regs[c_arg].first()->is_Register()) {
2063       reg_destroyed[out_regs[c_arg].first()->as_Register()->encoding()] = true;
2064     } else if (out_regs[c_arg].first()->is_FloatRegister()) {
2065       freg_destroyed[out_regs[c_arg].first()->as_FloatRegister()->encoding(FloatRegisterImpl::S)] = true;
2066     }
2067 #endif /* ASSERT */
2068 
2069     switch (in_sig_bt[i]) {
2070       case T_ARRAY:
2071       case T_OBJECT:
2072         object_move(masm, map, oop_handle_offset, stack_slots, in_regs[i], out_regs[c_arg],
2073                     ((i == 0) && (!is_static)),
2074                     &receiver_offset);
2075         break;
2076       case T_VOID:
2077         break;
2078 
2079       case T_FLOAT:
2080         float_move(masm, in_regs[i], out_regs[c_arg]);
2081           break;
2082 
2083       case T_DOUBLE:
2084         assert( i + 1 < total_in_args &&
2085                 in_sig_bt[i + 1] == T_VOID &&
2086                 out_sig_bt[c_arg+1] == T_VOID, "bad arg list");
2087         double_move(masm, in_regs[i], out_regs[c_arg]);
2088         break;
2089 
2090       case T_LONG :
2091         long_move(masm, in_regs[i], out_regs[c_arg]);
2092         break;
2093 
2094       case T_ADDRESS: assert(false, "found T_ADDRESS in java args");
2095 
2096       default:
2097         move32_64(masm, in_regs[i], out_regs[c_arg]);
2098     }
2099   }
2100 
2101   // Pre-load a static method's oop into O1.  Used both by locking code and
2102   // the normal JNI call code.
2103   if (method->is_static()) {
2104     __ set_oop_constant(JNIHandles::make_local(Klass::cast(method->method_holder())->java_mirror()), O1);
2105 
2106     // Now handlize the static class mirror in O1.  It's known not-null.
2107     __ st_ptr(O1, SP, klass_offset + STACK_BIAS);
2108     map->set_oop(VMRegImpl::stack2reg(klass_slot_offset));
2109     __ add(SP, klass_offset + STACK_BIAS, O1);
2110   }
2111 
2112 
2113   const Register L6_handle = L6;
2114 
2115   if (method->is_synchronized()) {
2116     __ mov(O1, L6_handle);
2117   }
2118 
2119   // We have all of the arguments setup at this point. We MUST NOT touch any Oregs
2120   // except O6/O7. So if we must call out we must push a new frame. We immediately
2121   // push a new frame and flush the windows.
2122 
2123 #ifdef _LP64
2124   intptr_t thepc = (intptr_t) __ pc();
2125   {
2126     address here = __ pc();
2127     // Call the next instruction
2128     __ call(here + 8, relocInfo::none);
2129     __ delayed()->nop();
2130   }
2131 #else
2132   intptr_t thepc = __ load_pc_address(O7, 0);
2133 #endif /* _LP64 */
2134 
2135   // We use the same pc/oopMap repeatedly when we call out
2136   oop_maps->add_gc_map(thepc - start, map);
2137 
2138   // O7 now has the pc loaded that we will use when we finally call to native.
2139 
2140   // Save thread in L7; it crosses a bunch of VM calls below
2141   // Don't use save_thread because it smashes G2 and we merely
2142   // want to save a copy
2143   __ mov(G2_thread, L7_thread_cache);
2144 
2145 
2146   // If we create an inner frame once is plenty
2147   // when we create it we must also save G2_thread
2148   bool inner_frame_created = false;
2149 
2150   // dtrace method entry support
2151   {
2152     SkipIfEqual skip_if(
2153       masm, G3_scratch, &DTraceMethodProbes, Assembler::zero);
2154     // create inner frame
2155     __ save_frame(0);
2156     __ mov(G2_thread, L7_thread_cache);
2157     __ set_oop_constant(JNIHandles::make_local(method()), O1);
2158     __ call_VM_leaf(L7_thread_cache,
2159          CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_entry),
2160          G2_thread, O1);
2161     __ restore();
2162   }
2163 
2164   // RedefineClasses() tracing support for obsolete method entry
2165   if (RC_TRACE_IN_RANGE(0x00001000, 0x00002000)) {
2166     // create inner frame
2167     __ save_frame(0);
2168     __ mov(G2_thread, L7_thread_cache);
2169     __ set_oop_constant(JNIHandles::make_local(method()), O1);
2170     __ call_VM_leaf(L7_thread_cache,
2171          CAST_FROM_FN_PTR(address, SharedRuntime::rc_trace_method_entry),
2172          G2_thread, O1);
2173     __ restore();
2174   }
2175 
2176   // We are in the jni frame unless saved_frame is true in which case
2177   // we are in one frame deeper (the "inner" frame). If we are in the
2178   // "inner" frames the args are in the Iregs and if the jni frame then
2179   // they are in the Oregs.
2180   // If we ever need to go to the VM (for locking, jvmti) then
2181   // we will always be in the "inner" frame.
2182 
2183   // Lock a synchronized method
2184   int lock_offset = -1;         // Set if locked
2185   if (method->is_synchronized()) {
2186     Register Roop = O1;
2187     const Register L3_box = L3;
2188 
2189     create_inner_frame(masm, &inner_frame_created);
2190 
2191     __ ld_ptr(I1, 0, O1);
2192     Label done;
2193 
2194     lock_offset = (lock_slot_offset * VMRegImpl::stack_slot_size);
2195     __ add(FP, lock_offset+STACK_BIAS, L3_box);
2196 #ifdef ASSERT
2197     if (UseBiasedLocking) {
2198       // making the box point to itself will make it clear it went unused
2199       // but also be obviously invalid
2200       __ st_ptr(L3_box, L3_box, 0);
2201     }
2202 #endif // ASSERT
2203     //
2204     // Compiler_lock_object (Roop, Rmark, Rbox, Rscratch) -- kills Rmark, Rbox, Rscratch
2205     //
2206     __ compiler_lock_object(Roop, L1,    L3_box, L2);
2207     __ br(Assembler::equal, false, Assembler::pt, done);
2208     __ delayed() -> add(FP, lock_offset+STACK_BIAS, L3_box);
2209 
2210 
2211     // None of the above fast optimizations worked so we have to get into the
2212     // slow case of monitor enter.  Inline a special case of call_VM that
2213     // disallows any pending_exception.
2214     __ mov(Roop, O0);            // Need oop in O0
2215     __ mov(L3_box, O1);
2216 
2217     // Record last_Java_sp, in case the VM code releases the JVM lock.
2218 
2219     __ set_last_Java_frame(FP, I7);
2220 
2221     // do the call
2222     __ call(CAST_FROM_FN_PTR(address, SharedRuntime::complete_monitor_locking_C), relocInfo::runtime_call_type);
2223     __ delayed()->mov(L7_thread_cache, O2);
2224 
2225     __ restore_thread(L7_thread_cache); // restore G2_thread
2226     __ reset_last_Java_frame();
2227 
2228 #ifdef ASSERT
2229     { Label L;
2230     __ ld_ptr(G2_thread, in_bytes(Thread::pending_exception_offset()), O0);
2231     __ br_null(O0, false, Assembler::pt, L);
2232     __ delayed()->nop();
2233     __ stop("no pending exception allowed on exit from IR::monitorenter");
2234     __ bind(L);
2235     }
2236 #endif
2237     __ bind(done);
2238   }
2239 
2240 
2241   // Finally just about ready to make the JNI call
2242 
2243   __ flush_windows();
2244   if (inner_frame_created) {
2245     __ restore();
2246   } else {
2247     // Store only what we need from this frame
2248     // QQQ I think that non-v9 (like we care) we don't need these saves
2249     // either as the flush traps and the current window goes too.
2250     __ st_ptr(FP, SP, FP->sp_offset_in_saved_window()*wordSize + STACK_BIAS);
2251     __ st_ptr(I7, SP, I7->sp_offset_in_saved_window()*wordSize + STACK_BIAS);
2252   }
2253 
2254   // get JNIEnv* which is first argument to native
2255 
2256   __ add(G2_thread, in_bytes(JavaThread::jni_environment_offset()), O0);
2257 
2258   // Use that pc we placed in O7 a while back as the current frame anchor
2259 
2260   __ set_last_Java_frame(SP, O7);
2261 
2262   // Transition from _thread_in_Java to _thread_in_native.
2263   __ set(_thread_in_native, G3_scratch);
2264   __ st(G3_scratch, G2_thread, JavaThread::thread_state_offset());
2265 
2266   // We flushed the windows ages ago now mark them as flushed
2267 
2268   // mark windows as flushed
2269   __ set(JavaFrameAnchor::flushed, G3_scratch);
2270 
2271   Address flags(G2_thread, JavaThread::frame_anchor_offset() + JavaFrameAnchor::flags_offset());
2272 
2273 #ifdef _LP64
2274   AddressLiteral dest(method->native_function());
2275   __ relocate(relocInfo::runtime_call_type);
2276   __ jumpl_to(dest, O7, O7);
2277 #else
2278   __ call(method->native_function(), relocInfo::runtime_call_type);
2279 #endif
2280   __ delayed()->st(G3_scratch, flags);
2281 
2282   __ restore_thread(L7_thread_cache); // restore G2_thread
2283 
2284   // Unpack native results.  For int-types, we do any needed sign-extension
2285   // and move things into I0.  The return value there will survive any VM
2286   // calls for blocking or unlocking.  An FP or OOP result (handle) is done
2287   // specially in the slow-path code.
2288   switch (ret_type) {
2289   case T_VOID:    break;        // Nothing to do!
2290   case T_FLOAT:   break;        // Got it where we want it (unless slow-path)
2291   case T_DOUBLE:  break;        // Got it where we want it (unless slow-path)
2292   // In 64 bits build result is in O0, in O0, O1 in 32bit build
2293   case T_LONG:
2294 #ifndef _LP64
2295                   __ mov(O1, I1);
2296 #endif
2297                   // Fall thru
2298   case T_OBJECT:                // Really a handle
2299   case T_ARRAY:
2300   case T_INT:
2301                   __ mov(O0, I0);
2302                   break;
2303   case T_BOOLEAN: __ subcc(G0, O0, G0); __ addc(G0, 0, I0); break; // !0 => true; 0 => false
2304   case T_BYTE   : __ sll(O0, 24, O0); __ sra(O0, 24, I0);   break;
2305   case T_CHAR   : __ sll(O0, 16, O0); __ srl(O0, 16, I0);   break; // cannot use and3, 0xFFFF too big as immediate value!
2306   case T_SHORT  : __ sll(O0, 16, O0); __ sra(O0, 16, I0);   break;
2307     break;                      // Cannot de-handlize until after reclaiming jvm_lock
2308   default:
2309     ShouldNotReachHere();
2310   }
2311 
2312   // must we block?
2313 
2314   // Block, if necessary, before resuming in _thread_in_Java state.
2315   // In order for GC to work, don't clear the last_Java_sp until after blocking.
2316   { Label no_block;
2317     AddressLiteral sync_state(SafepointSynchronize::address_of_state());
2318 
2319     // Switch thread to "native transition" state before reading the synchronization state.
2320     // This additional state is necessary because reading and testing the synchronization
2321     // state is not atomic w.r.t. GC, as this scenario demonstrates:
2322     //     Java thread A, in _thread_in_native state, loads _not_synchronized and is preempted.
2323     //     VM thread changes sync state to synchronizing and suspends threads for GC.
2324     //     Thread A is resumed to finish this native method, but doesn't block here since it
2325     //     didn't see any synchronization is progress, and escapes.
2326     __ set(_thread_in_native_trans, G3_scratch);
2327     __ st(G3_scratch, G2_thread, JavaThread::thread_state_offset());
2328     if(os::is_MP()) {
2329       if (UseMembar) {
2330         // Force this write out before the read below
2331         __ membar(Assembler::StoreLoad);
2332       } else {
2333         // Write serialization page so VM thread can do a pseudo remote membar.
2334         // We use the current thread pointer to calculate a thread specific
2335         // offset to write to within the page. This minimizes bus traffic
2336         // due to cache line collision.
2337         __ serialize_memory(G2_thread, G1_scratch, G3_scratch);
2338       }
2339     }
2340     __ load_contents(sync_state, G3_scratch);
2341     __ cmp(G3_scratch, SafepointSynchronize::_not_synchronized);
2342 
2343     Label L;
2344     Address suspend_state(G2_thread, JavaThread::suspend_flags_offset());
2345     __ br(Assembler::notEqual, false, Assembler::pn, L);
2346     __ delayed()->ld(suspend_state, G3_scratch);
2347     __ cmp(G3_scratch, 0);
2348     __ br(Assembler::equal, false, Assembler::pt, no_block);
2349     __ delayed()->nop();
2350     __ bind(L);
2351 
2352     // Block.  Save any potential method result value before the operation and
2353     // use a leaf call to leave the last_Java_frame setup undisturbed. Doing this
2354     // lets us share the oopMap we used when we went native rather the create
2355     // a distinct one for this pc
2356     //
2357     save_native_result(masm, ret_type, stack_slots);
2358     __ call_VM_leaf(L7_thread_cache,
2359                     CAST_FROM_FN_PTR(address, JavaThread::check_special_condition_for_native_trans),
2360                     G2_thread);
2361 
2362     // Restore any method result value
2363     restore_native_result(masm, ret_type, stack_slots);
2364     __ bind(no_block);
2365   }
2366 
2367   // thread state is thread_in_native_trans. Any safepoint blocking has already
2368   // happened so we can now change state to _thread_in_Java.
2369 
2370 
2371   __ set(_thread_in_Java, G3_scratch);
2372   __ st(G3_scratch, G2_thread, JavaThread::thread_state_offset());
2373 
2374 
2375   Label no_reguard;
2376   __ ld(G2_thread, JavaThread::stack_guard_state_offset(), G3_scratch);
2377   __ cmp(G3_scratch, JavaThread::stack_guard_yellow_disabled);
2378   __ br(Assembler::notEqual, false, Assembler::pt, no_reguard);
2379   __ delayed()->nop();
2380 
2381     save_native_result(masm, ret_type, stack_slots);
2382   __ call(CAST_FROM_FN_PTR(address, SharedRuntime::reguard_yellow_pages));
2383   __ delayed()->nop();
2384 
2385   __ restore_thread(L7_thread_cache); // restore G2_thread
2386     restore_native_result(masm, ret_type, stack_slots);
2387 
2388   __ bind(no_reguard);
2389 
2390   // Handle possible exception (will unlock if necessary)
2391 
2392   // native result if any is live in freg or I0 (and I1 if long and 32bit vm)
2393 
2394   // Unlock
2395   if (method->is_synchronized()) {
2396     Label done;
2397     Register I2_ex_oop = I2;
2398     const Register L3_box = L3;
2399     // Get locked oop from the handle we passed to jni
2400     __ ld_ptr(L6_handle, 0, L4);
2401     __ add(SP, lock_offset+STACK_BIAS, L3_box);
2402     // Must save pending exception around the slow-path VM call.  Since it's a
2403     // leaf call, the pending exception (if any) can be kept in a register.
2404     __ ld_ptr(G2_thread, in_bytes(Thread::pending_exception_offset()), I2_ex_oop);
2405     // Now unlock
2406     //                       (Roop, Rmark, Rbox,   Rscratch)
2407     __ compiler_unlock_object(L4,   L1,    L3_box, L2);
2408     __ br(Assembler::equal, false, Assembler::pt, done);
2409     __ delayed()-> add(SP, lock_offset+STACK_BIAS, L3_box);
2410 
2411     // save and restore any potential method result value around the unlocking
2412     // operation.  Will save in I0 (or stack for FP returns).
2413     save_native_result(masm, ret_type, stack_slots);
2414 
2415     // Must clear pending-exception before re-entering the VM.  Since this is
2416     // a leaf call, pending-exception-oop can be safely kept in a register.
2417     __ st_ptr(G0, G2_thread, in_bytes(Thread::pending_exception_offset()));
2418 
2419     // slow case of monitor enter.  Inline a special case of call_VM that
2420     // disallows any pending_exception.
2421     __ mov(L3_box, O1);
2422 
2423     __ call(CAST_FROM_FN_PTR(address, SharedRuntime::complete_monitor_unlocking_C), relocInfo::runtime_call_type);
2424     __ delayed()->mov(L4, O0);              // Need oop in O0
2425 
2426     __ restore_thread(L7_thread_cache); // restore G2_thread
2427 
2428 #ifdef ASSERT
2429     { Label L;
2430     __ ld_ptr(G2_thread, in_bytes(Thread::pending_exception_offset()), O0);
2431     __ br_null(O0, false, Assembler::pt, L);
2432     __ delayed()->nop();
2433     __ stop("no pending exception allowed on exit from IR::monitorexit");
2434     __ bind(L);
2435     }
2436 #endif
2437     restore_native_result(masm, ret_type, stack_slots);
2438     // check_forward_pending_exception jump to forward_exception if any pending
2439     // exception is set.  The forward_exception routine expects to see the
2440     // exception in pending_exception and not in a register.  Kind of clumsy,
2441     // since all folks who branch to forward_exception must have tested
2442     // pending_exception first and hence have it in a register already.
2443     __ st_ptr(I2_ex_oop, G2_thread, in_bytes(Thread::pending_exception_offset()));
2444     __ bind(done);
2445   }
2446 
2447   // Tell dtrace about this method exit
2448   {
2449     SkipIfEqual skip_if(
2450       masm, G3_scratch, &DTraceMethodProbes, Assembler::zero);
2451     save_native_result(masm, ret_type, stack_slots);
2452     __ set_oop_constant(JNIHandles::make_local(method()), O1);
2453     __ call_VM_leaf(L7_thread_cache,
2454        CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit),
2455        G2_thread, O1);
2456     restore_native_result(masm, ret_type, stack_slots);
2457   }
2458 
2459   // Clear "last Java frame" SP and PC.
2460   __ verify_thread(); // G2_thread must be correct
2461   __ reset_last_Java_frame();
2462 
2463   // Unpack oop result
2464   if (ret_type == T_OBJECT || ret_type == T_ARRAY) {
2465       Label L;
2466       __ addcc(G0, I0, G0);
2467       __ brx(Assembler::notZero, true, Assembler::pt, L);
2468       __ delayed()->ld_ptr(I0, 0, I0);
2469       __ mov(G0, I0);
2470       __ bind(L);
2471       __ verify_oop(I0);
2472   }
2473 
2474   // reset handle block
2475   __ ld_ptr(G2_thread, in_bytes(JavaThread::active_handles_offset()), L5);
2476   __ st_ptr(G0, L5, JNIHandleBlock::top_offset_in_bytes());
2477 
2478   __ ld_ptr(G2_thread, in_bytes(Thread::pending_exception_offset()), G3_scratch);
2479   check_forward_pending_exception(masm, G3_scratch);
2480 
2481 
2482   // Return
2483 
2484 #ifndef _LP64
2485   if (ret_type == T_LONG) {
2486 
2487     // Must leave proper result in O0,O1 and G1 (c2/tiered only)
2488     __ sllx(I0, 32, G1);          // Shift bits into high G1
2489     __ srl (I1, 0, I1);           // Zero extend O1 (harmless?)
2490     __ or3 (I1, G1, G1);          // OR 64 bits into G1
2491   }
2492 #endif
2493 
2494   __ ret();
2495   __ delayed()->restore();
2496 
2497   __ flush();
2498 
2499   nmethod *nm = nmethod::new_native_nmethod(method,
2500                                             masm->code(),
2501                                             vep_offset,
2502                                             frame_complete,
2503                                             stack_slots / VMRegImpl::slots_per_word,
2504                                             (is_static ? in_ByteSize(klass_offset) : in_ByteSize(receiver_offset)),
2505                                             in_ByteSize(lock_offset),
2506                                             oop_maps);
2507   return nm;
2508 
2509 }
2510 
2511 #ifdef HAVE_DTRACE_H
2512 // ---------------------------------------------------------------------------
2513 // Generate a dtrace nmethod for a given signature.  The method takes arguments
2514 // in the Java compiled code convention, marshals them to the native
2515 // abi and then leaves nops at the position you would expect to call a native
2516 // function. When the probe is enabled the nops are replaced with a trap
2517 // instruction that dtrace inserts and the trace will cause a notification
2518 // to dtrace.
2519 //
2520 // The probes are only able to take primitive types and java/lang/String as
2521 // arguments.  No other java types are allowed. Strings are converted to utf8
2522 // strings so that from dtrace point of view java strings are converted to C
2523 // strings. There is an arbitrary fixed limit on the total space that a method
2524 // can use for converting the strings. (256 chars per string in the signature).
2525 // So any java string larger then this is truncated.
2526 
2527 static int  fp_offset[ConcreteRegisterImpl::number_of_registers] = { 0 };
2528 static bool offsets_initialized = false;
2529 
2530 static VMRegPair reg64_to_VMRegPair(Register r) {
2531   VMRegPair ret;
2532   if (wordSize == 8) {
2533     ret.set2(r->as_VMReg());
2534   } else {
2535     ret.set_pair(r->successor()->as_VMReg(), r->as_VMReg());
2536   }
2537   return ret;
2538 }
2539 
2540 
2541 nmethod *SharedRuntime::generate_dtrace_nmethod(
2542     MacroAssembler *masm, methodHandle method) {
2543 
2544 
2545   // generate_dtrace_nmethod is guarded by a mutex so we are sure to
2546   // be single threaded in this method.
2547   assert(AdapterHandlerLibrary_lock->owned_by_self(), "must be");
2548 
2549   // Fill in the signature array, for the calling-convention call.
2550   int total_args_passed = method->size_of_parameters();
2551 
2552   BasicType* in_sig_bt  = NEW_RESOURCE_ARRAY(BasicType, total_args_passed);
2553   VMRegPair  *in_regs   = NEW_RESOURCE_ARRAY(VMRegPair, total_args_passed);
2554 
2555   // The signature we are going to use for the trap that dtrace will see
2556   // java/lang/String is converted. We drop "this" and any other object
2557   // is converted to NULL.  (A one-slot java/lang/Long object reference
2558   // is converted to a two-slot long, which is why we double the allocation).
2559   BasicType* out_sig_bt = NEW_RESOURCE_ARRAY(BasicType, total_args_passed * 2);
2560   VMRegPair* out_regs   = NEW_RESOURCE_ARRAY(VMRegPair, total_args_passed * 2);
2561 
2562   int i=0;
2563   int total_strings = 0;
2564   int first_arg_to_pass = 0;
2565   int total_c_args = 0;
2566 
2567   // Skip the receiver as dtrace doesn't want to see it
2568   if( !method->is_static() ) {
2569     in_sig_bt[i++] = T_OBJECT;
2570     first_arg_to_pass = 1;
2571   }
2572 
2573   SignatureStream ss(method->signature());
2574   for ( ; !ss.at_return_type(); ss.next()) {
2575     BasicType bt = ss.type();
2576     in_sig_bt[i++] = bt;  // Collect remaining bits of signature
2577     out_sig_bt[total_c_args++] = bt;
2578     if( bt == T_OBJECT) {
2579       symbolOop s = ss.as_symbol_or_null();
2580       if (s == vmSymbols::java_lang_String()) {
2581         total_strings++;
2582         out_sig_bt[total_c_args-1] = T_ADDRESS;
2583       } else if (s == vmSymbols::java_lang_Boolean() ||
2584                  s == vmSymbols::java_lang_Byte()) {
2585         out_sig_bt[total_c_args-1] = T_BYTE;
2586       } else if (s == vmSymbols::java_lang_Character() ||
2587                  s == vmSymbols::java_lang_Short()) {
2588         out_sig_bt[total_c_args-1] = T_SHORT;
2589       } else if (s == vmSymbols::java_lang_Integer() ||
2590                  s == vmSymbols::java_lang_Float()) {
2591         out_sig_bt[total_c_args-1] = T_INT;
2592       } else if (s == vmSymbols::java_lang_Long() ||
2593                  s == vmSymbols::java_lang_Double()) {
2594         out_sig_bt[total_c_args-1] = T_LONG;
2595         out_sig_bt[total_c_args++] = T_VOID;
2596       }
2597     } else if ( bt == T_LONG || bt == T_DOUBLE ) {
2598       in_sig_bt[i++] = T_VOID;   // Longs & doubles take 2 Java slots
2599       // We convert double to long
2600       out_sig_bt[total_c_args-1] = T_LONG;
2601       out_sig_bt[total_c_args++] = T_VOID;
2602     } else if ( bt == T_FLOAT) {
2603       // We convert float to int
2604       out_sig_bt[total_c_args-1] = T_INT;
2605     }
2606   }
2607 
2608   assert(i==total_args_passed, "validly parsed signature");
2609 
2610   // Now get the compiled-Java layout as input arguments
2611   int comp_args_on_stack;
2612   comp_args_on_stack = SharedRuntime::java_calling_convention(
2613       in_sig_bt, in_regs, total_args_passed, false);
2614 
2615   // We have received a description of where all the java arg are located
2616   // on entry to the wrapper. We need to convert these args to where
2617   // the a  native (non-jni) function would expect them. To figure out
2618   // where they go we convert the java signature to a C signature and remove
2619   // T_VOID for any long/double we might have received.
2620 
2621 
2622   // Now figure out where the args must be stored and how much stack space
2623   // they require (neglecting out_preserve_stack_slots but space for storing
2624   // the 1st six register arguments). It's weird see int_stk_helper.
2625   //
2626   int out_arg_slots;
2627   out_arg_slots = c_calling_convention(out_sig_bt, out_regs, total_c_args);
2628 
2629   // Calculate the total number of stack slots we will need.
2630 
2631   // First count the abi requirement plus all of the outgoing args
2632   int stack_slots = SharedRuntime::out_preserve_stack_slots() + out_arg_slots;
2633 
2634   // Plus a temp for possible converion of float/double/long register args
2635 
2636   int conversion_temp = stack_slots;
2637   stack_slots += 2;
2638 
2639 
2640   // Now space for the string(s) we must convert
2641 
2642   int string_locs = stack_slots;
2643   stack_slots += total_strings *
2644                    (max_dtrace_string_size / VMRegImpl::stack_slot_size);
2645 
2646   // Ok The space we have allocated will look like:
2647   //
2648   //
2649   // FP-> |                     |
2650   //      |---------------------|
2651   //      | string[n]           |
2652   //      |---------------------| <- string_locs[n]
2653   //      | string[n-1]         |
2654   //      |---------------------| <- string_locs[n-1]
2655   //      | ...                 |
2656   //      | ...                 |
2657   //      |---------------------| <- string_locs[1]
2658   //      | string[0]           |
2659   //      |---------------------| <- string_locs[0]
2660   //      | temp                |
2661   //      |---------------------| <- conversion_temp
2662   //      | outbound memory     |
2663   //      | based arguments     |
2664   //      |                     |
2665   //      |---------------------|
2666   //      |                     |
2667   // SP-> | out_preserved_slots |
2668   //
2669   //
2670 
2671   // Now compute actual number of stack words we need rounding to make
2672   // stack properly aligned.
2673   stack_slots = round_to(stack_slots, 4 * VMRegImpl::slots_per_word);
2674 
2675   int stack_size = stack_slots * VMRegImpl::stack_slot_size;
2676 
2677   intptr_t start = (intptr_t)__ pc();
2678 
2679   // First thing make an ic check to see if we should even be here
2680 
2681   {
2682     Label L;
2683     const Register temp_reg = G3_scratch;
2684     AddressLiteral ic_miss(SharedRuntime::get_ic_miss_stub());
2685     __ verify_oop(O0);
2686     __ ld_ptr(O0, oopDesc::klass_offset_in_bytes(), temp_reg);
2687     __ cmp(temp_reg, G5_inline_cache_reg);
2688     __ brx(Assembler::equal, true, Assembler::pt, L);
2689     __ delayed()->nop();
2690 
2691     __ jump_to(ic_miss, temp_reg);
2692     __ delayed()->nop();
2693     __ align(CodeEntryAlignment);
2694     __ bind(L);
2695   }
2696 
2697   int vep_offset = ((intptr_t)__ pc()) - start;
2698 
2699 
2700   // The instruction at the verified entry point must be 5 bytes or longer
2701   // because it can be patched on the fly by make_non_entrant. The stack bang
2702   // instruction fits that requirement.
2703 
2704   // Generate stack overflow check before creating frame
2705   __ generate_stack_overflow_check(stack_size);
2706 
2707   assert(((intptr_t)__ pc() - start - vep_offset) >= 5,
2708          "valid size for make_non_entrant");
2709 
2710   // Generate a new frame for the wrapper.
2711   __ save(SP, -stack_size, SP);
2712 
2713   // Frame is now completed as far a size and linkage.
2714 
2715   int frame_complete = ((intptr_t)__ pc()) - start;
2716 
2717 #ifdef ASSERT
2718   bool reg_destroyed[RegisterImpl::number_of_registers];
2719   bool freg_destroyed[FloatRegisterImpl::number_of_registers];
2720   for ( int r = 0 ; r < RegisterImpl::number_of_registers ; r++ ) {
2721     reg_destroyed[r] = false;
2722   }
2723   for ( int f = 0 ; f < FloatRegisterImpl::number_of_registers ; f++ ) {
2724     freg_destroyed[f] = false;
2725   }
2726 
2727 #endif /* ASSERT */
2728 
2729   VMRegPair zero;
2730   const Register g0 = G0; // without this we get a compiler warning (why??)
2731   zero.set2(g0->as_VMReg());
2732 
2733   int c_arg, j_arg;
2734 
2735   Register conversion_off = noreg;
2736 
2737   for (j_arg = first_arg_to_pass, c_arg = 0 ;
2738        j_arg < total_args_passed ; j_arg++, c_arg++ ) {
2739 
2740     VMRegPair src = in_regs[j_arg];
2741     VMRegPair dst = out_regs[c_arg];
2742 
2743 #ifdef ASSERT
2744     if (src.first()->is_Register()) {
2745       assert(!reg_destroyed[src.first()->as_Register()->encoding()], "ack!");
2746     } else if (src.first()->is_FloatRegister()) {
2747       assert(!freg_destroyed[src.first()->as_FloatRegister()->encoding(
2748                                                FloatRegisterImpl::S)], "ack!");
2749     }
2750     if (dst.first()->is_Register()) {
2751       reg_destroyed[dst.first()->as_Register()->encoding()] = true;
2752     } else if (dst.first()->is_FloatRegister()) {
2753       freg_destroyed[dst.first()->as_FloatRegister()->encoding(
2754                                                  FloatRegisterImpl::S)] = true;
2755     }
2756 #endif /* ASSERT */
2757 
2758     switch (in_sig_bt[j_arg]) {
2759       case T_ARRAY:
2760       case T_OBJECT:
2761         {
2762           if (out_sig_bt[c_arg] == T_BYTE  || out_sig_bt[c_arg] == T_SHORT ||
2763               out_sig_bt[c_arg] == T_INT || out_sig_bt[c_arg] == T_LONG) {
2764             // need to unbox a one-slot value
2765             Register in_reg = L0;
2766             Register tmp = L2;
2767             if ( src.first()->is_reg() ) {
2768               in_reg = src.first()->as_Register();
2769             } else {
2770               assert(Assembler::is_simm13(reg2offset(src.first()) + STACK_BIAS),
2771                      "must be");
2772               __ ld_ptr(FP, reg2offset(src.first()) + STACK_BIAS, in_reg);
2773             }
2774             // If the final destination is an acceptable register
2775             if ( dst.first()->is_reg() ) {
2776               if ( dst.is_single_phys_reg() || out_sig_bt[c_arg] != T_LONG ) {
2777                 tmp = dst.first()->as_Register();
2778               }
2779             }
2780 
2781             Label skipUnbox;
2782             if ( wordSize == 4 && out_sig_bt[c_arg] == T_LONG ) {
2783               __ mov(G0, tmp->successor());
2784             }
2785             __ br_null(in_reg, true, Assembler::pn, skipUnbox);
2786             __ delayed()->mov(G0, tmp);
2787 
2788             BasicType bt = out_sig_bt[c_arg];
2789             int box_offset = java_lang_boxing_object::value_offset_in_bytes(bt);
2790             switch (bt) {
2791                 case T_BYTE:
2792                   __ ldub(in_reg, box_offset, tmp); break;
2793                 case T_SHORT:
2794                   __ lduh(in_reg, box_offset, tmp); break;
2795                 case T_INT:
2796                   __ ld(in_reg, box_offset, tmp); break;
2797                 case T_LONG:
2798                   __ ld_long(in_reg, box_offset, tmp); break;
2799                 default: ShouldNotReachHere();
2800             }
2801 
2802             __ bind(skipUnbox);
2803             // If tmp wasn't final destination copy to final destination
2804             if (tmp == L2) {
2805               VMRegPair tmp_as_VM = reg64_to_VMRegPair(L2);
2806               if (out_sig_bt[c_arg] == T_LONG) {
2807                 long_move(masm, tmp_as_VM, dst);
2808               } else {
2809                 move32_64(masm, tmp_as_VM, out_regs[c_arg]);
2810               }
2811             }
2812             if (out_sig_bt[c_arg] == T_LONG) {
2813               assert(out_sig_bt[c_arg+1] == T_VOID, "must be");
2814               ++c_arg; // move over the T_VOID to keep the loop indices in sync
2815             }
2816           } else if (out_sig_bt[c_arg] == T_ADDRESS) {
2817             Register s =
2818                 src.first()->is_reg() ? src.first()->as_Register() : L2;
2819             Register d =
2820                 dst.first()->is_reg() ? dst.first()->as_Register() : L2;
2821 
2822             // We store the oop now so that the conversion pass can reach
2823             // while in the inner frame. This will be the only store if
2824             // the oop is NULL.
2825             if (s != L2) {
2826               // src is register
2827               if (d != L2) {
2828                 // dst is register
2829                 __ mov(s, d);
2830               } else {
2831                 assert(Assembler::is_simm13(reg2offset(dst.first()) +
2832                           STACK_BIAS), "must be");
2833                 __ st_ptr(s, SP, reg2offset(dst.first()) + STACK_BIAS);
2834               }
2835             } else {
2836                 // src not a register
2837                 assert(Assembler::is_simm13(reg2offset(src.first()) +
2838                            STACK_BIAS), "must be");
2839                 __ ld_ptr(FP, reg2offset(src.first()) + STACK_BIAS, d);
2840                 if (d == L2) {
2841                   assert(Assembler::is_simm13(reg2offset(dst.first()) +
2842                              STACK_BIAS), "must be");
2843                   __ st_ptr(d, SP, reg2offset(dst.first()) + STACK_BIAS);
2844                 }
2845             }
2846           } else if (out_sig_bt[c_arg] != T_VOID) {
2847             // Convert the arg to NULL
2848             if (dst.first()->is_reg()) {
2849               __ mov(G0, dst.first()->as_Register());
2850             } else {
2851               assert(Assembler::is_simm13(reg2offset(dst.first()) +
2852                          STACK_BIAS), "must be");
2853               __ st_ptr(G0, SP, reg2offset(dst.first()) + STACK_BIAS);
2854             }
2855           }
2856         }
2857         break;
2858       case T_VOID:
2859         break;
2860 
2861       case T_FLOAT:
2862         if (src.first()->is_stack()) {
2863           // Stack to stack/reg is simple
2864           move32_64(masm, src, dst);
2865         } else {
2866           if (dst.first()->is_reg()) {
2867             // freg -> reg
2868             int off =
2869               STACK_BIAS + conversion_temp * VMRegImpl::stack_slot_size;
2870             Register d = dst.first()->as_Register();
2871             if (Assembler::is_simm13(off)) {
2872               __ stf(FloatRegisterImpl::S, src.first()->as_FloatRegister(),
2873                      SP, off);
2874               __ ld(SP, off, d);
2875             } else {
2876               if (conversion_off == noreg) {
2877                 __ set(off, L6);
2878                 conversion_off = L6;
2879               }
2880               __ stf(FloatRegisterImpl::S, src.first()->as_FloatRegister(),
2881                      SP, conversion_off);
2882               __ ld(SP, conversion_off , d);
2883             }
2884           } else {
2885             // freg -> mem
2886             int off = STACK_BIAS + reg2offset(dst.first());
2887             if (Assembler::is_simm13(off)) {
2888               __ stf(FloatRegisterImpl::S, src.first()->as_FloatRegister(),
2889                      SP, off);
2890             } else {
2891               if (conversion_off == noreg) {
2892                 __ set(off, L6);
2893                 conversion_off = L6;
2894               }
2895               __ stf(FloatRegisterImpl::S, src.first()->as_FloatRegister(),
2896                      SP, conversion_off);
2897             }
2898           }
2899         }
2900         break;
2901 
2902       case T_DOUBLE:
2903         assert( j_arg + 1 < total_args_passed &&
2904                 in_sig_bt[j_arg + 1] == T_VOID &&
2905                 out_sig_bt[c_arg+1] == T_VOID, "bad arg list");
2906         if (src.first()->is_stack()) {
2907           // Stack to stack/reg is simple
2908           long_move(masm, src, dst);
2909         } else {
2910           Register d = dst.first()->is_reg() ? dst.first()->as_Register() : L2;
2911 
2912           // Destination could be an odd reg on 32bit in which case
2913           // we can't load direct to the destination.
2914 
2915           if (!d->is_even() && wordSize == 4) {
2916             d = L2;
2917           }
2918           int off = STACK_BIAS + conversion_temp * VMRegImpl::stack_slot_size;
2919           if (Assembler::is_simm13(off)) {
2920             __ stf(FloatRegisterImpl::D, src.first()->as_FloatRegister(),
2921                    SP, off);
2922             __ ld_long(SP, off, d);
2923           } else {
2924             if (conversion_off == noreg) {
2925               __ set(off, L6);
2926               conversion_off = L6;
2927             }
2928             __ stf(FloatRegisterImpl::D, src.first()->as_FloatRegister(),
2929                    SP, conversion_off);
2930             __ ld_long(SP, conversion_off, d);
2931           }
2932           if (d == L2) {
2933             long_move(masm, reg64_to_VMRegPair(L2), dst);
2934           }
2935         }
2936         break;
2937 
2938       case T_LONG :
2939         // 32bit can't do a split move of something like g1 -> O0, O1
2940         // so use a memory temp
2941         if (src.is_single_phys_reg() && wordSize == 4) {
2942           Register tmp = L2;
2943           if (dst.first()->is_reg() &&
2944               (wordSize == 8 || dst.first()->as_Register()->is_even())) {
2945             tmp = dst.first()->as_Register();
2946           }
2947 
2948           int off = STACK_BIAS + conversion_temp * VMRegImpl::stack_slot_size;
2949           if (Assembler::is_simm13(off)) {
2950             __ stx(src.first()->as_Register(), SP, off);
2951             __ ld_long(SP, off, tmp);
2952           } else {
2953             if (conversion_off == noreg) {
2954               __ set(off, L6);
2955               conversion_off = L6;
2956             }
2957             __ stx(src.first()->as_Register(), SP, conversion_off);
2958             __ ld_long(SP, conversion_off, tmp);
2959           }
2960 
2961           if (tmp == L2) {
2962             long_move(masm, reg64_to_VMRegPair(L2), dst);
2963           }
2964         } else {
2965           long_move(masm, src, dst);
2966         }
2967         break;
2968 
2969       case T_ADDRESS: assert(false, "found T_ADDRESS in java args");
2970 
2971       default:
2972         move32_64(masm, src, dst);
2973     }
2974   }
2975 
2976 
2977   // If we have any strings we must store any register based arg to the stack
2978   // This includes any still live xmm registers too.
2979 
2980   if (total_strings > 0 ) {
2981 
2982     // protect all the arg registers
2983     __ save_frame(0);
2984     __ mov(G2_thread, L7_thread_cache);
2985     const Register L2_string_off = L2;
2986 
2987     // Get first string offset
2988     __ set(string_locs * VMRegImpl::stack_slot_size, L2_string_off);
2989 
2990     for (c_arg = 0 ; c_arg < total_c_args ; c_arg++ ) {
2991       if (out_sig_bt[c_arg] == T_ADDRESS) {
2992 
2993         VMRegPair dst = out_regs[c_arg];
2994         const Register d = dst.first()->is_reg() ?
2995             dst.first()->as_Register()->after_save() : noreg;
2996 
2997         // It's a string the oop and it was already copied to the out arg
2998         // position
2999         if (d != noreg) {
3000           __ mov(d, O0);
3001         } else {
3002           assert(Assembler::is_simm13(reg2offset(dst.first()) + STACK_BIAS),
3003                  "must be");
3004           __ ld_ptr(FP,  reg2offset(dst.first()) + STACK_BIAS, O0);
3005         }
3006         Label skip;
3007 
3008         __ br_null(O0, false, Assembler::pn, skip);
3009         __ delayed()->add(FP, L2_string_off, O1);
3010 
3011         if (d != noreg) {
3012           __ mov(O1, d);
3013         } else {
3014           assert(Assembler::is_simm13(reg2offset(dst.first()) + STACK_BIAS),
3015                  "must be");
3016           __ st_ptr(O1, FP,  reg2offset(dst.first()) + STACK_BIAS);
3017         }
3018 
3019         __ call(CAST_FROM_FN_PTR(address, SharedRuntime::get_utf),
3020                 relocInfo::runtime_call_type);
3021         __ delayed()->add(L2_string_off, max_dtrace_string_size, L2_string_off);
3022 
3023         __ bind(skip);
3024 
3025       }
3026 
3027     }
3028     __ mov(L7_thread_cache, G2_thread);
3029     __ restore();
3030 
3031   }
3032 
3033 
3034   // Ok now we are done. Need to place the nop that dtrace wants in order to
3035   // patch in the trap
3036 
3037   int patch_offset = ((intptr_t)__ pc()) - start;
3038 
3039   __ nop();
3040 
3041 
3042   // Return
3043 
3044   __ ret();
3045   __ delayed()->restore();
3046 
3047   __ flush();
3048 
3049   nmethod *nm = nmethod::new_dtrace_nmethod(
3050       method, masm->code(), vep_offset, patch_offset, frame_complete,
3051       stack_slots / VMRegImpl::slots_per_word);
3052   return nm;
3053 
3054 }
3055 
3056 #endif // HAVE_DTRACE_H
3057 
3058 // this function returns the adjust size (in number of words) to a c2i adapter
3059 // activation for use during deoptimization
3060 int Deoptimization::last_frame_adjust(int callee_parameters, int callee_locals) {
3061   assert(callee_locals >= callee_parameters,
3062           "test and remove; got more parms than locals");
3063   if (callee_locals < callee_parameters)
3064     return 0;                   // No adjustment for negative locals
3065   int diff = (callee_locals - callee_parameters) * Interpreter::stackElementWords();
3066   return round_to(diff, WordsPerLong);
3067 }
3068 
3069 // "Top of Stack" slots that may be unused by the calling convention but must
3070 // otherwise be preserved.
3071 // On Intel these are not necessary and the value can be zero.
3072 // On Sparc this describes the words reserved for storing a register window
3073 // when an interrupt occurs.
3074 uint SharedRuntime::out_preserve_stack_slots() {
3075   return frame::register_save_words * VMRegImpl::slots_per_word;
3076 }
3077 
3078 static void gen_new_frame(MacroAssembler* masm, bool deopt) {
3079 //
3080 // Common out the new frame generation for deopt and uncommon trap
3081 //
3082   Register        G3pcs              = G3_scratch; // Array of new pcs (input)
3083   Register        Oreturn0           = O0;
3084   Register        Oreturn1           = O1;
3085   Register        O2UnrollBlock      = O2;
3086   Register        O3array            = O3;         // Array of frame sizes (input)
3087   Register        O4array_size       = O4;         // number of frames (input)
3088   Register        O7frame_size       = O7;         // number of frames (input)
3089 
3090   __ ld_ptr(O3array, 0, O7frame_size);
3091   __ sub(G0, O7frame_size, O7frame_size);
3092   __ save(SP, O7frame_size, SP);
3093   __ ld_ptr(G3pcs, 0, I7);                      // load frame's new pc
3094 
3095   #ifdef ASSERT
3096   // make sure that the frames are aligned properly
3097 #ifndef _LP64
3098   __ btst(wordSize*2-1, SP);
3099   __ breakpoint_trap(Assembler::notZero);
3100 #endif
3101   #endif
3102 
3103   // Deopt needs to pass some extra live values from frame to frame
3104 
3105   if (deopt) {
3106     __ mov(Oreturn0->after_save(), Oreturn0);
3107     __ mov(Oreturn1->after_save(), Oreturn1);
3108   }
3109 
3110   __ mov(O4array_size->after_save(), O4array_size);
3111   __ sub(O4array_size, 1, O4array_size);
3112   __ mov(O3array->after_save(), O3array);
3113   __ mov(O2UnrollBlock->after_save(), O2UnrollBlock);
3114   __ add(G3pcs, wordSize, G3pcs);               // point to next pc value
3115 
3116   #ifdef ASSERT
3117   // trash registers to show a clear pattern in backtraces
3118   __ set(0xDEAD0000, I0);
3119   __ add(I0,  2, I1);
3120   __ add(I0,  4, I2);
3121   __ add(I0,  6, I3);
3122   __ add(I0,  8, I4);
3123   // Don't touch I5 could have valuable savedSP
3124   __ set(0xDEADBEEF, L0);
3125   __ mov(L0, L1);
3126   __ mov(L0, L2);
3127   __ mov(L0, L3);
3128   __ mov(L0, L4);
3129   __ mov(L0, L5);
3130 
3131   // trash the return value as there is nothing to return yet
3132   __ set(0xDEAD0001, O7);
3133   #endif
3134 
3135   __ mov(SP, O5_savedSP);
3136 }
3137 
3138 
3139 static void make_new_frames(MacroAssembler* masm, bool deopt) {
3140   //
3141   // loop through the UnrollBlock info and create new frames
3142   //
3143   Register        G3pcs              = G3_scratch;
3144   Register        Oreturn0           = O0;
3145   Register        Oreturn1           = O1;
3146   Register        O2UnrollBlock      = O2;
3147   Register        O3array            = O3;
3148   Register        O4array_size       = O4;
3149   Label           loop;
3150 
3151   // Before we make new frames, check to see if stack is available.
3152   // Do this after the caller's return address is on top of stack
3153   if (UseStackBanging) {
3154     // Get total frame size for interpreted frames
3155     __ ld(O2UnrollBlock, Deoptimization::UnrollBlock::total_frame_sizes_offset_in_bytes(), O4);
3156     __ bang_stack_size(O4, O3, G3_scratch);
3157   }
3158 
3159   __ ld(O2UnrollBlock, Deoptimization::UnrollBlock::number_of_frames_offset_in_bytes(), O4array_size);
3160   __ ld_ptr(O2UnrollBlock, Deoptimization::UnrollBlock::frame_pcs_offset_in_bytes(), G3pcs);
3161   __ ld_ptr(O2UnrollBlock, Deoptimization::UnrollBlock::frame_sizes_offset_in_bytes(), O3array);
3162 
3163   // Adjust old interpreter frame to make space for new frame's extra java locals
3164   //
3165   // We capture the original sp for the transition frame only because it is needed in
3166   // order to properly calculate interpreter_sp_adjustment. Even though in real life
3167   // every interpreter frame captures a savedSP it is only needed at the transition
3168   // (fortunately). If we had to have it correct everywhere then we would need to
3169   // be told the sp_adjustment for each frame we create. If the frame size array
3170   // were to have twice the frame count entries then we could have pairs [sp_adjustment, frame_size]
3171   // for each frame we create and keep up the illusion every where.
3172   //
3173 
3174   __ ld(O2UnrollBlock, Deoptimization::UnrollBlock::caller_adjustment_offset_in_bytes(), O7);
3175   __ mov(SP, O5_savedSP);       // remember initial sender's original sp before adjustment
3176   __ sub(SP, O7, SP);
3177 
3178 #ifdef ASSERT
3179   // make sure that there is at least one entry in the array
3180   __ tst(O4array_size);
3181   __ breakpoint_trap(Assembler::zero);
3182 #endif
3183 
3184   // Now push the new interpreter frames
3185   __ bind(loop);
3186 
3187   // allocate a new frame, filling the registers
3188 
3189   gen_new_frame(masm, deopt);        // allocate an interpreter frame
3190 
3191   __ tst(O4array_size);
3192   __ br(Assembler::notZero, false, Assembler::pn, loop);
3193   __ delayed()->add(O3array, wordSize, O3array);
3194   __ ld_ptr(G3pcs, 0, O7);                      // load final frame new pc
3195 
3196 }
3197 
3198 //------------------------------generate_deopt_blob----------------------------
3199 // Ought to generate an ideal graph & compile, but here's some SPARC ASM
3200 // instead.
3201 void SharedRuntime::generate_deopt_blob() {
3202   // allocate space for the code
3203   ResourceMark rm;
3204   // setup code generation tools
3205   int pad = VerifyThread ? 512 : 0;// Extra slop space for more verify code
3206 #ifdef _LP64
3207   CodeBuffer buffer("deopt_blob", 2100+pad, 512);
3208 #else
3209   // Measured 8/7/03 at 1212 in 32bit debug build (no VerifyThread)
3210   // Measured 8/7/03 at 1396 in 32bit debug build (VerifyThread)
3211   CodeBuffer buffer("deopt_blob", 1600+pad, 512);
3212 #endif /* _LP64 */
3213   MacroAssembler* masm               = new MacroAssembler(&buffer);
3214   FloatRegister   Freturn0           = F0;
3215   Register        Greturn1           = G1;
3216   Register        Oreturn0           = O0;
3217   Register        Oreturn1           = O1;
3218   Register        O2UnrollBlock      = O2;
3219   Register        L0deopt_mode       = L0;
3220   Register        G4deopt_mode       = G4_scratch;
3221   int             frame_size_words;
3222   Address         saved_Freturn0_addr(FP, -sizeof(double) + STACK_BIAS);
3223 #if !defined(_LP64) && defined(COMPILER2)
3224   Address         saved_Greturn1_addr(FP, -sizeof(double) -sizeof(jlong) + STACK_BIAS);
3225 #endif
3226   Label           cont;
3227 
3228   OopMapSet *oop_maps = new OopMapSet();
3229 
3230   //
3231   // This is the entry point for code which is returning to a de-optimized
3232   // frame.
3233   // The steps taken by this frame are as follows:
3234   //   - push a dummy "register_save" and save the return values (O0, O1, F0/F1, G1)
3235   //     and all potentially live registers (at a pollpoint many registers can be live).
3236   //
3237   //   - call the C routine: Deoptimization::fetch_unroll_info (this function
3238   //     returns information about the number and size of interpreter frames
3239   //     which are equivalent to the frame which is being deoptimized)
3240   //   - deallocate the unpack frame, restoring only results values. Other
3241   //     volatile registers will now be captured in the vframeArray as needed.
3242   //   - deallocate the deoptimization frame
3243   //   - in a loop using the information returned in the previous step
3244   //     push new interpreter frames (take care to propagate the return
3245   //     values through each new frame pushed)
3246   //   - create a dummy "unpack_frame" and save the return values (O0, O1, F0)
3247   //   - call the C routine: Deoptimization::unpack_frames (this function
3248   //     lays out values on the interpreter frame which was just created)
3249   //   - deallocate the dummy unpack_frame
3250   //   - ensure that all the return values are correctly set and then do
3251   //     a return to the interpreter entry point
3252   //
3253   // Refer to the following methods for more information:
3254   //   - Deoptimization::fetch_unroll_info
3255   //   - Deoptimization::unpack_frames
3256 
3257   OopMap* map = NULL;
3258 
3259   int start = __ offset();
3260 
3261   // restore G2, the trampoline destroyed it
3262   __ get_thread();
3263 
3264   // On entry we have been called by the deoptimized nmethod with a call that
3265   // replaced the original call (or safepoint polling location) so the deoptimizing
3266   // pc is now in O7. Return values are still in the expected places
3267 
3268   map = RegisterSaver::save_live_registers(masm, 0, &frame_size_words);
3269   __ ba(false, cont);
3270   __ delayed()->mov(Deoptimization::Unpack_deopt, L0deopt_mode);
3271 
3272   int exception_offset = __ offset() - start;
3273 
3274   // restore G2, the trampoline destroyed it
3275   __ get_thread();
3276 
3277   // On entry we have been jumped to by the exception handler (or exception_blob
3278   // for server).  O0 contains the exception oop and O7 contains the original
3279   // exception pc.  So if we push a frame here it will look to the
3280   // stack walking code (fetch_unroll_info) just like a normal call so
3281   // state will be extracted normally.
3282 
3283   // save exception oop in JavaThread and fall through into the
3284   // exception_in_tls case since they are handled in same way except
3285   // for where the pending exception is kept.
3286   __ st_ptr(Oexception, G2_thread, JavaThread::exception_oop_offset());
3287 
3288   //
3289   // Vanilla deoptimization with an exception pending in exception_oop
3290   //
3291   int exception_in_tls_offset = __ offset() - start;
3292 
3293   // No need to update oop_map  as each call to save_live_registers will produce identical oopmap
3294   (void) RegisterSaver::save_live_registers(masm, 0, &frame_size_words);
3295 
3296   // Restore G2_thread
3297   __ get_thread();
3298 
3299 #ifdef ASSERT
3300   {
3301     // verify that there is really an exception oop in exception_oop
3302     Label has_exception;
3303     __ ld_ptr(G2_thread, JavaThread::exception_oop_offset(), Oexception);
3304     __ br_notnull(Oexception, false, Assembler::pt, has_exception);
3305     __ delayed()-> nop();
3306     __ stop("no exception in thread");
3307     __ bind(has_exception);
3308 
3309     // verify that there is no pending exception
3310     Label no_pending_exception;
3311     Address exception_addr(G2_thread, Thread::pending_exception_offset());
3312     __ ld_ptr(exception_addr, Oexception);
3313     __ br_null(Oexception, false, Assembler::pt, no_pending_exception);
3314     __ delayed()->nop();
3315     __ stop("must not have pending exception here");
3316     __ bind(no_pending_exception);
3317   }
3318 #endif
3319 
3320   __ ba(false, cont);
3321   __ delayed()->mov(Deoptimization::Unpack_exception, L0deopt_mode);;
3322 
3323   //
3324   // Reexecute entry, similar to c2 uncommon trap
3325   //
3326   int reexecute_offset = __ offset() - start;
3327 
3328   // No need to update oop_map  as each call to save_live_registers will produce identical oopmap
3329   (void) RegisterSaver::save_live_registers(masm, 0, &frame_size_words);
3330 
3331   __ mov(Deoptimization::Unpack_reexecute, L0deopt_mode);
3332 
3333   __ bind(cont);
3334 
3335   __ set_last_Java_frame(SP, noreg);
3336 
3337   // do the call by hand so we can get the oopmap
3338 
3339   __ mov(G2_thread, L7_thread_cache);
3340   __ call(CAST_FROM_FN_PTR(address, Deoptimization::fetch_unroll_info), relocInfo::runtime_call_type);
3341   __ delayed()->mov(G2_thread, O0);
3342 
3343   // Set an oopmap for the call site this describes all our saved volatile registers
3344 
3345   oop_maps->add_gc_map( __ offset()-start, map);
3346 
3347   __ mov(L7_thread_cache, G2_thread);
3348 
3349   __ reset_last_Java_frame();
3350 
3351   // NOTE: we know that only O0/O1 will be reloaded by restore_result_registers
3352   // so this move will survive
3353 
3354   __ mov(L0deopt_mode, G4deopt_mode);
3355 
3356   __ mov(O0, O2UnrollBlock->after_save());
3357 
3358   RegisterSaver::restore_result_registers(masm);
3359 
3360   Label noException;
3361   __ cmp(G4deopt_mode, Deoptimization::Unpack_exception);   // Was exception pending?
3362   __ br(Assembler::notEqual, false, Assembler::pt, noException);
3363   __ delayed()->nop();
3364 
3365   // Move the pending exception from exception_oop to Oexception so
3366   // the pending exception will be picked up the interpreter.
3367   __ ld_ptr(G2_thread, in_bytes(JavaThread::exception_oop_offset()), Oexception);
3368   __ st_ptr(G0, G2_thread, in_bytes(JavaThread::exception_oop_offset()));
3369   __ bind(noException);
3370 
3371   // deallocate the deoptimization frame taking care to preserve the return values
3372   __ mov(Oreturn0,     Oreturn0->after_save());
3373   __ mov(Oreturn1,     Oreturn1->after_save());
3374   __ mov(O2UnrollBlock, O2UnrollBlock->after_save());
3375   __ restore();
3376 
3377   // Allocate new interpreter frame(s) and possible c2i adapter frame
3378 
3379   make_new_frames(masm, true);
3380 
3381   // push a dummy "unpack_frame" taking care of float return values and
3382   // call Deoptimization::unpack_frames to have the unpacker layout
3383   // information in the interpreter frames just created and then return
3384   // to the interpreter entry point
3385   __ save(SP, -frame_size_words*wordSize, SP);
3386   __ stf(FloatRegisterImpl::D, Freturn0, saved_Freturn0_addr);
3387 #if !defined(_LP64)
3388 #if defined(COMPILER2)
3389   if (!TieredCompilation) {
3390     // 32-bit 1-register longs return longs in G1
3391     __ stx(Greturn1, saved_Greturn1_addr);
3392   }
3393 #endif
3394   __ set_last_Java_frame(SP, noreg);
3395   __ call_VM_leaf(L7_thread_cache, CAST_FROM_FN_PTR(address, Deoptimization::unpack_frames), G2_thread, G4deopt_mode);
3396 #else
3397   // LP64 uses g4 in set_last_Java_frame
3398   __ mov(G4deopt_mode, O1);
3399   __ set_last_Java_frame(SP, G0);
3400   __ call_VM_leaf(L7_thread_cache, CAST_FROM_FN_PTR(address, Deoptimization::unpack_frames), G2_thread, O1);
3401 #endif
3402   __ reset_last_Java_frame();
3403   __ ldf(FloatRegisterImpl::D, saved_Freturn0_addr, Freturn0);
3404 
3405   // In tiered we never use C2 to compile methods returning longs so
3406   // the result is where we expect it already.
3407 
3408 #if !defined(_LP64) && defined(COMPILER2)
3409   // In 32 bit, C2 returns longs in G1 so restore the saved G1 into
3410   // I0/I1 if the return value is long.  In the tiered world there is
3411   // a mismatch between how C1 and C2 return longs compiles and so
3412   // currently compilation of methods which return longs is disabled
3413   // for C2 and so is this code.  Eventually C1 and C2 will do the
3414   // same thing for longs in the tiered world.
3415   if (!TieredCompilation) {
3416     Label not_long;
3417     __ cmp(O0,T_LONG);
3418     __ br(Assembler::notEqual, false, Assembler::pt, not_long);
3419     __ delayed()->nop();
3420     __ ldd(saved_Greturn1_addr,I0);
3421     __ bind(not_long);
3422   }
3423 #endif
3424   __ ret();
3425   __ delayed()->restore();
3426 
3427   masm->flush();
3428   _deopt_blob = DeoptimizationBlob::create(&buffer, oop_maps, 0, exception_offset, reexecute_offset, frame_size_words);
3429   _deopt_blob->set_unpack_with_exception_in_tls_offset(exception_in_tls_offset);
3430 }
3431 
3432 #ifdef COMPILER2
3433 
3434 //------------------------------generate_uncommon_trap_blob--------------------
3435 // Ought to generate an ideal graph & compile, but here's some SPARC ASM
3436 // instead.
3437 void SharedRuntime::generate_uncommon_trap_blob() {
3438   // allocate space for the code
3439   ResourceMark rm;
3440   // setup code generation tools
3441   int pad = VerifyThread ? 512 : 0;
3442 #ifdef _LP64
3443   CodeBuffer buffer("uncommon_trap_blob", 2700+pad, 512);
3444 #else
3445   // Measured 8/7/03 at 660 in 32bit debug build (no VerifyThread)
3446   // Measured 8/7/03 at 1028 in 32bit debug build (VerifyThread)
3447   CodeBuffer buffer("uncommon_trap_blob", 2000+pad, 512);
3448 #endif
3449   MacroAssembler* masm               = new MacroAssembler(&buffer);
3450   Register        O2UnrollBlock      = O2;
3451   Register        O2klass_index      = O2;
3452 
3453   //
3454   // This is the entry point for all traps the compiler takes when it thinks
3455   // it cannot handle further execution of compilation code. The frame is
3456   // deoptimized in these cases and converted into interpreter frames for
3457   // execution
3458   // The steps taken by this frame are as follows:
3459   //   - push a fake "unpack_frame"
3460   //   - call the C routine Deoptimization::uncommon_trap (this function
3461   //     packs the current compiled frame into vframe arrays and returns
3462   //     information about the number and size of interpreter frames which
3463   //     are equivalent to the frame which is being deoptimized)
3464   //   - deallocate the "unpack_frame"
3465   //   - deallocate the deoptimization frame
3466   //   - in a loop using the information returned in the previous step
3467   //     push interpreter frames;
3468   //   - create a dummy "unpack_frame"
3469   //   - call the C routine: Deoptimization::unpack_frames (this function
3470   //     lays out values on the interpreter frame which was just created)
3471   //   - deallocate the dummy unpack_frame
3472   //   - return to the interpreter entry point
3473   //
3474   //  Refer to the following methods for more information:
3475   //   - Deoptimization::uncommon_trap
3476   //   - Deoptimization::unpack_frame
3477 
3478   // the unloaded class index is in O0 (first parameter to this blob)
3479 
3480   // push a dummy "unpack_frame"
3481   // and call Deoptimization::uncommon_trap to pack the compiled frame into
3482   // vframe array and return the UnrollBlock information
3483   __ save_frame(0);
3484   __ set_last_Java_frame(SP, noreg);
3485   __ mov(I0, O2klass_index);
3486   __ call_VM_leaf(L7_thread_cache, CAST_FROM_FN_PTR(address, Deoptimization::uncommon_trap), G2_thread, O2klass_index);
3487   __ reset_last_Java_frame();
3488   __ mov(O0, O2UnrollBlock->after_save());
3489   __ restore();
3490 
3491   // deallocate the deoptimized frame taking care to preserve the return values
3492   __ mov(O2UnrollBlock, O2UnrollBlock->after_save());
3493   __ restore();
3494 
3495   // Allocate new interpreter frame(s) and possible c2i adapter frame
3496 
3497   make_new_frames(masm, false);
3498 
3499   // push a dummy "unpack_frame" taking care of float return values and
3500   // call Deoptimization::unpack_frames to have the unpacker layout
3501   // information in the interpreter frames just created and then return
3502   // to the interpreter entry point
3503   __ save_frame(0);
3504   __ set_last_Java_frame(SP, noreg);
3505   __ mov(Deoptimization::Unpack_uncommon_trap, O3); // indicate it is the uncommon trap case
3506   __ call_VM_leaf(L7_thread_cache, CAST_FROM_FN_PTR(address, Deoptimization::unpack_frames), G2_thread, O3);
3507   __ reset_last_Java_frame();
3508   __ ret();
3509   __ delayed()->restore();
3510 
3511   masm->flush();
3512   _uncommon_trap_blob = UncommonTrapBlob::create(&buffer, NULL, __ total_frame_size_in_bytes(0)/wordSize);
3513 }
3514 
3515 #endif // COMPILER2
3516 
3517 //------------------------------generate_handler_blob-------------------
3518 //
3519 // Generate a special Compile2Runtime blob that saves all registers, and sets
3520 // up an OopMap.
3521 //
3522 // This blob is jumped to (via a breakpoint and the signal handler) from a
3523 // safepoint in compiled code.  On entry to this blob, O7 contains the
3524 // address in the original nmethod at which we should resume normal execution.
3525 // Thus, this blob looks like a subroutine which must preserve lots of
3526 // registers and return normally.  Note that O7 is never register-allocated,
3527 // so it is guaranteed to be free here.
3528 //
3529 
3530 // The hardest part of what this blob must do is to save the 64-bit %o
3531 // registers in the 32-bit build.  A simple 'save' turn the %o's to %i's and
3532 // an interrupt will chop off their heads.  Making space in the caller's frame
3533 // first will let us save the 64-bit %o's before save'ing, but we cannot hand
3534 // the adjusted FP off to the GC stack-crawler: this will modify the caller's
3535 // SP and mess up HIS OopMaps.  So we first adjust the caller's SP, then save
3536 // the 64-bit %o's, then do a save, then fixup the caller's SP (our FP).
3537 // Tricky, tricky, tricky...
3538 
3539 static SafepointBlob* generate_handler_blob(address call_ptr, bool cause_return) {
3540   assert (StubRoutines::forward_exception_entry() != NULL, "must be generated before");
3541 
3542   // allocate space for the code
3543   ResourceMark rm;
3544   // setup code generation tools
3545   // Measured 8/7/03 at 896 in 32bit debug build (no VerifyThread)
3546   // Measured 8/7/03 at 1080 in 32bit debug build (VerifyThread)
3547   // even larger with TraceJumps
3548   int pad = TraceJumps ? 512 : 0;
3549   CodeBuffer buffer("handler_blob", 1600 + pad, 512);
3550   MacroAssembler* masm                = new MacroAssembler(&buffer);
3551   int             frame_size_words;
3552   OopMapSet *oop_maps = new OopMapSet();
3553   OopMap* map = NULL;
3554 
3555   int start = __ offset();
3556 
3557   // If this causes a return before the processing, then do a "restore"
3558   if (cause_return) {
3559     __ restore();
3560   } else {
3561     // Make it look like we were called via the poll
3562     // so that frame constructor always sees a valid return address
3563     __ ld_ptr(G2_thread, in_bytes(JavaThread::saved_exception_pc_offset()), O7);
3564     __ sub(O7, frame::pc_return_offset, O7);
3565   }
3566 
3567   map = RegisterSaver::save_live_registers(masm, 0, &frame_size_words);
3568 
3569   // setup last_Java_sp (blows G4)
3570   __ set_last_Java_frame(SP, noreg);
3571 
3572   // call into the runtime to handle illegal instructions exception
3573   // Do not use call_VM_leaf, because we need to make a GC map at this call site.
3574   __ mov(G2_thread, O0);
3575   __ save_thread(L7_thread_cache);
3576   __ call(call_ptr);
3577   __ delayed()->nop();
3578 
3579   // Set an oopmap for the call site.
3580   // We need this not only for callee-saved registers, but also for volatile
3581   // registers that the compiler might be keeping live across a safepoint.
3582 
3583   oop_maps->add_gc_map( __ offset() - start, map);
3584 
3585   __ restore_thread(L7_thread_cache);
3586   // clear last_Java_sp
3587   __ reset_last_Java_frame();
3588 
3589   // Check for exceptions
3590   Label pending;
3591 
3592   __ ld_ptr(G2_thread, in_bytes(Thread::pending_exception_offset()), O1);
3593   __ tst(O1);
3594   __ brx(Assembler::notEqual, true, Assembler::pn, pending);
3595   __ delayed()->nop();
3596 
3597   RegisterSaver::restore_live_registers(masm);
3598 
3599   // We are back the the original state on entry and ready to go.
3600 
3601   __ retl();
3602   __ delayed()->nop();
3603 
3604   // Pending exception after the safepoint
3605 
3606   __ bind(pending);
3607 
3608   RegisterSaver::restore_live_registers(masm);
3609 
3610   // We are back the the original state on entry.
3611 
3612   // Tail-call forward_exception_entry, with the issuing PC in O7,
3613   // so it looks like the original nmethod called forward_exception_entry.
3614   __ set((intptr_t)StubRoutines::forward_exception_entry(), O0);
3615   __ JMP(O0, 0);
3616   __ delayed()->nop();
3617 
3618   // -------------
3619   // make sure all code is generated
3620   masm->flush();
3621 
3622   // return exception blob
3623   return SafepointBlob::create(&buffer, oop_maps, frame_size_words);
3624 }
3625 
3626 //
3627 // generate_resolve_blob - call resolution (static/virtual/opt-virtual/ic-miss
3628 //
3629 // Generate a stub that calls into vm to find out the proper destination
3630 // of a java call. All the argument registers are live at this point
3631 // but since this is generic code we don't know what they are and the caller
3632 // must do any gc of the args.
3633 //
3634 static RuntimeStub* generate_resolve_blob(address destination, const char* name) {
3635   assert (StubRoutines::forward_exception_entry() != NULL, "must be generated before");
3636 
3637   // allocate space for the code
3638   ResourceMark rm;
3639   // setup code generation tools
3640   // Measured 8/7/03 at 896 in 32bit debug build (no VerifyThread)
3641   // Measured 8/7/03 at 1080 in 32bit debug build (VerifyThread)
3642   // even larger with TraceJumps
3643   int pad = TraceJumps ? 512 : 0;
3644   CodeBuffer buffer(name, 1600 + pad, 512);
3645   MacroAssembler* masm                = new MacroAssembler(&buffer);
3646   int             frame_size_words;
3647   OopMapSet *oop_maps = new OopMapSet();
3648   OopMap* map = NULL;
3649 
3650   int start = __ offset();
3651 
3652   map = RegisterSaver::save_live_registers(masm, 0, &frame_size_words);
3653 
3654   int frame_complete = __ offset();
3655 
3656   // setup last_Java_sp (blows G4)
3657   __ set_last_Java_frame(SP, noreg);
3658 
3659   // call into the runtime to handle illegal instructions exception
3660   // Do not use call_VM_leaf, because we need to make a GC map at this call site.
3661   __ mov(G2_thread, O0);
3662   __ save_thread(L7_thread_cache);
3663   __ call(destination, relocInfo::runtime_call_type);
3664   __ delayed()->nop();
3665 
3666   // O0 contains the address we are going to jump to assuming no exception got installed
3667 
3668   // Set an oopmap for the call site.
3669   // We need this not only for callee-saved registers, but also for volatile
3670   // registers that the compiler might be keeping live across a safepoint.
3671 
3672   oop_maps->add_gc_map( __ offset() - start, map);
3673 
3674   __ restore_thread(L7_thread_cache);
3675   // clear last_Java_sp
3676   __ reset_last_Java_frame();
3677 
3678   // Check for exceptions
3679   Label pending;
3680 
3681   __ ld_ptr(G2_thread, in_bytes(Thread::pending_exception_offset()), O1);
3682   __ tst(O1);
3683   __ brx(Assembler::notEqual, true, Assembler::pn, pending);
3684   __ delayed()->nop();
3685 
3686   // get the returned methodOop
3687 
3688   __ get_vm_result(G5_method);
3689   __ stx(G5_method, SP, RegisterSaver::G5_offset()+STACK_BIAS);
3690 
3691   // O0 is where we want to jump, overwrite G3 which is saved and scratch
3692 
3693   __ stx(O0, SP, RegisterSaver::G3_offset()+STACK_BIAS);
3694 
3695   RegisterSaver::restore_live_registers(masm);
3696 
3697   // We are back the the original state on entry and ready to go.
3698 
3699   __ JMP(G3, 0);
3700   __ delayed()->nop();
3701 
3702   // Pending exception after the safepoint
3703 
3704   __ bind(pending);
3705 
3706   RegisterSaver::restore_live_registers(masm);
3707 
3708   // We are back the the original state on entry.
3709 
3710   // Tail-call forward_exception_entry, with the issuing PC in O7,
3711   // so it looks like the original nmethod called forward_exception_entry.
3712   __ set((intptr_t)StubRoutines::forward_exception_entry(), O0);
3713   __ JMP(O0, 0);
3714   __ delayed()->nop();
3715 
3716   // -------------
3717   // make sure all code is generated
3718   masm->flush();
3719 
3720   // return the  blob
3721   // frame_size_words or bytes??
3722   return RuntimeStub::new_runtime_stub(name, &buffer, frame_complete, frame_size_words, oop_maps, true);
3723 }
3724 
3725 void SharedRuntime::generate_stubs() {
3726 
3727   _wrong_method_blob = generate_resolve_blob(CAST_FROM_FN_PTR(address, SharedRuntime::handle_wrong_method),
3728                                              "wrong_method_stub");
3729 
3730   _ic_miss_blob = generate_resolve_blob(CAST_FROM_FN_PTR(address, SharedRuntime::handle_wrong_method_ic_miss),
3731                                         "ic_miss_stub");
3732 
3733   _resolve_opt_virtual_call_blob = generate_resolve_blob(CAST_FROM_FN_PTR(address, SharedRuntime::resolve_opt_virtual_call_C),
3734                                         "resolve_opt_virtual_call");
3735 
3736   _resolve_virtual_call_blob = generate_resolve_blob(CAST_FROM_FN_PTR(address, SharedRuntime::resolve_virtual_call_C),
3737                                         "resolve_virtual_call");
3738 
3739   _resolve_static_call_blob = generate_resolve_blob(CAST_FROM_FN_PTR(address, SharedRuntime::resolve_static_call_C),
3740                                         "resolve_static_call");
3741 
3742   _polling_page_safepoint_handler_blob =
3743     generate_handler_blob(CAST_FROM_FN_PTR(address,
3744                    SafepointSynchronize::handle_polling_page_exception), false);
3745 
3746   _polling_page_return_handler_blob =
3747     generate_handler_blob(CAST_FROM_FN_PTR(address,
3748                    SafepointSynchronize::handle_polling_page_exception), true);
3749 
3750   generate_deopt_blob();
3751 
3752 #ifdef COMPILER2
3753   generate_uncommon_trap_blob();
3754 #endif // COMPILER2
3755 }
--- EOF ---