1 /* 2 * Copyright 2000-2010 Sun Microsystems, Inc. All Rights Reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 20 * CA 95054 USA or visit www.sun.com if you need additional information or 21 * have any questions. 22 * 23 */ 24 25 class Compilation; 26 class ScopeValue; 27 class BarrierSet; 28 29 class LIR_Assembler: public CompilationResourceObj { 30 private: 31 C1_MacroAssembler* _masm; 32 CodeStubList* _slow_case_stubs; 33 BarrierSet* _bs; 34 35 Compilation* _compilation; 36 FrameMap* _frame_map; 37 BlockBegin* _current_block; 38 39 Instruction* _pending_non_safepoint; 40 int _pending_non_safepoint_offset; 41 42 #ifdef ASSERT 43 BlockList _branch_target_blocks; 44 void check_no_unbound_labels(); 45 #endif 46 47 FrameMap* frame_map() const { return _frame_map; } 48 49 void set_current_block(BlockBegin* b) { _current_block = b; } 50 BlockBegin* current_block() const { return _current_block; } 51 52 // non-safepoint debug info management 53 void flush_debug_info(int before_pc_offset) { 54 if (_pending_non_safepoint != NULL) { 55 if (_pending_non_safepoint_offset < before_pc_offset) 56 record_non_safepoint_debug_info(); 57 _pending_non_safepoint = NULL; 58 } 59 } 60 void process_debug_info(LIR_Op* op); 61 void record_non_safepoint_debug_info(); 62 63 // unified bailout support 64 void bailout(const char* msg) const { compilation()->bailout(msg); } 65 bool bailed_out() const { return compilation()->bailed_out(); } 66 67 // code emission patterns and accessors 68 void check_codespace(); 69 bool needs_icache(ciMethod* method) const; 70 71 // returns offset of icache check 72 int check_icache(); 73 74 void jobject2reg(jobject o, Register reg); 75 void jobject2reg_with_patching(Register reg, CodeEmitInfo* info); 76 77 void emit_stubs(CodeStubList* stub_list); 78 79 // addresses 80 Address as_Address(LIR_Address* addr); 81 Address as_Address_lo(LIR_Address* addr); 82 Address as_Address_hi(LIR_Address* addr); 83 84 // debug information 85 void add_call_info(int pc_offset, CodeEmitInfo* cinfo, bool is_method_handle_invoke = false); 86 void add_debug_info_for_branch(CodeEmitInfo* info); 87 void add_debug_info_for_div0(int pc_offset, CodeEmitInfo* cinfo); 88 void add_debug_info_for_div0_here(CodeEmitInfo* info); 89 void add_debug_info_for_null_check(int pc_offset, CodeEmitInfo* cinfo); 90 void add_debug_info_for_null_check_here(CodeEmitInfo* info); 91 92 void set_24bit_FPU(); 93 void reset_FPU(); 94 void fpop(); 95 void fxch(int i); 96 void fld(int i); 97 void ffree(int i); 98 99 void breakpoint(); 100 void push(LIR_Opr opr); 101 void pop(LIR_Opr opr); 102 103 // patching 104 void append_patching_stub(PatchingStub* stub); 105 void patching_epilog(PatchingStub* patch, LIR_PatchCode patch_code, Register obj, CodeEmitInfo* info); 106 107 void comp_op(LIR_Condition condition, LIR_Opr src, LIR_Opr result, LIR_Op2* op); 108 109 public: 110 LIR_Assembler(Compilation* c); 111 ~LIR_Assembler(); 112 C1_MacroAssembler* masm() const { return _masm; } 113 Compilation* compilation() const { return _compilation; } 114 ciMethod* method() const { return compilation()->method(); } 115 116 CodeOffsets* offsets() const { return _compilation->offsets(); } 117 int code_offset() const; 118 address pc() const; 119 120 int initial_frame_size_in_bytes(); 121 122 // test for constants which can be encoded directly in instructions 123 static bool is_small_constant(LIR_Opr opr); 124 125 static LIR_Opr receiverOpr(); 126 static LIR_Opr incomingReceiverOpr(); 127 static LIR_Opr osrBufferPointer(); 128 129 // stubs 130 void emit_slow_case_stubs(); 131 void emit_static_call_stub(); 132 void emit_code_stub(CodeStub* op); 133 void add_call_info_here(CodeEmitInfo* info) { add_call_info(code_offset(), info); } 134 135 // code patterns 136 int emit_exception_handler(); 137 void emit_exception_entries(ExceptionInfoList* info_list); 138 int emit_deopt_handler(); 139 140 void emit_code(BlockList* hir); 141 void emit_block(BlockBegin* block); 142 void emit_lir_list(LIR_List* list); 143 144 // any last minute peephole optimizations are performed here. In 145 // particular sparc uses this for delay slot filling. 146 void peephole(LIR_List* list); 147 148 void emit_string_compare(LIR_Opr left, LIR_Opr right, LIR_Opr dst, CodeEmitInfo* info); 149 150 void return_op(LIR_Opr result); 151 152 // returns offset of poll instruction 153 int safepoint_poll(LIR_Opr result, CodeEmitInfo* info); 154 155 void const2reg (LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info); 156 void const2stack(LIR_Opr src, LIR_Opr dest); 157 void const2mem (LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info); 158 void reg2stack (LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack); 159 void reg2reg (LIR_Opr src, LIR_Opr dest); 160 void reg2mem (LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool unaligned); 161 void stack2reg (LIR_Opr src, LIR_Opr dest, BasicType type); 162 void stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type); 163 void mem2reg (LIR_Opr src, LIR_Opr dest, BasicType type, 164 LIR_PatchCode patch_code = lir_patch_none, 165 CodeEmitInfo* info = NULL, bool unaligned = false); 166 167 void prefetchr (LIR_Opr src); 168 void prefetchw (LIR_Opr src); 169 170 void shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp); 171 void shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest); 172 173 void move_regs(Register from_reg, Register to_reg); 174 void swap_reg(Register a, Register b); 175 176 void emit_op0(LIR_Op0* op); 177 void emit_op1(LIR_Op1* op); 178 void emit_op2(LIR_Op2* op); 179 void emit_op3(LIR_Op3* op); 180 void emit_opBranch(LIR_OpBranch* op); 181 void emit_opLabel(LIR_OpLabel* op); 182 void emit_arraycopy(LIR_OpArrayCopy* op); 183 void emit_opConvert(LIR_OpConvert* op); 184 void emit_alloc_obj(LIR_OpAllocObj* op); 185 void emit_alloc_array(LIR_OpAllocArray* op); 186 void emit_opTypeCheck(LIR_OpTypeCheck* op); 187 void emit_compare_and_swap(LIR_OpCompareAndSwap* op); 188 void emit_lock(LIR_OpLock* op); 189 void emit_call(LIR_OpJavaCall* op); 190 void emit_rtcall(LIR_OpRTCall* op); 191 void emit_profile_call(LIR_OpProfileCall* op); 192 void emit_delay(LIR_OpDelay* op); 193 194 void arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack); 195 void arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info); 196 void intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr unused, LIR_Opr dest, LIR_Op* op); 197 198 void logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest); 199 200 void roundfp_op(LIR_Opr src, LIR_Opr tmp, LIR_Opr dest, bool pop_fpu_stack); 201 void move_op(LIR_Opr src, LIR_Opr result, BasicType type, 202 LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool unaligned); 203 void volatile_move_op(LIR_Opr src, LIR_Opr result, BasicType type, CodeEmitInfo* info); 204 void comp_mem_op(LIR_Opr src, LIR_Opr result, BasicType type, CodeEmitInfo* info); // info set for null exceptions 205 void comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr result, LIR_Op2* op); 206 void cmove(LIR_Condition code, LIR_Opr left, LIR_Opr right, LIR_Opr result); 207 208 void call( LIR_OpJavaCall* op, relocInfo::relocType rtype); 209 void ic_call( LIR_OpJavaCall* op); 210 void vtable_call( LIR_OpJavaCall* op); 211 212 // JSR 292 213 void preserve_SP(LIR_OpJavaCall* op); 214 void restore_SP( LIR_OpJavaCall* op); 215 216 void osr_entry(); 217 218 void build_frame(); 219 220 void throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info, bool unwind); 221 void monitor_address(int monitor_ix, LIR_Opr dst); 222 223 void align_backward_branch_target(); 224 void align_call(LIR_Code code); 225 226 void negate(LIR_Opr left, LIR_Opr dest); 227 void leal(LIR_Opr left, LIR_Opr dest); 228 229 void rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info); 230 231 void membar(); 232 void membar_acquire(); 233 void membar_release(); 234 void get_thread(LIR_Opr result); 235 236 void verify_oop_map(CodeEmitInfo* info); 237 238 #include "incls/_c1_LIRAssembler_pd.hpp.incl" 239 };