1 /*
   2  * Copyright 1999-2010 Sun Microsystems, Inc.  All Rights Reserved.
   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
  20  * CA 95054 USA or visit www.sun.com if you need additional information or
  21  * have any questions.
  22  *
  23  */
  24 
  25  public:
  26 
  27   enum {
  28     nof_reg_args = 6,   // registers o0-o5 are available for parameter passing
  29     first_available_sp_in_frame = frame::memory_parameter_word_sp_offset * BytesPerWord,
  30     frame_pad_in_bytes = 0
  31   };
  32 
  33   static const int pd_c_runtime_reserved_arg_size;
  34 
  35   static LIR_Opr G0_opr;
  36   static LIR_Opr G1_opr;
  37   static LIR_Opr G2_opr;
  38   static LIR_Opr G3_opr;
  39   static LIR_Opr G4_opr;
  40   static LIR_Opr G5_opr;
  41   static LIR_Opr G6_opr;
  42   static LIR_Opr G7_opr;
  43   static LIR_Opr O0_opr;
  44   static LIR_Opr O1_opr;
  45   static LIR_Opr O2_opr;
  46   static LIR_Opr O3_opr;
  47   static LIR_Opr O4_opr;
  48   static LIR_Opr O5_opr;
  49   static LIR_Opr O6_opr;
  50   static LIR_Opr O7_opr;
  51   static LIR_Opr L0_opr;
  52   static LIR_Opr L1_opr;
  53   static LIR_Opr L2_opr;
  54   static LIR_Opr L3_opr;
  55   static LIR_Opr L4_opr;
  56   static LIR_Opr L5_opr;
  57   static LIR_Opr L6_opr;
  58   static LIR_Opr L7_opr;
  59   static LIR_Opr I0_opr;
  60   static LIR_Opr I1_opr;
  61   static LIR_Opr I2_opr;
  62   static LIR_Opr I3_opr;
  63   static LIR_Opr I4_opr;
  64   static LIR_Opr I5_opr;
  65   static LIR_Opr I6_opr;
  66   static LIR_Opr I7_opr;
  67 
  68   static LIR_Opr SP_opr;
  69   static LIR_Opr FP_opr;
  70 
  71   static LIR_Opr G0_oop_opr;
  72   static LIR_Opr G1_oop_opr;
  73   static LIR_Opr G2_oop_opr;
  74   static LIR_Opr G3_oop_opr;
  75   static LIR_Opr G4_oop_opr;
  76   static LIR_Opr G5_oop_opr;
  77   static LIR_Opr G6_oop_opr;
  78   static LIR_Opr G7_oop_opr;
  79   static LIR_Opr O0_oop_opr;
  80   static LIR_Opr O1_oop_opr;
  81   static LIR_Opr O2_oop_opr;
  82   static LIR_Opr O3_oop_opr;
  83   static LIR_Opr O4_oop_opr;
  84   static LIR_Opr O5_oop_opr;
  85   static LIR_Opr O6_oop_opr;
  86   static LIR_Opr O7_oop_opr;
  87   static LIR_Opr L0_oop_opr;
  88   static LIR_Opr L1_oop_opr;
  89   static LIR_Opr L2_oop_opr;
  90   static LIR_Opr L3_oop_opr;
  91   static LIR_Opr L4_oop_opr;
  92   static LIR_Opr L5_oop_opr;
  93   static LIR_Opr L6_oop_opr;
  94   static LIR_Opr L7_oop_opr;
  95   static LIR_Opr I0_oop_opr;
  96   static LIR_Opr I1_oop_opr;
  97   static LIR_Opr I2_oop_opr;
  98   static LIR_Opr I3_oop_opr;
  99   static LIR_Opr I4_oop_opr;
 100   static LIR_Opr I5_oop_opr;
 101   static LIR_Opr I6_oop_opr;
 102   static LIR_Opr I7_oop_opr;
 103 
 104   static LIR_Opr in_long_opr;
 105   static LIR_Opr out_long_opr;
 106 
 107   static LIR_Opr F0_opr;
 108   static LIR_Opr F0_double_opr;
 109 
 110   static LIR_Opr Oexception_opr;
 111   static LIR_Opr Oissuing_pc_opr;
 112 
 113  private:
 114   static FloatRegister  _fpu_regs [nof_fpu_regs];
 115 
 116  public:
 117 
 118 #ifdef _LP64
 119   static LIR_Opr as_long_opr(Register r) {
 120     return LIR_OprFact::double_cpu(cpu_reg2rnr(r), cpu_reg2rnr(r));
 121   }
 122   static LIR_Opr as_pointer_opr(Register r) {
 123     return LIR_OprFact::double_cpu(cpu_reg2rnr(r), cpu_reg2rnr(r));
 124   }
 125 #else
 126   static LIR_Opr as_long_opr(Register r) {
 127     return LIR_OprFact::double_cpu(cpu_reg2rnr(r->successor()), cpu_reg2rnr(r));
 128   }
 129   static LIR_Opr as_pointer_opr(Register r) {
 130     return as_opr(r);
 131   }
 132 #endif
 133   static LIR_Opr as_float_opr(FloatRegister r) {
 134     return LIR_OprFact::single_fpu(r->encoding());
 135   }
 136   static LIR_Opr as_double_opr(FloatRegister r) {
 137     return LIR_OprFact::double_fpu(r->successor()->encoding(), r->encoding());
 138   }
 139 
 140   static FloatRegister nr2floatreg (int rnr);
 141 
 142   static VMReg fpu_regname (int n);
 143 
 144   static bool is_caller_save_register (LIR_Opr  reg);
 145   static bool is_caller_save_register (Register r);
 146 
 147   // JSR 292
 148   static LIR_Opr& method_handle_invoke_SP_save_opr() { return L7_opr; }