1 /*
   2  * Copyright 2000-2010 Sun Microsystems, Inc.  All Rights Reserved.
   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
  20  * CA 95054 USA or visit www.sun.com if you need additional information or
  21  * have any questions.
  22  *
  23  */
  24 
  25 # include "incls/_precompiled.incl"
  26 # include "incls/_c1_LIRAssembler_sparc.cpp.incl"
  27 
  28 #define __ _masm->
  29 
  30 
  31 //------------------------------------------------------------
  32 
  33 
  34 bool LIR_Assembler::is_small_constant(LIR_Opr opr) {
  35   if (opr->is_constant()) {
  36     LIR_Const* constant = opr->as_constant_ptr();
  37     switch (constant->type()) {
  38       case T_INT: {
  39         jint value = constant->as_jint();
  40         return Assembler::is_simm13(value);
  41       }
  42 
  43       default:
  44         return false;
  45     }
  46   }
  47   return false;
  48 }
  49 
  50 
  51 bool LIR_Assembler::is_single_instruction(LIR_Op* op) {
  52   switch (op->code()) {
  53     case lir_null_check:
  54     return true;
  55 
  56 
  57     case lir_add:
  58     case lir_ushr:
  59     case lir_shr:
  60     case lir_shl:
  61       // integer shifts and adds are always one instruction
  62       return op->result_opr()->is_single_cpu();
  63 
  64 
  65     case lir_move: {
  66       LIR_Op1* op1 = op->as_Op1();
  67       LIR_Opr src = op1->in_opr();
  68       LIR_Opr dst = op1->result_opr();
  69 
  70       if (src == dst) {
  71         NEEDS_CLEANUP;
  72         // this works around a problem where moves with the same src and dst
  73         // end up in the delay slot and then the assembler swallows the mov
  74         // since it has no effect and then it complains because the delay slot
  75         // is empty.  returning false stops the optimizer from putting this in
  76         // the delay slot
  77         return false;
  78       }
  79 
  80       // don't put moves involving oops into the delay slot since the VerifyOops code
  81       // will make it much larger than a single instruction.
  82       if (VerifyOops) {
  83         return false;
  84       }
  85 
  86       if (src->is_double_cpu() || dst->is_double_cpu() || op1->patch_code() != lir_patch_none ||
  87           ((src->is_double_fpu() || dst->is_double_fpu()) && op1->move_kind() != lir_move_normal)) {
  88         return false;
  89       }
  90 
  91       if (dst->is_register()) {
  92         if (src->is_address() && Assembler::is_simm13(src->as_address_ptr()->disp())) {
  93           return !PatchALot;
  94         } else if (src->is_single_stack()) {
  95           return true;
  96         }
  97       }
  98 
  99       if (src->is_register()) {
 100         if (dst->is_address() && Assembler::is_simm13(dst->as_address_ptr()->disp())) {
 101           return !PatchALot;
 102         } else if (dst->is_single_stack()) {
 103           return true;
 104         }
 105       }
 106 
 107       if (dst->is_register() &&
 108           ((src->is_register() && src->is_single_word() && src->is_same_type(dst)) ||
 109            (src->is_constant() && LIR_Assembler::is_small_constant(op->as_Op1()->in_opr())))) {
 110         return true;
 111       }
 112 
 113       return false;
 114     }
 115 
 116     default:
 117       return false;
 118   }
 119   ShouldNotReachHere();
 120 }
 121 
 122 
 123 LIR_Opr LIR_Assembler::receiverOpr() {
 124   return FrameMap::O0_oop_opr;
 125 }
 126 
 127 
 128 LIR_Opr LIR_Assembler::incomingReceiverOpr() {
 129   return FrameMap::I0_oop_opr;
 130 }
 131 
 132 
 133 LIR_Opr LIR_Assembler::osrBufferPointer() {
 134   return FrameMap::I0_opr;
 135 }
 136 
 137 
 138 int LIR_Assembler::initial_frame_size_in_bytes() {
 139   return in_bytes(frame_map()->framesize_in_bytes());
 140 }
 141 
 142 
 143 // inline cache check: the inline cached class is in G5_inline_cache_reg(G5);
 144 // we fetch the class of the receiver (O0) and compare it with the cached class.
 145 // If they do not match we jump to slow case.
 146 int LIR_Assembler::check_icache() {
 147   int offset = __ offset();
 148   __ inline_cache_check(O0, G5_inline_cache_reg);
 149   return offset;
 150 }
 151 
 152 
 153 void LIR_Assembler::osr_entry() {
 154   // On-stack-replacement entry sequence (interpreter frame layout described in interpreter_sparc.cpp):
 155   //
 156   //   1. Create a new compiled activation.
 157   //   2. Initialize local variables in the compiled activation.  The expression stack must be empty
 158   //      at the osr_bci; it is not initialized.
 159   //   3. Jump to the continuation address in compiled code to resume execution.
 160 
 161   // OSR entry point
 162   offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
 163   BlockBegin* osr_entry = compilation()->hir()->osr_entry();
 164   ValueStack* entry_state = osr_entry->end()->state();
 165   int number_of_locks = entry_state->locks_size();
 166 
 167   // Create a frame for the compiled activation.
 168   __ build_frame(initial_frame_size_in_bytes());
 169 
 170   // OSR buffer is
 171   //
 172   // locals[nlocals-1..0]
 173   // monitors[number_of_locks-1..0]
 174   //
 175   // locals is a direct copy of the interpreter frame so in the osr buffer
 176   // so first slot in the local array is the last local from the interpreter
 177   // and last slot is local[0] (receiver) from the interpreter
 178   //
 179   // Similarly with locks. The first lock slot in the osr buffer is the nth lock
 180   // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
 181   // in the interpreter frame (the method lock if a sync method)
 182 
 183   // Initialize monitors in the compiled activation.
 184   //   I0: pointer to osr buffer
 185   //
 186   // All other registers are dead at this point and the locals will be
 187   // copied into place by code emitted in the IR.
 188 
 189   Register OSR_buf = osrBufferPointer()->as_register();
 190   { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
 191     int monitor_offset = BytesPerWord * method()->max_locals() +
 192       (2 * BytesPerWord) * (number_of_locks - 1);
 193     // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
 194     // the OSR buffer using 2 word entries: first the lock and then
 195     // the oop.
 196     for (int i = 0; i < number_of_locks; i++) {
 197       int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
 198 #ifdef ASSERT
 199       // verify the interpreter's monitor has a non-null object
 200       {
 201         Label L;
 202         __ ld_ptr(OSR_buf, slot_offset + 1*BytesPerWord, O7);
 203         __ cmp(G0, O7);
 204         __ br(Assembler::notEqual, false, Assembler::pt, L);
 205         __ delayed()->nop();
 206         __ stop("locked object is NULL");
 207         __ bind(L);
 208       }
 209 #endif // ASSERT
 210       // Copy the lock field into the compiled activation.
 211       __ ld_ptr(OSR_buf, slot_offset + 0, O7);
 212       __ st_ptr(O7, frame_map()->address_for_monitor_lock(i));
 213       __ ld_ptr(OSR_buf, slot_offset + 1*BytesPerWord, O7);
 214       __ st_ptr(O7, frame_map()->address_for_monitor_object(i));
 215     }
 216   }
 217 }
 218 
 219 
 220 // Optimized Library calls
 221 // This is the fast version of java.lang.String.compare; it has not
 222 // OSR-entry and therefore, we generate a slow version for OSR's
 223 void LIR_Assembler::emit_string_compare(LIR_Opr left, LIR_Opr right, LIR_Opr dst, CodeEmitInfo* info) {
 224   Register str0 = left->as_register();
 225   Register str1 = right->as_register();
 226 
 227   Label Ldone;
 228 
 229   Register result = dst->as_register();
 230   {
 231     // Get a pointer to the first character of string0 in tmp0 and get string0.count in str0
 232     // Get a pointer to the first character of string1 in tmp1 and get string1.count in str1
 233     // Also, get string0.count-string1.count in o7 and get the condition code set
 234     // Note: some instructions have been hoisted for better instruction scheduling
 235 
 236     Register tmp0 = L0;
 237     Register tmp1 = L1;
 238     Register tmp2 = L2;
 239 
 240     int  value_offset = java_lang_String:: value_offset_in_bytes(); // char array
 241     int offset_offset = java_lang_String::offset_offset_in_bytes(); // first character position
 242     int  count_offset = java_lang_String:: count_offset_in_bytes();
 243 
 244     __ ld_ptr(str0, value_offset, tmp0);
 245     __ ld(str0, offset_offset, tmp2);
 246     __ add(tmp0, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp0);
 247     __ ld(str0, count_offset, str0);
 248     __ sll(tmp2, exact_log2(sizeof(jchar)), tmp2);
 249 
 250     // str1 may be null
 251     add_debug_info_for_null_check_here(info);
 252 
 253     __ ld_ptr(str1, value_offset, tmp1);
 254     __ add(tmp0, tmp2, tmp0);
 255 
 256     __ ld(str1, offset_offset, tmp2);
 257     __ add(tmp1, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp1);
 258     __ ld(str1, count_offset, str1);
 259     __ sll(tmp2, exact_log2(sizeof(jchar)), tmp2);
 260     __ subcc(str0, str1, O7);
 261     __ add(tmp1, tmp2, tmp1);
 262   }
 263 
 264   {
 265     // Compute the minimum of the string lengths, scale it and store it in limit
 266     Register count0 = I0;
 267     Register count1 = I1;
 268     Register limit  = L3;
 269 
 270     Label Lskip;
 271     __ sll(count0, exact_log2(sizeof(jchar)), limit);             // string0 is shorter
 272     __ br(Assembler::greater, true, Assembler::pt, Lskip);
 273     __ delayed()->sll(count1, exact_log2(sizeof(jchar)), limit);  // string1 is shorter
 274     __ bind(Lskip);
 275 
 276     // If either string is empty (or both of them) the result is the difference in lengths
 277     __ cmp(limit, 0);
 278     __ br(Assembler::equal, true, Assembler::pn, Ldone);
 279     __ delayed()->mov(O7, result);  // result is difference in lengths
 280   }
 281 
 282   {
 283     // Neither string is empty
 284     Label Lloop;
 285 
 286     Register base0 = L0;
 287     Register base1 = L1;
 288     Register chr0  = I0;
 289     Register chr1  = I1;
 290     Register limit = L3;
 291 
 292     // Shift base0 and base1 to the end of the arrays, negate limit
 293     __ add(base0, limit, base0);
 294     __ add(base1, limit, base1);
 295     __ neg(limit);  // limit = -min{string0.count, strin1.count}
 296 
 297     __ lduh(base0, limit, chr0);
 298     __ bind(Lloop);
 299     __ lduh(base1, limit, chr1);
 300     __ subcc(chr0, chr1, chr0);
 301     __ br(Assembler::notZero, false, Assembler::pn, Ldone);
 302     assert(chr0 == result, "result must be pre-placed");
 303     __ delayed()->inccc(limit, sizeof(jchar));
 304     __ br(Assembler::notZero, true, Assembler::pt, Lloop);
 305     __ delayed()->lduh(base0, limit, chr0);
 306   }
 307 
 308   // If strings are equal up to min length, return the length difference.
 309   __ mov(O7, result);
 310 
 311   // Otherwise, return the difference between the first mismatched chars.
 312   __ bind(Ldone);
 313 }
 314 
 315 
 316 // --------------------------------------------------------------------------------------------
 317 
 318 void LIR_Assembler::monitorexit(LIR_Opr obj_opr, LIR_Opr lock_opr, Register hdr, int monitor_no) {
 319   if (!GenerateSynchronizationCode) return;
 320 
 321   Register obj_reg = obj_opr->as_register();
 322   Register lock_reg = lock_opr->as_register();
 323 
 324   Address mon_addr = frame_map()->address_for_monitor_lock(monitor_no);
 325   Register reg = mon_addr.base();
 326   int offset = mon_addr.disp();
 327   // compute pointer to BasicLock
 328   if (mon_addr.is_simm13()) {
 329     __ add(reg, offset, lock_reg);
 330   }
 331   else {
 332     __ set(offset, lock_reg);
 333     __ add(reg, lock_reg, lock_reg);
 334   }
 335   // unlock object
 336   MonitorAccessStub* slow_case = new MonitorExitStub(lock_opr, UseFastLocking, monitor_no);
 337   // _slow_case_stubs->append(slow_case);
 338   // temporary fix: must be created after exceptionhandler, therefore as call stub
 339   _slow_case_stubs->append(slow_case);
 340   if (UseFastLocking) {
 341     // try inlined fast unlocking first, revert to slow locking if it fails
 342     // note: lock_reg points to the displaced header since the displaced header offset is 0!
 343     assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
 344     __ unlock_object(hdr, obj_reg, lock_reg, *slow_case->entry());
 345   } else {
 346     // always do slow unlocking
 347     // note: the slow unlocking code could be inlined here, however if we use
 348     //       slow unlocking, speed doesn't matter anyway and this solution is
 349     //       simpler and requires less duplicated code - additionally, the
 350     //       slow unlocking code is the same in either case which simplifies
 351     //       debugging
 352     __ br(Assembler::always, false, Assembler::pt, *slow_case->entry());
 353     __ delayed()->nop();
 354   }
 355   // done
 356   __ bind(*slow_case->continuation());
 357 }
 358 
 359 
 360 int LIR_Assembler::emit_exception_handler() {
 361   // if the last instruction is a call (typically to do a throw which
 362   // is coming at the end after block reordering) the return address
 363   // must still point into the code area in order to avoid assertion
 364   // failures when searching for the corresponding bci => add a nop
 365   // (was bug 5/14/1999 - gri)
 366   __ nop();
 367 
 368   // generate code for exception handler
 369   ciMethod* method = compilation()->method();
 370 
 371   address handler_base = __ start_a_stub(exception_handler_size);
 372 
 373   if (handler_base == NULL) {
 374     // not enough space left for the handler
 375     bailout("exception handler overflow");
 376     return -1;
 377   }
 378 
 379   int offset = code_offset();
 380 
 381   __ call(Runtime1::entry_for(Runtime1::handle_exception_id), relocInfo::runtime_call_type);
 382   __ delayed()->nop();
 383   debug_only(__ stop("should have gone to the caller");)
 384   assert(code_offset() - offset <= exception_handler_size, "overflow");
 385   __ end_a_stub();
 386 
 387   return offset;
 388 }
 389 
 390 
 391 // Emit the code to remove the frame from the stack in the exception
 392 // unwind path.
 393 int LIR_Assembler::emit_unwind_handler() {
 394 #ifndef PRODUCT
 395   if (CommentedAssembly) {
 396     _masm->block_comment("Unwind handler");
 397   }
 398 #endif
 399 
 400   int offset = code_offset();
 401 
 402   // Fetch the exception from TLS and clear out exception related thread state
 403   __ ld_ptr(G2_thread, in_bytes(JavaThread::exception_oop_offset()), O0);
 404   __ st_ptr(G0, G2_thread, in_bytes(JavaThread::exception_oop_offset()));
 405   __ st_ptr(G0, G2_thread, in_bytes(JavaThread::exception_pc_offset()));
 406 
 407   __ bind(_unwind_handler_entry);
 408   __ verify_not_null_oop(O0);
 409   if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
 410     __ mov(O0, I0);  // Preserve the exception
 411   }
 412 
 413   // Preform needed unlocking
 414   MonitorExitStub* stub = NULL;
 415   if (method()->is_synchronized()) {
 416     monitor_address(0, FrameMap::I1_opr);
 417     stub = new MonitorExitStub(FrameMap::I1_opr, true, 0);
 418     __ unlock_object(I3, I2, I1, *stub->entry());
 419     __ bind(*stub->continuation());
 420   }
 421 
 422   if (compilation()->env()->dtrace_method_probes()) {
 423     jobject2reg(method()->constant_encoding(), O0);
 424     __ call(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit), relocInfo::runtime_call_type);
 425     __ delayed()->nop();
 426   }
 427 
 428   if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
 429     __ mov(I0, O0);  // Restore the exception
 430   }
 431 
 432   // dispatch to the unwind logic
 433   __ call(Runtime1::entry_for(Runtime1::unwind_exception_id), relocInfo::runtime_call_type);
 434   __ delayed()->nop();
 435 
 436   // Emit the slow path assembly
 437   if (stub != NULL) {
 438     stub->emit_code(this);
 439   }
 440 
 441   return offset;
 442 }
 443 
 444 
 445 int LIR_Assembler::emit_deopt_handler() {
 446   // if the last instruction is a call (typically to do a throw which
 447   // is coming at the end after block reordering) the return address
 448   // must still point into the code area in order to avoid assertion
 449   // failures when searching for the corresponding bci => add a nop
 450   // (was bug 5/14/1999 - gri)
 451   __ nop();
 452 
 453   // generate code for deopt handler
 454   ciMethod* method = compilation()->method();
 455   address handler_base = __ start_a_stub(deopt_handler_size);
 456   if (handler_base == NULL) {
 457     // not enough space left for the handler
 458     bailout("deopt handler overflow");
 459     return -1;
 460   }
 461 
 462   int offset = code_offset();
 463   AddressLiteral deopt_blob(SharedRuntime::deopt_blob()->unpack());
 464   __ JUMP(deopt_blob, G3_scratch, 0); // sethi;jmp
 465   __ delayed()->nop();
 466   assert(code_offset() - offset <= deopt_handler_size, "overflow");
 467   debug_only(__ stop("should have gone to the caller");)
 468   __ end_a_stub();
 469 
 470   return offset;
 471 }
 472 
 473 
 474 void LIR_Assembler::jobject2reg(jobject o, Register reg) {
 475   if (o == NULL) {
 476     __ set(NULL_WORD, reg);
 477   } else {
 478     int oop_index = __ oop_recorder()->find_index(o);
 479     RelocationHolder rspec = oop_Relocation::spec(oop_index);
 480     __ set(NULL_WORD, reg, rspec); // Will be set when the nmethod is created
 481   }
 482 }
 483 
 484 
 485 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo *info) {
 486   // Allocate a new index in oop table to hold the oop once it's been patched
 487   int oop_index = __ oop_recorder()->allocate_index((jobject)NULL);
 488   PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id, oop_index);
 489 
 490   AddressLiteral addrlit(NULL, oop_Relocation::spec(oop_index));
 491   assert(addrlit.rspec().type() == relocInfo::oop_type, "must be an oop reloc");
 492   // It may not seem necessary to use a sethi/add pair to load a NULL into dest, but the
 493   // NULL will be dynamically patched later and the patched value may be large.  We must
 494   // therefore generate the sethi/add as a placeholders
 495   __ patchable_set(addrlit, reg);
 496 
 497   patching_epilog(patch, lir_patch_normal, reg, info);
 498 }
 499 
 500 
 501 void LIR_Assembler::emit_op3(LIR_Op3* op) {
 502   Register Rdividend = op->in_opr1()->as_register();
 503   Register Rdivisor  = noreg;
 504   Register Rscratch  = op->in_opr3()->as_register();
 505   Register Rresult   = op->result_opr()->as_register();
 506   int divisor = -1;
 507 
 508   if (op->in_opr2()->is_register()) {
 509     Rdivisor = op->in_opr2()->as_register();
 510   } else {
 511     divisor = op->in_opr2()->as_constant_ptr()->as_jint();
 512     assert(Assembler::is_simm13(divisor), "can only handle simm13");
 513   }
 514 
 515   assert(Rdividend != Rscratch, "");
 516   assert(Rdivisor  != Rscratch, "");
 517   assert(op->code() == lir_idiv || op->code() == lir_irem, "Must be irem or idiv");
 518 
 519   if (Rdivisor == noreg && is_power_of_2(divisor)) {
 520     // convert division by a power of two into some shifts and logical operations
 521     if (op->code() == lir_idiv) {
 522       if (divisor == 2) {
 523         __ srl(Rdividend, 31, Rscratch);
 524       } else {
 525         __ sra(Rdividend, 31, Rscratch);
 526         __ and3(Rscratch, divisor - 1, Rscratch);
 527       }
 528       __ add(Rdividend, Rscratch, Rscratch);
 529       __ sra(Rscratch, log2_intptr(divisor), Rresult);
 530       return;
 531     } else {
 532       if (divisor == 2) {
 533         __ srl(Rdividend, 31, Rscratch);
 534       } else {
 535         __ sra(Rdividend, 31, Rscratch);
 536         __ and3(Rscratch, divisor - 1,Rscratch);
 537       }
 538       __ add(Rdividend, Rscratch, Rscratch);
 539       __ andn(Rscratch, divisor - 1,Rscratch);
 540       __ sub(Rdividend, Rscratch, Rresult);
 541       return;
 542     }
 543   }
 544 
 545   __ sra(Rdividend, 31, Rscratch);
 546   __ wry(Rscratch);
 547   if (!VM_Version::v9_instructions_work()) {
 548     // v9 doesn't require these nops
 549     __ nop();
 550     __ nop();
 551     __ nop();
 552     __ nop();
 553   }
 554 
 555   add_debug_info_for_div0_here(op->info());
 556 
 557   if (Rdivisor != noreg) {
 558     __ sdivcc(Rdividend, Rdivisor, (op->code() == lir_idiv ? Rresult : Rscratch));
 559   } else {
 560     assert(Assembler::is_simm13(divisor), "can only handle simm13");
 561     __ sdivcc(Rdividend, divisor, (op->code() == lir_idiv ? Rresult : Rscratch));
 562   }
 563 
 564   Label skip;
 565   __ br(Assembler::overflowSet, true, Assembler::pn, skip);
 566   __ delayed()->Assembler::sethi(0x80000000, (op->code() == lir_idiv ? Rresult : Rscratch));
 567   __ bind(skip);
 568 
 569   if (op->code() == lir_irem) {
 570     if (Rdivisor != noreg) {
 571       __ smul(Rscratch, Rdivisor, Rscratch);
 572     } else {
 573       __ smul(Rscratch, divisor, Rscratch);
 574     }
 575     __ sub(Rdividend, Rscratch, Rresult);
 576   }
 577 }
 578 
 579 
 580 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
 581 #ifdef ASSERT
 582   assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label");
 583   if (op->block() != NULL)  _branch_target_blocks.append(op->block());
 584   if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock());
 585 #endif
 586   assert(op->info() == NULL, "shouldn't have CodeEmitInfo");
 587 
 588   if (op->cond() == lir_cond_always) {
 589     __ br(Assembler::always, false, Assembler::pt, *(op->label()));
 590   } else if (op->code() == lir_cond_float_branch) {
 591     assert(op->ublock() != NULL, "must have unordered successor");
 592     bool is_unordered = (op->ublock() == op->block());
 593     Assembler::Condition acond;
 594     switch (op->cond()) {
 595       case lir_cond_equal:         acond = Assembler::f_equal;    break;
 596       case lir_cond_notEqual:      acond = Assembler::f_notEqual; break;
 597       case lir_cond_less:          acond = (is_unordered ? Assembler::f_unorderedOrLess          : Assembler::f_less);           break;
 598       case lir_cond_greater:       acond = (is_unordered ? Assembler::f_unorderedOrGreater       : Assembler::f_greater);        break;
 599       case lir_cond_lessEqual:     acond = (is_unordered ? Assembler::f_unorderedOrLessOrEqual   : Assembler::f_lessOrEqual);    break;
 600       case lir_cond_greaterEqual:  acond = (is_unordered ? Assembler::f_unorderedOrGreaterOrEqual: Assembler::f_greaterOrEqual); break;
 601       default :                         ShouldNotReachHere();
 602     };
 603 
 604     if (!VM_Version::v9_instructions_work()) {
 605       __ nop();
 606     }
 607     __ fb( acond, false, Assembler::pn, *(op->label()));
 608   } else {
 609     assert (op->code() == lir_branch, "just checking");
 610 
 611     Assembler::Condition acond;
 612     switch (op->cond()) {
 613       case lir_cond_equal:        acond = Assembler::equal;                break;
 614       case lir_cond_notEqual:     acond = Assembler::notEqual;             break;
 615       case lir_cond_less:         acond = Assembler::less;                 break;
 616       case lir_cond_lessEqual:    acond = Assembler::lessEqual;            break;
 617       case lir_cond_greaterEqual: acond = Assembler::greaterEqual;         break;
 618       case lir_cond_greater:      acond = Assembler::greater;              break;
 619       case lir_cond_aboveEqual:   acond = Assembler::greaterEqualUnsigned; break;
 620       case lir_cond_belowEqual:   acond = Assembler::lessEqualUnsigned;    break;
 621       default:                         ShouldNotReachHere();
 622     };
 623 
 624     // sparc has different condition codes for testing 32-bit
 625     // vs. 64-bit values.  We could always test xcc is we could
 626     // guarantee that 32-bit loads always sign extended but that isn't
 627     // true and since sign extension isn't free, it would impose a
 628     // slight cost.
 629 #ifdef _LP64
 630     if  (op->type() == T_INT) {
 631       __ br(acond, false, Assembler::pn, *(op->label()));
 632     } else
 633 #endif
 634       __ brx(acond, false, Assembler::pn, *(op->label()));
 635   }
 636   // The peephole pass fills the delay slot
 637 }
 638 
 639 
 640 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
 641   Bytecodes::Code code = op->bytecode();
 642   LIR_Opr dst = op->result_opr();
 643 
 644   switch(code) {
 645     case Bytecodes::_i2l: {
 646       Register rlo  = dst->as_register_lo();
 647       Register rhi  = dst->as_register_hi();
 648       Register rval = op->in_opr()->as_register();
 649 #ifdef _LP64
 650       __ sra(rval, 0, rlo);
 651 #else
 652       __ mov(rval, rlo);
 653       __ sra(rval, BitsPerInt-1, rhi);
 654 #endif
 655       break;
 656     }
 657     case Bytecodes::_i2d:
 658     case Bytecodes::_i2f: {
 659       bool is_double = (code == Bytecodes::_i2d);
 660       FloatRegister rdst = is_double ? dst->as_double_reg() : dst->as_float_reg();
 661       FloatRegisterImpl::Width w = is_double ? FloatRegisterImpl::D : FloatRegisterImpl::S;
 662       FloatRegister rsrc = op->in_opr()->as_float_reg();
 663       if (rsrc != rdst) {
 664         __ fmov(FloatRegisterImpl::S, rsrc, rdst);
 665       }
 666       __ fitof(w, rdst, rdst);
 667       break;
 668     }
 669     case Bytecodes::_f2i:{
 670       FloatRegister rsrc = op->in_opr()->as_float_reg();
 671       Address       addr = frame_map()->address_for_slot(dst->single_stack_ix());
 672       Label L;
 673       // result must be 0 if value is NaN; test by comparing value to itself
 674       __ fcmp(FloatRegisterImpl::S, Assembler::fcc0, rsrc, rsrc);
 675       if (!VM_Version::v9_instructions_work()) {
 676         __ nop();
 677       }
 678       __ fb(Assembler::f_unordered, true, Assembler::pn, L);
 679       __ delayed()->st(G0, addr); // annuled if contents of rsrc is not NaN
 680       __ ftoi(FloatRegisterImpl::S, rsrc, rsrc);
 681       // move integer result from float register to int register
 682       __ stf(FloatRegisterImpl::S, rsrc, addr.base(), addr.disp());
 683       __ bind (L);
 684       break;
 685     }
 686     case Bytecodes::_l2i: {
 687       Register rlo  = op->in_opr()->as_register_lo();
 688       Register rhi  = op->in_opr()->as_register_hi();
 689       Register rdst = dst->as_register();
 690 #ifdef _LP64
 691       __ sra(rlo, 0, rdst);
 692 #else
 693       __ mov(rlo, rdst);
 694 #endif
 695       break;
 696     }
 697     case Bytecodes::_d2f:
 698     case Bytecodes::_f2d: {
 699       bool is_double = (code == Bytecodes::_f2d);
 700       assert((!is_double && dst->is_single_fpu()) || (is_double && dst->is_double_fpu()), "check");
 701       LIR_Opr val = op->in_opr();
 702       FloatRegister rval = (code == Bytecodes::_d2f) ? val->as_double_reg() : val->as_float_reg();
 703       FloatRegister rdst = is_double ? dst->as_double_reg() : dst->as_float_reg();
 704       FloatRegisterImpl::Width vw = is_double ? FloatRegisterImpl::S : FloatRegisterImpl::D;
 705       FloatRegisterImpl::Width dw = is_double ? FloatRegisterImpl::D : FloatRegisterImpl::S;
 706       __ ftof(vw, dw, rval, rdst);
 707       break;
 708     }
 709     case Bytecodes::_i2s:
 710     case Bytecodes::_i2b: {
 711       Register rval = op->in_opr()->as_register();
 712       Register rdst = dst->as_register();
 713       int shift = (code == Bytecodes::_i2b) ? (BitsPerInt - T_BYTE_aelem_bytes * BitsPerByte) : (BitsPerInt - BitsPerShort);
 714       __ sll (rval, shift, rdst);
 715       __ sra (rdst, shift, rdst);
 716       break;
 717     }
 718     case Bytecodes::_i2c: {
 719       Register rval = op->in_opr()->as_register();
 720       Register rdst = dst->as_register();
 721       int shift = BitsPerInt - T_CHAR_aelem_bytes * BitsPerByte;
 722       __ sll (rval, shift, rdst);
 723       __ srl (rdst, shift, rdst);
 724       break;
 725     }
 726 
 727     default: ShouldNotReachHere();
 728   }
 729 }
 730 
 731 
 732 void LIR_Assembler::align_call(LIR_Code) {
 733   // do nothing since all instructions are word aligned on sparc
 734 }
 735 
 736 
 737 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
 738   __ call(op->addr(), rtype);
 739   // the peephole pass fills the delay slot

 740 }
 741 
 742 
 743 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
 744   RelocationHolder rspec = virtual_call_Relocation::spec(pc());
 745   __ set_oop((jobject)Universe::non_oop_word(), G5_inline_cache_reg);
 746   __ relocate(rspec);
 747   __ call(op->addr(), relocInfo::none);
 748   // the peephole pass fills the delay slot

 749 }
 750 
 751 
 752 void LIR_Assembler::vtable_call(LIR_OpJavaCall* op) {
 753   add_debug_info_for_null_check_here(op->info());
 754   __ ld_ptr(O0, oopDesc::klass_offset_in_bytes(), G3_scratch);
 755   if (__ is_simm13(op->vtable_offset())) {
 756     __ ld_ptr(G3_scratch, op->vtable_offset(), G5_method);
 757   } else {
 758     // This will generate 2 instructions
 759     __ set(op->vtable_offset(), G5_method);
 760     // ld_ptr, set_hi, set
 761     __ ld_ptr(G3_scratch, G5_method, G5_method);
 762   }
 763   __ ld_ptr(G5_method, methodOopDesc::from_compiled_offset(), G3_scratch);
 764   __ callr(G3_scratch, G0);
 765   // the peephole pass fills the delay slot
 766 }
 767 
 768 
 769 void LIR_Assembler::preserve_SP(LIR_OpJavaCall* op) {
 770   Unimplemented();
 771 }
 772 
 773 
 774 void LIR_Assembler::restore_SP(LIR_OpJavaCall* op) {
 775   Unimplemented();
 776 }
 777 
 778 
 779 // load with 32-bit displacement
 780 int LIR_Assembler::load(Register s, int disp, Register d, BasicType ld_type, CodeEmitInfo *info) {
 781   int load_offset = code_offset();
 782   if (Assembler::is_simm13(disp)) {
 783     if (info != NULL) add_debug_info_for_null_check_here(info);
 784     switch(ld_type) {
 785       case T_BOOLEAN: // fall through
 786       case T_BYTE  : __ ldsb(s, disp, d); break;
 787       case T_CHAR  : __ lduh(s, disp, d); break;
 788       case T_SHORT : __ ldsh(s, disp, d); break;
 789       case T_INT   : __ ld(s, disp, d); break;
 790       case T_ADDRESS:// fall through
 791       case T_ARRAY : // fall through
 792       case T_OBJECT: __ ld_ptr(s, disp, d); break;
 793       default      : ShouldNotReachHere();
 794     }
 795   } else {
 796     __ set(disp, O7);
 797     if (info != NULL) add_debug_info_for_null_check_here(info);
 798     load_offset = code_offset();
 799     switch(ld_type) {
 800       case T_BOOLEAN: // fall through
 801       case T_BYTE  : __ ldsb(s, O7, d); break;
 802       case T_CHAR  : __ lduh(s, O7, d); break;
 803       case T_SHORT : __ ldsh(s, O7, d); break;
 804       case T_INT   : __ ld(s, O7, d); break;
 805       case T_ADDRESS:// fall through
 806       case T_ARRAY : // fall through
 807       case T_OBJECT: __ ld_ptr(s, O7, d); break;
 808       default      : ShouldNotReachHere();
 809     }
 810   }
 811   if (ld_type == T_ARRAY || ld_type == T_OBJECT) __ verify_oop(d);
 812   return load_offset;
 813 }
 814 
 815 
 816 // store with 32-bit displacement
 817 void LIR_Assembler::store(Register value, Register base, int offset, BasicType type, CodeEmitInfo *info) {
 818   if (Assembler::is_simm13(offset)) {
 819     if (info != NULL)  add_debug_info_for_null_check_here(info);
 820     switch (type) {
 821       case T_BOOLEAN: // fall through
 822       case T_BYTE  : __ stb(value, base, offset); break;
 823       case T_CHAR  : __ sth(value, base, offset); break;
 824       case T_SHORT : __ sth(value, base, offset); break;
 825       case T_INT   : __ stw(value, base, offset); break;
 826       case T_ADDRESS:// fall through
 827       case T_ARRAY : // fall through
 828       case T_OBJECT: __ st_ptr(value, base, offset); break;
 829       default      : ShouldNotReachHere();
 830     }
 831   } else {
 832     __ set(offset, O7);
 833     if (info != NULL) add_debug_info_for_null_check_here(info);
 834     switch (type) {
 835       case T_BOOLEAN: // fall through
 836       case T_BYTE  : __ stb(value, base, O7); break;
 837       case T_CHAR  : __ sth(value, base, O7); break;
 838       case T_SHORT : __ sth(value, base, O7); break;
 839       case T_INT   : __ stw(value, base, O7); break;
 840       case T_ADDRESS:// fall through
 841       case T_ARRAY : //fall through
 842       case T_OBJECT: __ st_ptr(value, base, O7); break;
 843       default      : ShouldNotReachHere();
 844     }
 845   }
 846   // Note: Do the store before verification as the code might be patched!
 847   if (type == T_ARRAY || type == T_OBJECT) __ verify_oop(value);
 848 }
 849 
 850 
 851 // load float with 32-bit displacement
 852 void LIR_Assembler::load(Register s, int disp, FloatRegister d, BasicType ld_type, CodeEmitInfo *info) {
 853   FloatRegisterImpl::Width w;
 854   switch(ld_type) {
 855     case T_FLOAT : w = FloatRegisterImpl::S; break;
 856     case T_DOUBLE: w = FloatRegisterImpl::D; break;
 857     default      : ShouldNotReachHere();
 858   }
 859 
 860   if (Assembler::is_simm13(disp)) {
 861     if (info != NULL) add_debug_info_for_null_check_here(info);
 862     if (disp % BytesPerLong != 0 && w == FloatRegisterImpl::D) {
 863       __ ldf(FloatRegisterImpl::S, s, disp + BytesPerWord, d->successor());
 864       __ ldf(FloatRegisterImpl::S, s, disp               , d);
 865     } else {
 866       __ ldf(w, s, disp, d);
 867     }
 868   } else {
 869     __ set(disp, O7);
 870     if (info != NULL) add_debug_info_for_null_check_here(info);
 871     __ ldf(w, s, O7, d);
 872   }
 873 }
 874 
 875 
 876 // store float with 32-bit displacement
 877 void LIR_Assembler::store(FloatRegister value, Register base, int offset, BasicType type, CodeEmitInfo *info) {
 878   FloatRegisterImpl::Width w;
 879   switch(type) {
 880     case T_FLOAT : w = FloatRegisterImpl::S; break;
 881     case T_DOUBLE: w = FloatRegisterImpl::D; break;
 882     default      : ShouldNotReachHere();
 883   }
 884 
 885   if (Assembler::is_simm13(offset)) {
 886     if (info != NULL) add_debug_info_for_null_check_here(info);
 887     if (w == FloatRegisterImpl::D && offset % BytesPerLong != 0) {
 888       __ stf(FloatRegisterImpl::S, value->successor(), base, offset + BytesPerWord);
 889       __ stf(FloatRegisterImpl::S, value             , base, offset);
 890     } else {
 891       __ stf(w, value, base, offset);
 892     }
 893   } else {
 894     __ set(offset, O7);
 895     if (info != NULL) add_debug_info_for_null_check_here(info);
 896     __ stf(w, value, O7, base);
 897   }
 898 }
 899 
 900 
 901 int LIR_Assembler::store(LIR_Opr from_reg, Register base, int offset, BasicType type, bool unaligned) {
 902   int store_offset;
 903   if (!Assembler::is_simm13(offset + (type == T_LONG) ? wordSize : 0)) {
 904     assert(!unaligned, "can't handle this");
 905     // for offsets larger than a simm13 we setup the offset in O7
 906     __ set(offset, O7);
 907     store_offset = store(from_reg, base, O7, type);
 908   } else {
 909     if (type == T_ARRAY || type == T_OBJECT) __ verify_oop(from_reg->as_register());
 910     store_offset = code_offset();
 911     switch (type) {
 912       case T_BOOLEAN: // fall through
 913       case T_BYTE  : __ stb(from_reg->as_register(), base, offset); break;
 914       case T_CHAR  : __ sth(from_reg->as_register(), base, offset); break;
 915       case T_SHORT : __ sth(from_reg->as_register(), base, offset); break;
 916       case T_INT   : __ stw(from_reg->as_register(), base, offset); break;
 917       case T_LONG  :
 918 #ifdef _LP64
 919         if (unaligned || PatchALot) {
 920           __ srax(from_reg->as_register_lo(), 32, O7);
 921           __ stw(from_reg->as_register_lo(), base, offset + lo_word_offset_in_bytes);
 922           __ stw(O7,                         base, offset + hi_word_offset_in_bytes);
 923         } else {
 924           __ stx(from_reg->as_register_lo(), base, offset);
 925         }
 926 #else
 927         assert(Assembler::is_simm13(offset + 4), "must be");
 928         __ stw(from_reg->as_register_lo(), base, offset + lo_word_offset_in_bytes);
 929         __ stw(from_reg->as_register_hi(), base, offset + hi_word_offset_in_bytes);
 930 #endif
 931         break;
 932       case T_ADDRESS:// fall through
 933       case T_ARRAY : // fall through
 934       case T_OBJECT: __ st_ptr(from_reg->as_register(), base, offset); break;
 935       case T_FLOAT : __ stf(FloatRegisterImpl::S, from_reg->as_float_reg(), base, offset); break;
 936       case T_DOUBLE:
 937         {
 938           FloatRegister reg = from_reg->as_double_reg();
 939           // split unaligned stores
 940           if (unaligned || PatchALot) {
 941             assert(Assembler::is_simm13(offset + 4), "must be");
 942             __ stf(FloatRegisterImpl::S, reg->successor(), base, offset + 4);
 943             __ stf(FloatRegisterImpl::S, reg,              base, offset);
 944           } else {
 945             __ stf(FloatRegisterImpl::D, reg, base, offset);
 946           }
 947           break;
 948         }
 949       default      : ShouldNotReachHere();
 950     }
 951   }
 952   return store_offset;
 953 }
 954 
 955 
 956 int LIR_Assembler::store(LIR_Opr from_reg, Register base, Register disp, BasicType type) {
 957   if (type == T_ARRAY || type == T_OBJECT) __ verify_oop(from_reg->as_register());
 958   int store_offset = code_offset();
 959   switch (type) {
 960     case T_BOOLEAN: // fall through
 961     case T_BYTE  : __ stb(from_reg->as_register(), base, disp); break;
 962     case T_CHAR  : __ sth(from_reg->as_register(), base, disp); break;
 963     case T_SHORT : __ sth(from_reg->as_register(), base, disp); break;
 964     case T_INT   : __ stw(from_reg->as_register(), base, disp); break;
 965     case T_LONG  :
 966 #ifdef _LP64
 967       __ stx(from_reg->as_register_lo(), base, disp);
 968 #else
 969       assert(from_reg->as_register_hi()->successor() == from_reg->as_register_lo(), "must match");
 970       __ std(from_reg->as_register_hi(), base, disp);
 971 #endif
 972       break;
 973     case T_ADDRESS:// fall through
 974     case T_ARRAY : // fall through
 975     case T_OBJECT: __ st_ptr(from_reg->as_register(), base, disp); break;
 976     case T_FLOAT : __ stf(FloatRegisterImpl::S, from_reg->as_float_reg(), base, disp); break;
 977     case T_DOUBLE: __ stf(FloatRegisterImpl::D, from_reg->as_double_reg(), base, disp); break;
 978     default      : ShouldNotReachHere();
 979   }
 980   return store_offset;
 981 }
 982 
 983 
 984 int LIR_Assembler::load(Register base, int offset, LIR_Opr to_reg, BasicType type, bool unaligned) {
 985   int load_offset;
 986   if (!Assembler::is_simm13(offset + (type == T_LONG) ? wordSize : 0)) {
 987     assert(base != O7, "destroying register");
 988     assert(!unaligned, "can't handle this");
 989     // for offsets larger than a simm13 we setup the offset in O7
 990     __ set(offset, O7);
 991     load_offset = load(base, O7, to_reg, type);
 992   } else {
 993     load_offset = code_offset();
 994     switch(type) {
 995       case T_BOOLEAN: // fall through
 996       case T_BYTE  : __ ldsb(base, offset, to_reg->as_register()); break;
 997       case T_CHAR  : __ lduh(base, offset, to_reg->as_register()); break;
 998       case T_SHORT : __ ldsh(base, offset, to_reg->as_register()); break;
 999       case T_INT   : __ ld(base, offset, to_reg->as_register()); break;
1000       case T_LONG  :
1001         if (!unaligned) {
1002 #ifdef _LP64
1003           __ ldx(base, offset, to_reg->as_register_lo());
1004 #else
1005           assert(to_reg->as_register_hi()->successor() == to_reg->as_register_lo(),
1006                  "must be sequential");
1007           __ ldd(base, offset, to_reg->as_register_hi());
1008 #endif
1009         } else {
1010 #ifdef _LP64
1011           assert(base != to_reg->as_register_lo(), "can't handle this");
1012           assert(O7 != to_reg->as_register_lo(), "can't handle this");
1013           __ ld(base, offset + hi_word_offset_in_bytes, to_reg->as_register_lo());
1014           __ lduw(base, offset + lo_word_offset_in_bytes, O7); // in case O7 is base or offset, use it last
1015           __ sllx(to_reg->as_register_lo(), 32, to_reg->as_register_lo());
1016           __ or3(to_reg->as_register_lo(), O7, to_reg->as_register_lo());
1017 #else
1018           if (base == to_reg->as_register_lo()) {
1019             __ ld(base, offset + hi_word_offset_in_bytes, to_reg->as_register_hi());
1020             __ ld(base, offset + lo_word_offset_in_bytes, to_reg->as_register_lo());
1021           } else {
1022             __ ld(base, offset + lo_word_offset_in_bytes, to_reg->as_register_lo());
1023             __ ld(base, offset + hi_word_offset_in_bytes, to_reg->as_register_hi());
1024           }
1025 #endif
1026         }
1027         break;
1028       case T_ADDRESS:// fall through
1029       case T_ARRAY : // fall through
1030       case T_OBJECT: __ ld_ptr(base, offset, to_reg->as_register()); break;
1031       case T_FLOAT:  __ ldf(FloatRegisterImpl::S, base, offset, to_reg->as_float_reg()); break;
1032       case T_DOUBLE:
1033         {
1034           FloatRegister reg = to_reg->as_double_reg();
1035           // split unaligned loads
1036           if (unaligned || PatchALot) {
1037             __ ldf(FloatRegisterImpl::S, base, offset + 4, reg->successor());
1038             __ ldf(FloatRegisterImpl::S, base, offset,     reg);
1039           } else {
1040             __ ldf(FloatRegisterImpl::D, base, offset, to_reg->as_double_reg());
1041           }
1042           break;
1043         }
1044       default      : ShouldNotReachHere();
1045     }
1046     if (type == T_ARRAY || type == T_OBJECT) __ verify_oop(to_reg->as_register());
1047   }
1048   return load_offset;
1049 }
1050 
1051 
1052 int LIR_Assembler::load(Register base, Register disp, LIR_Opr to_reg, BasicType type) {
1053   int load_offset = code_offset();
1054   switch(type) {
1055     case T_BOOLEAN: // fall through
1056     case T_BYTE  : __ ldsb(base, disp, to_reg->as_register()); break;
1057     case T_CHAR  : __ lduh(base, disp, to_reg->as_register()); break;
1058     case T_SHORT : __ ldsh(base, disp, to_reg->as_register()); break;
1059     case T_INT   : __ ld(base, disp, to_reg->as_register()); break;
1060     case T_ADDRESS:// fall through
1061     case T_ARRAY : // fall through
1062     case T_OBJECT: __ ld_ptr(base, disp, to_reg->as_register()); break;
1063     case T_FLOAT:  __ ldf(FloatRegisterImpl::S, base, disp, to_reg->as_float_reg()); break;
1064     case T_DOUBLE: __ ldf(FloatRegisterImpl::D, base, disp, to_reg->as_double_reg()); break;
1065     case T_LONG  :
1066 #ifdef _LP64
1067       __ ldx(base, disp, to_reg->as_register_lo());
1068 #else
1069       assert(to_reg->as_register_hi()->successor() == to_reg->as_register_lo(),
1070              "must be sequential");
1071       __ ldd(base, disp, to_reg->as_register_hi());
1072 #endif
1073       break;
1074     default      : ShouldNotReachHere();
1075   }
1076   if (type == T_ARRAY || type == T_OBJECT) __ verify_oop(to_reg->as_register());
1077   return load_offset;
1078 }
1079 
1080 
1081 // load/store with an Address
1082 void LIR_Assembler::load(const Address& a, Register d,  BasicType ld_type, CodeEmitInfo *info, int offset) {
1083   load(a.base(), a.disp() + offset, d, ld_type, info);
1084 }
1085 
1086 
1087 void LIR_Assembler::store(Register value, const Address& dest, BasicType type, CodeEmitInfo *info, int offset) {
1088   store(value, dest.base(), dest.disp() + offset, type, info);
1089 }
1090 
1091 
1092 // loadf/storef with an Address
1093 void LIR_Assembler::load(const Address& a, FloatRegister d, BasicType ld_type, CodeEmitInfo *info, int offset) {
1094   load(a.base(), a.disp() + offset, d, ld_type, info);
1095 }
1096 
1097 
1098 void LIR_Assembler::store(FloatRegister value, const Address& dest, BasicType type, CodeEmitInfo *info, int offset) {
1099   store(value, dest.base(), dest.disp() + offset, type, info);
1100 }
1101 
1102 
1103 // load/store with an Address
1104 void LIR_Assembler::load(LIR_Address* a, Register d,  BasicType ld_type, CodeEmitInfo *info) {
1105   load(as_Address(a), d, ld_type, info);
1106 }
1107 
1108 
1109 void LIR_Assembler::store(Register value, LIR_Address* dest, BasicType type, CodeEmitInfo *info) {
1110   store(value, as_Address(dest), type, info);
1111 }
1112 
1113 
1114 // loadf/storef with an Address
1115 void LIR_Assembler::load(LIR_Address* a, FloatRegister d, BasicType ld_type, CodeEmitInfo *info) {
1116   load(as_Address(a), d, ld_type, info);
1117 }
1118 
1119 
1120 void LIR_Assembler::store(FloatRegister value, LIR_Address* dest, BasicType type, CodeEmitInfo *info) {
1121   store(value, as_Address(dest), type, info);
1122 }
1123 
1124 
1125 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
1126   LIR_Const* c = src->as_constant_ptr();
1127   switch (c->type()) {
1128     case T_INT:
1129     case T_FLOAT:
1130     case T_ADDRESS: {
1131       Register src_reg = O7;
1132       int value = c->as_jint_bits();
1133       if (value == 0) {
1134         src_reg = G0;
1135       } else {
1136         __ set(value, O7);
1137       }
1138       Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
1139       __ stw(src_reg, addr.base(), addr.disp());
1140       break;
1141     }
1142     case T_OBJECT: {
1143       Register src_reg = O7;
1144       jobject2reg(c->as_jobject(), src_reg);
1145       Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
1146       __ st_ptr(src_reg, addr.base(), addr.disp());
1147       break;
1148     }
1149     case T_LONG:
1150     case T_DOUBLE: {
1151       Address addr = frame_map()->address_for_double_slot(dest->double_stack_ix());
1152 
1153       Register tmp = O7;
1154       int value_lo = c->as_jint_lo_bits();
1155       if (value_lo == 0) {
1156         tmp = G0;
1157       } else {
1158         __ set(value_lo, O7);
1159       }
1160       __ stw(tmp, addr.base(), addr.disp() + lo_word_offset_in_bytes);
1161       int value_hi = c->as_jint_hi_bits();
1162       if (value_hi == 0) {
1163         tmp = G0;
1164       } else {
1165         __ set(value_hi, O7);
1166       }
1167       __ stw(tmp, addr.base(), addr.disp() + hi_word_offset_in_bytes);
1168       break;
1169     }
1170     default:
1171       Unimplemented();
1172   }
1173 }
1174 
1175 
1176 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info ) {
1177   LIR_Const* c = src->as_constant_ptr();
1178   LIR_Address* addr     = dest->as_address_ptr();
1179   Register base = addr->base()->as_pointer_register();
1180 
1181   if (info != NULL) {
1182     add_debug_info_for_null_check_here(info);
1183   }
1184   switch (c->type()) {
1185     case T_INT:
1186     case T_FLOAT:
1187     case T_ADDRESS: {
1188       LIR_Opr tmp = FrameMap::O7_opr;
1189       int value = c->as_jint_bits();
1190       if (value == 0) {
1191         tmp = FrameMap::G0_opr;
1192       } else if (Assembler::is_simm13(value)) {
1193         __ set(value, O7);
1194       }
1195       if (addr->index()->is_valid()) {
1196         assert(addr->disp() == 0, "must be zero");
1197         store(tmp, base, addr->index()->as_pointer_register(), type);
1198       } else {
1199         assert(Assembler::is_simm13(addr->disp()), "can't handle larger addresses");
1200         store(tmp, base, addr->disp(), type);
1201       }
1202       break;
1203     }
1204     case T_LONG:
1205     case T_DOUBLE: {
1206       assert(!addr->index()->is_valid(), "can't handle reg reg address here");
1207       assert(Assembler::is_simm13(addr->disp()) &&
1208              Assembler::is_simm13(addr->disp() + 4), "can't handle larger addresses");
1209 
1210       Register tmp = O7;
1211       int value_lo = c->as_jint_lo_bits();
1212       if (value_lo == 0) {
1213         tmp = G0;
1214       } else {
1215         __ set(value_lo, O7);
1216       }
1217       store(tmp, base, addr->disp() + lo_word_offset_in_bytes, T_INT);
1218       int value_hi = c->as_jint_hi_bits();
1219       if (value_hi == 0) {
1220         tmp = G0;
1221       } else {
1222         __ set(value_hi, O7);
1223       }
1224       store(tmp, base, addr->disp() + hi_word_offset_in_bytes, T_INT);
1225       break;
1226     }
1227     case T_OBJECT: {
1228       jobject obj = c->as_jobject();
1229       LIR_Opr tmp;
1230       if (obj == NULL) {
1231         tmp = FrameMap::G0_opr;
1232       } else {
1233         tmp = FrameMap::O7_opr;
1234         jobject2reg(c->as_jobject(), O7);
1235       }
1236       // handle either reg+reg or reg+disp address
1237       if (addr->index()->is_valid()) {
1238         assert(addr->disp() == 0, "must be zero");
1239         store(tmp, base, addr->index()->as_pointer_register(), type);
1240       } else {
1241         assert(Assembler::is_simm13(addr->disp()), "can't handle larger addresses");
1242         store(tmp, base, addr->disp(), type);
1243       }
1244 
1245       break;
1246     }
1247     default:
1248       Unimplemented();
1249   }
1250 }
1251 
1252 
1253 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
1254   LIR_Const* c = src->as_constant_ptr();
1255   LIR_Opr to_reg = dest;
1256 
1257   switch (c->type()) {
1258     case T_INT:
1259     case T_ADDRESS:
1260       {
1261         jint con = c->as_jint();
1262         if (to_reg->is_single_cpu()) {
1263           assert(patch_code == lir_patch_none, "no patching handled here");
1264           __ set(con, to_reg->as_register());
1265         } else {
1266           ShouldNotReachHere();
1267           assert(to_reg->is_single_fpu(), "wrong register kind");
1268 
1269           __ set(con, O7);
1270           Address temp_slot(SP, (frame::register_save_words * wordSize) + STACK_BIAS);
1271           __ st(O7, temp_slot);
1272           __ ldf(FloatRegisterImpl::S, temp_slot, to_reg->as_float_reg());
1273         }
1274       }
1275       break;
1276 
1277     case T_LONG:
1278       {
1279         jlong con = c->as_jlong();
1280 
1281         if (to_reg->is_double_cpu()) {
1282 #ifdef _LP64
1283           __ set(con,  to_reg->as_register_lo());
1284 #else
1285           __ set(low(con),  to_reg->as_register_lo());
1286           __ set(high(con), to_reg->as_register_hi());
1287 #endif
1288 #ifdef _LP64
1289         } else if (to_reg->is_single_cpu()) {
1290           __ set(con, to_reg->as_register());
1291 #endif
1292         } else {
1293           ShouldNotReachHere();
1294           assert(to_reg->is_double_fpu(), "wrong register kind");
1295           Address temp_slot_lo(SP, ((frame::register_save_words  ) * wordSize) + STACK_BIAS);
1296           Address temp_slot_hi(SP, ((frame::register_save_words) * wordSize) + (longSize/2) + STACK_BIAS);
1297           __ set(low(con),  O7);
1298           __ st(O7, temp_slot_lo);
1299           __ set(high(con), O7);
1300           __ st(O7, temp_slot_hi);
1301           __ ldf(FloatRegisterImpl::D, temp_slot_lo, to_reg->as_double_reg());
1302         }
1303       }
1304       break;
1305 
1306     case T_OBJECT:
1307       {
1308         if (patch_code == lir_patch_none) {
1309           jobject2reg(c->as_jobject(), to_reg->as_register());
1310         } else {
1311           jobject2reg_with_patching(to_reg->as_register(), info);
1312         }
1313       }
1314       break;
1315 
1316     case T_FLOAT:
1317       {
1318         address const_addr = __ float_constant(c->as_jfloat());
1319         if (const_addr == NULL) {
1320           bailout("const section overflow");
1321           break;
1322         }
1323         RelocationHolder rspec = internal_word_Relocation::spec(const_addr);
1324         AddressLiteral const_addrlit(const_addr, rspec);
1325         if (to_reg->is_single_fpu()) {
1326           __ patchable_sethi(const_addrlit, O7);
1327           __ relocate(rspec);
1328           __ ldf(FloatRegisterImpl::S, O7, const_addrlit.low10(), to_reg->as_float_reg());
1329 
1330         } else {
1331           assert(to_reg->is_single_cpu(), "Must be a cpu register.");
1332 
1333           __ set(const_addrlit, O7);
1334           load(O7, 0, to_reg->as_register(), T_INT);
1335         }
1336       }
1337       break;
1338 
1339     case T_DOUBLE:
1340       {
1341         address const_addr = __ double_constant(c->as_jdouble());
1342         if (const_addr == NULL) {
1343           bailout("const section overflow");
1344           break;
1345         }
1346         RelocationHolder rspec = internal_word_Relocation::spec(const_addr);
1347 
1348         if (to_reg->is_double_fpu()) {
1349           AddressLiteral const_addrlit(const_addr, rspec);
1350           __ patchable_sethi(const_addrlit, O7);
1351           __ relocate(rspec);
1352           __ ldf (FloatRegisterImpl::D, O7, const_addrlit.low10(), to_reg->as_double_reg());
1353         } else {
1354           assert(to_reg->is_double_cpu(), "Must be a long register.");
1355 #ifdef _LP64
1356           __ set(jlong_cast(c->as_jdouble()), to_reg->as_register_lo());
1357 #else
1358           __ set(low(jlong_cast(c->as_jdouble())), to_reg->as_register_lo());
1359           __ set(high(jlong_cast(c->as_jdouble())), to_reg->as_register_hi());
1360 #endif
1361         }
1362 
1363       }
1364       break;
1365 
1366     default:
1367       ShouldNotReachHere();
1368   }
1369 }
1370 
1371 Address LIR_Assembler::as_Address(LIR_Address* addr) {
1372   Register reg = addr->base()->as_register();
1373   return Address(reg, addr->disp());
1374 }
1375 
1376 
1377 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
1378   switch (type) {
1379     case T_INT:
1380     case T_FLOAT: {
1381       Register tmp = O7;
1382       Address from = frame_map()->address_for_slot(src->single_stack_ix());
1383       Address to   = frame_map()->address_for_slot(dest->single_stack_ix());
1384       __ lduw(from.base(), from.disp(), tmp);
1385       __ stw(tmp, to.base(), to.disp());
1386       break;
1387     }
1388     case T_OBJECT: {
1389       Register tmp = O7;
1390       Address from = frame_map()->address_for_slot(src->single_stack_ix());
1391       Address to   = frame_map()->address_for_slot(dest->single_stack_ix());
1392       __ ld_ptr(from.base(), from.disp(), tmp);
1393       __ st_ptr(tmp, to.base(), to.disp());
1394       break;
1395     }
1396     case T_LONG:
1397     case T_DOUBLE: {
1398       Register tmp = O7;
1399       Address from = frame_map()->address_for_double_slot(src->double_stack_ix());
1400       Address to   = frame_map()->address_for_double_slot(dest->double_stack_ix());
1401       __ lduw(from.base(), from.disp(), tmp);
1402       __ stw(tmp, to.base(), to.disp());
1403       __ lduw(from.base(), from.disp() + 4, tmp);
1404       __ stw(tmp, to.base(), to.disp() + 4);
1405       break;
1406     }
1407 
1408     default:
1409       ShouldNotReachHere();
1410   }
1411 }
1412 
1413 
1414 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
1415   Address base = as_Address(addr);
1416   return Address(base.base(), base.disp() + hi_word_offset_in_bytes);
1417 }
1418 
1419 
1420 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
1421   Address base = as_Address(addr);
1422   return Address(base.base(), base.disp() + lo_word_offset_in_bytes);
1423 }
1424 
1425 
1426 void LIR_Assembler::mem2reg(LIR_Opr src_opr, LIR_Opr dest, BasicType type,
1427                             LIR_PatchCode patch_code, CodeEmitInfo* info, bool unaligned) {
1428 
1429   LIR_Address* addr = src_opr->as_address_ptr();
1430   LIR_Opr to_reg = dest;
1431 
1432   Register src = addr->base()->as_pointer_register();
1433   Register disp_reg = noreg;
1434   int disp_value = addr->disp();
1435   bool needs_patching = (patch_code != lir_patch_none);
1436 
1437   if (addr->base()->type() == T_OBJECT) {
1438     __ verify_oop(src);
1439   }
1440 
1441   PatchingStub* patch = NULL;
1442   if (needs_patching) {
1443     patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1444     assert(!to_reg->is_double_cpu() ||
1445            patch_code == lir_patch_none ||
1446            patch_code == lir_patch_normal, "patching doesn't match register");
1447   }
1448 
1449   if (addr->index()->is_illegal()) {
1450     if (!Assembler::is_simm13(disp_value) && (!unaligned || Assembler::is_simm13(disp_value + 4))) {
1451       if (needs_patching) {
1452         __ patchable_set(0, O7);
1453       } else {
1454         __ set(disp_value, O7);
1455       }
1456       disp_reg = O7;
1457     }
1458   } else if (unaligned || PatchALot) {
1459     __ add(src, addr->index()->as_register(), O7);
1460     src = O7;
1461   } else {
1462     disp_reg = addr->index()->as_pointer_register();
1463     assert(disp_value == 0, "can't handle 3 operand addresses");
1464   }
1465 
1466   // remember the offset of the load.  The patching_epilog must be done
1467   // before the call to add_debug_info, otherwise the PcDescs don't get
1468   // entered in increasing order.
1469   int offset = code_offset();
1470 
1471   assert(disp_reg != noreg || Assembler::is_simm13(disp_value), "should have set this up");
1472   if (disp_reg == noreg) {
1473     offset = load(src, disp_value, to_reg, type, unaligned);
1474   } else {
1475     assert(!unaligned, "can't handle this");
1476     offset = load(src, disp_reg, to_reg, type);
1477   }
1478 
1479   if (patch != NULL) {
1480     patching_epilog(patch, patch_code, src, info);
1481   }
1482 
1483   if (info != NULL) add_debug_info_for_null_check(offset, info);
1484 }
1485 
1486 
1487 void LIR_Assembler::prefetchr(LIR_Opr src) {
1488   LIR_Address* addr = src->as_address_ptr();
1489   Address from_addr = as_Address(addr);
1490 
1491   if (VM_Version::has_v9()) {
1492     __ prefetch(from_addr, Assembler::severalReads);
1493   }
1494 }
1495 
1496 
1497 void LIR_Assembler::prefetchw(LIR_Opr src) {
1498   LIR_Address* addr = src->as_address_ptr();
1499   Address from_addr = as_Address(addr);
1500 
1501   if (VM_Version::has_v9()) {
1502     __ prefetch(from_addr, Assembler::severalWritesAndPossiblyReads);
1503   }
1504 }
1505 
1506 
1507 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
1508   Address addr;
1509   if (src->is_single_word()) {
1510     addr = frame_map()->address_for_slot(src->single_stack_ix());
1511   } else if (src->is_double_word())  {
1512     addr = frame_map()->address_for_double_slot(src->double_stack_ix());
1513   }
1514 
1515   bool unaligned = (addr.disp() - STACK_BIAS) % 8 != 0;
1516   load(addr.base(), addr.disp(), dest, dest->type(), unaligned);
1517 }
1518 
1519 
1520 void LIR_Assembler::reg2stack(LIR_Opr from_reg, LIR_Opr dest, BasicType type, bool pop_fpu_stack) {
1521   Address addr;
1522   if (dest->is_single_word()) {
1523     addr = frame_map()->address_for_slot(dest->single_stack_ix());
1524   } else if (dest->is_double_word())  {
1525     addr = frame_map()->address_for_slot(dest->double_stack_ix());
1526   }
1527   bool unaligned = (addr.disp() - STACK_BIAS) % 8 != 0;
1528   store(from_reg, addr.base(), addr.disp(), from_reg->type(), unaligned);
1529 }
1530 
1531 
1532 void LIR_Assembler::reg2reg(LIR_Opr from_reg, LIR_Opr to_reg) {
1533   if (from_reg->is_float_kind() && to_reg->is_float_kind()) {
1534     if (from_reg->is_double_fpu()) {
1535       // double to double moves
1536       assert(to_reg->is_double_fpu(), "should match");
1537       __ fmov(FloatRegisterImpl::D, from_reg->as_double_reg(), to_reg->as_double_reg());
1538     } else {
1539       // float to float moves
1540       assert(to_reg->is_single_fpu(), "should match");
1541       __ fmov(FloatRegisterImpl::S, from_reg->as_float_reg(), to_reg->as_float_reg());
1542     }
1543   } else if (!from_reg->is_float_kind() && !to_reg->is_float_kind()) {
1544     if (from_reg->is_double_cpu()) {
1545 #ifdef _LP64
1546       __ mov(from_reg->as_pointer_register(), to_reg->as_pointer_register());
1547 #else
1548       assert(to_reg->is_double_cpu() &&
1549              from_reg->as_register_hi() != to_reg->as_register_lo() &&
1550              from_reg->as_register_lo() != to_reg->as_register_hi(),
1551              "should both be long and not overlap");
1552       // long to long moves
1553       __ mov(from_reg->as_register_hi(), to_reg->as_register_hi());
1554       __ mov(from_reg->as_register_lo(), to_reg->as_register_lo());
1555 #endif
1556 #ifdef _LP64
1557     } else if (to_reg->is_double_cpu()) {
1558       // int to int moves
1559       __ mov(from_reg->as_register(), to_reg->as_register_lo());
1560 #endif
1561     } else {
1562       // int to int moves
1563       __ mov(from_reg->as_register(), to_reg->as_register());
1564     }
1565   } else {
1566     ShouldNotReachHere();
1567   }
1568   if (to_reg->type() == T_OBJECT || to_reg->type() == T_ARRAY) {
1569     __ verify_oop(to_reg->as_register());
1570   }
1571 }
1572 
1573 
1574 void LIR_Assembler::reg2mem(LIR_Opr from_reg, LIR_Opr dest, BasicType type,
1575                             LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack,
1576                             bool unaligned) {
1577   LIR_Address* addr = dest->as_address_ptr();
1578 
1579   Register src = addr->base()->as_pointer_register();
1580   Register disp_reg = noreg;
1581   int disp_value = addr->disp();
1582   bool needs_patching = (patch_code != lir_patch_none);
1583 
1584   if (addr->base()->is_oop_register()) {
1585     __ verify_oop(src);
1586   }
1587 
1588   PatchingStub* patch = NULL;
1589   if (needs_patching) {
1590     patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1591     assert(!from_reg->is_double_cpu() ||
1592            patch_code == lir_patch_none ||
1593            patch_code == lir_patch_normal, "patching doesn't match register");
1594   }
1595 
1596   if (addr->index()->is_illegal()) {
1597     if (!Assembler::is_simm13(disp_value) && (!unaligned || Assembler::is_simm13(disp_value + 4))) {
1598       if (needs_patching) {
1599         __ patchable_set(0, O7);
1600       } else {
1601         __ set(disp_value, O7);
1602       }
1603       disp_reg = O7;
1604     }
1605   } else if (unaligned || PatchALot) {
1606     __ add(src, addr->index()->as_register(), O7);
1607     src = O7;
1608   } else {
1609     disp_reg = addr->index()->as_pointer_register();
1610     assert(disp_value == 0, "can't handle 3 operand addresses");
1611   }
1612 
1613   // remember the offset of the store.  The patching_epilog must be done
1614   // before the call to add_debug_info_for_null_check, otherwise the PcDescs don't get
1615   // entered in increasing order.
1616   int offset;
1617 
1618   assert(disp_reg != noreg || Assembler::is_simm13(disp_value), "should have set this up");
1619   if (disp_reg == noreg) {
1620     offset = store(from_reg, src, disp_value, type, unaligned);
1621   } else {
1622     assert(!unaligned, "can't handle this");
1623     offset = store(from_reg, src, disp_reg, type);
1624   }
1625 
1626   if (patch != NULL) {
1627     patching_epilog(patch, patch_code, src, info);
1628   }
1629 
1630   if (info != NULL) add_debug_info_for_null_check(offset, info);
1631 }
1632 
1633 
1634 void LIR_Assembler::return_op(LIR_Opr result) {
1635   // the poll may need a register so just pick one that isn't the return register
1636 #ifdef TIERED
1637   if (result->type_field() == LIR_OprDesc::long_type) {
1638     // Must move the result to G1
1639     // Must leave proper result in O0,O1 and G1 (TIERED only)
1640     __ sllx(I0, 32, G1);          // Shift bits into high G1
1641     __ srl (I1, 0, I1);           // Zero extend O1 (harmless?)
1642     __ or3 (I1, G1, G1);          // OR 64 bits into G1
1643   }
1644 #endif // TIERED
1645   __ set((intptr_t)os::get_polling_page(), L0);
1646   __ relocate(relocInfo::poll_return_type);
1647   __ ld_ptr(L0, 0, G0);
1648   __ ret();
1649   __ delayed()->restore();
1650 }
1651 
1652 
1653 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
1654   __ set((intptr_t)os::get_polling_page(), tmp->as_register());
1655   if (info != NULL) {
1656     add_debug_info_for_branch(info);
1657   } else {
1658     __ relocate(relocInfo::poll_type);
1659   }
1660 
1661   int offset = __ offset();
1662   __ ld_ptr(tmp->as_register(), 0, G0);
1663 
1664   return offset;
1665 }
1666 
1667 
1668 void LIR_Assembler::emit_static_call_stub() {
1669   address call_pc = __ pc();
1670   address stub = __ start_a_stub(call_stub_size);
1671   if (stub == NULL) {
1672     bailout("static call stub overflow");
1673     return;
1674   }
1675 
1676   int start = __ offset();
1677   __ relocate(static_stub_Relocation::spec(call_pc));
1678 
1679   __ set_oop(NULL, G5);
1680   // must be set to -1 at code generation time
1681   AddressLiteral addrlit(-1);
1682   __ jump_to(addrlit, G3);
1683   __ delayed()->nop();
1684 
1685   assert(__ offset() - start <= call_stub_size, "stub too big");
1686   __ end_a_stub();
1687 }
1688 
1689 
1690 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
1691   if (opr1->is_single_fpu()) {
1692     __ fcmp(FloatRegisterImpl::S, Assembler::fcc0, opr1->as_float_reg(), opr2->as_float_reg());
1693   } else if (opr1->is_double_fpu()) {
1694     __ fcmp(FloatRegisterImpl::D, Assembler::fcc0, opr1->as_double_reg(), opr2->as_double_reg());
1695   } else if (opr1->is_single_cpu()) {
1696     if (opr2->is_constant()) {
1697       switch (opr2->as_constant_ptr()->type()) {
1698         case T_INT:
1699           { jint con = opr2->as_constant_ptr()->as_jint();
1700             if (Assembler::is_simm13(con)) {
1701               __ cmp(opr1->as_register(), con);
1702             } else {
1703               __ set(con, O7);
1704               __ cmp(opr1->as_register(), O7);
1705             }
1706           }
1707           break;
1708 
1709         case T_OBJECT:
1710           // there are only equal/notequal comparisions on objects
1711           { jobject con = opr2->as_constant_ptr()->as_jobject();
1712             if (con == NULL) {
1713               __ cmp(opr1->as_register(), 0);
1714             } else {
1715               jobject2reg(con, O7);
1716               __ cmp(opr1->as_register(), O7);
1717             }
1718           }
1719           break;
1720 
1721         default:
1722           ShouldNotReachHere();
1723           break;
1724       }
1725     } else {
1726       if (opr2->is_address()) {
1727         LIR_Address * addr = opr2->as_address_ptr();
1728         BasicType type = addr->type();
1729         if ( type == T_OBJECT ) __ ld_ptr(as_Address(addr), O7);
1730         else                    __ ld(as_Address(addr), O7);
1731         __ cmp(opr1->as_register(), O7);
1732       } else {
1733         __ cmp(opr1->as_register(), opr2->as_register());
1734       }
1735     }
1736   } else if (opr1->is_double_cpu()) {
1737     Register xlo = opr1->as_register_lo();
1738     Register xhi = opr1->as_register_hi();
1739     if (opr2->is_constant() && opr2->as_jlong() == 0) {
1740       assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "only handles these cases");
1741 #ifdef _LP64
1742       __ orcc(xhi, G0, G0);
1743 #else
1744       __ orcc(xhi, xlo, G0);
1745 #endif
1746     } else if (opr2->is_register()) {
1747       Register ylo = opr2->as_register_lo();
1748       Register yhi = opr2->as_register_hi();
1749 #ifdef _LP64
1750       __ cmp(xlo, ylo);
1751 #else
1752       __ subcc(xlo, ylo, xlo);
1753       __ subccc(xhi, yhi, xhi);
1754       if (condition == lir_cond_equal || condition == lir_cond_notEqual) {
1755         __ orcc(xhi, xlo, G0);
1756       }
1757 #endif
1758     } else {
1759       ShouldNotReachHere();
1760     }
1761   } else if (opr1->is_address()) {
1762     LIR_Address * addr = opr1->as_address_ptr();
1763     BasicType type = addr->type();
1764     assert (opr2->is_constant(), "Checking");
1765     if ( type == T_OBJECT ) __ ld_ptr(as_Address(addr), O7);
1766     else                    __ ld(as_Address(addr), O7);
1767     __ cmp(O7, opr2->as_constant_ptr()->as_jint());
1768   } else {
1769     ShouldNotReachHere();
1770   }
1771 }
1772 
1773 
1774 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op){
1775   if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
1776     bool is_unordered_less = (code == lir_ucmp_fd2i);
1777     if (left->is_single_fpu()) {
1778       __ float_cmp(true, is_unordered_less ? -1 : 1, left->as_float_reg(), right->as_float_reg(), dst->as_register());
1779     } else if (left->is_double_fpu()) {
1780       __ float_cmp(false, is_unordered_less ? -1 : 1, left->as_double_reg(), right->as_double_reg(), dst->as_register());
1781     } else {
1782       ShouldNotReachHere();
1783     }
1784   } else if (code == lir_cmp_l2i) {
1785 #ifdef _LP64
1786     __ lcmp(left->as_register_lo(), right->as_register_lo(), dst->as_register());
1787 #else
1788     __ lcmp(left->as_register_hi(),  left->as_register_lo(),
1789             right->as_register_hi(), right->as_register_lo(),
1790             dst->as_register());
1791 #endif
1792   } else {
1793     ShouldNotReachHere();
1794   }
1795 }
1796 
1797 
1798 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result) {
1799 
1800   Assembler::Condition acond;
1801   switch (condition) {
1802     case lir_cond_equal:        acond = Assembler::equal;        break;
1803     case lir_cond_notEqual:     acond = Assembler::notEqual;     break;
1804     case lir_cond_less:         acond = Assembler::less;         break;
1805     case lir_cond_lessEqual:    acond = Assembler::lessEqual;    break;
1806     case lir_cond_greaterEqual: acond = Assembler::greaterEqual; break;
1807     case lir_cond_greater:      acond = Assembler::greater;      break;
1808     case lir_cond_aboveEqual:   acond = Assembler::greaterEqualUnsigned;      break;
1809     case lir_cond_belowEqual:   acond = Assembler::lessEqualUnsigned;      break;
1810     default:                         ShouldNotReachHere();
1811   };
1812 
1813   if (opr1->is_constant() && opr1->type() == T_INT) {
1814     Register dest = result->as_register();
1815     // load up first part of constant before branch
1816     // and do the rest in the delay slot.
1817     if (!Assembler::is_simm13(opr1->as_jint())) {
1818       __ sethi(opr1->as_jint(), dest);
1819     }
1820   } else if (opr1->is_constant()) {
1821     const2reg(opr1, result, lir_patch_none, NULL);
1822   } else if (opr1->is_register()) {
1823     reg2reg(opr1, result);
1824   } else if (opr1->is_stack()) {
1825     stack2reg(opr1, result, result->type());
1826   } else {
1827     ShouldNotReachHere();
1828   }
1829   Label skip;
1830   __ br(acond, false, Assembler::pt, skip);
1831   if (opr1->is_constant() && opr1->type() == T_INT) {
1832     Register dest = result->as_register();
1833     if (Assembler::is_simm13(opr1->as_jint())) {
1834       __ delayed()->or3(G0, opr1->as_jint(), dest);
1835     } else {
1836       // the sethi has been done above, so just put in the low 10 bits
1837       __ delayed()->or3(dest, opr1->as_jint() & 0x3ff, dest);
1838     }
1839   } else {
1840     // can't do anything useful in the delay slot
1841     __ delayed()->nop();
1842   }
1843   if (opr2->is_constant()) {
1844     const2reg(opr2, result, lir_patch_none, NULL);
1845   } else if (opr2->is_register()) {
1846     reg2reg(opr2, result);
1847   } else if (opr2->is_stack()) {
1848     stack2reg(opr2, result, result->type());
1849   } else {
1850     ShouldNotReachHere();
1851   }
1852   __ bind(skip);
1853 }
1854 
1855 
1856 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) {
1857   assert(info == NULL, "unused on this code path");
1858   assert(left->is_register(), "wrong items state");
1859   assert(dest->is_register(), "wrong items state");
1860 
1861   if (right->is_register()) {
1862     if (dest->is_float_kind()) {
1863 
1864       FloatRegister lreg, rreg, res;
1865       FloatRegisterImpl::Width w;
1866       if (right->is_single_fpu()) {
1867         w = FloatRegisterImpl::S;
1868         lreg = left->as_float_reg();
1869         rreg = right->as_float_reg();
1870         res  = dest->as_float_reg();
1871       } else {
1872         w = FloatRegisterImpl::D;
1873         lreg = left->as_double_reg();
1874         rreg = right->as_double_reg();
1875         res  = dest->as_double_reg();
1876       }
1877 
1878       switch (code) {
1879         case lir_add: __ fadd(w, lreg, rreg, res); break;
1880         case lir_sub: __ fsub(w, lreg, rreg, res); break;
1881         case lir_mul: // fall through
1882         case lir_mul_strictfp: __ fmul(w, lreg, rreg, res); break;
1883         case lir_div: // fall through
1884         case lir_div_strictfp: __ fdiv(w, lreg, rreg, res); break;
1885         default: ShouldNotReachHere();
1886       }
1887 
1888     } else if (dest->is_double_cpu()) {
1889 #ifdef _LP64
1890       Register dst_lo = dest->as_register_lo();
1891       Register op1_lo = left->as_pointer_register();
1892       Register op2_lo = right->as_pointer_register();
1893 
1894       switch (code) {
1895         case lir_add:
1896           __ add(op1_lo, op2_lo, dst_lo);
1897           break;
1898 
1899         case lir_sub:
1900           __ sub(op1_lo, op2_lo, dst_lo);
1901           break;
1902 
1903         default: ShouldNotReachHere();
1904       }
1905 #else
1906       Register op1_lo = left->as_register_lo();
1907       Register op1_hi = left->as_register_hi();
1908       Register op2_lo = right->as_register_lo();
1909       Register op2_hi = right->as_register_hi();
1910       Register dst_lo = dest->as_register_lo();
1911       Register dst_hi = dest->as_register_hi();
1912 
1913       switch (code) {
1914         case lir_add:
1915           __ addcc(op1_lo, op2_lo, dst_lo);
1916           __ addc (op1_hi, op2_hi, dst_hi);
1917           break;
1918 
1919         case lir_sub:
1920           __ subcc(op1_lo, op2_lo, dst_lo);
1921           __ subc (op1_hi, op2_hi, dst_hi);
1922           break;
1923 
1924         default: ShouldNotReachHere();
1925       }
1926 #endif
1927     } else {
1928       assert (right->is_single_cpu(), "Just Checking");
1929 
1930       Register lreg = left->as_register();
1931       Register res  = dest->as_register();
1932       Register rreg = right->as_register();
1933       switch (code) {
1934         case lir_add:  __ add  (lreg, rreg, res); break;
1935         case lir_sub:  __ sub  (lreg, rreg, res); break;
1936         case lir_mul:  __ mult (lreg, rreg, res); break;
1937         default: ShouldNotReachHere();
1938       }
1939     }
1940   } else {
1941     assert (right->is_constant(), "must be constant");
1942 
1943     if (dest->is_single_cpu()) {
1944       Register lreg = left->as_register();
1945       Register res  = dest->as_register();
1946       int    simm13 = right->as_constant_ptr()->as_jint();
1947 
1948       switch (code) {
1949         case lir_add:  __ add  (lreg, simm13, res); break;
1950         case lir_sub:  __ sub  (lreg, simm13, res); break;
1951         case lir_mul:  __ mult (lreg, simm13, res); break;
1952         default: ShouldNotReachHere();
1953       }
1954     } else {
1955       Register lreg = left->as_pointer_register();
1956       Register res  = dest->as_register_lo();
1957       long con = right->as_constant_ptr()->as_jlong();
1958       assert(Assembler::is_simm13(con), "must be simm13");
1959 
1960       switch (code) {
1961         case lir_add:  __ add  (lreg, (int)con, res); break;
1962         case lir_sub:  __ sub  (lreg, (int)con, res); break;
1963         case lir_mul:  __ mult (lreg, (int)con, res); break;
1964         default: ShouldNotReachHere();
1965       }
1966     }
1967   }
1968 }
1969 
1970 
1971 void LIR_Assembler::fpop() {
1972   // do nothing
1973 }
1974 
1975 
1976 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr thread, LIR_Opr dest, LIR_Op* op) {
1977   switch (code) {
1978     case lir_sin:
1979     case lir_tan:
1980     case lir_cos: {
1981       assert(thread->is_valid(), "preserve the thread object for performance reasons");
1982       assert(dest->as_double_reg() == F0, "the result will be in f0/f1");
1983       break;
1984     }
1985     case lir_sqrt: {
1986       assert(!thread->is_valid(), "there is no need for a thread_reg for dsqrt");
1987       FloatRegister src_reg = value->as_double_reg();
1988       FloatRegister dst_reg = dest->as_double_reg();
1989       __ fsqrt(FloatRegisterImpl::D, src_reg, dst_reg);
1990       break;
1991     }
1992     case lir_abs: {
1993       assert(!thread->is_valid(), "there is no need for a thread_reg for fabs");
1994       FloatRegister src_reg = value->as_double_reg();
1995       FloatRegister dst_reg = dest->as_double_reg();
1996       __ fabs(FloatRegisterImpl::D, src_reg, dst_reg);
1997       break;
1998     }
1999     default: {
2000       ShouldNotReachHere();
2001       break;
2002     }
2003   }
2004 }
2005 
2006 
2007 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest) {
2008   if (right->is_constant()) {
2009     if (dest->is_single_cpu()) {
2010       int simm13 = right->as_constant_ptr()->as_jint();
2011       switch (code) {
2012         case lir_logic_and:   __ and3 (left->as_register(), simm13, dest->as_register()); break;
2013         case lir_logic_or:    __ or3  (left->as_register(), simm13, dest->as_register()); break;
2014         case lir_logic_xor:   __ xor3 (left->as_register(), simm13, dest->as_register()); break;
2015         default: ShouldNotReachHere();
2016       }
2017     } else {
2018       long c = right->as_constant_ptr()->as_jlong();
2019       assert(c == (int)c && Assembler::is_simm13(c), "out of range");
2020       int simm13 = (int)c;
2021       switch (code) {
2022         case lir_logic_and:
2023 #ifndef _LP64
2024           __ and3 (left->as_register_hi(), 0,      dest->as_register_hi());
2025 #endif
2026           __ and3 (left->as_register_lo(), simm13, dest->as_register_lo());
2027           break;
2028 
2029         case lir_logic_or:
2030 #ifndef _LP64
2031           __ or3 (left->as_register_hi(), 0,      dest->as_register_hi());
2032 #endif
2033           __ or3 (left->as_register_lo(), simm13, dest->as_register_lo());
2034           break;
2035 
2036         case lir_logic_xor:
2037 #ifndef _LP64
2038           __ xor3 (left->as_register_hi(), 0,      dest->as_register_hi());
2039 #endif
2040           __ xor3 (left->as_register_lo(), simm13, dest->as_register_lo());
2041           break;
2042 
2043         default: ShouldNotReachHere();
2044       }
2045     }
2046   } else {
2047     assert(right->is_register(), "right should be in register");
2048 
2049     if (dest->is_single_cpu()) {
2050       switch (code) {
2051         case lir_logic_and:   __ and3 (left->as_register(), right->as_register(), dest->as_register()); break;
2052         case lir_logic_or:    __ or3  (left->as_register(), right->as_register(), dest->as_register()); break;
2053         case lir_logic_xor:   __ xor3 (left->as_register(), right->as_register(), dest->as_register()); break;
2054         default: ShouldNotReachHere();
2055       }
2056     } else {
2057 #ifdef _LP64
2058       Register l = (left->is_single_cpu() && left->is_oop_register()) ? left->as_register() :
2059                                                                         left->as_register_lo();
2060       Register r = (right->is_single_cpu() && right->is_oop_register()) ? right->as_register() :
2061                                                                           right->as_register_lo();
2062 
2063       switch (code) {
2064         case lir_logic_and: __ and3 (l, r, dest->as_register_lo()); break;
2065         case lir_logic_or:  __ or3  (l, r, dest->as_register_lo()); break;
2066         case lir_logic_xor: __ xor3 (l, r, dest->as_register_lo()); break;
2067         default: ShouldNotReachHere();
2068       }
2069 #else
2070       switch (code) {
2071         case lir_logic_and:
2072           __ and3 (left->as_register_hi(), right->as_register_hi(), dest->as_register_hi());
2073           __ and3 (left->as_register_lo(), right->as_register_lo(), dest->as_register_lo());
2074           break;
2075 
2076         case lir_logic_or:
2077           __ or3 (left->as_register_hi(), right->as_register_hi(), dest->as_register_hi());
2078           __ or3 (left->as_register_lo(), right->as_register_lo(), dest->as_register_lo());
2079           break;
2080 
2081         case lir_logic_xor:
2082           __ xor3 (left->as_register_hi(), right->as_register_hi(), dest->as_register_hi());
2083           __ xor3 (left->as_register_lo(), right->as_register_lo(), dest->as_register_lo());
2084           break;
2085 
2086         default: ShouldNotReachHere();
2087       }
2088 #endif
2089     }
2090   }
2091 }
2092 
2093 
2094 int LIR_Assembler::shift_amount(BasicType t) {
2095   int elem_size = type2aelembytes(t);
2096   switch (elem_size) {
2097     case 1 : return 0;
2098     case 2 : return 1;
2099     case 4 : return 2;
2100     case 8 : return 3;
2101   }
2102   ShouldNotReachHere();
2103   return -1;
2104 }
2105 
2106 
2107 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
2108   assert(exceptionOop->as_register() == Oexception, "should match");
2109   assert(exceptionPC->as_register() == Oissuing_pc, "should match");
2110 
2111   info->add_register_oop(exceptionOop);
2112 
2113   // reuse the debug info from the safepoint poll for the throw op itself
2114   address pc_for_athrow  = __ pc();
2115   int pc_for_athrow_offset = __ offset();
2116   RelocationHolder rspec = internal_word_Relocation::spec(pc_for_athrow);
2117   __ set(pc_for_athrow, Oissuing_pc, rspec);
2118   add_call_info(pc_for_athrow_offset, info); // for exception handler
2119 
2120   __ call(Runtime1::entry_for(Runtime1::handle_exception_id), relocInfo::runtime_call_type);
2121   __ delayed()->nop();
2122 }
2123 
2124 
2125 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
2126   assert(exceptionOop->as_register() == Oexception, "should match");
2127 
2128   __ br(Assembler::always, false, Assembler::pt, _unwind_handler_entry);
2129   __ delayed()->nop();
2130 }
2131 
2132 
2133 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
2134   Register src = op->src()->as_register();
2135   Register dst = op->dst()->as_register();
2136   Register src_pos = op->src_pos()->as_register();
2137   Register dst_pos = op->dst_pos()->as_register();
2138   Register length  = op->length()->as_register();
2139   Register tmp = op->tmp()->as_register();
2140   Register tmp2 = O7;
2141 
2142   int flags = op->flags();
2143   ciArrayKlass* default_type = op->expected_type();
2144   BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL;
2145   if (basic_type == T_ARRAY) basic_type = T_OBJECT;
2146 
2147   // set up the arraycopy stub information
2148   ArrayCopyStub* stub = op->stub();
2149 
2150   // always do stub if no type information is available.  it's ok if
2151   // the known type isn't loaded since the code sanity checks
2152   // in debug mode and the type isn't required when we know the exact type
2153   // also check that the type is an array type.
2154   // We also, for now, always call the stub if the barrier set requires a
2155   // write_ref_pre barrier (which the stub does, but none of the optimized
2156   // cases currently does).
2157   if (op->expected_type() == NULL ||
2158       Universe::heap()->barrier_set()->has_write_ref_pre_barrier()) {
2159     __ mov(src,     O0);
2160     __ mov(src_pos, O1);
2161     __ mov(dst,     O2);
2162     __ mov(dst_pos, O3);
2163     __ mov(length,  O4);
2164     __ call_VM_leaf(tmp, CAST_FROM_FN_PTR(address, Runtime1::arraycopy));
2165 
2166     __ br_zero(Assembler::less, false, Assembler::pn, O0, *stub->entry());
2167     __ delayed()->nop();
2168     __ bind(*stub->continuation());
2169     return;
2170   }
2171 
2172   assert(default_type != NULL && default_type->is_array_klass(), "must be true at this point");
2173 
2174   // make sure src and dst are non-null and load array length
2175   if (flags & LIR_OpArrayCopy::src_null_check) {
2176     __ tst(src);
2177     __ br(Assembler::equal, false, Assembler::pn, *stub->entry());
2178     __ delayed()->nop();
2179   }
2180 
2181   if (flags & LIR_OpArrayCopy::dst_null_check) {
2182     __ tst(dst);
2183     __ br(Assembler::equal, false, Assembler::pn, *stub->entry());
2184     __ delayed()->nop();
2185   }
2186 
2187   if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
2188     // test src_pos register
2189     __ tst(src_pos);
2190     __ br(Assembler::less, false, Assembler::pn, *stub->entry());
2191     __ delayed()->nop();
2192   }
2193 
2194   if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
2195     // test dst_pos register
2196     __ tst(dst_pos);
2197     __ br(Assembler::less, false, Assembler::pn, *stub->entry());
2198     __ delayed()->nop();
2199   }
2200 
2201   if (flags & LIR_OpArrayCopy::length_positive_check) {
2202     // make sure length isn't negative
2203     __ tst(length);
2204     __ br(Assembler::less, false, Assembler::pn, *stub->entry());
2205     __ delayed()->nop();
2206   }
2207 
2208   if (flags & LIR_OpArrayCopy::src_range_check) {
2209     __ ld(src, arrayOopDesc::length_offset_in_bytes(), tmp2);
2210     __ add(length, src_pos, tmp);
2211     __ cmp(tmp2, tmp);
2212     __ br(Assembler::carrySet, false, Assembler::pn, *stub->entry());
2213     __ delayed()->nop();
2214   }
2215 
2216   if (flags & LIR_OpArrayCopy::dst_range_check) {
2217     __ ld(dst, arrayOopDesc::length_offset_in_bytes(), tmp2);
2218     __ add(length, dst_pos, tmp);
2219     __ cmp(tmp2, tmp);
2220     __ br(Assembler::carrySet, false, Assembler::pn, *stub->entry());
2221     __ delayed()->nop();
2222   }
2223 
2224   if (flags & LIR_OpArrayCopy::type_check) {
2225     __ ld_ptr(src, oopDesc::klass_offset_in_bytes(), tmp);
2226     __ ld_ptr(dst, oopDesc::klass_offset_in_bytes(), tmp2);
2227     __ cmp(tmp, tmp2);
2228     __ br(Assembler::notEqual, false, Assembler::pt, *stub->entry());
2229     __ delayed()->nop();
2230   }
2231 
2232 #ifdef ASSERT
2233   if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
2234     // Sanity check the known type with the incoming class.  For the
2235     // primitive case the types must match exactly with src.klass and
2236     // dst.klass each exactly matching the default type.  For the
2237     // object array case, if no type check is needed then either the
2238     // dst type is exactly the expected type and the src type is a
2239     // subtype which we can't check or src is the same array as dst
2240     // but not necessarily exactly of type default_type.
2241     Label known_ok, halt;
2242     jobject2reg(op->expected_type()->constant_encoding(), tmp);
2243     __ ld_ptr(dst, oopDesc::klass_offset_in_bytes(), tmp2);
2244     if (basic_type != T_OBJECT) {
2245       __ cmp(tmp, tmp2);
2246       __ br(Assembler::notEqual, false, Assembler::pn, halt);
2247       __ delayed()->ld_ptr(src, oopDesc::klass_offset_in_bytes(), tmp2);
2248       __ cmp(tmp, tmp2);
2249       __ br(Assembler::equal, false, Assembler::pn, known_ok);
2250       __ delayed()->nop();
2251     } else {
2252       __ cmp(tmp, tmp2);
2253       __ br(Assembler::equal, false, Assembler::pn, known_ok);
2254       __ delayed()->cmp(src, dst);
2255       __ br(Assembler::equal, false, Assembler::pn, known_ok);
2256       __ delayed()->nop();
2257     }
2258     __ bind(halt);
2259     __ stop("incorrect type information in arraycopy");
2260     __ bind(known_ok);
2261   }
2262 #endif
2263 
2264   int shift = shift_amount(basic_type);
2265 
2266   Register src_ptr = O0;
2267   Register dst_ptr = O1;
2268   Register len     = O2;
2269 
2270   __ add(src, arrayOopDesc::base_offset_in_bytes(basic_type), src_ptr);
2271   LP64_ONLY(__ sra(src_pos, 0, src_pos);) //higher 32bits must be null
2272   if (shift == 0) {
2273     __ add(src_ptr, src_pos, src_ptr);
2274   } else {
2275     __ sll(src_pos, shift, tmp);
2276     __ add(src_ptr, tmp, src_ptr);
2277   }
2278 
2279   __ add(dst, arrayOopDesc::base_offset_in_bytes(basic_type), dst_ptr);
2280   LP64_ONLY(__ sra(dst_pos, 0, dst_pos);) //higher 32bits must be null
2281   if (shift == 0) {
2282     __ add(dst_ptr, dst_pos, dst_ptr);
2283   } else {
2284     __ sll(dst_pos, shift, tmp);
2285     __ add(dst_ptr, tmp, dst_ptr);
2286   }
2287 
2288   if (basic_type != T_OBJECT) {
2289     if (shift == 0) {
2290       __ mov(length, len);
2291     } else {
2292       __ sll(length, shift, len);
2293     }
2294     __ call_VM_leaf(tmp, CAST_FROM_FN_PTR(address, Runtime1::primitive_arraycopy));
2295   } else {
2296     // oop_arraycopy takes a length in number of elements, so don't scale it.
2297     __ mov(length, len);
2298     __ call_VM_leaf(tmp, CAST_FROM_FN_PTR(address, Runtime1::oop_arraycopy));
2299   }
2300 
2301   __ bind(*stub->continuation());
2302 }
2303 
2304 
2305 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2306   if (dest->is_single_cpu()) {
2307 #ifdef _LP64
2308     if (left->type() == T_OBJECT) {
2309       switch (code) {
2310         case lir_shl:  __ sllx  (left->as_register(), count->as_register(), dest->as_register()); break;
2311         case lir_shr:  __ srax  (left->as_register(), count->as_register(), dest->as_register()); break;
2312         case lir_ushr: __ srl   (left->as_register(), count->as_register(), dest->as_register()); break;
2313         default: ShouldNotReachHere();
2314       }
2315     } else
2316 #endif
2317       switch (code) {
2318         case lir_shl:  __ sll   (left->as_register(), count->as_register(), dest->as_register()); break;
2319         case lir_shr:  __ sra   (left->as_register(), count->as_register(), dest->as_register()); break;
2320         case lir_ushr: __ srl   (left->as_register(), count->as_register(), dest->as_register()); break;
2321         default: ShouldNotReachHere();
2322       }
2323   } else {
2324 #ifdef _LP64
2325     switch (code) {
2326       case lir_shl:  __ sllx  (left->as_register_lo(), count->as_register(), dest->as_register_lo()); break;
2327       case lir_shr:  __ srax  (left->as_register_lo(), count->as_register(), dest->as_register_lo()); break;
2328       case lir_ushr: __ srlx  (left->as_register_lo(), count->as_register(), dest->as_register_lo()); break;
2329       default: ShouldNotReachHere();
2330     }
2331 #else
2332     switch (code) {
2333       case lir_shl:  __ lshl  (left->as_register_hi(), left->as_register_lo(), count->as_register(), dest->as_register_hi(), dest->as_register_lo(), G3_scratch); break;
2334       case lir_shr:  __ lshr  (left->as_register_hi(), left->as_register_lo(), count->as_register(), dest->as_register_hi(), dest->as_register_lo(), G3_scratch); break;
2335       case lir_ushr: __ lushr (left->as_register_hi(), left->as_register_lo(), count->as_register(), dest->as_register_hi(), dest->as_register_lo(), G3_scratch); break;
2336       default: ShouldNotReachHere();
2337     }
2338 #endif
2339   }
2340 }
2341 
2342 
2343 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2344 #ifdef _LP64
2345   if (left->type() == T_OBJECT) {
2346     count = count & 63;  // shouldn't shift by more than sizeof(intptr_t)
2347     Register l = left->as_register();
2348     Register d = dest->as_register_lo();
2349     switch (code) {
2350       case lir_shl:  __ sllx  (l, count, d); break;
2351       case lir_shr:  __ srax  (l, count, d); break;
2352       case lir_ushr: __ srlx  (l, count, d); break;
2353       default: ShouldNotReachHere();
2354     }
2355     return;
2356   }
2357 #endif
2358 
2359   if (dest->is_single_cpu()) {
2360     count = count & 0x1F; // Java spec
2361     switch (code) {
2362       case lir_shl:  __ sll   (left->as_register(), count, dest->as_register()); break;
2363       case lir_shr:  __ sra   (left->as_register(), count, dest->as_register()); break;
2364       case lir_ushr: __ srl   (left->as_register(), count, dest->as_register()); break;
2365       default: ShouldNotReachHere();
2366     }
2367   } else if (dest->is_double_cpu()) {
2368     count = count & 63; // Java spec
2369     switch (code) {
2370       case lir_shl:  __ sllx  (left->as_pointer_register(), count, dest->as_pointer_register()); break;
2371       case lir_shr:  __ srax  (left->as_pointer_register(), count, dest->as_pointer_register()); break;
2372       case lir_ushr: __ srlx  (left->as_pointer_register(), count, dest->as_pointer_register()); break;
2373       default: ShouldNotReachHere();
2374     }
2375   } else {
2376     ShouldNotReachHere();
2377   }
2378 }
2379 
2380 
2381 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
2382   assert(op->tmp1()->as_register()  == G1 &&
2383          op->tmp2()->as_register()  == G3 &&
2384          op->tmp3()->as_register()  == G4 &&
2385          op->obj()->as_register()   == O0 &&
2386          op->klass()->as_register() == G5, "must be");
2387   if (op->init_check()) {
2388     __ ld(op->klass()->as_register(),
2389           instanceKlass::init_state_offset_in_bytes() + sizeof(oopDesc),
2390           op->tmp1()->as_register());
2391     add_debug_info_for_null_check_here(op->stub()->info());
2392     __ cmp(op->tmp1()->as_register(), instanceKlass::fully_initialized);
2393     __ br(Assembler::notEqual, false, Assembler::pn, *op->stub()->entry());
2394     __ delayed()->nop();
2395   }
2396   __ allocate_object(op->obj()->as_register(),
2397                      op->tmp1()->as_register(),
2398                      op->tmp2()->as_register(),
2399                      op->tmp3()->as_register(),
2400                      op->header_size(),
2401                      op->object_size(),
2402                      op->klass()->as_register(),
2403                      *op->stub()->entry());
2404   __ bind(*op->stub()->continuation());
2405   __ verify_oop(op->obj()->as_register());
2406 }
2407 
2408 
2409 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
2410   assert(op->tmp1()->as_register()  == G1 &&
2411          op->tmp2()->as_register()  == G3 &&
2412          op->tmp3()->as_register()  == G4 &&
2413          op->tmp4()->as_register()  == O1 &&
2414          op->klass()->as_register() == G5, "must be");
2415   if (UseSlowPath ||
2416       (!UseFastNewObjectArray && (op->type() == T_OBJECT || op->type() == T_ARRAY)) ||
2417       (!UseFastNewTypeArray   && (op->type() != T_OBJECT && op->type() != T_ARRAY))) {
2418     __ br(Assembler::always, false, Assembler::pt, *op->stub()->entry());
2419     __ delayed()->nop();
2420   } else {
2421     __ allocate_array(op->obj()->as_register(),
2422                       op->len()->as_register(),
2423                       op->tmp1()->as_register(),
2424                       op->tmp2()->as_register(),
2425                       op->tmp3()->as_register(),
2426                       arrayOopDesc::header_size(op->type()),
2427                       type2aelembytes(op->type()),
2428                       op->klass()->as_register(),
2429                       *op->stub()->entry());
2430   }
2431   __ bind(*op->stub()->continuation());
2432 }
2433 
2434 
2435 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
2436   LIR_Code code = op->code();
2437   if (code == lir_store_check) {
2438     Register value = op->object()->as_register();
2439     Register array = op->array()->as_register();
2440     Register k_RInfo = op->tmp1()->as_register();
2441     Register klass_RInfo = op->tmp2()->as_register();
2442     Register Rtmp1 = op->tmp3()->as_register();
2443 
2444     __ verify_oop(value);
2445 
2446     CodeStub* stub = op->stub();
2447     Label done;
2448     __ cmp(value, 0);
2449     __ br(Assembler::equal, false, Assembler::pn, done);
2450     __ delayed()->nop();
2451     load(array, oopDesc::klass_offset_in_bytes(), k_RInfo, T_OBJECT, op->info_for_exception());
2452     load(value, oopDesc::klass_offset_in_bytes(), klass_RInfo, T_OBJECT, NULL);
2453 
2454     // get instance klass
2455     load(k_RInfo, objArrayKlass::element_klass_offset_in_bytes() + sizeof(oopDesc), k_RInfo, T_OBJECT, NULL);
2456     // perform the fast part of the checking logic
2457     __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, O7, &done, stub->entry(), NULL);
2458 
2459     // call out-of-line instance of __ check_klass_subtype_slow_path(...):
2460     assert(klass_RInfo == G3 && k_RInfo == G1, "incorrect call setup");
2461     __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type);
2462     __ delayed()->nop();
2463     __ cmp(G3, 0);
2464     __ br(Assembler::equal, false, Assembler::pn, *stub->entry());
2465     __ delayed()->nop();
2466     __ bind(done);
2467   } else if (op->code() == lir_checkcast) {
2468     // we always need a stub for the failure case.
2469     CodeStub* stub = op->stub();
2470     Register obj = op->object()->as_register();
2471     Register k_RInfo = op->tmp1()->as_register();
2472     Register klass_RInfo = op->tmp2()->as_register();
2473     Register dst = op->result_opr()->as_register();
2474     Register Rtmp1 = op->tmp3()->as_register();
2475     ciKlass* k = op->klass();
2476 
2477     if (obj == k_RInfo) {
2478       k_RInfo = klass_RInfo;
2479       klass_RInfo = obj;
2480     }
2481     if (op->profiled_method() != NULL) {
2482       ciMethod* method = op->profiled_method();
2483       int bci          = op->profiled_bci();
2484 
2485       // We need two temporaries to perform this operation on SPARC,
2486       // so to keep things simple we perform a redundant test here
2487       Label profile_done;
2488       __ cmp(obj, 0);
2489       __ br(Assembler::notEqual, false, Assembler::pn, profile_done);
2490       __ delayed()->nop();
2491       // Object is null; update methodDataOop
2492       ciMethodData* md = method->method_data();
2493       if (md == NULL) {
2494         bailout("out of memory building methodDataOop");
2495         return;
2496       }
2497       ciProfileData* data = md->bci_to_data(bci);
2498       assert(data != NULL,       "need data for checkcast");
2499       assert(data->is_BitData(), "need BitData for checkcast");
2500       Register mdo      = k_RInfo;
2501       Register data_val = Rtmp1;
2502       jobject2reg(md->constant_encoding(), mdo);
2503 
2504       int mdo_offset_bias = 0;
2505       if (!Assembler::is_simm13(md->byte_offset_of_slot(data, DataLayout::header_offset()) + data->size_in_bytes())) {
2506         // The offset is large so bias the mdo by the base of the slot so
2507         // that the ld can use simm13s to reference the slots of the data
2508         mdo_offset_bias = md->byte_offset_of_slot(data, DataLayout::header_offset());
2509         __ set(mdo_offset_bias, data_val);
2510         __ add(mdo, data_val, mdo);
2511       }
2512 
2513 
2514       Address flags_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias);
2515       __ ldub(flags_addr, data_val);
2516       __ or3(data_val, BitData::null_seen_byte_constant(), data_val);
2517       __ stb(data_val, flags_addr);
2518       __ bind(profile_done);
2519     }
2520 
2521     Label done;
2522     // patching may screw with our temporaries on sparc,
2523     // so let's do it before loading the class
2524     if (k->is_loaded()) {
2525       jobject2reg(k->constant_encoding(), k_RInfo);
2526     } else {
2527       jobject2reg_with_patching(k_RInfo, op->info_for_patch());
2528     }
2529     assert(obj != k_RInfo, "must be different");
2530     __ cmp(obj, 0);
2531     __ br(Assembler::equal, false, Assembler::pn, done);
2532     __ delayed()->nop();
2533 
2534     // get object class
2535     // not a safepoint as obj null check happens earlier
2536     load(obj, oopDesc::klass_offset_in_bytes(), klass_RInfo, T_OBJECT, NULL);
2537     if (op->fast_check()) {
2538       assert_different_registers(klass_RInfo, k_RInfo);
2539       __ cmp(k_RInfo, klass_RInfo);
2540       __ br(Assembler::notEqual, false, Assembler::pt, *stub->entry());
2541       __ delayed()->nop();
2542       __ bind(done);
2543     } else {
2544       bool need_slow_path = true;
2545       if (k->is_loaded()) {
2546         if (k->super_check_offset() != sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes())
2547           need_slow_path = false;
2548         // perform the fast part of the checking logic
2549         __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, noreg,
2550                                          (need_slow_path ? &done : NULL),
2551                                          stub->entry(), NULL,
2552                                          RegisterOrConstant(k->super_check_offset()));
2553       } else {
2554         // perform the fast part of the checking logic
2555         __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, O7,
2556                                          &done, stub->entry(), NULL);
2557       }
2558       if (need_slow_path) {
2559         // call out-of-line instance of __ check_klass_subtype_slow_path(...):
2560         assert(klass_RInfo == G3 && k_RInfo == G1, "incorrect call setup");
2561         __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type);
2562         __ delayed()->nop();
2563         __ cmp(G3, 0);
2564         __ br(Assembler::equal, false, Assembler::pn, *stub->entry());
2565         __ delayed()->nop();
2566       }
2567       __ bind(done);
2568     }
2569     __ mov(obj, dst);
2570   } else if (code == lir_instanceof) {
2571     Register obj = op->object()->as_register();
2572     Register k_RInfo = op->tmp1()->as_register();
2573     Register klass_RInfo = op->tmp2()->as_register();
2574     Register dst = op->result_opr()->as_register();
2575     Register Rtmp1 = op->tmp3()->as_register();
2576     ciKlass* k = op->klass();
2577 
2578     Label done;
2579     if (obj == k_RInfo) {
2580       k_RInfo = klass_RInfo;
2581       klass_RInfo = obj;
2582     }
2583     // patching may screw with our temporaries on sparc,
2584     // so let's do it before loading the class
2585     if (k->is_loaded()) {
2586       jobject2reg(k->constant_encoding(), k_RInfo);
2587     } else {
2588       jobject2reg_with_patching(k_RInfo, op->info_for_patch());
2589     }
2590     assert(obj != k_RInfo, "must be different");
2591     __ cmp(obj, 0);
2592     __ br(Assembler::equal, true, Assembler::pn, done);
2593     __ delayed()->set(0, dst);
2594 
2595     // get object class
2596     // not a safepoint as obj null check happens earlier
2597     load(obj, oopDesc::klass_offset_in_bytes(), klass_RInfo, T_OBJECT, NULL);
2598     if (op->fast_check()) {
2599       __ cmp(k_RInfo, klass_RInfo);
2600       __ br(Assembler::equal, true, Assembler::pt, done);
2601       __ delayed()->set(1, dst);
2602       __ set(0, dst);
2603       __ bind(done);
2604     } else {
2605       bool need_slow_path = true;
2606       if (k->is_loaded()) {
2607         if (k->super_check_offset() != sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes())
2608           need_slow_path = false;
2609         // perform the fast part of the checking logic
2610         __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, O7, noreg,
2611                                          (need_slow_path ? &done : NULL),
2612                                          (need_slow_path ? &done : NULL), NULL,
2613                                          RegisterOrConstant(k->super_check_offset()),
2614                                          dst);
2615       } else {
2616         assert(dst != klass_RInfo && dst != k_RInfo, "need 3 registers");
2617         // perform the fast part of the checking logic
2618         __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, O7, dst,
2619                                          &done, &done, NULL,
2620                                          RegisterOrConstant(-1),
2621                                          dst);
2622       }
2623       if (need_slow_path) {
2624         // call out-of-line instance of __ check_klass_subtype_slow_path(...):
2625         assert(klass_RInfo == G3 && k_RInfo == G1, "incorrect call setup");
2626         __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type);
2627         __ delayed()->nop();
2628         __ mov(G3, dst);
2629       }
2630       __ bind(done);
2631     }
2632   } else {
2633     ShouldNotReachHere();
2634   }
2635 
2636 }
2637 
2638 
2639 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
2640   if (op->code() == lir_cas_long) {
2641     assert(VM_Version::supports_cx8(), "wrong machine");
2642     Register addr = op->addr()->as_pointer_register();
2643     Register cmp_value_lo = op->cmp_value()->as_register_lo();
2644     Register cmp_value_hi = op->cmp_value()->as_register_hi();
2645     Register new_value_lo = op->new_value()->as_register_lo();
2646     Register new_value_hi = op->new_value()->as_register_hi();
2647     Register t1 = op->tmp1()->as_register();
2648     Register t2 = op->tmp2()->as_register();
2649 #ifdef _LP64
2650     __ mov(cmp_value_lo, t1);
2651     __ mov(new_value_lo, t2);
2652 #else
2653     // move high and low halves of long values into single registers
2654     __ sllx(cmp_value_hi, 32, t1);         // shift high half into temp reg
2655     __ srl(cmp_value_lo, 0, cmp_value_lo); // clear upper 32 bits of low half
2656     __ or3(t1, cmp_value_lo, t1);          // t1 holds 64-bit compare value
2657     __ sllx(new_value_hi, 32, t2);
2658     __ srl(new_value_lo, 0, new_value_lo);
2659     __ or3(t2, new_value_lo, t2);          // t2 holds 64-bit value to swap
2660 #endif
2661     // perform the compare and swap operation
2662     __ casx(addr, t1, t2);
2663     // generate condition code - if the swap succeeded, t2 ("new value" reg) was
2664     // overwritten with the original value in "addr" and will be equal to t1.
2665     __ cmp(t1, t2);
2666 
2667   } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj) {
2668     Register addr = op->addr()->as_pointer_register();
2669     Register cmp_value = op->cmp_value()->as_register();
2670     Register new_value = op->new_value()->as_register();
2671     Register t1 = op->tmp1()->as_register();
2672     Register t2 = op->tmp2()->as_register();
2673     __ mov(cmp_value, t1);
2674     __ mov(new_value, t2);
2675 #ifdef _LP64
2676     if (op->code() == lir_cas_obj) {
2677       __ casx(addr, t1, t2);
2678     } else
2679 #endif
2680       {
2681         __ cas(addr, t1, t2);
2682       }
2683     __ cmp(t1, t2);
2684   } else {
2685     Unimplemented();
2686   }
2687 }
2688 
2689 void LIR_Assembler::set_24bit_FPU() {
2690   Unimplemented();
2691 }
2692 
2693 
2694 void LIR_Assembler::reset_FPU() {
2695   Unimplemented();
2696 }
2697 
2698 
2699 void LIR_Assembler::breakpoint() {
2700   __ breakpoint_trap();
2701 }
2702 
2703 
2704 void LIR_Assembler::push(LIR_Opr opr) {
2705   Unimplemented();
2706 }
2707 
2708 
2709 void LIR_Assembler::pop(LIR_Opr opr) {
2710   Unimplemented();
2711 }
2712 
2713 
2714 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst_opr) {
2715   Address mon_addr = frame_map()->address_for_monitor_lock(monitor_no);
2716   Register dst = dst_opr->as_register();
2717   Register reg = mon_addr.base();
2718   int offset = mon_addr.disp();
2719   // compute pointer to BasicLock
2720   if (mon_addr.is_simm13()) {
2721     __ add(reg, offset, dst);
2722   } else {
2723     __ set(offset, dst);
2724     __ add(dst, reg, dst);
2725   }
2726 }
2727 
2728 
2729 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
2730   Register obj = op->obj_opr()->as_register();
2731   Register hdr = op->hdr_opr()->as_register();
2732   Register lock = op->lock_opr()->as_register();
2733 
2734   // obj may not be an oop
2735   if (op->code() == lir_lock) {
2736     MonitorEnterStub* stub = (MonitorEnterStub*)op->stub();
2737     if (UseFastLocking) {
2738       assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2739       // add debug info for NullPointerException only if one is possible
2740       if (op->info() != NULL) {
2741         add_debug_info_for_null_check_here(op->info());
2742       }
2743       __ lock_object(hdr, obj, lock, op->scratch_opr()->as_register(), *op->stub()->entry());
2744     } else {
2745       // always do slow locking
2746       // note: the slow locking code could be inlined here, however if we use
2747       //       slow locking, speed doesn't matter anyway and this solution is
2748       //       simpler and requires less duplicated code - additionally, the
2749       //       slow locking code is the same in either case which simplifies
2750       //       debugging
2751       __ br(Assembler::always, false, Assembler::pt, *op->stub()->entry());
2752       __ delayed()->nop();
2753     }
2754   } else {
2755     assert (op->code() == lir_unlock, "Invalid code, expected lir_unlock");
2756     if (UseFastLocking) {
2757       assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2758       __ unlock_object(hdr, obj, lock, *op->stub()->entry());
2759     } else {
2760       // always do slow unlocking
2761       // note: the slow unlocking code could be inlined here, however if we use
2762       //       slow unlocking, speed doesn't matter anyway and this solution is
2763       //       simpler and requires less duplicated code - additionally, the
2764       //       slow unlocking code is the same in either case which simplifies
2765       //       debugging
2766       __ br(Assembler::always, false, Assembler::pt, *op->stub()->entry());
2767       __ delayed()->nop();
2768     }
2769   }
2770   __ bind(*op->stub()->continuation());
2771 }
2772 
2773 
2774 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
2775   ciMethod* method = op->profiled_method();
2776   int bci          = op->profiled_bci();
2777 
2778   // Update counter for all call types
2779   ciMethodData* md = method->method_data();
2780   if (md == NULL) {
2781     bailout("out of memory building methodDataOop");
2782     return;
2783   }
2784   ciProfileData* data = md->bci_to_data(bci);
2785   assert(data->is_CounterData(), "need CounterData for calls");
2786   assert(op->mdo()->is_single_cpu(),  "mdo must be allocated");
2787   assert(op->tmp1()->is_single_cpu(), "tmp1 must be allocated");
2788   Register mdo  = op->mdo()->as_register();
2789   Register tmp1 = op->tmp1()->as_register();
2790   jobject2reg(md->constant_encoding(), mdo);
2791   int mdo_offset_bias = 0;
2792   if (!Assembler::is_simm13(md->byte_offset_of_slot(data, CounterData::count_offset()) +
2793                             data->size_in_bytes())) {
2794     // The offset is large so bias the mdo by the base of the slot so
2795     // that the ld can use simm13s to reference the slots of the data
2796     mdo_offset_bias = md->byte_offset_of_slot(data, CounterData::count_offset());
2797     __ set(mdo_offset_bias, O7);
2798     __ add(mdo, O7, mdo);
2799   }
2800 
2801   Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias);
2802   Bytecodes::Code bc = method->java_code_at_bci(bci);
2803   // Perform additional virtual call profiling for invokevirtual and
2804   // invokeinterface bytecodes
2805   if ((bc == Bytecodes::_invokevirtual || bc == Bytecodes::_invokeinterface) &&
2806       Tier1ProfileVirtualCalls) {
2807     assert(op->recv()->is_single_cpu(), "recv must be allocated");
2808     Register recv = op->recv()->as_register();
2809     assert_different_registers(mdo, tmp1, recv);
2810     assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
2811     ciKlass* known_klass = op->known_holder();
2812     if (Tier1OptimizeVirtualCallProfiling && known_klass != NULL) {
2813       // We know the type that will be seen at this call site; we can
2814       // statically update the methodDataOop rather than needing to do
2815       // dynamic tests on the receiver type
2816 
2817       // NOTE: we should probably put a lock around this search to
2818       // avoid collisions by concurrent compilations
2819       ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
2820       uint i;
2821       for (i = 0; i < VirtualCallData::row_limit(); i++) {
2822         ciKlass* receiver = vc_data->receiver(i);
2823         if (known_klass->equals(receiver)) {
2824           Address data_addr(mdo, md->byte_offset_of_slot(data,
2825                                                          VirtualCallData::receiver_count_offset(i)) -
2826                             mdo_offset_bias);
2827           __ lduw(data_addr, tmp1);
2828           __ add(tmp1, DataLayout::counter_increment, tmp1);
2829           __ stw(tmp1, data_addr);
2830           return;
2831         }
2832       }
2833 
2834       // Receiver type not found in profile data; select an empty slot
2835 
2836       // Note that this is less efficient than it should be because it
2837       // always does a write to the receiver part of the
2838       // VirtualCallData rather than just the first time
2839       for (i = 0; i < VirtualCallData::row_limit(); i++) {
2840         ciKlass* receiver = vc_data->receiver(i);
2841         if (receiver == NULL) {
2842           Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)) -
2843                             mdo_offset_bias);
2844           jobject2reg(known_klass->constant_encoding(), tmp1);
2845           __ st_ptr(tmp1, recv_addr);
2846           Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) -
2847                             mdo_offset_bias);
2848           __ lduw(data_addr, tmp1);
2849           __ add(tmp1, DataLayout::counter_increment, tmp1);
2850           __ stw(tmp1, data_addr);
2851           return;
2852         }
2853       }
2854     } else {
2855       load(Address(recv, oopDesc::klass_offset_in_bytes()), recv, T_OBJECT);
2856       Label update_done;
2857       uint i;
2858       for (i = 0; i < VirtualCallData::row_limit(); i++) {
2859         Label next_test;
2860         // See if the receiver is receiver[n].
2861         Address receiver_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)) -
2862                               mdo_offset_bias);
2863         __ ld_ptr(receiver_addr, tmp1);
2864         __ verify_oop(tmp1);
2865         __ cmp(recv, tmp1);
2866         __ brx(Assembler::notEqual, false, Assembler::pt, next_test);
2867         __ delayed()->nop();
2868         Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) -
2869                           mdo_offset_bias);
2870         __ lduw(data_addr, tmp1);
2871         __ add(tmp1, DataLayout::counter_increment, tmp1);
2872         __ stw(tmp1, data_addr);
2873         __ br(Assembler::always, false, Assembler::pt, update_done);
2874         __ delayed()->nop();
2875         __ bind(next_test);
2876       }
2877 
2878       // Didn't find receiver; find next empty slot and fill it in
2879       for (i = 0; i < VirtualCallData::row_limit(); i++) {
2880         Label next_test;
2881         Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)) -
2882                           mdo_offset_bias);
2883         load(recv_addr, tmp1, T_OBJECT);
2884         __ tst(tmp1);
2885         __ brx(Assembler::notEqual, false, Assembler::pt, next_test);
2886         __ delayed()->nop();
2887         __ st_ptr(recv, recv_addr);
2888         __ set(DataLayout::counter_increment, tmp1);
2889         __ st_ptr(tmp1, mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) -
2890                   mdo_offset_bias);
2891         __ br(Assembler::always, false, Assembler::pt, update_done);
2892         __ delayed()->nop();
2893         __ bind(next_test);
2894       }
2895       // Receiver did not match any saved receiver and there is no empty row for it.
2896       // Increment total counter to indicate polymorphic case.
2897       __ lduw(counter_addr, tmp1);
2898       __ add(tmp1, DataLayout::counter_increment, tmp1);
2899       __ stw(tmp1, counter_addr);
2900 
2901       __ bind(update_done);
2902     }
2903   } else {
2904     // Static call
2905     __ lduw(counter_addr, tmp1);
2906     __ add(tmp1, DataLayout::counter_increment, tmp1);
2907     __ stw(tmp1, counter_addr);
2908   }
2909 }
2910 
2911 
2912 void LIR_Assembler::align_backward_branch_target() {
2913   __ align(OptoLoopAlignment);
2914 }
2915 
2916 
2917 void LIR_Assembler::emit_delay(LIR_OpDelay* op) {
2918   // make sure we are expecting a delay
2919   // this has the side effect of clearing the delay state
2920   // so we can use _masm instead of _masm->delayed() to do the
2921   // code generation.
2922   __ delayed();
2923 
2924   // make sure we only emit one instruction
2925   int offset = code_offset();
2926   op->delay_op()->emit_code(this);
2927 #ifdef ASSERT
2928   if (code_offset() - offset != NativeInstruction::nop_instruction_size) {
2929     op->delay_op()->print();
2930   }
2931   assert(code_offset() - offset == NativeInstruction::nop_instruction_size,
2932          "only one instruction can go in a delay slot");
2933 #endif
2934 
2935   // we may also be emitting the call info for the instruction
2936   // which we are the delay slot of.
2937   CodeEmitInfo * call_info = op->call_info();
2938   if (call_info) {
2939     add_call_info(code_offset(), call_info);
2940   }
2941 
2942   if (VerifyStackAtCalls) {
2943     _masm->sub(FP, SP, O7);
2944     _masm->cmp(O7, initial_frame_size_in_bytes());
2945     _masm->trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2 );
2946   }
2947 }
2948 
2949 
2950 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest) {
2951   assert(left->is_register(), "can only handle registers");
2952 
2953   if (left->is_single_cpu()) {
2954     __ neg(left->as_register(), dest->as_register());
2955   } else if (left->is_single_fpu()) {
2956     __ fneg(FloatRegisterImpl::S, left->as_float_reg(), dest->as_float_reg());
2957   } else if (left->is_double_fpu()) {
2958     __ fneg(FloatRegisterImpl::D, left->as_double_reg(), dest->as_double_reg());
2959   } else {
2960     assert (left->is_double_cpu(), "Must be a long");
2961     Register Rlow = left->as_register_lo();
2962     Register Rhi = left->as_register_hi();
2963 #ifdef _LP64
2964     __ sub(G0, Rlow, dest->as_register_lo());
2965 #else
2966     __ subcc(G0, Rlow, dest->as_register_lo());
2967     __ subc (G0, Rhi,  dest->as_register_hi());
2968 #endif
2969   }
2970 }
2971 
2972 
2973 void LIR_Assembler::fxch(int i) {
2974   Unimplemented();
2975 }
2976 
2977 void LIR_Assembler::fld(int i) {
2978   Unimplemented();
2979 }
2980 
2981 void LIR_Assembler::ffree(int i) {
2982   Unimplemented();
2983 }
2984 
2985 void LIR_Assembler::rt_call(LIR_Opr result, address dest,
2986                             const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
2987 
2988   // if tmp is invalid, then the function being called doesn't destroy the thread
2989   if (tmp->is_valid()) {
2990     __ save_thread(tmp->as_register());
2991   }
2992   __ call(dest, relocInfo::runtime_call_type);
2993   __ delayed()->nop();
2994   if (info != NULL) {
2995     add_call_info_here(info);
2996   }
2997   if (tmp->is_valid()) {
2998     __ restore_thread(tmp->as_register());
2999   }
3000 
3001 #ifdef ASSERT
3002   __ verify_thread();
3003 #endif // ASSERT
3004 }
3005 
3006 
3007 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
3008 #ifdef _LP64
3009   ShouldNotReachHere();
3010 #endif
3011 
3012   NEEDS_CLEANUP;
3013   if (type == T_LONG) {
3014     LIR_Address* mem_addr = dest->is_address() ? dest->as_address_ptr() : src->as_address_ptr();
3015 
3016     // (extended to allow indexed as well as constant displaced for JSR-166)
3017     Register idx = noreg; // contains either constant offset or index
3018 
3019     int disp = mem_addr->disp();
3020     if (mem_addr->index() == LIR_OprFact::illegalOpr) {
3021       if (!Assembler::is_simm13(disp)) {
3022         idx = O7;
3023         __ set(disp, idx);
3024       }
3025     } else {
3026       assert(disp == 0, "not both indexed and disp");
3027       idx = mem_addr->index()->as_register();
3028     }
3029 
3030     int null_check_offset = -1;
3031 
3032     Register base = mem_addr->base()->as_register();
3033     if (src->is_register() && dest->is_address()) {
3034       // G4 is high half, G5 is low half
3035       if (VM_Version::v9_instructions_work()) {
3036         // clear the top bits of G5, and scale up G4
3037         __ srl (src->as_register_lo(),  0, G5);
3038         __ sllx(src->as_register_hi(), 32, G4);
3039         // combine the two halves into the 64 bits of G4
3040         __ or3(G4, G5, G4);
3041         null_check_offset = __ offset();
3042         if (idx == noreg) {
3043           __ stx(G4, base, disp);
3044         } else {
3045           __ stx(G4, base, idx);
3046         }
3047       } else {
3048         __ mov (src->as_register_hi(), G4);
3049         __ mov (src->as_register_lo(), G5);
3050         null_check_offset = __ offset();
3051         if (idx == noreg) {
3052           __ std(G4, base, disp);
3053         } else {
3054           __ std(G4, base, idx);
3055         }
3056       }
3057     } else if (src->is_address() && dest->is_register()) {
3058       null_check_offset = __ offset();
3059       if (VM_Version::v9_instructions_work()) {
3060         if (idx == noreg) {
3061           __ ldx(base, disp, G5);
3062         } else {
3063           __ ldx(base, idx, G5);
3064         }
3065         __ srax(G5, 32, dest->as_register_hi()); // fetch the high half into hi
3066         __ mov (G5, dest->as_register_lo());     // copy low half into lo
3067       } else {
3068         if (idx == noreg) {
3069           __ ldd(base, disp, G4);
3070         } else {
3071           __ ldd(base, idx, G4);
3072         }
3073         // G4 is high half, G5 is low half
3074         __ mov (G4, dest->as_register_hi());
3075         __ mov (G5, dest->as_register_lo());
3076       }
3077     } else {
3078       Unimplemented();
3079     }
3080     if (info != NULL) {
3081       add_debug_info_for_null_check(null_check_offset, info);
3082     }
3083 
3084   } else {
3085     // use normal move for all other volatiles since they don't need
3086     // special handling to remain atomic.
3087     move_op(src, dest, type, lir_patch_none, info, false, false);
3088   }
3089 }
3090 
3091 void LIR_Assembler::membar() {
3092   // only StoreLoad membars are ever explicitly needed on sparcs in TSO mode
3093   __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad) );
3094 }
3095 
3096 void LIR_Assembler::membar_acquire() {
3097   // no-op on TSO
3098 }
3099 
3100 void LIR_Assembler::membar_release() {
3101   // no-op on TSO
3102 }
3103 
3104 // Macro to Pack two sequential registers containing 32 bit values
3105 // into a single 64 bit register.
3106 // rs and rs->successor() are packed into rd
3107 // rd and rs may be the same register.
3108 // Note: rs and rs->successor() are destroyed.
3109 void LIR_Assembler::pack64( Register rs, Register rd ) {
3110   __ sllx(rs, 32, rs);
3111   __ srl(rs->successor(), 0, rs->successor());
3112   __ or3(rs, rs->successor(), rd);
3113 }
3114 
3115 // Macro to unpack a 64 bit value in a register into
3116 // two sequential registers.
3117 // rd is unpacked into rd and rd->successor()
3118 void LIR_Assembler::unpack64( Register rd ) {
3119   __ mov(rd, rd->successor());
3120   __ srax(rd, 32, rd);
3121   __ sra(rd->successor(), 0, rd->successor());
3122 }
3123 
3124 
3125 void LIR_Assembler::leal(LIR_Opr addr_opr, LIR_Opr dest) {
3126   LIR_Address* addr = addr_opr->as_address_ptr();
3127   assert(addr->index()->is_illegal() && addr->scale() == LIR_Address::times_1 && Assembler::is_simm13(addr->disp()), "can't handle complex addresses yet");
3128   __ add(addr->base()->as_register(), addr->disp(), dest->as_register());
3129 }
3130 
3131 
3132 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
3133   assert(result_reg->is_register(), "check");
3134   __ mov(G2_thread, result_reg->as_register());
3135 }
3136 
3137 
3138 void LIR_Assembler::peephole(LIR_List* lir) {
3139   LIR_OpList* inst = lir->instructions_list();
3140   for (int i = 0; i < inst->length(); i++) {
3141     LIR_Op* op = inst->at(i);
3142     switch (op->code()) {
3143       case lir_cond_float_branch:
3144       case lir_branch: {
3145         LIR_OpBranch* branch = op->as_OpBranch();
3146         assert(branch->info() == NULL, "shouldn't be state on branches anymore");
3147         LIR_Op* delay_op = NULL;
3148         // we'd like to be able to pull following instructions into
3149         // this slot but we don't know enough to do it safely yet so
3150         // only optimize block to block control flow.
3151         if (LIRFillDelaySlots && branch->block()) {
3152           LIR_Op* prev = inst->at(i - 1);
3153           if (prev && LIR_Assembler::is_single_instruction(prev) && prev->info() == NULL) {
3154             // swap previous instruction into delay slot
3155             inst->at_put(i - 1, op);
3156             inst->at_put(i, new LIR_OpDelay(prev, op->info()));
3157 #ifndef PRODUCT
3158             if (LIRTracePeephole) {
3159               tty->print_cr("delayed");
3160               inst->at(i - 1)->print();
3161               inst->at(i)->print();

3162             }
3163 #endif
3164             continue;
3165           }
3166         }
3167 
3168         if (!delay_op) {
3169           delay_op = new LIR_OpDelay(new LIR_Op0(lir_nop), NULL);
3170         }
3171         inst->insert_before(i + 1, delay_op);
3172         break;
3173       }
3174       case lir_static_call:
3175       case lir_virtual_call:
3176       case lir_icvirtual_call:
3177       case lir_optvirtual_call: {
3178         LIR_Op* delay_op = NULL;
3179         LIR_Op* prev = inst->at(i - 1);
3180         if (LIRFillDelaySlots && prev && prev->code() == lir_move && prev->info() == NULL &&
3181             (op->code() != lir_virtual_call ||
3182              !prev->result_opr()->is_single_cpu() ||
3183              prev->result_opr()->as_register() != O0) &&
3184             LIR_Assembler::is_single_instruction(prev)) {
3185           // Only moves without info can be put into the delay slot.
3186           // Also don't allow the setup of the receiver in the delay
3187           // slot for vtable calls.
3188           inst->at_put(i - 1, op);
3189           inst->at_put(i, new LIR_OpDelay(prev, op->info()));
3190 #ifndef PRODUCT
3191           if (LIRTracePeephole) {
3192             tty->print_cr("delayed");
3193             inst->at(i - 1)->print();
3194             inst->at(i)->print();

3195           }
3196 #endif
3197           continue;
3198         }
3199 
3200         if (!delay_op) {
3201           delay_op = new LIR_OpDelay(new LIR_Op0(lir_nop), op->as_OpJavaCall()->info());
3202           inst->insert_before(i + 1, delay_op);
3203         }
3204         break;
3205       }
3206     }
3207   }
3208 }
3209 
3210 
3211 
3212 
3213 #undef __
--- EOF ---