src/cpu/sparc/vm/c1_LIRAssembler_sparc.cpp
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src/cpu/sparc/vm/c1_LIRAssembler_sparc.cpp

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 719       Register rval = op->in_opr()->as_register();
 720       Register rdst = dst->as_register();
 721       int shift = BitsPerInt - T_CHAR_aelem_bytes * BitsPerByte;
 722       __ sll (rval, shift, rdst);
 723       __ srl (rdst, shift, rdst);
 724       break;
 725     }
 726 
 727     default: ShouldNotReachHere();
 728   }
 729 }
 730 
 731 
 732 void LIR_Assembler::align_call(LIR_Code) {
 733   // do nothing since all instructions are word aligned on sparc
 734 }
 735 
 736 
 737 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
 738   __ call(op->addr(), rtype);
 739   // the peephole pass fills the delay slot

 740 }
 741 
 742 
 743 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
 744   RelocationHolder rspec = virtual_call_Relocation::spec(pc());
 745   __ set_oop((jobject)Universe::non_oop_word(), G5_inline_cache_reg);
 746   __ relocate(rspec);
 747   __ call(op->addr(), relocInfo::none);
 748   // the peephole pass fills the delay slot

 749 }
 750 
 751 
 752 void LIR_Assembler::vtable_call(LIR_OpJavaCall* op) {
 753   add_debug_info_for_null_check_here(op->info());
 754   __ ld_ptr(O0, oopDesc::klass_offset_in_bytes(), G3_scratch);
 755   if (__ is_simm13(op->vtable_offset())) {
 756     __ ld_ptr(G3_scratch, op->vtable_offset(), G5_method);
 757   } else {
 758     // This will generate 2 instructions
 759     __ set(op->vtable_offset(), G5_method);
 760     // ld_ptr, set_hi, set
 761     __ ld_ptr(G3_scratch, G5_method, G5_method);
 762   }
 763   __ ld_ptr(G5_method, methodOopDesc::from_compiled_offset(), G3_scratch);
 764   __ callr(G3_scratch, G0);
 765   // the peephole pass fills the delay slot
 766 }
 767 
 768 
 769 void LIR_Assembler::preserve_SP(LIR_OpJavaCall* op) {
 770   Unimplemented();
 771 }
 772 
 773 
 774 void LIR_Assembler::restore_SP(LIR_OpJavaCall* op) {
 775   Unimplemented();
 776 }
 777 
 778 
 779 // load with 32-bit displacement
 780 int LIR_Assembler::load(Register s, int disp, Register d, BasicType ld_type, CodeEmitInfo *info) {
 781   int load_offset = code_offset();
 782   if (Assembler::is_simm13(disp)) {
 783     if (info != NULL) add_debug_info_for_null_check_here(info);
 784     switch(ld_type) {
 785       case T_BOOLEAN: // fall through
 786       case T_BYTE  : __ ldsb(s, disp, d); break;
 787       case T_CHAR  : __ lduh(s, disp, d); break;
 788       case T_SHORT : __ ldsh(s, disp, d); break;
 789       case T_INT   : __ ld(s, disp, d); break;
 790       case T_ADDRESS:// fall through
 791       case T_ARRAY : // fall through
 792       case T_OBJECT: __ ld_ptr(s, disp, d); break;
 793       default      : ShouldNotReachHere();
 794     }
 795   } else {
 796     __ set(disp, O7);
 797     if (info != NULL) add_debug_info_for_null_check_here(info);
 798     load_offset = code_offset();


2917 void LIR_Assembler::emit_delay(LIR_OpDelay* op) {
2918   // make sure we are expecting a delay
2919   // this has the side effect of clearing the delay state
2920   // so we can use _masm instead of _masm->delayed() to do the
2921   // code generation.
2922   __ delayed();
2923 
2924   // make sure we only emit one instruction
2925   int offset = code_offset();
2926   op->delay_op()->emit_code(this);
2927 #ifdef ASSERT
2928   if (code_offset() - offset != NativeInstruction::nop_instruction_size) {
2929     op->delay_op()->print();
2930   }
2931   assert(code_offset() - offset == NativeInstruction::nop_instruction_size,
2932          "only one instruction can go in a delay slot");
2933 #endif
2934 
2935   // we may also be emitting the call info for the instruction
2936   // which we are the delay slot of.
2937   CodeEmitInfo * call_info = op->call_info();
2938   if (call_info) {
2939     add_call_info(code_offset(), call_info);
2940   }
2941 
2942   if (VerifyStackAtCalls) {
2943     _masm->sub(FP, SP, O7);
2944     _masm->cmp(O7, initial_frame_size_in_bytes());
2945     _masm->trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2 );
2946   }
2947 }
2948 
2949 
2950 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest) {
2951   assert(left->is_register(), "can only handle registers");
2952 
2953   if (left->is_single_cpu()) {
2954     __ neg(left->as_register(), dest->as_register());
2955   } else if (left->is_single_fpu()) {
2956     __ fneg(FloatRegisterImpl::S, left->as_float_reg(), dest->as_float_reg());
2957   } else if (left->is_double_fpu()) {


3142     switch (op->code()) {
3143       case lir_cond_float_branch:
3144       case lir_branch: {
3145         LIR_OpBranch* branch = op->as_OpBranch();
3146         assert(branch->info() == NULL, "shouldn't be state on branches anymore");
3147         LIR_Op* delay_op = NULL;
3148         // we'd like to be able to pull following instructions into
3149         // this slot but we don't know enough to do it safely yet so
3150         // only optimize block to block control flow.
3151         if (LIRFillDelaySlots && branch->block()) {
3152           LIR_Op* prev = inst->at(i - 1);
3153           if (prev && LIR_Assembler::is_single_instruction(prev) && prev->info() == NULL) {
3154             // swap previous instruction into delay slot
3155             inst->at_put(i - 1, op);
3156             inst->at_put(i, new LIR_OpDelay(prev, op->info()));
3157 #ifndef PRODUCT
3158             if (LIRTracePeephole) {
3159               tty->print_cr("delayed");
3160               inst->at(i - 1)->print();
3161               inst->at(i)->print();

3162             }
3163 #endif
3164             continue;
3165           }
3166         }
3167 
3168         if (!delay_op) {
3169           delay_op = new LIR_OpDelay(new LIR_Op0(lir_nop), NULL);
3170         }
3171         inst->insert_before(i + 1, delay_op);
3172         break;
3173       }
3174       case lir_static_call:
3175       case lir_virtual_call:
3176       case lir_icvirtual_call:
3177       case lir_optvirtual_call: {
3178         LIR_Op* delay_op = NULL;
3179         LIR_Op* prev = inst->at(i - 1);
3180         if (LIRFillDelaySlots && prev && prev->code() == lir_move && prev->info() == NULL &&
3181             (op->code() != lir_virtual_call ||
3182              !prev->result_opr()->is_single_cpu() ||
3183              prev->result_opr()->as_register() != O0) &&
3184             LIR_Assembler::is_single_instruction(prev)) {
3185           // Only moves without info can be put into the delay slot.
3186           // Also don't allow the setup of the receiver in the delay
3187           // slot for vtable calls.
3188           inst->at_put(i - 1, op);
3189           inst->at_put(i, new LIR_OpDelay(prev, op->info()));
3190 #ifndef PRODUCT
3191           if (LIRTracePeephole) {
3192             tty->print_cr("delayed");
3193             inst->at(i - 1)->print();
3194             inst->at(i)->print();

3195           }
3196 #endif
3197           continue;
3198         }
3199 
3200         if (!delay_op) {
3201           delay_op = new LIR_OpDelay(new LIR_Op0(lir_nop), op->as_OpJavaCall()->info());
3202           inst->insert_before(i + 1, delay_op);
3203         }
3204         break;
3205       }
3206     }
3207   }
3208 }
3209 
3210 
3211 
3212 
3213 #undef __


 719       Register rval = op->in_opr()->as_register();
 720       Register rdst = dst->as_register();
 721       int shift = BitsPerInt - T_CHAR_aelem_bytes * BitsPerByte;
 722       __ sll (rval, shift, rdst);
 723       __ srl (rdst, shift, rdst);
 724       break;
 725     }
 726 
 727     default: ShouldNotReachHere();
 728   }
 729 }
 730 
 731 
 732 void LIR_Assembler::align_call(LIR_Code) {
 733   // do nothing since all instructions are word aligned on sparc
 734 }
 735 
 736 
 737 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
 738   __ call(op->addr(), rtype);
 739   // The peephole pass fills the delay slot, add_call_info is done in
 740   // LIR_Assembler::emit_delay.
 741 }
 742 
 743 
 744 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
 745   RelocationHolder rspec = virtual_call_Relocation::spec(pc());
 746   __ set_oop((jobject)Universe::non_oop_word(), G5_inline_cache_reg);
 747   __ relocate(rspec);
 748   __ call(op->addr(), relocInfo::none);
 749   // The peephole pass fills the delay slot, add_call_info is done in
 750   // LIR_Assembler::emit_delay.
 751 }
 752 
 753 
 754 void LIR_Assembler::vtable_call(LIR_OpJavaCall* op) {
 755   add_debug_info_for_null_check_here(op->info());
 756   __ ld_ptr(O0, oopDesc::klass_offset_in_bytes(), G3_scratch);
 757   if (__ is_simm13(op->vtable_offset())) {
 758     __ ld_ptr(G3_scratch, op->vtable_offset(), G5_method);
 759   } else {
 760     // This will generate 2 instructions
 761     __ set(op->vtable_offset(), G5_method);
 762     // ld_ptr, set_hi, set
 763     __ ld_ptr(G3_scratch, G5_method, G5_method);
 764   }
 765   __ ld_ptr(G5_method, methodOopDesc::from_compiled_offset(), G3_scratch);
 766   __ callr(G3_scratch, G0);
 767   // the peephole pass fills the delay slot
 768 }
 769 
 770 










 771 // load with 32-bit displacement
 772 int LIR_Assembler::load(Register s, int disp, Register d, BasicType ld_type, CodeEmitInfo *info) {
 773   int load_offset = code_offset();
 774   if (Assembler::is_simm13(disp)) {
 775     if (info != NULL) add_debug_info_for_null_check_here(info);
 776     switch(ld_type) {
 777       case T_BOOLEAN: // fall through
 778       case T_BYTE  : __ ldsb(s, disp, d); break;
 779       case T_CHAR  : __ lduh(s, disp, d); break;
 780       case T_SHORT : __ ldsh(s, disp, d); break;
 781       case T_INT   : __ ld(s, disp, d); break;
 782       case T_ADDRESS:// fall through
 783       case T_ARRAY : // fall through
 784       case T_OBJECT: __ ld_ptr(s, disp, d); break;
 785       default      : ShouldNotReachHere();
 786     }
 787   } else {
 788     __ set(disp, O7);
 789     if (info != NULL) add_debug_info_for_null_check_here(info);
 790     load_offset = code_offset();


2909 void LIR_Assembler::emit_delay(LIR_OpDelay* op) {
2910   // make sure we are expecting a delay
2911   // this has the side effect of clearing the delay state
2912   // so we can use _masm instead of _masm->delayed() to do the
2913   // code generation.
2914   __ delayed();
2915 
2916   // make sure we only emit one instruction
2917   int offset = code_offset();
2918   op->delay_op()->emit_code(this);
2919 #ifdef ASSERT
2920   if (code_offset() - offset != NativeInstruction::nop_instruction_size) {
2921     op->delay_op()->print();
2922   }
2923   assert(code_offset() - offset == NativeInstruction::nop_instruction_size,
2924          "only one instruction can go in a delay slot");
2925 #endif
2926 
2927   // we may also be emitting the call info for the instruction
2928   // which we are the delay slot of.
2929   CodeEmitInfo* call_info = op->call_info();
2930   if (call_info) {
2931     add_call_info(code_offset(), call_info);
2932   }
2933 
2934   if (VerifyStackAtCalls) {
2935     _masm->sub(FP, SP, O7);
2936     _masm->cmp(O7, initial_frame_size_in_bytes());
2937     _masm->trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2 );
2938   }
2939 }
2940 
2941 
2942 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest) {
2943   assert(left->is_register(), "can only handle registers");
2944 
2945   if (left->is_single_cpu()) {
2946     __ neg(left->as_register(), dest->as_register());
2947   } else if (left->is_single_fpu()) {
2948     __ fneg(FloatRegisterImpl::S, left->as_float_reg(), dest->as_float_reg());
2949   } else if (left->is_double_fpu()) {


3134     switch (op->code()) {
3135       case lir_cond_float_branch:
3136       case lir_branch: {
3137         LIR_OpBranch* branch = op->as_OpBranch();
3138         assert(branch->info() == NULL, "shouldn't be state on branches anymore");
3139         LIR_Op* delay_op = NULL;
3140         // we'd like to be able to pull following instructions into
3141         // this slot but we don't know enough to do it safely yet so
3142         // only optimize block to block control flow.
3143         if (LIRFillDelaySlots && branch->block()) {
3144           LIR_Op* prev = inst->at(i - 1);
3145           if (prev && LIR_Assembler::is_single_instruction(prev) && prev->info() == NULL) {
3146             // swap previous instruction into delay slot
3147             inst->at_put(i - 1, op);
3148             inst->at_put(i, new LIR_OpDelay(prev, op->info()));
3149 #ifndef PRODUCT
3150             if (LIRTracePeephole) {
3151               tty->print_cr("delayed");
3152               inst->at(i - 1)->print();
3153               inst->at(i)->print();
3154               tty->cr();
3155             }
3156 #endif
3157             continue;
3158           }
3159         }
3160 
3161         if (!delay_op) {
3162           delay_op = new LIR_OpDelay(new LIR_Op0(lir_nop), NULL);
3163         }
3164         inst->insert_before(i + 1, delay_op);
3165         break;
3166       }
3167       case lir_static_call:
3168       case lir_virtual_call:
3169       case lir_icvirtual_call:
3170       case lir_optvirtual_call:
3171       case lir_dynamic_call: {
3172         LIR_Op* prev = inst->at(i - 1);
3173         if (LIRFillDelaySlots && prev && prev->code() == lir_move && prev->info() == NULL &&
3174             (op->code() != lir_virtual_call ||
3175              !prev->result_opr()->is_single_cpu() ||
3176              prev->result_opr()->as_register() != O0) &&
3177             LIR_Assembler::is_single_instruction(prev)) {
3178           // Only moves without info can be put into the delay slot.
3179           // Also don't allow the setup of the receiver in the delay
3180           // slot for vtable calls.
3181           inst->at_put(i - 1, op);
3182           inst->at_put(i, new LIR_OpDelay(prev, op->info()));
3183 #ifndef PRODUCT
3184           if (LIRTracePeephole) {
3185             tty->print_cr("delayed");
3186             inst->at(i - 1)->print();
3187             inst->at(i)->print();
3188             tty->cr();
3189           }
3190 #endif
3191           continue;
3192         }
3193 
3194         LIR_Op* delay_op = new LIR_OpDelay(new LIR_Op0(lir_nop), op->as_OpJavaCall()->info());

3195         inst->insert_before(i + 1, delay_op);

3196         break;
3197       }
3198     }
3199   }
3200 }
3201 
3202 
3203 
3204 
3205 #undef __
src/cpu/sparc/vm/c1_LIRAssembler_sparc.cpp
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