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          --- old/src/cpu/sparc/vm/c1_LIRAssembler_sparc.cpp
          +++ new/src/cpu/sparc/vm/c1_LIRAssembler_sparc.cpp
↓ open down ↓ 728 lines elided ↑ open up ↑
 729  729  }
 730  730  
 731  731  
 732  732  void LIR_Assembler::align_call(LIR_Code) {
 733  733    // do nothing since all instructions are word aligned on sparc
 734  734  }
 735  735  
 736  736  
 737  737  void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
 738  738    __ call(op->addr(), rtype);
 739      -  // the peephole pass fills the delay slot
      739 +  // The peephole pass fills the delay slot, add_call_info is done in
      740 +  // LIR_Assembler::emit_delay.
 740  741  }
 741  742  
 742  743  
 743  744  void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
 744  745    RelocationHolder rspec = virtual_call_Relocation::spec(pc());
 745  746    __ set_oop((jobject)Universe::non_oop_word(), G5_inline_cache_reg);
 746  747    __ relocate(rspec);
 747  748    __ call(op->addr(), relocInfo::none);
 748      -  // the peephole pass fills the delay slot
      749 +  // The peephole pass fills the delay slot, add_call_info is done in
      750 +  // LIR_Assembler::emit_delay.
 749  751  }
 750  752  
 751  753  
 752  754  void LIR_Assembler::vtable_call(LIR_OpJavaCall* op) {
 753  755    add_debug_info_for_null_check_here(op->info());
 754  756    __ ld_ptr(O0, oopDesc::klass_offset_in_bytes(), G3_scratch);
 755  757    if (__ is_simm13(op->vtable_offset())) {
 756  758      __ ld_ptr(G3_scratch, op->vtable_offset(), G5_method);
 757  759    } else {
 758  760      // This will generate 2 instructions
 759  761      __ set(op->vtable_offset(), G5_method);
 760  762      // ld_ptr, set_hi, set
 761  763      __ ld_ptr(G3_scratch, G5_method, G5_method);
 762  764    }
 763  765    __ ld_ptr(G5_method, methodOopDesc::from_compiled_offset(), G3_scratch);
 764  766    __ callr(G3_scratch, G0);
 765  767    // the peephole pass fills the delay slot
 766  768  }
 767  769  
 768  770  
 769      -void LIR_Assembler::preserve_SP(LIR_OpJavaCall* op) {
 770      -  Unimplemented();
 771      -}
 772      -
 773      -
 774      -void LIR_Assembler::restore_SP(LIR_OpJavaCall* op) {
 775      -  Unimplemented();
 776      -}
 777      -
 778      -
 779  771  // load with 32-bit displacement
 780  772  int LIR_Assembler::load(Register s, int disp, Register d, BasicType ld_type, CodeEmitInfo *info) {
 781  773    int load_offset = code_offset();
 782  774    if (Assembler::is_simm13(disp)) {
 783  775      if (info != NULL) add_debug_info_for_null_check_here(info);
 784  776      switch(ld_type) {
 785  777        case T_BOOLEAN: // fall through
 786  778        case T_BYTE  : __ ldsb(s, disp, d); break;
 787  779        case T_CHAR  : __ lduh(s, disp, d); break;
 788  780        case T_SHORT : __ ldsh(s, disp, d); break;
↓ open down ↓ 2138 lines elided ↑ open up ↑
2927 2919  #ifdef ASSERT
2928 2920    if (code_offset() - offset != NativeInstruction::nop_instruction_size) {
2929 2921      op->delay_op()->print();
2930 2922    }
2931 2923    assert(code_offset() - offset == NativeInstruction::nop_instruction_size,
2932 2924           "only one instruction can go in a delay slot");
2933 2925  #endif
2934 2926  
2935 2927    // we may also be emitting the call info for the instruction
2936 2928    // which we are the delay slot of.
2937      -  CodeEmitInfo * call_info = op->call_info();
     2929 +  CodeEmitInfo* call_info = op->call_info();
2938 2930    if (call_info) {
2939 2931      add_call_info(code_offset(), call_info);
2940 2932    }
2941 2933  
2942 2934    if (VerifyStackAtCalls) {
2943 2935      _masm->sub(FP, SP, O7);
2944 2936      _masm->cmp(O7, initial_frame_size_in_bytes());
2945 2937      _masm->trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2 );
2946 2938    }
2947 2939  }
↓ open down ↓ 204 lines elided ↑ open up ↑
3152 3144            LIR_Op* prev = inst->at(i - 1);
3153 3145            if (prev && LIR_Assembler::is_single_instruction(prev) && prev->info() == NULL) {
3154 3146              // swap previous instruction into delay slot
3155 3147              inst->at_put(i - 1, op);
3156 3148              inst->at_put(i, new LIR_OpDelay(prev, op->info()));
3157 3149  #ifndef PRODUCT
3158 3150              if (LIRTracePeephole) {
3159 3151                tty->print_cr("delayed");
3160 3152                inst->at(i - 1)->print();
3161 3153                inst->at(i)->print();
     3154 +              tty->cr();
3162 3155              }
3163 3156  #endif
3164 3157              continue;
3165 3158            }
3166 3159          }
3167 3160  
3168 3161          if (!delay_op) {
3169 3162            delay_op = new LIR_OpDelay(new LIR_Op0(lir_nop), NULL);
3170 3163          }
3171 3164          inst->insert_before(i + 1, delay_op);
3172 3165          break;
3173 3166        }
3174 3167        case lir_static_call:
3175 3168        case lir_virtual_call:
3176 3169        case lir_icvirtual_call:
3177      -      case lir_optvirtual_call: {
3178      -        LIR_Op* delay_op = NULL;
     3170 +      case lir_optvirtual_call:
     3171 +      case lir_dynamic_call: {
3179 3172          LIR_Op* prev = inst->at(i - 1);
3180 3173          if (LIRFillDelaySlots && prev && prev->code() == lir_move && prev->info() == NULL &&
3181 3174              (op->code() != lir_virtual_call ||
3182 3175               !prev->result_opr()->is_single_cpu() ||
3183 3176               prev->result_opr()->as_register() != O0) &&
3184 3177              LIR_Assembler::is_single_instruction(prev)) {
3185 3178            // Only moves without info can be put into the delay slot.
3186 3179            // Also don't allow the setup of the receiver in the delay
3187 3180            // slot for vtable calls.
3188 3181            inst->at_put(i - 1, op);
3189 3182            inst->at_put(i, new LIR_OpDelay(prev, op->info()));
3190 3183  #ifndef PRODUCT
3191 3184            if (LIRTracePeephole) {
3192 3185              tty->print_cr("delayed");
3193 3186              inst->at(i - 1)->print();
3194 3187              inst->at(i)->print();
     3188 +            tty->cr();
3195 3189            }
3196 3190  #endif
3197 3191            continue;
3198 3192          }
3199 3193  
3200      -        if (!delay_op) {
3201      -          delay_op = new LIR_OpDelay(new LIR_Op0(lir_nop), op->as_OpJavaCall()->info());
3202      -          inst->insert_before(i + 1, delay_op);
3203      -        }
     3194 +        LIR_Op* delay_op = new LIR_OpDelay(new LIR_Op0(lir_nop), op->as_OpJavaCall()->info());
     3195 +        inst->insert_before(i + 1, delay_op);
3204 3196          break;
3205 3197        }
3206 3198      }
3207 3199    }
3208 3200  }
3209 3201  
3210 3202  
3211 3203  
3212 3204  
3213 3205  #undef __
    
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