1 /*
   2  * Copyright 2000-2010 Sun Microsystems, Inc.  All Rights Reserved.
   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
  20  * CA 95054 USA or visit www.sun.com if you need additional information or
  21  * have any questions.
  22  *
  23  */
  24 
  25 # include "incls/_precompiled.incl"
  26 # include "incls/_c1_LIRAssembler_x86.cpp.incl"
  27 
  28 
  29 // These masks are used to provide 128-bit aligned bitmasks to the XMM
  30 // instructions, to allow sign-masking or sign-bit flipping.  They allow
  31 // fast versions of NegF/NegD and AbsF/AbsD.
  32 
  33 // Note: 'double' and 'long long' have 32-bits alignment on x86.
  34 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) {
  35   // Use the expression (adr)&(~0xF) to provide 128-bits aligned address
  36   // of 128-bits operands for SSE instructions.
  37   jlong *operand = (jlong*)(((long)adr)&((long)(~0xF)));
  38   // Store the value to a 128-bits operand.
  39   operand[0] = lo;
  40   operand[1] = hi;
  41   return operand;
  42 }
  43 
  44 // Buffer for 128-bits masks used by SSE instructions.
  45 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment)
  46 
  47 // Static initialization during VM startup.
  48 static jlong *float_signmask_pool  = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF));
  49 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF));
  50 static jlong *float_signflip_pool  = double_quadword(&fp_signmask_pool[3*2], CONST64(0x8000000080000000), CONST64(0x8000000080000000));
  51 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], CONST64(0x8000000000000000), CONST64(0x8000000000000000));
  52 
  53 
  54 
  55 NEEDS_CLEANUP // remove this definitions ?
  56 const Register IC_Klass    = rax;   // where the IC klass is cached
  57 const Register SYNC_header = rax;   // synchronization header
  58 const Register SHIFT_count = rcx;   // where count for shift operations must be
  59 
  60 #define __ _masm->
  61 
  62 
  63 static void select_different_registers(Register preserve,
  64                                        Register extra,
  65                                        Register &tmp1,
  66                                        Register &tmp2) {
  67   if (tmp1 == preserve) {
  68     assert_different_registers(tmp1, tmp2, extra);
  69     tmp1 = extra;
  70   } else if (tmp2 == preserve) {
  71     assert_different_registers(tmp1, tmp2, extra);
  72     tmp2 = extra;
  73   }
  74   assert_different_registers(preserve, tmp1, tmp2);
  75 }
  76 
  77 
  78 
  79 static void select_different_registers(Register preserve,
  80                                        Register extra,
  81                                        Register &tmp1,
  82                                        Register &tmp2,
  83                                        Register &tmp3) {
  84   if (tmp1 == preserve) {
  85     assert_different_registers(tmp1, tmp2, tmp3, extra);
  86     tmp1 = extra;
  87   } else if (tmp2 == preserve) {
  88     assert_different_registers(tmp1, tmp2, tmp3, extra);
  89     tmp2 = extra;
  90   } else if (tmp3 == preserve) {
  91     assert_different_registers(tmp1, tmp2, tmp3, extra);
  92     tmp3 = extra;
  93   }
  94   assert_different_registers(preserve, tmp1, tmp2, tmp3);
  95 }
  96 
  97 
  98 
  99 bool LIR_Assembler::is_small_constant(LIR_Opr opr) {
 100   if (opr->is_constant()) {
 101     LIR_Const* constant = opr->as_constant_ptr();
 102     switch (constant->type()) {
 103       case T_INT: {
 104         return true;
 105       }
 106 
 107       default:
 108         return false;
 109     }
 110   }
 111   return false;
 112 }
 113 
 114 
 115 LIR_Opr LIR_Assembler::receiverOpr() {
 116   return FrameMap::receiver_opr;
 117 }
 118 
 119 LIR_Opr LIR_Assembler::incomingReceiverOpr() {
 120   return receiverOpr();
 121 }
 122 
 123 LIR_Opr LIR_Assembler::osrBufferPointer() {
 124   return FrameMap::as_pointer_opr(receiverOpr()->as_register());
 125 }
 126 
 127 //--------------fpu register translations-----------------------
 128 
 129 
 130 address LIR_Assembler::float_constant(float f) {
 131   address const_addr = __ float_constant(f);
 132   if (const_addr == NULL) {
 133     bailout("const section overflow");
 134     return __ code()->consts()->start();
 135   } else {
 136     return const_addr;
 137   }
 138 }
 139 
 140 
 141 address LIR_Assembler::double_constant(double d) {
 142   address const_addr = __ double_constant(d);
 143   if (const_addr == NULL) {
 144     bailout("const section overflow");
 145     return __ code()->consts()->start();
 146   } else {
 147     return const_addr;
 148   }
 149 }
 150 
 151 
 152 void LIR_Assembler::set_24bit_FPU() {
 153   __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
 154 }
 155 
 156 void LIR_Assembler::reset_FPU() {
 157   __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
 158 }
 159 
 160 void LIR_Assembler::fpop() {
 161   __ fpop();
 162 }
 163 
 164 void LIR_Assembler::fxch(int i) {
 165   __ fxch(i);
 166 }
 167 
 168 void LIR_Assembler::fld(int i) {
 169   __ fld_s(i);
 170 }
 171 
 172 void LIR_Assembler::ffree(int i) {
 173   __ ffree(i);
 174 }
 175 
 176 void LIR_Assembler::breakpoint() {
 177   __ int3();
 178 }
 179 
 180 void LIR_Assembler::push(LIR_Opr opr) {
 181   if (opr->is_single_cpu()) {
 182     __ push_reg(opr->as_register());
 183   } else if (opr->is_double_cpu()) {
 184     NOT_LP64(__ push_reg(opr->as_register_hi()));
 185     __ push_reg(opr->as_register_lo());
 186   } else if (opr->is_stack()) {
 187     __ push_addr(frame_map()->address_for_slot(opr->single_stack_ix()));
 188   } else if (opr->is_constant()) {
 189     LIR_Const* const_opr = opr->as_constant_ptr();
 190     if (const_opr->type() == T_OBJECT) {
 191       __ push_oop(const_opr->as_jobject());
 192     } else if (const_opr->type() == T_INT) {
 193       __ push_jint(const_opr->as_jint());
 194     } else {
 195       ShouldNotReachHere();
 196     }
 197 
 198   } else {
 199     ShouldNotReachHere();
 200   }
 201 }
 202 
 203 void LIR_Assembler::pop(LIR_Opr opr) {
 204   if (opr->is_single_cpu()) {
 205     __ pop_reg(opr->as_register());
 206   } else {
 207     ShouldNotReachHere();
 208   }
 209 }
 210 
 211 bool LIR_Assembler::is_literal_address(LIR_Address* addr) {
 212   return addr->base()->is_illegal() && addr->index()->is_illegal();
 213 }
 214 
 215 //-------------------------------------------
 216 
 217 Address LIR_Assembler::as_Address(LIR_Address* addr) {
 218   return as_Address(addr, rscratch1);
 219 }
 220 
 221 Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) {
 222   if (addr->base()->is_illegal()) {
 223     assert(addr->index()->is_illegal(), "must be illegal too");
 224     AddressLiteral laddr((address)addr->disp(), relocInfo::none);
 225     if (! __ reachable(laddr)) {
 226       __ movptr(tmp, laddr.addr());
 227       Address res(tmp, 0);
 228       return res;
 229     } else {
 230       return __ as_Address(laddr);
 231     }
 232   }
 233 
 234   Register base = addr->base()->as_pointer_register();
 235 
 236   if (addr->index()->is_illegal()) {
 237     return Address( base, addr->disp());
 238   } else if (addr->index()->is_cpu_register()) {
 239     Register index = addr->index()->as_pointer_register();
 240     return Address(base, index, (Address::ScaleFactor) addr->scale(), addr->disp());
 241   } else if (addr->index()->is_constant()) {
 242     intptr_t addr_offset = (addr->index()->as_constant_ptr()->as_jint() << addr->scale()) + addr->disp();
 243     assert(Assembler::is_simm32(addr_offset), "must be");
 244 
 245     return Address(base, addr_offset);
 246   } else {
 247     Unimplemented();
 248     return Address();
 249   }
 250 }
 251 
 252 
 253 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
 254   Address base = as_Address(addr);
 255   return Address(base._base, base._index, base._scale, base._disp + BytesPerWord);
 256 }
 257 
 258 
 259 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
 260   return as_Address(addr);
 261 }
 262 
 263 
 264 void LIR_Assembler::osr_entry() {
 265   offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
 266   BlockBegin* osr_entry = compilation()->hir()->osr_entry();
 267   ValueStack* entry_state = osr_entry->state();
 268   int number_of_locks = entry_state->locks_size();
 269 
 270   // we jump here if osr happens with the interpreter
 271   // state set up to continue at the beginning of the
 272   // loop that triggered osr - in particular, we have
 273   // the following registers setup:
 274   //
 275   // rcx: osr buffer
 276   //
 277 
 278   // build frame
 279   ciMethod* m = compilation()->method();
 280   __ build_frame(initial_frame_size_in_bytes());
 281 
 282   // OSR buffer is
 283   //
 284   // locals[nlocals-1..0]
 285   // monitors[0..number_of_locks]
 286   //
 287   // locals is a direct copy of the interpreter frame so in the osr buffer
 288   // so first slot in the local array is the last local from the interpreter
 289   // and last slot is local[0] (receiver) from the interpreter
 290   //
 291   // Similarly with locks. The first lock slot in the osr buffer is the nth lock
 292   // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
 293   // in the interpreter frame (the method lock if a sync method)
 294 
 295   // Initialize monitors in the compiled activation.
 296   //   rcx: pointer to osr buffer
 297   //
 298   // All other registers are dead at this point and the locals will be
 299   // copied into place by code emitted in the IR.
 300 
 301   Register OSR_buf = osrBufferPointer()->as_pointer_register();
 302   { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
 303     int monitor_offset = BytesPerWord * method()->max_locals() +
 304       (2 * BytesPerWord) * (number_of_locks - 1);
 305     // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
 306     // the OSR buffer using 2 word entries: first the lock and then
 307     // the oop.
 308     for (int i = 0; i < number_of_locks; i++) {
 309       int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
 310 #ifdef ASSERT
 311       // verify the interpreter's monitor has a non-null object
 312       {
 313         Label L;
 314         __ cmpptr(Address(OSR_buf, slot_offset + 1*BytesPerWord), (int32_t)NULL_WORD);
 315         __ jcc(Assembler::notZero, L);
 316         __ stop("locked object is NULL");
 317         __ bind(L);
 318       }
 319 #endif
 320       __ movptr(rbx, Address(OSR_buf, slot_offset + 0));
 321       __ movptr(frame_map()->address_for_monitor_lock(i), rbx);
 322       __ movptr(rbx, Address(OSR_buf, slot_offset + 1*BytesPerWord));
 323       __ movptr(frame_map()->address_for_monitor_object(i), rbx);
 324     }
 325   }
 326 }
 327 
 328 
 329 // inline cache check; done before the frame is built.
 330 int LIR_Assembler::check_icache() {
 331   Register receiver = FrameMap::receiver_opr->as_register();
 332   Register ic_klass = IC_Klass;
 333   const int ic_cmp_size = LP64_ONLY(10) NOT_LP64(9);
 334 
 335   if (!VerifyOops) {
 336     // insert some nops so that the verified entry point is aligned on CodeEntryAlignment
 337     while ((__ offset() + ic_cmp_size) % CodeEntryAlignment != 0) {
 338       __ nop();
 339     }
 340   }
 341   int offset = __ offset();
 342   __ inline_cache_check(receiver, IC_Klass);
 343   assert(__ offset() % CodeEntryAlignment == 0 || VerifyOops, "alignment must be correct");
 344   if (VerifyOops) {
 345     // force alignment after the cache check.
 346     // It's been verified to be aligned if !VerifyOops
 347     __ align(CodeEntryAlignment);
 348   }
 349   return offset;
 350 }
 351 
 352 
 353 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo* info) {
 354   jobject o = NULL;
 355   PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id);
 356   __ movoop(reg, o);
 357   patching_epilog(patch, lir_patch_normal, reg, info);
 358 }
 359 
 360 
 361 void LIR_Assembler::monitorexit(LIR_Opr obj_opr, LIR_Opr lock_opr, Register new_hdr, int monitor_no, Register exception) {
 362   if (exception->is_valid()) {
 363     // preserve exception
 364     // note: the monitor_exit runtime call is a leaf routine
 365     //       and cannot block => no GC can happen
 366     // The slow case (MonitorAccessStub) uses the first two stack slots
 367     // ([esp+0] and [esp+4]), therefore we store the exception at [esp+8]
 368     __ movptr (Address(rsp, 2*wordSize), exception);
 369   }
 370 
 371   Register obj_reg  = obj_opr->as_register();
 372   Register lock_reg = lock_opr->as_register();
 373 
 374   // setup registers (lock_reg must be rax, for lock_object)
 375   assert(obj_reg != SYNC_header && lock_reg != SYNC_header, "rax, must be available here");
 376   Register hdr = lock_reg;
 377   assert(new_hdr == SYNC_header, "wrong register");
 378   lock_reg = new_hdr;
 379   // compute pointer to BasicLock
 380   Address lock_addr = frame_map()->address_for_monitor_lock(monitor_no);
 381   __ lea(lock_reg, lock_addr);
 382   // unlock object
 383   MonitorAccessStub* slow_case = new MonitorExitStub(lock_opr, true, monitor_no);
 384   // _slow_case_stubs->append(slow_case);
 385   // temporary fix: must be created after exceptionhandler, therefore as call stub
 386   _slow_case_stubs->append(slow_case);
 387   if (UseFastLocking) {
 388     // try inlined fast unlocking first, revert to slow locking if it fails
 389     // note: lock_reg points to the displaced header since the displaced header offset is 0!
 390     assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
 391     __ unlock_object(hdr, obj_reg, lock_reg, *slow_case->entry());
 392   } else {
 393     // always do slow unlocking
 394     // note: the slow unlocking code could be inlined here, however if we use
 395     //       slow unlocking, speed doesn't matter anyway and this solution is
 396     //       simpler and requires less duplicated code - additionally, the
 397     //       slow unlocking code is the same in either case which simplifies
 398     //       debugging
 399     __ jmp(*slow_case->entry());
 400   }
 401   // done
 402   __ bind(*slow_case->continuation());
 403 
 404   if (exception->is_valid()) {
 405     // restore exception
 406     __ movptr (exception, Address(rsp, 2 * wordSize));
 407   }
 408 }
 409 
 410 // This specifies the rsp decrement needed to build the frame
 411 int LIR_Assembler::initial_frame_size_in_bytes() {
 412   // if rounding, must let FrameMap know!
 413 
 414   // The frame_map records size in slots (32bit word)
 415 
 416   // subtract two words to account for return address and link
 417   return (frame_map()->framesize() - (2*VMRegImpl::slots_per_word))  * VMRegImpl::stack_slot_size;
 418 }
 419 
 420 
 421 int LIR_Assembler::emit_exception_handler() {
 422   // if the last instruction is a call (typically to do a throw which
 423   // is coming at the end after block reordering) the return address
 424   // must still point into the code area in order to avoid assertion
 425   // failures when searching for the corresponding bci => add a nop
 426   // (was bug 5/14/1999 - gri)
 427   __ nop();
 428 
 429   // generate code for exception handler
 430   address handler_base = __ start_a_stub(exception_handler_size);
 431   if (handler_base == NULL) {
 432     // not enough space left for the handler
 433     bailout("exception handler overflow");
 434     return -1;
 435   }
 436 
 437   int offset = code_offset();
 438 
 439   // the exception oop and pc are in rax, and rdx
 440   // no other registers need to be preserved, so invalidate them
 441   __ invalidate_registers(false, true, true, false, true, true);
 442 
 443   // check that there is really an exception
 444   __ verify_not_null_oop(rax);
 445 
 446   // search an exception handler (rax: exception oop, rdx: throwing pc)
 447   __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::handle_exception_nofpu_id)));
 448 
 449   __ stop("should not reach here");
 450 
 451   assert(code_offset() - offset <= exception_handler_size, "overflow");
 452   __ end_a_stub();
 453 
 454   return offset;
 455 }
 456 
 457 
 458 // Emit the code to remove the frame from the stack in the exception
 459 // unwind path.
 460 int LIR_Assembler::emit_unwind_handler() {
 461 #ifndef PRODUCT
 462   if (CommentedAssembly) {
 463     _masm->block_comment("Unwind handler");
 464   }
 465 #endif
 466 
 467   int offset = code_offset();
 468 
 469   // Fetch the exception from TLS and clear out exception related thread state
 470   __ get_thread(rsi);
 471   __ movptr(rax, Address(rsi, JavaThread::exception_oop_offset()));
 472   __ movptr(Address(rsi, JavaThread::exception_oop_offset()), (int32_t)NULL_WORD);
 473   __ movptr(Address(rsi, JavaThread::exception_pc_offset()), (int32_t)NULL_WORD);
 474 
 475   __ bind(_unwind_handler_entry);
 476   __ verify_not_null_oop(rax);
 477   if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
 478     __ mov(rsi, rax);  // Preserve the exception
 479   }
 480 
 481   // Preform needed unlocking
 482   MonitorExitStub* stub = NULL;
 483   if (method()->is_synchronized()) {
 484     monitor_address(0, FrameMap::rax_opr);
 485     stub = new MonitorExitStub(FrameMap::rax_opr, true, 0);
 486     __ unlock_object(rdi, rbx, rax, *stub->entry());
 487     __ bind(*stub->continuation());
 488   }
 489 
 490   if (compilation()->env()->dtrace_method_probes()) {
 491     __ movoop(Address(rsp, 0), method()->constant_encoding());
 492     __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit)));
 493   }
 494 
 495   if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
 496     __ mov(rax, rsi);  // Restore the exception
 497   }
 498 
 499   // remove the activation and dispatch to the unwind handler
 500   __ remove_frame(initial_frame_size_in_bytes());
 501   __ jump(RuntimeAddress(Runtime1::entry_for(Runtime1::unwind_exception_id)));
 502 
 503   // Emit the slow path assembly
 504   if (stub != NULL) {
 505     stub->emit_code(this);
 506   }
 507 
 508   return offset;
 509 }
 510 
 511 
 512 int LIR_Assembler::emit_deopt_handler() {
 513   // if the last instruction is a call (typically to do a throw which
 514   // is coming at the end after block reordering) the return address
 515   // must still point into the code area in order to avoid assertion
 516   // failures when searching for the corresponding bci => add a nop
 517   // (was bug 5/14/1999 - gri)
 518   __ nop();
 519 
 520   // generate code for exception handler
 521   address handler_base = __ start_a_stub(deopt_handler_size);
 522   if (handler_base == NULL) {
 523     // not enough space left for the handler
 524     bailout("deopt handler overflow");
 525     return -1;
 526   }
 527 
 528   int offset = code_offset();
 529   InternalAddress here(__ pc());
 530 
 531   __ pushptr(here.addr());
 532   __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
 533 
 534   assert(code_offset() - offset <= deopt_handler_size, "overflow");
 535   __ end_a_stub();
 536 
 537   return offset;
 538 }
 539 
 540 
 541 // This is the fast version of java.lang.String.compare; it has not
 542 // OSR-entry and therefore, we generate a slow version for OSR's
 543 void LIR_Assembler::emit_string_compare(LIR_Opr arg0, LIR_Opr arg1, LIR_Opr dst, CodeEmitInfo* info) {
 544   __ movptr (rbx, rcx); // receiver is in rcx
 545   __ movptr (rax, arg1->as_register());
 546 
 547   // Get addresses of first characters from both Strings
 548   __ movptr (rsi, Address(rax, java_lang_String::value_offset_in_bytes()));
 549   __ movptr (rcx, Address(rax, java_lang_String::offset_offset_in_bytes()));
 550   __ lea    (rsi, Address(rsi, rcx, Address::times_2, arrayOopDesc::base_offset_in_bytes(T_CHAR)));
 551 
 552 
 553   // rbx, may be NULL
 554   add_debug_info_for_null_check_here(info);
 555   __ movptr (rdi, Address(rbx, java_lang_String::value_offset_in_bytes()));
 556   __ movptr (rcx, Address(rbx, java_lang_String::offset_offset_in_bytes()));
 557   __ lea    (rdi, Address(rdi, rcx, Address::times_2, arrayOopDesc::base_offset_in_bytes(T_CHAR)));
 558 
 559   // compute minimum length (in rax) and difference of lengths (on top of stack)
 560   if (VM_Version::supports_cmov()) {
 561     __ movl     (rbx, Address(rbx, java_lang_String::count_offset_in_bytes()));
 562     __ movl     (rax, Address(rax, java_lang_String::count_offset_in_bytes()));
 563     __ mov      (rcx, rbx);
 564     __ subptr   (rbx, rax); // subtract lengths
 565     __ push     (rbx);      // result
 566     __ cmov     (Assembler::lessEqual, rax, rcx);
 567   } else {
 568     Label L;
 569     __ movl     (rbx, Address(rbx, java_lang_String::count_offset_in_bytes()));
 570     __ movl     (rcx, Address(rax, java_lang_String::count_offset_in_bytes()));
 571     __ mov      (rax, rbx);
 572     __ subptr   (rbx, rcx);
 573     __ push     (rbx);
 574     __ jcc      (Assembler::lessEqual, L);
 575     __ mov      (rax, rcx);
 576     __ bind (L);
 577   }
 578   // is minimum length 0?
 579   Label noLoop, haveResult;
 580   __ testptr (rax, rax);
 581   __ jcc (Assembler::zero, noLoop);
 582 
 583   // compare first characters
 584   __ load_unsigned_short(rcx, Address(rdi, 0));
 585   __ load_unsigned_short(rbx, Address(rsi, 0));
 586   __ subl(rcx, rbx);
 587   __ jcc(Assembler::notZero, haveResult);
 588   // starting loop
 589   __ decrement(rax); // we already tested index: skip one
 590   __ jcc(Assembler::zero, noLoop);
 591 
 592   // set rsi.edi to the end of the arrays (arrays have same length)
 593   // negate the index
 594 
 595   __ lea(rsi, Address(rsi, rax, Address::times_2, type2aelembytes(T_CHAR)));
 596   __ lea(rdi, Address(rdi, rax, Address::times_2, type2aelembytes(T_CHAR)));
 597   __ negptr(rax);
 598 
 599   // compare the strings in a loop
 600 
 601   Label loop;
 602   __ align(wordSize);
 603   __ bind(loop);
 604   __ load_unsigned_short(rcx, Address(rdi, rax, Address::times_2, 0));
 605   __ load_unsigned_short(rbx, Address(rsi, rax, Address::times_2, 0));
 606   __ subl(rcx, rbx);
 607   __ jcc(Assembler::notZero, haveResult);
 608   __ increment(rax);
 609   __ jcc(Assembler::notZero, loop);
 610 
 611   // strings are equal up to min length
 612 
 613   __ bind(noLoop);
 614   __ pop(rax);
 615   return_op(LIR_OprFact::illegalOpr);
 616 
 617   __ bind(haveResult);
 618   // leave instruction is going to discard the TOS value
 619   __ mov (rax, rcx); // result of call is in rax,
 620 }
 621 
 622 
 623 void LIR_Assembler::return_op(LIR_Opr result) {
 624   assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == rax, "word returns are in rax,");
 625   if (!result->is_illegal() && result->is_float_kind() && !result->is_xmm_register()) {
 626     assert(result->fpu() == 0, "result must already be on TOS");
 627   }
 628 
 629   // Pop the stack before the safepoint code
 630   __ remove_frame(initial_frame_size_in_bytes());
 631 
 632   bool result_is_oop = result->is_valid() ? result->is_oop() : false;
 633 
 634   // Note: we do not need to round double result; float result has the right precision
 635   // the poll sets the condition code, but no data registers
 636   AddressLiteral polling_page(os::get_polling_page() + (SafepointPollOffset % os::vm_page_size()),
 637                               relocInfo::poll_return_type);
 638 
 639   // NOTE: the requires that the polling page be reachable else the reloc
 640   // goes to the movq that loads the address and not the faulting instruction
 641   // which breaks the signal handler code
 642 
 643   __ test32(rax, polling_page);
 644 
 645   __ ret(0);
 646 }
 647 
 648 
 649 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
 650   AddressLiteral polling_page(os::get_polling_page() + (SafepointPollOffset % os::vm_page_size()),
 651                               relocInfo::poll_type);
 652 
 653   if (info != NULL) {
 654     add_debug_info_for_branch(info);
 655   } else {
 656     ShouldNotReachHere();
 657   }
 658 
 659   int offset = __ offset();
 660 
 661   // NOTE: the requires that the polling page be reachable else the reloc
 662   // goes to the movq that loads the address and not the faulting instruction
 663   // which breaks the signal handler code
 664 
 665   __ test32(rax, polling_page);
 666   return offset;
 667 }
 668 
 669 
 670 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) {
 671   if (from_reg != to_reg) __ mov(to_reg, from_reg);
 672 }
 673 
 674 void LIR_Assembler::swap_reg(Register a, Register b) {
 675   __ xchgptr(a, b);
 676 }
 677 
 678 
 679 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
 680   assert(src->is_constant(), "should not call otherwise");
 681   assert(dest->is_register(), "should not call otherwise");
 682   LIR_Const* c = src->as_constant_ptr();
 683 
 684   switch (c->type()) {
 685     case T_INT:
 686     case T_ADDRESS: {
 687       assert(patch_code == lir_patch_none, "no patching handled here");
 688       __ movl(dest->as_register(), c->as_jint());
 689       break;
 690     }
 691 
 692     case T_LONG: {
 693       assert(patch_code == lir_patch_none, "no patching handled here");
 694 #ifdef _LP64
 695       __ movptr(dest->as_register_lo(), (intptr_t)c->as_jlong());
 696 #else
 697       __ movptr(dest->as_register_lo(), c->as_jint_lo());
 698       __ movptr(dest->as_register_hi(), c->as_jint_hi());
 699 #endif // _LP64
 700       break;
 701     }
 702 
 703     case T_OBJECT: {
 704       if (patch_code != lir_patch_none) {
 705         jobject2reg_with_patching(dest->as_register(), info);
 706       } else {
 707         __ movoop(dest->as_register(), c->as_jobject());
 708       }
 709       break;
 710     }
 711 
 712     case T_FLOAT: {
 713       if (dest->is_single_xmm()) {
 714         if (c->is_zero_float()) {
 715           __ xorps(dest->as_xmm_float_reg(), dest->as_xmm_float_reg());
 716         } else {
 717           __ movflt(dest->as_xmm_float_reg(),
 718                    InternalAddress(float_constant(c->as_jfloat())));
 719         }
 720       } else {
 721         assert(dest->is_single_fpu(), "must be");
 722         assert(dest->fpu_regnr() == 0, "dest must be TOS");
 723         if (c->is_zero_float()) {
 724           __ fldz();
 725         } else if (c->is_one_float()) {
 726           __ fld1();
 727         } else {
 728           __ fld_s (InternalAddress(float_constant(c->as_jfloat())));
 729         }
 730       }
 731       break;
 732     }
 733 
 734     case T_DOUBLE: {
 735       if (dest->is_double_xmm()) {
 736         if (c->is_zero_double()) {
 737           __ xorpd(dest->as_xmm_double_reg(), dest->as_xmm_double_reg());
 738         } else {
 739           __ movdbl(dest->as_xmm_double_reg(),
 740                     InternalAddress(double_constant(c->as_jdouble())));
 741         }
 742       } else {
 743         assert(dest->is_double_fpu(), "must be");
 744         assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
 745         if (c->is_zero_double()) {
 746           __ fldz();
 747         } else if (c->is_one_double()) {
 748           __ fld1();
 749         } else {
 750           __ fld_d (InternalAddress(double_constant(c->as_jdouble())));
 751         }
 752       }
 753       break;
 754     }
 755 
 756     default:
 757       ShouldNotReachHere();
 758   }
 759 }
 760 
 761 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
 762   assert(src->is_constant(), "should not call otherwise");
 763   assert(dest->is_stack(), "should not call otherwise");
 764   LIR_Const* c = src->as_constant_ptr();
 765 
 766   switch (c->type()) {
 767     case T_INT:  // fall through
 768     case T_FLOAT:
 769     case T_ADDRESS:
 770       __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits());
 771       break;
 772 
 773     case T_OBJECT:
 774       __ movoop(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jobject());
 775       break;
 776 
 777     case T_LONG:  // fall through
 778     case T_DOUBLE:
 779 #ifdef _LP64
 780       __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
 781                                             lo_word_offset_in_bytes), (intptr_t)c->as_jlong_bits());
 782 #else
 783       __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
 784                                               lo_word_offset_in_bytes), c->as_jint_lo_bits());
 785       __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
 786                                               hi_word_offset_in_bytes), c->as_jint_hi_bits());
 787 #endif // _LP64
 788       break;
 789 
 790     default:
 791       ShouldNotReachHere();
 792   }
 793 }
 794 
 795 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info ) {
 796   assert(src->is_constant(), "should not call otherwise");
 797   assert(dest->is_address(), "should not call otherwise");
 798   LIR_Const* c = src->as_constant_ptr();
 799   LIR_Address* addr = dest->as_address_ptr();
 800 
 801   int null_check_here = code_offset();
 802   switch (type) {
 803     case T_INT:    // fall through
 804     case T_FLOAT:
 805     case T_ADDRESS:
 806       __ movl(as_Address(addr), c->as_jint_bits());
 807       break;
 808 
 809     case T_OBJECT:  // fall through
 810     case T_ARRAY:
 811       if (c->as_jobject() == NULL) {
 812         __ movptr(as_Address(addr), NULL_WORD);
 813       } else {
 814         if (is_literal_address(addr)) {
 815           ShouldNotReachHere();
 816           __ movoop(as_Address(addr, noreg), c->as_jobject());
 817         } else {
 818 #ifdef _LP64
 819           __ movoop(rscratch1, c->as_jobject());
 820           null_check_here = code_offset();
 821           __ movptr(as_Address_lo(addr), rscratch1);
 822 #else
 823           __ movoop(as_Address(addr), c->as_jobject());
 824 #endif
 825         }
 826       }
 827       break;
 828 
 829     case T_LONG:    // fall through
 830     case T_DOUBLE:
 831 #ifdef _LP64
 832       if (is_literal_address(addr)) {
 833         ShouldNotReachHere();
 834         __ movptr(as_Address(addr, r15_thread), (intptr_t)c->as_jlong_bits());
 835       } else {
 836         __ movptr(r10, (intptr_t)c->as_jlong_bits());
 837         null_check_here = code_offset();
 838         __ movptr(as_Address_lo(addr), r10);
 839       }
 840 #else
 841       // Always reachable in 32bit so this doesn't produce useless move literal
 842       __ movptr(as_Address_hi(addr), c->as_jint_hi_bits());
 843       __ movptr(as_Address_lo(addr), c->as_jint_lo_bits());
 844 #endif // _LP64
 845       break;
 846 
 847     case T_BOOLEAN: // fall through
 848     case T_BYTE:
 849       __ movb(as_Address(addr), c->as_jint() & 0xFF);
 850       break;
 851 
 852     case T_CHAR:    // fall through
 853     case T_SHORT:
 854       __ movw(as_Address(addr), c->as_jint() & 0xFFFF);
 855       break;
 856 
 857     default:
 858       ShouldNotReachHere();
 859   };
 860 
 861   if (info != NULL) {
 862     add_debug_info_for_null_check(null_check_here, info);
 863   }
 864 }
 865 
 866 
 867 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) {
 868   assert(src->is_register(), "should not call otherwise");
 869   assert(dest->is_register(), "should not call otherwise");
 870 
 871   // move between cpu-registers
 872   if (dest->is_single_cpu()) {
 873 #ifdef _LP64
 874     if (src->type() == T_LONG) {
 875       // Can do LONG -> OBJECT
 876       move_regs(src->as_register_lo(), dest->as_register());
 877       return;
 878     }
 879 #endif
 880     assert(src->is_single_cpu(), "must match");
 881     if (src->type() == T_OBJECT) {
 882       __ verify_oop(src->as_register());
 883     }
 884     move_regs(src->as_register(), dest->as_register());
 885 
 886   } else if (dest->is_double_cpu()) {
 887 #ifdef _LP64
 888     if (src->type() == T_OBJECT || src->type() == T_ARRAY) {
 889       // Surprising to me but we can see move of a long to t_object
 890       __ verify_oop(src->as_register());
 891       move_regs(src->as_register(), dest->as_register_lo());
 892       return;
 893     }
 894 #endif
 895     assert(src->is_double_cpu(), "must match");
 896     Register f_lo = src->as_register_lo();
 897     Register f_hi = src->as_register_hi();
 898     Register t_lo = dest->as_register_lo();
 899     Register t_hi = dest->as_register_hi();
 900 #ifdef _LP64
 901     assert(f_hi == f_lo, "must be same");
 902     assert(t_hi == t_lo, "must be same");
 903     move_regs(f_lo, t_lo);
 904 #else
 905     assert(f_lo != f_hi && t_lo != t_hi, "invalid register allocation");
 906 
 907 
 908     if (f_lo == t_hi && f_hi == t_lo) {
 909       swap_reg(f_lo, f_hi);
 910     } else if (f_hi == t_lo) {
 911       assert(f_lo != t_hi, "overwriting register");
 912       move_regs(f_hi, t_hi);
 913       move_regs(f_lo, t_lo);
 914     } else {
 915       assert(f_hi != t_lo, "overwriting register");
 916       move_regs(f_lo, t_lo);
 917       move_regs(f_hi, t_hi);
 918     }
 919 #endif // LP64
 920 
 921     // special moves from fpu-register to xmm-register
 922     // necessary for method results
 923   } else if (src->is_single_xmm() && !dest->is_single_xmm()) {
 924     __ movflt(Address(rsp, 0), src->as_xmm_float_reg());
 925     __ fld_s(Address(rsp, 0));
 926   } else if (src->is_double_xmm() && !dest->is_double_xmm()) {
 927     __ movdbl(Address(rsp, 0), src->as_xmm_double_reg());
 928     __ fld_d(Address(rsp, 0));
 929   } else if (dest->is_single_xmm() && !src->is_single_xmm()) {
 930     __ fstp_s(Address(rsp, 0));
 931     __ movflt(dest->as_xmm_float_reg(), Address(rsp, 0));
 932   } else if (dest->is_double_xmm() && !src->is_double_xmm()) {
 933     __ fstp_d(Address(rsp, 0));
 934     __ movdbl(dest->as_xmm_double_reg(), Address(rsp, 0));
 935 
 936     // move between xmm-registers
 937   } else if (dest->is_single_xmm()) {
 938     assert(src->is_single_xmm(), "must match");
 939     __ movflt(dest->as_xmm_float_reg(), src->as_xmm_float_reg());
 940   } else if (dest->is_double_xmm()) {
 941     assert(src->is_double_xmm(), "must match");
 942     __ movdbl(dest->as_xmm_double_reg(), src->as_xmm_double_reg());
 943 
 944     // move between fpu-registers (no instruction necessary because of fpu-stack)
 945   } else if (dest->is_single_fpu() || dest->is_double_fpu()) {
 946     assert(src->is_single_fpu() || src->is_double_fpu(), "must match");
 947     assert(src->fpu() == dest->fpu(), "currently should be nothing to do");
 948   } else {
 949     ShouldNotReachHere();
 950   }
 951 }
 952 
 953 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) {
 954   assert(src->is_register(), "should not call otherwise");
 955   assert(dest->is_stack(), "should not call otherwise");
 956 
 957   if (src->is_single_cpu()) {
 958     Address dst = frame_map()->address_for_slot(dest->single_stack_ix());
 959     if (type == T_OBJECT || type == T_ARRAY) {
 960       __ verify_oop(src->as_register());
 961       __ movptr (dst, src->as_register());
 962     } else {
 963       __ movl (dst, src->as_register());
 964     }
 965 
 966   } else if (src->is_double_cpu()) {
 967     Address dstLO = frame_map()->address_for_slot(dest->double_stack_ix(), lo_word_offset_in_bytes);
 968     Address dstHI = frame_map()->address_for_slot(dest->double_stack_ix(), hi_word_offset_in_bytes);
 969     __ movptr (dstLO, src->as_register_lo());
 970     NOT_LP64(__ movptr (dstHI, src->as_register_hi()));
 971 
 972   } else if (src->is_single_xmm()) {
 973     Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix());
 974     __ movflt(dst_addr, src->as_xmm_float_reg());
 975 
 976   } else if (src->is_double_xmm()) {
 977     Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix());
 978     __ movdbl(dst_addr, src->as_xmm_double_reg());
 979 
 980   } else if (src->is_single_fpu()) {
 981     assert(src->fpu_regnr() == 0, "argument must be on TOS");
 982     Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix());
 983     if (pop_fpu_stack)     __ fstp_s (dst_addr);
 984     else                   __ fst_s  (dst_addr);
 985 
 986   } else if (src->is_double_fpu()) {
 987     assert(src->fpu_regnrLo() == 0, "argument must be on TOS");
 988     Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix());
 989     if (pop_fpu_stack)     __ fstp_d (dst_addr);
 990     else                   __ fst_d  (dst_addr);
 991 
 992   } else {
 993     ShouldNotReachHere();
 994   }
 995 }
 996 
 997 
 998 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool /* unaligned */) {
 999   LIR_Address* to_addr = dest->as_address_ptr();
1000   PatchingStub* patch = NULL;
1001 
1002   if (type == T_ARRAY || type == T_OBJECT) {
1003     __ verify_oop(src->as_register());
1004   }
1005   if (patch_code != lir_patch_none) {
1006     patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1007     Address toa = as_Address(to_addr);
1008     assert(toa.disp() != 0, "must have");
1009   }
1010   if (info != NULL) {
1011     add_debug_info_for_null_check_here(info);
1012   }
1013 
1014   switch (type) {
1015     case T_FLOAT: {
1016       if (src->is_single_xmm()) {
1017         __ movflt(as_Address(to_addr), src->as_xmm_float_reg());
1018       } else {
1019         assert(src->is_single_fpu(), "must be");
1020         assert(src->fpu_regnr() == 0, "argument must be on TOS");
1021         if (pop_fpu_stack)      __ fstp_s(as_Address(to_addr));
1022         else                    __ fst_s (as_Address(to_addr));
1023       }
1024       break;
1025     }
1026 
1027     case T_DOUBLE: {
1028       if (src->is_double_xmm()) {
1029         __ movdbl(as_Address(to_addr), src->as_xmm_double_reg());
1030       } else {
1031         assert(src->is_double_fpu(), "must be");
1032         assert(src->fpu_regnrLo() == 0, "argument must be on TOS");
1033         if (pop_fpu_stack)      __ fstp_d(as_Address(to_addr));
1034         else                    __ fst_d (as_Address(to_addr));
1035       }
1036       break;
1037     }
1038 
1039     case T_ADDRESS: // fall through
1040     case T_ARRAY:   // fall through
1041     case T_OBJECT:  // fall through
1042 #ifdef _LP64
1043       __ movptr(as_Address(to_addr), src->as_register());
1044       break;
1045 #endif // _LP64
1046     case T_INT:
1047       __ movl(as_Address(to_addr), src->as_register());
1048       break;
1049 
1050     case T_LONG: {
1051       Register from_lo = src->as_register_lo();
1052       Register from_hi = src->as_register_hi();
1053 #ifdef _LP64
1054       __ movptr(as_Address_lo(to_addr), from_lo);
1055 #else
1056       Register base = to_addr->base()->as_register();
1057       Register index = noreg;
1058       if (to_addr->index()->is_register()) {
1059         index = to_addr->index()->as_register();
1060       }
1061       if (base == from_lo || index == from_lo) {
1062         assert(base != from_hi, "can't be");
1063         assert(index == noreg || (index != base && index != from_hi), "can't handle this");
1064         __ movl(as_Address_hi(to_addr), from_hi);
1065         if (patch != NULL) {
1066           patching_epilog(patch, lir_patch_high, base, info);
1067           patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1068           patch_code = lir_patch_low;
1069         }
1070         __ movl(as_Address_lo(to_addr), from_lo);
1071       } else {
1072         assert(index == noreg || (index != base && index != from_lo), "can't handle this");
1073         __ movl(as_Address_lo(to_addr), from_lo);
1074         if (patch != NULL) {
1075           patching_epilog(patch, lir_patch_low, base, info);
1076           patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1077           patch_code = lir_patch_high;
1078         }
1079         __ movl(as_Address_hi(to_addr), from_hi);
1080       }
1081 #endif // _LP64
1082       break;
1083     }
1084 
1085     case T_BYTE:    // fall through
1086     case T_BOOLEAN: {
1087       Register src_reg = src->as_register();
1088       Address dst_addr = as_Address(to_addr);
1089       assert(VM_Version::is_P6() || src_reg->has_byte_register(), "must use byte registers if not P6");
1090       __ movb(dst_addr, src_reg);
1091       break;
1092     }
1093 
1094     case T_CHAR:    // fall through
1095     case T_SHORT:
1096       __ movw(as_Address(to_addr), src->as_register());
1097       break;
1098 
1099     default:
1100       ShouldNotReachHere();
1101   }
1102 
1103   if (patch_code != lir_patch_none) {
1104     patching_epilog(patch, patch_code, to_addr->base()->as_register(), info);
1105   }
1106 }
1107 
1108 
1109 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
1110   assert(src->is_stack(), "should not call otherwise");
1111   assert(dest->is_register(), "should not call otherwise");
1112 
1113   if (dest->is_single_cpu()) {
1114     if (type == T_ARRAY || type == T_OBJECT) {
1115       __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1116       __ verify_oop(dest->as_register());
1117     } else {
1118       __ movl(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1119     }
1120 
1121   } else if (dest->is_double_cpu()) {
1122     Address src_addr_LO = frame_map()->address_for_slot(src->double_stack_ix(), lo_word_offset_in_bytes);
1123     Address src_addr_HI = frame_map()->address_for_slot(src->double_stack_ix(), hi_word_offset_in_bytes);
1124     __ movptr(dest->as_register_lo(), src_addr_LO);
1125     NOT_LP64(__ movptr(dest->as_register_hi(), src_addr_HI));
1126 
1127   } else if (dest->is_single_xmm()) {
1128     Address src_addr = frame_map()->address_for_slot(src->single_stack_ix());
1129     __ movflt(dest->as_xmm_float_reg(), src_addr);
1130 
1131   } else if (dest->is_double_xmm()) {
1132     Address src_addr = frame_map()->address_for_slot(src->double_stack_ix());
1133     __ movdbl(dest->as_xmm_double_reg(), src_addr);
1134 
1135   } else if (dest->is_single_fpu()) {
1136     assert(dest->fpu_regnr() == 0, "dest must be TOS");
1137     Address src_addr = frame_map()->address_for_slot(src->single_stack_ix());
1138     __ fld_s(src_addr);
1139 
1140   } else if (dest->is_double_fpu()) {
1141     assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
1142     Address src_addr = frame_map()->address_for_slot(src->double_stack_ix());
1143     __ fld_d(src_addr);
1144 
1145   } else {
1146     ShouldNotReachHere();
1147   }
1148 }
1149 
1150 
1151 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
1152   if (src->is_single_stack()) {
1153     if (type == T_OBJECT || type == T_ARRAY) {
1154       __ pushptr(frame_map()->address_for_slot(src ->single_stack_ix()));
1155       __ popptr (frame_map()->address_for_slot(dest->single_stack_ix()));
1156     } else {
1157 #ifndef _LP64
1158       __ pushl(frame_map()->address_for_slot(src ->single_stack_ix()));
1159       __ popl (frame_map()->address_for_slot(dest->single_stack_ix()));
1160 #else
1161       //no pushl on 64bits
1162       __ movl(rscratch1, frame_map()->address_for_slot(src ->single_stack_ix()));
1163       __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), rscratch1);
1164 #endif
1165     }
1166 
1167   } else if (src->is_double_stack()) {
1168 #ifdef _LP64
1169     __ pushptr(frame_map()->address_for_slot(src ->double_stack_ix()));
1170     __ popptr (frame_map()->address_for_slot(dest->double_stack_ix()));
1171 #else
1172     __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 0));
1173     // push and pop the part at src + wordSize, adding wordSize for the previous push
1174     __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 2 * wordSize));
1175     __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 2 * wordSize));
1176     __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 0));
1177 #endif // _LP64
1178 
1179   } else {
1180     ShouldNotReachHere();
1181   }
1182 }
1183 
1184 
1185 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool /* unaligned */) {
1186   assert(src->is_address(), "should not call otherwise");
1187   assert(dest->is_register(), "should not call otherwise");
1188 
1189   LIR_Address* addr = src->as_address_ptr();
1190   Address from_addr = as_Address(addr);
1191 
1192   switch (type) {
1193     case T_BOOLEAN: // fall through
1194     case T_BYTE:    // fall through
1195     case T_CHAR:    // fall through
1196     case T_SHORT:
1197       if (!VM_Version::is_P6() && !from_addr.uses(dest->as_register())) {
1198         // on pre P6 processors we may get partial register stalls
1199         // so blow away the value of to_rinfo before loading a
1200         // partial word into it.  Do it here so that it precedes
1201         // the potential patch point below.
1202         __ xorptr(dest->as_register(), dest->as_register());
1203       }
1204       break;
1205   }
1206 
1207   PatchingStub* patch = NULL;
1208   if (patch_code != lir_patch_none) {
1209     patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1210     assert(from_addr.disp() != 0, "must have");
1211   }
1212   if (info != NULL) {
1213     add_debug_info_for_null_check_here(info);
1214   }
1215 
1216   switch (type) {
1217     case T_FLOAT: {
1218       if (dest->is_single_xmm()) {
1219         __ movflt(dest->as_xmm_float_reg(), from_addr);
1220       } else {
1221         assert(dest->is_single_fpu(), "must be");
1222         assert(dest->fpu_regnr() == 0, "dest must be TOS");
1223         __ fld_s(from_addr);
1224       }
1225       break;
1226     }
1227 
1228     case T_DOUBLE: {
1229       if (dest->is_double_xmm()) {
1230         __ movdbl(dest->as_xmm_double_reg(), from_addr);
1231       } else {
1232         assert(dest->is_double_fpu(), "must be");
1233         assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
1234         __ fld_d(from_addr);
1235       }
1236       break;
1237     }
1238 
1239     case T_ADDRESS: // fall through
1240     case T_OBJECT:  // fall through
1241     case T_ARRAY:   // fall through
1242 #ifdef _LP64
1243       __ movptr(dest->as_register(), from_addr);
1244       break;
1245 #endif // _L64
1246     case T_INT:
1247       // %%% could this be a movl? this is safer but longer instruction
1248       __ movl2ptr(dest->as_register(), from_addr);
1249       break;
1250 
1251     case T_LONG: {
1252       Register to_lo = dest->as_register_lo();
1253       Register to_hi = dest->as_register_hi();
1254 #ifdef _LP64
1255       __ movptr(to_lo, as_Address_lo(addr));
1256 #else
1257       Register base = addr->base()->as_register();
1258       Register index = noreg;
1259       if (addr->index()->is_register()) {
1260         index = addr->index()->as_register();
1261       }
1262       if ((base == to_lo && index == to_hi) ||
1263           (base == to_hi && index == to_lo)) {
1264         // addresses with 2 registers are only formed as a result of
1265         // array access so this code will never have to deal with
1266         // patches or null checks.
1267         assert(info == NULL && patch == NULL, "must be");
1268         __ lea(to_hi, as_Address(addr));
1269         __ movl(to_lo, Address(to_hi, 0));
1270         __ movl(to_hi, Address(to_hi, BytesPerWord));
1271       } else if (base == to_lo || index == to_lo) {
1272         assert(base != to_hi, "can't be");
1273         assert(index == noreg || (index != base && index != to_hi), "can't handle this");
1274         __ movl(to_hi, as_Address_hi(addr));
1275         if (patch != NULL) {
1276           patching_epilog(patch, lir_patch_high, base, info);
1277           patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1278           patch_code = lir_patch_low;
1279         }
1280         __ movl(to_lo, as_Address_lo(addr));
1281       } else {
1282         assert(index == noreg || (index != base && index != to_lo), "can't handle this");
1283         __ movl(to_lo, as_Address_lo(addr));
1284         if (patch != NULL) {
1285           patching_epilog(patch, lir_patch_low, base, info);
1286           patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1287           patch_code = lir_patch_high;
1288         }
1289         __ movl(to_hi, as_Address_hi(addr));
1290       }
1291 #endif // _LP64
1292       break;
1293     }
1294 
1295     case T_BOOLEAN: // fall through
1296     case T_BYTE: {
1297       Register dest_reg = dest->as_register();
1298       assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6");
1299       if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1300         __ movsbl(dest_reg, from_addr);
1301       } else {
1302         __ movb(dest_reg, from_addr);
1303         __ shll(dest_reg, 24);
1304         __ sarl(dest_reg, 24);
1305       }
1306       // These are unsigned so the zero extension on 64bit is just what we need
1307       break;
1308     }
1309 
1310     case T_CHAR: {
1311       Register dest_reg = dest->as_register();
1312       assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6");
1313       if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1314         __ movzwl(dest_reg, from_addr);
1315       } else {
1316         __ movw(dest_reg, from_addr);
1317       }
1318       // This is unsigned so the zero extension on 64bit is just what we need
1319       // __ movl2ptr(dest_reg, dest_reg);
1320       break;
1321     }
1322 
1323     case T_SHORT: {
1324       Register dest_reg = dest->as_register();
1325       if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1326         __ movswl(dest_reg, from_addr);
1327       } else {
1328         __ movw(dest_reg, from_addr);
1329         __ shll(dest_reg, 16);
1330         __ sarl(dest_reg, 16);
1331       }
1332       // Might not be needed in 64bit but certainly doesn't hurt (except for code size)
1333       __ movl2ptr(dest_reg, dest_reg);
1334       break;
1335     }
1336 
1337     default:
1338       ShouldNotReachHere();
1339   }
1340 
1341   if (patch != NULL) {
1342     patching_epilog(patch, patch_code, addr->base()->as_register(), info);
1343   }
1344 
1345   if (type == T_ARRAY || type == T_OBJECT) {
1346     __ verify_oop(dest->as_register());
1347   }
1348 }
1349 
1350 
1351 void LIR_Assembler::prefetchr(LIR_Opr src) {
1352   LIR_Address* addr = src->as_address_ptr();
1353   Address from_addr = as_Address(addr);
1354 
1355   if (VM_Version::supports_sse()) {
1356     switch (ReadPrefetchInstr) {
1357       case 0:
1358         __ prefetchnta(from_addr); break;
1359       case 1:
1360         __ prefetcht0(from_addr); break;
1361       case 2:
1362         __ prefetcht2(from_addr); break;
1363       default:
1364         ShouldNotReachHere(); break;
1365     }
1366   } else if (VM_Version::supports_3dnow()) {
1367     __ prefetchr(from_addr);
1368   }
1369 }
1370 
1371 
1372 void LIR_Assembler::prefetchw(LIR_Opr src) {
1373   LIR_Address* addr = src->as_address_ptr();
1374   Address from_addr = as_Address(addr);
1375 
1376   if (VM_Version::supports_sse()) {
1377     switch (AllocatePrefetchInstr) {
1378       case 0:
1379         __ prefetchnta(from_addr); break;
1380       case 1:
1381         __ prefetcht0(from_addr); break;
1382       case 2:
1383         __ prefetcht2(from_addr); break;
1384       case 3:
1385         __ prefetchw(from_addr); break;
1386       default:
1387         ShouldNotReachHere(); break;
1388     }
1389   } else if (VM_Version::supports_3dnow()) {
1390     __ prefetchw(from_addr);
1391   }
1392 }
1393 
1394 
1395 NEEDS_CLEANUP; // This could be static?
1396 Address::ScaleFactor LIR_Assembler::array_element_size(BasicType type) const {
1397   int elem_size = type2aelembytes(type);
1398   switch (elem_size) {
1399     case 1: return Address::times_1;
1400     case 2: return Address::times_2;
1401     case 4: return Address::times_4;
1402     case 8: return Address::times_8;
1403   }
1404   ShouldNotReachHere();
1405   return Address::no_scale;
1406 }
1407 
1408 
1409 void LIR_Assembler::emit_op3(LIR_Op3* op) {
1410   switch (op->code()) {
1411     case lir_idiv:
1412     case lir_irem:
1413       arithmetic_idiv(op->code(),
1414                       op->in_opr1(),
1415                       op->in_opr2(),
1416                       op->in_opr3(),
1417                       op->result_opr(),
1418                       op->info());
1419       break;
1420     default:      ShouldNotReachHere(); break;
1421   }
1422 }
1423 
1424 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
1425 #ifdef ASSERT
1426   assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label");
1427   if (op->block() != NULL)  _branch_target_blocks.append(op->block());
1428   if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock());
1429 #endif
1430 
1431   if (op->cond() == lir_cond_always) {
1432     if (op->info() != NULL) add_debug_info_for_branch(op->info());
1433     __ jmp (*(op->label()));
1434   } else {
1435     Assembler::Condition acond = Assembler::zero;
1436     if (op->code() == lir_cond_float_branch) {
1437       assert(op->ublock() != NULL, "must have unordered successor");
1438       __ jcc(Assembler::parity, *(op->ublock()->label()));
1439       switch(op->cond()) {
1440         case lir_cond_equal:        acond = Assembler::equal;      break;
1441         case lir_cond_notEqual:     acond = Assembler::notEqual;   break;
1442         case lir_cond_less:         acond = Assembler::below;      break;
1443         case lir_cond_lessEqual:    acond = Assembler::belowEqual; break;
1444         case lir_cond_greaterEqual: acond = Assembler::aboveEqual; break;
1445         case lir_cond_greater:      acond = Assembler::above;      break;
1446         default:                         ShouldNotReachHere();
1447       }
1448     } else {
1449       switch (op->cond()) {
1450         case lir_cond_equal:        acond = Assembler::equal;       break;
1451         case lir_cond_notEqual:     acond = Assembler::notEqual;    break;
1452         case lir_cond_less:         acond = Assembler::less;        break;
1453         case lir_cond_lessEqual:    acond = Assembler::lessEqual;   break;
1454         case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break;
1455         case lir_cond_greater:      acond = Assembler::greater;     break;
1456         case lir_cond_belowEqual:   acond = Assembler::belowEqual;  break;
1457         case lir_cond_aboveEqual:   acond = Assembler::aboveEqual;  break;
1458         default:                         ShouldNotReachHere();
1459       }
1460     }
1461     __ jcc(acond,*(op->label()));
1462   }
1463 }
1464 
1465 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
1466   LIR_Opr src  = op->in_opr();
1467   LIR_Opr dest = op->result_opr();
1468 
1469   switch (op->bytecode()) {
1470     case Bytecodes::_i2l:
1471 #ifdef _LP64
1472       __ movl2ptr(dest->as_register_lo(), src->as_register());
1473 #else
1474       move_regs(src->as_register(), dest->as_register_lo());
1475       move_regs(src->as_register(), dest->as_register_hi());
1476       __ sarl(dest->as_register_hi(), 31);
1477 #endif // LP64
1478       break;
1479 
1480     case Bytecodes::_l2i:
1481       move_regs(src->as_register_lo(), dest->as_register());
1482       break;
1483 
1484     case Bytecodes::_i2b:
1485       move_regs(src->as_register(), dest->as_register());
1486       __ sign_extend_byte(dest->as_register());
1487       break;
1488 
1489     case Bytecodes::_i2c:
1490       move_regs(src->as_register(), dest->as_register());
1491       __ andl(dest->as_register(), 0xFFFF);
1492       break;
1493 
1494     case Bytecodes::_i2s:
1495       move_regs(src->as_register(), dest->as_register());
1496       __ sign_extend_short(dest->as_register());
1497       break;
1498 
1499 
1500     case Bytecodes::_f2d:
1501     case Bytecodes::_d2f:
1502       if (dest->is_single_xmm()) {
1503         __ cvtsd2ss(dest->as_xmm_float_reg(), src->as_xmm_double_reg());
1504       } else if (dest->is_double_xmm()) {
1505         __ cvtss2sd(dest->as_xmm_double_reg(), src->as_xmm_float_reg());
1506       } else {
1507         assert(src->fpu() == dest->fpu(), "register must be equal");
1508         // do nothing (float result is rounded later through spilling)
1509       }
1510       break;
1511 
1512     case Bytecodes::_i2f:
1513     case Bytecodes::_i2d:
1514       if (dest->is_single_xmm()) {
1515         __ cvtsi2ssl(dest->as_xmm_float_reg(), src->as_register());
1516       } else if (dest->is_double_xmm()) {
1517         __ cvtsi2sdl(dest->as_xmm_double_reg(), src->as_register());
1518       } else {
1519         assert(dest->fpu() == 0, "result must be on TOS");
1520         __ movl(Address(rsp, 0), src->as_register());
1521         __ fild_s(Address(rsp, 0));
1522       }
1523       break;
1524 
1525     case Bytecodes::_f2i:
1526     case Bytecodes::_d2i:
1527       if (src->is_single_xmm()) {
1528         __ cvttss2sil(dest->as_register(), src->as_xmm_float_reg());
1529       } else if (src->is_double_xmm()) {
1530         __ cvttsd2sil(dest->as_register(), src->as_xmm_double_reg());
1531       } else {
1532         assert(src->fpu() == 0, "input must be on TOS");
1533         __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc()));
1534         __ fist_s(Address(rsp, 0));
1535         __ movl(dest->as_register(), Address(rsp, 0));
1536         __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
1537       }
1538 
1539       // IA32 conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub
1540       assert(op->stub() != NULL, "stub required");
1541       __ cmpl(dest->as_register(), 0x80000000);
1542       __ jcc(Assembler::equal, *op->stub()->entry());
1543       __ bind(*op->stub()->continuation());
1544       break;
1545 
1546     case Bytecodes::_l2f:
1547     case Bytecodes::_l2d:
1548       assert(!dest->is_xmm_register(), "result in xmm register not supported (no SSE instruction present)");
1549       assert(dest->fpu() == 0, "result must be on TOS");
1550 
1551       __ movptr(Address(rsp, 0),            src->as_register_lo());
1552       NOT_LP64(__ movl(Address(rsp, BytesPerWord), src->as_register_hi()));
1553       __ fild_d(Address(rsp, 0));
1554       // float result is rounded later through spilling
1555       break;
1556 
1557     case Bytecodes::_f2l:
1558     case Bytecodes::_d2l:
1559       assert(!src->is_xmm_register(), "input in xmm register not supported (no SSE instruction present)");
1560       assert(src->fpu() == 0, "input must be on TOS");
1561       assert(dest == FrameMap::long0_opr, "runtime stub places result in these registers");
1562 
1563       // instruction sequence too long to inline it here
1564       {
1565         __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::fpu2long_stub_id)));
1566       }
1567       break;
1568 
1569     default: ShouldNotReachHere();
1570   }
1571 }
1572 
1573 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
1574   if (op->init_check()) {
1575     __ cmpl(Address(op->klass()->as_register(),
1576                     instanceKlass::init_state_offset_in_bytes() + sizeof(oopDesc)),
1577             instanceKlass::fully_initialized);
1578     add_debug_info_for_null_check_here(op->stub()->info());
1579     __ jcc(Assembler::notEqual, *op->stub()->entry());
1580   }
1581   __ allocate_object(op->obj()->as_register(),
1582                      op->tmp1()->as_register(),
1583                      op->tmp2()->as_register(),
1584                      op->header_size(),
1585                      op->object_size(),
1586                      op->klass()->as_register(),
1587                      *op->stub()->entry());
1588   __ bind(*op->stub()->continuation());
1589 }
1590 
1591 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
1592   if (UseSlowPath ||
1593       (!UseFastNewObjectArray && (op->type() == T_OBJECT || op->type() == T_ARRAY)) ||
1594       (!UseFastNewTypeArray   && (op->type() != T_OBJECT && op->type() != T_ARRAY))) {
1595     __ jmp(*op->stub()->entry());
1596   } else {
1597     Register len =  op->len()->as_register();
1598     Register tmp1 = op->tmp1()->as_register();
1599     Register tmp2 = op->tmp2()->as_register();
1600     Register tmp3 = op->tmp3()->as_register();
1601     if (len == tmp1) {
1602       tmp1 = tmp3;
1603     } else if (len == tmp2) {
1604       tmp2 = tmp3;
1605     } else if (len == tmp3) {
1606       // everything is ok
1607     } else {
1608       __ mov(tmp3, len);
1609     }
1610     __ allocate_array(op->obj()->as_register(),
1611                       len,
1612                       tmp1,
1613                       tmp2,
1614                       arrayOopDesc::header_size(op->type()),
1615                       array_element_size(op->type()),
1616                       op->klass()->as_register(),
1617                       *op->stub()->entry());
1618   }
1619   __ bind(*op->stub()->continuation());
1620 }
1621 
1622 
1623 
1624 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
1625   LIR_Code code = op->code();
1626   if (code == lir_store_check) {
1627     Register value = op->object()->as_register();
1628     Register array = op->array()->as_register();
1629     Register k_RInfo = op->tmp1()->as_register();
1630     Register klass_RInfo = op->tmp2()->as_register();
1631     Register Rtmp1 = op->tmp3()->as_register();
1632 
1633     CodeStub* stub = op->stub();
1634     Label done;
1635     __ cmpptr(value, (int32_t)NULL_WORD);
1636     __ jcc(Assembler::equal, done);
1637     add_debug_info_for_null_check_here(op->info_for_exception());
1638     __ movptr(k_RInfo, Address(array, oopDesc::klass_offset_in_bytes()));
1639     __ movptr(klass_RInfo, Address(value, oopDesc::klass_offset_in_bytes()));
1640 
1641     // get instance klass
1642     __ movptr(k_RInfo, Address(k_RInfo, objArrayKlass::element_klass_offset_in_bytes() + sizeof(oopDesc)));
1643     // perform the fast part of the checking logic
1644     __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, &done, stub->entry(), NULL);
1645     // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1646     __ push(klass_RInfo);
1647     __ push(k_RInfo);
1648     __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1649     __ pop(klass_RInfo);
1650     __ pop(k_RInfo);
1651     // result is a boolean
1652     __ cmpl(k_RInfo, 0);
1653     __ jcc(Assembler::equal, *stub->entry());
1654     __ bind(done);
1655   } else if (op->code() == lir_checkcast) {
1656     // we always need a stub for the failure case.
1657     CodeStub* stub = op->stub();
1658     Register obj = op->object()->as_register();
1659     Register k_RInfo = op->tmp1()->as_register();
1660     Register klass_RInfo = op->tmp2()->as_register();
1661     Register dst = op->result_opr()->as_register();
1662     ciKlass* k = op->klass();
1663     Register Rtmp1 = noreg;
1664 
1665     Label done;
1666     if (obj == k_RInfo) {
1667       k_RInfo = dst;
1668     } else if (obj == klass_RInfo) {
1669       klass_RInfo = dst;
1670     }
1671     if (k->is_loaded()) {
1672       select_different_registers(obj, dst, k_RInfo, klass_RInfo);
1673     } else {
1674       Rtmp1 = op->tmp3()->as_register();
1675       select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1);
1676     }
1677 
1678     assert_different_registers(obj, k_RInfo, klass_RInfo);
1679     if (!k->is_loaded()) {
1680       jobject2reg_with_patching(k_RInfo, op->info_for_patch());
1681     } else {
1682 #ifdef _LP64
1683       __ movoop(k_RInfo, k->constant_encoding());
1684 #else
1685       k_RInfo = noreg;
1686 #endif // _LP64
1687     }
1688     assert(obj != k_RInfo, "must be different");
1689     __ cmpptr(obj, (int32_t)NULL_WORD);
1690     if (op->profiled_method() != NULL) {
1691       ciMethod* method = op->profiled_method();
1692       int bci          = op->profiled_bci();
1693 
1694       Label profile_done;
1695       __ jcc(Assembler::notEqual, profile_done);
1696       // Object is null; update methodDataOop
1697       ciMethodData* md = method->method_data();
1698       if (md == NULL) {
1699         bailout("out of memory building methodDataOop");
1700         return;
1701       }
1702       ciProfileData* data = md->bci_to_data(bci);
1703       assert(data != NULL,       "need data for checkcast");
1704       assert(data->is_BitData(), "need BitData for checkcast");
1705       Register mdo  = klass_RInfo;
1706       __ movoop(mdo, md->constant_encoding());
1707       Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::header_offset()));
1708       int header_bits = DataLayout::flag_mask_to_header_mask(BitData::null_seen_byte_constant());
1709       __ orl(data_addr, header_bits);
1710       __ jmp(done);
1711       __ bind(profile_done);
1712     } else {
1713       __ jcc(Assembler::equal, done);
1714     }
1715     __ verify_oop(obj);
1716 
1717     if (op->fast_check()) {
1718       // get object classo
1719       // not a safepoint as obj null check happens earlier
1720       if (k->is_loaded()) {
1721 #ifdef _LP64
1722         __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
1723 #else
1724         __ cmpoop(Address(obj, oopDesc::klass_offset_in_bytes()), k->constant_encoding());
1725 #endif // _LP64
1726       } else {
1727         __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
1728 
1729       }
1730       __ jcc(Assembler::notEqual, *stub->entry());
1731       __ bind(done);
1732     } else {
1733       // get object class
1734       // not a safepoint as obj null check happens earlier
1735       __ movptr(klass_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
1736       if (k->is_loaded()) {
1737         // See if we get an immediate positive hit
1738 #ifdef _LP64
1739         __ cmpptr(k_RInfo, Address(klass_RInfo, k->super_check_offset()));
1740 #else
1741         __ cmpoop(Address(klass_RInfo, k->super_check_offset()), k->constant_encoding());
1742 #endif // _LP64
1743         if (sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes() != k->super_check_offset()) {
1744           __ jcc(Assembler::notEqual, *stub->entry());
1745         } else {
1746           // See if we get an immediate positive hit
1747           __ jcc(Assembler::equal, done);
1748           // check for self
1749 #ifdef _LP64
1750           __ cmpptr(klass_RInfo, k_RInfo);
1751 #else
1752           __ cmpoop(klass_RInfo, k->constant_encoding());
1753 #endif // _LP64
1754           __ jcc(Assembler::equal, done);
1755 
1756           __ push(klass_RInfo);
1757 #ifdef _LP64
1758           __ push(k_RInfo);
1759 #else
1760           __ pushoop(k->constant_encoding());
1761 #endif // _LP64
1762           __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1763           __ pop(klass_RInfo);
1764           __ pop(klass_RInfo);
1765           // result is a boolean
1766           __ cmpl(klass_RInfo, 0);
1767           __ jcc(Assembler::equal, *stub->entry());
1768         }
1769         __ bind(done);
1770       } else {
1771         // perform the fast part of the checking logic
1772         __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, &done, stub->entry(), NULL);
1773         // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1774         __ push(klass_RInfo);
1775         __ push(k_RInfo);
1776         __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1777         __ pop(klass_RInfo);
1778         __ pop(k_RInfo);
1779         // result is a boolean
1780         __ cmpl(k_RInfo, 0);
1781         __ jcc(Assembler::equal, *stub->entry());
1782         __ bind(done);
1783       }
1784 
1785     }
1786     if (dst != obj) {
1787       __ mov(dst, obj);
1788     }
1789   } else if (code == lir_instanceof) {
1790     Register obj = op->object()->as_register();
1791     Register k_RInfo = op->tmp1()->as_register();
1792     Register klass_RInfo = op->tmp2()->as_register();
1793     Register dst = op->result_opr()->as_register();
1794     ciKlass* k = op->klass();
1795 
1796     Label done;
1797     Label zero;
1798     Label one;
1799     if (obj == k_RInfo) {
1800       k_RInfo = klass_RInfo;
1801       klass_RInfo = obj;
1802     }
1803     // patching may screw with our temporaries on sparc,
1804     // so let's do it before loading the class
1805     if (!k->is_loaded()) {
1806       jobject2reg_with_patching(k_RInfo, op->info_for_patch());
1807     } else {
1808       LP64_ONLY(__ movoop(k_RInfo, k->constant_encoding()));
1809     }
1810     assert(obj != k_RInfo, "must be different");
1811 
1812     __ verify_oop(obj);
1813     if (op->fast_check()) {
1814       __ cmpptr(obj, (int32_t)NULL_WORD);
1815       __ jcc(Assembler::equal, zero);
1816       // get object class
1817       // not a safepoint as obj null check happens earlier
1818       if (LP64_ONLY(false &&) k->is_loaded()) {
1819         NOT_LP64(__ cmpoop(Address(obj, oopDesc::klass_offset_in_bytes()), k->constant_encoding()));
1820         k_RInfo = noreg;
1821       } else {
1822         __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
1823 
1824       }
1825       __ jcc(Assembler::equal, one);
1826     } else {
1827       // get object class
1828       // not a safepoint as obj null check happens earlier
1829       __ cmpptr(obj, (int32_t)NULL_WORD);
1830       __ jcc(Assembler::equal, zero);
1831       __ movptr(klass_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
1832 
1833 #ifndef _LP64
1834       if (k->is_loaded()) {
1835         // See if we get an immediate positive hit
1836         __ cmpoop(Address(klass_RInfo, k->super_check_offset()), k->constant_encoding());
1837         __ jcc(Assembler::equal, one);
1838         if (sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes() == k->super_check_offset()) {
1839           // check for self
1840           __ cmpoop(klass_RInfo, k->constant_encoding());
1841           __ jcc(Assembler::equal, one);
1842           __ push(klass_RInfo);
1843           __ pushoop(k->constant_encoding());
1844           __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1845           __ pop(klass_RInfo);
1846           __ pop(dst);
1847           __ jmp(done);
1848         }
1849       }
1850         else // next block is unconditional if LP64:
1851 #endif // LP64
1852       {
1853         assert(dst != klass_RInfo && dst != k_RInfo, "need 3 registers");
1854 
1855         // perform the fast part of the checking logic
1856         __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, dst, &one, &zero, NULL);
1857         // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1858         __ push(klass_RInfo);
1859         __ push(k_RInfo);
1860         __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1861         __ pop(klass_RInfo);
1862         __ pop(dst);
1863         __ jmp(done);
1864       }
1865     }
1866     __ bind(zero);
1867     __ xorptr(dst, dst);
1868     __ jmp(done);
1869     __ bind(one);
1870     __ movptr(dst, 1);
1871     __ bind(done);
1872   } else {
1873     ShouldNotReachHere();
1874   }
1875 
1876 }
1877 
1878 
1879 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
1880   if (LP64_ONLY(false &&) op->code() == lir_cas_long && VM_Version::supports_cx8()) {
1881     assert(op->cmp_value()->as_register_lo() == rax, "wrong register");
1882     assert(op->cmp_value()->as_register_hi() == rdx, "wrong register");
1883     assert(op->new_value()->as_register_lo() == rbx, "wrong register");
1884     assert(op->new_value()->as_register_hi() == rcx, "wrong register");
1885     Register addr = op->addr()->as_register();
1886     if (os::is_MP()) {
1887       __ lock();
1888     }
1889     NOT_LP64(__ cmpxchg8(Address(addr, 0)));
1890 
1891   } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj ) {
1892     NOT_LP64(assert(op->addr()->is_single_cpu(), "must be single");)
1893     Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo());
1894     Register newval = op->new_value()->as_register();
1895     Register cmpval = op->cmp_value()->as_register();
1896     assert(cmpval == rax, "wrong register");
1897     assert(newval != NULL, "new val must be register");
1898     assert(cmpval != newval, "cmp and new values must be in different registers");
1899     assert(cmpval != addr, "cmp and addr must be in different registers");
1900     assert(newval != addr, "new value and addr must be in different registers");
1901     if (os::is_MP()) {
1902       __ lock();
1903     }
1904     if ( op->code() == lir_cas_obj) {
1905       __ cmpxchgptr(newval, Address(addr, 0));
1906     } else if (op->code() == lir_cas_int) {
1907       __ cmpxchgl(newval, Address(addr, 0));
1908     } else {
1909       LP64_ONLY(__ cmpxchgq(newval, Address(addr, 0)));
1910     }
1911 #ifdef _LP64
1912   } else if (op->code() == lir_cas_long) {
1913     Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo());
1914     Register newval = op->new_value()->as_register_lo();
1915     Register cmpval = op->cmp_value()->as_register_lo();
1916     assert(cmpval == rax, "wrong register");
1917     assert(newval != NULL, "new val must be register");
1918     assert(cmpval != newval, "cmp and new values must be in different registers");
1919     assert(cmpval != addr, "cmp and addr must be in different registers");
1920     assert(newval != addr, "new value and addr must be in different registers");
1921     if (os::is_MP()) {
1922       __ lock();
1923     }
1924     __ cmpxchgq(newval, Address(addr, 0));
1925 #endif // _LP64
1926   } else {
1927     Unimplemented();
1928   }
1929 }
1930 
1931 
1932 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result) {
1933   Assembler::Condition acond, ncond;
1934   switch (condition) {
1935     case lir_cond_equal:        acond = Assembler::equal;        ncond = Assembler::notEqual;     break;
1936     case lir_cond_notEqual:     acond = Assembler::notEqual;     ncond = Assembler::equal;        break;
1937     case lir_cond_less:         acond = Assembler::less;         ncond = Assembler::greaterEqual; break;
1938     case lir_cond_lessEqual:    acond = Assembler::lessEqual;    ncond = Assembler::greater;      break;
1939     case lir_cond_greaterEqual: acond = Assembler::greaterEqual; ncond = Assembler::less;         break;
1940     case lir_cond_greater:      acond = Assembler::greater;      ncond = Assembler::lessEqual;    break;
1941     case lir_cond_belowEqual:   acond = Assembler::belowEqual;   ncond = Assembler::above;        break;
1942     case lir_cond_aboveEqual:   acond = Assembler::aboveEqual;   ncond = Assembler::below;        break;
1943     default:                    ShouldNotReachHere();
1944   }
1945 
1946   if (opr1->is_cpu_register()) {
1947     reg2reg(opr1, result);
1948   } else if (opr1->is_stack()) {
1949     stack2reg(opr1, result, result->type());
1950   } else if (opr1->is_constant()) {
1951     const2reg(opr1, result, lir_patch_none, NULL);
1952   } else {
1953     ShouldNotReachHere();
1954   }
1955 
1956   if (VM_Version::supports_cmov() && !opr2->is_constant()) {
1957     // optimized version that does not require a branch
1958     if (opr2->is_single_cpu()) {
1959       assert(opr2->cpu_regnr() != result->cpu_regnr(), "opr2 already overwritten by previous move");
1960       __ cmov(ncond, result->as_register(), opr2->as_register());
1961     } else if (opr2->is_double_cpu()) {
1962       assert(opr2->cpu_regnrLo() != result->cpu_regnrLo() && opr2->cpu_regnrLo() != result->cpu_regnrHi(), "opr2 already overwritten by previous move");
1963       assert(opr2->cpu_regnrHi() != result->cpu_regnrLo() && opr2->cpu_regnrHi() != result->cpu_regnrHi(), "opr2 already overwritten by previous move");
1964       __ cmovptr(ncond, result->as_register_lo(), opr2->as_register_lo());
1965       NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), opr2->as_register_hi());)
1966     } else if (opr2->is_single_stack()) {
1967       __ cmovl(ncond, result->as_register(), frame_map()->address_for_slot(opr2->single_stack_ix()));
1968     } else if (opr2->is_double_stack()) {
1969       __ cmovptr(ncond, result->as_register_lo(), frame_map()->address_for_slot(opr2->double_stack_ix(), lo_word_offset_in_bytes));
1970       NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), frame_map()->address_for_slot(opr2->double_stack_ix(), hi_word_offset_in_bytes));)
1971     } else {
1972       ShouldNotReachHere();
1973     }
1974 
1975   } else {
1976     Label skip;
1977     __ jcc (acond, skip);
1978     if (opr2->is_cpu_register()) {
1979       reg2reg(opr2, result);
1980     } else if (opr2->is_stack()) {
1981       stack2reg(opr2, result, result->type());
1982     } else if (opr2->is_constant()) {
1983       const2reg(opr2, result, lir_patch_none, NULL);
1984     } else {
1985       ShouldNotReachHere();
1986     }
1987     __ bind(skip);
1988   }
1989 }
1990 
1991 
1992 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) {
1993   assert(info == NULL, "should never be used, idiv/irem and ldiv/lrem not handled by this method");
1994 
1995   if (left->is_single_cpu()) {
1996     assert(left == dest, "left and dest must be equal");
1997     Register lreg = left->as_register();
1998 
1999     if (right->is_single_cpu()) {
2000       // cpu register - cpu register
2001       Register rreg = right->as_register();
2002       switch (code) {
2003         case lir_add: __ addl (lreg, rreg); break;
2004         case lir_sub: __ subl (lreg, rreg); break;
2005         case lir_mul: __ imull(lreg, rreg); break;
2006         default:      ShouldNotReachHere();
2007       }
2008 
2009     } else if (right->is_stack()) {
2010       // cpu register - stack
2011       Address raddr = frame_map()->address_for_slot(right->single_stack_ix());
2012       switch (code) {
2013         case lir_add: __ addl(lreg, raddr); break;
2014         case lir_sub: __ subl(lreg, raddr); break;
2015         default:      ShouldNotReachHere();
2016       }
2017 
2018     } else if (right->is_constant()) {
2019       // cpu register - constant
2020       jint c = right->as_constant_ptr()->as_jint();
2021       switch (code) {
2022         case lir_add: {
2023           __ increment(lreg, c);
2024           break;
2025         }
2026         case lir_sub: {
2027           __ decrement(lreg, c);
2028           break;
2029         }
2030         default: ShouldNotReachHere();
2031       }
2032 
2033     } else {
2034       ShouldNotReachHere();
2035     }
2036 
2037   } else if (left->is_double_cpu()) {
2038     assert(left == dest, "left and dest must be equal");
2039     Register lreg_lo = left->as_register_lo();
2040     Register lreg_hi = left->as_register_hi();
2041 
2042     if (right->is_double_cpu()) {
2043       // cpu register - cpu register
2044       Register rreg_lo = right->as_register_lo();
2045       Register rreg_hi = right->as_register_hi();
2046       NOT_LP64(assert_different_registers(lreg_lo, lreg_hi, rreg_lo, rreg_hi));
2047       LP64_ONLY(assert_different_registers(lreg_lo, rreg_lo));
2048       switch (code) {
2049         case lir_add:
2050           __ addptr(lreg_lo, rreg_lo);
2051           NOT_LP64(__ adcl(lreg_hi, rreg_hi));
2052           break;
2053         case lir_sub:
2054           __ subptr(lreg_lo, rreg_lo);
2055           NOT_LP64(__ sbbl(lreg_hi, rreg_hi));
2056           break;
2057         case lir_mul:
2058 #ifdef _LP64
2059           __ imulq(lreg_lo, rreg_lo);
2060 #else
2061           assert(lreg_lo == rax && lreg_hi == rdx, "must be");
2062           __ imull(lreg_hi, rreg_lo);
2063           __ imull(rreg_hi, lreg_lo);
2064           __ addl (rreg_hi, lreg_hi);
2065           __ mull (rreg_lo);
2066           __ addl (lreg_hi, rreg_hi);
2067 #endif // _LP64
2068           break;
2069         default:
2070           ShouldNotReachHere();
2071       }
2072 
2073     } else if (right->is_constant()) {
2074       // cpu register - constant
2075 #ifdef _LP64
2076       jlong c = right->as_constant_ptr()->as_jlong_bits();
2077       __ movptr(r10, (intptr_t) c);
2078       switch (code) {
2079         case lir_add:
2080           __ addptr(lreg_lo, r10);
2081           break;
2082         case lir_sub:
2083           __ subptr(lreg_lo, r10);
2084           break;
2085         default:
2086           ShouldNotReachHere();
2087       }
2088 #else
2089       jint c_lo = right->as_constant_ptr()->as_jint_lo();
2090       jint c_hi = right->as_constant_ptr()->as_jint_hi();
2091       switch (code) {
2092         case lir_add:
2093           __ addptr(lreg_lo, c_lo);
2094           __ adcl(lreg_hi, c_hi);
2095           break;
2096         case lir_sub:
2097           __ subptr(lreg_lo, c_lo);
2098           __ sbbl(lreg_hi, c_hi);
2099           break;
2100         default:
2101           ShouldNotReachHere();
2102       }
2103 #endif // _LP64
2104 
2105     } else {
2106       ShouldNotReachHere();
2107     }
2108 
2109   } else if (left->is_single_xmm()) {
2110     assert(left == dest, "left and dest must be equal");
2111     XMMRegister lreg = left->as_xmm_float_reg();
2112 
2113     if (right->is_single_xmm()) {
2114       XMMRegister rreg = right->as_xmm_float_reg();
2115       switch (code) {
2116         case lir_add: __ addss(lreg, rreg);  break;
2117         case lir_sub: __ subss(lreg, rreg);  break;
2118         case lir_mul_strictfp: // fall through
2119         case lir_mul: __ mulss(lreg, rreg);  break;
2120         case lir_div_strictfp: // fall through
2121         case lir_div: __ divss(lreg, rreg);  break;
2122         default: ShouldNotReachHere();
2123       }
2124     } else {
2125       Address raddr;
2126       if (right->is_single_stack()) {
2127         raddr = frame_map()->address_for_slot(right->single_stack_ix());
2128       } else if (right->is_constant()) {
2129         // hack for now
2130         raddr = __ as_Address(InternalAddress(float_constant(right->as_jfloat())));
2131       } else {
2132         ShouldNotReachHere();
2133       }
2134       switch (code) {
2135         case lir_add: __ addss(lreg, raddr);  break;
2136         case lir_sub: __ subss(lreg, raddr);  break;
2137         case lir_mul_strictfp: // fall through
2138         case lir_mul: __ mulss(lreg, raddr);  break;
2139         case lir_div_strictfp: // fall through
2140         case lir_div: __ divss(lreg, raddr);  break;
2141         default: ShouldNotReachHere();
2142       }
2143     }
2144 
2145   } else if (left->is_double_xmm()) {
2146     assert(left == dest, "left and dest must be equal");
2147 
2148     XMMRegister lreg = left->as_xmm_double_reg();
2149     if (right->is_double_xmm()) {
2150       XMMRegister rreg = right->as_xmm_double_reg();
2151       switch (code) {
2152         case lir_add: __ addsd(lreg, rreg);  break;
2153         case lir_sub: __ subsd(lreg, rreg);  break;
2154         case lir_mul_strictfp: // fall through
2155         case lir_mul: __ mulsd(lreg, rreg);  break;
2156         case lir_div_strictfp: // fall through
2157         case lir_div: __ divsd(lreg, rreg);  break;
2158         default: ShouldNotReachHere();
2159       }
2160     } else {
2161       Address raddr;
2162       if (right->is_double_stack()) {
2163         raddr = frame_map()->address_for_slot(right->double_stack_ix());
2164       } else if (right->is_constant()) {
2165         // hack for now
2166         raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble())));
2167       } else {
2168         ShouldNotReachHere();
2169       }
2170       switch (code) {
2171         case lir_add: __ addsd(lreg, raddr);  break;
2172         case lir_sub: __ subsd(lreg, raddr);  break;
2173         case lir_mul_strictfp: // fall through
2174         case lir_mul: __ mulsd(lreg, raddr);  break;
2175         case lir_div_strictfp: // fall through
2176         case lir_div: __ divsd(lreg, raddr);  break;
2177         default: ShouldNotReachHere();
2178       }
2179     }
2180 
2181   } else if (left->is_single_fpu()) {
2182     assert(dest->is_single_fpu(),  "fpu stack allocation required");
2183 
2184     if (right->is_single_fpu()) {
2185       arith_fpu_implementation(code, left->fpu_regnr(), right->fpu_regnr(), dest->fpu_regnr(), pop_fpu_stack);
2186 
2187     } else {
2188       assert(left->fpu_regnr() == 0, "left must be on TOS");
2189       assert(dest->fpu_regnr() == 0, "dest must be on TOS");
2190 
2191       Address raddr;
2192       if (right->is_single_stack()) {
2193         raddr = frame_map()->address_for_slot(right->single_stack_ix());
2194       } else if (right->is_constant()) {
2195         address const_addr = float_constant(right->as_jfloat());
2196         assert(const_addr != NULL, "incorrect float/double constant maintainance");
2197         // hack for now
2198         raddr = __ as_Address(InternalAddress(const_addr));
2199       } else {
2200         ShouldNotReachHere();
2201       }
2202 
2203       switch (code) {
2204         case lir_add: __ fadd_s(raddr); break;
2205         case lir_sub: __ fsub_s(raddr); break;
2206         case lir_mul_strictfp: // fall through
2207         case lir_mul: __ fmul_s(raddr); break;
2208         case lir_div_strictfp: // fall through
2209         case lir_div: __ fdiv_s(raddr); break;
2210         default:      ShouldNotReachHere();
2211       }
2212     }
2213 
2214   } else if (left->is_double_fpu()) {
2215     assert(dest->is_double_fpu(),  "fpu stack allocation required");
2216 
2217     if (code == lir_mul_strictfp || code == lir_div_strictfp) {
2218       // Double values require special handling for strictfp mul/div on x86
2219       __ fld_x(ExternalAddress(StubRoutines::addr_fpu_subnormal_bias1()));
2220       __ fmulp(left->fpu_regnrLo() + 1);
2221     }
2222 
2223     if (right->is_double_fpu()) {
2224       arith_fpu_implementation(code, left->fpu_regnrLo(), right->fpu_regnrLo(), dest->fpu_regnrLo(), pop_fpu_stack);
2225 
2226     } else {
2227       assert(left->fpu_regnrLo() == 0, "left must be on TOS");
2228       assert(dest->fpu_regnrLo() == 0, "dest must be on TOS");
2229 
2230       Address raddr;
2231       if (right->is_double_stack()) {
2232         raddr = frame_map()->address_for_slot(right->double_stack_ix());
2233       } else if (right->is_constant()) {
2234         // hack for now
2235         raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble())));
2236       } else {
2237         ShouldNotReachHere();
2238       }
2239 
2240       switch (code) {
2241         case lir_add: __ fadd_d(raddr); break;
2242         case lir_sub: __ fsub_d(raddr); break;
2243         case lir_mul_strictfp: // fall through
2244         case lir_mul: __ fmul_d(raddr); break;
2245         case lir_div_strictfp: // fall through
2246         case lir_div: __ fdiv_d(raddr); break;
2247         default: ShouldNotReachHere();
2248       }
2249     }
2250 
2251     if (code == lir_mul_strictfp || code == lir_div_strictfp) {
2252       // Double values require special handling for strictfp mul/div on x86
2253       __ fld_x(ExternalAddress(StubRoutines::addr_fpu_subnormal_bias2()));
2254       __ fmulp(dest->fpu_regnrLo() + 1);
2255     }
2256 
2257   } else if (left->is_single_stack() || left->is_address()) {
2258     assert(left == dest, "left and dest must be equal");
2259 
2260     Address laddr;
2261     if (left->is_single_stack()) {
2262       laddr = frame_map()->address_for_slot(left->single_stack_ix());
2263     } else if (left->is_address()) {
2264       laddr = as_Address(left->as_address_ptr());
2265     } else {
2266       ShouldNotReachHere();
2267     }
2268 
2269     if (right->is_single_cpu()) {
2270       Register rreg = right->as_register();
2271       switch (code) {
2272         case lir_add: __ addl(laddr, rreg); break;
2273         case lir_sub: __ subl(laddr, rreg); break;
2274         default:      ShouldNotReachHere();
2275       }
2276     } else if (right->is_constant()) {
2277       jint c = right->as_constant_ptr()->as_jint();
2278       switch (code) {
2279         case lir_add: {
2280           __ incrementl(laddr, c);
2281           break;
2282         }
2283         case lir_sub: {
2284           __ decrementl(laddr, c);
2285           break;
2286         }
2287         default: ShouldNotReachHere();
2288       }
2289     } else {
2290       ShouldNotReachHere();
2291     }
2292 
2293   } else {
2294     ShouldNotReachHere();
2295   }
2296 }
2297 
2298 void LIR_Assembler::arith_fpu_implementation(LIR_Code code, int left_index, int right_index, int dest_index, bool pop_fpu_stack) {
2299   assert(pop_fpu_stack  || (left_index     == dest_index || right_index     == dest_index), "invalid LIR");
2300   assert(!pop_fpu_stack || (left_index - 1 == dest_index || right_index - 1 == dest_index), "invalid LIR");
2301   assert(left_index == 0 || right_index == 0, "either must be on top of stack");
2302 
2303   bool left_is_tos = (left_index == 0);
2304   bool dest_is_tos = (dest_index == 0);
2305   int non_tos_index = (left_is_tos ? right_index : left_index);
2306 
2307   switch (code) {
2308     case lir_add:
2309       if (pop_fpu_stack)       __ faddp(non_tos_index);
2310       else if (dest_is_tos)    __ fadd (non_tos_index);
2311       else                     __ fadda(non_tos_index);
2312       break;
2313 
2314     case lir_sub:
2315       if (left_is_tos) {
2316         if (pop_fpu_stack)     __ fsubrp(non_tos_index);
2317         else if (dest_is_tos)  __ fsub  (non_tos_index);
2318         else                   __ fsubra(non_tos_index);
2319       } else {
2320         if (pop_fpu_stack)     __ fsubp (non_tos_index);
2321         else if (dest_is_tos)  __ fsubr (non_tos_index);
2322         else                   __ fsuba (non_tos_index);
2323       }
2324       break;
2325 
2326     case lir_mul_strictfp: // fall through
2327     case lir_mul:
2328       if (pop_fpu_stack)       __ fmulp(non_tos_index);
2329       else if (dest_is_tos)    __ fmul (non_tos_index);
2330       else                     __ fmula(non_tos_index);
2331       break;
2332 
2333     case lir_div_strictfp: // fall through
2334     case lir_div:
2335       if (left_is_tos) {
2336         if (pop_fpu_stack)     __ fdivrp(non_tos_index);
2337         else if (dest_is_tos)  __ fdiv  (non_tos_index);
2338         else                   __ fdivra(non_tos_index);
2339       } else {
2340         if (pop_fpu_stack)     __ fdivp (non_tos_index);
2341         else if (dest_is_tos)  __ fdivr (non_tos_index);
2342         else                   __ fdiva (non_tos_index);
2343       }
2344       break;
2345 
2346     case lir_rem:
2347       assert(left_is_tos && dest_is_tos && right_index == 1, "must be guaranteed by FPU stack allocation");
2348       __ fremr(noreg);
2349       break;
2350 
2351     default:
2352       ShouldNotReachHere();
2353   }
2354 }
2355 
2356 
2357 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr unused, LIR_Opr dest, LIR_Op* op) {
2358   if (value->is_double_xmm()) {
2359     switch(code) {
2360       case lir_abs :
2361         {
2362           if (dest->as_xmm_double_reg() != value->as_xmm_double_reg()) {
2363             __ movdbl(dest->as_xmm_double_reg(), value->as_xmm_double_reg());
2364           }
2365           __ andpd(dest->as_xmm_double_reg(),
2366                     ExternalAddress((address)double_signmask_pool));
2367         }
2368         break;
2369 
2370       case lir_sqrt: __ sqrtsd(dest->as_xmm_double_reg(), value->as_xmm_double_reg()); break;
2371       // all other intrinsics are not available in the SSE instruction set, so FPU is used
2372       default      : ShouldNotReachHere();
2373     }
2374 
2375   } else if (value->is_double_fpu()) {
2376     assert(value->fpu_regnrLo() == 0 && dest->fpu_regnrLo() == 0, "both must be on TOS");
2377     switch(code) {
2378       case lir_log   : __ flog() ; break;
2379       case lir_log10 : __ flog10() ; break;
2380       case lir_abs   : __ fabs() ; break;
2381       case lir_sqrt  : __ fsqrt(); break;
2382       case lir_sin   :
2383         // Should consider not saving rbx, if not necessary
2384         __ trigfunc('s', op->as_Op2()->fpu_stack_size());
2385         break;
2386       case lir_cos :
2387         // Should consider not saving rbx, if not necessary
2388         assert(op->as_Op2()->fpu_stack_size() <= 6, "sin and cos need two free stack slots");
2389         __ trigfunc('c', op->as_Op2()->fpu_stack_size());
2390         break;
2391       case lir_tan :
2392         // Should consider not saving rbx, if not necessary
2393         __ trigfunc('t', op->as_Op2()->fpu_stack_size());
2394         break;
2395       default      : ShouldNotReachHere();
2396     }
2397   } else {
2398     Unimplemented();
2399   }
2400 }
2401 
2402 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) {
2403   // assert(left->destroys_register(), "check");
2404   if (left->is_single_cpu()) {
2405     Register reg = left->as_register();
2406     if (right->is_constant()) {
2407       int val = right->as_constant_ptr()->as_jint();
2408       switch (code) {
2409         case lir_logic_and: __ andl (reg, val); break;
2410         case lir_logic_or:  __ orl  (reg, val); break;
2411         case lir_logic_xor: __ xorl (reg, val); break;
2412         default: ShouldNotReachHere();
2413       }
2414     } else if (right->is_stack()) {
2415       // added support for stack operands
2416       Address raddr = frame_map()->address_for_slot(right->single_stack_ix());
2417       switch (code) {
2418         case lir_logic_and: __ andl (reg, raddr); break;
2419         case lir_logic_or:  __ orl  (reg, raddr); break;
2420         case lir_logic_xor: __ xorl (reg, raddr); break;
2421         default: ShouldNotReachHere();
2422       }
2423     } else {
2424       Register rright = right->as_register();
2425       switch (code) {
2426         case lir_logic_and: __ andptr (reg, rright); break;
2427         case lir_logic_or : __ orptr  (reg, rright); break;
2428         case lir_logic_xor: __ xorptr (reg, rright); break;
2429         default: ShouldNotReachHere();
2430       }
2431     }
2432     move_regs(reg, dst->as_register());
2433   } else {
2434     Register l_lo = left->as_register_lo();
2435     Register l_hi = left->as_register_hi();
2436     if (right->is_constant()) {
2437 #ifdef _LP64
2438       __ mov64(rscratch1, right->as_constant_ptr()->as_jlong());
2439       switch (code) {
2440         case lir_logic_and:
2441           __ andq(l_lo, rscratch1);
2442           break;
2443         case lir_logic_or:
2444           __ orq(l_lo, rscratch1);
2445           break;
2446         case lir_logic_xor:
2447           __ xorq(l_lo, rscratch1);
2448           break;
2449         default: ShouldNotReachHere();
2450       }
2451 #else
2452       int r_lo = right->as_constant_ptr()->as_jint_lo();
2453       int r_hi = right->as_constant_ptr()->as_jint_hi();
2454       switch (code) {
2455         case lir_logic_and:
2456           __ andl(l_lo, r_lo);
2457           __ andl(l_hi, r_hi);
2458           break;
2459         case lir_logic_or:
2460           __ orl(l_lo, r_lo);
2461           __ orl(l_hi, r_hi);
2462           break;
2463         case lir_logic_xor:
2464           __ xorl(l_lo, r_lo);
2465           __ xorl(l_hi, r_hi);
2466           break;
2467         default: ShouldNotReachHere();
2468       }
2469 #endif // _LP64
2470     } else {
2471       Register r_lo = right->as_register_lo();
2472       Register r_hi = right->as_register_hi();
2473       assert(l_lo != r_hi, "overwriting registers");
2474       switch (code) {
2475         case lir_logic_and:
2476           __ andptr(l_lo, r_lo);
2477           NOT_LP64(__ andptr(l_hi, r_hi);)
2478           break;
2479         case lir_logic_or:
2480           __ orptr(l_lo, r_lo);
2481           NOT_LP64(__ orptr(l_hi, r_hi);)
2482           break;
2483         case lir_logic_xor:
2484           __ xorptr(l_lo, r_lo);
2485           NOT_LP64(__ xorptr(l_hi, r_hi);)
2486           break;
2487         default: ShouldNotReachHere();
2488       }
2489     }
2490 
2491     Register dst_lo = dst->as_register_lo();
2492     Register dst_hi = dst->as_register_hi();
2493 
2494 #ifdef _LP64
2495     move_regs(l_lo, dst_lo);
2496 #else
2497     if (dst_lo == l_hi) {
2498       assert(dst_hi != l_lo, "overwriting registers");
2499       move_regs(l_hi, dst_hi);
2500       move_regs(l_lo, dst_lo);
2501     } else {
2502       assert(dst_lo != l_hi, "overwriting registers");
2503       move_regs(l_lo, dst_lo);
2504       move_regs(l_hi, dst_hi);
2505     }
2506 #endif // _LP64
2507   }
2508 }
2509 
2510 
2511 // we assume that rax, and rdx can be overwritten
2512 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info) {
2513 
2514   assert(left->is_single_cpu(),   "left must be register");
2515   assert(right->is_single_cpu() || right->is_constant(),  "right must be register or constant");
2516   assert(result->is_single_cpu(), "result must be register");
2517 
2518   //  assert(left->destroys_register(), "check");
2519   //  assert(right->destroys_register(), "check");
2520 
2521   Register lreg = left->as_register();
2522   Register dreg = result->as_register();
2523 
2524   if (right->is_constant()) {
2525     int divisor = right->as_constant_ptr()->as_jint();
2526     assert(divisor > 0 && is_power_of_2(divisor), "must be");
2527     if (code == lir_idiv) {
2528       assert(lreg == rax, "must be rax,");
2529       assert(temp->as_register() == rdx, "tmp register must be rdx");
2530       __ cdql(); // sign extend into rdx:rax
2531       if (divisor == 2) {
2532         __ subl(lreg, rdx);
2533       } else {
2534         __ andl(rdx, divisor - 1);
2535         __ addl(lreg, rdx);
2536       }
2537       __ sarl(lreg, log2_intptr(divisor));
2538       move_regs(lreg, dreg);
2539     } else if (code == lir_irem) {
2540       Label done;
2541       __ mov(dreg, lreg);
2542       __ andl(dreg, 0x80000000 | (divisor - 1));
2543       __ jcc(Assembler::positive, done);
2544       __ decrement(dreg);
2545       __ orl(dreg, ~(divisor - 1));
2546       __ increment(dreg);
2547       __ bind(done);
2548     } else {
2549       ShouldNotReachHere();
2550     }
2551   } else {
2552     Register rreg = right->as_register();
2553     assert(lreg == rax, "left register must be rax,");
2554     assert(rreg != rdx, "right register must not be rdx");
2555     assert(temp->as_register() == rdx, "tmp register must be rdx");
2556 
2557     move_regs(lreg, rax);
2558 
2559     int idivl_offset = __ corrected_idivl(rreg);
2560     add_debug_info_for_div0(idivl_offset, info);
2561     if (code == lir_irem) {
2562       move_regs(rdx, dreg); // result is in rdx
2563     } else {
2564       move_regs(rax, dreg);
2565     }
2566   }
2567 }
2568 
2569 
2570 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
2571   if (opr1->is_single_cpu()) {
2572     Register reg1 = opr1->as_register();
2573     if (opr2->is_single_cpu()) {
2574       // cpu register - cpu register
2575       if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) {
2576         __ cmpptr(reg1, opr2->as_register());
2577       } else {
2578         assert(opr2->type() != T_OBJECT && opr2->type() != T_ARRAY, "cmp int, oop?");
2579         __ cmpl(reg1, opr2->as_register());
2580       }
2581     } else if (opr2->is_stack()) {
2582       // cpu register - stack
2583       if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) {
2584         __ cmpptr(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2585       } else {
2586         __ cmpl(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2587       }
2588     } else if (opr2->is_constant()) {
2589       // cpu register - constant
2590       LIR_Const* c = opr2->as_constant_ptr();
2591       if (c->type() == T_INT) {
2592         __ cmpl(reg1, c->as_jint());
2593       } else if (c->type() == T_OBJECT || c->type() == T_ARRAY) {
2594         // In 64bit oops are single register
2595         jobject o = c->as_jobject();
2596         if (o == NULL) {
2597           __ cmpptr(reg1, (int32_t)NULL_WORD);
2598         } else {
2599 #ifdef _LP64
2600           __ movoop(rscratch1, o);
2601           __ cmpptr(reg1, rscratch1);
2602 #else
2603           __ cmpoop(reg1, c->as_jobject());
2604 #endif // _LP64
2605         }
2606       } else {
2607         ShouldNotReachHere();
2608       }
2609       // cpu register - address
2610     } else if (opr2->is_address()) {
2611       if (op->info() != NULL) {
2612         add_debug_info_for_null_check_here(op->info());
2613       }
2614       __ cmpl(reg1, as_Address(opr2->as_address_ptr()));
2615     } else {
2616       ShouldNotReachHere();
2617     }
2618 
2619   } else if(opr1->is_double_cpu()) {
2620     Register xlo = opr1->as_register_lo();
2621     Register xhi = opr1->as_register_hi();
2622     if (opr2->is_double_cpu()) {
2623 #ifdef _LP64
2624       __ cmpptr(xlo, opr2->as_register_lo());
2625 #else
2626       // cpu register - cpu register
2627       Register ylo = opr2->as_register_lo();
2628       Register yhi = opr2->as_register_hi();
2629       __ subl(xlo, ylo);
2630       __ sbbl(xhi, yhi);
2631       if (condition == lir_cond_equal || condition == lir_cond_notEqual) {
2632         __ orl(xhi, xlo);
2633       }
2634 #endif // _LP64
2635     } else if (opr2->is_constant()) {
2636       // cpu register - constant 0
2637       assert(opr2->as_jlong() == (jlong)0, "only handles zero");
2638 #ifdef _LP64
2639       __ cmpptr(xlo, (int32_t)opr2->as_jlong());
2640 #else
2641       assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "only handles equals case");
2642       __ orl(xhi, xlo);
2643 #endif // _LP64
2644     } else {
2645       ShouldNotReachHere();
2646     }
2647 
2648   } else if (opr1->is_single_xmm()) {
2649     XMMRegister reg1 = opr1->as_xmm_float_reg();
2650     if (opr2->is_single_xmm()) {
2651       // xmm register - xmm register
2652       __ ucomiss(reg1, opr2->as_xmm_float_reg());
2653     } else if (opr2->is_stack()) {
2654       // xmm register - stack
2655       __ ucomiss(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2656     } else if (opr2->is_constant()) {
2657       // xmm register - constant
2658       __ ucomiss(reg1, InternalAddress(float_constant(opr2->as_jfloat())));
2659     } else if (opr2->is_address()) {
2660       // xmm register - address
2661       if (op->info() != NULL) {
2662         add_debug_info_for_null_check_here(op->info());
2663       }
2664       __ ucomiss(reg1, as_Address(opr2->as_address_ptr()));
2665     } else {
2666       ShouldNotReachHere();
2667     }
2668 
2669   } else if (opr1->is_double_xmm()) {
2670     XMMRegister reg1 = opr1->as_xmm_double_reg();
2671     if (opr2->is_double_xmm()) {
2672       // xmm register - xmm register
2673       __ ucomisd(reg1, opr2->as_xmm_double_reg());
2674     } else if (opr2->is_stack()) {
2675       // xmm register - stack
2676       __ ucomisd(reg1, frame_map()->address_for_slot(opr2->double_stack_ix()));
2677     } else if (opr2->is_constant()) {
2678       // xmm register - constant
2679       __ ucomisd(reg1, InternalAddress(double_constant(opr2->as_jdouble())));
2680     } else if (opr2->is_address()) {
2681       // xmm register - address
2682       if (op->info() != NULL) {
2683         add_debug_info_for_null_check_here(op->info());
2684       }
2685       __ ucomisd(reg1, as_Address(opr2->pointer()->as_address()));
2686     } else {
2687       ShouldNotReachHere();
2688     }
2689 
2690   } else if(opr1->is_single_fpu() || opr1->is_double_fpu()) {
2691     assert(opr1->is_fpu_register() && opr1->fpu() == 0, "currently left-hand side must be on TOS (relax this restriction)");
2692     assert(opr2->is_fpu_register(), "both must be registers");
2693     __ fcmp(noreg, opr2->fpu(), op->fpu_pop_count() > 0, op->fpu_pop_count() > 1);
2694 
2695   } else if (opr1->is_address() && opr2->is_constant()) {
2696     LIR_Const* c = opr2->as_constant_ptr();
2697 #ifdef _LP64
2698     if (c->type() == T_OBJECT || c->type() == T_ARRAY) {
2699       assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "need to reverse");
2700       __ movoop(rscratch1, c->as_jobject());
2701     }
2702 #endif // LP64
2703     if (op->info() != NULL) {
2704       add_debug_info_for_null_check_here(op->info());
2705     }
2706     // special case: address - constant
2707     LIR_Address* addr = opr1->as_address_ptr();
2708     if (c->type() == T_INT) {
2709       __ cmpl(as_Address(addr), c->as_jint());
2710     } else if (c->type() == T_OBJECT || c->type() == T_ARRAY) {
2711 #ifdef _LP64
2712       // %%% Make this explode if addr isn't reachable until we figure out a
2713       // better strategy by giving noreg as the temp for as_Address
2714       __ cmpptr(rscratch1, as_Address(addr, noreg));
2715 #else
2716       __ cmpoop(as_Address(addr), c->as_jobject());
2717 #endif // _LP64
2718     } else {
2719       ShouldNotReachHere();
2720     }
2721 
2722   } else {
2723     ShouldNotReachHere();
2724   }
2725 }
2726 
2727 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op) {
2728   if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
2729     if (left->is_single_xmm()) {
2730       assert(right->is_single_xmm(), "must match");
2731       __ cmpss2int(left->as_xmm_float_reg(), right->as_xmm_float_reg(), dst->as_register(), code == lir_ucmp_fd2i);
2732     } else if (left->is_double_xmm()) {
2733       assert(right->is_double_xmm(), "must match");
2734       __ cmpsd2int(left->as_xmm_double_reg(), right->as_xmm_double_reg(), dst->as_register(), code == lir_ucmp_fd2i);
2735 
2736     } else {
2737       assert(left->is_single_fpu() || left->is_double_fpu(), "must be");
2738       assert(right->is_single_fpu() || right->is_double_fpu(), "must match");
2739 
2740       assert(left->fpu() == 0, "left must be on TOS");
2741       __ fcmp2int(dst->as_register(), code == lir_ucmp_fd2i, right->fpu(),
2742                   op->fpu_pop_count() > 0, op->fpu_pop_count() > 1);
2743     }
2744   } else {
2745     assert(code == lir_cmp_l2i, "check");
2746 #ifdef _LP64
2747     Label done;
2748     Register dest = dst->as_register();
2749     __ cmpptr(left->as_register_lo(), right->as_register_lo());
2750     __ movl(dest, -1);
2751     __ jccb(Assembler::less, done);
2752     __ set_byte_if_not_zero(dest);
2753     __ movzbl(dest, dest);
2754     __ bind(done);
2755 #else
2756     __ lcmp2int(left->as_register_hi(),
2757                 left->as_register_lo(),
2758                 right->as_register_hi(),
2759                 right->as_register_lo());
2760     move_regs(left->as_register_hi(), dst->as_register());
2761 #endif // _LP64
2762   }
2763 }
2764 
2765 
2766 void LIR_Assembler::align_call(LIR_Code code) {
2767   if (os::is_MP()) {
2768     // make sure that the displacement word of the call ends up word aligned
2769     int offset = __ offset();
2770     switch (code) {
2771       case lir_static_call:
2772       case lir_optvirtual_call:
2773       case lir_dynamic_call:
2774         offset += NativeCall::displacement_offset;
2775         break;
2776       case lir_icvirtual_call:
2777         offset += NativeCall::displacement_offset + NativeMovConstReg::instruction_size;
2778       break;
2779       case lir_virtual_call:  // currently, sparc-specific for niagara
2780       default: ShouldNotReachHere();
2781     }
2782     while (offset++ % BytesPerWord != 0) {
2783       __ nop();
2784     }
2785   }
2786 }
2787 
2788 
2789 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
2790   assert(!os::is_MP() || (__ offset() + NativeCall::displacement_offset) % BytesPerWord == 0,
2791          "must be aligned");
2792   __ call(AddressLiteral(op->addr(), rtype));
2793   add_call_info(code_offset(), op->info());
2794 }
2795 
2796 
2797 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
2798   RelocationHolder rh = virtual_call_Relocation::spec(pc());
2799   __ movoop(IC_Klass, (jobject)Universe::non_oop_word());
2800   assert(!os::is_MP() ||
2801          (__ offset() + NativeCall::displacement_offset) % BytesPerWord == 0,
2802          "must be aligned");
2803   __ call(AddressLiteral(op->addr(), rh));
2804   add_call_info(code_offset(), op->info());
2805 }
2806 
2807 
2808 /* Currently, vtable-dispatch is only enabled for sparc platforms */
2809 void LIR_Assembler::vtable_call(LIR_OpJavaCall* op) {
2810   ShouldNotReachHere();
2811 }
2812 
2813 
2814 void LIR_Assembler::emit_static_call_stub() {
2815   address call_pc = __ pc();
2816   address stub = __ start_a_stub(call_stub_size);
2817   if (stub == NULL) {
2818     bailout("static call stub overflow");
2819     return;
2820   }
2821 
2822   int start = __ offset();
2823   if (os::is_MP()) {
2824     // make sure that the displacement word of the call ends up word aligned
2825     int offset = __ offset() + NativeMovConstReg::instruction_size + NativeCall::displacement_offset;
2826     while (offset++ % BytesPerWord != 0) {
2827       __ nop();
2828     }
2829   }
2830   __ relocate(static_stub_Relocation::spec(call_pc));
2831   __ movoop(rbx, (jobject)NULL);
2832   // must be set to -1 at code generation time
2833   assert(!os::is_MP() || ((__ offset() + 1) % BytesPerWord) == 0, "must be aligned on MP");
2834   // On 64bit this will die since it will take a movq & jmp, must be only a jmp
2835   __ jump(RuntimeAddress(__ pc()));
2836 
2837   assert(__ offset() - start <= call_stub_size, "stub too big")
2838   __ end_a_stub();
2839 }
2840 
2841 
2842 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
2843   assert(exceptionOop->as_register() == rax, "must match");
2844   assert(exceptionPC->as_register() == rdx, "must match");
2845 
2846   // exception object is not added to oop map by LinearScan
2847   // (LinearScan assumes that no oops are in fixed registers)
2848   info->add_register_oop(exceptionOop);
2849   Runtime1::StubID unwind_id;
2850 
2851   // get current pc information
2852   // pc is only needed if the method has an exception handler, the unwind code does not need it.
2853   int pc_for_athrow_offset = __ offset();
2854   InternalAddress pc_for_athrow(__ pc());
2855   __ lea(exceptionPC->as_register(), pc_for_athrow);
2856   add_call_info(pc_for_athrow_offset, info); // for exception handler
2857 
2858   __ verify_not_null_oop(rax);
2859   // search an exception handler (rax: exception oop, rdx: throwing pc)
2860   if (compilation()->has_fpu_code()) {
2861     unwind_id = Runtime1::handle_exception_id;
2862   } else {
2863     unwind_id = Runtime1::handle_exception_nofpu_id;
2864   }
2865   __ call(RuntimeAddress(Runtime1::entry_for(unwind_id)));
2866 
2867   // enough room for two byte trap
2868   __ nop();
2869 }
2870 
2871 
2872 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
2873   assert(exceptionOop->as_register() == rax, "must match");
2874 
2875   __ jmp(_unwind_handler_entry);
2876 }
2877 
2878 
2879 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2880 
2881   // optimized version for linear scan:
2882   // * count must be already in ECX (guaranteed by LinearScan)
2883   // * left and dest must be equal
2884   // * tmp must be unused
2885   assert(count->as_register() == SHIFT_count, "count must be in ECX");
2886   assert(left == dest, "left and dest must be equal");
2887   assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
2888 
2889   if (left->is_single_cpu()) {
2890     Register value = left->as_register();
2891     assert(value != SHIFT_count, "left cannot be ECX");
2892 
2893     switch (code) {
2894       case lir_shl:  __ shll(value); break;
2895       case lir_shr:  __ sarl(value); break;
2896       case lir_ushr: __ shrl(value); break;
2897       default: ShouldNotReachHere();
2898     }
2899   } else if (left->is_double_cpu()) {
2900     Register lo = left->as_register_lo();
2901     Register hi = left->as_register_hi();
2902     assert(lo != SHIFT_count && hi != SHIFT_count, "left cannot be ECX");
2903 #ifdef _LP64
2904     switch (code) {
2905       case lir_shl:  __ shlptr(lo);        break;
2906       case lir_shr:  __ sarptr(lo);        break;
2907       case lir_ushr: __ shrptr(lo);        break;
2908       default: ShouldNotReachHere();
2909     }
2910 #else
2911 
2912     switch (code) {
2913       case lir_shl:  __ lshl(hi, lo);        break;
2914       case lir_shr:  __ lshr(hi, lo, true);  break;
2915       case lir_ushr: __ lshr(hi, lo, false); break;
2916       default: ShouldNotReachHere();
2917     }
2918 #endif // LP64
2919   } else {
2920     ShouldNotReachHere();
2921   }
2922 }
2923 
2924 
2925 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2926   if (dest->is_single_cpu()) {
2927     // first move left into dest so that left is not destroyed by the shift
2928     Register value = dest->as_register();
2929     count = count & 0x1F; // Java spec
2930 
2931     move_regs(left->as_register(), value);
2932     switch (code) {
2933       case lir_shl:  __ shll(value, count); break;
2934       case lir_shr:  __ sarl(value, count); break;
2935       case lir_ushr: __ shrl(value, count); break;
2936       default: ShouldNotReachHere();
2937     }
2938   } else if (dest->is_double_cpu()) {
2939 #ifndef _LP64
2940     Unimplemented();
2941 #else
2942     // first move left into dest so that left is not destroyed by the shift
2943     Register value = dest->as_register_lo();
2944     count = count & 0x1F; // Java spec
2945 
2946     move_regs(left->as_register_lo(), value);
2947     switch (code) {
2948       case lir_shl:  __ shlptr(value, count); break;
2949       case lir_shr:  __ sarptr(value, count); break;
2950       case lir_ushr: __ shrptr(value, count); break;
2951       default: ShouldNotReachHere();
2952     }
2953 #endif // _LP64
2954   } else {
2955     ShouldNotReachHere();
2956   }
2957 }
2958 
2959 
2960 void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) {
2961   assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2962   int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2963   assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2964   __ movptr (Address(rsp, offset_from_rsp_in_bytes), r);
2965 }
2966 
2967 
2968 void LIR_Assembler::store_parameter(jint c,     int offset_from_rsp_in_words) {
2969   assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2970   int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2971   assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2972   __ movptr (Address(rsp, offset_from_rsp_in_bytes), c);
2973 }
2974 
2975 
2976 void LIR_Assembler::store_parameter(jobject o,  int offset_from_rsp_in_words) {
2977   assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2978   int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2979   assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2980   __ movoop (Address(rsp, offset_from_rsp_in_bytes), o);
2981 }
2982 
2983 
2984 // This code replaces a call to arraycopy; no exception may
2985 // be thrown in this code, they must be thrown in the System.arraycopy
2986 // activation frame; we could save some checks if this would not be the case
2987 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
2988   ciArrayKlass* default_type = op->expected_type();
2989   Register src = op->src()->as_register();
2990   Register dst = op->dst()->as_register();
2991   Register src_pos = op->src_pos()->as_register();
2992   Register dst_pos = op->dst_pos()->as_register();
2993   Register length  = op->length()->as_register();
2994   Register tmp = op->tmp()->as_register();
2995 
2996   CodeStub* stub = op->stub();
2997   int flags = op->flags();
2998   BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL;
2999   if (basic_type == T_ARRAY) basic_type = T_OBJECT;
3000 
3001   // if we don't know anything or it's an object array, just go through the generic arraycopy
3002   if (default_type == NULL) {
3003     Label done;
3004     // save outgoing arguments on stack in case call to System.arraycopy is needed
3005     // HACK ALERT. This code used to push the parameters in a hardwired fashion
3006     // for interpreter calling conventions. Now we have to do it in new style conventions.
3007     // For the moment until C1 gets the new register allocator I just force all the
3008     // args to the right place (except the register args) and then on the back side
3009     // reload the register args properly if we go slow path. Yuck
3010 
3011     // These are proper for the calling convention
3012 
3013     store_parameter(length, 2);
3014     store_parameter(dst_pos, 1);
3015     store_parameter(dst, 0);
3016 
3017     // these are just temporary placements until we need to reload
3018     store_parameter(src_pos, 3);
3019     store_parameter(src, 4);
3020     NOT_LP64(assert(src == rcx && src_pos == rdx, "mismatch in calling convention");)
3021 
3022     address entry = CAST_FROM_FN_PTR(address, Runtime1::arraycopy);
3023 
3024     // pass arguments: may push as this is not a safepoint; SP must be fix at each safepoint
3025 #ifdef _LP64
3026     // The arguments are in java calling convention so we can trivially shift them to C
3027     // convention
3028     assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4);
3029     __ mov(c_rarg0, j_rarg0);
3030     assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4);
3031     __ mov(c_rarg1, j_rarg1);
3032     assert_different_registers(c_rarg2, j_rarg3, j_rarg4);
3033     __ mov(c_rarg2, j_rarg2);
3034     assert_different_registers(c_rarg3, j_rarg4);
3035     __ mov(c_rarg3, j_rarg3);
3036 #ifdef _WIN64
3037     // Allocate abi space for args but be sure to keep stack aligned
3038     __ subptr(rsp, 6*wordSize);
3039     store_parameter(j_rarg4, 4);
3040     __ call(RuntimeAddress(entry));
3041     __ addptr(rsp, 6*wordSize);
3042 #else
3043     __ mov(c_rarg4, j_rarg4);
3044     __ call(RuntimeAddress(entry));
3045 #endif // _WIN64
3046 #else
3047     __ push(length);
3048     __ push(dst_pos);
3049     __ push(dst);
3050     __ push(src_pos);
3051     __ push(src);
3052     __ call_VM_leaf(entry, 5); // removes pushed parameter from the stack
3053 
3054 #endif // _LP64
3055 
3056     __ cmpl(rax, 0);
3057     __ jcc(Assembler::equal, *stub->continuation());
3058 
3059     // Reload values from the stack so they are where the stub
3060     // expects them.
3061     __ movptr   (dst,     Address(rsp, 0*BytesPerWord));
3062     __ movptr   (dst_pos, Address(rsp, 1*BytesPerWord));
3063     __ movptr   (length,  Address(rsp, 2*BytesPerWord));
3064     __ movptr   (src_pos, Address(rsp, 3*BytesPerWord));
3065     __ movptr   (src,     Address(rsp, 4*BytesPerWord));
3066     __ jmp(*stub->entry());
3067 
3068     __ bind(*stub->continuation());
3069     return;
3070   }
3071 
3072   assert(default_type != NULL && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point");
3073 
3074   int elem_size = type2aelembytes(basic_type);
3075   int shift_amount;
3076   Address::ScaleFactor scale;
3077 
3078   switch (elem_size) {
3079     case 1 :
3080       shift_amount = 0;
3081       scale = Address::times_1;
3082       break;
3083     case 2 :
3084       shift_amount = 1;
3085       scale = Address::times_2;
3086       break;
3087     case 4 :
3088       shift_amount = 2;
3089       scale = Address::times_4;
3090       break;
3091     case 8 :
3092       shift_amount = 3;
3093       scale = Address::times_8;
3094       break;
3095     default:
3096       ShouldNotReachHere();
3097   }
3098 
3099   Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes());
3100   Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes());
3101   Address src_klass_addr = Address(src, oopDesc::klass_offset_in_bytes());
3102   Address dst_klass_addr = Address(dst, oopDesc::klass_offset_in_bytes());
3103 
3104   // length and pos's are all sign extended at this point on 64bit
3105 
3106   // test for NULL
3107   if (flags & LIR_OpArrayCopy::src_null_check) {
3108     __ testptr(src, src);
3109     __ jcc(Assembler::zero, *stub->entry());
3110   }
3111   if (flags & LIR_OpArrayCopy::dst_null_check) {
3112     __ testptr(dst, dst);
3113     __ jcc(Assembler::zero, *stub->entry());
3114   }
3115 
3116   // check if negative
3117   if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
3118     __ testl(src_pos, src_pos);
3119     __ jcc(Assembler::less, *stub->entry());
3120   }
3121   if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
3122     __ testl(dst_pos, dst_pos);
3123     __ jcc(Assembler::less, *stub->entry());
3124   }
3125   if (flags & LIR_OpArrayCopy::length_positive_check) {
3126     __ testl(length, length);
3127     __ jcc(Assembler::less, *stub->entry());
3128   }
3129 
3130   if (flags & LIR_OpArrayCopy::src_range_check) {
3131     __ lea(tmp, Address(src_pos, length, Address::times_1, 0));
3132     __ cmpl(tmp, src_length_addr);
3133     __ jcc(Assembler::above, *stub->entry());
3134   }
3135   if (flags & LIR_OpArrayCopy::dst_range_check) {
3136     __ lea(tmp, Address(dst_pos, length, Address::times_1, 0));
3137     __ cmpl(tmp, dst_length_addr);
3138     __ jcc(Assembler::above, *stub->entry());
3139   }
3140 
3141   if (flags & LIR_OpArrayCopy::type_check) {
3142     __ movptr(tmp, src_klass_addr);
3143     __ cmpptr(tmp, dst_klass_addr);
3144     __ jcc(Assembler::notEqual, *stub->entry());
3145   }
3146 
3147 #ifdef ASSERT
3148   if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
3149     // Sanity check the known type with the incoming class.  For the
3150     // primitive case the types must match exactly with src.klass and
3151     // dst.klass each exactly matching the default type.  For the
3152     // object array case, if no type check is needed then either the
3153     // dst type is exactly the expected type and the src type is a
3154     // subtype which we can't check or src is the same array as dst
3155     // but not necessarily exactly of type default_type.
3156     Label known_ok, halt;
3157     __ movoop(tmp, default_type->constant_encoding());
3158     if (basic_type != T_OBJECT) {
3159       __ cmpptr(tmp, dst_klass_addr);
3160       __ jcc(Assembler::notEqual, halt);
3161       __ cmpptr(tmp, src_klass_addr);
3162       __ jcc(Assembler::equal, known_ok);
3163     } else {
3164       __ cmpptr(tmp, dst_klass_addr);
3165       __ jcc(Assembler::equal, known_ok);
3166       __ cmpptr(src, dst);
3167       __ jcc(Assembler::equal, known_ok);
3168     }
3169     __ bind(halt);
3170     __ stop("incorrect type information in arraycopy");
3171     __ bind(known_ok);
3172   }
3173 #endif
3174 
3175   if (shift_amount > 0 && basic_type != T_OBJECT) {
3176     __ shlptr(length, shift_amount);
3177   }
3178 
3179 #ifdef _LP64
3180   assert_different_registers(c_rarg0, dst, dst_pos, length);
3181   __ movl2ptr(src_pos, src_pos); //higher 32bits must be null
3182   __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3183   assert_different_registers(c_rarg1, length);
3184   __ movl2ptr(dst_pos, dst_pos); //higher 32bits must be null
3185   __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3186   __ mov(c_rarg2, length);
3187 
3188 #else
3189   __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3190   store_parameter(tmp, 0);
3191   __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3192   store_parameter(tmp, 1);
3193   store_parameter(length, 2);
3194 #endif // _LP64
3195   if (basic_type == T_OBJECT) {
3196     __ call_VM_leaf(CAST_FROM_FN_PTR(address, Runtime1::oop_arraycopy), 0);
3197   } else {
3198     __ call_VM_leaf(CAST_FROM_FN_PTR(address, Runtime1::primitive_arraycopy), 0);
3199   }
3200 
3201   __ bind(*stub->continuation());
3202 }
3203 
3204 
3205 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
3206   Register obj = op->obj_opr()->as_register();  // may not be an oop
3207   Register hdr = op->hdr_opr()->as_register();
3208   Register lock = op->lock_opr()->as_register();
3209   if (!UseFastLocking) {
3210     __ jmp(*op->stub()->entry());
3211   } else if (op->code() == lir_lock) {
3212     Register scratch = noreg;
3213     if (UseBiasedLocking) {
3214       scratch = op->scratch_opr()->as_register();
3215     }
3216     assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
3217     // add debug info for NullPointerException only if one is possible
3218     int null_check_offset = __ lock_object(hdr, obj, lock, scratch, *op->stub()->entry());
3219     if (op->info() != NULL) {
3220       add_debug_info_for_null_check(null_check_offset, op->info());
3221     }
3222     // done
3223   } else if (op->code() == lir_unlock) {
3224     assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
3225     __ unlock_object(hdr, obj, lock, *op->stub()->entry());
3226   } else {
3227     Unimplemented();
3228   }
3229   __ bind(*op->stub()->continuation());
3230 }
3231 
3232 
3233 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
3234   ciMethod* method = op->profiled_method();
3235   int bci          = op->profiled_bci();
3236 
3237   // Update counter for all call types
3238   ciMethodData* md = method->method_data();
3239   if (md == NULL) {
3240     bailout("out of memory building methodDataOop");
3241     return;
3242   }
3243   ciProfileData* data = md->bci_to_data(bci);
3244   assert(data->is_CounterData(), "need CounterData for calls");
3245   assert(op->mdo()->is_single_cpu(),  "mdo must be allocated");
3246   Register mdo  = op->mdo()->as_register();
3247   __ movoop(mdo, md->constant_encoding());
3248   Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
3249   Bytecodes::Code bc = method->java_code_at_bci(bci);
3250   // Perform additional virtual call profiling for invokevirtual and
3251   // invokeinterface bytecodes
3252   if ((bc == Bytecodes::_invokevirtual || bc == Bytecodes::_invokeinterface) &&
3253       Tier1ProfileVirtualCalls) {
3254     assert(op->recv()->is_single_cpu(), "recv must be allocated");
3255     Register recv = op->recv()->as_register();
3256     assert_different_registers(mdo, recv);
3257     assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
3258     ciKlass* known_klass = op->known_holder();
3259     if (Tier1OptimizeVirtualCallProfiling && known_klass != NULL) {
3260       // We know the type that will be seen at this call site; we can
3261       // statically update the methodDataOop rather than needing to do
3262       // dynamic tests on the receiver type
3263 
3264       // NOTE: we should probably put a lock around this search to
3265       // avoid collisions by concurrent compilations
3266       ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
3267       uint i;
3268       for (i = 0; i < VirtualCallData::row_limit(); i++) {
3269         ciKlass* receiver = vc_data->receiver(i);
3270         if (known_klass->equals(receiver)) {
3271           Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
3272           __ addl(data_addr, DataLayout::counter_increment);
3273           return;
3274         }
3275       }
3276 
3277       // Receiver type not found in profile data; select an empty slot
3278 
3279       // Note that this is less efficient than it should be because it
3280       // always does a write to the receiver part of the
3281       // VirtualCallData rather than just the first time
3282       for (i = 0; i < VirtualCallData::row_limit(); i++) {
3283         ciKlass* receiver = vc_data->receiver(i);
3284         if (receiver == NULL) {
3285           Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)));
3286           __ movoop(recv_addr, known_klass->constant_encoding());
3287           Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
3288           __ addl(data_addr, DataLayout::counter_increment);
3289           return;
3290         }
3291       }
3292     } else {
3293       __ movptr(recv, Address(recv, oopDesc::klass_offset_in_bytes()));
3294       Label update_done;
3295       uint i;
3296       for (i = 0; i < VirtualCallData::row_limit(); i++) {
3297         Label next_test;
3298         // See if the receiver is receiver[n].
3299         __ cmpptr(recv, Address(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i))));
3300         __ jcc(Assembler::notEqual, next_test);
3301         Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
3302         __ addl(data_addr, DataLayout::counter_increment);
3303         __ jmp(update_done);
3304         __ bind(next_test);
3305       }
3306 
3307       // Didn't find receiver; find next empty slot and fill it in
3308       for (i = 0; i < VirtualCallData::row_limit(); i++) {
3309         Label next_test;
3310         Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)));
3311         __ cmpptr(recv_addr, (int32_t)NULL_WORD);
3312         __ jcc(Assembler::notEqual, next_test);
3313         __ movptr(recv_addr, recv);
3314         __ movl(Address(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i))), DataLayout::counter_increment);
3315         __ jmp(update_done);
3316         __ bind(next_test);
3317       }
3318       // Receiver did not match any saved receiver and there is no empty row for it.
3319       // Increment total counter to indicate polymorphic case.
3320       __ addl(counter_addr, DataLayout::counter_increment);
3321 
3322       __ bind(update_done);
3323     }
3324   } else {
3325     // Static call
3326     __ addl(counter_addr, DataLayout::counter_increment);
3327   }
3328 }
3329 
3330 
3331 void LIR_Assembler::emit_delay(LIR_OpDelay*) {
3332   Unimplemented();
3333 }
3334 
3335 
3336 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) {
3337   __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no));
3338 }
3339 
3340 
3341 void LIR_Assembler::align_backward_branch_target() {
3342   __ align(BytesPerWord);
3343 }
3344 
3345 
3346 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest) {
3347   if (left->is_single_cpu()) {
3348     __ negl(left->as_register());
3349     move_regs(left->as_register(), dest->as_register());
3350 
3351   } else if (left->is_double_cpu()) {
3352     Register lo = left->as_register_lo();
3353 #ifdef _LP64
3354     Register dst = dest->as_register_lo();
3355     __ movptr(dst, lo);
3356     __ negptr(dst);
3357 #else
3358     Register hi = left->as_register_hi();
3359     __ lneg(hi, lo);
3360     if (dest->as_register_lo() == hi) {
3361       assert(dest->as_register_hi() != lo, "destroying register");
3362       move_regs(hi, dest->as_register_hi());
3363       move_regs(lo, dest->as_register_lo());
3364     } else {
3365       move_regs(lo, dest->as_register_lo());
3366       move_regs(hi, dest->as_register_hi());
3367     }
3368 #endif // _LP64
3369 
3370   } else if (dest->is_single_xmm()) {
3371     if (left->as_xmm_float_reg() != dest->as_xmm_float_reg()) {
3372       __ movflt(dest->as_xmm_float_reg(), left->as_xmm_float_reg());
3373     }
3374     __ xorps(dest->as_xmm_float_reg(),
3375              ExternalAddress((address)float_signflip_pool));
3376 
3377   } else if (dest->is_double_xmm()) {
3378     if (left->as_xmm_double_reg() != dest->as_xmm_double_reg()) {
3379       __ movdbl(dest->as_xmm_double_reg(), left->as_xmm_double_reg());
3380     }
3381     __ xorpd(dest->as_xmm_double_reg(),
3382              ExternalAddress((address)double_signflip_pool));
3383 
3384   } else if (left->is_single_fpu() || left->is_double_fpu()) {
3385     assert(left->fpu() == 0, "arg must be on TOS");
3386     assert(dest->fpu() == 0, "dest must be TOS");
3387     __ fchs();
3388 
3389   } else {
3390     ShouldNotReachHere();
3391   }
3392 }
3393 
3394 
3395 void LIR_Assembler::leal(LIR_Opr addr, LIR_Opr dest) {
3396   assert(addr->is_address() && dest->is_register(), "check");
3397   Register reg;
3398   reg = dest->as_pointer_register();
3399   __ lea(reg, as_Address(addr->as_address_ptr()));
3400 }
3401 
3402 
3403 
3404 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
3405   assert(!tmp->is_valid(), "don't need temporary");
3406   __ call(RuntimeAddress(dest));
3407   if (info != NULL) {
3408     add_call_info_here(info);
3409   }
3410 }
3411 
3412 
3413 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
3414   assert(type == T_LONG, "only for volatile long fields");
3415 
3416   if (info != NULL) {
3417     add_debug_info_for_null_check_here(info);
3418   }
3419 
3420   if (src->is_double_xmm()) {
3421     if (dest->is_double_cpu()) {
3422 #ifdef _LP64
3423       __ movdq(dest->as_register_lo(), src->as_xmm_double_reg());
3424 #else
3425       __ movdl(dest->as_register_lo(), src->as_xmm_double_reg());
3426       __ psrlq(src->as_xmm_double_reg(), 32);
3427       __ movdl(dest->as_register_hi(), src->as_xmm_double_reg());
3428 #endif // _LP64
3429     } else if (dest->is_double_stack()) {
3430       __ movdbl(frame_map()->address_for_slot(dest->double_stack_ix()), src->as_xmm_double_reg());
3431     } else if (dest->is_address()) {
3432       __ movdbl(as_Address(dest->as_address_ptr()), src->as_xmm_double_reg());
3433     } else {
3434       ShouldNotReachHere();
3435     }
3436 
3437   } else if (dest->is_double_xmm()) {
3438     if (src->is_double_stack()) {
3439       __ movdbl(dest->as_xmm_double_reg(), frame_map()->address_for_slot(src->double_stack_ix()));
3440     } else if (src->is_address()) {
3441       __ movdbl(dest->as_xmm_double_reg(), as_Address(src->as_address_ptr()));
3442     } else {
3443       ShouldNotReachHere();
3444     }
3445 
3446   } else if (src->is_double_fpu()) {
3447     assert(src->fpu_regnrLo() == 0, "must be TOS");
3448     if (dest->is_double_stack()) {
3449       __ fistp_d(frame_map()->address_for_slot(dest->double_stack_ix()));
3450     } else if (dest->is_address()) {
3451       __ fistp_d(as_Address(dest->as_address_ptr()));
3452     } else {
3453       ShouldNotReachHere();
3454     }
3455 
3456   } else if (dest->is_double_fpu()) {
3457     assert(dest->fpu_regnrLo() == 0, "must be TOS");
3458     if (src->is_double_stack()) {
3459       __ fild_d(frame_map()->address_for_slot(src->double_stack_ix()));
3460     } else if (src->is_address()) {
3461       __ fild_d(as_Address(src->as_address_ptr()));
3462     } else {
3463       ShouldNotReachHere();
3464     }
3465   } else {
3466     ShouldNotReachHere();
3467   }
3468 }
3469 
3470 
3471 void LIR_Assembler::membar() {
3472   // QQQ sparc TSO uses this,
3473   __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad));
3474 }
3475 
3476 void LIR_Assembler::membar_acquire() {
3477   // No x86 machines currently require load fences
3478   // __ load_fence();
3479 }
3480 
3481 void LIR_Assembler::membar_release() {
3482   // No x86 machines currently require store fences
3483   // __ store_fence();
3484 }
3485 
3486 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
3487   assert(result_reg->is_register(), "check");
3488 #ifdef _LP64
3489   // __ get_thread(result_reg->as_register_lo());
3490   __ mov(result_reg->as_register(), r15_thread);
3491 #else
3492   __ get_thread(result_reg->as_register());
3493 #endif // _LP64
3494 }
3495 
3496 
3497 void LIR_Assembler::peephole(LIR_List*) {
3498   // do nothing for now
3499 }
3500 
3501 
3502 #undef __