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--- old/src/share/vm/c1/c1_LIR.cpp
+++ new/src/share/vm/c1/c1_LIR.cpp
1 1 /*
2 2 * Copyright 2000-2010 Sun Microsystems, Inc. All Rights Reserved.
3 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 4 *
5 5 * This code is free software; you can redistribute it and/or modify it
6 6 * under the terms of the GNU General Public License version 2 only, as
7 7 * published by the Free Software Foundation.
8 8 *
9 9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 12 * version 2 for more details (a copy is included in the LICENSE file that
13 13 * accompanied this code).
14 14 *
15 15 * You should have received a copy of the GNU General Public License version
16 16 * 2 along with this work; if not, write to the Free Software Foundation,
17 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 18 *
19 19 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
20 20 * CA 95054 USA or visit www.sun.com if you need additional information or
21 21 * have any questions.
22 22 *
23 23 */
24 24
25 25 # include "incls/_precompiled.incl"
26 26 # include "incls/_c1_LIR.cpp.incl"
27 27
28 28 Register LIR_OprDesc::as_register() const {
29 29 return FrameMap::cpu_rnr2reg(cpu_regnr());
30 30 }
31 31
32 32 Register LIR_OprDesc::as_register_lo() const {
33 33 return FrameMap::cpu_rnr2reg(cpu_regnrLo());
34 34 }
35 35
36 36 Register LIR_OprDesc::as_register_hi() const {
37 37 return FrameMap::cpu_rnr2reg(cpu_regnrHi());
38 38 }
39 39
40 40 #if defined(X86)
41 41
42 42 XMMRegister LIR_OprDesc::as_xmm_float_reg() const {
43 43 return FrameMap::nr2xmmreg(xmm_regnr());
44 44 }
45 45
46 46 XMMRegister LIR_OprDesc::as_xmm_double_reg() const {
47 47 assert(xmm_regnrLo() == xmm_regnrHi(), "assumed in calculation");
48 48 return FrameMap::nr2xmmreg(xmm_regnrLo());
49 49 }
50 50
51 51 #endif // X86
52 52
53 53
54 54 #ifdef SPARC
55 55
56 56 FloatRegister LIR_OprDesc::as_float_reg() const {
57 57 return FrameMap::nr2floatreg(fpu_regnr());
58 58 }
59 59
60 60 FloatRegister LIR_OprDesc::as_double_reg() const {
61 61 return FrameMap::nr2floatreg(fpu_regnrHi());
62 62 }
63 63
64 64 #endif
65 65
66 66 LIR_Opr LIR_OprFact::illegalOpr = LIR_OprFact::illegal();
67 67
68 68 LIR_Opr LIR_OprFact::value_type(ValueType* type) {
69 69 ValueTag tag = type->tag();
70 70 switch (tag) {
71 71 case objectTag : {
72 72 ClassConstant* c = type->as_ClassConstant();
73 73 if (c != NULL && !c->value()->is_loaded()) {
74 74 return LIR_OprFact::oopConst(NULL);
75 75 } else {
76 76 return LIR_OprFact::oopConst(type->as_ObjectType()->encoding());
77 77 }
78 78 }
79 79 case addressTag: return LIR_OprFact::addressConst(type->as_AddressConstant()->value());
80 80 case intTag : return LIR_OprFact::intConst(type->as_IntConstant()->value());
81 81 case floatTag : return LIR_OprFact::floatConst(type->as_FloatConstant()->value());
82 82 case longTag : return LIR_OprFact::longConst(type->as_LongConstant()->value());
83 83 case doubleTag : return LIR_OprFact::doubleConst(type->as_DoubleConstant()->value());
84 84 default: ShouldNotReachHere(); return LIR_OprFact::intConst(-1);
85 85 }
86 86 }
87 87
88 88
89 89 LIR_Opr LIR_OprFact::dummy_value_type(ValueType* type) {
90 90 switch (type->tag()) {
91 91 case objectTag: return LIR_OprFact::oopConst(NULL);
92 92 case addressTag:return LIR_OprFact::addressConst(0);
93 93 case intTag: return LIR_OprFact::intConst(0);
94 94 case floatTag: return LIR_OprFact::floatConst(0.0);
95 95 case longTag: return LIR_OprFact::longConst(0);
96 96 case doubleTag: return LIR_OprFact::doubleConst(0.0);
97 97 default: ShouldNotReachHere(); return LIR_OprFact::intConst(-1);
98 98 }
99 99 return illegalOpr;
100 100 }
101 101
102 102
103 103
104 104 //---------------------------------------------------
105 105
106 106
107 107 LIR_Address::Scale LIR_Address::scale(BasicType type) {
108 108 int elem_size = type2aelembytes(type);
109 109 switch (elem_size) {
110 110 case 1: return LIR_Address::times_1;
111 111 case 2: return LIR_Address::times_2;
112 112 case 4: return LIR_Address::times_4;
113 113 case 8: return LIR_Address::times_8;
114 114 }
115 115 ShouldNotReachHere();
116 116 return LIR_Address::times_1;
117 117 }
118 118
119 119
120 120 #ifndef PRODUCT
121 121 void LIR_Address::verify() const {
122 122 #ifdef SPARC
123 123 assert(scale() == times_1, "Scaled addressing mode not available on SPARC and should not be used");
124 124 assert(disp() == 0 || index()->is_illegal(), "can't have both");
125 125 #endif
126 126 #ifdef _LP64
127 127 assert(base()->is_cpu_register(), "wrong base operand");
128 128 assert(index()->is_illegal() || index()->is_double_cpu(), "wrong index operand");
129 129 assert(base()->type() == T_OBJECT || base()->type() == T_LONG,
130 130 "wrong type for addresses");
131 131 #else
132 132 assert(base()->is_single_cpu(), "wrong base operand");
133 133 assert(index()->is_illegal() || index()->is_single_cpu(), "wrong index operand");
134 134 assert(base()->type() == T_OBJECT || base()->type() == T_INT,
135 135 "wrong type for addresses");
136 136 #endif
137 137 }
138 138 #endif
139 139
140 140
141 141 //---------------------------------------------------
142 142
143 143 char LIR_OprDesc::type_char(BasicType t) {
144 144 switch (t) {
145 145 case T_ARRAY:
146 146 t = T_OBJECT;
147 147 case T_BOOLEAN:
148 148 case T_CHAR:
149 149 case T_FLOAT:
150 150 case T_DOUBLE:
151 151 case T_BYTE:
152 152 case T_SHORT:
153 153 case T_INT:
154 154 case T_LONG:
155 155 case T_OBJECT:
156 156 case T_ADDRESS:
157 157 case T_VOID:
158 158 return ::type2char(t);
159 159
160 160 case T_ILLEGAL:
161 161 return '?';
162 162
163 163 default:
164 164 ShouldNotReachHere();
165 165 return '?';
166 166 }
167 167 }
168 168
169 169 #ifndef PRODUCT
170 170 void LIR_OprDesc::validate_type() const {
171 171
172 172 #ifdef ASSERT
173 173 if (!is_pointer() && !is_illegal()) {
174 174 switch (as_BasicType(type_field())) {
175 175 case T_LONG:
176 176 assert((kind_field() == cpu_register || kind_field() == stack_value) && size_field() == double_size, "must match");
177 177 break;
178 178 case T_FLOAT:
179 179 assert((kind_field() == fpu_register || kind_field() == stack_value) && size_field() == single_size, "must match");
180 180 break;
181 181 case T_DOUBLE:
182 182 assert((kind_field() == fpu_register || kind_field() == stack_value) && size_field() == double_size, "must match");
183 183 break;
184 184 case T_BOOLEAN:
185 185 case T_CHAR:
186 186 case T_BYTE:
187 187 case T_SHORT:
188 188 case T_INT:
189 189 case T_OBJECT:
190 190 case T_ARRAY:
191 191 assert((kind_field() == cpu_register || kind_field() == stack_value) && size_field() == single_size, "must match");
192 192 break;
193 193
194 194 case T_ILLEGAL:
195 195 // XXX TKR also means unknown right now
196 196 // assert(is_illegal(), "must match");
197 197 break;
198 198
199 199 default:
200 200 ShouldNotReachHere();
201 201 }
202 202 }
203 203 #endif
204 204
205 205 }
206 206 #endif // PRODUCT
207 207
208 208
209 209 bool LIR_OprDesc::is_oop() const {
210 210 if (is_pointer()) {
211 211 return pointer()->is_oop_pointer();
212 212 } else {
213 213 OprType t= type_field();
214 214 assert(t != unknown_type, "not set");
215 215 return t == object_type;
216 216 }
217 217 }
218 218
219 219
220 220
221 221 void LIR_Op2::verify() const {
222 222 #ifdef ASSERT
223 223 switch (code()) {
224 224 case lir_cmove:
225 225 break;
226 226
227 227 default:
228 228 assert(!result_opr()->is_register() || !result_opr()->is_oop_register(),
229 229 "can't produce oops from arith");
230 230 }
231 231
232 232 if (TwoOperandLIRForm) {
233 233 switch (code()) {
234 234 case lir_add:
235 235 case lir_sub:
236 236 case lir_mul:
237 237 case lir_mul_strictfp:
238 238 case lir_div:
239 239 case lir_div_strictfp:
240 240 case lir_rem:
241 241 case lir_logic_and:
242 242 case lir_logic_or:
243 243 case lir_logic_xor:
244 244 case lir_shl:
245 245 case lir_shr:
246 246 assert(in_opr1() == result_opr(), "opr1 and result must match");
247 247 assert(in_opr1()->is_valid() && in_opr2()->is_valid(), "must be valid");
248 248 break;
249 249
250 250 // special handling for lir_ushr because of write barriers
251 251 case lir_ushr:
252 252 assert(in_opr1() == result_opr() || in_opr2()->is_constant(), "opr1 and result must match or shift count is constant");
253 253 assert(in_opr1()->is_valid() && in_opr2()->is_valid(), "must be valid");
254 254 break;
255 255
256 256 }
257 257 }
258 258 #endif
259 259 }
260 260
261 261
262 262 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BasicType type, BlockBegin* block)
263 263 : LIR_Op(lir_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL)
264 264 , _cond(cond)
265 265 , _type(type)
266 266 , _label(block->label())
267 267 , _block(block)
268 268 , _ublock(NULL)
269 269 , _stub(NULL) {
270 270 }
271 271
272 272 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BasicType type, CodeStub* stub) :
273 273 LIR_Op(lir_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL)
274 274 , _cond(cond)
275 275 , _type(type)
276 276 , _label(stub->entry())
277 277 , _block(NULL)
278 278 , _ublock(NULL)
279 279 , _stub(stub) {
280 280 }
281 281
282 282 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BasicType type, BlockBegin* block, BlockBegin* ublock)
283 283 : LIR_Op(lir_cond_float_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL)
284 284 , _cond(cond)
285 285 , _type(type)
286 286 , _label(block->label())
287 287 , _block(block)
288 288 , _ublock(ublock)
289 289 , _stub(NULL)
290 290 {
291 291 }
292 292
293 293 void LIR_OpBranch::change_block(BlockBegin* b) {
294 294 assert(_block != NULL, "must have old block");
295 295 assert(_block->label() == label(), "must be equal");
296 296
297 297 _block = b;
298 298 _label = b->label();
299 299 }
300 300
301 301 void LIR_OpBranch::change_ublock(BlockBegin* b) {
302 302 assert(_ublock != NULL, "must have old block");
303 303 _ublock = b;
304 304 }
305 305
306 306 void LIR_OpBranch::negate_cond() {
307 307 switch (_cond) {
308 308 case lir_cond_equal: _cond = lir_cond_notEqual; break;
309 309 case lir_cond_notEqual: _cond = lir_cond_equal; break;
310 310 case lir_cond_less: _cond = lir_cond_greaterEqual; break;
311 311 case lir_cond_lessEqual: _cond = lir_cond_greater; break;
312 312 case lir_cond_greaterEqual: _cond = lir_cond_less; break;
313 313 case lir_cond_greater: _cond = lir_cond_lessEqual; break;
314 314 default: ShouldNotReachHere();
315 315 }
316 316 }
317 317
318 318
319 319 LIR_OpTypeCheck::LIR_OpTypeCheck(LIR_Code code, LIR_Opr result, LIR_Opr object, ciKlass* klass,
320 320 LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3,
321 321 bool fast_check, CodeEmitInfo* info_for_exception, CodeEmitInfo* info_for_patch,
322 322 CodeStub* stub,
323 323 ciMethod* profiled_method,
324 324 int profiled_bci)
325 325 : LIR_Op(code, result, NULL)
326 326 , _object(object)
327 327 , _array(LIR_OprFact::illegalOpr)
328 328 , _klass(klass)
329 329 , _tmp1(tmp1)
330 330 , _tmp2(tmp2)
331 331 , _tmp3(tmp3)
332 332 , _fast_check(fast_check)
333 333 , _stub(stub)
334 334 , _info_for_patch(info_for_patch)
335 335 , _info_for_exception(info_for_exception)
336 336 , _profiled_method(profiled_method)
337 337 , _profiled_bci(profiled_bci) {
338 338 if (code == lir_checkcast) {
339 339 assert(info_for_exception != NULL, "checkcast throws exceptions");
340 340 } else if (code == lir_instanceof) {
341 341 assert(info_for_exception == NULL, "instanceof throws no exceptions");
342 342 } else {
343 343 ShouldNotReachHere();
344 344 }
345 345 }
346 346
347 347
348 348
349 349 LIR_OpTypeCheck::LIR_OpTypeCheck(LIR_Code code, LIR_Opr object, LIR_Opr array, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, CodeEmitInfo* info_for_exception, ciMethod* profiled_method, int profiled_bci)
350 350 : LIR_Op(code, LIR_OprFact::illegalOpr, NULL)
351 351 , _object(object)
352 352 , _array(array)
353 353 , _klass(NULL)
354 354 , _tmp1(tmp1)
355 355 , _tmp2(tmp2)
356 356 , _tmp3(tmp3)
357 357 , _fast_check(false)
358 358 , _stub(NULL)
359 359 , _info_for_patch(NULL)
360 360 , _info_for_exception(info_for_exception)
361 361 , _profiled_method(profiled_method)
362 362 , _profiled_bci(profiled_bci) {
363 363 if (code == lir_store_check) {
364 364 _stub = new ArrayStoreExceptionStub(info_for_exception);
365 365 assert(info_for_exception != NULL, "store_check throws exceptions");
366 366 } else {
367 367 ShouldNotReachHere();
368 368 }
369 369 }
370 370
371 371
372 372 LIR_OpArrayCopy::LIR_OpArrayCopy(LIR_Opr src, LIR_Opr src_pos, LIR_Opr dst, LIR_Opr dst_pos, LIR_Opr length,
373 373 LIR_Opr tmp, ciArrayKlass* expected_type, int flags, CodeEmitInfo* info)
374 374 : LIR_Op(lir_arraycopy, LIR_OprFact::illegalOpr, info)
375 375 , _tmp(tmp)
376 376 , _src(src)
377 377 , _src_pos(src_pos)
378 378 , _dst(dst)
379 379 , _dst_pos(dst_pos)
380 380 , _flags(flags)
381 381 , _expected_type(expected_type)
382 382 , _length(length) {
383 383 _stub = new ArrayCopyStub(this);
384 384 }
385 385
386 386
387 387 //-------------------verify--------------------------
388 388
389 389 void LIR_Op1::verify() const {
390 390 switch(code()) {
391 391 case lir_move:
392 392 assert(in_opr()->is_valid() && result_opr()->is_valid(), "must be");
393 393 break;
394 394 case lir_null_check:
395 395 assert(in_opr()->is_register(), "must be");
396 396 break;
397 397 case lir_return:
398 398 assert(in_opr()->is_register() || in_opr()->is_illegal(), "must be");
399 399 break;
400 400 }
401 401 }
402 402
403 403 void LIR_OpRTCall::verify() const {
404 404 assert(strcmp(Runtime1::name_for_address(addr()), "<unknown function>") != 0, "unknown function");
405 405 }
406 406
407 407 //-------------------visits--------------------------
408 408
409 409 // complete rework of LIR instruction visitor.
410 410 // The virtual calls for each instruction type is replaced by a big
411 411 // switch that adds the operands for each instruction
412 412
413 413 void LIR_OpVisitState::visit(LIR_Op* op) {
414 414 // copy information from the LIR_Op
415 415 reset();
416 416 set_op(op);
417 417
418 418 switch (op->code()) {
419 419
420 420 // LIR_Op0
421 421 case lir_word_align: // result and info always invalid
422 422 case lir_backwardbranch_target: // result and info always invalid
423 423 case lir_build_frame: // result and info always invalid
424 424 case lir_fpop_raw: // result and info always invalid
425 425 case lir_24bit_FPU: // result and info always invalid
426 426 case lir_reset_FPU: // result and info always invalid
427 427 case lir_breakpoint: // result and info always invalid
428 428 case lir_membar: // result and info always invalid
429 429 case lir_membar_acquire: // result and info always invalid
430 430 case lir_membar_release: // result and info always invalid
431 431 {
432 432 assert(op->as_Op0() != NULL, "must be");
433 433 assert(op->_info == NULL, "info not used by this instruction");
434 434 assert(op->_result->is_illegal(), "not used");
435 435 break;
436 436 }
437 437
438 438 case lir_nop: // may have info, result always invalid
439 439 case lir_std_entry: // may have result, info always invalid
440 440 case lir_osr_entry: // may have result, info always invalid
441 441 case lir_get_thread: // may have result, info always invalid
442 442 {
443 443 assert(op->as_Op0() != NULL, "must be");
444 444 if (op->_info != NULL) do_info(op->_info);
445 445 if (op->_result->is_valid()) do_output(op->_result);
446 446 break;
447 447 }
448 448
449 449
450 450 // LIR_OpLabel
451 451 case lir_label: // result and info always invalid
452 452 {
453 453 assert(op->as_OpLabel() != NULL, "must be");
454 454 assert(op->_info == NULL, "info not used by this instruction");
455 455 assert(op->_result->is_illegal(), "not used");
456 456 break;
457 457 }
458 458
459 459
460 460 // LIR_Op1
461 461 case lir_fxch: // input always valid, result and info always invalid
462 462 case lir_fld: // input always valid, result and info always invalid
463 463 case lir_ffree: // input always valid, result and info always invalid
464 464 case lir_push: // input always valid, result and info always invalid
465 465 case lir_pop: // input always valid, result and info always invalid
466 466 case lir_return: // input always valid, result and info always invalid
467 467 case lir_leal: // input and result always valid, info always invalid
468 468 case lir_neg: // input and result always valid, info always invalid
469 469 case lir_monaddr: // input and result always valid, info always invalid
470 470 case lir_null_check: // input and info always valid, result always invalid
471 471 case lir_move: // input and result always valid, may have info
472 472 case lir_prefetchr: // input always valid, result and info always invalid
473 473 case lir_prefetchw: // input always valid, result and info always invalid
474 474 {
475 475 assert(op->as_Op1() != NULL, "must be");
476 476 LIR_Op1* op1 = (LIR_Op1*)op;
477 477
478 478 if (op1->_info) do_info(op1->_info);
479 479 if (op1->_opr->is_valid()) do_input(op1->_opr);
480 480 if (op1->_result->is_valid()) do_output(op1->_result);
481 481
482 482 break;
483 483 }
484 484
485 485 case lir_safepoint:
486 486 {
487 487 assert(op->as_Op1() != NULL, "must be");
488 488 LIR_Op1* op1 = (LIR_Op1*)op;
489 489
490 490 assert(op1->_info != NULL, ""); do_info(op1->_info);
491 491 if (op1->_opr->is_valid()) do_temp(op1->_opr); // safepoints on SPARC need temporary register
492 492 assert(op1->_result->is_illegal(), "safepoint does not produce value");
493 493
494 494 break;
495 495 }
496 496
497 497 // LIR_OpConvert;
498 498 case lir_convert: // input and result always valid, info always invalid
499 499 {
500 500 assert(op->as_OpConvert() != NULL, "must be");
501 501 LIR_OpConvert* opConvert = (LIR_OpConvert*)op;
502 502
503 503 assert(opConvert->_info == NULL, "must be");
504 504 if (opConvert->_opr->is_valid()) do_input(opConvert->_opr);
505 505 if (opConvert->_result->is_valid()) do_output(opConvert->_result);
506 506 do_stub(opConvert->_stub);
507 507
508 508 break;
509 509 }
510 510
511 511 // LIR_OpBranch;
512 512 case lir_branch: // may have info, input and result register always invalid
513 513 case lir_cond_float_branch: // may have info, input and result register always invalid
514 514 {
515 515 assert(op->as_OpBranch() != NULL, "must be");
516 516 LIR_OpBranch* opBranch = (LIR_OpBranch*)op;
517 517
518 518 if (opBranch->_info != NULL) do_info(opBranch->_info);
519 519 assert(opBranch->_result->is_illegal(), "not used");
520 520 if (opBranch->_stub != NULL) opBranch->stub()->visit(this);
521 521
522 522 break;
523 523 }
524 524
525 525
526 526 // LIR_OpAllocObj
527 527 case lir_alloc_object:
528 528 {
529 529 assert(op->as_OpAllocObj() != NULL, "must be");
530 530 LIR_OpAllocObj* opAllocObj = (LIR_OpAllocObj*)op;
531 531
532 532 if (opAllocObj->_info) do_info(opAllocObj->_info);
533 533 if (opAllocObj->_opr->is_valid()) do_input(opAllocObj->_opr);
534 534 if (opAllocObj->_tmp1->is_valid()) do_temp(opAllocObj->_tmp1);
535 535 if (opAllocObj->_tmp2->is_valid()) do_temp(opAllocObj->_tmp2);
536 536 if (opAllocObj->_tmp3->is_valid()) do_temp(opAllocObj->_tmp3);
537 537 if (opAllocObj->_tmp4->is_valid()) do_temp(opAllocObj->_tmp4);
538 538 if (opAllocObj->_result->is_valid()) do_output(opAllocObj->_result);
539 539 do_stub(opAllocObj->_stub);
540 540 break;
541 541 }
542 542
543 543
544 544 // LIR_OpRoundFP;
545 545 case lir_roundfp: {
546 546 assert(op->as_OpRoundFP() != NULL, "must be");
547 547 LIR_OpRoundFP* opRoundFP = (LIR_OpRoundFP*)op;
548 548
549 549 assert(op->_info == NULL, "info not used by this instruction");
550 550 assert(opRoundFP->_tmp->is_illegal(), "not used");
551 551 do_input(opRoundFP->_opr);
552 552 do_output(opRoundFP->_result);
553 553
554 554 break;
555 555 }
556 556
557 557
558 558 // LIR_Op2
559 559 case lir_cmp:
560 560 case lir_cmp_l2i:
561 561 case lir_ucmp_fd2i:
562 562 case lir_cmp_fd2i:
563 563 case lir_add:
564 564 case lir_sub:
565 565 case lir_mul:
566 566 case lir_div:
567 567 case lir_rem:
568 568 case lir_sqrt:
569 569 case lir_abs:
570 570 case lir_logic_and:
571 571 case lir_logic_or:
572 572 case lir_logic_xor:
573 573 case lir_shl:
574 574 case lir_shr:
575 575 case lir_ushr:
576 576 {
577 577 assert(op->as_Op2() != NULL, "must be");
578 578 LIR_Op2* op2 = (LIR_Op2*)op;
579 579
580 580 if (op2->_info) do_info(op2->_info);
581 581 if (op2->_opr1->is_valid()) do_input(op2->_opr1);
582 582 if (op2->_opr2->is_valid()) do_input(op2->_opr2);
583 583 if (op2->_tmp->is_valid()) do_temp(op2->_tmp);
584 584 if (op2->_result->is_valid()) do_output(op2->_result);
585 585
586 586 break;
587 587 }
588 588
589 589 // special handling for cmove: right input operand must not be equal
590 590 // to the result operand, otherwise the backend fails
591 591 case lir_cmove:
592 592 {
593 593 assert(op->as_Op2() != NULL, "must be");
594 594 LIR_Op2* op2 = (LIR_Op2*)op;
595 595
596 596 assert(op2->_info == NULL && op2->_tmp->is_illegal(), "not used");
597 597 assert(op2->_opr1->is_valid() && op2->_opr2->is_valid() && op2->_result->is_valid(), "used");
598 598
599 599 do_input(op2->_opr1);
600 600 do_input(op2->_opr2);
601 601 do_temp(op2->_opr2);
602 602 do_output(op2->_result);
603 603
604 604 break;
605 605 }
606 606
607 607 // vspecial handling for strict operations: register input operands
608 608 // as temp to guarantee that they do not overlap with other
609 609 // registers
610 610 case lir_mul_strictfp:
611 611 case lir_div_strictfp:
612 612 {
613 613 assert(op->as_Op2() != NULL, "must be");
614 614 LIR_Op2* op2 = (LIR_Op2*)op;
615 615
616 616 assert(op2->_info == NULL, "not used");
617 617 assert(op2->_opr1->is_valid(), "used");
618 618 assert(op2->_opr2->is_valid(), "used");
619 619 assert(op2->_result->is_valid(), "used");
620 620
621 621 do_input(op2->_opr1); do_temp(op2->_opr1);
622 622 do_input(op2->_opr2); do_temp(op2->_opr2);
623 623 if (op2->_tmp->is_valid()) do_temp(op2->_tmp);
624 624 do_output(op2->_result);
625 625
626 626 break;
627 627 }
628 628
629 629 case lir_throw: {
630 630 assert(op->as_Op2() != NULL, "must be");
631 631 LIR_Op2* op2 = (LIR_Op2*)op;
632 632
633 633 if (op2->_info) do_info(op2->_info);
634 634 if (op2->_opr1->is_valid()) do_temp(op2->_opr1);
635 635 if (op2->_opr2->is_valid()) do_input(op2->_opr2); // exception object is input parameter
636 636 assert(op2->_result->is_illegal(), "no result");
637 637
638 638 break;
639 639 }
640 640
641 641 case lir_unwind: {
642 642 assert(op->as_Op1() != NULL, "must be");
643 643 LIR_Op1* op1 = (LIR_Op1*)op;
644 644
645 645 assert(op1->_info == NULL, "no info");
646 646 assert(op1->_opr->is_valid(), "exception oop"); do_input(op1->_opr);
647 647 assert(op1->_result->is_illegal(), "no result");
648 648
649 649 break;
650 650 }
651 651
652 652
653 653 case lir_tan:
654 654 case lir_sin:
655 655 case lir_cos:
656 656 case lir_log:
657 657 case lir_log10: {
658 658 assert(op->as_Op2() != NULL, "must be");
659 659 LIR_Op2* op2 = (LIR_Op2*)op;
660 660
661 661 // On x86 tan/sin/cos need two temporary fpu stack slots and
662 662 // log/log10 need one so handle opr2 and tmp as temp inputs.
663 663 // Register input operand as temp to guarantee that it doesn't
664 664 // overlap with the input.
665 665 assert(op2->_info == NULL, "not used");
666 666 assert(op2->_opr1->is_valid(), "used");
667 667 do_input(op2->_opr1); do_temp(op2->_opr1);
668 668
669 669 if (op2->_opr2->is_valid()) do_temp(op2->_opr2);
670 670 if (op2->_tmp->is_valid()) do_temp(op2->_tmp);
671 671 if (op2->_result->is_valid()) do_output(op2->_result);
672 672
673 673 break;
674 674 }
675 675
676 676
677 677 // LIR_Op3
678 678 case lir_idiv:
679 679 case lir_irem: {
680 680 assert(op->as_Op3() != NULL, "must be");
681 681 LIR_Op3* op3= (LIR_Op3*)op;
682 682
683 683 if (op3->_info) do_info(op3->_info);
684 684 if (op3->_opr1->is_valid()) do_input(op3->_opr1);
685 685
686 686 // second operand is input and temp, so ensure that second operand
687 687 // and third operand get not the same register
688 688 if (op3->_opr2->is_valid()) do_input(op3->_opr2);
689 689 if (op3->_opr2->is_valid()) do_temp(op3->_opr2);
690 690 if (op3->_opr3->is_valid()) do_temp(op3->_opr3);
691 691
692 692 if (op3->_result->is_valid()) do_output(op3->_result);
693 693
694 694 break;
695 695 }
696 696
697 697
698 698 // LIR_OpJavaCall
699 699 case lir_static_call:
700 700 case lir_optvirtual_call:
701 701 case lir_icvirtual_call:
702 702 case lir_virtual_call:
703 703 case lir_dynamic_call: {
704 704 LIR_OpJavaCall* opJavaCall = op->as_OpJavaCall();
705 705 assert(opJavaCall != NULL, "must be");
706 706
707 707 if (opJavaCall->_receiver->is_valid()) do_input(opJavaCall->_receiver);
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708 708
709 709 // only visit register parameters
710 710 int n = opJavaCall->_arguments->length();
711 711 for (int i = 0; i < n; i++) {
712 712 if (!opJavaCall->_arguments->at(i)->is_pointer()) {
713 713 do_input(*opJavaCall->_arguments->adr_at(i));
714 714 }
715 715 }
716 716
717 717 if (opJavaCall->_info) do_info(opJavaCall->_info);
718 - if (opJavaCall->is_method_handle_invoke()) do_temp(FrameMap::method_handle_invoke_SP_save_opr());
718 + if (opJavaCall->is_method_handle_invoke()) {
719 + LIR_Opr method_handle_invoke_SP_save_opr = FrameMap::method_handle_invoke_SP_save_opr();
720 + do_temp(method_handle_invoke_SP_save_opr);
721 + }
719 722 do_call();
720 723 if (opJavaCall->_result->is_valid()) do_output(opJavaCall->_result);
721 724
722 725 break;
723 726 }
724 727
725 728
726 729 // LIR_OpRTCall
727 730 case lir_rtcall: {
728 731 assert(op->as_OpRTCall() != NULL, "must be");
729 732 LIR_OpRTCall* opRTCall = (LIR_OpRTCall*)op;
730 733
731 734 // only visit register parameters
732 735 int n = opRTCall->_arguments->length();
733 736 for (int i = 0; i < n; i++) {
734 737 if (!opRTCall->_arguments->at(i)->is_pointer()) {
735 738 do_input(*opRTCall->_arguments->adr_at(i));
736 739 }
737 740 }
738 741 if (opRTCall->_info) do_info(opRTCall->_info);
739 742 if (opRTCall->_tmp->is_valid()) do_temp(opRTCall->_tmp);
740 743 do_call();
741 744 if (opRTCall->_result->is_valid()) do_output(opRTCall->_result);
742 745
743 746 break;
744 747 }
745 748
746 749
747 750 // LIR_OpArrayCopy
748 751 case lir_arraycopy: {
749 752 assert(op->as_OpArrayCopy() != NULL, "must be");
750 753 LIR_OpArrayCopy* opArrayCopy = (LIR_OpArrayCopy*)op;
751 754
752 755 assert(opArrayCopy->_result->is_illegal(), "unused");
753 756 assert(opArrayCopy->_src->is_valid(), "used"); do_input(opArrayCopy->_src); do_temp(opArrayCopy->_src);
754 757 assert(opArrayCopy->_src_pos->is_valid(), "used"); do_input(opArrayCopy->_src_pos); do_temp(opArrayCopy->_src_pos);
755 758 assert(opArrayCopy->_dst->is_valid(), "used"); do_input(opArrayCopy->_dst); do_temp(opArrayCopy->_dst);
756 759 assert(opArrayCopy->_dst_pos->is_valid(), "used"); do_input(opArrayCopy->_dst_pos); do_temp(opArrayCopy->_dst_pos);
757 760 assert(opArrayCopy->_length->is_valid(), "used"); do_input(opArrayCopy->_length); do_temp(opArrayCopy->_length);
758 761 assert(opArrayCopy->_tmp->is_valid(), "used"); do_temp(opArrayCopy->_tmp);
759 762 if (opArrayCopy->_info) do_info(opArrayCopy->_info);
760 763
761 764 // the implementation of arraycopy always has a call into the runtime
762 765 do_call();
763 766
764 767 break;
765 768 }
766 769
767 770
768 771 // LIR_OpLock
769 772 case lir_lock:
770 773 case lir_unlock: {
771 774 assert(op->as_OpLock() != NULL, "must be");
772 775 LIR_OpLock* opLock = (LIR_OpLock*)op;
773 776
774 777 if (opLock->_info) do_info(opLock->_info);
775 778
776 779 // TODO: check if these operands really have to be temp
777 780 // (or if input is sufficient). This may have influence on the oop map!
778 781 assert(opLock->_lock->is_valid(), "used"); do_temp(opLock->_lock);
779 782 assert(opLock->_hdr->is_valid(), "used"); do_temp(opLock->_hdr);
780 783 assert(opLock->_obj->is_valid(), "used"); do_temp(opLock->_obj);
781 784
782 785 if (opLock->_scratch->is_valid()) do_temp(opLock->_scratch);
783 786 assert(opLock->_result->is_illegal(), "unused");
784 787
785 788 do_stub(opLock->_stub);
786 789
787 790 break;
788 791 }
789 792
790 793
791 794 // LIR_OpDelay
792 795 case lir_delay_slot: {
793 796 assert(op->as_OpDelay() != NULL, "must be");
794 797 LIR_OpDelay* opDelay = (LIR_OpDelay*)op;
795 798
796 799 visit(opDelay->delay_op());
797 800 break;
798 801 }
799 802
800 803 // LIR_OpTypeCheck
801 804 case lir_instanceof:
802 805 case lir_checkcast:
803 806 case lir_store_check: {
804 807 assert(op->as_OpTypeCheck() != NULL, "must be");
805 808 LIR_OpTypeCheck* opTypeCheck = (LIR_OpTypeCheck*)op;
806 809
807 810 if (opTypeCheck->_info_for_exception) do_info(opTypeCheck->_info_for_exception);
808 811 if (opTypeCheck->_info_for_patch) do_info(opTypeCheck->_info_for_patch);
809 812 if (opTypeCheck->_object->is_valid()) do_input(opTypeCheck->_object);
810 813 if (opTypeCheck->_array->is_valid()) do_input(opTypeCheck->_array);
811 814 if (opTypeCheck->_tmp1->is_valid()) do_temp(opTypeCheck->_tmp1);
812 815 if (opTypeCheck->_tmp2->is_valid()) do_temp(opTypeCheck->_tmp2);
813 816 if (opTypeCheck->_tmp3->is_valid()) do_temp(opTypeCheck->_tmp3);
814 817 if (opTypeCheck->_result->is_valid()) do_output(opTypeCheck->_result);
815 818 do_stub(opTypeCheck->_stub);
816 819 break;
817 820 }
818 821
819 822 // LIR_OpCompareAndSwap
820 823 case lir_cas_long:
821 824 case lir_cas_obj:
822 825 case lir_cas_int: {
823 826 assert(op->as_OpCompareAndSwap() != NULL, "must be");
824 827 LIR_OpCompareAndSwap* opCompareAndSwap = (LIR_OpCompareAndSwap*)op;
825 828
826 829 if (opCompareAndSwap->_info) do_info(opCompareAndSwap->_info);
827 830 if (opCompareAndSwap->_addr->is_valid()) do_input(opCompareAndSwap->_addr);
828 831 if (opCompareAndSwap->_cmp_value->is_valid()) do_input(opCompareAndSwap->_cmp_value);
829 832 if (opCompareAndSwap->_new_value->is_valid()) do_input(opCompareAndSwap->_new_value);
830 833 if (opCompareAndSwap->_tmp1->is_valid()) do_temp(opCompareAndSwap->_tmp1);
831 834 if (opCompareAndSwap->_tmp2->is_valid()) do_temp(opCompareAndSwap->_tmp2);
832 835 if (opCompareAndSwap->_result->is_valid()) do_output(opCompareAndSwap->_result);
833 836
834 837 break;
835 838 }
836 839
837 840
838 841 // LIR_OpAllocArray;
839 842 case lir_alloc_array: {
840 843 assert(op->as_OpAllocArray() != NULL, "must be");
841 844 LIR_OpAllocArray* opAllocArray = (LIR_OpAllocArray*)op;
842 845
843 846 if (opAllocArray->_info) do_info(opAllocArray->_info);
844 847 if (opAllocArray->_klass->is_valid()) do_input(opAllocArray->_klass); do_temp(opAllocArray->_klass);
845 848 if (opAllocArray->_len->is_valid()) do_input(opAllocArray->_len); do_temp(opAllocArray->_len);
846 849 if (opAllocArray->_tmp1->is_valid()) do_temp(opAllocArray->_tmp1);
847 850 if (opAllocArray->_tmp2->is_valid()) do_temp(opAllocArray->_tmp2);
848 851 if (opAllocArray->_tmp3->is_valid()) do_temp(opAllocArray->_tmp3);
849 852 if (opAllocArray->_tmp4->is_valid()) do_temp(opAllocArray->_tmp4);
850 853 if (opAllocArray->_result->is_valid()) do_output(opAllocArray->_result);
851 854 do_stub(opAllocArray->_stub);
852 855 break;
853 856 }
854 857
855 858 // LIR_OpProfileCall:
856 859 case lir_profile_call: {
857 860 assert(op->as_OpProfileCall() != NULL, "must be");
858 861 LIR_OpProfileCall* opProfileCall = (LIR_OpProfileCall*)op;
859 862
860 863 if (opProfileCall->_recv->is_valid()) do_temp(opProfileCall->_recv);
861 864 assert(opProfileCall->_mdo->is_valid(), "used"); do_temp(opProfileCall->_mdo);
862 865 assert(opProfileCall->_tmp1->is_valid(), "used"); do_temp(opProfileCall->_tmp1);
863 866 break;
864 867 }
865 868
866 869 default:
867 870 ShouldNotReachHere();
868 871 }
869 872 }
870 873
871 874
872 875 void LIR_OpVisitState::do_stub(CodeStub* stub) {
873 876 if (stub != NULL) {
874 877 stub->visit(this);
875 878 }
876 879 }
877 880
878 881 XHandlers* LIR_OpVisitState::all_xhandler() {
879 882 XHandlers* result = NULL;
880 883
881 884 int i;
882 885 for (i = 0; i < info_count(); i++) {
883 886 if (info_at(i)->exception_handlers() != NULL) {
884 887 result = info_at(i)->exception_handlers();
885 888 break;
886 889 }
887 890 }
888 891
889 892 #ifdef ASSERT
890 893 for (i = 0; i < info_count(); i++) {
891 894 assert(info_at(i)->exception_handlers() == NULL ||
892 895 info_at(i)->exception_handlers() == result,
893 896 "only one xhandler list allowed per LIR-operation");
894 897 }
895 898 #endif
896 899
897 900 if (result != NULL) {
898 901 return result;
899 902 } else {
900 903 return new XHandlers();
901 904 }
902 905
903 906 return result;
904 907 }
905 908
906 909
907 910 #ifdef ASSERT
908 911 bool LIR_OpVisitState::no_operands(LIR_Op* op) {
909 912 visit(op);
910 913
911 914 return opr_count(inputMode) == 0 &&
912 915 opr_count(outputMode) == 0 &&
913 916 opr_count(tempMode) == 0 &&
914 917 info_count() == 0 &&
915 918 !has_call() &&
916 919 !has_slow_case();
917 920 }
918 921 #endif
919 922
920 923 //---------------------------------------------------
921 924
922 925
923 926 void LIR_OpJavaCall::emit_code(LIR_Assembler* masm) {
924 927 masm->emit_call(this);
925 928 }
926 929
927 930 void LIR_OpRTCall::emit_code(LIR_Assembler* masm) {
928 931 masm->emit_rtcall(this);
929 932 }
930 933
931 934 void LIR_OpLabel::emit_code(LIR_Assembler* masm) {
932 935 masm->emit_opLabel(this);
933 936 }
934 937
935 938 void LIR_OpArrayCopy::emit_code(LIR_Assembler* masm) {
936 939 masm->emit_arraycopy(this);
937 940 masm->emit_code_stub(stub());
938 941 }
939 942
940 943 void LIR_Op0::emit_code(LIR_Assembler* masm) {
941 944 masm->emit_op0(this);
942 945 }
943 946
944 947 void LIR_Op1::emit_code(LIR_Assembler* masm) {
945 948 masm->emit_op1(this);
946 949 }
947 950
948 951 void LIR_OpAllocObj::emit_code(LIR_Assembler* masm) {
949 952 masm->emit_alloc_obj(this);
950 953 masm->emit_code_stub(stub());
951 954 }
952 955
953 956 void LIR_OpBranch::emit_code(LIR_Assembler* masm) {
954 957 masm->emit_opBranch(this);
955 958 if (stub()) {
956 959 masm->emit_code_stub(stub());
957 960 }
958 961 }
959 962
960 963 void LIR_OpConvert::emit_code(LIR_Assembler* masm) {
961 964 masm->emit_opConvert(this);
962 965 if (stub() != NULL) {
963 966 masm->emit_code_stub(stub());
964 967 }
965 968 }
966 969
967 970 void LIR_Op2::emit_code(LIR_Assembler* masm) {
968 971 masm->emit_op2(this);
969 972 }
970 973
971 974 void LIR_OpAllocArray::emit_code(LIR_Assembler* masm) {
972 975 masm->emit_alloc_array(this);
973 976 masm->emit_code_stub(stub());
974 977 }
975 978
976 979 void LIR_OpTypeCheck::emit_code(LIR_Assembler* masm) {
977 980 masm->emit_opTypeCheck(this);
978 981 if (stub()) {
979 982 masm->emit_code_stub(stub());
980 983 }
981 984 }
982 985
983 986 void LIR_OpCompareAndSwap::emit_code(LIR_Assembler* masm) {
984 987 masm->emit_compare_and_swap(this);
985 988 }
986 989
987 990 void LIR_Op3::emit_code(LIR_Assembler* masm) {
988 991 masm->emit_op3(this);
989 992 }
990 993
991 994 void LIR_OpLock::emit_code(LIR_Assembler* masm) {
992 995 masm->emit_lock(this);
993 996 if (stub()) {
994 997 masm->emit_code_stub(stub());
995 998 }
996 999 }
997 1000
998 1001
999 1002 void LIR_OpDelay::emit_code(LIR_Assembler* masm) {
1000 1003 masm->emit_delay(this);
1001 1004 }
1002 1005
1003 1006
1004 1007 void LIR_OpProfileCall::emit_code(LIR_Assembler* masm) {
1005 1008 masm->emit_profile_call(this);
1006 1009 }
1007 1010
1008 1011
1009 1012 // LIR_List
1010 1013 LIR_List::LIR_List(Compilation* compilation, BlockBegin* block)
1011 1014 : _operations(8)
1012 1015 , _compilation(compilation)
1013 1016 #ifndef PRODUCT
1014 1017 , _block(block)
1015 1018 #endif
1016 1019 #ifdef ASSERT
1017 1020 , _file(NULL)
1018 1021 , _line(0)
1019 1022 #endif
1020 1023 { }
1021 1024
1022 1025
1023 1026 #ifdef ASSERT
1024 1027 void LIR_List::set_file_and_line(const char * file, int line) {
1025 1028 const char * f = strrchr(file, '/');
1026 1029 if (f == NULL) f = strrchr(file, '\\');
1027 1030 if (f == NULL) {
1028 1031 f = file;
1029 1032 } else {
1030 1033 f++;
1031 1034 }
1032 1035 _file = f;
1033 1036 _line = line;
1034 1037 }
1035 1038 #endif
1036 1039
1037 1040
1038 1041 void LIR_List::append(LIR_InsertionBuffer* buffer) {
1039 1042 assert(this == buffer->lir_list(), "wrong lir list");
1040 1043 const int n = _operations.length();
1041 1044
1042 1045 if (buffer->number_of_ops() > 0) {
1043 1046 // increase size of instructions list
1044 1047 _operations.at_grow(n + buffer->number_of_ops() - 1, NULL);
1045 1048 // insert ops from buffer into instructions list
1046 1049 int op_index = buffer->number_of_ops() - 1;
1047 1050 int ip_index = buffer->number_of_insertion_points() - 1;
1048 1051 int from_index = n - 1;
1049 1052 int to_index = _operations.length() - 1;
1050 1053 for (; ip_index >= 0; ip_index --) {
1051 1054 int index = buffer->index_at(ip_index);
1052 1055 // make room after insertion point
1053 1056 while (index < from_index) {
1054 1057 _operations.at_put(to_index --, _operations.at(from_index --));
1055 1058 }
1056 1059 // insert ops from buffer
1057 1060 for (int i = buffer->count_at(ip_index); i > 0; i --) {
1058 1061 _operations.at_put(to_index --, buffer->op_at(op_index --));
1059 1062 }
1060 1063 }
1061 1064 }
1062 1065
1063 1066 buffer->finish();
1064 1067 }
1065 1068
1066 1069
1067 1070 void LIR_List::oop2reg_patch(jobject o, LIR_Opr reg, CodeEmitInfo* info) {
1068 1071 append(new LIR_Op1(lir_move, LIR_OprFact::oopConst(o), reg, T_OBJECT, lir_patch_normal, info));
1069 1072 }
1070 1073
1071 1074
1072 1075 void LIR_List::load(LIR_Address* addr, LIR_Opr src, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1073 1076 append(new LIR_Op1(
1074 1077 lir_move,
1075 1078 LIR_OprFact::address(addr),
1076 1079 src,
1077 1080 addr->type(),
1078 1081 patch_code,
1079 1082 info));
1080 1083 }
1081 1084
1082 1085
1083 1086 void LIR_List::volatile_load_mem_reg(LIR_Address* address, LIR_Opr dst, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1084 1087 append(new LIR_Op1(
1085 1088 lir_move,
1086 1089 LIR_OprFact::address(address),
1087 1090 dst,
1088 1091 address->type(),
1089 1092 patch_code,
1090 1093 info, lir_move_volatile));
1091 1094 }
1092 1095
1093 1096 void LIR_List::volatile_load_unsafe_reg(LIR_Opr base, LIR_Opr offset, LIR_Opr dst, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1094 1097 append(new LIR_Op1(
1095 1098 lir_move,
1096 1099 LIR_OprFact::address(new LIR_Address(base, offset, type)),
1097 1100 dst,
1098 1101 type,
1099 1102 patch_code,
1100 1103 info, lir_move_volatile));
1101 1104 }
1102 1105
1103 1106
1104 1107 void LIR_List::prefetch(LIR_Address* addr, bool is_store) {
1105 1108 append(new LIR_Op1(
1106 1109 is_store ? lir_prefetchw : lir_prefetchr,
1107 1110 LIR_OprFact::address(addr)));
1108 1111 }
1109 1112
1110 1113
1111 1114 void LIR_List::store_mem_int(jint v, LIR_Opr base, int offset_in_bytes, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1112 1115 append(new LIR_Op1(
1113 1116 lir_move,
1114 1117 LIR_OprFact::intConst(v),
1115 1118 LIR_OprFact::address(new LIR_Address(base, offset_in_bytes, type)),
1116 1119 type,
1117 1120 patch_code,
1118 1121 info));
1119 1122 }
1120 1123
1121 1124
1122 1125 void LIR_List::store_mem_oop(jobject o, LIR_Opr base, int offset_in_bytes, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1123 1126 append(new LIR_Op1(
1124 1127 lir_move,
1125 1128 LIR_OprFact::oopConst(o),
1126 1129 LIR_OprFact::address(new LIR_Address(base, offset_in_bytes, type)),
1127 1130 type,
1128 1131 patch_code,
1129 1132 info));
1130 1133 }
1131 1134
1132 1135
1133 1136 void LIR_List::store(LIR_Opr src, LIR_Address* addr, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1134 1137 append(new LIR_Op1(
1135 1138 lir_move,
1136 1139 src,
1137 1140 LIR_OprFact::address(addr),
1138 1141 addr->type(),
1139 1142 patch_code,
1140 1143 info));
1141 1144 }
1142 1145
1143 1146
1144 1147 void LIR_List::volatile_store_mem_reg(LIR_Opr src, LIR_Address* addr, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1145 1148 append(new LIR_Op1(
1146 1149 lir_move,
1147 1150 src,
1148 1151 LIR_OprFact::address(addr),
1149 1152 addr->type(),
1150 1153 patch_code,
1151 1154 info,
1152 1155 lir_move_volatile));
1153 1156 }
1154 1157
1155 1158 void LIR_List::volatile_store_unsafe_reg(LIR_Opr src, LIR_Opr base, LIR_Opr offset, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1156 1159 append(new LIR_Op1(
1157 1160 lir_move,
1158 1161 src,
1159 1162 LIR_OprFact::address(new LIR_Address(base, offset, type)),
1160 1163 type,
1161 1164 patch_code,
1162 1165 info, lir_move_volatile));
1163 1166 }
1164 1167
1165 1168
1166 1169 void LIR_List::idiv(LIR_Opr left, LIR_Opr right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) {
1167 1170 append(new LIR_Op3(
1168 1171 lir_idiv,
1169 1172 left,
1170 1173 right,
1171 1174 tmp,
1172 1175 res,
1173 1176 info));
1174 1177 }
1175 1178
1176 1179
1177 1180 void LIR_List::idiv(LIR_Opr left, int right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) {
1178 1181 append(new LIR_Op3(
1179 1182 lir_idiv,
1180 1183 left,
1181 1184 LIR_OprFact::intConst(right),
1182 1185 tmp,
1183 1186 res,
1184 1187 info));
1185 1188 }
1186 1189
1187 1190
1188 1191 void LIR_List::irem(LIR_Opr left, LIR_Opr right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) {
1189 1192 append(new LIR_Op3(
1190 1193 lir_irem,
1191 1194 left,
1192 1195 right,
1193 1196 tmp,
1194 1197 res,
1195 1198 info));
1196 1199 }
1197 1200
1198 1201
1199 1202 void LIR_List::irem(LIR_Opr left, int right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) {
1200 1203 append(new LIR_Op3(
1201 1204 lir_irem,
1202 1205 left,
1203 1206 LIR_OprFact::intConst(right),
1204 1207 tmp,
1205 1208 res,
1206 1209 info));
1207 1210 }
1208 1211
1209 1212
1210 1213 void LIR_List::cmp_mem_int(LIR_Condition condition, LIR_Opr base, int disp, int c, CodeEmitInfo* info) {
1211 1214 append(new LIR_Op2(
1212 1215 lir_cmp,
1213 1216 condition,
1214 1217 LIR_OprFact::address(new LIR_Address(base, disp, T_INT)),
1215 1218 LIR_OprFact::intConst(c),
1216 1219 info));
1217 1220 }
1218 1221
1219 1222
1220 1223 void LIR_List::cmp_reg_mem(LIR_Condition condition, LIR_Opr reg, LIR_Address* addr, CodeEmitInfo* info) {
1221 1224 append(new LIR_Op2(
1222 1225 lir_cmp,
1223 1226 condition,
1224 1227 reg,
1225 1228 LIR_OprFact::address(addr),
1226 1229 info));
1227 1230 }
1228 1231
1229 1232 void LIR_List::allocate_object(LIR_Opr dst, LIR_Opr t1, LIR_Opr t2, LIR_Opr t3, LIR_Opr t4,
1230 1233 int header_size, int object_size, LIR_Opr klass, bool init_check, CodeStub* stub) {
1231 1234 append(new LIR_OpAllocObj(
1232 1235 klass,
1233 1236 dst,
1234 1237 t1,
1235 1238 t2,
1236 1239 t3,
1237 1240 t4,
1238 1241 header_size,
1239 1242 object_size,
1240 1243 init_check,
1241 1244 stub));
1242 1245 }
1243 1246
1244 1247 void LIR_List::allocate_array(LIR_Opr dst, LIR_Opr len, LIR_Opr t1,LIR_Opr t2, LIR_Opr t3,LIR_Opr t4, BasicType type, LIR_Opr klass, CodeStub* stub) {
1245 1248 append(new LIR_OpAllocArray(
1246 1249 klass,
1247 1250 len,
1248 1251 dst,
1249 1252 t1,
1250 1253 t2,
1251 1254 t3,
1252 1255 t4,
1253 1256 type,
1254 1257 stub));
1255 1258 }
1256 1259
1257 1260 void LIR_List::shift_left(LIR_Opr value, LIR_Opr count, LIR_Opr dst, LIR_Opr tmp) {
1258 1261 append(new LIR_Op2(
1259 1262 lir_shl,
1260 1263 value,
1261 1264 count,
1262 1265 dst,
1263 1266 tmp));
1264 1267 }
1265 1268
1266 1269 void LIR_List::shift_right(LIR_Opr value, LIR_Opr count, LIR_Opr dst, LIR_Opr tmp) {
1267 1270 append(new LIR_Op2(
1268 1271 lir_shr,
1269 1272 value,
1270 1273 count,
1271 1274 dst,
1272 1275 tmp));
1273 1276 }
1274 1277
1275 1278
1276 1279 void LIR_List::unsigned_shift_right(LIR_Opr value, LIR_Opr count, LIR_Opr dst, LIR_Opr tmp) {
1277 1280 append(new LIR_Op2(
1278 1281 lir_ushr,
1279 1282 value,
1280 1283 count,
1281 1284 dst,
1282 1285 tmp));
1283 1286 }
1284 1287
1285 1288 void LIR_List::fcmp2int(LIR_Opr left, LIR_Opr right, LIR_Opr dst, bool is_unordered_less) {
1286 1289 append(new LIR_Op2(is_unordered_less ? lir_ucmp_fd2i : lir_cmp_fd2i,
1287 1290 left,
1288 1291 right,
1289 1292 dst));
1290 1293 }
1291 1294
1292 1295 void LIR_List::lock_object(LIR_Opr hdr, LIR_Opr obj, LIR_Opr lock, LIR_Opr scratch, CodeStub* stub, CodeEmitInfo* info) {
1293 1296 append(new LIR_OpLock(
1294 1297 lir_lock,
1295 1298 hdr,
1296 1299 obj,
1297 1300 lock,
1298 1301 scratch,
1299 1302 stub,
1300 1303 info));
1301 1304 }
1302 1305
1303 1306 void LIR_List::unlock_object(LIR_Opr hdr, LIR_Opr obj, LIR_Opr lock, CodeStub* stub) {
1304 1307 append(new LIR_OpLock(
1305 1308 lir_unlock,
1306 1309 hdr,
1307 1310 obj,
1308 1311 lock,
1309 1312 LIR_OprFact::illegalOpr,
1310 1313 stub,
1311 1314 NULL));
1312 1315 }
1313 1316
1314 1317
1315 1318 void check_LIR() {
1316 1319 // cannot do the proper checking as PRODUCT and other modes return different results
1317 1320 // guarantee(sizeof(LIR_OprDesc) == wordSize, "may not have a v-table");
1318 1321 }
1319 1322
1320 1323
1321 1324
1322 1325 void LIR_List::checkcast (LIR_Opr result, LIR_Opr object, ciKlass* klass,
1323 1326 LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, bool fast_check,
1324 1327 CodeEmitInfo* info_for_exception, CodeEmitInfo* info_for_patch, CodeStub* stub,
1325 1328 ciMethod* profiled_method, int profiled_bci) {
1326 1329 append(new LIR_OpTypeCheck(lir_checkcast, result, object, klass,
1327 1330 tmp1, tmp2, tmp3, fast_check, info_for_exception, info_for_patch, stub,
1328 1331 profiled_method, profiled_bci));
1329 1332 }
1330 1333
1331 1334
1332 1335 void LIR_List::instanceof(LIR_Opr result, LIR_Opr object, ciKlass* klass, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, bool fast_check, CodeEmitInfo* info_for_patch) {
1333 1336 append(new LIR_OpTypeCheck(lir_instanceof, result, object, klass, tmp1, tmp2, tmp3, fast_check, NULL, info_for_patch, NULL, NULL, 0));
1334 1337 }
1335 1338
1336 1339
1337 1340 void LIR_List::store_check(LIR_Opr object, LIR_Opr array, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, CodeEmitInfo* info_for_exception) {
1338 1341 append(new LIR_OpTypeCheck(lir_store_check, object, array, tmp1, tmp2, tmp3, info_for_exception, NULL, 0));
1339 1342 }
1340 1343
1341 1344
1342 1345 void LIR_List::cas_long(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value, LIR_Opr t1, LIR_Opr t2) {
1343 1346 // Compare and swap produces condition code "zero" if contents_of(addr) == cmp_value,
1344 1347 // implying successful swap of new_value into addr
1345 1348 append(new LIR_OpCompareAndSwap(lir_cas_long, addr, cmp_value, new_value, t1, t2));
1346 1349 }
1347 1350
1348 1351 void LIR_List::cas_obj(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value, LIR_Opr t1, LIR_Opr t2) {
1349 1352 // Compare and swap produces condition code "zero" if contents_of(addr) == cmp_value,
1350 1353 // implying successful swap of new_value into addr
1351 1354 append(new LIR_OpCompareAndSwap(lir_cas_obj, addr, cmp_value, new_value, t1, t2));
1352 1355 }
1353 1356
1354 1357 void LIR_List::cas_int(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value, LIR_Opr t1, LIR_Opr t2) {
1355 1358 // Compare and swap produces condition code "zero" if contents_of(addr) == cmp_value,
1356 1359 // implying successful swap of new_value into addr
1357 1360 append(new LIR_OpCompareAndSwap(lir_cas_int, addr, cmp_value, new_value, t1, t2));
1358 1361 }
1359 1362
1360 1363
1361 1364 #ifdef PRODUCT
1362 1365
1363 1366 void print_LIR(BlockList* blocks) {
1364 1367 }
1365 1368
1366 1369 #else
1367 1370 // LIR_OprDesc
1368 1371 void LIR_OprDesc::print() const {
1369 1372 print(tty);
1370 1373 }
1371 1374
1372 1375 void LIR_OprDesc::print(outputStream* out) const {
1373 1376 if (is_illegal()) {
1374 1377 return;
1375 1378 }
1376 1379
1377 1380 out->print("[");
1378 1381 if (is_pointer()) {
1379 1382 pointer()->print_value_on(out);
1380 1383 } else if (is_single_stack()) {
1381 1384 out->print("stack:%d", single_stack_ix());
1382 1385 } else if (is_double_stack()) {
1383 1386 out->print("dbl_stack:%d",double_stack_ix());
1384 1387 } else if (is_virtual()) {
1385 1388 out->print("R%d", vreg_number());
1386 1389 } else if (is_single_cpu()) {
1387 1390 out->print(as_register()->name());
1388 1391 } else if (is_double_cpu()) {
1389 1392 out->print(as_register_hi()->name());
1390 1393 out->print(as_register_lo()->name());
1391 1394 #if defined(X86)
1392 1395 } else if (is_single_xmm()) {
1393 1396 out->print(as_xmm_float_reg()->name());
1394 1397 } else if (is_double_xmm()) {
1395 1398 out->print(as_xmm_double_reg()->name());
1396 1399 } else if (is_single_fpu()) {
1397 1400 out->print("fpu%d", fpu_regnr());
1398 1401 } else if (is_double_fpu()) {
1399 1402 out->print("fpu%d", fpu_regnrLo());
1400 1403 #else
1401 1404 } else if (is_single_fpu()) {
1402 1405 out->print(as_float_reg()->name());
1403 1406 } else if (is_double_fpu()) {
1404 1407 out->print(as_double_reg()->name());
1405 1408 #endif
1406 1409
1407 1410 } else if (is_illegal()) {
1408 1411 out->print("-");
1409 1412 } else {
1410 1413 out->print("Unknown Operand");
1411 1414 }
1412 1415 if (!is_illegal()) {
1413 1416 out->print("|%c", type_char());
1414 1417 }
1415 1418 if (is_register() && is_last_use()) {
1416 1419 out->print("(last_use)");
1417 1420 }
1418 1421 out->print("]");
1419 1422 }
1420 1423
1421 1424
1422 1425 // LIR_Address
1423 1426 void LIR_Const::print_value_on(outputStream* out) const {
1424 1427 switch (type()) {
1425 1428 case T_ADDRESS:out->print("address:%d",as_jint()); break;
1426 1429 case T_INT: out->print("int:%d", as_jint()); break;
1427 1430 case T_LONG: out->print("lng:%lld", as_jlong()); break;
1428 1431 case T_FLOAT: out->print("flt:%f", as_jfloat()); break;
1429 1432 case T_DOUBLE: out->print("dbl:%f", as_jdouble()); break;
1430 1433 case T_OBJECT: out->print("obj:0x%x", as_jobject()); break;
1431 1434 default: out->print("%3d:0x%x",type(), as_jdouble()); break;
1432 1435 }
1433 1436 }
1434 1437
1435 1438 // LIR_Address
1436 1439 void LIR_Address::print_value_on(outputStream* out) const {
1437 1440 out->print("Base:"); _base->print(out);
1438 1441 if (!_index->is_illegal()) {
1439 1442 out->print(" Index:"); _index->print(out);
1440 1443 switch (scale()) {
1441 1444 case times_1: break;
1442 1445 case times_2: out->print(" * 2"); break;
1443 1446 case times_4: out->print(" * 4"); break;
1444 1447 case times_8: out->print(" * 8"); break;
1445 1448 }
1446 1449 }
1447 1450 out->print(" Disp: %d", _disp);
1448 1451 }
1449 1452
1450 1453 // debug output of block header without InstructionPrinter
1451 1454 // (because phi functions are not necessary for LIR)
1452 1455 static void print_block(BlockBegin* x) {
1453 1456 // print block id
1454 1457 BlockEnd* end = x->end();
1455 1458 tty->print("B%d ", x->block_id());
1456 1459
1457 1460 // print flags
1458 1461 if (x->is_set(BlockBegin::std_entry_flag)) tty->print("std ");
1459 1462 if (x->is_set(BlockBegin::osr_entry_flag)) tty->print("osr ");
1460 1463 if (x->is_set(BlockBegin::exception_entry_flag)) tty->print("ex ");
1461 1464 if (x->is_set(BlockBegin::subroutine_entry_flag)) tty->print("jsr ");
1462 1465 if (x->is_set(BlockBegin::backward_branch_target_flag)) tty->print("bb ");
1463 1466 if (x->is_set(BlockBegin::linear_scan_loop_header_flag)) tty->print("lh ");
1464 1467 if (x->is_set(BlockBegin::linear_scan_loop_end_flag)) tty->print("le ");
1465 1468
1466 1469 // print block bci range
1467 1470 tty->print("[%d, %d] ", x->bci(), (end == NULL ? -1 : end->bci()));
1468 1471
1469 1472 // print predecessors and successors
1470 1473 if (x->number_of_preds() > 0) {
1471 1474 tty->print("preds: ");
1472 1475 for (int i = 0; i < x->number_of_preds(); i ++) {
1473 1476 tty->print("B%d ", x->pred_at(i)->block_id());
1474 1477 }
1475 1478 }
1476 1479
1477 1480 if (x->number_of_sux() > 0) {
1478 1481 tty->print("sux: ");
1479 1482 for (int i = 0; i < x->number_of_sux(); i ++) {
1480 1483 tty->print("B%d ", x->sux_at(i)->block_id());
1481 1484 }
1482 1485 }
1483 1486
1484 1487 // print exception handlers
1485 1488 if (x->number_of_exception_handlers() > 0) {
1486 1489 tty->print("xhandler: ");
1487 1490 for (int i = 0; i < x->number_of_exception_handlers(); i++) {
1488 1491 tty->print("B%d ", x->exception_handler_at(i)->block_id());
1489 1492 }
1490 1493 }
1491 1494
1492 1495 tty->cr();
1493 1496 }
1494 1497
1495 1498 void print_LIR(BlockList* blocks) {
1496 1499 tty->print_cr("LIR:");
1497 1500 int i;
1498 1501 for (i = 0; i < blocks->length(); i++) {
1499 1502 BlockBegin* bb = blocks->at(i);
1500 1503 print_block(bb);
1501 1504 tty->print("__id_Instruction___________________________________________"); tty->cr();
1502 1505 bb->lir()->print_instructions();
1503 1506 }
1504 1507 }
1505 1508
1506 1509 void LIR_List::print_instructions() {
1507 1510 for (int i = 0; i < _operations.length(); i++) {
1508 1511 _operations.at(i)->print(); tty->cr();
1509 1512 }
1510 1513 tty->cr();
1511 1514 }
1512 1515
1513 1516 // LIR_Ops printing routines
1514 1517 // LIR_Op
1515 1518 void LIR_Op::print_on(outputStream* out) const {
1516 1519 if (id() != -1 || PrintCFGToFile) {
1517 1520 out->print("%4d ", id());
1518 1521 } else {
1519 1522 out->print(" ");
1520 1523 }
1521 1524 out->print(name()); out->print(" ");
1522 1525 print_instr(out);
1523 1526 if (info() != NULL) out->print(" [bci:%d]", info()->bci());
1524 1527 #ifdef ASSERT
1525 1528 if (Verbose && _file != NULL) {
1526 1529 out->print(" (%s:%d)", _file, _line);
1527 1530 }
1528 1531 #endif
1529 1532 }
1530 1533
1531 1534 const char * LIR_Op::name() const {
1532 1535 const char* s = NULL;
1533 1536 switch(code()) {
1534 1537 // LIR_Op0
1535 1538 case lir_membar: s = "membar"; break;
1536 1539 case lir_membar_acquire: s = "membar_acquire"; break;
1537 1540 case lir_membar_release: s = "membar_release"; break;
1538 1541 case lir_word_align: s = "word_align"; break;
1539 1542 case lir_label: s = "label"; break;
1540 1543 case lir_nop: s = "nop"; break;
1541 1544 case lir_backwardbranch_target: s = "backbranch"; break;
1542 1545 case lir_std_entry: s = "std_entry"; break;
1543 1546 case lir_osr_entry: s = "osr_entry"; break;
1544 1547 case lir_build_frame: s = "build_frm"; break;
1545 1548 case lir_fpop_raw: s = "fpop_raw"; break;
1546 1549 case lir_24bit_FPU: s = "24bit_FPU"; break;
1547 1550 case lir_reset_FPU: s = "reset_FPU"; break;
1548 1551 case lir_breakpoint: s = "breakpoint"; break;
1549 1552 case lir_get_thread: s = "get_thread"; break;
1550 1553 // LIR_Op1
1551 1554 case lir_fxch: s = "fxch"; break;
1552 1555 case lir_fld: s = "fld"; break;
1553 1556 case lir_ffree: s = "ffree"; break;
1554 1557 case lir_push: s = "push"; break;
1555 1558 case lir_pop: s = "pop"; break;
1556 1559 case lir_null_check: s = "null_check"; break;
1557 1560 case lir_return: s = "return"; break;
1558 1561 case lir_safepoint: s = "safepoint"; break;
1559 1562 case lir_neg: s = "neg"; break;
1560 1563 case lir_leal: s = "leal"; break;
1561 1564 case lir_branch: s = "branch"; break;
1562 1565 case lir_cond_float_branch: s = "flt_cond_br"; break;
1563 1566 case lir_move: s = "move"; break;
1564 1567 case lir_roundfp: s = "roundfp"; break;
1565 1568 case lir_rtcall: s = "rtcall"; break;
1566 1569 case lir_throw: s = "throw"; break;
1567 1570 case lir_unwind: s = "unwind"; break;
1568 1571 case lir_convert: s = "convert"; break;
1569 1572 case lir_alloc_object: s = "alloc_obj"; break;
1570 1573 case lir_monaddr: s = "mon_addr"; break;
1571 1574 // LIR_Op2
1572 1575 case lir_cmp: s = "cmp"; break;
1573 1576 case lir_cmp_l2i: s = "cmp_l2i"; break;
1574 1577 case lir_ucmp_fd2i: s = "ucomp_fd2i"; break;
1575 1578 case lir_cmp_fd2i: s = "comp_fd2i"; break;
1576 1579 case lir_cmove: s = "cmove"; break;
1577 1580 case lir_add: s = "add"; break;
1578 1581 case lir_sub: s = "sub"; break;
1579 1582 case lir_mul: s = "mul"; break;
1580 1583 case lir_mul_strictfp: s = "mul_strictfp"; break;
1581 1584 case lir_div: s = "div"; break;
1582 1585 case lir_div_strictfp: s = "div_strictfp"; break;
1583 1586 case lir_rem: s = "rem"; break;
1584 1587 case lir_abs: s = "abs"; break;
1585 1588 case lir_sqrt: s = "sqrt"; break;
1586 1589 case lir_sin: s = "sin"; break;
1587 1590 case lir_cos: s = "cos"; break;
1588 1591 case lir_tan: s = "tan"; break;
1589 1592 case lir_log: s = "log"; break;
1590 1593 case lir_log10: s = "log10"; break;
1591 1594 case lir_logic_and: s = "logic_and"; break;
1592 1595 case lir_logic_or: s = "logic_or"; break;
1593 1596 case lir_logic_xor: s = "logic_xor"; break;
1594 1597 case lir_shl: s = "shift_left"; break;
1595 1598 case lir_shr: s = "shift_right"; break;
1596 1599 case lir_ushr: s = "ushift_right"; break;
1597 1600 case lir_alloc_array: s = "alloc_array"; break;
1598 1601 // LIR_Op3
1599 1602 case lir_idiv: s = "idiv"; break;
1600 1603 case lir_irem: s = "irem"; break;
1601 1604 // LIR_OpJavaCall
1602 1605 case lir_static_call: s = "static"; break;
1603 1606 case lir_optvirtual_call: s = "optvirtual"; break;
1604 1607 case lir_icvirtual_call: s = "icvirtual"; break;
1605 1608 case lir_virtual_call: s = "virtual"; break;
1606 1609 case lir_dynamic_call: s = "dynamic"; break;
1607 1610 // LIR_OpArrayCopy
1608 1611 case lir_arraycopy: s = "arraycopy"; break;
1609 1612 // LIR_OpLock
1610 1613 case lir_lock: s = "lock"; break;
1611 1614 case lir_unlock: s = "unlock"; break;
1612 1615 // LIR_OpDelay
1613 1616 case lir_delay_slot: s = "delay"; break;
1614 1617 // LIR_OpTypeCheck
1615 1618 case lir_instanceof: s = "instanceof"; break;
1616 1619 case lir_checkcast: s = "checkcast"; break;
1617 1620 case lir_store_check: s = "store_check"; break;
1618 1621 // LIR_OpCompareAndSwap
1619 1622 case lir_cas_long: s = "cas_long"; break;
1620 1623 case lir_cas_obj: s = "cas_obj"; break;
1621 1624 case lir_cas_int: s = "cas_int"; break;
1622 1625 // LIR_OpProfileCall
1623 1626 case lir_profile_call: s = "profile_call"; break;
1624 1627
1625 1628 case lir_none: ShouldNotReachHere();break;
1626 1629 default: s = "illegal_op"; break;
1627 1630 }
1628 1631 return s;
1629 1632 }
1630 1633
1631 1634 // LIR_OpJavaCall
1632 1635 void LIR_OpJavaCall::print_instr(outputStream* out) const {
1633 1636 out->print("call: ");
1634 1637 out->print("[addr: 0x%x]", address());
1635 1638 if (receiver()->is_valid()) {
1636 1639 out->print(" [recv: "); receiver()->print(out); out->print("]");
1637 1640 }
1638 1641 if (result_opr()->is_valid()) {
1639 1642 out->print(" [result: "); result_opr()->print(out); out->print("]");
1640 1643 }
1641 1644 }
1642 1645
1643 1646 // LIR_OpLabel
1644 1647 void LIR_OpLabel::print_instr(outputStream* out) const {
1645 1648 out->print("[label:0x%x]", _label);
1646 1649 }
1647 1650
1648 1651 // LIR_OpArrayCopy
1649 1652 void LIR_OpArrayCopy::print_instr(outputStream* out) const {
1650 1653 src()->print(out); out->print(" ");
1651 1654 src_pos()->print(out); out->print(" ");
1652 1655 dst()->print(out); out->print(" ");
1653 1656 dst_pos()->print(out); out->print(" ");
1654 1657 length()->print(out); out->print(" ");
1655 1658 tmp()->print(out); out->print(" ");
1656 1659 }
1657 1660
1658 1661 // LIR_OpCompareAndSwap
1659 1662 void LIR_OpCompareAndSwap::print_instr(outputStream* out) const {
1660 1663 addr()->print(out); out->print(" ");
1661 1664 cmp_value()->print(out); out->print(" ");
1662 1665 new_value()->print(out); out->print(" ");
1663 1666 tmp1()->print(out); out->print(" ");
1664 1667 tmp2()->print(out); out->print(" ");
1665 1668
1666 1669 }
1667 1670
1668 1671 // LIR_Op0
1669 1672 void LIR_Op0::print_instr(outputStream* out) const {
1670 1673 result_opr()->print(out);
1671 1674 }
1672 1675
1673 1676 // LIR_Op1
1674 1677 const char * LIR_Op1::name() const {
1675 1678 if (code() == lir_move) {
1676 1679 switch (move_kind()) {
1677 1680 case lir_move_normal:
1678 1681 return "move";
1679 1682 case lir_move_unaligned:
1680 1683 return "unaligned move";
1681 1684 case lir_move_volatile:
1682 1685 return "volatile_move";
1683 1686 default:
1684 1687 ShouldNotReachHere();
1685 1688 return "illegal_op";
1686 1689 }
1687 1690 } else {
1688 1691 return LIR_Op::name();
1689 1692 }
1690 1693 }
1691 1694
1692 1695
1693 1696 void LIR_Op1::print_instr(outputStream* out) const {
1694 1697 _opr->print(out); out->print(" ");
1695 1698 result_opr()->print(out); out->print(" ");
1696 1699 print_patch_code(out, patch_code());
1697 1700 }
1698 1701
1699 1702
1700 1703 // LIR_Op1
1701 1704 void LIR_OpRTCall::print_instr(outputStream* out) const {
1702 1705 intx a = (intx)addr();
1703 1706 out->print(Runtime1::name_for_address(addr()));
1704 1707 out->print(" ");
1705 1708 tmp()->print(out);
1706 1709 }
1707 1710
1708 1711 void LIR_Op1::print_patch_code(outputStream* out, LIR_PatchCode code) {
1709 1712 switch(code) {
1710 1713 case lir_patch_none: break;
1711 1714 case lir_patch_low: out->print("[patch_low]"); break;
1712 1715 case lir_patch_high: out->print("[patch_high]"); break;
1713 1716 case lir_patch_normal: out->print("[patch_normal]"); break;
1714 1717 default: ShouldNotReachHere();
1715 1718 }
1716 1719 }
1717 1720
1718 1721 // LIR_OpBranch
1719 1722 void LIR_OpBranch::print_instr(outputStream* out) const {
1720 1723 print_condition(out, cond()); out->print(" ");
1721 1724 if (block() != NULL) {
1722 1725 out->print("[B%d] ", block()->block_id());
1723 1726 } else if (stub() != NULL) {
1724 1727 out->print("[");
1725 1728 stub()->print_name(out);
1726 1729 out->print(": 0x%x]", stub());
1727 1730 if (stub()->info() != NULL) out->print(" [bci:%d]", stub()->info()->bci());
1728 1731 } else {
1729 1732 out->print("[label:0x%x] ", label());
1730 1733 }
1731 1734 if (ublock() != NULL) {
1732 1735 out->print("unordered: [B%d] ", ublock()->block_id());
1733 1736 }
1734 1737 }
1735 1738
1736 1739 void LIR_Op::print_condition(outputStream* out, LIR_Condition cond) {
1737 1740 switch(cond) {
1738 1741 case lir_cond_equal: out->print("[EQ]"); break;
1739 1742 case lir_cond_notEqual: out->print("[NE]"); break;
1740 1743 case lir_cond_less: out->print("[LT]"); break;
1741 1744 case lir_cond_lessEqual: out->print("[LE]"); break;
1742 1745 case lir_cond_greaterEqual: out->print("[GE]"); break;
1743 1746 case lir_cond_greater: out->print("[GT]"); break;
1744 1747 case lir_cond_belowEqual: out->print("[BE]"); break;
1745 1748 case lir_cond_aboveEqual: out->print("[AE]"); break;
1746 1749 case lir_cond_always: out->print("[AL]"); break;
1747 1750 default: out->print("[%d]",cond); break;
1748 1751 }
1749 1752 }
1750 1753
1751 1754 // LIR_OpConvert
1752 1755 void LIR_OpConvert::print_instr(outputStream* out) const {
1753 1756 print_bytecode(out, bytecode());
1754 1757 in_opr()->print(out); out->print(" ");
1755 1758 result_opr()->print(out); out->print(" ");
1756 1759 }
1757 1760
1758 1761 void LIR_OpConvert::print_bytecode(outputStream* out, Bytecodes::Code code) {
1759 1762 switch(code) {
1760 1763 case Bytecodes::_d2f: out->print("[d2f] "); break;
1761 1764 case Bytecodes::_d2i: out->print("[d2i] "); break;
1762 1765 case Bytecodes::_d2l: out->print("[d2l] "); break;
1763 1766 case Bytecodes::_f2d: out->print("[f2d] "); break;
1764 1767 case Bytecodes::_f2i: out->print("[f2i] "); break;
1765 1768 case Bytecodes::_f2l: out->print("[f2l] "); break;
1766 1769 case Bytecodes::_i2b: out->print("[i2b] "); break;
1767 1770 case Bytecodes::_i2c: out->print("[i2c] "); break;
1768 1771 case Bytecodes::_i2d: out->print("[i2d] "); break;
1769 1772 case Bytecodes::_i2f: out->print("[i2f] "); break;
1770 1773 case Bytecodes::_i2l: out->print("[i2l] "); break;
1771 1774 case Bytecodes::_i2s: out->print("[i2s] "); break;
1772 1775 case Bytecodes::_l2i: out->print("[l2i] "); break;
1773 1776 case Bytecodes::_l2f: out->print("[l2f] "); break;
1774 1777 case Bytecodes::_l2d: out->print("[l2d] "); break;
1775 1778 default:
1776 1779 out->print("[?%d]",code);
1777 1780 break;
1778 1781 }
1779 1782 }
1780 1783
1781 1784 void LIR_OpAllocObj::print_instr(outputStream* out) const {
1782 1785 klass()->print(out); out->print(" ");
1783 1786 obj()->print(out); out->print(" ");
1784 1787 tmp1()->print(out); out->print(" ");
1785 1788 tmp2()->print(out); out->print(" ");
1786 1789 tmp3()->print(out); out->print(" ");
1787 1790 tmp4()->print(out); out->print(" ");
1788 1791 out->print("[hdr:%d]", header_size()); out->print(" ");
1789 1792 out->print("[obj:%d]", object_size()); out->print(" ");
1790 1793 out->print("[lbl:0x%x]", stub()->entry());
1791 1794 }
1792 1795
1793 1796 void LIR_OpRoundFP::print_instr(outputStream* out) const {
1794 1797 _opr->print(out); out->print(" ");
1795 1798 tmp()->print(out); out->print(" ");
1796 1799 result_opr()->print(out); out->print(" ");
1797 1800 }
1798 1801
1799 1802 // LIR_Op2
1800 1803 void LIR_Op2::print_instr(outputStream* out) const {
1801 1804 if (code() == lir_cmove) {
1802 1805 print_condition(out, condition()); out->print(" ");
1803 1806 }
1804 1807 in_opr1()->print(out); out->print(" ");
1805 1808 in_opr2()->print(out); out->print(" ");
1806 1809 if (tmp_opr()->is_valid()) { tmp_opr()->print(out); out->print(" "); }
1807 1810 result_opr()->print(out);
1808 1811 }
1809 1812
1810 1813 void LIR_OpAllocArray::print_instr(outputStream* out) const {
1811 1814 klass()->print(out); out->print(" ");
1812 1815 len()->print(out); out->print(" ");
1813 1816 obj()->print(out); out->print(" ");
1814 1817 tmp1()->print(out); out->print(" ");
1815 1818 tmp2()->print(out); out->print(" ");
1816 1819 tmp3()->print(out); out->print(" ");
1817 1820 tmp4()->print(out); out->print(" ");
1818 1821 out->print("[type:0x%x]", type()); out->print(" ");
1819 1822 out->print("[label:0x%x]", stub()->entry());
1820 1823 }
1821 1824
1822 1825
1823 1826 void LIR_OpTypeCheck::print_instr(outputStream* out) const {
1824 1827 object()->print(out); out->print(" ");
1825 1828 if (code() == lir_store_check) {
1826 1829 array()->print(out); out->print(" ");
1827 1830 }
1828 1831 if (code() != lir_store_check) {
1829 1832 klass()->print_name_on(out); out->print(" ");
1830 1833 if (fast_check()) out->print("fast_check ");
1831 1834 }
1832 1835 tmp1()->print(out); out->print(" ");
1833 1836 tmp2()->print(out); out->print(" ");
1834 1837 tmp3()->print(out); out->print(" ");
1835 1838 result_opr()->print(out); out->print(" ");
1836 1839 if (info_for_exception() != NULL) out->print(" [bci:%d]", info_for_exception()->bci());
1837 1840 }
1838 1841
1839 1842
1840 1843 // LIR_Op3
1841 1844 void LIR_Op3::print_instr(outputStream* out) const {
1842 1845 in_opr1()->print(out); out->print(" ");
1843 1846 in_opr2()->print(out); out->print(" ");
1844 1847 in_opr3()->print(out); out->print(" ");
1845 1848 result_opr()->print(out);
1846 1849 }
1847 1850
1848 1851
1849 1852 void LIR_OpLock::print_instr(outputStream* out) const {
1850 1853 hdr_opr()->print(out); out->print(" ");
1851 1854 obj_opr()->print(out); out->print(" ");
1852 1855 lock_opr()->print(out); out->print(" ");
1853 1856 if (_scratch->is_valid()) {
1854 1857 _scratch->print(out); out->print(" ");
1855 1858 }
1856 1859 out->print("[lbl:0x%x]", stub()->entry());
1857 1860 }
1858 1861
1859 1862
1860 1863 void LIR_OpDelay::print_instr(outputStream* out) const {
1861 1864 _op->print_on(out);
1862 1865 }
1863 1866
1864 1867
1865 1868 // LIR_OpProfileCall
1866 1869 void LIR_OpProfileCall::print_instr(outputStream* out) const {
1867 1870 profiled_method()->name()->print_symbol_on(out);
1868 1871 out->print(".");
1869 1872 profiled_method()->holder()->name()->print_symbol_on(out);
1870 1873 out->print(" @ %d ", profiled_bci());
1871 1874 mdo()->print(out); out->print(" ");
1872 1875 recv()->print(out); out->print(" ");
1873 1876 tmp1()->print(out); out->print(" ");
1874 1877 }
1875 1878
1876 1879
1877 1880 #endif // PRODUCT
1878 1881
1879 1882 // Implementation of LIR_InsertionBuffer
1880 1883
1881 1884 void LIR_InsertionBuffer::append(int index, LIR_Op* op) {
1882 1885 assert(_index_and_count.length() % 2 == 0, "must have a count for each index");
1883 1886
1884 1887 int i = number_of_insertion_points() - 1;
1885 1888 if (i < 0 || index_at(i) < index) {
1886 1889 append_new(index, 1);
1887 1890 } else {
1888 1891 assert(index_at(i) == index, "can append LIR_Ops in ascending order only");
1889 1892 assert(count_at(i) > 0, "check");
1890 1893 set_count_at(i, count_at(i) + 1);
1891 1894 }
1892 1895 _ops.push(op);
1893 1896
1894 1897 DEBUG_ONLY(verify());
1895 1898 }
1896 1899
1897 1900 #ifdef ASSERT
1898 1901 void LIR_InsertionBuffer::verify() {
1899 1902 int sum = 0;
1900 1903 int prev_idx = -1;
1901 1904
1902 1905 for (int i = 0; i < number_of_insertion_points(); i++) {
1903 1906 assert(prev_idx < index_at(i), "index must be ordered ascending");
1904 1907 sum += count_at(i);
1905 1908 }
1906 1909 assert(sum == number_of_ops(), "wrong total sum");
1907 1910 }
1908 1911 #endif
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